1 /* Native-dependent code for GNU/Linux AArch64.
3 Copyright (C) 2011-2014 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "linux-nat.h"
27 #include "target-descriptions.h"
30 #include "aarch64-tdep.h"
31 #include "aarch64-linux-tdep.h"
32 #include "elf/common.h"
34 #include <sys/ptrace.h>
35 #include <sys/utsname.h>
36 #include <asm/ptrace.h>
40 #include "features/aarch64.c"
42 /* Defines ps_err_e, struct ps_prochandle. */
43 #include "gdb_proc_service.h"
46 #define TRAP_HWBKPT 0x0004
49 /* On GNU/Linux, threads are implemented as pseudo-processes, in which
50 case we may be tracing more than one process at a time. In that
51 case, inferior_ptid will contain the main process ID and the
52 individual thread (process) ID. get_thread_id () is used to get
53 the thread id if it's available, and the process id otherwise. */
56 get_thread_id (ptid_t ptid)
58 int tid = ptid_get_lwp (ptid);
61 tid = ptid_get_pid (ptid);
65 /* Macro definitions, data structures, and code for the hardware
66 breakpoint and hardware watchpoint support follow. We use the
67 following abbreviations throughout the code:
73 /* Maximum number of hardware breakpoint and watchpoint registers.
74 Neither of these values may exceed the width of dr_changed_t
77 #define AARCH64_HBP_MAX_NUM 16
78 #define AARCH64_HWP_MAX_NUM 16
80 /* Alignment requirement in bytes for addresses written to
81 hardware breakpoint and watchpoint value registers.
83 A ptrace call attempting to set an address that does not meet the
84 alignment criteria will fail. Limited support has been provided in
85 this port for unaligned watchpoints, such that from a GDB user
86 perspective, an unaligned watchpoint may be requested.
88 This is achieved by minimally enlarging the watched area to meet the
89 alignment requirement, and if necessary, splitting the watchpoint
90 over several hardware watchpoint registers. */
92 #define AARCH64_HBP_ALIGNMENT 4
93 #define AARCH64_HWP_ALIGNMENT 8
95 /* The maximum length of a memory region that can be watched by one
96 hardware watchpoint register. */
98 #define AARCH64_HWP_MAX_LEN_PER_REG 8
100 /* ptrace hardware breakpoint resource info is formatted as follows:
103 +---------------+--------------+---------------+---------------+
104 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
105 +---------------+--------------+---------------+---------------+ */
108 /* Macros to extract fields from the hardware debug information word. */
109 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
110 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
112 /* Macro for the expected version of the ARMv8-A debug architecture. */
113 #define AARCH64_DEBUG_ARCH_V8 0x6
115 /* Number of hardware breakpoints/watchpoints the target supports.
116 They are initialized with values obtained via the ptrace calls
117 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
119 static int aarch64_num_bp_regs;
120 static int aarch64_num_wp_regs;
122 /* Debugging of hardware breakpoint/watchpoint support. */
124 static int debug_hw_points;
126 /* Each bit of a variable of this type is used to indicate whether a
127 hardware breakpoint or watchpoint setting has been changed since
130 Bit N corresponds to the Nth hardware breakpoint or watchpoint
131 setting which is managed in aarch64_debug_reg_state, where N is
132 valid between 0 and the total number of the hardware breakpoint or
133 watchpoint debug registers minus 1.
135 When bit N is 1, the corresponding breakpoint or watchpoint setting
136 has changed, and therefore the corresponding hardware debug
137 register needs to be updated via the ptrace interface.
139 In the per-thread arch-specific data area, we define two such
140 variables for per-thread hardware breakpoint and watchpoint
141 settings respectively.
143 This type is part of the mechanism which helps reduce the number of
144 ptrace calls to the kernel, i.e. avoid asking the kernel to write
145 to the debug registers with unchanged values. */
147 typedef unsigned LONGEST dr_changed_t;
149 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
151 #define DR_MARK_ALL_CHANGED(x, m) \
154 gdb_assert (sizeof ((x)) * 8 >= (m)); \
155 (x) = (((dr_changed_t)1 << (m)) - 1); \
158 #define DR_MARK_N_CHANGED(x, n) \
161 (x) |= ((dr_changed_t)1 << (n)); \
164 #define DR_CLEAR_CHANGED(x) \
170 #define DR_HAS_CHANGED(x) ((x) != 0)
171 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
173 /* Structure for managing the hardware breakpoint/watchpoint resources.
174 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
175 content, and DR_REF_COUNT_* counts the numbers of references to the
176 corresponding bp/wp, by which way the limited hardware resources
177 are not wasted on duplicated bp/wp settings (though so far gdb has
178 done a good job by not sending duplicated bp/wp requests). */
180 struct aarch64_debug_reg_state
182 /* hardware breakpoint */
183 CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
184 unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
185 unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
187 /* hardware watchpoint */
188 CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
189 unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
190 unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
193 /* Per-process data. We don't bind this to a per-inferior registry
194 because of targets like x86 GNU/Linux that need to keep track of
195 processes that aren't bound to any inferior (e.g., fork children,
198 struct aarch64_process_info
201 struct aarch64_process_info *next;
203 /* The process identifier. */
206 /* Copy of aarch64 hardware debug registers. */
207 struct aarch64_debug_reg_state state;
210 static struct aarch64_process_info *aarch64_process_list = NULL;
212 /* Find process data for process PID. */
214 static struct aarch64_process_info *
215 aarch64_find_process_pid (pid_t pid)
217 struct aarch64_process_info *proc;
219 for (proc = aarch64_process_list; proc; proc = proc->next)
220 if (proc->pid == pid)
226 /* Add process data for process PID. Returns newly allocated info
229 static struct aarch64_process_info *
230 aarch64_add_process (pid_t pid)
232 struct aarch64_process_info *proc;
234 proc = xcalloc (1, sizeof (*proc));
237 proc->next = aarch64_process_list;
238 aarch64_process_list = proc;
243 /* Get data specific info for process PID, creating it if necessary.
244 Never returns NULL. */
246 static struct aarch64_process_info *
247 aarch64_process_info_get (pid_t pid)
249 struct aarch64_process_info *proc;
251 proc = aarch64_find_process_pid (pid);
253 proc = aarch64_add_process (pid);
258 /* Called whenever GDB is no longer debugging process PID. It deletes
259 data structures that keep track of debug register state. */
262 aarch64_forget_process (pid_t pid)
264 struct aarch64_process_info *proc, **proc_link;
266 proc = aarch64_process_list;
267 proc_link = &aarch64_process_list;
271 if (proc->pid == pid)
273 *proc_link = proc->next;
279 proc_link = &proc->next;
284 /* Get debug registers state for process PID. */
286 static struct aarch64_debug_reg_state *
287 aarch64_get_debug_reg_state (pid_t pid)
289 return &aarch64_process_info_get (pid)->state;
292 /* Per-thread arch-specific data we want to keep. */
296 /* When bit N is 1, it indicates the Nth hardware breakpoint or
297 watchpoint register pair needs to be updated when the thread is
298 resumed; see aarch64_linux_prepare_to_resume. */
299 dr_changed_t dr_changed_bp;
300 dr_changed_t dr_changed_wp;
303 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
304 registers with data from *STATE. */
307 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
308 int tid, int watchpoint)
312 struct user_hwdebug_state regs;
313 const CORE_ADDR *addr;
314 const unsigned int *ctrl;
316 memset (®s, 0, sizeof (regs));
317 iov.iov_base = ®s;
318 count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
319 addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
320 ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
323 iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
324 + sizeof (regs.dbg_regs [count - 1]));
326 for (i = 0; i < count; i++)
328 regs.dbg_regs[i].addr = addr[i];
329 regs.dbg_regs[i].ctrl = ctrl[i];
332 if (ptrace (PTRACE_SETREGSET, tid,
333 watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
335 error (_("Unexpected error setting hardware debug registers"));
338 struct aarch64_dr_update_callback_param
344 /* Callback for iterate_over_lwps. Records the
345 information about the change of one hardware breakpoint/watchpoint
346 setting for the thread LWP.
347 The information is passed in via PTR.
348 N.B. The actual updating of hardware debug registers is not
349 carried out until the moment the thread is resumed. */
352 debug_reg_change_callback (struct lwp_info *lwp, void *ptr)
354 struct aarch64_dr_update_callback_param *param_p
355 = (struct aarch64_dr_update_callback_param *) ptr;
356 int pid = get_thread_id (lwp->ptid);
357 int idx = param_p->idx;
358 int is_watchpoint = param_p->is_watchpoint;
359 struct arch_lwp_info *info = lwp->arch_private;
360 dr_changed_t *dr_changed_ptr;
361 dr_changed_t dr_changed;
364 info = lwp->arch_private = XCNEW (struct arch_lwp_info);
368 fprintf_unfiltered (gdb_stdlog,
369 "debug_reg_change_callback: \n\tOn entry:\n");
370 fprintf_unfiltered (gdb_stdlog,
371 "\tpid%d, dr_changed_bp=0x%s, "
372 "dr_changed_wp=0x%s\n",
373 pid, phex (info->dr_changed_bp, 8),
374 phex (info->dr_changed_wp, 8));
377 dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
378 : &info->dr_changed_bp;
379 dr_changed = *dr_changed_ptr;
382 && (idx <= (is_watchpoint ? aarch64_num_wp_regs
383 : aarch64_num_bp_regs)));
385 /* The actual update is done later just before resuming the lwp,
386 we just mark that one register pair needs updating. */
387 DR_MARK_N_CHANGED (dr_changed, idx);
388 *dr_changed_ptr = dr_changed;
390 /* If the lwp isn't stopped, force it to momentarily pause, so
391 we can update its debug registers. */
393 linux_stop_lwp (lwp);
397 fprintf_unfiltered (gdb_stdlog,
398 "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, "
399 "dr_changed_wp=0x%s\n",
400 pid, phex (info->dr_changed_bp, 8),
401 phex (info->dr_changed_wp, 8));
404 /* Continue the iteration. */
408 /* Notify each thread that their IDXth breakpoint/watchpoint register
409 pair needs to be updated. The message will be recorded in each
410 thread's arch-specific data area, the actual updating will be done
411 when the thread is resumed. */
414 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
415 int is_watchpoint, unsigned int idx)
417 struct aarch64_dr_update_callback_param param;
418 ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (inferior_ptid));
420 param.is_watchpoint = is_watchpoint;
423 iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) ¶m);
426 /* Print the values of the cached breakpoint/watchpoint registers. */
429 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
430 const char *func, CORE_ADDR addr,
435 fprintf_unfiltered (gdb_stdlog, "%s", func);
437 fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)",
438 (unsigned long) addr, len,
439 type == hw_write ? "hw-write-watchpoint"
440 : (type == hw_read ? "hw-read-watchpoint"
441 : (type == hw_access ? "hw-access-watchpoint"
442 : (type == hw_execute ? "hw-breakpoint"
444 fprintf_unfiltered (gdb_stdlog, ":\n");
446 fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n");
447 for (i = 0; i < aarch64_num_bp_regs; i++)
448 fprintf_unfiltered (gdb_stdlog,
449 "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
450 i, state->dr_addr_bp[i],
451 state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
453 fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n");
454 for (i = 0; i < aarch64_num_wp_regs; i++)
455 fprintf_unfiltered (gdb_stdlog,
456 "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
457 i, state->dr_addr_wp[i],
458 state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
461 /* Fill GDB's register array with the general-purpose register values
462 from the current thread. */
465 fetch_gregs_from_thread (struct regcache *regcache)
471 tid = get_thread_id (inferior_ptid);
473 iovec.iov_base = ®s;
474 iovec.iov_len = sizeof (regs);
476 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
478 perror_with_name (_("Unable to fetch general registers."));
480 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
481 regcache_raw_supply (regcache, regno,
482 (char *) ®s[regno - AARCH64_X0_REGNUM]);
485 /* Store to the current thread the valid general-purpose register
486 values in the GDB's register array. */
489 store_gregs_to_thread (const struct regcache *regcache)
495 tid = get_thread_id (inferior_ptid);
497 iovec.iov_base = ®s;
498 iovec.iov_len = sizeof (regs);
500 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
502 perror_with_name (_("Unable to fetch general registers."));
504 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
505 if (REG_VALID == regcache_register_status (regcache, regno))
506 regcache_raw_collect (regcache, regno,
507 (char *) ®s[regno - AARCH64_X0_REGNUM]);
509 ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
511 perror_with_name (_("Unable to store general registers."));
514 /* Fill GDB's register array with the fp/simd register values
515 from the current thread. */
518 fetch_fpregs_from_thread (struct regcache *regcache)
524 tid = get_thread_id (inferior_ptid);
526 iovec.iov_base = ®s;
527 iovec.iov_len = sizeof (regs);
529 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
531 perror_with_name (_("Unable to fetch FP/SIMD registers."));
533 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
534 regcache_raw_supply (regcache, regno,
535 (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
537 regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
538 regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
541 /* Store to the current thread the valid fp/simd register
542 values in the GDB's register array. */
545 store_fpregs_to_thread (const struct regcache *regcache)
551 tid = get_thread_id (inferior_ptid);
553 iovec.iov_base = ®s;
554 iovec.iov_len = sizeof (regs);
556 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
558 perror_with_name (_("Unable to fetch FP/SIMD registers."));
560 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
561 if (REG_VALID == regcache_register_status (regcache, regno))
562 regcache_raw_collect (regcache, regno,
563 (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
565 if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM))
566 regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
567 if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM))
568 regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
570 ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
572 perror_with_name (_("Unable to store FP/SIMD registers."));
575 /* Implement the "to_fetch_register" target_ops method. */
578 aarch64_linux_fetch_inferior_registers (struct target_ops *ops,
579 struct regcache *regcache,
584 fetch_gregs_from_thread (regcache);
585 fetch_fpregs_from_thread (regcache);
587 else if (regno < AARCH64_V0_REGNUM)
588 fetch_gregs_from_thread (regcache);
590 fetch_fpregs_from_thread (regcache);
593 /* Implement the "to_store_register" target_ops method. */
596 aarch64_linux_store_inferior_registers (struct target_ops *ops,
597 struct regcache *regcache,
602 store_gregs_to_thread (regcache);
603 store_fpregs_to_thread (regcache);
605 else if (regno < AARCH64_V0_REGNUM)
606 store_gregs_to_thread (regcache);
608 store_fpregs_to_thread (regcache);
611 /* Fill register REGNO (if it is a general-purpose register) in
612 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
613 do this for all registers. */
616 fill_gregset (const struct regcache *regcache,
617 gdb_gregset_t *gregsetp, int regno)
619 gdb_byte *gregs_buf = (gdb_byte *) gregsetp;
622 for (i = AARCH64_X0_REGNUM; i <= AARCH64_CPSR_REGNUM; i++)
623 if (regno == -1 || regno == i)
624 regcache_raw_collect (regcache, i,
625 gregs_buf + X_REGISTER_SIZE
626 * (i - AARCH64_X0_REGNUM));
629 /* Fill GDB's register array with the general-purpose register values
633 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
635 aarch64_linux_supply_gregset (regcache, (const gdb_byte *) gregsetp);
638 /* Fill register REGNO (if it is a floating-point register) in
639 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
640 do this for all registers. */
643 fill_fpregset (const struct regcache *regcache,
644 gdb_fpregset_t *fpregsetp, int regno)
646 gdb_byte *fpregs_buf = (gdb_byte *) fpregsetp;
649 for (i = AARCH64_V0_REGNUM; i <= AARCH64_V31_REGNUM; i++)
650 if (regno == -1 || regno == i)
651 regcache_raw_collect (regcache, i,
652 fpregs_buf + V_REGISTER_SIZE
653 * (i - AARCH64_V0_REGNUM));
655 if (regno == -1 || regno == AARCH64_FPSR_REGNUM)
656 regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM,
657 fpregs_buf + V_REGISTER_SIZE * 32);
659 if (regno == -1 || regno == AARCH64_FPCR_REGNUM)
660 regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM,
661 fpregs_buf + V_REGISTER_SIZE * 32 + 4);
664 /* Fill GDB's register array with the floating-point register values
668 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
670 aarch64_linux_supply_fpregset (regcache, (const gdb_byte *) fpregsetp);
673 /* Called when resuming a thread.
674 The hardware debug registers are updated when there is any change. */
677 aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
679 struct arch_lwp_info *info = lwp->arch_private;
681 /* NULL means this is the main thread still going through the shell,
682 or, no watchpoint has been set yet. In that case, there's
687 if (DR_HAS_CHANGED (info->dr_changed_bp)
688 || DR_HAS_CHANGED (info->dr_changed_wp))
690 int tid = ptid_get_lwp (lwp->ptid);
691 struct aarch64_debug_reg_state *state
692 = aarch64_get_debug_reg_state (ptid_get_pid (lwp->ptid));
695 fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid);
698 if (DR_HAS_CHANGED (info->dr_changed_wp))
700 aarch64_linux_set_debug_regs (state, tid, 1);
701 DR_CLEAR_CHANGED (info->dr_changed_wp);
705 if (DR_HAS_CHANGED (info->dr_changed_bp))
707 aarch64_linux_set_debug_regs (state, tid, 0);
708 DR_CLEAR_CHANGED (info->dr_changed_bp);
714 aarch64_linux_new_thread (struct lwp_info *lp)
716 struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
718 /* Mark that all the hardware breakpoint/watchpoint register pairs
719 for this thread need to be initialized. */
720 DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
721 DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
723 lp->arch_private = info;
726 /* linux_nat_new_fork hook. */
729 aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid)
732 struct aarch64_debug_reg_state *parent_state;
733 struct aarch64_debug_reg_state *child_state;
735 /* NULL means no watchpoint has ever been set in the parent. In
736 that case, there's nothing to do. */
737 if (parent->arch_private == NULL)
740 /* GDB core assumes the child inherits the watchpoints/hw
741 breakpoints of the parent, and will remove them all from the
742 forked off process. Copy the debug registers mirrors into the
743 new process so that all breakpoints and watchpoints can be
746 parent_pid = ptid_get_pid (parent->ptid);
747 parent_state = aarch64_get_debug_reg_state (parent_pid);
748 child_state = aarch64_get_debug_reg_state (child_pid);
749 *child_state = *parent_state;
753 /* Called by libthread_db. Returns a pointer to the thread local
754 storage (or its descriptor). */
757 ps_get_thread_area (const struct ps_prochandle *ph,
758 lwpid_t lwpid, int idx, void **base)
763 iovec.iov_base = ®
764 iovec.iov_len = sizeof (reg);
766 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
769 /* IDX is the bias from the thread pointer to the beginning of the
770 thread descriptor. It has to be subtracted due to implementation
771 quirks in libthread_db. */
772 *base = (void *) (reg - idx);
778 /* Get the hardware debug register capacity information. */
781 aarch64_linux_get_debug_reg_capacity (void)
785 struct user_hwdebug_state dreg_state;
787 tid = get_thread_id (inferior_ptid);
788 iov.iov_base = &dreg_state;
789 iov.iov_len = sizeof (dreg_state);
791 /* Get hardware watchpoint register info. */
792 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
793 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
795 aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
796 if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
798 warning (_("Unexpected number of hardware watchpoint registers"
799 " reported by ptrace, got %d, expected %d."),
800 aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
801 aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
806 warning (_("Unable to determine the number of hardware watchpoints"
808 aarch64_num_wp_regs = 0;
811 /* Get hardware breakpoint register info. */
812 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
813 && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
815 aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
816 if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
818 warning (_("Unexpected number of hardware breakpoint registers"
819 " reported by ptrace, got %d, expected %d."),
820 aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
821 aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
826 warning (_("Unable to determine the number of hardware breakpoints"
828 aarch64_num_bp_regs = 0;
832 static void (*super_post_startup_inferior) (struct target_ops *self,
835 /* Implement the "to_post_startup_inferior" target_ops method. */
838 aarch64_linux_child_post_startup_inferior (struct target_ops *self,
841 aarch64_forget_process (ptid_get_pid (ptid));
842 aarch64_linux_get_debug_reg_capacity ();
843 super_post_startup_inferior (self, ptid);
846 /* Implement the "to_read_description" target_ops method. */
848 static const struct target_desc *
849 aarch64_linux_read_description (struct target_ops *ops)
851 initialize_tdesc_aarch64 ();
852 return tdesc_aarch64;
855 /* Given the (potentially unaligned) watchpoint address in ADDR and
856 length in LEN, return the aligned address and aligned length in
857 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
858 aligned address and length will be valid values to write to the
859 hardware watchpoint value and control registers.
861 The given watchpoint may get truncated if more than one hardware
862 register is needed to cover the watched region. *NEXT_ADDR_P
863 and *NEXT_LEN_P, if non-NULL, will return the address and length
864 of the remaining part of the watchpoint (which can be processed
865 by calling this routine again to generate another aligned address
868 See the comment above the function of the same name in
869 gdbserver/linux-aarch64-low.c for more information. */
872 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
873 int *aligned_len_p, CORE_ADDR *next_addr_p,
878 CORE_ADDR aligned_addr;
879 const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
880 const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
882 /* As assumed by the algorithm. */
883 gdb_assert (alignment == max_wp_len);
888 /* Address to be put into the hardware watchpoint value register
890 offset = addr & (alignment - 1);
891 aligned_addr = addr - offset;
893 gdb_assert (offset >= 0 && offset < alignment);
894 gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
895 gdb_assert (offset + len > 0);
897 if (offset + len >= max_wp_len)
899 /* Need more than one watchpoint registers; truncate it at the
900 alignment boundary. */
901 aligned_len = max_wp_len;
902 len -= (max_wp_len - offset);
903 addr += (max_wp_len - offset);
904 gdb_assert ((addr & (alignment - 1)) == 0);
908 /* Find the smallest valid length that is large enough to
909 accommodate this watchpoint. */
910 static const unsigned char
911 aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
912 { 1, 2, 4, 4, 8, 8, 8, 8 };
914 aligned_len = aligned_len_array[offset + len - 1];
920 *aligned_addr_p = aligned_addr;
922 *aligned_len_p = aligned_len;
929 /* Returns the number of hardware watchpoints of type TYPE that we can
930 set. Value is positive if we can set CNT watchpoints, zero if
931 setting watchpoints of type TYPE is not supported, and negative if
932 CNT is more than the maximum number of watchpoints of type TYPE
933 that we can support. TYPE is one of bp_hardware_watchpoint,
934 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
935 CNT is the number of such watchpoints used so far (including this
936 one). OTHERTYPE is non-zero if other types of watchpoints are
939 We always return 1 here because we don't have enough information
940 about possible overlap of addresses that they want to watch. As an
941 extreme example, consider the case where all the watchpoints watch
942 the same address and the same region length: then we can handle a
943 virtually unlimited number of watchpoints, due to debug register
944 sharing implemented via reference counts. */
947 aarch64_linux_can_use_hw_breakpoint (struct target_ops *self,
948 int type, int cnt, int othertype)
953 /* ptrace expects control registers to be formatted as follows:
956 +--------------------------------+----------+------+------+----+
957 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
958 +--------------------------------+----------+------+------+----+
960 The TYPE field is ignored for breakpoints. */
962 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
963 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
965 /* Utility function that returns the length in bytes of a watchpoint
966 according to the content of a hardware debug control register CTRL.
967 Note that the kernel currently only supports the following Byte
968 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
969 that for a hardware watchpoint, its valid length can only be 1
970 byte, 2 bytes, 4 bytes or 8 bytes. */
972 static inline unsigned int
973 aarch64_watchpoint_length (unsigned int ctrl)
975 switch (DR_CONTROL_LENGTH (ctrl))
990 /* Given the hardware breakpoint or watchpoint type TYPE and its
991 length LEN, return the expected encoding for a hardware
992 breakpoint/watchpoint control register. */
995 aarch64_point_encode_ctrl_reg (int type, int len)
997 unsigned int ctrl, ttype;
1015 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
1019 /* length bitmask */
1020 ctrl |= ((1 << len) - 1) << 5;
1021 /* enabled at el0 */
1022 ctrl |= (2 << 1) | 1;
1027 /* Addresses to be written to the hardware breakpoint and watchpoint
1028 value registers need to be aligned; the alignment is 4-byte and
1029 8-type respectively. Linux kernel rejects any non-aligned address
1030 it receives from the related ptrace call. Furthermore, the kernel
1031 currently only supports the following Byte Address Select (BAS)
1032 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
1033 watchpoint to be accepted by the kernel (via ptrace call), its
1034 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
1035 Despite these limitations, the unaligned watchpoint is supported in
1038 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
1041 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
1043 unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
1044 : AARCH64_HBP_ALIGNMENT;
1046 if (addr & (alignment - 1))
1049 if (len != 8 && len != 4 && len != 2 && len != 1)
1055 /* Record the insertion of one breakpoint/watchpoint, as represented
1056 by ADDR and CTRL, in the cached debug register state area *STATE. */
1059 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
1060 int type, CORE_ADDR addr, int len)
1062 int i, idx, num_regs, is_watchpoint;
1063 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
1064 CORE_ADDR *dr_addr_p;
1066 /* Set up state pointers. */
1067 is_watchpoint = (type != hw_execute);
1068 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
1071 num_regs = aarch64_num_wp_regs;
1072 dr_addr_p = state->dr_addr_wp;
1073 dr_ctrl_p = state->dr_ctrl_wp;
1074 dr_ref_count = state->dr_ref_count_wp;
1078 num_regs = aarch64_num_bp_regs;
1079 dr_addr_p = state->dr_addr_bp;
1080 dr_ctrl_p = state->dr_ctrl_bp;
1081 dr_ref_count = state->dr_ref_count_bp;
1084 ctrl = aarch64_point_encode_ctrl_reg (type, len);
1086 /* Find an existing or free register in our cache. */
1088 for (i = 0; i < num_regs; ++i)
1090 if ((dr_ctrl_p[i] & 1) == 0)
1092 gdb_assert (dr_ref_count[i] == 0);
1094 /* no break; continue hunting for an existing one. */
1096 else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
1098 gdb_assert (dr_ref_count[i] != 0);
1108 /* Update our cache. */
1109 if ((dr_ctrl_p[idx] & 1) == 0)
1112 dr_addr_p[idx] = addr;
1113 dr_ctrl_p[idx] = ctrl;
1114 dr_ref_count[idx] = 1;
1115 /* Notify the change. */
1116 aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
1120 /* existing entry */
1121 dr_ref_count[idx]++;
1127 /* Record the removal of one breakpoint/watchpoint, as represented by
1128 ADDR and CTRL, in the cached debug register state area *STATE. */
1131 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
1132 int type, CORE_ADDR addr, int len)
1134 int i, num_regs, is_watchpoint;
1135 unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
1136 CORE_ADDR *dr_addr_p;
1138 /* Set up state pointers. */
1139 is_watchpoint = (type != hw_execute);
1140 gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
1143 num_regs = aarch64_num_wp_regs;
1144 dr_addr_p = state->dr_addr_wp;
1145 dr_ctrl_p = state->dr_ctrl_wp;
1146 dr_ref_count = state->dr_ref_count_wp;
1150 num_regs = aarch64_num_bp_regs;
1151 dr_addr_p = state->dr_addr_bp;
1152 dr_ctrl_p = state->dr_ctrl_bp;
1153 dr_ref_count = state->dr_ref_count_bp;
1156 ctrl = aarch64_point_encode_ctrl_reg (type, len);
1158 /* Find the entry that matches the ADDR and CTRL. */
1159 for (i = 0; i < num_regs; ++i)
1160 if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
1162 gdb_assert (dr_ref_count[i] != 0);
1170 /* Clear our cache. */
1171 if (--dr_ref_count[i] == 0)
1173 /* Clear the enable bit. */
1176 dr_ctrl_p[i] = ctrl;
1177 /* Notify the change. */
1178 aarch64_notify_debug_reg_change (state, is_watchpoint, i);
1184 /* Implement insertion and removal of a single breakpoint. */
1187 aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert)
1189 struct aarch64_debug_reg_state *state;
1191 /* The hardware breakpoint on AArch64 should always be 4-byte
1193 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
1196 state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1199 return aarch64_dr_state_insert_one_point (state, type, addr, len);
1201 return aarch64_dr_state_remove_one_point (state, type, addr, len);
1204 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
1205 Return 0 on success, -1 on failure. */
1208 aarch64_linux_insert_hw_breakpoint (struct target_ops *self,
1209 struct gdbarch *gdbarch,
1210 struct bp_target_info *bp_tgt)
1213 CORE_ADDR addr = bp_tgt->placed_address;
1215 const int type = hw_execute;
1217 if (debug_hw_points)
1220 "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1221 (unsigned long) addr, len);
1223 ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */);
1225 if (debug_hw_points > 1)
1227 struct aarch64_debug_reg_state *state
1228 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1230 aarch64_show_debug_reg_state (state,
1231 "insert_hw_watchpoint", addr, len, type);
1237 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
1238 Return 0 on success, -1 on failure. */
1241 aarch64_linux_remove_hw_breakpoint (struct target_ops *self,
1242 struct gdbarch *gdbarch,
1243 struct bp_target_info *bp_tgt)
1246 CORE_ADDR addr = bp_tgt->placed_address;
1248 const int type = hw_execute;
1250 if (debug_hw_points)
1252 (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1253 (unsigned long) addr, len);
1255 ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */);
1257 if (debug_hw_points > 1)
1259 struct aarch64_debug_reg_state *state
1260 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1262 aarch64_show_debug_reg_state (state,
1263 "remove_hw_watchpoint", addr, len, type);
1269 /* This is essentially the same as aarch64_handle_breakpoint, apart
1270 from that it is an aligned watchpoint to be handled. */
1273 aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len,
1276 struct aarch64_debug_reg_state *state
1277 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1280 return aarch64_dr_state_insert_one_point (state, type, addr, len);
1282 return aarch64_dr_state_remove_one_point (state, type, addr, len);
1285 /* Insert/remove unaligned watchpoint by calling
1286 aarch64_align_watchpoint repeatedly until the whole watched region,
1287 as represented by ADDR and LEN, has been properly aligned and ready
1288 to be written to one or more hardware watchpoint registers.
1289 IS_INSERT indicates whether this is an insertion or a deletion.
1290 Return 0 if succeed. */
1293 aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len,
1296 struct aarch64_debug_reg_state *state
1297 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1301 CORE_ADDR aligned_addr;
1302 int aligned_len, ret;
1304 aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
1308 ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
1311 ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
1314 if (debug_hw_points)
1315 fprintf_unfiltered (gdb_stdlog,
1316 "handle_unaligned_watchpoint: is_insert: %d\n"
1317 " aligned_addr: 0x%08lx, aligned_len: %d\n"
1318 " next_addr: 0x%08lx, next_len: %d\n",
1319 is_insert, aligned_addr, aligned_len, addr, len);
1328 /* Implements insertion and removal of a single watchpoint. */
1331 aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert)
1333 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
1334 return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
1336 return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
1339 /* Implement the "to_insert_watchpoint" target_ops method.
1341 Insert a watchpoint to watch a memory region which starts at
1342 address ADDR and whose length is LEN bytes. Watch memory accesses
1343 of the type TYPE. Return 0 on success, -1 on failure. */
1346 aarch64_linux_insert_watchpoint (struct target_ops *self,
1347 CORE_ADDR addr, int len, int type,
1348 struct expression *cond)
1352 if (debug_hw_points)
1353 fprintf_unfiltered (gdb_stdlog,
1354 "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1355 (unsigned long) addr, len);
1357 gdb_assert (type != hw_execute);
1359 ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */);
1361 if (debug_hw_points > 1)
1363 struct aarch64_debug_reg_state *state
1364 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1366 aarch64_show_debug_reg_state (state,
1367 "insert_watchpoint", addr, len, type);
1373 /* Implement the "to_remove_watchpoint" target_ops method.
1374 Remove a watchpoint that watched the memory region which starts at
1375 address ADDR, whose length is LEN bytes, and for accesses of the
1376 type TYPE. Return 0 on success, -1 on failure. */
1379 aarch64_linux_remove_watchpoint (struct target_ops *self,
1380 CORE_ADDR addr, int len, int type,
1381 struct expression *cond)
1385 if (debug_hw_points)
1386 fprintf_unfiltered (gdb_stdlog,
1387 "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1388 (unsigned long) addr, len);
1390 gdb_assert (type != hw_execute);
1392 ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */);
1394 if (debug_hw_points > 1)
1396 struct aarch64_debug_reg_state *state
1397 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1399 aarch64_show_debug_reg_state (state,
1400 "remove_watchpoint", addr, len, type);
1406 /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */
1409 aarch64_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
1410 CORE_ADDR addr, int len)
1412 CORE_ADDR aligned_addr;
1414 /* Can not set watchpoints for zero or negative lengths. */
1418 /* Must have hardware watchpoint debug register(s). */
1419 if (aarch64_num_wp_regs == 0)
1422 /* We support unaligned watchpoint address and arbitrary length,
1423 as long as the size of the whole watched area after alignment
1424 doesn't exceed size of the total area that all watchpoint debug
1425 registers can watch cooperatively.
1427 This is a very relaxed rule, but unfortunately there are
1428 limitations, e.g. false-positive hits, due to limited support of
1429 hardware debug registers in the kernel. See comment above
1430 aarch64_align_watchpoint for more information. */
1432 aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1);
1433 if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG
1437 /* All tests passed so we are likely to be able to set the watchpoint.
1438 The reason that it is 'likely' rather than 'must' is because
1439 we don't check the current usage of the watchpoint registers, and
1440 there may not be enough registers available for this watchpoint.
1441 Ideally we should check the cached debug register state, however
1442 the checking is costly. */
1446 /* Implement the "to_stopped_data_address" target_ops method. */
1449 aarch64_linux_stopped_data_address (struct target_ops *target,
1454 struct aarch64_debug_reg_state *state;
1456 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
1459 /* This must be a hardware breakpoint. */
1460 if (siginfo.si_signo != SIGTRAP
1461 || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
1464 /* Check if the address matches any watched address. */
1465 state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
1466 for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1468 const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1469 const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1470 const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1472 if (state->dr_ref_count_wp[i]
1473 && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1474 && addr_trap >= addr_watch
1475 && addr_trap < addr_watch + len)
1477 *addr_p = addr_trap;
1485 /* Implement the "to_stopped_by_watchpoint" target_ops method. */
1488 aarch64_linux_stopped_by_watchpoint (struct target_ops *ops)
1492 return aarch64_linux_stopped_data_address (ops, &addr);
1495 /* Implement the "to_watchpoint_addr_within_range" target_ops method. */
1498 aarch64_linux_watchpoint_addr_within_range (struct target_ops *target,
1500 CORE_ADDR start, int length)
1502 return start <= addr && start + length - 1 >= addr;
1505 /* Define AArch64 maintenance commands. */
1508 add_show_debug_regs_command (void)
1510 /* A maintenance command to enable printing the internal DRi mirror
1512 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
1513 &debug_hw_points, _("\
1514 Set whether to show variables that mirror the AArch64 debug registers."), _("\
1515 Show whether to show variables that mirror the AArch64 debug registers."), _("\
1516 Use \"on\" to enable, \"off\" to disable.\n\
1517 If enabled, the debug registers values are shown when GDB inserts\n\
1518 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1519 triggers a breakpoint or watchpoint."),
1522 &maintenance_set_cmdlist,
1523 &maintenance_show_cmdlist);
1526 /* -Wmissing-prototypes. */
1527 void _initialize_aarch64_linux_nat (void);
1530 _initialize_aarch64_linux_nat (void)
1532 struct target_ops *t;
1534 /* Fill in the generic GNU/Linux methods. */
1535 t = linux_target ();
1537 add_show_debug_regs_command ();
1539 /* Add our register access methods. */
1540 t->to_fetch_registers = aarch64_linux_fetch_inferior_registers;
1541 t->to_store_registers = aarch64_linux_store_inferior_registers;
1543 t->to_read_description = aarch64_linux_read_description;
1545 t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint;
1546 t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint;
1547 t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint;
1548 t->to_region_ok_for_hw_watchpoint =
1549 aarch64_linux_region_ok_for_hw_watchpoint;
1550 t->to_insert_watchpoint = aarch64_linux_insert_watchpoint;
1551 t->to_remove_watchpoint = aarch64_linux_remove_watchpoint;
1552 t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint;
1553 t->to_stopped_data_address = aarch64_linux_stopped_data_address;
1554 t->to_watchpoint_addr_within_range =
1555 aarch64_linux_watchpoint_addr_within_range;
1557 /* Override the GNU/Linux inferior startup hook. */
1558 super_post_startup_inferior = t->to_post_startup_inferior;
1559 t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior;
1561 /* Register the target. */
1562 linux_nat_add_target (t);
1563 linux_nat_set_new_thread (t, aarch64_linux_new_thread);
1564 linux_nat_set_new_fork (t, aarch64_linux_new_fork);
1565 linux_nat_set_forget_process (t, aarch64_forget_process);
1566 linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume);