1 /* Test MIPS32 DSP instructions */
2 /* { dg-do compile } */
3 /* { dg-options "-mgp32 -mdsp" } */
4 /* { dg-final { scan-assembler "\taddq.ph\t" } } */
5 /* { dg-final { scan-assembler "\taddq_s.ph\t" } } */
6 /* { dg-final { scan-assembler "\taddq_s.w\t" } } */
7 /* { dg-final { scan-assembler "\taddu.qb\t" } } */
8 /* { dg-final { scan-assembler "\taddu_s.qb\t" } } */
9 /* { dg-final { scan-assembler "\tsubq.ph\t" } } */
10 /* { dg-final { scan-assembler "\tsubq_s.ph\t" } } */
11 /* { dg-final { scan-assembler "\tsubq_s.w\t" } } */
12 /* { dg-final { scan-assembler "\tsubu.qb\t" } } */
13 /* { dg-final { scan-assembler "\tsubu_s.qb\t" } } */
14 /* { dg-final { scan-assembler "\taddsc\t" } } */
15 /* { dg-final { scan-assembler "\taddwc\t" } } */
16 /* { dg-final { scan-assembler "\tmodsub\t" } } */
17 /* { dg-final { scan-assembler "\traddu.w.qb\t" } } */
18 /* { dg-final { scan-assembler "\tabsq_s.ph\t" } } */
19 /* { dg-final { scan-assembler "\tabsq_s.w\t" } } */
20 /* { dg-final { scan-assembler "\tprecrq.qb.ph\t" } } */
21 /* { dg-final { scan-assembler "\tprecrq.ph.w\t" } } */
22 /* { dg-final { scan-assembler "\tprecrq_rs.ph.w\t" } } */
23 /* { dg-final { scan-assembler "\tprecrqu_s.qb.ph\t" } } */
24 /* { dg-final { scan-assembler "\tpreceq.w.phl\t" } } */
25 /* { dg-final { scan-assembler "\tpreceq.w.phr\t" } } */
26 /* { dg-final { scan-assembler "\tprecequ.ph.qbl\t" } } */
27 /* { dg-final { scan-assembler "\tprecequ.ph.qbr\t" } } */
28 /* { dg-final { scan-assembler "\tprecequ.ph.qbla\t" } } */
29 /* { dg-final { scan-assembler "\tprecequ.ph.qbra\t" } } */
30 /* { dg-final { scan-assembler "\tpreceu.ph.qbl\t" } } */
31 /* { dg-final { scan-assembler "\tpreceu.ph.qbr\t" } } */
32 /* { dg-final { scan-assembler "\tpreceu.ph.qbla\t" } } */
33 /* { dg-final { scan-assembler "\tpreceu.ph.qbra\t" } } */
34 /* { dg-final { scan-assembler "\tshllv?.qb\t" } } */
35 /* { dg-final { scan-assembler "\tshllv?.ph\t" } } */
36 /* { dg-final { scan-assembler "\tshllv?_s.ph\t" } } */
37 /* { dg-final { scan-assembler "\tshllv?_s.w\t" } } */
38 /* { dg-final { scan-assembler "\tshrlv?.qb\t" } } */
39 /* { dg-final { scan-assembler "\tshrav?.ph\t" } } */
40 /* { dg-final { scan-assembler "\tshrav?_r.ph\t" } } */
41 /* { dg-final { scan-assembler "\tshrav?_r.w\t" } } */
42 /* { dg-final { scan-assembler "\tmuleu_s.ph.qbl\t" } } */
43 /* { dg-final { scan-assembler "\tmuleu_s.ph.qbr\t" } } */
44 /* { dg-final { scan-assembler "\tmulq_rs.ph\t" } } */
45 /* { dg-final { scan-assembler "\tmuleq_s.w.phl\t" } } */
46 /* { dg-final { scan-assembler "\tmuleq_s.w.phr\t" } } */
47 /* { dg-final { scan-assembler "\tdpau.h.qbl\t" } } */
48 /* { dg-final { scan-assembler "\tdpau.h.qbr\t" } } */
49 /* { dg-final { scan-assembler "\tdpsu.h.qbl\t" } } */
50 /* { dg-final { scan-assembler "\tdpsu.h.qbr\t" } } */
51 /* { dg-final { scan-assembler "\tdpaq_s.w.ph\t" } } */
52 /* { dg-final { scan-assembler "\tdpsq_s.w.ph\t" } } */
53 /* { dg-final { scan-assembler "\tmulsaq_s.w.ph\t" } } */
54 /* { dg-final { scan-assembler "\tdpaq_sa.l.w\t" } } */
55 /* { dg-final { scan-assembler "\tdpsq_sa.l.w\t" } } */
56 /* { dg-final { scan-assembler "\tmaq_s.w.phl\t" } } */
57 /* { dg-final { scan-assembler "\tmaq_s.w.phr\t" } } */
58 /* { dg-final { scan-assembler "\tmaq_sa.w.phl\t" } } */
59 /* { dg-final { scan-assembler "\tmaq_sa.w.phr\t" } } */
60 /* { dg-final { scan-assembler "\tbitrev\t" } } */
61 /* { dg-final { scan-assembler "\tinsv\t" } } */
62 /* { dg-final { scan-assembler "\treplv?.qb\t" } } */
63 /* { dg-final { scan-assembler "\trepl.ph\t" } } */
64 /* { dg-final { scan-assembler "\treplv.ph\t" } } */
65 /* { dg-final { scan-assembler "\tcmpu.eq.qb\t" } } */
66 /* { dg-final { scan-assembler "\tcmpu.lt.qb\t" } } */
67 /* { dg-final { scan-assembler "\tcmpu.le.qb\t" } } */
68 /* { dg-final { scan-assembler "\tcmpgu.eq.qb\t" } } */
69 /* { dg-final { scan-assembler "\tcmpgu.lt.qb\t" } } */
70 /* { dg-final { scan-assembler "\tcmpgu.le.qb\t" } } */
71 /* { dg-final { scan-assembler "\tcmp.eq.ph\t" } } */
72 /* { dg-final { scan-assembler "\tcmp.lt.ph\t" } } */
73 /* { dg-final { scan-assembler "\tcmp.le.ph\t" } } */
74 /* { dg-final { scan-assembler "\tpick.qb\t" } } */
75 /* { dg-final { scan-assembler "\tpick.ph\t" } } */
76 /* { dg-final { scan-assembler "\tpackrl.ph\t" } } */
77 /* { dg-final { scan-assembler "\textrv?.w\t" } } */
78 /* { dg-final { scan-assembler "\textrv?_s.h\t" } } */
79 /* { dg-final { scan-assembler "\textrv?_r.w\t" } } */
80 /* { dg-final { scan-assembler "\textrv?_rs.w\t" } } */
81 /* { dg-final { scan-assembler "\textpv?\t" } } */
82 /* { dg-final { scan-assembler "\textpdpv?\t" } } */
83 /* { dg-final { scan-assembler "\tshilov?\t" } } */
84 /* { dg-final { scan-assembler "\tmthlip\t" } } */
85 /* { dg-final { scan-assembler "\tmfhi\t" } } */
86 /* { dg-final { scan-assembler "\tmflo\t" } } */
87 /* { dg-final { scan-assembler "\tmthi\t" } } */
88 /* { dg-final { scan-assembler "\tmtlo\t" } } */
89 /* { dg-final { scan-assembler "\twrdsp\t" } } */
90 /* { dg-final { scan-assembler "\trddsp\t" } } */
91 /* { dg-final { scan-assembler "\tlbux?\t" } } */
92 /* { dg-final { scan-assembler "\tlhx?\t" } } */
93 /* { dg-final { scan-assembler "\tlwx?\t" } } */
94 /* { dg-final { scan-assembler "\tbposge32\t" } } */
95 /* { dg-final { scan-assembler "\tmadd\t" } } */
96 /* { dg-final { scan-assembler "\tmaddu\t" } } */
97 /* { dg-final { scan-assembler "\tmsub\t" } } */
98 /* { dg-final { scan-assembler "\tmsubu\t" } } */
99 /* { dg-final { scan-assembler "\tmult\t" } } */
100 /* { dg-final { scan-assembler "\tmultu\t" } } */
105 typedef signed char v4i8 __attribute__ ((vector_size(4)));
106 typedef short v2q15 __attribute__ ((vector_size(4)));
110 typedef unsigned int ui32;
111 typedef long long a64;
113 NOMIPS16 void test_MIPS_DSP (void);
122 union { long long ll; int i[2]; } endianness_test;
123 endianness_test.ll = 1;
124 little_endian = endianness_test.i[0];
126 for (i = 0; i < 100; i++)
134 NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
136 return __builtin_mips_addq_ph (a, b);
139 NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
141 return __builtin_mips_addu_qb (a, b);
144 NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
146 return __builtin_mips_subq_ph (a, b);
149 NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
151 return __builtin_mips_subu_qb (a, b);
154 NOMIPS16 void test_MIPS_DSP ()
156 v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
157 v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
158 q31 q31_a,q31_b,q31_c,q31_r,q31_s;
159 /* To protect the multiplication-related tests from being optimized
161 volatile i32 i32_a,i32_b,i32_c,i32_r,i32_s;
162 volatile ui32 ui32_a,ui32_b,ui32_c;
163 a64 a64_a,a64_b,a64_c,a64_r,a64_s;
169 v2q15_a = (v2q15) {0x1234, 0x5678};
170 v2q15_b = (v2q15) {0x6f89, 0x1111};
171 v2q15_s = (v2q15) {0x81bd, 0x6789};
172 v2q15_r = add_v2q15 (v2q15_a, v2q15_b);
178 v2q15_a = (v2q15) {0x1234, 0x5678};
179 v2q15_b = (v2q15) {0x6f89, 0x1111};
180 v2q15_s = (v2q15) {0x7fff, 0x6789};
181 v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b);
190 q31_r = __builtin_mips_addq_s_w (q31_a, q31_b);
194 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
195 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
196 v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89};
197 v4i8_r = add_v4i8 (v4i8_a, v4i8_b);
203 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
204 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
205 v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89};
206 v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b);
212 v2q15_a = (v2q15) {0x1234, 0x5678};
213 v2q15_b = (v2q15) {0x6f89, 0x1111};
214 v2q15_s = (v2q15) {0xa2ab, 0x4567};
215 v2q15_r = sub_v2q15 (v2q15_a, v2q15_b);
221 v2q15_a = (v2q15) {0x8000, 0x5678};
222 v2q15_b = (v2q15) {0x6f89, 0x1111};
223 v2q15_s = (v2q15) {0x8000, 0x4567};
224 v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b);
233 q31_r = __builtin_mips_subq_s_w (q31_a, q31_b);
237 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
238 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
239 v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67};
240 v4i8_r = sub_v4i8 (v4i8_a, v4i8_b);
246 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
247 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
248 v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67};
249 v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b);
258 i32_r = __builtin_mips_addsc (i32_a, i32_b);
265 i32_r = __builtin_mips_addwc (i32_a, i32_b);
272 i32_r = __builtin_mips_modsub (i32_a, i32_b);
276 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
278 i32_r = __builtin_mips_raddu_w_qb (v4i8_a);
282 v2q15_a = (v2q15) {0x8000, 0x8134};
283 v2q15_s = (v2q15) {0x7fff, 0x7ecc};
284 v2q15_r = __builtin_mips_absq_s_ph (v2q15_a);
290 q31_a = (q31) 0x80000000;
291 q31_s = (q31) 0x7fffffff;
292 q31_r = __builtin_mips_absq_s_w (q31_a);
296 v2q15_a = (v2q15) {0x9999, 0x5612};
297 v2q15_b = (v2q15) {0x5612, 0x3333};
299 v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56};
301 v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33};
302 v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b);
311 v2q15_s = (v2q15) {0x4444, 0x1234};
313 v2q15_s = (v2q15) {0x1234, 0x4444};
314 v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b);
323 v2q15_s = (v2q15) {0x4444, 0x1235};
325 v2q15_s = (v2q15) {0x1235, 0x4444};
326 v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b);
332 v2q15_a = (v2q15) {0x9999, 0x5612};
333 v2q15_b = (v2q15) {0x5612, 0x3333};
335 v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac};
337 v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66};
338 v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b);
344 v2q15_a = (v2q15) {0x3589, 0x4444};
349 q31_r = __builtin_mips_preceq_w_phl (v2q15_a);
353 v2q15_a = (v2q15) {0x3589, 0x4444};
358 q31_r = __builtin_mips_preceq_w_phr (v2q15_a);
362 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
364 v2q15_s = (v2q15) {0x2b00, 0x1980};
366 v2q15_s = (v2q15) {0x0900, 0x2b00};
367 v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a);
373 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
375 v2q15_s = (v2q15) {0x0900, 0x2b00};
377 v2q15_s = (v2q15) {0x2b00, 0x1980};
378 v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a);
384 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
386 v2q15_s = (v2q15) {0x2b00, 0x1980};
388 v2q15_s = (v2q15) {0x0900, 0x2b00};
389 v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a);
395 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
397 v2q15_s = (v2q15) {0x0900, 0x2b00};
399 v2q15_s = (v2q15) {0x2b00, 0x1980};
400 v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a);
406 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
408 v2q15_s = (v2q15) {0x56, 0x33};
410 v2q15_s = (v2q15) {0x12, 0x56};
411 v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a);
417 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
419 v2q15_s = (v2q15) {0x12, 0x56};
421 v2q15_s = (v2q15) {0x56, 0x33};
422 v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a);
428 v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
430 v2q15_s = (v2q15) {0x99, 0x33};
432 v2q15_s = (v2q15) {0x12, 0x56};
433 v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a);
439 v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
441 v2q15_s = (v2q15) {0x12, 0x56};
443 v2q15_s = (v2q15) {0x99, 0x33};
444 v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a);
450 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
451 v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0};
452 v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2);
458 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
460 v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0};
461 v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b);
467 v2q15_a = (v2q15) {0x1234, 0x5678};
468 v2q15_s = (v2q15) {0x48d0, 0x59e0};
469 v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2);
475 v2q15_a = (v2q15) {0x1234, 0x5678};
477 v2q15_s = (v2q15) {0x2468, 0xacf0};
478 v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b);
484 v2q15_a = (v2q15) {0x1234, 0x5678};
485 v2q15_s = (v2q15) {0x48d0, 0x7fff};
486 v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2);
492 v2q15_a = (v2q15) {0x1234, 0x5678};
494 v2q15_s = (v2q15) {0x2468, 0x7fff};
495 v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
503 q31_r = __builtin_mips_shll_s_w (q31_a, 2);
510 q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
514 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
515 v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e};
516 v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2);
522 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
524 v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c};
525 v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b);
531 v2q15_a = (v2q15) {0x1234, 0x5678};
532 v2q15_s = (v2q15) {0x48d, 0x159e};
533 v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2);
539 v2q15_a = (v2q15) {0x1234, 0x5678};
541 v2q15_s = (v2q15) {0x91a, 0x2b3c};
542 v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b);
548 v2q15_a = (v2q15) {0x1234, 0x5678};
549 v2q15_s = (v2q15) {0x48d, 0x159e};
550 v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2);
556 v2q15_a = (v2q15) {0x1234, 0x5678};
558 v2q15_s = (v2q15) {0x247, 0xacf};
559 v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b);
567 q31_r = __builtin_mips_shra_r_w (q31_a, 2);
574 q31_r = __builtin_mips_shra_r_w (q31_a, i32_b);
578 v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
579 v2q15_b = (v2q15) {0x6f89, 0x1111};
581 v2q15_s = (v2q15) {0xffff, 0x4444};
583 v2q15_s = (v2q15) {0x6f89, 0x2222};
584 v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b);
590 v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
591 v2q15_b = (v2q15) {0x6f89, 0x1111};
593 v2q15_s = (v2q15) {0x6f89, 0x2222};
595 v2q15_s = (v2q15) {0xffff, 0x4444};
596 v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b);
602 v2q15_a = (v2q15) {0x1234, 0x5678};
603 v2q15_b = (v2q15) {0x6f89, 0x1111};
604 v2q15_s = (v2q15) {0x0fdd, 0x0b87};
605 v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b);
611 v2q15_a = (v2q15) {0x8000, 0x8000};
612 v2q15_b = (v2q15) {0x8000, 0x8000};
614 q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b);
618 v2q15_a = (v2q15) {0x8000, 0x8000};
619 v2q15_b = (v2q15) {0x8000, 0x8000};
621 q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b);
627 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
628 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
633 a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c);
638 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
639 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
644 a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c);
649 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
650 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
655 a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c);
660 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
661 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
666 a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c);
671 v2q15_b = (v2q15) {0x8000, 0x5678};
672 v2q15_c = (v2q15) {0x8000, 0x1111};
674 a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
679 v2q15_b = (v2q15) {0x8000, 0x5678};
680 v2q15_c = (v2q15) {0x8000, 0x1111};
681 a64_s = 0xffffffff7478a522LL;
682 a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c);
687 v2q15_b = (v2q15) {0x8000, 0x5678};
688 v2q15_c = (v2q15) {0x8000, 0x1111};
690 a64_s = 0xffffffff8b877d02LL;
693 a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
700 a64_s = 0x7fffffffffffffffLL;
701 a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c);
708 a64_s = 0x8000000000001112LL;
709 a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c);
714 v2q15_b = (v2q15) {0x8000, 0x1};
715 v2q15_c = (v2q15) {0x8000, 0x2};
720 a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c);
725 v2q15_b = (v2q15) {0x8000, 0x1};
726 v2q15_c = (v2q15) {0x8000, 0x2};
731 a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c);
736 v2q15_b = (v2q15) {0x8000, 0x1};
737 v2q15_c = (v2q15) {0x8000, 0x2};
742 a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c);
747 v2q15_b = (v2q15) {0x8000, 0x1};
748 v2q15_c = (v2q15) {0x8000, 0x2};
753 a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c);
760 i32_r = __builtin_mips_bitrev (i32_a);
764 i32_a = 0x00000208; // pos is 8, size is 4
765 __builtin_mips_wrdsp (i32_a, 31);
769 i32_r = __builtin_mips_insv (i32_a, i32_b);
773 v4i8_s = (v4i8) {1, 1, 1, 1};
774 v4i8_r = __builtin_mips_repl_qb (1);
781 v4i8_s = (v4i8) {99, 99, 99, 99};
782 v4i8_r = __builtin_mips_repl_qb (i32_a);
788 v2q15_s = (v2q15) {30, 30};
789 v2q15_r = __builtin_mips_repl_ph (30);
796 v2q15_s = (v2q15) {0x5612, 0x5612};
797 v2q15_r = __builtin_mips_repl_ph (i32_a);
803 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
804 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
809 __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b);
810 i32_r = __builtin_mips_rddsp (16);
814 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
815 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
820 __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b);
821 i32_r = __builtin_mips_rddsp (16);
825 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
826 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
831 __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b);
832 i32_r = __builtin_mips_rddsp (16);
836 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
837 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
842 i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b);
846 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
847 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
852 i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b);
856 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
857 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
862 i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b);
866 __builtin_mips_wrdsp (0,31); // Clear all condition code bits.
867 v2q15_a = (v2q15) {0x1234, 0x5678};
868 v2q15_b = (v2q15) {0x1234, 0x7856};
873 __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b);
874 i32_r = __builtin_mips_rddsp (16);
878 v2q15_a = (v2q15) {0x1234, 0x5678};
879 v2q15_b = (v2q15) {0x1234, 0x7856};
884 __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b);
885 i32_r = __builtin_mips_rddsp (16);
889 v2q15_a = (v2q15) {0x1234, 0x5678};
890 v2q15_b = (v2q15) {0x1234, 0x7856};
892 __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b);
893 i32_r = __builtin_mips_rddsp (16);
897 i32_a = 0x0a000000; // cc: 0000 1010
898 __builtin_mips_wrdsp (i32_a, 31);
899 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
900 v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87};
902 v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78};
904 v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87};
905 v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b);
911 i32_a = 0x02000000; // cc: 0000 0010
912 __builtin_mips_wrdsp (i32_a, 31);
913 v2q15_a = (v2q15) {0x1234, 0x5678};
914 v2q15_b = (v2q15) {0x2143, 0x6587};
916 v2q15_s = (v2q15) {0x2143, 0x5678};
918 v2q15_s = (v2q15) {0x1234, 0x6587};
919 v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b);
925 v2q15_a = (v2q15) {0x1234, 0x5678};
926 v2q15_b = (v2q15) {0x1234, 0x7856};
928 v2q15_s = (v2q15) {0x7856, 0x1234};
930 v2q15_s = (v2q15) {0x5678, 0x1234};
931 v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b);
938 a64_a = 0x1234567887654321LL;
940 i32_r = __builtin_mips_extr_w (a64_a, 4);
944 a64_a = 0x1234567887658321LL;
946 i32_r = __builtin_mips_extr_r_w (a64_a, 16);
950 a64_a = 0x12345677fffffff8LL;
952 i32_r = __builtin_mips_extr_rs_w (a64_a, 4);
956 a64_a = 0x1234567887658321LL;
958 i32_r = __builtin_mips_extr_s_h (a64_a, 16);
962 a64_a = 0x0000007887658321LL;
965 i32_r = __builtin_mips_extr_s_h (a64_a, i32_b);
969 a64_a = 0x1234567887654321LL;
972 i32_r = __builtin_mips_extr_w (a64_a, i32_b);
976 a64_a = 0x1234567887658321LL;
979 i32_r = __builtin_mips_extr_r_w (a64_a, i32_b);
983 a64_a = 0x12345677fffffff8LL;
986 i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b);
990 i32_a = 0x0000021f; // pos is 31
991 __builtin_mips_wrdsp (i32_a, 31);
992 a64_a = 0x1234567887654321LL;
994 i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits
998 i32_a = 0x0000021f; // pos is 31
999 __builtin_mips_wrdsp (i32_a, 31);
1000 a64_a = 0x1234567887654321LL;
1001 i32_b = 7; // size is 8. NOTE!! we should use 7
1003 i32_r = __builtin_mips_extp (a64_a, i32_b);
1007 i32_a = 0x0000021f; // pos is 31
1008 __builtin_mips_wrdsp (i32_a, 31);
1009 a64_a = 0x1234567887654321LL;
1011 i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits
1015 i32_s = 0x0000021b; // pos is 27
1016 i32_r = __builtin_mips_rddsp (31);
1020 i32_a = 0x0000021f; // pos is 31
1021 __builtin_mips_wrdsp (i32_a, 31);
1022 a64_a = 0x1234567887654321LL;
1023 i32_b = 11; // size is 12. NOTE!!! We should use 11
1025 i32_r = __builtin_mips_extpdp (a64_a, i32_b);
1029 i32_s = 0x00000213; // pos is 19
1030 i32_r = __builtin_mips_rddsp (31);
1034 a64_a = 0x1234567887654321LL;
1035 a64_s = 0x0012345678876543LL;
1036 a64_r = __builtin_mips_shilo (a64_a, 8);
1040 a64_a = 0x1234567887654321LL;
1042 a64_s = 0x5678876543210000LL;
1043 a64_r = __builtin_mips_shilo (a64_a, i32_b);
1048 __builtin_mips_wrdsp (i32_a, 31);
1049 a64_a = 0x1234567887654321LL;
1051 a64_s = 0x8765432111112222LL;
1052 a64_r = __builtin_mips_mthlip (a64_a, i32_b);
1056 i32_r = __builtin_mips_rddsp (31);
1062 __builtin_mips_wrdsp (i32_a, 63);
1064 i32_r = __builtin_mips_rddsp (63);
1071 i32_r = __builtin_mips_lbux (ptr_a, i32_b);
1081 i32_r = __builtin_mips_lhx (ptr_a, i32_b);
1091 i32_r = __builtin_mips_lwx (ptr_a, i32_b);
1095 i32_a = 0x00000220; // pos is 32, size is 4
1096 __builtin_mips_wrdsp (i32_a, 63);
1098 i32_r = __builtin_mips_bposge32 ();
1106 a64_s = 0xF7776EEF12345678LL;
1107 a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
1114 ui32_b = 0x80000000;
1115 ui32_c = 0x11112222;
1116 a64_s = 0x0888911112345678LL;
1117 a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
1126 a64_s = 0x0888911112345678LL;
1127 a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
1134 ui32_b = 0x80000000;
1135 ui32_c = 0x11112222;
1136 a64_s = 0xF7776EEF12345678LL;
1137 a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
1145 a64_s = 0xF7776EEF00000000LL;
1146 a64_r = __builtin_mips_mult (i32_a, i32_b);
1152 ui32_a = 0x80000000;
1153 ui32_b = 0x11112222;
1154 a64_s = 0x888911100000000LL;
1155 a64_r = __builtin_mips_multu (ui32_a, ui32_b);