1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
34 #include "insn-config.h"
43 /* Simplification and canonicalization of RTL. */
45 /* Much code operates on (low, high) pairs; the low value is an
46 unsigned wide int, the high value a signed wide int. We
47 occasionally need to sign extend from low to high as if low were a
49 #define HWI_SIGN_EXTEND(low) \
50 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
52 static rtx neg_const_int (enum machine_mode, rtx);
53 static int simplify_plus_minus_op_data_cmp (const void *, const void *);
54 static rtx simplify_plus_minus (enum rtx_code, enum machine_mode, rtx,
56 static rtx simplify_immed_subreg (enum machine_mode, rtx, enum machine_mode,
58 static rtx simplify_associative_operation (enum rtx_code, enum machine_mode,
61 /* Negate a CONST_INT rtx, truncating (because a conversion from a
62 maximally negative number can overflow). */
64 neg_const_int (enum machine_mode mode, rtx i)
66 return gen_int_mode (- INTVAL (i), mode);
70 /* Make a binary operation by properly ordering the operands and
71 seeing if the expression folds. */
74 simplify_gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0,
79 /* Put complex operands first and constants second if commutative. */
80 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
81 && swap_commutative_operands_p (op0, op1))
82 tem = op0, op0 = op1, op1 = tem;
84 /* If this simplifies, do it. */
85 tem = simplify_binary_operation (code, mode, op0, op1);
89 /* Handle addition and subtraction specially. Otherwise, just form
92 if (code == PLUS || code == MINUS)
94 tem = simplify_plus_minus (code, mode, op0, op1, 1);
99 return gen_rtx_fmt_ee (code, mode, op0, op1);
102 /* If X is a MEM referencing the constant pool, return the real value.
103 Otherwise return X. */
105 avoid_constant_pool_reference (rtx x)
108 enum machine_mode cmode;
110 switch (GET_CODE (x))
116 /* Handle float extensions of constant pool references. */
118 c = avoid_constant_pool_reference (tmp);
119 if (c != tmp && GET_CODE (c) == CONST_DOUBLE)
123 REAL_VALUE_FROM_CONST_DOUBLE (d, c);
124 return CONST_DOUBLE_FROM_REAL_VALUE (d, GET_MODE (x));
134 /* Call target hook to avoid the effects of -fpic etc.... */
135 addr = (*targetm.delegitimize_address) (addr);
137 if (GET_CODE (addr) == LO_SUM)
138 addr = XEXP (addr, 1);
140 if (GET_CODE (addr) != SYMBOL_REF
141 || ! CONSTANT_POOL_ADDRESS_P (addr))
144 c = get_pool_constant (addr);
145 cmode = get_pool_mode (addr);
147 /* If we're accessing the constant in a different mode than it was
148 originally stored, attempt to fix that up via subreg simplifications.
149 If that fails we have no choice but to return the original memory. */
150 if (cmode != GET_MODE (x))
152 c = simplify_subreg (GET_MODE (x), c, cmode, 0);
159 /* Make a unary operation by first seeing if it folds and otherwise making
160 the specified operation. */
163 simplify_gen_unary (enum rtx_code code, enum machine_mode mode, rtx op,
164 enum machine_mode op_mode)
168 /* If this simplifies, use it. */
169 if ((tem = simplify_unary_operation (code, mode, op, op_mode)) != 0)
172 return gen_rtx_fmt_e (code, mode, op);
175 /* Likewise for ternary operations. */
178 simplify_gen_ternary (enum rtx_code code, enum machine_mode mode,
179 enum machine_mode op0_mode, rtx op0, rtx op1, rtx op2)
183 /* If this simplifies, use it. */
184 if (0 != (tem = simplify_ternary_operation (code, mode, op0_mode,
188 return gen_rtx_fmt_eee (code, mode, op0, op1, op2);
191 /* Likewise, for relational operations.
192 CMP_MODE specifies mode comparison is done in.
196 simplify_gen_relational (enum rtx_code code, enum machine_mode mode,
197 enum machine_mode cmp_mode, rtx op0, rtx op1)
201 if (cmp_mode == VOIDmode)
202 cmp_mode = GET_MODE (op0);
203 if (cmp_mode == VOIDmode)
204 cmp_mode = GET_MODE (op1);
206 if (cmp_mode != VOIDmode)
208 tem = simplify_relational_operation (code, cmp_mode, op0, op1);
212 #ifdef FLOAT_STORE_FLAG_VALUE
213 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
216 if (tem == const0_rtx)
217 return CONST0_RTX (mode);
218 if (tem != const_true_rtx)
220 val = FLOAT_STORE_FLAG_VALUE (mode);
221 return CONST_DOUBLE_FROM_REAL_VALUE (val, mode);
228 /* For the following tests, ensure const0_rtx is op1. */
229 if (swap_commutative_operands_p (op0, op1)
230 || (op0 == const0_rtx && op1 != const0_rtx))
231 tem = op0, op0 = op1, op1 = tem, code = swap_condition (code);
233 /* If op0 is a compare, extract the comparison arguments from it. */
234 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
235 return simplify_gen_relational (code, mode, VOIDmode,
236 XEXP (op0, 0), XEXP (op0, 1));
238 /* If op0 is a comparison, extract the comparison arguments form it. */
239 if (COMPARISON_P (op0) && op1 == const0_rtx)
243 if (GET_MODE (op0) == mode)
245 return simplify_gen_relational (GET_CODE (op0), mode, VOIDmode,
246 XEXP (op0, 0), XEXP (op0, 1));
250 enum rtx_code new = reversed_comparison_code (op0, NULL_RTX);
252 return simplify_gen_relational (new, mode, VOIDmode,
253 XEXP (op0, 0), XEXP (op0, 1));
257 return gen_rtx_fmt_ee (code, mode, op0, op1);
260 /* Replace all occurrences of OLD in X with NEW and try to simplify the
261 resulting RTX. Return a new RTX which is as simplified as possible. */
264 simplify_replace_rtx (rtx x, rtx old, rtx new)
266 enum rtx_code code = GET_CODE (x);
267 enum machine_mode mode = GET_MODE (x);
268 enum machine_mode op_mode;
271 /* If X is OLD, return NEW. Otherwise, if this is an expression, try
272 to build a new expression substituting recursively. If we can't do
273 anything, return our input. */
278 switch (GET_RTX_CLASS (code))
282 op_mode = GET_MODE (op0);
283 op0 = simplify_replace_rtx (op0, old, new);
284 if (op0 == XEXP (x, 0))
286 return simplify_gen_unary (code, mode, op0, op_mode);
290 op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
291 op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
292 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
294 return simplify_gen_binary (code, mode, op0, op1);
297 case RTX_COMM_COMPARE:
300 op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
301 op0 = simplify_replace_rtx (op0, old, new);
302 op1 = simplify_replace_rtx (op1, old, new);
303 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
305 return simplify_gen_relational (code, mode, op_mode, op0, op1);
308 case RTX_BITFIELD_OPS:
310 op_mode = GET_MODE (op0);
311 op0 = simplify_replace_rtx (op0, old, new);
312 op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
313 op2 = simplify_replace_rtx (XEXP (x, 2), old, new);
314 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2))
316 if (op_mode == VOIDmode)
317 op_mode = GET_MODE (op0);
318 return simplify_gen_ternary (code, mode, op_mode, op0, op1, op2);
321 /* The only case we try to handle is a SUBREG. */
324 op0 = simplify_replace_rtx (SUBREG_REG (x), old, new);
325 if (op0 == SUBREG_REG (x))
327 op0 = simplify_gen_subreg (GET_MODE (x), op0,
328 GET_MODE (SUBREG_REG (x)),
330 return op0 ? op0 : x;
337 op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
338 if (op0 == XEXP (x, 0))
340 return replace_equiv_address_nv (x, op0);
342 else if (code == LO_SUM)
344 op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
345 op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
347 /* (lo_sum (high x) x) -> x */
348 if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1))
351 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
353 return gen_rtx_LO_SUM (mode, op0, op1);
355 else if (code == REG)
357 if (REG_P (old) && REGNO (x) == REGNO (old))
368 /* Try to simplify a unary operation CODE whose output mode is to be
369 MODE with input operand OP whose mode was originally OP_MODE.
370 Return zero if no simplification can be made. */
372 simplify_unary_operation (enum rtx_code code, enum machine_mode mode,
373 rtx op, enum machine_mode op_mode)
375 unsigned int width = GET_MODE_BITSIZE (mode);
376 rtx trueop = avoid_constant_pool_reference (op);
378 if (code == VEC_DUPLICATE)
380 if (!VECTOR_MODE_P (mode))
382 if (GET_MODE (trueop) != VOIDmode
383 && !VECTOR_MODE_P (GET_MODE (trueop))
384 && GET_MODE_INNER (mode) != GET_MODE (trueop))
386 if (GET_MODE (trueop) != VOIDmode
387 && VECTOR_MODE_P (GET_MODE (trueop))
388 && GET_MODE_INNER (mode) != GET_MODE_INNER (GET_MODE (trueop)))
390 if (GET_CODE (trueop) == CONST_INT || GET_CODE (trueop) == CONST_DOUBLE
391 || GET_CODE (trueop) == CONST_VECTOR)
393 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
394 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
395 rtvec v = rtvec_alloc (n_elts);
398 if (GET_CODE (trueop) != CONST_VECTOR)
399 for (i = 0; i < n_elts; i++)
400 RTVEC_ELT (v, i) = trueop;
403 enum machine_mode inmode = GET_MODE (trueop);
404 int in_elt_size = GET_MODE_SIZE (GET_MODE_INNER (inmode));
405 unsigned in_n_elts = (GET_MODE_SIZE (inmode) / in_elt_size);
407 if (in_n_elts >= n_elts || n_elts % in_n_elts)
409 for (i = 0; i < n_elts; i++)
410 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop, i % in_n_elts);
412 return gen_rtx_CONST_VECTOR (mode, v);
415 else if (GET_CODE (op) == CONST)
416 return simplify_unary_operation (code, mode, XEXP (op, 0), op_mode);
418 if (VECTOR_MODE_P (mode) && GET_CODE (trueop) == CONST_VECTOR)
420 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
421 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
422 enum machine_mode opmode = GET_MODE (trueop);
423 int op_elt_size = GET_MODE_SIZE (GET_MODE_INNER (opmode));
424 unsigned op_n_elts = (GET_MODE_SIZE (opmode) / op_elt_size);
425 rtvec v = rtvec_alloc (n_elts);
428 if (op_n_elts != n_elts)
431 for (i = 0; i < n_elts; i++)
433 rtx x = simplify_unary_operation (code, GET_MODE_INNER (mode),
434 CONST_VECTOR_ELT (trueop, i),
435 GET_MODE_INNER (opmode));
438 RTVEC_ELT (v, i) = x;
440 return gen_rtx_CONST_VECTOR (mode, v);
443 /* The order of these tests is critical so that, for example, we don't
444 check the wrong mode (input vs. output) for a conversion operation,
445 such as FIX. At some point, this should be simplified. */
447 if (code == FLOAT && GET_MODE (trueop) == VOIDmode
448 && (GET_CODE (trueop) == CONST_DOUBLE || GET_CODE (trueop) == CONST_INT))
450 HOST_WIDE_INT hv, lv;
453 if (GET_CODE (trueop) == CONST_INT)
454 lv = INTVAL (trueop), hv = HWI_SIGN_EXTEND (lv);
456 lv = CONST_DOUBLE_LOW (trueop), hv = CONST_DOUBLE_HIGH (trueop);
458 REAL_VALUE_FROM_INT (d, lv, hv, mode);
459 d = real_value_truncate (mode, d);
460 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
462 else if (code == UNSIGNED_FLOAT && GET_MODE (trueop) == VOIDmode
463 && (GET_CODE (trueop) == CONST_DOUBLE
464 || GET_CODE (trueop) == CONST_INT))
466 HOST_WIDE_INT hv, lv;
469 if (GET_CODE (trueop) == CONST_INT)
470 lv = INTVAL (trueop), hv = HWI_SIGN_EXTEND (lv);
472 lv = CONST_DOUBLE_LOW (trueop), hv = CONST_DOUBLE_HIGH (trueop);
474 if (op_mode == VOIDmode)
476 /* We don't know how to interpret negative-looking numbers in
477 this case, so don't try to fold those. */
481 else if (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT * 2)
484 hv = 0, lv &= GET_MODE_MASK (op_mode);
486 REAL_VALUE_FROM_UNSIGNED_INT (d, lv, hv, mode);
487 d = real_value_truncate (mode, d);
488 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
491 if (GET_CODE (trueop) == CONST_INT
492 && width <= HOST_BITS_PER_WIDE_INT && width > 0)
494 HOST_WIDE_INT arg0 = INTVAL (trueop);
508 val = (arg0 >= 0 ? arg0 : - arg0);
512 /* Don't use ffs here. Instead, get low order bit and then its
513 number. If arg0 is zero, this will return 0, as desired. */
514 arg0 &= GET_MODE_MASK (mode);
515 val = exact_log2 (arg0 & (- arg0)) + 1;
519 arg0 &= GET_MODE_MASK (mode);
520 if (arg0 == 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode, val))
523 val = GET_MODE_BITSIZE (mode) - floor_log2 (arg0) - 1;
527 arg0 &= GET_MODE_MASK (mode);
530 /* Even if the value at zero is undefined, we have to come
531 up with some replacement. Seems good enough. */
532 if (! CTZ_DEFINED_VALUE_AT_ZERO (mode, val))
533 val = GET_MODE_BITSIZE (mode);
536 val = exact_log2 (arg0 & -arg0);
540 arg0 &= GET_MODE_MASK (mode);
543 val++, arg0 &= arg0 - 1;
547 arg0 &= GET_MODE_MASK (mode);
550 val++, arg0 &= arg0 - 1;
559 /* When zero-extending a CONST_INT, we need to know its
561 if (op_mode == VOIDmode)
563 if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT)
565 /* If we were really extending the mode,
566 we would have to distinguish between zero-extension
567 and sign-extension. */
568 if (width != GET_MODE_BITSIZE (op_mode))
572 else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
573 val = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
579 if (op_mode == VOIDmode)
581 if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT)
583 /* If we were really extending the mode,
584 we would have to distinguish between zero-extension
585 and sign-extension. */
586 if (width != GET_MODE_BITSIZE (op_mode))
590 else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
593 = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
595 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (op_mode) - 1)))
596 val -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
613 val = trunc_int_for_mode (val, mode);
615 return GEN_INT (val);
618 /* We can do some operations on integer CONST_DOUBLEs. Also allow
619 for a DImode operation on a CONST_INT. */
620 else if (GET_MODE (trueop) == VOIDmode
621 && width <= HOST_BITS_PER_WIDE_INT * 2
622 && (GET_CODE (trueop) == CONST_DOUBLE
623 || GET_CODE (trueop) == CONST_INT))
625 unsigned HOST_WIDE_INT l1, lv;
626 HOST_WIDE_INT h1, hv;
628 if (GET_CODE (trueop) == CONST_DOUBLE)
629 l1 = CONST_DOUBLE_LOW (trueop), h1 = CONST_DOUBLE_HIGH (trueop);
631 l1 = INTVAL (trueop), h1 = HWI_SIGN_EXTEND (l1);
641 neg_double (l1, h1, &lv, &hv);
646 neg_double (l1, h1, &lv, &hv);
658 lv = HOST_BITS_PER_WIDE_INT + exact_log2 (h1 & -h1) + 1;
661 lv = exact_log2 (l1 & -l1) + 1;
667 lv = GET_MODE_BITSIZE (mode) - floor_log2 (h1) - 1
668 - HOST_BITS_PER_WIDE_INT;
670 lv = GET_MODE_BITSIZE (mode) - floor_log2 (l1) - 1;
671 else if (! CLZ_DEFINED_VALUE_AT_ZERO (mode, lv))
672 lv = GET_MODE_BITSIZE (mode);
678 lv = exact_log2 (l1 & -l1);
680 lv = HOST_BITS_PER_WIDE_INT + exact_log2 (h1 & -h1);
681 else if (! CTZ_DEFINED_VALUE_AT_ZERO (mode, lv))
682 lv = GET_MODE_BITSIZE (mode);
705 /* This is just a change-of-mode, so do nothing. */
710 if (op_mode == VOIDmode)
713 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT)
717 lv = l1 & GET_MODE_MASK (op_mode);
721 if (op_mode == VOIDmode
722 || GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT)
726 lv = l1 & GET_MODE_MASK (op_mode);
727 if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT
728 && (lv & ((HOST_WIDE_INT) 1
729 << (GET_MODE_BITSIZE (op_mode) - 1))) != 0)
730 lv -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
732 hv = HWI_SIGN_EXTEND (lv);
743 return immed_double_const (lv, hv, mode);
746 else if (GET_CODE (trueop) == CONST_DOUBLE
747 && GET_MODE_CLASS (mode) == MODE_FLOAT)
749 REAL_VALUE_TYPE d, t;
750 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop);
755 if (HONOR_SNANS (mode) && real_isnan (&d))
757 real_sqrt (&t, mode, &d);
761 d = REAL_VALUE_ABS (d);
764 d = REAL_VALUE_NEGATE (d);
767 d = real_value_truncate (mode, d);
770 /* All this does is change the mode. */
773 real_arithmetic (&d, FIX_TRUNC_EXPR, &d, NULL);
780 real_to_target (tmp, &d, GET_MODE (trueop));
781 for (i = 0; i < 4; i++)
783 real_from_target (&d, tmp, mode);
788 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
791 else if (GET_CODE (trueop) == CONST_DOUBLE
792 && GET_MODE_CLASS (GET_MODE (trueop)) == MODE_FLOAT
793 && GET_MODE_CLASS (mode) == MODE_INT
794 && width <= 2*HOST_BITS_PER_WIDE_INT && width > 0)
796 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
797 operators are intentionally left unspecified (to ease implementation
798 by target backends), for consistency, this routine implements the
799 same semantics for constant folding as used by the middle-end. */
801 HOST_WIDE_INT xh, xl, th, tl;
802 REAL_VALUE_TYPE x, t;
803 REAL_VALUE_FROM_CONST_DOUBLE (x, trueop);
807 if (REAL_VALUE_ISNAN (x))
810 /* Test against the signed upper bound. */
811 if (width > HOST_BITS_PER_WIDE_INT)
813 th = ((unsigned HOST_WIDE_INT) 1
814 << (width - HOST_BITS_PER_WIDE_INT - 1)) - 1;
820 tl = ((unsigned HOST_WIDE_INT) 1 << (width - 1)) - 1;
822 real_from_integer (&t, VOIDmode, tl, th, 0);
823 if (REAL_VALUES_LESS (t, x))
830 /* Test against the signed lower bound. */
831 if (width > HOST_BITS_PER_WIDE_INT)
833 th = (HOST_WIDE_INT) -1 << (width - HOST_BITS_PER_WIDE_INT - 1);
839 tl = (HOST_WIDE_INT) -1 << (width - 1);
841 real_from_integer (&t, VOIDmode, tl, th, 0);
842 if (REAL_VALUES_LESS (x, t))
848 REAL_VALUE_TO_INT (&xl, &xh, x);
852 if (REAL_VALUE_ISNAN (x) || REAL_VALUE_NEGATIVE (x))
855 /* Test against the unsigned upper bound. */
856 if (width == 2*HOST_BITS_PER_WIDE_INT)
861 else if (width >= HOST_BITS_PER_WIDE_INT)
863 th = ((unsigned HOST_WIDE_INT) 1
864 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
870 tl = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
872 real_from_integer (&t, VOIDmode, tl, th, 1);
873 if (REAL_VALUES_LESS (t, x))
880 REAL_VALUE_TO_INT (&xl, &xh, x);
886 return immed_double_const (xl, xh, mode);
889 /* This was formerly used only for non-IEEE float.
890 eggert@twinsun.com says it is safe for IEEE also. */
893 enum rtx_code reversed;
896 /* There are some simplifications we can do even if the operands
901 /* (not (not X)) == X. */
902 if (GET_CODE (op) == NOT)
905 /* (not (eq X Y)) == (ne X Y), etc. */
906 if (COMPARISON_P (op)
907 && (mode == BImode || STORE_FLAG_VALUE == -1)
908 && ((reversed = reversed_comparison_code (op, NULL_RTX))
910 return simplify_gen_relational (reversed, mode, VOIDmode,
911 XEXP (op, 0), XEXP (op, 1));
913 /* (not (plus X -1)) can become (neg X). */
914 if (GET_CODE (op) == PLUS
915 && XEXP (op, 1) == constm1_rtx)
916 return simplify_gen_unary (NEG, mode, XEXP (op, 0), mode);
918 /* Similarly, (not (neg X)) is (plus X -1). */
919 if (GET_CODE (op) == NEG)
920 return plus_constant (XEXP (op, 0), -1);
922 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
923 if (GET_CODE (op) == XOR
924 && GET_CODE (XEXP (op, 1)) == CONST_INT
925 && (temp = simplify_unary_operation (NOT, mode,
928 return simplify_gen_binary (XOR, mode, XEXP (op, 0), temp);
931 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
932 operands other than 1, but that is not valid. We could do a
933 similar simplification for (not (lshiftrt C X)) where C is
934 just the sign bit, but this doesn't seem common enough to
936 if (GET_CODE (op) == ASHIFT
937 && XEXP (op, 0) == const1_rtx)
939 temp = simplify_gen_unary (NOT, mode, const1_rtx, mode);
940 return simplify_gen_binary (ROTATE, mode, temp, XEXP (op, 1));
943 /* If STORE_FLAG_VALUE is -1, (not (comparison X Y)) can be done
944 by reversing the comparison code if valid. */
945 if (STORE_FLAG_VALUE == -1
947 && (reversed = reversed_comparison_code (op, NULL_RTX))
949 return simplify_gen_relational (reversed, mode, VOIDmode,
950 XEXP (op, 0), XEXP (op, 1));
952 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
953 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
954 so we can perform the above simplification. */
956 if (STORE_FLAG_VALUE == -1
957 && GET_CODE (op) == ASHIFTRT
958 && GET_CODE (XEXP (op, 1)) == CONST_INT
959 && INTVAL (XEXP (op, 1)) == GET_MODE_BITSIZE (mode) - 1)
960 return simplify_gen_relational (GE, mode, VOIDmode,
961 XEXP (op, 0), const0_rtx);
966 /* (neg (neg X)) == X. */
967 if (GET_CODE (op) == NEG)
970 /* (neg (plus X 1)) can become (not X). */
971 if (GET_CODE (op) == PLUS
972 && XEXP (op, 1) == const1_rtx)
973 return simplify_gen_unary (NOT, mode, XEXP (op, 0), mode);
975 /* Similarly, (neg (not X)) is (plus X 1). */
976 if (GET_CODE (op) == NOT)
977 return plus_constant (XEXP (op, 0), 1);
979 /* (neg (minus X Y)) can become (minus Y X). This transformation
980 isn't safe for modes with signed zeros, since if X and Y are
981 both +0, (minus Y X) is the same as (minus X Y). If the
982 rounding mode is towards +infinity (or -infinity) then the two
983 expressions will be rounded differently. */
984 if (GET_CODE (op) == MINUS
985 && !HONOR_SIGNED_ZEROS (mode)
986 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
987 return simplify_gen_binary (MINUS, mode, XEXP (op, 1),
990 if (GET_CODE (op) == PLUS
991 && !HONOR_SIGNED_ZEROS (mode)
992 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
994 /* (neg (plus A C)) is simplified to (minus -C A). */
995 if (GET_CODE (XEXP (op, 1)) == CONST_INT
996 || GET_CODE (XEXP (op, 1)) == CONST_DOUBLE)
998 temp = simplify_unary_operation (NEG, mode, XEXP (op, 1),
1001 return simplify_gen_binary (MINUS, mode, temp,
1005 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
1006 temp = simplify_gen_unary (NEG, mode, XEXP (op, 0), mode);
1007 return simplify_gen_binary (MINUS, mode, temp, XEXP (op, 1));
1010 /* (neg (mult A B)) becomes (mult (neg A) B).
1011 This works even for floating-point values. */
1012 if (GET_CODE (op) == MULT
1013 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
1015 temp = simplify_gen_unary (NEG, mode, XEXP (op, 0), mode);
1016 return simplify_gen_binary (MULT, mode, temp, XEXP (op, 1));
1019 /* NEG commutes with ASHIFT since it is multiplication. Only do
1020 this if we can then eliminate the NEG (e.g., if the operand
1022 if (GET_CODE (op) == ASHIFT)
1024 temp = simplify_unary_operation (NEG, mode, XEXP (op, 0),
1027 return simplify_gen_binary (ASHIFT, mode, temp,
1034 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1035 becomes just the MINUS if its mode is MODE. This allows
1036 folding switch statements on machines using casesi (such as
1038 if (GET_CODE (op) == TRUNCATE
1039 && GET_MODE (XEXP (op, 0)) == mode
1040 && GET_CODE (XEXP (op, 0)) == MINUS
1041 && GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF
1042 && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
1043 return XEXP (op, 0);
1045 /* Check for a sign extension of a subreg of a promoted
1046 variable, where the promotion is sign-extended, and the
1047 target mode is the same as the variable's promotion. */
1048 if (GET_CODE (op) == SUBREG
1049 && SUBREG_PROMOTED_VAR_P (op)
1050 && ! SUBREG_PROMOTED_UNSIGNED_P (op)
1051 && GET_MODE (XEXP (op, 0)) == mode)
1052 return XEXP (op, 0);
1054 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1055 if (! POINTERS_EXTEND_UNSIGNED
1056 && mode == Pmode && GET_MODE (op) == ptr_mode
1058 || (GET_CODE (op) == SUBREG
1059 && GET_CODE (SUBREG_REG (op)) == REG
1060 && REG_POINTER (SUBREG_REG (op))
1061 && GET_MODE (SUBREG_REG (op)) == Pmode)))
1062 return convert_memory_address (Pmode, op);
1067 /* Check for a zero extension of a subreg of a promoted
1068 variable, where the promotion is zero-extended, and the
1069 target mode is the same as the variable's promotion. */
1070 if (GET_CODE (op) == SUBREG
1071 && SUBREG_PROMOTED_VAR_P (op)
1072 && SUBREG_PROMOTED_UNSIGNED_P (op)
1073 && GET_MODE (XEXP (op, 0)) == mode)
1074 return XEXP (op, 0);
1076 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1077 if (POINTERS_EXTEND_UNSIGNED > 0
1078 && mode == Pmode && GET_MODE (op) == ptr_mode
1080 || (GET_CODE (op) == SUBREG
1081 && GET_CODE (SUBREG_REG (op)) == REG
1082 && REG_POINTER (SUBREG_REG (op))
1083 && GET_MODE (SUBREG_REG (op)) == Pmode)))
1084 return convert_memory_address (Pmode, op);
1096 /* Subroutine of simplify_binary_operation to simplify a commutative,
1097 associative binary operation CODE with result mode MODE, operating
1098 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
1099 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
1100 canonicalization is possible. */
1103 simplify_associative_operation (enum rtx_code code, enum machine_mode mode,
1108 /* Linearize the operator to the left. */
1109 if (GET_CODE (op1) == code)
1111 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
1112 if (GET_CODE (op0) == code)
1114 tem = simplify_gen_binary (code, mode, op0, XEXP (op1, 0));
1115 return simplify_gen_binary (code, mode, tem, XEXP (op1, 1));
1118 /* "a op (b op c)" becomes "(b op c) op a". */
1119 if (! swap_commutative_operands_p (op1, op0))
1120 return simplify_gen_binary (code, mode, op1, op0);
1127 if (GET_CODE (op0) == code)
1129 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
1130 if (swap_commutative_operands_p (XEXP (op0, 1), op1))
1132 tem = simplify_gen_binary (code, mode, XEXP (op0, 0), op1);
1133 return simplify_gen_binary (code, mode, tem, XEXP (op0, 1));
1136 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
1137 tem = swap_commutative_operands_p (XEXP (op0, 1), op1)
1138 ? simplify_binary_operation (code, mode, op1, XEXP (op0, 1))
1139 : simplify_binary_operation (code, mode, XEXP (op0, 1), op1);
1141 return simplify_gen_binary (code, mode, XEXP (op0, 0), tem);
1143 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
1144 tem = swap_commutative_operands_p (XEXP (op0, 0), op1)
1145 ? simplify_binary_operation (code, mode, op1, XEXP (op0, 0))
1146 : simplify_binary_operation (code, mode, XEXP (op0, 0), op1);
1148 return simplify_gen_binary (code, mode, tem, XEXP (op0, 1));
1154 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
1155 and OP1. Return 0 if no simplification is possible.
1157 Don't use this for relational operations such as EQ or LT.
1158 Use simplify_relational_operation instead. */
1160 simplify_binary_operation (enum rtx_code code, enum machine_mode mode,
1163 HOST_WIDE_INT arg0, arg1, arg0s, arg1s;
1165 unsigned int width = GET_MODE_BITSIZE (mode);
1166 rtx trueop0, trueop1;
1169 #ifdef ENABLE_CHECKING
1170 /* Relational operations don't work here. We must know the mode
1171 of the operands in order to do the comparison correctly.
1172 Assuming a full word can give incorrect results.
1173 Consider comparing 128 with -128 in QImode. */
1175 if (GET_RTX_CLASS (code) == RTX_COMPARE
1176 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
1180 /* Make sure the constant is second. */
1181 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
1182 && swap_commutative_operands_p (op0, op1))
1184 tem = op0, op0 = op1, op1 = tem;
1187 trueop0 = avoid_constant_pool_reference (op0);
1188 trueop1 = avoid_constant_pool_reference (op1);
1190 if (VECTOR_MODE_P (mode)
1191 && GET_CODE (trueop0) == CONST_VECTOR
1192 && GET_CODE (trueop1) == CONST_VECTOR)
1194 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
1195 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
1196 enum machine_mode op0mode = GET_MODE (trueop0);
1197 int op0_elt_size = GET_MODE_SIZE (GET_MODE_INNER (op0mode));
1198 unsigned op0_n_elts = (GET_MODE_SIZE (op0mode) / op0_elt_size);
1199 enum machine_mode op1mode = GET_MODE (trueop1);
1200 int op1_elt_size = GET_MODE_SIZE (GET_MODE_INNER (op1mode));
1201 unsigned op1_n_elts = (GET_MODE_SIZE (op1mode) / op1_elt_size);
1202 rtvec v = rtvec_alloc (n_elts);
1205 if (op0_n_elts != n_elts || op1_n_elts != n_elts)
1208 for (i = 0; i < n_elts; i++)
1210 rtx x = simplify_binary_operation (code, GET_MODE_INNER (mode),
1211 CONST_VECTOR_ELT (trueop0, i),
1212 CONST_VECTOR_ELT (trueop1, i));
1215 RTVEC_ELT (v, i) = x;
1218 return gen_rtx_CONST_VECTOR (mode, v);
1221 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1222 && GET_CODE (trueop0) == CONST_DOUBLE
1223 && GET_CODE (trueop1) == CONST_DOUBLE
1224 && mode == GET_MODE (op0) && mode == GET_MODE (op1))
1235 real_to_target (tmp0, CONST_DOUBLE_REAL_VALUE (op0),
1237 real_to_target (tmp1, CONST_DOUBLE_REAL_VALUE (op1),
1239 for (i = 0; i < 4; i++)
1243 else if (code == IOR)
1245 else if (code == XOR)
1250 real_from_target (&r, tmp0, mode);
1251 return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
1255 REAL_VALUE_TYPE f0, f1, value;
1257 REAL_VALUE_FROM_CONST_DOUBLE (f0, trueop0);
1258 REAL_VALUE_FROM_CONST_DOUBLE (f1, trueop1);
1259 f0 = real_value_truncate (mode, f0);
1260 f1 = real_value_truncate (mode, f1);
1262 if (HONOR_SNANS (mode)
1263 && (REAL_VALUE_ISNAN (f0) || REAL_VALUE_ISNAN (f1)))
1267 && REAL_VALUES_EQUAL (f1, dconst0)
1268 && (flag_trapping_math || ! MODE_HAS_INFINITIES (mode)))
1271 REAL_ARITHMETIC (value, rtx_to_tree_code (code), f0, f1);
1273 value = real_value_truncate (mode, value);
1274 return CONST_DOUBLE_FROM_REAL_VALUE (value, mode);
1278 /* We can fold some multi-word operations. */
1279 if (GET_MODE_CLASS (mode) == MODE_INT
1280 && width == HOST_BITS_PER_WIDE_INT * 2
1281 && (GET_CODE (trueop0) == CONST_DOUBLE
1282 || GET_CODE (trueop0) == CONST_INT)
1283 && (GET_CODE (trueop1) == CONST_DOUBLE
1284 || GET_CODE (trueop1) == CONST_INT))
1286 unsigned HOST_WIDE_INT l1, l2, lv;
1287 HOST_WIDE_INT h1, h2, hv;
1289 if (GET_CODE (trueop0) == CONST_DOUBLE)
1290 l1 = CONST_DOUBLE_LOW (trueop0), h1 = CONST_DOUBLE_HIGH (trueop0);
1292 l1 = INTVAL (trueop0), h1 = HWI_SIGN_EXTEND (l1);
1294 if (GET_CODE (trueop1) == CONST_DOUBLE)
1295 l2 = CONST_DOUBLE_LOW (trueop1), h2 = CONST_DOUBLE_HIGH (trueop1);
1297 l2 = INTVAL (trueop1), h2 = HWI_SIGN_EXTEND (l2);
1302 /* A - B == A + (-B). */
1303 neg_double (l2, h2, &lv, &hv);
1306 /* Fall through.... */
1309 add_double (l1, h1, l2, h2, &lv, &hv);
1313 mul_double (l1, h1, l2, h2, &lv, &hv);
1316 case DIV: case MOD: case UDIV: case UMOD:
1317 /* We'd need to include tree.h to do this and it doesn't seem worth
1322 lv = l1 & l2, hv = h1 & h2;
1326 lv = l1 | l2, hv = h1 | h2;
1330 lv = l1 ^ l2, hv = h1 ^ h2;
1336 && ((unsigned HOST_WIDE_INT) l1
1337 < (unsigned HOST_WIDE_INT) l2)))
1346 && ((unsigned HOST_WIDE_INT) l1
1347 > (unsigned HOST_WIDE_INT) l2)))
1354 if ((unsigned HOST_WIDE_INT) h1 < (unsigned HOST_WIDE_INT) h2
1356 && ((unsigned HOST_WIDE_INT) l1
1357 < (unsigned HOST_WIDE_INT) l2)))
1364 if ((unsigned HOST_WIDE_INT) h1 > (unsigned HOST_WIDE_INT) h2
1366 && ((unsigned HOST_WIDE_INT) l1
1367 > (unsigned HOST_WIDE_INT) l2)))
1373 case LSHIFTRT: case ASHIFTRT:
1375 case ROTATE: case ROTATERT:
1376 if (SHIFT_COUNT_TRUNCATED)
1377 l2 &= (GET_MODE_BITSIZE (mode) - 1), h2 = 0;
1379 if (h2 != 0 || l2 >= GET_MODE_BITSIZE (mode))
1382 if (code == LSHIFTRT || code == ASHIFTRT)
1383 rshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv,
1385 else if (code == ASHIFT)
1386 lshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv, 1);
1387 else if (code == ROTATE)
1388 lrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv);
1389 else /* code == ROTATERT */
1390 rrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv);
1397 return immed_double_const (lv, hv, mode);
1400 if (GET_CODE (op0) != CONST_INT || GET_CODE (op1) != CONST_INT
1401 || width > HOST_BITS_PER_WIDE_INT || width == 0)
1403 /* Even if we can't compute a constant result,
1404 there are some cases worth simplifying. */
1409 /* Maybe simplify x + 0 to x. The two expressions are equivalent
1410 when x is NaN, infinite, or finite and nonzero. They aren't
1411 when x is -0 and the rounding mode is not towards -infinity,
1412 since (-0) + 0 is then 0. */
1413 if (!HONOR_SIGNED_ZEROS (mode) && trueop1 == CONST0_RTX (mode))
1416 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
1417 transformations are safe even for IEEE. */
1418 if (GET_CODE (op0) == NEG)
1419 return simplify_gen_binary (MINUS, mode, op1, XEXP (op0, 0));
1420 else if (GET_CODE (op1) == NEG)
1421 return simplify_gen_binary (MINUS, mode, op0, XEXP (op1, 0));
1423 /* (~a) + 1 -> -a */
1424 if (INTEGRAL_MODE_P (mode)
1425 && GET_CODE (op0) == NOT
1426 && trueop1 == const1_rtx)
1427 return simplify_gen_unary (NEG, mode, XEXP (op0, 0), mode);
1429 /* Handle both-operands-constant cases. We can only add
1430 CONST_INTs to constants since the sum of relocatable symbols
1431 can't be handled by most assemblers. Don't add CONST_INT
1432 to CONST_INT since overflow won't be computed properly if wider
1433 than HOST_BITS_PER_WIDE_INT. */
1435 if (CONSTANT_P (op0) && GET_MODE (op0) != VOIDmode
1436 && GET_CODE (op1) == CONST_INT)
1437 return plus_constant (op0, INTVAL (op1));
1438 else if (CONSTANT_P (op1) && GET_MODE (op1) != VOIDmode
1439 && GET_CODE (op0) == CONST_INT)
1440 return plus_constant (op1, INTVAL (op0));
1442 /* See if this is something like X * C - X or vice versa or
1443 if the multiplication is written as a shift. If so, we can
1444 distribute and make a new multiply, shift, or maybe just
1445 have X (if C is 2 in the example above). But don't make
1446 real multiply if we didn't have one before. */
1448 if (! FLOAT_MODE_P (mode))
1450 HOST_WIDE_INT coeff0 = 1, coeff1 = 1;
1451 rtx lhs = op0, rhs = op1;
1454 if (GET_CODE (lhs) == NEG)
1455 coeff0 = -1, lhs = XEXP (lhs, 0);
1456 else if (GET_CODE (lhs) == MULT
1457 && GET_CODE (XEXP (lhs, 1)) == CONST_INT)
1459 coeff0 = INTVAL (XEXP (lhs, 1)), lhs = XEXP (lhs, 0);
1462 else if (GET_CODE (lhs) == ASHIFT
1463 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
1464 && INTVAL (XEXP (lhs, 1)) >= 0
1465 && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
1467 coeff0 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (lhs, 1));
1468 lhs = XEXP (lhs, 0);
1471 if (GET_CODE (rhs) == NEG)
1472 coeff1 = -1, rhs = XEXP (rhs, 0);
1473 else if (GET_CODE (rhs) == MULT
1474 && GET_CODE (XEXP (rhs, 1)) == CONST_INT)
1476 coeff1 = INTVAL (XEXP (rhs, 1)), rhs = XEXP (rhs, 0);
1479 else if (GET_CODE (rhs) == ASHIFT
1480 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
1481 && INTVAL (XEXP (rhs, 1)) >= 0
1482 && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
1484 coeff1 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (rhs, 1));
1485 rhs = XEXP (rhs, 0);
1488 if (rtx_equal_p (lhs, rhs))
1490 tem = simplify_gen_binary (MULT, mode, lhs,
1491 GEN_INT (coeff0 + coeff1));
1492 return (GET_CODE (tem) == MULT && ! had_mult) ? 0 : tem;
1496 /* If one of the operands is a PLUS or a MINUS, see if we can
1497 simplify this by the associative law.
1498 Don't use the associative law for floating point.
1499 The inaccuracy makes it nonassociative,
1500 and subtle programs can break if operations are associated. */
1502 if (INTEGRAL_MODE_P (mode)
1503 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
1504 || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS
1505 || (GET_CODE (op0) == CONST
1506 && GET_CODE (XEXP (op0, 0)) == PLUS)
1507 || (GET_CODE (op1) == CONST
1508 && GET_CODE (XEXP (op1, 0)) == PLUS))
1509 && (tem = simplify_plus_minus (code, mode, op0, op1, 0)) != 0)
1512 /* Reassociate floating point addition only when the user
1513 specifies unsafe math optimizations. */
1514 if (FLOAT_MODE_P (mode)
1515 && flag_unsafe_math_optimizations)
1517 tem = simplify_associative_operation (code, mode, op0, op1);
1525 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
1526 using cc0, in which case we want to leave it as a COMPARE
1527 so we can distinguish it from a register-register-copy.
1529 In IEEE floating point, x-0 is not the same as x. */
1531 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
1532 || ! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
1533 && trueop1 == CONST0_RTX (mode))
1537 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
1538 if (((GET_CODE (op0) == GT && GET_CODE (op1) == LT)
1539 || (GET_CODE (op0) == GTU && GET_CODE (op1) == LTU))
1540 && XEXP (op0, 1) == const0_rtx && XEXP (op1, 1) == const0_rtx)
1542 rtx xop00 = XEXP (op0, 0);
1543 rtx xop10 = XEXP (op1, 0);
1546 if (GET_CODE (xop00) == CC0 && GET_CODE (xop10) == CC0)
1548 if (GET_CODE (xop00) == REG && GET_CODE (xop10) == REG
1549 && GET_MODE (xop00) == GET_MODE (xop10)
1550 && REGNO (xop00) == REGNO (xop10)
1551 && GET_MODE_CLASS (GET_MODE (xop00)) == MODE_CC
1552 && GET_MODE_CLASS (GET_MODE (xop10)) == MODE_CC)
1559 /* We can't assume x-x is 0 even with non-IEEE floating point,
1560 but since it is zero except in very strange circumstances, we
1561 will treat it as zero with -funsafe-math-optimizations. */
1562 if (rtx_equal_p (trueop0, trueop1)
1563 && ! side_effects_p (op0)
1564 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations))
1565 return CONST0_RTX (mode);
1567 /* Change subtraction from zero into negation. (0 - x) is the
1568 same as -x when x is NaN, infinite, or finite and nonzero.
1569 But if the mode has signed zeros, and does not round towards
1570 -infinity, then 0 - 0 is 0, not -0. */
1571 if (!HONOR_SIGNED_ZEROS (mode) && trueop0 == CONST0_RTX (mode))
1572 return simplify_gen_unary (NEG, mode, op1, mode);
1574 /* (-1 - a) is ~a. */
1575 if (trueop0 == constm1_rtx)
1576 return simplify_gen_unary (NOT, mode, op1, mode);
1578 /* Subtracting 0 has no effect unless the mode has signed zeros
1579 and supports rounding towards -infinity. In such a case,
1581 if (!(HONOR_SIGNED_ZEROS (mode)
1582 && HONOR_SIGN_DEPENDENT_ROUNDING (mode))
1583 && trueop1 == CONST0_RTX (mode))
1586 /* See if this is something like X * C - X or vice versa or
1587 if the multiplication is written as a shift. If so, we can
1588 distribute and make a new multiply, shift, or maybe just
1589 have X (if C is 2 in the example above). But don't make
1590 real multiply if we didn't have one before. */
1592 if (! FLOAT_MODE_P (mode))
1594 HOST_WIDE_INT coeff0 = 1, coeff1 = 1;
1595 rtx lhs = op0, rhs = op1;
1598 if (GET_CODE (lhs) == NEG)
1599 coeff0 = -1, lhs = XEXP (lhs, 0);
1600 else if (GET_CODE (lhs) == MULT
1601 && GET_CODE (XEXP (lhs, 1)) == CONST_INT)
1603 coeff0 = INTVAL (XEXP (lhs, 1)), lhs = XEXP (lhs, 0);
1606 else if (GET_CODE (lhs) == ASHIFT
1607 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
1608 && INTVAL (XEXP (lhs, 1)) >= 0
1609 && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
1611 coeff0 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (lhs, 1));
1612 lhs = XEXP (lhs, 0);
1615 if (GET_CODE (rhs) == NEG)
1616 coeff1 = - 1, rhs = XEXP (rhs, 0);
1617 else if (GET_CODE (rhs) == MULT
1618 && GET_CODE (XEXP (rhs, 1)) == CONST_INT)
1620 coeff1 = INTVAL (XEXP (rhs, 1)), rhs = XEXP (rhs, 0);
1623 else if (GET_CODE (rhs) == ASHIFT
1624 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
1625 && INTVAL (XEXP (rhs, 1)) >= 0
1626 && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
1628 coeff1 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (rhs, 1));
1629 rhs = XEXP (rhs, 0);
1632 if (rtx_equal_p (lhs, rhs))
1634 tem = simplify_gen_binary (MULT, mode, lhs,
1635 GEN_INT (coeff0 - coeff1));
1636 return (GET_CODE (tem) == MULT && ! had_mult) ? 0 : tem;
1640 /* (a - (-b)) -> (a + b). True even for IEEE. */
1641 if (GET_CODE (op1) == NEG)
1642 return simplify_gen_binary (PLUS, mode, op0, XEXP (op1, 0));
1644 /* (-x - c) may be simplified as (-c - x). */
1645 if (GET_CODE (op0) == NEG
1646 && (GET_CODE (op1) == CONST_INT
1647 || GET_CODE (op1) == CONST_DOUBLE))
1649 tem = simplify_unary_operation (NEG, mode, op1, mode);
1651 return simplify_gen_binary (MINUS, mode, tem, XEXP (op0, 0));
1654 /* If one of the operands is a PLUS or a MINUS, see if we can
1655 simplify this by the associative law.
1656 Don't use the associative law for floating point.
1657 The inaccuracy makes it nonassociative,
1658 and subtle programs can break if operations are associated. */
1660 if (INTEGRAL_MODE_P (mode)
1661 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
1662 || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS
1663 || (GET_CODE (op0) == CONST
1664 && GET_CODE (XEXP (op0, 0)) == PLUS)
1665 || (GET_CODE (op1) == CONST
1666 && GET_CODE (XEXP (op1, 0)) == PLUS))
1667 && (tem = simplify_plus_minus (code, mode, op0, op1, 0)) != 0)
1670 /* Don't let a relocatable value get a negative coeff. */
1671 if (GET_CODE (op1) == CONST_INT && GET_MODE (op0) != VOIDmode)
1672 return simplify_gen_binary (PLUS, mode,
1674 neg_const_int (mode, op1));
1676 /* (x - (x & y)) -> (x & ~y) */
1677 if (GET_CODE (op1) == AND)
1679 if (rtx_equal_p (op0, XEXP (op1, 0)))
1681 tem = simplify_gen_unary (NOT, mode, XEXP (op1, 1),
1682 GET_MODE (XEXP (op1, 1)));
1683 return simplify_gen_binary (AND, mode, op0, tem);
1685 if (rtx_equal_p (op0, XEXP (op1, 1)))
1687 tem = simplify_gen_unary (NOT, mode, XEXP (op1, 0),
1688 GET_MODE (XEXP (op1, 0)));
1689 return simplify_gen_binary (AND, mode, op0, tem);
1695 if (trueop1 == constm1_rtx)
1696 return simplify_gen_unary (NEG, mode, op0, mode);
1698 /* Maybe simplify x * 0 to 0. The reduction is not valid if
1699 x is NaN, since x * 0 is then also NaN. Nor is it valid
1700 when the mode has signed zeros, since multiplying a negative
1701 number by 0 will give -0, not 0. */
1702 if (!HONOR_NANS (mode)
1703 && !HONOR_SIGNED_ZEROS (mode)
1704 && trueop1 == CONST0_RTX (mode)
1705 && ! side_effects_p (op0))
1708 /* In IEEE floating point, x*1 is not equivalent to x for
1710 if (!HONOR_SNANS (mode)
1711 && trueop1 == CONST1_RTX (mode))
1714 /* Convert multiply by constant power of two into shift unless
1715 we are still generating RTL. This test is a kludge. */
1716 if (GET_CODE (trueop1) == CONST_INT
1717 && (val = exact_log2 (INTVAL (trueop1))) >= 0
1718 /* If the mode is larger than the host word size, and the
1719 uppermost bit is set, then this isn't a power of two due
1720 to implicit sign extension. */
1721 && (width <= HOST_BITS_PER_WIDE_INT
1722 || val != HOST_BITS_PER_WIDE_INT - 1)
1723 && ! rtx_equal_function_value_matters)
1724 return simplify_gen_binary (ASHIFT, mode, op0, GEN_INT (val));
1726 /* x*2 is x+x and x*(-1) is -x */
1727 if (GET_CODE (trueop1) == CONST_DOUBLE
1728 && GET_MODE_CLASS (GET_MODE (trueop1)) == MODE_FLOAT
1729 && GET_MODE (op0) == mode)
1732 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
1734 if (REAL_VALUES_EQUAL (d, dconst2))
1735 return simplify_gen_binary (PLUS, mode, op0, copy_rtx (op0));
1737 if (REAL_VALUES_EQUAL (d, dconstm1))
1738 return simplify_gen_unary (NEG, mode, op0, mode);
1741 /* Reassociate multiplication, but for floating point MULTs
1742 only when the user specifies unsafe math optimizations. */
1743 if (! FLOAT_MODE_P (mode)
1744 || flag_unsafe_math_optimizations)
1746 tem = simplify_associative_operation (code, mode, op0, op1);
1753 if (trueop1 == const0_rtx)
1755 if (GET_CODE (trueop1) == CONST_INT
1756 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1757 == GET_MODE_MASK (mode)))
1759 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1761 /* A | (~A) -> -1 */
1762 if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
1763 || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
1764 && ! side_effects_p (op0)
1765 && GET_MODE_CLASS (mode) != MODE_CC)
1767 tem = simplify_associative_operation (code, mode, op0, op1);
1773 if (trueop1 == const0_rtx)
1775 if (GET_CODE (trueop1) == CONST_INT
1776 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1777 == GET_MODE_MASK (mode)))
1778 return simplify_gen_unary (NOT, mode, op0, mode);
1779 if (trueop0 == trueop1 && ! side_effects_p (op0)
1780 && GET_MODE_CLASS (mode) != MODE_CC)
1782 tem = simplify_associative_operation (code, mode, op0, op1);
1788 if (trueop1 == const0_rtx && ! side_effects_p (op0))
1790 if (GET_CODE (trueop1) == CONST_INT
1791 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1792 == GET_MODE_MASK (mode)))
1794 if (trueop0 == trueop1 && ! side_effects_p (op0)
1795 && GET_MODE_CLASS (mode) != MODE_CC)
1798 if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
1799 || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
1800 && ! side_effects_p (op0)
1801 && GET_MODE_CLASS (mode) != MODE_CC)
1803 tem = simplify_associative_operation (code, mode, op0, op1);
1809 /* Convert divide by power of two into shift (divide by 1 handled
1811 if (GET_CODE (trueop1) == CONST_INT
1812 && (arg1 = exact_log2 (INTVAL (trueop1))) > 0)
1813 return simplify_gen_binary (LSHIFTRT, mode, op0, GEN_INT (arg1));
1815 /* Fall through.... */
1818 if (trueop1 == CONST1_RTX (mode))
1820 /* On some platforms DIV uses narrower mode than its
1822 rtx x = gen_lowpart_common (mode, op0);
1825 else if (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
1826 return gen_lowpart_SUBREG (mode, op0);
1831 /* Maybe change 0 / x to 0. This transformation isn't safe for
1832 modes with NaNs, since 0 / 0 will then be NaN rather than 0.
1833 Nor is it safe for modes with signed zeros, since dividing
1834 0 by a negative number gives -0, not 0. */
1835 if (!HONOR_NANS (mode)
1836 && !HONOR_SIGNED_ZEROS (mode)
1837 && trueop0 == CONST0_RTX (mode)
1838 && ! side_effects_p (op1))
1841 /* Change division by a constant into multiplication. Only do
1842 this with -funsafe-math-optimizations. */
1843 else if (GET_CODE (trueop1) == CONST_DOUBLE
1844 && GET_MODE_CLASS (GET_MODE (trueop1)) == MODE_FLOAT
1845 && trueop1 != CONST0_RTX (mode)
1846 && flag_unsafe_math_optimizations)
1849 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
1851 if (! REAL_VALUES_EQUAL (d, dconst0))
1853 REAL_ARITHMETIC (d, rtx_to_tree_code (DIV), dconst1, d);
1854 tem = CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
1855 return simplify_gen_binary (MULT, mode, op0, tem);
1861 /* Handle modulus by power of two (mod with 1 handled below). */
1862 if (GET_CODE (trueop1) == CONST_INT
1863 && exact_log2 (INTVAL (trueop1)) > 0)
1864 return simplify_gen_binary (AND, mode, op0,
1865 GEN_INT (INTVAL (op1) - 1));
1867 /* Fall through.... */
1870 if ((trueop0 == const0_rtx || trueop1 == const1_rtx)
1871 && ! side_effects_p (op0) && ! side_effects_p (op1))
1878 /* Rotating ~0 always results in ~0. */
1879 if (GET_CODE (trueop0) == CONST_INT && width <= HOST_BITS_PER_WIDE_INT
1880 && (unsigned HOST_WIDE_INT) INTVAL (trueop0) == GET_MODE_MASK (mode)
1881 && ! side_effects_p (op1))
1884 /* Fall through.... */
1888 if (trueop1 == const0_rtx)
1890 if (trueop0 == const0_rtx && ! side_effects_p (op1))
1895 if (width <= HOST_BITS_PER_WIDE_INT
1896 && GET_CODE (trueop1) == CONST_INT
1897 && INTVAL (trueop1) == (HOST_WIDE_INT) 1 << (width -1)
1898 && ! side_effects_p (op0))
1900 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1902 tem = simplify_associative_operation (code, mode, op0, op1);
1908 if (width <= HOST_BITS_PER_WIDE_INT
1909 && GET_CODE (trueop1) == CONST_INT
1910 && ((unsigned HOST_WIDE_INT) INTVAL (trueop1)
1911 == (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode) >> 1)
1912 && ! side_effects_p (op0))
1914 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1916 tem = simplify_associative_operation (code, mode, op0, op1);
1922 if (trueop1 == const0_rtx && ! side_effects_p (op0))
1924 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1926 tem = simplify_associative_operation (code, mode, op0, op1);
1932 if (trueop1 == constm1_rtx && ! side_effects_p (op0))
1934 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1936 tem = simplify_associative_operation (code, mode, op0, op1);
1945 /* ??? There are simplifications that can be done. */
1949 if (!VECTOR_MODE_P (mode))
1951 if (!VECTOR_MODE_P (GET_MODE (trueop0))
1953 != GET_MODE_INNER (GET_MODE (trueop0)))
1954 || GET_CODE (trueop1) != PARALLEL
1955 || XVECLEN (trueop1, 0) != 1
1956 || GET_CODE (XVECEXP (trueop1, 0, 0)) != CONST_INT)
1959 if (GET_CODE (trueop0) == CONST_VECTOR)
1960 return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP (trueop1, 0, 0)));
1964 if (!VECTOR_MODE_P (GET_MODE (trueop0))
1965 || (GET_MODE_INNER (mode)
1966 != GET_MODE_INNER (GET_MODE (trueop0)))
1967 || GET_CODE (trueop1) != PARALLEL)
1970 if (GET_CODE (trueop0) == CONST_VECTOR)
1972 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
1973 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
1974 rtvec v = rtvec_alloc (n_elts);
1977 if (XVECLEN (trueop1, 0) != (int) n_elts)
1979 for (i = 0; i < n_elts; i++)
1981 rtx x = XVECEXP (trueop1, 0, i);
1983 if (GET_CODE (x) != CONST_INT)
1985 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop0, INTVAL (x));
1988 return gen_rtx_CONST_VECTOR (mode, v);
1994 enum machine_mode op0_mode = (GET_MODE (trueop0) != VOIDmode
1995 ? GET_MODE (trueop0)
1996 : GET_MODE_INNER (mode));
1997 enum machine_mode op1_mode = (GET_MODE (trueop1) != VOIDmode
1998 ? GET_MODE (trueop1)
1999 : GET_MODE_INNER (mode));
2001 if (!VECTOR_MODE_P (mode)
2002 || (GET_MODE_SIZE (op0_mode) + GET_MODE_SIZE (op1_mode)
2003 != GET_MODE_SIZE (mode)))
2006 if ((VECTOR_MODE_P (op0_mode)
2007 && (GET_MODE_INNER (mode)
2008 != GET_MODE_INNER (op0_mode)))
2009 || (!VECTOR_MODE_P (op0_mode)
2010 && GET_MODE_INNER (mode) != op0_mode))
2013 if ((VECTOR_MODE_P (op1_mode)
2014 && (GET_MODE_INNER (mode)
2015 != GET_MODE_INNER (op1_mode)))
2016 || (!VECTOR_MODE_P (op1_mode)
2017 && GET_MODE_INNER (mode) != op1_mode))
2020 if ((GET_CODE (trueop0) == CONST_VECTOR
2021 || GET_CODE (trueop0) == CONST_INT
2022 || GET_CODE (trueop0) == CONST_DOUBLE)
2023 && (GET_CODE (trueop1) == CONST_VECTOR
2024 || GET_CODE (trueop1) == CONST_INT
2025 || GET_CODE (trueop1) == CONST_DOUBLE))
2027 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
2028 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
2029 rtvec v = rtvec_alloc (n_elts);
2031 unsigned in_n_elts = 1;
2033 if (VECTOR_MODE_P (op0_mode))
2034 in_n_elts = (GET_MODE_SIZE (op0_mode) / elt_size);
2035 for (i = 0; i < n_elts; i++)
2039 if (!VECTOR_MODE_P (op0_mode))
2040 RTVEC_ELT (v, i) = trueop0;
2042 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop0, i);
2046 if (!VECTOR_MODE_P (op1_mode))
2047 RTVEC_ELT (v, i) = trueop1;
2049 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop1,
2054 return gen_rtx_CONST_VECTOR (mode, v);
2066 /* Get the integer argument values in two forms:
2067 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
2069 arg0 = INTVAL (trueop0);
2070 arg1 = INTVAL (trueop1);
2072 if (width < HOST_BITS_PER_WIDE_INT)
2074 arg0 &= ((HOST_WIDE_INT) 1 << width) - 1;
2075 arg1 &= ((HOST_WIDE_INT) 1 << width) - 1;
2078 if (arg0s & ((HOST_WIDE_INT) 1 << (width - 1)))
2079 arg0s |= ((HOST_WIDE_INT) (-1) << width);
2082 if (arg1s & ((HOST_WIDE_INT) 1 << (width - 1)))
2083 arg1s |= ((HOST_WIDE_INT) (-1) << width);
2091 /* Compute the value of the arithmetic. */
2096 val = arg0s + arg1s;
2100 val = arg0s - arg1s;
2104 val = arg0s * arg1s;
2109 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2112 val = arg0s / arg1s;
2117 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2120 val = arg0s % arg1s;
2125 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2128 val = (unsigned HOST_WIDE_INT) arg0 / arg1;
2133 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2136 val = (unsigned HOST_WIDE_INT) arg0 % arg1;
2152 /* If shift count is undefined, don't fold it; let the machine do
2153 what it wants. But truncate it if the machine will do that. */
2157 if (SHIFT_COUNT_TRUNCATED)
2160 val = ((unsigned HOST_WIDE_INT) arg0) >> arg1;
2167 if (SHIFT_COUNT_TRUNCATED)
2170 val = ((unsigned HOST_WIDE_INT) arg0) << arg1;
2177 if (SHIFT_COUNT_TRUNCATED)
2180 val = arg0s >> arg1;
2182 /* Bootstrap compiler may not have sign extended the right shift.
2183 Manually extend the sign to insure bootstrap cc matches gcc. */
2184 if (arg0s < 0 && arg1 > 0)
2185 val |= ((HOST_WIDE_INT) -1) << (HOST_BITS_PER_WIDE_INT - arg1);
2194 val = ((((unsigned HOST_WIDE_INT) arg0) << (width - arg1))
2195 | (((unsigned HOST_WIDE_INT) arg0) >> arg1));
2203 val = ((((unsigned HOST_WIDE_INT) arg0) << arg1)
2204 | (((unsigned HOST_WIDE_INT) arg0) >> (width - arg1)));
2208 /* Do nothing here. */
2212 val = arg0s <= arg1s ? arg0s : arg1s;
2216 val = ((unsigned HOST_WIDE_INT) arg0
2217 <= (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
2221 val = arg0s > arg1s ? arg0s : arg1s;
2225 val = ((unsigned HOST_WIDE_INT) arg0
2226 > (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
2233 /* ??? There are simplifications that can be done. */
2240 val = trunc_int_for_mode (val, mode);
2242 return GEN_INT (val);
2245 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
2248 Rather than test for specific case, we do this by a brute-force method
2249 and do all possible simplifications until no more changes occur. Then
2250 we rebuild the operation.
2252 If FORCE is true, then always generate the rtx. This is used to
2253 canonicalize stuff emitted from simplify_gen_binary. Note that this
2254 can still fail if the rtx is too complex. It won't fail just because
2255 the result is not 'simpler' than the input, however. */
2257 struct simplify_plus_minus_op_data
2264 simplify_plus_minus_op_data_cmp (const void *p1, const void *p2)
2266 const struct simplify_plus_minus_op_data *d1 = p1;
2267 const struct simplify_plus_minus_op_data *d2 = p2;
2269 return (commutative_operand_precedence (d2->op)
2270 - commutative_operand_precedence (d1->op));
2274 simplify_plus_minus (enum rtx_code code, enum machine_mode mode, rtx op0,
2277 struct simplify_plus_minus_op_data ops[8];
2279 int n_ops = 2, input_ops = 2, input_consts = 0, n_consts;
2283 memset (ops, 0, sizeof ops);
2285 /* Set up the two operands and then expand them until nothing has been
2286 changed. If we run out of room in our array, give up; this should
2287 almost never happen. */
2292 ops[1].neg = (code == MINUS);
2298 for (i = 0; i < n_ops; i++)
2300 rtx this_op = ops[i].op;
2301 int this_neg = ops[i].neg;
2302 enum rtx_code this_code = GET_CODE (this_op);
2311 ops[n_ops].op = XEXP (this_op, 1);
2312 ops[n_ops].neg = (this_code == MINUS) ^ this_neg;
2315 ops[i].op = XEXP (this_op, 0);
2321 ops[i].op = XEXP (this_op, 0);
2322 ops[i].neg = ! this_neg;
2328 && GET_CODE (XEXP (this_op, 0)) == PLUS
2329 && CONSTANT_P (XEXP (XEXP (this_op, 0), 0))
2330 && CONSTANT_P (XEXP (XEXP (this_op, 0), 1)))
2332 ops[i].op = XEXP (XEXP (this_op, 0), 0);
2333 ops[n_ops].op = XEXP (XEXP (this_op, 0), 1);
2334 ops[n_ops].neg = this_neg;
2342 /* ~a -> (-a - 1) */
2345 ops[n_ops].op = constm1_rtx;
2346 ops[n_ops++].neg = this_neg;
2347 ops[i].op = XEXP (this_op, 0);
2348 ops[i].neg = !this_neg;
2356 ops[i].op = neg_const_int (mode, this_op);
2369 /* If we only have two operands, we can't do anything. */
2370 if (n_ops <= 2 && !force)
2373 /* Count the number of CONSTs we didn't split above. */
2374 for (i = 0; i < n_ops; i++)
2375 if (GET_CODE (ops[i].op) == CONST)
2378 /* Now simplify each pair of operands until nothing changes. The first
2379 time through just simplify constants against each other. */
2386 for (i = 0; i < n_ops - 1; i++)
2387 for (j = i + 1; j < n_ops; j++)
2389 rtx lhs = ops[i].op, rhs = ops[j].op;
2390 int lneg = ops[i].neg, rneg = ops[j].neg;
2392 if (lhs != 0 && rhs != 0
2393 && (! first || (CONSTANT_P (lhs) && CONSTANT_P (rhs))))
2395 enum rtx_code ncode = PLUS;
2401 tem = lhs, lhs = rhs, rhs = tem;
2403 else if (swap_commutative_operands_p (lhs, rhs))
2404 tem = lhs, lhs = rhs, rhs = tem;
2406 tem = simplify_binary_operation (ncode, mode, lhs, rhs);
2408 /* Reject "simplifications" that just wrap the two
2409 arguments in a CONST. Failure to do so can result
2410 in infinite recursion with simplify_binary_operation
2411 when it calls us to simplify CONST operations. */
2413 && ! (GET_CODE (tem) == CONST
2414 && GET_CODE (XEXP (tem, 0)) == ncode
2415 && XEXP (XEXP (tem, 0), 0) == lhs
2416 && XEXP (XEXP (tem, 0), 1) == rhs)
2417 /* Don't allow -x + -1 -> ~x simplifications in the
2418 first pass. This allows us the chance to combine
2419 the -1 with other constants. */
2421 && GET_CODE (tem) == NOT
2422 && XEXP (tem, 0) == rhs))
2425 if (GET_CODE (tem) == NEG)
2426 tem = XEXP (tem, 0), lneg = !lneg;
2427 if (GET_CODE (tem) == CONST_INT && lneg)
2428 tem = neg_const_int (mode, tem), lneg = 0;
2432 ops[j].op = NULL_RTX;
2442 /* Pack all the operands to the lower-numbered entries. */
2443 for (i = 0, j = 0; j < n_ops; j++)
2448 /* Sort the operations based on swap_commutative_operands_p. */
2449 qsort (ops, n_ops, sizeof (*ops), simplify_plus_minus_op_data_cmp);
2451 /* Create (minus -C X) instead of (neg (const (plus X C))). */
2453 && GET_CODE (ops[1].op) == CONST_INT
2454 && CONSTANT_P (ops[0].op)
2456 return gen_rtx_fmt_ee (MINUS, mode, ops[1].op, ops[0].op);
2458 /* We suppressed creation of trivial CONST expressions in the
2459 combination loop to avoid recursion. Create one manually now.
2460 The combination loop should have ensured that there is exactly
2461 one CONST_INT, and the sort will have ensured that it is last
2462 in the array and that any other constant will be next-to-last. */
2465 && GET_CODE (ops[n_ops - 1].op) == CONST_INT
2466 && CONSTANT_P (ops[n_ops - 2].op))
2468 rtx value = ops[n_ops - 1].op;
2469 if (ops[n_ops - 1].neg ^ ops[n_ops - 2].neg)
2470 value = neg_const_int (mode, value);
2471 ops[n_ops - 2].op = plus_constant (ops[n_ops - 2].op, INTVAL (value));
2475 /* Count the number of CONSTs that we generated. */
2477 for (i = 0; i < n_ops; i++)
2478 if (GET_CODE (ops[i].op) == CONST)
2481 /* Give up if we didn't reduce the number of operands we had. Make
2482 sure we count a CONST as two operands. If we have the same
2483 number of operands, but have made more CONSTs than before, this
2484 is also an improvement, so accept it. */
2486 && (n_ops + n_consts > input_ops
2487 || (n_ops + n_consts == input_ops && n_consts <= input_consts)))
2490 /* Put a non-negated operand first, if possible. */
2492 for (i = 0; i < n_ops && ops[i].neg; i++)
2495 ops[0].op = gen_rtx_NEG (mode, ops[0].op);
2504 /* Now make the result by performing the requested operations. */
2506 for (i = 1; i < n_ops; i++)
2507 result = gen_rtx_fmt_ee (ops[i].neg ? MINUS : PLUS,
2508 mode, result, ops[i].op);
2513 /* Like simplify_binary_operation except used for relational operators.
2514 MODE is the mode of the operands, not that of the result. If MODE
2515 is VOIDmode, both operands must also be VOIDmode and we compare the
2516 operands in "infinite precision".
2518 If no simplification is possible, this function returns zero. Otherwise,
2519 it returns either const_true_rtx or const0_rtx. */
2522 simplify_relational_operation (enum rtx_code code, enum machine_mode mode,
2525 int equal, op0lt, op0ltu, op1lt, op1ltu;
2530 if (mode == VOIDmode
2531 && (GET_MODE (op0) != VOIDmode
2532 || GET_MODE (op1) != VOIDmode))
2535 /* If op0 is a compare, extract the comparison arguments from it. */
2536 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
2537 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
2539 /* We can't simplify MODE_CC values since we don't know what the
2540 actual comparison is. */
2541 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC || CC0_P (op0))
2544 /* Make sure the constant is second. */
2545 if (swap_commutative_operands_p (op0, op1))
2547 tem = op0, op0 = op1, op1 = tem;
2548 code = swap_condition (code);
2551 trueop0 = avoid_constant_pool_reference (op0);
2552 trueop1 = avoid_constant_pool_reference (op1);
2554 /* For integer comparisons of A and B maybe we can simplify A - B and can
2555 then simplify a comparison of that with zero. If A and B are both either
2556 a register or a CONST_INT, this can't help; testing for these cases will
2557 prevent infinite recursion here and speed things up.
2559 If CODE is an unsigned comparison, then we can never do this optimization,
2560 because it gives an incorrect result if the subtraction wraps around zero.
2561 ANSI C defines unsigned operations such that they never overflow, and
2562 thus such cases can not be ignored; but we cannot do it even for
2563 signed comparisons for languages such as Java, so test flag_wrapv. */
2565 if (!flag_wrapv && INTEGRAL_MODE_P (mode) && trueop1 != const0_rtx
2566 && ! ((GET_CODE (op0) == REG || GET_CODE (trueop0) == CONST_INT)
2567 && (GET_CODE (op1) == REG || GET_CODE (trueop1) == CONST_INT))
2568 && 0 != (tem = simplify_binary_operation (MINUS, mode, op0, op1))
2569 /* We cannot do this for == or != if tem is a nonzero address. */
2570 && ((code != EQ && code != NE) || ! nonzero_address_p (tem))
2571 && code != GTU && code != GEU && code != LTU && code != LEU)
2572 return simplify_relational_operation (signed_condition (code),
2573 mode, tem, const0_rtx);
2575 if (flag_unsafe_math_optimizations && code == ORDERED)
2576 return const_true_rtx;
2578 if (flag_unsafe_math_optimizations && code == UNORDERED)
2581 /* For modes without NaNs, if the two operands are equal, we know the
2582 result except if they have side-effects. */
2583 if (! HONOR_NANS (GET_MODE (trueop0))
2584 && rtx_equal_p (trueop0, trueop1)
2585 && ! side_effects_p (trueop0))
2586 equal = 1, op0lt = 0, op0ltu = 0, op1lt = 0, op1ltu = 0;
2588 /* If the operands are floating-point constants, see if we can fold
2590 else if (GET_CODE (trueop0) == CONST_DOUBLE
2591 && GET_CODE (trueop1) == CONST_DOUBLE
2592 && GET_MODE_CLASS (GET_MODE (trueop0)) == MODE_FLOAT)
2594 REAL_VALUE_TYPE d0, d1;
2596 REAL_VALUE_FROM_CONST_DOUBLE (d0, trueop0);
2597 REAL_VALUE_FROM_CONST_DOUBLE (d1, trueop1);
2599 /* Comparisons are unordered iff at least one of the values is NaN. */
2600 if (REAL_VALUE_ISNAN (d0) || REAL_VALUE_ISNAN (d1))
2610 return const_true_rtx;
2623 equal = REAL_VALUES_EQUAL (d0, d1);
2624 op0lt = op0ltu = REAL_VALUES_LESS (d0, d1);
2625 op1lt = op1ltu = REAL_VALUES_LESS (d1, d0);
2628 /* Otherwise, see if the operands are both integers. */
2629 else if ((GET_MODE_CLASS (mode) == MODE_INT || mode == VOIDmode)
2630 && (GET_CODE (trueop0) == CONST_DOUBLE
2631 || GET_CODE (trueop0) == CONST_INT)
2632 && (GET_CODE (trueop1) == CONST_DOUBLE
2633 || GET_CODE (trueop1) == CONST_INT))
2635 int width = GET_MODE_BITSIZE (mode);
2636 HOST_WIDE_INT l0s, h0s, l1s, h1s;
2637 unsigned HOST_WIDE_INT l0u, h0u, l1u, h1u;
2639 /* Get the two words comprising each integer constant. */
2640 if (GET_CODE (trueop0) == CONST_DOUBLE)
2642 l0u = l0s = CONST_DOUBLE_LOW (trueop0);
2643 h0u = h0s = CONST_DOUBLE_HIGH (trueop0);
2647 l0u = l0s = INTVAL (trueop0);
2648 h0u = h0s = HWI_SIGN_EXTEND (l0s);
2651 if (GET_CODE (trueop1) == CONST_DOUBLE)
2653 l1u = l1s = CONST_DOUBLE_LOW (trueop1);
2654 h1u = h1s = CONST_DOUBLE_HIGH (trueop1);
2658 l1u = l1s = INTVAL (trueop1);
2659 h1u = h1s = HWI_SIGN_EXTEND (l1s);
2662 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
2663 we have to sign or zero-extend the values. */
2664 if (width != 0 && width < HOST_BITS_PER_WIDE_INT)
2666 l0u &= ((HOST_WIDE_INT) 1 << width) - 1;
2667 l1u &= ((HOST_WIDE_INT) 1 << width) - 1;
2669 if (l0s & ((HOST_WIDE_INT) 1 << (width - 1)))
2670 l0s |= ((HOST_WIDE_INT) (-1) << width);
2672 if (l1s & ((HOST_WIDE_INT) 1 << (width - 1)))
2673 l1s |= ((HOST_WIDE_INT) (-1) << width);
2675 if (width != 0 && width <= HOST_BITS_PER_WIDE_INT)
2676 h0u = h1u = 0, h0s = HWI_SIGN_EXTEND (l0s), h1s = HWI_SIGN_EXTEND (l1s);
2678 equal = (h0u == h1u && l0u == l1u);
2679 op0lt = (h0s < h1s || (h0s == h1s && l0u < l1u));
2680 op1lt = (h1s < h0s || (h1s == h0s && l1u < l0u));
2681 op0ltu = (h0u < h1u || (h0u == h1u && l0u < l1u));
2682 op1ltu = (h1u < h0u || (h1u == h0u && l1u < l0u));
2685 /* Otherwise, there are some code-specific tests we can make. */
2691 if (trueop1 == const0_rtx && nonzero_address_p (op0))
2696 if (trueop1 == const0_rtx && nonzero_address_p (op0))
2697 return const_true_rtx;
2701 /* Unsigned values are never negative. */
2702 if (trueop1 == const0_rtx)
2703 return const_true_rtx;
2707 if (trueop1 == const0_rtx)
2712 /* Unsigned values are never greater than the largest
2714 if (GET_CODE (trueop1) == CONST_INT
2715 && (unsigned HOST_WIDE_INT) INTVAL (trueop1) == GET_MODE_MASK (mode)
2716 && INTEGRAL_MODE_P (mode))
2717 return const_true_rtx;
2721 if (GET_CODE (trueop1) == CONST_INT
2722 && (unsigned HOST_WIDE_INT) INTVAL (trueop1) == GET_MODE_MASK (mode)
2723 && INTEGRAL_MODE_P (mode))
2728 /* Optimize abs(x) < 0.0. */
2729 if (trueop1 == CONST0_RTX (mode) && !HONOR_SNANS (mode))
2731 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
2733 if (GET_CODE (tem) == ABS)
2739 /* Optimize abs(x) >= 0.0. */
2740 if (trueop1 == CONST0_RTX (mode) && !HONOR_NANS (mode))
2742 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
2744 if (GET_CODE (tem) == ABS)
2745 return const_true_rtx;
2750 /* Optimize ! (abs(x) < 0.0). */
2751 if (trueop1 == CONST0_RTX (mode))
2753 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
2755 if (GET_CODE (tem) == ABS)
2756 return const_true_rtx;
2767 /* If we reach here, EQUAL, OP0LT, OP0LTU, OP1LT, and OP1LTU are set
2773 return equal ? const_true_rtx : const0_rtx;
2776 return ! equal ? const_true_rtx : const0_rtx;
2779 return op0lt ? const_true_rtx : const0_rtx;
2782 return op1lt ? const_true_rtx : const0_rtx;
2784 return op0ltu ? const_true_rtx : const0_rtx;
2786 return op1ltu ? const_true_rtx : const0_rtx;
2789 return equal || op0lt ? const_true_rtx : const0_rtx;
2792 return equal || op1lt ? const_true_rtx : const0_rtx;
2794 return equal || op0ltu ? const_true_rtx : const0_rtx;
2796 return equal || op1ltu ? const_true_rtx : const0_rtx;
2798 return const_true_rtx;
2806 /* Simplify CODE, an operation with result mode MODE and three operands,
2807 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
2808 a constant. Return 0 if no simplifications is possible. */
2811 simplify_ternary_operation (enum rtx_code code, enum machine_mode mode,
2812 enum machine_mode op0_mode, rtx op0, rtx op1,
2815 unsigned int width = GET_MODE_BITSIZE (mode);
2817 /* VOIDmode means "infinite" precision. */
2819 width = HOST_BITS_PER_WIDE_INT;
2825 if (GET_CODE (op0) == CONST_INT
2826 && GET_CODE (op1) == CONST_INT
2827 && GET_CODE (op2) == CONST_INT
2828 && ((unsigned) INTVAL (op1) + (unsigned) INTVAL (op2) <= width)
2829 && width <= (unsigned) HOST_BITS_PER_WIDE_INT)
2831 /* Extracting a bit-field from a constant */
2832 HOST_WIDE_INT val = INTVAL (op0);
2834 if (BITS_BIG_ENDIAN)
2835 val >>= (GET_MODE_BITSIZE (op0_mode)
2836 - INTVAL (op2) - INTVAL (op1));
2838 val >>= INTVAL (op2);
2840 if (HOST_BITS_PER_WIDE_INT != INTVAL (op1))
2842 /* First zero-extend. */
2843 val &= ((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1;
2844 /* If desired, propagate sign bit. */
2845 if (code == SIGN_EXTRACT
2846 && (val & ((HOST_WIDE_INT) 1 << (INTVAL (op1) - 1))))
2847 val |= ~ (((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1);
2850 /* Clear the bits that don't belong in our mode,
2851 unless they and our sign bit are all one.
2852 So we get either a reasonable negative value or a reasonable
2853 unsigned value for this mode. */
2854 if (width < HOST_BITS_PER_WIDE_INT
2855 && ((val & ((HOST_WIDE_INT) (-1) << (width - 1)))
2856 != ((HOST_WIDE_INT) (-1) << (width - 1))))
2857 val &= ((HOST_WIDE_INT) 1 << width) - 1;
2859 return GEN_INT (val);
2864 if (GET_CODE (op0) == CONST_INT)
2865 return op0 != const0_rtx ? op1 : op2;
2867 /* Convert c ? a : a into "a". */
2868 if (rtx_equal_p (op1, op2) && ! side_effects_p (op0))
2871 /* Convert a != b ? a : b into "a". */
2872 if (GET_CODE (op0) == NE
2873 && ! side_effects_p (op0)
2874 && ! HONOR_NANS (mode)
2875 && ! HONOR_SIGNED_ZEROS (mode)
2876 && ((rtx_equal_p (XEXP (op0, 0), op1)
2877 && rtx_equal_p (XEXP (op0, 1), op2))
2878 || (rtx_equal_p (XEXP (op0, 0), op2)
2879 && rtx_equal_p (XEXP (op0, 1), op1))))
2882 /* Convert a == b ? a : b into "b". */
2883 if (GET_CODE (op0) == EQ
2884 && ! side_effects_p (op0)
2885 && ! HONOR_NANS (mode)
2886 && ! HONOR_SIGNED_ZEROS (mode)
2887 && ((rtx_equal_p (XEXP (op0, 0), op1)
2888 && rtx_equal_p (XEXP (op0, 1), op2))
2889 || (rtx_equal_p (XEXP (op0, 0), op2)
2890 && rtx_equal_p (XEXP (op0, 1), op1))))
2893 if (COMPARISON_P (op0) && ! side_effects_p (op0))
2895 enum machine_mode cmp_mode = (GET_MODE (XEXP (op0, 0)) == VOIDmode
2896 ? GET_MODE (XEXP (op0, 1))
2897 : GET_MODE (XEXP (op0, 0)));
2899 if (cmp_mode == VOIDmode)
2900 cmp_mode = op0_mode;
2901 temp = simplify_relational_operation (GET_CODE (op0), cmp_mode,
2902 XEXP (op0, 0), XEXP (op0, 1));
2904 /* See if any simplifications were possible. */
2905 if (temp == const0_rtx)
2907 else if (temp == const_true_rtx)
2912 /* Look for happy constants in op1 and op2. */
2913 if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
2915 HOST_WIDE_INT t = INTVAL (op1);
2916 HOST_WIDE_INT f = INTVAL (op2);
2918 if (t == STORE_FLAG_VALUE && f == 0)
2919 code = GET_CODE (op0);
2920 else if (t == 0 && f == STORE_FLAG_VALUE)
2923 tmp = reversed_comparison_code (op0, NULL_RTX);
2931 return gen_rtx_fmt_ee (code, mode, XEXP (op0, 0), XEXP (op0, 1));
2937 if (GET_MODE (op0) != mode
2938 || GET_MODE (op1) != mode
2939 || !VECTOR_MODE_P (mode))
2941 op2 = avoid_constant_pool_reference (op2);
2942 if (GET_CODE (op2) == CONST_INT)
2944 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
2945 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
2946 int mask = (1 << n_elts) - 1;
2948 if (!(INTVAL (op2) & mask))
2950 if ((INTVAL (op2) & mask) == mask)
2953 op0 = avoid_constant_pool_reference (op0);
2954 op1 = avoid_constant_pool_reference (op1);
2955 if (GET_CODE (op0) == CONST_VECTOR
2956 && GET_CODE (op1) == CONST_VECTOR)
2958 rtvec v = rtvec_alloc (n_elts);
2961 for (i = 0; i < n_elts; i++)
2962 RTVEC_ELT (v, i) = (INTVAL (op2) & (1 << i)
2963 ? CONST_VECTOR_ELT (op0, i)
2964 : CONST_VECTOR_ELT (op1, i));
2965 return gen_rtx_CONST_VECTOR (mode, v);
2977 /* Evaluate a SUBREG of a CONST_INT or CONST_DOUBLE or CONST_VECTOR,
2978 returning another CONST_INT or CONST_DOUBLE or CONST_VECTOR.
2980 Works by unpacking OP into a collection of 8-bit values
2981 represented as a little-endian array of 'unsigned char', selecting by BYTE,
2982 and then repacking them again for OUTERMODE. */
2985 simplify_immed_subreg (enum machine_mode outermode, rtx op,
2986 enum machine_mode innermode, unsigned int byte)
2988 /* We support up to 512-bit values (for V8DFmode). */
2992 value_mask = (1 << value_bit) - 1
2994 unsigned char value[max_bitsize / value_bit];
3003 rtvec result_v = NULL;
3004 enum mode_class outer_class;
3005 enum machine_mode outer_submode;
3007 /* Some ports misuse CCmode. */
3008 if (GET_MODE_CLASS (outermode) == MODE_CC && GET_CODE (op) == CONST_INT)
3011 /* Unpack the value. */
3013 if (GET_CODE (op) == CONST_VECTOR)
3015 num_elem = CONST_VECTOR_NUNITS (op);
3016 elems = &CONST_VECTOR_ELT (op, 0);
3017 elem_bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (innermode));
3023 elem_bitsize = max_bitsize;
3026 if (BITS_PER_UNIT % value_bit != 0)
3027 abort (); /* Too complicated; reducing value_bit may help. */
3028 if (elem_bitsize % BITS_PER_UNIT != 0)
3029 abort (); /* I don't know how to handle endianness of sub-units. */
3031 for (elem = 0; elem < num_elem; elem++)
3034 rtx el = elems[elem];
3036 /* Vectors are kept in target memory order. (This is probably
3039 unsigned byte = (elem * elem_bitsize) / BITS_PER_UNIT;
3040 unsigned ibyte = (((num_elem - 1 - elem) * elem_bitsize)
3042 unsigned word_byte = WORDS_BIG_ENDIAN ? ibyte : byte;
3043 unsigned subword_byte = BYTES_BIG_ENDIAN ? ibyte : byte;
3044 unsigned bytele = (subword_byte % UNITS_PER_WORD
3045 + (word_byte / UNITS_PER_WORD) * UNITS_PER_WORD);
3046 vp = value + (bytele * BITS_PER_UNIT) / value_bit;
3049 switch (GET_CODE (el))
3053 i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize;
3055 *vp++ = INTVAL (el) >> i;
3056 /* CONST_INTs are always logically sign-extended. */
3057 for (; i < elem_bitsize; i += value_bit)
3058 *vp++ = INTVAL (el) < 0 ? -1 : 0;
3062 if (GET_MODE (el) == VOIDmode)
3064 /* If this triggers, someone should have generated a
3065 CONST_INT instead. */
3066 if (elem_bitsize <= HOST_BITS_PER_WIDE_INT)
3069 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i += value_bit)
3070 *vp++ = CONST_DOUBLE_LOW (el) >> i;
3071 while (i < HOST_BITS_PER_WIDE_INT * 2 && i < elem_bitsize)
3074 = CONST_DOUBLE_HIGH (el) >> (i - HOST_BITS_PER_WIDE_INT);
3077 /* It shouldn't matter what's done here, so fill it with
3079 for (; i < max_bitsize; i += value_bit)
3082 else if (GET_MODE_CLASS (GET_MODE (el)) == MODE_FLOAT)
3084 long tmp[max_bitsize / 32];
3085 int bitsize = GET_MODE_BITSIZE (GET_MODE (el));
3087 if (bitsize > elem_bitsize)
3089 if (bitsize % value_bit != 0)
3092 real_to_target (tmp, CONST_DOUBLE_REAL_VALUE (el),
3095 /* real_to_target produces its result in words affected by
3096 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
3097 and use WORDS_BIG_ENDIAN instead; see the documentation
3098 of SUBREG in rtl.texi. */
3099 for (i = 0; i < bitsize; i += value_bit)
3102 if (WORDS_BIG_ENDIAN)
3103 ibase = bitsize - 1 - i;
3106 *vp++ = tmp[ibase / 32] >> i % 32;
3109 /* It shouldn't matter what's done here, so fill it with
3111 for (; i < elem_bitsize; i += value_bit)
3123 /* Now, pick the right byte to start with. */
3124 /* Renumber BYTE so that the least-significant byte is byte 0. A special
3125 case is paradoxical SUBREGs, which shouldn't be adjusted since they
3126 will already have offset 0. */
3127 if (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode))
3129 unsigned ibyte = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)
3131 unsigned word_byte = WORDS_BIG_ENDIAN ? ibyte : byte;
3132 unsigned subword_byte = BYTES_BIG_ENDIAN ? ibyte : byte;
3133 byte = (subword_byte % UNITS_PER_WORD
3134 + (word_byte / UNITS_PER_WORD) * UNITS_PER_WORD);
3137 /* BYTE should still be inside OP. (Note that BYTE is unsigned,
3138 so if it's become negative it will instead be very large.) */
3139 if (byte >= GET_MODE_SIZE (innermode))
3142 /* Convert from bytes to chunks of size value_bit. */
3143 value_start = byte * (BITS_PER_UNIT / value_bit);
3145 /* Re-pack the value. */
3147 if (VECTOR_MODE_P (outermode))
3149 num_elem = GET_MODE_NUNITS (outermode);
3150 result_v = rtvec_alloc (num_elem);
3151 elems = &RTVEC_ELT (result_v, 0);
3152 outer_submode = GET_MODE_INNER (outermode);
3158 outer_submode = outermode;
3161 outer_class = GET_MODE_CLASS (outer_submode);
3162 elem_bitsize = GET_MODE_BITSIZE (outer_submode);
3164 if (elem_bitsize % value_bit != 0)
3166 if (elem_bitsize + value_start * value_bit > max_bitsize)
3169 for (elem = 0; elem < num_elem; elem++)
3173 /* Vectors are stored in target memory order. (This is probably
3176 unsigned byte = (elem * elem_bitsize) / BITS_PER_UNIT;
3177 unsigned ibyte = (((num_elem - 1 - elem) * elem_bitsize)
3179 unsigned word_byte = WORDS_BIG_ENDIAN ? ibyte : byte;
3180 unsigned subword_byte = BYTES_BIG_ENDIAN ? ibyte : byte;
3181 unsigned bytele = (subword_byte % UNITS_PER_WORD
3182 + (word_byte / UNITS_PER_WORD) * UNITS_PER_WORD);
3183 vp = value + value_start + (bytele * BITS_PER_UNIT) / value_bit;
3186 switch (outer_class)
3189 case MODE_PARTIAL_INT:
3191 unsigned HOST_WIDE_INT hi = 0, lo = 0;
3194 i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize;
3196 lo |= (HOST_WIDE_INT)(*vp++ & value_mask) << i;
3197 for (; i < elem_bitsize; i += value_bit)
3198 hi |= ((HOST_WIDE_INT)(*vp++ & value_mask)
3199 << (i - HOST_BITS_PER_WIDE_INT));
3201 /* immed_double_const doesn't call trunc_int_for_mode. I don't
3203 if (elem_bitsize <= HOST_BITS_PER_WIDE_INT)
3204 elems[elem] = gen_int_mode (lo, outer_submode);
3206 elems[elem] = immed_double_const (lo, hi, outer_submode);
3213 long tmp[max_bitsize / 32];
3215 /* real_from_target wants its input in words affected by
3216 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
3217 and use WORDS_BIG_ENDIAN instead; see the documentation
3218 of SUBREG in rtl.texi. */
3219 for (i = 0; i < max_bitsize / 32; i++)
3221 for (i = 0; i < elem_bitsize; i += value_bit)
3224 if (WORDS_BIG_ENDIAN)
3225 ibase = elem_bitsize - 1 - i;
3228 tmp[ibase / 32] |= (*vp++ & value_mask) << i % 32;
3231 real_from_target (&r, tmp, outer_submode);
3232 elems[elem] = CONST_DOUBLE_FROM_REAL_VALUE (r, outer_submode);
3240 if (VECTOR_MODE_P (outermode))
3241 return gen_rtx_CONST_VECTOR (outermode, result_v);
3246 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
3247 Return 0 if no simplifications are possible. */
3249 simplify_subreg (enum machine_mode outermode, rtx op,
3250 enum machine_mode innermode, unsigned int byte)
3252 /* Little bit of sanity checking. */
3253 if (innermode == VOIDmode || outermode == VOIDmode
3254 || innermode == BLKmode || outermode == BLKmode)
3257 if (GET_MODE (op) != innermode
3258 && GET_MODE (op) != VOIDmode)
3261 if (byte % GET_MODE_SIZE (outermode)
3262 || byte >= GET_MODE_SIZE (innermode))
3265 if (outermode == innermode && !byte)
3268 if (GET_CODE (op) == CONST_INT
3269 || GET_CODE (op) == CONST_DOUBLE
3270 || GET_CODE (op) == CONST_VECTOR)
3271 return simplify_immed_subreg (outermode, op, innermode, byte);
3273 /* Changing mode twice with SUBREG => just change it once,
3274 or not at all if changing back op starting mode. */
3275 if (GET_CODE (op) == SUBREG)
3277 enum machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
3278 int final_offset = byte + SUBREG_BYTE (op);
3281 if (outermode == innermostmode
3282 && byte == 0 && SUBREG_BYTE (op) == 0)
3283 return SUBREG_REG (op);
3285 /* The SUBREG_BYTE represents offset, as if the value were stored
3286 in memory. Irritating exception is paradoxical subreg, where
3287 we define SUBREG_BYTE to be 0. On big endian machines, this
3288 value should be negative. For a moment, undo this exception. */
3289 if (byte == 0 && GET_MODE_SIZE (innermode) < GET_MODE_SIZE (outermode))
3291 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
3292 if (WORDS_BIG_ENDIAN)
3293 final_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
3294 if (BYTES_BIG_ENDIAN)
3295 final_offset += difference % UNITS_PER_WORD;
3297 if (SUBREG_BYTE (op) == 0
3298 && GET_MODE_SIZE (innermostmode) < GET_MODE_SIZE (innermode))
3300 int difference = (GET_MODE_SIZE (innermostmode) - GET_MODE_SIZE (innermode));
3301 if (WORDS_BIG_ENDIAN)
3302 final_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
3303 if (BYTES_BIG_ENDIAN)
3304 final_offset += difference % UNITS_PER_WORD;
3307 /* See whether resulting subreg will be paradoxical. */
3308 if (GET_MODE_SIZE (innermostmode) > GET_MODE_SIZE (outermode))
3310 /* In nonparadoxical subregs we can't handle negative offsets. */
3311 if (final_offset < 0)
3313 /* Bail out in case resulting subreg would be incorrect. */
3314 if (final_offset % GET_MODE_SIZE (outermode)
3315 || (unsigned) final_offset >= GET_MODE_SIZE (innermostmode))
3321 int difference = (GET_MODE_SIZE (innermostmode) - GET_MODE_SIZE (outermode));
3323 /* In paradoxical subreg, see if we are still looking on lower part.
3324 If so, our SUBREG_BYTE will be 0. */
3325 if (WORDS_BIG_ENDIAN)
3326 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
3327 if (BYTES_BIG_ENDIAN)
3328 offset += difference % UNITS_PER_WORD;
3329 if (offset == final_offset)
3335 /* Recurse for further possible simplifications. */
3336 new = simplify_subreg (outermode, SUBREG_REG (op),
3337 GET_MODE (SUBREG_REG (op)),
3341 return gen_rtx_SUBREG (outermode, SUBREG_REG (op), final_offset);
3344 /* SUBREG of a hard register => just change the register number
3345 and/or mode. If the hard register is not valid in that mode,
3346 suppress this simplification. If the hard register is the stack,
3347 frame, or argument pointer, leave this as a SUBREG. */
3350 && (! REG_FUNCTION_VALUE_P (op)
3351 || ! rtx_equal_function_value_matters)
3352 && REGNO (op) < FIRST_PSEUDO_REGISTER
3353 #ifdef CANNOT_CHANGE_MODE_CLASS
3354 && ! (REG_CANNOT_CHANGE_MODE_P (REGNO (op), innermode, outermode)
3355 && GET_MODE_CLASS (innermode) != MODE_COMPLEX_INT
3356 && GET_MODE_CLASS (innermode) != MODE_COMPLEX_FLOAT)
3358 && ((reload_completed && !frame_pointer_needed)
3359 || (REGNO (op) != FRAME_POINTER_REGNUM
3360 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3361 && REGNO (op) != HARD_FRAME_POINTER_REGNUM
3364 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3365 && REGNO (op) != ARG_POINTER_REGNUM
3367 && REGNO (op) != STACK_POINTER_REGNUM
3368 && subreg_offset_representable_p (REGNO (op), innermode,
3371 rtx tem = gen_rtx_SUBREG (outermode, op, byte);
3372 int final_regno = subreg_hard_regno (tem, 0);
3374 /* ??? We do allow it if the current REG is not valid for
3375 its mode. This is a kludge to work around how float/complex
3376 arguments are passed on 32-bit SPARC and should be fixed. */
3377 if (HARD_REGNO_MODE_OK (final_regno, outermode)
3378 || ! HARD_REGNO_MODE_OK (REGNO (op), innermode))
3380 rtx x = gen_rtx_REG_offset (op, outermode, final_regno, byte);
3382 /* Propagate original regno. We don't have any way to specify
3383 the offset inside original regno, so do so only for lowpart.
3384 The information is used only by alias analysis that can not
3385 grog partial register anyway. */
3387 if (subreg_lowpart_offset (outermode, innermode) == byte)
3388 ORIGINAL_REGNO (x) = ORIGINAL_REGNO (op);
3393 /* If we have a SUBREG of a register that we are replacing and we are
3394 replacing it with a MEM, make a new MEM and try replacing the
3395 SUBREG with it. Don't do this if the MEM has a mode-dependent address
3396 or if we would be widening it. */
3398 if (GET_CODE (op) == MEM
3399 && ! mode_dependent_address_p (XEXP (op, 0))
3400 /* Allow splitting of volatile memory references in case we don't
3401 have instruction to move the whole thing. */
3402 && (! MEM_VOLATILE_P (op)
3403 || ! have_insn_for (SET, innermode))
3404 && GET_MODE_SIZE (outermode) <= GET_MODE_SIZE (GET_MODE (op)))
3405 return adjust_address_nv (op, outermode, byte);
3407 /* Handle complex values represented as CONCAT
3408 of real and imaginary part. */
3409 if (GET_CODE (op) == CONCAT)
3411 int is_realpart = byte < (unsigned int) GET_MODE_UNIT_SIZE (innermode);
3412 rtx part = is_realpart ? XEXP (op, 0) : XEXP (op, 1);
3413 unsigned int final_offset;
3416 final_offset = byte % (GET_MODE_UNIT_SIZE (innermode));
3417 res = simplify_subreg (outermode, part, GET_MODE (part), final_offset);
3420 /* We can at least simplify it by referring directly to the
3422 return gen_rtx_SUBREG (outermode, part, final_offset);
3425 /* Optimize SUBREG truncations of zero and sign extended values. */
3426 if ((GET_CODE (op) == ZERO_EXTEND
3427 || GET_CODE (op) == SIGN_EXTEND)
3428 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode))
3430 unsigned int bitpos = subreg_lsb_1 (outermode, innermode, byte);
3432 /* If we're requesting the lowpart of a zero or sign extension,
3433 there are three possibilities. If the outermode is the same
3434 as the origmode, we can omit both the extension and the subreg.
3435 If the outermode is not larger than the origmode, we can apply
3436 the truncation without the extension. Finally, if the outermode
3437 is larger than the origmode, but both are integer modes, we
3438 can just extend to the appropriate mode. */
3441 enum machine_mode origmode = GET_MODE (XEXP (op, 0));
3442 if (outermode == origmode)
3443 return XEXP (op, 0);
3444 if (GET_MODE_BITSIZE (outermode) <= GET_MODE_BITSIZE (origmode))
3445 return simplify_gen_subreg (outermode, XEXP (op, 0), origmode,
3446 subreg_lowpart_offset (outermode,
3448 if (SCALAR_INT_MODE_P (outermode))
3449 return simplify_gen_unary (GET_CODE (op), outermode,
3450 XEXP (op, 0), origmode);
3453 /* A SUBREG resulting from a zero extension may fold to zero if
3454 it extracts higher bits that the ZERO_EXTEND's source bits. */
3455 if (GET_CODE (op) == ZERO_EXTEND
3456 && bitpos >= GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))))
3457 return CONST0_RTX (outermode);
3463 /* Make a SUBREG operation or equivalent if it folds. */
3466 simplify_gen_subreg (enum machine_mode outermode, rtx op,
3467 enum machine_mode innermode, unsigned int byte)
3470 /* Little bit of sanity checking. */
3471 if (innermode == VOIDmode || outermode == VOIDmode
3472 || innermode == BLKmode || outermode == BLKmode)
3475 if (GET_MODE (op) != innermode
3476 && GET_MODE (op) != VOIDmode)
3479 if (byte % GET_MODE_SIZE (outermode)
3480 || byte >= GET_MODE_SIZE (innermode))
3483 if (GET_CODE (op) == QUEUED)
3486 new = simplify_subreg (outermode, op, innermode, byte);
3490 if (GET_CODE (op) == SUBREG || GET_MODE (op) == VOIDmode)
3493 return gen_rtx_SUBREG (outermode, op, byte);
3495 /* Simplify X, an rtx expression.
3497 Return the simplified expression or NULL if no simplifications
3500 This is the preferred entry point into the simplification routines;
3501 however, we still allow passes to call the more specific routines.
3503 Right now GCC has three (yes, three) major bodies of RTL simplification
3504 code that need to be unified.
3506 1. fold_rtx in cse.c. This code uses various CSE specific
3507 information to aid in RTL simplification.
3509 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
3510 it uses combine specific information to aid in RTL
3513 3. The routines in this file.
3516 Long term we want to only have one body of simplification code; to
3517 get to that state I recommend the following steps:
3519 1. Pour over fold_rtx & simplify_rtx and move any simplifications
3520 which are not pass dependent state into these routines.
3522 2. As code is moved by #1, change fold_rtx & simplify_rtx to
3523 use this routine whenever possible.
3525 3. Allow for pass dependent state to be provided to these
3526 routines and add simplifications based on the pass dependent
3527 state. Remove code from cse.c & combine.c that becomes
3530 It will take time, but ultimately the compiler will be easier to
3531 maintain and improve. It's totally silly that when we add a
3532 simplification that it needs to be added to 4 places (3 for RTL
3533 simplification and 1 for tree simplification. */
3536 simplify_rtx (rtx x)
3538 enum rtx_code code = GET_CODE (x);
3539 enum machine_mode mode = GET_MODE (x);
3542 switch (GET_RTX_CLASS (code))
3545 return simplify_unary_operation (code, mode,
3546 XEXP (x, 0), GET_MODE (XEXP (x, 0)));
3547 case RTX_COMM_ARITH:
3548 if (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3549 return simplify_gen_binary (code, mode, XEXP (x, 1), XEXP (x, 0));
3551 /* Fall through.... */
3554 return simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3557 case RTX_BITFIELD_OPS:
3558 return simplify_ternary_operation (code, mode, GET_MODE (XEXP (x, 0)),
3559 XEXP (x, 0), XEXP (x, 1),
3563 case RTX_COMM_COMPARE:
3564 temp = simplify_relational_operation (code,
3565 ((GET_MODE (XEXP (x, 0))
3567 ? GET_MODE (XEXP (x, 0))
3568 : GET_MODE (XEXP (x, 1))),
3569 XEXP (x, 0), XEXP (x, 1));
3570 #ifdef FLOAT_STORE_FLAG_VALUE
3571 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3573 if (temp == const0_rtx)
3574 temp = CONST0_RTX (mode);
3576 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3584 return simplify_gen_subreg (mode, SUBREG_REG (x),
3585 GET_MODE (SUBREG_REG (x)),
3587 if (code == CONSTANT_P_RTX)
3589 if (CONSTANT_P (XEXP (x, 0)))
3597 /* Convert (lo_sum (high FOO) FOO) to FOO. */
3598 if (GET_CODE (XEXP (x, 0)) == HIGH
3599 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))