1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "insn-config.h"
31 #include "insn-attr.h"
34 #include "sched-int.h"
35 #include "rtlhooks-def.h"
40 #ifdef INSN_SCHEDULING
43 #include "sel-sched-ir.h"
44 #include "sel-sched-dump.h"
45 #include "sel-sched.h"
48 /* Implementation of selective scheduling approach.
49 The below implementation follows the original approach with the following
52 o the scheduler works after register allocation (but can be also tuned
54 o some instructions are not copied or register renamed;
55 o conditional jumps are not moved with code duplication;
56 o several jumps in one parallel group are not supported;
57 o when pipelining outer loops, code motion through inner loops
59 o control and data speculation are supported;
60 o some improvements for better compile time/performance were made.
65 A vinsn, or virtual insn, is an insn with additional data characterizing
66 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
67 Vinsns also act as smart pointers to save memory by reusing them in
68 different expressions. A vinsn is described by vinsn_t type.
70 An expression is a vinsn with additional data characterizing its properties
71 at some point in the control flow graph. The data may be its usefulness,
72 priority, speculative status, whether it was renamed/subsituted, etc.
73 An expression is described by expr_t type.
75 Availability set (av_set) is a set of expressions at a given control flow
76 point. It is represented as av_set_t. The expressions in av sets are kept
77 sorted in the terms of expr_greater_p function. It allows to truncate
78 the set while leaving the best expressions.
80 A fence is a point through which code motion is prohibited. On each step,
81 we gather a parallel group of insns at a fence. It is possible to have
82 multiple fences. A fence is represented via fence_t.
84 A boundary is the border between the fence group and the rest of the code.
85 Currently, we never have more than one boundary per fence, as we finalize
86 the fence group when a jump is scheduled. A boundary is represented
92 The scheduler finds regions to schedule, schedules each one, and finalizes.
93 The regions are formed starting from innermost loops, so that when the inner
94 loop is pipelined, its prologue can be scheduled together with yet unprocessed
95 outer loop. The rest of acyclic regions are found using extend_rgns:
96 the blocks that are not yet allocated to any regions are traversed in top-down
97 order, and a block is added to a region to which all its predecessors belong;
98 otherwise, the block starts its own region.
100 The main scheduling loop (sel_sched_region_2) consists of just
101 scheduling on each fence and updating fences. For each fence,
102 we fill a parallel group of insns (fill_insns) until some insns can be added.
103 First, we compute available exprs (av-set) at the boundary of the current
104 group. Second, we choose the best expression from it. If the stall is
105 required to schedule any of the expressions, we advance the current cycle
106 appropriately. So, the final group does not exactly correspond to a VLIW
107 word. Third, we move the chosen expression to the boundary (move_op)
108 and update the intermediate av sets and liveness sets. We quit fill_insns
109 when either no insns left for scheduling or we have scheduled enough insns
110 so we feel like advancing a scheduling point.
112 Computing available expressions
113 ===============================
115 The computation (compute_av_set) is a bottom-up traversal. At each insn,
116 we're moving the union of its successors' sets through it via
117 moveup_expr_set. The dependent expressions are removed. Local
118 transformations (substitution, speculation) are applied to move more
119 exprs. Then the expr corresponding to the current insn is added.
120 The result is saved on each basic block header.
122 When traversing the CFG, we're moving down for no more than max_ws insns.
123 Also, we do not move down to ineligible successors (is_ineligible_successor),
124 which include moving along a back-edge, moving to already scheduled code,
125 and moving to another fence. The first two restrictions are lifted during
126 pipelining, which allows us to move insns along a back-edge. We always have
127 an acyclic region for scheduling because we forbid motion through fences.
129 Choosing the best expression
130 ============================
132 We sort the final availability set via sel_rank_for_schedule, then we remove
133 expressions which are not yet ready (tick_check_p) or which dest registers
134 cannot be used. For some of them, we choose another register via
135 find_best_reg. To do this, we run find_used_regs to calculate the set of
136 registers which cannot be used. The find_used_regs function performs
137 a traversal of code motion paths for an expr. We consider for renaming
138 only registers which are from the same regclass as the original one and
139 using which does not interfere with any live ranges. Finally, we convert
140 the resulting set to the ready list format and use max_issue and reorder*
141 hooks similarly to the Haifa scheduler.
143 Scheduling the best expression
144 ==============================
146 We run the move_op routine to perform the same type of code motion paths
147 traversal as in find_used_regs. (These are working via the same driver,
148 code_motion_path_driver.) When moving down the CFG, we look for original
149 instruction that gave birth to a chosen expression. We undo
150 the transformations performed on an expression via the history saved in it.
151 When found, we remove the instruction or leave a reg-reg copy/speculation
152 check if needed. On a way up, we insert bookkeeping copies at each join
153 point. If a copy is not needed, it will be removed later during this
154 traversal. We update the saved av sets and liveness sets on the way up, too.
156 Finalizing the schedule
157 =======================
159 When pipelining, we reschedule the blocks from which insns were pipelined
160 to get a tighter schedule. On Itanium, we also perform bundling via
161 the same routine from ia64.c.
163 Dependence analysis changes
164 ===========================
166 We augmented the sched-deps.c with hooks that get called when a particular
167 dependence is found in a particular part of an insn. Using these hooks, we
168 can do several actions such as: determine whether an insn can be moved through
169 another (has_dependence_p, moveup_expr); find out whether an insn can be
170 scheduled on the current cycle (tick_check_p); find out registers that
171 are set/used/clobbered by an insn and find out all the strange stuff that
172 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
173 init_global_and_expr_for_insn).
175 Initialization changes
176 ======================
178 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
179 reused in all of the schedulers. We have split up the initialization of data
180 of such parts into different functions prefixed with scheduler type and
181 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
182 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
183 The same splitting is done with current_sched_info structure:
184 dependence-related parts are in sched_deps_info, common part is in
185 common_sched_info, and haifa/sel/etc part is in current_sched_info.
190 As we now have multiple-point scheduling, this would not work with backends
191 which save some of the scheduler state to use it in the target hooks.
192 For this purpose, we introduce a concept of target contexts, which
193 encapsulate such information. The backend should implement simple routines
194 of allocating/freeing/setting such a context. The scheduler calls these
195 as target hooks and handles the target context as an opaque pointer (similar
196 to the DFA state type, state_t).
201 As the correct data dependence graph is not supported during scheduling (which
202 is to be changed in mid-term), we cache as much of the dependence analysis
203 results as possible to avoid reanalyzing. This includes: bitmap caches on
204 each insn in stream of the region saying yes/no for a query with a pair of
205 UIDs; hashtables with the previously done transformations on each insn in
206 stream; a vector keeping a history of transformations on each expr.
208 Also, we try to minimize the dependence context used on each fence to check
209 whether the given expression is ready for scheduling by removing from it
210 insns that are definitely completed the execution. The results of
211 tick_check_p checks are also cached in a vector on each fence.
213 We keep a valid liveness set on each insn in a region to avoid the high
214 cost of recomputation on large basic blocks.
216 Finally, we try to minimize the number of needed updates to the availability
217 sets. The updates happen in two cases: when fill_insns terminates,
218 we advance all fences and increase the stage number to show that the region
219 has changed and the sets are to be recomputed; and when the next iteration
220 of a loop in fill_insns happens (but this one reuses the saved av sets
221 on bb headers.) Thus, we try to break the fill_insns loop only when
222 "significant" number of insns from the current scheduling window was
223 scheduled. This should be made a target param.
226 TODO: correctly support the data dependence graph at all stages and get rid
227 of all caches. This should speed up the scheduler.
228 TODO: implement moving cond jumps with bookkeeping copies on both targets.
229 TODO: tune the scheduler before RA so it does not create too much pseudos.
233 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
234 selective scheduling and software pipelining.
235 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
237 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
238 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
239 for GCC. In Proceedings of GCC Developers' Summit 2006.
241 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
242 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
243 http://rogue.colorado.edu/EPIC7/.
247 /* True when pipelining is enabled. */
250 /* True if bookkeeping is enabled. */
253 /* Maximum number of insns that are eligible for renaming. */
254 int max_insns_to_rename;
257 /* Definitions of local types and macros. */
259 /* Represents possible outcomes of moving an expression through an insn. */
260 enum MOVEUP_EXPR_CODE
262 /* The expression is not changed. */
265 /* Not changed, but requires a new destination register. */
268 /* Cannot be moved. */
271 /* Changed (substituted or speculated). */
275 /* The container to be passed into rtx search & replace functions. */
276 struct rtx_search_arg
278 /* What we are searching for. */
281 /* The occurrence counter. */
285 typedef struct rtx_search_arg *rtx_search_arg_p;
287 /* This struct contains precomputed hard reg sets that are needed when
288 computing registers available for renaming. */
289 struct hard_regs_data
291 /* For every mode, this stores registers available for use with
293 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
295 /* True when regs_for_mode[mode] is initialized. */
296 bool regs_for_mode_ok[NUM_MACHINE_MODES];
298 /* For every register, it has regs that are ok to rename into it.
299 The register in question is always set. If not, this means
300 that the whole set is not computed yet. */
301 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
303 /* For every mode, this stores registers not available due to
305 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
307 /* All registers that are used or call used. */
308 HARD_REG_SET regs_ever_used;
311 /* Stack registers. */
312 HARD_REG_SET stack_regs;
316 /* Holds the results of computation of available for renaming and
317 unavailable hard registers. */
320 /* These are unavailable due to calls crossing, globalness, etc. */
321 HARD_REG_SET unavailable_hard_regs;
323 /* These are *available* for renaming. */
324 HARD_REG_SET available_for_renaming;
326 /* Whether this code motion path crosses a call. */
330 /* A global structure that contains the needed information about harg
332 static struct hard_regs_data sel_hrd;
335 /* This structure holds local data used in code_motion_path_driver hooks on
336 the same or adjacent levels of recursion. Here we keep those parameters
337 that are not used in code_motion_path_driver routine itself, but only in
338 its hooks. Moreover, all parameters that can be modified in hooks are
339 in this structure, so all other parameters passed explicitly to hooks are
341 struct cmpd_local_params
343 /* Local params used in move_op_* functions. */
345 /* Edges for bookkeeping generation. */
348 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
349 expr_t c_expr_merged, c_expr_local;
351 /* Local params used in fur_* functions. */
352 /* Copy of the ORIGINAL_INSN list, stores the original insns already
353 found before entering the current level of code_motion_path_driver. */
354 def_list_t old_original_insns;
356 /* Local params used in move_op_* functions. */
357 /* True when we have removed last insn in the block which was
358 also a boundary. Do not update anything or create bookkeeping copies. */
359 BOOL_BITFIELD removed_last_insn : 1;
362 /* Stores the static parameters for move_op_* calls. */
363 struct moveop_static_params
365 /* Destination register. */
368 /* Current C_EXPR. */
371 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
372 they are to be removed. */
375 /* This is initialized to the insn on which the driver stopped its traversal. */
378 /* True if we scheduled an insn with different register. */
382 /* Stores the static parameters for fur_* calls. */
383 struct fur_static_params
385 /* Set of registers unavailable on the code motion path. */
388 /* Pointer to the list of original insns definitions. */
389 def_list_t *original_insns;
391 /* True if a code motion path contains a CALL insn. */
395 typedef struct fur_static_params *fur_static_params_p;
396 typedef struct cmpd_local_params *cmpd_local_params_p;
397 typedef struct moveop_static_params *moveop_static_params_p;
399 /* Set of hooks and parameters that determine behavior specific to
400 move_op or find_used_regs functions. */
401 struct code_motion_path_driver_info_def
403 /* Called on enter to the basic block. */
404 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
406 /* Called when original expr is found. */
407 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
409 /* Called while descending current basic block if current insn is not
410 the original EXPR we're searching for. */
411 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
413 /* Function to merge C_EXPRes from different successors. */
414 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
416 /* Function to finalize merge from different successors and possibly
417 deallocate temporary data structures used for merging. */
418 void (*after_merge_succs) (cmpd_local_params_p, void *);
420 /* Called on the backward stage of recursion to do moveup_expr.
421 Used only with move_op_*. */
422 void (*ascend) (insn_t, void *);
424 /* Called on the ascending pass, before returning from the current basic
425 block or from the whole traversal. */
426 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
428 /* When processing successors in move_op we need only descend into
429 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
432 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
433 const char *routine_name;
436 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
438 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
440 /* Set of hooks for performing move_op and find_used_regs routines with
441 code_motion_path_driver. */
442 extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
444 /* True if/when we want to emulate Haifa scheduler in the common code.
445 This is used in sched_rgn_local_init and in various places in
447 int sched_emulate_haifa_p;
449 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
450 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
451 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
452 scheduling window. */
455 /* Current fences. */
458 /* True when separable insns should be scheduled as RHSes. */
459 static bool enable_schedule_as_rhs_p;
461 /* Used in verify_target_availability to assert that target reg is reported
462 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
463 we haven't scheduled anything on the previous fence.
464 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
465 have more conservative value than the one returned by the
466 find_used_regs, thus we shouldn't assert that these values are equal. */
467 static bool scheduled_something_on_previous_fence;
469 /* All newly emitted insns will have their uids greater than this value. */
470 static int first_emitted_uid;
472 /* Set of basic blocks that are forced to start new ebbs. This is a subset
473 of all the ebb heads. */
474 static bitmap_head _forced_ebb_heads;
475 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
477 /* Blocks that need to be rescheduled after pipelining. */
478 bitmap blocks_to_reschedule = NULL;
480 /* True when the first lv set should be ignored when updating liveness. */
481 static bool ignore_first = false;
483 /* Number of insns max_issue has initialized data structures for. */
484 static int max_issue_size = 0;
486 /* Whether we can issue more instructions. */
487 static int can_issue_more;
489 /* Maximum software lookahead window size, reduced when rescheduling after
493 /* Number of insns scheduled in current region. */
494 static int num_insns_scheduled;
496 /* A vector of expressions is used to be able to sort them. */
497 static vec<expr_t> vec_av_set = vNULL;
499 /* A vector of vinsns is used to hold temporary lists of vinsns. */
500 typedef vec<vinsn_t> vinsn_vec_t;
502 /* This vector has the exprs which may still present in av_sets, but actually
503 can't be moved up due to bookkeeping created during code motion to another
504 fence. See comment near the call to update_and_record_unavailable_insns
505 for the detailed explanations. */
506 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = vinsn_vec_t ();
508 /* This vector has vinsns which are scheduled with renaming on the first fence
509 and then seen on the second. For expressions with such vinsns, target
510 availability information may be wrong. */
511 static vinsn_vec_t vec_target_unavailable_vinsns = vinsn_vec_t ();
513 /* Vector to store temporary nops inserted in move_op to prevent removal
515 static vec<insn_t> vec_temp_moveop_nops = vNULL;
517 /* These bitmaps record original instructions scheduled on the current
518 iteration and bookkeeping copies created by them. */
519 static bitmap current_originators = NULL;
520 static bitmap current_copies = NULL;
522 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
523 visit them afterwards. */
524 static bitmap code_motion_visited_blocks = NULL;
526 /* Variables to accumulate different statistics. */
528 /* The number of bookkeeping copies created. */
529 static int stat_bookkeeping_copies;
531 /* The number of insns that required bookkeeiping for their scheduling. */
532 static int stat_insns_needed_bookkeeping;
534 /* The number of insns that got renamed. */
535 static int stat_renamed_scheduled;
537 /* The number of substitutions made during scheduling. */
538 static int stat_substitutions_total;
541 /* Forward declarations of static functions. */
542 static bool rtx_ok_for_substitution_p (rtx, rtx);
543 static int sel_rank_for_schedule (const void *, const void *);
544 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
545 static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax);
547 static rtx get_dest_from_orig_ops (av_set_t);
548 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
549 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
551 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
552 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
553 cmpd_local_params_p, void *);
554 static void sel_sched_region_1 (void);
555 static void sel_sched_region_2 (int);
556 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
558 static void debug_state (state_t);
561 /* Functions that work with fences. */
563 /* Advance one cycle on FENCE. */
565 advance_one_cycle (fence_t fence)
571 advance_state (FENCE_STATE (fence));
572 cycle = ++FENCE_CYCLE (fence);
573 FENCE_ISSUED_INSNS (fence) = 0;
574 FENCE_STARTS_CYCLE_P (fence) = 1;
575 can_issue_more = issue_rate;
576 FENCE_ISSUE_MORE (fence) = can_issue_more;
578 for (i = 0; vec_safe_iterate (FENCE_EXECUTING_INSNS (fence), i, &insn); )
580 if (INSN_READY_CYCLE (insn) < cycle)
582 remove_from_deps (FENCE_DC (fence), insn);
583 FENCE_EXECUTING_INSNS (fence)->unordered_remove (i);
588 if (sched_verbose >= 2)
590 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
591 debug_state (FENCE_STATE (fence));
595 /* Returns true when SUCC in a fallthru bb of INSN, possibly
596 skipping empty basic blocks. */
598 in_fallthru_bb_p (rtx_insn *insn, rtx succ)
600 basic_block bb = BLOCK_FOR_INSN (insn);
603 if (bb == BLOCK_FOR_INSN (succ))
606 e = find_fallthru_edge_from (bb);
612 while (sel_bb_empty_p (bb))
615 return bb == BLOCK_FOR_INSN (succ);
618 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
619 When a successor will continue a ebb, transfer all parameters of a fence
620 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
621 of scheduling helping to distinguish between the old and the new code. */
623 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
626 bool was_here_p = false;
631 fence_t fence = FLIST_FENCE (old_fences);
634 /* Get the only element of FENCE_BNDS (fence). */
635 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
637 gcc_assert (!was_here_p);
640 gcc_assert (was_here_p && insn != NULL_RTX);
642 /* When in the "middle" of the block, just move this fence
644 bb = BLOCK_FOR_INSN (insn);
645 if (! sel_bb_end_p (insn)
646 || (single_succ_p (bb)
647 && single_pred_p (single_succ (bb))))
651 succ = (sel_bb_end_p (insn)
652 ? sel_bb_head (single_succ (bb))
655 if (INSN_SEQNO (succ) > 0
656 && INSN_SEQNO (succ) <= orig_max_seqno
657 && INSN_SCHED_TIMES (succ) <= 0)
659 FENCE_INSN (fence) = succ;
660 move_fence_to_fences (old_fences, new_fences);
662 if (sched_verbose >= 1)
663 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
664 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
669 /* Otherwise copy fence's structures to (possibly) multiple successors. */
670 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
672 int seqno = INSN_SEQNO (succ);
674 if (0 < seqno && seqno <= orig_max_seqno
675 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
677 bool b = (in_same_ebb_p (insn, succ)
678 || in_fallthru_bb_p (insn, succ));
680 if (sched_verbose >= 1)
681 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
682 INSN_UID (insn), INSN_UID (succ),
683 BLOCK_NUM (succ), b ? "continue" : "reset");
686 add_dirty_fence_to_fences (new_fences, succ, fence);
689 /* Mark block of the SUCC as head of the new ebb. */
690 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
691 add_clean_fence_to_fences (new_fences, succ, fence);
698 /* Functions to support substitution. */
700 /* Returns whether INSN with dependence status DS is eligible for
701 substitution, i.e. it's a copy operation x := y, and RHS that is
702 moved up through this insn should be substituted. */
704 can_substitute_through_p (insn_t insn, ds_t ds)
706 /* We can substitute only true dependencies. */
707 if ((ds & DEP_OUTPUT)
710 || ! INSN_LHS (insn))
713 /* Now we just need to make sure the INSN_RHS consists of only one
715 if (REG_P (INSN_LHS (insn))
716 && REG_P (INSN_RHS (insn)))
721 /* Substitute all occurrences of INSN's destination in EXPR' vinsn with INSN's
722 source (if INSN is eligible for substitution). Returns TRUE if
723 substitution was actually performed, FALSE otherwise. Substitution might
724 be not performed because it's either EXPR' vinsn doesn't contain INSN's
725 destination or the resulting insn is invalid for the target machine.
726 When UNDO is true, perform unsubstitution instead (the difference is in
727 the part of rtx on which validate_replace_rtx is called). */
729 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
733 vinsn_t *vi = &EXPR_VINSN (expr);
734 bool has_rhs = VINSN_RHS (*vi) != NULL;
737 /* Do not try to replace in SET_DEST. Although we'll choose new
738 register for the RHS, we don't want to change RHS' original reg.
739 If the insn is not SET, we may still be able to substitute something
740 in it, and if we're here (don't have deps), it doesn't write INSN's
744 : &PATTERN (VINSN_INSN_RTX (*vi)));
745 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
747 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
748 if (rtx_ok_for_substitution_p (old, *where))
753 /* We should copy these rtxes before substitution. */
754 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
755 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
757 /* Where we'll replace.
758 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
759 used instead of SET_SRC. */
760 where_replace = (has_rhs
761 ? &SET_SRC (PATTERN (new_insn))
762 : &PATTERN (new_insn));
765 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
768 /* ??? Actually, constrain_operands result depends upon choice of
769 destination register. E.g. if we allow single register to be an rhs,
770 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
771 in invalid insn dx=dx, so we'll loose this rhs here.
772 Just can't come up with significant testcase for this, so just
773 leaving it for now. */
776 change_vinsn_in_expr (expr,
777 create_vinsn_from_insn_rtx (new_insn, false));
779 /* Do not allow clobbering the address register of speculative
781 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
782 && register_unavailable_p (VINSN_REG_USES (EXPR_VINSN (expr)),
783 expr_dest_reg (expr)))
784 EXPR_TARGET_AVAILABLE (expr) = false;
795 /* Return the number of places WHAT appears within WHERE.
796 Bail out when we found a reference occupying several hard registers. */
798 count_occurrences_equiv (const_rtx what, const_rtx where)
801 subrtx_iterator::array_type array;
802 FOR_EACH_SUBRTX (iter, array, where, NONCONST)
805 if (REG_P (x) && REGNO (x) == REGNO (what))
807 /* Bail out if mode is different or more than one register is
809 if (GET_MODE (x) != GET_MODE (what) || REG_NREGS (x) > 1)
813 else if (GET_CODE (x) == SUBREG
814 && (!REG_P (SUBREG_REG (x))
815 || REGNO (SUBREG_REG (x)) == REGNO (what)))
816 /* ??? Do not support substituting regs inside subregs. In that case,
817 simplify_subreg will be called by validate_replace_rtx, and
818 unsubstitution will fail later. */
824 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
826 rtx_ok_for_substitution_p (rtx what, rtx where)
828 return (count_occurrences_equiv (what, where) > 0);
832 /* Functions to support register renaming. */
834 /* Substitute VI's set source with REGNO. Returns newly created pattern
835 that has REGNO as its source. */
837 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
843 lhs_rtx = copy_rtx (VINSN_LHS (vi));
845 pattern = gen_rtx_SET (lhs_rtx, rhs_rtx);
846 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
851 /* Returns whether INSN's src can be replaced with register number
852 NEW_SRC_REG. E.g. the following insn is valid for i386:
854 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
855 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
856 (reg:SI 0 ax [orig:770 c1 ] [770]))
857 (const_int 288 [0x120])) [0 str S1 A8])
858 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
861 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
862 because of operand constraints:
864 (define_insn "*movqi_1"
865 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
866 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
869 So do constrain_operands here, before choosing NEW_SRC_REG as best
873 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
875 vinsn_t vi = INSN_VINSN (insn);
880 gcc_assert (VINSN_SEPARABLE_P (vi));
882 get_dest_and_mode (insn, &dst_loc, &mode);
883 gcc_assert (mode == GET_MODE (new_src_reg));
885 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
888 /* See whether SET_SRC can be replaced with this register. */
889 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
890 res = verify_changes (0);
896 /* Returns whether INSN still be valid after replacing it's DEST with
899 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
901 vinsn_t vi = INSN_VINSN (insn);
904 /* We should deal here only with separable insns. */
905 gcc_assert (VINSN_SEPARABLE_P (vi));
906 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
908 /* See whether SET_DEST can be replaced with this register. */
909 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
910 res = verify_changes (0);
916 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
918 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
924 rhs_rtx = copy_rtx (VINSN_RHS (vi));
926 pattern = gen_rtx_SET (lhs_rtx, rhs_rtx);
927 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
932 /* Substitute lhs in the given expression EXPR for the register with number
933 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
935 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
940 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
941 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
943 change_vinsn_in_expr (expr, vinsn);
944 EXPR_WAS_RENAMED (expr) = 1;
945 EXPR_TARGET_AVAILABLE (expr) = 1;
948 /* Returns whether VI writes either one of the USED_REGS registers or,
949 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
951 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
952 HARD_REG_SET unavailable_hard_regs)
955 reg_set_iterator rsi;
957 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
959 if (REGNO_REG_SET_P (used_regs, regno))
961 if (HARD_REGISTER_NUM_P (regno)
962 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
966 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
968 if (REGNO_REG_SET_P (used_regs, regno))
970 if (HARD_REGISTER_NUM_P (regno)
971 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
978 /* Returns register class of the output register in INSN.
979 Returns NO_REGS for call insns because some targets have constraints on
980 destination register of a call insn.
982 Code adopted from regrename.c::build_def_use. */
983 static enum reg_class
984 get_reg_class (rtx_insn *insn)
988 extract_constrain_insn (insn);
989 preprocess_constraints (insn);
990 n_ops = recog_data.n_operands;
992 const operand_alternative *op_alt = which_op_alt ();
993 if (asm_noperands (PATTERN (insn)) > 0)
995 for (i = 0; i < n_ops; i++)
996 if (recog_data.operand_type[i] == OP_OUT)
998 rtx *loc = recog_data.operand_loc[i];
1000 enum reg_class cl = alternative_class (op_alt, i);
1003 && REGNO (op) == ORIGINAL_REGNO (op))
1009 else if (!CALL_P (insn))
1011 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1013 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1014 enum reg_class cl = alternative_class (op_alt, opn);
1016 if (recog_data.operand_type[opn] == OP_OUT ||
1017 recog_data.operand_type[opn] == OP_INOUT)
1023 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1024 may result in returning NO_REGS, cause flags is written implicitly through
1025 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1029 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1031 init_hard_regno_rename (int regno)
1035 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1037 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1039 /* We are not interested in renaming in other regs. */
1040 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1043 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1044 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1048 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1051 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1053 /* Check whether this is all calculated. */
1054 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1055 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1057 init_hard_regno_rename (from);
1059 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1062 /* Calculate set of registers that are capable of holding MODE. */
1064 init_regs_for_mode (machine_mode mode)
1068 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1069 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1071 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1076 /* See whether it accepts all modes that occur in
1078 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1081 nregs = hard_regno_nregs[cur_reg][mode];
1083 for (i = nregs - 1; i >= 0; --i)
1084 if (fixed_regs[cur_reg + i]
1085 || global_regs[cur_reg + i]
1086 /* Can't use regs which aren't saved by
1088 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1089 /* Can't use regs with non-null REG_BASE_VALUE, because adjusting
1090 it affects aliasing globally and invalidates all AV sets. */
1091 || get_reg_base_value (cur_reg + i)
1092 #ifdef LEAF_REGISTERS
1093 /* We can't use a non-leaf register if we're in a
1096 && !LEAF_REGISTERS[cur_reg + i])
1104 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1105 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1108 /* If the CUR_REG passed all the checks above,
1110 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1113 sel_hrd.regs_for_mode_ok[mode] = true;
1116 /* Init all register sets gathered in HRD. */
1118 init_hard_regs_data (void)
1123 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1124 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1125 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1126 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1128 /* Initialize registers that are valid based on mode when this is
1130 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1131 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1133 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1134 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1135 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1138 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1140 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1141 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1145 /* Mark hardware regs in REG_RENAME_P that are not suitable
1146 for renaming rhs in INSN due to hardware restrictions (register class,
1147 modes compatibility etc). This doesn't affect original insn's dest reg,
1148 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1149 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1150 Registers that are in used_regs are always marked in
1151 unavailable_hard_regs as well. */
1154 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1155 regset used_regs ATTRIBUTE_UNUSED)
1158 enum reg_class cl = NO_REGS;
1160 unsigned cur_reg, regno;
1161 hard_reg_set_iterator hrsi;
1163 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1164 gcc_assert (reg_rename_p);
1166 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1168 /* We have decided not to rename 'mem = something;' insns, as 'something'
1169 is usually a register. */
1170 if (!REG_P (orig_dest))
1173 regno = REGNO (orig_dest);
1175 /* If before reload, don't try to work with pseudos. */
1176 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1179 if (reload_completed)
1180 cl = get_reg_class (def->orig_insn);
1182 /* Stop if the original register is one of the fixed_regs, global_regs or
1183 frame pointer, or we could not discover its class. */
1184 if (fixed_regs[regno]
1185 || global_regs[regno]
1186 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed
1187 && regno == HARD_FRAME_POINTER_REGNUM)
1188 || (HARD_FRAME_POINTER_REGNUM && frame_pointer_needed
1189 && regno == FRAME_POINTER_REGNUM)
1190 || (reload_completed && cl == NO_REGS))
1192 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1194 /* Give a chance for original register, if it isn't in used_regs. */
1195 if (!def->crosses_call)
1196 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1201 /* If something allocated on stack in this function, mark frame pointer
1202 register unavailable, considering also modes.
1203 FIXME: it is enough to do this once per all original defs. */
1204 if (frame_pointer_needed)
1206 add_to_hard_reg_set (®_rename_p->unavailable_hard_regs,
1207 Pmode, FRAME_POINTER_REGNUM);
1209 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER)
1210 add_to_hard_reg_set (®_rename_p->unavailable_hard_regs,
1211 Pmode, HARD_FRAME_POINTER_REGNUM);
1215 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1216 is equivalent to as if all stack regs were in this set.
1217 I.e. no stack register can be renamed, and even if it's an original
1218 register here we make sure it won't be lifted over it's previous def
1219 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1220 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1221 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1222 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1223 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1224 sel_hrd.stack_regs);
1227 /* If there's a call on this path, make regs from call_used_reg_set
1229 if (def->crosses_call)
1230 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1233 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1234 but not register classes. */
1235 if (!reload_completed)
1238 /* Leave regs as 'available' only from the current
1240 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1241 reg_class_contents[cl]);
1243 mode = GET_MODE (orig_dest);
1245 /* Leave only registers available for this mode. */
1246 if (!sel_hrd.regs_for_mode_ok[mode])
1247 init_regs_for_mode (mode);
1248 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1249 sel_hrd.regs_for_mode[mode]);
1251 /* Exclude registers that are partially call clobbered. */
1252 if (def->crosses_call
1253 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1254 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1255 sel_hrd.regs_for_call_clobbered[mode]);
1257 /* Leave only those that are ok to rename. */
1258 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1264 nregs = hard_regno_nregs[cur_reg][mode];
1265 gcc_assert (nregs > 0);
1267 for (i = nregs - 1; i >= 0; --i)
1268 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1272 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1276 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1277 reg_rename_p->unavailable_hard_regs);
1279 /* Regno is always ok from the renaming part of view, but it really
1280 could be in *unavailable_hard_regs already, so set it here instead
1282 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1285 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1286 best register more recently than REG2. */
1287 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1289 /* Indicates the number of times renaming happened before the current one. */
1290 static int reg_rename_this_tick;
1292 /* Choose the register among free, that is suitable for storing
1295 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1296 originally appears. There could be multiple original operations
1297 for single rhs since we moving it up and merging along different
1300 Some code is adapted from regrename.c (regrename_optimize).
1301 If original register is available, function returns it.
1302 Otherwise it performs the checks, so the new register should
1303 comply with the following:
1304 - it should not violate any live ranges (such registers are in
1305 REG_RENAME_P->available_for_renaming set);
1306 - it should not be in the HARD_REGS_USED regset;
1307 - it should be in the class compatible with original uses;
1308 - it should not be clobbered through reference with different mode;
1309 - if we're in the leaf function, then the new register should
1310 not be in the LEAF_REGISTERS;
1313 If several registers meet the conditions, the register with smallest
1314 tick is returned to achieve more even register allocation.
1316 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1318 If no register satisfies the above conditions, NULL_RTX is returned. */
1320 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1321 struct reg_rename *reg_rename_p,
1322 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1326 machine_mode mode = VOIDmode;
1327 unsigned regno, i, n;
1328 hard_reg_set_iterator hrsi;
1329 def_list_iterator di;
1332 /* If original register is available, return it. */
1333 *is_orig_reg_p_ptr = true;
1335 FOR_EACH_DEF (def, di, original_insns)
1337 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1339 gcc_assert (REG_P (orig_dest));
1341 /* Check that all original operations have the same mode.
1342 This is done for the next loop; if we'd return from this
1343 loop, we'd check only part of them, but in this case
1344 it doesn't matter. */
1345 if (mode == VOIDmode)
1346 mode = GET_MODE (orig_dest);
1347 gcc_assert (mode == GET_MODE (orig_dest));
1349 regno = REGNO (orig_dest);
1350 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1351 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1354 /* All hard registers are available. */
1357 gcc_assert (mode != VOIDmode);
1359 /* Hard registers should not be shared. */
1360 return gen_rtx_REG (mode, regno);
1364 *is_orig_reg_p_ptr = false;
1367 /* Among all available regs choose the register that was
1368 allocated earliest. */
1369 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1371 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1373 /* Check that all hard regs for mode are available. */
1374 for (i = 1, n = hard_regno_nregs[cur_reg][mode]; i < n; i++)
1375 if (TEST_HARD_REG_BIT (hard_regs_used, cur_reg + i)
1376 || !TEST_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1383 /* All hard registers are available. */
1384 if (best_new_reg < 0
1385 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1387 best_new_reg = cur_reg;
1389 /* Return immediately when we know there's no better reg. */
1390 if (! reg_rename_tick[best_new_reg])
1395 if (best_new_reg >= 0)
1397 /* Use the check from the above loop. */
1398 gcc_assert (mode != VOIDmode);
1399 return gen_rtx_REG (mode, best_new_reg);
1405 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1406 assumptions about available registers in the function. */
1408 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1409 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1411 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1412 original_insns, is_orig_reg_p_ptr);
1414 /* FIXME loop over hard_regno_nregs here. */
1415 gcc_assert (best_reg == NULL_RTX
1416 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1421 /* Choose the pseudo register for storing rhs value. As this is supposed
1422 to work before reload, we return either the original register or make
1423 the new one. The parameters are the same that in choose_nest_reg_1
1424 functions, except that USED_REGS may contain pseudos.
1425 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1427 TODO: take into account register pressure while doing this. Up to this
1428 moment, this function would never return NULL for pseudos, but we should
1429 not rely on this. */
1431 choose_best_pseudo_reg (regset used_regs,
1432 struct reg_rename *reg_rename_p,
1433 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1435 def_list_iterator i;
1437 machine_mode mode = VOIDmode;
1438 bool bad_hard_regs = false;
1440 /* We should not use this after reload. */
1441 gcc_assert (!reload_completed);
1443 /* If original register is available, return it. */
1444 *is_orig_reg_p_ptr = true;
1446 FOR_EACH_DEF (def, i, original_insns)
1448 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1451 gcc_assert (REG_P (dest));
1453 /* Check that all original operations have the same mode. */
1454 if (mode == VOIDmode)
1455 mode = GET_MODE (dest);
1457 gcc_assert (mode == GET_MODE (dest));
1458 orig_regno = REGNO (dest);
1460 /* Check that nothing in used_regs intersects with orig_regno. When
1461 we have a hard reg here, still loop over hard_regno_nregs. */
1462 if (HARD_REGISTER_NUM_P (orig_regno))
1465 for (j = 0, n = hard_regno_nregs[orig_regno][mode]; j < n; j++)
1466 if (REGNO_REG_SET_P (used_regs, orig_regno + j))
1473 if (REGNO_REG_SET_P (used_regs, orig_regno))
1476 if (HARD_REGISTER_NUM_P (orig_regno))
1478 gcc_assert (df_regs_ever_live_p (orig_regno));
1480 /* For hard registers, we have to check hardware imposed
1481 limitations (frame/stack registers, calls crossed). */
1482 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1485 /* Don't let register cross a call if it doesn't already
1486 cross one. This condition is written in accordance with
1487 that in sched-deps.c sched_analyze_reg(). */
1488 if (!reg_rename_p->crosses_call
1489 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1490 return gen_rtx_REG (mode, orig_regno);
1493 bad_hard_regs = true;
1499 *is_orig_reg_p_ptr = false;
1501 /* We had some original hard registers that couldn't be used.
1502 Those were likely special. Don't try to create a pseudo. */
1506 /* We haven't found a register from original operations. Get a new one.
1507 FIXME: control register pressure somehow. */
1509 rtx new_reg = gen_reg_rtx (mode);
1511 gcc_assert (mode != VOIDmode);
1513 max_regno = max_reg_num ();
1514 maybe_extend_reg_info_p ();
1515 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1521 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1522 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1524 verify_target_availability (expr_t expr, regset used_regs,
1525 struct reg_rename *reg_rename_p)
1527 unsigned n, i, regno;
1529 bool target_available, live_available, hard_available;
1531 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1534 regno = expr_dest_regno (expr);
1535 mode = GET_MODE (EXPR_LHS (expr));
1536 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1537 n = HARD_REGISTER_NUM_P (regno) ? hard_regno_nregs[regno][mode] : 1;
1539 live_available = hard_available = true;
1540 for (i = 0; i < n; i++)
1542 if (bitmap_bit_p (used_regs, regno + i))
1543 live_available = false;
1544 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1545 hard_available = false;
1548 /* When target is not available, it may be due to hard register
1549 restrictions, e.g. crosses calls, so we check hard_available too. */
1550 if (target_available)
1551 gcc_assert (live_available);
1553 /* Check only if we haven't scheduled something on the previous fence,
1554 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1555 and having more than one fence, we may end having targ_un in a block
1556 in which successors target register is actually available.
1558 The last condition handles the case when a dependence from a call insn
1559 was created in sched-deps.c for insns with destination registers that
1560 never crossed a call before, but do cross one after our code motion.
1562 FIXME: in the latter case, we just uselessly called find_used_regs,
1563 because we can't move this expression with any other register
1565 gcc_assert (scheduled_something_on_previous_fence || !live_available
1567 || (!reload_completed && reg_rename_p->crosses_call
1568 && REG_N_CALLS_CROSSED (regno) == 0));
1571 /* Collect unavailable registers due to liveness for EXPR from BNDS
1572 into USED_REGS. Save additional information about available
1573 registers and unavailable due to hardware restriction registers
1574 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1577 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1578 struct reg_rename *reg_rename_p,
1579 def_list_t *original_insns)
1581 for (; bnds; bnds = BLIST_NEXT (bnds))
1584 av_set_t orig_ops = NULL;
1585 bnd_t bnd = BLIST_BND (bnds);
1587 /* If the chosen best expr doesn't belong to current boundary,
1589 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1592 /* Put in ORIG_OPS all exprs from this boundary that became
1594 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1596 /* Compute used regs and OR it into the USED_REGS. */
1597 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1598 reg_rename_p, original_insns);
1600 /* FIXME: the assert is true until we'd have several boundaries. */
1602 av_set_clear (&orig_ops);
1606 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1607 If BEST_REG is valid, replace LHS of EXPR with it. */
1609 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1611 /* Try whether we'll be able to generate the insn
1612 'dest := best_reg' at the place of the original operation. */
1613 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1615 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1617 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1619 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1620 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1621 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1625 /* Make sure that EXPR has the right destination
1627 if (expr_dest_regno (expr) != REGNO (best_reg))
1628 replace_dest_with_reg_in_expr (expr, best_reg);
1630 EXPR_TARGET_AVAILABLE (expr) = 1;
1635 /* Select and assign best register to EXPR searching from BNDS.
1636 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1637 Return FALSE if no register can be chosen, which could happen when:
1638 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1639 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1640 that are used on the moving path. */
1642 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1644 static struct reg_rename reg_rename_data;
1647 def_list_t original_insns = NULL;
1650 *is_orig_reg_p = false;
1652 /* Don't bother to do anything if this insn doesn't set any registers. */
1653 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1654 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1657 used_regs = get_clear_regset_from_pool ();
1658 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1660 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data,
1663 /* If after reload, make sure we're working with hard regs here. */
1664 if (flag_checking && reload_completed)
1666 reg_set_iterator rsi;
1669 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1673 if (EXPR_SEPARABLE_P (expr))
1675 rtx best_reg = NULL_RTX;
1676 /* Check that we have computed availability of a target register
1678 verify_target_availability (expr, used_regs, ®_rename_data);
1680 /* Turn everything in hard regs after reload. */
1681 if (reload_completed)
1683 HARD_REG_SET hard_regs_used;
1684 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1686 /* Join hard registers unavailable due to register class
1687 restrictions and live range intersection. */
1688 IOR_HARD_REG_SET (hard_regs_used,
1689 reg_rename_data.unavailable_hard_regs);
1691 best_reg = choose_best_reg (hard_regs_used, ®_rename_data,
1692 original_insns, is_orig_reg_p);
1695 best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data,
1696 original_insns, is_orig_reg_p);
1700 else if (*is_orig_reg_p)
1702 /* In case of unification BEST_REG may be different from EXPR's LHS
1703 when EXPR's LHS is unavailable, and there is another LHS among
1705 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1709 /* Forbid renaming of low-cost insns. */
1710 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1713 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1718 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1719 any of the HARD_REGS_USED set. */
1720 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1721 reg_rename_data.unavailable_hard_regs))
1724 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1729 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1733 ilist_clear (&original_insns);
1734 return_regset_to_pool (used_regs);
1740 /* Return true if dependence described by DS can be overcomed. */
1742 can_speculate_dep_p (ds_t ds)
1744 if (spec_info == NULL)
1747 /* Leave only speculative data. */
1754 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1755 that we can overcome. */
1756 ds_t spec_mask = spec_info->mask;
1758 if ((ds & spec_mask) != ds)
1762 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1768 /* Get a speculation check instruction.
1769 C_EXPR is a speculative expression,
1770 CHECK_DS describes speculations that should be checked,
1771 ORIG_INSN is the original non-speculative insn in the stream. */
1773 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1778 basic_block recovery_block;
1781 /* Create a recovery block if target is going to emit branchy check, or if
1782 ORIG_INSN was speculative already. */
1783 if (targetm.sched.needs_block_p (check_ds)
1784 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1786 recovery_block = sel_create_recovery_block (orig_insn);
1787 label = BB_HEAD (recovery_block);
1791 recovery_block = NULL;
1795 /* Get pattern of the check. */
1796 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1799 gcc_assert (check_pattern != NULL);
1802 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1804 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1805 INSN_SEQNO (orig_insn), orig_insn);
1807 /* Make check to be non-speculative. */
1808 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1809 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1811 /* Decrease priority of check by difference of load/check instruction
1813 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1814 - sel_vinsn_cost (INSN_VINSN (insn)));
1816 /* Emit copy of original insn (though with replaced target register,
1817 if needed) to the recovery block. */
1818 if (recovery_block != NULL)
1822 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1823 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1824 sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1825 INSN_EXPR (orig_insn),
1827 bb_note (recovery_block));
1830 /* If we've generated a data speculation check, make sure
1831 that all the bookkeeping instruction we'll create during
1832 this move_op () will allocate an ALAT entry so that the
1834 In case of control speculation we must convert C_EXPR to control
1835 speculative mode, because failing to do so will bring us an exception
1836 thrown by the non-control-speculative load. */
1837 check_ds = ds_get_max_dep_weak (check_ds);
1838 speculate_expr (c_expr, check_ds);
1843 /* True when INSN is a "regN = regN" copy. */
1845 identical_copy_p (rtx_insn *insn)
1849 pat = PATTERN (insn);
1851 if (GET_CODE (pat) != SET)
1854 lhs = SET_DEST (pat);
1858 rhs = SET_SRC (pat);
1862 return REGNO (lhs) == REGNO (rhs);
1865 /* Undo all transformations on *AV_PTR that were done when
1866 moving through INSN. */
1868 undo_transformations (av_set_t *av_ptr, rtx_insn *insn)
1870 av_set_iterator av_iter;
1872 av_set_t new_set = NULL;
1874 /* First, kill any EXPR that uses registers set by an insn. This is
1875 required for correctness. */
1876 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1877 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1878 && bitmap_intersect_p (INSN_REG_SETS (insn),
1879 VINSN_REG_USES (EXPR_VINSN (expr)))
1880 /* When an insn looks like 'r1 = r1', we could substitute through
1881 it, but the above condition will still hold. This happened with
1882 gcc.c-torture/execute/961125-1.c. */
1883 && !identical_copy_p (insn))
1885 if (sched_verbose >= 6)
1886 sel_print ("Expr %d removed due to use/set conflict\n",
1887 INSN_UID (EXPR_INSN_RTX (expr)));
1888 av_set_iter_remove (&av_iter);
1891 /* Undo transformations looking at the history vector. */
1892 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1894 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1895 insn, EXPR_VINSN (expr), true);
1899 expr_history_def *phist;
1901 phist = &EXPR_HISTORY_OF_CHANGES (expr)[index];
1903 switch (phist->type)
1905 case TRANS_SPECULATION:
1907 ds_t old_ds, new_ds;
1909 /* Compute the difference between old and new speculative
1910 statuses: that's what we need to check.
1911 Earlier we used to assert that the status will really
1912 change. This no longer works because only the probability
1913 bits in the status may have changed during compute_av_set,
1914 and in the case of merging different probabilities of the
1915 same speculative status along different paths we do not
1916 record this in the history vector. */
1917 old_ds = phist->spec_ds;
1918 new_ds = EXPR_SPEC_DONE_DS (expr);
1920 old_ds &= SPECULATIVE;
1921 new_ds &= SPECULATIVE;
1924 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1927 case TRANS_SUBSTITUTION:
1929 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1933 new_vi = phist->old_expr_vinsn;
1935 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1936 == EXPR_SEPARABLE_P (expr));
1937 copy_expr (tmp_expr, expr);
1939 if (vinsn_equal_p (phist->new_expr_vinsn,
1940 EXPR_VINSN (tmp_expr)))
1941 change_vinsn_in_expr (tmp_expr, new_vi);
1943 /* This happens when we're unsubstituting on a bookkeeping
1944 copy, which was in turn substituted. The history is wrong
1945 in this case. Do it the hard way. */
1946 add = substitute_reg_in_expr (tmp_expr, insn, true);
1948 av_set_add (&new_set, tmp_expr);
1949 clear_expr (tmp_expr);
1959 av_set_union_and_clear (av_ptr, &new_set, NULL);
1963 /* Moveup_* helpers for code motion and computing av sets. */
1965 /* Propagates EXPR inside an insn group through THROUGH_INSN.
1966 The difference from the below function is that only substitution is
1968 static enum MOVEUP_EXPR_CODE
1969 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
1971 vinsn_t vi = EXPR_VINSN (expr);
1975 /* Do this only inside insn group. */
1976 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
1978 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
1980 return MOVEUP_EXPR_SAME;
1982 /* Substitution is the possible choice in this case. */
1983 if (has_dep_p[DEPS_IN_RHS])
1985 /* Can't substitute UNIQUE VINSNs. */
1986 gcc_assert (!VINSN_UNIQUE_P (vi));
1988 if (can_substitute_through_p (through_insn,
1989 has_dep_p[DEPS_IN_RHS])
1990 && substitute_reg_in_expr (expr, through_insn, false))
1992 EXPR_WAS_SUBSTITUTED (expr) = true;
1993 return MOVEUP_EXPR_CHANGED;
1996 /* Don't care about this, as even true dependencies may be allowed
1997 in an insn group. */
1998 return MOVEUP_EXPR_SAME;
2001 /* This can catch output dependencies in COND_EXECs. */
2002 if (has_dep_p[DEPS_IN_INSN])
2003 return MOVEUP_EXPR_NULL;
2005 /* This is either an output or an anti dependence, which usually have
2006 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2008 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2009 return MOVEUP_EXPR_AS_RHS;
2012 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2013 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2014 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2015 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2016 && !sel_insn_is_speculation_check (through_insn))
2018 /* True when a conflict on a target register was found during moveup_expr. */
2019 static bool was_target_conflict = false;
2021 /* Return true when moving a debug INSN across THROUGH_INSN will
2022 create a bookkeeping block. We don't want to create such blocks,
2023 for they would cause codegen differences between compilations with
2024 and without debug info. */
2027 moving_insn_creates_bookkeeping_block_p (insn_t insn,
2028 insn_t through_insn)
2030 basic_block bbi, bbt;
2032 edge_iterator ei1, ei2;
2034 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn))
2036 if (sched_verbose >= 9)
2037 sel_print ("no bookkeeping required: ");
2041 bbi = BLOCK_FOR_INSN (insn);
2043 if (EDGE_COUNT (bbi->preds) == 1)
2045 if (sched_verbose >= 9)
2046 sel_print ("only one pred edge: ");
2050 bbt = BLOCK_FOR_INSN (through_insn);
2052 FOR_EACH_EDGE (e1, ei1, bbt->succs)
2054 FOR_EACH_EDGE (e2, ei2, bbi->preds)
2056 if (find_block_for_bookkeeping (e1, e2, TRUE))
2058 if (sched_verbose >= 9)
2059 sel_print ("found existing block: ");
2065 if (sched_verbose >= 9)
2066 sel_print ("would create bookkeeping block: ");
2071 /* Return true when the conflict with newly created implicit clobbers
2072 between EXPR and THROUGH_INSN is found because of renaming. */
2074 implicit_clobber_conflict_p (insn_t through_insn, expr_t expr)
2079 hard_reg_set_iterator hrsi;
2083 /* Make a new pseudo register. */
2084 reg = gen_reg_rtx (GET_MODE (EXPR_LHS (expr)));
2085 max_regno = max_reg_num ();
2086 maybe_extend_reg_info_p ();
2088 /* Validate a change and bail out early. */
2089 insn = EXPR_INSN_RTX (expr);
2090 validate_change (insn, &SET_DEST (PATTERN (insn)), reg, true);
2091 valid = verify_changes (0);
2095 if (sched_verbose >= 6)
2096 sel_print ("implicit clobbers failed validation, ");
2100 /* Make a new insn with it. */
2101 rhs = copy_rtx (VINSN_RHS (EXPR_VINSN (expr)));
2102 pat = gen_rtx_SET (reg, rhs);
2104 insn = emit_insn (pat);
2107 /* Calculate implicit clobbers. */
2108 extract_insn (insn);
2109 preprocess_constraints (insn);
2110 alternative_mask prefrred = get_preferred_alternatives (insn);
2111 ira_implicitly_set_insn_hard_regs (&temp, prefrred);
2112 AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs);
2114 /* If any implicit clobber registers intersect with regular ones in
2115 through_insn, we have a dependency and thus bail out. */
2116 EXECUTE_IF_SET_IN_HARD_REG_SET (temp, 0, regno, hrsi)
2118 vinsn_t vi = INSN_VINSN (through_insn);
2119 if (bitmap_bit_p (VINSN_REG_SETS (vi), regno)
2120 || bitmap_bit_p (VINSN_REG_CLOBBERS (vi), regno)
2121 || bitmap_bit_p (VINSN_REG_USES (vi), regno))
2128 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2129 performing necessary transformations. Record the type of transformation
2130 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2131 permit all dependencies except true ones, and try to remove those
2132 too via forward substitution. All cases when a non-eliminable
2133 non-zero cost dependency exists inside an insn group will be fixed
2134 in tick_check_p instead. */
2135 static enum MOVEUP_EXPR_CODE
2136 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2137 enum local_trans_type *ptrans_type)
2139 vinsn_t vi = EXPR_VINSN (expr);
2140 insn_t insn = VINSN_INSN_RTX (vi);
2141 bool was_changed = false;
2142 bool as_rhs = false;
2146 /* ??? We use dependencies of non-debug insns on debug insns to
2147 indicate that the debug insns need to be reset if the non-debug
2148 insn is pulled ahead of it. It's hard to figure out how to
2149 introduce such a notion in sel-sched, but it already fails to
2150 support debug insns in other ways, so we just go ahead and
2151 let the deug insns go corrupt for now. */
2152 if (DEBUG_INSN_P (through_insn) && !DEBUG_INSN_P (insn))
2153 return MOVEUP_EXPR_SAME;
2155 /* When inside_insn_group, delegate to the helper. */
2156 if (inside_insn_group)
2157 return moveup_expr_inside_insn_group (expr, through_insn);
2159 /* Deal with unique insns and control dependencies. */
2160 if (VINSN_UNIQUE_P (vi))
2162 /* We can move jumps without side-effects or jumps that are
2163 mutually exclusive with instruction THROUGH_INSN (all in cases
2164 dependencies allow to do so and jump is not speculative). */
2165 if (control_flow_insn_p (insn))
2167 basic_block fallthru_bb;
2169 /* Do not move checks and do not move jumps through other
2171 if (control_flow_insn_p (through_insn)
2172 || sel_insn_is_speculation_check (insn))
2173 return MOVEUP_EXPR_NULL;
2175 /* Don't move jumps through CFG joins. */
2176 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2177 return MOVEUP_EXPR_NULL;
2179 /* The jump should have a clear fallthru block, and
2180 this block should be in the current region. */
2181 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2182 || ! in_current_region_p (fallthru_bb))
2183 return MOVEUP_EXPR_NULL;
2185 /* And it should be mutually exclusive with through_insn. */
2186 if (! sched_insns_conditions_mutex_p (insn, through_insn)
2187 && ! DEBUG_INSN_P (through_insn))
2188 return MOVEUP_EXPR_NULL;
2191 /* Don't move what we can't move. */
2192 if (EXPR_CANT_MOVE (expr)
2193 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2194 return MOVEUP_EXPR_NULL;
2196 /* Don't move SCHED_GROUP instruction through anything.
2197 If we don't force this, then it will be possible to start
2198 scheduling a sched_group before all its dependencies are
2200 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2201 as late as possible through rank_for_schedule. */
2202 if (SCHED_GROUP_P (insn))
2203 return MOVEUP_EXPR_NULL;
2206 gcc_assert (!control_flow_insn_p (insn));
2208 /* Don't move debug insns if this would require bookkeeping. */
2209 if (DEBUG_INSN_P (insn)
2210 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)
2211 && moving_insn_creates_bookkeeping_block_p (insn, through_insn))
2212 return MOVEUP_EXPR_NULL;
2214 /* Deal with data dependencies. */
2215 was_target_conflict = false;
2216 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2219 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2220 return MOVEUP_EXPR_SAME;
2224 /* We can move UNIQUE insn up only as a whole and unchanged,
2225 so it shouldn't have any dependencies. */
2226 if (VINSN_UNIQUE_P (vi))
2227 return MOVEUP_EXPR_NULL;
2230 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2234 res = speculate_expr (expr, full_ds);
2237 /* Speculation was successful. */
2239 was_changed = (res > 0);
2241 was_target_conflict = true;
2243 *ptrans_type = TRANS_SPECULATION;
2244 sel_clear_has_dependence ();
2248 if (has_dep_p[DEPS_IN_INSN])
2249 /* We have some dependency that cannot be discarded. */
2250 return MOVEUP_EXPR_NULL;
2252 if (has_dep_p[DEPS_IN_LHS])
2254 /* Only separable insns can be moved up with the new register.
2255 Anyways, we should mark that the original register is
2257 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2258 return MOVEUP_EXPR_NULL;
2260 /* When renaming a hard register to a pseudo before reload, extra
2261 dependencies can occur from the implicit clobbers of the insn.
2262 Filter out such cases here. */
2263 if (!reload_completed && REG_P (EXPR_LHS (expr))
2264 && HARD_REGISTER_P (EXPR_LHS (expr))
2265 && implicit_clobber_conflict_p (through_insn, expr))
2267 if (sched_verbose >= 6)
2268 sel_print ("implicit clobbers conflict detected, ");
2269 return MOVEUP_EXPR_NULL;
2271 EXPR_TARGET_AVAILABLE (expr) = false;
2272 was_target_conflict = true;
2276 /* At this point we have either separable insns, that will be lifted
2277 up only as RHSes, or non-separable insns with no dependency in lhs.
2278 If dependency is in RHS, then try to perform substitution and move up
2285 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2286 moved above y=x assignment as z=x*2.
2288 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2289 side can be moved because of the output dependency. The operation was
2290 cropped to its rhs above. */
2291 if (has_dep_p[DEPS_IN_RHS])
2293 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2295 /* Can't substitute UNIQUE VINSNs. */
2296 gcc_assert (!VINSN_UNIQUE_P (vi));
2298 if (can_speculate_dep_p (*rhs_dsp))
2302 res = speculate_expr (expr, *rhs_dsp);
2305 /* Speculation was successful. */
2307 was_changed = (res > 0);
2309 was_target_conflict = true;
2311 *ptrans_type = TRANS_SPECULATION;
2314 return MOVEUP_EXPR_NULL;
2316 else if (can_substitute_through_p (through_insn,
2318 && substitute_reg_in_expr (expr, through_insn, false))
2320 /* ??? We cannot perform substitution AND speculation on the same
2322 gcc_assert (!was_changed);
2325 *ptrans_type = TRANS_SUBSTITUTION;
2326 EXPR_WAS_SUBSTITUTED (expr) = true;
2329 return MOVEUP_EXPR_NULL;
2332 /* Don't move trapping insns through jumps.
2333 This check should be at the end to give a chance to control speculation
2334 to perform its duties. */
2335 if (CANT_MOVE_TRAPPING (expr, through_insn))
2336 return MOVEUP_EXPR_NULL;
2339 ? MOVEUP_EXPR_CHANGED
2341 ? MOVEUP_EXPR_AS_RHS
2342 : MOVEUP_EXPR_SAME));
2345 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2346 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2347 that can exist within a parallel group. Write to RES the resulting
2348 code for moveup_expr. */
2350 try_bitmap_cache (expr_t expr, insn_t insn,
2351 bool inside_insn_group,
2352 enum MOVEUP_EXPR_CODE *res)
2354 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2356 /* First check whether we've analyzed this situation already. */
2357 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2359 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2361 if (sched_verbose >= 6)
2362 sel_print ("removed (cached)\n");
2363 *res = MOVEUP_EXPR_NULL;
2368 if (sched_verbose >= 6)
2369 sel_print ("unchanged (cached)\n");
2370 *res = MOVEUP_EXPR_SAME;
2374 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2376 if (inside_insn_group)
2378 if (sched_verbose >= 6)
2379 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2380 *res = MOVEUP_EXPR_SAME;
2385 EXPR_TARGET_AVAILABLE (expr) = false;
2387 /* This is the only case when propagation result can change over time,
2388 as we can dynamically switch off scheduling as RHS. In this case,
2389 just check the flag to reach the correct decision. */
2390 if (enable_schedule_as_rhs_p)
2392 if (sched_verbose >= 6)
2393 sel_print ("unchanged (as RHS, cached)\n");
2394 *res = MOVEUP_EXPR_AS_RHS;
2399 if (sched_verbose >= 6)
2400 sel_print ("removed (cached as RHS, but renaming"
2401 " is now disabled)\n");
2402 *res = MOVEUP_EXPR_NULL;
2410 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2411 if successful. Write to RES the resulting code for moveup_expr. */
2413 try_transformation_cache (expr_t expr, insn_t insn,
2414 enum MOVEUP_EXPR_CODE *res)
2416 struct transformed_insns *pti
2417 = (struct transformed_insns *)
2418 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2420 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2423 /* This EXPR was already moved through this insn and was
2424 changed as a result. Fetch the proper data from
2426 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2427 INSN_UID (insn), pti->type,
2428 pti->vinsn_old, pti->vinsn_new,
2429 EXPR_SPEC_DONE_DS (expr));
2431 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2432 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2433 change_vinsn_in_expr (expr, pti->vinsn_new);
2434 if (pti->was_target_conflict)
2435 EXPR_TARGET_AVAILABLE (expr) = false;
2436 if (pti->type == TRANS_SPECULATION)
2438 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2439 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2442 if (sched_verbose >= 6)
2444 sel_print ("changed (cached): ");
2449 *res = MOVEUP_EXPR_CHANGED;
2456 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2458 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2459 enum MOVEUP_EXPR_CODE res)
2461 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2463 /* Do not cache result of propagating jumps through an insn group,
2464 as it is always true, which is not useful outside the group. */
2465 if (inside_insn_group)
2468 if (res == MOVEUP_EXPR_NULL)
2470 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2471 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2473 else if (res == MOVEUP_EXPR_SAME)
2475 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2476 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2478 else if (res == MOVEUP_EXPR_AS_RHS)
2480 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2481 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2487 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2488 and transformation type TRANS_TYPE. */
2490 update_transformation_cache (expr_t expr, insn_t insn,
2491 bool inside_insn_group,
2492 enum local_trans_type trans_type,
2493 vinsn_t expr_old_vinsn)
2495 struct transformed_insns *pti;
2497 if (inside_insn_group)
2500 pti = XNEW (struct transformed_insns);
2501 pti->vinsn_old = expr_old_vinsn;
2502 pti->vinsn_new = EXPR_VINSN (expr);
2503 pti->type = trans_type;
2504 pti->was_target_conflict = was_target_conflict;
2505 pti->ds = EXPR_SPEC_DONE_DS (expr);
2506 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2507 vinsn_attach (pti->vinsn_old);
2508 vinsn_attach (pti->vinsn_new);
2509 *((struct transformed_insns **)
2510 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2511 pti, VINSN_HASH_RTX (expr_old_vinsn),
2515 /* Same as moveup_expr, but first looks up the result of
2516 transformation in caches. */
2517 static enum MOVEUP_EXPR_CODE
2518 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2520 enum MOVEUP_EXPR_CODE res;
2521 bool got_answer = false;
2523 if (sched_verbose >= 6)
2525 sel_print ("Moving ");
2527 sel_print (" through %d: ", INSN_UID (insn));
2530 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr))
2531 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr)))
2532 == EXPR_INSN_RTX (expr)))
2533 /* Don't use cached information for debug insns that are heads of
2535 else if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2536 /* When inside insn group, we do not want remove stores conflicting
2537 with previosly issued loads. */
2538 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2539 else if (try_transformation_cache (expr, insn, &res))
2544 /* Invoke moveup_expr and record the results. */
2545 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2546 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2547 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2548 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2549 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2551 /* ??? Invent something better than this. We can't allow old_vinsn
2552 to go, we need it for the history vector. */
2553 vinsn_attach (expr_old_vinsn);
2555 res = moveup_expr (expr, insn, inside_insn_group,
2559 case MOVEUP_EXPR_NULL:
2560 update_bitmap_cache (expr, insn, inside_insn_group, res);
2561 if (sched_verbose >= 6)
2562 sel_print ("removed\n");
2565 case MOVEUP_EXPR_SAME:
2566 update_bitmap_cache (expr, insn, inside_insn_group, res);
2567 if (sched_verbose >= 6)
2568 sel_print ("unchanged\n");
2571 case MOVEUP_EXPR_AS_RHS:
2572 gcc_assert (!unique_p || inside_insn_group);
2573 update_bitmap_cache (expr, insn, inside_insn_group, res);
2574 if (sched_verbose >= 6)
2575 sel_print ("unchanged (as RHS)\n");
2578 case MOVEUP_EXPR_CHANGED:
2579 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2580 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2581 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2582 INSN_UID (insn), trans_type,
2583 expr_old_vinsn, EXPR_VINSN (expr),
2585 update_transformation_cache (expr, insn, inside_insn_group,
2586 trans_type, expr_old_vinsn);
2587 if (sched_verbose >= 6)
2589 sel_print ("changed: ");
2598 vinsn_detach (expr_old_vinsn);
2604 /* Moves an av set AVP up through INSN, performing necessary
2607 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2612 FOR_EACH_EXPR_1 (expr, i, avp)
2615 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2617 case MOVEUP_EXPR_SAME:
2618 case MOVEUP_EXPR_AS_RHS:
2621 case MOVEUP_EXPR_NULL:
2622 av_set_iter_remove (&i);
2625 case MOVEUP_EXPR_CHANGED:
2626 expr = merge_with_other_exprs (avp, &i, expr);
2635 /* Moves AVP set along PATH. */
2637 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2641 if (sched_verbose >= 6)
2642 sel_print ("Moving expressions up in the insn group...\n");
2645 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2647 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2649 moveup_set_expr (avp, ILIST_INSN (path), true);
2650 path = ILIST_NEXT (path);
2654 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2656 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2658 expr_def _tmp, *tmp = &_tmp;
2662 copy_expr_onside (tmp, expr);
2663 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2666 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2668 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2669 != MOVEUP_EXPR_NULL);
2670 path = ILIST_NEXT (path);
2675 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2676 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2678 if (tmp_vinsn != expr_vliw_vinsn)
2679 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2687 /* Functions that compute av and lv sets. */
2689 /* Returns true if INSN is not a downward continuation of the given path P in
2690 the current stage. */
2692 is_ineligible_successor (insn_t insn, ilist_t p)
2696 /* Check if insn is not deleted. */
2697 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2699 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2702 /* If it's the first insn visited, then the successor is ok. */
2706 prev_insn = ILIST_INSN (p);
2708 if (/* a backward edge. */
2709 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2710 /* is already visited. */
2711 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2712 && (ilist_is_in_p (p, insn)
2713 /* We can reach another fence here and still seqno of insn
2714 would be equal to seqno of prev_insn. This is possible
2715 when prev_insn is a previously created bookkeeping copy.
2716 In that case it'd get a seqno of insn. Thus, check here
2717 whether insn is in current fence too. */
2718 || IN_CURRENT_FENCE_P (insn)))
2719 /* Was already scheduled on this round. */
2720 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2721 && IN_CURRENT_FENCE_P (insn))
2722 /* An insn from another fence could also be
2723 scheduled earlier even if this insn is not in
2724 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2726 && INSN_SCHED_TIMES (insn) > 0))
2732 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2733 of handling multiple successors and properly merging its av_sets. P is
2734 the current path traversed. WS is the size of lookahead window.
2735 Return the av set computed. */
2737 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2739 struct succs_info *sinfo;
2740 av_set_t expr_in_all_succ_branches = NULL;
2742 insn_t succ, zero_succ = NULL;
2743 av_set_t av1 = NULL;
2745 gcc_assert (sel_bb_end_p (insn));
2747 /* Find different kind of successors needed for correct computing of
2748 SPEC and TARGET_AVAILABLE attributes. */
2749 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2752 if (sched_verbose >= 6)
2754 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2755 dump_insn_vector (sinfo->succs_ok);
2757 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2758 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2761 /* Add insn to the tail of current path. */
2762 ilist_add (&p, insn);
2764 FOR_EACH_VEC_ELT (sinfo->succs_ok, is, succ)
2768 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2769 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2771 av_set_split_usefulness (succ_set,
2772 sinfo->probs_ok[is],
2775 if (sinfo->all_succs_n > 1)
2777 /* Find EXPR'es that came from *all* successors and save them
2778 into expr_in_all_succ_branches. This set will be used later
2779 for calculating speculation attributes of EXPR'es. */
2782 expr_in_all_succ_branches = av_set_copy (succ_set);
2784 /* Remember the first successor for later. */
2792 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2793 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2794 av_set_iter_remove (&i);
2798 /* Union the av_sets. Check liveness restrictions on target registers
2799 in special case of two successors. */
2800 if (sinfo->succs_ok_n == 2 && is == 1)
2802 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2803 basic_block bb1 = BLOCK_FOR_INSN (succ);
2805 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2806 av_set_union_and_live (&av1, &succ_set,
2812 av_set_union_and_clear (&av1, &succ_set, insn);
2815 /* Check liveness restrictions via hard way when there are more than
2817 if (sinfo->succs_ok_n > 2)
2818 FOR_EACH_VEC_ELT (sinfo->succs_ok, is, succ)
2820 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2822 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2823 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2824 BB_LV_SET (succ_bb));
2827 /* Finally, check liveness restrictions on paths leaving the region. */
2828 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2829 FOR_EACH_VEC_ELT (sinfo->succs_other, is, succ)
2830 mark_unavailable_targets
2831 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2833 if (sinfo->all_succs_n > 1)
2838 /* Increase the spec attribute of all EXPR'es that didn't come
2839 from all successors. */
2840 FOR_EACH_EXPR (expr, i, av1)
2841 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2844 av_set_clear (&expr_in_all_succ_branches);
2846 /* Do not move conditional branches through other
2847 conditional branches. So, remove all conditional
2848 branches from av_set if current operator is a conditional
2850 av_set_substract_cond_branches (&av1);
2854 free_succs_info (sinfo);
2856 if (sched_verbose >= 6)
2858 sel_print ("av_succs (%d): ", INSN_UID (insn));
2866 /* This function computes av_set for the FIRST_INSN by dragging valid
2867 av_set through all basic block insns either from the end of basic block
2868 (computed using compute_av_set_at_bb_end) or from the insn on which
2869 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2870 below the basic block and handling conditional branches.
2871 FIRST_INSN - the basic block head, P - path consisting of the insns
2872 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2873 and bb ends are added to the path), WS - current window size,
2874 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2876 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2881 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2882 insn_t after_bb_end = NEXT_INSN (bb_end);
2885 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2887 /* Return NULL if insn is not on the legitimate downward path. */
2888 if (is_ineligible_successor (first_insn, p))
2890 if (sched_verbose >= 6)
2891 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2896 /* If insn already has valid av(insn) computed, just return it. */
2897 if (AV_SET_VALID_P (first_insn))
2901 if (sel_bb_head_p (first_insn))
2902 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2906 if (sched_verbose >= 6)
2908 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2909 dump_av_set (av_set);
2913 return need_copy_p ? av_set_copy (av_set) : av_set;
2916 ilist_add (&p, first_insn);
2918 /* As the result after this loop have completed, in LAST_INSN we'll
2919 have the insn which has valid av_set to start backward computation
2920 from: it either will be NULL because on it the window size was exceeded
2921 or other valid av_set as returned by compute_av_set for the last insn
2922 of the basic block. */
2923 for (last_insn = first_insn; last_insn != after_bb_end;
2924 last_insn = NEXT_INSN (last_insn))
2926 /* We may encounter valid av_set not only on bb_head, but also on
2927 those insns on which previously MAX_WS was exceeded. */
2928 if (AV_SET_VALID_P (last_insn))
2930 if (sched_verbose >= 6)
2931 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2935 /* The special case: the last insn of the BB may be an
2936 ineligible_successor due to its SEQ_NO that was set on
2937 it as a bookkeeping. */
2938 if (last_insn != first_insn
2939 && is_ineligible_successor (last_insn, p))
2941 if (sched_verbose >= 6)
2942 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
2946 if (DEBUG_INSN_P (last_insn))
2949 if (end_ws > max_ws)
2951 /* We can reach max lookahead size at bb_header, so clean av_set
2953 INSN_WS_LEVEL (last_insn) = global_level;
2955 if (sched_verbose >= 6)
2956 sel_print ("Insn %d is beyond the software lookahead window size\n",
2957 INSN_UID (last_insn));
2964 /* Get the valid av_set into AV above the LAST_INSN to start backward
2965 computation from. It either will be empty av_set or av_set computed from
2966 the successors on the last insn of the current bb. */
2967 if (last_insn != after_bb_end)
2971 /* This is needed only to obtain av_sets that are identical to
2972 those computed by the old compute_av_set version. */
2973 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
2974 av_set_add (&av, INSN_EXPR (last_insn));
2977 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2978 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
2980 /* Compute av_set in AV starting from below the LAST_INSN up to
2981 location above the FIRST_INSN. */
2982 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
2983 cur_insn = PREV_INSN (cur_insn))
2984 if (!INSN_NOP_P (cur_insn))
2988 moveup_set_expr (&av, cur_insn, false);
2990 /* If the expression for CUR_INSN is already in the set,
2991 replace it by the new one. */
2992 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
2996 copy_expr (expr, INSN_EXPR (cur_insn));
2999 av_set_add (&av, INSN_EXPR (cur_insn));
3002 /* Clear stale bb_av_set. */
3003 if (sel_bb_head_p (first_insn))
3005 av_set_clear (&BB_AV_SET (cur_bb));
3006 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
3007 BB_AV_LEVEL (cur_bb) = global_level;
3010 if (sched_verbose >= 6)
3012 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
3021 /* Compute av set before INSN.
3022 INSN - the current operation (actual rtx INSN)
3023 P - the current path, which is list of insns visited so far
3024 WS - software lookahead window size.
3025 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3026 if we want to save computed av_set in s_i_d, we should make a copy of it.
3028 In the resulting set we will have only expressions that don't have delay
3029 stalls and nonsubstitutable dependences. */
3031 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
3033 return compute_av_set_inside_bb (insn, p, ws, unique_p);
3036 /* Propagate a liveness set LV through INSN. */
3038 propagate_lv_set (regset lv, insn_t insn)
3040 gcc_assert (INSN_P (insn));
3042 if (INSN_NOP_P (insn))
3045 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
3048 /* Return livness set at the end of BB. */
3050 compute_live_after_bb (basic_block bb)
3054 regset lv = get_clear_regset_from_pool ();
3056 gcc_assert (!ignore_first);
3058 FOR_EACH_EDGE (e, ei, bb->succs)
3059 if (sel_bb_empty_p (e->dest))
3061 if (! BB_LV_SET_VALID_P (e->dest))
3064 gcc_assert (BB_LV_SET (e->dest) == NULL);
3065 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
3066 BB_LV_SET_VALID_P (e->dest) = true;
3068 IOR_REG_SET (lv, BB_LV_SET (e->dest));
3071 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
3076 /* Compute the set of all live registers at the point before INSN and save
3077 it at INSN if INSN is bb header. */
3079 compute_live (insn_t insn)
3081 basic_block bb = BLOCK_FOR_INSN (insn);
3085 /* Return the valid set if we're already on it. */
3090 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3091 src = BB_LV_SET (bb);
3094 gcc_assert (in_current_region_p (bb));
3095 if (INSN_LIVE_VALID_P (insn))
3096 src = INSN_LIVE (insn);
3101 lv = get_regset_from_pool ();
3102 COPY_REG_SET (lv, src);
3104 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3106 COPY_REG_SET (BB_LV_SET (bb), lv);
3107 BB_LV_SET_VALID_P (bb) = true;
3110 return_regset_to_pool (lv);
3115 /* We've skipped the wrong lv_set. Don't skip the right one. */
3116 ignore_first = false;
3117 gcc_assert (in_current_region_p (bb));
3119 /* Find a valid LV set in this block or below, if needed.
3120 Start searching from the next insn: either ignore_first is true, or
3121 INSN doesn't have a correct live set. */
3122 temp = NEXT_INSN (insn);
3123 final = NEXT_INSN (BB_END (bb));
3124 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3125 temp = NEXT_INSN (temp);
3128 lv = compute_live_after_bb (bb);
3129 temp = PREV_INSN (temp);
3133 lv = get_regset_from_pool ();
3134 COPY_REG_SET (lv, INSN_LIVE (temp));
3137 /* Put correct lv sets on the insns which have bad sets. */
3138 final = PREV_INSN (insn);
3139 while (temp != final)
3141 propagate_lv_set (lv, temp);
3142 COPY_REG_SET (INSN_LIVE (temp), lv);
3143 INSN_LIVE_VALID_P (temp) = true;
3144 temp = PREV_INSN (temp);
3147 /* Also put it in a BB. */
3148 if (sel_bb_head_p (insn))
3150 basic_block bb = BLOCK_FOR_INSN (insn);
3152 COPY_REG_SET (BB_LV_SET (bb), lv);
3153 BB_LV_SET_VALID_P (bb) = true;
3156 /* We return LV to the pool, but will not clear it there. Thus we can
3157 legimatelly use LV till the next use of regset_pool_get (). */
3158 return_regset_to_pool (lv);
3162 /* Update liveness sets for INSN. */
3164 update_liveness_on_insn (rtx_insn *insn)
3166 ignore_first = true;
3167 compute_live (insn);
3170 /* Compute liveness below INSN and write it into REGS. */
3172 compute_live_below_insn (rtx_insn *insn, regset regs)
3177 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3178 IOR_REG_SET (regs, compute_live (succ));
3181 /* Update the data gathered in av and lv sets starting from INSN. */
3183 update_data_sets (rtx_insn *insn)
3185 update_liveness_on_insn (insn);
3186 if (sel_bb_head_p (insn))
3188 gcc_assert (AV_LEVEL (insn) != 0);
3189 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3190 compute_av_set (insn, NULL, 0, 0);
3195 /* Helper for move_op () and find_used_regs ().
3196 Return speculation type for which a check should be created on the place
3197 of INSN. EXPR is one of the original ops we are searching for. */
3199 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3202 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3204 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3206 if (targetm.sched.get_insn_checked_ds)
3207 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3209 if (spec_info != NULL
3210 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3211 already_checked_ds |= BEGIN_CONTROL;
3213 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3215 to_check_ds &= ~already_checked_ds;
3220 /* Find the set of registers that are unavailable for storing expres
3221 while moving ORIG_OPS up on the path starting from INSN due to
3222 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3224 All the original operations found during the traversal are saved in the
3225 ORIGINAL_INSNS list.
3227 REG_RENAME_P denotes the set of hardware registers that
3228 can not be used with renaming due to the register class restrictions,
3229 mode restrictions and other (the register we'll choose should be
3230 compatible class with the original uses, shouldn't be in call_used_regs,
3231 should be HARD_REGNO_RENAME_OK etc).
3233 Returns TRUE if we've found all original insns, FALSE otherwise.
3235 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3236 to traverse the code motion paths. This helper function finds registers
3237 that are not available for storing expres while moving ORIG_OPS up on the
3238 path starting from INSN. A register considered as used on the moving path,
3239 if one of the following conditions is not satisfied:
3241 (1) a register not set or read on any path from xi to an instance of
3242 the original operation,
3243 (2) not among the live registers of the point immediately following the
3244 first original operation on a given downward path, except for the
3245 original target register of the operation,
3246 (3) not live on the other path of any conditional branch that is passed
3247 by the operation, in case original operations are not present on
3248 both paths of the conditional branch.
3250 All the original operations found during the traversal are saved in the
3251 ORIGINAL_INSNS list.
3253 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3254 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3255 to unavailable hard regs at the point original operation is found. */
3258 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3259 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3261 def_list_iterator i;
3264 bool needs_spec_check_p = false;
3266 av_set_iterator expr_iter;
3267 struct fur_static_params sparams;
3268 struct cmpd_local_params lparams;
3270 /* We haven't visited any blocks yet. */
3271 bitmap_clear (code_motion_visited_blocks);
3273 /* Init parameters for code_motion_path_driver. */
3274 sparams.crosses_call = false;
3275 sparams.original_insns = original_insns;
3276 sparams.used_regs = used_regs;
3278 /* Set the appropriate hooks and data. */
3279 code_motion_path_driver_info = &fur_hooks;
3281 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3283 reg_rename_p->crosses_call |= sparams.crosses_call;
3285 gcc_assert (res == 1);
3286 gcc_assert (original_insns && *original_insns);
3288 /* ??? We calculate whether an expression needs a check when computing
3289 av sets. This information is not as precise as it could be due to
3290 merging this bit in merge_expr. We can do better in find_used_regs,
3291 but we want to avoid multiple traversals of the same code motion
3293 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3294 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3296 /* Mark hardware regs in REG_RENAME_P that are not suitable
3297 for renaming expr in INSN due to hardware restrictions (register class,
3298 modes compatibility etc). */
3299 FOR_EACH_DEF (def, i, *original_insns)
3301 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3303 if (VINSN_SEPARABLE_P (vinsn))
3304 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3306 /* Do not allow clobbering of ld.[sa] address in case some of the
3307 original operations need a check. */
3308 if (needs_spec_check_p)
3309 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3316 /* Functions to choose the best insn from available ones. */
3318 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3320 sel_target_adjust_priority (expr_t expr)
3322 int priority = EXPR_PRIORITY (expr);
3325 if (targetm.sched.adjust_priority)
3326 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3328 new_priority = priority;
3330 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3331 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3333 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3335 if (sched_verbose >= 4)
3336 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3337 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3338 EXPR_PRIORITY_ADJ (expr), new_priority);
3340 return new_priority;
3343 /* Rank two available exprs for schedule. Never return 0 here. */
3345 sel_rank_for_schedule (const void *x, const void *y)
3347 expr_t tmp = *(const expr_t *) y;
3348 expr_t tmp2 = *(const expr_t *) x;
3349 insn_t tmp_insn, tmp2_insn;
3350 vinsn_t tmp_vinsn, tmp2_vinsn;
3353 tmp_vinsn = EXPR_VINSN (tmp);
3354 tmp2_vinsn = EXPR_VINSN (tmp2);
3355 tmp_insn = EXPR_INSN_RTX (tmp);
3356 tmp2_insn = EXPR_INSN_RTX (tmp2);
3358 /* Schedule debug insns as early as possible. */
3359 if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn))
3361 else if (DEBUG_INSN_P (tmp2_insn))
3364 /* Prefer SCHED_GROUP_P insns to any others. */
3365 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3367 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3368 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3370 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3371 cannot be cloned. */
3372 if (VINSN_UNIQUE_P (tmp2_vinsn))
3377 /* Discourage scheduling of speculative checks. */
3378 val = (sel_insn_is_speculation_check (tmp_insn)
3379 - sel_insn_is_speculation_check (tmp2_insn));
3383 /* Prefer not scheduled insn over scheduled one. */
3384 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3386 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3391 /* Prefer jump over non-jump instruction. */
3392 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3394 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3397 /* Prefer an expr with greater priority. */
3398 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3400 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3401 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3403 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3406 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3407 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3411 if (spec_info != NULL && spec_info->mask != 0)
3412 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3418 ds1 = EXPR_SPEC_DONE_DS (tmp);
3420 dw1 = ds_weak (ds1);
3424 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3426 dw2 = ds_weak (ds2);
3431 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3435 /* Prefer an old insn to a bookkeeping insn. */
3436 if (INSN_UID (tmp_insn) < first_emitted_uid
3437 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3439 if (INSN_UID (tmp_insn) >= first_emitted_uid
3440 && INSN_UID (tmp2_insn) < first_emitted_uid)
3443 /* Prefer an insn with smaller UID, as a last resort.
3444 We can't safely use INSN_LUID as it is defined only for those insns
3445 that are in the stream. */
3446 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3449 /* Filter out expressions from av set pointed to by AV_PTR
3450 that are pipelined too many times. */
3452 process_pipelined_exprs (av_set_t *av_ptr)
3457 /* Don't pipeline already pipelined code as that would increase
3458 number of unnecessary register moves. */
3459 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3461 if (EXPR_SCHED_TIMES (expr)
3462 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3463 av_set_iter_remove (&si);
3467 /* Filter speculative insns from AV_PTR if we don't want them. */
3469 process_spec_exprs (av_set_t *av_ptr)
3474 if (spec_info == NULL)
3477 /* Scan *AV_PTR to find out if we want to consider speculative
3478 instructions for scheduling. */
3479 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3483 ds = EXPR_SPEC_DONE_DS (expr);
3485 /* The probability of a success is too low - don't speculate. */
3486 if ((ds & SPECULATIVE)
3487 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3488 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3489 || (pipelining_p && false
3491 && (ds & CONTROL_SPEC))))
3493 av_set_iter_remove (&si);
3499 /* Search for any use-like insns in AV_PTR and decide on scheduling
3500 them. Return one when found, and NULL otherwise.
3501 Note that we check here whether a USE could be scheduled to avoid
3502 an infinite loop later. */
3504 process_use_exprs (av_set_t *av_ptr)
3508 bool uses_present_p = false;
3509 bool try_uses_p = true;
3511 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3513 /* This will also initialize INSN_CODE for later use. */
3514 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3516 /* If we have a USE in *AV_PTR that was not scheduled yet,
3517 do so because it will do good only. */
3518 if (EXPR_SCHED_TIMES (expr) <= 0)
3520 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3523 av_set_iter_remove (&si);
3527 gcc_assert (pipelining_p);
3529 uses_present_p = true;
3538 /* If we don't want to schedule any USEs right now and we have some
3539 in *AV_PTR, remove them, else just return the first one found. */
3542 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3543 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3544 av_set_iter_remove (&si);
3548 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3550 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3552 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3555 av_set_iter_remove (&si);
3563 /* Lookup EXPR in VINSN_VEC and return TRUE if found. Also check patterns from
3564 EXPR's history of changes. */
3566 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3568 vinsn_t vinsn, expr_vinsn;
3572 /* Start with checking expr itself and then proceed with all the old forms
3573 of expr taken from its history vector. */
3574 for (i = 0, expr_vinsn = EXPR_VINSN (expr);
3576 expr_vinsn = (i < EXPR_HISTORY_OF_CHANGES (expr).length ()
3577 ? EXPR_HISTORY_OF_CHANGES (expr)[i++].old_expr_vinsn
3579 FOR_EACH_VEC_ELT (vinsn_vec, n, vinsn)
3580 if (VINSN_SEPARABLE_P (vinsn))
3582 if (vinsn_equal_p (vinsn, expr_vinsn))
3587 /* For non-separable instructions, the blocking insn can have
3588 another pattern due to substitution, and we can't choose
3589 different register as in the above case. Check all registers
3590 being written instead. */
3591 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3592 VINSN_REG_SETS (expr_vinsn)))
3599 /* Return true if either of expressions from ORIG_OPS can be blocked
3600 by previously created bookkeeping code. STATIC_PARAMS points to static
3601 parameters of move_op. */
3603 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3606 av_set_iterator iter;
3607 moveop_static_params_p sparams;
3609 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3610 created while scheduling on another fence. */
3611 FOR_EACH_EXPR (expr, iter, orig_ops)
3612 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3615 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3616 sparams = (moveop_static_params_p) static_params;
3618 /* Expressions can be also blocked by bookkeeping created during current
3620 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3621 FOR_EACH_EXPR (expr, iter, orig_ops)
3622 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3625 /* Expressions in ORIG_OPS may have wrong destination register due to
3626 renaming. Check with the right register instead. */
3627 if (sparams->dest && REG_P (sparams->dest))
3629 rtx reg = sparams->dest;
3630 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3632 if (register_unavailable_p (VINSN_REG_SETS (failed_vinsn), reg)
3633 || register_unavailable_p (VINSN_REG_USES (failed_vinsn), reg)
3634 || register_unavailable_p (VINSN_REG_CLOBBERS (failed_vinsn), reg))
3641 /* Clear VINSN_VEC and detach vinsns. */
3643 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3645 unsigned len = vinsn_vec->length ();
3651 FOR_EACH_VEC_ELT (*vinsn_vec, n, vinsn)
3652 vinsn_detach (vinsn);
3653 vinsn_vec->block_remove (0, len);
3657 /* Add the vinsn of EXPR to the VINSN_VEC. */
3659 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3661 vinsn_attach (EXPR_VINSN (expr));
3662 vinsn_vec->safe_push (EXPR_VINSN (expr));
3665 /* Free the vector representing blocked expressions. */
3667 vinsn_vec_free (vinsn_vec_t &vinsn_vec)
3669 vinsn_vec.release ();
3672 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3674 void sel_add_to_insn_priority (rtx insn, int amount)
3676 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3678 if (sched_verbose >= 2)
3679 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3680 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3681 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3684 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3685 true if there is something to schedule. BNDS and FENCE are current
3686 boundaries and fence, respectively. If we need to stall for some cycles
3687 before an expr from AV would become available, write this number to
3690 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3695 int sched_next_worked = 0, stalled, n;
3696 static int av_max_prio, est_ticks_till_branch;
3697 int min_need_stall = -1;
3698 deps_t dc = BND_DC (BLIST_BND (bnds));
3700 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3701 already scheduled. */
3705 /* Empty vector from the previous stuff. */
3706 if (vec_av_set.length () > 0)
3707 vec_av_set.block_remove (0, vec_av_set.length ());
3709 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3711 gcc_assert (vec_av_set.is_empty ());
3712 FOR_EACH_EXPR (expr, si, av)
3714 vec_av_set.safe_push (expr);
3716 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3718 /* Adjust priority using target backend hook. */
3719 sel_target_adjust_priority (expr);
3722 /* Sort the vector. */
3723 vec_av_set.qsort (sel_rank_for_schedule);
3725 /* We record maximal priority of insns in av set for current instruction
3727 if (FENCE_STARTS_CYCLE_P (fence))
3728 av_max_prio = est_ticks_till_branch = INT_MIN;
3730 /* Filter out inappropriate expressions. Loop's direction is reversed to
3731 visit "best" instructions first. We assume that vec::unordered_remove
3732 moves last element in place of one being deleted. */
3733 for (n = vec_av_set.length () - 1, stalled = 0; n >= 0; n--)
3735 expr_t expr = vec_av_set[n];
3736 insn_t insn = EXPR_INSN_RTX (expr);
3737 signed char target_available;
3738 bool is_orig_reg_p = true;
3739 int need_cycles, new_prio;
3740 bool fence_insn_p = INSN_UID (insn) == INSN_UID (FENCE_INSN (fence));
3742 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3743 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3745 vec_av_set.unordered_remove (n);
3749 /* Set number of sched_next insns (just in case there
3750 could be several). */
3751 if (FENCE_SCHED_NEXT (fence))
3752 sched_next_worked++;
3754 /* Check all liveness requirements and try renaming.
3755 FIXME: try to minimize calls to this. */
3756 target_available = EXPR_TARGET_AVAILABLE (expr);
3758 /* If insn was already scheduled on the current fence,
3759 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3760 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr)
3762 target_available = -1;
3764 /* If the availability of the EXPR is invalidated by the insertion of
3765 bookkeeping earlier, make sure that we won't choose this expr for
3766 scheduling if it's not separable, and if it is separable, then
3767 we have to recompute the set of available registers for it. */
3768 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3770 vec_av_set.unordered_remove (n);
3771 if (sched_verbose >= 4)
3772 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3777 if (target_available == true)
3779 /* Do nothing -- we can use an existing register. */
3780 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3782 else if (/* Non-separable instruction will never
3783 get another register. */
3784 (target_available == false
3785 && !EXPR_SEPARABLE_P (expr))
3786 /* Don't try to find a register for low-priority expression. */
3787 || (int) vec_av_set.length () - 1 - n >= max_insns_to_rename
3788 /* ??? FIXME: Don't try to rename data speculation. */
3789 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3790 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3792 vec_av_set.unordered_remove (n);
3793 if (sched_verbose >= 4)
3794 sel_print ("Expr %d has no suitable target register\n",
3797 /* A fence insn should not get here. */
3798 gcc_assert (!fence_insn_p);
3802 /* At this point a fence insn should always be available. */
3803 gcc_assert (!fence_insn_p
3804 || INSN_UID (FENCE_INSN (fence)) == INSN_UID (EXPR_INSN_RTX (expr)));
3806 /* Filter expressions that need to be renamed or speculated when
3807 pipelining, because compensating register copies or speculation
3808 checks are likely to be placed near the beginning of the loop,
3810 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3811 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3813 /* Estimation of number of cycles until loop branch for
3814 renaming/speculation to be successful. */
3815 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3817 if ((int) current_loop_nest->ninsns < 9)
3819 vec_av_set.unordered_remove (n);
3820 if (sched_verbose >= 4)
3821 sel_print ("Pipelining expr %d will likely cause stall\n",
3826 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3827 < need_n_ticks_till_branch * issue_rate / 2
3828 && est_ticks_till_branch < need_n_ticks_till_branch)
3830 vec_av_set.unordered_remove (n);
3831 if (sched_verbose >= 4)
3832 sel_print ("Pipelining expr %d will likely cause stall\n",
3838 /* We want to schedule speculation checks as late as possible. Discard
3839 them from av set if there are instructions with higher priority. */
3840 if (sel_insn_is_speculation_check (insn)
3841 && EXPR_PRIORITY (expr) < av_max_prio)
3844 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3845 vec_av_set.unordered_remove (n);
3846 if (sched_verbose >= 4)
3847 sel_print ("Delaying speculation check %d until its first use\n",
3852 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3853 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3854 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3856 /* Don't allow any insns whose data is not yet ready.
3857 Check first whether we've already tried them and failed. */
3858 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3860 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3861 - FENCE_CYCLE (fence));
3862 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3863 est_ticks_till_branch = MAX (est_ticks_till_branch,
3864 EXPR_PRIORITY (expr) + need_cycles);
3866 if (need_cycles > 0)
3869 min_need_stall = (min_need_stall < 0
3871 : MIN (min_need_stall, need_cycles));
3872 vec_av_set.unordered_remove (n);
3874 if (sched_verbose >= 4)
3875 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3877 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3882 /* Now resort to dependence analysis to find whether EXPR might be
3883 stalled due to dependencies from FENCE's context. */
3884 need_cycles = tick_check_p (expr, dc, fence);
3885 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3887 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3888 est_ticks_till_branch = MAX (est_ticks_till_branch,
3891 if (need_cycles > 0)
3893 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3895 int new_size = INSN_UID (insn) * 3 / 2;
3897 FENCE_READY_TICKS (fence)
3898 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3899 new_size, FENCE_READY_TICKS_SIZE (fence),
3902 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3903 = FENCE_CYCLE (fence) + need_cycles;
3906 min_need_stall = (min_need_stall < 0
3908 : MIN (min_need_stall, need_cycles));
3910 vec_av_set.unordered_remove (n);
3912 if (sched_verbose >= 4)
3913 sel_print ("Expr %d is not ready yet until cycle %d\n",
3915 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3919 if (sched_verbose >= 4)
3920 sel_print ("Expr %d is ok\n", INSN_UID (insn));
3924 /* Clear SCHED_NEXT. */
3925 if (FENCE_SCHED_NEXT (fence))
3927 gcc_assert (sched_next_worked == 1);
3928 FENCE_SCHED_NEXT (fence) = NULL;
3931 /* No need to stall if this variable was not initialized. */
3932 if (min_need_stall < 0)
3935 if (vec_av_set.is_empty ())
3937 /* We need to set *pneed_stall here, because later we skip this code
3938 when ready list is empty. */
3939 *pneed_stall = min_need_stall;
3943 gcc_assert (min_need_stall == 0);
3945 /* Sort the vector. */
3946 vec_av_set.qsort (sel_rank_for_schedule);
3948 if (sched_verbose >= 4)
3950 sel_print ("Total ready exprs: %d, stalled: %d\n",
3951 vec_av_set.length (), stalled);
3952 sel_print ("Sorted av set (%d): ", vec_av_set.length ());
3953 FOR_EACH_VEC_ELT (vec_av_set, n, expr)
3962 /* Convert a vectored and sorted av set to the ready list that
3963 the rest of the backend wants to see. */
3965 convert_vec_av_set_to_ready (void)
3970 /* Allocate and fill the ready list from the sorted vector. */
3971 ready.n_ready = vec_av_set.length ();
3972 ready.first = ready.n_ready - 1;
3974 gcc_assert (ready.n_ready > 0);
3976 if (ready.n_ready > max_issue_size)
3978 max_issue_size = ready.n_ready;
3979 sched_extend_ready_list (ready.n_ready);
3982 FOR_EACH_VEC_ELT (vec_av_set, n, expr)
3984 vinsn_t vi = EXPR_VINSN (expr);
3985 insn_t insn = VINSN_INSN_RTX (vi);
3988 ready.vec[n] = insn;
3992 /* Initialize ready list from *AV_PTR for the max_issue () call.
3993 If any unrecognizable insn found in *AV_PTR, return it (and skip
3994 max_issue). BND and FENCE are current boundary and fence,
3995 respectively. If we need to stall for some cycles before an expr
3996 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3998 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
4003 /* We do not support multiple boundaries per fence. */
4004 gcc_assert (BLIST_NEXT (bnds) == NULL);
4006 /* Process expressions required special handling, i.e. pipelined,
4007 speculative and recog() < 0 expressions first. */
4008 process_pipelined_exprs (av_ptr);
4009 process_spec_exprs (av_ptr);
4011 /* A USE could be scheduled immediately. */
4012 expr = process_use_exprs (av_ptr);
4019 /* Turn the av set to a vector for sorting. */
4020 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
4026 /* Build the final ready list. */
4027 convert_vec_av_set_to_ready ();
4031 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4033 sel_dfa_new_cycle (insn_t insn, fence_t fence)
4035 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
4036 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
4037 : FENCE_CYCLE (fence) - 1;
4041 if (!targetm.sched.dfa_new_cycle)
4044 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4046 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
4047 insn, last_scheduled_cycle,
4048 FENCE_CYCLE (fence), &sort_p))
4050 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4051 advance_one_cycle (fence);
4052 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4059 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4060 we can issue. FENCE is the current fence. */
4062 invoke_reorder_hooks (fence_t fence)
4065 bool ran_hook = false;
4067 /* Call the reorder hook at the beginning of the cycle, and call
4068 the reorder2 hook in the middle of the cycle. */
4069 if (FENCE_ISSUED_INSNS (fence) == 0)
4071 if (targetm.sched.reorder
4072 && !SCHED_GROUP_P (ready_element (&ready, 0))
4073 && ready.n_ready > 1)
4075 /* Don't give reorder the most prioritized insn as it can break
4081 = targetm.sched.reorder (sched_dump, sched_verbose,
4082 ready_lastpos (&ready),
4083 &ready.n_ready, FENCE_CYCLE (fence));
4091 /* Initialize can_issue_more for variable_issue. */
4092 issue_more = issue_rate;
4094 else if (targetm.sched.reorder2
4095 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4097 if (ready.n_ready == 1)
4099 targetm.sched.reorder2 (sched_dump, sched_verbose,
4100 ready_lastpos (&ready),
4101 &ready.n_ready, FENCE_CYCLE (fence));
4108 targetm.sched.reorder2 (sched_dump, sched_verbose,
4110 ? ready_lastpos (&ready) : NULL,
4111 &ready.n_ready, FENCE_CYCLE (fence));
4120 issue_more = FENCE_ISSUE_MORE (fence);
4122 /* Ensure that ready list and vec_av_set are in line with each other,
4123 i.e. vec_av_set[i] == ready_element (&ready, i). */
4124 if (issue_more && ran_hook)
4127 rtx_insn **arr = ready.vec;
4128 expr_t *vec = vec_av_set.address ();
4130 for (i = 0, n = ready.n_ready; i < n; i++)
4131 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4133 for (j = i; j < n; j++)
4134 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4138 std::swap (vec[i], vec[j]);
4145 /* Return an EXPR corresponding to INDEX element of ready list, if
4146 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4147 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4148 ready.vec otherwise. */
4149 static inline expr_t
4150 find_expr_for_ready (int index, bool follow_ready_element)
4155 real_index = follow_ready_element ? ready.first - index : index;
4157 expr = vec_av_set[real_index];
4158 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4163 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4164 of such insns found. */
4166 invoke_dfa_lookahead_guard (void)
4170 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4172 if (sched_verbose >= 2)
4173 sel_print ("ready after reorder: ");
4175 for (i = 0, n = 0; i < ready.n_ready; i++)
4181 /* In this loop insn is Ith element of the ready list given by
4182 ready_element, not Ith element of ready.vec. */
4183 insn = ready_element (&ready, i);
4185 if (! have_hook || i == 0)
4188 r = targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn, i);
4190 gcc_assert (INSN_CODE (insn) >= 0);
4192 /* Only insns with ready_try = 0 can get here
4193 from fill_ready_list. */
4194 gcc_assert (ready_try [i] == 0);
4199 expr = find_expr_for_ready (i, true);
4201 if (sched_verbose >= 2)
4203 dump_vinsn (EXPR_VINSN (expr));
4204 sel_print (":%d; ", ready_try[i]);
4208 if (sched_verbose >= 2)
4213 /* Calculate the number of privileged insns and return it. */
4215 calculate_privileged_insns (void)
4217 expr_t cur_expr, min_spec_expr = NULL;
4218 int privileged_n = 0, i;
4220 for (i = 0; i < ready.n_ready; i++)
4225 if (! min_spec_expr)
4226 min_spec_expr = find_expr_for_ready (i, true);
4228 cur_expr = find_expr_for_ready (i, true);
4230 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4236 if (i == ready.n_ready)
4239 if (sched_verbose >= 2)
4240 sel_print ("privileged_n: %d insns with SPEC %d\n",
4241 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4242 return privileged_n;
4245 /* Call the rest of the hooks after the choice was made. Return
4246 the number of insns that still can be issued given that the current
4247 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4248 and the insn chosen for scheduling, respectively. */
4250 invoke_aftermath_hooks (fence_t fence, rtx_insn *best_insn, int issue_more)
4252 gcc_assert (INSN_P (best_insn));
4254 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4255 sel_dfa_new_cycle (best_insn, fence);
4257 if (targetm.sched.variable_issue)
4259 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4261 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4263 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4265 else if (!DEBUG_INSN_P (best_insn)
4266 && GET_CODE (PATTERN (best_insn)) != USE
4267 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4273 /* Estimate the cost of issuing INSN on DFA state STATE. */
4275 estimate_insn_cost (rtx_insn *insn, state_t state)
4277 static state_t temp = NULL;
4281 temp = xmalloc (dfa_state_size);
4283 memcpy (temp, state, dfa_state_size);
4284 cost = state_transition (temp, insn);
4293 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4294 This function properly handles ASMs, USEs etc. */
4296 get_expr_cost (expr_t expr, fence_t fence)
4298 rtx_insn *insn = EXPR_INSN_RTX (expr);
4300 if (recog_memoized (insn) < 0)
4302 if (!FENCE_STARTS_CYCLE_P (fence)
4303 && INSN_ASM_P (insn))
4304 /* This is asm insn which is tryed to be issued on the
4305 cycle not first. Issue it on the next cycle. */
4308 /* A USE insn, or something else we don't need to
4309 understand. We can't pass these directly to
4310 state_transition because it will trigger a
4311 fatal error for unrecognizable insns. */
4315 return estimate_insn_cost (insn, FENCE_STATE (fence));
4318 /* Find the best insn for scheduling, either via max_issue or just take
4319 the most prioritized available. */
4321 choose_best_insn (fence_t fence, int privileged_n, int *index)
4325 if (dfa_lookahead > 0)
4327 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4328 /* TODO: pass equivalent of first_cycle_insn_p to max_issue (). */
4329 can_issue = max_issue (&ready, privileged_n,
4330 FENCE_STATE (fence), true, index);
4331 if (sched_verbose >= 2)
4332 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4333 can_issue, FENCE_ISSUED_INSNS (fence));
4337 /* We can't use max_issue; just return the first available element. */
4340 for (i = 0; i < ready.n_ready; i++)
4342 expr_t expr = find_expr_for_ready (i, true);
4344 if (get_expr_cost (expr, fence) < 1)
4346 can_issue = can_issue_more;
4349 if (sched_verbose >= 2)
4350 sel_print ("using %dth insn from the ready list\n", i + 1);
4356 if (i == ready.n_ready)
4366 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4367 BNDS and FENCE are current boundaries and scheduling fence respectively.
4368 Return the expr found and NULL if nothing can be issued atm.
4369 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4371 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4376 /* Choose the best insn for scheduling via:
4377 1) sorting the ready list based on priority;
4378 2) calling the reorder hook;
4379 3) calling max_issue. */
4380 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4381 if (best == NULL && ready.n_ready > 0)
4383 int privileged_n, index;
4385 can_issue_more = invoke_reorder_hooks (fence);
4386 if (can_issue_more > 0)
4388 /* Try choosing the best insn until we find one that is could be
4389 scheduled due to liveness restrictions on its destination register.
4390 In the future, we'd like to choose once and then just probe insns
4391 in the order of their priority. */
4392 invoke_dfa_lookahead_guard ();
4393 privileged_n = calculate_privileged_insns ();
4394 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4396 best = find_expr_for_ready (index, true);
4398 /* We had some available insns, so if we can't issue them,
4400 if (can_issue_more == 0)
4409 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4411 if (targetm.sched.variable_issue
4412 && can_issue_more == 0)
4416 if (sched_verbose >= 2)
4420 sel_print ("Best expression (vliw form): ");
4422 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4425 sel_print ("No best expr found!\n");
4432 /* Functions that implement the core of the scheduler. */
4435 /* Emit an instruction from EXPR with SEQNO and VINSN after
4438 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4439 insn_t place_to_insert)
4441 /* This assert fails when we have identical instructions
4442 one of which dominates the other. In this case move_op ()
4443 finds the first instruction and doesn't search for second one.
4444 The solution would be to compute av_set after the first found
4445 insn and, if insn present in that set, continue searching.
4446 For now we workaround this issue in move_op. */
4447 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4449 if (EXPR_WAS_RENAMED (expr))
4451 unsigned regno = expr_dest_regno (expr);
4453 if (HARD_REGISTER_NUM_P (regno))
4455 df_set_regs_ever_live (regno, true);
4456 reg_rename_tick[regno] = ++reg_rename_this_tick;
4460 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4464 /* Return TRUE if BB can hold bookkeeping code. */
4466 block_valid_for_bookkeeping_p (basic_block bb)
4468 insn_t bb_end = BB_END (bb);
4470 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4473 if (INSN_P (bb_end))
4475 if (INSN_SCHED_TIMES (bb_end) > 0)
4479 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4484 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4485 into E2->dest, except from E1->src (there may be a sequence of empty basic
4486 blocks between E1->src and E2->dest). Return found block, or NULL if new
4487 one must be created. If LAX holds, don't assume there is a simple path
4488 from E1->src to E2->dest. */
4490 find_block_for_bookkeeping (edge e1, edge e2, bool lax)
4492 basic_block candidate_block = NULL;
4495 /* Loop over edges from E1 to E2, inclusive. */
4496 for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun); e =
4497 EDGE_SUCC (e->dest, 0))
4499 if (EDGE_COUNT (e->dest->preds) == 2)
4501 if (candidate_block == NULL)
4502 candidate_block = (EDGE_PRED (e->dest, 0) == e
4503 ? EDGE_PRED (e->dest, 1)->src
4504 : EDGE_PRED (e->dest, 0)->src);
4506 /* Found additional edge leading to path from e1 to e2
4510 else if (EDGE_COUNT (e->dest->preds) > 2)
4511 /* Several edges leading to path from e1 to e2 from aside. */
4515 return ((!lax || candidate_block)
4516 && block_valid_for_bookkeeping_p (candidate_block)
4520 if (lax && EDGE_COUNT (e->dest->succs) != 1)
4530 /* Create new basic block for bookkeeping code for path(s) incoming into
4531 E2->dest, except from E1->src. Return created block. */
4533 create_block_for_bookkeeping (edge e1, edge e2)
4535 basic_block new_bb, bb = e2->dest;
4537 /* Check that we don't spoil the loop structure. */
4538 if (current_loop_nest)
4540 basic_block latch = current_loop_nest->latch;
4542 /* We do not split header. */
4543 gcc_assert (e2->dest != current_loop_nest->header);
4545 /* We do not redirect the only edge to the latch block. */
4546 gcc_assert (e1->dest != latch
4547 || !single_pred_p (latch)
4548 || e1 != single_pred_edge (latch));
4551 /* Split BB to insert BOOK_INSN there. */
4552 new_bb = sched_split_block (bb, NULL);
4554 /* Move note_list from the upper bb. */
4555 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4556 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4557 BB_NOTE_LIST (bb) = NULL;
4559 gcc_assert (e2->dest == bb);
4561 /* Skip block for bookkeeping copy when leaving E1->src. */
4562 if (e1->flags & EDGE_FALLTHRU)
4563 sel_redirect_edge_and_branch_force (e1, new_bb);
4565 sel_redirect_edge_and_branch (e1, new_bb);
4567 gcc_assert (e1->dest == new_bb);
4568 gcc_assert (sel_bb_empty_p (bb));
4570 /* To keep basic block numbers in sync between debug and non-debug
4571 compilations, we have to rotate blocks here. Consider that we
4572 started from (a,b)->d, (c,d)->e, and d contained only debug
4573 insns. It would have been removed before if the debug insns
4574 weren't there, so we'd have split e rather than d. So what we do
4575 now is to swap the block numbers of new_bb and
4576 single_succ(new_bb) == e, so that the insns that were in e before
4577 get the new block number. */
4579 if (MAY_HAVE_DEBUG_INSNS)
4582 insn_t insn = sel_bb_head (new_bb);
4585 if (DEBUG_INSN_P (insn)
4586 && single_succ_p (new_bb)
4587 && (succ = single_succ (new_bb))
4588 && succ != EXIT_BLOCK_PTR_FOR_FN (cfun)
4589 && DEBUG_INSN_P ((last = sel_bb_end (new_bb))))
4591 while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4592 insn = NEXT_INSN (insn);
4596 sel_global_bb_info_def gbi;
4597 sel_region_bb_info_def rbi;
4599 if (sched_verbose >= 2)
4600 sel_print ("Swapping block ids %i and %i\n",
4601 new_bb->index, succ->index);
4603 std::swap (new_bb->index, succ->index);
4605 SET_BASIC_BLOCK_FOR_FN (cfun, new_bb->index, new_bb);
4606 SET_BASIC_BLOCK_FOR_FN (cfun, succ->index, succ);
4608 memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi));
4609 memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ),
4611 memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi));
4613 memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi));
4614 memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ),
4616 memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi));
4618 std::swap (BLOCK_TO_BB (new_bb->index),
4619 BLOCK_TO_BB (succ->index));
4621 std::swap (CONTAINING_RGN (new_bb->index),
4622 CONTAINING_RGN (succ->index));
4624 for (int i = 0; i < current_nr_blocks; i++)
4625 if (BB_TO_BLOCK (i) == succ->index)
4626 BB_TO_BLOCK (i) = new_bb->index;
4627 else if (BB_TO_BLOCK (i) == new_bb->index)
4628 BB_TO_BLOCK (i) = succ->index;
4630 FOR_BB_INSNS (new_bb, insn)
4632 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index;
4634 FOR_BB_INSNS (succ, insn)
4636 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index;
4638 if (bitmap_clear_bit (code_motion_visited_blocks, new_bb->index))
4639 bitmap_set_bit (code_motion_visited_blocks, succ->index);
4641 gcc_assert (LABEL_P (BB_HEAD (new_bb))
4642 && LABEL_P (BB_HEAD (succ)));
4644 if (sched_verbose >= 4)
4645 sel_print ("Swapping code labels %i and %i\n",
4646 CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4647 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4649 std::swap (CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4650 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4658 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4659 into E2->dest, except from E1->src. If the returned insn immediately
4660 precedes a fence, assign that fence to *FENCE_TO_REWIND. */
4662 find_place_for_bookkeeping (edge e1, edge e2, fence_t *fence_to_rewind)
4664 insn_t place_to_insert;
4665 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4666 create new basic block, but insert bookkeeping there. */
4667 basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE);
4671 place_to_insert = BB_END (book_block);
4673 /* Don't use a block containing only debug insns for
4674 bookkeeping, this causes scheduling differences between debug
4675 and non-debug compilations, for the block would have been
4677 if (DEBUG_INSN_P (place_to_insert))
4679 rtx_insn *insn = sel_bb_head (book_block);
4681 while (insn != place_to_insert &&
4682 (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4683 insn = NEXT_INSN (insn);
4685 if (insn == place_to_insert)
4692 book_block = create_block_for_bookkeeping (e1, e2);
4693 place_to_insert = BB_END (book_block);
4694 if (sched_verbose >= 9)
4695 sel_print ("New block is %i, split from bookkeeping block %i\n",
4696 EDGE_SUCC (book_block, 0)->dest->index, book_block->index);
4700 if (sched_verbose >= 9)
4701 sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index);
4704 *fence_to_rewind = NULL;
4705 /* If basic block ends with a jump, insert bookkeeping code right before it.
4706 Notice if we are crossing a fence when taking PREV_INSN. */
4707 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4709 *fence_to_rewind = flist_lookup (fences, place_to_insert);
4710 place_to_insert = PREV_INSN (place_to_insert);
4713 return place_to_insert;
4716 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4719 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4723 /* Check if we are about to insert bookkeeping copy before a jump, and use
4724 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4725 rtx_insn *next = NEXT_INSN (place_to_insert);
4728 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4730 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4731 seqno = INSN_SEQNO (next);
4733 else if (INSN_SEQNO (join_point) > 0)
4734 seqno = INSN_SEQNO (join_point);
4737 seqno = get_seqno_by_preds (place_to_insert);
4739 /* Sometimes the fences can move in such a way that there will be
4740 no instructions with positive seqno around this bookkeeping.
4741 This means that there will be no way to get to it by a regular
4742 fence movement. Never mind because we pick up such pieces for
4743 rescheduling anyways, so any positive value will do for now. */
4746 gcc_assert (pipelining_p);
4751 gcc_assert (seqno > 0);
4755 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4756 NEW_SEQNO to it. Return created insn. */
4758 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4760 rtx_insn *new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4763 = create_vinsn_from_insn_rtx (new_insn_rtx,
4764 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4766 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4769 INSN_SCHED_TIMES (new_insn) = 0;
4770 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4775 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4776 E2->dest, except from E1->src (there may be a sequence of empty blocks
4777 between E1->src and E2->dest). Return block containing the copy.
4778 All scheduler data is initialized for the newly created insn. */
4780 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4782 insn_t join_point, place_to_insert, new_insn;
4784 bool need_to_exchange_data_sets;
4785 fence_t fence_to_rewind;
4787 if (sched_verbose >= 4)
4788 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4791 join_point = sel_bb_head (e2->dest);
4792 place_to_insert = find_place_for_bookkeeping (e1, e2, &fence_to_rewind);
4793 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4794 need_to_exchange_data_sets
4795 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4797 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4799 if (fence_to_rewind)
4800 FENCE_INSN (fence_to_rewind) = new_insn;
4802 /* When inserting bookkeeping insn in new block, av sets should be
4803 following: old basic block (that now holds bookkeeping) data sets are
4804 the same as was before generation of bookkeeping, and new basic block
4805 (that now hold all other insns of old basic block) data sets are
4806 invalid. So exchange data sets for these basic blocks as sel_split_block
4807 mistakenly exchanges them in this case. Cannot do it earlier because
4808 when single instruction is added to new basic block it should hold NULL
4810 if (need_to_exchange_data_sets)
4811 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4812 BLOCK_FOR_INSN (join_point));
4814 stat_bookkeeping_copies++;
4815 return BLOCK_FOR_INSN (new_insn);
4818 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4819 on FENCE, but we are unable to copy them. */
4821 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4826 /* An expression does not need bookkeeping if it is available on all paths
4827 from current block to original block and current block dominates
4828 original block. We check availability on all paths by examining
4829 EXPR_SPEC; this is not equivalent, because it may be positive even
4830 if expr is available on all paths (but if expr is not available on
4831 any path, EXPR_SPEC will be positive). */
4833 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4835 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4836 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4837 && (EXPR_SPEC (expr)
4838 || !EXPR_ORIG_BB_INDEX (expr)
4839 || !dominated_by_p (CDI_DOMINATORS,
4840 BASIC_BLOCK_FOR_FN (cfun,
4841 EXPR_ORIG_BB_INDEX (expr)),
4842 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4844 if (sched_verbose >= 4)
4845 sel_print ("Expr %d removed because it would need bookkeeping, which "
4846 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4847 av_set_iter_remove (&i);
4852 /* Moving conditional jump through some instructions.
4856 ... <- current scheduling point
4857 NOTE BASIC BLOCK: <- bb header
4858 (p8) add r14=r14+0x9;;
4864 We can schedule jump one cycle earlier, than mov, because they cannot be
4865 executed together as their predicates are mutually exclusive.
4867 This is done in this way: first, new fallthrough basic block is created
4868 after jump (it is always can be done, because there already should be a
4869 fallthrough block, where control flow goes in case of predicate being true -
4870 in our example; otherwise there should be a dependence between those
4871 instructions and jump and we cannot schedule jump right now);
4872 next, all instructions between jump and current scheduling point are moved
4873 to this new block. And the result is this:
4876 (!p8) jump L1 <- current scheduling point
4877 NOTE BASIC BLOCK: <- bb header
4878 (p8) add r14=r14+0x9;;
4884 move_cond_jump (rtx_insn *insn, bnd_t bnd)
4887 basic_block block_from, block_next, block_new, block_bnd, bb;
4888 rtx_insn *next, *prev, *link, *head;
4890 block_from = BLOCK_FOR_INSN (insn);
4891 block_bnd = BLOCK_FOR_INSN (BND_TO (bnd));
4892 prev = BND_TO (bnd);
4894 /* Moving of jump should not cross any other jumps or beginnings of new
4895 basic blocks. The only exception is when we move a jump through
4896 mutually exclusive insns along fallthru edges. */
4897 if (flag_checking && block_from != block_bnd)
4900 for (link = PREV_INSN (insn); link != PREV_INSN (prev);
4901 link = PREV_INSN (link))
4904 gcc_assert (sched_insns_conditions_mutex_p (insn, link));
4905 if (BLOCK_FOR_INSN (link) && BLOCK_FOR_INSN (link) != bb)
4907 gcc_assert (single_pred (bb) == BLOCK_FOR_INSN (link));
4908 bb = BLOCK_FOR_INSN (link);
4913 /* Jump is moved to the boundary. */
4914 next = PREV_INSN (insn);
4915 BND_TO (bnd) = insn;
4917 ft_edge = find_fallthru_edge_from (block_from);
4918 block_next = ft_edge->dest;
4919 /* There must be a fallthrough block (or where should go
4920 control flow in case of false jump predicate otherwise?). */
4921 gcc_assert (block_next);
4923 /* Create new empty basic block after source block. */
4924 block_new = sel_split_edge (ft_edge);
4925 gcc_assert (block_new->next_bb == block_next
4926 && block_from->next_bb == block_new);
4928 /* Move all instructions except INSN to BLOCK_NEW. */
4930 head = BB_HEAD (block_new);
4931 while (bb != block_from->next_bb)
4933 rtx_insn *from, *to;
4934 from = bb == block_bnd ? prev : sel_bb_head (bb);
4935 to = bb == block_from ? next : sel_bb_end (bb);
4937 /* The jump being moved can be the first insn in the block.
4938 In this case we don't have to move anything in this block. */
4939 if (NEXT_INSN (to) != from)
4941 reorder_insns (from, to, head);
4943 for (link = to; link != head; link = PREV_INSN (link))
4944 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
4948 /* Cleanup possibly empty blocks left. */
4949 block_next = bb->next_bb;
4950 if (bb != block_from)
4951 tidy_control_flow (bb, false);
4955 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4956 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
4958 gcc_assert (!sel_bb_empty_p (block_from)
4959 && !sel_bb_empty_p (block_new));
4961 /* Update data sets for BLOCK_NEW to represent that INSN and
4962 instructions from the other branch of INSN is no longer
4963 available at BLOCK_NEW. */
4964 BB_AV_LEVEL (block_new) = global_level;
4965 gcc_assert (BB_LV_SET (block_new) == NULL);
4966 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
4967 update_data_sets (sel_bb_head (block_new));
4969 /* INSN is a new basic block header - so prepare its data
4970 structures and update availability and liveness sets. */
4971 update_data_sets (insn);
4973 if (sched_verbose >= 4)
4974 sel_print ("Moving jump %d\n", INSN_UID (insn));
4977 /* Remove nops generated during move_op for preventing removal of empty
4980 remove_temp_moveop_nops (bool full_tidying)
4985 FOR_EACH_VEC_ELT (vec_temp_moveop_nops, i, insn)
4987 gcc_assert (INSN_NOP_P (insn));
4988 return_nop_to_pool (insn, full_tidying);
4991 /* Empty the vector. */
4992 if (vec_temp_moveop_nops.length () > 0)
4993 vec_temp_moveop_nops.block_remove (0, vec_temp_moveop_nops.length ());
4996 /* Records the maximal UID before moving up an instruction. Used for
4997 distinguishing between bookkeeping copies and original insns. */
4998 static int max_uid_before_move_op = 0;
5000 /* Remove from AV_VLIW_P all instructions but next when debug counter
5001 tells us so. Next instruction is fetched from BNDS. */
5003 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
5005 if (! dbg_cnt (sel_sched_insn_cnt))
5006 /* Leave only the next insn in av_vliw. */
5008 av_set_iterator av_it;
5010 bnd_t bnd = BLIST_BND (bnds);
5011 insn_t next = BND_TO (bnd);
5013 gcc_assert (BLIST_NEXT (bnds) == NULL);
5015 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
5016 if (EXPR_INSN_RTX (expr) != next)
5017 av_set_iter_remove (&av_it);
5021 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5022 the computed set to *AV_VLIW_P. */
5024 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
5026 if (sched_verbose >= 2)
5028 sel_print ("Boundaries: ");
5033 for (; bnds; bnds = BLIST_NEXT (bnds))
5035 bnd_t bnd = BLIST_BND (bnds);
5037 insn_t bnd_to = BND_TO (bnd);
5039 /* Rewind BND->TO to the basic block header in case some bookkeeping
5040 instructions were inserted before BND->TO and it needs to be
5042 if (sel_bb_head_p (bnd_to))
5043 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
5045 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
5047 bnd_to = PREV_INSN (bnd_to);
5048 if (sel_bb_head_p (bnd_to))
5052 if (BND_TO (bnd) != bnd_to)
5054 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
5055 FENCE_INSN (fence) = bnd_to;
5056 BND_TO (bnd) = bnd_to;
5059 av_set_clear (&BND_AV (bnd));
5060 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
5062 av_set_clear (&BND_AV1 (bnd));
5063 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
5065 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
5067 av1_copy = av_set_copy (BND_AV1 (bnd));
5068 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
5071 if (sched_verbose >= 2)
5073 sel_print ("Available exprs (vliw form): ");
5074 dump_av_set (*av_vliw_p);
5079 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5080 expression. When FOR_MOVEOP is true, also replace the register of
5081 expressions found with the register from EXPR_VLIW. */
5083 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
5085 av_set_t expr_seq = NULL;
5089 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
5091 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
5095 /* The sequential expression has the right form to pass
5096 to move_op except when renaming happened. Put the
5097 correct register in EXPR then. */
5098 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
5100 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
5102 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
5103 stat_renamed_scheduled++;
5105 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5106 This is needed when renaming came up with original
5108 else if (EXPR_TARGET_AVAILABLE (expr)
5109 != EXPR_TARGET_AVAILABLE (expr_vliw))
5111 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
5112 EXPR_TARGET_AVAILABLE (expr) = 1;
5115 if (EXPR_WAS_SUBSTITUTED (expr))
5116 stat_substitutions_total++;
5119 av_set_add (&expr_seq, expr);
5121 /* With substitution inside insn group, it is possible
5122 that more than one expression in expr_seq will correspond
5123 to expr_vliw. In this case, choose one as the attempt to
5124 move both leads to miscompiles. */
5129 if (for_moveop && sched_verbose >= 2)
5131 sel_print ("Best expression(s) (sequential form): ");
5132 dump_av_set (expr_seq);
5140 /* Move nop to previous block. */
5141 static void ATTRIBUTE_UNUSED
5142 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
5144 insn_t prev_insn, next_insn;
5146 gcc_assert (sel_bb_head_p (nop)
5147 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
5148 rtx_note *note = bb_note (BLOCK_FOR_INSN (nop));
5149 prev_insn = sel_bb_end (prev_bb);
5150 next_insn = NEXT_INSN (nop);
5151 gcc_assert (prev_insn != NULL_RTX
5152 && PREV_INSN (note) == prev_insn);
5154 SET_NEXT_INSN (prev_insn) = nop;
5155 SET_PREV_INSN (nop) = prev_insn;
5157 SET_PREV_INSN (note) = nop;
5158 SET_NEXT_INSN (note) = next_insn;
5160 SET_NEXT_INSN (nop) = note;
5161 SET_PREV_INSN (next_insn) = note;
5163 BB_END (prev_bb) = nop;
5164 BLOCK_FOR_INSN (nop) = prev_bb;
5167 /* Prepare a place to insert the chosen expression on BND. */
5169 prepare_place_to_insert (bnd_t bnd)
5171 insn_t place_to_insert;
5173 /* Init place_to_insert before calling move_op, as the later
5174 can possibly remove BND_TO (bnd). */
5175 if (/* If this is not the first insn scheduled. */
5178 /* Add it after last scheduled. */
5179 place_to_insert = ILIST_INSN (BND_PTR (bnd));
5180 if (DEBUG_INSN_P (place_to_insert))
5182 ilist_t l = BND_PTR (bnd);
5183 while ((l = ILIST_NEXT (l)) &&
5184 DEBUG_INSN_P (ILIST_INSN (l)))
5187 place_to_insert = NULL;
5191 place_to_insert = NULL;
5193 if (!place_to_insert)
5195 /* Add it before BND_TO. The difference is in the
5196 basic block, where INSN will be added. */
5197 place_to_insert = get_nop_from_pool (BND_TO (bnd));
5198 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
5199 == BLOCK_FOR_INSN (BND_TO (bnd)));
5202 return place_to_insert;
5205 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5206 Return the expression to emit in C_EXPR. */
5208 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5209 av_set_t expr_seq, expr_t c_expr)
5211 bool b, should_move;
5214 int n_bookkeeping_copies_before_moveop;
5216 /* Make a move. This call will remove the original operation,
5217 insert all necessary bookkeeping instructions and update the
5218 data sets. After that all we have to do is add the operation
5219 at before BND_TO (BND). */
5220 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5221 max_uid_before_move_op = get_max_uid ();
5222 bitmap_clear (current_copies);
5223 bitmap_clear (current_originators);
5225 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5226 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5228 /* We should be able to find the expression we've chosen for
5232 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5233 stat_insns_needed_bookkeeping++;
5235 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5240 /* We allocate these bitmaps lazily. */
5241 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5242 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5244 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5245 current_originators);
5247 /* Transitively add all originators' originators. */
5248 EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi)
5249 if (INSN_ORIGINATORS_BY_UID (uid))
5250 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid),
5251 INSN_ORIGINATORS_BY_UID (uid));
5258 /* Debug a DFA state as an array of bytes. */
5260 debug_state (state_t state)
5263 unsigned int i, size = dfa_state_size;
5265 sel_print ("state (%u):", size);
5266 for (i = 0, p = (unsigned char *) state; i < size; i++)
5267 sel_print (" %d", p[i]);
5271 /* Advance state on FENCE with INSN. Return true if INSN is
5272 an ASM, and we should advance state once more. */
5274 advance_state_on_fence (fence_t fence, insn_t insn)
5278 if (recog_memoized (insn) >= 0)
5281 state_t temp_state = alloca (dfa_state_size);
5283 gcc_assert (!INSN_ASM_P (insn));
5286 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5287 res = state_transition (FENCE_STATE (fence), insn);
5288 gcc_assert (res < 0);
5290 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5292 FENCE_ISSUED_INSNS (fence)++;
5294 /* We should never issue more than issue_rate insns. */
5295 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5301 /* This could be an ASM insn which we'd like to schedule
5302 on the next cycle. */
5303 asm_p = INSN_ASM_P (insn);
5304 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5305 advance_one_cycle (fence);
5308 if (sched_verbose >= 2)
5309 debug_state (FENCE_STATE (fence));
5310 if (!DEBUG_INSN_P (insn))
5311 FENCE_STARTS_CYCLE_P (fence) = 0;
5312 FENCE_ISSUE_MORE (fence) = can_issue_more;
5316 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5317 is nonzero if we need to stall after issuing INSN. */
5319 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5323 /* First, reflect that something is scheduled on this fence. */
5324 asm_p = advance_state_on_fence (fence, insn);
5325 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5326 vec_safe_push (FENCE_EXECUTING_INSNS (fence), insn);
5327 if (SCHED_GROUP_P (insn))
5329 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5330 SCHED_GROUP_P (insn) = 0;
5333 FENCE_SCHED_NEXT (fence) = NULL;
5334 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5335 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5337 /* Set instruction scheduling info. This will be used in bundling,
5338 pipelining, tick computations etc. */
5339 ++INSN_SCHED_TIMES (insn);
5340 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5341 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5342 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5343 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5345 /* This does not account for adjust_cost hooks, just add the biggest
5346 constant the hook may add to the latency. TODO: make this
5347 a target dependent constant. */
5348 INSN_READY_CYCLE (insn)
5349 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5351 : maximal_insn_latency (insn) + 1);
5353 /* Change these fields last, as they're used above. */
5354 FENCE_AFTER_STALL_P (fence) = 0;
5355 if (asm_p || need_stall)
5356 advance_one_cycle (fence);
5358 /* Indicate that we've scheduled something on this fence. */
5359 FENCE_SCHEDULED_P (fence) = true;
5360 scheduled_something_on_previous_fence = true;
5362 /* Print debug information when insn's fields are updated. */
5363 if (sched_verbose >= 2)
5365 sel_print ("Scheduling insn: ");
5366 dump_insn_1 (insn, 1);
5371 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5372 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5375 update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp,
5376 blist_t *bnds_tailp)
5381 advance_deps_context (BND_DC (bnd), insn);
5382 FOR_EACH_SUCC_1 (succ, si, insn,
5383 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5385 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5387 ilist_add (&ptr, insn);
5389 if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn)
5390 && is_ineligible_successor (succ, ptr))
5396 if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn))
5398 if (sched_verbose >= 9)
5399 sel_print ("Updating fence insn from %i to %i\n",
5400 INSN_UID (insn), INSN_UID (succ));
5401 FENCE_INSN (fence) = succ;
5403 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5404 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5407 blist_remove (bndsp);
5411 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5413 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5416 expr_t c_expr = XALLOCA (expr_def);
5417 insn_t place_to_insert;
5421 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5423 /* In case of scheduling a jump skipping some other instructions,
5424 prepare CFG. After this, jump is at the boundary and can be
5425 scheduled as usual insn by MOVE_OP. */
5426 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5428 insn = EXPR_INSN_RTX (expr_vliw);
5430 /* Speculative jumps are not handled. */
5431 if (insn != BND_TO (bnd)
5432 && !sel_insn_is_speculation_check (insn))
5433 move_cond_jump (insn, bnd);
5436 /* Find a place for C_EXPR to schedule. */
5437 place_to_insert = prepare_place_to_insert (bnd);
5438 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5439 clear_expr (c_expr);
5441 /* Add the instruction. The corner case to care about is when
5442 the expr_seq set has more than one expr, and we chose the one that
5443 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5444 we can't use it. Generate the new vinsn. */
5445 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5449 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5450 change_vinsn_in_expr (expr_vliw, vinsn_new);
5451 should_move = false;
5454 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5456 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5459 /* Return the nops generated for preserving of data sets back
5461 if (INSN_NOP_P (place_to_insert))
5462 return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn));
5463 remove_temp_moveop_nops (!DEBUG_INSN_P (insn));
5465 av_set_clear (&expr_seq);
5467 /* Save the expression scheduled so to reset target availability if we'll
5468 meet it later on the same fence. */
5469 if (EXPR_WAS_RENAMED (expr_vliw))
5470 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5472 /* Check that the recent movement didn't destroyed loop
5474 gcc_assert (!pipelining_p
5475 || current_loop_nest == NULL
5476 || loop_latch_edge (current_loop_nest));
5480 /* Stall for N cycles on FENCE. */
5482 stall_for_cycles (fence_t fence, int n)
5486 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5488 advance_one_cycle (fence);
5490 FENCE_AFTER_STALL_P (fence) = 1;
5493 /* Gather a parallel group of insns at FENCE and assign their seqno
5494 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5495 list for later recalculation of seqnos. */
5497 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5499 blist_t bnds = NULL, *bnds_tailp;
5500 av_set_t av_vliw = NULL;
5501 insn_t insn = FENCE_INSN (fence);
5503 if (sched_verbose >= 2)
5504 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5505 INSN_UID (insn), FENCE_CYCLE (fence));
5507 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5508 bnds_tailp = &BLIST_NEXT (bnds);
5509 set_target_context (FENCE_TC (fence));
5510 can_issue_more = FENCE_ISSUE_MORE (fence);
5511 target_bb = INSN_BB (insn);
5513 /* Do while we can add any operation to the current group. */
5516 blist_t *bnds_tailp1, *bndsp;
5518 int need_stall = false;
5519 int was_stall = 0, scheduled_insns = 0;
5520 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5521 int max_stall = pipelining_p ? 1 : 3;
5522 bool last_insn_was_debug = false;
5523 bool was_debug_bb_end_p = false;
5525 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5526 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5527 remove_insns_for_debug (bnds, &av_vliw);
5529 /* Return early if we have nothing to schedule. */
5530 if (av_vliw == NULL)
5533 /* Choose the best expression and, if needed, destination register
5537 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5538 if (! expr_vliw && need_stall)
5540 /* All expressions required a stall. Do not recompute av sets
5541 as we'll get the same answer (modulo the insns between
5542 the fence and its boundary, which will not be available for
5544 If we are going to stall for too long, break to recompute av
5545 sets and bring more insns for pipelining. */
5547 if (need_stall <= 3)
5548 stall_for_cycles (fence, need_stall);
5551 stall_for_cycles (fence, 1);
5556 while (! expr_vliw && need_stall);
5558 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5561 av_set_clear (&av_vliw);
5566 bnds_tailp1 = bnds_tailp;
5569 /* This code will be executed only once until we'd have several
5570 boundaries per fence. */
5572 bnd_t bnd = BLIST_BND (*bndsp);
5574 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5576 bndsp = &BLIST_NEXT (*bndsp);
5580 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5581 last_insn_was_debug = DEBUG_INSN_P (insn);
5582 if (last_insn_was_debug)
5583 was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn));
5584 update_fence_and_insn (fence, insn, need_stall);
5585 bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp);
5587 /* Add insn to the list of scheduled on this cycle instructions. */
5588 ilist_add (*scheduled_insns_tailpp, insn);
5589 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5591 while (*bndsp != *bnds_tailp1);
5593 av_set_clear (&av_vliw);
5594 if (!last_insn_was_debug)
5597 /* We currently support information about candidate blocks only for
5598 one 'target_bb' block. Hence we can't schedule after jump insn,
5599 as this will bring two boundaries and, hence, necessity to handle
5600 information for two or more blocks concurrently. */
5601 if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn))
5603 && (was_stall >= max_stall
5604 || scheduled_insns >= max_insns)))
5609 gcc_assert (!FENCE_BNDS (fence));
5611 /* Update boundaries of the FENCE. */
5614 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5618 insn = ILIST_INSN (ptr);
5620 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5621 ilist_add (&FENCE_BNDS (fence), insn);
5624 blist_remove (&bnds);
5627 /* Update target context on the fence. */
5628 reset_target_context (FENCE_TC (fence), false);
5631 /* All exprs in ORIG_OPS must have the same destination register or memory.
5632 Return that destination. */
5634 get_dest_from_orig_ops (av_set_t orig_ops)
5636 rtx dest = NULL_RTX;
5637 av_set_iterator av_it;
5639 bool first_p = true;
5641 FOR_EACH_EXPR (expr, av_it, orig_ops)
5643 rtx x = EXPR_LHS (expr);
5651 gcc_assert (dest == x
5652 || (dest != NULL_RTX && x != NULL_RTX
5653 && rtx_equal_p (dest, x)));
5659 /* Update data sets for the bookkeeping block and record those expressions
5660 which become no longer available after inserting this bookkeeping. */
5662 update_and_record_unavailable_insns (basic_block book_block)
5665 av_set_t old_av_set = NULL;
5667 rtx_insn *bb_end = sel_bb_end (book_block);
5669 /* First, get correct liveness in the bookkeeping block. The problem is
5670 the range between the bookeeping insn and the end of block. */
5671 update_liveness_on_insn (bb_end);
5672 if (control_flow_insn_p (bb_end))
5673 update_liveness_on_insn (PREV_INSN (bb_end));
5675 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5676 fence above, where we may choose to schedule an insn which is
5677 actually blocked from moving up with the bookkeeping we create here. */
5678 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5680 old_av_set = av_set_copy (BB_AV_SET (book_block));
5681 update_data_sets (sel_bb_head (book_block));
5683 /* Traverse all the expressions in the old av_set and check whether
5684 CUR_EXPR is in new AV_SET. */
5685 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5687 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5688 EXPR_VINSN (cur_expr));
5691 /* In this case, we can just turn off the E_T_A bit, but we can't
5692 represent this information with the current vector. */
5693 || EXPR_TARGET_AVAILABLE (new_expr)
5694 != EXPR_TARGET_AVAILABLE (cur_expr))
5695 /* Unfortunately, the below code could be also fired up on
5696 separable insns, e.g. when moving insns through the new
5697 speculation check as in PR 53701. */
5698 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5701 av_set_clear (&old_av_set);
5705 /* The main effect of this function is that sparams->c_expr is merged
5706 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5707 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5708 lparams->c_expr_merged is copied back to sparams->c_expr after all
5709 successors has been traversed. lparams->c_expr_local is an expr allocated
5710 on stack in the caller function, and is used if there is more than one
5713 SUCC is one of the SUCCS_NORMAL successors of INSN,
5714 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5715 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5717 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5718 insn_t succ ATTRIBUTE_UNUSED,
5719 int moveop_drv_call_res,
5720 cmpd_local_params_p lparams, void *static_params)
5722 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5724 /* Nothing to do, if original expr wasn't found below. */
5725 if (moveop_drv_call_res != 1)
5728 /* If this is a first successor. */
5729 if (!lparams->c_expr_merged)
5731 lparams->c_expr_merged = sparams->c_expr;
5732 sparams->c_expr = lparams->c_expr_local;
5736 /* We must merge all found expressions to get reasonable
5737 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5738 do so then we can first find the expr with epsilon
5739 speculation success probability and only then with the
5740 good probability. As a result the insn will get epsilon
5741 probability and will never be scheduled because of
5742 weakness_cutoff in find_best_expr.
5744 We call merge_expr_data here instead of merge_expr
5745 because due to speculation C_EXPR and X may have the
5746 same insns with different speculation types. And as of
5747 now such insns are considered non-equal.
5749 However, EXPR_SCHED_TIMES is different -- we must get
5750 SCHED_TIMES from a real insn, not a bookkeeping copy.
5751 We force this here. Instead, we may consider merging
5752 SCHED_TIMES to the maximum instead of minimum in the
5754 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5756 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5757 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5758 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5760 clear_expr (sparams->c_expr);
5764 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5766 SUCC is one of the SUCCS_NORMAL successors of INSN,
5767 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5768 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5769 STATIC_PARAMS contain USED_REGS set. */
5771 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5772 int moveop_drv_call_res,
5773 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5774 void *static_params)
5777 fur_static_params_p sparams = (fur_static_params_p) static_params;
5779 /* Here we compute live regsets only for branches that do not lie
5780 on the code motion paths. These branches correspond to value
5781 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5782 for such branches code_motion_path_driver is not called. */
5783 if (moveop_drv_call_res != 0)
5786 /* Mark all registers that do not meet the following condition:
5787 (3) not live on the other path of any conditional branch
5788 that is passed by the operation, in case original
5789 operations are not present on both paths of the
5790 conditional branch. */
5791 succ_live = compute_live (succ);
5792 IOR_REG_SET (sparams->used_regs, succ_live);
5795 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5798 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5800 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5802 sp->c_expr = lp->c_expr_merged;
5805 /* Track bookkeeping copies created, insns scheduled, and blocks for
5806 rescheduling when INSN is found by move_op. */
5808 track_scheduled_insns_and_blocks (rtx_insn *insn)
5810 /* Even if this insn can be a copy that will be removed during current move_op,
5811 we still need to count it as an originator. */
5812 bitmap_set_bit (current_originators, INSN_UID (insn));
5814 if (!bitmap_clear_bit (current_copies, INSN_UID (insn)))
5816 /* Note that original block needs to be rescheduled, as we pulled an
5817 instruction out of it. */
5818 if (INSN_SCHED_TIMES (insn) > 0)
5819 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5820 else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn))
5821 num_insns_scheduled++;
5824 /* For instructions we must immediately remove insn from the
5825 stream, so subsequent update_data_sets () won't include this
5827 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5828 if (INSN_UID (insn) > max_uid_before_move_op)
5829 stat_bookkeeping_copies--;
5832 /* Emit a register-register copy for INSN if needed. Return true if
5833 emitted one. PARAMS is the move_op static parameters. */
5835 maybe_emit_renaming_copy (rtx_insn *insn,
5836 moveop_static_params_p params)
5838 bool insn_emitted = false;
5841 /* Bail out early when expression can not be renamed at all. */
5842 if (!EXPR_SEPARABLE_P (params->c_expr))
5845 cur_reg = expr_dest_reg (params->c_expr);
5846 gcc_assert (cur_reg && params->dest && REG_P (params->dest));
5848 /* If original operation has expr and the register chosen for
5849 that expr is not original operation's dest reg, substitute
5850 operation's right hand side with the register chosen. */
5851 if (REGNO (params->dest) != REGNO (cur_reg))
5853 insn_t reg_move_insn, reg_move_insn_rtx;
5855 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5857 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5861 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5862 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5864 insn_emitted = true;
5865 params->was_renamed = true;
5868 return insn_emitted;
5871 /* Emit a speculative check for INSN speculated as EXPR if needed.
5872 Return true if we've emitted one. PARAMS is the move_op static
5875 maybe_emit_speculative_check (rtx_insn *insn, expr_t expr,
5876 moveop_static_params_p params)
5878 bool insn_emitted = false;
5882 check_ds = get_spec_check_type_for_insn (insn, expr);
5885 /* A speculation check should be inserted. */
5886 x = create_speculation_check (params->c_expr, check_ds, insn);
5887 insn_emitted = true;
5891 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5895 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5896 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5897 return insn_emitted;
5900 /* Handle transformations that leave an insn in place of original
5901 insn such as renaming/speculation. Return true if one of such
5902 transformations actually happened, and we have emitted this insn. */
5904 handle_emitting_transformations (rtx_insn *insn, expr_t expr,
5905 moveop_static_params_p params)
5907 bool insn_emitted = false;
5909 insn_emitted = maybe_emit_renaming_copy (insn, params);
5910 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5912 return insn_emitted;
5915 /* If INSN is the only insn in the basic block (not counting JUMP,
5916 which may be a jump to next insn, and DEBUG_INSNs), we want to
5917 leave a NOP there till the return to fill_insns. */
5920 need_nop_to_preserve_insn_bb (rtx_insn *insn)
5922 insn_t bb_head, bb_end, bb_next, in_next;
5923 basic_block bb = BLOCK_FOR_INSN (insn);
5925 bb_head = sel_bb_head (bb);
5926 bb_end = sel_bb_end (bb);
5928 if (bb_head == bb_end)
5931 while (bb_head != bb_end && DEBUG_INSN_P (bb_head))
5932 bb_head = NEXT_INSN (bb_head);
5934 if (bb_head == bb_end)
5937 while (bb_head != bb_end && DEBUG_INSN_P (bb_end))
5938 bb_end = PREV_INSN (bb_end);
5940 if (bb_head == bb_end)
5943 bb_next = NEXT_INSN (bb_head);
5944 while (bb_next != bb_end && DEBUG_INSN_P (bb_next))
5945 bb_next = NEXT_INSN (bb_next);
5947 if (bb_next == bb_end && JUMP_P (bb_end))
5950 in_next = NEXT_INSN (insn);
5951 while (DEBUG_INSN_P (in_next))
5952 in_next = NEXT_INSN (in_next);
5954 if (IN_CURRENT_FENCE_P (in_next))
5960 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5961 is not removed but reused when INSN is re-emitted. */
5963 remove_insn_from_stream (rtx_insn *insn, bool only_disconnect)
5965 /* If there's only one insn in the BB, make sure that a nop is
5966 inserted into it, so the basic block won't disappear when we'll
5967 delete INSN below with sel_remove_insn. It should also survive
5968 till the return to fill_insns. */
5969 if (need_nop_to_preserve_insn_bb (insn))
5971 insn_t nop = get_nop_from_pool (insn);
5972 gcc_assert (INSN_NOP_P (nop));
5973 vec_temp_moveop_nops.safe_push (nop);
5976 sel_remove_insn (insn, only_disconnect, false);
5979 /* This function is called when original expr is found.
5980 INSN - current insn traversed, EXPR - the corresponding expr found.
5981 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5982 is static parameters of move_op. */
5984 move_op_orig_expr_found (insn_t insn, expr_t expr,
5985 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5986 void *static_params)
5988 bool only_disconnect;
5989 moveop_static_params_p params = (moveop_static_params_p) static_params;
5991 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
5992 track_scheduled_insns_and_blocks (insn);
5993 handle_emitting_transformations (insn, expr, params);
5994 only_disconnect = params->uid == INSN_UID (insn);
5996 /* Mark that we've disconnected an insn. */
5997 if (only_disconnect)
5999 remove_insn_from_stream (insn, only_disconnect);
6002 /* The function is called when original expr is found.
6003 INSN - current insn traversed, EXPR - the corresponding expr found,
6004 crosses_call and original_insns in STATIC_PARAMS are updated. */
6006 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
6007 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6008 void *static_params)
6010 fur_static_params_p params = (fur_static_params_p) static_params;
6014 params->crosses_call = true;
6016 def_list_add (params->original_insns, insn, params->crosses_call);
6018 /* Mark the registers that do not meet the following condition:
6019 (2) not among the live registers of the point
6020 immediately following the first original operation on
6021 a given downward path, except for the original target
6022 register of the operation. */
6023 tmp = get_clear_regset_from_pool ();
6024 compute_live_below_insn (insn, tmp);
6025 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
6026 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
6027 IOR_REG_SET (params->used_regs, tmp);
6028 return_regset_to_pool (tmp);
6030 /* (*1) We need to add to USED_REGS registers that are read by
6031 INSN's lhs. This may lead to choosing wrong src register.
6032 E.g. (scheduling const expr enabled):
6034 429: ax=0x0 <- Can't use AX for this expr (0x0)
6041 /* FIXME: see comment above and enable MEM_P
6042 in vinsn_separable_p. */
6043 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
6044 || !MEM_P (INSN_LHS (insn)));
6047 /* This function is called on the ascending pass, before returning from
6048 current basic block. */
6050 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
6051 void *static_params)
6053 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6054 basic_block book_block = NULL;
6056 /* When we have removed the boundary insn for scheduling, which also
6057 happened to be the end insn in its bb, we don't need to update sets. */
6058 if (!lparams->removed_last_insn
6060 && sel_bb_head_p (insn))
6062 /* We should generate bookkeeping code only if we are not at the
6063 top level of the move_op. */
6064 if (sel_num_cfg_preds_gt_1 (insn))
6065 book_block = generate_bookkeeping_insn (sparams->c_expr,
6066 lparams->e1, lparams->e2);
6067 /* Update data sets for the current insn. */
6068 update_data_sets (insn);
6071 /* If bookkeeping code was inserted, we need to update av sets of basic
6072 block that received bookkeeping. After generation of bookkeeping insn,
6073 bookkeeping block does not contain valid av set because we are not following
6074 the original algorithm in every detail with regards to e.g. renaming
6075 simple reg-reg copies. Consider example:
6077 bookkeeping block scheduling fence
6087 We try to schedule insn "r1 := r3" on the current
6088 scheduling fence. Also, note that av set of bookkeeping block
6089 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6090 been scheduled, the CFG is as follows:
6093 bookkeeping block scheduling fence
6103 Here, insn "r1 := r3" was scheduled at the current scheduling point
6104 and bookkeeping code was generated at the bookeeping block. This
6105 way insn "r1 := r2" is no longer available as a whole instruction
6106 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6107 This situation is handled by calling update_data_sets.
6109 Since update_data_sets is called only on the bookkeeping block, and
6110 it also may have predecessors with av_sets, containing instructions that
6111 are no longer available, we save all such expressions that become
6112 unavailable during data sets update on the bookkeeping block in
6113 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6114 expressions for scheduling. This allows us to avoid recomputation of
6115 av_sets outside the code motion path. */
6118 update_and_record_unavailable_insns (book_block);
6120 /* If INSN was previously marked for deletion, it's time to do it. */
6121 if (lparams->removed_last_insn)
6122 insn = PREV_INSN (insn);
6124 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6125 kill a block with a single nop in which the insn should be emitted. */
6127 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
6130 /* This function is called on the ascending pass, before returning from the
6131 current basic block. */
6133 fur_at_first_insn (insn_t insn,
6134 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6135 void *static_params ATTRIBUTE_UNUSED)
6137 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
6138 || AV_LEVEL (insn) == -1);
6141 /* Called on the backward stage of recursion to call moveup_expr for insn
6142 and sparams->c_expr. */
6144 move_op_ascend (insn_t insn, void *static_params)
6146 enum MOVEUP_EXPR_CODE res;
6147 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6149 if (! INSN_NOP_P (insn))
6151 res = moveup_expr_cached (sparams->c_expr, insn, false);
6152 gcc_assert (res != MOVEUP_EXPR_NULL);
6155 /* Update liveness for this insn as it was invalidated. */
6156 update_liveness_on_insn (insn);
6159 /* This function is called on enter to the basic block.
6160 Returns TRUE if this block already have been visited and
6161 code_motion_path_driver should return 1, FALSE otherwise. */
6163 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
6164 void *static_params, bool visited_p)
6166 fur_static_params_p sparams = (fur_static_params_p) static_params;
6170 /* If we have found something below this block, there should be at
6171 least one insn in ORIGINAL_INSNS. */
6172 gcc_assert (*sparams->original_insns);
6174 /* Adjust CROSSES_CALL, since we may have come to this block along
6176 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
6177 |= sparams->crosses_call;
6180 local_params->old_original_insns = *sparams->original_insns;
6185 /* Same as above but for move_op. */
6187 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
6188 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
6189 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
6196 /* This function is called while descending current basic block if current
6197 insn is not the original EXPR we're searching for.
6199 Return value: FALSE, if code_motion_path_driver should perform a local
6200 cleanup and return 0 itself;
6201 TRUE, if code_motion_path_driver should continue. */
6203 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
6204 void *static_params)
6206 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6208 sparams->failed_insn = insn;
6210 /* If we're scheduling separate expr, in order to generate correct code
6211 we need to stop the search at bookkeeping code generated with the
6212 same destination register or memory. */
6213 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
6218 /* This function is called while descending current basic block if current
6219 insn is not the original EXPR we're searching for.
6221 Return value: TRUE (code_motion_path_driver should continue). */
6223 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
6227 av_set_iterator avi;
6228 fur_static_params_p sparams = (fur_static_params_p) static_params;
6231 sparams->crosses_call = true;
6232 else if (DEBUG_INSN_P (insn))
6235 /* If current insn we are looking at cannot be executed together
6236 with original insn, then we can skip it safely.
6238 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6239 INSN = (!p6) r14 = r14 + 1;
6241 Here we can schedule ORIG_OP with lhs = r14, though only
6242 looking at the set of used and set registers of INSN we must
6243 forbid it. So, add set/used in INSN registers to the
6244 untouchable set only if there is an insn in ORIG_OPS that can
6247 FOR_EACH_EXPR (r, avi, orig_ops)
6248 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
6254 /* Mark all registers that do not meet the following condition:
6255 (1) Not set or read on any path from xi to an instance of the
6256 original operation. */
6259 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6260 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6261 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6267 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6268 struct code_motion_path_driver_info_def move_op_hooks = {
6270 move_op_orig_expr_found,
6271 move_op_orig_expr_not_found,
6272 move_op_merge_succs,
6273 move_op_after_merge_succs,
6275 move_op_at_first_insn,
6280 /* Hooks and data to perform find_used_regs operations
6281 with code_motion_path_driver. */
6282 struct code_motion_path_driver_info_def fur_hooks = {
6284 fur_orig_expr_found,
6285 fur_orig_expr_not_found,
6287 NULL, /* fur_after_merge_succs */
6288 NULL, /* fur_ascend */
6294 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6295 code_motion_path_driver is called recursively. Original operation
6296 was found at least on one path that is starting with one of INSN's
6297 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6298 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6299 of either move_op or find_used_regs depending on the caller.
6301 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6302 know for sure at this point. */
6304 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6305 ilist_t path, void *static_params)
6308 succ_iterator succ_i;
6314 struct cmpd_local_params lparams;
6317 lparams.c_expr_local = &_x;
6318 lparams.c_expr_merged = NULL;
6320 /* We need to process only NORMAL succs for move_op, and collect live
6321 registers from ALL branches (including those leading out of the
6322 region) for find_used_regs.
6324 In move_op, there can be a case when insn's bb number has changed
6325 due to created bookkeeping. This happens very rare, as we need to
6326 move expression from the beginning to the end of the same block.
6327 Rescan successors in this case. */
6330 bb = BLOCK_FOR_INSN (insn);
6331 old_index = bb->index;
6332 old_succs = EDGE_COUNT (bb->succs);
6334 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6338 lparams.e1 = succ_i.e1;
6339 lparams.e2 = succ_i.e2;
6341 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6343 if (succ_i.current_flags == SUCCS_NORMAL)
6344 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6349 /* Merge c_expres found or unify live register sets from different
6351 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6355 else if (b == -1 && res != 1)
6358 /* We have simplified the control flow below this point. In this case,
6359 the iterator becomes invalid. We need to try again.
6360 If we have removed the insn itself, it could be only an
6361 unconditional jump. Thus, do not rescan but break immediately --
6362 we have already visited the only successor block. */
6363 if (!BLOCK_FOR_INSN (insn))
6365 if (sched_verbose >= 6)
6366 sel_print ("Not doing rescan: already visited the only successor"
6367 " of block %d\n", old_index);
6370 if (BLOCK_FOR_INSN (insn)->index != old_index
6371 || EDGE_COUNT (bb->succs) != old_succs)
6373 if (sched_verbose >= 6)
6374 sel_print ("Rescan: CFG was simplified below insn %d, block %d\n",
6375 INSN_UID (insn), BLOCK_FOR_INSN (insn)->index);
6376 insn = sel_bb_end (BLOCK_FOR_INSN (insn));
6381 /* Here, RES==1 if original expr was found at least for one of the
6382 successors. After the loop, RES may happen to have zero value
6383 only if at some point the expr searched is present in av_set, but is
6384 not found below. In most cases, this situation is an error.
6385 The exception is when the original operation is blocked by
6386 bookkeeping generated for another fence or for another path in current
6388 gcc_checking_assert (res == 1
6390 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops, static_params))
6393 /* Merge data, clean up, etc. */
6394 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6395 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6401 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6402 is the pointer to the av set with expressions we were looking for,
6403 PATH_P is the pointer to the traversed path. */
6405 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6407 ilist_remove (path_p);
6408 av_set_clear (orig_ops_p);
6411 /* The driver function that implements move_op or find_used_regs
6412 functionality dependent whether code_motion_path_driver_INFO is set to
6413 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6414 of code (CFG traversal etc) that are shared among both functions. INSN
6415 is the insn we're starting the search from, ORIG_OPS are the expressions
6416 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6417 parameters of the driver, and STATIC_PARAMS are static parameters of
6420 Returns whether original instructions were found. Note that top-level
6421 code_motion_path_driver always returns true. */
6423 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6424 cmpd_local_params_p local_params_in,
6425 void *static_params)
6428 basic_block bb = BLOCK_FOR_INSN (insn);
6429 insn_t first_insn, bb_tail, before_first;
6430 bool removed_last_insn = false;
6432 if (sched_verbose >= 6)
6434 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6437 dump_av_set (orig_ops);
6441 gcc_assert (orig_ops);
6443 /* If no original operations exist below this insn, return immediately. */
6444 if (is_ineligible_successor (insn, path))
6446 if (sched_verbose >= 6)
6447 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6451 /* The block can have invalid av set, in which case it was created earlier
6452 during move_op. Return immediately. */
6453 if (sel_bb_head_p (insn))
6455 if (! AV_SET_VALID_P (insn))
6457 if (sched_verbose >= 6)
6458 sel_print ("Returned from block %d as it had invalid av set\n",
6463 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6465 /* We have already found an original operation on this branch, do not
6466 go any further and just return TRUE here. If we don't stop here,
6467 function can have exponential behavior even on the small code
6468 with many different paths (e.g. with data speculation and
6469 recovery blocks). */
6470 if (sched_verbose >= 6)
6471 sel_print ("Block %d already visited in this traversal\n", bb->index);
6472 if (code_motion_path_driver_info->on_enter)
6473 return code_motion_path_driver_info->on_enter (insn,
6480 if (code_motion_path_driver_info->on_enter)
6481 code_motion_path_driver_info->on_enter (insn, local_params_in,
6482 static_params, false);
6483 orig_ops = av_set_copy (orig_ops);
6485 /* Filter the orig_ops set. */
6486 if (AV_SET_VALID_P (insn))
6487 av_set_code_motion_filter (&orig_ops, AV_SET (insn));
6489 /* If no more original ops, return immediately. */
6492 if (sched_verbose >= 6)
6493 sel_print ("No intersection with av set of block %d\n", bb->index);
6497 /* For non-speculative insns we have to leave only one form of the
6498 original operation, because if we don't, we may end up with
6499 different C_EXPRes and, consequently, with bookkeepings for different
6500 expression forms along the same code motion path. That may lead to
6501 generation of incorrect code. So for each code motion we stick to
6502 the single form of the instruction, except for speculative insns
6503 which we need to keep in different forms with all speculation
6505 av_set_leave_one_nonspec (&orig_ops);
6507 /* It is not possible that all ORIG_OPS are filtered out. */
6508 gcc_assert (orig_ops);
6510 /* It is enough to place only heads and tails of visited basic blocks into
6512 ilist_add (&path, insn);
6514 bb_tail = sel_bb_end (bb);
6516 /* Descend the basic block in search of the original expr; this part
6517 corresponds to the part of the original move_op procedure executed
6518 before the recursive call. */
6521 /* Look at the insn and decide if it could be an ancestor of currently
6522 scheduling operation. If it is so, then the insn "dest = op" could
6523 either be replaced with "dest = reg", because REG now holds the result
6524 of OP, or just removed, if we've scheduled the insn as a whole.
6526 If this insn doesn't contain currently scheduling OP, then proceed
6527 with searching and look at its successors. Operations we're searching
6528 for could have changed when moving up through this insn via
6529 substituting. In this case, perform unsubstitution on them first.
6531 When traversing the DAG below this insn is finished, insert
6532 bookkeeping code, if the insn is a joint point, and remove
6535 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6538 insn_t last_insn = PREV_INSN (insn);
6540 /* We have found the original operation. */
6541 if (sched_verbose >= 6)
6542 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6544 code_motion_path_driver_info->orig_expr_found
6545 (insn, expr, local_params_in, static_params);
6547 /* Step back, so on the way back we'll start traversing from the
6548 previous insn (or we'll see that it's bb_note and skip that
6550 if (insn == first_insn)
6552 first_insn = NEXT_INSN (last_insn);
6553 removed_last_insn = sel_bb_end_p (last_insn);
6560 /* We haven't found the original expr, continue descending the basic
6562 if (code_motion_path_driver_info->orig_expr_not_found
6563 (insn, orig_ops, static_params))
6565 /* Av set ops could have been changed when moving through this
6566 insn. To find them below it, we have to un-substitute them. */
6567 undo_transformations (&orig_ops, insn);
6571 /* Clean up and return, if the hook tells us to do so. It may
6572 happen if we've encountered the previously created
6574 code_motion_path_driver_cleanup (&orig_ops, &path);
6578 gcc_assert (orig_ops);
6581 /* Stop at insn if we got to the end of BB. */
6582 if (insn == bb_tail)
6585 insn = NEXT_INSN (insn);
6588 /* Here INSN either points to the insn before the original insn (may be
6589 bb_note, if original insn was a bb_head) or to the bb_end. */
6593 rtx_insn *last_insn = PREV_INSN (insn);
6596 gcc_assert (insn == sel_bb_end (bb));
6598 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6599 it's already in PATH then). */
6600 if (insn != first_insn)
6602 ilist_add (&path, insn);
6603 added_to_path = true;
6606 added_to_path = false;
6608 /* Process_successors should be able to find at least one
6609 successor for which code_motion_path_driver returns TRUE. */
6610 res = code_motion_process_successors (insn, orig_ops,
6611 path, static_params);
6613 /* Jump in the end of basic block could have been removed or replaced
6614 during code_motion_process_successors, so recompute insn as the
6616 if (NEXT_INSN (last_insn) != insn)
6618 insn = sel_bb_end (bb);
6619 first_insn = sel_bb_head (bb);
6622 /* Remove bb tail from path. */
6624 ilist_remove (&path);
6628 /* This is the case when one of the original expr is no longer available
6629 due to bookkeeping created on this branch with the same register.
6630 In the original algorithm, which doesn't have update_data_sets call
6631 on a bookkeeping block, it would simply result in returning
6632 FALSE when we've encountered a previously generated bookkeeping
6633 insn in moveop_orig_expr_not_found. */
6634 code_motion_path_driver_cleanup (&orig_ops, &path);
6639 /* Don't need it any more. */
6640 av_set_clear (&orig_ops);
6642 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6643 the beginning of the basic block. */
6644 before_first = PREV_INSN (first_insn);
6645 while (insn != before_first)
6647 if (code_motion_path_driver_info->ascend)
6648 code_motion_path_driver_info->ascend (insn, static_params);
6650 insn = PREV_INSN (insn);
6653 /* Now we're at the bb head. */
6655 ilist_remove (&path);
6656 local_params_in->removed_last_insn = removed_last_insn;
6657 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6659 /* This should be the very last operation as at bb head we could change
6660 the numbering by creating bookkeeping blocks. */
6661 if (removed_last_insn)
6662 insn = PREV_INSN (insn);
6664 /* If we have simplified the control flow and removed the first jump insn,
6665 there's no point in marking this block in the visited blocks bitmap. */
6666 if (BLOCK_FOR_INSN (insn))
6667 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6671 /* Move up the operations from ORIG_OPS set traversing the dag starting
6672 from INSN. PATH represents the edges traversed so far.
6673 DEST is the register chosen for scheduling the current expr. Insert
6674 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6675 C_EXPR is how it looks like at the given cfg point.
6676 Set *SHOULD_MOVE to indicate whether we have only disconnected
6677 one of the insns found.
6679 Returns whether original instructions were found, which is asserted
6680 to be true in the caller. */
6682 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6683 rtx dest, expr_t c_expr, bool *should_move)
6685 struct moveop_static_params sparams;
6686 struct cmpd_local_params lparams;
6689 /* Init params for code_motion_path_driver. */
6690 sparams.dest = dest;
6691 sparams.c_expr = c_expr;
6692 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6693 sparams.failed_insn = NULL;
6694 sparams.was_renamed = false;
6697 /* We haven't visited any blocks yet. */
6698 bitmap_clear (code_motion_visited_blocks);
6700 /* Set appropriate hooks and data. */
6701 code_motion_path_driver_info = &move_op_hooks;
6702 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6704 gcc_assert (res != -1);
6706 if (sparams.was_renamed)
6707 EXPR_WAS_RENAMED (expr_vliw) = true;
6709 *should_move = (sparams.uid == -1);
6715 /* Functions that work with regions. */
6717 /* Current number of seqno used in init_seqno and init_seqno_1. */
6718 static int cur_seqno;
6720 /* A helper for init_seqno. Traverse the region starting from BB and
6721 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6722 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6724 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6726 int bbi = BLOCK_TO_BB (bb->index);
6731 rtx_note *note = bb_note (bb);
6732 bitmap_set_bit (visited_bbs, bbi);
6733 if (blocks_to_reschedule)
6734 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6736 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6737 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6739 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6740 int succ_bbi = BLOCK_TO_BB (succ->index);
6742 gcc_assert (in_current_region_p (succ));
6744 if (!bitmap_bit_p (visited_bbs, succ_bbi))
6746 gcc_assert (succ_bbi > bbi);
6748 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6750 else if (blocks_to_reschedule)
6751 bitmap_set_bit (forced_ebb_heads, succ->index);
6754 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6755 INSN_SEQNO (insn) = cur_seqno--;
6758 /* Initialize seqnos for the current region. BLOCKS_TO_RESCHEDULE contains
6759 blocks on which we're rescheduling when pipelining, FROM is the block where
6760 traversing region begins (it may not be the head of the region when
6761 pipelining, but the head of the loop instead).
6763 Returns the maximal seqno found. */
6765 init_seqno (bitmap blocks_to_reschedule, basic_block from)
6767 sbitmap visited_bbs;
6771 visited_bbs = sbitmap_alloc (current_nr_blocks);
6773 if (blocks_to_reschedule)
6775 bitmap_ones (visited_bbs);
6776 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6778 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6779 bitmap_clear_bit (visited_bbs, BLOCK_TO_BB (bbi));
6784 bitmap_clear (visited_bbs);
6785 from = EBB_FIRST_BB (0);
6788 cur_seqno = sched_max_luid - 1;
6789 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6791 /* cur_seqno may be positive if the number of instructions is less than
6792 sched_max_luid - 1 (when rescheduling or if some instructions have been
6793 removed by the call to purge_empty_blocks in sel_sched_region_1). */
6794 gcc_assert (cur_seqno >= 0);
6796 sbitmap_free (visited_bbs);
6797 return sched_max_luid - 1;
6800 /* Initialize scheduling parameters for current region. */
6802 sel_setup_region_sched_flags (void)
6804 enable_schedule_as_rhs_p = 1;
6806 pipelining_p = (bookkeeping_p
6807 && (flag_sel_sched_pipelining != 0)
6808 && current_loop_nest != NULL
6809 && loop_has_exit_edges (current_loop_nest));
6810 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6814 /* Return true if all basic blocks of current region are empty. */
6816 current_region_empty_p (void)
6819 for (i = 0; i < current_nr_blocks; i++)
6820 if (! sel_bb_empty_p (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (i))))
6826 /* Prepare and verify loop nest for pipelining. */
6828 setup_current_loop_nest (int rgn, bb_vec_t *bbs)
6830 current_loop_nest = get_loop_nest_for_rgn (rgn);
6832 if (!current_loop_nest)
6835 /* If this loop has any saved loop preheaders from nested loops,
6836 add these basic blocks to the current region. */
6837 sel_add_loop_preheaders (bbs);
6839 /* Check that we're starting with a valid information. */
6840 gcc_assert (loop_latch_edge (current_loop_nest));
6841 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6844 /* Compute instruction priorities for current region. */
6846 sel_compute_priorities (int rgn)
6848 sched_rgn_compute_dependencies (rgn);
6850 /* Compute insn priorities in haifa style. Then free haifa style
6851 dependencies that we've calculated for this. */
6852 compute_priorities ();
6854 if (sched_verbose >= 5)
6855 debug_rgn_dependencies (0);
6860 /* Init scheduling data for RGN. Returns true when this region should not
6863 sel_region_init (int rgn)
6868 rgn_setup_region (rgn);
6870 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6871 do region initialization here so the region can be bundled correctly,
6872 but we'll skip the scheduling in sel_sched_region (). */
6873 if (current_region_empty_p ())
6876 bbs.create (current_nr_blocks);
6878 for (i = 0; i < current_nr_blocks; i++)
6879 bbs.quick_push (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (i)));
6883 if (flag_sel_sched_pipelining)
6884 setup_current_loop_nest (rgn, &bbs);
6886 sel_setup_region_sched_flags ();
6888 /* Initialize luids and dependence analysis which both sel-sched and haifa
6890 sched_init_luids (bbs);
6891 sched_deps_init (false);
6893 /* Initialize haifa data. */
6894 rgn_setup_sched_infos ();
6895 sel_set_sched_flags ();
6896 haifa_init_h_i_d (bbs);
6898 sel_compute_priorities (rgn);
6899 init_deps_global ();
6901 /* Main initialization. */
6902 sel_setup_sched_infos ();
6903 sel_init_global_and_expr (bbs);
6907 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6909 /* Init correct liveness sets on each instruction of a single-block loop.
6910 This is the only situation when we can't update liveness when calling
6911 compute_live for the first insn of the loop. */
6912 if (current_loop_nest)
6915 (sel_is_loop_preheader_p (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (0)))
6919 if (current_nr_blocks == header + 1)
6920 update_liveness_on_insn
6921 (sel_bb_head (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (header))));
6924 /* Set hooks so that no newly generated insn will go out unnoticed. */
6925 sel_register_cfg_hooks ();
6927 /* !!! We call target.sched.init () for the whole region, but we invoke
6928 targetm.sched.finish () for every ebb. */
6929 if (targetm.sched.init)
6930 /* None of the arguments are actually used in any target. */
6931 targetm.sched.init (sched_dump, sched_verbose, -1);
6933 first_emitted_uid = get_max_uid () + 1;
6934 preheader_removed = false;
6936 /* Reset register allocation ticks array. */
6937 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6938 reg_rename_this_tick = 0;
6940 bitmap_initialize (forced_ebb_heads, 0);
6941 bitmap_clear (forced_ebb_heads);
6944 current_copies = BITMAP_ALLOC (NULL);
6945 current_originators = BITMAP_ALLOC (NULL);
6946 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
6951 /* Simplify insns after the scheduling. */
6953 simplify_changed_insns (void)
6957 for (i = 0; i < current_nr_blocks; i++)
6959 basic_block bb = BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (i));
6962 FOR_BB_INSNS (bb, insn)
6965 expr_t expr = INSN_EXPR (insn);
6967 if (EXPR_WAS_SUBSTITUTED (expr))
6968 validate_simplify_insn (insn);
6973 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6974 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6975 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6977 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
6979 rtx_insn *head, *tail;
6980 basic_block bb1 = bb;
6981 if (sched_verbose >= 2)
6982 sel_print ("Finishing schedule in bbs: ");
6986 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
6988 if (sched_verbose >= 2)
6989 sel_print ("%d; ", bb1->index);
6991 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
6993 if (sched_verbose >= 2)
6996 get_ebb_head_tail (bb, bb1, &head, &tail);
6998 current_sched_info->head = head;
6999 current_sched_info->tail = tail;
7000 current_sched_info->prev_head = PREV_INSN (head);
7001 current_sched_info->next_tail = NEXT_INSN (tail);
7004 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
7006 reset_sched_cycles_in_current_ebb (void)
7009 int haifa_last_clock = -1;
7010 int haifa_clock = 0;
7011 int issued_insns = 0;
7014 if (targetm.sched.init)
7016 /* None of the arguments are actually used in any target.
7017 NB: We should have md_reset () hook for cases like this. */
7018 targetm.sched.init (sched_dump, sched_verbose, -1);
7021 state_reset (curr_state);
7022 advance_state (curr_state);
7024 for (insn = current_sched_info->head;
7025 insn != current_sched_info->next_tail;
7026 insn = NEXT_INSN (insn))
7028 int cost, haifa_cost;
7030 bool asm_p, real_insn, after_stall, all_issued;
7037 real_insn = recog_memoized (insn) >= 0;
7038 clock = INSN_SCHED_CYCLE (insn);
7040 cost = clock - last_clock;
7042 /* Initialize HAIFA_COST. */
7045 asm_p = INSN_ASM_P (insn);
7048 /* This is asm insn which *had* to be scheduled first
7052 /* This is a use/clobber insn. It should not change
7057 haifa_cost = estimate_insn_cost (insn, curr_state);
7059 /* Stall for whatever cycles we've stalled before. */
7061 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
7066 all_issued = issued_insns == issue_rate;
7067 if (haifa_cost == 0 && all_issued)
7073 while (haifa_cost--)
7075 advance_state (curr_state);
7079 if (sched_verbose >= 2)
7081 sel_print ("advance_state (state_transition)\n");
7082 debug_state (curr_state);
7085 /* The DFA may report that e.g. insn requires 2 cycles to be
7086 issued, but on the next cycle it says that insn is ready
7087 to go. Check this here. */
7091 && estimate_insn_cost (insn, curr_state) == 0)
7094 /* When the data dependency stall is longer than the DFA stall,
7095 and when we have issued exactly issue_rate insns and stalled,
7096 it could be that after this longer stall the insn will again
7097 become unavailable to the DFA restrictions. Looks strange
7098 but happens e.g. on x86-64. So recheck DFA on the last
7100 if ((after_stall || all_issued)
7103 haifa_cost = estimate_insn_cost (insn, curr_state);
7107 if (sched_verbose >= 2)
7108 sel_print ("haifa clock: %d\n", haifa_clock);
7111 gcc_assert (haifa_cost == 0);
7113 if (sched_verbose >= 2)
7114 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
7116 if (targetm.sched.dfa_new_cycle)
7117 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
7118 haifa_last_clock, haifa_clock,
7121 advance_state (curr_state);
7124 if (sched_verbose >= 2)
7126 sel_print ("advance_state (dfa_new_cycle)\n");
7127 debug_state (curr_state);
7128 sel_print ("haifa clock: %d\n", haifa_clock + 1);
7134 static state_t temp = NULL;
7137 temp = xmalloc (dfa_state_size);
7138 memcpy (temp, curr_state, dfa_state_size);
7140 cost = state_transition (curr_state, insn);
7141 if (memcmp (temp, curr_state, dfa_state_size))
7144 if (sched_verbose >= 2)
7146 sel_print ("scheduled insn %d, clock %d\n", INSN_UID (insn),
7148 debug_state (curr_state);
7150 gcc_assert (cost < 0);
7153 if (targetm.sched.variable_issue)
7154 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
7156 INSN_SCHED_CYCLE (insn) = haifa_clock;
7159 haifa_last_clock = haifa_clock;
7163 /* Put TImode markers on insns starting a new issue group. */
7167 int last_clock = -1;
7170 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
7171 insn = NEXT_INSN (insn))
7178 clock = INSN_SCHED_CYCLE (insn);
7179 cost = (last_clock == -1) ? 1 : clock - last_clock;
7181 gcc_assert (cost >= 0);
7184 && GET_CODE (PATTERN (insn)) != USE
7185 && GET_CODE (PATTERN (insn)) != CLOBBER)
7187 if (reload_completed && cost > 0)
7188 PUT_MODE (insn, TImode);
7193 if (sched_verbose >= 2)
7194 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
7198 /* Perform MD_FINISH on EBBs comprising current region. When
7199 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7200 to produce correct sched cycles on insns. */
7202 sel_region_target_finish (bool reset_sched_cycles_p)
7205 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
7207 for (i = 0; i < current_nr_blocks; i++)
7209 if (bitmap_bit_p (scheduled_blocks, i))
7212 /* While pipelining outer loops, skip bundling for loop
7213 preheaders. Those will be rescheduled in the outer loop. */
7214 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
7217 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
7219 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
7222 if (reset_sched_cycles_p)
7223 reset_sched_cycles_in_current_ebb ();
7225 if (targetm.sched.init)
7226 targetm.sched.init (sched_dump, sched_verbose, -1);
7230 if (targetm.sched.finish)
7232 targetm.sched.finish (sched_dump, sched_verbose);
7234 /* Extend luids so that insns generated by the target will
7236 sched_extend_luids ();
7240 BITMAP_FREE (scheduled_blocks);
7243 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7244 is true, make an additional pass emulating scheduler to get correct insn
7245 cycles for md_finish calls. */
7247 sel_region_finish (bool reset_sched_cycles_p)
7249 simplify_changed_insns ();
7250 sched_finish_ready_list ();
7253 /* Free the vectors. */
7254 vec_av_set.release ();
7255 BITMAP_FREE (current_copies);
7256 BITMAP_FREE (current_originators);
7257 BITMAP_FREE (code_motion_visited_blocks);
7258 vinsn_vec_free (vec_bookkeeping_blocked_vinsns);
7259 vinsn_vec_free (vec_target_unavailable_vinsns);
7261 /* If LV_SET of the region head should be updated, do it now because
7262 there will be no other chance. */
7267 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
7268 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
7270 basic_block bb = BLOCK_FOR_INSN (insn);
7272 if (!BB_LV_SET_VALID_P (bb))
7273 compute_live (insn);
7277 /* Emulate the Haifa scheduler for bundling. */
7278 if (reload_completed)
7279 sel_region_target_finish (reset_sched_cycles_p);
7281 sel_finish_global_and_expr ();
7283 bitmap_clear (forced_ebb_heads);
7287 finish_deps_global ();
7288 sched_finish_luids ();
7292 BITMAP_FREE (blocks_to_reschedule);
7294 sel_unregister_cfg_hooks ();
7300 /* Functions that implement the scheduler driver. */
7302 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7303 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7304 of insns scheduled -- these would be postprocessed later. */
7306 schedule_on_fences (flist_t fences, int max_seqno,
7307 ilist_t **scheduled_insns_tailpp)
7309 flist_t old_fences = fences;
7311 if (sched_verbose >= 1)
7313 sel_print ("\nScheduling on fences: ");
7314 dump_flist (fences);
7318 scheduled_something_on_previous_fence = false;
7319 for (; fences; fences = FLIST_NEXT (fences))
7321 fence_t fence = NULL;
7324 bool first_p = true;
7326 /* Choose the next fence group to schedule.
7327 The fact that insn can be scheduled only once
7328 on the cycle is guaranteed by two properties:
7329 1. seqnos of parallel groups decrease with each iteration.
7330 2. If is_ineligible_successor () sees the larger seqno, it
7331 checks if candidate insn is_in_current_fence_p (). */
7332 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7334 fence_t f = FLIST_FENCE (fences2);
7336 if (!FENCE_PROCESSED_P (f))
7338 int i = INSN_SEQNO (FENCE_INSN (f));
7340 if (first_p || i > seqno)
7347 /* ??? Seqnos of different groups should be different. */
7348 gcc_assert (1 || i != seqno);
7354 /* As FENCE is nonnull, SEQNO is initialized. */
7355 seqno -= max_seqno + 1;
7356 fill_insns (fence, seqno, scheduled_insns_tailpp);
7357 FENCE_PROCESSED_P (fence) = true;
7360 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7361 don't need to keep bookkeeping-invalidated and target-unavailable
7363 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7364 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7367 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7369 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7371 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7373 /* The first element is already processed. */
7374 while ((fences = FLIST_NEXT (fences)))
7376 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7378 if (*min_seqno > seqno)
7380 else if (*max_seqno < seqno)
7385 /* Calculate new fences from FENCES. Write the current time to PTIME. */
7387 calculate_new_fences (flist_t fences, int orig_max_seqno, int *ptime)
7389 flist_t old_fences = fences;
7390 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7393 flist_tail_init (new_fences);
7394 for (; fences; fences = FLIST_NEXT (fences))
7396 fence_t fence = FLIST_FENCE (fences);
7399 if (!FENCE_BNDS (fence))
7401 /* This fence doesn't have any successors. */
7402 if (!FENCE_SCHEDULED_P (fence))
7404 /* Nothing was scheduled on this fence. */
7407 insn = FENCE_INSN (fence);
7408 seqno = INSN_SEQNO (insn);
7409 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7411 if (sched_verbose >= 1)
7412 sel_print ("Fence %d[%d] has not changed\n",
7415 move_fence_to_fences (fences, new_fences);
7419 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7420 max_time = MAX (max_time, FENCE_CYCLE (fence));
7423 flist_clear (&old_fences);
7425 return FLIST_TAIL_HEAD (new_fences);
7428 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7429 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7430 the highest seqno used in a region. Return the updated highest seqno. */
7432 update_seqnos_and_stage (int min_seqno, int max_seqno,
7433 int highest_seqno_in_use,
7434 ilist_t *pscheduled_insns)
7440 /* Actually, new_hs is the seqno of the instruction, that was
7441 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7442 if (*pscheduled_insns)
7444 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7445 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7446 gcc_assert (new_hs > highest_seqno_in_use);
7449 new_hs = highest_seqno_in_use;
7451 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7453 gcc_assert (INSN_SEQNO (insn) < 0);
7454 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7455 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7457 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7458 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7459 require > 1GB of memory e.g. on limit-fnargs.c. */
7461 free_data_for_scheduled_insn (insn);
7464 ilist_clear (pscheduled_insns);
7470 /* The main driver for scheduling a region. This function is responsible
7471 for correct propagation of fences (i.e. scheduling points) and creating
7472 a group of parallel insns at each of them. It also supports
7473 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7476 sel_sched_region_2 (int orig_max_seqno)
7478 int highest_seqno_in_use = orig_max_seqno;
7481 stat_bookkeeping_copies = 0;
7482 stat_insns_needed_bookkeeping = 0;
7483 stat_renamed_scheduled = 0;
7484 stat_substitutions_total = 0;
7485 num_insns_scheduled = 0;
7489 int min_seqno, max_seqno;
7490 ilist_t scheduled_insns = NULL;
7491 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7493 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7494 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7495 fences = calculate_new_fences (fences, orig_max_seqno, &max_time);
7496 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7497 highest_seqno_in_use,
7501 if (sched_verbose >= 1)
7503 sel_print ("Total scheduling time: %d cycles\n", max_time);
7504 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7505 "bookkeeping, %d insns renamed, %d insns substituted\n",
7506 stat_bookkeeping_copies,
7507 stat_insns_needed_bookkeeping,
7508 stat_renamed_scheduled,
7509 stat_substitutions_total);
7513 /* Schedule a region. When pipelining, search for possibly never scheduled
7514 bookkeeping code and schedule it. Reschedule pipelined code without
7515 pipelining after. */
7517 sel_sched_region_1 (void)
7521 /* Remove empty blocks that might be in the region from the beginning. */
7522 purge_empty_blocks ();
7524 orig_max_seqno = init_seqno (NULL, NULL);
7525 gcc_assert (orig_max_seqno >= 1);
7527 /* When pipelining outer loops, create fences on the loop header,
7530 if (current_loop_nest)
7531 init_fences (BB_END (EBB_FIRST_BB (0)));
7533 init_fences (bb_note (EBB_FIRST_BB (0)));
7536 sel_sched_region_2 (orig_max_seqno);
7538 gcc_assert (fences == NULL);
7544 struct flist_tail_def _new_fences;
7545 flist_tail_t new_fences = &_new_fences;
7548 pipelining_p = false;
7549 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7550 bookkeeping_p = false;
7551 enable_schedule_as_rhs_p = false;
7553 /* Schedule newly created code, that has not been scheduled yet. */
7560 for (i = 0; i < current_nr_blocks; i++)
7562 basic_block bb = EBB_FIRST_BB (i);
7564 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7566 if (! bb_ends_ebb_p (bb))
7567 bitmap_set_bit (blocks_to_reschedule, bb_next_bb (bb)->index);
7568 if (sel_bb_empty_p (bb))
7570 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7573 clear_outdated_rtx_info (bb);
7574 if (sel_insn_is_speculation_check (BB_END (bb))
7575 && JUMP_P (BB_END (bb)))
7576 bitmap_set_bit (blocks_to_reschedule,
7577 BRANCH_EDGE (bb)->dest->index);
7579 else if (! sel_bb_empty_p (bb)
7580 && INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7581 bitmap_set_bit (blocks_to_reschedule, bb->index);
7584 for (i = 0; i < current_nr_blocks; i++)
7586 bb = EBB_FIRST_BB (i);
7588 /* While pipelining outer loops, skip bundling for loop
7589 preheaders. Those will be rescheduled in the outer
7591 if (sel_is_loop_preheader_p (bb))
7593 clear_outdated_rtx_info (bb);
7597 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7599 flist_tail_init (new_fences);
7601 orig_max_seqno = init_seqno (blocks_to_reschedule, bb);
7603 /* Mark BB as head of the new ebb. */
7604 bitmap_set_bit (forced_ebb_heads, bb->index);
7606 gcc_assert (fences == NULL);
7608 init_fences (bb_note (bb));
7610 sel_sched_region_2 (orig_max_seqno);
7620 /* Schedule the RGN region. */
7622 sel_sched_region (int rgn)
7625 bool reset_sched_cycles_p;
7627 if (sel_region_init (rgn))
7630 if (sched_verbose >= 1)
7631 sel_print ("Scheduling region %d\n", rgn);
7633 schedule_p = (!sched_is_disabled_for_current_region_p ()
7634 && dbg_cnt (sel_sched_region_cnt));
7635 reset_sched_cycles_p = pipelining_p;
7637 sel_sched_region_1 ();
7639 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7640 reset_sched_cycles_p = true;
7642 sel_region_finish (reset_sched_cycles_p);
7645 /* Perform global init for the scheduler. */
7647 sel_global_init (void)
7649 calculate_dominance_info (CDI_DOMINATORS);
7650 alloc_sched_pools ();
7652 /* Setup the infos for sched_init. */
7653 sel_setup_sched_infos ();
7654 setup_sched_dump ();
7656 sched_rgn_init (false);
7660 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7662 can_issue_more = issue_rate;
7664 sched_extend_target ();
7665 sched_deps_init (true);
7666 setup_nop_and_exit_insns ();
7667 sel_extend_global_bb_info ();
7669 init_hard_regs_data ();
7672 /* Free the global data of the scheduler. */
7674 sel_global_finish (void)
7676 free_bb_note_pool ();
7678 sel_finish_global_bb_info ();
7680 free_regset_pool ();
7681 free_nop_and_exit_insns ();
7683 sched_rgn_finish ();
7684 sched_deps_finish ();
7688 sel_finish_pipelining ();
7690 free_sched_pools ();
7691 free_dominance_info (CDI_DOMINATORS);
7694 /* Return true when we need to skip selective scheduling. Used for debugging. */
7696 maybe_skip_selective_scheduling (void)
7698 return ! dbg_cnt (sel_sched_cnt);
7701 /* The entry point. */
7703 run_selective_scheduling (void)
7707 if (n_basic_blocks_for_fn (cfun) == NUM_FIXED_BLOCKS)
7712 for (rgn = 0; rgn < nr_regions; rgn++)
7713 sel_sched_region (rgn);
7715 sel_global_finish ();