1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "diagnostic-core.h"
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
38 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
39 #include "addresses.h"
42 /* Forward declarations */
43 static void set_of_1 (rtx, const_rtx, void *);
44 static bool covers_regno_p (const_rtx, unsigned int);
45 static bool covers_regno_no_parallel_p (const_rtx, unsigned int);
46 static int computed_jump_p_1 (const_rtx);
47 static void parms_set (rtx, const_rtx, void *);
49 static unsigned HOST_WIDE_INT cached_nonzero_bits (const_rtx, enum machine_mode,
50 const_rtx, enum machine_mode,
51 unsigned HOST_WIDE_INT);
52 static unsigned HOST_WIDE_INT nonzero_bits1 (const_rtx, enum machine_mode,
53 const_rtx, enum machine_mode,
54 unsigned HOST_WIDE_INT);
55 static unsigned int cached_num_sign_bit_copies (const_rtx, enum machine_mode, const_rtx,
58 static unsigned int num_sign_bit_copies1 (const_rtx, enum machine_mode, const_rtx,
59 enum machine_mode, unsigned int);
61 /* Offset of the first 'e', 'E' or 'V' operand for each rtx code, or
62 -1 if a code has no such operand. */
63 static int non_rtx_starting_operands[NUM_RTX_CODE];
65 rtx_subrtx_bound_info rtx_all_subrtx_bounds[NUM_RTX_CODE];
66 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds[NUM_RTX_CODE];
68 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
69 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
70 SIGN_EXTEND then while narrowing we also have to enforce the
71 representation and sign-extend the value to mode DESTINATION_REP.
73 If the value is already sign-extended to DESTINATION_REP mode we
74 can just switch to DESTINATION mode on it. For each pair of
75 integral modes SOURCE and DESTINATION, when truncating from SOURCE
76 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
77 contains the number of high-order bits in SOURCE that have to be
78 copies of the sign-bit so that we can do this mode-switch to
82 num_sign_bit_copies_in_rep[MAX_MODE_INT + 1][MAX_MODE_INT + 1];
84 /* Store X into index I of ARRAY. ARRAY is known to have at least I
85 elements. Return the new base of ARRAY. */
88 typename T::value_type *
89 generic_subrtx_iterator <T>::add_single_to_queue (array_type &array,
91 size_t i, value_type x)
93 if (base == array.stack)
100 gcc_checking_assert (i == LOCAL_ELEMS);
101 vec_safe_grow (array.heap, i + 1);
102 base = array.heap->address ();
103 memcpy (base, array.stack, sizeof (array.stack));
104 base[LOCAL_ELEMS] = x;
107 unsigned int length = array.heap->length ();
110 gcc_checking_assert (base == array.heap->address ());
116 gcc_checking_assert (i == length);
117 vec_safe_push (array.heap, x);
118 return array.heap->address ();
122 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
123 number of elements added to the worklist. */
125 template <typename T>
127 generic_subrtx_iterator <T>::add_subrtxes_to_queue (array_type &array,
129 size_t end, rtx_type x)
131 const char *format = GET_RTX_FORMAT (GET_CODE (x));
132 size_t orig_end = end;
133 for (int i = 0; format[i]; ++i)
134 if (format[i] == 'e')
136 value_type subx = T::get_value (x->u.fld[i].rt_rtx);
137 if (__builtin_expect (end < LOCAL_ELEMS, true))
140 base = add_single_to_queue (array, base, end++, subx);
142 else if (format[i] == 'E')
144 int length = GET_NUM_ELEM (x->u.fld[i].rt_rtvec);
145 rtx *vec = x->u.fld[i].rt_rtvec->elem;
146 if (__builtin_expect (end + length <= LOCAL_ELEMS, true))
147 for (int j = 0; j < length; j++)
148 base[end++] = T::get_value (vec[j]);
150 for (int j = 0; j < length; j++)
151 base = add_single_to_queue (array, base, end++,
152 T::get_value (vec[j]));
154 return end - orig_end;
157 template <typename T>
159 generic_subrtx_iterator <T>::free_array (array_type &array)
161 vec_free (array.heap);
164 template <typename T>
165 const size_t generic_subrtx_iterator <T>::LOCAL_ELEMS;
167 template class generic_subrtx_iterator <const_rtx_accessor>;
168 template class generic_subrtx_iterator <rtx_var_accessor>;
169 template class generic_subrtx_iterator <rtx_ptr_accessor>;
171 /* Return 1 if the value of X is unstable
172 (would be different at a different point in the program).
173 The frame pointer, arg pointer, etc. are considered stable
174 (within one function) and so is anything marked `unchanging'. */
177 rtx_unstable_p (const_rtx x)
179 const RTX_CODE code = GET_CODE (x);
186 return !MEM_READONLY_P (x) || rtx_unstable_p (XEXP (x, 0));
195 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
196 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
197 /* The arg pointer varies if it is not a fixed register. */
198 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
200 /* ??? When call-clobbered, the value is stable modulo the restore
201 that must happen after a call. This currently screws up local-alloc
202 into believing that the restore is not needed. */
203 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED && x == pic_offset_table_rtx)
208 if (MEM_VOLATILE_P (x))
217 fmt = GET_RTX_FORMAT (code);
218 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
221 if (rtx_unstable_p (XEXP (x, i)))
224 else if (fmt[i] == 'E')
227 for (j = 0; j < XVECLEN (x, i); j++)
228 if (rtx_unstable_p (XVECEXP (x, i, j)))
235 /* Return 1 if X has a value that can vary even between two
236 executions of the program. 0 means X can be compared reliably
237 against certain constants or near-constants.
238 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
239 zero, we are slightly more conservative.
240 The frame pointer and the arg pointer are considered constant. */
243 rtx_varies_p (const_rtx x, bool for_alias)
256 return !MEM_READONLY_P (x) || rtx_varies_p (XEXP (x, 0), for_alias);
265 /* Note that we have to test for the actual rtx used for the frame
266 and arg pointers and not just the register number in case we have
267 eliminated the frame and/or arg pointer and are using it
269 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
270 /* The arg pointer varies if it is not a fixed register. */
271 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
273 if (x == pic_offset_table_rtx
274 /* ??? When call-clobbered, the value is stable modulo the restore
275 that must happen after a call. This currently screws up
276 local-alloc into believing that the restore is not needed, so we
277 must return 0 only if we are called from alias analysis. */
278 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED || for_alias))
283 /* The operand 0 of a LO_SUM is considered constant
284 (in fact it is related specifically to operand 1)
285 during alias analysis. */
286 return (! for_alias && rtx_varies_p (XEXP (x, 0), for_alias))
287 || rtx_varies_p (XEXP (x, 1), for_alias);
290 if (MEM_VOLATILE_P (x))
299 fmt = GET_RTX_FORMAT (code);
300 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
303 if (rtx_varies_p (XEXP (x, i), for_alias))
306 else if (fmt[i] == 'E')
309 for (j = 0; j < XVECLEN (x, i); j++)
310 if (rtx_varies_p (XVECEXP (x, i, j), for_alias))
317 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
318 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
319 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
320 references on strict alignment machines. */
323 rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size,
324 enum machine_mode mode, bool unaligned_mems)
326 enum rtx_code code = GET_CODE (x);
328 /* The offset must be a multiple of the mode size if we are considering
329 unaligned memory references on strict alignment machines. */
330 if (STRICT_ALIGNMENT && unaligned_mems && GET_MODE_SIZE (mode) != 0)
332 HOST_WIDE_INT actual_offset = offset;
334 #ifdef SPARC_STACK_BOUNDARY_HACK
335 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
336 the real alignment of %sp. However, when it does this, the
337 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
338 if (SPARC_STACK_BOUNDARY_HACK
339 && (x == stack_pointer_rtx || x == hard_frame_pointer_rtx))
340 actual_offset -= STACK_POINTER_OFFSET;
343 if (actual_offset % GET_MODE_SIZE (mode) != 0)
350 if (SYMBOL_REF_WEAK (x))
352 if (!CONSTANT_POOL_ADDRESS_P (x))
355 HOST_WIDE_INT decl_size;
360 size = GET_MODE_SIZE (mode);
364 /* If the size of the access or of the symbol is unknown,
366 decl = SYMBOL_REF_DECL (x);
368 /* Else check that the access is in bounds. TODO: restructure
369 expr_size/tree_expr_size/int_expr_size and just use the latter. */
372 else if (DECL_P (decl) && DECL_SIZE_UNIT (decl))
373 decl_size = (tree_fits_shwi_p (DECL_SIZE_UNIT (decl))
374 ? tree_to_shwi (DECL_SIZE_UNIT (decl))
376 else if (TREE_CODE (decl) == STRING_CST)
377 decl_size = TREE_STRING_LENGTH (decl);
378 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl)))
379 decl_size = int_size_in_bytes (TREE_TYPE (decl));
383 return (decl_size <= 0 ? offset != 0 : offset + size > decl_size);
392 /* Stack references are assumed not to trap, but we need to deal with
393 nonsensical offsets. */
394 if (x == frame_pointer_rtx)
396 HOST_WIDE_INT adj_offset = offset - STARTING_FRAME_OFFSET;
398 size = GET_MODE_SIZE (mode);
399 if (FRAME_GROWS_DOWNWARD)
401 if (adj_offset < frame_offset || adj_offset + size - 1 >= 0)
406 if (adj_offset < 0 || adj_offset + size - 1 >= frame_offset)
411 /* ??? Need to add a similar guard for nonsensical offsets. */
412 if (x == hard_frame_pointer_rtx
413 || x == stack_pointer_rtx
414 /* The arg pointer varies if it is not a fixed register. */
415 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
417 /* All of the virtual frame registers are stack references. */
418 if (REGNO (x) >= FIRST_VIRTUAL_REGISTER
419 && REGNO (x) <= LAST_VIRTUAL_REGISTER)
424 return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size,
425 mode, unaligned_mems);
428 /* An address is assumed not to trap if:
429 - it is the pic register plus a constant. */
430 if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1)))
433 /* - or it is an address that can't trap plus a constant integer. */
434 if (CONST_INT_P (XEXP (x, 1))
435 && !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset + INTVAL (XEXP (x, 1)),
436 size, mode, unaligned_mems))
443 return rtx_addr_can_trap_p_1 (XEXP (x, 1), offset, size,
444 mode, unaligned_mems);
451 return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size,
452 mode, unaligned_mems);
458 /* If it isn't one of the case above, it can cause a trap. */
462 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
465 rtx_addr_can_trap_p (const_rtx x)
467 return rtx_addr_can_trap_p_1 (x, 0, 0, VOIDmode, false);
470 /* Return true if X is an address that is known to not be zero. */
473 nonzero_address_p (const_rtx x)
475 const enum rtx_code code = GET_CODE (x);
480 return !SYMBOL_REF_WEAK (x);
486 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
487 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
488 || x == stack_pointer_rtx
489 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
491 /* All of the virtual frame registers are stack references. */
492 if (REGNO (x) >= FIRST_VIRTUAL_REGISTER
493 && REGNO (x) <= LAST_VIRTUAL_REGISTER)
498 return nonzero_address_p (XEXP (x, 0));
501 /* Handle PIC references. */
502 if (XEXP (x, 0) == pic_offset_table_rtx
503 && CONSTANT_P (XEXP (x, 1)))
508 /* Similar to the above; allow positive offsets. Further, since
509 auto-inc is only allowed in memories, the register must be a
511 if (CONST_INT_P (XEXP (x, 1))
512 && INTVAL (XEXP (x, 1)) > 0)
514 return nonzero_address_p (XEXP (x, 0));
517 /* Similarly. Further, the offset is always positive. */
524 return nonzero_address_p (XEXP (x, 0));
527 return nonzero_address_p (XEXP (x, 1));
533 /* If it isn't one of the case above, might be zero. */
537 /* Return 1 if X refers to a memory location whose address
538 cannot be compared reliably with constant addresses,
539 or if X refers to a BLKmode memory object.
540 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
541 zero, we are slightly more conservative. */
544 rtx_addr_varies_p (const_rtx x, bool for_alias)
555 return GET_MODE (x) == BLKmode || rtx_varies_p (XEXP (x, 0), for_alias);
557 fmt = GET_RTX_FORMAT (code);
558 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
561 if (rtx_addr_varies_p (XEXP (x, i), for_alias))
564 else if (fmt[i] == 'E')
567 for (j = 0; j < XVECLEN (x, i); j++)
568 if (rtx_addr_varies_p (XVECEXP (x, i, j), for_alias))
574 /* Return the CALL in X if there is one. */
577 get_call_rtx_from (rtx x)
581 if (GET_CODE (x) == PARALLEL)
582 x = XVECEXP (x, 0, 0);
583 if (GET_CODE (x) == SET)
585 if (GET_CODE (x) == CALL && MEM_P (XEXP (x, 0)))
590 /* Return the value of the integer term in X, if one is apparent;
592 Only obvious integer terms are detected.
593 This is used in cse.c with the `related_value' field. */
596 get_integer_term (const_rtx x)
598 if (GET_CODE (x) == CONST)
601 if (GET_CODE (x) == MINUS
602 && CONST_INT_P (XEXP (x, 1)))
603 return - INTVAL (XEXP (x, 1));
604 if (GET_CODE (x) == PLUS
605 && CONST_INT_P (XEXP (x, 1)))
606 return INTVAL (XEXP (x, 1));
610 /* If X is a constant, return the value sans apparent integer term;
612 Only obvious integer terms are detected. */
615 get_related_value (const_rtx x)
617 if (GET_CODE (x) != CONST)
620 if (GET_CODE (x) == PLUS
621 && CONST_INT_P (XEXP (x, 1)))
623 else if (GET_CODE (x) == MINUS
624 && CONST_INT_P (XEXP (x, 1)))
629 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
630 to somewhere in the same object or object_block as SYMBOL. */
633 offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset)
637 if (GET_CODE (symbol) != SYMBOL_REF)
645 if (CONSTANT_POOL_ADDRESS_P (symbol)
646 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
649 decl = SYMBOL_REF_DECL (symbol);
650 if (decl && offset < int_size_in_bytes (TREE_TYPE (decl)))
654 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
655 && SYMBOL_REF_BLOCK (symbol)
656 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
657 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
658 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
664 /* Split X into a base and a constant offset, storing them in *BASE_OUT
665 and *OFFSET_OUT respectively. */
668 split_const (rtx x, rtx *base_out, rtx *offset_out)
670 if (GET_CODE (x) == CONST)
673 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
675 *base_out = XEXP (x, 0);
676 *offset_out = XEXP (x, 1);
681 *offset_out = const0_rtx;
684 /* Return the number of places FIND appears within X. If COUNT_DEST is
685 zero, we do not count occurrences inside the destination of a SET. */
688 count_occurrences (const_rtx x, const_rtx find, int count_dest)
692 const char *format_ptr;
711 count = count_occurrences (XEXP (x, 0), find, count_dest);
713 count += count_occurrences (XEXP (x, 1), find, count_dest);
717 if (MEM_P (find) && rtx_equal_p (x, find))
722 if (SET_DEST (x) == find && ! count_dest)
723 return count_occurrences (SET_SRC (x), find, count_dest);
730 format_ptr = GET_RTX_FORMAT (code);
733 for (i = 0; i < GET_RTX_LENGTH (code); i++)
735 switch (*format_ptr++)
738 count += count_occurrences (XEXP (x, i), find, count_dest);
742 for (j = 0; j < XVECLEN (x, i); j++)
743 count += count_occurrences (XVECEXP (x, i, j), find, count_dest);
751 /* Return TRUE if OP is a register or subreg of a register that
752 holds an unsigned quantity. Otherwise, return FALSE. */
755 unsigned_reg_p (rtx op)
759 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op))))
762 if (GET_CODE (op) == SUBREG
763 && SUBREG_PROMOTED_SIGN (op))
770 /* Nonzero if register REG appears somewhere within IN.
771 Also works if REG is not a register; in this case it checks
772 for a subexpression of IN that is Lisp "equal" to REG. */
775 reg_mentioned_p (const_rtx reg, const_rtx in)
787 if (GET_CODE (in) == LABEL_REF)
788 return reg == XEXP (in, 0);
790 code = GET_CODE (in);
794 /* Compare registers by number. */
796 return REG_P (reg) && REGNO (in) == REGNO (reg);
798 /* These codes have no constituent expressions
806 /* These are kept unique for a given value. */
813 if (GET_CODE (reg) == code && rtx_equal_p (reg, in))
816 fmt = GET_RTX_FORMAT (code);
818 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
823 for (j = XVECLEN (in, i) - 1; j >= 0; j--)
824 if (reg_mentioned_p (reg, XVECEXP (in, i, j)))
827 else if (fmt[i] == 'e'
828 && reg_mentioned_p (reg, XEXP (in, i)))
834 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
835 no CODE_LABEL insn. */
838 no_labels_between_p (const rtx_insn *beg, const rtx_insn *end)
843 for (p = NEXT_INSN (beg); p != end; p = NEXT_INSN (p))
849 /* Nonzero if register REG is used in an insn between
850 FROM_INSN and TO_INSN (exclusive of those two). */
853 reg_used_between_p (const_rtx reg, const rtx_insn *from_insn,
854 const rtx_insn *to_insn)
858 if (from_insn == to_insn)
861 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
862 if (NONDEBUG_INSN_P (insn)
863 && (reg_overlap_mentioned_p (reg, PATTERN (insn))
864 || (CALL_P (insn) && find_reg_fusage (insn, USE, reg))))
869 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
870 is entirely replaced by a new value and the only use is as a SET_DEST,
871 we do not consider it a reference. */
874 reg_referenced_p (const_rtx x, const_rtx body)
878 switch (GET_CODE (body))
881 if (reg_overlap_mentioned_p (x, SET_SRC (body)))
884 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
885 of a REG that occupies all of the REG, the insn references X if
886 it is mentioned in the destination. */
887 if (GET_CODE (SET_DEST (body)) != CC0
888 && GET_CODE (SET_DEST (body)) != PC
889 && !REG_P (SET_DEST (body))
890 && ! (GET_CODE (SET_DEST (body)) == SUBREG
891 && REG_P (SUBREG_REG (SET_DEST (body)))
892 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body))))
893 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
894 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body)))
895 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
896 && reg_overlap_mentioned_p (x, SET_DEST (body)))
901 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--)
902 if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i)))
909 return reg_overlap_mentioned_p (x, body);
912 return reg_overlap_mentioned_p (x, TRAP_CONDITION (body));
915 return reg_overlap_mentioned_p (x, XEXP (body, 0));
918 case UNSPEC_VOLATILE:
919 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
920 if (reg_overlap_mentioned_p (x, XVECEXP (body, 0, i)))
925 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
926 if (reg_referenced_p (x, XVECEXP (body, 0, i)))
931 if (MEM_P (XEXP (body, 0)))
932 if (reg_overlap_mentioned_p (x, XEXP (XEXP (body, 0), 0)))
937 if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body)))
939 return reg_referenced_p (x, COND_EXEC_CODE (body));
946 /* Nonzero if register REG is set or clobbered in an insn between
947 FROM_INSN and TO_INSN (exclusive of those two). */
950 reg_set_between_p (const_rtx reg, const_rtx uncast_from_insn, const_rtx to_insn)
952 const rtx_insn *from_insn =
953 safe_as_a <const rtx_insn *> (uncast_from_insn);
954 const rtx_insn *insn;
956 if (from_insn == to_insn)
959 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
960 if (INSN_P (insn) && reg_set_p (reg, insn))
965 /* Internals of reg_set_between_p. */
967 reg_set_p (const_rtx reg, const_rtx insn)
969 /* We can be passed an insn or part of one. If we are passed an insn,
970 check if a side-effect of the insn clobbers REG. */
972 && (FIND_REG_INC_NOTE (insn, reg)
975 && REGNO (reg) < FIRST_PSEUDO_REGISTER
976 && overlaps_hard_reg_set_p (regs_invalidated_by_call,
977 GET_MODE (reg), REGNO (reg)))
979 || find_reg_fusage (insn, CLOBBER, reg)))))
982 return set_of (reg, insn) != NULL_RTX;
985 /* Similar to reg_set_between_p, but check all registers in X. Return 0
986 only if none of them are modified between START and END. Return 1 if
987 X contains a MEM; this routine does use memory aliasing. */
990 modified_between_p (const_rtx x, const rtx_insn *start, const rtx_insn *end)
992 const enum rtx_code code = GET_CODE (x);
1013 if (modified_between_p (XEXP (x, 0), start, end))
1015 if (MEM_READONLY_P (x))
1017 for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn))
1018 if (memory_modified_in_insn_p (x, insn))
1024 return reg_set_between_p (x, start, end);
1030 fmt = GET_RTX_FORMAT (code);
1031 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1033 if (fmt[i] == 'e' && modified_between_p (XEXP (x, i), start, end))
1036 else if (fmt[i] == 'E')
1037 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1038 if (modified_between_p (XVECEXP (x, i, j), start, end))
1045 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1046 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1047 does use memory aliasing. */
1050 modified_in_p (const_rtx x, const_rtx insn)
1052 const enum rtx_code code = GET_CODE (x);
1069 if (modified_in_p (XEXP (x, 0), insn))
1071 if (MEM_READONLY_P (x))
1073 if (memory_modified_in_insn_p (x, insn))
1079 return reg_set_p (x, insn);
1085 fmt = GET_RTX_FORMAT (code);
1086 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1088 if (fmt[i] == 'e' && modified_in_p (XEXP (x, i), insn))
1091 else if (fmt[i] == 'E')
1092 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1093 if (modified_in_p (XVECEXP (x, i, j), insn))
1100 /* Helper function for set_of. */
1108 set_of_1 (rtx x, const_rtx pat, void *data1)
1110 struct set_of_data *const data = (struct set_of_data *) (data1);
1111 if (rtx_equal_p (x, data->pat)
1112 || (!MEM_P (x) && reg_overlap_mentioned_p (data->pat, x)))
1116 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1117 (either directly or via STRICT_LOW_PART and similar modifiers). */
1119 set_of (const_rtx pat, const_rtx insn)
1121 struct set_of_data data;
1122 data.found = NULL_RTX;
1124 note_stores (INSN_P (insn) ? PATTERN (insn) : insn, set_of_1, &data);
1128 /* Add all hard register in X to *PSET. */
1130 find_all_hard_regs (const_rtx x, HARD_REG_SET *pset)
1132 subrtx_iterator::array_type array;
1133 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
1135 const_rtx x = *iter;
1136 if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
1137 add_to_hard_reg_set (pset, GET_MODE (x), REGNO (x));
1141 /* This function, called through note_stores, collects sets and
1142 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1145 record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
1147 HARD_REG_SET *pset = (HARD_REG_SET *)data;
1148 if (REG_P (x) && HARD_REGISTER_P (x))
1149 add_to_hard_reg_set (pset, GET_MODE (x), REGNO (x));
1152 /* Examine INSN, and compute the set of hard registers written by it.
1153 Store it in *PSET. Should only be called after reload. */
1155 find_all_hard_reg_sets (const_rtx insn, HARD_REG_SET *pset, bool implicit)
1159 CLEAR_HARD_REG_SET (*pset);
1160 note_stores (PATTERN (insn), record_hard_reg_sets, pset);
1164 IOR_HARD_REG_SET (*pset, call_used_reg_set);
1166 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
1167 record_hard_reg_sets (XEXP (link, 0), NULL, pset);
1169 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1170 if (REG_NOTE_KIND (link) == REG_INC)
1171 record_hard_reg_sets (XEXP (link, 0), NULL, pset);
1174 /* Like record_hard_reg_sets, but called through note_uses. */
1176 record_hard_reg_uses (rtx *px, void *data)
1178 find_all_hard_regs (*px, (HARD_REG_SET *) data);
1181 /* Given an INSN, return a SET expression if this insn has only a single SET.
1182 It may also have CLOBBERs, USEs, or SET whose output
1183 will not be used, which we ignore. */
1186 single_set_2 (const rtx_insn *insn, const_rtx pat)
1189 int set_verified = 1;
1192 if (GET_CODE (pat) == PARALLEL)
1194 for (i = 0; i < XVECLEN (pat, 0); i++)
1196 rtx sub = XVECEXP (pat, 0, i);
1197 switch (GET_CODE (sub))
1204 /* We can consider insns having multiple sets, where all
1205 but one are dead as single set insns. In common case
1206 only single set is present in the pattern so we want
1207 to avoid checking for REG_UNUSED notes unless necessary.
1209 When we reach set first time, we just expect this is
1210 the single set we are looking for and only when more
1211 sets are found in the insn, we check them. */
1214 if (find_reg_note (insn, REG_UNUSED, SET_DEST (set))
1215 && !side_effects_p (set))
1221 set = sub, set_verified = 0;
1222 else if (!find_reg_note (insn, REG_UNUSED, SET_DEST (sub))
1223 || side_effects_p (sub))
1235 /* Given an INSN, return nonzero if it has more than one SET, else return
1239 multiple_sets (const_rtx insn)
1244 /* INSN must be an insn. */
1245 if (! INSN_P (insn))
1248 /* Only a PARALLEL can have multiple SETs. */
1249 if (GET_CODE (PATTERN (insn)) == PARALLEL)
1251 for (i = 0, found = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1252 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET)
1254 /* If we have already found a SET, then return now. */
1262 /* Either zero or one SET. */
1266 /* Return nonzero if the destination of SET equals the source
1267 and there are no side effects. */
1270 set_noop_p (const_rtx set)
1272 rtx src = SET_SRC (set);
1273 rtx dst = SET_DEST (set);
1275 if (dst == pc_rtx && src == pc_rtx)
1278 if (MEM_P (dst) && MEM_P (src))
1279 return rtx_equal_p (dst, src) && !side_effects_p (dst);
1281 if (GET_CODE (dst) == ZERO_EXTRACT)
1282 return rtx_equal_p (XEXP (dst, 0), src)
1283 && ! BYTES_BIG_ENDIAN && XEXP (dst, 2) == const0_rtx
1284 && !side_effects_p (src);
1286 if (GET_CODE (dst) == STRICT_LOW_PART)
1287 dst = XEXP (dst, 0);
1289 if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG)
1291 if (SUBREG_BYTE (src) != SUBREG_BYTE (dst))
1293 src = SUBREG_REG (src);
1294 dst = SUBREG_REG (dst);
1297 /* It is a NOOP if destination overlaps with selected src vector
1299 if (GET_CODE (src) == VEC_SELECT
1300 && REG_P (XEXP (src, 0)) && REG_P (dst)
1301 && HARD_REGISTER_P (XEXP (src, 0))
1302 && HARD_REGISTER_P (dst))
1305 rtx par = XEXP (src, 1);
1306 rtx src0 = XEXP (src, 0);
1307 int c0 = INTVAL (XVECEXP (par, 0, 0));
1308 HOST_WIDE_INT offset = GET_MODE_UNIT_SIZE (GET_MODE (src0)) * c0;
1310 for (i = 1; i < XVECLEN (par, 0); i++)
1311 if (INTVAL (XVECEXP (par, 0, i)) != c0 + i)
1314 simplify_subreg_regno (REGNO (src0), GET_MODE (src0),
1315 offset, GET_MODE (dst)) == (int) REGNO (dst);
1318 return (REG_P (src) && REG_P (dst)
1319 && REGNO (src) == REGNO (dst));
1322 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1326 noop_move_p (const_rtx insn)
1328 rtx pat = PATTERN (insn);
1330 if (INSN_CODE (insn) == NOOP_MOVE_INSN_CODE)
1333 /* Insns carrying these notes are useful later on. */
1334 if (find_reg_note (insn, REG_EQUAL, NULL_RTX))
1337 /* Check the code to be executed for COND_EXEC. */
1338 if (GET_CODE (pat) == COND_EXEC)
1339 pat = COND_EXEC_CODE (pat);
1341 if (GET_CODE (pat) == SET && set_noop_p (pat))
1344 if (GET_CODE (pat) == PARALLEL)
1347 /* If nothing but SETs of registers to themselves,
1348 this insn can also be deleted. */
1349 for (i = 0; i < XVECLEN (pat, 0); i++)
1351 rtx tem = XVECEXP (pat, 0, i);
1353 if (GET_CODE (tem) == USE
1354 || GET_CODE (tem) == CLOBBER)
1357 if (GET_CODE (tem) != SET || ! set_noop_p (tem))
1367 /* Return nonzero if register in range [REGNO, ENDREGNO)
1368 appears either explicitly or implicitly in X
1369 other than being stored into.
1371 References contained within the substructure at LOC do not count.
1372 LOC may be zero, meaning don't ignore anything. */
1375 refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
1379 unsigned int x_regno;
1384 /* The contents of a REG_NONNEG note is always zero, so we must come here
1385 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1389 code = GET_CODE (x);
1394 x_regno = REGNO (x);
1396 /* If we modifying the stack, frame, or argument pointer, it will
1397 clobber a virtual register. In fact, we could be more precise,
1398 but it isn't worth it. */
1399 if ((x_regno == STACK_POINTER_REGNUM
1400 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1401 || x_regno == ARG_POINTER_REGNUM
1403 || x_regno == FRAME_POINTER_REGNUM)
1404 && regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_REGISTER)
1407 return endregno > x_regno && regno < END_REGNO (x);
1410 /* If this is a SUBREG of a hard reg, we can see exactly which
1411 registers are being modified. Otherwise, handle normally. */
1412 if (REG_P (SUBREG_REG (x))
1413 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
1415 unsigned int inner_regno = subreg_regno (x);
1416 unsigned int inner_endregno
1417 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
1418 ? subreg_nregs (x) : 1);
1420 return endregno > inner_regno && regno < inner_endregno;
1426 if (&SET_DEST (x) != loc
1427 /* Note setting a SUBREG counts as referring to the REG it is in for
1428 a pseudo but not for hard registers since we can
1429 treat each word individually. */
1430 && ((GET_CODE (SET_DEST (x)) == SUBREG
1431 && loc != &SUBREG_REG (SET_DEST (x))
1432 && REG_P (SUBREG_REG (SET_DEST (x)))
1433 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
1434 && refers_to_regno_p (regno, endregno,
1435 SUBREG_REG (SET_DEST (x)), loc))
1436 || (!REG_P (SET_DEST (x))
1437 && refers_to_regno_p (regno, endregno, SET_DEST (x), loc))))
1440 if (code == CLOBBER || loc == &SET_SRC (x))
1449 /* X does not match, so try its subexpressions. */
1451 fmt = GET_RTX_FORMAT (code);
1452 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1454 if (fmt[i] == 'e' && loc != &XEXP (x, i))
1462 if (refers_to_regno_p (regno, endregno, XEXP (x, i), loc))
1465 else if (fmt[i] == 'E')
1468 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1469 if (loc != &XVECEXP (x, i, j)
1470 && refers_to_regno_p (regno, endregno, XVECEXP (x, i, j), loc))
1477 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1478 we check if any register number in X conflicts with the relevant register
1479 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1480 contains a MEM (we don't bother checking for memory addresses that can't
1481 conflict because we expect this to be a rare case. */
1484 reg_overlap_mentioned_p (const_rtx x, const_rtx in)
1486 unsigned int regno, endregno;
1488 /* If either argument is a constant, then modifying X can not
1489 affect IN. Here we look at IN, we can profitably combine
1490 CONSTANT_P (x) with the switch statement below. */
1491 if (CONSTANT_P (in))
1495 switch (GET_CODE (x))
1497 case STRICT_LOW_PART:
1500 /* Overly conservative. */
1505 regno = REGNO (SUBREG_REG (x));
1506 if (regno < FIRST_PSEUDO_REGISTER)
1507 regno = subreg_regno (x);
1508 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
1509 ? subreg_nregs (x) : 1);
1514 endregno = END_REGNO (x);
1516 return refers_to_regno_p (regno, endregno, in, (rtx*) 0);
1526 fmt = GET_RTX_FORMAT (GET_CODE (in));
1527 for (i = GET_RTX_LENGTH (GET_CODE (in)) - 1; i >= 0; i--)
1530 if (reg_overlap_mentioned_p (x, XEXP (in, i)))
1533 else if (fmt[i] == 'E')
1536 for (j = XVECLEN (in, i) - 1; j >= 0; --j)
1537 if (reg_overlap_mentioned_p (x, XVECEXP (in, i, j)))
1547 return reg_mentioned_p (x, in);
1553 /* If any register in here refers to it we return true. */
1554 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
1555 if (XEXP (XVECEXP (x, 0, i), 0) != 0
1556 && reg_overlap_mentioned_p (XEXP (XVECEXP (x, 0, i), 0), in))
1562 gcc_assert (CONSTANT_P (x));
1567 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1568 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1569 ignored by note_stores, but passed to FUN.
1571 FUN receives three arguments:
1572 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1573 2. the SET or CLOBBER rtx that does the store,
1574 3. the pointer DATA provided to note_stores.
1576 If the item being stored in or clobbered is a SUBREG of a hard register,
1577 the SUBREG will be passed. */
1580 note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data)
1584 if (GET_CODE (x) == COND_EXEC)
1585 x = COND_EXEC_CODE (x);
1587 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1589 rtx dest = SET_DEST (x);
1591 while ((GET_CODE (dest) == SUBREG
1592 && (!REG_P (SUBREG_REG (dest))
1593 || REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER))
1594 || GET_CODE (dest) == ZERO_EXTRACT
1595 || GET_CODE (dest) == STRICT_LOW_PART)
1596 dest = XEXP (dest, 0);
1598 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1599 each of whose first operand is a register. */
1600 if (GET_CODE (dest) == PARALLEL)
1602 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
1603 if (XEXP (XVECEXP (dest, 0, i), 0) != 0)
1604 (*fun) (XEXP (XVECEXP (dest, 0, i), 0), x, data);
1607 (*fun) (dest, x, data);
1610 else if (GET_CODE (x) == PARALLEL)
1611 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
1612 note_stores (XVECEXP (x, 0, i), fun, data);
1615 /* Like notes_stores, but call FUN for each expression that is being
1616 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1617 FUN for each expression, not any interior subexpressions. FUN receives a
1618 pointer to the expression and the DATA passed to this function.
1620 Note that this is not quite the same test as that done in reg_referenced_p
1621 since that considers something as being referenced if it is being
1622 partially set, while we do not. */
1625 note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
1630 switch (GET_CODE (body))
1633 (*fun) (&COND_EXEC_TEST (body), data);
1634 note_uses (&COND_EXEC_CODE (body), fun, data);
1638 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1639 note_uses (&XVECEXP (body, 0, i), fun, data);
1643 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1644 note_uses (&PATTERN (XVECEXP (body, 0, i)), fun, data);
1648 (*fun) (&XEXP (body, 0), data);
1652 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--)
1653 (*fun) (&ASM_OPERANDS_INPUT (body, i), data);
1657 (*fun) (&TRAP_CONDITION (body), data);
1661 (*fun) (&XEXP (body, 0), data);
1665 case UNSPEC_VOLATILE:
1666 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1667 (*fun) (&XVECEXP (body, 0, i), data);
1671 if (MEM_P (XEXP (body, 0)))
1672 (*fun) (&XEXP (XEXP (body, 0), 0), data);
1677 rtx dest = SET_DEST (body);
1679 /* For sets we replace everything in source plus registers in memory
1680 expression in store and operands of a ZERO_EXTRACT. */
1681 (*fun) (&SET_SRC (body), data);
1683 if (GET_CODE (dest) == ZERO_EXTRACT)
1685 (*fun) (&XEXP (dest, 1), data);
1686 (*fun) (&XEXP (dest, 2), data);
1689 while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART)
1690 dest = XEXP (dest, 0);
1693 (*fun) (&XEXP (dest, 0), data);
1698 /* All the other possibilities never store. */
1699 (*fun) (pbody, data);
1704 /* Return nonzero if X's old contents don't survive after INSN.
1705 This will be true if X is (cc0) or if X is a register and
1706 X dies in INSN or because INSN entirely sets X.
1708 "Entirely set" means set directly and not through a SUBREG, or
1709 ZERO_EXTRACT, so no trace of the old contents remains.
1710 Likewise, REG_INC does not count.
1712 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1713 but for this use that makes no difference, since regs don't overlap
1714 during their lifetimes. Therefore, this function may be used
1715 at any time after deaths have been computed.
1717 If REG is a hard reg that occupies multiple machine registers, this
1718 function will only return 1 if each of those registers will be replaced
1722 dead_or_set_p (const_rtx insn, const_rtx x)
1724 unsigned int regno, end_regno;
1727 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1728 if (GET_CODE (x) == CC0)
1731 gcc_assert (REG_P (x));
1734 end_regno = END_REGNO (x);
1735 for (i = regno; i < end_regno; i++)
1736 if (! dead_or_set_regno_p (insn, i))
1742 /* Return TRUE iff DEST is a register or subreg of a register and
1743 doesn't change the number of words of the inner register, and any
1744 part of the register is TEST_REGNO. */
1747 covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
1749 unsigned int regno, endregno;
1751 if (GET_CODE (dest) == SUBREG
1752 && (((GET_MODE_SIZE (GET_MODE (dest))
1753 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1754 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
1755 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1756 dest = SUBREG_REG (dest);
1761 regno = REGNO (dest);
1762 endregno = END_REGNO (dest);
1763 return (test_regno >= regno && test_regno < endregno);
1766 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1767 any member matches the covers_regno_no_parallel_p criteria. */
1770 covers_regno_p (const_rtx dest, unsigned int test_regno)
1772 if (GET_CODE (dest) == PARALLEL)
1774 /* Some targets place small structures in registers for return
1775 values of functions, and those registers are wrapped in
1776 PARALLELs that we may see as the destination of a SET. */
1779 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
1781 rtx inner = XEXP (XVECEXP (dest, 0, i), 0);
1782 if (inner != NULL_RTX
1783 && covers_regno_no_parallel_p (inner, test_regno))
1790 return covers_regno_no_parallel_p (dest, test_regno);
1793 /* Utility function for dead_or_set_p to check an individual register. */
1796 dead_or_set_regno_p (const_rtx insn, unsigned int test_regno)
1800 /* See if there is a death note for something that includes TEST_REGNO. */
1801 if (find_regno_note (insn, REG_DEAD, test_regno))
1805 && find_regno_fusage (insn, CLOBBER, test_regno))
1808 pattern = PATTERN (insn);
1810 /* If a COND_EXEC is not executed, the value survives. */
1811 if (GET_CODE (pattern) == COND_EXEC)
1814 if (GET_CODE (pattern) == SET)
1815 return covers_regno_p (SET_DEST (pattern), test_regno);
1816 else if (GET_CODE (pattern) == PARALLEL)
1820 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
1822 rtx body = XVECEXP (pattern, 0, i);
1824 if (GET_CODE (body) == COND_EXEC)
1825 body = COND_EXEC_CODE (body);
1827 if ((GET_CODE (body) == SET || GET_CODE (body) == CLOBBER)
1828 && covers_regno_p (SET_DEST (body), test_regno))
1836 /* Return the reg-note of kind KIND in insn INSN, if there is one.
1837 If DATUM is nonzero, look for one whose datum is DATUM. */
1840 find_reg_note (const_rtx insn, enum reg_note kind, const_rtx datum)
1844 gcc_checking_assert (insn);
1846 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1847 if (! INSN_P (insn))
1851 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1852 if (REG_NOTE_KIND (link) == kind)
1857 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1858 if (REG_NOTE_KIND (link) == kind && datum == XEXP (link, 0))
1863 /* Return the reg-note of kind KIND in insn INSN which applies to register
1864 number REGNO, if any. Return 0 if there is no such reg-note. Note that
1865 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
1866 it might be the case that the note overlaps REGNO. */
1869 find_regno_note (const_rtx insn, enum reg_note kind, unsigned int regno)
1873 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1874 if (! INSN_P (insn))
1877 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1878 if (REG_NOTE_KIND (link) == kind
1879 /* Verify that it is a register, so that scratch and MEM won't cause a
1881 && REG_P (XEXP (link, 0))
1882 && REGNO (XEXP (link, 0)) <= regno
1883 && END_REGNO (XEXP (link, 0)) > regno)
1888 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
1892 find_reg_equal_equiv_note (const_rtx insn)
1899 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1900 if (REG_NOTE_KIND (link) == REG_EQUAL
1901 || REG_NOTE_KIND (link) == REG_EQUIV)
1903 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
1904 insns that have multiple sets. Checking single_set to
1905 make sure of this is not the proper check, as explained
1906 in the comment in set_unique_reg_note.
1908 This should be changed into an assert. */
1909 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1916 /* Check whether INSN is a single_set whose source is known to be
1917 equivalent to a constant. Return that constant if so, otherwise
1921 find_constant_src (const rtx_insn *insn)
1925 set = single_set (insn);
1928 x = avoid_constant_pool_reference (SET_SRC (set));
1933 note = find_reg_equal_equiv_note (insn);
1934 if (note && CONSTANT_P (XEXP (note, 0)))
1935 return XEXP (note, 0);
1940 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
1941 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
1944 find_reg_fusage (const_rtx insn, enum rtx_code code, const_rtx datum)
1946 /* If it's not a CALL_INSN, it can't possibly have a
1947 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
1957 for (link = CALL_INSN_FUNCTION_USAGE (insn);
1959 link = XEXP (link, 1))
1960 if (GET_CODE (XEXP (link, 0)) == code
1961 && rtx_equal_p (datum, XEXP (XEXP (link, 0), 0)))
1966 unsigned int regno = REGNO (datum);
1968 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
1969 to pseudo registers, so don't bother checking. */
1971 if (regno < FIRST_PSEUDO_REGISTER)
1973 unsigned int end_regno = END_HARD_REGNO (datum);
1976 for (i = regno; i < end_regno; i++)
1977 if (find_regno_fusage (insn, code, i))
1985 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
1986 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
1989 find_regno_fusage (const_rtx insn, enum rtx_code code, unsigned int regno)
1993 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
1994 to pseudo registers, so don't bother checking. */
1996 if (regno >= FIRST_PSEUDO_REGISTER
2000 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
2004 if (GET_CODE (op = XEXP (link, 0)) == code
2005 && REG_P (reg = XEXP (op, 0))
2006 && REGNO (reg) <= regno
2007 && END_HARD_REGNO (reg) > regno)
2015 /* Return true if KIND is an integer REG_NOTE. */
2018 int_reg_note_p (enum reg_note kind)
2020 return kind == REG_BR_PROB;
2023 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2024 stored as the pointer to the next register note. */
2027 alloc_reg_note (enum reg_note kind, rtx datum, rtx list)
2031 gcc_checking_assert (!int_reg_note_p (kind));
2036 case REG_LABEL_TARGET:
2037 case REG_LABEL_OPERAND:
2039 /* These types of register notes use an INSN_LIST rather than an
2040 EXPR_LIST, so that copying is done right and dumps look
2042 note = alloc_INSN_LIST (datum, list);
2043 PUT_REG_NOTE_KIND (note, kind);
2047 note = alloc_EXPR_LIST (kind, datum, list);
2054 /* Add register note with kind KIND and datum DATUM to INSN. */
2057 add_reg_note (rtx insn, enum reg_note kind, rtx datum)
2059 REG_NOTES (insn) = alloc_reg_note (kind, datum, REG_NOTES (insn));
2062 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2065 add_int_reg_note (rtx insn, enum reg_note kind, int datum)
2067 gcc_checking_assert (int_reg_note_p (kind));
2068 REG_NOTES (insn) = gen_rtx_INT_LIST ((enum machine_mode) kind,
2069 datum, REG_NOTES (insn));
2072 /* Add a register note like NOTE to INSN. */
2075 add_shallow_copy_of_reg_note (rtx insn, rtx note)
2077 if (GET_CODE (note) == INT_LIST)
2078 add_int_reg_note (insn, REG_NOTE_KIND (note), XINT (note, 0));
2080 add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0));
2083 /* Remove register note NOTE from the REG_NOTES of INSN. */
2086 remove_note (rtx insn, const_rtx note)
2090 if (note == NULL_RTX)
2093 if (REG_NOTES (insn) == note)
2094 REG_NOTES (insn) = XEXP (note, 1);
2096 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2097 if (XEXP (link, 1) == note)
2099 XEXP (link, 1) = XEXP (note, 1);
2103 switch (REG_NOTE_KIND (note))
2107 df_notes_rescan (as_a <rtx_insn *> (insn));
2114 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2117 remove_reg_equal_equiv_notes (rtx insn)
2121 loc = ®_NOTES (insn);
2124 enum reg_note kind = REG_NOTE_KIND (*loc);
2125 if (kind == REG_EQUAL || kind == REG_EQUIV)
2126 *loc = XEXP (*loc, 1);
2128 loc = &XEXP (*loc, 1);
2132 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2135 remove_reg_equal_equiv_notes_for_regno (unsigned int regno)
2142 /* This loop is a little tricky. We cannot just go down the chain because
2143 it is being modified by some actions in the loop. So we just iterate
2144 over the head. We plan to drain the list anyway. */
2145 while ((eq_use = DF_REG_EQ_USE_CHAIN (regno)) != NULL)
2147 rtx_insn *insn = DF_REF_INSN (eq_use);
2148 rtx note = find_reg_equal_equiv_note (insn);
2150 /* This assert is generally triggered when someone deletes a REG_EQUAL
2151 or REG_EQUIV note by hacking the list manually rather than calling
2155 remove_note (insn, note);
2159 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2160 return 1 if it is found. A simple equality test is used to determine if
2164 in_expr_list_p (const_rtx listp, const_rtx node)
2168 for (x = listp; x; x = XEXP (x, 1))
2169 if (node == XEXP (x, 0))
2175 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2176 remove that entry from the list if it is found.
2178 A simple equality test is used to determine if NODE matches. */
2181 remove_node_from_expr_list (const_rtx node, rtx_expr_list **listp)
2183 rtx_expr_list *temp = *listp;
2184 rtx prev = NULL_RTX;
2188 if (node == temp->element ())
2190 /* Splice the node out of the list. */
2192 XEXP (prev, 1) = temp->next ();
2194 *listp = temp->next ();
2200 temp = temp->next ();
2204 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2205 remove that entry from the list if it is found.
2207 A simple equality test is used to determine if NODE matches. */
2210 remove_node_from_insn_list (const rtx_insn *node, rtx_insn_list **listp)
2212 rtx_insn_list *temp = *listp;
2217 if (node == temp->insn ())
2219 /* Splice the node out of the list. */
2221 XEXP (prev, 1) = temp->next ();
2223 *listp = temp->next ();
2229 temp = temp->next ();
2233 /* Nonzero if X contains any volatile instructions. These are instructions
2234 which may cause unpredictable machine state instructions, and thus no
2235 instructions or register uses should be moved or combined across them.
2236 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2239 volatile_insn_p (const_rtx x)
2241 const RTX_CODE code = GET_CODE (x);
2259 case UNSPEC_VOLATILE:
2264 if (MEM_VOLATILE_P (x))
2271 /* Recursively scan the operands of this expression. */
2274 const char *const fmt = GET_RTX_FORMAT (code);
2277 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2281 if (volatile_insn_p (XEXP (x, i)))
2284 else if (fmt[i] == 'E')
2287 for (j = 0; j < XVECLEN (x, i); j++)
2288 if (volatile_insn_p (XVECEXP (x, i, j)))
2296 /* Nonzero if X contains any volatile memory references
2297 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2300 volatile_refs_p (const_rtx x)
2302 const RTX_CODE code = GET_CODE (x);
2318 case UNSPEC_VOLATILE:
2324 if (MEM_VOLATILE_P (x))
2331 /* Recursively scan the operands of this expression. */
2334 const char *const fmt = GET_RTX_FORMAT (code);
2337 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2341 if (volatile_refs_p (XEXP (x, i)))
2344 else if (fmt[i] == 'E')
2347 for (j = 0; j < XVECLEN (x, i); j++)
2348 if (volatile_refs_p (XVECEXP (x, i, j)))
2356 /* Similar to above, except that it also rejects register pre- and post-
2360 side_effects_p (const_rtx x)
2362 const RTX_CODE code = GET_CODE (x);
2379 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2380 when some combination can't be done. If we see one, don't think
2381 that we can simplify the expression. */
2382 return (GET_MODE (x) != VOIDmode);
2391 case UNSPEC_VOLATILE:
2397 if (MEM_VOLATILE_P (x))
2404 /* Recursively scan the operands of this expression. */
2407 const char *fmt = GET_RTX_FORMAT (code);
2410 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2414 if (side_effects_p (XEXP (x, i)))
2417 else if (fmt[i] == 'E')
2420 for (j = 0; j < XVECLEN (x, i); j++)
2421 if (side_effects_p (XVECEXP (x, i, j)))
2429 /* Return nonzero if evaluating rtx X might cause a trap.
2430 FLAGS controls how to consider MEMs. A nonzero means the context
2431 of the access may have changed from the original, such that the
2432 address may have become invalid. */
2435 may_trap_p_1 (const_rtx x, unsigned flags)
2441 /* We make no distinction currently, but this function is part of
2442 the internal target-hooks ABI so we keep the parameter as
2443 "unsigned flags". */
2444 bool code_changed = flags != 0;
2448 code = GET_CODE (x);
2451 /* Handle these cases quickly. */
2463 return targetm.unspec_may_trap_p (x, flags);
2465 case UNSPEC_VOLATILE:
2471 return MEM_VOLATILE_P (x);
2473 /* Memory ref can trap unless it's a static var or a stack slot. */
2475 /* Recognize specific pattern of stack checking probes. */
2476 if (flag_stack_check
2477 && MEM_VOLATILE_P (x)
2478 && XEXP (x, 0) == stack_pointer_rtx)
2480 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2481 reference; moving it out of context such as when moving code
2482 when optimizing, might cause its address to become invalid. */
2484 || !MEM_NOTRAP_P (x))
2486 HOST_WIDE_INT size = MEM_SIZE_KNOWN_P (x) ? MEM_SIZE (x) : 0;
2487 return rtx_addr_can_trap_p_1 (XEXP (x, 0), 0, size,
2488 GET_MODE (x), code_changed);
2493 /* Division by a non-constant might trap. */
2498 if (HONOR_SNANS (GET_MODE (x)))
2500 if (SCALAR_FLOAT_MODE_P (GET_MODE (x)))
2501 return flag_trapping_math;
2502 if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx))
2507 /* An EXPR_LIST is used to represent a function call. This
2508 certainly may trap. */
2517 /* Some floating point comparisons may trap. */
2518 if (!flag_trapping_math)
2520 /* ??? There is no machine independent way to check for tests that trap
2521 when COMPARE is used, though many targets do make this distinction.
2522 For instance, sparc uses CCFPE for compares which generate exceptions
2523 and CCFP for compares which do not generate exceptions. */
2524 if (HONOR_NANS (GET_MODE (x)))
2526 /* But often the compare has some CC mode, so check operand
2528 if (HONOR_NANS (GET_MODE (XEXP (x, 0)))
2529 || HONOR_NANS (GET_MODE (XEXP (x, 1))))
2535 if (HONOR_SNANS (GET_MODE (x)))
2537 /* Often comparison is CC mode, so check operand modes. */
2538 if (HONOR_SNANS (GET_MODE (XEXP (x, 0)))
2539 || HONOR_SNANS (GET_MODE (XEXP (x, 1))))
2544 /* Conversion of floating point might trap. */
2545 if (flag_trapping_math && HONOR_NANS (GET_MODE (XEXP (x, 0))))
2552 /* These operations don't trap even with floating point. */
2556 /* Any floating arithmetic may trap. */
2557 if (SCALAR_FLOAT_MODE_P (GET_MODE (x)) && flag_trapping_math)
2561 fmt = GET_RTX_FORMAT (code);
2562 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2566 if (may_trap_p_1 (XEXP (x, i), flags))
2569 else if (fmt[i] == 'E')
2572 for (j = 0; j < XVECLEN (x, i); j++)
2573 if (may_trap_p_1 (XVECEXP (x, i, j), flags))
2580 /* Return nonzero if evaluating rtx X might cause a trap. */
2583 may_trap_p (const_rtx x)
2585 return may_trap_p_1 (x, 0);
2588 /* Same as above, but additionally return nonzero if evaluating rtx X might
2589 cause a fault. We define a fault for the purpose of this function as a
2590 erroneous execution condition that cannot be encountered during the normal
2591 execution of a valid program; the typical example is an unaligned memory
2592 access on a strict alignment machine. The compiler guarantees that it
2593 doesn't generate code that will fault from a valid program, but this
2594 guarantee doesn't mean anything for individual instructions. Consider
2595 the following example:
2597 struct S { int d; union { char *cp; int *ip; }; };
2599 int foo(struct S *s)
2607 on a strict alignment machine. In a valid program, foo will never be
2608 invoked on a structure for which d is equal to 1 and the underlying
2609 unique field of the union not aligned on a 4-byte boundary, but the
2610 expression *s->ip might cause a fault if considered individually.
2612 At the RTL level, potentially problematic expressions will almost always
2613 verify may_trap_p; for example, the above dereference can be emitted as
2614 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2615 However, suppose that foo is inlined in a caller that causes s->cp to
2616 point to a local character variable and guarantees that s->d is not set
2617 to 1; foo may have been effectively translated into pseudo-RTL as:
2620 (set (reg:SI) (mem:SI (%fp - 7)))
2622 (set (reg:QI) (mem:QI (%fp - 7)))
2624 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2625 memory reference to a stack slot, but it will certainly cause a fault
2626 on a strict alignment machine. */
2629 may_trap_or_fault_p (const_rtx x)
2631 return may_trap_p_1 (x, 1);
2634 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2635 i.e., an inequality. */
2638 inequality_comparisons_p (const_rtx x)
2642 const enum rtx_code code = GET_CODE (x);
2670 len = GET_RTX_LENGTH (code);
2671 fmt = GET_RTX_FORMAT (code);
2673 for (i = 0; i < len; i++)
2677 if (inequality_comparisons_p (XEXP (x, i)))
2680 else if (fmt[i] == 'E')
2683 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2684 if (inequality_comparisons_p (XVECEXP (x, i, j)))
2692 /* Replace any occurrence of FROM in X with TO. The function does
2693 not enter into CONST_DOUBLE for the replace.
2695 Note that copying is not done so X must not be shared unless all copies
2696 are to be modified. */
2699 replace_rtx (rtx x, rtx from, rtx to)
2707 /* Allow this function to make replacements in EXPR_LISTs. */
2711 if (GET_CODE (x) == SUBREG)
2713 rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to);
2715 if (CONST_INT_P (new_rtx))
2717 x = simplify_subreg (GET_MODE (x), new_rtx,
2718 GET_MODE (SUBREG_REG (x)),
2723 SUBREG_REG (x) = new_rtx;
2727 else if (GET_CODE (x) == ZERO_EXTEND)
2729 rtx new_rtx = replace_rtx (XEXP (x, 0), from, to);
2731 if (CONST_INT_P (new_rtx))
2733 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
2734 new_rtx, GET_MODE (XEXP (x, 0)));
2738 XEXP (x, 0) = new_rtx;
2743 fmt = GET_RTX_FORMAT (GET_CODE (x));
2744 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2747 XEXP (x, i) = replace_rtx (XEXP (x, i), from, to);
2748 else if (fmt[i] == 'E')
2749 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2750 XVECEXP (x, i, j) = replace_rtx (XVECEXP (x, i, j), from, to);
2756 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
2757 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
2760 replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
2762 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
2764 if (JUMP_TABLE_DATA_P (x))
2767 rtvec vec = XVEC (x, GET_CODE (x) == ADDR_DIFF_VEC);
2768 int len = GET_NUM_ELEM (vec);
2769 for (int i = 0; i < len; ++i)
2771 rtx ref = RTVEC_ELT (vec, i);
2772 if (XEXP (ref, 0) == old_label)
2774 XEXP (ref, 0) = new_label;
2775 if (update_label_nuses)
2777 ++LABEL_NUSES (new_label);
2778 --LABEL_NUSES (old_label);
2785 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
2786 field. This is not handled by the iterator because it doesn't
2787 handle unprinted ('0') fields. */
2788 if (JUMP_P (x) && JUMP_LABEL (x) == old_label)
2789 JUMP_LABEL (x) = new_label;
2791 subrtx_ptr_iterator::array_type array;
2792 FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL)
2797 if (GET_CODE (x) == SYMBOL_REF
2798 && CONSTANT_POOL_ADDRESS_P (x))
2800 rtx c = get_pool_constant (x);
2801 if (rtx_referenced_p (old_label, c))
2803 /* Create a copy of constant C; replace the label inside
2804 but do not update LABEL_NUSES because uses in constant pool
2806 rtx new_c = copy_rtx (c);
2807 replace_label (&new_c, old_label, new_label, false);
2809 /* Add the new constant NEW_C to constant pool and replace
2810 the old reference to constant by new reference. */
2811 rtx new_mem = force_const_mem (get_pool_mode (x), new_c);
2812 *loc = replace_rtx (x, x, XEXP (new_mem, 0));
2816 if ((GET_CODE (x) == LABEL_REF
2817 || GET_CODE (x) == INSN_LIST)
2818 && XEXP (x, 0) == old_label)
2820 XEXP (x, 0) = new_label;
2821 if (update_label_nuses)
2823 ++LABEL_NUSES (new_label);
2824 --LABEL_NUSES (old_label);
2832 replace_label_in_insn (rtx_insn *insn, rtx old_label, rtx new_label,
2833 bool update_label_nuses)
2835 rtx insn_as_rtx = insn;
2836 replace_label (&insn_as_rtx, old_label, new_label, update_label_nuses);
2837 gcc_checking_assert (insn_as_rtx == insn);
2840 /* Return true if X is referenced in BODY. */
2843 rtx_referenced_p (const_rtx x, const_rtx body)
2845 subrtx_iterator::array_type array;
2846 FOR_EACH_SUBRTX (iter, array, body, ALL)
2847 if (const_rtx y = *iter)
2849 /* Check if a label_ref Y refers to label X. */
2850 if (GET_CODE (y) == LABEL_REF && LABEL_P (x) && XEXP (y, 0) == x)
2853 if (rtx_equal_p (x, y))
2856 /* If Y is a reference to pool constant traverse the constant. */
2857 if (GET_CODE (y) == SYMBOL_REF
2858 && CONSTANT_POOL_ADDRESS_P (y))
2859 iter.substitute (get_pool_constant (y));
2864 /* If INSN is a tablejump return true and store the label (before jump table) to
2865 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
2868 tablejump_p (const rtx_insn *insn, rtx *labelp, rtx_jump_table_data **tablep)
2875 label = JUMP_LABEL (insn);
2876 if (label != NULL_RTX && !ANY_RETURN_P (label)
2877 && (table = NEXT_INSN (as_a <rtx_insn *> (label))) != NULL_RTX
2878 && JUMP_TABLE_DATA_P (table))
2883 *tablep = as_a <rtx_jump_table_data *> (table);
2889 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
2890 constant that is not in the constant pool and not in the condition
2891 of an IF_THEN_ELSE. */
2894 computed_jump_p_1 (const_rtx x)
2896 const enum rtx_code code = GET_CODE (x);
2913 return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
2914 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
2917 return (computed_jump_p_1 (XEXP (x, 1))
2918 || computed_jump_p_1 (XEXP (x, 2)));
2924 fmt = GET_RTX_FORMAT (code);
2925 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2928 && computed_jump_p_1 (XEXP (x, i)))
2931 else if (fmt[i] == 'E')
2932 for (j = 0; j < XVECLEN (x, i); j++)
2933 if (computed_jump_p_1 (XVECEXP (x, i, j)))
2940 /* Return nonzero if INSN is an indirect jump (aka computed jump).
2942 Tablejumps and casesi insns are not considered indirect jumps;
2943 we can recognize them by a (use (label_ref)). */
2946 computed_jump_p (const_rtx insn)
2951 rtx pat = PATTERN (insn);
2953 /* If we have a JUMP_LABEL set, we're not a computed jump. */
2954 if (JUMP_LABEL (insn) != NULL)
2957 if (GET_CODE (pat) == PARALLEL)
2959 int len = XVECLEN (pat, 0);
2960 int has_use_labelref = 0;
2962 for (i = len - 1; i >= 0; i--)
2963 if (GET_CODE (XVECEXP (pat, 0, i)) == USE
2964 && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))
2967 has_use_labelref = 1;
2971 if (! has_use_labelref)
2972 for (i = len - 1; i >= 0; i--)
2973 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
2974 && SET_DEST (XVECEXP (pat, 0, i)) == pc_rtx
2975 && computed_jump_p_1 (SET_SRC (XVECEXP (pat, 0, i))))
2978 else if (GET_CODE (pat) == SET
2979 && SET_DEST (pat) == pc_rtx
2980 && computed_jump_p_1 (SET_SRC (pat)))
2986 /* Optimized loop of for_each_rtx, trying to avoid useless recursive
2987 calls. Processes the subexpressions of EXP and passes them to F. */
2989 for_each_rtx_1 (rtx exp, int n, rtx_function f, void *data)
2992 const char *format = GET_RTX_FORMAT (GET_CODE (exp));
2995 for (; format[n] != '\0'; n++)
3002 result = (*f) (x, data);
3004 /* Do not traverse sub-expressions. */
3006 else if (result != 0)
3007 /* Stop the traversal. */
3011 /* There are no sub-expressions. */
3014 i = non_rtx_starting_operands[GET_CODE (*x)];
3017 result = for_each_rtx_1 (*x, i, f, data);
3025 if (XVEC (exp, n) == 0)
3027 for (j = 0; j < XVECLEN (exp, n); ++j)
3030 x = &XVECEXP (exp, n, j);
3031 result = (*f) (x, data);
3033 /* Do not traverse sub-expressions. */
3035 else if (result != 0)
3036 /* Stop the traversal. */
3040 /* There are no sub-expressions. */
3043 i = non_rtx_starting_operands[GET_CODE (*x)];
3046 result = for_each_rtx_1 (*x, i, f, data);
3054 /* Nothing to do. */
3062 /* Traverse X via depth-first search, calling F for each
3063 sub-expression (including X itself). F is also passed the DATA.
3064 If F returns -1, do not traverse sub-expressions, but continue
3065 traversing the rest of the tree. If F ever returns any other
3066 nonzero value, stop the traversal, and return the value returned
3067 by F. Otherwise, return 0. This function does not traverse inside
3068 tree structure that contains RTX_EXPRs, or into sub-expressions
3069 whose format code is `0' since it is not known whether or not those
3070 codes are actually RTL.
3072 This routine is very general, and could (should?) be used to
3073 implement many of the other routines in this file. */
3076 for_each_rtx (rtx *x, rtx_function f, void *data)
3082 result = (*f) (x, data);
3084 /* Do not traverse sub-expressions. */
3086 else if (result != 0)
3087 /* Stop the traversal. */
3091 /* There are no sub-expressions. */
3094 i = non_rtx_starting_operands[GET_CODE (*x)];
3098 return for_each_rtx_1 (*x, i, f, data);
3101 /* Like "for_each_rtx", but for calling on an rtx_insn **. */
3104 for_each_rtx_in_insn (rtx_insn **insn, rtx_function f, void *data)
3106 rtx insn_as_rtx = *insn;
3109 result = for_each_rtx (&insn_as_rtx, f, data);
3111 if (insn_as_rtx != *insn)
3112 *insn = safe_as_a <rtx_insn *> (insn_as_rtx);
3119 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3120 the equivalent add insn and pass the result to FN, using DATA as the
3124 for_each_inc_dec_find_inc_dec (rtx mem, for_each_inc_dec_fn fn, void *data)
3126 rtx x = XEXP (mem, 0);
3127 switch (GET_CODE (x))
3132 int size = GET_MODE_SIZE (GET_MODE (mem));
3133 rtx r1 = XEXP (x, 0);
3134 rtx c = gen_int_mode (size, GET_MODE (r1));
3135 return fn (mem, x, r1, r1, c, data);
3141 int size = GET_MODE_SIZE (GET_MODE (mem));
3142 rtx r1 = XEXP (x, 0);
3143 rtx c = gen_int_mode (-size, GET_MODE (r1));
3144 return fn (mem, x, r1, r1, c, data);
3150 rtx r1 = XEXP (x, 0);
3151 rtx add = XEXP (x, 1);
3152 return fn (mem, x, r1, add, NULL, data);
3160 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3161 For each such autoinc operation found, call FN, passing it
3162 the innermost enclosing MEM, the operation itself, the RTX modified
3163 by the operation, two RTXs (the second may be NULL) that, once
3164 added, represent the value to be held by the modified RTX
3165 afterwards, and DATA. FN is to return 0 to continue the
3166 traversal or any other value to have it returned to the caller of
3167 for_each_inc_dec. */
3170 for_each_inc_dec (rtx x,
3171 for_each_inc_dec_fn fn,
3174 subrtx_var_iterator::array_type array;
3175 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
3180 && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0))) == RTX_AUTOINC)
3182 int res = for_each_inc_dec_find_inc_dec (mem, fn, data);
3185 iter.skip_subrtxes ();
3192 /* Searches X for any reference to REGNO, returning the rtx of the
3193 reference found if any. Otherwise, returns NULL_RTX. */
3196 regno_use_in (unsigned int regno, rtx x)
3202 if (REG_P (x) && REGNO (x) == regno)
3205 fmt = GET_RTX_FORMAT (GET_CODE (x));
3206 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3210 if ((tem = regno_use_in (regno, XEXP (x, i))))
3213 else if (fmt[i] == 'E')
3214 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3215 if ((tem = regno_use_in (regno , XVECEXP (x, i, j))))
3222 /* Return a value indicating whether OP, an operand of a commutative
3223 operation, is preferred as the first or second operand. The higher
3224 the value, the stronger the preference for being the first operand.
3225 We use negative values to indicate a preference for the first operand
3226 and positive values for the second operand. */
3229 commutative_operand_precedence (rtx op)
3231 enum rtx_code code = GET_CODE (op);
3233 /* Constants always come the second operand. Prefer "nice" constants. */
3234 if (code == CONST_INT)
3236 if (code == CONST_WIDE_INT)
3238 if (code == CONST_DOUBLE)
3240 if (code == CONST_FIXED)
3242 op = avoid_constant_pool_reference (op);
3243 code = GET_CODE (op);
3245 switch (GET_RTX_CLASS (code))
3248 if (code == CONST_INT)
3250 if (code == CONST_WIDE_INT)
3252 if (code == CONST_DOUBLE)
3254 if (code == CONST_FIXED)
3259 /* SUBREGs of objects should come second. */
3260 if (code == SUBREG && OBJECT_P (SUBREG_REG (op)))
3265 /* Complex expressions should be the first, so decrease priority
3266 of objects. Prefer pointer objects over non pointer objects. */
3267 if ((REG_P (op) && REG_POINTER (op))
3268 || (MEM_P (op) && MEM_POINTER (op)))
3272 case RTX_COMM_ARITH:
3273 /* Prefer operands that are themselves commutative to be first.
3274 This helps to make things linear. In particular,
3275 (and (and (reg) (reg)) (not (reg))) is canonical. */
3279 /* If only one operand is a binary expression, it will be the first
3280 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3281 is canonical, although it will usually be further simplified. */
3285 /* Then prefer NEG and NOT. */
3286 if (code == NEG || code == NOT)
3294 /* Return 1 iff it is necessary to swap operands of commutative operation
3295 in order to canonicalize expression. */
3298 swap_commutative_operands_p (rtx x, rtx y)
3300 return (commutative_operand_precedence (x)
3301 < commutative_operand_precedence (y));
3304 /* Return 1 if X is an autoincrement side effect and the register is
3305 not the stack pointer. */
3307 auto_inc_p (const_rtx x)
3309 switch (GET_CODE (x))
3317 /* There are no REG_INC notes for SP. */
3318 if (XEXP (x, 0) != stack_pointer_rtx)
3326 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3328 loc_mentioned_in_p (rtx *loc, const_rtx in)
3337 code = GET_CODE (in);
3338 fmt = GET_RTX_FORMAT (code);
3339 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3343 if (loc == &XEXP (in, i) || loc_mentioned_in_p (loc, XEXP (in, i)))
3346 else if (fmt[i] == 'E')
3347 for (j = XVECLEN (in, i) - 1; j >= 0; j--)
3348 if (loc == &XVECEXP (in, i, j)
3349 || loc_mentioned_in_p (loc, XVECEXP (in, i, j)))
3355 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3356 and SUBREG_BYTE, return the bit offset where the subreg begins
3357 (counting from the least significant bit of the operand). */
3360 subreg_lsb_1 (enum machine_mode outer_mode,
3361 enum machine_mode inner_mode,
3362 unsigned int subreg_byte)
3364 unsigned int bitpos;
3368 /* A paradoxical subreg begins at bit position 0. */
3369 if (GET_MODE_PRECISION (outer_mode) > GET_MODE_PRECISION (inner_mode))
3372 if (WORDS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
3373 /* If the subreg crosses a word boundary ensure that
3374 it also begins and ends on a word boundary. */
3375 gcc_assert (!((subreg_byte % UNITS_PER_WORD
3376 + GET_MODE_SIZE (outer_mode)) > UNITS_PER_WORD
3377 && (subreg_byte % UNITS_PER_WORD
3378 || GET_MODE_SIZE (outer_mode) % UNITS_PER_WORD)));
3380 if (WORDS_BIG_ENDIAN)
3381 word = (GET_MODE_SIZE (inner_mode)
3382 - (subreg_byte + GET_MODE_SIZE (outer_mode))) / UNITS_PER_WORD;
3384 word = subreg_byte / UNITS_PER_WORD;
3385 bitpos = word * BITS_PER_WORD;
3387 if (BYTES_BIG_ENDIAN)
3388 byte = (GET_MODE_SIZE (inner_mode)
3389 - (subreg_byte + GET_MODE_SIZE (outer_mode))) % UNITS_PER_WORD;
3391 byte = subreg_byte % UNITS_PER_WORD;
3392 bitpos += byte * BITS_PER_UNIT;
3397 /* Given a subreg X, return the bit offset where the subreg begins
3398 (counting from the least significant bit of the reg). */
3401 subreg_lsb (const_rtx x)
3403 return subreg_lsb_1 (GET_MODE (x), GET_MODE (SUBREG_REG (x)),
3407 /* Fill in information about a subreg of a hard register.
3408 xregno - A regno of an inner hard subreg_reg (or what will become one).
3409 xmode - The mode of xregno.
3410 offset - The byte offset.
3411 ymode - The mode of a top level SUBREG (or what may become one).
3412 info - Pointer to structure to fill in. */
3414 subreg_get_info (unsigned int xregno, enum machine_mode xmode,
3415 unsigned int offset, enum machine_mode ymode,
3416 struct subreg_info *info)
3418 int nregs_xmode, nregs_ymode;
3419 int mode_multiple, nregs_multiple;
3420 int offset_adj, y_offset, y_offset_adj;
3421 int regsize_xmode, regsize_ymode;
3424 gcc_assert (xregno < FIRST_PSEUDO_REGISTER);
3428 /* If there are holes in a non-scalar mode in registers, we expect
3429 that it is made up of its units concatenated together. */
3430 if (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode))
3432 enum machine_mode xmode_unit;
3434 nregs_xmode = HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode);
3435 if (GET_MODE_INNER (xmode) == VOIDmode)
3438 xmode_unit = GET_MODE_INNER (xmode);
3439 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode_unit));
3440 gcc_assert (nregs_xmode
3441 == (GET_MODE_NUNITS (xmode)
3442 * HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode_unit)));
3443 gcc_assert (hard_regno_nregs[xregno][xmode]
3444 == (hard_regno_nregs[xregno][xmode_unit]
3445 * GET_MODE_NUNITS (xmode)));
3447 /* You can only ask for a SUBREG of a value with holes in the middle
3448 if you don't cross the holes. (Such a SUBREG should be done by
3449 picking a different register class, or doing it in memory if
3450 necessary.) An example of a value with holes is XCmode on 32-bit
3451 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3452 3 for each part, but in memory it's two 128-bit parts.
3453 Padding is assumed to be at the end (not necessarily the 'high part')
3455 if ((offset / GET_MODE_SIZE (xmode_unit) + 1
3456 < GET_MODE_NUNITS (xmode))
3457 && (offset / GET_MODE_SIZE (xmode_unit)
3458 != ((offset + GET_MODE_SIZE (ymode) - 1)
3459 / GET_MODE_SIZE (xmode_unit))))
3461 info->representable_p = false;
3466 nregs_xmode = hard_regno_nregs[xregno][xmode];
3468 nregs_ymode = hard_regno_nregs[xregno][ymode];
3470 /* Paradoxical subregs are otherwise valid. */
3473 && GET_MODE_PRECISION (ymode) > GET_MODE_PRECISION (xmode))
3475 info->representable_p = true;
3476 /* If this is a big endian paradoxical subreg, which uses more
3477 actual hard registers than the original register, we must
3478 return a negative offset so that we find the proper highpart
3480 if (GET_MODE_SIZE (ymode) > UNITS_PER_WORD
3481 ? REG_WORDS_BIG_ENDIAN : BYTES_BIG_ENDIAN)
3482 info->offset = nregs_xmode - nregs_ymode;
3485 info->nregs = nregs_ymode;
3489 /* If registers store different numbers of bits in the different
3490 modes, we cannot generally form this subreg. */
3491 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)
3492 && !HARD_REGNO_NREGS_HAS_PADDING (xregno, ymode)
3493 && (GET_MODE_SIZE (xmode) % nregs_xmode) == 0
3494 && (GET_MODE_SIZE (ymode) % nregs_ymode) == 0)
3496 regsize_xmode = GET_MODE_SIZE (xmode) / nregs_xmode;
3497 regsize_ymode = GET_MODE_SIZE (ymode) / nregs_ymode;
3498 if (!rknown && regsize_xmode > regsize_ymode && nregs_ymode > 1)
3500 info->representable_p = false;
3502 = (GET_MODE_SIZE (ymode) + regsize_xmode - 1) / regsize_xmode;
3503 info->offset = offset / regsize_xmode;
3506 if (!rknown && regsize_ymode > regsize_xmode && nregs_xmode > 1)
3508 info->representable_p = false;
3510 = (GET_MODE_SIZE (ymode) + regsize_xmode - 1) / regsize_xmode;
3511 info->offset = offset / regsize_xmode;
3516 /* Lowpart subregs are otherwise valid. */
3517 if (!rknown && offset == subreg_lowpart_offset (ymode, xmode))
3519 info->representable_p = true;
3522 if (offset == 0 || nregs_xmode == nregs_ymode)
3525 info->nregs = nregs_ymode;
3530 /* This should always pass, otherwise we don't know how to verify
3531 the constraint. These conditions may be relaxed but
3532 subreg_regno_offset would need to be redesigned. */
3533 gcc_assert ((GET_MODE_SIZE (xmode) % GET_MODE_SIZE (ymode)) == 0);
3534 gcc_assert ((nregs_xmode % nregs_ymode) == 0);
3536 if (WORDS_BIG_ENDIAN != REG_WORDS_BIG_ENDIAN
3537 && GET_MODE_SIZE (xmode) > UNITS_PER_WORD)
3539 HOST_WIDE_INT xsize = GET_MODE_SIZE (xmode);
3540 HOST_WIDE_INT ysize = GET_MODE_SIZE (ymode);
3541 HOST_WIDE_INT off_low = offset & (ysize - 1);
3542 HOST_WIDE_INT off_high = offset & ~(ysize - 1);
3543 offset = (xsize - ysize - off_high) | off_low;
3545 /* The XMODE value can be seen as a vector of NREGS_XMODE
3546 values. The subreg must represent a lowpart of given field.
3547 Compute what field it is. */
3548 offset_adj = offset;
3549 offset_adj -= subreg_lowpart_offset (ymode,
3550 mode_for_size (GET_MODE_BITSIZE (xmode)
3554 /* Size of ymode must not be greater than the size of xmode. */
3555 mode_multiple = GET_MODE_SIZE (xmode) / GET_MODE_SIZE (ymode);
3556 gcc_assert (mode_multiple != 0);
3558 y_offset = offset / GET_MODE_SIZE (ymode);
3559 y_offset_adj = offset_adj / GET_MODE_SIZE (ymode);
3560 nregs_multiple = nregs_xmode / nregs_ymode;
3562 gcc_assert ((offset_adj % GET_MODE_SIZE (ymode)) == 0);
3563 gcc_assert ((mode_multiple % nregs_multiple) == 0);
3567 info->representable_p = (!(y_offset_adj % (mode_multiple / nregs_multiple)));
3570 info->offset = (y_offset / (mode_multiple / nregs_multiple)) * nregs_ymode;
3571 info->nregs = nregs_ymode;
3574 /* This function returns the regno offset of a subreg expression.
3575 xregno - A regno of an inner hard subreg_reg (or what will become one).
3576 xmode - The mode of xregno.
3577 offset - The byte offset.
3578 ymode - The mode of a top level SUBREG (or what may become one).
3579 RETURN - The regno offset which would be used. */
3581 subreg_regno_offset (unsigned int xregno, enum machine_mode xmode,
3582 unsigned int offset, enum machine_mode ymode)
3584 struct subreg_info info;
3585 subreg_get_info (xregno, xmode, offset, ymode, &info);
3589 /* This function returns true when the offset is representable via
3590 subreg_offset in the given regno.
3591 xregno - A regno of an inner hard subreg_reg (or what will become one).
3592 xmode - The mode of xregno.
3593 offset - The byte offset.
3594 ymode - The mode of a top level SUBREG (or what may become one).
3595 RETURN - Whether the offset is representable. */
3597 subreg_offset_representable_p (unsigned int xregno, enum machine_mode xmode,
3598 unsigned int offset, enum machine_mode ymode)
3600 struct subreg_info info;
3601 subreg_get_info (xregno, xmode, offset, ymode, &info);
3602 return info.representable_p;
3605 /* Return the number of a YMODE register to which
3607 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3609 can be simplified. Return -1 if the subreg can't be simplified.
3611 XREGNO is a hard register number. */
3614 simplify_subreg_regno (unsigned int xregno, enum machine_mode xmode,
3615 unsigned int offset, enum machine_mode ymode)
3617 struct subreg_info info;
3618 unsigned int yregno;
3620 #ifdef CANNOT_CHANGE_MODE_CLASS
3621 /* Give the backend a chance to disallow the mode change. */
3622 if (GET_MODE_CLASS (xmode) != MODE_COMPLEX_INT
3623 && GET_MODE_CLASS (xmode) != MODE_COMPLEX_FLOAT
3624 && REG_CANNOT_CHANGE_MODE_P (xregno, xmode, ymode)
3625 /* We can use mode change in LRA for some transformations. */
3626 && ! lra_in_progress)
3630 /* We shouldn't simplify stack-related registers. */
3631 if ((!reload_completed || frame_pointer_needed)
3632 && xregno == FRAME_POINTER_REGNUM)
3635 if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3636 && xregno == ARG_POINTER_REGNUM)
3639 if (xregno == STACK_POINTER_REGNUM
3640 /* We should convert hard stack register in LRA if it is
3642 && ! lra_in_progress)
3645 /* Try to get the register offset. */
3646 subreg_get_info (xregno, xmode, offset, ymode, &info);
3647 if (!info.representable_p)
3650 /* Make sure that the offsetted register value is in range. */
3651 yregno = xregno + info.offset;
3652 if (!HARD_REGISTER_NUM_P (yregno))
3655 /* See whether (reg:YMODE YREGNO) is valid.
3657 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3658 This is a kludge to work around how complex FP arguments are passed
3659 on IA-64 and should be fixed. See PR target/49226. */
3660 if (!HARD_REGNO_MODE_OK (yregno, ymode)
3661 && HARD_REGNO_MODE_OK (xregno, xmode))
3664 return (int) yregno;
3667 /* Return the final regno that a subreg expression refers to. */
3669 subreg_regno (const_rtx x)
3672 rtx subreg = SUBREG_REG (x);
3673 int regno = REGNO (subreg);
3675 ret = regno + subreg_regno_offset (regno,
3683 /* Return the number of registers that a subreg expression refers
3686 subreg_nregs (const_rtx x)
3688 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x)), x);
3691 /* Return the number of registers that a subreg REG with REGNO
3692 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3693 changed so that the regno can be passed in. */
3696 subreg_nregs_with_regno (unsigned int regno, const_rtx x)
3698 struct subreg_info info;
3699 rtx subreg = SUBREG_REG (x);
3701 subreg_get_info (regno, GET_MODE (subreg), SUBREG_BYTE (x), GET_MODE (x),
3707 struct parms_set_data
3713 /* Helper function for noticing stores to parameter registers. */
3715 parms_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
3717 struct parms_set_data *const d = (struct parms_set_data *) data;
3718 if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER
3719 && TEST_HARD_REG_BIT (d->regs, REGNO (x)))
3721 CLEAR_HARD_REG_BIT (d->regs, REGNO (x));
3726 /* Look backward for first parameter to be loaded.
3727 Note that loads of all parameters will not necessarily be
3728 found if CSE has eliminated some of them (e.g., an argument
3729 to the outer function is passed down as a parameter).
3730 Do not skip BOUNDARY. */
3732 find_first_parameter_load (rtx_insn *call_insn, rtx_insn *boundary)
3734 struct parms_set_data parm;
3736 rtx_insn *before, *first_set;
3738 /* Since different machines initialize their parameter registers
3739 in different orders, assume nothing. Collect the set of all
3740 parameter registers. */
3741 CLEAR_HARD_REG_SET (parm.regs);
3743 for (p = CALL_INSN_FUNCTION_USAGE (call_insn); p; p = XEXP (p, 1))
3744 if (GET_CODE (XEXP (p, 0)) == USE
3745 && REG_P (XEXP (XEXP (p, 0), 0)))
3747 gcc_assert (REGNO (XEXP (XEXP (p, 0), 0)) < FIRST_PSEUDO_REGISTER);
3749 /* We only care about registers which can hold function
3751 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p, 0), 0))))
3754 SET_HARD_REG_BIT (parm.regs, REGNO (XEXP (XEXP (p, 0), 0)));
3758 first_set = call_insn;
3760 /* Search backward for the first set of a register in this set. */
3761 while (parm.nregs && before != boundary)
3763 before = PREV_INSN (before);
3765 /* It is possible that some loads got CSEed from one call to
3766 another. Stop in that case. */
3767 if (CALL_P (before))
3770 /* Our caller needs either ensure that we will find all sets
3771 (in case code has not been optimized yet), or take care
3772 for possible labels in a way by setting boundary to preceding
3774 if (LABEL_P (before))
3776 gcc_assert (before == boundary);
3780 if (INSN_P (before))
3782 int nregs_old = parm.nregs;
3783 note_stores (PATTERN (before), parms_set, &parm);
3784 /* If we found something that did not set a parameter reg,
3785 we're done. Do not keep going, as that might result
3786 in hoisting an insn before the setting of a pseudo
3787 that is used by the hoisted insn. */
3788 if (nregs_old != parm.nregs)
3797 /* Return true if we should avoid inserting code between INSN and preceding
3798 call instruction. */
3801 keep_with_call_p (const rtx_insn *insn)
3805 if (INSN_P (insn) && (set = single_set (insn)) != NULL)
3807 if (REG_P (SET_DEST (set))
3808 && REGNO (SET_DEST (set)) < FIRST_PSEUDO_REGISTER
3809 && fixed_regs[REGNO (SET_DEST (set))]
3810 && general_operand (SET_SRC (set), VOIDmode))
3812 if (REG_P (SET_SRC (set))
3813 && targetm.calls.function_value_regno_p (REGNO (SET_SRC (set)))
3814 && REG_P (SET_DEST (set))
3815 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER)
3817 /* There may be a stack pop just after the call and before the store
3818 of the return register. Search for the actual store when deciding
3819 if we can break or not. */
3820 if (SET_DEST (set) == stack_pointer_rtx)
3822 /* This CONST_CAST is okay because next_nonnote_insn just
3823 returns its argument and we assign it to a const_rtx
3826 = next_nonnote_insn (const_cast<rtx_insn *> (insn));
3827 if (i2 && keep_with_call_p (i2))
3834 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3835 to non-complex jumps. That is, direct unconditional, conditional,
3836 and tablejumps, but not computed jumps or returns. It also does
3837 not apply to the fallthru case of a conditional jump. */
3840 label_is_jump_target_p (const_rtx label, const rtx_insn *jump_insn)
3842 rtx tmp = JUMP_LABEL (jump_insn);
3843 rtx_jump_table_data *table;
3848 if (tablejump_p (jump_insn, NULL, &table))
3850 rtvec vec = table->get_labels ();
3851 int i, veclen = GET_NUM_ELEM (vec);
3853 for (i = 0; i < veclen; ++i)
3854 if (XEXP (RTVEC_ELT (vec, i), 0) == label)
3858 if (find_reg_note (jump_insn, REG_LABEL_TARGET, label))
3865 /* Return an estimate of the cost of computing rtx X.
3866 One use is in cse, to decide which expression to keep in the hash table.
3867 Another is in rtl generation, to pick the cheapest way to multiply.
3868 Other uses like the latter are expected in the future.
3870 X appears as operand OPNO in an expression with code OUTER_CODE.
3871 SPEED specifies whether costs optimized for speed or size should
3875 rtx_cost (rtx x, enum rtx_code outer_code, int opno, bool speed)
3886 /* A size N times larger than UNITS_PER_WORD likely needs N times as
3887 many insns, taking N times as long. */
3888 factor = GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD;
3892 /* Compute the default costs of certain things.
3893 Note that targetm.rtx_costs can override the defaults. */
3895 code = GET_CODE (x);
3899 /* Multiplication has time-complexity O(N*N), where N is the
3900 number of units (translated from digits) when using
3901 schoolbook long multiplication. */
3902 total = factor * factor * COSTS_N_INSNS (5);
3908 /* Similarly, complexity for schoolbook long division. */
3909 total = factor * factor * COSTS_N_INSNS (7);
3912 /* Used in combine.c as a marker. */
3916 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
3917 the mode for the factor. */
3918 factor = GET_MODE_SIZE (GET_MODE (SET_DEST (x))) / UNITS_PER_WORD;
3923 total = factor * COSTS_N_INSNS (1);
3933 /* If we can't tie these modes, make this expensive. The larger
3934 the mode, the more expensive it is. */
3935 if (! MODES_TIEABLE_P (GET_MODE (x), GET_MODE (SUBREG_REG (x))))
3936 return COSTS_N_INSNS (2 + factor);
3940 if (targetm.rtx_costs (x, code, outer_code, opno, &total, speed))
3945 /* Sum the costs of the sub-rtx's, plus cost of this operation,
3946 which is already in total. */
3948 fmt = GET_RTX_FORMAT (code);
3949 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3951 total += rtx_cost (XEXP (x, i), code, i, speed);
3952 else if (fmt[i] == 'E')
3953 for (j = 0; j < XVECLEN (x, i); j++)
3954 total += rtx_cost (XVECEXP (x, i, j), code, i, speed);
3959 /* Fill in the structure C with information about both speed and size rtx
3960 costs for X, which is operand OPNO in an expression with code OUTER. */
3963 get_full_rtx_cost (rtx x, enum rtx_code outer, int opno,
3964 struct full_rtx_costs *c)
3966 c->speed = rtx_cost (x, outer, opno, true);
3967 c->size = rtx_cost (x, outer, opno, false);
3971 /* Return cost of address expression X.
3972 Expect that X is properly formed address reference.
3974 SPEED parameter specify whether costs optimized for speed or size should
3978 address_cost (rtx x, enum machine_mode mode, addr_space_t as, bool speed)
3980 /* We may be asked for cost of various unusual addresses, such as operands
3981 of push instruction. It is not worthwhile to complicate writing
3982 of the target hook by such cases. */
3984 if (!memory_address_addr_space_p (mode, x, as))
3987 return targetm.address_cost (x, mode, as, speed);
3990 /* If the target doesn't override, compute the cost as with arithmetic. */
3993 default_address_cost (rtx x, enum machine_mode, addr_space_t, bool speed)
3995 return rtx_cost (x, MEM, 0, speed);
3999 unsigned HOST_WIDE_INT
4000 nonzero_bits (const_rtx x, enum machine_mode mode)
4002 return cached_nonzero_bits (x, mode, NULL_RTX, VOIDmode, 0);
4006 num_sign_bit_copies (const_rtx x, enum machine_mode mode)
4008 return cached_num_sign_bit_copies (x, mode, NULL_RTX, VOIDmode, 0);
4011 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4012 It avoids exponential behavior in nonzero_bits1 when X has
4013 identical subexpressions on the first or the second level. */
4015 static unsigned HOST_WIDE_INT
4016 cached_nonzero_bits (const_rtx x, enum machine_mode mode, const_rtx known_x,
4017 enum machine_mode known_mode,
4018 unsigned HOST_WIDE_INT known_ret)
4020 if (x == known_x && mode == known_mode)
4023 /* Try to find identical subexpressions. If found call
4024 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4025 precomputed value for the subexpression as KNOWN_RET. */
4027 if (ARITHMETIC_P (x))
4029 rtx x0 = XEXP (x, 0);
4030 rtx x1 = XEXP (x, 1);
4032 /* Check the first level. */
4034 return nonzero_bits1 (x, mode, x0, mode,
4035 cached_nonzero_bits (x0, mode, known_x,
4036 known_mode, known_ret));
4038 /* Check the second level. */
4039 if (ARITHMETIC_P (x0)
4040 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
4041 return nonzero_bits1 (x, mode, x1, mode,
4042 cached_nonzero_bits (x1, mode, known_x,
4043 known_mode, known_ret));
4045 if (ARITHMETIC_P (x1)
4046 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
4047 return nonzero_bits1 (x, mode, x0, mode,
4048 cached_nonzero_bits (x0, mode, known_x,
4049 known_mode, known_ret));
4052 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
4055 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4056 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4057 is less useful. We can't allow both, because that results in exponential
4058 run time recursion. There is a nullstone testcase that triggered
4059 this. This macro avoids accidental uses of num_sign_bit_copies. */
4060 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4062 /* Given an expression, X, compute which bits in X can be nonzero.
4063 We don't care about bits outside of those defined in MODE.
4065 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4066 an arithmetic operation, we can do better. */
4068 static unsigned HOST_WIDE_INT
4069 nonzero_bits1 (const_rtx x, enum machine_mode mode, const_rtx known_x,
4070 enum machine_mode known_mode,
4071 unsigned HOST_WIDE_INT known_ret)
4073 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
4074 unsigned HOST_WIDE_INT inner_nz;
4076 enum machine_mode inner_mode;
4077 unsigned int mode_width = GET_MODE_PRECISION (mode);
4079 /* For floating-point and vector values, assume all bits are needed. */
4080 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)
4081 || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode))
4084 /* If X is wider than MODE, use its mode instead. */
4085 if (GET_MODE_PRECISION (GET_MODE (x)) > mode_width)
4087 mode = GET_MODE (x);
4088 nonzero = GET_MODE_MASK (mode);
4089 mode_width = GET_MODE_PRECISION (mode);
4092 if (mode_width > HOST_BITS_PER_WIDE_INT)
4093 /* Our only callers in this case look for single bit values. So
4094 just return the mode mask. Those tests will then be false. */
4097 #ifndef WORD_REGISTER_OPERATIONS
4098 /* If MODE is wider than X, but both are a single word for both the host
4099 and target machines, we can compute this from which bits of the
4100 object might be nonzero in its own mode, taking into account the fact
4101 that on many CISC machines, accessing an object in a wider mode
4102 causes the high-order bits to become undefined. So they are
4103 not known to be zero. */
4105 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
4106 && GET_MODE_PRECISION (GET_MODE (x)) <= BITS_PER_WORD
4107 && GET_MODE_PRECISION (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
4108 && GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (GET_MODE (x)))
4110 nonzero &= cached_nonzero_bits (x, GET_MODE (x),
4111 known_x, known_mode, known_ret);
4112 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
4117 code = GET_CODE (x);
4121 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
4122 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4123 all the bits above ptr_mode are known to be zero. */
4124 /* As we do not know which address space the pointer is referring to,
4125 we can do this only if the target does not support different pointer
4126 or address modes depending on the address space. */
4127 if (target_default_pointer_address_modes_p ()
4128 && POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
4130 nonzero &= GET_MODE_MASK (ptr_mode);
4133 /* Include declared information about alignment of pointers. */
4134 /* ??? We don't properly preserve REG_POINTER changes across
4135 pointer-to-integer casts, so we can't trust it except for
4136 things that we know must be pointers. See execute/960116-1.c. */
4137 if ((x == stack_pointer_rtx
4138 || x == frame_pointer_rtx
4139 || x == arg_pointer_rtx)
4140 && REGNO_POINTER_ALIGN (REGNO (x)))
4142 unsigned HOST_WIDE_INT alignment
4143 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
4145 #ifdef PUSH_ROUNDING
4146 /* If PUSH_ROUNDING is defined, it is possible for the
4147 stack to be momentarily aligned only to that amount,
4148 so we pick the least alignment. */
4149 if (x == stack_pointer_rtx && PUSH_ARGS)
4150 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
4154 nonzero &= ~(alignment - 1);
4158 unsigned HOST_WIDE_INT nonzero_for_hook = nonzero;
4159 rtx new_rtx = rtl_hooks.reg_nonzero_bits (x, mode, known_x,
4160 known_mode, known_ret,
4164 nonzero_for_hook &= cached_nonzero_bits (new_rtx, mode, known_x,
4165 known_mode, known_ret);
4167 return nonzero_for_hook;
4171 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
4172 /* If X is negative in MODE, sign-extend the value. */
4174 && mode_width < BITS_PER_WORD
4175 && (UINTVAL (x) & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
4177 return UINTVAL (x) | (HOST_WIDE_INT_M1U << mode_width);
4183 #ifdef LOAD_EXTEND_OP
4184 /* In many, if not most, RISC machines, reading a byte from memory
4185 zeros the rest of the register. Noticing that fact saves a lot
4186 of extra zero-extends. */
4187 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
4188 nonzero &= GET_MODE_MASK (GET_MODE (x));
4193 case UNEQ: case LTGT:
4194 case GT: case GTU: case UNGT:
4195 case LT: case LTU: case UNLT:
4196 case GE: case GEU: case UNGE:
4197 case LE: case LEU: case UNLE:
4198 case UNORDERED: case ORDERED:
4199 /* If this produces an integer result, we know which bits are set.
4200 Code here used to clear bits outside the mode of X, but that is
4202 /* Mind that MODE is the mode the caller wants to look at this
4203 operation in, and not the actual operation mode. We can wind
4204 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4205 that describes the results of a vector compare. */
4206 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
4207 && mode_width <= HOST_BITS_PER_WIDE_INT)
4208 nonzero = STORE_FLAG_VALUE;
4213 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4214 and num_sign_bit_copies. */
4215 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
4216 == GET_MODE_PRECISION (GET_MODE (x)))
4220 if (GET_MODE_PRECISION (GET_MODE (x)) < mode_width)
4221 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
4226 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4227 and num_sign_bit_copies. */
4228 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
4229 == GET_MODE_PRECISION (GET_MODE (x)))
4235 nonzero &= (cached_nonzero_bits (XEXP (x, 0), mode,
4236 known_x, known_mode, known_ret)
4237 & GET_MODE_MASK (mode));
4241 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode,
4242 known_x, known_mode, known_ret);
4243 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
4244 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
4248 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4249 Otherwise, show all the bits in the outer mode but not the inner
4251 inner_nz = cached_nonzero_bits (XEXP (x, 0), mode,
4252 known_x, known_mode, known_ret);
4253 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
4255 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
4256 if (val_signbit_known_set_p (GET_MODE (XEXP (x, 0)), inner_nz))
4257 inner_nz |= (GET_MODE_MASK (mode)
4258 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
4261 nonzero &= inner_nz;
4265 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode,
4266 known_x, known_mode, known_ret)
4267 & cached_nonzero_bits (XEXP (x, 1), mode,
4268 known_x, known_mode, known_ret);
4272 case UMIN: case UMAX: case SMIN: case SMAX:
4274 unsigned HOST_WIDE_INT nonzero0
4275 = cached_nonzero_bits (XEXP (x, 0), mode,
4276 known_x, known_mode, known_ret);
4278 /* Don't call nonzero_bits for the second time if it cannot change
4280 if ((nonzero & nonzero0) != nonzero)
4282 | cached_nonzero_bits (XEXP (x, 1), mode,
4283 known_x, known_mode, known_ret);
4287 case PLUS: case MINUS:
4289 case DIV: case UDIV:
4290 case MOD: case UMOD:
4291 /* We can apply the rules of arithmetic to compute the number of
4292 high- and low-order zero bits of these operations. We start by
4293 computing the width (position of the highest-order nonzero bit)
4294 and the number of low-order zero bits for each value. */
4296 unsigned HOST_WIDE_INT nz0
4297 = cached_nonzero_bits (XEXP (x, 0), mode,
4298 known_x, known_mode, known_ret);
4299 unsigned HOST_WIDE_INT nz1
4300 = cached_nonzero_bits (XEXP (x, 1), mode,
4301 known_x, known_mode, known_ret);
4302 int sign_index = GET_MODE_PRECISION (GET_MODE (x)) - 1;
4303 int width0 = floor_log2 (nz0) + 1;
4304 int width1 = floor_log2 (nz1) + 1;
4305 int low0 = floor_log2 (nz0 & -nz0);
4306 int low1 = floor_log2 (nz1 & -nz1);
4307 unsigned HOST_WIDE_INT op0_maybe_minusp
4308 = nz0 & ((unsigned HOST_WIDE_INT) 1 << sign_index);
4309 unsigned HOST_WIDE_INT op1_maybe_minusp
4310 = nz1 & ((unsigned HOST_WIDE_INT) 1 << sign_index);
4311 unsigned int result_width = mode_width;
4317 result_width = MAX (width0, width1) + 1;
4318 result_low = MIN (low0, low1);
4321 result_low = MIN (low0, low1);
4324 result_width = width0 + width1;
4325 result_low = low0 + low1;
4330 if (!op0_maybe_minusp && !op1_maybe_minusp)
4331 result_width = width0;
4336 result_width = width0;
4341 if (!op0_maybe_minusp && !op1_maybe_minusp)
4342 result_width = MIN (width0, width1);
4343 result_low = MIN (low0, low1);
4348 result_width = MIN (width0, width1);
4349 result_low = MIN (low0, low1);
4355 if (result_width < mode_width)
4356 nonzero &= ((unsigned HOST_WIDE_INT) 1 << result_width) - 1;
4359 nonzero &= ~(((unsigned HOST_WIDE_INT) 1 << result_low) - 1);
4364 if (CONST_INT_P (XEXP (x, 1))
4365 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
4366 nonzero &= ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
4370 /* If this is a SUBREG formed for a promoted variable that has
4371 been zero-extended, we know that at least the high-order bits
4372 are zero, though others might be too. */
4374 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
4375 nonzero = GET_MODE_MASK (GET_MODE (x))
4376 & cached_nonzero_bits (SUBREG_REG (x), GET_MODE (x),
4377 known_x, known_mode, known_ret);
4379 inner_mode = GET_MODE (SUBREG_REG (x));
4380 /* If the inner mode is a single word for both the host and target
4381 machines, we can compute this from which bits of the inner
4382 object might be nonzero. */
4383 if (GET_MODE_PRECISION (inner_mode) <= BITS_PER_WORD
4384 && (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT))
4386 nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
4387 known_x, known_mode, known_ret);
4389 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
4390 /* If this is a typical RISC machine, we only have to worry
4391 about the way loads are extended. */
4392 if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
4393 ? val_signbit_known_set_p (inner_mode, nonzero)
4394 : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
4395 || !MEM_P (SUBREG_REG (x)))
4398 /* On many CISC machines, accessing an object in a wider mode
4399 causes the high-order bits to become undefined. So they are
4400 not known to be zero. */
4401 if (GET_MODE_PRECISION (GET_MODE (x))
4402 > GET_MODE_PRECISION (inner_mode))
4403 nonzero |= (GET_MODE_MASK (GET_MODE (x))
4404 & ~GET_MODE_MASK (inner_mode));
4413 /* The nonzero bits are in two classes: any bits within MODE
4414 that aren't in GET_MODE (x) are always significant. The rest of the
4415 nonzero bits are those that are significant in the operand of
4416 the shift when shifted the appropriate number of bits. This
4417 shows that high-order bits are cleared by the right shift and
4418 low-order bits by left shifts. */
4419 if (CONST_INT_P (XEXP (x, 1))
4420 && INTVAL (XEXP (x, 1)) >= 0
4421 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
4422 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (GET_MODE (x)))
4424 enum machine_mode inner_mode = GET_MODE (x);
4425 unsigned int width = GET_MODE_PRECISION (inner_mode);
4426 int count = INTVAL (XEXP (x, 1));
4427 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
4428 unsigned HOST_WIDE_INT op_nonzero
4429 = cached_nonzero_bits (XEXP (x, 0), mode,
4430 known_x, known_mode, known_ret);
4431 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
4432 unsigned HOST_WIDE_INT outer = 0;
4434 if (mode_width > width)
4435 outer = (op_nonzero & nonzero & ~mode_mask);
4437 if (code == LSHIFTRT)
4439 else if (code == ASHIFTRT)
4443 /* If the sign bit may have been nonzero before the shift, we
4444 need to mark all the places it could have been copied to
4445 by the shift as possibly nonzero. */
4446 if (inner & ((unsigned HOST_WIDE_INT) 1 << (width - 1 - count)))
4447 inner |= (((unsigned HOST_WIDE_INT) 1 << count) - 1)
4450 else if (code == ASHIFT)
4453 inner = ((inner << (count % width)
4454 | (inner >> (width - (count % width)))) & mode_mask);
4456 nonzero &= (outer | inner);
4462 /* This is at most the number of bits in the mode. */
4463 nonzero = ((unsigned HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
4467 /* If CLZ has a known value at zero, then the nonzero bits are
4468 that value, plus the number of bits in the mode minus one. */
4469 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
4471 |= ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
4477 /* If CTZ has a known value at zero, then the nonzero bits are
4478 that value, plus the number of bits in the mode minus one. */
4479 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
4481 |= ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
4487 /* This is at most the number of bits in the mode minus 1. */
4488 nonzero = ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
4497 unsigned HOST_WIDE_INT nonzero_true
4498 = cached_nonzero_bits (XEXP (x, 1), mode,
4499 known_x, known_mode, known_ret);
4501 /* Don't call nonzero_bits for the second time if it cannot change
4503 if ((nonzero & nonzero_true) != nonzero)
4504 nonzero &= nonzero_true
4505 | cached_nonzero_bits (XEXP (x, 2), mode,
4506 known_x, known_mode, known_ret);
4517 /* See the macro definition above. */
4518 #undef cached_num_sign_bit_copies
4521 /* The function cached_num_sign_bit_copies is a wrapper around
4522 num_sign_bit_copies1. It avoids exponential behavior in
4523 num_sign_bit_copies1 when X has identical subexpressions on the
4524 first or the second level. */
4527 cached_num_sign_bit_copies (const_rtx x, enum machine_mode mode, const_rtx known_x,
4528 enum machine_mode known_mode,
4529 unsigned int known_ret)
4531 if (x == known_x && mode == known_mode)
4534 /* Try to find identical subexpressions. If found call
4535 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4536 the precomputed value for the subexpression as KNOWN_RET. */
4538 if (ARITHMETIC_P (x))
4540 rtx x0 = XEXP (x, 0);
4541 rtx x1 = XEXP (x, 1);
4543 /* Check the first level. */
4546 num_sign_bit_copies1 (x, mode, x0, mode,
4547 cached_num_sign_bit_copies (x0, mode, known_x,
4551 /* Check the second level. */
4552 if (ARITHMETIC_P (x0)
4553 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
4555 num_sign_bit_copies1 (x, mode, x1, mode,
4556 cached_num_sign_bit_copies (x1, mode, known_x,
4560 if (ARITHMETIC_P (x1)
4561 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
4563 num_sign_bit_copies1 (x, mode, x0, mode,
4564 cached_num_sign_bit_copies (x0, mode, known_x,
4569 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
4572 /* Return the number of bits at the high-order end of X that are known to
4573 be equal to the sign bit. X will be used in mode MODE; if MODE is
4574 VOIDmode, X will be used in its own mode. The returned value will always
4575 be between 1 and the number of bits in MODE. */
4578 num_sign_bit_copies1 (const_rtx x, enum machine_mode mode, const_rtx known_x,
4579 enum machine_mode known_mode,
4580 unsigned int known_ret)
4582 enum rtx_code code = GET_CODE (x);
4583 unsigned int bitwidth = GET_MODE_PRECISION (mode);
4584 int num0, num1, result;
4585 unsigned HOST_WIDE_INT nonzero;
4587 /* If we weren't given a mode, use the mode of X. If the mode is still
4588 VOIDmode, we don't know anything. Likewise if one of the modes is
4591 if (mode == VOIDmode)
4592 mode = GET_MODE (x);
4594 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))
4595 || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode))
4598 /* For a smaller object, just ignore the high bits. */
4599 if (bitwidth < GET_MODE_PRECISION (GET_MODE (x)))
4601 num0 = cached_num_sign_bit_copies (x, GET_MODE (x),
4602 known_x, known_mode, known_ret);
4604 num0 - (int) (GET_MODE_PRECISION (GET_MODE (x)) - bitwidth));
4607 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_PRECISION (GET_MODE (x)))
4609 #ifndef WORD_REGISTER_OPERATIONS
4610 /* If this machine does not do all register operations on the entire
4611 register and MODE is wider than the mode of X, we can say nothing
4612 at all about the high-order bits. */
4615 /* Likewise on machines that do, if the mode of the object is smaller
4616 than a word and loads of that size don't sign extend, we can say
4617 nothing about the high order bits. */
4618 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
4619 #ifdef LOAD_EXTEND_OP
4620 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
4631 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
4632 /* If pointers extend signed and this is a pointer in Pmode, say that
4633 all the bits above ptr_mode are known to be sign bit copies. */
4634 /* As we do not know which address space the pointer is referring to,
4635 we can do this only if the target does not support different pointer
4636 or address modes depending on the address space. */
4637 if (target_default_pointer_address_modes_p ()
4638 && ! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
4639 && mode == Pmode && REG_POINTER (x))
4640 return GET_MODE_PRECISION (Pmode) - GET_MODE_PRECISION (ptr_mode) + 1;
4644 unsigned int copies_for_hook = 1, copies = 1;
4645 rtx new_rtx = rtl_hooks.reg_num_sign_bit_copies (x, mode, known_x,
4646 known_mode, known_ret,
4650 copies = cached_num_sign_bit_copies (new_rtx, mode, known_x,
4651 known_mode, known_ret);
4653 if (copies > 1 || copies_for_hook > 1)
4654 return MAX (copies, copies_for_hook);
4656 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4661 #ifdef LOAD_EXTEND_OP
4662 /* Some RISC machines sign-extend all loads of smaller than a word. */
4663 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
4664 return MAX (1, ((int) bitwidth
4665 - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1));
4670 /* If the constant is negative, take its 1's complement and remask.
4671 Then see how many zero bits we have. */
4672 nonzero = UINTVAL (x) & GET_MODE_MASK (mode);
4673 if (bitwidth <= HOST_BITS_PER_WIDE_INT
4674 && (nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4675 nonzero = (~nonzero) & GET_MODE_MASK (mode);
4677 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
4680 /* If this is a SUBREG for a promoted object that is sign-extended
4681 and we are looking at it in a wider mode, we know that at least the
4682 high-order bits are known to be sign bit copies. */
4684 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_SIGNED_P (x))
4686 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), mode,
4687 known_x, known_mode, known_ret);
4688 return MAX ((int) bitwidth
4689 - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1,
4693 /* For a smaller object, just ignore the high bits. */
4694 if (bitwidth <= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x))))
4696 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), VOIDmode,
4697 known_x, known_mode, known_ret);
4698 return MAX (1, (num0
4699 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x)))
4703 #ifdef WORD_REGISTER_OPERATIONS
4704 #ifdef LOAD_EXTEND_OP
4705 /* For paradoxical SUBREGs on machines where all register operations
4706 affect the entire register, just look inside. Note that we are
4707 passing MODE to the recursive call, so the number of sign bit copies
4708 will remain relative to that mode, not the inner mode. */
4710 /* This works only if loads sign extend. Otherwise, if we get a
4711 reload for the inner part, it may be loaded from the stack, and
4712 then we lose all sign bit copies that existed before the store
4715 if (paradoxical_subreg_p (x)
4716 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
4717 && MEM_P (SUBREG_REG (x)))
4718 return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
4719 known_x, known_mode, known_ret);
4725 if (CONST_INT_P (XEXP (x, 1)))
4726 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
4730 return (bitwidth - GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
4731 + cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode,
4732 known_x, known_mode, known_ret));
4735 /* For a smaller object, just ignore the high bits. */
4736 num0 = cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode,
4737 known_x, known_mode, known_ret);
4738 return MAX (1, (num0 - (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
4742 return cached_num_sign_bit_copies (XEXP (x, 0), mode,
4743 known_x, known_mode, known_ret);
4745 case ROTATE: case ROTATERT:
4746 /* If we are rotating left by a number of bits less than the number
4747 of sign bit copies, we can just subtract that amount from the
4749 if (CONST_INT_P (XEXP (x, 1))
4750 && INTVAL (XEXP (x, 1)) >= 0
4751 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
4753 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4754 known_x, known_mode, known_ret);
4755 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
4756 : (int) bitwidth - INTVAL (XEXP (x, 1))));
4761 /* In general, this subtracts one sign bit copy. But if the value
4762 is known to be positive, the number of sign bit copies is the
4763 same as that of the input. Finally, if the input has just one bit
4764 that might be nonzero, all the bits are copies of the sign bit. */
4765 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4766 known_x, known_mode, known_ret);
4767 if (bitwidth > HOST_BITS_PER_WIDE_INT)
4768 return num0 > 1 ? num0 - 1 : 1;
4770 nonzero = nonzero_bits (XEXP (x, 0), mode);
4775 && (((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
4780 case IOR: case AND: case XOR:
4781 case SMIN: case SMAX: case UMIN: case UMAX:
4782 /* Logical operations will preserve the number of sign-bit copies.
4783 MIN and MAX operations always return one of the operands. */
4784 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4785 known_x, known_mode, known_ret);
4786 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4787 known_x, known_mode, known_ret);
4789 /* If num1 is clearing some of the top bits then regardless of
4790 the other term, we are guaranteed to have at least that many
4791 high-order zero bits. */
4794 && bitwidth <= HOST_BITS_PER_WIDE_INT
4795 && CONST_INT_P (XEXP (x, 1))
4796 && (UINTVAL (XEXP (x, 1))
4797 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) == 0)
4800 /* Similarly for IOR when setting high-order bits. */
4803 && bitwidth <= HOST_BITS_PER_WIDE_INT
4804 && CONST_INT_P (XEXP (x, 1))
4805 && (UINTVAL (XEXP (x, 1))
4806 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4809 return MIN (num0, num1);
4811 case PLUS: case MINUS:
4812 /* For addition and subtraction, we can have a 1-bit carry. However,
4813 if we are subtracting 1 from a positive number, there will not
4814 be such a carry. Furthermore, if the positive number is known to
4815 be 0 or 1, we know the result is either -1 or 0. */
4817 if (code == PLUS && XEXP (x, 1) == constm1_rtx
4818 && bitwidth <= HOST_BITS_PER_WIDE_INT)
4820 nonzero = nonzero_bits (XEXP (x, 0), mode);
4821 if ((((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
4822 return (nonzero == 1 || nonzero == 0 ? bitwidth
4823 : bitwidth - floor_log2 (nonzero) - 1);
4826 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4827 known_x, known_mode, known_ret);
4828 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4829 known_x, known_mode, known_ret);
4830 result = MAX (1, MIN (num0, num1) - 1);
4835 /* The number of bits of the product is the sum of the number of
4836 bits of both terms. However, unless one of the terms if known
4837 to be positive, we must allow for an additional bit since negating
4838 a negative number can remove one sign bit copy. */
4840 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4841 known_x, known_mode, known_ret);
4842 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4843 known_x, known_mode, known_ret);
4845 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
4847 && (bitwidth > HOST_BITS_PER_WIDE_INT
4848 || (((nonzero_bits (XEXP (x, 0), mode)
4849 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4850 && ((nonzero_bits (XEXP (x, 1), mode)
4851 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)))
4855 return MAX (1, result);
4858 /* The result must be <= the first operand. If the first operand
4859 has the high bit set, we know nothing about the number of sign
4861 if (bitwidth > HOST_BITS_PER_WIDE_INT)
4863 else if ((nonzero_bits (XEXP (x, 0), mode)
4864 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4867 return cached_num_sign_bit_copies (XEXP (x, 0), mode,
4868 known_x, known_mode, known_ret);
4871 /* The result must be <= the second operand. If the second operand
4872 has (or just might have) the high bit set, we know nothing about
4873 the number of sign bit copies. */
4874 if (bitwidth > HOST_BITS_PER_WIDE_INT)
4876 else if ((nonzero_bits (XEXP (x, 1), mode)
4877 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4880 return cached_num_sign_bit_copies (XEXP (x, 1), mode,
4881 known_x, known_mode, known_ret);
4884 /* Similar to unsigned division, except that we have to worry about
4885 the case where the divisor is negative, in which case we have
4887 result = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4888 known_x, known_mode, known_ret);
4890 && (bitwidth > HOST_BITS_PER_WIDE_INT
4891 || (nonzero_bits (XEXP (x, 1), mode)
4892 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
4898 result = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4899 known_x, known_mode, known_ret);
4901 && (bitwidth > HOST_BITS_PER_WIDE_INT
4902 || (nonzero_bits (XEXP (x, 1), mode)
4903 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
4909 /* Shifts by a constant add to the number of bits equal to the
4911 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4912 known_x, known_mode, known_ret);
4913 if (CONST_INT_P (XEXP (x, 1))
4914 && INTVAL (XEXP (x, 1)) > 0
4915 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (GET_MODE (x)))
4916 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
4921 /* Left shifts destroy copies. */
4922 if (!CONST_INT_P (XEXP (x, 1))
4923 || INTVAL (XEXP (x, 1)) < 0
4924 || INTVAL (XEXP (x, 1)) >= (int) bitwidth
4925 || INTVAL (XEXP (x, 1)) >= GET_MODE_PRECISION (GET_MODE (x)))
4928 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4929 known_x, known_mode, known_ret);
4930 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
4933 num0 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4934 known_x, known_mode, known_ret);
4935 num1 = cached_num_sign_bit_copies (XEXP (x, 2), mode,
4936 known_x, known_mode, known_ret);
4937 return MIN (num0, num1);
4939 case EQ: case NE: case GE: case GT: case LE: case LT:
4940 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
4941 case GEU: case GTU: case LEU: case LTU:
4942 case UNORDERED: case ORDERED:
4943 /* If the constant is negative, take its 1's complement and remask.
4944 Then see how many zero bits we have. */
4945 nonzero = STORE_FLAG_VALUE;
4946 if (bitwidth <= HOST_BITS_PER_WIDE_INT
4947 && (nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4948 nonzero = (~nonzero) & GET_MODE_MASK (mode);
4950 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
4956 /* If we haven't been able to figure it out by one of the above rules,
4957 see if some of the high-order bits are known to be zero. If so,
4958 count those bits and return one less than that amount. If we can't
4959 safely compute the mask for this mode, always return BITWIDTH. */
4961 bitwidth = GET_MODE_PRECISION (mode);
4962 if (bitwidth > HOST_BITS_PER_WIDE_INT)
4965 nonzero = nonzero_bits (x, mode);
4966 return nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))
4967 ? 1 : bitwidth - floor_log2 (nonzero) - 1;
4970 /* Calculate the rtx_cost of a single instruction. A return value of
4971 zero indicates an instruction pattern without a known cost. */
4974 insn_rtx_cost (rtx pat, bool speed)
4979 /* Extract the single set rtx from the instruction pattern.
4980 We can't use single_set since we only have the pattern. */
4981 if (GET_CODE (pat) == SET)
4983 else if (GET_CODE (pat) == PARALLEL)
4986 for (i = 0; i < XVECLEN (pat, 0); i++)
4988 rtx x = XVECEXP (pat, 0, i);
4989 if (GET_CODE (x) == SET)
5002 cost = set_src_cost (SET_SRC (set), speed);
5003 return cost > 0 ? cost : COSTS_N_INSNS (1);
5006 /* Given an insn INSN and condition COND, return the condition in a
5007 canonical form to simplify testing by callers. Specifically:
5009 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5010 (2) Both operands will be machine operands; (cc0) will have been replaced.
5011 (3) If an operand is a constant, it will be the second operand.
5012 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5013 for GE, GEU, and LEU.
5015 If the condition cannot be understood, or is an inequality floating-point
5016 comparison which needs to be reversed, 0 will be returned.
5018 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5020 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5021 insn used in locating the condition was found. If a replacement test
5022 of the condition is desired, it should be placed in front of that
5023 insn and we will be sure that the inputs are still valid.
5025 If WANT_REG is nonzero, we wish the condition to be relative to that
5026 register, if possible. Therefore, do not canonicalize the condition
5027 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5028 to be a compare to a CC mode register.
5030 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5034 canonicalize_condition (rtx_insn *insn, rtx cond, int reverse,
5035 rtx_insn **earliest,
5036 rtx want_reg, int allow_cc_mode, int valid_at_insn_p)
5039 rtx_insn *prev = insn;
5043 int reverse_code = 0;
5044 enum machine_mode mode;
5045 basic_block bb = BLOCK_FOR_INSN (insn);
5047 code = GET_CODE (cond);
5048 mode = GET_MODE (cond);
5049 op0 = XEXP (cond, 0);
5050 op1 = XEXP (cond, 1);
5053 code = reversed_comparison_code (cond, insn);
5054 if (code == UNKNOWN)
5060 /* If we are comparing a register with zero, see if the register is set
5061 in the previous insn to a COMPARE or a comparison operation. Perform
5062 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5065 while ((GET_RTX_CLASS (code) == RTX_COMPARE
5066 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
5067 && op1 == CONST0_RTX (GET_MODE (op0))
5070 /* Set nonzero when we find something of interest. */
5074 /* If comparison with cc0, import actual comparison from compare
5078 if ((prev = prev_nonnote_insn (prev)) == 0
5079 || !NONJUMP_INSN_P (prev)
5080 || (set = single_set (prev)) == 0
5081 || SET_DEST (set) != cc0_rtx)
5084 op0 = SET_SRC (set);
5085 op1 = CONST0_RTX (GET_MODE (op0));
5091 /* If this is a COMPARE, pick up the two things being compared. */
5092 if (GET_CODE (op0) == COMPARE)
5094 op1 = XEXP (op0, 1);
5095 op0 = XEXP (op0, 0);
5098 else if (!REG_P (op0))
5101 /* Go back to the previous insn. Stop if it is not an INSN. We also
5102 stop if it isn't a single set or if it has a REG_INC note because
5103 we don't want to bother dealing with it. */
5105 prev = prev_nonnote_nondebug_insn (prev);
5108 || !NONJUMP_INSN_P (prev)
5109 || FIND_REG_INC_NOTE (prev, NULL_RTX)
5110 /* In cfglayout mode, there do not have to be labels at the
5111 beginning of a block, or jumps at the end, so the previous
5112 conditions would not stop us when we reach bb boundary. */
5113 || BLOCK_FOR_INSN (prev) != bb)
5116 set = set_of (op0, prev);
5119 && (GET_CODE (set) != SET
5120 || !rtx_equal_p (SET_DEST (set), op0)))
5123 /* If this is setting OP0, get what it sets it to if it looks
5127 enum machine_mode inner_mode = GET_MODE (SET_DEST (set));
5128 #ifdef FLOAT_STORE_FLAG_VALUE
5129 REAL_VALUE_TYPE fsfv;
5132 /* ??? We may not combine comparisons done in a CCmode with
5133 comparisons not done in a CCmode. This is to aid targets
5134 like Alpha that have an IEEE compliant EQ instruction, and
5135 a non-IEEE compliant BEQ instruction. The use of CCmode is
5136 actually artificial, simply to prevent the combination, but
5137 should not affect other platforms.
5139 However, we must allow VOIDmode comparisons to match either
5140 CCmode or non-CCmode comparison, because some ports have
5141 modeless comparisons inside branch patterns.
5143 ??? This mode check should perhaps look more like the mode check
5144 in simplify_comparison in combine. */
5145 if (((GET_MODE_CLASS (mode) == MODE_CC)
5146 != (GET_MODE_CLASS (inner_mode) == MODE_CC))
5148 && inner_mode != VOIDmode)
5150 if (GET_CODE (SET_SRC (set)) == COMPARE
5153 && val_signbit_known_set_p (inner_mode,
5155 #ifdef FLOAT_STORE_FLAG_VALUE
5157 && SCALAR_FLOAT_MODE_P (inner_mode)
5158 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode),
5159 REAL_VALUE_NEGATIVE (fsfv)))
5162 && COMPARISON_P (SET_SRC (set))))
5164 else if (((code == EQ
5166 && val_signbit_known_set_p (inner_mode,
5168 #ifdef FLOAT_STORE_FLAG_VALUE
5170 && SCALAR_FLOAT_MODE_P (inner_mode)
5171 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode),
5172 REAL_VALUE_NEGATIVE (fsfv)))
5175 && COMPARISON_P (SET_SRC (set)))
5180 else if ((code == EQ || code == NE)
5181 && GET_CODE (SET_SRC (set)) == XOR)
5182 /* Handle sequences like:
5185 ...(eq|ne op0 (const_int 0))...
5189 (eq op0 (const_int 0)) reduces to (eq X Y)
5190 (ne op0 (const_int 0)) reduces to (ne X Y)
5192 This is the form used by MIPS16, for example. */
5198 else if (reg_set_p (op0, prev))
5199 /* If this sets OP0, but not directly, we have to give up. */
5204 /* If the caller is expecting the condition to be valid at INSN,
5205 make sure X doesn't change before INSN. */
5206 if (valid_at_insn_p)
5207 if (modified_in_p (x, prev) || modified_between_p (x, prev, insn))
5209 if (COMPARISON_P (x))
5210 code = GET_CODE (x);
5213 code = reversed_comparison_code (x, prev);
5214 if (code == UNKNOWN)
5219 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5225 /* If constant is first, put it last. */
5226 if (CONSTANT_P (op0))
5227 code = swap_condition (code), tem = op0, op0 = op1, op1 = tem;
5229 /* If OP0 is the result of a comparison, we weren't able to find what
5230 was really being compared, so fail. */
5232 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5235 /* Canonicalize any ordered comparison with integers involving equality
5236 if we can do computations in the relevant mode and we do not
5239 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_CC
5240 && CONST_INT_P (op1)
5241 && GET_MODE (op0) != VOIDmode
5242 && GET_MODE_PRECISION (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT)
5244 HOST_WIDE_INT const_val = INTVAL (op1);
5245 unsigned HOST_WIDE_INT uconst_val = const_val;
5246 unsigned HOST_WIDE_INT max_val
5247 = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0));
5252 if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1)
5253 code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0));
5256 /* When cross-compiling, const_val might be sign-extended from
5257 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5259 if ((const_val & max_val)
5260 != ((unsigned HOST_WIDE_INT) 1
5261 << (GET_MODE_PRECISION (GET_MODE (op0)) - 1)))
5262 code = GT, op1 = gen_int_mode (const_val - 1, GET_MODE (op0));
5266 if (uconst_val < max_val)
5267 code = LTU, op1 = gen_int_mode (uconst_val + 1, GET_MODE (op0));
5271 if (uconst_val != 0)
5272 code = GTU, op1 = gen_int_mode (uconst_val - 1, GET_MODE (op0));
5280 /* Never return CC0; return zero instead. */
5284 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
5287 /* Given a jump insn JUMP, return the condition that will cause it to branch
5288 to its JUMP_LABEL. If the condition cannot be understood, or is an
5289 inequality floating-point comparison which needs to be reversed, 0 will
5292 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5293 insn used in locating the condition was found. If a replacement test
5294 of the condition is desired, it should be placed in front of that
5295 insn and we will be sure that the inputs are still valid. If EARLIEST
5296 is null, the returned condition will be valid at INSN.
5298 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5299 compare CC mode register.
5301 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5304 get_condition (rtx_insn *jump, rtx_insn **earliest, int allow_cc_mode,
5305 int valid_at_insn_p)
5311 /* If this is not a standard conditional jump, we can't parse it. */
5313 || ! any_condjump_p (jump))
5315 set = pc_set (jump);
5317 cond = XEXP (SET_SRC (set), 0);
5319 /* If this branches to JUMP_LABEL when the condition is false, reverse
5322 = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
5323 && XEXP (XEXP (SET_SRC (set), 2), 0) == JUMP_LABEL (jump);
5325 return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX,
5326 allow_cc_mode, valid_at_insn_p);
5329 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5330 TARGET_MODE_REP_EXTENDED.
5332 Note that we assume that the property of
5333 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5334 narrower than mode B. I.e., if A is a mode narrower than B then in
5335 order to be able to operate on it in mode B, mode A needs to
5336 satisfy the requirements set by the representation of mode B. */
5339 init_num_sign_bit_copies_in_rep (void)
5341 enum machine_mode mode, in_mode;
5343 for (in_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); in_mode != VOIDmode;
5344 in_mode = GET_MODE_WIDER_MODE (mode))
5345 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != in_mode;
5346 mode = GET_MODE_WIDER_MODE (mode))
5348 enum machine_mode i;
5350 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5351 extends to the next widest mode. */
5352 gcc_assert (targetm.mode_rep_extended (mode, in_mode) == UNKNOWN
5353 || GET_MODE_WIDER_MODE (mode) == in_mode);
5355 /* We are in in_mode. Count how many bits outside of mode
5356 have to be copies of the sign-bit. */
5357 for (i = mode; i != in_mode; i = GET_MODE_WIDER_MODE (i))
5359 enum machine_mode wider = GET_MODE_WIDER_MODE (i);
5361 if (targetm.mode_rep_extended (i, wider) == SIGN_EXTEND
5362 /* We can only check sign-bit copies starting from the
5363 top-bit. In order to be able to check the bits we
5364 have already seen we pretend that subsequent bits
5365 have to be sign-bit copies too. */
5366 || num_sign_bit_copies_in_rep [in_mode][mode])
5367 num_sign_bit_copies_in_rep [in_mode][mode]
5368 += GET_MODE_PRECISION (wider) - GET_MODE_PRECISION (i);
5373 /* Suppose that truncation from the machine mode of X to MODE is not a
5374 no-op. See if there is anything special about X so that we can
5375 assume it already contains a truncated value of MODE. */
5378 truncated_to_mode (enum machine_mode mode, const_rtx x)
5380 /* This register has already been used in MODE without explicit
5382 if (REG_P (x) && rtl_hooks.reg_truncated_to_mode (mode, x))
5385 /* See if we already satisfy the requirements of MODE. If yes we
5386 can just switch to MODE. */
5387 if (num_sign_bit_copies_in_rep[GET_MODE (x)][mode]
5388 && (num_sign_bit_copies (x, GET_MODE (x))
5389 >= num_sign_bit_copies_in_rep[GET_MODE (x)][mode] + 1))
5395 /* Return true if RTX code CODE has a single sequence of zero or more
5396 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5397 entry in that case. */
5400 setup_reg_subrtx_bounds (unsigned int code)
5402 const char *format = GET_RTX_FORMAT ((enum rtx_code) code);
5404 for (; format[i] != 'e'; ++i)
5407 /* No subrtxes. Leave start and count as 0. */
5409 if (format[i] == 'E' || format[i] == 'V')
5413 /* Record the sequence of 'e's. */
5414 rtx_all_subrtx_bounds[code].start = i;
5417 while (format[i] == 'e');
5418 rtx_all_subrtx_bounds[code].count = i - rtx_all_subrtx_bounds[code].start;
5419 /* rtl-iter.h relies on this. */
5420 gcc_checking_assert (rtx_all_subrtx_bounds[code].count <= 3);
5422 for (; format[i]; ++i)
5423 if (format[i] == 'E' || format[i] == 'V' || format[i] == 'e')
5429 /* Initialize non_rtx_starting_operands, which is used to speed up
5430 for_each_rtx, and rtx_all_subrtx_bounds. */
5435 for (i = 0; i < NUM_RTX_CODE; i++)
5437 const char *format = GET_RTX_FORMAT (i);
5438 const char *first = strpbrk (format, "eEV");
5439 non_rtx_starting_operands[i] = first ? first - format : -1;
5440 if (!setup_reg_subrtx_bounds (i))
5441 rtx_all_subrtx_bounds[i].count = UCHAR_MAX;
5442 if (GET_RTX_CLASS (i) != RTX_CONST_OBJ)
5443 rtx_nonconst_subrtx_bounds[i] = rtx_all_subrtx_bounds[i];
5446 init_num_sign_bit_copies_in_rep ();
5449 /* Check whether this is a constant pool constant. */
5451 constant_pool_constant_p (rtx x)
5453 x = avoid_constant_pool_reference (x);
5454 return CONST_DOUBLE_P (x);
5457 /* If M is a bitmask that selects a field of low-order bits within an item but
5458 not the entire word, return the length of the field. Return -1 otherwise.
5459 M is used in machine mode MODE. */
5462 low_bitmask_len (enum machine_mode mode, unsigned HOST_WIDE_INT m)
5464 if (mode != VOIDmode)
5466 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
5468 m &= GET_MODE_MASK (mode);
5471 return exact_log2 (m + 1);
5474 /* Return the mode of MEM's address. */
5477 get_address_mode (rtx mem)
5479 enum machine_mode mode;
5481 gcc_assert (MEM_P (mem));
5482 mode = GET_MODE (XEXP (mem, 0));
5483 if (mode != VOIDmode)
5485 return targetm.addr_space.address_mode (MEM_ADDR_SPACE (mem));
5488 /* Split up a CONST_DOUBLE or integer constant rtx
5489 into two rtx's for single words,
5490 storing in *FIRST the word that comes first in memory in the target
5491 and in *SECOND the other.
5493 TODO: This function needs to be rewritten to work on any size
5497 split_double (rtx value, rtx *first, rtx *second)
5499 if (CONST_INT_P (value))
5501 if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD))
5503 /* In this case the CONST_INT holds both target words.
5504 Extract the bits from it into two word-sized pieces.
5505 Sign extend each half to HOST_WIDE_INT. */
5506 unsigned HOST_WIDE_INT low, high;
5507 unsigned HOST_WIDE_INT mask, sign_bit, sign_extend;
5508 unsigned bits_per_word = BITS_PER_WORD;
5510 /* Set sign_bit to the most significant bit of a word. */
5512 sign_bit <<= bits_per_word - 1;
5514 /* Set mask so that all bits of the word are set. We could
5515 have used 1 << BITS_PER_WORD instead of basing the
5516 calculation on sign_bit. However, on machines where
5517 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5518 compiler warning, even though the code would never be
5520 mask = sign_bit << 1;
5523 /* Set sign_extend as any remaining bits. */
5524 sign_extend = ~mask;
5526 /* Pick the lower word and sign-extend it. */
5527 low = INTVAL (value);
5532 /* Pick the higher word, shifted to the least significant
5533 bits, and sign-extend it. */
5534 high = INTVAL (value);
5535 high >>= bits_per_word - 1;
5538 if (high & sign_bit)
5539 high |= sign_extend;
5541 /* Store the words in the target machine order. */
5542 if (WORDS_BIG_ENDIAN)
5544 *first = GEN_INT (high);
5545 *second = GEN_INT (low);
5549 *first = GEN_INT (low);
5550 *second = GEN_INT (high);
5555 /* The rule for using CONST_INT for a wider mode
5556 is that we regard the value as signed.
5557 So sign-extend it. */
5558 rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx);
5559 if (WORDS_BIG_ENDIAN)
5571 else if (GET_CODE (value) == CONST_WIDE_INT)
5573 /* All of this is scary code and needs to be converted to
5574 properly work with any size integer. */
5575 gcc_assert (CONST_WIDE_INT_NUNITS (value) == 2);
5576 if (WORDS_BIG_ENDIAN)
5578 *first = GEN_INT (CONST_WIDE_INT_ELT (value, 1));
5579 *second = GEN_INT (CONST_WIDE_INT_ELT (value, 0));
5583 *first = GEN_INT (CONST_WIDE_INT_ELT (value, 0));
5584 *second = GEN_INT (CONST_WIDE_INT_ELT (value, 1));
5587 else if (!CONST_DOUBLE_P (value))
5589 if (WORDS_BIG_ENDIAN)
5591 *first = const0_rtx;
5597 *second = const0_rtx;
5600 else if (GET_MODE (value) == VOIDmode
5601 /* This is the old way we did CONST_DOUBLE integers. */
5602 || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT)
5604 /* In an integer, the words are defined as most and least significant.
5605 So order them by the target's convention. */
5606 if (WORDS_BIG_ENDIAN)
5608 *first = GEN_INT (CONST_DOUBLE_HIGH (value));
5609 *second = GEN_INT (CONST_DOUBLE_LOW (value));
5613 *first = GEN_INT (CONST_DOUBLE_LOW (value));
5614 *second = GEN_INT (CONST_DOUBLE_HIGH (value));
5621 REAL_VALUE_FROM_CONST_DOUBLE (r, value);
5623 /* Note, this converts the REAL_VALUE_TYPE to the target's
5624 format, splits up the floating point double and outputs
5625 exactly 32 bits of it into each of l[0] and l[1] --
5626 not necessarily BITS_PER_WORD bits. */
5627 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
5629 /* If 32 bits is an entire word for the target, but not for the host,
5630 then sign-extend on the host so that the number will look the same
5631 way on the host that it would on the target. See for instance
5632 simplify_unary_operation. The #if is needed to avoid compiler
5635 #if HOST_BITS_PER_LONG > 32
5636 if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32)
5638 if (l[0] & ((long) 1 << 31))
5639 l[0] |= ((long) (-1) << 32);
5640 if (l[1] & ((long) 1 << 31))
5641 l[1] |= ((long) (-1) << 32);
5645 *first = GEN_INT (l[0]);
5646 *second = GEN_INT (l[1]);
5650 /* Return true if X is a sign_extract or zero_extract from the least
5654 lsb_bitfield_op_p (rtx x)
5656 if (GET_RTX_CLASS (GET_CODE (x)) == RTX_BITFIELD_OPS)
5658 enum machine_mode mode = GET_MODE (XEXP (x, 0));
5659 HOST_WIDE_INT len = INTVAL (XEXP (x, 1));
5660 HOST_WIDE_INT pos = INTVAL (XEXP (x, 2));
5662 return (pos == (BITS_BIG_ENDIAN ? GET_MODE_PRECISION (mode) - len : 0));
5667 /* Strip outer address "mutations" from LOC and return a pointer to the
5668 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5669 stripped expression there.
5671 "Mutations" either convert between modes or apply some kind of
5672 extension, truncation or alignment. */
5675 strip_address_mutations (rtx *loc, enum rtx_code *outer_code)
5679 enum rtx_code code = GET_CODE (*loc);
5680 if (GET_RTX_CLASS (code) == RTX_UNARY)
5681 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5682 used to convert between pointer sizes. */
5683 loc = &XEXP (*loc, 0);
5684 else if (lsb_bitfield_op_p (*loc))
5685 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5686 acts as a combined truncation and extension. */
5687 loc = &XEXP (*loc, 0);
5688 else if (code == AND && CONST_INT_P (XEXP (*loc, 1)))
5689 /* (and ... (const_int -X)) is used to align to X bytes. */
5690 loc = &XEXP (*loc, 0);
5691 else if (code == SUBREG
5692 && !OBJECT_P (SUBREG_REG (*loc))
5693 && subreg_lowpart_p (*loc))
5694 /* (subreg (operator ...) ...) inside and is used for mode
5696 loc = &SUBREG_REG (*loc);
5704 /* Return true if CODE applies some kind of scale. The scaled value is
5705 is the first operand and the scale is the second. */
5708 binary_scale_code_p (enum rtx_code code)
5710 return (code == MULT
5712 /* Needed by ARM targets. */
5716 || code == ROTATERT);
5719 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5720 (see address_info). Return null otherwise. */
5723 get_base_term (rtx *inner)
5725 if (GET_CODE (*inner) == LO_SUM)
5726 inner = strip_address_mutations (&XEXP (*inner, 0));
5729 || GET_CODE (*inner) == SUBREG)
5734 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5735 (see address_info). Return null otherwise. */
5738 get_index_term (rtx *inner)
5740 /* At present, only constant scales are allowed. */
5741 if (binary_scale_code_p (GET_CODE (*inner)) && CONSTANT_P (XEXP (*inner, 1)))
5742 inner = strip_address_mutations (&XEXP (*inner, 0));
5745 || GET_CODE (*inner) == SUBREG)
5750 /* Set the segment part of address INFO to LOC, given that INNER is the
5754 set_address_segment (struct address_info *info, rtx *loc, rtx *inner)
5756 gcc_assert (!info->segment);
5757 info->segment = loc;
5758 info->segment_term = inner;
5761 /* Set the base part of address INFO to LOC, given that INNER is the
5765 set_address_base (struct address_info *info, rtx *loc, rtx *inner)
5767 gcc_assert (!info->base);
5769 info->base_term = inner;
5772 /* Set the index part of address INFO to LOC, given that INNER is the
5776 set_address_index (struct address_info *info, rtx *loc, rtx *inner)
5778 gcc_assert (!info->index);
5780 info->index_term = inner;
5783 /* Set the displacement part of address INFO to LOC, given that INNER
5784 is the constant term. */
5787 set_address_disp (struct address_info *info, rtx *loc, rtx *inner)
5789 gcc_assert (!info->disp);
5791 info->disp_term = inner;
5794 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
5795 rest of INFO accordingly. */
5798 decompose_incdec_address (struct address_info *info)
5800 info->autoinc_p = true;
5802 rtx *base = &XEXP (*info->inner, 0);
5803 set_address_base (info, base, base);
5804 gcc_checking_assert (info->base == info->base_term);
5806 /* These addresses are only valid when the size of the addressed
5808 gcc_checking_assert (info->mode != VOIDmode);
5811 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
5812 of INFO accordingly. */
5815 decompose_automod_address (struct address_info *info)
5817 info->autoinc_p = true;
5819 rtx *base = &XEXP (*info->inner, 0);
5820 set_address_base (info, base, base);
5821 gcc_checking_assert (info->base == info->base_term);
5823 rtx plus = XEXP (*info->inner, 1);
5824 gcc_assert (GET_CODE (plus) == PLUS);
5826 info->base_term2 = &XEXP (plus, 0);
5827 gcc_checking_assert (rtx_equal_p (*info->base_term, *info->base_term2));
5829 rtx *step = &XEXP (plus, 1);
5830 rtx *inner_step = strip_address_mutations (step);
5831 if (CONSTANT_P (*inner_step))
5832 set_address_disp (info, step, inner_step);
5834 set_address_index (info, step, inner_step);
5837 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
5838 values in [PTR, END). Return a pointer to the end of the used array. */
5841 extract_plus_operands (rtx *loc, rtx **ptr, rtx **end)
5844 if (GET_CODE (x) == PLUS)
5846 ptr = extract_plus_operands (&XEXP (x, 0), ptr, end);
5847 ptr = extract_plus_operands (&XEXP (x, 1), ptr, end);
5851 gcc_assert (ptr != end);
5857 /* Evaluate the likelihood of X being a base or index value, returning
5858 positive if it is likely to be a base, negative if it is likely to be
5859 an index, and 0 if we can't tell. Make the magnitude of the return
5860 value reflect the amount of confidence we have in the answer.
5862 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
5865 baseness (rtx x, enum machine_mode mode, addr_space_t as,
5866 enum rtx_code outer_code, enum rtx_code index_code)
5868 /* Believe *_POINTER unless the address shape requires otherwise. */
5869 if (REG_P (x) && REG_POINTER (x))
5871 if (MEM_P (x) && MEM_POINTER (x))
5874 if (REG_P (x) && HARD_REGISTER_P (x))
5876 /* X is a hard register. If it only fits one of the base
5877 or index classes, choose that interpretation. */
5878 int regno = REGNO (x);
5879 bool base_p = ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
5880 bool index_p = REGNO_OK_FOR_INDEX_P (regno);
5881 if (base_p != index_p)
5882 return base_p ? 1 : -1;
5887 /* INFO->INNER describes a normal, non-automodified address.
5888 Fill in the rest of INFO accordingly. */
5891 decompose_normal_address (struct address_info *info)
5893 /* Treat the address as the sum of up to four values. */
5895 size_t n_ops = extract_plus_operands (info->inner, ops,
5896 ops + ARRAY_SIZE (ops)) - ops;
5898 /* If there is more than one component, any base component is in a PLUS. */
5900 info->base_outer_code = PLUS;
5902 /* Try to classify each sum operand now. Leave those that could be
5903 either a base or an index in OPS. */
5906 for (size_t in = 0; in < n_ops; ++in)
5909 rtx *inner = strip_address_mutations (loc);
5910 if (CONSTANT_P (*inner))
5911 set_address_disp (info, loc, inner);
5912 else if (GET_CODE (*inner) == UNSPEC)
5913 set_address_segment (info, loc, inner);
5916 /* The only other possibilities are a base or an index. */
5917 rtx *base_term = get_base_term (inner);
5918 rtx *index_term = get_index_term (inner);
5919 gcc_assert (base_term || index_term);
5921 set_address_index (info, loc, index_term);
5922 else if (!index_term)
5923 set_address_base (info, loc, base_term);
5926 gcc_assert (base_term == index_term);
5928 inner_ops[out] = base_term;
5934 /* Classify the remaining OPS members as bases and indexes. */
5937 /* If we haven't seen a base or an index yet, assume that this is
5938 the base. If we were confident that another term was the base
5939 or index, treat the remaining operand as the other kind. */
5941 set_address_base (info, ops[0], inner_ops[0]);
5943 set_address_index (info, ops[0], inner_ops[0]);
5947 /* In the event of a tie, assume the base comes first. */
5948 if (baseness (*inner_ops[0], info->mode, info->as, PLUS,
5950 >= baseness (*inner_ops[1], info->mode, info->as, PLUS,
5951 GET_CODE (*ops[0])))
5953 set_address_base (info, ops[0], inner_ops[0]);
5954 set_address_index (info, ops[1], inner_ops[1]);
5958 set_address_base (info, ops[1], inner_ops[1]);
5959 set_address_index (info, ops[0], inner_ops[0]);
5963 gcc_assert (out == 0);
5966 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
5967 or VOIDmode if not known. AS is the address space associated with LOC.
5968 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
5971 decompose_address (struct address_info *info, rtx *loc, enum machine_mode mode,
5972 addr_space_t as, enum rtx_code outer_code)
5974 memset (info, 0, sizeof (*info));
5977 info->addr_outer_code = outer_code;
5979 info->inner = strip_address_mutations (loc, &outer_code);
5980 info->base_outer_code = outer_code;
5981 switch (GET_CODE (*info->inner))
5987 decompose_incdec_address (info);
5992 decompose_automod_address (info);
5996 decompose_normal_address (info);
6001 /* Describe address operand LOC in INFO. */
6004 decompose_lea_address (struct address_info *info, rtx *loc)
6006 decompose_address (info, loc, VOIDmode, ADDR_SPACE_GENERIC, ADDRESS);
6009 /* Describe the address of MEM X in INFO. */
6012 decompose_mem_address (struct address_info *info, rtx x)
6014 gcc_assert (MEM_P (x));
6015 decompose_address (info, &XEXP (x, 0), GET_MODE (x),
6016 MEM_ADDR_SPACE (x), MEM);
6019 /* Update INFO after a change to the address it describes. */
6022 update_address (struct address_info *info)
6024 decompose_address (info, info->outer, info->mode, info->as,
6025 info->addr_outer_code);
6028 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6029 more complicated than that. */
6032 get_index_scale (const struct address_info *info)
6034 rtx index = *info->index;
6035 if (GET_CODE (index) == MULT
6036 && CONST_INT_P (XEXP (index, 1))
6037 && info->index_term == &XEXP (index, 0))
6038 return INTVAL (XEXP (index, 1));
6040 if (GET_CODE (index) == ASHIFT
6041 && CONST_INT_P (XEXP (index, 1))
6042 && info->index_term == &XEXP (index, 0))
6043 return (HOST_WIDE_INT) 1 << INTVAL (XEXP (index, 1));
6045 if (info->index == info->index_term)
6051 /* Return the "index code" of INFO, in the form required by
6055 get_index_code (const struct address_info *info)
6058 return GET_CODE (*info->index);
6061 return GET_CODE (*info->disp);
6066 /* Return true if X contains a thread-local symbol. */
6069 tls_referenced_p (const_rtx x)
6071 if (!targetm.have_tls)
6074 subrtx_iterator::array_type array;
6075 FOR_EACH_SUBRTX (iter, array, x, ALL)
6076 if (GET_CODE (*iter) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (*iter) != 0)