1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987-1991 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* Expression definitions and descriptions for all targets are in this file.
24 Some will not be used for some targets.
26 The fields in the cpp macro call "DEF_RTL_EXPR()"
27 are used to create declarations in the C source of the compiler.
31 1. The internal name of the rtx used in the C source.
32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33 By convention these are in UPPER_CASE.
35 2. The name of the rtx in the external ASCII format read by
36 read_rtx(), and printed by print_rtx().
37 These names are stored in rtx_name[].
38 By convention these are the internal (field 1) names in lower_case.
40 3. The print format, and type of each rtx->fld[] (field) in this rtx.
41 These formats are stored in rtx_format[].
42 The meaning of the formats is documented in front of this array in rtl.c
44 4. The class of the rtx. These are stored in rtx_class and are accessed
45 via the GET_RTX_CLASS macro. They are defined as follows:
47 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
48 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
49 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
50 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
51 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
52 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
53 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
54 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
55 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
60 /* ---------------------------------------------------------------------
61 Expressions (and "meta" expressions) used for structuring the
62 rtl representation of a program.
63 --------------------------------------------------------------------- */
65 /* an expression code name unknown to the reader */
66 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
68 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
70 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
72 /* ---------------------------------------------------------------------
73 Expressions used in constructing lists.
74 --------------------------------------------------------------------- */
76 /* a linked list of expressions */
77 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
79 /* a linked list of instructions.
80 The insns are represented in print by their uids. */
81 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
83 /* ----------------------------------------------------------------------
84 Expression types for machine descripions.
85 These do not appear in actual rtl code in the compiler.
86 ---------------------------------------------------------------------- */
88 /* Appears only in machine descriptions.
89 Means use the function named by the second arg (the string)
90 as a predicate; if matched, store the structure that was matched
91 in the operand table at index specified by the first arg (the integer).
92 If the second arg is the null string, the structure is just stored.
94 A third string argument indicates to the register allocator restrictions
95 on where the operand can be allocated.
97 If the target needs no restriction on any instruction this field should
100 The string is prepended by:
101 '=' to indicate the operand is only written to.
102 '+' to indicate the operand is both read and written to.
104 Each character in the string represents an allocatable class for an operand.
105 'g' indicates the operand can be any valid class.
106 'i' indicates the operand can be immediate (in the instruction) data.
107 'r' indicates the operand can be in a register.
108 'm' indicates the operand can be in memory.
109 'o' a subset of the 'm' class. Those memory addressing modes that
110 can be offset at compile time (have a constant added to them).
112 Other characters indicate target dependent operand classes and
113 are described in each target's machine description.
115 For instructions with more than one operand, sets of classes can be
116 separated by a comma to indicate the appropriate multi-operand constraints.
117 There must be a 1 to 1 correspondence between these sets of classes in
118 all operands for an instruction.
120 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
122 /* Appears only in machine descriptions.
123 Means match a SCRATCH or a register. When used to generate rtl, a
124 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
125 the desired mode and the first argument is the operand number.
126 The second argument is the constraint. */
127 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
129 /* Appears only in machine descriptions.
130 Means match only something equal to what is stored in the operand table
131 at the index specified by the argument. */
132 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
134 /* Appears only in machine descriptions.
135 Means apply a predicate, AND match recursively the operands of the rtx.
136 Operand 0 is the operand-number, as in match_operand.
137 Operand 1 is a predicate to apply (as a string, a function name).
138 Operand 2 is a vector of expressions, each of which must match
139 one subexpression of the rtx this construct is matching. */
140 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
142 /* Appears only in machine descriptions.
143 Means to match a PARALLEL of arbitrary length. The predicate is applied
144 to the PARALLEL and the initial expressions in the PARALLEL are matched.
145 Operand 0 is the operand-number, as in match_operand.
146 Operand 1 is a predicate to apply to the PARALLEL.
147 Operand 2 is a vector of expressions, each of which must match the
148 corresponding element in the PARALLEL. */
149 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
151 /* Appears only in machine descriptions.
152 Means match only something equal to what is stored in the operand table
153 at the index specified by the argument. For MATCH_OPERATOR. */
154 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
156 /* Appears only in machine descriptions.
157 Defines the pattern for one kind of instruction.
159 0: names this instruction.
160 If the name is the null string, the instruction is in the
161 machine description just to be recognized, and will never be emitted by
162 the tree to rtl expander.
164 2: is a string which is a C expression
165 giving an additional condition for recognizing this pattern.
166 A null string means no extra condition.
167 3: is the action to execute if this pattern is matched.
168 If this assembler code template starts with a * then it is a fragment of
169 C code to run to decide on a template to use. Otherwise, it is the
171 4: optionally, a vector of attributes for this insn.
173 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
175 /* Definition of a peephole optimization.
176 1st operand: vector of insn patterns to match
177 2nd operand: C expression that must be true
178 3rd operand: template or C code to produce assembler output.
179 4: optionally, a vector of attributes for this insn.
181 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
183 /* Definition of a split operation.
184 1st operand: insn pattern to match
185 2nd operand: C expression that must be true
186 3rd operand: vector of insn patterns to place into a SEQUENCE
187 4th operand: optionally, some C code to execute before generating the
188 insns. This might, for example, create some RTX's and store them in
189 elements of `recog_operand' for use by the vector of insn-patterns.
190 (`operands' is an alias here for `recog_operand'). */
191 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
193 /* Definition of a combiner pattern.
194 Operands not defined yet. */
195 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
197 /* Define how to generate multiple insns for a standard insn name.
198 1st operand: the insn name.
199 2nd operand: vector of insn-patterns.
200 Use match_operand to substitute an element of `recog_operand'.
201 3rd operand: C expression that must be true for this to be available.
202 This may not test any operands.
203 4th operand: Extra C code to execute before generating the insns.
204 This might, for example, create some RTX's and store them in
205 elements of `recog_operand' for use by the vector of insn-patterns.
206 (`operands' is an alias here for `recog_operand'). */
207 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
209 /* Define a requirement for delay slots.
210 1st operand: Condition involving insn attributes that, if true,
211 indicates that the insn requires the number of delay slots
213 2nd operand: Vector whose length is the three times the number of delay
215 Each entry gives three conditions, each involving attributes.
216 The first must be true for an insn to occupy that delay slot
217 location. The second is true for all insns that can be
218 annulled if the branch is true and the third is true for all
219 insns that can be annulled if the branch is false.
221 Multiple DEFINE_DELAYs may be present. They indicate differing
222 requirements for delay slots. */
223 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
225 /* Define a set of insns that requires a function unit. This means that
226 these insns produce their result after a delay and that there may be
227 restrictions on the number of insns of this type that can be scheduled
230 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
231 Each gives a set of operations and associated delays. The first three
232 operands must be the same for each operation for the same function unit.
234 All delays are specified in units of COST_PER_CYCLE.
236 1st operand: Name of function unit (mostly for documentation)
237 2nd operand: Number of identical function units in CPU
238 3rd operand: Total number of simultaneous insns that can execute on this
239 function unit; 0 if unlimited.
240 4th operand: Condition involving insn attribute, that, if true, specifies
241 those insns that this expression applies to.
242 5th operand: Constant delay after which insn result will be
244 6th operand: Delay until next insn can be scheduled on the function unit
245 executing this operation. The meaning depends on whether or
246 not the next operand is supplied.
247 7th operand: If this operand is not specified, the 6th operand gives the
248 cost of scheduling another operation on this unit while a
249 previous one is active. A value of zero should be used for a
250 pipelined unit. If only one operation can be executed a time
251 and the unit is busy for the entire time, the 3rd operand
252 should be specified as 1 and the 6th and 7th operands will
255 If this operand is specified, it is a list of attribute
256 expressions. If an insn for which any of these expressions
257 is true is currently executing on the function unit, the
258 delay will be given by the 6th operand. Otherwise, the
259 insn can be immediately scheduled (subject to the limit on
260 the number of simultaneous operations executing on the
262 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
264 /* Define attribute computation for `asm' instructions. */
265 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
267 /* SEQUENCE appears in the result of a `gen_...' function
268 for a DEFINE_EXPAND that wants to make several insns.
269 Its elements are the bodies of the insns that should be made.
270 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
271 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
273 /* Refers to the address of its argument.
274 This appears only in machine descriptions, indicating that
275 any expression that would be acceptable as the operand of MEM
276 should be matched. */
277 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
279 /* ----------------------------------------------------------------------
280 Expressions used for insn attributes. These also do not appear in
281 actual rtl code in the compiler.
282 ---------------------------------------------------------------------- */
284 /* Definition of an insn attribute.
285 1st operand: name of the attribute
286 2nd operand: comma-separated list of possible attribute values
287 3rd operand: expression for the default value of the attribute. */
288 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
290 /* Marker for the name of an attribute. */
291 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
293 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
294 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
297 (set_attr "name" "value") is equivalent to
298 (set (attr "name") (const_string "value")) */
299 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
301 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
302 specify that attribute values are to be assigned according to the
305 The following three expressions are equivalent:
307 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
308 (eq_attrq "alternative" "2") (const_string "a2")]
309 (const_string "a3")))
310 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
311 (const_string "a3")])
312 (set_attr "att" "a1,a2,a3")
314 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
316 /* A conditional expression true if the value of the specified attribute of
317 the current insn equals the specified value. The first operand is the
318 attribute name and the second is the comparison value. */
319 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
321 /* ----------------------------------------------------------------------
322 Expression types used for things in the instruction chain.
324 All formats must start with "iuu" to handle the chain.
325 Each insn expression holds an rtl instruction and its semantics
326 during back-end processing.
327 See macros's in "rtl.h" for the meaning of each rtx->fld[].
329 ---------------------------------------------------------------------- */
331 /* An instruction that cannot jump. */
332 DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
334 /* An instruction that can possibly jump.
335 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
336 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
338 /* An instruction that can possibly call a subroutine
339 but which will not change which instruction comes next
340 in the current function.
341 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
342 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueiee", 'i')
344 /* A marker that indicates that control will not flow through. */
345 DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
347 /* Holds a label that is followed by instructions.
349 3: is a number that is unique in the entire compilation.
350 4: is the user-given name of the label, if any.
351 5: is used in jump.c for the use-count of the label.
352 and in flow.c to point to the chain of label_ref's to this label. */
353 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis0", 'x')
355 /* Say where in the code a source line starts, for symbol table's sake.
356 Contains a filename and a line number. Line numbers <= 0 are special:
357 0 is used in a dummy placed at the front of every function
358 just so there will never be a need to delete the first insn;
359 -1 indicates a dummy; insns to be deleted by flow analysis and combining
360 are really changed to NOTEs with a number of -1.
361 -2 means beginning of a name binding contour; output N_LBRAC.
362 -3 means end of a contour; output N_RBRAC. */
363 DEF_RTL_EXPR(NOTE, "note", "iuusn", 'x')
365 /* INLINE_HEADER is use by inline function machinery. The information
366 it contains helps to build the mapping function between the rtx's of
367 the function to be inlined and the current function being expanded. */
369 DEF_RTL_EXPR(INLINE_HEADER, "inline_header", "iuuuiiiiiieiiEe", 'x')
371 /* ----------------------------------------------------------------------
372 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
373 ---------------------------------------------------------------------- */
375 /* Several operations to be done in parallel. */
376 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
378 /* A string that is passed through to the assembler as input.
379 One can obviously pass comments through by using the
380 assembler comment syntax.
381 These occur in an insn all by themselves as the PATTERN.
382 They also appear inside an ASM_OPERANDS
383 as a convenient way to hold a string. */
384 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
386 /* An assembler instruction with operands.
387 1st operand is the instruction template.
388 2nd operand is the constraint for the output.
389 3rd operand is the number of the output this expression refers to.
390 When an insn stores more than one value, a separate ASM_OPERANDS
391 is made for each output; this integer distinguishes them.
392 4th is a vector of values of input operands.
393 5th is a vector of modes and constraints for the input operands.
394 Each element is an ASM_INPUT containing a constraint string
395 and whose mode indicates the mode of the input operand.
396 6th is the name of the containing source file.
397 7th is the source line number. */
398 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
400 /* Vector of addresses, stored as full words. */
401 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
402 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
404 /* Vector of address differences X0 - BASE, X1 - BASE, ...
405 First operand is BASE; the vector contains the X's.
406 The machine mode of this rtx says how much space to leave
407 for each difference. */
408 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eE", 'x')
410 /* ----------------------------------------------------------------------
411 At the top level of an instruction (perhaps under PARALLEL).
412 ---------------------------------------------------------------------- */
415 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
416 Operand 2 is the value stored there.
417 ALL assignment must use SET.
418 Instructions that do multiple assignments must use multiple SET,
420 DEF_RTL_EXPR(SET, "set", "ee", 'x')
422 /* Indicate something is used in a way that we don't want to explain.
423 For example, subroutine calls will use the register
424 in which the static chain is passed. */
425 DEF_RTL_EXPR(USE, "use", "e", 'x')
427 /* Indicate something is clobbered in a way that we don't want to explain.
428 For example, subroutine calls will clobber some physical registers
429 (the ones that are by convention not saved). */
430 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
432 /* Call a subroutine.
433 Operand 1 is the address to call.
434 Operand 2 is the number of arguments. */
436 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
438 /* Return from a subroutine. */
440 DEF_RTL_EXPR(RETURN, "return", "", 'x')
443 Operand 1 is the condition.
444 Operand 2 is the trap code.
445 For an unconditional trap, make the condition (const_int 1). */
446 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ei", 'x')
448 /* ----------------------------------------------------------------------
449 Primitive values for use in expressions.
450 ---------------------------------------------------------------------- */
452 /* numeric integer constant */
453 DEF_RTL_EXPR(CONST_INT, "const_int", "i", 'o')
455 /* numeric double constant.
456 Operand 0 is the MEM that stores this constant in memory,
457 or various other things (see comments at immed_double_const in varasm.c).
458 Operand 1 is a chain of all CONST_DOUBLEs in use in the current function.
459 Remaining operands hold the actual value.
460 The number of operands may be more than 2 if cross-compiling;
462 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", "e0ii", 'o')
464 /* String constant. Used only for attributes right now. */
465 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
467 /* This is used to encapsulate an expression whose value is constant
468 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
469 recognized as a constant operand rather than by arithmetic instructions. */
471 DEF_RTL_EXPR(CONST, "const", "e", 'o')
473 /* program counter. Ordinary jumps are represented
474 by a SET whose first operand is (PC). */
475 DEF_RTL_EXPR(PC, "pc", "", 'o')
477 /* A register. The "operand" is the register number, accessed
478 with the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
479 than a hardware register is being referred to. */
480 DEF_RTL_EXPR(REG, "reg", "i", 'o')
482 /* A scratch register. This represents a register used only within a
483 single insn. It will be turned into a REG during register allocation
484 or reload unless the constraint indicates that the register won't be
485 needed, in which case it can remain a SCRATCH. This code is
486 marked as having one operand so it can be turned into a REG. */
487 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
489 /* One word of a multi-word value.
490 The first operand is the complete value; the second says which word.
491 The WORDS_BIG_ENDIAN flag controls whether word number 0
492 (as numbered in a SUBREG) is the most or least significant word.
494 This is also used to refer to a value in a different machine mode.
495 For example, it can be used to refer to a SImode value as if it were
496 Qimode, or vice versa. Then the word number is always 0. */
497 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
499 /* This one-argument rtx is used for move instructions
500 that are guaranteed to alter only the low part of a destination.
501 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
502 has an unspecified effect on the high part of REG,
503 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
504 is guaranteed to alter only the bits of REG that are in HImode.
506 The actual instruction used is probably the same in both cases,
507 but the register constraints may be tighter when STRICT_LOW_PART
510 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
512 /* A memory location; operand is the address.
513 Can be nested inside a VOLATILE. */
514 DEF_RTL_EXPR(MEM, "mem", "e", 'o')
516 /* Reference to an assembler label in the code for this function.
517 The operand is a CODE_LABEL found in the insn chain.
518 The unprinted fields 1 and 2 are used in flow.c for the
519 LABEL_NEXTREF and CONTAINING_INSN. */
520 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
522 /* Reference to a named label: the string that is the first operand,
523 with `_' added implicitly in front.
524 Exception: if the first character explicitly given is `*',
525 to give it to the assembler, remove the `*' and do not add `_'. */
526 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
528 /* The condition code register is represented, in our imagination,
529 as a register holding a value that can be compared to zero.
530 In fact, the machine has already compared them and recorded the
531 results; but instructions that look at the condition code
532 pretend to be looking at the entire value and comparing it. */
533 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
535 /* =====================================================================
536 A QUEUED expression really points to a member of the queue of instructions
537 to be output later for postincrement/postdecrement.
538 QUEUED expressions never become part of instructions.
539 When a QUEUED expression would be put into an instruction,
540 instead either the incremented variable or a copy of its previous
544 0. the variable to be incremented (a REG rtx).
545 1. the incrementing instruction, or 0 if it hasn't been output yet.
546 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
547 3. the body to use for the incrementing instruction
548 4. the next QUEUED expression in the queue.
549 ====================================================================== */
551 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
553 /* ----------------------------------------------------------------------
554 Expressions for operators in an rtl pattern
555 ---------------------------------------------------------------------- */
557 /* if_then_else. This is used in representing ordinary
558 conditional jump instructions.
563 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
565 /* General conditional. The first operand is a vector composed of pairs of
566 expressions. The first element of each pair is evaluated, in turn.
567 The value of the conditional is the second expression of the first pair
568 whose first expression evaluates non-zero. If none of the expressions is
569 true, the second operand will be used as the value of the conditional.
571 This should be replaced with use of IF_THEN_ELSE. */
572 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
574 /* Comparison, produces a condition code result. */
575 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
578 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
580 /* Operand 0 minus operand 1. */
581 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
583 /* Minus operand 0. */
584 DEF_RTL_EXPR(NEG, "neg", "e", '1')
586 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
588 /* Operand 0 divided by operand 1. */
589 DEF_RTL_EXPR(DIV, "div", "ee", '2')
590 /* Remainder of operand 0 divided by operand 1. */
591 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
593 /* Unsigned divide and remainder. */
594 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
595 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
597 /* Bitwise operations. */
598 DEF_RTL_EXPR(AND, "and", "ee", 'c')
600 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
602 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
604 DEF_RTL_EXPR(NOT, "not", "e", '1')
607 0: value to be shifted.
609 ASHIFT and LSHIFT are distinguished because on some machines
610 these allow a negative operand and shift right in that case. */
611 DEF_RTL_EXPR(LSHIFT, "lshift", "ee", '2')
612 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
613 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
615 /* Right shift operations, for machines where these are not the same
616 as left shifting with a negative argument. */
618 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2')
619 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2')
620 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2')
622 /* Minimum and maximum values of two operands. We need both signed and
623 unsigned forms. (We cannot use MIN for SMIN because it conflicts
624 with a macro of the same name.) */
626 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
627 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
628 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
629 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
631 /* These unary operations are used to represent incrementation
632 and decrementation as they occur in memory addresses.
633 The amount of increment or decrement are not represented
634 because they can be understood from the machine-mode of the
635 containing MEM. These operations exist in only two cases:
636 1. pushes onto the stack.
637 2. created automatically by the life_analysis pass in flow.c. */
638 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
639 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
640 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
641 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
643 /* Comparison operations. The ordered comparisons exist in two
644 flavors, signed and unsigned. */
645 DEF_RTL_EXPR(NE, "ne", "ee", '<')
646 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
647 DEF_RTL_EXPR(GE, "ge", "ee", '<')
648 DEF_RTL_EXPR(GT, "gt", "ee", '<')
649 DEF_RTL_EXPR(LE, "le", "ee", '<')
650 DEF_RTL_EXPR(LT, "lt", "ee", '<')
651 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
652 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
653 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
654 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
656 /* Represents the result of sign-extending the sole operand.
657 The machine modes of the operand and of the SIGN_EXTEND expression
658 determine how much sign-extension is going on. */
659 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
661 /* Similar for zero-extension (such as unsigned short to int). */
662 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
664 /* Similar but here the operand has a wider mode. */
665 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
667 /* Similar for extending floating-point values (such as SFmode to DFmode). */
668 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
669 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
671 /* Conversion of fixed point operand to floating point value. */
672 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
674 /* With fixed-point machine mode:
675 Conversion of floating point operand to fixed point value.
676 Value is defined only when the operand's value is an integer.
677 With floating-point machine mode (and operand with same mode):
678 Operand is rounded toward zero to produce an integer value
679 represented in floating point. */
680 DEF_RTL_EXPR(FIX, "fix", "e", '1')
682 /* Conversion of unsigned fixed point operand to floating point value. */
683 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
685 /* With fixed-point machine mode:
686 Conversion of floating point operand to *unsigned* fixed point value.
687 Value is defined only when the operand's value is an integer. */
688 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
691 DEF_RTL_EXPR(ABS, "abs", "e", '1')
694 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
696 /* Find first bit that is set.
697 Value is 1 + number of trailing zeros in the arg.,
699 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
701 /* Reference to a signed bit-field of specified size and position.
702 Operand 0 is the memory unit (usually SImode or QImode) which
703 contains the field's first bit. Operand 1 is the width, in bits.
704 Operand 2 is the number of bits in the memory unit before the
705 first bit of this field.
706 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
707 operand 2 counts from the msb of the memory unit.
708 Otherwise, the first bit is the lsb and operand 2 counts from
709 the lsb of the memory unit. */
710 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
712 /* Similar for unsigned bit-field. */
713 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
715 /* For RISC machines. These save memory when splitting insns. */
717 /* HIGH are the high-order bits of a constant expression. */
718 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
720 /* LO_SUM is the sum of a register and the low-order bits
721 of a constant expression. */
722 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
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