1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Instruction reorganization pass.
25 This pass runs after register allocation and final jump
26 optimization. It should be the last pass to run before peephole.
27 It serves primarily to fill delay slots of insns, typically branch
28 and call insns. Other insns typically involve more complicated
29 interactions of data dependencies and resource constraints, and
30 are better handled by scheduling before register allocation (by the
31 function `schedule_insns').
33 The Branch Penalty is the number of extra cycles that are needed to
34 execute a branch insn. On an ideal machine, branches take a single
35 cycle, and the Branch Penalty is 0. Several RISC machines approach
36 branch delays differently:
38 The MIPS and AMD 29000 have a single branch delay slot. Most insns
39 (except other branches) can be used to fill this slot. When the
40 slot is filled, two insns execute in two cycles, reducing the
41 branch penalty to zero.
43 The Motorola 88000 conditionally exposes its branch delay slot,
44 so code is shorter when it is turned off, but will run faster
45 when useful insns are scheduled there.
47 The IBM ROMP has two forms of branch and call insns, both with and
48 without a delay slot. Much like the 88k, insns not using the delay
49 slot can be shorted (2 bytes vs. 4 bytes), but will run slowed.
51 The SPARC always has a branch delay slot, but its effects can be
52 annulled when the branch is not taken. This means that failing to
53 find other sources of insns, we can hoist an insn from the branch
54 target that would only be safe to execute knowing that the branch
57 The HP-PA always has a branch delay slot. For unconditional branches
58 its effects can be annulled when the branch is taken. The effects
59 of the delay slot in a conditional branch can be nullified for forward
60 taken branches, or for untaken backward branches. This means
61 we can hoist insns from the fall-through path for forward branches or
62 steal insns from the target of backward branches.
64 Three techniques for filling delay slots have been implemented so far:
66 (1) `fill_simple_delay_slots' is the simplest, most efficient way
67 to fill delay slots. This pass first looks for insns which come
68 from before the branch and which are safe to execute after the
69 branch. Then it searches after the insn requiring delay slots or,
70 in the case of a branch, for insns that are after the point at
71 which the branch merges into the fallthrough code, if such a point
72 exists. When such insns are found, the branch penalty decreases
73 and no code expansion takes place.
75 (2) `fill_eager_delay_slots' is more complicated: it is used for
76 scheduling conditional jumps, or for scheduling jumps which cannot
77 be filled using (1). A machine need not have annulled jumps to use
78 this strategy, but it helps (by keeping more options open).
79 `fill_eager_delay_slots' tries to guess the direction the branch
80 will go; if it guesses right 100% of the time, it can reduce the
81 branch penalty as much as `fill_simple_delay_slots' does. If it
82 guesses wrong 100% of the time, it might as well schedule nops (or
83 on the m88k, unexpose the branch slot). When
84 `fill_eager_delay_slots' takes insns from the fall-through path of
85 the jump, usually there is no code expansion; when it takes insns
86 from the branch target, there is code expansion if it is not the
87 only way to reach that target.
89 (3) `relax_delay_slots' uses a set of rules to simplify code that
90 has been reorganized by (1) and (2). It finds cases where
91 conditional test can be eliminated, jumps can be threaded, extra
92 insns can be eliminated, etc. It is the job of (1) and (2) to do a
93 good job of scheduling locally; `relax_delay_slots' takes care of
94 making the various individual schedules work well together. It is
95 especially tuned to handle the control flow interactions of branch
96 insns. It does nothing for insns with delay slots that do not
99 On machines that use CC0, we are very conservative. We will not make
100 a copy of an insn involving CC0 since we want to maintain a 1-1
101 correspondence between the insn that sets and uses CC0. The insns are
102 allowed to be separated by placing an insn that sets CC0 (but not an insn
103 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
104 delay slot. In that case, we point each insn at the other with REG_CC_USER
105 and REG_CC_SETTER notes. Note that these restrictions affect very few
106 machines because most RISC machines with delay slots will not use CC0
107 (the RT is the only known exception at this point).
111 The Acorn Risc Machine can conditionally execute most insns, so
112 it is profitable to move single insns into a position to execute
113 based on the condition code of the previous insn.
115 The HP-PA can conditionally nullify insns, providing a similar
116 effect to the ARM, differing mostly in which insn is "in charge". */
122 #include "insn-config.h"
123 #include "conditions.h"
124 #include "hard-reg-set.h"
125 #include "basic-block.h"
127 #include "insn-flags.h"
132 #include "insn-attr.h"
134 /* Import list of registers used as spill regs from reload. */
135 extern HARD_REG_SET used_spill_regs;
137 /* Import highest label used in function at end of reload. */
138 extern int max_label_num_after_reload;
143 #define obstack_chunk_alloc xmalloc
144 #define obstack_chunk_free free
146 #ifndef ANNUL_IFTRUE_SLOTS
147 #define eligible_for_annul_true(INSN, SLOTS, TRIAL, FLAGS) 0
149 #ifndef ANNUL_IFFALSE_SLOTS
150 #define eligible_for_annul_false(INSN, SLOTS, TRIAL, FLAGS) 0
153 /* Insns which have delay slots that have not yet been filled. */
155 static struct obstack unfilled_slots_obstack;
156 static rtx *unfilled_firstobj;
158 /* Define macros to refer to the first and last slot containing unfilled
159 insns. These are used because the list may move and its address
160 should be recomputed at each use. */
162 #define unfilled_slots_base \
163 ((rtx *) obstack_base (&unfilled_slots_obstack))
165 #define unfilled_slots_next \
166 ((rtx *) obstack_next_free (&unfilled_slots_obstack))
168 /* This structure is used to indicate which hardware resources are set or
169 needed by insns so far. */
173 char memory; /* Insn sets or needs a memory location. */
174 char unch_memory; /* Insn sets of needs a "unchanging" MEM. */
175 char volatil; /* Insn sets or needs a volatile memory loc. */
176 char cc; /* Insn sets or needs the condition codes. */
177 HARD_REG_SET regs; /* Which registers are set or needed. */
180 /* Macro to clear all resources. */
181 #define CLEAR_RESOURCE(RES) \
182 do { (RES)->memory = (RES)->unch_memory = (RES)->volatil = (RES)->cc = 0; \
183 CLEAR_HARD_REG_SET ((RES)->regs); } while (0)
185 /* Indicates what resources are required at the beginning of the epilogue. */
186 static struct resources start_of_epilogue_needs;
188 /* Indicates what resources are required at function end. */
189 static struct resources end_of_function_needs;
191 /* Points to the label before the end of the function. */
192 static rtx end_of_function_label;
194 /* This structure is used to record liveness information at the targets or
195 fallthrough insns of branches. We will most likely need the information
196 at targets again, so save them in a hash table rather than recomputing them
201 int uid; /* INSN_UID of target. */
202 struct target_info *next; /* Next info for same hash bucket. */
203 HARD_REG_SET live_regs; /* Registers live at target. */
204 int block; /* Basic block number containing target. */
205 int bb_tick; /* Generation count of basic block info. */
208 #define TARGET_HASH_PRIME 257
210 /* Define the hash table itself. */
211 static struct target_info **target_hash_table;
213 /* For each basic block, we maintain a generation number of its basic
214 block info, which is updated each time we move an insn from the
215 target of a jump. This is the generation number indexed by block
218 static int *bb_ticks;
220 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
221 not always monotonically increase. */
222 static int *uid_to_ruid;
224 /* Highest valid index in `uid_to_ruid'. */
227 static void mark_referenced_resources PROTO((rtx, struct resources *, int));
228 static void mark_set_resources PROTO((rtx, struct resources *, int, int));
229 static int stop_search_p PROTO((rtx, int));
230 static int resource_conflicts_p PROTO((struct resources *,
231 struct resources *));
232 static int insn_references_resource_p PROTO((rtx, struct resources *, int));
233 static int insn_sets_resource_p PROTO((rtx, struct resources *, int));
234 static rtx find_end_label PROTO((void));
235 static rtx emit_delay_sequence PROTO((rtx, rtx, int));
236 static rtx add_to_delay_list PROTO((rtx, rtx));
237 static void delete_from_delay_slot PROTO((rtx));
238 static void delete_scheduled_jump PROTO((rtx));
239 static void note_delay_statistics PROTO((int, int));
240 static rtx optimize_skip PROTO((rtx));
241 static int get_jump_flags PROTO((rtx, rtx));
242 static int rare_destination PROTO((rtx));
243 static int mostly_true_jump PROTO((rtx, rtx));
244 static rtx get_branch_condition PROTO((rtx, rtx));
245 static int condition_dominates_p PROTO((rtx, rtx));
246 static rtx steal_delay_list_from_target PROTO((rtx, rtx, rtx, rtx,
250 int, int *, int *, rtx *));
251 static rtx steal_delay_list_from_fallthrough PROTO((rtx, rtx, rtx, rtx,
256 static void try_merge_delay_insns PROTO((rtx, rtx));
257 static rtx redundant_insn PROTO((rtx, rtx, rtx));
258 static int own_thread_p PROTO((rtx, rtx, int));
259 static int find_basic_block PROTO((rtx));
260 static void update_block PROTO((rtx, rtx));
261 static int reorg_redirect_jump PROTO((rtx, rtx));
262 static void update_reg_dead_notes PROTO((rtx, rtx));
263 static void fix_reg_dead_note PROTO((rtx, rtx));
264 static void update_reg_unused_notes PROTO((rtx, rtx));
265 static void update_live_status PROTO((rtx, rtx));
266 static rtx next_insn_no_annul PROTO((rtx));
267 static void mark_target_live_regs PROTO((rtx, struct resources *));
268 static void fill_simple_delay_slots PROTO((int));
269 static rtx fill_slots_from_thread PROTO((rtx, rtx, rtx, rtx, int, int,
270 int, int, int *, rtx));
271 static void fill_eager_delay_slots PROTO((void));
272 static void relax_delay_slots PROTO((rtx));
273 static void make_return_insns PROTO((rtx));
274 static int redirect_with_delay_slots_safe_p PROTO ((rtx, rtx, rtx));
275 static int redirect_with_delay_list_safe_p PROTO ((rtx, rtx, rtx));
277 /* Given X, some rtl, and RES, a pointer to a `struct resource', mark
278 which resources are references by the insn. If INCLUDE_DELAYED_EFFECTS
279 is TRUE, resources used by the called routine will be included for
283 mark_referenced_resources (x, res, include_delayed_effects)
285 register struct resources *res;
286 register int include_delayed_effects;
288 register enum rtx_code code = GET_CODE (x);
290 register char *format_ptr;
292 /* Handle leaf items for which we set resource flags. Also, special-case
293 CALL, SET and CLOBBER operators. */
305 if (GET_CODE (SUBREG_REG (x)) != REG)
306 mark_referenced_resources (SUBREG_REG (x), res, 0);
309 int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
310 int last_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
311 for (i = regno; i < last_regno; i++)
312 SET_HARD_REG_BIT (res->regs, i);
317 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
318 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
322 /* If this memory shouldn't change, it really isn't referencing
324 if (RTX_UNCHANGING_P (x))
325 res->unch_memory = 1;
328 res->volatil = MEM_VOLATILE_P (x);
330 /* Mark registers used to access memory. */
331 mark_referenced_resources (XEXP (x, 0), res, 0);
338 case UNSPEC_VOLATILE:
341 /* Traditional asm's are always volatile. */
346 res->volatil = MEM_VOLATILE_P (x);
348 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
349 We can not just fall through here since then we would be confused
350 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
351 traditional asms unlike their normal usage. */
353 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
354 mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, 0);
358 /* The first operand will be a (MEM (xxx)) but doesn't really reference
359 memory. The second operand may be referenced, though. */
360 mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, 0);
361 mark_referenced_resources (XEXP (x, 1), res, 0);
365 /* Usually, the first operand of SET is set, not referenced. But
366 registers used to access memory are referenced. SET_DEST is
367 also referenced if it is a ZERO_EXTRACT or SIGN_EXTRACT. */
369 mark_referenced_resources (SET_SRC (x), res, 0);
372 if (GET_CODE (x) == SIGN_EXTRACT || GET_CODE (x) == ZERO_EXTRACT)
373 mark_referenced_resources (x, res, 0);
374 else if (GET_CODE (x) == SUBREG)
376 if (GET_CODE (x) == MEM)
377 mark_referenced_resources (XEXP (x, 0), res, 0);
384 if (include_delayed_effects)
386 /* A CALL references memory, the frame pointer if it exists, the
387 stack pointer, any global registers and any registers given in
388 USE insns immediately in front of the CALL.
390 However, we may have moved some of the parameter loading insns
391 into the delay slot of this CALL. If so, the USE's for them
392 don't count and should be skipped. */
393 rtx insn = PREV_INSN (x);
396 rtx next = NEXT_INSN (x);
399 /* If we are part of a delay slot sequence, point at the SEQUENCE. */
400 if (NEXT_INSN (insn) != x)
402 next = NEXT_INSN (NEXT_INSN (insn));
403 sequence = PATTERN (NEXT_INSN (insn));
404 seq_size = XVECLEN (sequence, 0);
405 if (GET_CODE (sequence) != SEQUENCE)
410 SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM);
411 if (frame_pointer_needed)
413 SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM);
414 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
415 SET_HARD_REG_BIT (res->regs, HARD_FRAME_POINTER_REGNUM);
419 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
421 SET_HARD_REG_BIT (res->regs, i);
423 /* Check for a NOTE_INSN_SETJMP. If it exists, then we must
424 assume that this call can need any register.
426 This is done to be more conservative about how we handle setjmp.
427 We assume that they both use and set all registers. Using all
428 registers ensures that a register will not be considered dead
429 just because it crosses a setjmp call. A register should be
430 considered dead only if the setjmp call returns non-zero. */
431 if (next && GET_CODE (next) == NOTE
432 && NOTE_LINE_NUMBER (next) == NOTE_INSN_SETJMP)
433 SET_HARD_REG_SET (res->regs);
438 for (link = CALL_INSN_FUNCTION_USAGE (x);
440 link = XEXP (link, 1))
441 if (GET_CODE (XEXP (link, 0)) == USE)
443 for (i = 1; i < seq_size; i++)
445 rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i));
446 if (GET_CODE (slot_pat) == SET
447 && rtx_equal_p (SET_DEST (slot_pat),
448 SET_DEST (XEXP (link, 0))))
452 mark_referenced_resources (SET_DEST (XEXP (link, 0)),
458 /* ... fall through to other INSN processing ... */
463 #ifdef INSN_REFERENCES_ARE_DELAYED
464 if (! include_delayed_effects
465 && INSN_REFERENCES_ARE_DELAYED (x))
469 /* No special processing, just speed up. */
470 mark_referenced_resources (PATTERN (x), res, include_delayed_effects);
477 /* Process each sub-expression and flag what it needs. */
478 format_ptr = GET_RTX_FORMAT (code);
479 for (i = 0; i < GET_RTX_LENGTH (code); i++)
480 switch (*format_ptr++)
483 mark_referenced_resources (XEXP (x, i), res, include_delayed_effects);
487 for (j = 0; j < XVECLEN (x, i); j++)
488 mark_referenced_resources (XVECEXP (x, i, j), res,
489 include_delayed_effects);
494 /* Given X, a part of an insn, and a pointer to a `struct resource',
495 RES, indicate which resources are modified by the insn. If
496 INCLUDE_DELAYED_EFFECTS is nonzero, also mark resources potentially
497 set by the called routine.
499 If IN_DEST is nonzero, it means we are inside a SET. Otherwise,
500 objects are being referenced instead of set.
502 We never mark the insn as modifying the condition code unless it explicitly
503 SETs CC0 even though this is not totally correct. The reason for this is
504 that we require a SET of CC0 to immediately precede the reference to CC0.
505 So if some other insn sets CC0 as a side-effect, we know it cannot affect
506 our computation and thus may be placed in a delay slot. */
509 mark_set_resources (x, res, in_dest, include_delayed_effects)
511 register struct resources *res;
513 int include_delayed_effects;
515 register enum rtx_code code;
517 register char *format_ptr;
535 /* These don't set any resources. */
544 /* Called routine modifies the condition code, memory, any registers
545 that aren't saved across calls, global registers and anything
546 explicitly CLOBBERed immediately after the CALL_INSN. */
548 if (include_delayed_effects)
550 rtx next = NEXT_INSN (x);
551 rtx prev = PREV_INSN (x);
554 res->cc = res->memory = 1;
555 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
556 if (call_used_regs[i] || global_regs[i])
557 SET_HARD_REG_BIT (res->regs, i);
559 /* If X is part of a delay slot sequence, then NEXT should be
560 the first insn after the sequence. */
561 if (NEXT_INSN (prev) != x)
562 next = NEXT_INSN (NEXT_INSN (prev));
564 for (link = CALL_INSN_FUNCTION_USAGE (x);
565 link; link = XEXP (link, 1))
566 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
567 mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, 0);
569 /* Check for a NOTE_INSN_SETJMP. If it exists, then we must
570 assume that this call can clobber any register. */
571 if (next && GET_CODE (next) == NOTE
572 && NOTE_LINE_NUMBER (next) == NOTE_INSN_SETJMP)
573 SET_HARD_REG_SET (res->regs);
576 /* ... and also what it's RTL says it modifies, if anything. */
581 /* An insn consisting of just a CLOBBER (or USE) is just for flow
582 and doesn't actually do anything, so we ignore it. */
584 #ifdef INSN_SETS_ARE_DELAYED
585 if (! include_delayed_effects
586 && INSN_SETS_ARE_DELAYED (x))
591 if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER)
596 /* If the source of a SET is a CALL, this is actually done by
597 the called routine. So only include it if we are to include the
598 effects of the calling routine. */
600 mark_set_resources (SET_DEST (x), res,
601 (include_delayed_effects
602 || GET_CODE (SET_SRC (x)) != CALL),
605 mark_set_resources (SET_SRC (x), res, 0, 0);
609 mark_set_resources (XEXP (x, 0), res, 1, 0);
613 for (i = 0; i < XVECLEN (x, 0); i++)
614 if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0))
615 && INSN_FROM_TARGET_P (XVECEXP (x, 0, i))))
616 mark_set_resources (XVECEXP (x, 0, i), res, 0,
617 include_delayed_effects);
624 mark_set_resources (XEXP (x, 0), res, 1, 0);
628 mark_set_resources (XEXP (x, 0), res, in_dest, 0);
629 mark_set_resources (XEXP (x, 1), res, 0, 0);
630 mark_set_resources (XEXP (x, 2), res, 0, 0);
637 res->unch_memory = RTX_UNCHANGING_P (x);
638 res->volatil = MEM_VOLATILE_P (x);
641 mark_set_resources (XEXP (x, 0), res, 0, 0);
647 if (GET_CODE (SUBREG_REG (x)) != REG)
648 mark_set_resources (SUBREG_REG (x), res,
649 in_dest, include_delayed_effects);
652 int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
653 int last_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
654 for (i = regno; i < last_regno; i++)
655 SET_HARD_REG_BIT (res->regs, i);
662 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
663 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
670 /* Process each sub-expression and flag what it needs. */
671 format_ptr = GET_RTX_FORMAT (code);
672 for (i = 0; i < GET_RTX_LENGTH (code); i++)
673 switch (*format_ptr++)
676 mark_set_resources (XEXP (x, i), res, in_dest, include_delayed_effects);
680 for (j = 0; j < XVECLEN (x, i); j++)
681 mark_set_resources (XVECEXP (x, i, j), res, in_dest,
682 include_delayed_effects);
687 /* Return TRUE if this insn should stop the search for insn to fill delay
688 slots. LABELS_P indicates that labels should terminate the search.
689 In all cases, jumps terminate the search. */
692 stop_search_p (insn, labels_p)
699 switch (GET_CODE (insn))
713 /* OK unless it contains a delay slot or is an `asm' insn of some type.
714 We don't know anything about these. */
715 return (GET_CODE (PATTERN (insn)) == SEQUENCE
716 || GET_CODE (PATTERN (insn)) == ASM_INPUT
717 || asm_noperands (PATTERN (insn)) >= 0);
724 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
725 resource set contains a volatile memory reference. Otherwise, return FALSE. */
728 resource_conflicts_p (res1, res2)
729 struct resources *res1, *res2;
731 if ((res1->cc && res2->cc) || (res1->memory && res2->memory)
732 || (res1->unch_memory && res2->unch_memory)
733 || res1->volatil || res2->volatil)
737 return (res1->regs & res2->regs) != HARD_CONST (0);
742 for (i = 0; i < HARD_REG_SET_LONGS; i++)
743 if ((res1->regs[i] & res2->regs[i]) != 0)
750 /* Return TRUE if any resource marked in RES, a `struct resources', is
751 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
752 routine is using those resources.
754 We compute this by computing all the resources referenced by INSN and
755 seeing if this conflicts with RES. It might be faster to directly check
756 ourselves, and this is the way it used to work, but it means duplicating
757 a large block of complex code. */
760 insn_references_resource_p (insn, res, include_delayed_effects)
762 register struct resources *res;
763 int include_delayed_effects;
765 struct resources insn_res;
767 CLEAR_RESOURCE (&insn_res);
768 mark_referenced_resources (insn, &insn_res, include_delayed_effects);
769 return resource_conflicts_p (&insn_res, res);
772 /* Return TRUE if INSN modifies resources that are marked in RES.
773 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
774 included. CC0 is only modified if it is explicitly set; see comments
775 in front of mark_set_resources for details. */
778 insn_sets_resource_p (insn, res, include_delayed_effects)
780 register struct resources *res;
781 int include_delayed_effects;
783 struct resources insn_sets;
785 CLEAR_RESOURCE (&insn_sets);
786 mark_set_resources (insn, &insn_sets, 0, include_delayed_effects);
787 return resource_conflicts_p (&insn_sets, res);
790 /* Find a label at the end of the function or before a RETURN. If there is
798 /* If we found one previously, return it. */
799 if (end_of_function_label)
800 return end_of_function_label;
802 /* Otherwise, see if there is a label at the end of the function. If there
803 is, it must be that RETURN insns aren't needed, so that is our return
804 label and we don't have to do anything else. */
806 insn = get_last_insn ();
807 while (GET_CODE (insn) == NOTE
808 || (GET_CODE (insn) == INSN
809 && (GET_CODE (PATTERN (insn)) == USE
810 || GET_CODE (PATTERN (insn)) == CLOBBER)))
811 insn = PREV_INSN (insn);
813 /* When a target threads its epilogue we might already have a
814 suitable return insn. If so put a label before it for the
815 end_of_function_label. */
816 if (GET_CODE (insn) == BARRIER
817 && GET_CODE (PREV_INSN (insn)) == JUMP_INSN
818 && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN)
820 rtx temp = PREV_INSN (PREV_INSN (insn));
821 end_of_function_label = gen_label_rtx ();
822 LABEL_NUSES (end_of_function_label) = 0;
824 /* Put the label before an USE insns that may proceed the RETURN insn. */
825 while (GET_CODE (temp) == USE)
826 temp = PREV_INSN (temp);
828 emit_label_after (end_of_function_label, temp);
831 else if (GET_CODE (insn) == CODE_LABEL)
832 end_of_function_label = insn;
835 /* Otherwise, make a new label and emit a RETURN and BARRIER,
837 end_of_function_label = gen_label_rtx ();
838 LABEL_NUSES (end_of_function_label) = 0;
839 emit_label (end_of_function_label);
843 /* The return we make may have delay slots too. */
844 rtx insn = gen_return ();
845 insn = emit_jump_insn (insn);
847 if (num_delay_slots (insn) > 0)
848 obstack_ptr_grow (&unfilled_slots_obstack, insn);
853 /* Show one additional use for this label so it won't go away until
855 ++LABEL_NUSES (end_of_function_label);
857 return end_of_function_label;
860 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
861 the pattern of INSN with the SEQUENCE.
863 Chain the insns so that NEXT_INSN of each insn in the sequence points to
864 the next and NEXT_INSN of the last insn in the sequence points to
865 the first insn after the sequence. Similarly for PREV_INSN. This makes
866 it easier to scan all insns.
868 Returns the SEQUENCE that replaces INSN. */
871 emit_delay_sequence (insn, list, length)
880 /* Allocate the the rtvec to hold the insns and the SEQUENCE. */
881 rtvec seqv = rtvec_alloc (length + 1);
882 rtx seq = gen_rtx_SEQUENCE (VOIDmode, seqv);
883 rtx seq_insn = make_insn_raw (seq);
884 rtx first = get_insns ();
885 rtx last = get_last_insn ();
887 /* Make a copy of the insn having delay slots. */
888 rtx delay_insn = copy_rtx (insn);
890 /* If INSN is followed by a BARRIER, delete the BARRIER since it will only
891 confuse further processing. Update LAST in case it was the last insn.
892 We will put the BARRIER back in later. */
893 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == BARRIER)
895 delete_insn (NEXT_INSN (insn));
896 last = get_last_insn ();
900 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
901 NEXT_INSN (seq_insn) = NEXT_INSN (insn);
902 PREV_INSN (seq_insn) = PREV_INSN (insn);
905 PREV_INSN (NEXT_INSN (seq_insn)) = seq_insn;
908 NEXT_INSN (PREV_INSN (seq_insn)) = seq_insn;
910 /* Note the calls to set_new_first_and_last_insn must occur after
911 SEQ_INSN has been completely spliced into the insn stream.
913 Otherwise CUR_INSN_UID will get set to an incorrect value because
914 set_new_first_and_last_insn will not find SEQ_INSN in the chain. */
916 set_new_first_and_last_insn (first, seq_insn);
919 set_new_first_and_last_insn (seq_insn, last);
921 /* Build our SEQUENCE and rebuild the insn chain. */
922 XVECEXP (seq, 0, 0) = delay_insn;
923 INSN_DELETED_P (delay_insn) = 0;
924 PREV_INSN (delay_insn) = PREV_INSN (seq_insn);
926 for (li = list; li; li = XEXP (li, 1), i++)
928 rtx tem = XEXP (li, 0);
931 /* Show that this copy of the insn isn't deleted. */
932 INSN_DELETED_P (tem) = 0;
934 XVECEXP (seq, 0, i) = tem;
935 PREV_INSN (tem) = XVECEXP (seq, 0, i - 1);
936 NEXT_INSN (XVECEXP (seq, 0, i - 1)) = tem;
938 /* Remove any REG_DEAD notes because we can't rely on them now
939 that the insn has been moved. */
940 for (note = REG_NOTES (tem); note; note = XEXP (note, 1))
941 if (REG_NOTE_KIND (note) == REG_DEAD)
942 XEXP (note, 0) = const0_rtx;
945 NEXT_INSN (XVECEXP (seq, 0, length)) = NEXT_INSN (seq_insn);
947 /* If the previous insn is a SEQUENCE, update the NEXT_INSN pointer on the
948 last insn in that SEQUENCE to point to us. Similarly for the first
949 insn in the following insn if it is a SEQUENCE. */
951 if (PREV_INSN (seq_insn) && GET_CODE (PREV_INSN (seq_insn)) == INSN
952 && GET_CODE (PATTERN (PREV_INSN (seq_insn))) == SEQUENCE)
953 NEXT_INSN (XVECEXP (PATTERN (PREV_INSN (seq_insn)), 0,
954 XVECLEN (PATTERN (PREV_INSN (seq_insn)), 0) - 1))
957 if (NEXT_INSN (seq_insn) && GET_CODE (NEXT_INSN (seq_insn)) == INSN
958 && GET_CODE (PATTERN (NEXT_INSN (seq_insn))) == SEQUENCE)
959 PREV_INSN (XVECEXP (PATTERN (NEXT_INSN (seq_insn)), 0, 0)) = seq_insn;
961 /* If there used to be a BARRIER, put it back. */
963 emit_barrier_after (seq_insn);
971 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
972 be in the order in which the insns are to be executed. */
975 add_to_delay_list (insn, delay_list)
979 /* If we have an empty list, just make a new list element. If
980 INSN has it's block number recorded, clear it since we may
981 be moving the insn to a new block. */
985 struct target_info *tinfo;
987 for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME];
988 tinfo; tinfo = tinfo->next)
989 if (tinfo->uid == INSN_UID (insn))
995 return gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX);
998 /* Otherwise this must be an INSN_LIST. Add INSN to the end of the
1000 XEXP (delay_list, 1) = add_to_delay_list (insn, XEXP (delay_list, 1));
1005 /* Delete INSN from the the delay slot of the insn that it is in. This may
1006 produce an insn without anything in its delay slots. */
1009 delete_from_delay_slot (insn)
1012 rtx trial, seq_insn, seq, prev;
1016 /* We first must find the insn containing the SEQUENCE with INSN in its
1017 delay slot. Do this by finding an insn, TRIAL, where
1018 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
1021 PREV_INSN (NEXT_INSN (trial)) == trial;
1022 trial = NEXT_INSN (trial))
1025 seq_insn = PREV_INSN (NEXT_INSN (trial));
1026 seq = PATTERN (seq_insn);
1028 /* Create a delay list consisting of all the insns other than the one
1029 we are deleting (unless we were the only one). */
1030 if (XVECLEN (seq, 0) > 2)
1031 for (i = 1; i < XVECLEN (seq, 0); i++)
1032 if (XVECEXP (seq, 0, i) != insn)
1033 delay_list = add_to_delay_list (XVECEXP (seq, 0, i), delay_list);
1035 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
1036 list, and rebuild the delay list if non-empty. */
1037 prev = PREV_INSN (seq_insn);
1038 trial = XVECEXP (seq, 0, 0);
1039 delete_insn (seq_insn);
1040 add_insn_after (trial, prev);
1042 if (GET_CODE (trial) == JUMP_INSN
1043 && (simplejump_p (trial) || GET_CODE (PATTERN (trial)) == RETURN))
1044 emit_barrier_after (trial);
1046 /* If there are any delay insns, remit them. Otherwise clear the
1049 trial = emit_delay_sequence (trial, delay_list, XVECLEN (seq, 0) - 2);
1051 INSN_ANNULLED_BRANCH_P (trial) = 0;
1053 INSN_FROM_TARGET_P (insn) = 0;
1055 /* Show we need to fill this insn again. */
1056 obstack_ptr_grow (&unfilled_slots_obstack, trial);
1059 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
1060 the insn that sets CC0 for it and delete it too. */
1063 delete_scheduled_jump (insn)
1066 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
1067 delete the insn that sets the condition code, but it is hard to find it.
1068 Since this case is rare anyway, don't bother trying; there would likely
1069 be other insns that became dead anyway, which we wouldn't know to
1073 if (reg_mentioned_p (cc0_rtx, insn))
1075 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
1077 /* If a reg-note was found, it points to an insn to set CC0. This
1078 insn is in the delay list of some other insn. So delete it from
1079 the delay list it was in. */
1082 if (! FIND_REG_INC_NOTE (XEXP (note, 0), NULL_RTX)
1083 && sets_cc0_p (PATTERN (XEXP (note, 0))) == 1)
1084 delete_from_delay_slot (XEXP (note, 0));
1088 /* The insn setting CC0 is our previous insn, but it may be in
1089 a delay slot. It will be the last insn in the delay slot, if
1091 rtx trial = previous_insn (insn);
1092 if (GET_CODE (trial) == NOTE)
1093 trial = prev_nonnote_insn (trial);
1094 if (sets_cc0_p (PATTERN (trial)) != 1
1095 || FIND_REG_INC_NOTE (trial, 0))
1097 if (PREV_INSN (NEXT_INSN (trial)) == trial)
1098 delete_insn (trial);
1100 delete_from_delay_slot (trial);
1108 /* Counters for delay-slot filling. */
1110 #define NUM_REORG_FUNCTIONS 2
1111 #define MAX_DELAY_HISTOGRAM 3
1112 #define MAX_REORG_PASSES 2
1114 static int num_insns_needing_delays[NUM_REORG_FUNCTIONS][MAX_REORG_PASSES];
1116 static int num_filled_delays[NUM_REORG_FUNCTIONS][MAX_DELAY_HISTOGRAM+1][MAX_REORG_PASSES];
1118 static int reorg_pass_number;
1121 note_delay_statistics (slots_filled, index)
1122 int slots_filled, index;
1124 num_insns_needing_delays[index][reorg_pass_number]++;
1125 if (slots_filled > MAX_DELAY_HISTOGRAM)
1126 slots_filled = MAX_DELAY_HISTOGRAM;
1127 num_filled_delays[index][slots_filled][reorg_pass_number]++;
1130 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
1132 /* Optimize the following cases:
1134 1. When a conditional branch skips over only one instruction,
1135 use an annulling branch and put that insn in the delay slot.
1136 Use either a branch that annuls when the condition if true or
1137 invert the test with a branch that annuls when the condition is
1138 false. This saves insns, since otherwise we must copy an insn
1141 (orig) (skip) (otherwise)
1142 Bcc.n L1 Bcc',a L1 Bcc,a L1'
1149 2. When a conditional branch skips over only one instruction,
1150 and after that, it unconditionally branches somewhere else,
1151 perform the similar optimization. This saves executing the
1152 second branch in the case where the inverted condition is true.
1159 INSN is a JUMP_INSN.
1161 This should be expanded to skip over N insns, where N is the number
1162 of delay slots required. */
1165 optimize_skip (insn)
1168 register rtx trial = next_nonnote_insn (insn);
1169 rtx next_trial = next_active_insn (trial);
1174 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1177 || GET_CODE (trial) != INSN
1178 || GET_CODE (PATTERN (trial)) == SEQUENCE
1179 || recog_memoized (trial) < 0
1180 || (! eligible_for_annul_false (insn, 0, trial, flags)
1181 && ! eligible_for_annul_true (insn, 0, trial, flags)))
1184 /* There are two cases where we are just executing one insn (we assume
1185 here that a branch requires only one insn; this should be generalized
1186 at some point): Where the branch goes around a single insn or where
1187 we have one insn followed by a branch to the same label we branch to.
1188 In both of these cases, inverting the jump and annulling the delay
1189 slot give the same effect in fewer insns. */
1190 if ((next_trial == next_active_insn (JUMP_LABEL (insn)))
1192 && GET_CODE (next_trial) == JUMP_INSN
1193 && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)
1194 && (simplejump_p (next_trial)
1195 || GET_CODE (PATTERN (next_trial)) == RETURN)))
1197 if (eligible_for_annul_false (insn, 0, trial, flags))
1199 if (invert_jump (insn, JUMP_LABEL (insn)))
1200 INSN_FROM_TARGET_P (trial) = 1;
1201 else if (! eligible_for_annul_true (insn, 0, trial, flags))
1205 delay_list = add_to_delay_list (trial, NULL_RTX);
1206 next_trial = next_active_insn (trial);
1207 update_block (trial, trial);
1208 delete_insn (trial);
1210 /* Also, if we are targeting an unconditional
1211 branch, thread our jump to the target of that branch. Don't
1212 change this into a RETURN here, because it may not accept what
1213 we have in the delay slot. We'll fix this up later. */
1214 if (next_trial && GET_CODE (next_trial) == JUMP_INSN
1215 && (simplejump_p (next_trial)
1216 || GET_CODE (PATTERN (next_trial)) == RETURN))
1218 target_label = JUMP_LABEL (next_trial);
1219 if (target_label == 0)
1220 target_label = find_end_label ();
1222 /* Recompute the flags based on TARGET_LABEL since threading
1223 the jump to TARGET_LABEL may change the direction of the
1224 jump (which may change the circumstances in which the
1225 delay slot is nullified). */
1226 flags = get_jump_flags (insn, target_label);
1227 if (eligible_for_annul_true (insn, 0, trial, flags))
1228 reorg_redirect_jump (insn, target_label);
1231 INSN_ANNULLED_BRANCH_P (insn) = 1;
1239 /* Encode and return branch direction and prediction information for
1240 INSN assuming it will jump to LABEL.
1242 Non conditional branches return no direction information and
1243 are predicted as very likely taken. */
1246 get_jump_flags (insn, label)
1251 /* get_jump_flags can be passed any insn with delay slots, these may
1252 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
1253 direction information, and only if they are conditional jumps.
1255 If LABEL is zero, then there is no way to determine the branch
1257 if (GET_CODE (insn) == JUMP_INSN
1258 && (condjump_p (insn) || condjump_in_parallel_p (insn))
1259 && INSN_UID (insn) <= max_uid
1261 && INSN_UID (label) <= max_uid)
1263 = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)])
1264 ? ATTR_FLAG_forward : ATTR_FLAG_backward;
1265 /* No valid direction information. */
1269 /* If insn is a conditional branch call mostly_true_jump to get
1270 determine the branch prediction.
1272 Non conditional branches are predicted as very likely taken. */
1273 if (GET_CODE (insn) == JUMP_INSN
1274 && (condjump_p (insn) || condjump_in_parallel_p (insn)))
1278 prediction = mostly_true_jump (insn, get_branch_condition (insn, label));
1282 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1285 flags |= ATTR_FLAG_likely;
1288 flags |= ATTR_FLAG_unlikely;
1291 flags |= (ATTR_FLAG_very_unlikely | ATTR_FLAG_unlikely);
1299 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1304 /* Return 1 if INSN is a destination that will be branched to rarely (the
1305 return point of a function); return 2 if DEST will be branched to very
1306 rarely (a call to a function that doesn't return). Otherwise,
1310 rare_destination (insn)
1316 for (; insn; insn = next)
1318 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
1319 insn = XVECEXP (PATTERN (insn), 0, 0);
1321 next = NEXT_INSN (insn);
1323 switch (GET_CODE (insn))
1328 /* A BARRIER can either be after a JUMP_INSN or a CALL_INSN. We
1329 don't scan past JUMP_INSNs, so any barrier we find here must
1330 have been after a CALL_INSN and hence mean the call doesn't
1334 if (GET_CODE (PATTERN (insn)) == RETURN)
1336 else if (simplejump_p (insn)
1337 && jump_count++ < 10)
1338 next = JUMP_LABEL (insn);
1347 /* If we got here it means we hit the end of the function. So this
1348 is an unlikely destination. */
1353 /* Return truth value of the statement that this branch
1354 is mostly taken. If we think that the branch is extremely likely
1355 to be taken, we return 2. If the branch is slightly more likely to be
1356 taken, return 1. If the branch is slightly less likely to be taken,
1357 return 0 and if the branch is highly unlikely to be taken, return -1.
1359 CONDITION, if non-zero, is the condition that JUMP_INSN is testing. */
1362 mostly_true_jump (jump_insn, condition)
1363 rtx jump_insn, condition;
1365 rtx target_label = JUMP_LABEL (jump_insn);
1367 int rare_dest = rare_destination (target_label);
1368 int rare_fallthrough = rare_destination (NEXT_INSN (jump_insn));
1370 /* If branch probabilities are available, then use that number since it
1371 always gives a correct answer. */
1372 if (flag_branch_probabilities)
1374 rtx note = find_reg_note (jump_insn, REG_BR_PROB, 0);;
1377 int prob = XINT (note, 0);
1379 if (prob >= REG_BR_PROB_BASE * 9 / 10)
1381 else if (prob >= REG_BR_PROB_BASE / 2)
1383 else if (prob >= REG_BR_PROB_BASE / 10)
1390 /* If this is a branch outside a loop, it is highly unlikely. */
1391 if (GET_CODE (PATTERN (jump_insn)) == SET
1392 && GET_CODE (SET_SRC (PATTERN (jump_insn))) == IF_THEN_ELSE
1393 && ((GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 1)) == LABEL_REF
1394 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 1)))
1395 || (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 2)) == LABEL_REF
1396 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 2)))))
1401 /* If this is the test of a loop, it is very likely true. We scan
1402 backwards from the target label. If we find a NOTE_INSN_LOOP_BEG
1403 before the next real insn, we assume the branch is to the top of
1405 for (insn = PREV_INSN (target_label);
1406 insn && GET_CODE (insn) == NOTE;
1407 insn = PREV_INSN (insn))
1408 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1411 /* If this is a jump to the test of a loop, it is likely true. We scan
1412 forwards from the target label. If we find a NOTE_INSN_LOOP_VTOP
1413 before the next real insn, we assume the branch is to the loop branch
1415 for (insn = NEXT_INSN (target_label);
1416 insn && GET_CODE (insn) == NOTE;
1417 insn = PREV_INSN (insn))
1418 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_VTOP)
1422 /* Look at the relative rarities of the fallthrough and destination. If
1423 they differ, we can predict the branch that way. */
1425 switch (rare_fallthrough - rare_dest)
1439 /* If we couldn't figure out what this jump was, assume it won't be
1440 taken. This should be rare. */
1444 /* EQ tests are usually false and NE tests are usually true. Also,
1445 most quantities are positive, so we can make the appropriate guesses
1446 about signed comparisons against zero. */
1447 switch (GET_CODE (condition))
1450 /* Unconditional branch. */
1458 if (XEXP (condition, 1) == const0_rtx)
1463 if (XEXP (condition, 1) == const0_rtx)
1471 /* Predict backward branches usually take, forward branches usually not. If
1472 we don't know whether this is forward or backward, assume the branch
1473 will be taken, since most are. */
1474 return (target_label == 0 || INSN_UID (jump_insn) > max_uid
1475 || INSN_UID (target_label) > max_uid
1476 || (uid_to_ruid[INSN_UID (jump_insn)]
1477 > uid_to_ruid[INSN_UID (target_label)]));;
1480 /* Return the condition under which INSN will branch to TARGET. If TARGET
1481 is zero, return the condition under which INSN will return. If INSN is
1482 an unconditional branch, return const_true_rtx. If INSN isn't a simple
1483 type of jump, or it doesn't go to TARGET, return 0. */
1486 get_branch_condition (insn, target)
1490 rtx pat = PATTERN (insn);
1493 if (condjump_in_parallel_p (insn))
1494 pat = XVECEXP (pat, 0, 0);
1496 if (GET_CODE (pat) == RETURN)
1497 return target == 0 ? const_true_rtx : 0;
1499 else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
1502 src = SET_SRC (pat);
1503 if (GET_CODE (src) == LABEL_REF && XEXP (src, 0) == target)
1504 return const_true_rtx;
1506 else if (GET_CODE (src) == IF_THEN_ELSE
1507 && ((target == 0 && GET_CODE (XEXP (src, 1)) == RETURN)
1508 || (GET_CODE (XEXP (src, 1)) == LABEL_REF
1509 && XEXP (XEXP (src, 1), 0) == target))
1510 && XEXP (src, 2) == pc_rtx)
1511 return XEXP (src, 0);
1513 else if (GET_CODE (src) == IF_THEN_ELSE
1514 && ((target == 0 && GET_CODE (XEXP (src, 2)) == RETURN)
1515 || (GET_CODE (XEXP (src, 2)) == LABEL_REF
1516 && XEXP (XEXP (src, 2), 0) == target))
1517 && XEXP (src, 1) == pc_rtx)
1518 return gen_rtx_fmt_ee (reverse_condition (GET_CODE (XEXP (src, 0))),
1519 GET_MODE (XEXP (src, 0)),
1520 XEXP (XEXP (src, 0), 0), XEXP (XEXP (src, 0), 1));
1525 /* Return non-zero if CONDITION is more strict than the condition of
1526 INSN, i.e., if INSN will always branch if CONDITION is true. */
1529 condition_dominates_p (condition, insn)
1533 rtx other_condition = get_branch_condition (insn, JUMP_LABEL (insn));
1534 enum rtx_code code = GET_CODE (condition);
1535 enum rtx_code other_code;
1537 if (rtx_equal_p (condition, other_condition)
1538 || other_condition == const_true_rtx)
1541 else if (condition == const_true_rtx || other_condition == 0)
1544 other_code = GET_CODE (other_condition);
1545 if (GET_RTX_LENGTH (code) != 2 || GET_RTX_LENGTH (other_code) != 2
1546 || ! rtx_equal_p (XEXP (condition, 0), XEXP (other_condition, 0))
1547 || ! rtx_equal_p (XEXP (condition, 1), XEXP (other_condition, 1)))
1550 return comparison_dominates_p (code, other_code);
1553 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1554 any insns already in the delay slot of JUMP. */
1557 redirect_with_delay_slots_safe_p (jump, newlabel, seq)
1558 rtx jump, newlabel, seq;
1561 rtx pat = PATTERN (seq);
1563 /* Make sure all the delay slots of this jump would still
1564 be valid after threading the jump. If they are still
1565 valid, then return non-zero. */
1567 flags = get_jump_flags (jump, newlabel);
1568 for (i = 1; i < XVECLEN (pat, 0); i++)
1570 #ifdef ANNUL_IFFALSE_SLOTS
1571 (INSN_ANNULLED_BRANCH_P (jump)
1572 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1573 ? eligible_for_annul_false (jump, i - 1,
1574 XVECEXP (pat, 0, i), flags) :
1576 #ifdef ANNUL_IFTRUE_SLOTS
1577 (INSN_ANNULLED_BRANCH_P (jump)
1578 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1579 ? eligible_for_annul_true (jump, i - 1,
1580 XVECEXP (pat, 0, i), flags) :
1582 eligible_for_delay (jump, i -1, XVECEXP (pat, 0, i), flags)))
1585 return (i == XVECLEN (pat, 0));
1588 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1589 any insns we wish to place in the delay slot of JUMP. */
1592 redirect_with_delay_list_safe_p (jump, newlabel, delay_list)
1593 rtx jump, newlabel, delay_list;
1598 /* Make sure all the insns in DELAY_LIST would still be
1599 valid after threading the jump. If they are still
1600 valid, then return non-zero. */
1602 flags = get_jump_flags (jump, newlabel);
1603 for (li = delay_list, i = 0; li; li = XEXP (li, 1), i++)
1605 #ifdef ANNUL_IFFALSE_SLOTS
1606 (INSN_ANNULLED_BRANCH_P (jump)
1607 && INSN_FROM_TARGET_P (XEXP (li, 0)))
1608 ? eligible_for_annul_false (jump, i, XEXP (li, 0), flags) :
1610 #ifdef ANNUL_IFTRUE_SLOTS
1611 (INSN_ANNULLED_BRANCH_P (jump)
1612 && ! INSN_FROM_TARGET_P (XEXP (li, 0)))
1613 ? eligible_for_annul_true (jump, i, XEXP (li, 0), flags) :
1615 eligible_for_delay (jump, i, XEXP (li, 0), flags)))
1618 return (li == NULL);
1622 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1623 the condition tested by INSN is CONDITION and the resources shown in
1624 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1625 from SEQ's delay list, in addition to whatever insns it may execute
1626 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1627 needed while searching for delay slot insns. Return the concatenated
1628 delay list if possible, otherwise, return 0.
1630 SLOTS_TO_FILL is the total number of slots required by INSN, and
1631 PSLOTS_FILLED points to the number filled so far (also the number of
1632 insns in DELAY_LIST). It is updated with the number that have been
1633 filled from the SEQUENCE, if any.
1635 PANNUL_P points to a non-zero value if we already know that we need
1636 to annul INSN. If this routine determines that annulling is needed,
1637 it may set that value non-zero.
1639 PNEW_THREAD points to a location that is to receive the place at which
1640 execution should continue. */
1643 steal_delay_list_from_target (insn, condition, seq, delay_list,
1644 sets, needed, other_needed,
1645 slots_to_fill, pslots_filled, pannul_p,
1647 rtx insn, condition;
1650 struct resources *sets, *needed, *other_needed;
1657 int slots_remaining = slots_to_fill - *pslots_filled;
1658 int total_slots_filled = *pslots_filled;
1659 rtx new_delay_list = 0;
1660 int must_annul = *pannul_p;
1663 /* We can't do anything if there are more delay slots in SEQ than we
1664 can handle, or if we don't know that it will be a taken branch.
1665 We know that it will be a taken branch if it is either an unconditional
1666 branch or a conditional branch with a stricter branch condition.
1668 Also, exit if the branch has more than one set, since then it is computing
1669 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1670 ??? It may be possible to move other sets into INSN in addition to
1671 moving the instructions in the delay slots. */
1673 if (XVECLEN (seq, 0) - 1 > slots_remaining
1674 || ! condition_dominates_p (condition, XVECEXP (seq, 0, 0))
1675 || ! single_set (XVECEXP (seq, 0, 0)))
1678 for (i = 1; i < XVECLEN (seq, 0); i++)
1680 rtx trial = XVECEXP (seq, 0, i);
1683 if (insn_references_resource_p (trial, sets, 0)
1684 || insn_sets_resource_p (trial, needed, 0)
1685 || insn_sets_resource_p (trial, sets, 0)
1687 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1689 || find_reg_note (trial, REG_CC_USER, NULL_RTX)
1691 /* If TRIAL is from the fallthrough code of an annulled branch insn
1692 in SEQ, we cannot use it. */
1693 || (INSN_ANNULLED_BRANCH_P (XVECEXP (seq, 0, 0))
1694 && ! INSN_FROM_TARGET_P (trial)))
1697 /* If this insn was already done (usually in a previous delay slot),
1698 pretend we put it in our delay slot. */
1699 if (redundant_insn (trial, insn, new_delay_list))
1702 /* We will end up re-vectoring this branch, so compute flags
1703 based on jumping to the new label. */
1704 flags = get_jump_flags (insn, JUMP_LABEL (XVECEXP (seq, 0, 0)));
1707 && ((condition == const_true_rtx
1708 || (! insn_sets_resource_p (trial, other_needed, 0)
1709 && ! may_trap_p (PATTERN (trial)))))
1710 ? eligible_for_delay (insn, total_slots_filled, trial, flags)
1712 eligible_for_annul_false (insn, total_slots_filled, trial, flags)))
1714 temp = copy_rtx (trial);
1715 INSN_FROM_TARGET_P (temp) = 1;
1716 new_delay_list = add_to_delay_list (temp, new_delay_list);
1717 total_slots_filled++;
1719 if (--slots_remaining == 0)
1726 /* Show the place to which we will be branching. */
1727 *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));
1729 /* Add any new insns to the delay list and update the count of the
1730 number of slots filled. */
1731 *pslots_filled = total_slots_filled;
1732 *pannul_p = must_annul;
1734 if (delay_list == 0)
1735 return new_delay_list;
1737 for (temp = new_delay_list; temp; temp = XEXP (temp, 1))
1738 delay_list = add_to_delay_list (XEXP (temp, 0), delay_list);
1743 /* Similar to steal_delay_list_from_target except that SEQ is on the
1744 fallthrough path of INSN. Here we only do something if the delay insn
1745 of SEQ is an unconditional branch. In that case we steal its delay slot
1746 for INSN since unconditional branches are much easier to fill. */
1749 steal_delay_list_from_fallthrough (insn, condition, seq,
1750 delay_list, sets, needed, other_needed,
1751 slots_to_fill, pslots_filled, pannul_p)
1752 rtx insn, condition;
1755 struct resources *sets, *needed, *other_needed;
1763 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1765 /* We can't do anything if SEQ's delay insn isn't an
1766 unconditional branch. */
1768 if (! simplejump_p (XVECEXP (seq, 0, 0))
1769 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN)
1772 for (i = 1; i < XVECLEN (seq, 0); i++)
1774 rtx trial = XVECEXP (seq, 0, i);
1776 /* If TRIAL sets CC0, stealing it will move it too far from the use
1778 if (insn_references_resource_p (trial, sets, 0)
1779 || insn_sets_resource_p (trial, needed, 0)
1780 || insn_sets_resource_p (trial, sets, 0)
1782 || sets_cc0_p (PATTERN (trial))
1788 /* If this insn was already done, we don't need it. */
1789 if (redundant_insn (trial, insn, delay_list))
1791 delete_from_delay_slot (trial);
1796 && ((condition == const_true_rtx
1797 || (! insn_sets_resource_p (trial, other_needed, 0)
1798 && ! may_trap_p (PATTERN (trial)))))
1799 ? eligible_for_delay (insn, *pslots_filled, trial, flags)
1801 eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
1803 delete_from_delay_slot (trial);
1804 delay_list = add_to_delay_list (trial, delay_list);
1806 if (++(*pslots_filled) == slots_to_fill)
1816 /* Try merging insns starting at THREAD which match exactly the insns in
1819 If all insns were matched and the insn was previously annulling, the
1820 annul bit will be cleared.
1822 For each insn that is merged, if the branch is or will be non-annulling,
1823 we delete the merged insn. */
1826 try_merge_delay_insns (insn, thread)
1829 rtx trial, next_trial;
1830 rtx delay_insn = XVECEXP (PATTERN (insn), 0, 0);
1831 int annul_p = INSN_ANNULLED_BRANCH_P (delay_insn);
1832 int slot_number = 1;
1833 int num_slots = XVECLEN (PATTERN (insn), 0);
1834 rtx next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1835 struct resources set, needed;
1836 rtx merged_insns = 0;
1840 flags = get_jump_flags (delay_insn, JUMP_LABEL (delay_insn));
1842 CLEAR_RESOURCE (&needed);
1843 CLEAR_RESOURCE (&set);
1845 /* If this is not an annulling branch, take into account anything needed in
1846 NEXT_TO_MATCH. This prevents two increments from being incorrectly
1847 folded into one. If we are annulling, this would be the correct
1848 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1849 will essentially disable this optimization. This method is somewhat of
1850 a kludge, but I don't see a better way.) */
1852 mark_referenced_resources (next_to_match, &needed, 1);
1854 for (trial = thread; !stop_search_p (trial, 1); trial = next_trial)
1856 rtx pat = PATTERN (trial);
1857 rtx oldtrial = trial;
1859 next_trial = next_nonnote_insn (trial);
1861 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1862 if (GET_CODE (trial) == INSN
1863 && (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER))
1866 if (GET_CODE (next_to_match) == GET_CODE (trial)
1868 /* We can't share an insn that sets cc0. */
1869 && ! sets_cc0_p (pat)
1871 && ! insn_references_resource_p (trial, &set, 1)
1872 && ! insn_sets_resource_p (trial, &set, 1)
1873 && ! insn_sets_resource_p (trial, &needed, 1)
1874 && (trial = try_split (pat, trial, 0)) != 0
1875 /* Update next_trial, in case try_split succeeded. */
1876 && (next_trial = next_nonnote_insn (trial))
1877 /* Likewise THREAD. */
1878 && (thread = oldtrial == thread ? trial : thread)
1879 && rtx_equal_p (PATTERN (next_to_match), PATTERN (trial))
1880 /* Have to test this condition if annul condition is different
1881 from (and less restrictive than) non-annulling one. */
1882 && eligible_for_delay (delay_insn, slot_number - 1, trial, flags))
1887 update_block (trial, thread);
1888 if (trial == thread)
1889 thread = next_active_insn (thread);
1891 delete_insn (trial);
1892 INSN_FROM_TARGET_P (next_to_match) = 0;
1895 merged_insns = gen_rtx_INSN_LIST (VOIDmode, trial, merged_insns);
1897 if (++slot_number == num_slots)
1900 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1902 mark_referenced_resources (next_to_match, &needed, 1);
1905 mark_set_resources (trial, &set, 0, 1);
1906 mark_referenced_resources (trial, &needed, 1);
1909 /* See if we stopped on a filled insn. If we did, try to see if its
1910 delay slots match. */
1911 if (slot_number != num_slots
1912 && trial && GET_CODE (trial) == INSN
1913 && GET_CODE (PATTERN (trial)) == SEQUENCE
1914 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (PATTERN (trial), 0, 0)))
1916 rtx pat = PATTERN (trial);
1917 rtx filled_insn = XVECEXP (pat, 0, 0);
1919 /* Account for resources set/needed by the filled insn. */
1920 mark_set_resources (filled_insn, &set, 0, 1);
1921 mark_referenced_resources (filled_insn, &needed, 1);
1923 for (i = 1; i < XVECLEN (pat, 0); i++)
1925 rtx dtrial = XVECEXP (pat, 0, i);
1927 if (! insn_references_resource_p (dtrial, &set, 1)
1928 && ! insn_sets_resource_p (dtrial, &set, 1)
1929 && ! insn_sets_resource_p (dtrial, &needed, 1)
1931 && ! sets_cc0_p (PATTERN (dtrial))
1933 && rtx_equal_p (PATTERN (next_to_match), PATTERN (dtrial))
1934 && eligible_for_delay (delay_insn, slot_number - 1, dtrial, flags))
1938 update_block (dtrial, thread);
1939 delete_from_delay_slot (dtrial);
1940 INSN_FROM_TARGET_P (next_to_match) = 0;
1943 merged_insns = gen_rtx_INSN_LIST (SImode, dtrial,
1946 if (++slot_number == num_slots)
1949 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1954 /* If all insns in the delay slot have been matched and we were previously
1955 annulling the branch, we need not any more. In that case delete all the
1956 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn the
1957 the delay list so that we know that it isn't only being used at the
1959 if (slot_number == num_slots && annul_p)
1961 for (; merged_insns; merged_insns = XEXP (merged_insns, 1))
1963 if (GET_MODE (merged_insns) == SImode)
1965 update_block (XEXP (merged_insns, 0), thread);
1966 delete_from_delay_slot (XEXP (merged_insns, 0));
1970 update_block (XEXP (merged_insns, 0), thread);
1971 delete_insn (XEXP (merged_insns, 0));
1975 INSN_ANNULLED_BRANCH_P (delay_insn) = 0;
1977 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1978 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) = 0;
1982 /* See if INSN is redundant with an insn in front of TARGET. Often this
1983 is called when INSN is a candidate for a delay slot of TARGET.
1984 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1985 of INSN. Often INSN will be redundant with an insn in a delay slot of
1986 some previous insn. This happens when we have a series of branches to the
1987 same label; in that case the first insn at the target might want to go
1988 into each of the delay slots.
1990 If we are not careful, this routine can take up a significant fraction
1991 of the total compilation time (4%), but only wins rarely. Hence we
1992 speed this routine up by making two passes. The first pass goes back
1993 until it hits a label and sees if it find an insn with an identical
1994 pattern. Only in this (relatively rare) event does it check for
1997 We do not split insns we encounter. This could cause us not to find a
1998 redundant insn, but the cost of splitting seems greater than the possible
1999 gain in rare cases. */
2002 redundant_insn (insn, target, delay_list)
2007 rtx target_main = target;
2008 rtx ipat = PATTERN (insn);
2010 struct resources needed, set;
2013 /* If INSN has any REG_UNUSED notes, it can't match anything since we
2014 are allowed to not actually assign to such a register. */
2015 if (find_reg_note (insn, REG_UNUSED, NULL_RTX) != 0)
2018 /* Scan backwards looking for a match. */
2019 for (trial = PREV_INSN (target); trial; trial = PREV_INSN (trial))
2021 if (GET_CODE (trial) == CODE_LABEL)
2024 if (GET_RTX_CLASS (GET_CODE (trial)) != 'i')
2027 pat = PATTERN (trial);
2028 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2031 if (GET_CODE (pat) == SEQUENCE)
2033 /* Stop for a CALL and its delay slots because it is difficult to
2034 track its resource needs correctly. */
2035 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
2038 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
2039 slots because it is difficult to track its resource needs
2042 #ifdef INSN_SETS_ARE_DELAYED
2043 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2047 #ifdef INSN_REFERENCES_ARE_DELAYED
2048 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2052 /* See if any of the insns in the delay slot match, updating
2053 resource requirements as we go. */
2054 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
2055 if (GET_CODE (XVECEXP (pat, 0, i)) == GET_CODE (insn)
2056 && rtx_equal_p (PATTERN (XVECEXP (pat, 0, i)), ipat)
2057 && ! find_reg_note (XVECEXP (pat, 0, i), REG_UNUSED, NULL_RTX))
2060 /* If found a match, exit this loop early. */
2065 else if (GET_CODE (trial) == GET_CODE (insn) && rtx_equal_p (pat, ipat)
2066 && ! find_reg_note (trial, REG_UNUSED, NULL_RTX))
2070 /* If we didn't find an insn that matches, return 0. */
2074 /* See what resources this insn sets and needs. If they overlap, or
2075 if this insn references CC0, it can't be redundant. */
2077 CLEAR_RESOURCE (&needed);
2078 CLEAR_RESOURCE (&set);
2079 mark_set_resources (insn, &set, 0, 1);
2080 mark_referenced_resources (insn, &needed, 1);
2082 /* If TARGET is a SEQUENCE, get the main insn. */
2083 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
2084 target_main = XVECEXP (PATTERN (target), 0, 0);
2086 if (resource_conflicts_p (&needed, &set)
2088 || reg_mentioned_p (cc0_rtx, ipat)
2090 /* The insn requiring the delay may not set anything needed or set by
2092 || insn_sets_resource_p (target_main, &needed, 1)
2093 || insn_sets_resource_p (target_main, &set, 1))
2096 /* Insns we pass may not set either NEEDED or SET, so merge them for
2098 needed.memory |= set.memory;
2099 needed.unch_memory |= set.unch_memory;
2100 IOR_HARD_REG_SET (needed.regs, set.regs);
2102 /* This insn isn't redundant if it conflicts with an insn that either is
2103 or will be in a delay slot of TARGET. */
2107 if (insn_sets_resource_p (XEXP (delay_list, 0), &needed, 1))
2109 delay_list = XEXP (delay_list, 1);
2112 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
2113 for (i = 1; i < XVECLEN (PATTERN (target), 0); i++)
2114 if (insn_sets_resource_p (XVECEXP (PATTERN (target), 0, i), &needed, 1))
2117 /* Scan backwards until we reach a label or an insn that uses something
2118 INSN sets or sets something insn uses or sets. */
2120 for (trial = PREV_INSN (target);
2121 trial && GET_CODE (trial) != CODE_LABEL;
2122 trial = PREV_INSN (trial))
2124 if (GET_CODE (trial) != INSN && GET_CODE (trial) != CALL_INSN
2125 && GET_CODE (trial) != JUMP_INSN)
2128 pat = PATTERN (trial);
2129 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2132 if (GET_CODE (pat) == SEQUENCE)
2134 /* If this is a CALL_INSN and its delay slots, it is hard to track
2135 the resource needs properly, so give up. */
2136 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
2139 /* If this this is an INSN or JUMP_INSN with delayed effects, it
2140 is hard to track the resource needs properly, so give up. */
2142 #ifdef INSN_SETS_ARE_DELAYED
2143 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2147 #ifdef INSN_REFERENCES_ARE_DELAYED
2148 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2152 /* See if any of the insns in the delay slot match, updating
2153 resource requirements as we go. */
2154 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
2156 rtx candidate = XVECEXP (pat, 0, i);
2158 /* If an insn will be annulled if the branch is false, it isn't
2159 considered as a possible duplicate insn. */
2160 if (rtx_equal_p (PATTERN (candidate), ipat)
2161 && ! (INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2162 && INSN_FROM_TARGET_P (candidate)))
2164 /* Show that this insn will be used in the sequel. */
2165 INSN_FROM_TARGET_P (candidate) = 0;
2169 /* Unless this is an annulled insn from the target of a branch,
2170 we must stop if it sets anything needed or set by INSN. */
2171 if ((! INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2172 || ! INSN_FROM_TARGET_P (candidate))
2173 && insn_sets_resource_p (candidate, &needed, 1))
2178 /* If the insn requiring the delay slot conflicts with INSN, we
2180 if (insn_sets_resource_p (XVECEXP (pat, 0, 0), &needed, 1))
2185 /* See if TRIAL is the same as INSN. */
2186 pat = PATTERN (trial);
2187 if (rtx_equal_p (pat, ipat))
2190 /* Can't go any further if TRIAL conflicts with INSN. */
2191 if (insn_sets_resource_p (trial, &needed, 1))
2199 /* Return 1 if THREAD can only be executed in one way. If LABEL is non-zero,
2200 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
2201 is non-zero, we are allowed to fall into this thread; otherwise, we are
2204 If LABEL is used more than one or we pass a label other than LABEL before
2205 finding an active insn, we do not own this thread. */
2208 own_thread_p (thread, label, allow_fallthrough)
2211 int allow_fallthrough;
2216 /* We don't own the function end. */
2220 /* Get the first active insn, or THREAD, if it is an active insn. */
2221 active_insn = next_active_insn (PREV_INSN (thread));
2223 for (insn = thread; insn != active_insn; insn = NEXT_INSN (insn))
2224 if (GET_CODE (insn) == CODE_LABEL
2225 && (insn != label || LABEL_NUSES (insn) != 1))
2228 if (allow_fallthrough)
2231 /* Ensure that we reach a BARRIER before any insn or label. */
2232 for (insn = prev_nonnote_insn (thread);
2233 insn == 0 || GET_CODE (insn) != BARRIER;
2234 insn = prev_nonnote_insn (insn))
2236 || GET_CODE (insn) == CODE_LABEL
2237 || (GET_CODE (insn) == INSN
2238 && GET_CODE (PATTERN (insn)) != USE
2239 && GET_CODE (PATTERN (insn)) != CLOBBER))
2245 /* Find the number of the basic block that starts closest to INSN. Return -1
2246 if we couldn't find such a basic block. */
2249 find_basic_block (insn)
2254 /* Scan backwards to the previous BARRIER. Then see if we can find a
2255 label that starts a basic block. Return the basic block number. */
2257 for (insn = prev_nonnote_insn (insn);
2258 insn && GET_CODE (insn) != BARRIER;
2259 insn = prev_nonnote_insn (insn))
2262 /* The start of the function is basic block zero. */
2266 /* See if any of the upcoming CODE_LABELs start a basic block. If we reach
2267 anything other than a CODE_LABEL or note, we can't find this code. */
2268 for (insn = next_nonnote_insn (insn);
2269 insn && GET_CODE (insn) == CODE_LABEL;
2270 insn = next_nonnote_insn (insn))
2272 for (i = 0; i < n_basic_blocks; i++)
2273 if (insn == basic_block_head[i])
2280 /* Called when INSN is being moved from a location near the target of a jump.
2281 We leave a marker of the form (use (INSN)) immediately in front
2282 of WHERE for mark_target_live_regs. These markers will be deleted when
2285 We used to try to update the live status of registers if WHERE is at
2286 the start of a basic block, but that can't work since we may remove a
2287 BARRIER in relax_delay_slots. */
2290 update_block (insn, where)
2296 /* Ignore if this was in a delay slot and it came from the target of
2298 if (INSN_FROM_TARGET_P (insn))
2301 emit_insn_before (gen_rtx_USE (VOIDmode, insn), where);
2303 /* INSN might be making a value live in a block where it didn't use to
2304 be. So recompute liveness information for this block. */
2306 b = find_basic_block (insn);
2311 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
2312 the basic block containing the jump. */
2315 reorg_redirect_jump (jump, nlabel)
2319 int b = find_basic_block (jump);
2324 return redirect_jump (jump, nlabel);
2327 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
2328 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
2329 that reference values used in INSN. If we find one, then we move the
2330 REG_DEAD note to INSN.
2332 This is needed to handle the case where an later insn (after INSN) has a
2333 REG_DEAD note for a register used by INSN, and this later insn subsequently
2334 gets moved before a CODE_LABEL because it is a redundant insn. In this
2335 case, mark_target_live_regs may be confused into thinking the register
2336 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
2339 update_reg_dead_notes (insn, delayed_insn)
2340 rtx insn, delayed_insn;
2344 for (p = next_nonnote_insn (insn); p != delayed_insn;
2345 p = next_nonnote_insn (p))
2346 for (link = REG_NOTES (p); link; link = next)
2348 next = XEXP (link, 1);
2350 if (REG_NOTE_KIND (link) != REG_DEAD
2351 || GET_CODE (XEXP (link, 0)) != REG)
2354 if (reg_referenced_p (XEXP (link, 0), PATTERN (insn)))
2356 /* Move the REG_DEAD note from P to INSN. */
2357 remove_note (p, link);
2358 XEXP (link, 1) = REG_NOTES (insn);
2359 REG_NOTES (insn) = link;
2364 /* Called when an insn redundant with start_insn is deleted. If there
2365 is a REG_DEAD note for the target of start_insn between start_insn
2366 and stop_insn, then the REG_DEAD note needs to be deleted since the
2367 value no longer dies there.
2369 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
2370 confused into thinking the register is dead. */
2373 fix_reg_dead_note (start_insn, stop_insn)
2374 rtx start_insn, stop_insn;
2378 for (p = next_nonnote_insn (start_insn); p != stop_insn;
2379 p = next_nonnote_insn (p))
2380 for (link = REG_NOTES (p); link; link = next)
2382 next = XEXP (link, 1);
2384 if (REG_NOTE_KIND (link) != REG_DEAD
2385 || GET_CODE (XEXP (link, 0)) != REG)
2388 if (reg_set_p (XEXP (link, 0), PATTERN (start_insn)))
2390 remove_note (p, link);
2396 /* Delete any REG_UNUSED notes that exist on INSN but not on REDUNDANT_INSN.
2398 This handles the case of udivmodXi4 instructions which optimize their
2399 output depending on whether any REG_UNUSED notes are present.
2400 we must make sure that INSN calculates as many results as REDUNDANT_INSN
2404 update_reg_unused_notes (insn, redundant_insn)
2405 rtx insn, redundant_insn;
2409 for (link = REG_NOTES (insn); link; link = next)
2411 next = XEXP (link, 1);
2413 if (REG_NOTE_KIND (link) != REG_UNUSED
2414 || GET_CODE (XEXP (link, 0)) != REG)
2417 if (! find_regno_note (redundant_insn, REG_UNUSED,
2418 REGNO (XEXP (link, 0))))
2419 remove_note (insn, link);
2423 /* Marks registers possibly live at the current place being scanned by
2424 mark_target_live_regs. Used only by next two function. */
2426 static HARD_REG_SET current_live_regs;
2428 /* Marks registers for which we have seen a REG_DEAD note but no assignment.
2429 Also only used by the next two functions. */
2431 static HARD_REG_SET pending_dead_regs;
2433 /* Utility function called from mark_target_live_regs via note_stores.
2434 It deadens any CLOBBERed registers and livens any SET registers. */
2437 update_live_status (dest, x)
2441 int first_regno, last_regno;
2444 if (GET_CODE (dest) != REG
2445 && (GET_CODE (dest) != SUBREG || GET_CODE (SUBREG_REG (dest)) != REG))
2448 if (GET_CODE (dest) == SUBREG)
2449 first_regno = REGNO (SUBREG_REG (dest)) + SUBREG_WORD (dest);
2451 first_regno = REGNO (dest);
2453 last_regno = first_regno + HARD_REGNO_NREGS (first_regno, GET_MODE (dest));
2455 if (GET_CODE (x) == CLOBBER)
2456 for (i = first_regno; i < last_regno; i++)
2457 CLEAR_HARD_REG_BIT (current_live_regs, i);
2459 for (i = first_regno; i < last_regno; i++)
2461 SET_HARD_REG_BIT (current_live_regs, i);
2462 CLEAR_HARD_REG_BIT (pending_dead_regs, i);
2466 /* Similar to next_insn, but ignores insns in the delay slots of
2467 an annulled branch. */
2470 next_insn_no_annul (insn)
2475 /* If INSN is an annulled branch, skip any insns from the target
2477 if (INSN_ANNULLED_BRANCH_P (insn)
2478 && NEXT_INSN (PREV_INSN (insn)) != insn)
2479 while (INSN_FROM_TARGET_P (NEXT_INSN (insn)))
2480 insn = NEXT_INSN (insn);
2482 insn = NEXT_INSN (insn);
2483 if (insn && GET_CODE (insn) == INSN
2484 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2485 insn = XVECEXP (PATTERN (insn), 0, 0);
2491 /* A subroutine of mark_target_live_regs. Search forward from TARGET
2492 looking for registers that are set before they are used. These are dead.
2493 Stop after passing a few conditional jumps, and/or a small
2494 number of unconditional branches. */
2497 find_dead_or_set_registers (target, res, jump_target, jump_count, set, needed)
2499 struct resources *res;
2502 struct resources set, needed;
2504 HARD_REG_SET scratch;
2509 for (insn = target; insn; insn = next)
2511 rtx this_jump_insn = insn;
2513 next = NEXT_INSN (insn);
2514 switch (GET_CODE (insn))
2517 /* After a label, any pending dead registers that weren't yet
2518 used can be made dead. */
2519 AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs);
2520 AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs);
2521 CLEAR_HARD_REG_SET (pending_dead_regs);
2523 if (CODE_LABEL_NUMBER (insn) < max_label_num_after_reload)
2525 /* All spill registers are dead at a label, so kill all of the
2526 ones that aren't needed also. */
2527 COPY_HARD_REG_SET (scratch, used_spill_regs);
2528 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2529 AND_COMPL_HARD_REG_SET (res->regs, scratch);
2538 if (GET_CODE (PATTERN (insn)) == USE)
2540 /* If INSN is a USE made by update_block, we care about the
2541 underlying insn. Any registers set by the underlying insn
2542 are live since the insn is being done somewhere else. */
2543 if (GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2544 mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, 1);
2546 /* All other USE insns are to be ignored. */
2549 else if (GET_CODE (PATTERN (insn)) == CLOBBER)
2551 else if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2553 /* An unconditional jump can be used to fill the delay slot
2554 of a call, so search for a JUMP_INSN in any position. */
2555 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
2557 this_jump_insn = XVECEXP (PATTERN (insn), 0, i);
2558 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2567 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2569 if (jump_count++ < 10)
2571 if (simplejump_p (this_jump_insn)
2572 || GET_CODE (PATTERN (this_jump_insn)) == RETURN)
2574 next = JUMP_LABEL (this_jump_insn);
2579 *jump_target = JUMP_LABEL (this_jump_insn);
2582 else if (condjump_p (this_jump_insn)
2583 || condjump_in_parallel_p (this_jump_insn))
2585 struct resources target_set, target_res;
2586 struct resources fallthrough_res;
2588 /* We can handle conditional branches here by following
2589 both paths, and then IOR the results of the two paths
2590 together, which will give us registers that are dead
2591 on both paths. Since this is expensive, we give it
2592 a much higher cost than unconditional branches. The
2593 cost was chosen so that we will follow at most 1
2594 conditional branch. */
2597 if (jump_count >= 10)
2600 mark_referenced_resources (insn, &needed, 1);
2602 /* For an annulled branch, mark_set_resources ignores slots
2603 filled by instructions from the target. This is correct
2604 if the branch is not taken. Since we are following both
2605 paths from the branch, we must also compute correct info
2606 if the branch is taken. We do this by inverting all of
2607 the INSN_FROM_TARGET_P bits, calling mark_set_resources,
2608 and then inverting the INSN_FROM_TARGET_P bits again. */
2610 if (GET_CODE (PATTERN (insn)) == SEQUENCE
2611 && INSN_ANNULLED_BRANCH_P (this_jump_insn))
2613 for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
2614 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i))
2615 = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i));
2618 mark_set_resources (insn, &target_set, 0, 1);
2620 for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
2621 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i))
2622 = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i));
2624 mark_set_resources (insn, &set, 0, 1);
2628 mark_set_resources (insn, &set, 0, 1);
2633 COPY_HARD_REG_SET (scratch, target_set.regs);
2634 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2635 AND_COMPL_HARD_REG_SET (target_res.regs, scratch);
2637 fallthrough_res = *res;
2638 COPY_HARD_REG_SET (scratch, set.regs);
2639 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2640 AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch);
2642 find_dead_or_set_registers (JUMP_LABEL (this_jump_insn),
2643 &target_res, 0, jump_count,
2644 target_set, needed);
2645 find_dead_or_set_registers (next,
2646 &fallthrough_res, 0, jump_count,
2648 IOR_HARD_REG_SET (fallthrough_res.regs, target_res.regs);
2649 AND_HARD_REG_SET (res->regs, fallthrough_res.regs);
2657 /* Don't try this optimization if we expired our jump count
2658 above, since that would mean there may be an infinite loop
2659 in the function being compiled. */
2665 mark_referenced_resources (insn, &needed, 1);
2666 mark_set_resources (insn, &set, 0, 1);
2668 COPY_HARD_REG_SET (scratch, set.regs);
2669 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2670 AND_COMPL_HARD_REG_SET (res->regs, scratch);
2676 /* Set the resources that are live at TARGET.
2678 If TARGET is zero, we refer to the end of the current function and can
2679 return our precomputed value.
2681 Otherwise, we try to find out what is live by consulting the basic block
2682 information. This is tricky, because we must consider the actions of
2683 reload and jump optimization, which occur after the basic block information
2686 Accordingly, we proceed as follows::
2688 We find the previous BARRIER and look at all immediately following labels
2689 (with no intervening active insns) to see if any of them start a basic
2690 block. If we hit the start of the function first, we use block 0.
2692 Once we have found a basic block and a corresponding first insns, we can
2693 accurately compute the live status from basic_block_live_regs and
2694 reg_renumber. (By starting at a label following a BARRIER, we are immune
2695 to actions taken by reload and jump.) Then we scan all insns between
2696 that point and our target. For each CLOBBER (or for call-clobbered regs
2697 when we pass a CALL_INSN), mark the appropriate registers are dead. For
2698 a SET, mark them as live.
2700 We have to be careful when using REG_DEAD notes because they are not
2701 updated by such things as find_equiv_reg. So keep track of registers
2702 marked as dead that haven't been assigned to, and mark them dead at the
2703 next CODE_LABEL since reload and jump won't propagate values across labels.
2705 If we cannot find the start of a basic block (should be a very rare
2706 case, if it can happen at all), mark everything as potentially live.
2708 Next, scan forward from TARGET looking for things set or clobbered
2709 before they are used. These are not live.
2711 Because we can be called many times on the same target, save our results
2712 in a hash table indexed by INSN_UID. */
2715 mark_target_live_regs (target, res)
2717 struct resources *res;
2721 struct target_info *tinfo;
2725 HARD_REG_SET scratch;
2726 struct resources set, needed;
2728 /* Handle end of function. */
2731 *res = end_of_function_needs;
2735 /* We have to assume memory is needed, but the CC isn't. */
2737 res->volatil = res->unch_memory = 0;
2740 /* See if we have computed this value already. */
2741 for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2742 tinfo; tinfo = tinfo->next)
2743 if (tinfo->uid == INSN_UID (target))
2746 /* Start by getting the basic block number. If we have saved information,
2747 we can get it from there unless the insn at the start of the basic block
2748 has been deleted. */
2749 if (tinfo && tinfo->block != -1
2750 && ! INSN_DELETED_P (basic_block_head[tinfo->block]))
2754 b = find_basic_block (target);
2758 /* If the information is up-to-date, use it. Otherwise, we will
2760 if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b])
2762 COPY_HARD_REG_SET (res->regs, tinfo->live_regs);
2768 /* Allocate a place to put our results and chain it into the
2770 tinfo = (struct target_info *) oballoc (sizeof (struct target_info));
2771 tinfo->uid = INSN_UID (target);
2773 tinfo->next = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2774 target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo;
2777 CLEAR_HARD_REG_SET (pending_dead_regs);
2779 /* If we found a basic block, get the live registers from it and update
2780 them with anything set or killed between its start and the insn before
2781 TARGET. Otherwise, we must assume everything is live. */
2784 regset regs_live = basic_block_live_at_start[b];
2787 rtx start_insn, stop_insn;
2789 /* Compute hard regs live at start of block -- this is the real hard regs
2790 marked live, plus live pseudo regs that have been renumbered to
2793 REG_SET_TO_HARD_REG_SET (current_live_regs, regs_live);
2795 EXECUTE_IF_SET_IN_REG_SET
2796 (regs_live, FIRST_PSEUDO_REGISTER, i,
2798 if ((regno = reg_renumber[i]) >= 0)
2800 j < regno + HARD_REGNO_NREGS (regno,
2801 PSEUDO_REGNO_MODE (i));
2803 SET_HARD_REG_BIT (current_live_regs, j);
2806 /* Get starting and ending insn, handling the case where each might
2808 start_insn = (b == 0 ? get_insns () : basic_block_head[b]);
2811 if (GET_CODE (start_insn) == INSN
2812 && GET_CODE (PATTERN (start_insn)) == SEQUENCE)
2813 start_insn = XVECEXP (PATTERN (start_insn), 0, 0);
2815 if (GET_CODE (stop_insn) == INSN
2816 && GET_CODE (PATTERN (stop_insn)) == SEQUENCE)
2817 stop_insn = next_insn (PREV_INSN (stop_insn));
2819 for (insn = start_insn; insn != stop_insn;
2820 insn = next_insn_no_annul (insn))
2823 rtx real_insn = insn;
2825 /* If this insn is from the target of a branch, it isn't going to
2826 be used in the sequel. If it is used in both cases, this
2827 test will not be true. */
2828 if (INSN_FROM_TARGET_P (insn))
2831 /* If this insn is a USE made by update_block, we care about the
2833 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
2834 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2835 real_insn = XEXP (PATTERN (insn), 0);
2837 if (GET_CODE (real_insn) == CALL_INSN)
2839 /* CALL clobbers all call-used regs that aren't fixed except
2840 sp, ap, and fp. Do this before setting the result of the
2842 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2843 if (call_used_regs[i]
2844 && i != STACK_POINTER_REGNUM && i != FRAME_POINTER_REGNUM
2845 && i != ARG_POINTER_REGNUM
2846 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2847 && i != HARD_FRAME_POINTER_REGNUM
2849 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2850 && ! (i == ARG_POINTER_REGNUM && fixed_regs[i])
2852 #ifdef PIC_OFFSET_TABLE_REGNUM
2853 && ! (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
2856 CLEAR_HARD_REG_BIT (current_live_regs, i);
2858 /* A CALL_INSN sets any global register live, since it may
2859 have been modified by the call. */
2860 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2862 SET_HARD_REG_BIT (current_live_regs, i);
2865 /* Mark anything killed in an insn to be deadened at the next
2866 label. Ignore USE insns; the only REG_DEAD notes will be for
2867 parameters. But they might be early. A CALL_INSN will usually
2868 clobber registers used for parameters. It isn't worth bothering
2869 with the unlikely case when it won't. */
2870 if ((GET_CODE (real_insn) == INSN
2871 && GET_CODE (PATTERN (real_insn)) != USE
2872 && GET_CODE (PATTERN (real_insn)) != CLOBBER)
2873 || GET_CODE (real_insn) == JUMP_INSN
2874 || GET_CODE (real_insn) == CALL_INSN)
2876 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2877 if (REG_NOTE_KIND (link) == REG_DEAD
2878 && GET_CODE (XEXP (link, 0)) == REG
2879 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2881 int first_regno = REGNO (XEXP (link, 0));
2884 + HARD_REGNO_NREGS (first_regno,
2885 GET_MODE (XEXP (link, 0))));
2887 for (i = first_regno; i < last_regno; i++)
2888 SET_HARD_REG_BIT (pending_dead_regs, i);
2891 note_stores (PATTERN (real_insn), update_live_status);
2893 /* If any registers were unused after this insn, kill them.
2894 These notes will always be accurate. */
2895 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2896 if (REG_NOTE_KIND (link) == REG_UNUSED
2897 && GET_CODE (XEXP (link, 0)) == REG
2898 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2900 int first_regno = REGNO (XEXP (link, 0));
2903 + HARD_REGNO_NREGS (first_regno,
2904 GET_MODE (XEXP (link, 0))));
2906 for (i = first_regno; i < last_regno; i++)
2907 CLEAR_HARD_REG_BIT (current_live_regs, i);
2911 else if (GET_CODE (real_insn) == CODE_LABEL)
2913 /* A label clobbers the pending dead registers since neither
2914 reload nor jump will propagate a value across a label. */
2915 AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs);
2916 CLEAR_HARD_REG_SET (pending_dead_regs);
2919 /* The beginning of the epilogue corresponds to the end of the
2920 RTL chain when there are no epilogue insns. Certain resources
2921 are implicitly required at that point. */
2922 else if (GET_CODE (real_insn) == NOTE
2923 && NOTE_LINE_NUMBER (real_insn) == NOTE_INSN_EPILOGUE_BEG)
2924 IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs);
2927 COPY_HARD_REG_SET (res->regs, current_live_regs);
2929 tinfo->bb_tick = bb_ticks[b];
2932 /* We didn't find the start of a basic block. Assume everything
2933 in use. This should happen only extremely rarely. */
2934 SET_HARD_REG_SET (res->regs);
2936 CLEAR_RESOURCE (&set);
2937 CLEAR_RESOURCE (&needed);
2939 jump_insn = find_dead_or_set_registers (target, res, &jump_target, 0,
2942 /* If we hit an unconditional branch, we have another way of finding out
2943 what is live: we can see what is live at the branch target and include
2944 anything used but not set before the branch. The only things that are
2945 live are those that are live using the above test and the test below. */
2949 struct resources new_resources;
2950 rtx stop_insn = next_active_insn (jump_insn);
2952 mark_target_live_regs (next_active_insn (jump_target), &new_resources);
2953 CLEAR_RESOURCE (&set);
2954 CLEAR_RESOURCE (&needed);
2956 /* Include JUMP_INSN in the needed registers. */
2957 for (insn = target; insn != stop_insn; insn = next_active_insn (insn))
2959 mark_referenced_resources (insn, &needed, 1);
2961 COPY_HARD_REG_SET (scratch, needed.regs);
2962 AND_COMPL_HARD_REG_SET (scratch, set.regs);
2963 IOR_HARD_REG_SET (new_resources.regs, scratch);
2965 mark_set_resources (insn, &set, 0, 1);
2968 AND_HARD_REG_SET (res->regs, new_resources.regs);
2971 COPY_HARD_REG_SET (tinfo->live_regs, res->regs);
2974 /* Scan a function looking for insns that need a delay slot and find insns to
2975 put into the delay slot.
2977 NON_JUMPS_P is non-zero if we are to only try to fill non-jump insns (such
2978 as calls). We do these first since we don't want jump insns (that are
2979 easier to fill) to get the only insns that could be used for non-jump insns.
2980 When it is zero, only try to fill JUMP_INSNs.
2982 When slots are filled in this manner, the insns (including the
2983 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
2984 it is possible to tell whether a delay slot has really been filled
2985 or not. `final' knows how to deal with this, by communicating
2986 through FINAL_SEQUENCE. */
2989 fill_simple_delay_slots (non_jumps_p)
2992 register rtx insn, pat, trial, next_trial;
2994 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
2995 struct resources needed, set;
2996 int slots_to_fill, slots_filled;
2999 for (i = 0; i < num_unfilled_slots; i++)
3002 /* Get the next insn to fill. If it has already had any slots assigned,
3003 we can't do anything with it. Maybe we'll improve this later. */
3005 insn = unfilled_slots_base[i];
3007 || INSN_DELETED_P (insn)
3008 || (GET_CODE (insn) == INSN
3009 && GET_CODE (PATTERN (insn)) == SEQUENCE)
3010 || (GET_CODE (insn) == JUMP_INSN && non_jumps_p)
3011 || (GET_CODE (insn) != JUMP_INSN && ! non_jumps_p))
3014 if (GET_CODE (insn) == JUMP_INSN)
3015 flags = get_jump_flags (insn, JUMP_LABEL (insn));
3017 flags = get_jump_flags (insn, NULL_RTX);
3018 slots_to_fill = num_delay_slots (insn);
3019 if (slots_to_fill == 0)
3022 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
3023 says how many. After initialization, first try optimizing
3026 nop add %o7,.-L1,%o7
3030 If this case applies, the delay slot of the call is filled with
3031 the unconditional jump. This is done first to avoid having the
3032 delay slot of the call filled in the backward scan. Also, since
3033 the unconditional jump is likely to also have a delay slot, that
3034 insn must exist when it is subsequently scanned.
3036 This is tried on each insn with delay slots as some machines
3037 have insns which perform calls, but are not represented as
3043 if ((trial = next_active_insn (insn))
3044 && GET_CODE (trial) == JUMP_INSN
3045 && simplejump_p (trial)
3046 && eligible_for_delay (insn, slots_filled, trial, flags)
3047 && no_labels_between_p (insn, trial))
3051 delay_list = add_to_delay_list (trial, delay_list);
3053 /* TRIAL may have had its delay slot filled, then unfilled. When
3054 the delay slot is unfilled, TRIAL is placed back on the unfilled
3055 slots obstack. Unfortunately, it is placed on the end of the
3056 obstack, not in its original location. Therefore, we must search
3057 from entry i + 1 to the end of the unfilled slots obstack to
3058 try and find TRIAL. */
3059 tmp = &unfilled_slots_base[i + 1];
3060 while (*tmp != trial && tmp != unfilled_slots_next)
3063 /* Remove the unconditional jump from consideration for delay slot
3064 filling and unthread it. */
3068 rtx next = NEXT_INSN (trial);
3069 rtx prev = PREV_INSN (trial);
3071 NEXT_INSN (prev) = next;
3073 PREV_INSN (next) = prev;
3077 /* Now, scan backwards from the insn to search for a potential
3078 delay-slot candidate. Stop searching when a label or jump is hit.
3080 For each candidate, if it is to go into the delay slot (moved
3081 forward in execution sequence), it must not need or set any resources
3082 that were set by later insns and must not set any resources that
3083 are needed for those insns.
3085 The delay slot insn itself sets resources unless it is a call
3086 (in which case the called routine, not the insn itself, is doing
3089 if (slots_filled < slots_to_fill)
3091 CLEAR_RESOURCE (&needed);
3092 CLEAR_RESOURCE (&set);
3093 mark_set_resources (insn, &set, 0, 0);
3094 mark_referenced_resources (insn, &needed, 0);
3096 for (trial = prev_nonnote_insn (insn); ! stop_search_p (trial, 1);
3099 next_trial = prev_nonnote_insn (trial);
3101 /* This must be an INSN or CALL_INSN. */
3102 pat = PATTERN (trial);
3104 /* USE and CLOBBER at this level was just for flow; ignore it. */
3105 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3108 /* Check for resource conflict first, to avoid unnecessary
3110 if (! insn_references_resource_p (trial, &set, 1)
3111 && ! insn_sets_resource_p (trial, &set, 1)
3112 && ! insn_sets_resource_p (trial, &needed, 1)
3114 /* Can't separate set of cc0 from its use. */
3115 && ! (reg_mentioned_p (cc0_rtx, pat)
3116 && ! sets_cc0_p (cc0_rtx, pat))
3120 trial = try_split (pat, trial, 1);
3121 next_trial = prev_nonnote_insn (trial);
3122 if (eligible_for_delay (insn, slots_filled, trial, flags))
3124 /* In this case, we are searching backward, so if we
3125 find insns to put on the delay list, we want
3126 to put them at the head, rather than the
3127 tail, of the list. */
3129 update_reg_dead_notes (trial, insn);
3130 delay_list = gen_rtx_INSN_LIST (VOIDmode,
3132 update_block (trial, trial);
3133 delete_insn (trial);
3134 if (slots_to_fill == ++slots_filled)
3140 mark_set_resources (trial, &set, 0, 1);
3141 mark_referenced_resources (trial, &needed, 1);
3145 /* If all needed slots haven't been filled, we come here. */
3147 /* Try to optimize case of jumping around a single insn. */
3148 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
3149 if (slots_filled != slots_to_fill
3151 && GET_CODE (insn) == JUMP_INSN
3152 && (condjump_p (insn) || condjump_in_parallel_p (insn)))
3154 delay_list = optimize_skip (insn);
3160 /* Try to get insns from beyond the insn needing the delay slot.
3161 These insns can neither set or reference resources set in insns being
3162 skipped, cannot set resources in the insn being skipped, and, if this
3163 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
3164 call might not return).
3166 There used to be code which continued past the target label if
3167 we saw all uses of the target label. This code did not work,
3168 because it failed to account for some instructions which were
3169 both annulled and marked as from the target. This can happen as a
3170 result of optimize_skip. Since this code was redundant with
3171 fill_eager_delay_slots anyways, it was just deleted. */
3173 if (slots_filled != slots_to_fill
3174 && (GET_CODE (insn) != JUMP_INSN
3175 || ((condjump_p (insn) || condjump_in_parallel_p (insn))
3176 && ! simplejump_p (insn)
3177 && JUMP_LABEL (insn) != 0)))
3180 int maybe_never = 0;
3181 struct resources needed_at_jump;
3183 CLEAR_RESOURCE (&needed);
3184 CLEAR_RESOURCE (&set);
3186 if (GET_CODE (insn) == CALL_INSN)
3188 mark_set_resources (insn, &set, 0, 1);
3189 mark_referenced_resources (insn, &needed, 1);
3194 mark_set_resources (insn, &set, 0, 1);
3195 mark_referenced_resources (insn, &needed, 1);
3196 if (GET_CODE (insn) == JUMP_INSN)
3197 target = JUMP_LABEL (insn);
3200 for (trial = next_nonnote_insn (insn); trial; trial = next_trial)
3202 rtx pat, trial_delay;
3204 next_trial = next_nonnote_insn (trial);
3206 if (GET_CODE (trial) == CODE_LABEL
3207 || GET_CODE (trial) == BARRIER)
3210 /* We must have an INSN, JUMP_INSN, or CALL_INSN. */
3211 pat = PATTERN (trial);
3213 /* Stand-alone USE and CLOBBER are just for flow. */
3214 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3217 /* If this already has filled delay slots, get the insn needing
3219 if (GET_CODE (pat) == SEQUENCE)
3220 trial_delay = XVECEXP (pat, 0, 0);
3222 trial_delay = trial;
3224 /* If this is a jump insn to our target, indicate that we have
3225 seen another jump to it. If we aren't handling a conditional
3226 jump, stop our search. Otherwise, compute the needs at its
3227 target and add them to NEEDED. */
3228 if (GET_CODE (trial_delay) == JUMP_INSN)
3232 else if (JUMP_LABEL (trial_delay) != target)
3234 mark_target_live_regs
3235 (next_active_insn (JUMP_LABEL (trial_delay)),
3237 needed.memory |= needed_at_jump.memory;
3238 needed.unch_memory |= needed_at_jump.unch_memory;
3239 IOR_HARD_REG_SET (needed.regs, needed_at_jump.regs);
3243 /* See if we have a resource problem before we try to
3246 && GET_CODE (pat) != SEQUENCE
3247 && ! insn_references_resource_p (trial, &set, 1)
3248 && ! insn_sets_resource_p (trial, &set, 1)
3249 && ! insn_sets_resource_p (trial, &needed, 1)
3251 && ! (reg_mentioned_p (cc0_rtx, pat) && ! sets_cc0_p (pat))
3253 && ! (maybe_never && may_trap_p (pat))
3254 && (trial = try_split (pat, trial, 0))
3255 && eligible_for_delay (insn, slots_filled, trial, flags))
3257 next_trial = next_nonnote_insn (trial);
3258 delay_list = add_to_delay_list (trial, delay_list);
3261 if (reg_mentioned_p (cc0_rtx, pat))
3262 link_cc0_insns (trial);
3265 delete_insn (trial);
3266 if (slots_to_fill == ++slots_filled)
3271 mark_set_resources (trial, &set, 0, 1);
3272 mark_referenced_resources (trial, &needed, 1);
3274 /* Ensure we don't put insns between the setting of cc and the
3275 comparison by moving a setting of cc into an earlier delay
3276 slot since these insns could clobber the condition code. */
3279 /* If this is a call or jump, we might not get here. */
3280 if (GET_CODE (trial_delay) == CALL_INSN
3281 || GET_CODE (trial_delay) == JUMP_INSN)
3285 /* If there are slots left to fill and our search was stopped by an
3286 unconditional branch, try the insn at the branch target. We can
3287 redirect the branch if it works.
3289 Don't do this if the insn at the branch target is a branch. */
3290 if (slots_to_fill != slots_filled
3292 && GET_CODE (trial) == JUMP_INSN
3293 && simplejump_p (trial)
3294 && (target == 0 || JUMP_LABEL (trial) == target)
3295 && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0
3296 && ! (GET_CODE (next_trial) == INSN
3297 && GET_CODE (PATTERN (next_trial)) == SEQUENCE)
3298 && GET_CODE (next_trial) != JUMP_INSN
3299 && ! insn_references_resource_p (next_trial, &set, 1)
3300 && ! insn_sets_resource_p (next_trial, &set, 1)
3301 && ! insn_sets_resource_p (next_trial, &needed, 1)
3303 && ! reg_mentioned_p (cc0_rtx, PATTERN (next_trial))
3305 && ! (maybe_never && may_trap_p (PATTERN (next_trial)))
3306 && (next_trial = try_split (PATTERN (next_trial), next_trial, 0))
3307 && eligible_for_delay (insn, slots_filled, next_trial, flags))
3309 rtx new_label = next_active_insn (next_trial);
3312 new_label = get_label_before (new_label);
3314 new_label = find_end_label ();
3317 = add_to_delay_list (copy_rtx (next_trial), delay_list);
3319 reorg_redirect_jump (trial, new_label);
3321 /* If we merged because we both jumped to the same place,
3322 redirect the original insn also. */
3324 reorg_redirect_jump (insn, new_label);
3328 /* If this is an unconditional jump, then try to get insns from the
3329 target of the jump. */
3330 if (GET_CODE (insn) == JUMP_INSN
3331 && simplejump_p (insn)
3332 && slots_filled != slots_to_fill)
3334 = fill_slots_from_thread (insn, const_true_rtx,
3335 next_active_insn (JUMP_LABEL (insn)),
3337 own_thread_p (JUMP_LABEL (insn),
3338 JUMP_LABEL (insn), 0),
3339 slots_to_fill, &slots_filled,
3343 unfilled_slots_base[i]
3344 = emit_delay_sequence (insn, delay_list, slots_filled);
3346 if (slots_to_fill == slots_filled)
3347 unfilled_slots_base[i] = 0;
3349 note_delay_statistics (slots_filled, 0);
3352 #ifdef DELAY_SLOTS_FOR_EPILOGUE
3353 /* See if the epilogue needs any delay slots. Try to fill them if so.
3354 The only thing we can do is scan backwards from the end of the
3355 function. If we did this in a previous pass, it is incorrect to do it
3357 if (current_function_epilogue_delay_list)
3360 slots_to_fill = DELAY_SLOTS_FOR_EPILOGUE;
3361 if (slots_to_fill == 0)
3365 CLEAR_RESOURCE (&set);
3367 /* The frame pointer and stack pointer are needed at the beginning of
3368 the epilogue, so instructions setting them can not be put in the
3369 epilogue delay slot. However, everything else needed at function
3370 end is safe, so we don't want to use end_of_function_needs here. */
3371 CLEAR_RESOURCE (&needed);
3372 if (frame_pointer_needed)
3374 SET_HARD_REG_BIT (needed.regs, FRAME_POINTER_REGNUM);
3375 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3376 SET_HARD_REG_BIT (needed.regs, HARD_FRAME_POINTER_REGNUM);
3378 #ifdef EXIT_IGNORE_STACK
3379 if (! EXIT_IGNORE_STACK)
3381 SET_HARD_REG_BIT (needed.regs, STACK_POINTER_REGNUM);
3384 SET_HARD_REG_BIT (needed.regs, STACK_POINTER_REGNUM);
3386 #ifdef EPILOGUE_USES
3387 for (i = 0; i <FIRST_PSEUDO_REGISTER; i++)
3389 if (EPILOGUE_USES (i))
3390 SET_HARD_REG_BIT (needed.regs, i);
3394 for (trial = get_last_insn (); ! stop_search_p (trial, 1);
3395 trial = PREV_INSN (trial))
3397 if (GET_CODE (trial) == NOTE)
3399 pat = PATTERN (trial);
3400 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3403 if (! insn_references_resource_p (trial, &set, 1)
3404 && ! insn_sets_resource_p (trial, &needed, 1)
3405 && ! insn_sets_resource_p (trial, &set, 1)
3407 /* Don't want to mess with cc0 here. */
3408 && ! reg_mentioned_p (cc0_rtx, pat)
3412 trial = try_split (pat, trial, 1);
3413 if (ELIGIBLE_FOR_EPILOGUE_DELAY (trial, slots_filled))
3415 /* Here as well we are searching backward, so put the
3416 insns we find on the head of the list. */
3418 current_function_epilogue_delay_list
3419 = gen_rtx_INSN_LIST (VOIDmode, trial,
3420 current_function_epilogue_delay_list);
3421 mark_referenced_resources (trial, &end_of_function_needs, 1);
3422 update_block (trial, trial);
3423 delete_insn (trial);
3425 /* Clear deleted bit so final.c will output the insn. */
3426 INSN_DELETED_P (trial) = 0;
3428 if (slots_to_fill == ++slots_filled)
3434 mark_set_resources (trial, &set, 0, 1);
3435 mark_referenced_resources (trial, &needed, 1);
3438 note_delay_statistics (slots_filled, 0);
3442 /* Try to find insns to place in delay slots.
3444 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
3445 or is an unconditional branch if CONDITION is const_true_rtx.
3446 *PSLOTS_FILLED is updated with the number of slots that we have filled.
3448 THREAD is a flow-of-control, either the insns to be executed if the
3449 branch is true or if the branch is false, THREAD_IF_TRUE says which.
3451 OPPOSITE_THREAD is the thread in the opposite direction. It is used
3452 to see if any potential delay slot insns set things needed there.
3454 LIKELY is non-zero if it is extremely likely that the branch will be
3455 taken and THREAD_IF_TRUE is set. This is used for the branch at the
3456 end of a loop back up to the top.
3458 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
3459 thread. I.e., it is the fallthrough code of our jump or the target of the
3460 jump when we are the only jump going there.
3462 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
3463 case, we can only take insns from the head of the thread for our delay
3464 slot. We then adjust the jump to point after the insns we have taken. */
3467 fill_slots_from_thread (insn, condition, thread, opposite_thread, likely,
3468 thread_if_true, own_thread,
3469 slots_to_fill, pslots_filled, delay_list)
3472 rtx thread, opposite_thread;
3476 int slots_to_fill, *pslots_filled;
3480 struct resources opposite_needed, set, needed;
3486 /* Validate our arguments. */
3487 if ((condition == const_true_rtx && ! thread_if_true)
3488 || (! own_thread && ! thread_if_true))
3491 flags = get_jump_flags (insn, JUMP_LABEL (insn));
3493 /* If our thread is the end of subroutine, we can't get any delay
3498 /* If this is an unconditional branch, nothing is needed at the
3499 opposite thread. Otherwise, compute what is needed there. */
3500 if (condition == const_true_rtx)
3501 CLEAR_RESOURCE (&opposite_needed);
3503 mark_target_live_regs (opposite_thread, &opposite_needed);
3505 /* If the insn at THREAD can be split, do it here to avoid having to
3506 update THREAD and NEW_THREAD if it is done in the loop below. Also
3507 initialize NEW_THREAD. */
3509 new_thread = thread = try_split (PATTERN (thread), thread, 0);
3511 /* Scan insns at THREAD. We are looking for an insn that can be removed
3512 from THREAD (it neither sets nor references resources that were set
3513 ahead of it and it doesn't set anything needs by the insns ahead of
3514 it) and that either can be placed in an annulling insn or aren't
3515 needed at OPPOSITE_THREAD. */
3517 CLEAR_RESOURCE (&needed);
3518 CLEAR_RESOURCE (&set);
3520 /* If we do not own this thread, we must stop as soon as we find
3521 something that we can't put in a delay slot, since all we can do
3522 is branch into THREAD at a later point. Therefore, labels stop
3523 the search if this is not the `true' thread. */
3525 for (trial = thread;
3526 ! stop_search_p (trial, ! thread_if_true) && (! lose || own_thread);
3527 trial = next_nonnote_insn (trial))
3531 /* If we have passed a label, we no longer own this thread. */
3532 if (GET_CODE (trial) == CODE_LABEL)
3538 pat = PATTERN (trial);
3539 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3542 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
3543 don't separate or copy insns that set and use CC0. */
3544 if (! insn_references_resource_p (trial, &set, 1)
3545 && ! insn_sets_resource_p (trial, &set, 1)
3546 && ! insn_sets_resource_p (trial, &needed, 1)
3548 && ! (reg_mentioned_p (cc0_rtx, pat)
3549 && (! own_thread || ! sets_cc0_p (pat)))
3555 /* If TRIAL is redundant with some insn before INSN, we don't
3556 actually need to add it to the delay list; we can merely pretend
3558 if ((prior_insn = redundant_insn (trial, insn, delay_list)))
3560 fix_reg_dead_note (prior_insn, insn);
3563 update_block (trial, thread);
3564 if (trial == thread)
3566 thread = next_active_insn (thread);
3567 if (new_thread == trial)
3568 new_thread = thread;
3571 delete_insn (trial);
3575 update_reg_unused_notes (prior_insn, trial);
3576 new_thread = next_active_insn (trial);
3582 /* There are two ways we can win: If TRIAL doesn't set anything
3583 needed at the opposite thread and can't trap, or if it can
3584 go into an annulled delay slot. */
3585 if (condition == const_true_rtx
3586 || (! insn_sets_resource_p (trial, &opposite_needed, 1)
3587 && ! may_trap_p (pat)))
3590 trial = try_split (pat, trial, 0);
3591 if (new_thread == old_trial)
3593 if (thread == old_trial)
3595 pat = PATTERN (trial);
3596 if (eligible_for_delay (insn, *pslots_filled, trial, flags))
3600 #ifdef ANNUL_IFTRUE_SLOTS
3603 #ifdef ANNUL_IFFALSE_SLOTS
3609 trial = try_split (pat, trial, 0);
3610 if (new_thread == old_trial)
3612 if (thread == old_trial)
3614 pat = PATTERN (trial);
3616 ? eligible_for_annul_false (insn, *pslots_filled, trial, flags)
3617 : eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
3625 if (reg_mentioned_p (cc0_rtx, pat))
3626 link_cc0_insns (trial);
3629 /* If we own this thread, delete the insn. If this is the
3630 destination of a branch, show that a basic block status
3631 may have been updated. In any case, mark the new
3632 starting point of this thread. */
3635 update_block (trial, thread);
3636 if (trial == thread)
3638 thread = next_active_insn (thread);
3639 if (new_thread == trial)
3640 new_thread = thread;
3642 delete_insn (trial);
3645 new_thread = next_active_insn (trial);
3647 temp = own_thread ? trial : copy_rtx (trial);
3649 INSN_FROM_TARGET_P (temp) = 1;
3651 delay_list = add_to_delay_list (temp, delay_list);
3653 mark_set_resources (trial, &opposite_needed, 0, 1);
3655 if (slots_to_fill == ++(*pslots_filled))
3657 /* Even though we have filled all the slots, we
3658 may be branching to a location that has a
3659 redundant insn. Skip any if so. */
3660 while (new_thread && ! own_thread
3661 && ! insn_sets_resource_p (new_thread, &set, 1)
3662 && ! insn_sets_resource_p (new_thread, &needed, 1)
3663 && ! insn_references_resource_p (new_thread,
3665 && redundant_insn (new_thread, insn, delay_list))
3666 new_thread = next_active_insn (new_thread);
3675 /* This insn can't go into a delay slot. */
3677 mark_set_resources (trial, &set, 0, 1);
3678 mark_referenced_resources (trial, &needed, 1);
3680 /* Ensure we don't put insns between the setting of cc and the comparison
3681 by moving a setting of cc into an earlier delay slot since these insns
3682 could clobber the condition code. */
3685 /* If this insn is a register-register copy and the next insn has
3686 a use of our destination, change it to use our source. That way,
3687 it will become a candidate for our delay slot the next time
3688 through this loop. This case occurs commonly in loops that
3691 We could check for more complex cases than those tested below,
3692 but it doesn't seem worth it. It might also be a good idea to try
3693 to swap the two insns. That might do better.
3695 We can't do this if the next insn modifies our destination, because
3696 that would make the replacement into the insn invalid. We also can't
3697 do this if it modifies our source, because it might be an earlyclobber
3698 operand. This latter test also prevents updating the contents of
3701 if (GET_CODE (trial) == INSN && GET_CODE (pat) == SET
3702 && GET_CODE (SET_SRC (pat)) == REG
3703 && GET_CODE (SET_DEST (pat)) == REG)
3705 rtx next = next_nonnote_insn (trial);
3707 if (next && GET_CODE (next) == INSN
3708 && GET_CODE (PATTERN (next)) != USE
3709 && ! reg_set_p (SET_DEST (pat), next)
3710 && ! reg_set_p (SET_SRC (pat), next)
3711 && reg_referenced_p (SET_DEST (pat), PATTERN (next)))
3712 validate_replace_rtx (SET_DEST (pat), SET_SRC (pat), next);
3716 /* If we stopped on a branch insn that has delay slots, see if we can
3717 steal some of the insns in those slots. */
3718 if (trial && GET_CODE (trial) == INSN
3719 && GET_CODE (PATTERN (trial)) == SEQUENCE
3720 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN)
3722 /* If this is the `true' thread, we will want to follow the jump,
3723 so we can only do this if we have taken everything up to here. */
3724 if (thread_if_true && trial == new_thread
3725 && ! insn_references_resource_p (XVECEXP (PATTERN (trial), 0, 0),
3726 &opposite_needed, 0))
3728 = steal_delay_list_from_target (insn, condition, PATTERN (trial),
3729 delay_list, &set, &needed,
3730 &opposite_needed, slots_to_fill,
3731 pslots_filled, &must_annul,
3733 else if (! thread_if_true)
3735 = steal_delay_list_from_fallthrough (insn, condition,
3737 delay_list, &set, &needed,
3738 &opposite_needed, slots_to_fill,
3739 pslots_filled, &must_annul);
3742 /* If we haven't found anything for this delay slot and it is very
3743 likely that the branch will be taken, see if the insn at our target
3744 increments or decrements a register with an increment that does not
3745 depend on the destination register. If so, try to place the opposite
3746 arithmetic insn after the jump insn and put the arithmetic insn in the
3747 delay slot. If we can't do this, return. */
3748 if (delay_list == 0 && likely && new_thread
3749 && GET_CODE (new_thread) == INSN
3750 && GET_CODE (PATTERN (new_thread)) != ASM_INPUT
3751 && asm_noperands (PATTERN (new_thread)) < 0)
3753 rtx pat = PATTERN (new_thread);
3758 pat = PATTERN (trial);
3760 if (GET_CODE (trial) != INSN || GET_CODE (pat) != SET
3761 || ! eligible_for_delay (insn, 0, trial, flags))
3764 dest = SET_DEST (pat), src = SET_SRC (pat);
3765 if ((GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
3766 && rtx_equal_p (XEXP (src, 0), dest)
3767 && ! reg_overlap_mentioned_p (dest, XEXP (src, 1)))
3769 rtx other = XEXP (src, 1);
3773 /* If this is a constant adjustment, use the same code with
3774 the negated constant. Otherwise, reverse the sense of the
3776 if (GET_CODE (other) == CONST_INT)
3777 new_arith = gen_rtx_fmt_ee (GET_CODE (src), GET_MODE (src), dest,
3778 negate_rtx (GET_MODE (src), other));
3780 new_arith = gen_rtx_fmt_ee (GET_CODE (src) == PLUS ? MINUS : PLUS,
3781 GET_MODE (src), dest, other);
3783 ninsn = emit_insn_after (gen_rtx_SET (VOIDmode, dest, new_arith),
3786 if (recog_memoized (ninsn) < 0
3787 || (insn_extract (ninsn),
3788 ! constrain_operands (INSN_CODE (ninsn), 1)))
3790 delete_insn (ninsn);
3796 update_block (trial, thread);
3797 if (trial == thread)
3799 thread = next_active_insn (thread);
3800 if (new_thread == trial)
3801 new_thread = thread;
3803 delete_insn (trial);
3806 new_thread = next_active_insn (trial);
3808 ninsn = own_thread ? trial : copy_rtx (trial);
3810 INSN_FROM_TARGET_P (ninsn) = 1;
3812 delay_list = add_to_delay_list (ninsn, NULL_RTX);
3817 if (delay_list && must_annul)
3818 INSN_ANNULLED_BRANCH_P (insn) = 1;
3820 /* If we are to branch into the middle of this thread, find an appropriate
3821 label or make a new one if none, and redirect INSN to it. If we hit the
3822 end of the function, use the end-of-function label. */
3823 if (new_thread != thread)
3827 if (! thread_if_true)
3830 if (new_thread && GET_CODE (new_thread) == JUMP_INSN
3831 && (simplejump_p (new_thread)
3832 || GET_CODE (PATTERN (new_thread)) == RETURN)
3833 && redirect_with_delay_list_safe_p (insn,
3834 JUMP_LABEL (new_thread),
3836 new_thread = follow_jumps (JUMP_LABEL (new_thread));
3838 if (new_thread == 0)
3839 label = find_end_label ();
3840 else if (GET_CODE (new_thread) == CODE_LABEL)
3843 label = get_label_before (new_thread);
3845 reorg_redirect_jump (insn, label);
3851 /* Make another attempt to find insns to place in delay slots.
3853 We previously looked for insns located in front of the delay insn
3854 and, for non-jump delay insns, located behind the delay insn.
3856 Here only try to schedule jump insns and try to move insns from either
3857 the target or the following insns into the delay slot. If annulling is
3858 supported, we will be likely to do this. Otherwise, we can do this only
3862 fill_eager_delay_slots ()
3866 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
3868 for (i = 0; i < num_unfilled_slots; i++)
3871 rtx target_label, insn_at_target, fallthrough_insn;
3874 int own_fallthrough;
3875 int prediction, slots_to_fill, slots_filled;
3877 insn = unfilled_slots_base[i];
3879 || INSN_DELETED_P (insn)
3880 || GET_CODE (insn) != JUMP_INSN
3881 || ! (condjump_p (insn) || condjump_in_parallel_p (insn)))
3884 slots_to_fill = num_delay_slots (insn);
3885 if (slots_to_fill == 0)
3889 target_label = JUMP_LABEL (insn);
3890 condition = get_branch_condition (insn, target_label);
3895 /* Get the next active fallthrough and target insns and see if we own
3896 them. Then see whether the branch is likely true. We don't need
3897 to do a lot of this for unconditional branches. */
3899 insn_at_target = next_active_insn (target_label);
3900 own_target = own_thread_p (target_label, target_label, 0);
3902 if (condition == const_true_rtx)
3904 own_fallthrough = 0;
3905 fallthrough_insn = 0;
3910 fallthrough_insn = next_active_insn (insn);
3911 own_fallthrough = own_thread_p (NEXT_INSN (insn), NULL_RTX, 1);
3912 prediction = mostly_true_jump (insn, condition);
3915 /* If this insn is expected to branch, first try to get insns from our
3916 target, then our fallthrough insns. If it is not, expected to branch,
3917 try the other order. */
3922 = fill_slots_from_thread (insn, condition, insn_at_target,
3923 fallthrough_insn, prediction == 2, 1,
3925 slots_to_fill, &slots_filled, delay_list);
3927 if (delay_list == 0 && own_fallthrough)
3929 /* Even though we didn't find anything for delay slots,
3930 we might have found a redundant insn which we deleted
3931 from the thread that was filled. So we have to recompute
3932 the next insn at the target. */
3933 target_label = JUMP_LABEL (insn);
3934 insn_at_target = next_active_insn (target_label);
3937 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3938 insn_at_target, 0, 0,
3940 slots_to_fill, &slots_filled,
3946 if (own_fallthrough)
3948 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3949 insn_at_target, 0, 0,
3951 slots_to_fill, &slots_filled,
3954 if (delay_list == 0)
3956 = fill_slots_from_thread (insn, condition, insn_at_target,
3957 next_active_insn (insn), 0, 1,
3959 slots_to_fill, &slots_filled,
3964 unfilled_slots_base[i]
3965 = emit_delay_sequence (insn, delay_list, slots_filled);
3967 if (slots_to_fill == slots_filled)
3968 unfilled_slots_base[i] = 0;
3970 note_delay_statistics (slots_filled, 1);
3974 /* Once we have tried two ways to fill a delay slot, make a pass over the
3975 code to try to improve the results and to do such things as more jump
3979 relax_delay_slots (first)
3982 register rtx insn, next, pat;
3983 register rtx trial, delay_insn, target_label;
3985 /* Look at every JUMP_INSN and see if we can improve it. */
3986 for (insn = first; insn; insn = next)
3990 next = next_active_insn (insn);
3992 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3993 the next insn, or jumps to a label that is not the last of a
3994 group of consecutive labels. */
3995 if (GET_CODE (insn) == JUMP_INSN
3996 && (condjump_p (insn) || condjump_in_parallel_p (insn))
3997 && (target_label = JUMP_LABEL (insn)) != 0)
3999 target_label = follow_jumps (target_label);
4000 target_label = prev_label (next_active_insn (target_label));
4002 if (target_label == 0)
4003 target_label = find_end_label ();
4005 if (next_active_insn (target_label) == next
4006 && ! condjump_in_parallel_p (insn))
4012 if (target_label != JUMP_LABEL (insn))
4013 reorg_redirect_jump (insn, target_label);
4015 /* See if this jump branches around a unconditional jump.
4016 If so, invert this jump and point it to the target of the
4018 if (next && GET_CODE (next) == JUMP_INSN
4019 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
4020 && next_active_insn (target_label) == next_active_insn (next)
4021 && no_labels_between_p (insn, next))
4023 rtx label = JUMP_LABEL (next);
4025 /* Be careful how we do this to avoid deleting code or
4026 labels that are momentarily dead. See similar optimization
4029 We also need to ensure we properly handle the case when
4030 invert_jump fails. */
4032 ++LABEL_NUSES (target_label);
4034 ++LABEL_NUSES (label);
4036 if (invert_jump (insn, label))
4043 --LABEL_NUSES (label);
4045 if (--LABEL_NUSES (target_label) == 0)
4046 delete_insn (target_label);
4052 /* If this is an unconditional jump and the previous insn is a
4053 conditional jump, try reversing the condition of the previous
4054 insn and swapping our targets. The next pass might be able to
4057 Don't do this if we expect the conditional branch to be true, because
4058 we would then be making the more common case longer. */
4060 if (GET_CODE (insn) == JUMP_INSN
4061 && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN)
4062 && (other = prev_active_insn (insn)) != 0
4063 && (condjump_p (other) || condjump_in_parallel_p (other))
4064 && no_labels_between_p (other, insn)
4065 && 0 < mostly_true_jump (other,
4066 get_branch_condition (other,
4067 JUMP_LABEL (other))))
4069 rtx other_target = JUMP_LABEL (other);
4070 target_label = JUMP_LABEL (insn);
4072 /* Increment the count of OTHER_TARGET, so it doesn't get deleted
4073 as we move the label. */
4075 ++LABEL_NUSES (other_target);
4077 if (invert_jump (other, target_label))
4078 reorg_redirect_jump (insn, other_target);
4081 --LABEL_NUSES (other_target);
4084 /* Now look only at cases where we have filled a delay slot. */
4085 if (GET_CODE (insn) != INSN
4086 || GET_CODE (PATTERN (insn)) != SEQUENCE)
4089 pat = PATTERN (insn);
4090 delay_insn = XVECEXP (pat, 0, 0);
4092 /* See if the first insn in the delay slot is redundant with some
4093 previous insn. Remove it from the delay slot if so; then set up
4094 to reprocess this insn. */
4095 if (redundant_insn (XVECEXP (pat, 0, 1), delay_insn, 0))
4097 delete_from_delay_slot (XVECEXP (pat, 0, 1));
4098 next = prev_active_insn (next);
4102 /* Now look only at the cases where we have a filled JUMP_INSN. */
4103 if (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
4104 || ! (condjump_p (XVECEXP (PATTERN (insn), 0, 0))
4105 || condjump_in_parallel_p (XVECEXP (PATTERN (insn), 0, 0))))
4108 target_label = JUMP_LABEL (delay_insn);
4112 /* If this jump goes to another unconditional jump, thread it, but
4113 don't convert a jump into a RETURN here. */
4114 trial = follow_jumps (target_label);
4115 /* We use next_real_insn instead of next_active_insn, so that
4116 the special USE insns emitted by reorg won't be ignored.
4117 If they are ignored, then they will get deleted if target_label
4118 is now unreachable, and that would cause mark_target_live_regs
4120 trial = prev_label (next_real_insn (trial));
4121 if (trial == 0 && target_label != 0)
4122 trial = find_end_label ();
4124 if (trial != target_label
4125 && redirect_with_delay_slots_safe_p (delay_insn, trial, insn))
4127 reorg_redirect_jump (delay_insn, trial);
4128 target_label = trial;
4131 /* If the first insn at TARGET_LABEL is redundant with a previous
4132 insn, redirect the jump to the following insn process again. */
4133 trial = next_active_insn (target_label);
4134 if (trial && GET_CODE (PATTERN (trial)) != SEQUENCE
4135 && redundant_insn (trial, insn, 0))
4139 /* Figure out where to emit the special USE insn so we don't
4140 later incorrectly compute register live/death info. */
4141 tmp = next_active_insn (trial);
4143 tmp = find_end_label ();
4145 /* Insert the special USE insn and update dataflow info. */
4146 update_block (trial, tmp);
4148 /* Now emit a label before the special USE insn, and
4149 redirect our jump to the new label. */
4150 target_label = get_label_before (PREV_INSN (tmp));
4151 reorg_redirect_jump (delay_insn, target_label);
4156 /* Similarly, if it is an unconditional jump with one insn in its
4157 delay list and that insn is redundant, thread the jump. */
4158 if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE
4159 && XVECLEN (PATTERN (trial), 0) == 2
4160 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN
4161 && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0))
4162 || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN)
4163 && redundant_insn (XVECEXP (PATTERN (trial), 0, 1), insn, 0))
4165 target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0));
4166 if (target_label == 0)
4167 target_label = find_end_label ();
4169 if (redirect_with_delay_slots_safe_p (delay_insn, target_label,
4172 reorg_redirect_jump (delay_insn, target_label);
4179 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
4180 && prev_active_insn (target_label) == insn
4181 && ! condjump_in_parallel_p (delay_insn)
4183 /* If the last insn in the delay slot sets CC0 for some insn,
4184 various code assumes that it is in a delay slot. We could
4185 put it back where it belonged and delete the register notes,
4186 but it doesn't seem worthwhile in this uncommon case. */
4187 && ! find_reg_note (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1),
4188 REG_CC_USER, NULL_RTX)
4194 /* All this insn does is execute its delay list and jump to the
4195 following insn. So delete the jump and just execute the delay
4198 We do this by deleting the INSN containing the SEQUENCE, then
4199 re-emitting the insns separately, and then deleting the jump.
4200 This allows the count of the jump target to be properly
4203 /* Clear the from target bit, since these insns are no longer
4205 for (i = 0; i < XVECLEN (pat, 0); i++)
4206 INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)) = 0;
4208 trial = PREV_INSN (insn);
4210 emit_insn_after (pat, trial);
4211 delete_scheduled_jump (delay_insn);
4215 /* See if this is an unconditional jump around a single insn which is
4216 identical to the one in its delay slot. In this case, we can just
4217 delete the branch and the insn in its delay slot. */
4218 if (next && GET_CODE (next) == INSN
4219 && prev_label (next_active_insn (next)) == target_label
4220 && simplejump_p (insn)
4221 && XVECLEN (pat, 0) == 2
4222 && rtx_equal_p (PATTERN (next), PATTERN (XVECEXP (pat, 0, 1))))
4228 /* See if this jump (with its delay slots) branches around another
4229 jump (without delay slots). If so, invert this jump and point
4230 it to the target of the second jump. We cannot do this for
4231 annulled jumps, though. Again, don't convert a jump to a RETURN
4233 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
4234 && next && GET_CODE (next) == JUMP_INSN
4235 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
4236 && next_active_insn (target_label) == next_active_insn (next)
4237 && no_labels_between_p (insn, next))
4239 rtx label = JUMP_LABEL (next);
4240 rtx old_label = JUMP_LABEL (delay_insn);
4243 label = find_end_label ();
4245 if (redirect_with_delay_slots_safe_p (delay_insn, label, insn))
4247 /* Be careful how we do this to avoid deleting code or labels
4248 that are momentarily dead. See similar optimization in
4251 ++LABEL_NUSES (old_label);
4253 if (invert_jump (delay_insn, label))
4257 /* Must update the INSN_FROM_TARGET_P bits now that
4258 the branch is reversed, so that mark_target_live_regs
4259 will handle the delay slot insn correctly. */
4260 for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
4262 rtx slot = XVECEXP (PATTERN (insn), 0, i);
4263 INSN_FROM_TARGET_P (slot) = ! INSN_FROM_TARGET_P (slot);
4270 if (old_label && --LABEL_NUSES (old_label) == 0)
4271 delete_insn (old_label);
4276 /* If we own the thread opposite the way this insn branches, see if we
4277 can merge its delay slots with following insns. */
4278 if (INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
4279 && own_thread_p (NEXT_INSN (insn), 0, 1))
4280 try_merge_delay_insns (insn, next);
4281 else if (! INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
4282 && own_thread_p (target_label, target_label, 0))
4283 try_merge_delay_insns (insn, next_active_insn (target_label));
4285 /* If we get here, we haven't deleted INSN. But we may have deleted
4286 NEXT, so recompute it. */
4287 next = next_active_insn (insn);
4293 /* Look for filled jumps to the end of function label. We can try to convert
4294 them into RETURN insns if the insns in the delay slot are valid for the
4298 make_return_insns (first)
4301 rtx insn, jump_insn, pat;
4302 rtx real_return_label = end_of_function_label;
4305 /* See if there is a RETURN insn in the function other than the one we
4306 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
4307 into a RETURN to jump to it. */
4308 for (insn = first; insn; insn = NEXT_INSN (insn))
4309 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) == RETURN)
4311 real_return_label = get_label_before (insn);
4315 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
4316 was equal to END_OF_FUNCTION_LABEL. */
4317 LABEL_NUSES (real_return_label)++;
4319 /* Clear the list of insns to fill so we can use it. */
4320 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
4322 for (insn = first; insn; insn = NEXT_INSN (insn))
4326 /* Only look at filled JUMP_INSNs that go to the end of function
4328 if (GET_CODE (insn) != INSN
4329 || GET_CODE (PATTERN (insn)) != SEQUENCE
4330 || GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
4331 || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label)
4334 pat = PATTERN (insn);
4335 jump_insn = XVECEXP (pat, 0, 0);
4337 /* If we can't make the jump into a RETURN, try to redirect it to the best
4338 RETURN and go on to the next insn. */
4339 if (! reorg_redirect_jump (jump_insn, NULL_RTX))
4341 /* Make sure redirecting the jump will not invalidate the delay
4343 if (redirect_with_delay_slots_safe_p (jump_insn,
4346 reorg_redirect_jump (jump_insn, real_return_label);
4350 /* See if this RETURN can accept the insns current in its delay slot.
4351 It can if it has more or an equal number of slots and the contents
4352 of each is valid. */
4354 flags = get_jump_flags (jump_insn, JUMP_LABEL (jump_insn));
4355 slots = num_delay_slots (jump_insn);
4356 if (slots >= XVECLEN (pat, 0) - 1)
4358 for (i = 1; i < XVECLEN (pat, 0); i++)
4360 #ifdef ANNUL_IFFALSE_SLOTS
4361 (INSN_ANNULLED_BRANCH_P (jump_insn)
4362 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
4363 ? eligible_for_annul_false (jump_insn, i - 1,
4364 XVECEXP (pat, 0, i), flags) :
4366 #ifdef ANNUL_IFTRUE_SLOTS
4367 (INSN_ANNULLED_BRANCH_P (jump_insn)
4368 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
4369 ? eligible_for_annul_true (jump_insn, i - 1,
4370 XVECEXP (pat, 0, i), flags) :
4372 eligible_for_delay (jump_insn, i -1, XVECEXP (pat, 0, i), flags)))
4378 if (i == XVECLEN (pat, 0))
4381 /* We have to do something with this insn. If it is an unconditional
4382 RETURN, delete the SEQUENCE and output the individual insns,
4383 followed by the RETURN. Then set things up so we try to find
4384 insns for its delay slots, if it needs some. */
4385 if (GET_CODE (PATTERN (jump_insn)) == RETURN)
4387 rtx prev = PREV_INSN (insn);
4390 for (i = 1; i < XVECLEN (pat, 0); i++)
4391 prev = emit_insn_after (PATTERN (XVECEXP (pat, 0, i)), prev);
4393 insn = emit_jump_insn_after (PATTERN (jump_insn), prev);
4394 emit_barrier_after (insn);
4397 obstack_ptr_grow (&unfilled_slots_obstack, insn);
4400 /* It is probably more efficient to keep this with its current
4401 delay slot as a branch to a RETURN. */
4402 reorg_redirect_jump (jump_insn, real_return_label);
4405 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
4406 new delay slots we have created. */
4407 if (--LABEL_NUSES (real_return_label) == 0)
4408 delete_insn (real_return_label);
4410 fill_simple_delay_slots (1);
4411 fill_simple_delay_slots (0);
4415 /* Try to find insns to place in delay slots. */
4418 dbr_schedule (first, file)
4422 rtx insn, next, epilogue_insn = 0;
4425 int old_flag_no_peephole = flag_no_peephole;
4427 /* Execute `final' once in prescan mode to delete any insns that won't be
4428 used. Don't let final try to do any peephole optimization--it will
4429 ruin dataflow information for this pass. */
4431 flag_no_peephole = 1;
4432 final (first, 0, NO_DEBUG, 1, 1);
4433 flag_no_peephole = old_flag_no_peephole;
4436 /* If the current function has no insns other than the prologue and
4437 epilogue, then do not try to fill any delay slots. */
4438 if (n_basic_blocks == 0)
4441 /* Find the highest INSN_UID and allocate and initialize our map from
4442 INSN_UID's to position in code. */
4443 for (max_uid = 0, insn = first; insn; insn = NEXT_INSN (insn))
4445 if (INSN_UID (insn) > max_uid)
4446 max_uid = INSN_UID (insn);
4447 if (GET_CODE (insn) == NOTE
4448 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG)
4449 epilogue_insn = insn;
4452 uid_to_ruid = (int *) alloca ((max_uid + 1) * sizeof (int *));
4453 for (i = 0, insn = first; insn; i++, insn = NEXT_INSN (insn))
4454 uid_to_ruid[INSN_UID (insn)] = i;
4456 /* Initialize the list of insns that need filling. */
4457 if (unfilled_firstobj == 0)
4459 gcc_obstack_init (&unfilled_slots_obstack);
4460 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4463 for (insn = next_active_insn (first); insn; insn = next_active_insn (insn))
4467 INSN_ANNULLED_BRANCH_P (insn) = 0;
4468 INSN_FROM_TARGET_P (insn) = 0;
4470 /* Skip vector tables. We can't get attributes for them. */
4471 if (GET_CODE (insn) == JUMP_INSN
4472 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
4473 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
4476 if (num_delay_slots (insn) > 0)
4477 obstack_ptr_grow (&unfilled_slots_obstack, insn);
4479 /* Ensure all jumps go to the last of a set of consecutive labels. */
4480 if (GET_CODE (insn) == JUMP_INSN
4481 && (condjump_p (insn) || condjump_in_parallel_p (insn))
4482 && JUMP_LABEL (insn) != 0
4483 && ((target = prev_label (next_active_insn (JUMP_LABEL (insn))))
4484 != JUMP_LABEL (insn)))
4485 redirect_jump (insn, target);
4488 /* Indicate what resources are required to be valid at the end of the current
4489 function. The condition code never is and memory always is. If the
4490 frame pointer is needed, it is and so is the stack pointer unless
4491 EXIT_IGNORE_STACK is non-zero. If the frame pointer is not needed, the
4492 stack pointer is. Registers used to return the function value are
4493 needed. Registers holding global variables are needed. */
4495 end_of_function_needs.cc = 0;
4496 end_of_function_needs.memory = 1;
4497 end_of_function_needs.unch_memory = 0;
4498 CLEAR_HARD_REG_SET (end_of_function_needs.regs);
4500 if (frame_pointer_needed)
4502 SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM);
4503 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
4504 SET_HARD_REG_BIT (end_of_function_needs.regs, HARD_FRAME_POINTER_REGNUM);
4506 #ifdef EXIT_IGNORE_STACK
4507 if (! EXIT_IGNORE_STACK)
4509 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4512 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4514 if (current_function_return_rtx != 0)
4515 mark_referenced_resources (current_function_return_rtx,
4516 &end_of_function_needs, 1);
4518 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4520 #ifdef EPILOGUE_USES
4521 || EPILOGUE_USES (i)
4524 SET_HARD_REG_BIT (end_of_function_needs.regs, i);
4526 /* The registers required to be live at the end of the function are
4527 represented in the flow information as being dead just prior to
4528 reaching the end of the function. For example, the return of a value
4529 might be represented by a USE of the return register immediately
4530 followed by an unconditional jump to the return label where the
4531 return label is the end of the RTL chain. The end of the RTL chain
4532 is then taken to mean that the return register is live.
4534 This sequence is no longer maintained when epilogue instructions are
4535 added to the RTL chain. To reconstruct the original meaning, the
4536 start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the
4537 point where these registers become live (start_of_epilogue_needs).
4538 If epilogue instructions are present, the registers set by those
4539 instructions won't have been processed by flow. Thus, those
4540 registers are additionally required at the end of the RTL chain
4541 (end_of_function_needs). */
4543 start_of_epilogue_needs = end_of_function_needs;
4545 while ((epilogue_insn = next_nonnote_insn (epilogue_insn)))
4546 mark_set_resources (epilogue_insn, &end_of_function_needs, 0, 1);
4548 /* Show we haven't computed an end-of-function label yet. */
4549 end_of_function_label = 0;
4551 /* Allocate and initialize the tables used by mark_target_live_regs. */
4553 = (struct target_info **) alloca ((TARGET_HASH_PRIME
4554 * sizeof (struct target_info *)));
4555 bzero ((char *) target_hash_table,
4556 TARGET_HASH_PRIME * sizeof (struct target_info *));
4558 bb_ticks = (int *) alloca (n_basic_blocks * sizeof (int));
4559 bzero ((char *) bb_ticks, n_basic_blocks * sizeof (int));
4561 /* Initialize the statistics for this function. */
4562 bzero ((char *) num_insns_needing_delays, sizeof num_insns_needing_delays);
4563 bzero ((char *) num_filled_delays, sizeof num_filled_delays);
4565 /* Now do the delay slot filling. Try everything twice in case earlier
4566 changes make more slots fillable. */
4568 for (reorg_pass_number = 0;
4569 reorg_pass_number < MAX_REORG_PASSES;
4570 reorg_pass_number++)
4572 fill_simple_delay_slots (1);
4573 fill_simple_delay_slots (0);
4574 fill_eager_delay_slots ();
4575 relax_delay_slots (first);
4578 /* Delete any USE insns made by update_block; subsequent passes don't need
4579 them or know how to deal with them. */
4580 for (insn = first; insn; insn = next)
4582 next = NEXT_INSN (insn);
4584 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
4585 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
4586 next = delete_insn (insn);
4589 /* If we made an end of function label, indicate that it is now
4590 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
4591 If it is now unused, delete it. */
4592 if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0)
4593 delete_insn (end_of_function_label);
4596 if (HAVE_return && end_of_function_label != 0)
4597 make_return_insns (first);
4600 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
4602 /* It is not clear why the line below is needed, but it does seem to be. */
4603 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4605 /* Reposition the prologue and epilogue notes in case we moved the
4606 prologue/epilogue insns. */
4607 reposition_prologue_and_epilogue_notes (first);
4611 register int i, j, need_comma;
4613 for (reorg_pass_number = 0;
4614 reorg_pass_number < MAX_REORG_PASSES;
4615 reorg_pass_number++)
4617 fprintf (file, ";; Reorg pass #%d:\n", reorg_pass_number + 1);
4618 for (i = 0; i < NUM_REORG_FUNCTIONS; i++)
4621 fprintf (file, ";; Reorg function #%d\n", i);
4623 fprintf (file, ";; %d insns needing delay slots\n;; ",
4624 num_insns_needing_delays[i][reorg_pass_number]);
4626 for (j = 0; j < MAX_DELAY_HISTOGRAM; j++)
4627 if (num_filled_delays[i][j][reorg_pass_number])
4630 fprintf (file, ", ");
4632 fprintf (file, "%d got %d delays",
4633 num_filled_delays[i][j][reorg_pass_number], j);
4635 fprintf (file, "\n");
4640 /* For all JUMP insns, fill in branch prediction notes, so that during
4641 assembler output a target can set branch prediction bits in the code.
4642 We have to do this now, as up until this point the destinations of
4643 JUMPS can be moved around and changed, but past right here that cannot
4645 for (insn = first; insn; insn = NEXT_INSN (insn))
4649 if (GET_CODE (insn) != JUMP_INSN)
4652 pred_flags = get_jump_flags (insn, JUMP_LABEL (insn));
4653 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_BR_PRED,
4654 GEN_INT (pred_flags),
4658 #endif /* DELAY_SLOTS */