1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS and AMD 29000 have a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The Motorola 88000 conditionally exposes its branch delay slot,
43 so code is shorter when it is turned off, but will run faster
44 when useful insns are scheduled there.
46 The IBM ROMP has two forms of branch and call insns, both with and
47 without a delay slot. Much like the 88k, insns not using the delay
48 slot can be shorted (2 bytes vs. 4 bytes), but will run slowed.
50 The SPARC always has a branch delay slot, but its effects can be
51 annulled when the branch is not taken. This means that failing to
52 find other sources of insns, we can hoist an insn from the branch
53 target that would only be safe to execute knowing that the branch
56 The HP-PA always has a branch delay slot. For unconditional branches
57 its effects can be annulled when the branch is taken. The effects
58 of the delay slot in a conditional branch can be nullified for forward
59 taken branches, or for untaken backward branches. This means
60 we can hoist insns from the fall-through path for forward branches or
61 steal insns from the target of backward branches.
63 Three techniques for filling delay slots have been implemented so far:
65 (1) `fill_simple_delay_slots' is the simplest, most efficient way
66 to fill delay slots. This pass first looks for insns which come
67 from before the branch and which are safe to execute after the
68 branch. Then it searches after the insn requiring delay slots or,
69 in the case of a branch, for insns that are after the point at
70 which the branch merges into the fallthrough code, if such a point
71 exists. When such insns are found, the branch penalty decreases
72 and no code expansion takes place.
74 (2) `fill_eager_delay_slots' is more complicated: it is used for
75 scheduling conditional jumps, or for scheduling jumps which cannot
76 be filled using (1). A machine need not have annulled jumps to use
77 this strategy, but it helps (by keeping more options open).
78 `fill_eager_delay_slots' tries to guess the direction the branch
79 will go; if it guesses right 100% of the time, it can reduce the
80 branch penalty as much as `fill_simple_delay_slots' does. If it
81 guesses wrong 100% of the time, it might as well schedule nops (or
82 on the m88k, unexpose the branch slot). When
83 `fill_eager_delay_slots' takes insns from the fall-through path of
84 the jump, usually there is no code expansion; when it takes insns
85 from the branch target, there is code expansion if it is not the
86 only way to reach that target.
88 (3) `relax_delay_slots' uses a set of rules to simplify code that
89 has been reorganized by (1) and (2). It finds cases where
90 conditional test can be eliminated, jumps can be threaded, extra
91 insns can be eliminated, etc. It is the job of (1) and (2) to do a
92 good job of scheduling locally; `relax_delay_slots' takes care of
93 making the various individual schedules work well together. It is
94 especially tuned to handle the control flow interactions of branch
95 insns. It does nothing for insns with delay slots that do not
98 On machines that use CC0, we are very conservative. We will not make
99 a copy of an insn involving CC0 since we want to maintain a 1-1
100 correspondence between the insn that sets and uses CC0. The insns are
101 allowed to be separated by placing an insn that sets CC0 (but not an insn
102 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
103 delay slot. In that case, we point each insn at the other with REG_CC_USER
104 and REG_CC_SETTER notes. Note that these restrictions affect very few
105 machines because most RISC machines with delay slots will not use CC0
106 (the RT is the only known exception at this point).
110 The Acorn Risc Machine can conditionally execute most insns, so
111 it is profitable to move single insns into a position to execute
112 based on the condition code of the previous insn.
114 The HP-PA can conditionally nullify insns, providing a similar
115 effect to the ARM, differing mostly in which insn is "in charge". */
120 #include "insn-config.h"
121 #include "conditions.h"
122 #include "hard-reg-set.h"
123 #include "basic-block.h"
125 #include "insn-flags.h"
130 #include "insn-attr.h"
134 #define obstack_chunk_alloc xmalloc
135 #define obstack_chunk_free free
137 #ifndef ANNUL_IFTRUE_SLOTS
138 #define eligible_for_annul_true(INSN, SLOTS, TRIAL, FLAGS) 0
140 #ifndef ANNUL_IFFALSE_SLOTS
141 #define eligible_for_annul_false(INSN, SLOTS, TRIAL, FLAGS) 0
144 /* Insns which have delay slots that have not yet been filled. */
146 static struct obstack unfilled_slots_obstack;
147 static rtx *unfilled_firstobj;
149 /* Define macros to refer to the first and last slot containing unfilled
150 insns. These are used because the list may move and its address
151 should be recomputed at each use. */
153 #define unfilled_slots_base \
154 ((rtx *) obstack_base (&unfilled_slots_obstack))
156 #define unfilled_slots_next \
157 ((rtx *) obstack_next_free (&unfilled_slots_obstack))
159 /* This structure is used to indicate which hardware resources are set or
160 needed by insns so far. */
164 char memory; /* Insn sets or needs a memory location. */
165 char volatil; /* Insn sets or needs a volatile memory loc. */
166 char cc; /* Insn sets or needs the condition codes. */
167 HARD_REG_SET regs; /* Which registers are set or needed. */
170 /* Macro to clear all resources. */
171 #define CLEAR_RESOURCE(RES) \
172 do { (RES)->memory = (RES)->volatil = (RES)->cc = 0; \
173 CLEAR_HARD_REG_SET ((RES)->regs); } while (0)
175 /* Indicates what resources are required at the beginning of the epilogue. */
176 static struct resources start_of_epilogue_needs;
178 /* Indicates what resources are required at function end. */
179 static struct resources end_of_function_needs;
181 /* Points to the label before the end of the function. */
182 static rtx end_of_function_label;
184 /* This structure is used to record liveness information at the targets or
185 fallthrough insns of branches. We will most likely need the information
186 at targets again, so save them in a hash table rather than recomputing them
191 int uid; /* INSN_UID of target. */
192 struct target_info *next; /* Next info for same hash bucket. */
193 HARD_REG_SET live_regs; /* Registers live at target. */
194 int block; /* Basic block number containing target. */
195 int bb_tick; /* Generation count of basic block info. */
198 #define TARGET_HASH_PRIME 257
200 /* Define the hash table itself. */
201 static struct target_info **target_hash_table;
203 /* For each basic block, we maintain a generation number of its basic
204 block info, which is updated each time we move an insn from the
205 target of a jump. This is the generation number indexed by block
208 static int *bb_ticks;
210 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
211 not always monotonically increase. */
212 static int *uid_to_ruid;
214 /* Highest valid index in `uid_to_ruid'. */
217 static void mark_referenced_resources PROTO((rtx, struct resources *, int));
218 static void mark_set_resources PROTO((rtx, struct resources *, int, int));
219 static int stop_search_p PROTO((rtx, int));
220 static int resource_conflicts_p PROTO((struct resources *,
221 struct resources *));
222 static int insn_references_resource_p PROTO((rtx, struct resources *, int));
223 static int insn_sets_resources_p PROTO((rtx, struct resources *, int));
224 static rtx find_end_label PROTO((void));
225 static rtx emit_delay_sequence PROTO((rtx, rtx, int, int));
226 static rtx add_to_delay_list PROTO((rtx, rtx));
227 static void delete_from_delay_slot PROTO((rtx));
228 static void delete_scheduled_jump PROTO((rtx));
229 static void note_delay_statistics PROTO((int, int));
230 static rtx optimize_skip PROTO((rtx));
231 static int get_jump_flags PROTO((rtx, rtx));
232 static int rare_destination PROTO((rtx));
233 static int mostly_true_jump PROTO((rtx, rtx));
234 static rtx get_branch_condition PROTO((rtx, rtx));
235 static int condition_dominates_p PROTO((rtx, rtx));
236 static rtx steal_delay_list_from_target PROTO((rtx, rtx, rtx, rtx,
240 int, int *, int *, rtx *));
241 static rtx steal_delay_list_from_fallthrough PROTO((rtx, rtx, rtx, rtx,
246 static void try_merge_delay_insns PROTO((rtx, rtx));
247 static int redundant_insn_p PROTO((rtx, rtx, rtx));
248 static int own_thread_p PROTO((rtx, rtx, int));
249 static int find_basic_block PROTO((rtx));
250 static void update_block PROTO((rtx, rtx));
251 static int reorg_redirect_jump PROTO((rtx, rtx));
252 static void update_reg_dead_notes PROTO((rtx, rtx));
253 static void update_live_status PROTO((rtx, rtx));
254 static rtx next_insn_no_annul PROTO((rtx));
255 static void mark_target_live_regs PROTO((rtx, struct resources *));
256 static void fill_simple_delay_slots PROTO((rtx, int));
257 static rtx fill_slots_from_thread PROTO((rtx, rtx, rtx, rtx, int, int,
258 int, int, int, int *));
259 static void fill_eager_delay_slots PROTO((rtx));
260 static void relax_delay_slots PROTO((rtx));
261 static void make_return_insns PROTO((rtx));
262 static int redirect_with_delay_slots_safe_p PROTO ((rtx, rtx, rtx));
263 static int redirect_with_delay_list_safe_p PROTO ((rtx, rtx, rtx));
265 /* Given X, some rtl, and RES, a pointer to a `struct resource', mark
266 which resources are references by the insn. If INCLUDE_CALLED_ROUTINE
267 is TRUE, resources used by the called routine will be included for
271 mark_referenced_resources (x, res, include_delayed_effects)
273 register struct resources *res;
274 register int include_delayed_effects;
276 register enum rtx_code code = GET_CODE (x);
278 register char *format_ptr;
280 /* Handle leaf items for which we set resource flags. Also, special-case
281 CALL, SET and CLOBBER operators. */
293 if (GET_CODE (SUBREG_REG (x)) != REG)
294 mark_referenced_resources (SUBREG_REG (x), res, 0);
297 int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
298 int last_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
299 for (i = regno; i < last_regno; i++)
300 SET_HARD_REG_BIT (res->regs, i);
305 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
306 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
310 /* If this memory shouldn't change, it really isn't referencing
312 if (! RTX_UNCHANGING_P (x))
314 res->volatil = MEM_VOLATILE_P (x);
316 /* Mark registers used to access memory. */
317 mark_referenced_resources (XEXP (x, 0), res, 0);
324 case UNSPEC_VOLATILE:
326 /* Traditional asm's are always volatile. */
331 res->volatil = MEM_VOLATILE_P (x);
333 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
334 We can not just fall through here since then we would be confused
335 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
336 traditional asms unlike their normal usage. */
338 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
339 mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, 0);
343 /* The first operand will be a (MEM (xxx)) but doesn't really reference
344 memory. The second operand may be referenced, though. */
345 mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, 0);
346 mark_referenced_resources (XEXP (x, 1), res, 0);
350 /* Usually, the first operand of SET is set, not referenced. But
351 registers used to access memory are referenced. SET_DEST is
352 also referenced if it is a ZERO_EXTRACT or SIGN_EXTRACT. */
354 mark_referenced_resources (SET_SRC (x), res, 0);
357 if (GET_CODE (x) == SIGN_EXTRACT || GET_CODE (x) == ZERO_EXTRACT)
358 mark_referenced_resources (x, res, 0);
359 else if (GET_CODE (x) == SUBREG)
361 if (GET_CODE (x) == MEM)
362 mark_referenced_resources (XEXP (x, 0), res, 0);
369 if (include_delayed_effects)
371 /* A CALL references memory, the frame pointer if it exists, the
372 stack pointer, any global registers and any registers given in
373 USE insns immediately in front of the CALL.
375 However, we may have moved some of the parameter loading insns
376 into the delay slot of this CALL. If so, the USE's for them
377 don't count and should be skipped. */
378 rtx insn = PREV_INSN (x);
383 /* If we are part of a delay slot sequence, point at the SEQUENCE. */
384 if (NEXT_INSN (insn) != x)
386 sequence = PATTERN (NEXT_INSN (insn));
387 seq_size = XVECLEN (sequence, 0);
388 if (GET_CODE (sequence) != SEQUENCE)
393 SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM);
394 if (frame_pointer_needed)
396 SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM);
397 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
398 SET_HARD_REG_BIT (res->regs, HARD_FRAME_POINTER_REGNUM);
402 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
404 SET_HARD_REG_BIT (res->regs, i);
409 for (link = CALL_INSN_FUNCTION_USAGE (insn);
411 link = XEXP (link, 1))
412 if (GET_CODE (XEXP (link, 0)) == USE)
414 for (i = 1; i < seq_size; i++)
416 rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i));
417 if (GET_CODE (slot_pat) == SET
418 && rtx_equal_p (SET_DEST (slot_pat),
419 SET_DEST (XEXP (link, 0))))
423 mark_referenced_resources (SET_DEST (XEXP (link, 0)),
429 /* ... fall through to other INSN processing ... */
434 #ifdef INSN_REFERENCES_ARE_DELAYED
435 if (! include_delayed_effects
436 && INSN_REFERENCES_ARE_DELAYED (x))
440 /* No special processing, just speed up. */
441 mark_referenced_resources (PATTERN (x), res, include_delayed_effects);
445 /* Process each sub-expression and flag what it needs. */
446 format_ptr = GET_RTX_FORMAT (code);
447 for (i = 0; i < GET_RTX_LENGTH (code); i++)
448 switch (*format_ptr++)
451 mark_referenced_resources (XEXP (x, i), res, include_delayed_effects);
455 for (j = 0; j < XVECLEN (x, i); j++)
456 mark_referenced_resources (XVECEXP (x, i, j), res,
457 include_delayed_effects);
462 /* Given X, a part of an insn, and a pointer to a `struct resource', RES,
463 indicate which resources are modified by the insn. If INCLUDE_CALLED_ROUTINE
464 is nonzero, also mark resources potentially set by the called routine.
466 If IN_DEST is nonzero, it means we are inside a SET. Otherwise,
467 objects are being referenced instead of set.
469 We never mark the insn as modifying the condition code unless it explicitly
470 SETs CC0 even though this is not totally correct. The reason for this is
471 that we require a SET of CC0 to immediately precede the reference to CC0.
472 So if some other insn sets CC0 as a side-effect, we know it cannot affect
473 our computation and thus may be placed in a delay slot. */
476 mark_set_resources (x, res, in_dest, include_delayed_effects)
478 register struct resources *res;
480 int include_delayed_effects;
482 register enum rtx_code code;
484 register char *format_ptr;
502 /* These don't set any resources. */
511 /* Called routine modifies the condition code, memory, any registers
512 that aren't saved across calls, global registers and anything
513 explicitly CLOBBERed immediately after the CALL_INSN. */
515 if (include_delayed_effects)
517 rtx next = NEXT_INSN (x);
518 rtx prev = PREV_INSN (x);
521 res->cc = res->memory = 1;
522 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
523 if (call_used_regs[i] || global_regs[i])
524 SET_HARD_REG_BIT (res->regs, i);
526 /* If X is part of a delay slot sequence, then NEXT should be
527 the first insn after the sequence. */
528 if (NEXT_INSN (prev) != x)
529 next = NEXT_INSN (NEXT_INSN (prev));
531 for (link = CALL_INSN_FUNCTION_USAGE (x);
532 link; link = XEXP (link, 1))
533 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
534 mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, 0);
536 /* Check for a NOTE_INSN_SETJMP. If it exists, then we must
537 assume that this call can clobber any register. */
538 if (next && GET_CODE (next) == NOTE
539 && NOTE_LINE_NUMBER (next) == NOTE_INSN_SETJMP)
540 SET_HARD_REG_SET (res->regs);
543 /* ... and also what it's RTL says it modifies, if anything. */
548 /* An insn consisting of just a CLOBBER (or USE) is just for flow
549 and doesn't actually do anything, so we ignore it. */
551 #ifdef INSN_SETS_ARE_DELAYED
552 if (! include_delayed_effects
553 && INSN_SETS_ARE_DELAYED (x))
558 if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER)
563 /* If the source of a SET is a CALL, this is actually done by
564 the called routine. So only include it if we are to include the
565 effects of the calling routine. */
567 mark_set_resources (SET_DEST (x), res,
568 (include_delayed_effects
569 || GET_CODE (SET_SRC (x)) != CALL),
572 mark_set_resources (SET_SRC (x), res, 0, 0);
576 mark_set_resources (XEXP (x, 0), res, 1, 0);
580 for (i = 0; i < XVECLEN (x, 0); i++)
581 if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0))
582 && INSN_FROM_TARGET_P (XVECEXP (x, 0, i))))
583 mark_set_resources (XVECEXP (x, 0, i), res, 0,
584 include_delayed_effects);
591 mark_set_resources (XEXP (x, 0), res, 1, 0);
595 mark_set_resources (XEXP (x, 0), res, in_dest, 0);
596 mark_set_resources (XEXP (x, 1), res, 0, 0);
597 mark_set_resources (XEXP (x, 2), res, 0, 0);
604 res->volatil = MEM_VOLATILE_P (x);
607 mark_set_resources (XEXP (x, 0), res, 0, 0);
612 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
613 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
617 /* Process each sub-expression and flag what it needs. */
618 format_ptr = GET_RTX_FORMAT (code);
619 for (i = 0; i < GET_RTX_LENGTH (code); i++)
620 switch (*format_ptr++)
623 mark_set_resources (XEXP (x, i), res, in_dest, include_delayed_effects);
627 for (j = 0; j < XVECLEN (x, i); j++)
628 mark_set_resources (XVECEXP (x, i, j), res, in_dest,
629 include_delayed_effects);
634 /* Return TRUE if this insn should stop the search for insn to fill delay
635 slots. LABELS_P indicates that labels should terminate the search.
636 In all cases, jumps terminate the search. */
639 stop_search_p (insn, labels_p)
646 switch (GET_CODE (insn))
660 /* OK unless it contains a delay slot or is an `asm' insn of some type.
661 We don't know anything about these. */
662 return (GET_CODE (PATTERN (insn)) == SEQUENCE
663 || GET_CODE (PATTERN (insn)) == ASM_INPUT
664 || asm_noperands (PATTERN (insn)) >= 0);
671 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
672 resource set contains a volatile memory reference. Otherwise, return FALSE. */
675 resource_conflicts_p (res1, res2)
676 struct resources *res1, *res2;
678 if ((res1->cc && res2->cc) || (res1->memory && res2->memory)
679 || res1->volatil || res2->volatil)
683 return (res1->regs & res2->regs) != HARD_CONST (0);
688 for (i = 0; i < HARD_REG_SET_LONGS; i++)
689 if ((res1->regs[i] & res2->regs[i]) != 0)
696 /* Return TRUE if any resource marked in RES, a `struct resources', is
697 referenced by INSN. If INCLUDE_CALLED_ROUTINE is set, return if the called
698 routine is using those resources.
700 We compute this by computing all the resources referenced by INSN and
701 seeing if this conflicts with RES. It might be faster to directly check
702 ourselves, and this is the way it used to work, but it means duplicating
703 a large block of complex code. */
706 insn_references_resource_p (insn, res, include_delayed_effects)
708 register struct resources *res;
709 int include_delayed_effects;
711 struct resources insn_res;
713 CLEAR_RESOURCE (&insn_res);
714 mark_referenced_resources (insn, &insn_res, include_delayed_effects);
715 return resource_conflicts_p (&insn_res, res);
718 /* Return TRUE if INSN modifies resources that are marked in RES.
719 INCLUDE_CALLED_ROUTINE is set if the actions of that routine should be
720 included. CC0 is only modified if it is explicitly set; see comments
721 in front of mark_set_resources for details. */
724 insn_sets_resource_p (insn, res, include_delayed_effects)
726 register struct resources *res;
727 int include_delayed_effects;
729 struct resources insn_sets;
731 CLEAR_RESOURCE (&insn_sets);
732 mark_set_resources (insn, &insn_sets, 0, include_delayed_effects);
733 return resource_conflicts_p (&insn_sets, res);
736 /* Find a label at the end of the function or before a RETURN. If there is
744 /* If we found one previously, return it. */
745 if (end_of_function_label)
746 return end_of_function_label;
748 /* Otherwise, see if there is a label at the end of the function. If there
749 is, it must be that RETURN insns aren't needed, so that is our return
750 label and we don't have to do anything else. */
752 insn = get_last_insn ();
753 while (GET_CODE (insn) == NOTE
754 || (GET_CODE (insn) == INSN
755 && (GET_CODE (PATTERN (insn)) == USE
756 || GET_CODE (PATTERN (insn)) == CLOBBER)))
757 insn = PREV_INSN (insn);
759 /* When a target threads its epilogue we might already have a
760 suitable return insn. If so put a label before it for the
761 end_of_function_label. */
762 if (GET_CODE (insn) == BARRIER
763 && GET_CODE (PREV_INSN (insn)) == JUMP_INSN
764 && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN)
766 rtx temp = PREV_INSN (PREV_INSN (insn));
767 end_of_function_label = gen_label_rtx ();
768 LABEL_NUSES (end_of_function_label) = 0;
770 /* Put the label before an USE insns that may proceed the RETURN insn. */
771 while (GET_CODE (temp) == USE)
772 temp = PREV_INSN (temp);
774 emit_label_after (end_of_function_label, temp);
777 else if (GET_CODE (insn) == CODE_LABEL)
778 end_of_function_label = insn;
781 /* Otherwise, make a new label and emit a RETURN and BARRIER,
783 end_of_function_label = gen_label_rtx ();
784 LABEL_NUSES (end_of_function_label) = 0;
785 emit_label (end_of_function_label);
789 /* The return we make may have delay slots too. */
790 rtx insn = gen_return ();
791 insn = emit_jump_insn (insn);
793 if (num_delay_slots (insn) > 0)
794 obstack_ptr_grow (&unfilled_slots_obstack, insn);
799 /* Show one additional use for this label so it won't go away until
801 ++LABEL_NUSES (end_of_function_label);
803 return end_of_function_label;
806 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
807 the pattern of INSN with the SEQUENCE.
809 Chain the insns so that NEXT_INSN of each insn in the sequence points to
810 the next and NEXT_INSN of the last insn in the sequence points to
811 the first insn after the sequence. Similarly for PREV_INSN. This makes
812 it easier to scan all insns.
814 Returns the SEQUENCE that replaces INSN. */
817 emit_delay_sequence (insn, list, length, avail)
827 /* Allocate the the rtvec to hold the insns and the SEQUENCE. */
828 rtvec seqv = rtvec_alloc (length + 1);
829 rtx seq = gen_rtx (SEQUENCE, VOIDmode, seqv);
830 rtx seq_insn = make_insn_raw (seq);
831 rtx first = get_insns ();
832 rtx last = get_last_insn ();
834 /* Make a copy of the insn having delay slots. */
835 rtx delay_insn = copy_rtx (insn);
837 /* If INSN is followed by a BARRIER, delete the BARRIER since it will only
838 confuse further processing. Update LAST in case it was the last insn.
839 We will put the BARRIER back in later. */
840 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == BARRIER)
842 delete_insn (NEXT_INSN (insn));
843 last = get_last_insn ();
847 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
848 NEXT_INSN (seq_insn) = NEXT_INSN (insn);
849 PREV_INSN (seq_insn) = PREV_INSN (insn);
852 set_new_first_and_last_insn (first, seq_insn);
854 PREV_INSN (NEXT_INSN (seq_insn)) = seq_insn;
857 set_new_first_and_last_insn (seq_insn, last);
859 NEXT_INSN (PREV_INSN (seq_insn)) = seq_insn;
861 /* Build our SEQUENCE and rebuild the insn chain. */
862 XVECEXP (seq, 0, 0) = delay_insn;
863 INSN_DELETED_P (delay_insn) = 0;
864 PREV_INSN (delay_insn) = PREV_INSN (seq_insn);
866 for (li = list; li; li = XEXP (li, 1), i++)
868 rtx tem = XEXP (li, 0);
871 /* Show that this copy of the insn isn't deleted. */
872 INSN_DELETED_P (tem) = 0;
874 XVECEXP (seq, 0, i) = tem;
875 PREV_INSN (tem) = XVECEXP (seq, 0, i - 1);
876 NEXT_INSN (XVECEXP (seq, 0, i - 1)) = tem;
878 /* Remove any REG_DEAD notes because we can't rely on them now
879 that the insn has been moved. */
880 for (note = REG_NOTES (tem); note; note = XEXP (note, 1))
881 if (REG_NOTE_KIND (note) == REG_DEAD)
882 XEXP (note, 0) = const0_rtx;
885 NEXT_INSN (XVECEXP (seq, 0, length)) = NEXT_INSN (seq_insn);
887 /* If the previous insn is a SEQUENCE, update the NEXT_INSN pointer on the
888 last insn in that SEQUENCE to point to us. Similarly for the first
889 insn in the following insn if it is a SEQUENCE. */
891 if (PREV_INSN (seq_insn) && GET_CODE (PREV_INSN (seq_insn)) == INSN
892 && GET_CODE (PATTERN (PREV_INSN (seq_insn))) == SEQUENCE)
893 NEXT_INSN (XVECEXP (PATTERN (PREV_INSN (seq_insn)), 0,
894 XVECLEN (PATTERN (PREV_INSN (seq_insn)), 0) - 1))
897 if (NEXT_INSN (seq_insn) && GET_CODE (NEXT_INSN (seq_insn)) == INSN
898 && GET_CODE (PATTERN (NEXT_INSN (seq_insn))) == SEQUENCE)
899 PREV_INSN (XVECEXP (PATTERN (NEXT_INSN (seq_insn)), 0, 0)) = seq_insn;
901 /* If there used to be a BARRIER, put it back. */
903 emit_barrier_after (seq_insn);
911 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
912 be in the order in which the insns are to be executed. */
915 add_to_delay_list (insn, delay_list)
919 /* If we have an empty list, just make a new list element. If
920 INSN has it's block number recorded, clear it since we may
921 be moving the insn to a new block. */
925 struct target_info *tinfo;
927 for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME];
928 tinfo; tinfo = tinfo->next)
929 if (tinfo->uid == INSN_UID (insn))
935 return gen_rtx (INSN_LIST, VOIDmode, insn, NULL_RTX);
938 /* Otherwise this must be an INSN_LIST. Add INSN to the end of the
940 XEXP (delay_list, 1) = add_to_delay_list (insn, XEXP (delay_list, 1));
945 /* Delete INSN from the the delay slot of the insn that it is in. This may
946 produce an insn without anything in its delay slots. */
949 delete_from_delay_slot (insn)
952 rtx trial, seq_insn, seq, prev;
956 /* We first must find the insn containing the SEQUENCE with INSN in its
957 delay slot. Do this by finding an insn, TRIAL, where
958 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
961 PREV_INSN (NEXT_INSN (trial)) == trial;
962 trial = NEXT_INSN (trial))
965 seq_insn = PREV_INSN (NEXT_INSN (trial));
966 seq = PATTERN (seq_insn);
968 /* Create a delay list consisting of all the insns other than the one
969 we are deleting (unless we were the only one). */
970 if (XVECLEN (seq, 0) > 2)
971 for (i = 1; i < XVECLEN (seq, 0); i++)
972 if (XVECEXP (seq, 0, i) != insn)
973 delay_list = add_to_delay_list (XVECEXP (seq, 0, i), delay_list);
975 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
976 list, and rebuild the delay list if non-empty. */
977 prev = PREV_INSN (seq_insn);
978 trial = XVECEXP (seq, 0, 0);
979 delete_insn (seq_insn);
980 add_insn_after (trial, prev);
982 if (GET_CODE (trial) == JUMP_INSN
983 && (simplejump_p (trial) || GET_CODE (PATTERN (trial)) == RETURN))
984 emit_barrier_after (trial);
986 /* If there are any delay insns, remit them. Otherwise clear the
989 trial = emit_delay_sequence (trial, delay_list, XVECLEN (seq, 0) - 2, 0);
991 INSN_ANNULLED_BRANCH_P (trial) = 0;
993 INSN_FROM_TARGET_P (insn) = 0;
995 /* Show we need to fill this insn again. */
996 obstack_ptr_grow (&unfilled_slots_obstack, trial);
999 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
1000 the insn that sets CC0 for it and delete it too. */
1003 delete_scheduled_jump (insn)
1006 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
1007 delete the insn that sets the condition code, but it is hard to find it.
1008 Since this case is rare anyway, don't bother trying; there would likely
1009 be other insns that became dead anyway, which we wouldn't know to
1013 if (reg_mentioned_p (cc0_rtx, insn))
1015 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
1017 /* If a reg-note was found, it points to an insn to set CC0. This
1018 insn is in the delay list of some other insn. So delete it from
1019 the delay list it was in. */
1022 if (! FIND_REG_INC_NOTE (XEXP (note, 0), NULL_RTX)
1023 && sets_cc0_p (PATTERN (XEXP (note, 0))) == 1)
1024 delete_from_delay_slot (XEXP (note, 0));
1028 /* The insn setting CC0 is our previous insn, but it may be in
1029 a delay slot. It will be the last insn in the delay slot, if
1031 rtx trial = previous_insn (insn);
1032 if (GET_CODE (trial) == NOTE)
1033 trial = prev_nonnote_insn (trial);
1034 if (sets_cc0_p (PATTERN (trial)) != 1
1035 || FIND_REG_INC_NOTE (trial, 0))
1037 if (PREV_INSN (NEXT_INSN (trial)) == trial)
1038 delete_insn (trial);
1040 delete_from_delay_slot (trial);
1048 /* Counters for delay-slot filling. */
1050 #define NUM_REORG_FUNCTIONS 2
1051 #define MAX_DELAY_HISTOGRAM 3
1052 #define MAX_REORG_PASSES 2
1054 static int num_insns_needing_delays[NUM_REORG_FUNCTIONS][MAX_REORG_PASSES];
1056 static int num_filled_delays[NUM_REORG_FUNCTIONS][MAX_DELAY_HISTOGRAM+1][MAX_REORG_PASSES];
1058 static int reorg_pass_number;
1061 note_delay_statistics (slots_filled, index)
1062 int slots_filled, index;
1064 num_insns_needing_delays[index][reorg_pass_number]++;
1065 if (slots_filled > MAX_DELAY_HISTOGRAM)
1066 slots_filled = MAX_DELAY_HISTOGRAM;
1067 num_filled_delays[index][slots_filled][reorg_pass_number]++;
1070 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
1072 /* Optimize the following cases:
1074 1. When a conditional branch skips over only one instruction,
1075 use an annulling branch and put that insn in the delay slot.
1076 Use either a branch that annuls when the condition if true or
1077 invert the test with a branch that annuls when the condition is
1078 false. This saves insns, since otherwise we must copy an insn
1081 (orig) (skip) (otherwise)
1082 Bcc.n L1 Bcc',a L1 Bcc,a L1'
1089 2. When a conditional branch skips over only one instruction,
1090 and after that, it unconditionally branches somewhere else,
1091 perform the similar optimization. This saves executing the
1092 second branch in the case where the inverted condition is true.
1099 INSN is a JUMP_INSN.
1101 This should be expanded to skip over N insns, where N is the number
1102 of delay slots required. */
1105 optimize_skip (insn)
1108 register rtx trial = next_nonnote_insn (insn);
1109 rtx next_trial = next_active_insn (trial);
1114 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1117 || GET_CODE (trial) != INSN
1118 || GET_CODE (PATTERN (trial)) == SEQUENCE
1119 || recog_memoized (trial) < 0
1120 || (! eligible_for_annul_false (insn, 0, trial, flags)
1121 && ! eligible_for_annul_true (insn, 0, trial, flags)))
1124 /* There are two cases where we are just executing one insn (we assume
1125 here that a branch requires only one insn; this should be generalized
1126 at some point): Where the branch goes around a single insn or where
1127 we have one insn followed by a branch to the same label we branch to.
1128 In both of these cases, inverting the jump and annulling the delay
1129 slot give the same effect in fewer insns. */
1130 if ((next_trial == next_active_insn (JUMP_LABEL (insn)))
1132 && GET_CODE (next_trial) == JUMP_INSN
1133 && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)
1134 && (simplejump_p (next_trial)
1135 || GET_CODE (PATTERN (next_trial)) == RETURN)))
1137 if (eligible_for_annul_false (insn, 0, trial, flags))
1139 if (invert_jump (insn, JUMP_LABEL (insn)))
1140 INSN_FROM_TARGET_P (trial) = 1;
1141 else if (! eligible_for_annul_true (insn, 0, trial, flags))
1145 delay_list = add_to_delay_list (trial, NULL_RTX);
1146 next_trial = next_active_insn (trial);
1147 update_block (trial, trial);
1148 delete_insn (trial);
1150 /* Also, if we are targeting an unconditional
1151 branch, thread our jump to the target of that branch. Don't
1152 change this into a RETURN here, because it may not accept what
1153 we have in the delay slot. We'll fix this up later. */
1154 if (next_trial && GET_CODE (next_trial) == JUMP_INSN
1155 && (simplejump_p (next_trial)
1156 || GET_CODE (PATTERN (next_trial)) == RETURN))
1158 target_label = JUMP_LABEL (next_trial);
1159 if (target_label == 0)
1160 target_label = find_end_label ();
1162 /* Recompute the flags based on TARGET_LABEL since threading
1163 the jump to TARGET_LABEL may change the direction of the
1164 jump (which may change the circumstances in which the
1165 delay slot is nullified). */
1166 flags = get_jump_flags (insn, target_label);
1167 if (eligible_for_annul_true (insn, 0, trial, flags))
1168 reorg_redirect_jump (insn, target_label);
1171 INSN_ANNULLED_BRANCH_P (insn) = 1;
1179 /* Encode and return branch direction and prediction information for
1180 INSN assuming it will jump to LABEL.
1182 Non conditional branches return no direction information and
1183 are predicted as very likely taken. */
1185 get_jump_flags (insn, label)
1190 /* get_jump_flags can be passed any insn with delay slots, these may
1191 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
1192 direction information, and only if they are conditional jumps.
1194 If LABEL is zero, then there is no way to determine the branch
1196 if (GET_CODE (insn) == JUMP_INSN
1197 && condjump_p (insn)
1198 && INSN_UID (insn) <= max_uid
1200 && INSN_UID (label) <= max_uid)
1202 = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)])
1203 ? ATTR_FLAG_forward : ATTR_FLAG_backward;
1204 /* No valid direction information. */
1208 /* If insn is a conditional branch call mostly_true_jump to get
1209 determine the branch prediction.
1211 Non conditional branches are predicted as very likely taken. */
1212 if (GET_CODE (insn) == JUMP_INSN
1213 && condjump_p (insn))
1217 prediction = mostly_true_jump (insn, get_branch_condition (insn, label));
1221 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1224 flags |= ATTR_FLAG_likely;
1227 flags |= ATTR_FLAG_unlikely;
1230 flags |= (ATTR_FLAG_very_unlikely | ATTR_FLAG_unlikely);
1238 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1243 /* Return 1 if INSN is a destination that will be branched to rarely (the
1244 return point of a function); return 2 if DEST will be branched to very
1245 rarely (a call to a function that doesn't return). Otherwise,
1249 rare_destination (insn)
1255 for (; insn; insn = next)
1257 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
1258 insn = XVECEXP (PATTERN (insn), 0, 0);
1260 next = NEXT_INSN (insn);
1262 switch (GET_CODE (insn))
1267 /* A BARRIER can either be after a JUMP_INSN or a CALL_INSN. We
1268 don't scan past JUMP_INSNs, so any barrier we find here must
1269 have been after a CALL_INSN and hence mean the call doesn't
1273 if (GET_CODE (PATTERN (insn)) == RETURN)
1275 else if (simplejump_p (insn)
1276 && jump_count++ < 10)
1277 next = JUMP_LABEL (insn);
1283 /* If we got here it means we hit the end of the function. So this
1284 is an unlikely destination. */
1289 /* Return truth value of the statement that this branch
1290 is mostly taken. If we think that the branch is extremely likely
1291 to be taken, we return 2. If the branch is slightly more likely to be
1292 taken, return 1. If the branch is slightly less likely to be taken,
1293 return 0 and if the branch is highly unlikely to be taken, return -1.
1295 CONDITION, if non-zero, is the condition that JUMP_INSN is testing. */
1298 mostly_true_jump (jump_insn, condition)
1299 rtx jump_insn, condition;
1301 rtx target_label = JUMP_LABEL (jump_insn);
1303 int rare_dest = rare_destination (target_label);
1304 int rare_fallthrough = rare_destination (NEXT_INSN (jump_insn));
1306 /* If this is a branch outside a loop, it is highly unlikely. */
1307 if (GET_CODE (PATTERN (jump_insn)) == SET
1308 && GET_CODE (SET_SRC (PATTERN (jump_insn))) == IF_THEN_ELSE
1309 && ((GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 1)) == LABEL_REF
1310 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 1)))
1311 || (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 2)) == LABEL_REF
1312 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 2)))))
1317 /* If this is the test of a loop, it is very likely true. We scan
1318 backwards from the target label. If we find a NOTE_INSN_LOOP_BEG
1319 before the next real insn, we assume the branch is to the top of
1321 for (insn = PREV_INSN (target_label);
1322 insn && GET_CODE (insn) == NOTE;
1323 insn = PREV_INSN (insn))
1324 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1327 /* If this is a jump to the test of a loop, it is likely true. We scan
1328 forwards from the target label. If we find a NOTE_INSN_LOOP_VTOP
1329 before the next real insn, we assume the branch is to the loop branch
1331 for (insn = NEXT_INSN (target_label);
1332 insn && GET_CODE (insn) == NOTE;
1333 insn = PREV_INSN (insn))
1334 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_VTOP)
1338 /* Look at the relative rarities of the fallthough and destination. If
1339 they differ, we can predict the branch that way. */
1341 switch (rare_fallthrough - rare_dest)
1355 /* If we couldn't figure out what this jump was, assume it won't be
1356 taken. This should be rare. */
1360 /* EQ tests are usually false and NE tests are usually true. Also,
1361 most quantities are positive, so we can make the appropriate guesses
1362 about signed comparisons against zero. */
1363 switch (GET_CODE (condition))
1366 /* Unconditional branch. */
1374 if (XEXP (condition, 1) == const0_rtx)
1379 if (XEXP (condition, 1) == const0_rtx)
1384 /* Predict backward branches usually take, forward branches usually not. If
1385 we don't know whether this is forward or backward, assume the branch
1386 will be taken, since most are. */
1387 return (target_label == 0 || INSN_UID (jump_insn) > max_uid
1388 || INSN_UID (target_label) > max_uid
1389 || (uid_to_ruid[INSN_UID (jump_insn)]
1390 > uid_to_ruid[INSN_UID (target_label)]));;
1393 /* Return the condition under which INSN will branch to TARGET. If TARGET
1394 is zero, return the condition under which INSN will return. If INSN is
1395 an unconditional branch, return const_true_rtx. If INSN isn't a simple
1396 type of jump, or it doesn't go to TARGET, return 0. */
1399 get_branch_condition (insn, target)
1403 rtx pat = PATTERN (insn);
1406 if (GET_CODE (pat) == RETURN)
1407 return target == 0 ? const_true_rtx : 0;
1409 else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
1412 src = SET_SRC (pat);
1413 if (GET_CODE (src) == LABEL_REF && XEXP (src, 0) == target)
1414 return const_true_rtx;
1416 else if (GET_CODE (src) == IF_THEN_ELSE
1417 && ((target == 0 && GET_CODE (XEXP (src, 1)) == RETURN)
1418 || (GET_CODE (XEXP (src, 1)) == LABEL_REF
1419 && XEXP (XEXP (src, 1), 0) == target))
1420 && XEXP (src, 2) == pc_rtx)
1421 return XEXP (src, 0);
1423 else if (GET_CODE (src) == IF_THEN_ELSE
1424 && ((target == 0 && GET_CODE (XEXP (src, 2)) == RETURN)
1425 || (GET_CODE (XEXP (src, 2)) == LABEL_REF
1426 && XEXP (XEXP (src, 2), 0) == target))
1427 && XEXP (src, 1) == pc_rtx)
1428 return gen_rtx (reverse_condition (GET_CODE (XEXP (src, 0))),
1429 GET_MODE (XEXP (src, 0)),
1430 XEXP (XEXP (src, 0), 0), XEXP (XEXP (src, 0), 1));
1435 /* Return non-zero if CONDITION is more strict than the condition of
1436 INSN, i.e., if INSN will always branch if CONDITION is true. */
1439 condition_dominates_p (condition, insn)
1443 rtx other_condition = get_branch_condition (insn, JUMP_LABEL (insn));
1444 enum rtx_code code = GET_CODE (condition);
1445 enum rtx_code other_code;
1447 if (rtx_equal_p (condition, other_condition)
1448 || other_condition == const_true_rtx)
1451 else if (condition == const_true_rtx || other_condition == 0)
1454 other_code = GET_CODE (other_condition);
1455 if (GET_RTX_LENGTH (code) != 2 || GET_RTX_LENGTH (other_code) != 2
1456 || ! rtx_equal_p (XEXP (condition, 0), XEXP (other_condition, 0))
1457 || ! rtx_equal_p (XEXP (condition, 1), XEXP (other_condition, 1)))
1460 return comparison_dominates_p (code, other_code);
1463 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1464 any insns already in the delay slot of JUMP. */
1467 redirect_with_delay_slots_safe_p (jump, newlabel, seq)
1468 rtx jump, newlabel, seq;
1470 int flags, slots, i;
1471 rtx pat = PATTERN (seq);
1473 /* Make sure all the delay slots of this jump would still
1474 be valid after threading the jump. If they are still
1475 valid, then return non-zero. */
1477 flags = get_jump_flags (jump, newlabel);
1478 for (i = 1; i < XVECLEN (pat, 0); i++)
1480 #ifdef ANNUL_IFFALSE_SLOTS
1481 (INSN_ANNULLED_BRANCH_P (jump)
1482 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1483 ? eligible_for_annul_false (jump, i - 1,
1484 XVECEXP (pat, 0, i), flags) :
1486 #ifdef ANNUL_IFTRUE_SLOTS
1487 (INSN_ANNULLED_BRANCH_P (jump)
1488 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1489 ? eligible_for_annul_true (jump, i - 1,
1490 XVECEXP (pat, 0, i), flags) :
1492 eligible_for_delay (jump, i -1, XVECEXP (pat, 0, i), flags)))
1495 return (i == XVECLEN (pat, 0));
1498 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1499 any insns we wish to place in the delay slot of JUMP. */
1502 redirect_with_delay_list_safe_p (jump, newlabel, delay_list)
1503 rtx jump, newlabel, delay_list;
1508 /* Make sure all the insns in DELAY_LIST would still be
1509 valid after threading the jump. If they are still
1510 valid, then return non-zero. */
1512 flags = get_jump_flags (jump, newlabel);
1513 for (li = delay_list, i = 0; li; li = XEXP (li, 1), i++)
1515 #ifdef ANNUL_IFFALSE_SLOTS
1516 (INSN_ANNULLED_BRANCH_P (jump)
1517 && INSN_FROM_TARGET_P (XEXP (li, 0)))
1518 ? eligible_for_annul_false (jump, i, XEXP (li, 0), flags) :
1520 #ifdef ANNUL_IFTRUE_SLOTS
1521 (INSN_ANNULLED_BRANCH_P (jump)
1522 && ! INSN_FROM_TARGET_P (XEXP (li, 0)))
1523 ? eligible_for_annul_true (jump, i, XEXP (li, 0), flags) :
1525 eligible_for_delay (jump, i, XEXP (li, 0), flags)))
1528 return (li == NULL);
1532 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1533 the condition tested by INSN is CONDITION and the resources shown in
1534 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1535 from SEQ's delay list, in addition to whatever insns it may execute
1536 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1537 needed while searching for delay slot insns. Return the concatenated
1538 delay list if possible, otherwise, return 0.
1540 SLOTS_TO_FILL is the total number of slots required by INSN, and
1541 PSLOTS_FILLED points to the number filled so far (also the number of
1542 insns in DELAY_LIST). It is updated with the number that have been
1543 filled from the SEQUENCE, if any.
1545 PANNUL_P points to a non-zero value if we already know that we need
1546 to annul INSN. If this routine determines that annulling is needed,
1547 it may set that value non-zero.
1549 PNEW_THREAD points to a location that is to receive the place at which
1550 execution should continue. */
1553 steal_delay_list_from_target (insn, condition, seq, delay_list,
1554 sets, needed, other_needed,
1555 slots_to_fill, pslots_filled, pannul_p,
1557 rtx insn, condition;
1560 struct resources *sets, *needed, *other_needed;
1567 int slots_remaining = slots_to_fill - *pslots_filled;
1568 int total_slots_filled = *pslots_filled;
1569 rtx new_delay_list = 0;
1570 int must_annul = *pannul_p;
1573 /* We can't do anything if there are more delay slots in SEQ than we
1574 can handle, or if we don't know that it will be a taken branch.
1576 We know that it will be a taken branch if it is either an unconditional
1577 branch or a conditional branch with a stricter branch condition. */
1579 if (XVECLEN (seq, 0) - 1 > slots_remaining
1580 || ! condition_dominates_p (condition, XVECEXP (seq, 0, 0)))
1583 for (i = 1; i < XVECLEN (seq, 0); i++)
1585 rtx trial = XVECEXP (seq, 0, i);
1588 if (insn_references_resource_p (trial, sets, 0)
1589 || insn_sets_resource_p (trial, needed, 0)
1590 || insn_sets_resource_p (trial, sets, 0)
1592 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1594 || find_reg_note (trial, REG_CC_USER, NULL_RTX)
1596 /* If TRIAL is from the fallthrough code of an annulled branch insn
1597 in SEQ, we cannot use it. */
1598 || (INSN_ANNULLED_BRANCH_P (XVECEXP (seq, 0, 0))
1599 && ! INSN_FROM_TARGET_P (trial)))
1602 /* If this insn was already done (usually in a previous delay slot),
1603 pretend we put it in our delay slot. */
1604 if (redundant_insn_p (trial, insn, new_delay_list))
1607 /* We will end up re-vectoring this branch, so compute flags
1608 based on jumping to the new label. */
1609 flags = get_jump_flags (insn, JUMP_LABEL (XVECEXP (seq, 0, 0)));
1612 && ((condition == const_true_rtx
1613 || (! insn_sets_resource_p (trial, other_needed, 0)
1614 && ! may_trap_p (PATTERN (trial)))))
1615 ? eligible_for_delay (insn, total_slots_filled, trial, flags)
1617 eligible_for_annul_false (insn, total_slots_filled, trial, flags)))
1619 temp = copy_rtx (trial);
1620 INSN_FROM_TARGET_P (temp) = 1;
1621 new_delay_list = add_to_delay_list (temp, new_delay_list);
1622 total_slots_filled++;
1624 if (--slots_remaining == 0)
1631 /* Show the place to which we will be branching. */
1632 *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));
1634 /* Add any new insns to the delay list and update the count of the
1635 number of slots filled. */
1636 *pslots_filled = total_slots_filled;
1637 *pannul_p = must_annul;
1639 if (delay_list == 0)
1640 return new_delay_list;
1642 for (temp = new_delay_list; temp; temp = XEXP (temp, 1))
1643 delay_list = add_to_delay_list (XEXP (temp, 0), delay_list);
1648 /* Similar to steal_delay_list_from_target except that SEQ is on the
1649 fallthrough path of INSN. Here we only do something if the delay insn
1650 of SEQ is an unconditional branch. In that case we steal its delay slot
1651 for INSN since unconditional branches are much easier to fill. */
1654 steal_delay_list_from_fallthrough (insn, condition, seq,
1655 delay_list, sets, needed, other_needed,
1656 slots_to_fill, pslots_filled, pannul_p)
1657 rtx insn, condition;
1660 struct resources *sets, *needed, *other_needed;
1668 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1670 /* We can't do anything if SEQ's delay insn isn't an
1671 unconditional branch. */
1673 if (! simplejump_p (XVECEXP (seq, 0, 0))
1674 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN)
1677 for (i = 1; i < XVECLEN (seq, 0); i++)
1679 rtx trial = XVECEXP (seq, 0, i);
1681 /* If TRIAL sets CC0, stealing it will move it too far from the use
1683 if (insn_references_resource_p (trial, sets, 0)
1684 || insn_sets_resource_p (trial, needed, 0)
1685 || insn_sets_resource_p (trial, sets, 0)
1687 || sets_cc0_p (PATTERN (trial))
1693 /* If this insn was already done, we don't need it. */
1694 if (redundant_insn_p (trial, insn, delay_list))
1696 delete_from_delay_slot (trial);
1701 && ((condition == const_true_rtx
1702 || (! insn_sets_resource_p (trial, other_needed, 0)
1703 && ! may_trap_p (PATTERN (trial)))))
1704 ? eligible_for_delay (insn, *pslots_filled, trial, flags)
1706 eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
1708 delete_from_delay_slot (trial);
1709 delay_list = add_to_delay_list (trial, delay_list);
1711 if (++(*pslots_filled) == slots_to_fill)
1721 /* Try merging insns starting at THREAD which match exactly the insns in
1724 If all insns were matched and the insn was previously annulling, the
1725 annul bit will be cleared.
1727 For each insn that is merged, if the branch is or will be non-annulling,
1728 we delete the merged insn. */
1731 try_merge_delay_insns (insn, thread)
1734 rtx trial, next_trial;
1735 rtx delay_insn = XVECEXP (PATTERN (insn), 0, 0);
1736 int annul_p = INSN_ANNULLED_BRANCH_P (delay_insn);
1737 int slot_number = 1;
1738 int num_slots = XVECLEN (PATTERN (insn), 0);
1739 rtx next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1740 struct resources set, needed;
1741 rtx merged_insns = 0;
1745 flags = get_jump_flags (delay_insn, JUMP_LABEL (delay_insn));
1747 CLEAR_RESOURCE (&needed);
1748 CLEAR_RESOURCE (&set);
1750 /* If this is not an annulling branch, take into account anything needed in
1751 NEXT_TO_MATCH. This prevents two increments from being incorrectly
1752 folded into one. If we are annulling, this would be the correct
1753 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1754 will essentially disable this optimization. This method is somewhat of
1755 a kludge, but I don't see a better way.) */
1757 mark_referenced_resources (next_to_match, &needed, 1);
1759 for (trial = thread; !stop_search_p (trial, 1); trial = next_trial)
1761 rtx pat = PATTERN (trial);
1763 next_trial = next_nonnote_insn (trial);
1765 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1766 if (GET_CODE (trial) == INSN
1767 && (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER))
1770 if (GET_CODE (next_to_match) == GET_CODE (trial)
1772 /* We can't share an insn that sets cc0. */
1773 && ! sets_cc0_p (pat)
1775 && ! insn_references_resource_p (trial, &set, 1)
1776 && ! insn_sets_resource_p (trial, &set, 1)
1777 && ! insn_sets_resource_p (trial, &needed, 1)
1778 && (trial = try_split (pat, trial, 0)) != 0
1779 /* Update next_trial, in case try_split succeeded. */
1780 && (next_trial = next_nonnote_insn (trial))
1781 && rtx_equal_p (PATTERN (next_to_match), PATTERN (trial))
1782 /* Have to test this condition if annul condition is different
1783 from (and less restrictive than) non-annulling one. */
1784 && eligible_for_delay (delay_insn, slot_number - 1, trial, flags))
1789 update_block (trial, thread);
1790 delete_insn (trial);
1791 INSN_FROM_TARGET_P (next_to_match) = 0;
1794 merged_insns = gen_rtx (INSN_LIST, VOIDmode, trial, merged_insns);
1796 if (++slot_number == num_slots)
1799 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1801 mark_referenced_resources (next_to_match, &needed, 1);
1804 mark_set_resources (trial, &set, 0, 1);
1805 mark_referenced_resources (trial, &needed, 1);
1808 /* See if we stopped on a filled insn. If we did, try to see if its
1809 delay slots match. */
1810 if (slot_number != num_slots
1811 && trial && GET_CODE (trial) == INSN
1812 && GET_CODE (PATTERN (trial)) == SEQUENCE
1813 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (PATTERN (trial), 0, 0)))
1815 rtx pat = PATTERN (trial);
1816 rtx filled_insn = XVECEXP (pat, 0, 0);
1818 /* Account for resources set/needed by the filled insn. */
1819 mark_set_resources (filled_insn, &set, 0, 1);
1820 mark_referenced_resources (filled_insn, &needed, 1);
1822 for (i = 1; i < XVECLEN (pat, 0); i++)
1824 rtx dtrial = XVECEXP (pat, 0, i);
1826 if (! insn_references_resource_p (dtrial, &set, 1)
1827 && ! insn_sets_resource_p (dtrial, &set, 1)
1828 && ! insn_sets_resource_p (dtrial, &needed, 1)
1830 && ! sets_cc0_p (PATTERN (dtrial))
1832 && rtx_equal_p (PATTERN (next_to_match), PATTERN (dtrial))
1833 && eligible_for_delay (delay_insn, slot_number - 1, dtrial, flags))
1837 update_block (dtrial, thread);
1838 delete_from_delay_slot (dtrial);
1839 INSN_FROM_TARGET_P (next_to_match) = 0;
1842 merged_insns = gen_rtx (INSN_LIST, SImode, dtrial,
1845 if (++slot_number == num_slots)
1848 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1853 /* If all insns in the delay slot have been matched and we were previously
1854 annulling the branch, we need not any more. In that case delete all the
1855 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn the
1856 the delay list so that we know that it isn't only being used at the
1858 if (slot_number == num_slots && annul_p)
1860 for (; merged_insns; merged_insns = XEXP (merged_insns, 1))
1862 if (GET_MODE (merged_insns) == SImode)
1864 update_block (XEXP (merged_insns, 0), thread);
1865 delete_from_delay_slot (XEXP (merged_insns, 0));
1869 update_block (XEXP (merged_insns, 0), thread);
1870 delete_insn (XEXP (merged_insns, 0));
1874 INSN_ANNULLED_BRANCH_P (delay_insn) = 0;
1876 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1877 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) = 0;
1881 /* See if INSN is redundant with an insn in front of TARGET. Often this
1882 is called when INSN is a candidate for a delay slot of TARGET.
1883 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1884 of INSN. Often INSN will be redundant with an insn in a delay slot of
1885 some previous insn. This happens when we have a series of branches to the
1886 same label; in that case the first insn at the target might want to go
1887 into each of the delay slots.
1889 If we are not careful, this routine can take up a significant fraction
1890 of the total compilation time (4%), but only wins rarely. Hence we
1891 speed this routine up by making two passes. The first pass goes back
1892 until it hits a label and sees if it find an insn with an identical
1893 pattern. Only in this (relatively rare) event does it check for
1896 We do not split insns we encounter. This could cause us not to find a
1897 redundant insn, but the cost of splitting seems greater than the possible
1898 gain in rare cases. */
1901 redundant_insn_p (insn, target, delay_list)
1906 rtx target_main = target;
1907 rtx ipat = PATTERN (insn);
1909 struct resources needed, set;
1912 /* Scan backwards looking for a match. */
1913 for (trial = PREV_INSN (target); trial; trial = PREV_INSN (trial))
1915 if (GET_CODE (trial) == CODE_LABEL)
1918 if (GET_RTX_CLASS (GET_CODE (trial)) != 'i')
1921 pat = PATTERN (trial);
1922 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
1925 if (GET_CODE (pat) == SEQUENCE)
1927 /* Stop for a CALL and its delay slots because it is difficult to
1928 track its resource needs correctly. */
1929 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
1932 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1933 slots because it is difficult to track its resource needs
1936 #ifdef INSN_SETS_ARE_DELAYED
1937 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
1941 #ifdef INSN_REFERENCES_ARE_DELAYED
1942 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
1946 /* See if any of the insns in the delay slot match, updating
1947 resource requirements as we go. */
1948 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
1949 if (GET_CODE (XVECEXP (pat, 0, i)) == GET_CODE (insn)
1950 && rtx_equal_p (PATTERN (XVECEXP (pat, 0, i)), ipat))
1953 /* If found a match, exit this loop early. */
1958 else if (GET_CODE (trial) == GET_CODE (insn) && rtx_equal_p (pat, ipat))
1962 /* If we didn't find an insn that matches, return 0. */
1966 /* See what resources this insn sets and needs. If they overlap, or
1967 if this insn references CC0, it can't be redundant. */
1969 CLEAR_RESOURCE (&needed);
1970 CLEAR_RESOURCE (&set);
1971 mark_set_resources (insn, &set, 0, 1);
1972 mark_referenced_resources (insn, &needed, 1);
1974 /* If TARGET is a SEQUENCE, get the main insn. */
1975 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
1976 target_main = XVECEXP (PATTERN (target), 0, 0);
1978 if (resource_conflicts_p (&needed, &set)
1980 || reg_mentioned_p (cc0_rtx, ipat)
1982 /* The insn requiring the delay may not set anything needed or set by
1984 || insn_sets_resource_p (target_main, &needed, 1)
1985 || insn_sets_resource_p (target_main, &set, 1))
1988 /* Insns we pass may not set either NEEDED or SET, so merge them for
1990 needed.memory |= set.memory;
1991 IOR_HARD_REG_SET (needed.regs, set.regs);
1993 /* This insn isn't redundant if it conflicts with an insn that either is
1994 or will be in a delay slot of TARGET. */
1998 if (insn_sets_resource_p (XEXP (delay_list, 0), &needed, 1))
2000 delay_list = XEXP (delay_list, 1);
2003 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
2004 for (i = 1; i < XVECLEN (PATTERN (target), 0); i++)
2005 if (insn_sets_resource_p (XVECEXP (PATTERN (target), 0, i), &needed, 1))
2008 /* Scan backwards until we reach a label or an insn that uses something
2009 INSN sets or sets something insn uses or sets. */
2011 for (trial = PREV_INSN (target);
2012 trial && GET_CODE (trial) != CODE_LABEL;
2013 trial = PREV_INSN (trial))
2015 if (GET_CODE (trial) != INSN && GET_CODE (trial) != CALL_INSN
2016 && GET_CODE (trial) != JUMP_INSN)
2019 pat = PATTERN (trial);
2020 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2023 if (GET_CODE (pat) == SEQUENCE)
2025 /* If this is a CALL_INSN and its delay slots, it is hard to track
2026 the resource needs properly, so give up. */
2027 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
2030 /* If this this is an INSN or JUMP_INSN with delayed effects, it
2031 is hard to track the resource needs properly, so give up. */
2033 #ifdef INSN_SETS_ARE_DELAYED
2034 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2038 #ifdef INSN_REFERENCES_ARE_DELAYED
2039 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2043 /* See if any of the insns in the delay slot match, updating
2044 resource requirements as we go. */
2045 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
2047 rtx candidate = XVECEXP (pat, 0, i);
2049 /* If an insn will be annulled if the branch is false, it isn't
2050 considered as a possible duplicate insn. */
2051 if (rtx_equal_p (PATTERN (candidate), ipat)
2052 && ! (INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2053 && INSN_FROM_TARGET_P (candidate)))
2055 /* Show that this insn will be used in the sequel. */
2056 INSN_FROM_TARGET_P (candidate) = 0;
2060 /* Unless this is an annulled insn from the target of a branch,
2061 we must stop if it sets anything needed or set by INSN. */
2062 if ((! INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2063 || ! INSN_FROM_TARGET_P (candidate))
2064 && insn_sets_resource_p (candidate, &needed, 1))
2069 /* If the insn requiring the delay slot conflicts with INSN, we
2071 if (insn_sets_resource_p (XVECEXP (pat, 0, 0), &needed, 1))
2076 /* See if TRIAL is the same as INSN. */
2077 pat = PATTERN (trial);
2078 if (rtx_equal_p (pat, ipat))
2081 /* Can't go any further if TRIAL conflicts with INSN. */
2082 if (insn_sets_resource_p (trial, &needed, 1))
2090 /* Return 1 if THREAD can only be executed in one way. If LABEL is non-zero,
2091 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
2092 is non-zero, we are allowed to fall into this thread; otherwise, we are
2095 If LABEL is used more than one or we pass a label other than LABEL before
2096 finding an active insn, we do not own this thread. */
2099 own_thread_p (thread, label, allow_fallthrough)
2102 int allow_fallthrough;
2107 /* We don't own the function end. */
2111 /* Get the first active insn, or THREAD, if it is an active insn. */
2112 active_insn = next_active_insn (PREV_INSN (thread));
2114 for (insn = thread; insn != active_insn; insn = NEXT_INSN (insn))
2115 if (GET_CODE (insn) == CODE_LABEL
2116 && (insn != label || LABEL_NUSES (insn) != 1))
2119 if (allow_fallthrough)
2122 /* Ensure that we reach a BARRIER before any insn or label. */
2123 for (insn = prev_nonnote_insn (thread);
2124 insn == 0 || GET_CODE (insn) != BARRIER;
2125 insn = prev_nonnote_insn (insn))
2127 || GET_CODE (insn) == CODE_LABEL
2128 || (GET_CODE (insn) == INSN
2129 && GET_CODE (PATTERN (insn)) != USE
2130 && GET_CODE (PATTERN (insn)) != CLOBBER))
2136 /* Find the number of the basic block that starts closest to INSN. Return -1
2137 if we couldn't find such a basic block. */
2140 find_basic_block (insn)
2145 /* Scan backwards to the previous BARRIER. Then see if we can find a
2146 label that starts a basic block. Return the basic block number. */
2148 for (insn = prev_nonnote_insn (insn);
2149 insn && GET_CODE (insn) != BARRIER;
2150 insn = prev_nonnote_insn (insn))
2153 /* The start of the function is basic block zero. */
2157 /* See if any of the upcoming CODE_LABELs start a basic block. If we reach
2158 anything other than a CODE_LABEL or note, we can't find this code. */
2159 for (insn = next_nonnote_insn (insn);
2160 insn && GET_CODE (insn) == CODE_LABEL;
2161 insn = next_nonnote_insn (insn))
2163 for (i = 0; i < n_basic_blocks; i++)
2164 if (insn == basic_block_head[i])
2171 /* Called when INSN is being moved from a location near the target of a jump.
2172 We leave a marker of the form (use (INSN)) immediately in front
2173 of WHERE for mark_target_live_regs. These markers will be deleted when
2176 We used to try to update the live status of registers if WHERE is at
2177 the start of a basic block, but that can't work since we may remove a
2178 BARRIER in relax_delay_slots. */
2181 update_block (insn, where)
2187 /* Ignore if this was in a delay slot and it came from the target of
2189 if (INSN_FROM_TARGET_P (insn))
2192 emit_insn_before (gen_rtx (USE, VOIDmode, insn), where);
2194 /* INSN might be making a value live in a block where it didn't use to
2195 be. So recompute liveness information for this block. */
2197 b = find_basic_block (insn);
2202 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
2203 the basic block containing the jump. */
2206 reorg_redirect_jump (jump, nlabel)
2210 int b = find_basic_block (jump);
2215 return redirect_jump (jump, nlabel);
2218 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
2219 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
2220 that reference values used in INSN. If we find one, then we move the
2221 REG_DEAD note to INSN.
2223 This is needed to handle the case where an later insn (after INSN) has a
2224 REG_DEAD note for a register used by INSN, and this later insn subsequently
2225 gets moved before a CODE_LABEL because it is a redundant insn. In this
2226 case, mark_target_live_regs may be confused into thinking the register
2227 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
2230 update_reg_dead_notes (insn, delayed_insn)
2231 rtx insn, delayed_insn;
2235 for (p = next_nonnote_insn (insn); p != delayed_insn;
2236 p = next_nonnote_insn (p))
2237 for (link = REG_NOTES (p); link; link = next)
2239 next = XEXP (link, 1);
2241 if (REG_NOTE_KIND (link) != REG_DEAD
2242 || GET_CODE (XEXP (link, 0)) != REG)
2245 if (reg_referenced_p (XEXP (link, 0), PATTERN (insn)))
2247 /* Move the REG_DEAD note from P to INSN. */
2248 remove_note (p, link);
2249 XEXP (link, 1) = REG_NOTES (insn);
2250 REG_NOTES (insn) = link;
2255 /* Marks registers possibly live at the current place being scanned by
2256 mark_target_live_regs. Used only by next two function. */
2258 static HARD_REG_SET current_live_regs;
2260 /* Marks registers for which we have seen a REG_DEAD note but no assignment.
2261 Also only used by the next two functions. */
2263 static HARD_REG_SET pending_dead_regs;
2265 /* Utility function called from mark_target_live_regs via note_stores.
2266 It deadens any CLOBBERed registers and livens any SET registers. */
2269 update_live_status (dest, x)
2273 int first_regno, last_regno;
2276 if (GET_CODE (dest) != REG
2277 && (GET_CODE (dest) != SUBREG || GET_CODE (SUBREG_REG (dest)) != REG))
2280 if (GET_CODE (dest) == SUBREG)
2281 first_regno = REGNO (SUBREG_REG (dest)) + SUBREG_WORD (dest);
2283 first_regno = REGNO (dest);
2285 last_regno = first_regno + HARD_REGNO_NREGS (first_regno, GET_MODE (dest));
2287 if (GET_CODE (x) == CLOBBER)
2288 for (i = first_regno; i < last_regno; i++)
2289 CLEAR_HARD_REG_BIT (current_live_regs, i);
2291 for (i = first_regno; i < last_regno; i++)
2293 SET_HARD_REG_BIT (current_live_regs, i);
2294 CLEAR_HARD_REG_BIT (pending_dead_regs, i);
2298 /* Similar to next_insn, but ignores insns in the delay slots of
2299 an annulled branch. */
2302 next_insn_no_annul (insn)
2307 /* If INSN is an annulled branch, skip any insns from the target
2309 if (INSN_ANNULLED_BRANCH_P (insn)
2310 && NEXT_INSN (PREV_INSN (insn)) != insn)
2311 while (INSN_FROM_TARGET_P (NEXT_INSN (insn)))
2312 insn = NEXT_INSN (insn);
2314 insn = NEXT_INSN (insn);
2315 if (insn && GET_CODE (insn) == INSN
2316 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2317 insn = XVECEXP (PATTERN (insn), 0, 0);
2323 /* Set the resources that are live at TARGET.
2325 If TARGET is zero, we refer to the end of the current function and can
2326 return our precomputed value.
2328 Otherwise, we try to find out what is live by consulting the basic block
2329 information. This is tricky, because we must consider the actions of
2330 reload and jump optimization, which occur after the basic block information
2333 Accordingly, we proceed as follows::
2335 We find the previous BARRIER and look at all immediately following labels
2336 (with no intervening active insns) to see if any of them start a basic
2337 block. If we hit the start of the function first, we use block 0.
2339 Once we have found a basic block and a corresponding first insns, we can
2340 accurately compute the live status from basic_block_live_regs and
2341 reg_renumber. (By starting at a label following a BARRIER, we are immune
2342 to actions taken by reload and jump.) Then we scan all insns between
2343 that point and our target. For each CLOBBER (or for call-clobbered regs
2344 when we pass a CALL_INSN), mark the appropriate registers are dead. For
2345 a SET, mark them as live.
2347 We have to be careful when using REG_DEAD notes because they are not
2348 updated by such things as find_equiv_reg. So keep track of registers
2349 marked as dead that haven't been assigned to, and mark them dead at the
2350 next CODE_LABEL since reload and jump won't propagate values across labels.
2352 If we cannot find the start of a basic block (should be a very rare
2353 case, if it can happen at all), mark everything as potentially live.
2355 Next, scan forward from TARGET looking for things set or clobbered
2356 before they are used. These are not live.
2358 Because we can be called many times on the same target, save our results
2359 in a hash table indexed by INSN_UID. */
2362 mark_target_live_regs (target, res)
2364 struct resources *res;
2368 struct target_info *tinfo;
2372 HARD_REG_SET scratch;
2373 struct resources set, needed;
2376 /* Handle end of function. */
2379 *res = end_of_function_needs;
2383 /* We have to assume memory is needed, but the CC isn't. */
2388 /* See if we have computed this value already. */
2389 for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2390 tinfo; tinfo = tinfo->next)
2391 if (tinfo->uid == INSN_UID (target))
2394 /* Start by getting the basic block number. If we have saved information,
2395 we can get it from there unless the insn at the start of the basic block
2396 has been deleted. */
2397 if (tinfo && tinfo->block != -1
2398 && ! INSN_DELETED_P (basic_block_head[tinfo->block]))
2402 b = find_basic_block (target);
2406 /* If the information is up-to-date, use it. Otherwise, we will
2408 if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b])
2410 COPY_HARD_REG_SET (res->regs, tinfo->live_regs);
2416 /* Allocate a place to put our results and chain it into the
2418 tinfo = (struct target_info *) oballoc (sizeof (struct target_info));
2419 tinfo->uid = INSN_UID (target);
2421 tinfo->next = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2422 target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo;
2425 CLEAR_HARD_REG_SET (pending_dead_regs);
2427 /* If we found a basic block, get the live registers from it and update
2428 them with anything set or killed between its start and the insn before
2429 TARGET. Otherwise, we must assume everything is live. */
2432 regset regs_live = basic_block_live_at_start[b];
2434 REGSET_ELT_TYPE bit;
2436 rtx start_insn, stop_insn;
2438 /* Compute hard regs live at start of block -- this is the real hard regs
2439 marked live, plus live pseudo regs that have been renumbered to
2443 current_live_regs = *regs_live;
2445 COPY_HARD_REG_SET (current_live_regs, regs_live);
2448 for (offset = 0, i = 0; offset < regset_size; offset++)
2450 if (regs_live[offset] == 0)
2451 i += REGSET_ELT_BITS;
2453 for (bit = 1; bit && i < max_regno; bit <<= 1, i++)
2454 if ((regs_live[offset] & bit)
2455 && (regno = reg_renumber[i]) >= 0)
2457 j < regno + HARD_REGNO_NREGS (regno,
2458 PSEUDO_REGNO_MODE (i));
2460 SET_HARD_REG_BIT (current_live_regs, j);
2463 /* Get starting and ending insn, handling the case where each might
2465 start_insn = (b == 0 ? get_insns () : basic_block_head[b]);
2468 if (GET_CODE (start_insn) == INSN
2469 && GET_CODE (PATTERN (start_insn)) == SEQUENCE)
2470 start_insn = XVECEXP (PATTERN (start_insn), 0, 0);
2472 if (GET_CODE (stop_insn) == INSN
2473 && GET_CODE (PATTERN (stop_insn)) == SEQUENCE)
2474 stop_insn = next_insn (PREV_INSN (stop_insn));
2476 for (insn = start_insn; insn != stop_insn;
2477 insn = next_insn_no_annul (insn))
2480 rtx real_insn = insn;
2482 /* If this insn is from the target of a branch, it isn't going to
2483 be used in the sequel. If it is used in both cases, this
2484 test will not be true. */
2485 if (INSN_FROM_TARGET_P (insn))
2488 /* If this insn is a USE made by update_block, we care about the
2490 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
2491 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2492 real_insn = XEXP (PATTERN (insn), 0);
2494 if (GET_CODE (real_insn) == CALL_INSN)
2496 /* CALL clobbers all call-used regs that aren't fixed except
2497 sp, ap, and fp. Do this before setting the result of the
2499 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2500 if (call_used_regs[i]
2501 && i != STACK_POINTER_REGNUM && i != FRAME_POINTER_REGNUM
2502 && i != ARG_POINTER_REGNUM
2503 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2504 && i != HARD_FRAME_POINTER_REGNUM
2506 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2507 && ! (i == ARG_POINTER_REGNUM && fixed_regs[i])
2509 #ifdef PIC_OFFSET_TABLE_REGNUM
2510 && ! (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
2513 CLEAR_HARD_REG_BIT (current_live_regs, i);
2515 /* A CALL_INSN sets any global register live, since it may
2516 have been modified by the call. */
2517 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2519 SET_HARD_REG_BIT (current_live_regs, i);
2522 /* Mark anything killed in an insn to be deadened at the next
2523 label. Ignore USE insns; the only REG_DEAD notes will be for
2524 parameters. But they might be early. A CALL_INSN will usually
2525 clobber registers used for parameters. It isn't worth bothering
2526 with the unlikely case when it won't. */
2527 if ((GET_CODE (real_insn) == INSN
2528 && GET_CODE (PATTERN (real_insn)) != USE
2529 && GET_CODE (PATTERN (real_insn)) != CLOBBER)
2530 || GET_CODE (real_insn) == JUMP_INSN
2531 || GET_CODE (real_insn) == CALL_INSN)
2533 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2534 if (REG_NOTE_KIND (link) == REG_DEAD
2535 && GET_CODE (XEXP (link, 0)) == REG
2536 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2538 int first_regno = REGNO (XEXP (link, 0));
2541 + HARD_REGNO_NREGS (first_regno,
2542 GET_MODE (XEXP (link, 0))));
2544 for (i = first_regno; i < last_regno; i++)
2545 SET_HARD_REG_BIT (pending_dead_regs, i);
2548 note_stores (PATTERN (real_insn), update_live_status);
2550 /* If any registers were unused after this insn, kill them.
2551 These notes will always be accurate. */
2552 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2553 if (REG_NOTE_KIND (link) == REG_UNUSED
2554 && GET_CODE (XEXP (link, 0)) == REG
2555 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2557 int first_regno = REGNO (XEXP (link, 0));
2560 + HARD_REGNO_NREGS (first_regno,
2561 GET_MODE (XEXP (link, 0))));
2563 for (i = first_regno; i < last_regno; i++)
2564 CLEAR_HARD_REG_BIT (current_live_regs, i);
2568 else if (GET_CODE (real_insn) == CODE_LABEL)
2570 /* A label clobbers the pending dead registers since neither
2571 reload nor jump will propagate a value across a label. */
2572 AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs);
2573 CLEAR_HARD_REG_SET (pending_dead_regs);
2576 /* The beginning of the epilogue corresponds to the end of the
2577 RTL chain when there are no epilogue insns. Certain resources
2578 are implicitly required at that point. */
2579 else if (GET_CODE (real_insn) == NOTE
2580 && NOTE_LINE_NUMBER (real_insn) == NOTE_INSN_EPILOGUE_BEG)
2581 IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs);
2584 COPY_HARD_REG_SET (res->regs, current_live_regs);
2586 tinfo->bb_tick = bb_ticks[b];
2589 /* We didn't find the start of a basic block. Assume everything
2590 in use. This should happen only extremely rarely. */
2591 SET_HARD_REG_SET (res->regs);
2593 /* Now step forward from TARGET looking for registers that are set before
2594 they are used. These are dead. If we pass a label, any pending dead
2595 registers that weren't yet used can be made dead. Stop when we pass a
2596 conditional JUMP_INSN; follow the first few unconditional branches. */
2598 CLEAR_RESOURCE (&set);
2599 CLEAR_RESOURCE (&needed);
2601 for (insn = target; insn; insn = next)
2603 rtx this_jump_insn = insn;
2605 next = NEXT_INSN (insn);
2606 switch (GET_CODE (insn))
2609 AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs);
2610 AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs);
2611 CLEAR_HARD_REG_SET (pending_dead_regs);
2619 if (GET_CODE (PATTERN (insn)) == USE)
2621 /* If INSN is a USE made by update_block, we care about the
2622 underlying insn. Any registers set by the underlying insn
2623 are live since the insn is being done somewhere else. */
2624 if (GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2625 mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, 1);
2627 /* All other USE insns are to be ignored. */
2630 else if (GET_CODE (PATTERN (insn)) == CLOBBER)
2632 else if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2634 /* An unconditional jump can be used to fill the delay slot
2635 of a call, so search for a JUMP_INSN in any position. */
2636 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
2638 this_jump_insn = XVECEXP (PATTERN (insn), 0, i);
2639 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2645 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2647 if (jump_count++ < 10
2648 && (simplejump_p (this_jump_insn)
2649 || GET_CODE (PATTERN (this_jump_insn)) == RETURN))
2651 next = next_active_insn (JUMP_LABEL (this_jump_insn));
2655 jump_target = JUMP_LABEL (this_jump_insn);
2662 mark_referenced_resources (insn, &needed, 1);
2663 mark_set_resources (insn, &set, 0, 1);
2665 COPY_HARD_REG_SET (scratch, set.regs);
2666 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2667 AND_COMPL_HARD_REG_SET (res->regs, scratch);
2670 /* If we hit an unconditional branch, we have another way of finding out
2671 what is live: we can see what is live at the branch target and include
2672 anything used but not set before the branch. The only things that are
2673 live are those that are live using the above test and the test below.
2675 Don't try this if we expired our jump count above, since that would
2676 mean there may be an infinite loop in the function being compiled. */
2678 if (jump_insn && jump_count < 10)
2680 struct resources new_resources;
2681 rtx stop_insn = next_active_insn (jump_insn);
2683 mark_target_live_regs (next_active_insn (jump_target), &new_resources);
2684 CLEAR_RESOURCE (&set);
2685 CLEAR_RESOURCE (&needed);
2687 /* Include JUMP_INSN in the needed registers. */
2688 for (insn = target; insn != stop_insn; insn = next_active_insn (insn))
2690 mark_referenced_resources (insn, &needed, 1);
2692 COPY_HARD_REG_SET (scratch, needed.regs);
2693 AND_COMPL_HARD_REG_SET (scratch, set.regs);
2694 IOR_HARD_REG_SET (new_resources.regs, scratch);
2696 mark_set_resources (insn, &set, 0, 1);
2699 AND_HARD_REG_SET (res->regs, new_resources.regs);
2702 COPY_HARD_REG_SET (tinfo->live_regs, res->regs);
2705 /* Scan a function looking for insns that need a delay slot and find insns to
2706 put into the delay slot.
2708 NON_JUMPS_P is non-zero if we are to only try to fill non-jump insns (such
2709 as calls). We do these first since we don't want jump insns (that are
2710 easier to fill) to get the only insns that could be used for non-jump insns.
2711 When it is zero, only try to fill JUMP_INSNs.
2713 When slots are filled in this manner, the insns (including the
2714 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
2715 it is possible to tell whether a delay slot has really been filled
2716 or not. `final' knows how to deal with this, by communicating
2717 through FINAL_SEQUENCE. */
2720 fill_simple_delay_slots (first, non_jumps_p)
2724 register rtx insn, pat, trial, next_trial;
2726 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
2727 struct resources needed, set;
2728 register int slots_to_fill, slots_filled;
2731 for (i = 0; i < num_unfilled_slots; i++)
2734 /* Get the next insn to fill. If it has already had any slots assigned,
2735 we can't do anything with it. Maybe we'll improve this later. */
2737 insn = unfilled_slots_base[i];
2739 || INSN_DELETED_P (insn)
2740 || (GET_CODE (insn) == INSN
2741 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2742 || (GET_CODE (insn) == JUMP_INSN && non_jumps_p)
2743 || (GET_CODE (insn) != JUMP_INSN && ! non_jumps_p))
2746 if (GET_CODE (insn) == JUMP_INSN)
2747 flags = get_jump_flags (insn, JUMP_LABEL (insn));
2749 flags = get_jump_flags (insn, NULL_RTX);
2750 slots_to_fill = num_delay_slots (insn);
2751 if (slots_to_fill == 0)
2754 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
2755 says how many. After initialization, first try optimizing
2758 nop add %o7,.-L1,%o7
2762 If this case applies, the delay slot of the call is filled with
2763 the unconditional jump. This is done first to avoid having the
2764 delay slot of the call filled in the backward scan. Also, since
2765 the unconditional jump is likely to also have a delay slot, that
2766 insn must exist when it is subsequently scanned.
2768 This is tried on each insn with delay slots as some machines
2769 have insns which perform calls, but are not represented as
2775 if ((trial = next_active_insn (insn))
2776 && GET_CODE (trial) == JUMP_INSN
2777 && simplejump_p (trial)
2778 && eligible_for_delay (insn, slots_filled, trial, flags)
2779 && no_labels_between_p (insn, trial))
2782 delay_list = add_to_delay_list (trial, delay_list);
2783 /* Remove the unconditional jump from consideration for delay slot
2784 filling and unthread it. */
2785 if (unfilled_slots_base[i + 1] == trial)
2786 unfilled_slots_base[i + 1] = 0;
2788 rtx next = NEXT_INSN (trial);
2789 rtx prev = PREV_INSN (trial);
2791 NEXT_INSN (prev) = next;
2793 PREV_INSN (next) = prev;
2797 /* Now, scan backwards from the insn to search for a potential
2798 delay-slot candidate. Stop searching when a label or jump is hit.
2800 For each candidate, if it is to go into the delay slot (moved
2801 forward in execution sequence), it must not need or set any resources
2802 that were set by later insns and must not set any resources that
2803 are needed for those insns.
2805 The delay slot insn itself sets resources unless it is a call
2806 (in which case the called routine, not the insn itself, is doing
2809 if (slots_filled < slots_to_fill)
2811 CLEAR_RESOURCE (&needed);
2812 CLEAR_RESOURCE (&set);
2813 mark_set_resources (insn, &set, 0, 0);
2814 mark_referenced_resources (insn, &needed, 0);
2816 for (trial = prev_nonnote_insn (insn); ! stop_search_p (trial, 1);
2819 next_trial = prev_nonnote_insn (trial);
2821 /* This must be an INSN or CALL_INSN. */
2822 pat = PATTERN (trial);
2824 /* USE and CLOBBER at this level was just for flow; ignore it. */
2825 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2828 /* Check for resource conflict first, to avoid unnecessary
2830 if (! insn_references_resource_p (trial, &set, 1)
2831 && ! insn_sets_resource_p (trial, &set, 1)
2832 && ! insn_sets_resource_p (trial, &needed, 1)
2834 /* Can't separate set of cc0 from its use. */
2835 && ! (reg_mentioned_p (cc0_rtx, pat)
2836 && ! sets_cc0_p (cc0_rtx, pat))
2840 trial = try_split (pat, trial, 1);
2841 next_trial = prev_nonnote_insn (trial);
2842 if (eligible_for_delay (insn, slots_filled, trial, flags))
2844 /* In this case, we are searching backward, so if we
2845 find insns to put on the delay list, we want
2846 to put them at the head, rather than the
2847 tail, of the list. */
2849 update_reg_dead_notes (trial, insn);
2850 delay_list = gen_rtx (INSN_LIST, VOIDmode,
2852 update_block (trial, trial);
2853 delete_insn (trial);
2854 if (slots_to_fill == ++slots_filled)
2860 mark_set_resources (trial, &set, 0, 1);
2861 mark_referenced_resources (trial, &needed, 1);
2865 /* If all needed slots haven't been filled, we come here. */
2867 /* Try to optimize case of jumping around a single insn. */
2868 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
2869 if (slots_filled != slots_to_fill
2871 && GET_CODE (insn) == JUMP_INSN && condjump_p (insn))
2873 delay_list = optimize_skip (insn);
2879 /* Try to get insns from beyond the insn needing the delay slot.
2880 These insns can neither set or reference resources set in insns being
2881 skipped, cannot set resources in the insn being skipped, and, if this
2882 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2883 call might not return).
2885 If this is a conditional jump, see if it merges back to us early
2886 enough for us to pick up insns from the merge point. Don't do
2887 this if there is another branch to our label unless we pass all of
2890 Another similar merge is if we jump to the same place that a
2891 later unconditional jump branches to. In that case, we don't
2892 care about the number of uses of our label. */
2894 if (slots_filled != slots_to_fill
2895 && (GET_CODE (insn) != JUMP_INSN
2896 || (condjump_p (insn) && ! simplejump_p (insn)
2897 && JUMP_LABEL (insn) != 0)))
2900 int maybe_never = 0;
2901 int passed_label = 0;
2903 struct resources needed_at_jump;
2905 CLEAR_RESOURCE (&needed);
2906 CLEAR_RESOURCE (&set);
2908 if (GET_CODE (insn) == CALL_INSN)
2910 mark_set_resources (insn, &set, 0, 1);
2911 mark_referenced_resources (insn, &needed, 1);
2916 mark_set_resources (insn, &set, 0, 1);
2917 mark_referenced_resources (insn, &needed, 1);
2918 if (GET_CODE (insn) == JUMP_INSN)
2920 /* Get our target and show how many more uses we want to
2921 see before we hit the label. */
2922 target = JUMP_LABEL (insn);
2923 target_uses = LABEL_NUSES (target) - 1;
2928 for (trial = next_nonnote_insn (insn); trial; trial = next_trial)
2930 rtx pat, trial_delay;
2932 next_trial = next_nonnote_insn (trial);
2934 if (GET_CODE (trial) == CODE_LABEL)
2938 /* If this is our target, see if we have seen all its uses.
2939 If so, indicate we have passed our target and ignore it.
2940 All other labels cause us to stop our search. */
2941 if (trial == target && target_uses == 0)
2949 else if (GET_CODE (trial) == BARRIER)
2952 /* We must have an INSN, JUMP_INSN, or CALL_INSN. */
2953 pat = PATTERN (trial);
2955 /* Stand-alone USE and CLOBBER are just for flow. */
2956 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2959 /* If this already has filled delay slots, get the insn needing
2961 if (GET_CODE (pat) == SEQUENCE)
2962 trial_delay = XVECEXP (pat, 0, 0);
2964 trial_delay = trial;
2966 /* If this is a jump insn to our target, indicate that we have
2967 seen another jump to it. If we aren't handling a conditional
2968 jump, stop our search. Otherwise, compute the needs at its
2969 target and add them to NEEDED. */
2970 if (GET_CODE (trial_delay) == JUMP_INSN)
2974 else if (JUMP_LABEL (trial_delay) == target)
2978 mark_target_live_regs
2979 (next_active_insn (JUMP_LABEL (trial_delay)),
2981 needed.memory |= needed_at_jump.memory;
2982 IOR_HARD_REG_SET (needed.regs, needed_at_jump.regs);
2986 /* See if we have a resource problem before we try to
2989 && GET_CODE (pat) != SEQUENCE
2990 && ! insn_references_resource_p (trial, &set, 1)
2991 && ! insn_sets_resource_p (trial, &set, 1)
2992 && ! insn_sets_resource_p (trial, &needed, 1)
2994 && ! (reg_mentioned_p (cc0_rtx, pat) && ! sets_cc0_p (pat))
2996 && ! (maybe_never && may_trap_p (pat))
2997 && (trial = try_split (pat, trial, 0))
2998 && eligible_for_delay (insn, slots_filled, trial, flags))
3000 next_trial = next_nonnote_insn (trial);
3001 delay_list = add_to_delay_list (trial, delay_list);
3004 if (reg_mentioned_p (cc0_rtx, pat))
3005 link_cc0_insns (trial);
3009 update_block (trial, trial);
3010 delete_insn (trial);
3011 if (slots_to_fill == ++slots_filled)
3016 mark_set_resources (trial, &set, 0, 1);
3017 mark_referenced_resources (trial, &needed, 1);
3019 /* Ensure we don't put insns between the setting of cc and the
3020 comparison by moving a setting of cc into an earlier delay
3021 slot since these insns could clobber the condition code. */
3024 /* If this is a call or jump, we might not get here. */
3025 if (GET_CODE (trial) == CALL_INSN
3026 || GET_CODE (trial) == JUMP_INSN)
3030 /* If there are slots left to fill and our search was stopped by an
3031 unconditional branch, try the insn at the branch target. We can
3032 redirect the branch if it works. */
3033 if (slots_to_fill != slots_filled
3035 && GET_CODE (trial) == JUMP_INSN
3036 && simplejump_p (trial)
3037 && (target == 0 || JUMP_LABEL (trial) == target)
3038 && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0
3039 && ! (GET_CODE (next_trial) == INSN
3040 && GET_CODE (PATTERN (next_trial)) == SEQUENCE)
3041 && ! insn_references_resource_p (next_trial, &set, 1)
3042 && ! insn_sets_resource_p (next_trial, &set, 1)
3043 && ! insn_sets_resource_p (next_trial, &needed, 1)
3045 && ! reg_mentioned_p (cc0_rtx, PATTERN (next_trial))
3047 && ! (maybe_never && may_trap_p (PATTERN (next_trial)))
3048 && (next_trial = try_split (PATTERN (next_trial), next_trial, 0))
3049 && eligible_for_delay (insn, slots_filled, next_trial, flags))
3051 rtx new_label = next_active_insn (next_trial);
3054 new_label = get_label_before (new_label);
3056 new_label = find_end_label ();
3059 = add_to_delay_list (copy_rtx (next_trial), delay_list);
3061 reorg_redirect_jump (trial, new_label);
3063 /* If we merged because we both jumped to the same place,
3064 redirect the original insn also. */
3066 reorg_redirect_jump (insn, new_label);
3071 unfilled_slots_base[i]
3072 = emit_delay_sequence (insn, delay_list,
3073 slots_filled, slots_to_fill);
3075 if (slots_to_fill == slots_filled)
3076 unfilled_slots_base[i] = 0;
3078 note_delay_statistics (slots_filled, 0);
3081 #ifdef DELAY_SLOTS_FOR_EPILOGUE
3082 /* See if the epilogue needs any delay slots. Try to fill them if so.
3083 The only thing we can do is scan backwards from the end of the
3084 function. If we did this in a previous pass, it is incorrect to do it
3086 if (current_function_epilogue_delay_list)
3089 slots_to_fill = DELAY_SLOTS_FOR_EPILOGUE;
3090 if (slots_to_fill == 0)
3094 needed = end_of_function_needs;
3095 CLEAR_RESOURCE (&set);
3097 for (trial = get_last_insn (); ! stop_search_p (trial, 1);
3098 trial = PREV_INSN (trial))
3100 if (GET_CODE (trial) == NOTE)
3102 pat = PATTERN (trial);
3103 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3106 if (! insn_references_resource_p (trial, &set, 1)
3107 && ! insn_sets_resource_p (trial, &needed, 1)
3109 /* Don't want to mess with cc0 here. */
3110 && ! reg_mentioned_p (cc0_rtx, pat)
3114 trial = try_split (pat, trial, 1);
3115 if (ELIGIBLE_FOR_EPILOGUE_DELAY (trial, slots_filled))
3117 /* Here as well we are searching backward, so put the
3118 insns we find on the head of the list. */
3120 current_function_epilogue_delay_list
3121 = gen_rtx (INSN_LIST, VOIDmode, trial,
3122 current_function_epilogue_delay_list);
3123 mark_referenced_resources (trial, &end_of_function_needs, 1);
3124 update_block (trial, trial);
3125 delete_insn (trial);
3127 /* Clear deleted bit so final.c will output the insn. */
3128 INSN_DELETED_P (trial) = 0;
3130 if (slots_to_fill == ++slots_filled)
3136 mark_set_resources (trial, &set, 0, 1);
3137 mark_referenced_resources (trial, &needed, 1);
3140 note_delay_statistics (slots_filled, 0);
3144 /* Try to find insns to place in delay slots.
3146 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
3147 or is an unconditional branch if CONDITION is const_true_rtx.
3148 *PSLOTS_FILLED is updated with the number of slots that we have filled.
3150 THREAD is a flow-of-control, either the insns to be executed if the
3151 branch is true or if the branch is false, THREAD_IF_TRUE says which.
3153 OPPOSITE_THREAD is the thread in the opposite direction. It is used
3154 to see if any potential delay slot insns set things needed there.
3156 LIKELY is non-zero if it is extremely likely that the branch will be
3157 taken and THREAD_IF_TRUE is set. This is used for the branch at the
3158 end of a loop back up to the top.
3160 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
3161 thread. I.e., it is the fallthrough code of our jump or the target of the
3162 jump when we are the only jump going there.
3164 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
3165 case, we can only take insns from the head of the thread for our delay
3166 slot. We then adjust the jump to point after the insns we have taken. */
3169 fill_slots_from_thread (insn, condition, thread, opposite_thread, likely,
3170 thread_if_true, own_thread, own_opposite_thread,
3171 slots_to_fill, pslots_filled)
3174 rtx thread, opposite_thread;
3177 int own_thread, own_opposite_thread;
3178 int slots_to_fill, *pslots_filled;
3182 struct resources opposite_needed, set, needed;
3188 /* Validate our arguments. */
3189 if ((condition == const_true_rtx && ! thread_if_true)
3190 || (! own_thread && ! thread_if_true))
3193 flags = get_jump_flags (insn, JUMP_LABEL (insn));
3195 /* If our thread is the end of subroutine, we can't get any delay
3200 /* If this is an unconditional branch, nothing is needed at the
3201 opposite thread. Otherwise, compute what is needed there. */
3202 if (condition == const_true_rtx)
3203 CLEAR_RESOURCE (&opposite_needed);
3205 mark_target_live_regs (opposite_thread, &opposite_needed);
3207 /* If the insn at THREAD can be split, do it here to avoid having to
3208 update THREAD and NEW_THREAD if it is done in the loop below. Also
3209 initialize NEW_THREAD. */
3211 new_thread = thread = try_split (PATTERN (thread), thread, 0);
3213 /* Scan insns at THREAD. We are looking for an insn that can be removed
3214 from THREAD (it neither sets nor references resources that were set
3215 ahead of it and it doesn't set anything needs by the insns ahead of
3216 it) and that either can be placed in an annulling insn or aren't
3217 needed at OPPOSITE_THREAD. */
3219 CLEAR_RESOURCE (&needed);
3220 CLEAR_RESOURCE (&set);
3222 /* If we do not own this thread, we must stop as soon as we find
3223 something that we can't put in a delay slot, since all we can do
3224 is branch into THREAD at a later point. Therefore, labels stop
3225 the search if this is not the `true' thread. */
3227 for (trial = thread;
3228 ! stop_search_p (trial, ! thread_if_true) && (! lose || own_thread);
3229 trial = next_nonnote_insn (trial))
3233 /* If we have passed a label, we no longer own this thread. */
3234 if (GET_CODE (trial) == CODE_LABEL)
3240 pat = PATTERN (trial);
3241 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3244 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
3245 don't separate or copy insns that set and use CC0. */
3246 if (! insn_references_resource_p (trial, &set, 1)
3247 && ! insn_sets_resource_p (trial, &set, 1)
3248 && ! insn_sets_resource_p (trial, &needed, 1)
3250 && ! (reg_mentioned_p (cc0_rtx, pat)
3251 && (! own_thread || ! sets_cc0_p (pat)))
3255 /* If TRIAL is redundant with some insn before INSN, we don't
3256 actually need to add it to the delay list; we can merely pretend
3258 if (redundant_insn_p (trial, insn, delay_list))
3262 update_block (trial, thread);
3263 delete_insn (trial);
3266 new_thread = next_active_insn (trial);
3271 /* There are two ways we can win: If TRIAL doesn't set anything
3272 needed at the opposite thread and can't trap, or if it can
3273 go into an annulled delay slot. */
3274 if (condition == const_true_rtx
3275 || (! insn_sets_resource_p (trial, &opposite_needed, 1)
3276 && ! may_trap_p (pat)))
3279 trial = try_split (pat, trial, 0);
3280 if (new_thread == old_trial)
3282 pat = PATTERN (trial);
3283 if (eligible_for_delay (insn, *pslots_filled, trial, flags))
3287 #ifdef ANNUL_IFTRUE_SLOTS
3290 #ifdef ANNUL_IFFALSE_SLOTS
3296 trial = try_split (pat, trial, 0);
3297 if (new_thread == old_trial)
3299 pat = PATTERN (trial);
3301 ? eligible_for_annul_false (insn, *pslots_filled, trial, flags)
3302 : eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
3310 if (reg_mentioned_p (cc0_rtx, pat))
3311 link_cc0_insns (trial);
3314 /* If we own this thread, delete the insn. If this is the
3315 destination of a branch, show that a basic block status
3316 may have been updated. In any case, mark the new
3317 starting point of this thread. */
3320 update_block (trial, thread);
3321 delete_insn (trial);
3324 new_thread = next_active_insn (trial);
3326 temp = own_thread ? trial : copy_rtx (trial);
3328 INSN_FROM_TARGET_P (temp) = 1;
3330 delay_list = add_to_delay_list (temp, delay_list);
3332 if (slots_to_fill == ++(*pslots_filled))
3334 /* Even though we have filled all the slots, we
3335 may be branching to a location that has a
3336 redundant insn. Skip any if so. */
3337 while (new_thread && ! own_thread
3338 && ! insn_sets_resource_p (new_thread, &set, 1)
3339 && ! insn_sets_resource_p (new_thread, &needed, 1)
3340 && ! insn_references_resource_p (new_thread,
3342 && redundant_insn_p (new_thread, insn,
3344 new_thread = next_active_insn (new_thread);
3353 /* This insn can't go into a delay slot. */
3355 mark_set_resources (trial, &set, 0, 1);
3356 mark_referenced_resources (trial, &needed, 1);
3358 /* Ensure we don't put insns between the setting of cc and the comparison
3359 by moving a setting of cc into an earlier delay slot since these insns
3360 could clobber the condition code. */
3363 /* If this insn is a register-register copy and the next insn has
3364 a use of our destination, change it to use our source. That way,
3365 it will become a candidate for our delay slot the next time
3366 through this loop. This case occurs commonly in loops that
3369 We could check for more complex cases than those tested below,
3370 but it doesn't seem worth it. It might also be a good idea to try
3371 to swap the two insns. That might do better.
3373 We can't do this if the next insn modifies our destination, because
3374 that would make the replacement into the insn invalid. We also can't
3375 do this if it modifies our source, because it might be an earlyclobber
3376 operand. This latter test also prevents updating the contents of
3379 if (GET_CODE (trial) == INSN && GET_CODE (pat) == SET
3380 && GET_CODE (SET_SRC (pat)) == REG
3381 && GET_CODE (SET_DEST (pat)) == REG)
3383 rtx next = next_nonnote_insn (trial);
3385 if (next && GET_CODE (next) == INSN
3386 && GET_CODE (PATTERN (next)) != USE
3387 && ! reg_set_p (SET_DEST (pat), next)
3388 && ! reg_set_p (SET_SRC (pat), next)
3389 && reg_referenced_p (SET_DEST (pat), PATTERN (next)))
3390 validate_replace_rtx (SET_DEST (pat), SET_SRC (pat), next);
3394 /* If we stopped on a branch insn that has delay slots, see if we can
3395 steal some of the insns in those slots. */
3396 if (trial && GET_CODE (trial) == INSN
3397 && GET_CODE (PATTERN (trial)) == SEQUENCE
3398 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN)
3400 /* If this is the `true' thread, we will want to follow the jump,
3401 so we can only do this if we have taken everything up to here. */
3402 if (thread_if_true && trial == new_thread)
3404 = steal_delay_list_from_target (insn, condition, PATTERN (trial),
3405 delay_list, &set, &needed,
3406 &opposite_needed, slots_to_fill,
3407 pslots_filled, &must_annul,
3409 else if (! thread_if_true)
3411 = steal_delay_list_from_fallthrough (insn, condition,
3413 delay_list, &set, &needed,
3414 &opposite_needed, slots_to_fill,
3415 pslots_filled, &must_annul);
3418 /* If we haven't found anything for this delay slot and it is very
3419 likely that the branch will be taken, see if the insn at our target
3420 increments or decrements a register with an increment that does not
3421 depend on the destination register. If so, try to place the opposite
3422 arithmetic insn after the jump insn and put the arithmetic insn in the
3423 delay slot. If we can't do this, return. */
3424 if (delay_list == 0 && likely && new_thread && GET_CODE (new_thread) == INSN)
3426 rtx pat = PATTERN (new_thread);
3431 pat = PATTERN (trial);
3433 if (GET_CODE (trial) != INSN || GET_CODE (pat) != SET
3434 || ! eligible_for_delay (insn, 0, trial, flags))
3437 dest = SET_DEST (pat), src = SET_SRC (pat);
3438 if ((GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
3439 && rtx_equal_p (XEXP (src, 0), dest)
3440 && ! reg_overlap_mentioned_p (dest, XEXP (src, 1)))
3442 rtx other = XEXP (src, 1);
3446 /* If this is a constant adjustment, use the same code with
3447 the negated constant. Otherwise, reverse the sense of the
3449 if (GET_CODE (other) == CONST_INT)
3450 new_arith = gen_rtx (GET_CODE (src), GET_MODE (src), dest,
3451 negate_rtx (GET_MODE (src), other));
3453 new_arith = gen_rtx (GET_CODE (src) == PLUS ? MINUS : PLUS,
3454 GET_MODE (src), dest, other);
3456 ninsn = emit_insn_after (gen_rtx (SET, VOIDmode, dest, new_arith),
3459 if (recog_memoized (ninsn) < 0
3460 || (insn_extract (ninsn),
3461 ! constrain_operands (INSN_CODE (ninsn), 1)))
3463 delete_insn (ninsn);
3469 update_block (trial, thread);
3470 delete_insn (trial);
3473 new_thread = next_active_insn (trial);
3475 ninsn = own_thread ? trial : copy_rtx (trial);
3477 INSN_FROM_TARGET_P (ninsn) = 1;
3479 delay_list = add_to_delay_list (ninsn, NULL_RTX);
3484 if (delay_list && must_annul)
3485 INSN_ANNULLED_BRANCH_P (insn) = 1;
3487 /* If we are to branch into the middle of this thread, find an appropriate
3488 label or make a new one if none, and redirect INSN to it. If we hit the
3489 end of the function, use the end-of-function label. */
3490 if (new_thread != thread)
3494 if (! thread_if_true)
3497 if (new_thread && GET_CODE (new_thread) == JUMP_INSN
3498 && (simplejump_p (new_thread)
3499 || GET_CODE (PATTERN (new_thread)) == RETURN)
3500 && redirect_with_delay_list_safe_p (insn,
3501 JUMP_LABEL (new_thread),
3503 new_thread = follow_jumps (JUMP_LABEL (new_thread));
3505 if (new_thread == 0)
3506 label = find_end_label ();
3507 else if (GET_CODE (new_thread) == CODE_LABEL)
3510 label = get_label_before (new_thread);
3512 reorg_redirect_jump (insn, label);
3518 /* Make another attempt to find insns to place in delay slots.
3520 We previously looked for insns located in front of the delay insn
3521 and, for non-jump delay insns, located behind the delay insn.
3523 Here only try to schedule jump insns and try to move insns from either
3524 the target or the following insns into the delay slot. If annulling is
3525 supported, we will be likely to do this. Otherwise, we can do this only
3529 fill_eager_delay_slots (first)
3534 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
3536 for (i = 0; i < num_unfilled_slots; i++)
3539 rtx target_label, insn_at_target, fallthrough_insn;
3542 int own_fallthrough;
3543 int prediction, slots_to_fill, slots_filled;
3545 insn = unfilled_slots_base[i];
3547 || INSN_DELETED_P (insn)
3548 || GET_CODE (insn) != JUMP_INSN
3549 || ! condjump_p (insn))
3552 slots_to_fill = num_delay_slots (insn);
3553 if (slots_to_fill == 0)
3557 target_label = JUMP_LABEL (insn);
3558 condition = get_branch_condition (insn, target_label);
3563 /* Get the next active fallthough and target insns and see if we own
3564 them. Then see whether the branch is likely true. We don't need
3565 to do a lot of this for unconditional branches. */
3567 insn_at_target = next_active_insn (target_label);
3568 own_target = own_thread_p (target_label, target_label, 0);
3570 if (condition == const_true_rtx)
3572 own_fallthrough = 0;
3573 fallthrough_insn = 0;
3578 fallthrough_insn = next_active_insn (insn);
3579 own_fallthrough = own_thread_p (NEXT_INSN (insn), NULL_RTX, 1);
3580 prediction = mostly_true_jump (insn, condition);
3583 /* If this insn is expected to branch, first try to get insns from our
3584 target, then our fallthrough insns. If it is not, expected to branch,
3585 try the other order. */
3590 = fill_slots_from_thread (insn, condition, insn_at_target,
3591 fallthrough_insn, prediction == 2, 1,
3592 own_target, own_fallthrough,
3593 slots_to_fill, &slots_filled);
3595 if (delay_list == 0 && own_fallthrough)
3597 /* Even though we didn't find anything for delay slots,
3598 we might have found a redundant insn which we deleted
3599 from the thread that was filled. So we have to recompute
3600 the next insn at the target. */
3601 target_label = JUMP_LABEL (insn);
3602 insn_at_target = next_active_insn (target_label);
3605 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3606 insn_at_target, 0, 0,
3607 own_fallthrough, own_target,
3608 slots_to_fill, &slots_filled);
3613 if (own_fallthrough)
3615 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3616 insn_at_target, 0, 0,
3617 own_fallthrough, own_target,
3618 slots_to_fill, &slots_filled);
3620 if (delay_list == 0)
3622 = fill_slots_from_thread (insn, condition, insn_at_target,
3623 next_active_insn (insn), 0, 1,
3624 own_target, own_fallthrough,
3625 slots_to_fill, &slots_filled);
3629 unfilled_slots_base[i]
3630 = emit_delay_sequence (insn, delay_list,
3631 slots_filled, slots_to_fill);
3633 if (slots_to_fill == slots_filled)
3634 unfilled_slots_base[i] = 0;
3636 note_delay_statistics (slots_filled, 1);
3640 /* Once we have tried two ways to fill a delay slot, make a pass over the
3641 code to try to improve the results and to do such things as more jump
3645 relax_delay_slots (first)
3648 register rtx insn, next, pat;
3649 register rtx trial, delay_insn, target_label;
3651 /* Look at every JUMP_INSN and see if we can improve it. */
3652 for (insn = first; insn; insn = next)
3656 next = next_active_insn (insn);
3658 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3659 the next insn, or jumps to a label that is not the last of a
3660 group of consecutive labels. */
3661 if (GET_CODE (insn) == JUMP_INSN
3662 && condjump_p (insn)
3663 && (target_label = JUMP_LABEL (insn)) != 0)
3665 target_label = follow_jumps (target_label);
3666 target_label = prev_label (next_active_insn (target_label));
3668 if (target_label == 0)
3669 target_label = find_end_label ();
3671 if (next_active_insn (target_label) == next)
3677 if (target_label != JUMP_LABEL (insn))
3678 reorg_redirect_jump (insn, target_label);
3680 /* See if this jump branches around a unconditional jump.
3681 If so, invert this jump and point it to the target of the
3683 if (next && GET_CODE (next) == JUMP_INSN
3684 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
3685 && next_active_insn (target_label) == next_active_insn (next)
3686 && no_labels_between_p (insn, next))
3688 rtx label = JUMP_LABEL (next);
3690 /* Be careful how we do this to avoid deleting code or
3691 labels that are momentarily dead. See similar optimization
3694 We also need to ensure we properly handle the case when
3695 invert_jump fails. */
3697 ++LABEL_NUSES (target_label);
3699 ++LABEL_NUSES (label);
3701 if (invert_jump (insn, label))
3708 --LABEL_NUSES (label);
3710 if (--LABEL_NUSES (target_label) == 0)
3711 delete_insn (target_label);
3717 /* If this is an unconditional jump and the previous insn is a
3718 conditional jump, try reversing the condition of the previous
3719 insn and swapping our targets. The next pass might be able to
3722 Don't do this if we expect the conditional branch to be true, because
3723 we would then be making the more common case longer. */
3725 if (GET_CODE (insn) == JUMP_INSN
3726 && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN)
3727 && (other = prev_active_insn (insn)) != 0
3728 && condjump_p (other)
3729 && no_labels_between_p (other, insn)
3730 && 0 < mostly_true_jump (other,
3731 get_branch_condition (other,
3732 JUMP_LABEL (other))))
3734 rtx other_target = JUMP_LABEL (other);
3735 target_label = JUMP_LABEL (insn);
3737 /* Increment the count of OTHER_TARGET, so it doesn't get deleted
3738 as we move the label. */
3740 ++LABEL_NUSES (other_target);
3742 if (invert_jump (other, target_label))
3743 reorg_redirect_jump (insn, other_target);
3746 --LABEL_NUSES (other_target);
3749 /* Now look only at cases where we have filled a delay slot. */
3750 if (GET_CODE (insn) != INSN
3751 || GET_CODE (PATTERN (insn)) != SEQUENCE)
3754 pat = PATTERN (insn);
3755 delay_insn = XVECEXP (pat, 0, 0);
3757 /* See if the first insn in the delay slot is redundant with some
3758 previous insn. Remove it from the delay slot if so; then set up
3759 to reprocess this insn. */
3760 if (redundant_insn_p (XVECEXP (pat, 0, 1), delay_insn, 0))
3762 delete_from_delay_slot (XVECEXP (pat, 0, 1));
3763 next = prev_active_insn (next);
3767 /* Now look only at the cases where we have a filled JUMP_INSN. */
3768 if (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
3769 || ! condjump_p (XVECEXP (PATTERN (insn), 0, 0)))
3772 target_label = JUMP_LABEL (delay_insn);
3776 /* If this jump goes to another unconditional jump, thread it, but
3777 don't convert a jump into a RETURN here. */
3778 trial = follow_jumps (target_label);
3779 trial = prev_label (next_active_insn (trial));
3780 if (trial == 0 && target_label != 0)
3781 trial = find_end_label ();
3783 if (trial != target_label
3784 && redirect_with_delay_slots_safe_p (delay_insn, trial, insn))
3786 reorg_redirect_jump (delay_insn, trial);
3787 target_label = trial;
3790 /* If the first insn at TARGET_LABEL is redundant with a previous
3791 insn, redirect the jump to the following insn process again. */
3792 trial = next_active_insn (target_label);
3793 if (trial && GET_CODE (PATTERN (trial)) != SEQUENCE
3794 && redundant_insn_p (trial, insn, 0))
3796 trial = next_active_insn (trial);
3798 target_label = find_end_label ();
3800 target_label = get_label_before (trial);
3801 reorg_redirect_jump (delay_insn, target_label);
3806 /* Similarly, if it is an unconditional jump with one insn in its
3807 delay list and that insn is redundant, thread the jump. */
3808 if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE
3809 && XVECLEN (PATTERN (trial), 0) == 2
3810 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN
3811 && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0))
3812 || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN)
3813 && redundant_insn_p (XVECEXP (PATTERN (trial), 0, 1), insn, 0))
3815 target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0));
3816 if (target_label == 0)
3817 target_label = find_end_label ();
3819 if (redirect_with_delay_slots_safe_p (delay_insn, target_label,
3822 reorg_redirect_jump (delay_insn, target_label);
3829 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
3830 && prev_active_insn (target_label) == insn
3832 /* If the last insn in the delay slot sets CC0 for some insn,
3833 various code assumes that it is in a delay slot. We could
3834 put it back where it belonged and delete the register notes,
3835 but it doesn't seem worthwhile in this uncommon case. */
3836 && ! find_reg_note (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1),
3837 REG_CC_USER, NULL_RTX)
3843 /* All this insn does is execute its delay list and jump to the
3844 following insn. So delete the jump and just execute the delay
3847 We do this by deleting the INSN containing the SEQUENCE, then
3848 re-emitting the insns separately, and then deleting the jump.
3849 This allows the count of the jump target to be properly
3852 /* Clear the from target bit, since these insns are no longer
3854 for (i = 0; i < XVECLEN (pat, 0); i++)
3855 INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)) = 0;
3857 trial = PREV_INSN (insn);
3859 emit_insn_after (pat, trial);
3860 delete_scheduled_jump (delay_insn);
3864 /* See if this is an unconditional jump around a single insn which is
3865 identical to the one in its delay slot. In this case, we can just
3866 delete the branch and the insn in its delay slot. */
3867 if (next && GET_CODE (next) == INSN
3868 && prev_label (next_active_insn (next)) == target_label
3869 && simplejump_p (insn)
3870 && XVECLEN (pat, 0) == 2
3871 && rtx_equal_p (PATTERN (next), PATTERN (XVECEXP (pat, 0, 1))))
3877 /* See if this jump (with its delay slots) branches around another
3878 jump (without delay slots). If so, invert this jump and point
3879 it to the target of the second jump. We cannot do this for
3880 annulled jumps, though. Again, don't convert a jump to a RETURN
3882 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
3883 && next && GET_CODE (next) == JUMP_INSN
3884 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
3885 && next_active_insn (target_label) == next_active_insn (next)
3886 && no_labels_between_p (insn, next))
3888 rtx label = JUMP_LABEL (next);
3889 rtx old_label = JUMP_LABEL (delay_insn);
3892 label = find_end_label ();
3894 if (redirect_with_delay_slots_safe_p (delay_insn, label, insn))
3896 /* Be careful how we do this to avoid deleting code or labels
3897 that are momentarily dead. See similar optimization in
3900 ++LABEL_NUSES (old_label);
3902 if (invert_jump (delay_insn, label))
3908 if (old_label && --LABEL_NUSES (old_label) == 0)
3909 delete_insn (old_label);
3914 /* If we own the thread opposite the way this insn branches, see if we
3915 can merge its delay slots with following insns. */
3916 if (INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
3917 && own_thread_p (NEXT_INSN (insn), 0, 1))
3918 try_merge_delay_insns (insn, next);
3919 else if (! INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
3920 && own_thread_p (target_label, target_label, 0))
3921 try_merge_delay_insns (insn, next_active_insn (target_label));
3923 /* If we get here, we haven't deleted INSN. But we may have deleted
3924 NEXT, so recompute it. */
3925 next = next_active_insn (insn);
3931 /* Look for filled jumps to the end of function label. We can try to convert
3932 them into RETURN insns if the insns in the delay slot are valid for the
3936 make_return_insns (first)
3939 rtx insn, jump_insn, pat;
3940 rtx real_return_label = end_of_function_label;
3943 /* See if there is a RETURN insn in the function other than the one we
3944 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3945 into a RETURN to jump to it. */
3946 for (insn = first; insn; insn = NEXT_INSN (insn))
3947 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) == RETURN)
3949 real_return_label = get_label_before (insn);
3953 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3954 was equal to END_OF_FUNCTION_LABEL. */
3955 LABEL_NUSES (real_return_label)++;
3957 /* Clear the list of insns to fill so we can use it. */
3958 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
3960 for (insn = first; insn; insn = NEXT_INSN (insn))
3964 /* Only look at filled JUMP_INSNs that go to the end of function
3966 if (GET_CODE (insn) != INSN
3967 || GET_CODE (PATTERN (insn)) != SEQUENCE
3968 || GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
3969 || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label)
3972 pat = PATTERN (insn);
3973 jump_insn = XVECEXP (pat, 0, 0);
3975 /* If we can't make the jump into a RETURN, redirect it to the best
3976 RETURN and go on to the next insn. */
3977 if (! reorg_redirect_jump (jump_insn, NULL_RTX))
3979 reorg_redirect_jump (jump_insn, real_return_label);
3983 /* See if this RETURN can accept the insns current in its delay slot.
3984 It can if it has more or an equal number of slots and the contents
3985 of each is valid. */
3987 flags = get_jump_flags (jump_insn, JUMP_LABEL (jump_insn));
3988 slots = num_delay_slots (jump_insn);
3989 if (slots >= XVECLEN (pat, 0) - 1)
3991 for (i = 1; i < XVECLEN (pat, 0); i++)
3993 #ifdef ANNUL_IFFALSE_SLOTS
3994 (INSN_ANNULLED_BRANCH_P (jump_insn)
3995 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
3996 ? eligible_for_annul_false (jump_insn, i - 1,
3997 XVECEXP (pat, 0, i), flags) :
3999 #ifdef ANNUL_IFTRUE_SLOTS
4000 (INSN_ANNULLED_BRANCH_P (jump_insn)
4001 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
4002 ? eligible_for_annul_true (jump_insn, i - 1,
4003 XVECEXP (pat, 0, i), flags) :
4005 eligible_for_delay (jump_insn, i -1, XVECEXP (pat, 0, i), flags)))
4011 if (i == XVECLEN (pat, 0))
4014 /* We have to do something with this insn. If it is an unconditional
4015 RETURN, delete the SEQUENCE and output the individual insns,
4016 followed by the RETURN. Then set things up so we try to find
4017 insns for its delay slots, if it needs some. */
4018 if (GET_CODE (PATTERN (jump_insn)) == RETURN)
4020 rtx prev = PREV_INSN (insn);
4023 for (i = 1; i < XVECLEN (pat, 0); i++)
4024 prev = emit_insn_after (PATTERN (XVECEXP (pat, 0, i)), prev);
4026 insn = emit_jump_insn_after (PATTERN (jump_insn), prev);
4027 emit_barrier_after (insn);
4030 obstack_ptr_grow (&unfilled_slots_obstack, insn);
4033 /* It is probably more efficient to keep this with its current
4034 delay slot as a branch to a RETURN. */
4035 reorg_redirect_jump (jump_insn, real_return_label);
4038 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
4039 new delay slots we have created. */
4040 if (--LABEL_NUSES (real_return_label) == 0)
4041 delete_insn (real_return_label);
4043 fill_simple_delay_slots (first, 1);
4044 fill_simple_delay_slots (first, 0);
4048 /* Try to find insns to place in delay slots. */
4051 dbr_schedule (first, file)
4055 rtx insn, next, epilogue_insn = 0;
4058 int old_flag_no_peephole = flag_no_peephole;
4060 /* Execute `final' once in prescan mode to delete any insns that won't be
4061 used. Don't let final try to do any peephole optimization--it will
4062 ruin dataflow information for this pass. */
4064 flag_no_peephole = 1;
4065 final (first, 0, NO_DEBUG, 1, 1);
4066 flag_no_peephole = old_flag_no_peephole;
4069 /* If the current function has no insns other than the prologue and
4070 epilogue, then do not try to fill any delay slots. */
4071 if (n_basic_blocks == 0)
4074 /* Find the highest INSN_UID and allocate and initialize our map from
4075 INSN_UID's to position in code. */
4076 for (max_uid = 0, insn = first; insn; insn = NEXT_INSN (insn))
4078 if (INSN_UID (insn) > max_uid)
4079 max_uid = INSN_UID (insn);
4080 if (GET_CODE (insn) == NOTE
4081 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG)
4082 epilogue_insn = insn;
4085 uid_to_ruid = (int *) alloca ((max_uid + 1) * sizeof (int *));
4086 for (i = 0, insn = first; insn; i++, insn = NEXT_INSN (insn))
4087 uid_to_ruid[INSN_UID (insn)] = i;
4089 /* Initialize the list of insns that need filling. */
4090 if (unfilled_firstobj == 0)
4092 gcc_obstack_init (&unfilled_slots_obstack);
4093 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4096 for (insn = next_active_insn (first); insn; insn = next_active_insn (insn))
4100 INSN_ANNULLED_BRANCH_P (insn) = 0;
4101 INSN_FROM_TARGET_P (insn) = 0;
4103 /* Skip vector tables. We can't get attributes for them. */
4104 if (GET_CODE (insn) == JUMP_INSN
4105 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
4106 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
4109 if (num_delay_slots (insn) > 0)
4110 obstack_ptr_grow (&unfilled_slots_obstack, insn);
4112 /* Ensure all jumps go to the last of a set of consecutive labels. */
4113 if (GET_CODE (insn) == JUMP_INSN && condjump_p (insn)
4114 && JUMP_LABEL (insn) != 0
4115 && ((target = prev_label (next_active_insn (JUMP_LABEL (insn))))
4116 != JUMP_LABEL (insn)))
4117 redirect_jump (insn, target);
4120 /* Indicate what resources are required to be valid at the end of the current
4121 function. The condition code never is and memory always is. If the
4122 frame pointer is needed, it is and so is the stack pointer unless
4123 EXIT_IGNORE_STACK is non-zero. If the frame pointer is not needed, the
4124 stack pointer is. Registers used to return the function value are
4125 needed. Registers holding global variables are needed. */
4127 end_of_function_needs.cc = 0;
4128 end_of_function_needs.memory = 1;
4129 CLEAR_HARD_REG_SET (end_of_function_needs.regs);
4131 if (frame_pointer_needed)
4133 SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM);
4134 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
4135 SET_HARD_REG_BIT (end_of_function_needs.regs, HARD_FRAME_POINTER_REGNUM);
4137 #ifdef EXIT_IGNORE_STACK
4138 if (! EXIT_IGNORE_STACK)
4140 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4143 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4145 if (current_function_return_rtx != 0
4146 && GET_CODE (current_function_return_rtx) == REG)
4147 mark_referenced_resources (current_function_return_rtx,
4148 &end_of_function_needs, 1);
4150 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4152 SET_HARD_REG_BIT (end_of_function_needs.regs, i);
4154 /* The registers required to be live at the end of the function are
4155 represented in the flow information as being dead just prior to
4156 reaching the end of the function. For example, the return of a value
4157 might be represented by a USE of the return register immediately
4158 followed by an unconditional jump to the return label where the
4159 return label is the end of the RTL chain. The end of the RTL chain
4160 is then taken to mean that the return register is live.
4162 This sequence is no longer maintained when epilogue instructions are
4163 added to the RTL chain. To reconstruct the original meaning, the
4164 start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the
4165 point where these registers become live (start_of_epilogue_needs).
4166 If epilogue instructions are present, the registers set by those
4167 instructions won't have been processed by flow. Thus, those
4168 registers are additionally required at the end of the RTL chain
4169 (end_of_function_needs). */
4171 start_of_epilogue_needs = end_of_function_needs;
4173 while (epilogue_insn = next_nonnote_insn (epilogue_insn))
4174 mark_set_resources (epilogue_insn, &end_of_function_needs, 0, 1);
4176 /* Show we haven't computed an end-of-function label yet. */
4177 end_of_function_label = 0;
4179 /* Allocate and initialize the tables used by mark_target_live_regs. */
4181 = (struct target_info **) alloca ((TARGET_HASH_PRIME
4182 * sizeof (struct target_info *)));
4183 bzero (target_hash_table, TARGET_HASH_PRIME * sizeof (struct target_info *));
4185 bb_ticks = (int *) alloca (n_basic_blocks * sizeof (int));
4186 bzero (bb_ticks, n_basic_blocks * sizeof (int));
4188 /* Initialize the statistics for this function. */
4189 bzero (num_insns_needing_delays, sizeof num_insns_needing_delays);
4190 bzero (num_filled_delays, sizeof num_filled_delays);
4192 /* Now do the delay slot filling. Try everything twice in case earlier
4193 changes make more slots fillable. */
4195 for (reorg_pass_number = 0;
4196 reorg_pass_number < MAX_REORG_PASSES;
4197 reorg_pass_number++)
4199 fill_simple_delay_slots (first, 1);
4200 fill_simple_delay_slots (first, 0);
4201 fill_eager_delay_slots (first);
4202 relax_delay_slots (first);
4205 /* Delete any USE insns made by update_block; subsequent passes don't need
4206 them or know how to deal with them. */
4207 for (insn = first; insn; insn = next)
4209 next = NEXT_INSN (insn);
4211 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
4212 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
4213 next = delete_insn (insn);
4216 /* If we made an end of function label, indicate that it is now
4217 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
4218 If it is now unused, delete it. */
4219 if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0)
4220 delete_insn (end_of_function_label);
4223 if (HAVE_return && end_of_function_label != 0)
4224 make_return_insns (first);
4227 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
4229 /* It is not clear why the line below is needed, but it does seem to be. */
4230 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4232 /* Reposition the prologue and epilogue notes in case we moved the
4233 prologue/epilogue insns. */
4234 reposition_prologue_and_epilogue_notes (first);
4238 register int i, j, need_comma;
4240 for (reorg_pass_number = 0;
4241 reorg_pass_number < MAX_REORG_PASSES;
4242 reorg_pass_number++)
4244 fprintf (file, ";; Reorg pass #%d:\n", reorg_pass_number + 1);
4245 for (i = 0; i < NUM_REORG_FUNCTIONS; i++)
4248 fprintf (file, ";; Reorg function #%d\n", i);
4250 fprintf (file, ";; %d insns needing delay slots\n;; ",
4251 num_insns_needing_delays[i][reorg_pass_number]);
4253 for (j = 0; j < MAX_DELAY_HISTOGRAM; j++)
4254 if (num_filled_delays[i][j][reorg_pass_number])
4257 fprintf (file, ", ");
4259 fprintf (file, "%d got %d delays",
4260 num_filled_delays[i][j][reorg_pass_number], j);
4262 fprintf (file, "\n");
4267 #endif /* DELAY_SLOTS */