1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static bool inherit_piecemeal_p (int, int);
438 static void emit_reload_insns (struct insn_chain *);
439 static void delete_output_reload (rtx, int, int);
440 static void delete_address_reloads (rtx, rtx);
441 static void delete_address_reloads_1 (rtx, rtx, rtx);
442 static rtx inc_for_reload (rtx, rtx, rtx, int);
444 static void add_auto_inc_notes (rtx, rtx);
446 static void copy_eh_notes (rtx, rtx);
447 static int reloads_conflict (int, int);
448 static rtx gen_reload (rtx, rtx, int, enum reload_type);
449 static rtx emit_insn_if_valid_for_reload (rtx);
451 /* Initialize the reload pass. This is called at the beginning of compilation
452 and may be called again if the target is reinitialized. */
459 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
460 Set spill_indirect_levels to the number of levels such addressing is
461 permitted, zero if it is not permitted at all. */
464 = gen_rtx_MEM (Pmode,
467 LAST_VIRTUAL_REGISTER + 1),
469 spill_indirect_levels = 0;
471 while (memory_address_p (QImode, tem))
473 spill_indirect_levels++;
474 tem = gen_rtx_MEM (Pmode, tem);
477 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
479 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
480 indirect_symref_ok = memory_address_p (QImode, tem);
482 /* See if reg+reg is a valid (and offsettable) address. */
484 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
486 tem = gen_rtx_PLUS (Pmode,
487 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
488 gen_rtx_REG (Pmode, i));
490 /* This way, we make sure that reg+reg is an offsettable address. */
491 tem = plus_constant (tem, 4);
493 if (memory_address_p (QImode, tem))
495 double_reg_address_ok = 1;
500 /* Initialize obstack for our rtl allocation. */
501 gcc_obstack_init (&reload_obstack);
502 reload_startobj = obstack_alloc (&reload_obstack, 0);
504 INIT_REG_SET (&spilled_pseudos);
505 INIT_REG_SET (&pseudos_counted);
508 /* List of insn chains that are currently unused. */
509 static struct insn_chain *unused_insn_chains = 0;
511 /* Allocate an empty insn_chain structure. */
513 new_insn_chain (void)
515 struct insn_chain *c;
517 if (unused_insn_chains == 0)
519 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
520 INIT_REG_SET (&c->live_throughout);
521 INIT_REG_SET (&c->dead_or_set);
525 c = unused_insn_chains;
526 unused_insn_chains = c->next;
528 c->is_caller_save_insn = 0;
529 c->need_operand_change = 0;
535 /* Small utility function to set all regs in hard reg set TO which are
536 allocated to pseudos in regset FROM. */
539 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
542 reg_set_iterator rsi;
544 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
546 int r = reg_renumber[regno];
550 /* reload_combine uses the information from
551 DF_RA_LIVE_IN (BASIC_BLOCK), which might still
552 contain registers that have not actually been allocated
553 since they have an equivalence. */
554 gcc_assert (reload_completed);
557 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
561 /* Replace all pseudos found in LOC with their corresponding
565 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
578 unsigned int regno = REGNO (x);
580 if (regno < FIRST_PSEUDO_REGISTER)
583 x = eliminate_regs (x, mem_mode, usage);
587 replace_pseudos_in (loc, mem_mode, usage);
591 if (reg_equiv_constant[regno])
592 *loc = reg_equiv_constant[regno];
593 else if (reg_equiv_mem[regno])
594 *loc = reg_equiv_mem[regno];
595 else if (reg_equiv_address[regno])
596 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
599 gcc_assert (!REG_P (regno_reg_rtx[regno])
600 || REGNO (regno_reg_rtx[regno]) != regno);
601 *loc = regno_reg_rtx[regno];
606 else if (code == MEM)
608 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
612 /* Process each of our operands recursively. */
613 fmt = GET_RTX_FORMAT (code);
614 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
616 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
617 else if (*fmt == 'E')
618 for (j = 0; j < XVECLEN (x, i); j++)
619 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
622 /* Determine if the current function has an exception receiver block
623 that reaches the exit block via non-exceptional edges */
626 has_nonexceptional_receiver (void)
630 basic_block *tos, *worklist, bb;
632 /* If we're not optimizing, then just err on the safe side. */
636 /* First determine which blocks can reach exit via normal paths. */
637 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
640 bb->flags &= ~BB_REACHABLE;
642 /* Place the exit block on our worklist. */
643 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
644 *tos++ = EXIT_BLOCK_PTR;
646 /* Iterate: find everything reachable from what we've already seen. */
647 while (tos != worklist)
651 FOR_EACH_EDGE (e, ei, bb->preds)
652 if (!(e->flags & EDGE_ABNORMAL))
654 basic_block src = e->src;
656 if (!(src->flags & BB_REACHABLE))
658 src->flags |= BB_REACHABLE;
665 /* Now see if there's a reachable block with an exceptional incoming
668 if (bb->flags & BB_REACHABLE)
669 FOR_EACH_EDGE (e, ei, bb->preds)
670 if (e->flags & EDGE_ABNORMAL)
673 /* No exceptional block reached exit unexceptionally. */
678 /* Global variables used by reload and its subroutines. */
680 /* Set during calculate_needs if an insn needs register elimination. */
681 static int something_needs_elimination;
682 /* Set during calculate_needs if an insn needs an operand changed. */
683 static int something_needs_operands_changed;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is nonzero if reload failed
699 and we must not do any more for this function. */
702 reload (rtx first, int global)
706 struct elim_table *ep;
709 /* Make sure even insns with volatile mem refs are recognizable. */
714 reload_firstobj = obstack_alloc (&reload_obstack, 0);
716 /* Make sure that the last insn in the chain
717 is not something that needs reloading. */
718 emit_note (NOTE_INSN_DELETED);
720 /* Enable find_equiv_reg to distinguish insns made by reload. */
721 reload_first_uid = get_max_uid ();
723 #ifdef SECONDARY_MEMORY_NEEDED
724 /* Initialize the secondary memory table. */
725 clear_secondary_mem ();
728 /* We don't have a stack slot for any spill reg yet. */
729 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
730 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
732 /* Initialize the save area information for caller-save, in case some
736 /* Compute which hard registers are now in use
737 as homes for pseudo registers.
738 This is done here rather than (eg) in global_alloc
739 because this point is reached even if not optimizing. */
740 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
743 /* A function that has a nonlocal label that can reach the exit
744 block via non-exceptional paths must save all call-saved
746 if (current_function_has_nonlocal_label
747 && has_nonexceptional_receiver ())
748 current_function_saves_all_registers = 1;
750 if (current_function_saves_all_registers)
751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
752 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
753 df_set_regs_ever_live (i, true);
755 /* Find all the pseudo registers that didn't get hard regs
756 but do have known equivalent constants or memory slots.
757 These include parameters (known equivalent to parameter slots)
758 and cse'd or loop-moved constant memory addresses.
760 Record constant equivalents in reg_equiv_constant
761 so they will be substituted by find_reloads.
762 Record memory equivalents in reg_mem_equiv so they can
763 be substituted eventually by altering the REG-rtx's. */
765 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
766 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
767 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
768 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
769 reg_equiv_address = XCNEWVEC (rtx, max_regno);
770 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
771 reg_old_renumber = XCNEWVEC (short, max_regno);
772 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
773 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
774 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
776 CLEAR_HARD_REG_SET (bad_spill_regs_global);
778 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
779 to. Also find all paradoxical subregs and find largest such for
782 num_eliminable_invariants = 0;
783 for (insn = first; insn; insn = NEXT_INSN (insn))
785 rtx set = single_set (insn);
787 /* We may introduce USEs that we want to remove at the end, so
788 we'll mark them with QImode. Make sure there are no
789 previously-marked insns left by say regmove. */
790 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
791 && GET_MODE (insn) != VOIDmode)
792 PUT_MODE (insn, VOIDmode);
795 scan_paradoxical_subregs (PATTERN (insn));
797 if (set != 0 && REG_P (SET_DEST (set)))
799 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
805 i = REGNO (SET_DEST (set));
808 if (i <= LAST_VIRTUAL_REGISTER)
811 if (! function_invariant_p (x)
813 /* A function invariant is often CONSTANT_P but may
814 include a register. We promise to only pass
815 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
817 && LEGITIMATE_PIC_OPERAND_P (x)))
819 /* It can happen that a REG_EQUIV note contains a MEM
820 that is not a legitimate memory operand. As later
821 stages of reload assume that all addresses found
822 in the reg_equiv_* arrays were originally legitimate,
823 we ignore such REG_EQUIV notes. */
824 if (memory_operand (x, VOIDmode))
826 /* Always unshare the equivalence, so we can
827 substitute into this insn without touching the
829 reg_equiv_memory_loc[i] = copy_rtx (x);
831 else if (function_invariant_p (x))
833 if (GET_CODE (x) == PLUS)
835 /* This is PLUS of frame pointer and a constant,
836 and might be shared. Unshare it. */
837 reg_equiv_invariant[i] = copy_rtx (x);
838 num_eliminable_invariants++;
840 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
842 reg_equiv_invariant[i] = x;
843 num_eliminable_invariants++;
845 else if (LEGITIMATE_CONSTANT_P (x))
846 reg_equiv_constant[i] = x;
849 reg_equiv_memory_loc[i]
850 = force_const_mem (GET_MODE (SET_DEST (set)), x);
851 if (! reg_equiv_memory_loc[i])
852 reg_equiv_init[i] = NULL_RTX;
857 reg_equiv_init[i] = NULL_RTX;
862 reg_equiv_init[i] = NULL_RTX;
867 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
868 if (reg_equiv_init[i])
870 fprintf (dump_file, "init_insns for %u: ", i);
871 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
872 fprintf (dump_file, "\n");
877 first_label_num = get_first_label_num ();
878 num_labels = max_label_num () - first_label_num;
880 /* Allocate the tables used to store offset information at labels. */
881 /* We used to use alloca here, but the size of what it would try to
882 allocate would occasionally cause it to exceed the stack limit and
883 cause a core dump. */
884 offsets_known_at = XNEWVEC (char, num_labels);
885 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
887 /* Alter each pseudo-reg rtx to contain its hard reg number.
888 Assign stack slots to the pseudos that lack hard regs or equivalents.
889 Do not touch virtual registers. */
891 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
894 /* If we have some registers we think can be eliminated, scan all insns to
895 see if there is an insn that sets one of these registers to something
896 other than itself plus a constant. If so, the register cannot be
897 eliminated. Doing this scan here eliminates an extra pass through the
898 main reload loop in the most common case where register elimination
900 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
902 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
904 maybe_fix_stack_asms ();
906 insns_need_reload = 0;
907 something_needs_elimination = 0;
909 /* Initialize to -1, which means take the first spill register. */
912 /* Spill any hard regs that we know we can't eliminate. */
913 CLEAR_HARD_REG_SET (used_spill_regs);
914 /* There can be multiple ways to eliminate a register;
915 they should be listed adjacently.
916 Elimination for any register fails only if all possible ways fail. */
917 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
920 int can_eliminate = 0;
923 can_eliminate |= ep->can_eliminate;
926 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
928 spill_hard_reg (from, 1);
931 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
932 if (frame_pointer_needed)
933 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
935 finish_spills (global);
937 /* From now on, we may need to generate moves differently. We may also
938 allow modifications of insns which cause them to not be recognized.
939 Any such modifications will be cleaned up during reload itself. */
940 reload_in_progress = 1;
942 /* This loop scans the entire function each go-round
943 and repeats until one repetition spills no additional hard regs. */
946 int something_changed;
948 HOST_WIDE_INT starting_frame_size;
950 starting_frame_size = get_frame_size ();
952 set_initial_elim_offsets ();
953 set_initial_label_offsets ();
955 /* For each pseudo register that has an equivalent location defined,
956 try to eliminate any eliminable registers (such as the frame pointer)
957 assuming initial offsets for the replacement register, which
960 If the resulting location is directly addressable, substitute
961 the MEM we just got directly for the old REG.
963 If it is not addressable but is a constant or the sum of a hard reg
964 and constant, it is probably not addressable because the constant is
965 out of range, in that case record the address; we will generate
966 hairy code to compute the address in a register each time it is
967 needed. Similarly if it is a hard register, but one that is not
968 valid as an address register.
970 If the location is not addressable, but does not have one of the
971 above forms, assign a stack slot. We have to do this to avoid the
972 potential of producing lots of reloads if, e.g., a location involves
973 a pseudo that didn't get a hard register and has an equivalent memory
974 location that also involves a pseudo that didn't get a hard register.
976 Perhaps at some point we will improve reload_when_needed handling
977 so this problem goes away. But that's very hairy. */
979 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
980 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
982 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
984 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
986 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
987 else if (CONSTANT_P (XEXP (x, 0))
988 || (REG_P (XEXP (x, 0))
989 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
990 || (GET_CODE (XEXP (x, 0)) == PLUS
991 && REG_P (XEXP (XEXP (x, 0), 0))
992 && (REGNO (XEXP (XEXP (x, 0), 0))
993 < FIRST_PSEUDO_REGISTER)
994 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
995 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
998 /* Make a new stack slot. Then indicate that something
999 changed so we go back and recompute offsets for
1000 eliminable registers because the allocation of memory
1001 below might change some offset. reg_equiv_{mem,address}
1002 will be set up for this pseudo on the next pass around
1004 reg_equiv_memory_loc[i] = 0;
1005 reg_equiv_init[i] = 0;
1010 if (caller_save_needed)
1011 setup_save_areas ();
1013 /* If we allocated another stack slot, redo elimination bookkeeping. */
1014 if (starting_frame_size != get_frame_size ())
1016 if (starting_frame_size && cfun->stack_alignment_needed)
1018 /* If we have a stack frame, we must align it now. The
1019 stack size may be a part of the offset computation for
1020 register elimination. So if this changes the stack size,
1021 then repeat the elimination bookkeeping. We don't
1022 realign when there is no stack, as that will cause a
1023 stack frame when none is needed should
1024 STARTING_FRAME_OFFSET not be already aligned to
1026 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
1027 if (starting_frame_size != get_frame_size ())
1031 if (caller_save_needed)
1033 save_call_clobbered_regs ();
1034 /* That might have allocated new insn_chain structures. */
1035 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1038 calculate_needs_all_insns (global);
1040 CLEAR_REG_SET (&spilled_pseudos);
1043 something_changed = 0;
1045 /* If we allocated any new memory locations, make another pass
1046 since it might have changed elimination offsets. */
1047 if (starting_frame_size != get_frame_size ())
1048 something_changed = 1;
1050 /* Even if the frame size remained the same, we might still have
1051 changed elimination offsets, e.g. if find_reloads called
1052 force_const_mem requiring the back end to allocate a constant
1053 pool base register that needs to be saved on the stack. */
1054 else if (!verify_initial_elim_offsets ())
1055 something_changed = 1;
1058 HARD_REG_SET to_spill;
1059 CLEAR_HARD_REG_SET (to_spill);
1060 update_eliminables (&to_spill);
1061 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1063 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1064 if (TEST_HARD_REG_BIT (to_spill, i))
1066 spill_hard_reg (i, 1);
1069 /* Regardless of the state of spills, if we previously had
1070 a register that we thought we could eliminate, but now can
1071 not eliminate, we must run another pass.
1073 Consider pseudos which have an entry in reg_equiv_* which
1074 reference an eliminable register. We must make another pass
1075 to update reg_equiv_* so that we do not substitute in the
1076 old value from when we thought the elimination could be
1078 something_changed = 1;
1082 select_reload_regs ();
1086 if (insns_need_reload != 0 || did_spill)
1087 something_changed |= finish_spills (global);
1089 if (! something_changed)
1092 if (caller_save_needed)
1093 delete_caller_save_insns ();
1095 obstack_free (&reload_obstack, reload_firstobj);
1098 /* If global-alloc was run, notify it of any register eliminations we have
1101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1102 if (ep->can_eliminate)
1103 mark_elimination (ep->from, ep->to);
1105 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1106 If that insn didn't set the register (i.e., it copied the register to
1107 memory), just delete that insn instead of the equivalencing insn plus
1108 anything now dead. If we call delete_dead_insn on that insn, we may
1109 delete the insn that actually sets the register if the register dies
1110 there and that is incorrect. */
1112 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1114 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1117 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1119 rtx equiv_insn = XEXP (list, 0);
1121 /* If we already deleted the insn or if it may trap, we can't
1122 delete it. The latter case shouldn't happen, but can
1123 if an insn has a variable address, gets a REG_EH_REGION
1124 note added to it, and then gets converted into a load
1125 from a constant address. */
1126 if (NOTE_P (equiv_insn)
1127 || can_throw_internal (equiv_insn))
1129 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1130 delete_dead_insn (equiv_insn);
1132 SET_INSN_DELETED (equiv_insn);
1137 /* Use the reload registers where necessary
1138 by generating move instructions to move the must-be-register
1139 values into or out of the reload registers. */
1141 if (insns_need_reload != 0 || something_needs_elimination
1142 || something_needs_operands_changed)
1144 HOST_WIDE_INT old_frame_size = get_frame_size ();
1146 reload_as_needed (global);
1148 gcc_assert (old_frame_size == get_frame_size ());
1150 gcc_assert (verify_initial_elim_offsets ());
1153 /* If we were able to eliminate the frame pointer, show that it is no
1154 longer live at the start of any basic block. If it ls live by
1155 virtue of being in a pseudo, that pseudo will be marked live
1156 and hence the frame pointer will be known to be live via that
1159 if (! frame_pointer_needed)
1162 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1163 bitmap_clear_bit (df_get_live_top (bb), HARD_FRAME_POINTER_REGNUM);
1166 /* Come here (with failure set nonzero) if we can't get enough spill
1170 CLEAR_REG_SET (&spilled_pseudos);
1171 reload_in_progress = 0;
1173 /* Now eliminate all pseudo regs by modifying them into
1174 their equivalent memory references.
1175 The REG-rtx's for the pseudos are modified in place,
1176 so all insns that used to refer to them now refer to memory.
1178 For a reg that has a reg_equiv_address, all those insns
1179 were changed by reloading so that no insns refer to it any longer;
1180 but the DECL_RTL of a variable decl may refer to it,
1181 and if so this causes the debugging info to mention the variable. */
1183 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1187 if (reg_equiv_mem[i])
1188 addr = XEXP (reg_equiv_mem[i], 0);
1190 if (reg_equiv_address[i])
1191 addr = reg_equiv_address[i];
1195 if (reg_renumber[i] < 0)
1197 rtx reg = regno_reg_rtx[i];
1199 REG_USERVAR_P (reg) = 0;
1200 PUT_CODE (reg, MEM);
1201 XEXP (reg, 0) = addr;
1202 if (reg_equiv_memory_loc[i])
1203 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1206 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1207 MEM_ATTRS (reg) = 0;
1209 MEM_NOTRAP_P (reg) = 1;
1211 else if (reg_equiv_mem[i])
1212 XEXP (reg_equiv_mem[i], 0) = addr;
1216 /* We must set reload_completed now since the cleanup_subreg_operands call
1217 below will re-recognize each insn and reload may have generated insns
1218 which are only valid during and after reload. */
1219 reload_completed = 1;
1221 /* Make a pass over all the insns and delete all USEs which we inserted
1222 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1223 notes. Delete all CLOBBER insns, except those that refer to the return
1224 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1225 from misarranging variable-array code, and simplify (subreg (reg))
1226 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1227 are no longer useful or accurate. Strip and regenerate REG_INC notes
1228 that may have been moved around. */
1230 for (insn = first; insn; insn = NEXT_INSN (insn))
1236 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1237 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1239 if ((GET_CODE (PATTERN (insn)) == USE
1240 /* We mark with QImode USEs introduced by reload itself. */
1241 && (GET_MODE (insn) == QImode
1242 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1243 || (GET_CODE (PATTERN (insn)) == CLOBBER
1244 && (!MEM_P (XEXP (PATTERN (insn), 0))
1245 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1246 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1247 && XEXP (XEXP (PATTERN (insn), 0), 0)
1248 != stack_pointer_rtx))
1249 && (!REG_P (XEXP (PATTERN (insn), 0))
1250 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1256 /* Some CLOBBERs may survive until here and still reference unassigned
1257 pseudos with const equivalent, which may in turn cause ICE in later
1258 passes if the reference remains in place. */
1259 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1260 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1261 VOIDmode, PATTERN (insn));
1263 /* Discard obvious no-ops, even without -O. This optimization
1264 is fast and doesn't interfere with debugging. */
1265 if (NONJUMP_INSN_P (insn)
1266 && GET_CODE (PATTERN (insn)) == SET
1267 && REG_P (SET_SRC (PATTERN (insn)))
1268 && REG_P (SET_DEST (PATTERN (insn)))
1269 && (REGNO (SET_SRC (PATTERN (insn)))
1270 == REGNO (SET_DEST (PATTERN (insn)))))
1276 pnote = ®_NOTES (insn);
1279 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1280 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1281 || REG_NOTE_KIND (*pnote) == REG_INC
1282 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1283 || REG_NOTE_KIND (*pnote) == REG_LIBCALL_ID
1284 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1285 *pnote = XEXP (*pnote, 1);
1287 pnote = &XEXP (*pnote, 1);
1291 add_auto_inc_notes (insn, PATTERN (insn));
1294 /* Simplify (subreg (reg)) if it appears as an operand. */
1295 cleanup_subreg_operands (insn);
1297 /* Clean up invalid ASMs so that they don't confuse later passes.
1299 if (asm_noperands (PATTERN (insn)) >= 0)
1301 extract_insn (insn);
1302 if (!constrain_operands (1))
1304 error_for_asm (insn,
1305 "%<asm%> operand has impossible constraints");
1312 /* If we are doing stack checking, give a warning if this function's
1313 frame size is larger than we expect. */
1314 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1316 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1317 static int verbose_warned = 0;
1319 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1320 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1321 size += UNITS_PER_WORD;
1323 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1325 warning (0, "frame size too large for reliable stack checking");
1326 if (! verbose_warned)
1328 warning (0, "try reducing the number of local variables");
1334 /* Indicate that we no longer have known memory locations or constants. */
1335 if (reg_equiv_constant)
1336 free (reg_equiv_constant);
1337 if (reg_equiv_invariant)
1338 free (reg_equiv_invariant);
1339 reg_equiv_constant = 0;
1340 reg_equiv_invariant = 0;
1341 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1342 reg_equiv_memory_loc = 0;
1344 if (offsets_known_at)
1345 free (offsets_known_at);
1349 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1350 if (reg_equiv_alt_mem_list[i])
1351 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1352 free (reg_equiv_alt_mem_list);
1354 free (reg_equiv_mem);
1356 free (reg_equiv_address);
1357 free (reg_max_ref_width);
1358 free (reg_old_renumber);
1359 free (pseudo_previous_regs);
1360 free (pseudo_forbidden_regs);
1362 CLEAR_HARD_REG_SET (used_spill_regs);
1363 for (i = 0; i < n_spills; i++)
1364 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1366 /* Free all the insn_chain structures at once. */
1367 obstack_free (&reload_obstack, reload_startobj);
1368 unused_insn_chains = 0;
1369 fixup_abnormal_edges ();
1371 /* Replacing pseudos with their memory equivalents might have
1372 created shared rtx. Subsequent passes would get confused
1373 by this, so unshare everything here. */
1374 unshare_all_rtl_again (first);
1376 #ifdef STACK_BOUNDARY
1377 /* init_emit has set the alignment of the hard frame pointer
1378 to STACK_BOUNDARY. It is very likely no longer valid if
1379 the hard frame pointer was used for register allocation. */
1380 if (!frame_pointer_needed)
1381 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1387 /* Yet another special case. Unfortunately, reg-stack forces people to
1388 write incorrect clobbers in asm statements. These clobbers must not
1389 cause the register to appear in bad_spill_regs, otherwise we'll call
1390 fatal_insn later. We clear the corresponding regnos in the live
1391 register sets to avoid this.
1392 The whole thing is rather sick, I'm afraid. */
1395 maybe_fix_stack_asms (void)
1398 const char *constraints[MAX_RECOG_OPERANDS];
1399 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1400 struct insn_chain *chain;
1402 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1405 HARD_REG_SET clobbered, allowed;
1408 if (! INSN_P (chain->insn)
1409 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1411 pat = PATTERN (chain->insn);
1412 if (GET_CODE (pat) != PARALLEL)
1415 CLEAR_HARD_REG_SET (clobbered);
1416 CLEAR_HARD_REG_SET (allowed);
1418 /* First, make a mask of all stack regs that are clobbered. */
1419 for (i = 0; i < XVECLEN (pat, 0); i++)
1421 rtx t = XVECEXP (pat, 0, i);
1422 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1423 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1426 /* Get the operand values and constraints out of the insn. */
1427 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1428 constraints, operand_mode, NULL);
1430 /* For every operand, see what registers are allowed. */
1431 for (i = 0; i < noperands; i++)
1433 const char *p = constraints[i];
1434 /* For every alternative, we compute the class of registers allowed
1435 for reloading in CLS, and merge its contents into the reg set
1437 int cls = (int) NO_REGS;
1443 if (c == '\0' || c == ',' || c == '#')
1445 /* End of one alternative - mark the regs in the current
1446 class, and reset the class. */
1447 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1453 } while (c != '\0' && c != ',');
1461 case '=': case '+': case '*': case '%': case '?': case '!':
1462 case '0': case '1': case '2': case '3': case '4': case 'm':
1463 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1464 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1465 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1470 cls = (int) reg_class_subunion[cls]
1471 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1476 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1480 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1481 cls = (int) reg_class_subunion[cls]
1482 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1484 cls = (int) reg_class_subunion[cls]
1485 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1487 p += CONSTRAINT_LEN (c, p);
1490 /* Those of the registers which are clobbered, but allowed by the
1491 constraints, must be usable as reload registers. So clear them
1492 out of the life information. */
1493 AND_HARD_REG_SET (allowed, clobbered);
1494 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1495 if (TEST_HARD_REG_BIT (allowed, i))
1497 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1498 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1505 /* Copy the global variables n_reloads and rld into the corresponding elts
1508 copy_reloads (struct insn_chain *chain)
1510 chain->n_reloads = n_reloads;
1511 chain->rld = obstack_alloc (&reload_obstack,
1512 n_reloads * sizeof (struct reload));
1513 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1514 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1517 /* Walk the chain of insns, and determine for each whether it needs reloads
1518 and/or eliminations. Build the corresponding insns_need_reload list, and
1519 set something_needs_elimination as appropriate. */
1521 calculate_needs_all_insns (int global)
1523 struct insn_chain **pprev_reload = &insns_need_reload;
1524 struct insn_chain *chain, *next = 0;
1526 something_needs_elimination = 0;
1528 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1529 for (chain = reload_insn_chain; chain != 0; chain = next)
1531 rtx insn = chain->insn;
1535 /* Clear out the shortcuts. */
1536 chain->n_reloads = 0;
1537 chain->need_elim = 0;
1538 chain->need_reload = 0;
1539 chain->need_operand_change = 0;
1541 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1542 include REG_LABEL), we need to see what effects this has on the
1543 known offsets at labels. */
1545 if (LABEL_P (insn) || JUMP_P (insn)
1546 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1547 set_label_offsets (insn, insn, 0);
1551 rtx old_body = PATTERN (insn);
1552 int old_code = INSN_CODE (insn);
1553 rtx old_notes = REG_NOTES (insn);
1554 int did_elimination = 0;
1555 int operands_changed = 0;
1556 rtx set = single_set (insn);
1558 /* Skip insns that only set an equivalence. */
1559 if (set && REG_P (SET_DEST (set))
1560 && reg_renumber[REGNO (SET_DEST (set))] < 0
1561 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1562 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1563 && reg_equiv_init[REGNO (SET_DEST (set))])
1566 /* If needed, eliminate any eliminable registers. */
1567 if (num_eliminable || num_eliminable_invariants)
1568 did_elimination = eliminate_regs_in_insn (insn, 0);
1570 /* Analyze the instruction. */
1571 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1572 global, spill_reg_order);
1574 /* If a no-op set needs more than one reload, this is likely
1575 to be something that needs input address reloads. We
1576 can't get rid of this cleanly later, and it is of no use
1577 anyway, so discard it now.
1578 We only do this when expensive_optimizations is enabled,
1579 since this complements reload inheritance / output
1580 reload deletion, and it can make debugging harder. */
1581 if (flag_expensive_optimizations && n_reloads > 1)
1583 rtx set = single_set (insn);
1585 && SET_SRC (set) == SET_DEST (set)
1586 && REG_P (SET_SRC (set))
1587 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1590 /* Delete it from the reload chain. */
1592 chain->prev->next = next;
1594 reload_insn_chain = next;
1596 next->prev = chain->prev;
1597 chain->next = unused_insn_chains;
1598 unused_insn_chains = chain;
1603 update_eliminable_offsets ();
1605 /* Remember for later shortcuts which insns had any reloads or
1606 register eliminations. */
1607 chain->need_elim = did_elimination;
1608 chain->need_reload = n_reloads > 0;
1609 chain->need_operand_change = operands_changed;
1611 /* Discard any register replacements done. */
1612 if (did_elimination)
1614 obstack_free (&reload_obstack, reload_insn_firstobj);
1615 PATTERN (insn) = old_body;
1616 INSN_CODE (insn) = old_code;
1617 REG_NOTES (insn) = old_notes;
1618 something_needs_elimination = 1;
1621 something_needs_operands_changed |= operands_changed;
1625 copy_reloads (chain);
1626 *pprev_reload = chain;
1627 pprev_reload = &chain->next_need_reload;
1634 /* Comparison function for qsort to decide which of two reloads
1635 should be handled first. *P1 and *P2 are the reload numbers. */
1638 reload_reg_class_lower (const void *r1p, const void *r2p)
1640 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1643 /* Consider required reloads before optional ones. */
1644 t = rld[r1].optional - rld[r2].optional;
1648 /* Count all solitary classes before non-solitary ones. */
1649 t = ((reg_class_size[(int) rld[r2].class] == 1)
1650 - (reg_class_size[(int) rld[r1].class] == 1));
1654 /* Aside from solitaires, consider all multi-reg groups first. */
1655 t = rld[r2].nregs - rld[r1].nregs;
1659 /* Consider reloads in order of increasing reg-class number. */
1660 t = (int) rld[r1].class - (int) rld[r2].class;
1664 /* If reloads are equally urgent, sort by reload number,
1665 so that the results of qsort leave nothing to chance. */
1669 /* The cost of spilling each hard reg. */
1670 static int spill_cost[FIRST_PSEUDO_REGISTER];
1672 /* When spilling multiple hard registers, we use SPILL_COST for the first
1673 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1674 only the first hard reg for a multi-reg pseudo. */
1675 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1677 /* Update the spill cost arrays, considering that pseudo REG is live. */
1680 count_pseudo (int reg)
1682 int freq = REG_FREQ (reg);
1683 int r = reg_renumber[reg];
1686 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1687 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1690 SET_REGNO_REG_SET (&pseudos_counted, reg);
1692 gcc_assert (r >= 0);
1694 spill_add_cost[r] += freq;
1696 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1698 spill_cost[r + nregs] += freq;
1701 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1702 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1705 order_regs_for_reload (struct insn_chain *chain)
1708 HARD_REG_SET used_by_pseudos;
1709 HARD_REG_SET used_by_pseudos2;
1710 reg_set_iterator rsi;
1712 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1714 memset (spill_cost, 0, sizeof spill_cost);
1715 memset (spill_add_cost, 0, sizeof spill_add_cost);
1717 /* Count number of uses of each hard reg by pseudo regs allocated to it
1718 and then order them by decreasing use. First exclude hard registers
1719 that are live in or across this insn. */
1721 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1722 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1723 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1724 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1726 /* Now find out which pseudos are allocated to it, and update
1728 CLEAR_REG_SET (&pseudos_counted);
1730 EXECUTE_IF_SET_IN_REG_SET
1731 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1735 EXECUTE_IF_SET_IN_REG_SET
1736 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1740 CLEAR_REG_SET (&pseudos_counted);
1743 /* Vector of reload-numbers showing the order in which the reloads should
1745 static short reload_order[MAX_RELOADS];
1747 /* This is used to keep track of the spill regs used in one insn. */
1748 static HARD_REG_SET used_spill_regs_local;
1750 /* We decided to spill hard register SPILLED, which has a size of
1751 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1752 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1753 update SPILL_COST/SPILL_ADD_COST. */
1756 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1758 int r = reg_renumber[reg];
1759 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1761 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1762 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1765 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1767 spill_add_cost[r] -= REG_FREQ (reg);
1769 spill_cost[r + nregs] -= REG_FREQ (reg);
1772 /* Find reload register to use for reload number ORDER. */
1775 find_reg (struct insn_chain *chain, int order)
1777 int rnum = reload_order[order];
1778 struct reload *rl = rld + rnum;
1779 int best_cost = INT_MAX;
1783 HARD_REG_SET not_usable;
1784 HARD_REG_SET used_by_other_reload;
1785 reg_set_iterator rsi;
1787 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1788 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1789 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1791 CLEAR_HARD_REG_SET (used_by_other_reload);
1792 for (k = 0; k < order; k++)
1794 int other = reload_order[k];
1796 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1797 for (j = 0; j < rld[other].nregs; j++)
1798 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1801 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1803 unsigned int regno = i;
1805 if (! TEST_HARD_REG_BIT (not_usable, regno)
1806 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1807 && HARD_REGNO_MODE_OK (regno, rl->mode))
1809 int this_cost = spill_cost[regno];
1811 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1813 for (j = 1; j < this_nregs; j++)
1815 this_cost += spill_add_cost[regno + j];
1816 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1817 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1822 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1824 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1826 if (this_cost < best_cost
1827 /* Among registers with equal cost, prefer caller-saved ones, or
1828 use REG_ALLOC_ORDER if it is defined. */
1829 || (this_cost == best_cost
1830 #ifdef REG_ALLOC_ORDER
1831 && (inv_reg_alloc_order[regno]
1832 < inv_reg_alloc_order[best_reg])
1834 && call_used_regs[regno]
1835 && ! call_used_regs[best_reg]
1840 best_cost = this_cost;
1848 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1850 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1851 rl->regno = best_reg;
1853 EXECUTE_IF_SET_IN_REG_SET
1854 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1856 count_spilled_pseudo (best_reg, rl->nregs, j);
1859 EXECUTE_IF_SET_IN_REG_SET
1860 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1862 count_spilled_pseudo (best_reg, rl->nregs, j);
1865 for (i = 0; i < rl->nregs; i++)
1867 gcc_assert (spill_cost[best_reg + i] == 0);
1868 gcc_assert (spill_add_cost[best_reg + i] == 0);
1869 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1874 /* Find more reload regs to satisfy the remaining need of an insn, which
1876 Do it by ascending class number, since otherwise a reg
1877 might be spilled for a big class and might fail to count
1878 for a smaller class even though it belongs to that class. */
1881 find_reload_regs (struct insn_chain *chain)
1885 /* In order to be certain of getting the registers we need,
1886 we must sort the reloads into order of increasing register class.
1887 Then our grabbing of reload registers will parallel the process
1888 that provided the reload registers. */
1889 for (i = 0; i < chain->n_reloads; i++)
1891 /* Show whether this reload already has a hard reg. */
1892 if (chain->rld[i].reg_rtx)
1894 int regno = REGNO (chain->rld[i].reg_rtx);
1895 chain->rld[i].regno = regno;
1897 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1900 chain->rld[i].regno = -1;
1901 reload_order[i] = i;
1904 n_reloads = chain->n_reloads;
1905 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1907 CLEAR_HARD_REG_SET (used_spill_regs_local);
1910 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1912 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1914 /* Compute the order of preference for hard registers to spill. */
1916 order_regs_for_reload (chain);
1918 for (i = 0; i < n_reloads; i++)
1920 int r = reload_order[i];
1922 /* Ignore reloads that got marked inoperative. */
1923 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1924 && ! rld[r].optional
1925 && rld[r].regno == -1)
1926 if (! find_reg (chain, i))
1929 fprintf (dump_file, "reload failure for reload %d\n", r);
1930 spill_failure (chain->insn, rld[r].class);
1936 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1937 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1939 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1943 select_reload_regs (void)
1945 struct insn_chain *chain;
1947 /* Try to satisfy the needs for each insn. */
1948 for (chain = insns_need_reload; chain != 0;
1949 chain = chain->next_need_reload)
1950 find_reload_regs (chain);
1953 /* Delete all insns that were inserted by emit_caller_save_insns during
1956 delete_caller_save_insns (void)
1958 struct insn_chain *c = reload_insn_chain;
1962 while (c != 0 && c->is_caller_save_insn)
1964 struct insn_chain *next = c->next;
1967 if (c == reload_insn_chain)
1968 reload_insn_chain = next;
1972 next->prev = c->prev;
1974 c->prev->next = next;
1975 c->next = unused_insn_chains;
1976 unused_insn_chains = c;
1984 /* Handle the failure to find a register to spill.
1985 INSN should be one of the insns which needed this particular spill reg. */
1988 spill_failure (rtx insn, enum reg_class class)
1990 if (asm_noperands (PATTERN (insn)) >= 0)
1991 error_for_asm (insn, "can't find a register in class %qs while "
1992 "reloading %<asm%>",
1993 reg_class_names[class]);
1996 error ("unable to find a register to spill in class %qs",
1997 reg_class_names[class]);
2001 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2002 debug_reload_to_stream (dump_file);
2004 fatal_insn ("this is the insn:", insn);
2008 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2009 data that is dead in INSN. */
2012 delete_dead_insn (rtx insn)
2014 rtx prev = prev_real_insn (insn);
2017 /* If the previous insn sets a register that dies in our insn, delete it
2019 if (prev && GET_CODE (PATTERN (prev)) == SET
2020 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2021 && reg_mentioned_p (prev_dest, PATTERN (insn))
2022 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2023 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2024 delete_dead_insn (prev);
2026 SET_INSN_DELETED (insn);
2029 /* Modify the home of pseudo-reg I.
2030 The new home is present in reg_renumber[I].
2032 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2033 or it may be -1, meaning there is none or it is not relevant.
2034 This is used so that all pseudos spilled from a given hard reg
2035 can share one stack slot. */
2038 alter_reg (int i, int from_reg)
2040 /* When outputting an inline function, this can happen
2041 for a reg that isn't actually used. */
2042 if (regno_reg_rtx[i] == 0)
2045 /* If the reg got changed to a MEM at rtl-generation time,
2047 if (!REG_P (regno_reg_rtx[i]))
2050 /* Modify the reg-rtx to contain the new hard reg
2051 number or else to contain its pseudo reg number. */
2052 SET_REGNO (regno_reg_rtx[i],
2053 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2055 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2056 allocate a stack slot for it. */
2058 if (reg_renumber[i] < 0
2059 && REG_N_REFS (i) > 0
2060 && reg_equiv_constant[i] == 0
2061 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2062 && reg_equiv_memory_loc[i] == 0)
2065 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2066 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2067 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2068 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2069 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2072 /* Each pseudo reg has an inherent size which comes from its own mode,
2073 and a total size which provides room for paradoxical subregs
2074 which refer to the pseudo reg in wider modes.
2076 We can use a slot already allocated if it provides both
2077 enough inherent space and enough total space.
2078 Otherwise, we allocate a new slot, making sure that it has no less
2079 inherent space, and no less total space, then the previous slot. */
2082 alias_set_type alias_set = new_alias_set ();
2084 /* No known place to spill from => no slot to reuse. */
2085 x = assign_stack_local (mode, total_size,
2086 min_align > inherent_align
2087 || total_size > inherent_size ? -1 : 0);
2088 if (BYTES_BIG_ENDIAN)
2089 /* Cancel the big-endian correction done in assign_stack_local.
2090 Get the address of the beginning of the slot.
2091 This is so we can do a big-endian correction unconditionally
2093 adjust = inherent_size - total_size;
2095 /* Nothing can alias this slot except this pseudo. */
2096 set_mem_alias_set (x, alias_set);
2097 dse_record_singleton_alias_set (alias_set, mode);
2100 /* Reuse a stack slot if possible. */
2101 else if (spill_stack_slot[from_reg] != 0
2102 && spill_stack_slot_width[from_reg] >= total_size
2103 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2105 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2106 x = spill_stack_slot[from_reg];
2107 /* Allocate a bigger slot. */
2110 /* Compute maximum size needed, both for inherent size
2111 and for total size. */
2114 if (spill_stack_slot[from_reg])
2116 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2118 mode = GET_MODE (spill_stack_slot[from_reg]);
2119 if (spill_stack_slot_width[from_reg] > total_size)
2120 total_size = spill_stack_slot_width[from_reg];
2121 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2122 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2125 /* Make a slot with that size. */
2126 x = assign_stack_local (mode, total_size,
2127 min_align > inherent_align
2128 || total_size > inherent_size ? -1 : 0);
2131 /* All pseudos mapped to this slot can alias each other. */
2132 if (spill_stack_slot[from_reg])
2134 alias_set_type alias_set
2135 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2136 set_mem_alias_set (x, alias_set);
2137 dse_invalidate_singleton_alias_set (alias_set);
2141 alias_set_type alias_set = new_alias_set ();
2142 set_mem_alias_set (x, alias_set);
2143 dse_record_singleton_alias_set (alias_set, mode);
2146 if (BYTES_BIG_ENDIAN)
2148 /* Cancel the big-endian correction done in assign_stack_local.
2149 Get the address of the beginning of the slot.
2150 This is so we can do a big-endian correction unconditionally
2152 adjust = GET_MODE_SIZE (mode) - total_size;
2155 = adjust_address_nv (x, mode_for_size (total_size
2161 spill_stack_slot[from_reg] = stack_slot;
2162 spill_stack_slot_width[from_reg] = total_size;
2165 /* On a big endian machine, the "address" of the slot
2166 is the address of the low part that fits its inherent mode. */
2167 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2168 adjust += (total_size - inherent_size);
2170 /* If we have any adjustment to make, or if the stack slot is the
2171 wrong mode, make a new stack slot. */
2172 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2174 /* If we have a decl for the original register, set it for the
2175 memory. If this is a shared MEM, make a copy. */
2176 if (REG_EXPR (regno_reg_rtx[i])
2177 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2179 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2181 /* We can do this only for the DECLs home pseudo, not for
2182 any copies of it, since otherwise when the stack slot
2183 is reused, nonoverlapping_memrefs_p might think they
2185 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2187 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2190 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2194 /* Save the stack slot for later. */
2195 reg_equiv_memory_loc[i] = x;
2199 /* Mark the slots in regs_ever_live for the hard regs used by
2200 pseudo-reg number REGNO, accessed in MODE. */
2203 mark_home_live_1 (int regno, enum machine_mode mode)
2207 i = reg_renumber[regno];
2210 lim = end_hard_regno (mode, i);
2212 df_set_regs_ever_live(i++, true);
2215 /* Mark the slots in regs_ever_live for the hard regs
2216 used by pseudo-reg number REGNO. */
2219 mark_home_live (int regno)
2221 if (reg_renumber[regno] >= 0)
2222 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2225 /* This function handles the tracking of elimination offsets around branches.
2227 X is a piece of RTL being scanned.
2229 INSN is the insn that it came from, if any.
2231 INITIAL_P is nonzero if we are to set the offset to be the initial
2232 offset and zero if we are setting the offset of the label to be the
2236 set_label_offsets (rtx x, rtx insn, int initial_p)
2238 enum rtx_code code = GET_CODE (x);
2241 struct elim_table *p;
2246 if (LABEL_REF_NONLOCAL_P (x))
2251 /* ... fall through ... */
2254 /* If we know nothing about this label, set the desired offsets. Note
2255 that this sets the offset at a label to be the offset before a label
2256 if we don't know anything about the label. This is not correct for
2257 the label after a BARRIER, but is the best guess we can make. If
2258 we guessed wrong, we will suppress an elimination that might have
2259 been possible had we been able to guess correctly. */
2261 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2263 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2264 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2265 = (initial_p ? reg_eliminate[i].initial_offset
2266 : reg_eliminate[i].offset);
2267 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2270 /* Otherwise, if this is the definition of a label and it is
2271 preceded by a BARRIER, set our offsets to the known offset of
2275 && (tem = prev_nonnote_insn (insn)) != 0
2277 set_offsets_for_label (insn);
2279 /* If neither of the above cases is true, compare each offset
2280 with those previously recorded and suppress any eliminations
2281 where the offsets disagree. */
2283 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2284 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2285 != (initial_p ? reg_eliminate[i].initial_offset
2286 : reg_eliminate[i].offset))
2287 reg_eliminate[i].can_eliminate = 0;
2292 set_label_offsets (PATTERN (insn), insn, initial_p);
2294 /* ... fall through ... */
2298 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2299 and hence must have all eliminations at their initial offsets. */
2300 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2301 if (REG_NOTE_KIND (tem) == REG_LABEL)
2302 set_label_offsets (XEXP (tem, 0), insn, 1);
2308 /* Each of the labels in the parallel or address vector must be
2309 at their initial offsets. We want the first field for PARALLEL
2310 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2312 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2313 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2318 /* We only care about setting PC. If the source is not RETURN,
2319 IF_THEN_ELSE, or a label, disable any eliminations not at
2320 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2321 isn't one of those possibilities. For branches to a label,
2322 call ourselves recursively.
2324 Note that this can disable elimination unnecessarily when we have
2325 a non-local goto since it will look like a non-constant jump to
2326 someplace in the current function. This isn't a significant
2327 problem since such jumps will normally be when all elimination
2328 pairs are back to their initial offsets. */
2330 if (SET_DEST (x) != pc_rtx)
2333 switch (GET_CODE (SET_SRC (x)))
2340 set_label_offsets (SET_SRC (x), insn, initial_p);
2344 tem = XEXP (SET_SRC (x), 1);
2345 if (GET_CODE (tem) == LABEL_REF)
2346 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2347 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2350 tem = XEXP (SET_SRC (x), 2);
2351 if (GET_CODE (tem) == LABEL_REF)
2352 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2353 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2361 /* If we reach here, all eliminations must be at their initial
2362 offset because we are doing a jump to a variable address. */
2363 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2364 if (p->offset != p->initial_offset)
2365 p->can_eliminate = 0;
2373 /* Scan X and replace any eliminable registers (such as fp) with a
2374 replacement (such as sp), plus an offset.
2376 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2377 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2378 MEM, we are allowed to replace a sum of a register and the constant zero
2379 with the register, which we cannot do outside a MEM. In addition, we need
2380 to record the fact that a register is referenced outside a MEM.
2382 If INSN is an insn, it is the insn containing X. If we replace a REG
2383 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2384 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2385 the REG is being modified.
2387 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2388 That's used when we eliminate in expressions stored in notes.
2389 This means, do not set ref_outside_mem even if the reference
2392 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2393 replacements done assuming all offsets are at their initial values. If
2394 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2395 encounter, return the actual location so that find_reloads will do
2396 the proper thing. */
2399 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2400 bool may_use_invariant)
2402 enum rtx_code code = GET_CODE (x);
2403 struct elim_table *ep;
2410 if (! current_function_decl)
2433 /* First handle the case where we encounter a bare register that
2434 is eliminable. Replace it with a PLUS. */
2435 if (regno < FIRST_PSEUDO_REGISTER)
2437 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2439 if (ep->from_rtx == x && ep->can_eliminate)
2440 return plus_constant (ep->to_rtx, ep->previous_offset);
2443 else if (reg_renumber && reg_renumber[regno] < 0
2444 && reg_equiv_invariant && reg_equiv_invariant[regno])
2446 if (may_use_invariant)
2447 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2448 mem_mode, insn, true);
2449 /* There exists at least one use of REGNO that cannot be
2450 eliminated. Prevent the defining insn from being deleted. */
2451 reg_equiv_init[regno] = NULL_RTX;
2452 alter_reg (regno, -1);
2456 /* You might think handling MINUS in a manner similar to PLUS is a
2457 good idea. It is not. It has been tried multiple times and every
2458 time the change has had to have been reverted.
2460 Other parts of reload know a PLUS is special (gen_reload for example)
2461 and require special code to handle code a reloaded PLUS operand.
2463 Also consider backends where the flags register is clobbered by a
2464 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2465 lea instruction comes to mind). If we try to reload a MINUS, we
2466 may kill the flags register that was holding a useful value.
2468 So, please before trying to handle MINUS, consider reload as a
2469 whole instead of this little section as well as the backend issues. */
2471 /* If this is the sum of an eliminable register and a constant, rework
2473 if (REG_P (XEXP (x, 0))
2474 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2475 && CONSTANT_P (XEXP (x, 1)))
2477 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2479 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2481 /* The only time we want to replace a PLUS with a REG (this
2482 occurs when the constant operand of the PLUS is the negative
2483 of the offset) is when we are inside a MEM. We won't want
2484 to do so at other times because that would change the
2485 structure of the insn in a way that reload can't handle.
2486 We special-case the commonest situation in
2487 eliminate_regs_in_insn, so just replace a PLUS with a
2488 PLUS here, unless inside a MEM. */
2489 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2490 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2493 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2494 plus_constant (XEXP (x, 1),
2495 ep->previous_offset));
2498 /* If the register is not eliminable, we are done since the other
2499 operand is a constant. */
2503 /* If this is part of an address, we want to bring any constant to the
2504 outermost PLUS. We will do this by doing register replacement in
2505 our operands and seeing if a constant shows up in one of them.
2507 Note that there is no risk of modifying the structure of the insn,
2508 since we only get called for its operands, thus we are either
2509 modifying the address inside a MEM, or something like an address
2510 operand of a load-address insn. */
2513 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2514 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2516 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2518 /* If one side is a PLUS and the other side is a pseudo that
2519 didn't get a hard register but has a reg_equiv_constant,
2520 we must replace the constant here since it may no longer
2521 be in the position of any operand. */
2522 if (GET_CODE (new0) == PLUS && REG_P (new1)
2523 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2524 && reg_renumber[REGNO (new1)] < 0
2525 && reg_equiv_constant != 0
2526 && reg_equiv_constant[REGNO (new1)] != 0)
2527 new1 = reg_equiv_constant[REGNO (new1)];
2528 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2529 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2530 && reg_renumber[REGNO (new0)] < 0
2531 && reg_equiv_constant[REGNO (new0)] != 0)
2532 new0 = reg_equiv_constant[REGNO (new0)];
2534 new = form_sum (new0, new1);
2536 /* As above, if we are not inside a MEM we do not want to
2537 turn a PLUS into something else. We might try to do so here
2538 for an addition of 0 if we aren't optimizing. */
2539 if (! mem_mode && GET_CODE (new) != PLUS)
2540 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2548 /* If this is the product of an eliminable register and a
2549 constant, apply the distribute law and move the constant out
2550 so that we have (plus (mult ..) ..). This is needed in order
2551 to keep load-address insns valid. This case is pathological.
2552 We ignore the possibility of overflow here. */
2553 if (REG_P (XEXP (x, 0))
2554 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2555 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2556 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2558 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2561 /* Refs inside notes don't count for this purpose. */
2562 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2563 || GET_CODE (insn) == INSN_LIST)))
2564 ep->ref_outside_mem = 1;
2567 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2568 ep->previous_offset * INTVAL (XEXP (x, 1)));
2571 /* ... fall through ... */
2575 /* See comments before PLUS about handling MINUS. */
2577 case DIV: case UDIV:
2578 case MOD: case UMOD:
2579 case AND: case IOR: case XOR:
2580 case ROTATERT: case ROTATE:
2581 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2583 case GE: case GT: case GEU: case GTU:
2584 case LE: case LT: case LEU: case LTU:
2586 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2587 rtx new1 = XEXP (x, 1)
2588 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2590 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2591 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2596 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2599 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2600 if (new != XEXP (x, 0))
2602 /* If this is a REG_DEAD note, it is not valid anymore.
2603 Using the eliminated version could result in creating a
2604 REG_DEAD note for the stack or frame pointer. */
2605 if (GET_MODE (x) == REG_DEAD)
2607 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2610 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2614 /* ... fall through ... */
2617 /* Now do eliminations in the rest of the chain. If this was
2618 an EXPR_LIST, this might result in allocating more memory than is
2619 strictly needed, but it simplifies the code. */
2622 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2623 if (new != XEXP (x, 1))
2625 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2633 /* We do not support elimination of a register that is modified.
2634 elimination_effects has already make sure that this does not
2640 /* We do not support elimination of a register that is modified.
2641 elimination_effects has already make sure that this does not
2642 happen. The only remaining case we need to consider here is
2643 that the increment value may be an eliminable register. */
2644 if (GET_CODE (XEXP (x, 1)) == PLUS
2645 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2647 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2650 if (new != XEXP (XEXP (x, 1), 1))
2651 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2652 gen_rtx_PLUS (GET_MODE (x),
2657 case STRICT_LOW_PART:
2659 case SIGN_EXTEND: case ZERO_EXTEND:
2660 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2661 case FLOAT: case FIX:
2662 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2671 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2672 if (new != XEXP (x, 0))
2673 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2677 /* Similar to above processing, but preserve SUBREG_BYTE.
2678 Convert (subreg (mem)) to (mem) if not paradoxical.
2679 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2680 pseudo didn't get a hard reg, we must replace this with the
2681 eliminated version of the memory location because push_reload
2682 may do the replacement in certain circumstances. */
2683 if (REG_P (SUBREG_REG (x))
2684 && (GET_MODE_SIZE (GET_MODE (x))
2685 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2686 && reg_equiv_memory_loc != 0
2687 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2689 new = SUBREG_REG (x);
2692 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2694 if (new != SUBREG_REG (x))
2696 int x_size = GET_MODE_SIZE (GET_MODE (x));
2697 int new_size = GET_MODE_SIZE (GET_MODE (new));
2700 && ((x_size < new_size
2701 #ifdef WORD_REGISTER_OPERATIONS
2702 /* On these machines, combine can create rtl of the form
2703 (set (subreg:m1 (reg:m2 R) 0) ...)
2704 where m1 < m2, and expects something interesting to
2705 happen to the entire word. Moreover, it will use the
2706 (reg:m2 R) later, expecting all bits to be preserved.
2707 So if the number of words is the same, preserve the
2708 subreg so that push_reload can see it. */
2709 && ! ((x_size - 1) / UNITS_PER_WORD
2710 == (new_size -1 ) / UNITS_PER_WORD)
2713 || x_size == new_size)
2715 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2717 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2723 /* Our only special processing is to pass the mode of the MEM to our
2724 recursive call and copy the flags. While we are here, handle this
2725 case more efficiently. */
2727 replace_equiv_address_nv (x,
2728 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2732 /* Handle insn_list USE that a call to a pure function may generate. */
2733 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2734 if (new != XEXP (x, 0))
2735 return gen_rtx_USE (GET_MODE (x), new);
2747 /* Process each of our operands recursively. If any have changed, make a
2749 fmt = GET_RTX_FORMAT (code);
2750 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2754 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2755 if (new != XEXP (x, i) && ! copied)
2757 x = shallow_copy_rtx (x);
2762 else if (*fmt == 'E')
2765 for (j = 0; j < XVECLEN (x, i); j++)
2767 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2768 if (new != XVECEXP (x, i, j) && ! copied_vec)
2770 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2774 x = shallow_copy_rtx (x);
2777 XVEC (x, i) = new_v;
2780 XVECEXP (x, i, j) = new;
2789 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2791 return eliminate_regs_1 (x, mem_mode, insn, false);
2794 /* Scan rtx X for modifications of elimination target registers. Update
2795 the table of eliminables to reflect the changed state. MEM_MODE is
2796 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2799 elimination_effects (rtx x, enum machine_mode mem_mode)
2801 enum rtx_code code = GET_CODE (x);
2802 struct elim_table *ep;
2827 /* First handle the case where we encounter a bare register that
2828 is eliminable. Replace it with a PLUS. */
2829 if (regno < FIRST_PSEUDO_REGISTER)
2831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2833 if (ep->from_rtx == x && ep->can_eliminate)
2836 ep->ref_outside_mem = 1;
2841 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2842 && reg_equiv_constant[regno]
2843 && ! function_invariant_p (reg_equiv_constant[regno]))
2844 elimination_effects (reg_equiv_constant[regno], mem_mode);
2853 /* If we modify the source of an elimination rule, disable it. */
2854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2855 if (ep->from_rtx == XEXP (x, 0))
2856 ep->can_eliminate = 0;
2858 /* If we modify the target of an elimination rule by adding a constant,
2859 update its offset. If we modify the target in any other way, we'll
2860 have to disable the rule as well. */
2861 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2862 if (ep->to_rtx == XEXP (x, 0))
2864 int size = GET_MODE_SIZE (mem_mode);
2866 /* If more bytes than MEM_MODE are pushed, account for them. */
2867 #ifdef PUSH_ROUNDING
2868 if (ep->to_rtx == stack_pointer_rtx)
2869 size = PUSH_ROUNDING (size);
2871 if (code == PRE_DEC || code == POST_DEC)
2873 else if (code == PRE_INC || code == POST_INC)
2875 else if (code == PRE_MODIFY || code == POST_MODIFY)
2877 if (GET_CODE (XEXP (x, 1)) == PLUS
2878 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2879 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2880 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2882 ep->can_eliminate = 0;
2886 /* These two aren't unary operators. */
2887 if (code == POST_MODIFY || code == PRE_MODIFY)
2890 /* Fall through to generic unary operation case. */
2891 case STRICT_LOW_PART:
2893 case SIGN_EXTEND: case ZERO_EXTEND:
2894 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2895 case FLOAT: case FIX:
2896 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2905 elimination_effects (XEXP (x, 0), mem_mode);
2909 if (REG_P (SUBREG_REG (x))
2910 && (GET_MODE_SIZE (GET_MODE (x))
2911 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2912 && reg_equiv_memory_loc != 0
2913 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2916 elimination_effects (SUBREG_REG (x), mem_mode);
2920 /* If using a register that is the source of an eliminate we still
2921 think can be performed, note it cannot be performed since we don't
2922 know how this register is used. */
2923 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2924 if (ep->from_rtx == XEXP (x, 0))
2925 ep->can_eliminate = 0;
2927 elimination_effects (XEXP (x, 0), mem_mode);
2931 /* If clobbering a register that is the replacement register for an
2932 elimination we still think can be performed, note that it cannot
2933 be performed. Otherwise, we need not be concerned about it. */
2934 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2935 if (ep->to_rtx == XEXP (x, 0))
2936 ep->can_eliminate = 0;
2938 elimination_effects (XEXP (x, 0), mem_mode);
2942 /* Check for setting a register that we know about. */
2943 if (REG_P (SET_DEST (x)))
2945 /* See if this is setting the replacement register for an
2948 If DEST is the hard frame pointer, we do nothing because we
2949 assume that all assignments to the frame pointer are for
2950 non-local gotos and are being done at a time when they are valid
2951 and do not disturb anything else. Some machines want to
2952 eliminate a fake argument pointer (or even a fake frame pointer)
2953 with either the real frame or the stack pointer. Assignments to
2954 the hard frame pointer must not prevent this elimination. */
2956 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2958 if (ep->to_rtx == SET_DEST (x)
2959 && SET_DEST (x) != hard_frame_pointer_rtx)
2961 /* If it is being incremented, adjust the offset. Otherwise,
2962 this elimination can't be done. */
2963 rtx src = SET_SRC (x);
2965 if (GET_CODE (src) == PLUS
2966 && XEXP (src, 0) == SET_DEST (x)
2967 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2968 ep->offset -= INTVAL (XEXP (src, 1));
2970 ep->can_eliminate = 0;
2974 elimination_effects (SET_DEST (x), 0);
2975 elimination_effects (SET_SRC (x), 0);
2979 /* Our only special processing is to pass the mode of the MEM to our
2981 elimination_effects (XEXP (x, 0), GET_MODE (x));
2988 fmt = GET_RTX_FORMAT (code);
2989 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2992 elimination_effects (XEXP (x, i), mem_mode);
2993 else if (*fmt == 'E')
2994 for (j = 0; j < XVECLEN (x, i); j++)
2995 elimination_effects (XVECEXP (x, i, j), mem_mode);
2999 /* Descend through rtx X and verify that no references to eliminable registers
3000 remain. If any do remain, mark the involved register as not
3004 check_eliminable_occurrences (rtx x)
3013 code = GET_CODE (x);
3015 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3017 struct elim_table *ep;
3019 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3020 if (ep->from_rtx == x)
3021 ep->can_eliminate = 0;
3025 fmt = GET_RTX_FORMAT (code);
3026 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3029 check_eliminable_occurrences (XEXP (x, i));
3030 else if (*fmt == 'E')
3033 for (j = 0; j < XVECLEN (x, i); j++)
3034 check_eliminable_occurrences (XVECEXP (x, i, j));
3039 /* Scan INSN and eliminate all eliminable registers in it.
3041 If REPLACE is nonzero, do the replacement destructively. Also
3042 delete the insn as dead it if it is setting an eliminable register.
3044 If REPLACE is zero, do all our allocations in reload_obstack.
3046 If no eliminations were done and this insn doesn't require any elimination
3047 processing (these are not identical conditions: it might be updating sp,
3048 but not referencing fp; this needs to be seen during reload_as_needed so
3049 that the offset between fp and sp can be taken into consideration), zero
3050 is returned. Otherwise, 1 is returned. */
3053 eliminate_regs_in_insn (rtx insn, int replace)
3055 int icode = recog_memoized (insn);
3056 rtx old_body = PATTERN (insn);
3057 int insn_is_asm = asm_noperands (old_body) >= 0;
3058 rtx old_set = single_set (insn);
3062 rtx substed_operand[MAX_RECOG_OPERANDS];
3063 rtx orig_operand[MAX_RECOG_OPERANDS];
3064 struct elim_table *ep;
3065 rtx plus_src, plus_cst_src;
3067 if (! insn_is_asm && icode < 0)
3069 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3070 || GET_CODE (PATTERN (insn)) == CLOBBER
3071 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3072 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3073 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3077 if (old_set != 0 && REG_P (SET_DEST (old_set))
3078 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3080 /* Check for setting an eliminable register. */
3081 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3082 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3084 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3085 /* If this is setting the frame pointer register to the
3086 hardware frame pointer register and this is an elimination
3087 that will be done (tested above), this insn is really
3088 adjusting the frame pointer downward to compensate for
3089 the adjustment done before a nonlocal goto. */
3090 if (ep->from == FRAME_POINTER_REGNUM
3091 && ep->to == HARD_FRAME_POINTER_REGNUM)
3093 rtx base = SET_SRC (old_set);
3094 rtx base_insn = insn;
3095 HOST_WIDE_INT offset = 0;
3097 while (base != ep->to_rtx)
3099 rtx prev_insn, prev_set;
3101 if (GET_CODE (base) == PLUS
3102 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3104 offset += INTVAL (XEXP (base, 1));
3105 base = XEXP (base, 0);
3107 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3108 && (prev_set = single_set (prev_insn)) != 0
3109 && rtx_equal_p (SET_DEST (prev_set), base))
3111 base = SET_SRC (prev_set);
3112 base_insn = prev_insn;
3118 if (base == ep->to_rtx)
3121 = plus_constant (ep->to_rtx, offset - ep->offset);
3123 new_body = old_body;
3126 new_body = copy_insn (old_body);
3127 if (REG_NOTES (insn))
3128 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3130 PATTERN (insn) = new_body;
3131 old_set = single_set (insn);
3133 /* First see if this insn remains valid when we
3134 make the change. If not, keep the INSN_CODE
3135 the same and let reload fit it up. */
3136 validate_change (insn, &SET_SRC (old_set), src, 1);
3137 validate_change (insn, &SET_DEST (old_set),
3139 if (! apply_change_group ())
3141 SET_SRC (old_set) = src;
3142 SET_DEST (old_set) = ep->to_rtx;
3151 /* In this case this insn isn't serving a useful purpose. We
3152 will delete it in reload_as_needed once we know that this
3153 elimination is, in fact, being done.
3155 If REPLACE isn't set, we can't delete this insn, but needn't
3156 process it since it won't be used unless something changes. */
3159 delete_dead_insn (insn);
3167 /* We allow one special case which happens to work on all machines we
3168 currently support: a single set with the source or a REG_EQUAL
3169 note being a PLUS of an eliminable register and a constant. */
3170 plus_src = plus_cst_src = 0;
3171 if (old_set && REG_P (SET_DEST (old_set)))
3173 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3174 plus_src = SET_SRC (old_set);
3175 /* First see if the source is of the form (plus (...) CST). */
3177 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3178 plus_cst_src = plus_src;
3179 else if (REG_P (SET_SRC (old_set))
3182 /* Otherwise, see if we have a REG_EQUAL note of the form
3183 (plus (...) CST). */
3185 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3187 if ((REG_NOTE_KIND (links) == REG_EQUAL
3188 || REG_NOTE_KIND (links) == REG_EQUIV)
3189 && GET_CODE (XEXP (links, 0)) == PLUS
3190 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3192 plus_cst_src = XEXP (links, 0);
3198 /* Check that the first operand of the PLUS is a hard reg or
3199 the lowpart subreg of one. */
3202 rtx reg = XEXP (plus_cst_src, 0);
3203 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3204 reg = SUBREG_REG (reg);
3206 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3212 rtx reg = XEXP (plus_cst_src, 0);
3213 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3215 if (GET_CODE (reg) == SUBREG)
3216 reg = SUBREG_REG (reg);
3218 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3219 if (ep->from_rtx == reg && ep->can_eliminate)
3221 rtx to_rtx = ep->to_rtx;
3222 offset += ep->offset;
3223 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3225 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3226 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3228 /* If we have a nonzero offset, and the source is already
3229 a simple REG, the following transformation would
3230 increase the cost of the insn by replacing a simple REG
3231 with (plus (reg sp) CST). So try only when we already
3232 had a PLUS before. */
3233 if (offset == 0 || plus_src)
3235 rtx new_src = plus_constant (to_rtx, offset);
3237 new_body = old_body;
3240 new_body = copy_insn (old_body);
3241 if (REG_NOTES (insn))
3242 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3244 PATTERN (insn) = new_body;
3245 old_set = single_set (insn);
3247 /* First see if this insn remains valid when we make the
3248 change. If not, try to replace the whole pattern with
3249 a simple set (this may help if the original insn was a
3250 PARALLEL that was only recognized as single_set due to
3251 REG_UNUSED notes). If this isn't valid either, keep
3252 the INSN_CODE the same and let reload fix it up. */
3253 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3255 rtx new_pat = gen_rtx_SET (VOIDmode,
3256 SET_DEST (old_set), new_src);
3258 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3259 SET_SRC (old_set) = new_src;
3266 /* This can't have an effect on elimination offsets, so skip right
3272 /* Determine the effects of this insn on elimination offsets. */
3273 elimination_effects (old_body, 0);
3275 /* Eliminate all eliminable registers occurring in operands that
3276 can be handled by reload. */
3277 extract_insn (insn);
3278 for (i = 0; i < recog_data.n_operands; i++)
3280 orig_operand[i] = recog_data.operand[i];
3281 substed_operand[i] = recog_data.operand[i];
3283 /* For an asm statement, every operand is eliminable. */
3284 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3286 bool is_set_src, in_plus;
3288 /* Check for setting a register that we know about. */
3289 if (recog_data.operand_type[i] != OP_IN
3290 && REG_P (orig_operand[i]))
3292 /* If we are assigning to a register that can be eliminated, it
3293 must be as part of a PARALLEL, since the code above handles
3294 single SETs. We must indicate that we can no longer
3295 eliminate this reg. */
3296 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3298 if (ep->from_rtx == orig_operand[i])
3299 ep->can_eliminate = 0;
3302 /* Companion to the above plus substitution, we can allow
3303 invariants as the source of a plain move. */
3305 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3309 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3310 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3314 = eliminate_regs_1 (recog_data.operand[i], 0,
3315 replace ? insn : NULL_RTX,
3316 is_set_src || in_plus);
3317 if (substed_operand[i] != orig_operand[i])
3319 /* Terminate the search in check_eliminable_occurrences at
3321 *recog_data.operand_loc[i] = 0;
3323 /* If an output operand changed from a REG to a MEM and INSN is an
3324 insn, write a CLOBBER insn. */
3325 if (recog_data.operand_type[i] != OP_IN
3326 && REG_P (orig_operand[i])
3327 && MEM_P (substed_operand[i])
3329 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3334 for (i = 0; i < recog_data.n_dups; i++)
3335 *recog_data.dup_loc[i]
3336 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3338 /* If any eliminable remain, they aren't eliminable anymore. */
3339 check_eliminable_occurrences (old_body);
3341 /* Substitute the operands; the new values are in the substed_operand
3343 for (i = 0; i < recog_data.n_operands; i++)
3344 *recog_data.operand_loc[i] = substed_operand[i];
3345 for (i = 0; i < recog_data.n_dups; i++)
3346 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3348 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3349 re-recognize the insn. We do this in case we had a simple addition
3350 but now can do this as a load-address. This saves an insn in this
3352 If re-recognition fails, the old insn code number will still be used,
3353 and some register operands may have changed into PLUS expressions.
3354 These will be handled by find_reloads by loading them into a register
3359 /* If we aren't replacing things permanently and we changed something,
3360 make another copy to ensure that all the RTL is new. Otherwise
3361 things can go wrong if find_reload swaps commutative operands
3362 and one is inside RTL that has been copied while the other is not. */
3363 new_body = old_body;
3366 new_body = copy_insn (old_body);
3367 if (REG_NOTES (insn))
3368 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3370 PATTERN (insn) = new_body;
3372 /* If we had a move insn but now we don't, rerecognize it. This will
3373 cause spurious re-recognition if the old move had a PARALLEL since
3374 the new one still will, but we can't call single_set without
3375 having put NEW_BODY into the insn and the re-recognition won't
3376 hurt in this rare case. */
3377 /* ??? Why this huge if statement - why don't we just rerecognize the
3381 && ((REG_P (SET_SRC (old_set))
3382 && (GET_CODE (new_body) != SET
3383 || !REG_P (SET_SRC (new_body))))
3384 /* If this was a load from or store to memory, compare
3385 the MEM in recog_data.operand to the one in the insn.
3386 If they are not equal, then rerecognize the insn. */
3388 && ((MEM_P (SET_SRC (old_set))
3389 && SET_SRC (old_set) != recog_data.operand[1])
3390 || (MEM_P (SET_DEST (old_set))
3391 && SET_DEST (old_set) != recog_data.operand[0])))
3392 /* If this was an add insn before, rerecognize. */
3393 || GET_CODE (SET_SRC (old_set)) == PLUS))
3395 int new_icode = recog (PATTERN (insn), insn, 0);
3397 INSN_CODE (insn) = new_icode;
3401 /* Restore the old body. If there were any changes to it, we made a copy
3402 of it while the changes were still in place, so we'll correctly return
3403 a modified insn below. */
3406 /* Restore the old body. */
3407 for (i = 0; i < recog_data.n_operands; i++)
3408 *recog_data.operand_loc[i] = orig_operand[i];
3409 for (i = 0; i < recog_data.n_dups; i++)
3410 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3413 /* Update all elimination pairs to reflect the status after the current
3414 insn. The changes we make were determined by the earlier call to
3415 elimination_effects.
3417 We also detect cases where register elimination cannot be done,
3418 namely, if a register would be both changed and referenced outside a MEM
3419 in the resulting insn since such an insn is often undefined and, even if
3420 not, we cannot know what meaning will be given to it. Note that it is
3421 valid to have a register used in an address in an insn that changes it
3422 (presumably with a pre- or post-increment or decrement).
3424 If anything changes, return nonzero. */
3426 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3428 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3429 ep->can_eliminate = 0;
3431 ep->ref_outside_mem = 0;
3433 if (ep->previous_offset != ep->offset)
3438 /* If we changed something, perform elimination in REG_NOTES. This is
3439 needed even when REPLACE is zero because a REG_DEAD note might refer
3440 to a register that we eliminate and could cause a different number
3441 of spill registers to be needed in the final reload pass than in
3443 if (val && REG_NOTES (insn) != 0)
3445 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3450 /* Loop through all elimination pairs.
3451 Recalculate the number not at initial offset.
3453 Compute the maximum offset (minimum offset if the stack does not
3454 grow downward) for each elimination pair. */
3457 update_eliminable_offsets (void)
3459 struct elim_table *ep;
3461 num_not_at_initial_offset = 0;
3462 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3464 ep->previous_offset = ep->offset;
3465 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3466 num_not_at_initial_offset++;
3470 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3471 replacement we currently believe is valid, mark it as not eliminable if X
3472 modifies DEST in any way other than by adding a constant integer to it.
3474 If DEST is the frame pointer, we do nothing because we assume that
3475 all assignments to the hard frame pointer are nonlocal gotos and are being
3476 done at a time when they are valid and do not disturb anything else.
3477 Some machines want to eliminate a fake argument pointer with either the
3478 frame or stack pointer. Assignments to the hard frame pointer must not
3479 prevent this elimination.
3481 Called via note_stores from reload before starting its passes to scan
3482 the insns of the function. */
3485 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3489 /* A SUBREG of a hard register here is just changing its mode. We should
3490 not see a SUBREG of an eliminable hard register, but check just in
3492 if (GET_CODE (dest) == SUBREG)
3493 dest = SUBREG_REG (dest);
3495 if (dest == hard_frame_pointer_rtx)
3498 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3499 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3500 && (GET_CODE (x) != SET
3501 || GET_CODE (SET_SRC (x)) != PLUS
3502 || XEXP (SET_SRC (x), 0) != dest
3503 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3505 reg_eliminate[i].can_eliminate_previous
3506 = reg_eliminate[i].can_eliminate = 0;
3511 /* Verify that the initial elimination offsets did not change since the
3512 last call to set_initial_elim_offsets. This is used to catch cases
3513 where something illegal happened during reload_as_needed that could
3514 cause incorrect code to be generated if we did not check for it. */
3517 verify_initial_elim_offsets (void)
3521 if (!num_eliminable)
3524 #ifdef ELIMINABLE_REGS
3526 struct elim_table *ep;
3528 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3530 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3531 if (t != ep->initial_offset)
3536 INITIAL_FRAME_POINTER_OFFSET (t);
3537 if (t != reg_eliminate[0].initial_offset)
3544 /* Reset all offsets on eliminable registers to their initial values. */
3547 set_initial_elim_offsets (void)
3549 struct elim_table *ep = reg_eliminate;
3551 #ifdef ELIMINABLE_REGS
3552 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3554 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3555 ep->previous_offset = ep->offset = ep->initial_offset;
3558 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3559 ep->previous_offset = ep->offset = ep->initial_offset;
3562 num_not_at_initial_offset = 0;
3565 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3568 set_initial_eh_label_offset (rtx label)
3570 set_label_offsets (label, NULL_RTX, 1);
3573 /* Initialize the known label offsets.
3574 Set a known offset for each forced label to be at the initial offset
3575 of each elimination. We do this because we assume that all
3576 computed jumps occur from a location where each elimination is
3577 at its initial offset.
3578 For all other labels, show that we don't know the offsets. */
3581 set_initial_label_offsets (void)
3584 memset (offsets_known_at, 0, num_labels);
3586 for (x = forced_labels; x; x = XEXP (x, 1))
3588 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3590 for_each_eh_label (set_initial_eh_label_offset);
3593 /* Set all elimination offsets to the known values for the code label given
3597 set_offsets_for_label (rtx insn)
3600 int label_nr = CODE_LABEL_NUMBER (insn);
3601 struct elim_table *ep;
3603 num_not_at_initial_offset = 0;
3604 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3606 ep->offset = ep->previous_offset
3607 = offsets_at[label_nr - first_label_num][i];
3608 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3609 num_not_at_initial_offset++;
3613 /* See if anything that happened changes which eliminations are valid.
3614 For example, on the SPARC, whether or not the frame pointer can
3615 be eliminated can depend on what registers have been used. We need
3616 not check some conditions again (such as flag_omit_frame_pointer)
3617 since they can't have changed. */
3620 update_eliminables (HARD_REG_SET *pset)
3622 int previous_frame_pointer_needed = frame_pointer_needed;
3623 struct elim_table *ep;
3625 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3626 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3627 #ifdef ELIMINABLE_REGS
3628 || ! CAN_ELIMINATE (ep->from, ep->to)
3631 ep->can_eliminate = 0;
3633 /* Look for the case where we have discovered that we can't replace
3634 register A with register B and that means that we will now be
3635 trying to replace register A with register C. This means we can
3636 no longer replace register C with register B and we need to disable
3637 such an elimination, if it exists. This occurs often with A == ap,
3638 B == sp, and C == fp. */
3640 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3642 struct elim_table *op;
3645 if (! ep->can_eliminate && ep->can_eliminate_previous)
3647 /* Find the current elimination for ep->from, if there is a
3649 for (op = reg_eliminate;
3650 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3651 if (op->from == ep->from && op->can_eliminate)
3657 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3659 for (op = reg_eliminate;
3660 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3661 if (op->from == new_to && op->to == ep->to)
3662 op->can_eliminate = 0;
3666 /* See if any registers that we thought we could eliminate the previous
3667 time are no longer eliminable. If so, something has changed and we
3668 must spill the register. Also, recompute the number of eliminable
3669 registers and see if the frame pointer is needed; it is if there is
3670 no elimination of the frame pointer that we can perform. */
3672 frame_pointer_needed = 1;
3673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3675 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3676 && ep->to != HARD_FRAME_POINTER_REGNUM)
3677 frame_pointer_needed = 0;
3679 if (! ep->can_eliminate && ep->can_eliminate_previous)
3681 ep->can_eliminate_previous = 0;
3682 SET_HARD_REG_BIT (*pset, ep->from);
3687 /* If we didn't need a frame pointer last time, but we do now, spill
3688 the hard frame pointer. */
3689 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3690 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3693 /* Return true if X is used as the target register of an elimination. */
3696 elimination_target_reg_p (rtx x)
3698 struct elim_table *ep;
3700 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3701 if (ep->to_rtx == x && ep->can_eliminate)
3707 /* Initialize the table of registers to eliminate. */
3710 init_elim_table (void)
3712 struct elim_table *ep;
3713 #ifdef ELIMINABLE_REGS
3714 const struct elim_table_1 *ep1;
3718 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3720 /* Does this function require a frame pointer? */
3722 frame_pointer_needed = (! flag_omit_frame_pointer
3723 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3724 and restore sp for alloca. So we can't eliminate
3725 the frame pointer in that case. At some point,
3726 we should improve this by emitting the
3727 sp-adjusting insns for this case. */
3728 || (current_function_calls_alloca
3729 && EXIT_IGNORE_STACK)
3730 || current_function_accesses_prior_frames
3731 || FRAME_POINTER_REQUIRED);
3735 #ifdef ELIMINABLE_REGS
3736 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3737 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3739 ep->from = ep1->from;
3741 ep->can_eliminate = ep->can_eliminate_previous
3742 = (CAN_ELIMINATE (ep->from, ep->to)
3743 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3746 reg_eliminate[0].from = reg_eliminate_1[0].from;
3747 reg_eliminate[0].to = reg_eliminate_1[0].to;
3748 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3749 = ! frame_pointer_needed;
3752 /* Count the number of eliminable registers and build the FROM and TO
3753 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3754 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3755 We depend on this. */
3756 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3758 num_eliminable += ep->can_eliminate;
3759 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3760 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3764 /* Kick all pseudos out of hard register REGNO.
3766 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3767 because we found we can't eliminate some register. In the case, no pseudos
3768 are allowed to be in the register, even if they are only in a block that
3769 doesn't require spill registers, unlike the case when we are spilling this
3770 hard reg to produce another spill register.
3772 Return nonzero if any pseudos needed to be kicked out. */
3775 spill_hard_reg (unsigned int regno, int cant_eliminate)
3781 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3782 df_set_regs_ever_live (regno, true);
3785 /* Spill every pseudo reg that was allocated to this reg
3786 or to something that overlaps this reg. */
3788 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3789 if (reg_renumber[i] >= 0
3790 && (unsigned int) reg_renumber[i] <= regno
3791 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3792 SET_REGNO_REG_SET (&spilled_pseudos, i);
3795 /* After find_reload_regs has been run for all insn that need reloads,
3796 and/or spill_hard_regs was called, this function is used to actually
3797 spill pseudo registers and try to reallocate them. It also sets up the
3798 spill_regs array for use by choose_reload_regs. */
3801 finish_spills (int global)
3803 struct insn_chain *chain;
3804 int something_changed = 0;
3806 reg_set_iterator rsi;
3808 /* Build the spill_regs array for the function. */
3809 /* If there are some registers still to eliminate and one of the spill regs
3810 wasn't ever used before, additional stack space may have to be
3811 allocated to store this register. Thus, we may have changed the offset
3812 between the stack and frame pointers, so mark that something has changed.
3814 One might think that we need only set VAL to 1 if this is a call-used
3815 register. However, the set of registers that must be saved by the
3816 prologue is not identical to the call-used set. For example, the
3817 register used by the call insn for the return PC is a call-used register,
3818 but must be saved by the prologue. */
3821 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3822 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3824 spill_reg_order[i] = n_spills;
3825 spill_regs[n_spills++] = i;
3826 if (num_eliminable && ! df_regs_ever_live_p (i))
3827 something_changed = 1;
3828 df_set_regs_ever_live (i, true);
3831 spill_reg_order[i] = -1;
3833 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3835 /* Record the current hard register the pseudo is allocated to in
3836 pseudo_previous_regs so we avoid reallocating it to the same
3837 hard reg in a later pass. */
3838 gcc_assert (reg_renumber[i] >= 0);
3840 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3841 /* Mark it as no longer having a hard register home. */
3842 reg_renumber[i] = -1;
3843 /* We will need to scan everything again. */
3844 something_changed = 1;
3847 /* Retry global register allocation if possible. */
3850 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3851 /* For every insn that needs reloads, set the registers used as spill
3852 regs in pseudo_forbidden_regs for every pseudo live across the
3854 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3856 EXECUTE_IF_SET_IN_REG_SET
3857 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3859 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3860 chain->used_spill_regs);
3862 EXECUTE_IF_SET_IN_REG_SET
3863 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3865 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3866 chain->used_spill_regs);
3870 /* Retry allocating the spilled pseudos. For each reg, merge the
3871 various reg sets that indicate which hard regs can't be used,
3872 and call retry_global_alloc.
3873 We change spill_pseudos here to only contain pseudos that did not
3874 get a new hard register. */
3875 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3876 if (reg_old_renumber[i] != reg_renumber[i])
3878 HARD_REG_SET forbidden;
3879 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3880 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3881 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3882 retry_global_alloc (i, forbidden);
3883 if (reg_renumber[i] >= 0)
3884 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3888 /* Fix up the register information in the insn chain.
3889 This involves deleting those of the spilled pseudos which did not get
3890 a new hard register home from the live_{before,after} sets. */
3891 for (chain = reload_insn_chain; chain; chain = chain->next)
3893 HARD_REG_SET used_by_pseudos;
3894 HARD_REG_SET used_by_pseudos2;
3896 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3897 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3899 /* Mark any unallocated hard regs as available for spills. That
3900 makes inheritance work somewhat better. */
3901 if (chain->need_reload)
3903 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3904 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3905 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3907 /* Save the old value for the sanity test below. */
3908 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3910 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3911 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3912 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3913 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3915 /* Make sure we only enlarge the set. */
3916 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3917 chain->used_spill_regs));
3921 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3922 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3924 int regno = reg_renumber[i];
3925 if (reg_old_renumber[i] == regno)
3928 alter_reg (i, reg_old_renumber[i]);
3929 reg_old_renumber[i] = regno;
3933 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3935 fprintf (dump_file, " Register %d now in %d.\n\n",
3936 i, reg_renumber[i]);
3940 return something_changed;
3943 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3946 scan_paradoxical_subregs (rtx x)
3950 enum rtx_code code = GET_CODE (x);
3961 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3969 if (REG_P (SUBREG_REG (x))
3970 && (GET_MODE_SIZE (GET_MODE (x))
3971 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3973 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3974 = GET_MODE_SIZE (GET_MODE (x));
3975 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3983 fmt = GET_RTX_FORMAT (code);
3984 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3987 scan_paradoxical_subregs (XEXP (x, i));
3988 else if (fmt[i] == 'E')
3991 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3992 scan_paradoxical_subregs (XVECEXP (x, i, j));
3997 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3998 examine all of the reload insns between PREV and NEXT exclusive, and
3999 annotate all that may trap. */
4002 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4004 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4005 unsigned int trap_count;
4011 if (may_trap_p (PATTERN (insn)))
4015 remove_note (insn, note);
4019 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4020 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4024 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4028 /* Reload pseudo-registers into hard regs around each insn as needed.
4029 Additional register load insns are output before the insn that needs it
4030 and perhaps store insns after insns that modify the reloaded pseudo reg.
4032 reg_last_reload_reg and reg_reloaded_contents keep track of
4033 which registers are already available in reload registers.
4034 We update these for the reloads that we perform,
4035 as the insns are scanned. */
4038 reload_as_needed (int live_known)
4040 struct insn_chain *chain;
4041 #if defined (AUTO_INC_DEC)
4046 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4047 memset (spill_reg_store, 0, sizeof spill_reg_store);
4048 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4049 INIT_REG_SET (®_has_output_reload);
4050 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4051 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4053 set_initial_elim_offsets ();
4055 for (chain = reload_insn_chain; chain; chain = chain->next)
4058 rtx insn = chain->insn;
4059 rtx old_next = NEXT_INSN (insn);
4061 /* If we pass a label, copy the offsets from the label information
4062 into the current offsets of each elimination. */
4064 set_offsets_for_label (insn);
4066 else if (INSN_P (insn))
4068 regset_head regs_to_forget;
4069 INIT_REG_SET (®s_to_forget);
4070 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4072 /* If this is a USE and CLOBBER of a MEM, ensure that any
4073 references to eliminable registers have been removed. */
4075 if ((GET_CODE (PATTERN (insn)) == USE
4076 || GET_CODE (PATTERN (insn)) == CLOBBER)
4077 && MEM_P (XEXP (PATTERN (insn), 0)))
4078 XEXP (XEXP (PATTERN (insn), 0), 0)
4079 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4080 GET_MODE (XEXP (PATTERN (insn), 0)),
4083 /* If we need to do register elimination processing, do so.
4084 This might delete the insn, in which case we are done. */
4085 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4087 eliminate_regs_in_insn (insn, 1);
4090 update_eliminable_offsets ();
4091 CLEAR_REG_SET (®s_to_forget);
4096 /* If need_elim is nonzero but need_reload is zero, one might think
4097 that we could simply set n_reloads to 0. However, find_reloads
4098 could have done some manipulation of the insn (such as swapping
4099 commutative operands), and these manipulations are lost during
4100 the first pass for every insn that needs register elimination.
4101 So the actions of find_reloads must be redone here. */
4103 if (! chain->need_elim && ! chain->need_reload
4104 && ! chain->need_operand_change)
4106 /* First find the pseudo regs that must be reloaded for this insn.
4107 This info is returned in the tables reload_... (see reload.h).
4108 Also modify the body of INSN by substituting RELOAD
4109 rtx's for those pseudo regs. */
4112 CLEAR_REG_SET (®_has_output_reload);
4113 CLEAR_HARD_REG_SET (reg_is_output_reload);
4115 find_reloads (insn, 1, spill_indirect_levels, live_known,
4121 rtx next = NEXT_INSN (insn);
4124 prev = PREV_INSN (insn);
4126 /* Now compute which reload regs to reload them into. Perhaps
4127 reusing reload regs from previous insns, or else output
4128 load insns to reload them. Maybe output store insns too.
4129 Record the choices of reload reg in reload_reg_rtx. */
4130 choose_reload_regs (chain);
4132 /* Merge any reloads that we didn't combine for fear of
4133 increasing the number of spill registers needed but now
4134 discover can be safely merged. */
4135 if (SMALL_REGISTER_CLASSES)
4136 merge_assigned_reloads (insn);
4138 /* Generate the insns to reload operands into or out of
4139 their reload regs. */
4140 emit_reload_insns (chain);
4142 /* Substitute the chosen reload regs from reload_reg_rtx
4143 into the insn's body (or perhaps into the bodies of other
4144 load and store insn that we just made for reloading
4145 and that we moved the structure into). */
4146 subst_reloads (insn);
4148 /* Adjust the exception region notes for loads and stores. */
4149 if (flag_non_call_exceptions && !CALL_P (insn))
4150 fixup_eh_region_note (insn, prev, next);
4152 /* If this was an ASM, make sure that all the reload insns
4153 we have generated are valid. If not, give an error
4155 if (asm_noperands (PATTERN (insn)) >= 0)
4156 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4157 if (p != insn && INSN_P (p)
4158 && GET_CODE (PATTERN (p)) != USE
4159 && (recog_memoized (p) < 0
4160 || (extract_insn (p), ! constrain_operands (1))))
4162 error_for_asm (insn,
4163 "%<asm%> operand requires "
4164 "impossible reload");
4169 if (num_eliminable && chain->need_elim)
4170 update_eliminable_offsets ();
4172 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4173 is no longer validly lying around to save a future reload.
4174 Note that this does not detect pseudos that were reloaded
4175 for this insn in order to be stored in
4176 (obeying register constraints). That is correct; such reload
4177 registers ARE still valid. */
4178 forget_marked_reloads (®s_to_forget);
4179 CLEAR_REG_SET (®s_to_forget);
4181 /* There may have been CLOBBER insns placed after INSN. So scan
4182 between INSN and NEXT and use them to forget old reloads. */
4183 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4184 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4185 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4188 /* Likewise for regs altered by auto-increment in this insn.
4189 REG_INC notes have been changed by reloading:
4190 find_reloads_address_1 records substitutions for them,
4191 which have been performed by subst_reloads above. */
4192 for (i = n_reloads - 1; i >= 0; i--)
4194 rtx in_reg = rld[i].in_reg;
4197 enum rtx_code code = GET_CODE (in_reg);
4198 /* PRE_INC / PRE_DEC will have the reload register ending up
4199 with the same value as the stack slot, but that doesn't
4200 hold true for POST_INC / POST_DEC. Either we have to
4201 convert the memory access to a true POST_INC / POST_DEC,
4202 or we can't use the reload register for inheritance. */
4203 if ((code == POST_INC || code == POST_DEC)
4204 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4205 REGNO (rld[i].reg_rtx))
4206 /* Make sure it is the inc/dec pseudo, and not
4207 some other (e.g. output operand) pseudo. */
4208 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4209 == REGNO (XEXP (in_reg, 0))))
4212 rtx reload_reg = rld[i].reg_rtx;
4213 enum machine_mode mode = GET_MODE (reload_reg);
4217 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4219 /* We really want to ignore REG_INC notes here, so
4220 use PATTERN (p) as argument to reg_set_p . */
4221 if (reg_set_p (reload_reg, PATTERN (p)))
4223 n = count_occurrences (PATTERN (p), reload_reg, 0);
4228 n = validate_replace_rtx (reload_reg,
4229 gen_rtx_fmt_e (code,
4234 /* We must also verify that the constraints
4235 are met after the replacement. */
4238 n = constrain_operands (1);
4242 /* If the constraints were not met, then
4243 undo the replacement. */
4246 validate_replace_rtx (gen_rtx_fmt_e (code,
4259 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4261 /* Mark this as having an output reload so that the
4262 REG_INC processing code below won't invalidate
4263 the reload for inheritance. */
4264 SET_HARD_REG_BIT (reg_is_output_reload,
4265 REGNO (reload_reg));
4266 SET_REGNO_REG_SET (®_has_output_reload,
4267 REGNO (XEXP (in_reg, 0)));
4270 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4273 else if ((code == PRE_INC || code == PRE_DEC)
4274 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4275 REGNO (rld[i].reg_rtx))
4276 /* Make sure it is the inc/dec pseudo, and not
4277 some other (e.g. output operand) pseudo. */
4278 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4279 == REGNO (XEXP (in_reg, 0))))
4281 SET_HARD_REG_BIT (reg_is_output_reload,
4282 REGNO (rld[i].reg_rtx));
4283 SET_REGNO_REG_SET (®_has_output_reload,
4284 REGNO (XEXP (in_reg, 0)));
4288 /* If a pseudo that got a hard register is auto-incremented,
4289 we must purge records of copying it into pseudos without
4291 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4292 if (REG_NOTE_KIND (x) == REG_INC)
4294 /* See if this pseudo reg was reloaded in this insn.
4295 If so, its last-reload info is still valid
4296 because it is based on this insn's reload. */
4297 for (i = 0; i < n_reloads; i++)
4298 if (rld[i].out == XEXP (x, 0))
4302 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4306 /* A reload reg's contents are unknown after a label. */
4308 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4310 /* Don't assume a reload reg is still good after a call insn
4311 if it is a call-used reg, or if it contains a value that will
4312 be partially clobbered by the call. */
4313 else if (CALL_P (insn))
4315 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4316 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4321 free (reg_last_reload_reg);
4322 CLEAR_REG_SET (®_has_output_reload);
4325 /* Discard all record of any value reloaded from X,
4326 or reloaded in X from someplace else;
4327 unless X is an output reload reg of the current insn.
4329 X may be a hard reg (the reload reg)
4330 or it may be a pseudo reg that was reloaded from.
4332 When DATA is non-NULL just mark the registers in regset
4333 to be forgotten later. */
4336 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4341 regset regs = (regset) data;
4343 /* note_stores does give us subregs of hard regs,
4344 subreg_regno_offset requires a hard reg. */
4345 while (GET_CODE (x) == SUBREG)
4347 /* We ignore the subreg offset when calculating the regno,
4348 because we are using the entire underlying hard register
4358 if (regno >= FIRST_PSEUDO_REGISTER)
4364 nr = hard_regno_nregs[regno][GET_MODE (x)];
4365 /* Storing into a spilled-reg invalidates its contents.
4366 This can happen if a block-local pseudo is allocated to that reg
4367 and it wasn't spilled because this block's total need is 0.
4368 Then some insn might have an optional reload and use this reg. */
4370 for (i = 0; i < nr; i++)
4371 /* But don't do this if the reg actually serves as an output
4372 reload reg in the current instruction. */
4374 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4376 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4377 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4378 spill_reg_store[regno + i] = 0;
4384 SET_REGNO_REG_SET (regs, regno + nr);
4387 /* Since value of X has changed,
4388 forget any value previously copied from it. */
4391 /* But don't forget a copy if this is the output reload
4392 that establishes the copy's validity. */
4394 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4395 reg_last_reload_reg[regno + nr] = 0;
4399 /* Forget the reloads marked in regset by previous function. */
4401 forget_marked_reloads (regset regs)
4404 reg_set_iterator rsi;
4405 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4407 if (reg < FIRST_PSEUDO_REGISTER
4408 /* But don't do this if the reg actually serves as an output
4409 reload reg in the current instruction. */
4411 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4413 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4414 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4415 spill_reg_store[reg] = 0;
4418 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4419 reg_last_reload_reg[reg] = 0;
4423 /* The following HARD_REG_SETs indicate when each hard register is
4424 used for a reload of various parts of the current insn. */
4426 /* If reg is unavailable for all reloads. */
4427 static HARD_REG_SET reload_reg_unavailable;
4428 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4429 static HARD_REG_SET reload_reg_used;
4430 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4431 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4432 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4433 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4434 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4435 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4436 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4437 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4438 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4439 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4440 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4441 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4442 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4443 static HARD_REG_SET reload_reg_used_in_op_addr;
4444 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4445 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4446 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4447 static HARD_REG_SET reload_reg_used_in_insn;
4448 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4449 static HARD_REG_SET reload_reg_used_in_other_addr;
4451 /* If reg is in use as a reload reg for any sort of reload. */
4452 static HARD_REG_SET reload_reg_used_at_all;
4454 /* If reg is use as an inherited reload. We just mark the first register
4456 static HARD_REG_SET reload_reg_used_for_inherit;
4458 /* Records which hard regs are used in any way, either as explicit use or
4459 by being allocated to a pseudo during any point of the current insn. */
4460 static HARD_REG_SET reg_used_in_insn;
4462 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4463 TYPE. MODE is used to indicate how many consecutive regs are
4467 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4468 enum machine_mode mode)
4470 unsigned int nregs = hard_regno_nregs[regno][mode];
4473 for (i = regno; i < nregs + regno; i++)
4478 SET_HARD_REG_BIT (reload_reg_used, i);
4481 case RELOAD_FOR_INPUT_ADDRESS:
4482 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4485 case RELOAD_FOR_INPADDR_ADDRESS:
4486 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4489 case RELOAD_FOR_OUTPUT_ADDRESS:
4490 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4493 case RELOAD_FOR_OUTADDR_ADDRESS:
4494 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4497 case RELOAD_FOR_OPERAND_ADDRESS:
4498 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4501 case RELOAD_FOR_OPADDR_ADDR:
4502 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4505 case RELOAD_FOR_OTHER_ADDRESS:
4506 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4509 case RELOAD_FOR_INPUT:
4510 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4513 case RELOAD_FOR_OUTPUT:
4514 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4517 case RELOAD_FOR_INSN:
4518 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4522 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4526 /* Similarly, but show REGNO is no longer in use for a reload. */
4529 clear_reload_reg_in_use (unsigned int regno, int opnum,
4530 enum reload_type type, enum machine_mode mode)
4532 unsigned int nregs = hard_regno_nregs[regno][mode];
4533 unsigned int start_regno, end_regno, r;
4535 /* A complication is that for some reload types, inheritance might
4536 allow multiple reloads of the same types to share a reload register.
4537 We set check_opnum if we have to check only reloads with the same
4538 operand number, and check_any if we have to check all reloads. */
4539 int check_opnum = 0;
4541 HARD_REG_SET *used_in_set;
4546 used_in_set = &reload_reg_used;
4549 case RELOAD_FOR_INPUT_ADDRESS:
4550 used_in_set = &reload_reg_used_in_input_addr[opnum];
4553 case RELOAD_FOR_INPADDR_ADDRESS:
4555 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4558 case RELOAD_FOR_OUTPUT_ADDRESS:
4559 used_in_set = &reload_reg_used_in_output_addr[opnum];
4562 case RELOAD_FOR_OUTADDR_ADDRESS:
4564 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4567 case RELOAD_FOR_OPERAND_ADDRESS:
4568 used_in_set = &reload_reg_used_in_op_addr;
4571 case RELOAD_FOR_OPADDR_ADDR:
4573 used_in_set = &reload_reg_used_in_op_addr_reload;
4576 case RELOAD_FOR_OTHER_ADDRESS:
4577 used_in_set = &reload_reg_used_in_other_addr;
4581 case RELOAD_FOR_INPUT:
4582 used_in_set = &reload_reg_used_in_input[opnum];
4585 case RELOAD_FOR_OUTPUT:
4586 used_in_set = &reload_reg_used_in_output[opnum];
4589 case RELOAD_FOR_INSN:
4590 used_in_set = &reload_reg_used_in_insn;
4595 /* We resolve conflicts with remaining reloads of the same type by
4596 excluding the intervals of reload registers by them from the
4597 interval of freed reload registers. Since we only keep track of
4598 one set of interval bounds, we might have to exclude somewhat
4599 more than what would be necessary if we used a HARD_REG_SET here.
4600 But this should only happen very infrequently, so there should
4601 be no reason to worry about it. */
4603 start_regno = regno;
4604 end_regno = regno + nregs;
4605 if (check_opnum || check_any)
4607 for (i = n_reloads - 1; i >= 0; i--)
4609 if (rld[i].when_needed == type
4610 && (check_any || rld[i].opnum == opnum)
4613 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4614 unsigned int conflict_end
4615 = end_hard_regno (rld[i].mode, conflict_start);
4617 /* If there is an overlap with the first to-be-freed register,
4618 adjust the interval start. */
4619 if (conflict_start <= start_regno && conflict_end > start_regno)
4620 start_regno = conflict_end;
4621 /* Otherwise, if there is a conflict with one of the other
4622 to-be-freed registers, adjust the interval end. */
4623 if (conflict_start > start_regno && conflict_start < end_regno)
4624 end_regno = conflict_start;
4629 for (r = start_regno; r < end_regno; r++)
4630 CLEAR_HARD_REG_BIT (*used_in_set, r);
4633 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4634 specified by OPNUM and TYPE. */
4637 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4641 /* In use for a RELOAD_OTHER means it's not available for anything. */
4642 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4643 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4649 /* In use for anything means we can't use it for RELOAD_OTHER. */
4650 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4651 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4652 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4656 for (i = 0; i < reload_n_operands; i++)
4657 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4658 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4659 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4660 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4661 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4667 case RELOAD_FOR_INPUT:
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4672 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4675 /* If it is used for some other input, can't use it. */
4676 for (i = 0; i < reload_n_operands; i++)
4677 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4680 /* If it is used in a later operand's address, can't use it. */
4681 for (i = opnum + 1; i < reload_n_operands; i++)
4682 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4683 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4688 case RELOAD_FOR_INPUT_ADDRESS:
4689 /* Can't use a register if it is used for an input address for this
4690 operand or used as an input in an earlier one. */
4691 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4692 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4695 for (i = 0; i < opnum; i++)
4696 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4701 case RELOAD_FOR_INPADDR_ADDRESS:
4702 /* Can't use a register if it is used for an input address
4703 for this operand or used as an input in an earlier
4705 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4708 for (i = 0; i < opnum; i++)
4709 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4714 case RELOAD_FOR_OUTPUT_ADDRESS:
4715 /* Can't use a register if it is used for an output address for this
4716 operand or used as an output in this or a later operand. Note
4717 that multiple output operands are emitted in reverse order, so
4718 the conflicting ones are those with lower indices. */
4719 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4722 for (i = 0; i <= opnum; i++)
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4728 case RELOAD_FOR_OUTADDR_ADDRESS:
4729 /* Can't use a register if it is used for an output address
4730 for this operand or used as an output in this or a
4731 later operand. Note that multiple output operands are
4732 emitted in reverse order, so the conflicting ones are
4733 those with lower indices. */
4734 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4737 for (i = 0; i <= opnum; i++)
4738 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4743 case RELOAD_FOR_OPERAND_ADDRESS:
4744 for (i = 0; i < reload_n_operands; i++)
4745 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4748 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4749 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4751 case RELOAD_FOR_OPADDR_ADDR:
4752 for (i = 0; i < reload_n_operands; i++)
4753 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4756 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4758 case RELOAD_FOR_OUTPUT:
4759 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4760 outputs, or an operand address for this or an earlier output.
4761 Note that multiple output operands are emitted in reverse order,
4762 so the conflicting ones are those with higher indices. */
4763 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4766 for (i = 0; i < reload_n_operands; i++)
4767 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4770 for (i = opnum; i < reload_n_operands; i++)
4771 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4772 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4777 case RELOAD_FOR_INSN:
4778 for (i = 0; i < reload_n_operands; i++)
4779 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4780 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4783 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4784 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4786 case RELOAD_FOR_OTHER_ADDRESS:
4787 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4794 /* Return 1 if the value in reload reg REGNO, as used by a reload
4795 needed for the part of the insn specified by OPNUM and TYPE,
4796 is still available in REGNO at the end of the insn.
4798 We can assume that the reload reg was already tested for availability
4799 at the time it is needed, and we should not check this again,
4800 in case the reg has already been marked in use. */
4803 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4810 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4811 its value must reach the end. */
4814 /* If this use is for part of the insn,
4815 its value reaches if no subsequent part uses the same register.
4816 Just like the above function, don't try to do this with lots
4819 case RELOAD_FOR_OTHER_ADDRESS:
4820 /* Here we check for everything else, since these don't conflict
4821 with anything else and everything comes later. */
4823 for (i = 0; i < reload_n_operands; i++)
4824 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4825 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4826 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4827 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4828 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4829 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4832 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4833 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4834 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4835 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4837 case RELOAD_FOR_INPUT_ADDRESS:
4838 case RELOAD_FOR_INPADDR_ADDRESS:
4839 /* Similar, except that we check only for this and subsequent inputs
4840 and the address of only subsequent inputs and we do not need
4841 to check for RELOAD_OTHER objects since they are known not to
4844 for (i = opnum; i < reload_n_operands; i++)
4845 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4848 for (i = opnum + 1; i < reload_n_operands; i++)
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4850 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4853 for (i = 0; i < reload_n_operands; i++)
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4855 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4856 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4859 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4862 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4863 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4864 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4866 case RELOAD_FOR_INPUT:
4867 /* Similar to input address, except we start at the next operand for
4868 both input and input address and we do not check for
4869 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4872 for (i = opnum + 1; i < reload_n_operands; i++)
4873 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4874 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4875 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4878 /* ... fall through ... */
4880 case RELOAD_FOR_OPERAND_ADDRESS:
4881 /* Check outputs and their addresses. */
4883 for (i = 0; i < reload_n_operands; i++)
4884 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4885 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4886 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4889 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4891 case RELOAD_FOR_OPADDR_ADDR:
4892 for (i = 0; i < reload_n_operands; i++)
4893 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4894 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4895 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4898 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4899 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4900 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4902 case RELOAD_FOR_INSN:
4903 /* These conflict with other outputs with RELOAD_OTHER. So
4904 we need only check for output addresses. */
4906 opnum = reload_n_operands;
4908 /* ... fall through ... */
4910 case RELOAD_FOR_OUTPUT:
4911 case RELOAD_FOR_OUTPUT_ADDRESS:
4912 case RELOAD_FOR_OUTADDR_ADDRESS:
4913 /* We already know these can't conflict with a later output. So the
4914 only thing to check are later output addresses.
4915 Note that multiple output operands are emitted in reverse order,
4916 so the conflicting ones are those with lower indices. */
4917 for (i = 0; i < opnum; i++)
4918 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4919 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4930 /* Returns whether R1 and R2 are uniquely chained: the value of one
4931 is used by the other, and that value is not used by any other
4932 reload for this insn. This is used to partially undo the decision
4933 made in find_reloads when in the case of multiple
4934 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4935 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4936 reloads. This code tries to avoid the conflict created by that
4937 change. It might be cleaner to explicitly keep track of which
4938 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4939 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4940 this after the fact. */
4942 reloads_unique_chain_p (int r1, int r2)
4946 /* We only check input reloads. */
4947 if (! rld[r1].in || ! rld[r2].in)
4950 /* Avoid anything with output reloads. */
4951 if (rld[r1].out || rld[r2].out)
4954 /* "chained" means one reload is a component of the other reload,
4955 not the same as the other reload. */
4956 if (rld[r1].opnum != rld[r2].opnum
4957 || rtx_equal_p (rld[r1].in, rld[r2].in)
4958 || rld[r1].optional || rld[r2].optional
4959 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4960 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4963 for (i = 0; i < n_reloads; i ++)
4964 /* Look for input reloads that aren't our two */
4965 if (i != r1 && i != r2 && rld[i].in)
4967 /* If our reload is mentioned at all, it isn't a simple chain. */
4968 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4974 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4977 This function uses the same algorithm as reload_reg_free_p above. */
4980 reloads_conflict (int r1, int r2)
4982 enum reload_type r1_type = rld[r1].when_needed;
4983 enum reload_type r2_type = rld[r2].when_needed;
4984 int r1_opnum = rld[r1].opnum;
4985 int r2_opnum = rld[r2].opnum;
4987 /* RELOAD_OTHER conflicts with everything. */
4988 if (r2_type == RELOAD_OTHER)
4991 /* Otherwise, check conflicts differently for each type. */
4995 case RELOAD_FOR_INPUT:
4996 return (r2_type == RELOAD_FOR_INSN
4997 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4998 || r2_type == RELOAD_FOR_OPADDR_ADDR
4999 || r2_type == RELOAD_FOR_INPUT
5000 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5001 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5002 && r2_opnum > r1_opnum));
5004 case RELOAD_FOR_INPUT_ADDRESS:
5005 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5006 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5008 case RELOAD_FOR_INPADDR_ADDRESS:
5009 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5010 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5012 case RELOAD_FOR_OUTPUT_ADDRESS:
5013 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5014 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5016 case RELOAD_FOR_OUTADDR_ADDRESS:
5017 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5018 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5020 case RELOAD_FOR_OPERAND_ADDRESS:
5021 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5022 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5023 && !reloads_unique_chain_p (r1, r2)));
5025 case RELOAD_FOR_OPADDR_ADDR:
5026 return (r2_type == RELOAD_FOR_INPUT
5027 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5029 case RELOAD_FOR_OUTPUT:
5030 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5031 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5032 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5033 && r2_opnum >= r1_opnum));
5035 case RELOAD_FOR_INSN:
5036 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5037 || r2_type == RELOAD_FOR_INSN
5038 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5040 case RELOAD_FOR_OTHER_ADDRESS:
5041 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5051 /* Indexed by reload number, 1 if incoming value
5052 inherited from previous insns. */
5053 static char reload_inherited[MAX_RELOADS];
5055 /* For an inherited reload, this is the insn the reload was inherited from,
5056 if we know it. Otherwise, this is 0. */
5057 static rtx reload_inheritance_insn[MAX_RELOADS];
5059 /* If nonzero, this is a place to get the value of the reload,
5060 rather than using reload_in. */
5061 static rtx reload_override_in[MAX_RELOADS];
5063 /* For each reload, the hard register number of the register used,
5064 or -1 if we did not need a register for this reload. */
5065 static int reload_spill_index[MAX_RELOADS];
5067 /* Subroutine of free_for_value_p, used to check a single register.
5068 START_REGNO is the starting regno of the full reload register
5069 (possibly comprising multiple hard registers) that we are considering. */
5072 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5073 enum reload_type type, rtx value, rtx out,
5074 int reloadnum, int ignore_address_reloads)
5077 /* Set if we see an input reload that must not share its reload register
5078 with any new earlyclobber, but might otherwise share the reload
5079 register with an output or input-output reload. */
5080 int check_earlyclobber = 0;
5084 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5087 if (out == const0_rtx)
5093 /* We use some pseudo 'time' value to check if the lifetimes of the
5094 new register use would overlap with the one of a previous reload
5095 that is not read-only or uses a different value.
5096 The 'time' used doesn't have to be linear in any shape or form, just
5098 Some reload types use different 'buckets' for each operand.
5099 So there are MAX_RECOG_OPERANDS different time values for each
5101 We compute TIME1 as the time when the register for the prospective
5102 new reload ceases to be live, and TIME2 for each existing
5103 reload as the time when that the reload register of that reload
5105 Where there is little to be gained by exact lifetime calculations,
5106 we just make conservative assumptions, i.e. a longer lifetime;
5107 this is done in the 'default:' cases. */
5110 case RELOAD_FOR_OTHER_ADDRESS:
5111 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5112 time1 = copy ? 0 : 1;
5115 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5117 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5118 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5119 respectively, to the time values for these, we get distinct time
5120 values. To get distinct time values for each operand, we have to
5121 multiply opnum by at least three. We round that up to four because
5122 multiply by four is often cheaper. */
5123 case RELOAD_FOR_INPADDR_ADDRESS:
5124 time1 = opnum * 4 + 2;
5126 case RELOAD_FOR_INPUT_ADDRESS:
5127 time1 = opnum * 4 + 3;
5129 case RELOAD_FOR_INPUT:
5130 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5131 executes (inclusive). */
5132 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5134 case RELOAD_FOR_OPADDR_ADDR:
5136 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5137 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5139 case RELOAD_FOR_OPERAND_ADDRESS:
5140 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5142 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5144 case RELOAD_FOR_OUTADDR_ADDRESS:
5145 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5147 case RELOAD_FOR_OUTPUT_ADDRESS:
5148 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5151 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5154 for (i = 0; i < n_reloads; i++)
5156 rtx reg = rld[i].reg_rtx;
5157 if (reg && REG_P (reg)
5158 && ((unsigned) regno - true_regnum (reg)
5159 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5162 rtx other_input = rld[i].in;
5164 /* If the other reload loads the same input value, that
5165 will not cause a conflict only if it's loading it into
5166 the same register. */
5167 if (true_regnum (reg) != start_regno)
5168 other_input = NULL_RTX;
5169 if (! other_input || ! rtx_equal_p (other_input, value)
5170 || rld[i].out || out)
5173 switch (rld[i].when_needed)
5175 case RELOAD_FOR_OTHER_ADDRESS:
5178 case RELOAD_FOR_INPADDR_ADDRESS:
5179 /* find_reloads makes sure that a
5180 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5181 by at most one - the first -
5182 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5183 address reload is inherited, the address address reload
5184 goes away, so we can ignore this conflict. */
5185 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5186 && ignore_address_reloads
5187 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5188 Then the address address is still needed to store
5189 back the new address. */
5190 && ! rld[reloadnum].out)
5192 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5193 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5195 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5196 && ignore_address_reloads
5197 /* Unless we are reloading an auto_inc expression. */
5198 && ! rld[reloadnum].out)
5200 time2 = rld[i].opnum * 4 + 2;
5202 case RELOAD_FOR_INPUT_ADDRESS:
5203 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5204 && ignore_address_reloads
5205 && ! rld[reloadnum].out)
5207 time2 = rld[i].opnum * 4 + 3;
5209 case RELOAD_FOR_INPUT:
5210 time2 = rld[i].opnum * 4 + 4;
5211 check_earlyclobber = 1;
5213 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5214 == MAX_RECOG_OPERAND * 4 */
5215 case RELOAD_FOR_OPADDR_ADDR:
5216 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5217 && ignore_address_reloads
5218 && ! rld[reloadnum].out)
5220 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5222 case RELOAD_FOR_OPERAND_ADDRESS:
5223 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5224 check_earlyclobber = 1;
5226 case RELOAD_FOR_INSN:
5227 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5229 case RELOAD_FOR_OUTPUT:
5230 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5231 instruction is executed. */
5232 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5234 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5235 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5237 case RELOAD_FOR_OUTADDR_ADDRESS:
5238 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5239 && ignore_address_reloads
5240 && ! rld[reloadnum].out)
5242 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5244 case RELOAD_FOR_OUTPUT_ADDRESS:
5245 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5248 /* If there is no conflict in the input part, handle this
5249 like an output reload. */
5250 if (! rld[i].in || rtx_equal_p (other_input, value))
5252 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5253 /* Earlyclobbered outputs must conflict with inputs. */
5254 if (earlyclobber_operand_p (rld[i].out))
5255 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5260 /* RELOAD_OTHER might be live beyond instruction execution,
5261 but this is not obvious when we set time2 = 1. So check
5262 here if there might be a problem with the new reload
5263 clobbering the register used by the RELOAD_OTHER. */
5271 && (! rld[i].in || rld[i].out
5272 || ! rtx_equal_p (other_input, value)))
5273 || (out && rld[reloadnum].out_reg
5274 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5280 /* Earlyclobbered outputs must conflict with inputs. */
5281 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5287 /* Return 1 if the value in reload reg REGNO, as used by a reload
5288 needed for the part of the insn specified by OPNUM and TYPE,
5289 may be used to load VALUE into it.
5291 MODE is the mode in which the register is used, this is needed to
5292 determine how many hard regs to test.
5294 Other read-only reloads with the same value do not conflict
5295 unless OUT is nonzero and these other reloads have to live while
5296 output reloads live.
5297 If OUT is CONST0_RTX, this is a special case: it means that the
5298 test should not be for using register REGNO as reload register, but
5299 for copying from register REGNO into the reload register.
5301 RELOADNUM is the number of the reload we want to load this value for;
5302 a reload does not conflict with itself.
5304 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5305 reloads that load an address for the very reload we are considering.
5307 The caller has to make sure that there is no conflict with the return
5311 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5312 enum reload_type type, rtx value, rtx out, int reloadnum,
5313 int ignore_address_reloads)
5315 int nregs = hard_regno_nregs[regno][mode];
5317 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5318 value, out, reloadnum,
5319 ignore_address_reloads))
5324 /* Return nonzero if the rtx X is invariant over the current function. */
5325 /* ??? Actually, the places where we use this expect exactly what is
5326 tested here, and not everything that is function invariant. In
5327 particular, the frame pointer and arg pointer are special cased;
5328 pic_offset_table_rtx is not, and we must not spill these things to
5332 function_invariant_p (const_rtx x)
5336 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5338 if (GET_CODE (x) == PLUS
5339 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5340 && CONSTANT_P (XEXP (x, 1)))
5345 /* Determine whether the reload reg X overlaps any rtx'es used for
5346 overriding inheritance. Return nonzero if so. */
5349 conflicts_with_override (rtx x)
5352 for (i = 0; i < n_reloads; i++)
5353 if (reload_override_in[i]
5354 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5359 /* Give an error message saying we failed to find a reload for INSN,
5360 and clear out reload R. */
5362 failed_reload (rtx insn, int r)
5364 if (asm_noperands (PATTERN (insn)) < 0)
5365 /* It's the compiler's fault. */
5366 fatal_insn ("could not find a spill register", insn);
5368 /* It's the user's fault; the operand's mode and constraint
5369 don't match. Disable this reload so we don't crash in final. */
5370 error_for_asm (insn,
5371 "%<asm%> operand constraint incompatible with operand size");
5375 rld[r].optional = 1;
5376 rld[r].secondary_p = 1;
5379 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5380 for reload R. If it's valid, get an rtx for it. Return nonzero if
5383 set_reload_reg (int i, int r)
5386 rtx reg = spill_reg_rtx[i];
5388 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5389 spill_reg_rtx[i] = reg
5390 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5392 regno = true_regnum (reg);
5394 /* Detect when the reload reg can't hold the reload mode.
5395 This used to be one `if', but Sequent compiler can't handle that. */
5396 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5398 enum machine_mode test_mode = VOIDmode;
5400 test_mode = GET_MODE (rld[r].in);
5401 /* If rld[r].in has VOIDmode, it means we will load it
5402 in whatever mode the reload reg has: to wit, rld[r].mode.
5403 We have already tested that for validity. */
5404 /* Aside from that, we need to test that the expressions
5405 to reload from or into have modes which are valid for this
5406 reload register. Otherwise the reload insns would be invalid. */
5407 if (! (rld[r].in != 0 && test_mode != VOIDmode
5408 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5409 if (! (rld[r].out != 0
5410 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5412 /* The reg is OK. */
5415 /* Mark as in use for this insn the reload regs we use
5417 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5418 rld[r].when_needed, rld[r].mode);
5420 rld[r].reg_rtx = reg;
5421 reload_spill_index[r] = spill_regs[i];
5428 /* Find a spill register to use as a reload register for reload R.
5429 LAST_RELOAD is nonzero if this is the last reload for the insn being
5432 Set rld[R].reg_rtx to the register allocated.
5434 We return 1 if successful, or 0 if we couldn't find a spill reg and
5435 we didn't change anything. */
5438 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5443 /* If we put this reload ahead, thinking it is a group,
5444 then insist on finding a group. Otherwise we can grab a
5445 reg that some other reload needs.
5446 (That can happen when we have a 68000 DATA_OR_FP_REG
5447 which is a group of data regs or one fp reg.)
5448 We need not be so restrictive if there are no more reloads
5451 ??? Really it would be nicer to have smarter handling
5452 for that kind of reg class, where a problem like this is normal.
5453 Perhaps those classes should be avoided for reloading
5454 by use of more alternatives. */
5456 int force_group = rld[r].nregs > 1 && ! last_reload;
5458 /* If we want a single register and haven't yet found one,
5459 take any reg in the right class and not in use.
5460 If we want a consecutive group, here is where we look for it.
5462 We use two passes so we can first look for reload regs to
5463 reuse, which are already in use for other reloads in this insn,
5464 and only then use additional registers.
5465 I think that maximizing reuse is needed to make sure we don't
5466 run out of reload regs. Suppose we have three reloads, and
5467 reloads A and B can share regs. These need two regs.
5468 Suppose A and B are given different regs.
5469 That leaves none for C. */
5470 for (pass = 0; pass < 2; pass++)
5472 /* I is the index in spill_regs.
5473 We advance it round-robin between insns to use all spill regs
5474 equally, so that inherited reloads have a chance
5475 of leapfrogging each other. */
5479 for (count = 0; count < n_spills; count++)
5481 int class = (int) rld[r].class;
5487 regnum = spill_regs[i];
5489 if ((reload_reg_free_p (regnum, rld[r].opnum,
5492 /* We check reload_reg_used to make sure we
5493 don't clobber the return register. */
5494 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5495 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5496 rld[r].when_needed, rld[r].in,
5498 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5499 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5500 /* Look first for regs to share, then for unshared. But
5501 don't share regs used for inherited reloads; they are
5502 the ones we want to preserve. */
5504 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5506 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5509 int nr = hard_regno_nregs[regnum][rld[r].mode];
5510 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5511 (on 68000) got us two FP regs. If NR is 1,
5512 we would reject both of them. */
5515 /* If we need only one reg, we have already won. */
5518 /* But reject a single reg if we demand a group. */
5523 /* Otherwise check that as many consecutive regs as we need
5524 are available here. */
5527 int regno = regnum + nr - 1;
5528 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5529 && spill_reg_order[regno] >= 0
5530 && reload_reg_free_p (regno, rld[r].opnum,
5531 rld[r].when_needed)))
5540 /* If we found something on pass 1, omit pass 2. */
5541 if (count < n_spills)
5545 /* We should have found a spill register by now. */
5546 if (count >= n_spills)
5549 /* I is the index in SPILL_REG_RTX of the reload register we are to
5550 allocate. Get an rtx for it and find its register number. */
5552 return set_reload_reg (i, r);
5555 /* Initialize all the tables needed to allocate reload registers.
5556 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5557 is the array we use to restore the reg_rtx field for every reload. */
5560 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5564 for (i = 0; i < n_reloads; i++)
5565 rld[i].reg_rtx = save_reload_reg_rtx[i];
5567 memset (reload_inherited, 0, MAX_RELOADS);
5568 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5569 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5571 CLEAR_HARD_REG_SET (reload_reg_used);
5572 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5573 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5574 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5575 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5576 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5578 CLEAR_HARD_REG_SET (reg_used_in_insn);
5581 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5582 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5583 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5584 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5585 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5586 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5589 for (i = 0; i < reload_n_operands; i++)
5591 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5592 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5593 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5594 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5595 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5596 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5599 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5601 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5603 for (i = 0; i < n_reloads; i++)
5604 /* If we have already decided to use a certain register,
5605 don't use it in another way. */
5607 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5608 rld[i].when_needed, rld[i].mode);
5611 /* Assign hard reg targets for the pseudo-registers we must reload
5612 into hard regs for this insn.
5613 Also output the instructions to copy them in and out of the hard regs.
5615 For machines with register classes, we are responsible for
5616 finding a reload reg in the proper class. */
5619 choose_reload_regs (struct insn_chain *chain)
5621 rtx insn = chain->insn;
5623 unsigned int max_group_size = 1;
5624 enum reg_class group_class = NO_REGS;
5625 int pass, win, inheritance;
5627 rtx save_reload_reg_rtx[MAX_RELOADS];
5629 /* In order to be certain of getting the registers we need,
5630 we must sort the reloads into order of increasing register class.
5631 Then our grabbing of reload registers will parallel the process
5632 that provided the reload registers.
5634 Also note whether any of the reloads wants a consecutive group of regs.
5635 If so, record the maximum size of the group desired and what
5636 register class contains all the groups needed by this insn. */
5638 for (j = 0; j < n_reloads; j++)
5640 reload_order[j] = j;
5641 if (rld[j].reg_rtx != NULL_RTX)
5643 gcc_assert (REG_P (rld[j].reg_rtx)
5644 && HARD_REGISTER_P (rld[j].reg_rtx));
5645 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5648 reload_spill_index[j] = -1;
5650 if (rld[j].nregs > 1)
5652 max_group_size = MAX (rld[j].nregs, max_group_size);
5654 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5657 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5661 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5663 /* If -O, try first with inheritance, then turning it off.
5664 If not -O, don't do inheritance.
5665 Using inheritance when not optimizing leads to paradoxes
5666 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5667 because one side of the comparison might be inherited. */
5669 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5671 choose_reload_regs_init (chain, save_reload_reg_rtx);
5673 /* Process the reloads in order of preference just found.
5674 Beyond this point, subregs can be found in reload_reg_rtx.
5676 This used to look for an existing reloaded home for all of the
5677 reloads, and only then perform any new reloads. But that could lose
5678 if the reloads were done out of reg-class order because a later
5679 reload with a looser constraint might have an old home in a register
5680 needed by an earlier reload with a tighter constraint.
5682 To solve this, we make two passes over the reloads, in the order
5683 described above. In the first pass we try to inherit a reload
5684 from a previous insn. If there is a later reload that needs a
5685 class that is a proper subset of the class being processed, we must
5686 also allocate a spill register during the first pass.
5688 Then make a second pass over the reloads to allocate any reloads
5689 that haven't been given registers yet. */
5691 for (j = 0; j < n_reloads; j++)
5693 int r = reload_order[j];
5694 rtx search_equiv = NULL_RTX;
5696 /* Ignore reloads that got marked inoperative. */
5697 if (rld[r].out == 0 && rld[r].in == 0
5698 && ! rld[r].secondary_p)
5701 /* If find_reloads chose to use reload_in or reload_out as a reload
5702 register, we don't need to chose one. Otherwise, try even if it
5703 found one since we might save an insn if we find the value lying
5705 Try also when reload_in is a pseudo without a hard reg. */
5706 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5707 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5708 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5709 && !MEM_P (rld[r].in)
5710 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5713 #if 0 /* No longer needed for correct operation.
5714 It might give better code, or might not; worth an experiment? */
5715 /* If this is an optional reload, we can't inherit from earlier insns
5716 until we are sure that any non-optional reloads have been allocated.
5717 The following code takes advantage of the fact that optional reloads
5718 are at the end of reload_order. */
5719 if (rld[r].optional != 0)
5720 for (i = 0; i < j; i++)
5721 if ((rld[reload_order[i]].out != 0
5722 || rld[reload_order[i]].in != 0
5723 || rld[reload_order[i]].secondary_p)
5724 && ! rld[reload_order[i]].optional
5725 && rld[reload_order[i]].reg_rtx == 0)
5726 allocate_reload_reg (chain, reload_order[i], 0);
5729 /* First see if this pseudo is already available as reloaded
5730 for a previous insn. We cannot try to inherit for reloads
5731 that are smaller than the maximum number of registers needed
5732 for groups unless the register we would allocate cannot be used
5735 We could check here to see if this is a secondary reload for
5736 an object that is already in a register of the desired class.
5737 This would avoid the need for the secondary reload register.
5738 But this is complex because we can't easily determine what
5739 objects might want to be loaded via this reload. So let a
5740 register be allocated here. In `emit_reload_insns' we suppress
5741 one of the loads in the case described above. */
5747 enum machine_mode mode = VOIDmode;
5751 else if (REG_P (rld[r].in))
5753 regno = REGNO (rld[r].in);
5754 mode = GET_MODE (rld[r].in);
5756 else if (REG_P (rld[r].in_reg))
5758 regno = REGNO (rld[r].in_reg);
5759 mode = GET_MODE (rld[r].in_reg);
5761 else if (GET_CODE (rld[r].in_reg) == SUBREG
5762 && REG_P (SUBREG_REG (rld[r].in_reg)))
5764 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5765 if (regno < FIRST_PSEUDO_REGISTER)
5766 regno = subreg_regno (rld[r].in_reg);
5768 byte = SUBREG_BYTE (rld[r].in_reg);
5769 mode = GET_MODE (rld[r].in_reg);
5772 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5773 && REG_P (XEXP (rld[r].in_reg, 0)))
5775 regno = REGNO (XEXP (rld[r].in_reg, 0));
5776 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5777 rld[r].out = rld[r].in;
5781 /* This won't work, since REGNO can be a pseudo reg number.
5782 Also, it takes much more hair to keep track of all the things
5783 that can invalidate an inherited reload of part of a pseudoreg. */
5784 else if (GET_CODE (rld[r].in) == SUBREG
5785 && REG_P (SUBREG_REG (rld[r].in)))
5786 regno = subreg_regno (rld[r].in);
5790 && reg_last_reload_reg[regno] != 0
5791 #ifdef CANNOT_CHANGE_MODE_CLASS
5792 /* Verify that the register it's in can be used in
5794 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5795 GET_MODE (reg_last_reload_reg[regno]),
5800 enum reg_class class = rld[r].class, last_class;
5801 rtx last_reg = reg_last_reload_reg[regno];
5802 enum machine_mode need_mode;
5804 i = REGNO (last_reg);
5805 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5806 last_class = REGNO_REG_CLASS (i);
5812 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5813 + byte * BITS_PER_UNIT,
5814 GET_MODE_CLASS (mode));
5816 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5817 >= GET_MODE_SIZE (need_mode))
5818 && reg_reloaded_contents[i] == regno
5819 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5820 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5821 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5822 /* Even if we can't use this register as a reload
5823 register, we might use it for reload_override_in,
5824 if copying it to the desired class is cheap
5826 || ((REGISTER_MOVE_COST (mode, last_class, class)
5827 < MEMORY_MOVE_COST (mode, class, 1))
5828 && (secondary_reload_class (1, class, mode,
5831 #ifdef SECONDARY_MEMORY_NEEDED
5832 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5837 && (rld[r].nregs == max_group_size
5838 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5840 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5841 rld[r].when_needed, rld[r].in,
5844 /* If a group is needed, verify that all the subsequent
5845 registers still have their values intact. */
5846 int nr = hard_regno_nregs[i][rld[r].mode];
5849 for (k = 1; k < nr; k++)
5850 if (reg_reloaded_contents[i + k] != regno
5851 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5859 last_reg = (GET_MODE (last_reg) == mode
5860 ? last_reg : gen_rtx_REG (mode, i));
5863 for (k = 0; k < nr; k++)
5864 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5867 /* We found a register that contains the
5868 value we need. If this register is the
5869 same as an `earlyclobber' operand of the
5870 current insn, just mark it as a place to
5871 reload from since we can't use it as the
5872 reload register itself. */
5874 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5875 if (reg_overlap_mentioned_for_reload_p
5876 (reg_last_reload_reg[regno],
5877 reload_earlyclobbers[i1]))
5880 if (i1 != n_earlyclobbers
5881 || ! (free_for_value_p (i, rld[r].mode,
5883 rld[r].when_needed, rld[r].in,
5885 /* Don't use it if we'd clobber a pseudo reg. */
5886 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5888 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5889 /* Don't clobber the frame pointer. */
5890 || (i == HARD_FRAME_POINTER_REGNUM
5891 && frame_pointer_needed
5893 /* Don't really use the inherited spill reg
5894 if we need it wider than we've got it. */
5895 || (GET_MODE_SIZE (rld[r].mode)
5896 > GET_MODE_SIZE (mode))
5899 /* If find_reloads chose reload_out as reload
5900 register, stay with it - that leaves the
5901 inherited register for subsequent reloads. */
5902 || (rld[r].out && rld[r].reg_rtx
5903 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5905 if (! rld[r].optional)
5907 reload_override_in[r] = last_reg;
5908 reload_inheritance_insn[r]
5909 = reg_reloaded_insn[i];
5915 /* We can use this as a reload reg. */
5916 /* Mark the register as in use for this part of
5918 mark_reload_reg_in_use (i,
5922 rld[r].reg_rtx = last_reg;
5923 reload_inherited[r] = 1;
5924 reload_inheritance_insn[r]
5925 = reg_reloaded_insn[i];
5926 reload_spill_index[r] = i;
5927 for (k = 0; k < nr; k++)
5928 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5936 /* Here's another way to see if the value is already lying around. */
5939 && ! reload_inherited[r]
5941 && (CONSTANT_P (rld[r].in)
5942 || GET_CODE (rld[r].in) == PLUS
5943 || REG_P (rld[r].in)
5944 || MEM_P (rld[r].in))
5945 && (rld[r].nregs == max_group_size
5946 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5947 search_equiv = rld[r].in;
5948 /* If this is an output reload from a simple move insn, look
5949 if an equivalence for the input is available. */
5950 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5952 rtx set = single_set (insn);
5955 && rtx_equal_p (rld[r].out, SET_DEST (set))
5956 && CONSTANT_P (SET_SRC (set)))
5957 search_equiv = SET_SRC (set);
5963 = find_equiv_reg (search_equiv, insn, rld[r].class,
5964 -1, NULL, 0, rld[r].mode);
5970 regno = REGNO (equiv);
5973 /* This must be a SUBREG of a hard register.
5974 Make a new REG since this might be used in an
5975 address and not all machines support SUBREGs
5977 gcc_assert (GET_CODE (equiv) == SUBREG);
5978 regno = subreg_regno (equiv);
5979 equiv = gen_rtx_REG (rld[r].mode, regno);
5980 /* If we choose EQUIV as the reload register, but the
5981 loop below decides to cancel the inheritance, we'll
5982 end up reloading EQUIV in rld[r].mode, not the mode
5983 it had originally. That isn't safe when EQUIV isn't
5984 available as a spill register since its value might
5985 still be live at this point. */
5986 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5987 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5992 /* If we found a spill reg, reject it unless it is free
5993 and of the desired class. */
5997 int bad_for_class = 0;
5998 int max_regno = regno + rld[r].nregs;
6000 for (i = regno; i < max_regno; i++)
6002 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6004 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6009 && ! free_for_value_p (regno, rld[r].mode,
6010 rld[r].opnum, rld[r].when_needed,
6011 rld[r].in, rld[r].out, r, 1))
6016 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6019 /* We found a register that contains the value we need.
6020 If this register is the same as an `earlyclobber' operand
6021 of the current insn, just mark it as a place to reload from
6022 since we can't use it as the reload register itself. */
6025 for (i = 0; i < n_earlyclobbers; i++)
6026 if (reg_overlap_mentioned_for_reload_p (equiv,
6027 reload_earlyclobbers[i]))
6029 if (! rld[r].optional)
6030 reload_override_in[r] = equiv;
6035 /* If the equiv register we have found is explicitly clobbered
6036 in the current insn, it depends on the reload type if we
6037 can use it, use it for reload_override_in, or not at all.
6038 In particular, we then can't use EQUIV for a
6039 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6043 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6044 switch (rld[r].when_needed)
6046 case RELOAD_FOR_OTHER_ADDRESS:
6047 case RELOAD_FOR_INPADDR_ADDRESS:
6048 case RELOAD_FOR_INPUT_ADDRESS:
6049 case RELOAD_FOR_OPADDR_ADDR:
6052 case RELOAD_FOR_INPUT:
6053 case RELOAD_FOR_OPERAND_ADDRESS:
6054 if (! rld[r].optional)
6055 reload_override_in[r] = equiv;
6061 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6062 switch (rld[r].when_needed)
6064 case RELOAD_FOR_OTHER_ADDRESS:
6065 case RELOAD_FOR_INPADDR_ADDRESS:
6066 case RELOAD_FOR_INPUT_ADDRESS:
6067 case RELOAD_FOR_OPADDR_ADDR:
6068 case RELOAD_FOR_OPERAND_ADDRESS:
6069 case RELOAD_FOR_INPUT:
6072 if (! rld[r].optional)
6073 reload_override_in[r] = equiv;
6081 /* If we found an equivalent reg, say no code need be generated
6082 to load it, and use it as our reload reg. */
6084 && (regno != HARD_FRAME_POINTER_REGNUM
6085 || !frame_pointer_needed))
6087 int nr = hard_regno_nregs[regno][rld[r].mode];
6089 rld[r].reg_rtx = equiv;
6090 reload_inherited[r] = 1;
6092 /* If reg_reloaded_valid is not set for this register,
6093 there might be a stale spill_reg_store lying around.
6094 We must clear it, since otherwise emit_reload_insns
6095 might delete the store. */
6096 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6097 spill_reg_store[regno] = NULL_RTX;
6098 /* If any of the hard registers in EQUIV are spill
6099 registers, mark them as in use for this insn. */
6100 for (k = 0; k < nr; k++)
6102 i = spill_reg_order[regno + k];
6105 mark_reload_reg_in_use (regno, rld[r].opnum,
6108 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6115 /* If we found a register to use already, or if this is an optional
6116 reload, we are done. */
6117 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6121 /* No longer needed for correct operation. Might or might
6122 not give better code on the average. Want to experiment? */
6124 /* See if there is a later reload that has a class different from our
6125 class that intersects our class or that requires less register
6126 than our reload. If so, we must allocate a register to this
6127 reload now, since that reload might inherit a previous reload
6128 and take the only available register in our class. Don't do this
6129 for optional reloads since they will force all previous reloads
6130 to be allocated. Also don't do this for reloads that have been
6133 for (i = j + 1; i < n_reloads; i++)
6135 int s = reload_order[i];
6137 if ((rld[s].in == 0 && rld[s].out == 0
6138 && ! rld[s].secondary_p)
6142 if ((rld[s].class != rld[r].class
6143 && reg_classes_intersect_p (rld[r].class,
6145 || rld[s].nregs < rld[r].nregs)
6152 allocate_reload_reg (chain, r, j == n_reloads - 1);
6156 /* Now allocate reload registers for anything non-optional that
6157 didn't get one yet. */
6158 for (j = 0; j < n_reloads; j++)
6160 int r = reload_order[j];
6162 /* Ignore reloads that got marked inoperative. */
6163 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6166 /* Skip reloads that already have a register allocated or are
6168 if (rld[r].reg_rtx != 0 || rld[r].optional)
6171 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6175 /* If that loop got all the way, we have won. */
6182 /* Loop around and try without any inheritance. */
6187 /* First undo everything done by the failed attempt
6188 to allocate with inheritance. */
6189 choose_reload_regs_init (chain, save_reload_reg_rtx);
6191 /* Some sanity tests to verify that the reloads found in the first
6192 pass are identical to the ones we have now. */
6193 gcc_assert (chain->n_reloads == n_reloads);
6195 for (i = 0; i < n_reloads; i++)
6197 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6199 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6200 for (j = 0; j < n_spills; j++)
6201 if (spill_regs[j] == chain->rld[i].regno)
6202 if (! set_reload_reg (j, i))
6203 failed_reload (chain->insn, i);
6207 /* If we thought we could inherit a reload, because it seemed that
6208 nothing else wanted the same reload register earlier in the insn,
6209 verify that assumption, now that all reloads have been assigned.
6210 Likewise for reloads where reload_override_in has been set. */
6212 /* If doing expensive optimizations, do one preliminary pass that doesn't
6213 cancel any inheritance, but removes reloads that have been needed only
6214 for reloads that we know can be inherited. */
6215 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6217 for (j = 0; j < n_reloads; j++)
6219 int r = reload_order[j];
6221 if (reload_inherited[r] && rld[r].reg_rtx)
6222 check_reg = rld[r].reg_rtx;
6223 else if (reload_override_in[r]
6224 && (REG_P (reload_override_in[r])
6225 || GET_CODE (reload_override_in[r]) == SUBREG))
6226 check_reg = reload_override_in[r];
6229 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6230 rld[r].opnum, rld[r].when_needed, rld[r].in,
6231 (reload_inherited[r]
6232 ? rld[r].out : const0_rtx),
6237 reload_inherited[r] = 0;
6238 reload_override_in[r] = 0;
6240 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6241 reload_override_in, then we do not need its related
6242 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6243 likewise for other reload types.
6244 We handle this by removing a reload when its only replacement
6245 is mentioned in reload_in of the reload we are going to inherit.
6246 A special case are auto_inc expressions; even if the input is
6247 inherited, we still need the address for the output. We can
6248 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6249 If we succeeded removing some reload and we are doing a preliminary
6250 pass just to remove such reloads, make another pass, since the
6251 removal of one reload might allow us to inherit another one. */
6253 && rld[r].out != rld[r].in
6254 && remove_address_replacements (rld[r].in) && pass)
6259 /* Now that reload_override_in is known valid,
6260 actually override reload_in. */
6261 for (j = 0; j < n_reloads; j++)
6262 if (reload_override_in[j])
6263 rld[j].in = reload_override_in[j];
6265 /* If this reload won't be done because it has been canceled or is
6266 optional and not inherited, clear reload_reg_rtx so other
6267 routines (such as subst_reloads) don't get confused. */
6268 for (j = 0; j < n_reloads; j++)
6269 if (rld[j].reg_rtx != 0
6270 && ((rld[j].optional && ! reload_inherited[j])
6271 || (rld[j].in == 0 && rld[j].out == 0
6272 && ! rld[j].secondary_p)))
6274 int regno = true_regnum (rld[j].reg_rtx);
6276 if (spill_reg_order[regno] >= 0)
6277 clear_reload_reg_in_use (regno, rld[j].opnum,
6278 rld[j].when_needed, rld[j].mode);
6280 reload_spill_index[j] = -1;
6283 /* Record which pseudos and which spill regs have output reloads. */
6284 for (j = 0; j < n_reloads; j++)
6286 int r = reload_order[j];
6288 i = reload_spill_index[r];
6290 /* I is nonneg if this reload uses a register.
6291 If rld[r].reg_rtx is 0, this is an optional reload
6292 that we opted to ignore. */
6293 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6294 && rld[r].reg_rtx != 0)
6296 int nregno = REGNO (rld[r].out_reg);
6299 if (nregno < FIRST_PSEUDO_REGISTER)
6300 nr = hard_regno_nregs[nregno][rld[r].mode];
6303 SET_REGNO_REG_SET (®_has_output_reload,
6308 nr = hard_regno_nregs[i][rld[r].mode];
6310 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6313 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6314 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6315 || rld[r].when_needed == RELOAD_FOR_INSN);
6320 /* Deallocate the reload register for reload R. This is called from
6321 remove_address_replacements. */
6324 deallocate_reload_reg (int r)
6328 if (! rld[r].reg_rtx)
6330 regno = true_regnum (rld[r].reg_rtx);
6332 if (spill_reg_order[regno] >= 0)
6333 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6335 reload_spill_index[r] = -1;
6338 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6339 reloads of the same item for fear that we might not have enough reload
6340 registers. However, normally they will get the same reload register
6341 and hence actually need not be loaded twice.
6343 Here we check for the most common case of this phenomenon: when we have
6344 a number of reloads for the same object, each of which were allocated
6345 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6346 reload, and is not modified in the insn itself. If we find such,
6347 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6348 This will not increase the number of spill registers needed and will
6349 prevent redundant code. */
6352 merge_assigned_reloads (rtx insn)
6356 /* Scan all the reloads looking for ones that only load values and
6357 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6358 assigned and not modified by INSN. */
6360 for (i = 0; i < n_reloads; i++)
6362 int conflicting_input = 0;
6363 int max_input_address_opnum = -1;
6364 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6366 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6367 || rld[i].out != 0 || rld[i].reg_rtx == 0
6368 || reg_set_p (rld[i].reg_rtx, insn))
6371 /* Look at all other reloads. Ensure that the only use of this
6372 reload_reg_rtx is in a reload that just loads the same value
6373 as we do. Note that any secondary reloads must be of the identical
6374 class since the values, modes, and result registers are the
6375 same, so we need not do anything with any secondary reloads. */
6377 for (j = 0; j < n_reloads; j++)
6379 if (i == j || rld[j].reg_rtx == 0
6380 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6384 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6385 && rld[j].opnum > max_input_address_opnum)
6386 max_input_address_opnum = rld[j].opnum;
6388 /* If the reload regs aren't exactly the same (e.g, different modes)
6389 or if the values are different, we can't merge this reload.
6390 But if it is an input reload, we might still merge
6391 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6393 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6394 || rld[j].out != 0 || rld[j].in == 0
6395 || ! rtx_equal_p (rld[i].in, rld[j].in))
6397 if (rld[j].when_needed != RELOAD_FOR_INPUT
6398 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6399 || rld[i].opnum > rld[j].opnum)
6400 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6402 conflicting_input = 1;
6403 if (min_conflicting_input_opnum > rld[j].opnum)
6404 min_conflicting_input_opnum = rld[j].opnum;
6408 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6409 we, in fact, found any matching reloads. */
6412 && max_input_address_opnum <= min_conflicting_input_opnum)
6414 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6416 for (j = 0; j < n_reloads; j++)
6417 if (i != j && rld[j].reg_rtx != 0
6418 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6419 && (! conflicting_input
6420 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6421 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6423 rld[i].when_needed = RELOAD_OTHER;
6425 reload_spill_index[j] = -1;
6426 transfer_replacements (i, j);
6429 /* If this is now RELOAD_OTHER, look for any reloads that
6430 load parts of this operand and set them to
6431 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6432 RELOAD_OTHER for outputs. Note that this test is
6433 equivalent to looking for reloads for this operand
6436 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6437 it may share registers with a RELOAD_FOR_INPUT, so we can
6438 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6439 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6441 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6442 instruction is assigned the same register as the earlier
6443 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6444 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6445 instruction to be deleted later on. */
6447 if (rld[i].when_needed == RELOAD_OTHER)
6448 for (j = 0; j < n_reloads; j++)
6450 && rld[j].when_needed != RELOAD_OTHER
6451 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6452 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6453 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6454 && (! conflicting_input
6455 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6456 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6457 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6463 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6464 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6465 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6467 /* Check to see if we accidentally converted two
6468 reloads that use the same reload register with
6469 different inputs to the same type. If so, the
6470 resulting code won't work. */
6472 for (k = 0; k < j; k++)
6473 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6474 || rld[k].when_needed != rld[j].when_needed
6475 || !rtx_equal_p (rld[k].reg_rtx,
6477 || rtx_equal_p (rld[k].in,
6484 /* These arrays are filled by emit_reload_insns and its subroutines. */
6485 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6486 static rtx other_input_address_reload_insns = 0;
6487 static rtx other_input_reload_insns = 0;
6488 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6489 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6490 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6491 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6492 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6493 static rtx operand_reload_insns = 0;
6494 static rtx other_operand_reload_insns = 0;
6495 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6497 /* Values to be put in spill_reg_store are put here first. */
6498 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6499 static HARD_REG_SET reg_reloaded_died;
6501 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6502 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6503 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6504 adjusted register, and return true. Otherwise, return false. */
6506 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6507 enum reg_class new_class,
6508 enum machine_mode new_mode)
6513 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6515 unsigned regno = REGNO (reg);
6517 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6519 if (GET_MODE (reg) != new_mode)
6521 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6523 if (hard_regno_nregs[regno][new_mode]
6524 > hard_regno_nregs[regno][GET_MODE (reg)])
6526 reg = reload_adjust_reg_for_mode (reg, new_mode);
6534 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6535 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6536 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6537 adjusted register, and return true. Otherwise, return false. */
6539 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6540 enum insn_code icode)
6543 enum reg_class new_class = scratch_reload_class (icode);
6544 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6546 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6547 new_class, new_mode);
6550 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6551 has the number J. OLD contains the value to be used as input. */
6554 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6557 rtx insn = chain->insn;
6558 rtx reloadreg = rl->reg_rtx;
6559 rtx oldequiv_reg = 0;
6562 enum machine_mode mode;
6565 /* Determine the mode to reload in.
6566 This is very tricky because we have three to choose from.
6567 There is the mode the insn operand wants (rl->inmode).
6568 There is the mode of the reload register RELOADREG.
6569 There is the intrinsic mode of the operand, which we could find
6570 by stripping some SUBREGs.
6571 It turns out that RELOADREG's mode is irrelevant:
6572 we can change that arbitrarily.
6574 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6575 then the reload reg may not support QImode moves, so use SImode.
6576 If foo is in memory due to spilling a pseudo reg, this is safe,
6577 because the QImode value is in the least significant part of a
6578 slot big enough for a SImode. If foo is some other sort of
6579 memory reference, then it is impossible to reload this case,
6580 so previous passes had better make sure this never happens.
6582 Then consider a one-word union which has SImode and one of its
6583 members is a float, being fetched as (SUBREG:SF union:SI).
6584 We must fetch that as SFmode because we could be loading into
6585 a float-only register. In this case OLD's mode is correct.
6587 Consider an immediate integer: it has VOIDmode. Here we need
6588 to get a mode from something else.
6590 In some cases, there is a fourth mode, the operand's
6591 containing mode. If the insn specifies a containing mode for
6592 this operand, it overrides all others.
6594 I am not sure whether the algorithm here is always right,
6595 but it does the right things in those cases. */
6597 mode = GET_MODE (old);
6598 if (mode == VOIDmode)
6601 /* delete_output_reload is only invoked properly if old contains
6602 the original pseudo register. Since this is replaced with a
6603 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6604 find the pseudo in RELOAD_IN_REG. */
6605 if (reload_override_in[j]
6606 && REG_P (rl->in_reg))
6613 else if (REG_P (oldequiv))
6614 oldequiv_reg = oldequiv;
6615 else if (GET_CODE (oldequiv) == SUBREG)
6616 oldequiv_reg = SUBREG_REG (oldequiv);
6618 /* If we are reloading from a register that was recently stored in
6619 with an output-reload, see if we can prove there was
6620 actually no need to store the old value in it. */
6622 if (optimize && REG_P (oldequiv)
6623 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6624 && spill_reg_store[REGNO (oldequiv)]
6626 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6627 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6629 delete_output_reload (insn, j, REGNO (oldequiv));
6631 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6632 then load RELOADREG from OLDEQUIV. Note that we cannot use
6633 gen_lowpart_common since it can do the wrong thing when
6634 RELOADREG has a multi-word mode. Note that RELOADREG
6635 must always be a REG here. */
6637 if (GET_MODE (reloadreg) != mode)
6638 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6639 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6640 oldequiv = SUBREG_REG (oldequiv);
6641 if (GET_MODE (oldequiv) != VOIDmode
6642 && mode != GET_MODE (oldequiv))
6643 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6645 /* Switch to the right place to emit the reload insns. */
6646 switch (rl->when_needed)
6649 where = &other_input_reload_insns;
6651 case RELOAD_FOR_INPUT:
6652 where = &input_reload_insns[rl->opnum];
6654 case RELOAD_FOR_INPUT_ADDRESS:
6655 where = &input_address_reload_insns[rl->opnum];
6657 case RELOAD_FOR_INPADDR_ADDRESS:
6658 where = &inpaddr_address_reload_insns[rl->opnum];
6660 case RELOAD_FOR_OUTPUT_ADDRESS:
6661 where = &output_address_reload_insns[rl->opnum];
6663 case RELOAD_FOR_OUTADDR_ADDRESS:
6664 where = &outaddr_address_reload_insns[rl->opnum];
6666 case RELOAD_FOR_OPERAND_ADDRESS:
6667 where = &operand_reload_insns;
6669 case RELOAD_FOR_OPADDR_ADDR:
6670 where = &other_operand_reload_insns;
6672 case RELOAD_FOR_OTHER_ADDRESS:
6673 where = &other_input_address_reload_insns;
6679 push_to_sequence (*where);
6681 /* Auto-increment addresses must be reloaded in a special way. */
6682 if (rl->out && ! rl->out_reg)
6684 /* We are not going to bother supporting the case where a
6685 incremented register can't be copied directly from
6686 OLDEQUIV since this seems highly unlikely. */
6687 gcc_assert (rl->secondary_in_reload < 0);
6689 if (reload_inherited[j])
6690 oldequiv = reloadreg;
6692 old = XEXP (rl->in_reg, 0);
6694 if (optimize && REG_P (oldequiv)
6695 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6696 && spill_reg_store[REGNO (oldequiv)]
6698 && (dead_or_set_p (insn,
6699 spill_reg_stored_to[REGNO (oldequiv)])
6700 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6702 delete_output_reload (insn, j, REGNO (oldequiv));
6704 /* Prevent normal processing of this reload. */
6706 /* Output a special code sequence for this case. */
6707 new_spill_reg_store[REGNO (reloadreg)]
6708 = inc_for_reload (reloadreg, oldequiv, rl->out,
6712 /* If we are reloading a pseudo-register that was set by the previous
6713 insn, see if we can get rid of that pseudo-register entirely
6714 by redirecting the previous insn into our reload register. */
6716 else if (optimize && REG_P (old)
6717 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6718 && dead_or_set_p (insn, old)
6719 /* This is unsafe if some other reload
6720 uses the same reg first. */
6721 && ! conflicts_with_override (reloadreg)
6722 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6723 rl->when_needed, old, rl->out, j, 0))
6725 rtx temp = PREV_INSN (insn);
6726 while (temp && NOTE_P (temp))
6727 temp = PREV_INSN (temp);
6729 && NONJUMP_INSN_P (temp)
6730 && GET_CODE (PATTERN (temp)) == SET
6731 && SET_DEST (PATTERN (temp)) == old
6732 /* Make sure we can access insn_operand_constraint. */
6733 && asm_noperands (PATTERN (temp)) < 0
6734 /* This is unsafe if operand occurs more than once in current
6735 insn. Perhaps some occurrences aren't reloaded. */
6736 && count_occurrences (PATTERN (insn), old, 0) == 1)
6738 rtx old = SET_DEST (PATTERN (temp));
6739 /* Store into the reload register instead of the pseudo. */
6740 SET_DEST (PATTERN (temp)) = reloadreg;
6742 /* Verify that resulting insn is valid. */
6743 extract_insn (temp);
6744 if (constrain_operands (1))
6746 /* If the previous insn is an output reload, the source is
6747 a reload register, and its spill_reg_store entry will
6748 contain the previous destination. This is now
6750 if (REG_P (SET_SRC (PATTERN (temp)))
6751 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6753 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6754 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6757 /* If these are the only uses of the pseudo reg,
6758 pretend for GDB it lives in the reload reg we used. */
6759 if (REG_N_DEATHS (REGNO (old)) == 1
6760 && REG_N_SETS (REGNO (old)) == 1)
6762 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6763 alter_reg (REGNO (old), -1);
6769 SET_DEST (PATTERN (temp)) = old;
6774 /* We can't do that, so output an insn to load RELOADREG. */
6776 /* If we have a secondary reload, pick up the secondary register
6777 and icode, if any. If OLDEQUIV and OLD are different or
6778 if this is an in-out reload, recompute whether or not we
6779 still need a secondary register and what the icode should
6780 be. If we still need a secondary register and the class or
6781 icode is different, go back to reloading from OLD if using
6782 OLDEQUIV means that we got the wrong type of register. We
6783 cannot have different class or icode due to an in-out reload
6784 because we don't make such reloads when both the input and
6785 output need secondary reload registers. */
6787 if (! special && rl->secondary_in_reload >= 0)
6789 rtx second_reload_reg = 0;
6790 rtx third_reload_reg = 0;
6791 int secondary_reload = rl->secondary_in_reload;
6792 rtx real_oldequiv = oldequiv;
6795 enum insn_code icode;
6796 enum insn_code tertiary_icode = CODE_FOR_nothing;
6798 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6799 and similarly for OLD.
6800 See comments in get_secondary_reload in reload.c. */
6801 /* If it is a pseudo that cannot be replaced with its
6802 equivalent MEM, we must fall back to reload_in, which
6803 will have all the necessary substitutions registered.
6804 Likewise for a pseudo that can't be replaced with its
6805 equivalent constant.
6807 Take extra care for subregs of such pseudos. Note that
6808 we cannot use reg_equiv_mem in this case because it is
6809 not in the right mode. */
6812 if (GET_CODE (tmp) == SUBREG)
6813 tmp = SUBREG_REG (tmp);
6815 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6816 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6817 || reg_equiv_constant[REGNO (tmp)] != 0))
6819 if (! reg_equiv_mem[REGNO (tmp)]
6820 || num_not_at_initial_offset
6821 || GET_CODE (oldequiv) == SUBREG)
6822 real_oldequiv = rl->in;
6824 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6828 if (GET_CODE (tmp) == SUBREG)
6829 tmp = SUBREG_REG (tmp);
6831 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6832 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6833 || reg_equiv_constant[REGNO (tmp)] != 0))
6835 if (! reg_equiv_mem[REGNO (tmp)]
6836 || num_not_at_initial_offset
6837 || GET_CODE (old) == SUBREG)
6840 real_old = reg_equiv_mem[REGNO (tmp)];
6843 second_reload_reg = rld[secondary_reload].reg_rtx;
6844 if (rld[secondary_reload].secondary_in_reload >= 0)
6846 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6848 third_reload_reg = rld[tertiary_reload].reg_rtx;
6849 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6850 /* We'd have to add more code for quartary reloads. */
6851 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6853 icode = rl->secondary_in_icode;
6855 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6856 || (rl->in != 0 && rl->out != 0))
6858 secondary_reload_info sri, sri2;
6859 enum reg_class new_class, new_t_class;
6861 sri.icode = CODE_FOR_nothing;
6862 sri.prev_sri = NULL;
6863 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6866 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6867 second_reload_reg = 0;
6868 else if (new_class == NO_REGS)
6870 if (reload_adjust_reg_for_icode (&second_reload_reg,
6871 third_reload_reg, sri.icode))
6872 icode = sri.icode, third_reload_reg = 0;
6874 oldequiv = old, real_oldequiv = real_old;
6876 else if (sri.icode != CODE_FOR_nothing)
6877 /* We currently lack a way to express this in reloads. */
6881 sri2.icode = CODE_FOR_nothing;
6882 sri2.prev_sri = &sri;
6883 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6884 new_class, mode, &sri);
6885 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6887 if (reload_adjust_reg_for_temp (&second_reload_reg,
6890 third_reload_reg = 0, tertiary_icode = sri2.icode;
6892 oldequiv = old, real_oldequiv = real_old;
6894 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6896 rtx intermediate = second_reload_reg;
6898 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6900 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6903 second_reload_reg = intermediate;
6904 tertiary_icode = sri2.icode;
6907 oldequiv = old, real_oldequiv = real_old;
6909 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6911 rtx intermediate = second_reload_reg;
6913 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6915 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6918 second_reload_reg = intermediate;
6919 tertiary_icode = sri2.icode;
6922 oldequiv = old, real_oldequiv = real_old;
6925 /* This could be handled more intelligently too. */
6926 oldequiv = old, real_oldequiv = real_old;
6930 /* If we still need a secondary reload register, check
6931 to see if it is being used as a scratch or intermediate
6932 register and generate code appropriately. If we need
6933 a scratch register, use REAL_OLDEQUIV since the form of
6934 the insn may depend on the actual address if it is
6937 if (second_reload_reg)
6939 if (icode != CODE_FOR_nothing)
6941 /* We'd have to add extra code to handle this case. */
6942 gcc_assert (!third_reload_reg);
6944 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6945 second_reload_reg));
6950 /* See if we need a scratch register to load the
6951 intermediate register (a tertiary reload). */
6952 if (tertiary_icode != CODE_FOR_nothing)
6954 emit_insn ((GEN_FCN (tertiary_icode)
6955 (second_reload_reg, real_oldequiv,
6956 third_reload_reg)));
6958 else if (third_reload_reg)
6960 gen_reload (third_reload_reg, real_oldequiv,
6963 gen_reload (second_reload_reg, third_reload_reg,
6968 gen_reload (second_reload_reg, real_oldequiv,
6972 oldequiv = second_reload_reg;
6977 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6979 rtx real_oldequiv = oldequiv;
6981 if ((REG_P (oldequiv)
6982 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6983 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6984 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6985 || (GET_CODE (oldequiv) == SUBREG
6986 && REG_P (SUBREG_REG (oldequiv))
6987 && (REGNO (SUBREG_REG (oldequiv))
6988 >= FIRST_PSEUDO_REGISTER)
6989 && ((reg_equiv_memory_loc
6990 [REGNO (SUBREG_REG (oldequiv))] != 0)
6991 || (reg_equiv_constant
6992 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6993 || (CONSTANT_P (oldequiv)
6994 && (PREFERRED_RELOAD_CLASS (oldequiv,
6995 REGNO_REG_CLASS (REGNO (reloadreg)))
6997 real_oldequiv = rl->in;
6998 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7002 if (flag_non_call_exceptions)
7003 copy_eh_notes (insn, get_insns ());
7005 /* End this sequence. */
7006 *where = get_insns ();
7009 /* Update reload_override_in so that delete_address_reloads_1
7010 can see the actual register usage. */
7012 reload_override_in[j] = oldequiv;
7015 /* Generate insns to for the output reload RL, which is for the insn described
7016 by CHAIN and has the number J. */
7018 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7021 rtx reloadreg = rl->reg_rtx;
7022 rtx insn = chain->insn;
7025 enum machine_mode mode = GET_MODE (old);
7028 if (rl->when_needed == RELOAD_OTHER)
7031 push_to_sequence (output_reload_insns[rl->opnum]);
7033 /* Determine the mode to reload in.
7034 See comments above (for input reloading). */
7036 if (mode == VOIDmode)
7038 /* VOIDmode should never happen for an output. */
7039 if (asm_noperands (PATTERN (insn)) < 0)
7040 /* It's the compiler's fault. */
7041 fatal_insn ("VOIDmode on an output", insn);
7042 error_for_asm (insn, "output operand is constant in %<asm%>");
7043 /* Prevent crash--use something we know is valid. */
7045 old = gen_rtx_REG (mode, REGNO (reloadreg));
7048 if (GET_MODE (reloadreg) != mode)
7049 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7051 /* If we need two reload regs, set RELOADREG to the intermediate
7052 one, since it will be stored into OLD. We might need a secondary
7053 register only for an input reload, so check again here. */
7055 if (rl->secondary_out_reload >= 0)
7058 int secondary_reload = rl->secondary_out_reload;
7059 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7061 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7062 && reg_equiv_mem[REGNO (old)] != 0)
7063 real_old = reg_equiv_mem[REGNO (old)];
7065 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7067 rtx second_reloadreg = reloadreg;
7068 reloadreg = rld[secondary_reload].reg_rtx;
7070 /* See if RELOADREG is to be used as a scratch register
7071 or as an intermediate register. */
7072 if (rl->secondary_out_icode != CODE_FOR_nothing)
7074 /* We'd have to add extra code to handle this case. */
7075 gcc_assert (tertiary_reload < 0);
7077 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7078 (real_old, second_reloadreg, reloadreg)));
7083 /* See if we need both a scratch and intermediate reload
7086 enum insn_code tertiary_icode
7087 = rld[secondary_reload].secondary_out_icode;
7089 /* We'd have to add more code for quartary reloads. */
7090 gcc_assert (tertiary_reload < 0
7091 || rld[tertiary_reload].secondary_out_reload < 0);
7093 if (GET_MODE (reloadreg) != mode)
7094 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7096 if (tertiary_icode != CODE_FOR_nothing)
7098 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7101 /* Copy primary reload reg to secondary reload reg.
7102 (Note that these have been swapped above, then
7103 secondary reload reg to OLD using our insn.) */
7105 /* If REAL_OLD is a paradoxical SUBREG, remove it
7106 and try to put the opposite SUBREG on
7108 if (GET_CODE (real_old) == SUBREG
7109 && (GET_MODE_SIZE (GET_MODE (real_old))
7110 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7111 && 0 != (tem = gen_lowpart_common
7112 (GET_MODE (SUBREG_REG (real_old)),
7114 real_old = SUBREG_REG (real_old), reloadreg = tem;
7116 gen_reload (reloadreg, second_reloadreg,
7117 rl->opnum, rl->when_needed);
7118 emit_insn ((GEN_FCN (tertiary_icode)
7119 (real_old, reloadreg, third_reloadreg)));
7125 /* Copy between the reload regs here and then to
7128 gen_reload (reloadreg, second_reloadreg,
7129 rl->opnum, rl->when_needed);
7130 if (tertiary_reload >= 0)
7132 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7134 gen_reload (third_reloadreg, reloadreg,
7135 rl->opnum, rl->when_needed);
7136 reloadreg = third_reloadreg;
7143 /* Output the last reload insn. */
7148 /* Don't output the last reload if OLD is not the dest of
7149 INSN and is in the src and is clobbered by INSN. */
7150 if (! flag_expensive_optimizations
7152 || !(set = single_set (insn))
7153 || rtx_equal_p (old, SET_DEST (set))
7154 || !reg_mentioned_p (old, SET_SRC (set))
7155 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7156 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7157 gen_reload (old, reloadreg, rl->opnum,
7161 /* Look at all insns we emitted, just to be safe. */
7162 for (p = get_insns (); p; p = NEXT_INSN (p))
7165 rtx pat = PATTERN (p);
7167 /* If this output reload doesn't come from a spill reg,
7168 clear any memory of reloaded copies of the pseudo reg.
7169 If this output reload comes from a spill reg,
7170 reg_has_output_reload will make this do nothing. */
7171 note_stores (pat, forget_old_reloads_1, NULL);
7173 if (reg_mentioned_p (rl->reg_rtx, pat))
7175 rtx set = single_set (insn);
7176 if (reload_spill_index[j] < 0
7178 && SET_SRC (set) == rl->reg_rtx)
7180 int src = REGNO (SET_SRC (set));
7182 reload_spill_index[j] = src;
7183 SET_HARD_REG_BIT (reg_is_output_reload, src);
7184 if (find_regno_note (insn, REG_DEAD, src))
7185 SET_HARD_REG_BIT (reg_reloaded_died, src);
7187 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7189 int s = rl->secondary_out_reload;
7190 set = single_set (p);
7191 /* If this reload copies only to the secondary reload
7192 register, the secondary reload does the actual
7194 if (s >= 0 && set == NULL_RTX)
7195 /* We can't tell what function the secondary reload
7196 has and where the actual store to the pseudo is
7197 made; leave new_spill_reg_store alone. */
7200 && SET_SRC (set) == rl->reg_rtx
7201 && SET_DEST (set) == rld[s].reg_rtx)
7203 /* Usually the next instruction will be the
7204 secondary reload insn; if we can confirm
7205 that it is, setting new_spill_reg_store to
7206 that insn will allow an extra optimization. */
7207 rtx s_reg = rld[s].reg_rtx;
7208 rtx next = NEXT_INSN (p);
7209 rld[s].out = rl->out;
7210 rld[s].out_reg = rl->out_reg;
7211 set = single_set (next);
7212 if (set && SET_SRC (set) == s_reg
7213 && ! new_spill_reg_store[REGNO (s_reg)])
7215 SET_HARD_REG_BIT (reg_is_output_reload,
7217 new_spill_reg_store[REGNO (s_reg)] = next;
7221 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7226 if (rl->when_needed == RELOAD_OTHER)
7228 emit_insn (other_output_reload_insns[rl->opnum]);
7229 other_output_reload_insns[rl->opnum] = get_insns ();
7232 output_reload_insns[rl->opnum] = get_insns ();
7234 if (flag_non_call_exceptions)
7235 copy_eh_notes (insn, get_insns ());
7240 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7241 and has the number J. */
7243 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7245 rtx insn = chain->insn;
7246 rtx old = (rl->in && MEM_P (rl->in)
7247 ? rl->in_reg : rl->in);
7250 /* AUTO_INC reloads need to be handled even if inherited. We got an
7251 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7252 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7253 && ! rtx_equal_p (rl->reg_rtx, old)
7254 && rl->reg_rtx != 0)
7255 emit_input_reload_insns (chain, rld + j, old, j);
7257 /* When inheriting a wider reload, we have a MEM in rl->in,
7258 e.g. inheriting a SImode output reload for
7259 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7260 if (optimize && reload_inherited[j] && rl->in
7262 && MEM_P (rl->in_reg)
7263 && reload_spill_index[j] >= 0
7264 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7265 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7267 /* If we are reloading a register that was recently stored in with an
7268 output-reload, see if we can prove there was
7269 actually no need to store the old value in it. */
7272 && (reload_inherited[j] || reload_override_in[j])
7274 && REG_P (rl->reg_rtx)
7275 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7277 /* There doesn't seem to be any reason to restrict this to pseudos
7278 and doing so loses in the case where we are copying from a
7279 register of the wrong class. */
7280 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7281 >= FIRST_PSEUDO_REGISTER)
7283 /* The insn might have already some references to stackslots
7284 replaced by MEMs, while reload_out_reg still names the
7286 && (dead_or_set_p (insn,
7287 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7288 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7290 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7293 /* Do output reloading for reload RL, which is for the insn described by
7294 CHAIN and has the number J.
7295 ??? At some point we need to support handling output reloads of
7296 JUMP_INSNs or insns that set cc0. */
7298 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7301 rtx insn = chain->insn;
7302 /* If this is an output reload that stores something that is
7303 not loaded in this same reload, see if we can eliminate a previous
7305 rtx pseudo = rl->out_reg;
7310 && ! rtx_equal_p (rl->in_reg, pseudo)
7311 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7312 && reg_last_reload_reg[REGNO (pseudo)])
7314 int pseudo_no = REGNO (pseudo);
7315 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7317 /* We don't need to test full validity of last_regno for
7318 inherit here; we only want to know if the store actually
7319 matches the pseudo. */
7320 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7321 && reg_reloaded_contents[last_regno] == pseudo_no
7322 && spill_reg_store[last_regno]
7323 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7324 delete_output_reload (insn, j, last_regno);
7329 || rl->reg_rtx == old
7330 || rl->reg_rtx == 0)
7333 /* An output operand that dies right away does need a reload,
7334 but need not be copied from it. Show the new location in the
7336 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7337 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7339 XEXP (note, 0) = rl->reg_rtx;
7342 /* Likewise for a SUBREG of an operand that dies. */
7343 else if (GET_CODE (old) == SUBREG
7344 && REG_P (SUBREG_REG (old))
7345 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7348 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7352 else if (GET_CODE (old) == SCRATCH)
7353 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7354 but we don't want to make an output reload. */
7357 /* If is a JUMP_INSN, we can't support output reloads yet. */
7358 gcc_assert (NONJUMP_INSN_P (insn));
7360 emit_output_reload_insns (chain, rld + j, j);
7363 /* Reload number R reloads from or to a group of hard registers starting at
7364 register REGNO. Return true if it can be treated for inheritance purposes
7365 like a group of reloads, each one reloading a single hard register.
7366 The caller has already checked that the spill register and REGNO use
7367 the same number of registers to store the reload value. */
7370 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7372 #ifdef CANNOT_CHANGE_MODE_CLASS
7373 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7374 GET_MODE (rld[r].reg_rtx),
7375 reg_raw_mode[reload_spill_index[r]])
7376 && !REG_CANNOT_CHANGE_MODE_P (regno,
7377 GET_MODE (rld[r].reg_rtx),
7378 reg_raw_mode[regno]));
7384 /* Output insns to reload values in and out of the chosen reload regs. */
7387 emit_reload_insns (struct insn_chain *chain)
7389 rtx insn = chain->insn;
7393 CLEAR_HARD_REG_SET (reg_reloaded_died);
7395 for (j = 0; j < reload_n_operands; j++)
7396 input_reload_insns[j] = input_address_reload_insns[j]
7397 = inpaddr_address_reload_insns[j]
7398 = output_reload_insns[j] = output_address_reload_insns[j]
7399 = outaddr_address_reload_insns[j]
7400 = other_output_reload_insns[j] = 0;
7401 other_input_address_reload_insns = 0;
7402 other_input_reload_insns = 0;
7403 operand_reload_insns = 0;
7404 other_operand_reload_insns = 0;
7406 /* Dump reloads into the dump file. */
7409 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7410 debug_reload_to_stream (dump_file);
7413 /* Now output the instructions to copy the data into and out of the
7414 reload registers. Do these in the order that the reloads were reported,
7415 since reloads of base and index registers precede reloads of operands
7416 and the operands may need the base and index registers reloaded. */
7418 for (j = 0; j < n_reloads; j++)
7421 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7422 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7424 do_input_reload (chain, rld + j, j);
7425 do_output_reload (chain, rld + j, j);
7428 /* Now write all the insns we made for reloads in the order expected by
7429 the allocation functions. Prior to the insn being reloaded, we write
7430 the following reloads:
7432 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7434 RELOAD_OTHER reloads.
7436 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7437 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7438 RELOAD_FOR_INPUT reload for the operand.
7440 RELOAD_FOR_OPADDR_ADDRS reloads.
7442 RELOAD_FOR_OPERAND_ADDRESS reloads.
7444 After the insn being reloaded, we write the following:
7446 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7447 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7448 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7449 reloads for the operand. The RELOAD_OTHER output reloads are
7450 output in descending order by reload number. */
7452 emit_insn_before (other_input_address_reload_insns, insn);
7453 emit_insn_before (other_input_reload_insns, insn);
7455 for (j = 0; j < reload_n_operands; j++)
7457 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7458 emit_insn_before (input_address_reload_insns[j], insn);
7459 emit_insn_before (input_reload_insns[j], insn);
7462 emit_insn_before (other_operand_reload_insns, insn);
7463 emit_insn_before (operand_reload_insns, insn);
7465 for (j = 0; j < reload_n_operands; j++)
7467 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7468 x = emit_insn_after (output_address_reload_insns[j], x);
7469 x = emit_insn_after (output_reload_insns[j], x);
7470 emit_insn_after (other_output_reload_insns[j], x);
7473 /* For all the spill regs newly reloaded in this instruction,
7474 record what they were reloaded from, so subsequent instructions
7475 can inherit the reloads.
7477 Update spill_reg_store for the reloads of this insn.
7478 Copy the elements that were updated in the loop above. */
7480 for (j = 0; j < n_reloads; j++)
7482 int r = reload_order[j];
7483 int i = reload_spill_index[r];
7485 /* If this is a non-inherited input reload from a pseudo, we must
7486 clear any memory of a previous store to the same pseudo. Only do
7487 something if there will not be an output reload for the pseudo
7489 if (rld[r].in_reg != 0
7490 && ! (reload_inherited[r] || reload_override_in[r]))
7492 rtx reg = rld[r].in_reg;
7494 if (GET_CODE (reg) == SUBREG)
7495 reg = SUBREG_REG (reg);
7498 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7499 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7501 int nregno = REGNO (reg);
7503 if (reg_last_reload_reg[nregno])
7505 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7507 if (reg_reloaded_contents[last_regno] == nregno)
7508 spill_reg_store[last_regno] = 0;
7513 /* I is nonneg if this reload used a register.
7514 If rld[r].reg_rtx is 0, this is an optional reload
7515 that we opted to ignore. */
7517 if (i >= 0 && rld[r].reg_rtx != 0)
7519 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7521 int part_reaches_end = 0;
7522 int all_reaches_end = 1;
7524 /* For a multi register reload, we need to check if all or part
7525 of the value lives to the end. */
7526 for (k = 0; k < nr; k++)
7528 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7529 rld[r].when_needed))
7530 part_reaches_end = 1;
7532 all_reaches_end = 0;
7535 /* Ignore reloads that don't reach the end of the insn in
7537 if (all_reaches_end)
7539 /* First, clear out memory of what used to be in this spill reg.
7540 If consecutive registers are used, clear them all. */
7542 for (k = 0; k < nr; k++)
7544 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7545 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7548 /* Maybe the spill reg contains a copy of reload_out. */
7550 && (REG_P (rld[r].out)
7554 || REG_P (rld[r].out_reg)))
7556 rtx out = (REG_P (rld[r].out)
7560 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7561 int nregno = REGNO (out);
7562 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7563 : hard_regno_nregs[nregno]
7564 [GET_MODE (rld[r].reg_rtx)]);
7567 spill_reg_store[i] = new_spill_reg_store[i];
7568 spill_reg_stored_to[i] = out;
7569 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7571 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7573 && inherit_piecemeal_p (r, nregno));
7575 /* If NREGNO is a hard register, it may occupy more than
7576 one register. If it does, say what is in the
7577 rest of the registers assuming that both registers
7578 agree on how many words the object takes. If not,
7579 invalidate the subsequent registers. */
7581 if (nregno < FIRST_PSEUDO_REGISTER)
7582 for (k = 1; k < nnr; k++)
7583 reg_last_reload_reg[nregno + k]
7585 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7588 /* Now do the inverse operation. */
7589 for (k = 0; k < nr; k++)
7591 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7592 reg_reloaded_contents[i + k]
7593 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7596 reg_reloaded_insn[i + k] = insn;
7597 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7598 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7599 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7603 /* Maybe the spill reg contains a copy of reload_in. Only do
7604 something if there will not be an output reload for
7605 the register being reloaded. */
7606 else if (rld[r].out_reg == 0
7608 && ((REG_P (rld[r].in)
7609 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7610 && !REGNO_REG_SET_P (®_has_output_reload,
7612 || (REG_P (rld[r].in_reg)
7613 && !REGNO_REG_SET_P (®_has_output_reload,
7614 REGNO (rld[r].in_reg))))
7615 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7622 if (REG_P (rld[r].in)
7623 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7625 else if (REG_P (rld[r].in_reg))
7628 in = XEXP (rld[r].in_reg, 0);
7629 nregno = REGNO (in);
7631 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7632 : hard_regno_nregs[nregno]
7633 [GET_MODE (rld[r].reg_rtx)]);
7635 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7637 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7639 && inherit_piecemeal_p (r, nregno));
7641 if (nregno < FIRST_PSEUDO_REGISTER)
7642 for (k = 1; k < nnr; k++)
7643 reg_last_reload_reg[nregno + k]
7645 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7648 /* Unless we inherited this reload, show we haven't
7649 recently done a store.
7650 Previous stores of inherited auto_inc expressions
7651 also have to be discarded. */
7652 if (! reload_inherited[r]
7653 || (rld[r].out && ! rld[r].out_reg))
7654 spill_reg_store[i] = 0;
7656 for (k = 0; k < nr; k++)
7658 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7659 reg_reloaded_contents[i + k]
7660 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7663 reg_reloaded_insn[i + k] = insn;
7664 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7665 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7666 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7671 /* However, if part of the reload reaches the end, then we must
7672 invalidate the old info for the part that survives to the end. */
7673 else if (part_reaches_end)
7675 for (k = 0; k < nr; k++)
7676 if (reload_reg_reaches_end_p (i + k,
7678 rld[r].when_needed))
7679 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7683 /* The following if-statement was #if 0'd in 1.34 (or before...).
7684 It's reenabled in 1.35 because supposedly nothing else
7685 deals with this problem. */
7687 /* If a register gets output-reloaded from a non-spill register,
7688 that invalidates any previous reloaded copy of it.
7689 But forget_old_reloads_1 won't get to see it, because
7690 it thinks only about the original insn. So invalidate it here.
7691 Also do the same thing for RELOAD_OTHER constraints where the
7692 output is discarded. */
7694 && ((rld[r].out != 0
7695 && (REG_P (rld[r].out)
7696 || (MEM_P (rld[r].out)
7697 && REG_P (rld[r].out_reg))))
7698 || (rld[r].out == 0 && rld[r].out_reg
7699 && REG_P (rld[r].out_reg))))
7701 rtx out = ((rld[r].out && REG_P (rld[r].out))
7702 ? rld[r].out : rld[r].out_reg);
7703 int nregno = REGNO (out);
7705 /* REG_RTX is now set or clobbered by the main instruction.
7706 As the comment above explains, forget_old_reloads_1 only
7707 sees the original instruction, and there is no guarantee
7708 that the original instruction also clobbered REG_RTX.
7709 For example, if find_reloads sees that the input side of
7710 a matched operand pair dies in this instruction, it may
7711 use the input register as the reload register.
7713 Calling forget_old_reloads_1 is a waste of effort if
7714 REG_RTX is also the output register.
7716 If we know that REG_RTX holds the value of a pseudo
7717 register, the code after the call will record that fact. */
7718 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7719 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7721 if (nregno >= FIRST_PSEUDO_REGISTER)
7723 rtx src_reg, store_insn = NULL_RTX;
7725 reg_last_reload_reg[nregno] = 0;
7727 /* If we can find a hard register that is stored, record
7728 the storing insn so that we may delete this insn with
7729 delete_output_reload. */
7730 src_reg = rld[r].reg_rtx;
7732 /* If this is an optional reload, try to find the source reg
7733 from an input reload. */
7736 rtx set = single_set (insn);
7737 if (set && SET_DEST (set) == rld[r].out)
7741 src_reg = SET_SRC (set);
7743 for (k = 0; k < n_reloads; k++)
7745 if (rld[k].in == src_reg)
7747 src_reg = rld[k].reg_rtx;
7754 store_insn = new_spill_reg_store[REGNO (src_reg)];
7755 if (src_reg && REG_P (src_reg)
7756 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7758 int src_regno = REGNO (src_reg);
7759 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7760 /* The place where to find a death note varies with
7761 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7762 necessarily checked exactly in the code that moves
7763 notes, so just check both locations. */
7764 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7765 if (! note && store_insn)
7766 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7769 spill_reg_store[src_regno + nr] = store_insn;
7770 spill_reg_stored_to[src_regno + nr] = out;
7771 reg_reloaded_contents[src_regno + nr] = nregno;
7772 reg_reloaded_insn[src_regno + nr] = store_insn;
7773 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7774 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7775 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7776 GET_MODE (src_reg)))
7777 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7779 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7781 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7783 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7785 reg_last_reload_reg[nregno] = src_reg;
7786 /* We have to set reg_has_output_reload here, or else
7787 forget_old_reloads_1 will clear reg_last_reload_reg
7789 SET_REGNO_REG_SET (®_has_output_reload,
7795 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7797 while (num_regs-- > 0)
7798 reg_last_reload_reg[nregno + num_regs] = 0;
7802 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7805 /* Go through the motions to emit INSN and test if it is strictly valid.
7806 Return the emitted insn if valid, else return NULL. */
7809 emit_insn_if_valid_for_reload (rtx insn)
7811 rtx last = get_last_insn ();
7814 insn = emit_insn (insn);
7815 code = recog_memoized (insn);
7819 extract_insn (insn);
7820 /* We want constrain operands to treat this insn strictly in its
7821 validity determination, i.e., the way it would after reload has
7823 if (constrain_operands (1))
7827 delete_insns_since (last);
7831 /* Emit code to perform a reload from IN (which may be a reload register) to
7832 OUT (which may also be a reload register). IN or OUT is from operand
7833 OPNUM with reload type TYPE.
7835 Returns first insn emitted. */
7838 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7840 rtx last = get_last_insn ();
7843 /* If IN is a paradoxical SUBREG, remove it and try to put the
7844 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7845 if (GET_CODE (in) == SUBREG
7846 && (GET_MODE_SIZE (GET_MODE (in))
7847 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7848 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7849 in = SUBREG_REG (in), out = tem;
7850 else if (GET_CODE (out) == SUBREG
7851 && (GET_MODE_SIZE (GET_MODE (out))
7852 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7853 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7854 out = SUBREG_REG (out), in = tem;
7856 /* How to do this reload can get quite tricky. Normally, we are being
7857 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7858 register that didn't get a hard register. In that case we can just
7859 call emit_move_insn.
7861 We can also be asked to reload a PLUS that adds a register or a MEM to
7862 another register, constant or MEM. This can occur during frame pointer
7863 elimination and while reloading addresses. This case is handled by
7864 trying to emit a single insn to perform the add. If it is not valid,
7865 we use a two insn sequence.
7867 Or we can be asked to reload an unary operand that was a fragment of
7868 an addressing mode, into a register. If it isn't recognized as-is,
7869 we try making the unop operand and the reload-register the same:
7870 (set reg:X (unop:X expr:Y))
7871 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7873 Finally, we could be called to handle an 'o' constraint by putting
7874 an address into a register. In that case, we first try to do this
7875 with a named pattern of "reload_load_address". If no such pattern
7876 exists, we just emit a SET insn and hope for the best (it will normally
7877 be valid on machines that use 'o').
7879 This entire process is made complex because reload will never
7880 process the insns we generate here and so we must ensure that
7881 they will fit their constraints and also by the fact that parts of
7882 IN might be being reloaded separately and replaced with spill registers.
7883 Because of this, we are, in some sense, just guessing the right approach
7884 here. The one listed above seems to work.
7886 ??? At some point, this whole thing needs to be rethought. */
7888 if (GET_CODE (in) == PLUS
7889 && (REG_P (XEXP (in, 0))
7890 || GET_CODE (XEXP (in, 0)) == SUBREG
7891 || MEM_P (XEXP (in, 0)))
7892 && (REG_P (XEXP (in, 1))
7893 || GET_CODE (XEXP (in, 1)) == SUBREG
7894 || CONSTANT_P (XEXP (in, 1))
7895 || MEM_P (XEXP (in, 1))))
7897 /* We need to compute the sum of a register or a MEM and another
7898 register, constant, or MEM, and put it into the reload
7899 register. The best possible way of doing this is if the machine
7900 has a three-operand ADD insn that accepts the required operands.
7902 The simplest approach is to try to generate such an insn and see if it
7903 is recognized and matches its constraints. If so, it can be used.
7905 It might be better not to actually emit the insn unless it is valid,
7906 but we need to pass the insn as an operand to `recog' and
7907 `extract_insn' and it is simpler to emit and then delete the insn if
7908 not valid than to dummy things up. */
7910 rtx op0, op1, tem, insn;
7913 op0 = find_replacement (&XEXP (in, 0));
7914 op1 = find_replacement (&XEXP (in, 1));
7916 /* Since constraint checking is strict, commutativity won't be
7917 checked, so we need to do that here to avoid spurious failure
7918 if the add instruction is two-address and the second operand
7919 of the add is the same as the reload reg, which is frequently
7920 the case. If the insn would be A = B + A, rearrange it so
7921 it will be A = A + B as constrain_operands expects. */
7923 if (REG_P (XEXP (in, 1))
7924 && REGNO (out) == REGNO (XEXP (in, 1)))
7925 tem = op0, op0 = op1, op1 = tem;
7927 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7928 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7930 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7934 /* If that failed, we must use a conservative two-insn sequence.
7936 Use a move to copy one operand into the reload register. Prefer
7937 to reload a constant, MEM or pseudo since the move patterns can
7938 handle an arbitrary operand. If OP1 is not a constant, MEM or
7939 pseudo and OP1 is not a valid operand for an add instruction, then
7942 After reloading one of the operands into the reload register, add
7943 the reload register to the output register.
7945 If there is another way to do this for a specific machine, a
7946 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7949 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7951 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7953 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7954 || (code != CODE_FOR_nothing
7955 && ! ((*insn_data[code].operand[2].predicate)
7956 (op1, insn_data[code].operand[2].mode))))
7957 tem = op0, op0 = op1, op1 = tem;
7959 gen_reload (out, op0, opnum, type);
7961 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7962 This fixes a problem on the 32K where the stack pointer cannot
7963 be used as an operand of an add insn. */
7965 if (rtx_equal_p (op0, op1))
7968 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7971 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7972 set_unique_reg_note (insn, REG_EQUIV, in);
7976 /* If that failed, copy the address register to the reload register.
7977 Then add the constant to the reload register. */
7979 gcc_assert (!reg_overlap_mentioned_p (out, op0));
7980 gen_reload (out, op1, opnum, type);
7981 insn = emit_insn (gen_add2_insn (out, op0));
7982 set_unique_reg_note (insn, REG_EQUIV, in);
7985 #ifdef SECONDARY_MEMORY_NEEDED
7986 /* If we need a memory location to do the move, do it that way. */
7987 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7988 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7989 && (REG_P (out) || GET_CODE (out) == SUBREG)
7990 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7991 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7992 REGNO_REG_CLASS (reg_or_subregno (out)),
7995 /* Get the memory to use and rewrite both registers to its mode. */
7996 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7998 if (GET_MODE (loc) != GET_MODE (out))
7999 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8001 if (GET_MODE (loc) != GET_MODE (in))
8002 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8004 gen_reload (loc, in, opnum, type);
8005 gen_reload (out, loc, opnum, type);
8008 else if (REG_P (out) && UNARY_P (in))
8015 op1 = find_replacement (&XEXP (in, 0));
8016 if (op1 != XEXP (in, 0))
8017 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8019 /* First, try a plain SET. */
8020 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8024 /* If that failed, move the inner operand to the reload
8025 register, and try the same unop with the inner expression
8026 replaced with the reload register. */
8028 if (GET_MODE (op1) != GET_MODE (out))
8029 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8033 gen_reload (out_moded, op1, opnum, type);
8036 = gen_rtx_SET (VOIDmode, out,
8037 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8039 insn = emit_insn_if_valid_for_reload (insn);
8042 set_unique_reg_note (insn, REG_EQUIV, in);
8046 fatal_insn ("Failure trying to reload:", set);
8048 /* If IN is a simple operand, use gen_move_insn. */
8049 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8051 tem = emit_insn (gen_move_insn (out, in));
8052 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
8053 mark_jump_label (in, tem, 0);
8056 #ifdef HAVE_reload_load_address
8057 else if (HAVE_reload_load_address)
8058 emit_insn (gen_reload_load_address (out, in));
8061 /* Otherwise, just write (set OUT IN) and hope for the best. */
8063 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8065 /* Return the first insn emitted.
8066 We can not just return get_last_insn, because there may have
8067 been multiple instructions emitted. Also note that gen_move_insn may
8068 emit more than one insn itself, so we can not assume that there is one
8069 insn emitted per emit_insn_before call. */
8071 return last ? NEXT_INSN (last) : get_insns ();
8074 /* Delete a previously made output-reload whose result we now believe
8075 is not needed. First we double-check.
8077 INSN is the insn now being processed.
8078 LAST_RELOAD_REG is the hard register number for which we want to delete
8079 the last output reload.
8080 J is the reload-number that originally used REG. The caller has made
8081 certain that reload J doesn't use REG any longer for input. */
8084 delete_output_reload (rtx insn, int j, int last_reload_reg)
8086 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8087 rtx reg = spill_reg_stored_to[last_reload_reg];
8090 int n_inherited = 0;
8094 /* It is possible that this reload has been only used to set another reload
8095 we eliminated earlier and thus deleted this instruction too. */
8096 if (INSN_DELETED_P (output_reload_insn))
8099 /* Get the raw pseudo-register referred to. */
8101 while (GET_CODE (reg) == SUBREG)
8102 reg = SUBREG_REG (reg);
8103 substed = reg_equiv_memory_loc[REGNO (reg)];
8105 /* This is unsafe if the operand occurs more often in the current
8106 insn than it is inherited. */
8107 for (k = n_reloads - 1; k >= 0; k--)
8109 rtx reg2 = rld[k].in;
8112 if (MEM_P (reg2) || reload_override_in[k])
8113 reg2 = rld[k].in_reg;
8115 if (rld[k].out && ! rld[k].out_reg)
8116 reg2 = XEXP (rld[k].in_reg, 0);
8118 while (GET_CODE (reg2) == SUBREG)
8119 reg2 = SUBREG_REG (reg2);
8120 if (rtx_equal_p (reg2, reg))
8122 if (reload_inherited[k] || reload_override_in[k] || k == j)
8128 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8129 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8130 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8133 n_occurrences += count_occurrences (PATTERN (insn),
8134 eliminate_regs (substed, 0,
8136 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8138 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8139 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8141 if (n_occurrences > n_inherited)
8144 /* If the pseudo-reg we are reloading is no longer referenced
8145 anywhere between the store into it and here,
8146 and we're within the same basic block, then the value can only
8147 pass through the reload reg and end up here.
8148 Otherwise, give up--return. */
8149 for (i1 = NEXT_INSN (output_reload_insn);
8150 i1 != insn; i1 = NEXT_INSN (i1))
8152 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8154 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8155 && reg_mentioned_p (reg, PATTERN (i1)))
8157 /* If this is USE in front of INSN, we only have to check that
8158 there are no more references than accounted for by inheritance. */
8159 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8161 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8162 i1 = NEXT_INSN (i1);
8164 if (n_occurrences <= n_inherited && i1 == insn)
8170 /* We will be deleting the insn. Remove the spill reg information. */
8171 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8173 spill_reg_store[last_reload_reg + k] = 0;
8174 spill_reg_stored_to[last_reload_reg + k] = 0;
8177 /* The caller has already checked that REG dies or is set in INSN.
8178 It has also checked that we are optimizing, and thus some
8179 inaccuracies in the debugging information are acceptable.
8180 So we could just delete output_reload_insn. But in some cases
8181 we can improve the debugging information without sacrificing
8182 optimization - maybe even improving the code: See if the pseudo
8183 reg has been completely replaced with reload regs. If so, delete
8184 the store insn and forget we had a stack slot for the pseudo. */
8185 if (rld[j].out != rld[j].in
8186 && REG_N_DEATHS (REGNO (reg)) == 1
8187 && REG_N_SETS (REGNO (reg)) == 1
8188 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8189 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8193 /* We know that it was used only between here and the beginning of
8194 the current basic block. (We also know that the last use before
8195 INSN was the output reload we are thinking of deleting, but never
8196 mind that.) Search that range; see if any ref remains. */
8197 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8199 rtx set = single_set (i2);
8201 /* Uses which just store in the pseudo don't count,
8202 since if they are the only uses, they are dead. */
8203 if (set != 0 && SET_DEST (set) == reg)
8208 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8209 && reg_mentioned_p (reg, PATTERN (i2)))
8211 /* Some other ref remains; just delete the output reload we
8213 delete_address_reloads (output_reload_insn, insn);
8214 delete_insn (output_reload_insn);
8219 /* Delete the now-dead stores into this pseudo. Note that this
8220 loop also takes care of deleting output_reload_insn. */
8221 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8223 rtx set = single_set (i2);
8225 if (set != 0 && SET_DEST (set) == reg)
8227 delete_address_reloads (i2, insn);
8235 /* For the debugging info, say the pseudo lives in this reload reg. */
8236 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8237 alter_reg (REGNO (reg), -1);
8241 delete_address_reloads (output_reload_insn, insn);
8242 delete_insn (output_reload_insn);
8246 /* We are going to delete DEAD_INSN. Recursively delete loads of
8247 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8248 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8250 delete_address_reloads (rtx dead_insn, rtx current_insn)
8252 rtx set = single_set (dead_insn);
8253 rtx set2, dst, prev, next;
8256 rtx dst = SET_DEST (set);
8258 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8260 /* If we deleted the store from a reloaded post_{in,de}c expression,
8261 we can delete the matching adds. */
8262 prev = PREV_INSN (dead_insn);
8263 next = NEXT_INSN (dead_insn);
8264 if (! prev || ! next)
8266 set = single_set (next);
8267 set2 = single_set (prev);
8269 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8270 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8271 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8273 dst = SET_DEST (set);
8274 if (! rtx_equal_p (dst, SET_DEST (set2))
8275 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8276 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8277 || (INTVAL (XEXP (SET_SRC (set), 1))
8278 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8280 delete_related_insns (prev);
8281 delete_related_insns (next);
8284 /* Subfunction of delete_address_reloads: process registers found in X. */
8286 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8288 rtx prev, set, dst, i2;
8290 enum rtx_code code = GET_CODE (x);
8294 const char *fmt = GET_RTX_FORMAT (code);
8295 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8298 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8299 else if (fmt[i] == 'E')
8301 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8302 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8309 if (spill_reg_order[REGNO (x)] < 0)
8312 /* Scan backwards for the insn that sets x. This might be a way back due
8314 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8316 code = GET_CODE (prev);
8317 if (code == CODE_LABEL || code == JUMP_INSN)
8321 if (reg_set_p (x, PATTERN (prev)))
8323 if (reg_referenced_p (x, PATTERN (prev)))
8326 if (! prev || INSN_UID (prev) < reload_first_uid)
8328 /* Check that PREV only sets the reload register. */
8329 set = single_set (prev);
8332 dst = SET_DEST (set);
8334 || ! rtx_equal_p (dst, x))
8336 if (! reg_set_p (dst, PATTERN (dead_insn)))
8338 /* Check if DST was used in a later insn -
8339 it might have been inherited. */
8340 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8346 if (reg_referenced_p (dst, PATTERN (i2)))
8348 /* If there is a reference to the register in the current insn,
8349 it might be loaded in a non-inherited reload. If no other
8350 reload uses it, that means the register is set before
8352 if (i2 == current_insn)
8354 for (j = n_reloads - 1; j >= 0; j--)
8355 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8356 || reload_override_in[j] == dst)
8358 for (j = n_reloads - 1; j >= 0; j--)
8359 if (rld[j].in && rld[j].reg_rtx == dst)
8368 /* If DST is still live at CURRENT_INSN, check if it is used for
8369 any reload. Note that even if CURRENT_INSN sets DST, we still
8370 have to check the reloads. */
8371 if (i2 == current_insn)
8373 for (j = n_reloads - 1; j >= 0; j--)
8374 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8375 || reload_override_in[j] == dst)
8377 /* ??? We can't finish the loop here, because dst might be
8378 allocated to a pseudo in this block if no reload in this
8379 block needs any of the classes containing DST - see
8380 spill_hard_reg. There is no easy way to tell this, so we
8381 have to scan till the end of the basic block. */
8383 if (reg_set_p (dst, PATTERN (i2)))
8387 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8388 reg_reloaded_contents[REGNO (dst)] = -1;
8392 /* Output reload-insns to reload VALUE into RELOADREG.
8393 VALUE is an autoincrement or autodecrement RTX whose operand
8394 is a register or memory location;
8395 so reloading involves incrementing that location.
8396 IN is either identical to VALUE, or some cheaper place to reload from.
8398 INC_AMOUNT is the number to increment or decrement by (always positive).
8399 This cannot be deduced from VALUE.
8401 Return the instruction that stores into RELOADREG. */
8404 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8406 /* REG or MEM to be copied and incremented. */
8407 rtx incloc = find_replacement (&XEXP (value, 0));
8408 /* Nonzero if increment after copying. */
8409 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8410 || GET_CODE (value) == POST_MODIFY);
8416 rtx real_in = in == value ? incloc : in;
8418 /* No hard register is equivalent to this register after
8419 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8420 we could inc/dec that register as well (maybe even using it for
8421 the source), but I'm not sure it's worth worrying about. */
8423 reg_last_reload_reg[REGNO (incloc)] = 0;
8425 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8427 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8428 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8432 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8433 inc_amount = -inc_amount;
8435 inc = GEN_INT (inc_amount);
8438 /* If this is post-increment, first copy the location to the reload reg. */
8439 if (post && real_in != reloadreg)
8440 emit_insn (gen_move_insn (reloadreg, real_in));
8444 /* See if we can directly increment INCLOC. Use a method similar to
8445 that in gen_reload. */
8447 last = get_last_insn ();
8448 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8449 gen_rtx_PLUS (GET_MODE (incloc),
8452 code = recog_memoized (add_insn);
8455 extract_insn (add_insn);
8456 if (constrain_operands (1))
8458 /* If this is a pre-increment and we have incremented the value
8459 where it lives, copy the incremented value to RELOADREG to
8460 be used as an address. */
8463 emit_insn (gen_move_insn (reloadreg, incloc));
8468 delete_insns_since (last);
8471 /* If couldn't do the increment directly, must increment in RELOADREG.
8472 The way we do this depends on whether this is pre- or post-increment.
8473 For pre-increment, copy INCLOC to the reload register, increment it
8474 there, then save back. */
8478 if (in != reloadreg)
8479 emit_insn (gen_move_insn (reloadreg, real_in));
8480 emit_insn (gen_add2_insn (reloadreg, inc));
8481 store = emit_insn (gen_move_insn (incloc, reloadreg));
8486 Because this might be a jump insn or a compare, and because RELOADREG
8487 may not be available after the insn in an input reload, we must do
8488 the incrementation before the insn being reloaded for.
8490 We have already copied IN to RELOADREG. Increment the copy in
8491 RELOADREG, save that back, then decrement RELOADREG so it has
8492 the original value. */
8494 emit_insn (gen_add2_insn (reloadreg, inc));
8495 store = emit_insn (gen_move_insn (incloc, reloadreg));
8496 if (GET_CODE (inc) == CONST_INT)
8497 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8499 emit_insn (gen_sub2_insn (reloadreg, inc));
8507 add_auto_inc_notes (rtx insn, rtx x)
8509 enum rtx_code code = GET_CODE (x);
8513 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8516 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8520 /* Scan all the operand sub-expressions. */
8521 fmt = GET_RTX_FORMAT (code);
8522 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8525 add_auto_inc_notes (insn, XEXP (x, i));
8526 else if (fmt[i] == 'E')
8527 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8528 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8533 /* Copy EH notes from an insn to its reloads. */
8535 copy_eh_notes (rtx insn, rtx x)
8537 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8540 for (; x != 0; x = NEXT_INSN (x))
8542 if (may_trap_p (PATTERN (x)))
8544 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8550 /* This is used by reload pass, that does emit some instructions after
8551 abnormal calls moving basic block end, but in fact it wants to emit
8552 them on the edge. Looks for abnormal call edges, find backward the
8553 proper call and fix the damage.
8555 Similar handle instructions throwing exceptions internally. */
8557 fixup_abnormal_edges (void)
8559 bool inserted = false;
8567 /* Look for cases we are interested in - calls or instructions causing
8569 FOR_EACH_EDGE (e, ei, bb->succs)
8571 if (e->flags & EDGE_ABNORMAL_CALL)
8573 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8574 == (EDGE_ABNORMAL | EDGE_EH))
8577 if (e && !CALL_P (BB_END (bb))
8578 && !can_throw_internal (BB_END (bb)))
8582 /* Get past the new insns generated. Allow notes, as the insns
8583 may be already deleted. */
8585 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8586 && !can_throw_internal (insn)
8587 && insn != BB_HEAD (bb))
8588 insn = PREV_INSN (insn);
8590 if (CALL_P (insn) || can_throw_internal (insn))
8594 stop = NEXT_INSN (BB_END (bb));
8596 insn = NEXT_INSN (insn);
8598 FOR_EACH_EDGE (e, ei, bb->succs)
8599 if (e->flags & EDGE_FALLTHRU)
8602 while (insn && insn != stop)
8604 next = NEXT_INSN (insn);
8609 /* Sometimes there's still the return value USE.
8610 If it's placed after a trapping call (i.e. that
8611 call is the last insn anyway), we have no fallthru
8612 edge. Simply delete this use and don't try to insert
8613 on the non-existent edge. */
8614 if (GET_CODE (PATTERN (insn)) != USE)
8616 /* We're not deleting it, we're moving it. */
8617 INSN_DELETED_P (insn) = 0;
8618 PREV_INSN (insn) = NULL_RTX;
8619 NEXT_INSN (insn) = NULL_RTX;
8621 insert_insn_on_edge (insn, e);
8625 else if (!BARRIER_P (insn))
8626 set_block_for_insn (insn, NULL);
8631 /* It may be that we don't find any such trapping insn. In this
8632 case we discovered quite late that the insn that had been
8633 marked as can_throw_internal in fact couldn't trap at all.
8634 So we should in fact delete the EH edges out of the block. */
8636 purge_dead_edges (bb);
8640 /* We've possibly turned single trapping insn into multiple ones. */
8641 if (flag_non_call_exceptions)
8644 blocks = sbitmap_alloc (last_basic_block);
8645 sbitmap_ones (blocks);
8646 find_many_sub_basic_blocks (blocks);
8647 sbitmap_free (blocks);
8651 commit_edge_insertions ();
8653 #ifdef ENABLE_CHECKING
8654 /* Verify that we didn't turn one trapping insn into many, and that
8655 we found and corrected all of the problems wrt fixups on the
8657 verify_flow_info ();
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