1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
161 call-saved. This is only meaningful for members of reg_reloaded_valid. */
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int, rtx);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass. This is called at the beginning of compilation
451 and may be called again if the target is reinitialized. */
458 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
459 Set spill_indirect_levels to the number of levels such addressing is
460 permitted, zero if it is not permitted at all. */
463 = gen_rtx_MEM (Pmode,
466 LAST_VIRTUAL_REGISTER + 1),
468 spill_indirect_levels = 0;
470 while (memory_address_p (QImode, tem))
472 spill_indirect_levels++;
473 tem = gen_rtx_MEM (Pmode, tem);
476 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
478 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
479 indirect_symref_ok = memory_address_p (QImode, tem);
481 /* See if reg+reg is a valid (and offsettable) address. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
485 tem = gen_rtx_PLUS (Pmode,
486 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
487 gen_rtx_REG (Pmode, i));
489 /* This way, we make sure that reg+reg is an offsettable address. */
490 tem = plus_constant (tem, 4);
492 if (memory_address_p (QImode, tem))
494 double_reg_address_ok = 1;
499 /* Initialize obstack for our rtl allocation. */
500 gcc_obstack_init (&reload_obstack);
501 reload_startobj = obstack_alloc (&reload_obstack, 0);
503 INIT_REG_SET (&spilled_pseudos);
504 INIT_REG_SET (&pseudos_counted);
507 /* List of insn chains that are currently unused. */
508 static struct insn_chain *unused_insn_chains = 0;
510 /* Allocate an empty insn_chain structure. */
512 new_insn_chain (void)
514 struct insn_chain *c;
516 if (unused_insn_chains == 0)
518 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
519 INIT_REG_SET (&c->live_throughout);
520 INIT_REG_SET (&c->dead_or_set);
524 c = unused_insn_chains;
525 unused_insn_chains = c->next;
527 c->is_caller_save_insn = 0;
528 c->need_operand_change = 0;
534 /* Small utility function to set all regs in hard reg set TO which are
535 allocated to pseudos in regset FROM. */
538 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
541 reg_set_iterator rsi;
543 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
545 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 DF_LIVE_IN (BASIC_BLOCK), which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
556 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
560 /* Replace all pseudos found in LOC with their corresponding
564 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
577 unsigned int regno = REGNO (x);
579 if (regno < FIRST_PSEUDO_REGISTER)
582 x = eliminate_regs (x, mem_mode, usage);
586 replace_pseudos_in (loc, mem_mode, usage);
590 if (reg_equiv_constant[regno])
591 *loc = reg_equiv_constant[regno];
592 else if (reg_equiv_mem[regno])
593 *loc = reg_equiv_mem[regno];
594 else if (reg_equiv_address[regno])
595 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
598 gcc_assert (!REG_P (regno_reg_rtx[regno])
599 || REGNO (regno_reg_rtx[regno]) != regno);
600 *loc = regno_reg_rtx[regno];
605 else if (code == MEM)
607 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
611 /* Process each of our operands recursively. */
612 fmt = GET_RTX_FORMAT (code);
613 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
615 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
616 else if (*fmt == 'E')
617 for (j = 0; j < XVECLEN (x, i); j++)
618 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Determine if the current function has an exception receiver block
622 that reaches the exit block via non-exceptional edges */
625 has_nonexceptional_receiver (void)
629 basic_block *tos, *worklist, bb;
631 /* If we're not optimizing, then just err on the safe side. */
635 /* First determine which blocks can reach exit via normal paths. */
636 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
639 bb->flags &= ~BB_REACHABLE;
641 /* Place the exit block on our worklist. */
642 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
643 *tos++ = EXIT_BLOCK_PTR;
645 /* Iterate: find everything reachable from what we've already seen. */
646 while (tos != worklist)
650 FOR_EACH_EDGE (e, ei, bb->preds)
651 if (!(e->flags & EDGE_ABNORMAL))
653 basic_block src = e->src;
655 if (!(src->flags & BB_REACHABLE))
657 src->flags |= BB_REACHABLE;
664 /* Now see if there's a reachable block with an exceptional incoming
667 if (bb->flags & BB_REACHABLE)
668 FOR_EACH_EDGE (e, ei, bb->preds)
669 if (e->flags & EDGE_ABNORMAL)
672 /* No exceptional block reached exit unexceptionally. */
677 /* Global variables used by reload and its subroutines. */
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed;
684 /* Nonzero means we couldn't get enough spill regs. */
687 /* Main entry point for the reload pass.
689 FIRST is the first insn of the function being compiled.
691 GLOBAL nonzero means we were called from global_alloc
692 and should attempt to reallocate any pseudoregs that we
693 displace from hard regs we will use for reloads.
694 If GLOBAL is zero, we do not have enough information to do that,
695 so any pseudo reg that is spilled must go to the stack.
697 Return value is nonzero if reload failed
698 and we must not do any more for this function. */
701 reload (rtx first, int global)
705 struct elim_table *ep;
708 /* Make sure even insns with volatile mem refs are recognizable. */
713 reload_firstobj = obstack_alloc (&reload_obstack, 0);
715 /* Make sure that the last insn in the chain
716 is not something that needs reloading. */
717 emit_note (NOTE_INSN_DELETED);
719 /* Enable find_equiv_reg to distinguish insns made by reload. */
720 reload_first_uid = get_max_uid ();
722 #ifdef SECONDARY_MEMORY_NEEDED
723 /* Initialize the secondary memory table. */
724 clear_secondary_mem ();
727 /* We don't have a stack slot for any spill reg yet. */
728 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
729 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
731 /* Initialize the save area information for caller-save, in case some
735 /* Compute which hard registers are now in use
736 as homes for pseudo registers.
737 This is done here rather than (eg) in global_alloc
738 because this point is reached even if not optimizing. */
739 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
742 /* A function that has a nonlocal label that can reach the exit
743 block via non-exceptional paths must save all call-saved
745 if (cfun->has_nonlocal_label
746 && has_nonexceptional_receiver ())
747 crtl->saves_all_registers = 1;
749 if (crtl->saves_all_registers)
750 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
751 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
752 df_set_regs_ever_live (i, true);
754 /* Find all the pseudo registers that didn't get hard regs
755 but do have known equivalent constants or memory slots.
756 These include parameters (known equivalent to parameter slots)
757 and cse'd or loop-moved constant memory addresses.
759 Record constant equivalents in reg_equiv_constant
760 so they will be substituted by find_reloads.
761 Record memory equivalents in reg_mem_equiv so they can
762 be substituted eventually by altering the REG-rtx's. */
764 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
765 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
766 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
767 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
768 reg_equiv_address = XCNEWVEC (rtx, max_regno);
769 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
770 reg_old_renumber = XCNEWVEC (short, max_regno);
771 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
772 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
773 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
775 CLEAR_HARD_REG_SET (bad_spill_regs_global);
777 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
778 to. Also find all paradoxical subregs and find largest such for
781 num_eliminable_invariants = 0;
782 for (insn = first; insn; insn = NEXT_INSN (insn))
784 rtx set = single_set (insn);
786 /* We may introduce USEs that we want to remove at the end, so
787 we'll mark them with QImode. Make sure there are no
788 previously-marked insns left by say regmove. */
789 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
790 && GET_MODE (insn) != VOIDmode)
791 PUT_MODE (insn, VOIDmode);
794 scan_paradoxical_subregs (PATTERN (insn));
796 if (set != 0 && REG_P (SET_DEST (set)))
798 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
804 i = REGNO (SET_DEST (set));
807 if (i <= LAST_VIRTUAL_REGISTER)
810 if (! function_invariant_p (x)
812 /* A function invariant is often CONSTANT_P but may
813 include a register. We promise to only pass
814 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
816 && LEGITIMATE_PIC_OPERAND_P (x)))
818 /* It can happen that a REG_EQUIV note contains a MEM
819 that is not a legitimate memory operand. As later
820 stages of reload assume that all addresses found
821 in the reg_equiv_* arrays were originally legitimate,
822 we ignore such REG_EQUIV notes. */
823 if (memory_operand (x, VOIDmode))
825 /* Always unshare the equivalence, so we can
826 substitute into this insn without touching the
828 reg_equiv_memory_loc[i] = copy_rtx (x);
830 else if (function_invariant_p (x))
832 if (GET_CODE (x) == PLUS)
834 /* This is PLUS of frame pointer and a constant,
835 and might be shared. Unshare it. */
836 reg_equiv_invariant[i] = copy_rtx (x);
837 num_eliminable_invariants++;
839 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
841 reg_equiv_invariant[i] = x;
842 num_eliminable_invariants++;
844 else if (LEGITIMATE_CONSTANT_P (x))
845 reg_equiv_constant[i] = x;
848 reg_equiv_memory_loc[i]
849 = force_const_mem (GET_MODE (SET_DEST (set)), x);
850 if (! reg_equiv_memory_loc[i])
851 reg_equiv_init[i] = NULL_RTX;
856 reg_equiv_init[i] = NULL_RTX;
861 reg_equiv_init[i] = NULL_RTX;
866 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
867 if (reg_equiv_init[i])
869 fprintf (dump_file, "init_insns for %u: ", i);
870 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
871 fprintf (dump_file, "\n");
876 first_label_num = get_first_label_num ();
877 num_labels = max_label_num () - first_label_num;
879 /* Allocate the tables used to store offset information at labels. */
880 /* We used to use alloca here, but the size of what it would try to
881 allocate would occasionally cause it to exceed the stack limit and
882 cause a core dump. */
883 offsets_known_at = XNEWVEC (char, num_labels);
884 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
886 /* Alter each pseudo-reg rtx to contain its hard reg number.
887 Assign stack slots to the pseudos that lack hard regs or equivalents.
888 Do not touch virtual registers. */
890 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
893 /* If we have some registers we think can be eliminated, scan all insns to
894 see if there is an insn that sets one of these registers to something
895 other than itself plus a constant. If so, the register cannot be
896 eliminated. Doing this scan here eliminates an extra pass through the
897 main reload loop in the most common case where register elimination
899 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
901 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
903 maybe_fix_stack_asms ();
905 insns_need_reload = 0;
906 something_needs_elimination = 0;
908 /* Initialize to -1, which means take the first spill register. */
911 /* Spill any hard regs that we know we can't eliminate. */
912 CLEAR_HARD_REG_SET (used_spill_regs);
913 /* There can be multiple ways to eliminate a register;
914 they should be listed adjacently.
915 Elimination for any register fails only if all possible ways fail. */
916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
919 int can_eliminate = 0;
922 can_eliminate |= ep->can_eliminate;
925 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
927 spill_hard_reg (from, 1);
930 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
931 if (frame_pointer_needed)
932 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
934 finish_spills (global);
936 /* From now on, we may need to generate moves differently. We may also
937 allow modifications of insns which cause them to not be recognized.
938 Any such modifications will be cleaned up during reload itself. */
939 reload_in_progress = 1;
941 /* This loop scans the entire function each go-round
942 and repeats until one repetition spills no additional hard regs. */
945 int something_changed;
947 HOST_WIDE_INT starting_frame_size;
949 starting_frame_size = get_frame_size ();
951 set_initial_elim_offsets ();
952 set_initial_label_offsets ();
954 /* For each pseudo register that has an equivalent location defined,
955 try to eliminate any eliminable registers (such as the frame pointer)
956 assuming initial offsets for the replacement register, which
959 If the resulting location is directly addressable, substitute
960 the MEM we just got directly for the old REG.
962 If it is not addressable but is a constant or the sum of a hard reg
963 and constant, it is probably not addressable because the constant is
964 out of range, in that case record the address; we will generate
965 hairy code to compute the address in a register each time it is
966 needed. Similarly if it is a hard register, but one that is not
967 valid as an address register.
969 If the location is not addressable, but does not have one of the
970 above forms, assign a stack slot. We have to do this to avoid the
971 potential of producing lots of reloads if, e.g., a location involves
972 a pseudo that didn't get a hard register and has an equivalent memory
973 location that also involves a pseudo that didn't get a hard register.
975 Perhaps at some point we will improve reload_when_needed handling
976 so this problem goes away. But that's very hairy. */
978 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
979 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
981 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
983 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
985 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
986 else if (CONSTANT_P (XEXP (x, 0))
987 || (REG_P (XEXP (x, 0))
988 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
989 || (GET_CODE (XEXP (x, 0)) == PLUS
990 && REG_P (XEXP (XEXP (x, 0), 0))
991 && (REGNO (XEXP (XEXP (x, 0), 0))
992 < FIRST_PSEUDO_REGISTER)
993 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
994 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
997 /* Make a new stack slot. Then indicate that something
998 changed so we go back and recompute offsets for
999 eliminable registers because the allocation of memory
1000 below might change some offset. reg_equiv_{mem,address}
1001 will be set up for this pseudo on the next pass around
1003 reg_equiv_memory_loc[i] = 0;
1004 reg_equiv_init[i] = 0;
1009 if (caller_save_needed)
1010 setup_save_areas ();
1012 /* If we allocated another stack slot, redo elimination bookkeeping. */
1013 if (starting_frame_size != get_frame_size ())
1015 if (starting_frame_size && crtl->stack_alignment_needed)
1017 /* If we have a stack frame, we must align it now. The
1018 stack size may be a part of the offset computation for
1019 register elimination. So if this changes the stack size,
1020 then repeat the elimination bookkeeping. We don't
1021 realign when there is no stack, as that will cause a
1022 stack frame when none is needed should
1023 STARTING_FRAME_OFFSET not be already aligned to
1025 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1026 if (starting_frame_size != get_frame_size ())
1030 if (caller_save_needed)
1032 save_call_clobbered_regs ();
1033 /* That might have allocated new insn_chain structures. */
1034 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1037 calculate_needs_all_insns (global);
1039 CLEAR_REG_SET (&spilled_pseudos);
1042 something_changed = 0;
1044 /* If we allocated any new memory locations, make another pass
1045 since it might have changed elimination offsets. */
1046 if (starting_frame_size != get_frame_size ())
1047 something_changed = 1;
1049 /* Even if the frame size remained the same, we might still have
1050 changed elimination offsets, e.g. if find_reloads called
1051 force_const_mem requiring the back end to allocate a constant
1052 pool base register that needs to be saved on the stack. */
1053 else if (!verify_initial_elim_offsets ())
1054 something_changed = 1;
1057 HARD_REG_SET to_spill;
1058 CLEAR_HARD_REG_SET (to_spill);
1059 update_eliminables (&to_spill);
1060 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1062 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1063 if (TEST_HARD_REG_BIT (to_spill, i))
1065 spill_hard_reg (i, 1);
1068 /* Regardless of the state of spills, if we previously had
1069 a register that we thought we could eliminate, but now can
1070 not eliminate, we must run another pass.
1072 Consider pseudos which have an entry in reg_equiv_* which
1073 reference an eliminable register. We must make another pass
1074 to update reg_equiv_* so that we do not substitute in the
1075 old value from when we thought the elimination could be
1077 something_changed = 1;
1081 select_reload_regs ();
1085 if (insns_need_reload != 0 || did_spill)
1086 something_changed |= finish_spills (global);
1088 if (! something_changed)
1091 if (caller_save_needed)
1092 delete_caller_save_insns ();
1094 obstack_free (&reload_obstack, reload_firstobj);
1097 /* If global-alloc was run, notify it of any register eliminations we have
1100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1101 if (ep->can_eliminate)
1102 mark_elimination (ep->from, ep->to);
1104 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1105 If that insn didn't set the register (i.e., it copied the register to
1106 memory), just delete that insn instead of the equivalencing insn plus
1107 anything now dead. If we call delete_dead_insn on that insn, we may
1108 delete the insn that actually sets the register if the register dies
1109 there and that is incorrect. */
1111 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1113 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1116 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1118 rtx equiv_insn = XEXP (list, 0);
1120 /* If we already deleted the insn or if it may trap, we can't
1121 delete it. The latter case shouldn't happen, but can
1122 if an insn has a variable address, gets a REG_EH_REGION
1123 note added to it, and then gets converted into a load
1124 from a constant address. */
1125 if (NOTE_P (equiv_insn)
1126 || can_throw_internal (equiv_insn))
1128 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1129 delete_dead_insn (equiv_insn);
1131 SET_INSN_DELETED (equiv_insn);
1136 /* Use the reload registers where necessary
1137 by generating move instructions to move the must-be-register
1138 values into or out of the reload registers. */
1140 if (insns_need_reload != 0 || something_needs_elimination
1141 || something_needs_operands_changed)
1143 HOST_WIDE_INT old_frame_size = get_frame_size ();
1145 reload_as_needed (global);
1147 gcc_assert (old_frame_size == get_frame_size ());
1149 gcc_assert (verify_initial_elim_offsets ());
1152 /* If we were able to eliminate the frame pointer, show that it is no
1153 longer live at the start of any basic block. If it ls live by
1154 virtue of being in a pseudo, that pseudo will be marked live
1155 and hence the frame pointer will be known to be live via that
1158 if (! frame_pointer_needed)
1160 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1162 /* Come here (with failure set nonzero) if we can't get enough spill
1166 CLEAR_REG_SET (&spilled_pseudos);
1167 reload_in_progress = 0;
1169 /* Now eliminate all pseudo regs by modifying them into
1170 their equivalent memory references.
1171 The REG-rtx's for the pseudos are modified in place,
1172 so all insns that used to refer to them now refer to memory.
1174 For a reg that has a reg_equiv_address, all those insns
1175 were changed by reloading so that no insns refer to it any longer;
1176 but the DECL_RTL of a variable decl may refer to it,
1177 and if so this causes the debugging info to mention the variable. */
1179 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1183 if (reg_equiv_mem[i])
1184 addr = XEXP (reg_equiv_mem[i], 0);
1186 if (reg_equiv_address[i])
1187 addr = reg_equiv_address[i];
1191 if (reg_renumber[i] < 0)
1193 rtx reg = regno_reg_rtx[i];
1195 REG_USERVAR_P (reg) = 0;
1196 PUT_CODE (reg, MEM);
1197 XEXP (reg, 0) = addr;
1198 if (reg_equiv_memory_loc[i])
1199 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1202 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1203 MEM_ATTRS (reg) = 0;
1205 MEM_NOTRAP_P (reg) = 1;
1207 else if (reg_equiv_mem[i])
1208 XEXP (reg_equiv_mem[i], 0) = addr;
1212 /* We must set reload_completed now since the cleanup_subreg_operands call
1213 below will re-recognize each insn and reload may have generated insns
1214 which are only valid during and after reload. */
1215 reload_completed = 1;
1217 /* Make a pass over all the insns and delete all USEs which we inserted
1218 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1219 notes. Delete all CLOBBER insns, except those that refer to the return
1220 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1221 from misarranging variable-array code, and simplify (subreg (reg))
1222 operands. Strip and regenerate REG_INC notes that may have been moved
1225 for (insn = first; insn; insn = NEXT_INSN (insn))
1231 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1232 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1234 if ((GET_CODE (PATTERN (insn)) == USE
1235 /* We mark with QImode USEs introduced by reload itself. */
1236 && (GET_MODE (insn) == QImode
1237 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1238 || (GET_CODE (PATTERN (insn)) == CLOBBER
1239 && (!MEM_P (XEXP (PATTERN (insn), 0))
1240 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1241 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1242 && XEXP (XEXP (PATTERN (insn), 0), 0)
1243 != stack_pointer_rtx))
1244 && (!REG_P (XEXP (PATTERN (insn), 0))
1245 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1251 /* Some CLOBBERs may survive until here and still reference unassigned
1252 pseudos with const equivalent, which may in turn cause ICE in later
1253 passes if the reference remains in place. */
1254 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1255 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1256 VOIDmode, PATTERN (insn));
1258 /* Discard obvious no-ops, even without -O. This optimization
1259 is fast and doesn't interfere with debugging. */
1260 if (NONJUMP_INSN_P (insn)
1261 && GET_CODE (PATTERN (insn)) == SET
1262 && REG_P (SET_SRC (PATTERN (insn)))
1263 && REG_P (SET_DEST (PATTERN (insn)))
1264 && (REGNO (SET_SRC (PATTERN (insn)))
1265 == REGNO (SET_DEST (PATTERN (insn)))))
1271 pnote = ®_NOTES (insn);
1274 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1275 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1276 || REG_NOTE_KIND (*pnote) == REG_INC)
1277 *pnote = XEXP (*pnote, 1);
1279 pnote = &XEXP (*pnote, 1);
1283 add_auto_inc_notes (insn, PATTERN (insn));
1286 /* Simplify (subreg (reg)) if it appears as an operand. */
1287 cleanup_subreg_operands (insn);
1289 /* Clean up invalid ASMs so that they don't confuse later passes.
1291 if (asm_noperands (PATTERN (insn)) >= 0)
1293 extract_insn (insn);
1294 if (!constrain_operands (1))
1296 error_for_asm (insn,
1297 "%<asm%> operand has impossible constraints");
1304 /* If we are doing stack checking, give a warning if this function's
1305 frame size is larger than we expect. */
1306 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1308 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1309 static int verbose_warned = 0;
1311 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1312 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1313 size += UNITS_PER_WORD;
1315 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1317 warning (0, "frame size too large for reliable stack checking");
1318 if (! verbose_warned)
1320 warning (0, "try reducing the number of local variables");
1326 /* Indicate that we no longer have known memory locations or constants. */
1327 if (reg_equiv_constant)
1328 free (reg_equiv_constant);
1329 if (reg_equiv_invariant)
1330 free (reg_equiv_invariant);
1331 reg_equiv_constant = 0;
1332 reg_equiv_invariant = 0;
1333 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1334 reg_equiv_memory_loc = 0;
1336 if (offsets_known_at)
1337 free (offsets_known_at);
1341 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1342 if (reg_equiv_alt_mem_list[i])
1343 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1344 free (reg_equiv_alt_mem_list);
1346 free (reg_equiv_mem);
1348 free (reg_equiv_address);
1349 free (reg_max_ref_width);
1350 free (reg_old_renumber);
1351 free (pseudo_previous_regs);
1352 free (pseudo_forbidden_regs);
1354 CLEAR_HARD_REG_SET (used_spill_regs);
1355 for (i = 0; i < n_spills; i++)
1356 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1358 /* Free all the insn_chain structures at once. */
1359 obstack_free (&reload_obstack, reload_startobj);
1360 unused_insn_chains = 0;
1361 fixup_abnormal_edges ();
1363 /* Replacing pseudos with their memory equivalents might have
1364 created shared rtx. Subsequent passes would get confused
1365 by this, so unshare everything here. */
1366 unshare_all_rtl_again (first);
1368 #ifdef STACK_BOUNDARY
1369 /* init_emit has set the alignment of the hard frame pointer
1370 to STACK_BOUNDARY. It is very likely no longer valid if
1371 the hard frame pointer was used for register allocation. */
1372 if (!frame_pointer_needed)
1373 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1379 /* Yet another special case. Unfortunately, reg-stack forces people to
1380 write incorrect clobbers in asm statements. These clobbers must not
1381 cause the register to appear in bad_spill_regs, otherwise we'll call
1382 fatal_insn later. We clear the corresponding regnos in the live
1383 register sets to avoid this.
1384 The whole thing is rather sick, I'm afraid. */
1387 maybe_fix_stack_asms (void)
1390 const char *constraints[MAX_RECOG_OPERANDS];
1391 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1392 struct insn_chain *chain;
1394 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1397 HARD_REG_SET clobbered, allowed;
1400 if (! INSN_P (chain->insn)
1401 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1403 pat = PATTERN (chain->insn);
1404 if (GET_CODE (pat) != PARALLEL)
1407 CLEAR_HARD_REG_SET (clobbered);
1408 CLEAR_HARD_REG_SET (allowed);
1410 /* First, make a mask of all stack regs that are clobbered. */
1411 for (i = 0; i < XVECLEN (pat, 0); i++)
1413 rtx t = XVECEXP (pat, 0, i);
1414 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1415 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1418 /* Get the operand values and constraints out of the insn. */
1419 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1420 constraints, operand_mode, NULL);
1422 /* For every operand, see what registers are allowed. */
1423 for (i = 0; i < noperands; i++)
1425 const char *p = constraints[i];
1426 /* For every alternative, we compute the class of registers allowed
1427 for reloading in CLS, and merge its contents into the reg set
1429 int cls = (int) NO_REGS;
1435 if (c == '\0' || c == ',' || c == '#')
1437 /* End of one alternative - mark the regs in the current
1438 class, and reset the class. */
1439 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1445 } while (c != '\0' && c != ',');
1453 case '=': case '+': case '*': case '%': case '?': case '!':
1454 case '0': case '1': case '2': case '3': case '4': case '<':
1455 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1456 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1457 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1458 case TARGET_MEM_CONSTRAINT:
1462 cls = (int) reg_class_subunion[cls]
1463 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1468 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1472 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1473 cls = (int) reg_class_subunion[cls]
1474 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1476 cls = (int) reg_class_subunion[cls]
1477 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1479 p += CONSTRAINT_LEN (c, p);
1482 /* Those of the registers which are clobbered, but allowed by the
1483 constraints, must be usable as reload registers. So clear them
1484 out of the life information. */
1485 AND_HARD_REG_SET (allowed, clobbered);
1486 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1487 if (TEST_HARD_REG_BIT (allowed, i))
1489 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1490 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1497 /* Copy the global variables n_reloads and rld into the corresponding elts
1500 copy_reloads (struct insn_chain *chain)
1502 chain->n_reloads = n_reloads;
1503 chain->rld = obstack_alloc (&reload_obstack,
1504 n_reloads * sizeof (struct reload));
1505 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1506 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1509 /* Walk the chain of insns, and determine for each whether it needs reloads
1510 and/or eliminations. Build the corresponding insns_need_reload list, and
1511 set something_needs_elimination as appropriate. */
1513 calculate_needs_all_insns (int global)
1515 struct insn_chain **pprev_reload = &insns_need_reload;
1516 struct insn_chain *chain, *next = 0;
1518 something_needs_elimination = 0;
1520 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1521 for (chain = reload_insn_chain; chain != 0; chain = next)
1523 rtx insn = chain->insn;
1527 /* Clear out the shortcuts. */
1528 chain->n_reloads = 0;
1529 chain->need_elim = 0;
1530 chain->need_reload = 0;
1531 chain->need_operand_change = 0;
1533 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1534 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1535 what effects this has on the known offsets at labels. */
1537 if (LABEL_P (insn) || JUMP_P (insn)
1538 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1539 set_label_offsets (insn, insn, 0);
1543 rtx old_body = PATTERN (insn);
1544 int old_code = INSN_CODE (insn);
1545 rtx old_notes = REG_NOTES (insn);
1546 int did_elimination = 0;
1547 int operands_changed = 0;
1548 rtx set = single_set (insn);
1550 /* Skip insns that only set an equivalence. */
1551 if (set && REG_P (SET_DEST (set))
1552 && reg_renumber[REGNO (SET_DEST (set))] < 0
1553 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1554 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1555 && reg_equiv_init[REGNO (SET_DEST (set))])
1558 /* If needed, eliminate any eliminable registers. */
1559 if (num_eliminable || num_eliminable_invariants)
1560 did_elimination = eliminate_regs_in_insn (insn, 0);
1562 /* Analyze the instruction. */
1563 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1564 global, spill_reg_order);
1566 /* If a no-op set needs more than one reload, this is likely
1567 to be something that needs input address reloads. We
1568 can't get rid of this cleanly later, and it is of no use
1569 anyway, so discard it now.
1570 We only do this when expensive_optimizations is enabled,
1571 since this complements reload inheritance / output
1572 reload deletion, and it can make debugging harder. */
1573 if (flag_expensive_optimizations && n_reloads > 1)
1575 rtx set = single_set (insn);
1577 && SET_SRC (set) == SET_DEST (set)
1578 && REG_P (SET_SRC (set))
1579 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1582 /* Delete it from the reload chain. */
1584 chain->prev->next = next;
1586 reload_insn_chain = next;
1588 next->prev = chain->prev;
1589 chain->next = unused_insn_chains;
1590 unused_insn_chains = chain;
1595 update_eliminable_offsets ();
1597 /* Remember for later shortcuts which insns had any reloads or
1598 register eliminations. */
1599 chain->need_elim = did_elimination;
1600 chain->need_reload = n_reloads > 0;
1601 chain->need_operand_change = operands_changed;
1603 /* Discard any register replacements done. */
1604 if (did_elimination)
1606 obstack_free (&reload_obstack, reload_insn_firstobj);
1607 PATTERN (insn) = old_body;
1608 INSN_CODE (insn) = old_code;
1609 REG_NOTES (insn) = old_notes;
1610 something_needs_elimination = 1;
1613 something_needs_operands_changed |= operands_changed;
1617 copy_reloads (chain);
1618 *pprev_reload = chain;
1619 pprev_reload = &chain->next_need_reload;
1626 /* Comparison function for qsort to decide which of two reloads
1627 should be handled first. *P1 and *P2 are the reload numbers. */
1630 reload_reg_class_lower (const void *r1p, const void *r2p)
1632 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1635 /* Consider required reloads before optional ones. */
1636 t = rld[r1].optional - rld[r2].optional;
1640 /* Count all solitary classes before non-solitary ones. */
1641 t = ((reg_class_size[(int) rld[r2].class] == 1)
1642 - (reg_class_size[(int) rld[r1].class] == 1));
1646 /* Aside from solitaires, consider all multi-reg groups first. */
1647 t = rld[r2].nregs - rld[r1].nregs;
1651 /* Consider reloads in order of increasing reg-class number. */
1652 t = (int) rld[r1].class - (int) rld[r2].class;
1656 /* If reloads are equally urgent, sort by reload number,
1657 so that the results of qsort leave nothing to chance. */
1661 /* The cost of spilling each hard reg. */
1662 static int spill_cost[FIRST_PSEUDO_REGISTER];
1664 /* When spilling multiple hard registers, we use SPILL_COST for the first
1665 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1666 only the first hard reg for a multi-reg pseudo. */
1667 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1669 /* Update the spill cost arrays, considering that pseudo REG is live. */
1672 count_pseudo (int reg)
1674 int freq = REG_FREQ (reg);
1675 int r = reg_renumber[reg];
1678 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1679 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1682 SET_REGNO_REG_SET (&pseudos_counted, reg);
1684 gcc_assert (r >= 0);
1686 spill_add_cost[r] += freq;
1688 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1690 spill_cost[r + nregs] += freq;
1693 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1694 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1697 order_regs_for_reload (struct insn_chain *chain)
1700 HARD_REG_SET used_by_pseudos;
1701 HARD_REG_SET used_by_pseudos2;
1702 reg_set_iterator rsi;
1704 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1706 memset (spill_cost, 0, sizeof spill_cost);
1707 memset (spill_add_cost, 0, sizeof spill_add_cost);
1709 /* Count number of uses of each hard reg by pseudo regs allocated to it
1710 and then order them by decreasing use. First exclude hard registers
1711 that are live in or across this insn. */
1713 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1714 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1715 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1716 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1718 /* Now find out which pseudos are allocated to it, and update
1720 CLEAR_REG_SET (&pseudos_counted);
1722 EXECUTE_IF_SET_IN_REG_SET
1723 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1727 EXECUTE_IF_SET_IN_REG_SET
1728 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1732 CLEAR_REG_SET (&pseudos_counted);
1735 /* Vector of reload-numbers showing the order in which the reloads should
1737 static short reload_order[MAX_RELOADS];
1739 /* This is used to keep track of the spill regs used in one insn. */
1740 static HARD_REG_SET used_spill_regs_local;
1742 /* We decided to spill hard register SPILLED, which has a size of
1743 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1744 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1745 update SPILL_COST/SPILL_ADD_COST. */
1748 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1750 int r = reg_renumber[reg];
1751 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1753 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1754 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1757 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1759 spill_add_cost[r] -= REG_FREQ (reg);
1761 spill_cost[r + nregs] -= REG_FREQ (reg);
1764 /* Find reload register to use for reload number ORDER. */
1767 find_reg (struct insn_chain *chain, int order)
1769 int rnum = reload_order[order];
1770 struct reload *rl = rld + rnum;
1771 int best_cost = INT_MAX;
1775 HARD_REG_SET not_usable;
1776 HARD_REG_SET used_by_other_reload;
1777 reg_set_iterator rsi;
1779 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1780 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1781 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1783 CLEAR_HARD_REG_SET (used_by_other_reload);
1784 for (k = 0; k < order; k++)
1786 int other = reload_order[k];
1788 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1789 for (j = 0; j < rld[other].nregs; j++)
1790 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1793 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1795 unsigned int regno = i;
1797 if (! TEST_HARD_REG_BIT (not_usable, regno)
1798 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1799 && HARD_REGNO_MODE_OK (regno, rl->mode))
1801 int this_cost = spill_cost[regno];
1803 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1805 for (j = 1; j < this_nregs; j++)
1807 this_cost += spill_add_cost[regno + j];
1808 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1809 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1814 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1816 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1818 if (this_cost < best_cost
1819 /* Among registers with equal cost, prefer caller-saved ones, or
1820 use REG_ALLOC_ORDER if it is defined. */
1821 || (this_cost == best_cost
1822 #ifdef REG_ALLOC_ORDER
1823 && (inv_reg_alloc_order[regno]
1824 < inv_reg_alloc_order[best_reg])
1826 && call_used_regs[regno]
1827 && ! call_used_regs[best_reg]
1832 best_cost = this_cost;
1840 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1842 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1843 rl->regno = best_reg;
1845 EXECUTE_IF_SET_IN_REG_SET
1846 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1848 count_spilled_pseudo (best_reg, rl->nregs, j);
1851 EXECUTE_IF_SET_IN_REG_SET
1852 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1854 count_spilled_pseudo (best_reg, rl->nregs, j);
1857 for (i = 0; i < rl->nregs; i++)
1859 gcc_assert (spill_cost[best_reg + i] == 0);
1860 gcc_assert (spill_add_cost[best_reg + i] == 0);
1861 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1866 /* Find more reload regs to satisfy the remaining need of an insn, which
1868 Do it by ascending class number, since otherwise a reg
1869 might be spilled for a big class and might fail to count
1870 for a smaller class even though it belongs to that class. */
1873 find_reload_regs (struct insn_chain *chain)
1877 /* In order to be certain of getting the registers we need,
1878 we must sort the reloads into order of increasing register class.
1879 Then our grabbing of reload registers will parallel the process
1880 that provided the reload registers. */
1881 for (i = 0; i < chain->n_reloads; i++)
1883 /* Show whether this reload already has a hard reg. */
1884 if (chain->rld[i].reg_rtx)
1886 int regno = REGNO (chain->rld[i].reg_rtx);
1887 chain->rld[i].regno = regno;
1889 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1892 chain->rld[i].regno = -1;
1893 reload_order[i] = i;
1896 n_reloads = chain->n_reloads;
1897 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1899 CLEAR_HARD_REG_SET (used_spill_regs_local);
1902 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1904 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1906 /* Compute the order of preference for hard registers to spill. */
1908 order_regs_for_reload (chain);
1910 for (i = 0; i < n_reloads; i++)
1912 int r = reload_order[i];
1914 /* Ignore reloads that got marked inoperative. */
1915 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1916 && ! rld[r].optional
1917 && rld[r].regno == -1)
1918 if (! find_reg (chain, i))
1921 fprintf (dump_file, "reload failure for reload %d\n", r);
1922 spill_failure (chain->insn, rld[r].class);
1928 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1929 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1931 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1935 select_reload_regs (void)
1937 struct insn_chain *chain;
1939 /* Try to satisfy the needs for each insn. */
1940 for (chain = insns_need_reload; chain != 0;
1941 chain = chain->next_need_reload)
1942 find_reload_regs (chain);
1945 /* Delete all insns that were inserted by emit_caller_save_insns during
1948 delete_caller_save_insns (void)
1950 struct insn_chain *c = reload_insn_chain;
1954 while (c != 0 && c->is_caller_save_insn)
1956 struct insn_chain *next = c->next;
1959 if (c == reload_insn_chain)
1960 reload_insn_chain = next;
1964 next->prev = c->prev;
1966 c->prev->next = next;
1967 c->next = unused_insn_chains;
1968 unused_insn_chains = c;
1976 /* Handle the failure to find a register to spill.
1977 INSN should be one of the insns which needed this particular spill reg. */
1980 spill_failure (rtx insn, enum reg_class class)
1982 if (asm_noperands (PATTERN (insn)) >= 0)
1983 error_for_asm (insn, "can't find a register in class %qs while "
1984 "reloading %<asm%>",
1985 reg_class_names[class]);
1988 error ("unable to find a register to spill in class %qs",
1989 reg_class_names[class]);
1993 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1994 debug_reload_to_stream (dump_file);
1996 fatal_insn ("this is the insn:", insn);
2000 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2001 data that is dead in INSN. */
2004 delete_dead_insn (rtx insn)
2006 rtx prev = prev_real_insn (insn);
2009 /* If the previous insn sets a register that dies in our insn, delete it
2011 if (prev && GET_CODE (PATTERN (prev)) == SET
2012 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2013 && reg_mentioned_p (prev_dest, PATTERN (insn))
2014 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2015 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2016 delete_dead_insn (prev);
2018 SET_INSN_DELETED (insn);
2021 /* Modify the home of pseudo-reg I.
2022 The new home is present in reg_renumber[I].
2024 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2025 or it may be -1, meaning there is none or it is not relevant.
2026 This is used so that all pseudos spilled from a given hard reg
2027 can share one stack slot. */
2030 alter_reg (int i, int from_reg)
2032 /* When outputting an inline function, this can happen
2033 for a reg that isn't actually used. */
2034 if (regno_reg_rtx[i] == 0)
2037 /* If the reg got changed to a MEM at rtl-generation time,
2039 if (!REG_P (regno_reg_rtx[i]))
2042 /* Modify the reg-rtx to contain the new hard reg
2043 number or else to contain its pseudo reg number. */
2044 SET_REGNO (regno_reg_rtx[i],
2045 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2047 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2048 allocate a stack slot for it. */
2050 if (reg_renumber[i] < 0
2051 && REG_N_REFS (i) > 0
2052 && reg_equiv_constant[i] == 0
2053 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2054 && reg_equiv_memory_loc[i] == 0)
2057 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2058 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2059 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2060 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2061 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2064 /* Each pseudo reg has an inherent size which comes from its own mode,
2065 and a total size which provides room for paradoxical subregs
2066 which refer to the pseudo reg in wider modes.
2068 We can use a slot already allocated if it provides both
2069 enough inherent space and enough total space.
2070 Otherwise, we allocate a new slot, making sure that it has no less
2071 inherent space, and no less total space, then the previous slot. */
2074 alias_set_type alias_set = new_alias_set ();
2076 /* No known place to spill from => no slot to reuse. */
2077 x = assign_stack_local (mode, total_size,
2078 min_align > inherent_align
2079 || total_size > inherent_size ? -1 : 0);
2080 if (BYTES_BIG_ENDIAN)
2081 /* Cancel the big-endian correction done in assign_stack_local.
2082 Get the address of the beginning of the slot.
2083 This is so we can do a big-endian correction unconditionally
2085 adjust = inherent_size - total_size;
2087 /* Nothing can alias this slot except this pseudo. */
2088 set_mem_alias_set (x, alias_set);
2089 dse_record_singleton_alias_set (alias_set, mode);
2092 /* Reuse a stack slot if possible. */
2093 else if (spill_stack_slot[from_reg] != 0
2094 && spill_stack_slot_width[from_reg] >= total_size
2095 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2097 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2098 x = spill_stack_slot[from_reg];
2099 /* Allocate a bigger slot. */
2102 /* Compute maximum size needed, both for inherent size
2103 and for total size. */
2106 if (spill_stack_slot[from_reg])
2108 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2110 mode = GET_MODE (spill_stack_slot[from_reg]);
2111 if (spill_stack_slot_width[from_reg] > total_size)
2112 total_size = spill_stack_slot_width[from_reg];
2113 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2114 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2117 /* Make a slot with that size. */
2118 x = assign_stack_local (mode, total_size,
2119 min_align > inherent_align
2120 || total_size > inherent_size ? -1 : 0);
2123 /* All pseudos mapped to this slot can alias each other. */
2124 if (spill_stack_slot[from_reg])
2126 alias_set_type alias_set
2127 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2128 set_mem_alias_set (x, alias_set);
2129 dse_invalidate_singleton_alias_set (alias_set);
2133 alias_set_type alias_set = new_alias_set ();
2134 set_mem_alias_set (x, alias_set);
2135 dse_record_singleton_alias_set (alias_set, mode);
2138 if (BYTES_BIG_ENDIAN)
2140 /* Cancel the big-endian correction done in assign_stack_local.
2141 Get the address of the beginning of the slot.
2142 This is so we can do a big-endian correction unconditionally
2144 adjust = GET_MODE_SIZE (mode) - total_size;
2147 = adjust_address_nv (x, mode_for_size (total_size
2153 spill_stack_slot[from_reg] = stack_slot;
2154 spill_stack_slot_width[from_reg] = total_size;
2157 /* On a big endian machine, the "address" of the slot
2158 is the address of the low part that fits its inherent mode. */
2159 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2160 adjust += (total_size - inherent_size);
2162 /* If we have any adjustment to make, or if the stack slot is the
2163 wrong mode, make a new stack slot. */
2164 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2166 /* If we have a decl for the original register, set it for the
2167 memory. If this is a shared MEM, make a copy. */
2168 if (REG_EXPR (regno_reg_rtx[i])
2169 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2171 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2173 /* We can do this only for the DECLs home pseudo, not for
2174 any copies of it, since otherwise when the stack slot
2175 is reused, nonoverlapping_memrefs_p might think they
2177 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2179 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2182 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2186 /* Save the stack slot for later. */
2187 reg_equiv_memory_loc[i] = x;
2191 /* Mark the slots in regs_ever_live for the hard regs used by
2192 pseudo-reg number REGNO, accessed in MODE. */
2195 mark_home_live_1 (int regno, enum machine_mode mode)
2199 i = reg_renumber[regno];
2202 lim = end_hard_regno (mode, i);
2204 df_set_regs_ever_live(i++, true);
2207 /* Mark the slots in regs_ever_live for the hard regs
2208 used by pseudo-reg number REGNO. */
2211 mark_home_live (int regno)
2213 if (reg_renumber[regno] >= 0)
2214 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2217 /* This function handles the tracking of elimination offsets around branches.
2219 X is a piece of RTL being scanned.
2221 INSN is the insn that it came from, if any.
2223 INITIAL_P is nonzero if we are to set the offset to be the initial
2224 offset and zero if we are setting the offset of the label to be the
2228 set_label_offsets (rtx x, rtx insn, int initial_p)
2230 enum rtx_code code = GET_CODE (x);
2233 struct elim_table *p;
2238 if (LABEL_REF_NONLOCAL_P (x))
2243 /* ... fall through ... */
2246 /* If we know nothing about this label, set the desired offsets. Note
2247 that this sets the offset at a label to be the offset before a label
2248 if we don't know anything about the label. This is not correct for
2249 the label after a BARRIER, but is the best guess we can make. If
2250 we guessed wrong, we will suppress an elimination that might have
2251 been possible had we been able to guess correctly. */
2253 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2255 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2256 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2257 = (initial_p ? reg_eliminate[i].initial_offset
2258 : reg_eliminate[i].offset);
2259 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2262 /* Otherwise, if this is the definition of a label and it is
2263 preceded by a BARRIER, set our offsets to the known offset of
2267 && (tem = prev_nonnote_insn (insn)) != 0
2269 set_offsets_for_label (insn);
2271 /* If neither of the above cases is true, compare each offset
2272 with those previously recorded and suppress any eliminations
2273 where the offsets disagree. */
2275 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2276 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2277 != (initial_p ? reg_eliminate[i].initial_offset
2278 : reg_eliminate[i].offset))
2279 reg_eliminate[i].can_eliminate = 0;
2284 set_label_offsets (PATTERN (insn), insn, initial_p);
2286 /* ... fall through ... */
2290 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2291 to indirectly and hence must have all eliminations at their
2293 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2294 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2295 set_label_offsets (XEXP (tem, 0), insn, 1);
2301 /* Each of the labels in the parallel or address vector must be
2302 at their initial offsets. We want the first field for PARALLEL
2303 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2305 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2306 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2311 /* We only care about setting PC. If the source is not RETURN,
2312 IF_THEN_ELSE, or a label, disable any eliminations not at
2313 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2314 isn't one of those possibilities. For branches to a label,
2315 call ourselves recursively.
2317 Note that this can disable elimination unnecessarily when we have
2318 a non-local goto since it will look like a non-constant jump to
2319 someplace in the current function. This isn't a significant
2320 problem since such jumps will normally be when all elimination
2321 pairs are back to their initial offsets. */
2323 if (SET_DEST (x) != pc_rtx)
2326 switch (GET_CODE (SET_SRC (x)))
2333 set_label_offsets (SET_SRC (x), insn, initial_p);
2337 tem = XEXP (SET_SRC (x), 1);
2338 if (GET_CODE (tem) == LABEL_REF)
2339 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2340 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2343 tem = XEXP (SET_SRC (x), 2);
2344 if (GET_CODE (tem) == LABEL_REF)
2345 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2346 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2354 /* If we reach here, all eliminations must be at their initial
2355 offset because we are doing a jump to a variable address. */
2356 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2357 if (p->offset != p->initial_offset)
2358 p->can_eliminate = 0;
2366 /* Scan X and replace any eliminable registers (such as fp) with a
2367 replacement (such as sp), plus an offset.
2369 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2370 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2371 MEM, we are allowed to replace a sum of a register and the constant zero
2372 with the register, which we cannot do outside a MEM. In addition, we need
2373 to record the fact that a register is referenced outside a MEM.
2375 If INSN is an insn, it is the insn containing X. If we replace a REG
2376 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2377 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2378 the REG is being modified.
2380 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2381 That's used when we eliminate in expressions stored in notes.
2382 This means, do not set ref_outside_mem even if the reference
2385 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2386 replacements done assuming all offsets are at their initial values. If
2387 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2388 encounter, return the actual location so that find_reloads will do
2389 the proper thing. */
2392 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2393 bool may_use_invariant)
2395 enum rtx_code code = GET_CODE (x);
2396 struct elim_table *ep;
2403 if (! current_function_decl)
2426 /* First handle the case where we encounter a bare register that
2427 is eliminable. Replace it with a PLUS. */
2428 if (regno < FIRST_PSEUDO_REGISTER)
2430 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2432 if (ep->from_rtx == x && ep->can_eliminate)
2433 return plus_constant (ep->to_rtx, ep->previous_offset);
2436 else if (reg_renumber && reg_renumber[regno] < 0
2437 && reg_equiv_invariant && reg_equiv_invariant[regno])
2439 if (may_use_invariant)
2440 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2441 mem_mode, insn, true);
2442 /* There exists at least one use of REGNO that cannot be
2443 eliminated. Prevent the defining insn from being deleted. */
2444 reg_equiv_init[regno] = NULL_RTX;
2445 alter_reg (regno, -1);
2449 /* You might think handling MINUS in a manner similar to PLUS is a
2450 good idea. It is not. It has been tried multiple times and every
2451 time the change has had to have been reverted.
2453 Other parts of reload know a PLUS is special (gen_reload for example)
2454 and require special code to handle code a reloaded PLUS operand.
2456 Also consider backends where the flags register is clobbered by a
2457 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2458 lea instruction comes to mind). If we try to reload a MINUS, we
2459 may kill the flags register that was holding a useful value.
2461 So, please before trying to handle MINUS, consider reload as a
2462 whole instead of this little section as well as the backend issues. */
2464 /* If this is the sum of an eliminable register and a constant, rework
2466 if (REG_P (XEXP (x, 0))
2467 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2468 && CONSTANT_P (XEXP (x, 1)))
2470 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2472 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2474 /* The only time we want to replace a PLUS with a REG (this
2475 occurs when the constant operand of the PLUS is the negative
2476 of the offset) is when we are inside a MEM. We won't want
2477 to do so at other times because that would change the
2478 structure of the insn in a way that reload can't handle.
2479 We special-case the commonest situation in
2480 eliminate_regs_in_insn, so just replace a PLUS with a
2481 PLUS here, unless inside a MEM. */
2482 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2483 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2486 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2487 plus_constant (XEXP (x, 1),
2488 ep->previous_offset));
2491 /* If the register is not eliminable, we are done since the other
2492 operand is a constant. */
2496 /* If this is part of an address, we want to bring any constant to the
2497 outermost PLUS. We will do this by doing register replacement in
2498 our operands and seeing if a constant shows up in one of them.
2500 Note that there is no risk of modifying the structure of the insn,
2501 since we only get called for its operands, thus we are either
2502 modifying the address inside a MEM, or something like an address
2503 operand of a load-address insn. */
2506 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2507 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2509 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2511 /* If one side is a PLUS and the other side is a pseudo that
2512 didn't get a hard register but has a reg_equiv_constant,
2513 we must replace the constant here since it may no longer
2514 be in the position of any operand. */
2515 if (GET_CODE (new0) == PLUS && REG_P (new1)
2516 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2517 && reg_renumber[REGNO (new1)] < 0
2518 && reg_equiv_constant != 0
2519 && reg_equiv_constant[REGNO (new1)] != 0)
2520 new1 = reg_equiv_constant[REGNO (new1)];
2521 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2522 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2523 && reg_renumber[REGNO (new0)] < 0
2524 && reg_equiv_constant[REGNO (new0)] != 0)
2525 new0 = reg_equiv_constant[REGNO (new0)];
2527 new = form_sum (new0, new1);
2529 /* As above, if we are not inside a MEM we do not want to
2530 turn a PLUS into something else. We might try to do so here
2531 for an addition of 0 if we aren't optimizing. */
2532 if (! mem_mode && GET_CODE (new) != PLUS)
2533 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2541 /* If this is the product of an eliminable register and a
2542 constant, apply the distribute law and move the constant out
2543 so that we have (plus (mult ..) ..). This is needed in order
2544 to keep load-address insns valid. This case is pathological.
2545 We ignore the possibility of overflow here. */
2546 if (REG_P (XEXP (x, 0))
2547 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2548 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2549 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2551 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2554 /* Refs inside notes don't count for this purpose. */
2555 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2556 || GET_CODE (insn) == INSN_LIST)))
2557 ep->ref_outside_mem = 1;
2560 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2561 ep->previous_offset * INTVAL (XEXP (x, 1)));
2564 /* ... fall through ... */
2568 /* See comments before PLUS about handling MINUS. */
2570 case DIV: case UDIV:
2571 case MOD: case UMOD:
2572 case AND: case IOR: case XOR:
2573 case ROTATERT: case ROTATE:
2574 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2576 case GE: case GT: case GEU: case GTU:
2577 case LE: case LT: case LEU: case LTU:
2579 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2580 rtx new1 = XEXP (x, 1)
2581 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2583 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2584 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2589 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2592 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2593 if (new != XEXP (x, 0))
2595 /* If this is a REG_DEAD note, it is not valid anymore.
2596 Using the eliminated version could result in creating a
2597 REG_DEAD note for the stack or frame pointer. */
2598 if (GET_MODE (x) == REG_DEAD)
2600 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2603 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2607 /* ... fall through ... */
2610 /* Now do eliminations in the rest of the chain. If this was
2611 an EXPR_LIST, this might result in allocating more memory than is
2612 strictly needed, but it simplifies the code. */
2615 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2616 if (new != XEXP (x, 1))
2618 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2626 /* We do not support elimination of a register that is modified.
2627 elimination_effects has already make sure that this does not
2633 /* We do not support elimination of a register that is modified.
2634 elimination_effects has already make sure that this does not
2635 happen. The only remaining case we need to consider here is
2636 that the increment value may be an eliminable register. */
2637 if (GET_CODE (XEXP (x, 1)) == PLUS
2638 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2640 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2643 if (new != XEXP (XEXP (x, 1), 1))
2644 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2645 gen_rtx_PLUS (GET_MODE (x),
2650 case STRICT_LOW_PART:
2652 case SIGN_EXTEND: case ZERO_EXTEND:
2653 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2654 case FLOAT: case FIX:
2655 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2664 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2665 if (new != XEXP (x, 0))
2666 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2670 /* Similar to above processing, but preserve SUBREG_BYTE.
2671 Convert (subreg (mem)) to (mem) if not paradoxical.
2672 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2673 pseudo didn't get a hard reg, we must replace this with the
2674 eliminated version of the memory location because push_reload
2675 may do the replacement in certain circumstances. */
2676 if (REG_P (SUBREG_REG (x))
2677 && (GET_MODE_SIZE (GET_MODE (x))
2678 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2679 && reg_equiv_memory_loc != 0
2680 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2682 new = SUBREG_REG (x);
2685 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2687 if (new != SUBREG_REG (x))
2689 int x_size = GET_MODE_SIZE (GET_MODE (x));
2690 int new_size = GET_MODE_SIZE (GET_MODE (new));
2693 && ((x_size < new_size
2694 #ifdef WORD_REGISTER_OPERATIONS
2695 /* On these machines, combine can create rtl of the form
2696 (set (subreg:m1 (reg:m2 R) 0) ...)
2697 where m1 < m2, and expects something interesting to
2698 happen to the entire word. Moreover, it will use the
2699 (reg:m2 R) later, expecting all bits to be preserved.
2700 So if the number of words is the same, preserve the
2701 subreg so that push_reload can see it. */
2702 && ! ((x_size - 1) / UNITS_PER_WORD
2703 == (new_size -1 ) / UNITS_PER_WORD)
2706 || x_size == new_size)
2708 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2710 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2716 /* Our only special processing is to pass the mode of the MEM to our
2717 recursive call and copy the flags. While we are here, handle this
2718 case more efficiently. */
2720 replace_equiv_address_nv (x,
2721 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2725 /* Handle insn_list USE that a call to a pure function may generate. */
2726 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2727 if (new != XEXP (x, 0))
2728 return gen_rtx_USE (GET_MODE (x), new);
2740 /* Process each of our operands recursively. If any have changed, make a
2742 fmt = GET_RTX_FORMAT (code);
2743 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2747 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2748 if (new != XEXP (x, i) && ! copied)
2750 x = shallow_copy_rtx (x);
2755 else if (*fmt == 'E')
2758 for (j = 0; j < XVECLEN (x, i); j++)
2760 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2761 if (new != XVECEXP (x, i, j) && ! copied_vec)
2763 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2767 x = shallow_copy_rtx (x);
2770 XVEC (x, i) = new_v;
2773 XVECEXP (x, i, j) = new;
2782 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2784 return eliminate_regs_1 (x, mem_mode, insn, false);
2787 /* Scan rtx X for modifications of elimination target registers. Update
2788 the table of eliminables to reflect the changed state. MEM_MODE is
2789 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2792 elimination_effects (rtx x, enum machine_mode mem_mode)
2794 enum rtx_code code = GET_CODE (x);
2795 struct elim_table *ep;
2820 /* First handle the case where we encounter a bare register that
2821 is eliminable. Replace it with a PLUS. */
2822 if (regno < FIRST_PSEUDO_REGISTER)
2824 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2826 if (ep->from_rtx == x && ep->can_eliminate)
2829 ep->ref_outside_mem = 1;
2834 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2835 && reg_equiv_constant[regno]
2836 && ! function_invariant_p (reg_equiv_constant[regno]))
2837 elimination_effects (reg_equiv_constant[regno], mem_mode);
2846 /* If we modify the source of an elimination rule, disable it. */
2847 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2848 if (ep->from_rtx == XEXP (x, 0))
2849 ep->can_eliminate = 0;
2851 /* If we modify the target of an elimination rule by adding a constant,
2852 update its offset. If we modify the target in any other way, we'll
2853 have to disable the rule as well. */
2854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2855 if (ep->to_rtx == XEXP (x, 0))
2857 int size = GET_MODE_SIZE (mem_mode);
2859 /* If more bytes than MEM_MODE are pushed, account for them. */
2860 #ifdef PUSH_ROUNDING
2861 if (ep->to_rtx == stack_pointer_rtx)
2862 size = PUSH_ROUNDING (size);
2864 if (code == PRE_DEC || code == POST_DEC)
2866 else if (code == PRE_INC || code == POST_INC)
2868 else if (code == PRE_MODIFY || code == POST_MODIFY)
2870 if (GET_CODE (XEXP (x, 1)) == PLUS
2871 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2872 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2873 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2875 ep->can_eliminate = 0;
2879 /* These two aren't unary operators. */
2880 if (code == POST_MODIFY || code == PRE_MODIFY)
2883 /* Fall through to generic unary operation case. */
2884 case STRICT_LOW_PART:
2886 case SIGN_EXTEND: case ZERO_EXTEND:
2887 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2888 case FLOAT: case FIX:
2889 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2898 elimination_effects (XEXP (x, 0), mem_mode);
2902 if (REG_P (SUBREG_REG (x))
2903 && (GET_MODE_SIZE (GET_MODE (x))
2904 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2905 && reg_equiv_memory_loc != 0
2906 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2909 elimination_effects (SUBREG_REG (x), mem_mode);
2913 /* If using a register that is the source of an eliminate we still
2914 think can be performed, note it cannot be performed since we don't
2915 know how this register is used. */
2916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2917 if (ep->from_rtx == XEXP (x, 0))
2918 ep->can_eliminate = 0;
2920 elimination_effects (XEXP (x, 0), mem_mode);
2924 /* If clobbering a register that is the replacement register for an
2925 elimination we still think can be performed, note that it cannot
2926 be performed. Otherwise, we need not be concerned about it. */
2927 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2928 if (ep->to_rtx == XEXP (x, 0))
2929 ep->can_eliminate = 0;
2931 elimination_effects (XEXP (x, 0), mem_mode);
2935 /* Check for setting a register that we know about. */
2936 if (REG_P (SET_DEST (x)))
2938 /* See if this is setting the replacement register for an
2941 If DEST is the hard frame pointer, we do nothing because we
2942 assume that all assignments to the frame pointer are for
2943 non-local gotos and are being done at a time when they are valid
2944 and do not disturb anything else. Some machines want to
2945 eliminate a fake argument pointer (or even a fake frame pointer)
2946 with either the real frame or the stack pointer. Assignments to
2947 the hard frame pointer must not prevent this elimination. */
2949 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2951 if (ep->to_rtx == SET_DEST (x)
2952 && SET_DEST (x) != hard_frame_pointer_rtx)
2954 /* If it is being incremented, adjust the offset. Otherwise,
2955 this elimination can't be done. */
2956 rtx src = SET_SRC (x);
2958 if (GET_CODE (src) == PLUS
2959 && XEXP (src, 0) == SET_DEST (x)
2960 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2961 ep->offset -= INTVAL (XEXP (src, 1));
2963 ep->can_eliminate = 0;
2967 elimination_effects (SET_DEST (x), 0);
2968 elimination_effects (SET_SRC (x), 0);
2972 /* Our only special processing is to pass the mode of the MEM to our
2974 elimination_effects (XEXP (x, 0), GET_MODE (x));
2981 fmt = GET_RTX_FORMAT (code);
2982 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2985 elimination_effects (XEXP (x, i), mem_mode);
2986 else if (*fmt == 'E')
2987 for (j = 0; j < XVECLEN (x, i); j++)
2988 elimination_effects (XVECEXP (x, i, j), mem_mode);
2992 /* Descend through rtx X and verify that no references to eliminable registers
2993 remain. If any do remain, mark the involved register as not
2997 check_eliminable_occurrences (rtx x)
3006 code = GET_CODE (x);
3008 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3010 struct elim_table *ep;
3012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3013 if (ep->from_rtx == x)
3014 ep->can_eliminate = 0;
3018 fmt = GET_RTX_FORMAT (code);
3019 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3022 check_eliminable_occurrences (XEXP (x, i));
3023 else if (*fmt == 'E')
3026 for (j = 0; j < XVECLEN (x, i); j++)
3027 check_eliminable_occurrences (XVECEXP (x, i, j));
3032 /* Scan INSN and eliminate all eliminable registers in it.
3034 If REPLACE is nonzero, do the replacement destructively. Also
3035 delete the insn as dead it if it is setting an eliminable register.
3037 If REPLACE is zero, do all our allocations in reload_obstack.
3039 If no eliminations were done and this insn doesn't require any elimination
3040 processing (these are not identical conditions: it might be updating sp,
3041 but not referencing fp; this needs to be seen during reload_as_needed so
3042 that the offset between fp and sp can be taken into consideration), zero
3043 is returned. Otherwise, 1 is returned. */
3046 eliminate_regs_in_insn (rtx insn, int replace)
3048 int icode = recog_memoized (insn);
3049 rtx old_body = PATTERN (insn);
3050 int insn_is_asm = asm_noperands (old_body) >= 0;
3051 rtx old_set = single_set (insn);
3055 rtx substed_operand[MAX_RECOG_OPERANDS];
3056 rtx orig_operand[MAX_RECOG_OPERANDS];
3057 struct elim_table *ep;
3058 rtx plus_src, plus_cst_src;
3060 if (! insn_is_asm && icode < 0)
3062 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3063 || GET_CODE (PATTERN (insn)) == CLOBBER
3064 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3065 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3066 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3070 if (old_set != 0 && REG_P (SET_DEST (old_set))
3071 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3073 /* Check for setting an eliminable register. */
3074 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3075 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3077 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3078 /* If this is setting the frame pointer register to the
3079 hardware frame pointer register and this is an elimination
3080 that will be done (tested above), this insn is really
3081 adjusting the frame pointer downward to compensate for
3082 the adjustment done before a nonlocal goto. */
3083 if (ep->from == FRAME_POINTER_REGNUM
3084 && ep->to == HARD_FRAME_POINTER_REGNUM)
3086 rtx base = SET_SRC (old_set);
3087 rtx base_insn = insn;
3088 HOST_WIDE_INT offset = 0;
3090 while (base != ep->to_rtx)
3092 rtx prev_insn, prev_set;
3094 if (GET_CODE (base) == PLUS
3095 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3097 offset += INTVAL (XEXP (base, 1));
3098 base = XEXP (base, 0);
3100 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3101 && (prev_set = single_set (prev_insn)) != 0
3102 && rtx_equal_p (SET_DEST (prev_set), base))
3104 base = SET_SRC (prev_set);
3105 base_insn = prev_insn;
3111 if (base == ep->to_rtx)
3114 = plus_constant (ep->to_rtx, offset - ep->offset);
3116 new_body = old_body;
3119 new_body = copy_insn (old_body);
3120 if (REG_NOTES (insn))
3121 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3123 PATTERN (insn) = new_body;
3124 old_set = single_set (insn);
3126 /* First see if this insn remains valid when we
3127 make the change. If not, keep the INSN_CODE
3128 the same and let reload fit it up. */
3129 validate_change (insn, &SET_SRC (old_set), src, 1);
3130 validate_change (insn, &SET_DEST (old_set),
3132 if (! apply_change_group ())
3134 SET_SRC (old_set) = src;
3135 SET_DEST (old_set) = ep->to_rtx;
3144 /* In this case this insn isn't serving a useful purpose. We
3145 will delete it in reload_as_needed once we know that this
3146 elimination is, in fact, being done.
3148 If REPLACE isn't set, we can't delete this insn, but needn't
3149 process it since it won't be used unless something changes. */
3152 delete_dead_insn (insn);
3160 /* We allow one special case which happens to work on all machines we
3161 currently support: a single set with the source or a REG_EQUAL
3162 note being a PLUS of an eliminable register and a constant. */
3163 plus_src = plus_cst_src = 0;
3164 if (old_set && REG_P (SET_DEST (old_set)))
3166 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3167 plus_src = SET_SRC (old_set);
3168 /* First see if the source is of the form (plus (...) CST). */
3170 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3171 plus_cst_src = plus_src;
3172 else if (REG_P (SET_SRC (old_set))
3175 /* Otherwise, see if we have a REG_EQUAL note of the form
3176 (plus (...) CST). */
3178 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3180 if ((REG_NOTE_KIND (links) == REG_EQUAL
3181 || REG_NOTE_KIND (links) == REG_EQUIV)
3182 && GET_CODE (XEXP (links, 0)) == PLUS
3183 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3185 plus_cst_src = XEXP (links, 0);
3191 /* Check that the first operand of the PLUS is a hard reg or
3192 the lowpart subreg of one. */
3195 rtx reg = XEXP (plus_cst_src, 0);
3196 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3197 reg = SUBREG_REG (reg);
3199 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3205 rtx reg = XEXP (plus_cst_src, 0);
3206 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3208 if (GET_CODE (reg) == SUBREG)
3209 reg = SUBREG_REG (reg);
3211 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3212 if (ep->from_rtx == reg && ep->can_eliminate)
3214 rtx to_rtx = ep->to_rtx;
3215 offset += ep->offset;
3216 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3218 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3219 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3221 /* If we have a nonzero offset, and the source is already
3222 a simple REG, the following transformation would
3223 increase the cost of the insn by replacing a simple REG
3224 with (plus (reg sp) CST). So try only when we already
3225 had a PLUS before. */
3226 if (offset == 0 || plus_src)
3228 rtx new_src = plus_constant (to_rtx, offset);
3230 new_body = old_body;
3233 new_body = copy_insn (old_body);
3234 if (REG_NOTES (insn))
3235 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3237 PATTERN (insn) = new_body;
3238 old_set = single_set (insn);
3240 /* First see if this insn remains valid when we make the
3241 change. If not, try to replace the whole pattern with
3242 a simple set (this may help if the original insn was a
3243 PARALLEL that was only recognized as single_set due to
3244 REG_UNUSED notes). If this isn't valid either, keep
3245 the INSN_CODE the same and let reload fix it up. */
3246 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3248 rtx new_pat = gen_rtx_SET (VOIDmode,
3249 SET_DEST (old_set), new_src);
3251 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3252 SET_SRC (old_set) = new_src;
3259 /* This can't have an effect on elimination offsets, so skip right
3265 /* Determine the effects of this insn on elimination offsets. */
3266 elimination_effects (old_body, 0);
3268 /* Eliminate all eliminable registers occurring in operands that
3269 can be handled by reload. */
3270 extract_insn (insn);
3271 for (i = 0; i < recog_data.n_operands; i++)
3273 orig_operand[i] = recog_data.operand[i];
3274 substed_operand[i] = recog_data.operand[i];
3276 /* For an asm statement, every operand is eliminable. */
3277 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3279 bool is_set_src, in_plus;
3281 /* Check for setting a register that we know about. */
3282 if (recog_data.operand_type[i] != OP_IN
3283 && REG_P (orig_operand[i]))
3285 /* If we are assigning to a register that can be eliminated, it
3286 must be as part of a PARALLEL, since the code above handles
3287 single SETs. We must indicate that we can no longer
3288 eliminate this reg. */
3289 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3291 if (ep->from_rtx == orig_operand[i])
3292 ep->can_eliminate = 0;
3295 /* Companion to the above plus substitution, we can allow
3296 invariants as the source of a plain move. */
3298 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3302 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3303 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3307 = eliminate_regs_1 (recog_data.operand[i], 0,
3308 replace ? insn : NULL_RTX,
3309 is_set_src || in_plus);
3310 if (substed_operand[i] != orig_operand[i])
3312 /* Terminate the search in check_eliminable_occurrences at
3314 *recog_data.operand_loc[i] = 0;
3316 /* If an output operand changed from a REG to a MEM and INSN is an
3317 insn, write a CLOBBER insn. */
3318 if (recog_data.operand_type[i] != OP_IN
3319 && REG_P (orig_operand[i])
3320 && MEM_P (substed_operand[i])
3322 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3326 for (i = 0; i < recog_data.n_dups; i++)
3327 *recog_data.dup_loc[i]
3328 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3330 /* If any eliminable remain, they aren't eliminable anymore. */
3331 check_eliminable_occurrences (old_body);
3333 /* Substitute the operands; the new values are in the substed_operand
3335 for (i = 0; i < recog_data.n_operands; i++)
3336 *recog_data.operand_loc[i] = substed_operand[i];
3337 for (i = 0; i < recog_data.n_dups; i++)
3338 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3340 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3341 re-recognize the insn. We do this in case we had a simple addition
3342 but now can do this as a load-address. This saves an insn in this
3344 If re-recognition fails, the old insn code number will still be used,
3345 and some register operands may have changed into PLUS expressions.
3346 These will be handled by find_reloads by loading them into a register
3351 /* If we aren't replacing things permanently and we changed something,
3352 make another copy to ensure that all the RTL is new. Otherwise
3353 things can go wrong if find_reload swaps commutative operands
3354 and one is inside RTL that has been copied while the other is not. */
3355 new_body = old_body;
3358 new_body = copy_insn (old_body);
3359 if (REG_NOTES (insn))
3360 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3362 PATTERN (insn) = new_body;
3364 /* If we had a move insn but now we don't, rerecognize it. This will
3365 cause spurious re-recognition if the old move had a PARALLEL since
3366 the new one still will, but we can't call single_set without
3367 having put NEW_BODY into the insn and the re-recognition won't
3368 hurt in this rare case. */
3369 /* ??? Why this huge if statement - why don't we just rerecognize the
3373 && ((REG_P (SET_SRC (old_set))
3374 && (GET_CODE (new_body) != SET
3375 || !REG_P (SET_SRC (new_body))))
3376 /* If this was a load from or store to memory, compare
3377 the MEM in recog_data.operand to the one in the insn.
3378 If they are not equal, then rerecognize the insn. */
3380 && ((MEM_P (SET_SRC (old_set))
3381 && SET_SRC (old_set) != recog_data.operand[1])
3382 || (MEM_P (SET_DEST (old_set))
3383 && SET_DEST (old_set) != recog_data.operand[0])))
3384 /* If this was an add insn before, rerecognize. */
3385 || GET_CODE (SET_SRC (old_set)) == PLUS))
3387 int new_icode = recog (PATTERN (insn), insn, 0);
3389 INSN_CODE (insn) = new_icode;
3393 /* Restore the old body. If there were any changes to it, we made a copy
3394 of it while the changes were still in place, so we'll correctly return
3395 a modified insn below. */
3398 /* Restore the old body. */
3399 for (i = 0; i < recog_data.n_operands; i++)
3400 *recog_data.operand_loc[i] = orig_operand[i];
3401 for (i = 0; i < recog_data.n_dups; i++)
3402 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3405 /* Update all elimination pairs to reflect the status after the current
3406 insn. The changes we make were determined by the earlier call to
3407 elimination_effects.
3409 We also detect cases where register elimination cannot be done,
3410 namely, if a register would be both changed and referenced outside a MEM
3411 in the resulting insn since such an insn is often undefined and, even if
3412 not, we cannot know what meaning will be given to it. Note that it is
3413 valid to have a register used in an address in an insn that changes it
3414 (presumably with a pre- or post-increment or decrement).
3416 If anything changes, return nonzero. */
3418 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3420 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3421 ep->can_eliminate = 0;
3423 ep->ref_outside_mem = 0;
3425 if (ep->previous_offset != ep->offset)
3430 /* If we changed something, perform elimination in REG_NOTES. This is
3431 needed even when REPLACE is zero because a REG_DEAD note might refer
3432 to a register that we eliminate and could cause a different number
3433 of spill registers to be needed in the final reload pass than in
3435 if (val && REG_NOTES (insn) != 0)
3437 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3442 /* Loop through all elimination pairs.
3443 Recalculate the number not at initial offset.
3445 Compute the maximum offset (minimum offset if the stack does not
3446 grow downward) for each elimination pair. */
3449 update_eliminable_offsets (void)
3451 struct elim_table *ep;
3453 num_not_at_initial_offset = 0;
3454 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3456 ep->previous_offset = ep->offset;
3457 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3458 num_not_at_initial_offset++;
3462 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3463 replacement we currently believe is valid, mark it as not eliminable if X
3464 modifies DEST in any way other than by adding a constant integer to it.
3466 If DEST is the frame pointer, we do nothing because we assume that
3467 all assignments to the hard frame pointer are nonlocal gotos and are being
3468 done at a time when they are valid and do not disturb anything else.
3469 Some machines want to eliminate a fake argument pointer with either the
3470 frame or stack pointer. Assignments to the hard frame pointer must not
3471 prevent this elimination.
3473 Called via note_stores from reload before starting its passes to scan
3474 the insns of the function. */
3477 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3481 /* A SUBREG of a hard register here is just changing its mode. We should
3482 not see a SUBREG of an eliminable hard register, but check just in
3484 if (GET_CODE (dest) == SUBREG)
3485 dest = SUBREG_REG (dest);
3487 if (dest == hard_frame_pointer_rtx)
3490 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3491 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3492 && (GET_CODE (x) != SET
3493 || GET_CODE (SET_SRC (x)) != PLUS
3494 || XEXP (SET_SRC (x), 0) != dest
3495 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3497 reg_eliminate[i].can_eliminate_previous
3498 = reg_eliminate[i].can_eliminate = 0;
3503 /* Verify that the initial elimination offsets did not change since the
3504 last call to set_initial_elim_offsets. This is used to catch cases
3505 where something illegal happened during reload_as_needed that could
3506 cause incorrect code to be generated if we did not check for it. */
3509 verify_initial_elim_offsets (void)
3513 if (!num_eliminable)
3516 #ifdef ELIMINABLE_REGS
3518 struct elim_table *ep;
3520 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3522 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3523 if (t != ep->initial_offset)
3528 INITIAL_FRAME_POINTER_OFFSET (t);
3529 if (t != reg_eliminate[0].initial_offset)
3536 /* Reset all offsets on eliminable registers to their initial values. */
3539 set_initial_elim_offsets (void)
3541 struct elim_table *ep = reg_eliminate;
3543 #ifdef ELIMINABLE_REGS
3544 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3546 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3547 ep->previous_offset = ep->offset = ep->initial_offset;
3550 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3551 ep->previous_offset = ep->offset = ep->initial_offset;
3554 num_not_at_initial_offset = 0;
3557 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3560 set_initial_eh_label_offset (rtx label)
3562 set_label_offsets (label, NULL_RTX, 1);
3565 /* Initialize the known label offsets.
3566 Set a known offset for each forced label to be at the initial offset
3567 of each elimination. We do this because we assume that all
3568 computed jumps occur from a location where each elimination is
3569 at its initial offset.
3570 For all other labels, show that we don't know the offsets. */
3573 set_initial_label_offsets (void)
3576 memset (offsets_known_at, 0, num_labels);
3578 for (x = forced_labels; x; x = XEXP (x, 1))
3580 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3582 for_each_eh_label (set_initial_eh_label_offset);
3585 /* Set all elimination offsets to the known values for the code label given
3589 set_offsets_for_label (rtx insn)
3592 int label_nr = CODE_LABEL_NUMBER (insn);
3593 struct elim_table *ep;
3595 num_not_at_initial_offset = 0;
3596 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3598 ep->offset = ep->previous_offset
3599 = offsets_at[label_nr - first_label_num][i];
3600 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3601 num_not_at_initial_offset++;
3605 /* See if anything that happened changes which eliminations are valid.
3606 For example, on the SPARC, whether or not the frame pointer can
3607 be eliminated can depend on what registers have been used. We need
3608 not check some conditions again (such as flag_omit_frame_pointer)
3609 since they can't have changed. */
3612 update_eliminables (HARD_REG_SET *pset)
3614 int previous_frame_pointer_needed = frame_pointer_needed;
3615 struct elim_table *ep;
3617 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3618 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3619 #ifdef ELIMINABLE_REGS
3620 || ! CAN_ELIMINATE (ep->from, ep->to)
3623 ep->can_eliminate = 0;
3625 /* Look for the case where we have discovered that we can't replace
3626 register A with register B and that means that we will now be
3627 trying to replace register A with register C. This means we can
3628 no longer replace register C with register B and we need to disable
3629 such an elimination, if it exists. This occurs often with A == ap,
3630 B == sp, and C == fp. */
3632 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3634 struct elim_table *op;
3637 if (! ep->can_eliminate && ep->can_eliminate_previous)
3639 /* Find the current elimination for ep->from, if there is a
3641 for (op = reg_eliminate;
3642 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3643 if (op->from == ep->from && op->can_eliminate)
3649 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3651 for (op = reg_eliminate;
3652 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3653 if (op->from == new_to && op->to == ep->to)
3654 op->can_eliminate = 0;
3658 /* See if any registers that we thought we could eliminate the previous
3659 time are no longer eliminable. If so, something has changed and we
3660 must spill the register. Also, recompute the number of eliminable
3661 registers and see if the frame pointer is needed; it is if there is
3662 no elimination of the frame pointer that we can perform. */
3664 frame_pointer_needed = 1;
3665 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3667 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3668 && ep->to != HARD_FRAME_POINTER_REGNUM)
3669 frame_pointer_needed = 0;
3671 if (! ep->can_eliminate && ep->can_eliminate_previous)
3673 ep->can_eliminate_previous = 0;
3674 SET_HARD_REG_BIT (*pset, ep->from);
3679 /* If we didn't need a frame pointer last time, but we do now, spill
3680 the hard frame pointer. */
3681 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3682 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3685 /* Return true if X is used as the target register of an elimination. */
3688 elimination_target_reg_p (rtx x)
3690 struct elim_table *ep;
3692 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3693 if (ep->to_rtx == x && ep->can_eliminate)
3699 /* Initialize the table of registers to eliminate. */
3702 init_elim_table (void)
3704 struct elim_table *ep;
3705 #ifdef ELIMINABLE_REGS
3706 const struct elim_table_1 *ep1;
3710 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3712 /* Does this function require a frame pointer? */
3714 frame_pointer_needed = (! flag_omit_frame_pointer
3715 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3716 and restore sp for alloca. So we can't eliminate
3717 the frame pointer in that case. At some point,
3718 we should improve this by emitting the
3719 sp-adjusting insns for this case. */
3720 || (cfun->calls_alloca
3721 && EXIT_IGNORE_STACK)
3722 || crtl->accesses_prior_frames
3723 || FRAME_POINTER_REQUIRED);
3727 #ifdef ELIMINABLE_REGS
3728 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3729 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3731 ep->from = ep1->from;
3733 ep->can_eliminate = ep->can_eliminate_previous
3734 = (CAN_ELIMINATE (ep->from, ep->to)
3735 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3738 reg_eliminate[0].from = reg_eliminate_1[0].from;
3739 reg_eliminate[0].to = reg_eliminate_1[0].to;
3740 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3741 = ! frame_pointer_needed;
3744 /* Count the number of eliminable registers and build the FROM and TO
3745 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3746 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3747 We depend on this. */
3748 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3750 num_eliminable += ep->can_eliminate;
3751 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3752 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3756 /* Kick all pseudos out of hard register REGNO.
3758 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3759 because we found we can't eliminate some register. In the case, no pseudos
3760 are allowed to be in the register, even if they are only in a block that
3761 doesn't require spill registers, unlike the case when we are spilling this
3762 hard reg to produce another spill register.
3764 Return nonzero if any pseudos needed to be kicked out. */
3767 spill_hard_reg (unsigned int regno, int cant_eliminate)
3773 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3774 df_set_regs_ever_live (regno, true);
3777 /* Spill every pseudo reg that was allocated to this reg
3778 or to something that overlaps this reg. */
3780 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3781 if (reg_renumber[i] >= 0
3782 && (unsigned int) reg_renumber[i] <= regno
3783 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3784 SET_REGNO_REG_SET (&spilled_pseudos, i);
3787 /* After find_reload_regs has been run for all insn that need reloads,
3788 and/or spill_hard_regs was called, this function is used to actually
3789 spill pseudo registers and try to reallocate them. It also sets up the
3790 spill_regs array for use by choose_reload_regs. */
3793 finish_spills (int global)
3795 struct insn_chain *chain;
3796 int something_changed = 0;
3798 reg_set_iterator rsi;
3800 /* Build the spill_regs array for the function. */
3801 /* If there are some registers still to eliminate and one of the spill regs
3802 wasn't ever used before, additional stack space may have to be
3803 allocated to store this register. Thus, we may have changed the offset
3804 between the stack and frame pointers, so mark that something has changed.
3806 One might think that we need only set VAL to 1 if this is a call-used
3807 register. However, the set of registers that must be saved by the
3808 prologue is not identical to the call-used set. For example, the
3809 register used by the call insn for the return PC is a call-used register,
3810 but must be saved by the prologue. */
3813 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3814 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3816 spill_reg_order[i] = n_spills;
3817 spill_regs[n_spills++] = i;
3818 if (num_eliminable && ! df_regs_ever_live_p (i))
3819 something_changed = 1;
3820 df_set_regs_ever_live (i, true);
3823 spill_reg_order[i] = -1;
3825 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3827 /* Record the current hard register the pseudo is allocated to in
3828 pseudo_previous_regs so we avoid reallocating it to the same
3829 hard reg in a later pass. */
3830 gcc_assert (reg_renumber[i] >= 0);
3832 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3833 /* Mark it as no longer having a hard register home. */
3834 reg_renumber[i] = -1;
3835 /* We will need to scan everything again. */
3836 something_changed = 1;
3839 /* Retry global register allocation if possible. */
3842 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3843 /* For every insn that needs reloads, set the registers used as spill
3844 regs in pseudo_forbidden_regs for every pseudo live across the
3846 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3848 EXECUTE_IF_SET_IN_REG_SET
3849 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3851 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3852 chain->used_spill_regs);
3854 EXECUTE_IF_SET_IN_REG_SET
3855 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3857 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3858 chain->used_spill_regs);
3862 /* Retry allocating the spilled pseudos. For each reg, merge the
3863 various reg sets that indicate which hard regs can't be used,
3864 and call retry_global_alloc.
3865 We change spill_pseudos here to only contain pseudos that did not
3866 get a new hard register. */
3867 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3868 if (reg_old_renumber[i] != reg_renumber[i])
3870 HARD_REG_SET forbidden;
3871 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3872 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3873 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3874 retry_global_alloc (i, forbidden);
3875 if (reg_renumber[i] >= 0)
3876 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3880 /* Fix up the register information in the insn chain.
3881 This involves deleting those of the spilled pseudos which did not get
3882 a new hard register home from the live_{before,after} sets. */
3883 for (chain = reload_insn_chain; chain; chain = chain->next)
3885 HARD_REG_SET used_by_pseudos;
3886 HARD_REG_SET used_by_pseudos2;
3888 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3889 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3891 /* Mark any unallocated hard regs as available for spills. That
3892 makes inheritance work somewhat better. */
3893 if (chain->need_reload)
3895 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3896 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3897 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3899 /* Save the old value for the sanity test below. */
3900 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3902 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3903 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3904 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3905 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3907 /* Make sure we only enlarge the set. */
3908 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3909 chain->used_spill_regs));
3913 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3914 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3916 int regno = reg_renumber[i];
3917 if (reg_old_renumber[i] == regno)
3920 alter_reg (i, reg_old_renumber[i]);
3921 reg_old_renumber[i] = regno;
3925 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3927 fprintf (dump_file, " Register %d now in %d.\n\n",
3928 i, reg_renumber[i]);
3932 return something_changed;
3935 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3938 scan_paradoxical_subregs (rtx x)
3942 enum rtx_code code = GET_CODE (x);
3953 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3961 if (REG_P (SUBREG_REG (x))
3962 && (GET_MODE_SIZE (GET_MODE (x))
3963 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3965 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3966 = GET_MODE_SIZE (GET_MODE (x));
3967 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3975 fmt = GET_RTX_FORMAT (code);
3976 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3979 scan_paradoxical_subregs (XEXP (x, i));
3980 else if (fmt[i] == 'E')
3983 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3984 scan_paradoxical_subregs (XVECEXP (x, i, j));
3989 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3990 examine all of the reload insns between PREV and NEXT exclusive, and
3991 annotate all that may trap. */
3994 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3996 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3997 unsigned int trap_count;
4003 if (may_trap_p (PATTERN (insn)))
4007 remove_note (insn, note);
4011 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4012 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4016 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4020 /* Reload pseudo-registers into hard regs around each insn as needed.
4021 Additional register load insns are output before the insn that needs it
4022 and perhaps store insns after insns that modify the reloaded pseudo reg.
4024 reg_last_reload_reg and reg_reloaded_contents keep track of
4025 which registers are already available in reload registers.
4026 We update these for the reloads that we perform,
4027 as the insns are scanned. */
4030 reload_as_needed (int live_known)
4032 struct insn_chain *chain;
4033 #if defined (AUTO_INC_DEC)
4038 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4039 memset (spill_reg_store, 0, sizeof spill_reg_store);
4040 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4041 INIT_REG_SET (®_has_output_reload);
4042 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4043 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4045 set_initial_elim_offsets ();
4047 for (chain = reload_insn_chain; chain; chain = chain->next)
4050 rtx insn = chain->insn;
4051 rtx old_next = NEXT_INSN (insn);
4053 /* If we pass a label, copy the offsets from the label information
4054 into the current offsets of each elimination. */
4056 set_offsets_for_label (insn);
4058 else if (INSN_P (insn))
4060 regset_head regs_to_forget;
4061 INIT_REG_SET (®s_to_forget);
4062 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4064 /* If this is a USE and CLOBBER of a MEM, ensure that any
4065 references to eliminable registers have been removed. */
4067 if ((GET_CODE (PATTERN (insn)) == USE
4068 || GET_CODE (PATTERN (insn)) == CLOBBER)
4069 && MEM_P (XEXP (PATTERN (insn), 0)))
4070 XEXP (XEXP (PATTERN (insn), 0), 0)
4071 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4072 GET_MODE (XEXP (PATTERN (insn), 0)),
4075 /* If we need to do register elimination processing, do so.
4076 This might delete the insn, in which case we are done. */
4077 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4079 eliminate_regs_in_insn (insn, 1);
4082 update_eliminable_offsets ();
4083 CLEAR_REG_SET (®s_to_forget);
4088 /* If need_elim is nonzero but need_reload is zero, one might think
4089 that we could simply set n_reloads to 0. However, find_reloads
4090 could have done some manipulation of the insn (such as swapping
4091 commutative operands), and these manipulations are lost during
4092 the first pass for every insn that needs register elimination.
4093 So the actions of find_reloads must be redone here. */
4095 if (! chain->need_elim && ! chain->need_reload
4096 && ! chain->need_operand_change)
4098 /* First find the pseudo regs that must be reloaded for this insn.
4099 This info is returned in the tables reload_... (see reload.h).
4100 Also modify the body of INSN by substituting RELOAD
4101 rtx's for those pseudo regs. */
4104 CLEAR_REG_SET (®_has_output_reload);
4105 CLEAR_HARD_REG_SET (reg_is_output_reload);
4107 find_reloads (insn, 1, spill_indirect_levels, live_known,
4113 rtx next = NEXT_INSN (insn);
4116 prev = PREV_INSN (insn);
4118 /* Now compute which reload regs to reload them into. Perhaps
4119 reusing reload regs from previous insns, or else output
4120 load insns to reload them. Maybe output store insns too.
4121 Record the choices of reload reg in reload_reg_rtx. */
4122 choose_reload_regs (chain);
4124 /* Merge any reloads that we didn't combine for fear of
4125 increasing the number of spill registers needed but now
4126 discover can be safely merged. */
4127 if (SMALL_REGISTER_CLASSES)
4128 merge_assigned_reloads (insn);
4130 /* Generate the insns to reload operands into or out of
4131 their reload regs. */
4132 emit_reload_insns (chain);
4134 /* Substitute the chosen reload regs from reload_reg_rtx
4135 into the insn's body (or perhaps into the bodies of other
4136 load and store insn that we just made for reloading
4137 and that we moved the structure into). */
4138 subst_reloads (insn);
4140 /* Adjust the exception region notes for loads and stores. */
4141 if (flag_non_call_exceptions && !CALL_P (insn))
4142 fixup_eh_region_note (insn, prev, next);
4144 /* If this was an ASM, make sure that all the reload insns
4145 we have generated are valid. If not, give an error
4147 if (asm_noperands (PATTERN (insn)) >= 0)
4148 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4149 if (p != insn && INSN_P (p)
4150 && GET_CODE (PATTERN (p)) != USE
4151 && (recog_memoized (p) < 0
4152 || (extract_insn (p), ! constrain_operands (1))))
4154 error_for_asm (insn,
4155 "%<asm%> operand requires "
4156 "impossible reload");
4161 if (num_eliminable && chain->need_elim)
4162 update_eliminable_offsets ();
4164 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4165 is no longer validly lying around to save a future reload.
4166 Note that this does not detect pseudos that were reloaded
4167 for this insn in order to be stored in
4168 (obeying register constraints). That is correct; such reload
4169 registers ARE still valid. */
4170 forget_marked_reloads (®s_to_forget);
4171 CLEAR_REG_SET (®s_to_forget);
4173 /* There may have been CLOBBER insns placed after INSN. So scan
4174 between INSN and NEXT and use them to forget old reloads. */
4175 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4176 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4177 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4180 /* Likewise for regs altered by auto-increment in this insn.
4181 REG_INC notes have been changed by reloading:
4182 find_reloads_address_1 records substitutions for them,
4183 which have been performed by subst_reloads above. */
4184 for (i = n_reloads - 1; i >= 0; i--)
4186 rtx in_reg = rld[i].in_reg;
4189 enum rtx_code code = GET_CODE (in_reg);
4190 /* PRE_INC / PRE_DEC will have the reload register ending up
4191 with the same value as the stack slot, but that doesn't
4192 hold true for POST_INC / POST_DEC. Either we have to
4193 convert the memory access to a true POST_INC / POST_DEC,
4194 or we can't use the reload register for inheritance. */
4195 if ((code == POST_INC || code == POST_DEC)
4196 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4197 REGNO (rld[i].reg_rtx))
4198 /* Make sure it is the inc/dec pseudo, and not
4199 some other (e.g. output operand) pseudo. */
4200 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4201 == REGNO (XEXP (in_reg, 0))))
4204 rtx reload_reg = rld[i].reg_rtx;
4205 enum machine_mode mode = GET_MODE (reload_reg);
4209 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4211 /* We really want to ignore REG_INC notes here, so
4212 use PATTERN (p) as argument to reg_set_p . */
4213 if (reg_set_p (reload_reg, PATTERN (p)))
4215 n = count_occurrences (PATTERN (p), reload_reg, 0);
4220 n = validate_replace_rtx (reload_reg,
4221 gen_rtx_fmt_e (code,
4226 /* We must also verify that the constraints
4227 are met after the replacement. */
4230 n = constrain_operands (1);
4234 /* If the constraints were not met, then
4235 undo the replacement. */
4238 validate_replace_rtx (gen_rtx_fmt_e (code,
4251 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4253 /* Mark this as having an output reload so that the
4254 REG_INC processing code below won't invalidate
4255 the reload for inheritance. */
4256 SET_HARD_REG_BIT (reg_is_output_reload,
4257 REGNO (reload_reg));
4258 SET_REGNO_REG_SET (®_has_output_reload,
4259 REGNO (XEXP (in_reg, 0)));
4262 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4265 else if ((code == PRE_INC || code == PRE_DEC)
4266 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4267 REGNO (rld[i].reg_rtx))
4268 /* Make sure it is the inc/dec pseudo, and not
4269 some other (e.g. output operand) pseudo. */
4270 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4271 == REGNO (XEXP (in_reg, 0))))
4273 SET_HARD_REG_BIT (reg_is_output_reload,
4274 REGNO (rld[i].reg_rtx));
4275 SET_REGNO_REG_SET (®_has_output_reload,
4276 REGNO (XEXP (in_reg, 0)));
4280 /* If a pseudo that got a hard register is auto-incremented,
4281 we must purge records of copying it into pseudos without
4283 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4284 if (REG_NOTE_KIND (x) == REG_INC)
4286 /* See if this pseudo reg was reloaded in this insn.
4287 If so, its last-reload info is still valid
4288 because it is based on this insn's reload. */
4289 for (i = 0; i < n_reloads; i++)
4290 if (rld[i].out == XEXP (x, 0))
4294 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4298 /* A reload reg's contents are unknown after a label. */
4300 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4302 /* Don't assume a reload reg is still good after a call insn
4303 if it is a call-used reg, or if it contains a value that will
4304 be partially clobbered by the call. */
4305 else if (CALL_P (insn))
4307 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4308 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4313 free (reg_last_reload_reg);
4314 CLEAR_REG_SET (®_has_output_reload);
4317 /* Discard all record of any value reloaded from X,
4318 or reloaded in X from someplace else;
4319 unless X is an output reload reg of the current insn.
4321 X may be a hard reg (the reload reg)
4322 or it may be a pseudo reg that was reloaded from.
4324 When DATA is non-NULL just mark the registers in regset
4325 to be forgotten later. */
4328 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4333 regset regs = (regset) data;
4335 /* note_stores does give us subregs of hard regs,
4336 subreg_regno_offset requires a hard reg. */
4337 while (GET_CODE (x) == SUBREG)
4339 /* We ignore the subreg offset when calculating the regno,
4340 because we are using the entire underlying hard register
4350 if (regno >= FIRST_PSEUDO_REGISTER)
4356 nr = hard_regno_nregs[regno][GET_MODE (x)];
4357 /* Storing into a spilled-reg invalidates its contents.
4358 This can happen if a block-local pseudo is allocated to that reg
4359 and it wasn't spilled because this block's total need is 0.
4360 Then some insn might have an optional reload and use this reg. */
4362 for (i = 0; i < nr; i++)
4363 /* But don't do this if the reg actually serves as an output
4364 reload reg in the current instruction. */
4366 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4368 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4369 spill_reg_store[regno + i] = 0;
4375 SET_REGNO_REG_SET (regs, regno + nr);
4378 /* Since value of X has changed,
4379 forget any value previously copied from it. */
4382 /* But don't forget a copy if this is the output reload
4383 that establishes the copy's validity. */
4385 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4386 reg_last_reload_reg[regno + nr] = 0;
4390 /* Forget the reloads marked in regset by previous function. */
4392 forget_marked_reloads (regset regs)
4395 reg_set_iterator rsi;
4396 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4398 if (reg < FIRST_PSEUDO_REGISTER
4399 /* But don't do this if the reg actually serves as an output
4400 reload reg in the current instruction. */
4402 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4404 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4405 spill_reg_store[reg] = 0;
4408 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4409 reg_last_reload_reg[reg] = 0;
4413 /* The following HARD_REG_SETs indicate when each hard register is
4414 used for a reload of various parts of the current insn. */
4416 /* If reg is unavailable for all reloads. */
4417 static HARD_REG_SET reload_reg_unavailable;
4418 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4419 static HARD_REG_SET reload_reg_used;
4420 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4421 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4422 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4423 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4424 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4425 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4426 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4427 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4428 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4429 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4430 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4431 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4432 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4433 static HARD_REG_SET reload_reg_used_in_op_addr;
4434 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4435 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4436 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4437 static HARD_REG_SET reload_reg_used_in_insn;
4438 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4439 static HARD_REG_SET reload_reg_used_in_other_addr;
4441 /* If reg is in use as a reload reg for any sort of reload. */
4442 static HARD_REG_SET reload_reg_used_at_all;
4444 /* If reg is use as an inherited reload. We just mark the first register
4446 static HARD_REG_SET reload_reg_used_for_inherit;
4448 /* Records which hard regs are used in any way, either as explicit use or
4449 by being allocated to a pseudo during any point of the current insn. */
4450 static HARD_REG_SET reg_used_in_insn;
4452 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4453 TYPE. MODE is used to indicate how many consecutive regs are
4457 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4458 enum machine_mode mode)
4460 unsigned int nregs = hard_regno_nregs[regno][mode];
4463 for (i = regno; i < nregs + regno; i++)
4468 SET_HARD_REG_BIT (reload_reg_used, i);
4471 case RELOAD_FOR_INPUT_ADDRESS:
4472 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4475 case RELOAD_FOR_INPADDR_ADDRESS:
4476 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4479 case RELOAD_FOR_OUTPUT_ADDRESS:
4480 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4483 case RELOAD_FOR_OUTADDR_ADDRESS:
4484 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4487 case RELOAD_FOR_OPERAND_ADDRESS:
4488 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4491 case RELOAD_FOR_OPADDR_ADDR:
4492 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4495 case RELOAD_FOR_OTHER_ADDRESS:
4496 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4499 case RELOAD_FOR_INPUT:
4500 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4503 case RELOAD_FOR_OUTPUT:
4504 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4507 case RELOAD_FOR_INSN:
4508 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4512 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4516 /* Similarly, but show REGNO is no longer in use for a reload. */
4519 clear_reload_reg_in_use (unsigned int regno, int opnum,
4520 enum reload_type type, enum machine_mode mode)
4522 unsigned int nregs = hard_regno_nregs[regno][mode];
4523 unsigned int start_regno, end_regno, r;
4525 /* A complication is that for some reload types, inheritance might
4526 allow multiple reloads of the same types to share a reload register.
4527 We set check_opnum if we have to check only reloads with the same
4528 operand number, and check_any if we have to check all reloads. */
4529 int check_opnum = 0;
4531 HARD_REG_SET *used_in_set;
4536 used_in_set = &reload_reg_used;
4539 case RELOAD_FOR_INPUT_ADDRESS:
4540 used_in_set = &reload_reg_used_in_input_addr[opnum];
4543 case RELOAD_FOR_INPADDR_ADDRESS:
4545 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4548 case RELOAD_FOR_OUTPUT_ADDRESS:
4549 used_in_set = &reload_reg_used_in_output_addr[opnum];
4552 case RELOAD_FOR_OUTADDR_ADDRESS:
4554 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4557 case RELOAD_FOR_OPERAND_ADDRESS:
4558 used_in_set = &reload_reg_used_in_op_addr;
4561 case RELOAD_FOR_OPADDR_ADDR:
4563 used_in_set = &reload_reg_used_in_op_addr_reload;
4566 case RELOAD_FOR_OTHER_ADDRESS:
4567 used_in_set = &reload_reg_used_in_other_addr;
4571 case RELOAD_FOR_INPUT:
4572 used_in_set = &reload_reg_used_in_input[opnum];
4575 case RELOAD_FOR_OUTPUT:
4576 used_in_set = &reload_reg_used_in_output[opnum];
4579 case RELOAD_FOR_INSN:
4580 used_in_set = &reload_reg_used_in_insn;
4585 /* We resolve conflicts with remaining reloads of the same type by
4586 excluding the intervals of reload registers by them from the
4587 interval of freed reload registers. Since we only keep track of
4588 one set of interval bounds, we might have to exclude somewhat
4589 more than what would be necessary if we used a HARD_REG_SET here.
4590 But this should only happen very infrequently, so there should
4591 be no reason to worry about it. */
4593 start_regno = regno;
4594 end_regno = regno + nregs;
4595 if (check_opnum || check_any)
4597 for (i = n_reloads - 1; i >= 0; i--)
4599 if (rld[i].when_needed == type
4600 && (check_any || rld[i].opnum == opnum)
4603 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4604 unsigned int conflict_end
4605 = end_hard_regno (rld[i].mode, conflict_start);
4607 /* If there is an overlap with the first to-be-freed register,
4608 adjust the interval start. */
4609 if (conflict_start <= start_regno && conflict_end > start_regno)
4610 start_regno = conflict_end;
4611 /* Otherwise, if there is a conflict with one of the other
4612 to-be-freed registers, adjust the interval end. */
4613 if (conflict_start > start_regno && conflict_start < end_regno)
4614 end_regno = conflict_start;
4619 for (r = start_regno; r < end_regno; r++)
4620 CLEAR_HARD_REG_BIT (*used_in_set, r);
4623 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4624 specified by OPNUM and TYPE. */
4627 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4631 /* In use for a RELOAD_OTHER means it's not available for anything. */
4632 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4633 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4639 /* In use for anything means we can't use it for RELOAD_OTHER. */
4640 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4641 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4646 for (i = 0; i < reload_n_operands; i++)
4647 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4649 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4650 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4651 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4652 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4657 case RELOAD_FOR_INPUT:
4658 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4659 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4662 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4665 /* If it is used for some other input, can't use it. */
4666 for (i = 0; i < reload_n_operands; i++)
4667 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4670 /* If it is used in a later operand's address, can't use it. */
4671 for (i = opnum + 1; i < reload_n_operands; i++)
4672 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4673 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4678 case RELOAD_FOR_INPUT_ADDRESS:
4679 /* Can't use a register if it is used for an input address for this
4680 operand or used as an input in an earlier one. */
4681 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4682 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4685 for (i = 0; i < opnum; i++)
4686 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4691 case RELOAD_FOR_INPADDR_ADDRESS:
4692 /* Can't use a register if it is used for an input address
4693 for this operand or used as an input in an earlier
4695 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4698 for (i = 0; i < opnum; i++)
4699 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4704 case RELOAD_FOR_OUTPUT_ADDRESS:
4705 /* Can't use a register if it is used for an output address for this
4706 operand or used as an output in this or a later operand. Note
4707 that multiple output operands are emitted in reverse order, so
4708 the conflicting ones are those with lower indices. */
4709 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4712 for (i = 0; i <= opnum; i++)
4713 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4718 case RELOAD_FOR_OUTADDR_ADDRESS:
4719 /* Can't use a register if it is used for an output address
4720 for this operand or used as an output in this or a
4721 later operand. Note that multiple output operands are
4722 emitted in reverse order, so the conflicting ones are
4723 those with lower indices. */
4724 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4727 for (i = 0; i <= opnum; i++)
4728 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4733 case RELOAD_FOR_OPERAND_ADDRESS:
4734 for (i = 0; i < reload_n_operands; i++)
4735 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4738 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4739 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4741 case RELOAD_FOR_OPADDR_ADDR:
4742 for (i = 0; i < reload_n_operands; i++)
4743 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4746 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4748 case RELOAD_FOR_OUTPUT:
4749 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4750 outputs, or an operand address for this or an earlier output.
4751 Note that multiple output operands are emitted in reverse order,
4752 so the conflicting ones are those with higher indices. */
4753 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4756 for (i = 0; i < reload_n_operands; i++)
4757 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4760 for (i = opnum; i < reload_n_operands; i++)
4761 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4762 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4767 case RELOAD_FOR_INSN:
4768 for (i = 0; i < reload_n_operands; i++)
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4773 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4774 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4776 case RELOAD_FOR_OTHER_ADDRESS:
4777 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4784 /* Return 1 if the value in reload reg REGNO, as used by a reload
4785 needed for the part of the insn specified by OPNUM and TYPE,
4786 is still available in REGNO at the end of the insn.
4788 We can assume that the reload reg was already tested for availability
4789 at the time it is needed, and we should not check this again,
4790 in case the reg has already been marked in use. */
4793 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4800 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4801 its value must reach the end. */
4804 /* If this use is for part of the insn,
4805 its value reaches if no subsequent part uses the same register.
4806 Just like the above function, don't try to do this with lots
4809 case RELOAD_FOR_OTHER_ADDRESS:
4810 /* Here we check for everything else, since these don't conflict
4811 with anything else and everything comes later. */
4813 for (i = 0; i < reload_n_operands; i++)
4814 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4815 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4816 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4817 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4818 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4819 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4822 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4823 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4824 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4825 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4827 case RELOAD_FOR_INPUT_ADDRESS:
4828 case RELOAD_FOR_INPADDR_ADDRESS:
4829 /* Similar, except that we check only for this and subsequent inputs
4830 and the address of only subsequent inputs and we do not need
4831 to check for RELOAD_OTHER objects since they are known not to
4834 for (i = opnum; i < reload_n_operands; i++)
4835 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4838 for (i = opnum + 1; i < reload_n_operands; i++)
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4843 for (i = 0; i < reload_n_operands; i++)
4844 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4845 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4846 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4852 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4853 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4854 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4856 case RELOAD_FOR_INPUT:
4857 /* Similar to input address, except we start at the next operand for
4858 both input and input address and we do not check for
4859 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4862 for (i = opnum + 1; i < reload_n_operands; i++)
4863 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4865 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4868 /* ... fall through ... */
4870 case RELOAD_FOR_OPERAND_ADDRESS:
4871 /* Check outputs and their addresses. */
4873 for (i = 0; i < reload_n_operands; i++)
4874 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4875 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4876 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4879 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4881 case RELOAD_FOR_OPADDR_ADDR:
4882 for (i = 0; i < reload_n_operands; i++)
4883 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4884 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4885 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4888 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4889 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4890 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4892 case RELOAD_FOR_INSN:
4893 /* These conflict with other outputs with RELOAD_OTHER. So
4894 we need only check for output addresses. */
4896 opnum = reload_n_operands;
4898 /* ... fall through ... */
4900 case RELOAD_FOR_OUTPUT:
4901 case RELOAD_FOR_OUTPUT_ADDRESS:
4902 case RELOAD_FOR_OUTADDR_ADDRESS:
4903 /* We already know these can't conflict with a later output. So the
4904 only thing to check are later output addresses.
4905 Note that multiple output operands are emitted in reverse order,
4906 so the conflicting ones are those with lower indices. */
4907 for (i = 0; i < opnum; i++)
4908 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4909 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4919 /* Like reload_reg_reaches_end_p, but check that the condition holds for
4920 every register in the range [REGNO, REGNO + NREGS). */
4923 reload_regs_reach_end_p (unsigned int regno, int nregs,
4924 int opnum, enum reload_type type)
4928 for (i = 0; i < nregs; i++)
4929 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
4935 /* Returns whether R1 and R2 are uniquely chained: the value of one
4936 is used by the other, and that value is not used by any other
4937 reload for this insn. This is used to partially undo the decision
4938 made in find_reloads when in the case of multiple
4939 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4940 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4941 reloads. This code tries to avoid the conflict created by that
4942 change. It might be cleaner to explicitly keep track of which
4943 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4944 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4945 this after the fact. */
4947 reloads_unique_chain_p (int r1, int r2)
4951 /* We only check input reloads. */
4952 if (! rld[r1].in || ! rld[r2].in)
4955 /* Avoid anything with output reloads. */
4956 if (rld[r1].out || rld[r2].out)
4959 /* "chained" means one reload is a component of the other reload,
4960 not the same as the other reload. */
4961 if (rld[r1].opnum != rld[r2].opnum
4962 || rtx_equal_p (rld[r1].in, rld[r2].in)
4963 || rld[r1].optional || rld[r2].optional
4964 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4965 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4968 for (i = 0; i < n_reloads; i ++)
4969 /* Look for input reloads that aren't our two */
4970 if (i != r1 && i != r2 && rld[i].in)
4972 /* If our reload is mentioned at all, it isn't a simple chain. */
4973 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4979 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4982 This function uses the same algorithm as reload_reg_free_p above. */
4985 reloads_conflict (int r1, int r2)
4987 enum reload_type r1_type = rld[r1].when_needed;
4988 enum reload_type r2_type = rld[r2].when_needed;
4989 int r1_opnum = rld[r1].opnum;
4990 int r2_opnum = rld[r2].opnum;
4992 /* RELOAD_OTHER conflicts with everything. */
4993 if (r2_type == RELOAD_OTHER)
4996 /* Otherwise, check conflicts differently for each type. */
5000 case RELOAD_FOR_INPUT:
5001 return (r2_type == RELOAD_FOR_INSN
5002 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5003 || r2_type == RELOAD_FOR_OPADDR_ADDR
5004 || r2_type == RELOAD_FOR_INPUT
5005 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5006 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5007 && r2_opnum > r1_opnum));
5009 case RELOAD_FOR_INPUT_ADDRESS:
5010 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5011 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5013 case RELOAD_FOR_INPADDR_ADDRESS:
5014 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5015 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5017 case RELOAD_FOR_OUTPUT_ADDRESS:
5018 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5019 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5021 case RELOAD_FOR_OUTADDR_ADDRESS:
5022 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5023 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5025 case RELOAD_FOR_OPERAND_ADDRESS:
5026 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5027 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5028 && !reloads_unique_chain_p (r1, r2)));
5030 case RELOAD_FOR_OPADDR_ADDR:
5031 return (r2_type == RELOAD_FOR_INPUT
5032 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5034 case RELOAD_FOR_OUTPUT:
5035 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5036 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5037 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5038 && r2_opnum >= r1_opnum));
5040 case RELOAD_FOR_INSN:
5041 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5042 || r2_type == RELOAD_FOR_INSN
5043 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5045 case RELOAD_FOR_OTHER_ADDRESS:
5046 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5056 /* Indexed by reload number, 1 if incoming value
5057 inherited from previous insns. */
5058 static char reload_inherited[MAX_RELOADS];
5060 /* For an inherited reload, this is the insn the reload was inherited from,
5061 if we know it. Otherwise, this is 0. */
5062 static rtx reload_inheritance_insn[MAX_RELOADS];
5064 /* If nonzero, this is a place to get the value of the reload,
5065 rather than using reload_in. */
5066 static rtx reload_override_in[MAX_RELOADS];
5068 /* For each reload, the hard register number of the register used,
5069 or -1 if we did not need a register for this reload. */
5070 static int reload_spill_index[MAX_RELOADS];
5072 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5073 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5075 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5076 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5078 /* Subroutine of free_for_value_p, used to check a single register.
5079 START_REGNO is the starting regno of the full reload register
5080 (possibly comprising multiple hard registers) that we are considering. */
5083 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5084 enum reload_type type, rtx value, rtx out,
5085 int reloadnum, int ignore_address_reloads)
5088 /* Set if we see an input reload that must not share its reload register
5089 with any new earlyclobber, but might otherwise share the reload
5090 register with an output or input-output reload. */
5091 int check_earlyclobber = 0;
5095 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5098 if (out == const0_rtx)
5104 /* We use some pseudo 'time' value to check if the lifetimes of the
5105 new register use would overlap with the one of a previous reload
5106 that is not read-only or uses a different value.
5107 The 'time' used doesn't have to be linear in any shape or form, just
5109 Some reload types use different 'buckets' for each operand.
5110 So there are MAX_RECOG_OPERANDS different time values for each
5112 We compute TIME1 as the time when the register for the prospective
5113 new reload ceases to be live, and TIME2 for each existing
5114 reload as the time when that the reload register of that reload
5116 Where there is little to be gained by exact lifetime calculations,
5117 we just make conservative assumptions, i.e. a longer lifetime;
5118 this is done in the 'default:' cases. */
5121 case RELOAD_FOR_OTHER_ADDRESS:
5122 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5123 time1 = copy ? 0 : 1;
5126 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5128 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5129 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5130 respectively, to the time values for these, we get distinct time
5131 values. To get distinct time values for each operand, we have to
5132 multiply opnum by at least three. We round that up to four because
5133 multiply by four is often cheaper. */
5134 case RELOAD_FOR_INPADDR_ADDRESS:
5135 time1 = opnum * 4 + 2;
5137 case RELOAD_FOR_INPUT_ADDRESS:
5138 time1 = opnum * 4 + 3;
5140 case RELOAD_FOR_INPUT:
5141 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5142 executes (inclusive). */
5143 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5145 case RELOAD_FOR_OPADDR_ADDR:
5147 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5148 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5150 case RELOAD_FOR_OPERAND_ADDRESS:
5151 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5153 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5155 case RELOAD_FOR_OUTADDR_ADDRESS:
5156 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5158 case RELOAD_FOR_OUTPUT_ADDRESS:
5159 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5162 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5165 for (i = 0; i < n_reloads; i++)
5167 rtx reg = rld[i].reg_rtx;
5168 if (reg && REG_P (reg)
5169 && ((unsigned) regno - true_regnum (reg)
5170 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5173 rtx other_input = rld[i].in;
5175 /* If the other reload loads the same input value, that
5176 will not cause a conflict only if it's loading it into
5177 the same register. */
5178 if (true_regnum (reg) != start_regno)
5179 other_input = NULL_RTX;
5180 if (! other_input || ! rtx_equal_p (other_input, value)
5181 || rld[i].out || out)
5184 switch (rld[i].when_needed)
5186 case RELOAD_FOR_OTHER_ADDRESS:
5189 case RELOAD_FOR_INPADDR_ADDRESS:
5190 /* find_reloads makes sure that a
5191 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5192 by at most one - the first -
5193 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5194 address reload is inherited, the address address reload
5195 goes away, so we can ignore this conflict. */
5196 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5197 && ignore_address_reloads
5198 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5199 Then the address address is still needed to store
5200 back the new address. */
5201 && ! rld[reloadnum].out)
5203 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5204 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5206 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5207 && ignore_address_reloads
5208 /* Unless we are reloading an auto_inc expression. */
5209 && ! rld[reloadnum].out)
5211 time2 = rld[i].opnum * 4 + 2;
5213 case RELOAD_FOR_INPUT_ADDRESS:
5214 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5215 && ignore_address_reloads
5216 && ! rld[reloadnum].out)
5218 time2 = rld[i].opnum * 4 + 3;
5220 case RELOAD_FOR_INPUT:
5221 time2 = rld[i].opnum * 4 + 4;
5222 check_earlyclobber = 1;
5224 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5225 == MAX_RECOG_OPERAND * 4 */
5226 case RELOAD_FOR_OPADDR_ADDR:
5227 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5228 && ignore_address_reloads
5229 && ! rld[reloadnum].out)
5231 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5233 case RELOAD_FOR_OPERAND_ADDRESS:
5234 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5235 check_earlyclobber = 1;
5237 case RELOAD_FOR_INSN:
5238 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5240 case RELOAD_FOR_OUTPUT:
5241 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5242 instruction is executed. */
5243 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5245 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5246 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5248 case RELOAD_FOR_OUTADDR_ADDRESS:
5249 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5250 && ignore_address_reloads
5251 && ! rld[reloadnum].out)
5253 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5255 case RELOAD_FOR_OUTPUT_ADDRESS:
5256 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5259 /* If there is no conflict in the input part, handle this
5260 like an output reload. */
5261 if (! rld[i].in || rtx_equal_p (other_input, value))
5263 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5264 /* Earlyclobbered outputs must conflict with inputs. */
5265 if (earlyclobber_operand_p (rld[i].out))
5266 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5271 /* RELOAD_OTHER might be live beyond instruction execution,
5272 but this is not obvious when we set time2 = 1. So check
5273 here if there might be a problem with the new reload
5274 clobbering the register used by the RELOAD_OTHER. */
5282 && (! rld[i].in || rld[i].out
5283 || ! rtx_equal_p (other_input, value)))
5284 || (out && rld[reloadnum].out_reg
5285 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5291 /* Earlyclobbered outputs must conflict with inputs. */
5292 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5298 /* Return 1 if the value in reload reg REGNO, as used by a reload
5299 needed for the part of the insn specified by OPNUM and TYPE,
5300 may be used to load VALUE into it.
5302 MODE is the mode in which the register is used, this is needed to
5303 determine how many hard regs to test.
5305 Other read-only reloads with the same value do not conflict
5306 unless OUT is nonzero and these other reloads have to live while
5307 output reloads live.
5308 If OUT is CONST0_RTX, this is a special case: it means that the
5309 test should not be for using register REGNO as reload register, but
5310 for copying from register REGNO into the reload register.
5312 RELOADNUM is the number of the reload we want to load this value for;
5313 a reload does not conflict with itself.
5315 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5316 reloads that load an address for the very reload we are considering.
5318 The caller has to make sure that there is no conflict with the return
5322 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5323 enum reload_type type, rtx value, rtx out, int reloadnum,
5324 int ignore_address_reloads)
5326 int nregs = hard_regno_nregs[regno][mode];
5328 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5329 value, out, reloadnum,
5330 ignore_address_reloads))
5335 /* Return nonzero if the rtx X is invariant over the current function. */
5336 /* ??? Actually, the places where we use this expect exactly what is
5337 tested here, and not everything that is function invariant. In
5338 particular, the frame pointer and arg pointer are special cased;
5339 pic_offset_table_rtx is not, and we must not spill these things to
5343 function_invariant_p (const_rtx x)
5347 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5349 if (GET_CODE (x) == PLUS
5350 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5351 && CONSTANT_P (XEXP (x, 1)))
5356 /* Determine whether the reload reg X overlaps any rtx'es used for
5357 overriding inheritance. Return nonzero if so. */
5360 conflicts_with_override (rtx x)
5363 for (i = 0; i < n_reloads; i++)
5364 if (reload_override_in[i]
5365 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5370 /* Give an error message saying we failed to find a reload for INSN,
5371 and clear out reload R. */
5373 failed_reload (rtx insn, int r)
5375 if (asm_noperands (PATTERN (insn)) < 0)
5376 /* It's the compiler's fault. */
5377 fatal_insn ("could not find a spill register", insn);
5379 /* It's the user's fault; the operand's mode and constraint
5380 don't match. Disable this reload so we don't crash in final. */
5381 error_for_asm (insn,
5382 "%<asm%> operand constraint incompatible with operand size");
5386 rld[r].optional = 1;
5387 rld[r].secondary_p = 1;
5390 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5391 for reload R. If it's valid, get an rtx for it. Return nonzero if
5394 set_reload_reg (int i, int r)
5397 rtx reg = spill_reg_rtx[i];
5399 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5400 spill_reg_rtx[i] = reg
5401 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5403 regno = true_regnum (reg);
5405 /* Detect when the reload reg can't hold the reload mode.
5406 This used to be one `if', but Sequent compiler can't handle that. */
5407 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5409 enum machine_mode test_mode = VOIDmode;
5411 test_mode = GET_MODE (rld[r].in);
5412 /* If rld[r].in has VOIDmode, it means we will load it
5413 in whatever mode the reload reg has: to wit, rld[r].mode.
5414 We have already tested that for validity. */
5415 /* Aside from that, we need to test that the expressions
5416 to reload from or into have modes which are valid for this
5417 reload register. Otherwise the reload insns would be invalid. */
5418 if (! (rld[r].in != 0 && test_mode != VOIDmode
5419 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5420 if (! (rld[r].out != 0
5421 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5423 /* The reg is OK. */
5426 /* Mark as in use for this insn the reload regs we use
5428 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5429 rld[r].when_needed, rld[r].mode);
5431 rld[r].reg_rtx = reg;
5432 reload_spill_index[r] = spill_regs[i];
5439 /* Find a spill register to use as a reload register for reload R.
5440 LAST_RELOAD is nonzero if this is the last reload for the insn being
5443 Set rld[R].reg_rtx to the register allocated.
5445 We return 1 if successful, or 0 if we couldn't find a spill reg and
5446 we didn't change anything. */
5449 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5454 /* If we put this reload ahead, thinking it is a group,
5455 then insist on finding a group. Otherwise we can grab a
5456 reg that some other reload needs.
5457 (That can happen when we have a 68000 DATA_OR_FP_REG
5458 which is a group of data regs or one fp reg.)
5459 We need not be so restrictive if there are no more reloads
5462 ??? Really it would be nicer to have smarter handling
5463 for that kind of reg class, where a problem like this is normal.
5464 Perhaps those classes should be avoided for reloading
5465 by use of more alternatives. */
5467 int force_group = rld[r].nregs > 1 && ! last_reload;
5469 /* If we want a single register and haven't yet found one,
5470 take any reg in the right class and not in use.
5471 If we want a consecutive group, here is where we look for it.
5473 We use two passes so we can first look for reload regs to
5474 reuse, which are already in use for other reloads in this insn,
5475 and only then use additional registers.
5476 I think that maximizing reuse is needed to make sure we don't
5477 run out of reload regs. Suppose we have three reloads, and
5478 reloads A and B can share regs. These need two regs.
5479 Suppose A and B are given different regs.
5480 That leaves none for C. */
5481 for (pass = 0; pass < 2; pass++)
5483 /* I is the index in spill_regs.
5484 We advance it round-robin between insns to use all spill regs
5485 equally, so that inherited reloads have a chance
5486 of leapfrogging each other. */
5490 for (count = 0; count < n_spills; count++)
5492 int class = (int) rld[r].class;
5498 regnum = spill_regs[i];
5500 if ((reload_reg_free_p (regnum, rld[r].opnum,
5503 /* We check reload_reg_used to make sure we
5504 don't clobber the return register. */
5505 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5506 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5507 rld[r].when_needed, rld[r].in,
5509 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5510 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5511 /* Look first for regs to share, then for unshared. But
5512 don't share regs used for inherited reloads; they are
5513 the ones we want to preserve. */
5515 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5517 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5520 int nr = hard_regno_nregs[regnum][rld[r].mode];
5521 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5522 (on 68000) got us two FP regs. If NR is 1,
5523 we would reject both of them. */
5526 /* If we need only one reg, we have already won. */
5529 /* But reject a single reg if we demand a group. */
5534 /* Otherwise check that as many consecutive regs as we need
5535 are available here. */
5538 int regno = regnum + nr - 1;
5539 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5540 && spill_reg_order[regno] >= 0
5541 && reload_reg_free_p (regno, rld[r].opnum,
5542 rld[r].when_needed)))
5551 /* If we found something on pass 1, omit pass 2. */
5552 if (count < n_spills)
5556 /* We should have found a spill register by now. */
5557 if (count >= n_spills)
5560 /* I is the index in SPILL_REG_RTX of the reload register we are to
5561 allocate. Get an rtx for it and find its register number. */
5563 return set_reload_reg (i, r);
5566 /* Initialize all the tables needed to allocate reload registers.
5567 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5568 is the array we use to restore the reg_rtx field for every reload. */
5571 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5575 for (i = 0; i < n_reloads; i++)
5576 rld[i].reg_rtx = save_reload_reg_rtx[i];
5578 memset (reload_inherited, 0, MAX_RELOADS);
5579 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5580 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5582 CLEAR_HARD_REG_SET (reload_reg_used);
5583 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5584 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5585 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5586 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5587 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5589 CLEAR_HARD_REG_SET (reg_used_in_insn);
5592 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5593 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5594 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5595 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5596 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5597 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5600 for (i = 0; i < reload_n_operands; i++)
5602 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5603 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5604 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5605 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5606 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5607 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5610 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5612 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5614 for (i = 0; i < n_reloads; i++)
5615 /* If we have already decided to use a certain register,
5616 don't use it in another way. */
5618 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5619 rld[i].when_needed, rld[i].mode);
5622 /* Assign hard reg targets for the pseudo-registers we must reload
5623 into hard regs for this insn.
5624 Also output the instructions to copy them in and out of the hard regs.
5626 For machines with register classes, we are responsible for
5627 finding a reload reg in the proper class. */
5630 choose_reload_regs (struct insn_chain *chain)
5632 rtx insn = chain->insn;
5634 unsigned int max_group_size = 1;
5635 enum reg_class group_class = NO_REGS;
5636 int pass, win, inheritance;
5638 rtx save_reload_reg_rtx[MAX_RELOADS];
5640 /* In order to be certain of getting the registers we need,
5641 we must sort the reloads into order of increasing register class.
5642 Then our grabbing of reload registers will parallel the process
5643 that provided the reload registers.
5645 Also note whether any of the reloads wants a consecutive group of regs.
5646 If so, record the maximum size of the group desired and what
5647 register class contains all the groups needed by this insn. */
5649 for (j = 0; j < n_reloads; j++)
5651 reload_order[j] = j;
5652 if (rld[j].reg_rtx != NULL_RTX)
5654 gcc_assert (REG_P (rld[j].reg_rtx)
5655 && HARD_REGISTER_P (rld[j].reg_rtx));
5656 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5659 reload_spill_index[j] = -1;
5661 if (rld[j].nregs > 1)
5663 max_group_size = MAX (rld[j].nregs, max_group_size);
5665 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5668 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5672 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5674 /* If -O, try first with inheritance, then turning it off.
5675 If not -O, don't do inheritance.
5676 Using inheritance when not optimizing leads to paradoxes
5677 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5678 because one side of the comparison might be inherited. */
5680 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5682 choose_reload_regs_init (chain, save_reload_reg_rtx);
5684 /* Process the reloads in order of preference just found.
5685 Beyond this point, subregs can be found in reload_reg_rtx.
5687 This used to look for an existing reloaded home for all of the
5688 reloads, and only then perform any new reloads. But that could lose
5689 if the reloads were done out of reg-class order because a later
5690 reload with a looser constraint might have an old home in a register
5691 needed by an earlier reload with a tighter constraint.
5693 To solve this, we make two passes over the reloads, in the order
5694 described above. In the first pass we try to inherit a reload
5695 from a previous insn. If there is a later reload that needs a
5696 class that is a proper subset of the class being processed, we must
5697 also allocate a spill register during the first pass.
5699 Then make a second pass over the reloads to allocate any reloads
5700 that haven't been given registers yet. */
5702 for (j = 0; j < n_reloads; j++)
5704 int r = reload_order[j];
5705 rtx search_equiv = NULL_RTX;
5707 /* Ignore reloads that got marked inoperative. */
5708 if (rld[r].out == 0 && rld[r].in == 0
5709 && ! rld[r].secondary_p)
5712 /* If find_reloads chose to use reload_in or reload_out as a reload
5713 register, we don't need to chose one. Otherwise, try even if it
5714 found one since we might save an insn if we find the value lying
5716 Try also when reload_in is a pseudo without a hard reg. */
5717 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5718 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5719 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5720 && !MEM_P (rld[r].in)
5721 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5724 #if 0 /* No longer needed for correct operation.
5725 It might give better code, or might not; worth an experiment? */
5726 /* If this is an optional reload, we can't inherit from earlier insns
5727 until we are sure that any non-optional reloads have been allocated.
5728 The following code takes advantage of the fact that optional reloads
5729 are at the end of reload_order. */
5730 if (rld[r].optional != 0)
5731 for (i = 0; i < j; i++)
5732 if ((rld[reload_order[i]].out != 0
5733 || rld[reload_order[i]].in != 0
5734 || rld[reload_order[i]].secondary_p)
5735 && ! rld[reload_order[i]].optional
5736 && rld[reload_order[i]].reg_rtx == 0)
5737 allocate_reload_reg (chain, reload_order[i], 0);
5740 /* First see if this pseudo is already available as reloaded
5741 for a previous insn. We cannot try to inherit for reloads
5742 that are smaller than the maximum number of registers needed
5743 for groups unless the register we would allocate cannot be used
5746 We could check here to see if this is a secondary reload for
5747 an object that is already in a register of the desired class.
5748 This would avoid the need for the secondary reload register.
5749 But this is complex because we can't easily determine what
5750 objects might want to be loaded via this reload. So let a
5751 register be allocated here. In `emit_reload_insns' we suppress
5752 one of the loads in the case described above. */
5758 enum machine_mode mode = VOIDmode;
5762 else if (REG_P (rld[r].in))
5764 regno = REGNO (rld[r].in);
5765 mode = GET_MODE (rld[r].in);
5767 else if (REG_P (rld[r].in_reg))
5769 regno = REGNO (rld[r].in_reg);
5770 mode = GET_MODE (rld[r].in_reg);
5772 else if (GET_CODE (rld[r].in_reg) == SUBREG
5773 && REG_P (SUBREG_REG (rld[r].in_reg)))
5775 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5776 if (regno < FIRST_PSEUDO_REGISTER)
5777 regno = subreg_regno (rld[r].in_reg);
5779 byte = SUBREG_BYTE (rld[r].in_reg);
5780 mode = GET_MODE (rld[r].in_reg);
5783 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5784 && REG_P (XEXP (rld[r].in_reg, 0)))
5786 regno = REGNO (XEXP (rld[r].in_reg, 0));
5787 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5788 rld[r].out = rld[r].in;
5792 /* This won't work, since REGNO can be a pseudo reg number.
5793 Also, it takes much more hair to keep track of all the things
5794 that can invalidate an inherited reload of part of a pseudoreg. */
5795 else if (GET_CODE (rld[r].in) == SUBREG
5796 && REG_P (SUBREG_REG (rld[r].in)))
5797 regno = subreg_regno (rld[r].in);
5801 && reg_last_reload_reg[regno] != 0
5802 #ifdef CANNOT_CHANGE_MODE_CLASS
5803 /* Verify that the register it's in can be used in
5805 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5806 GET_MODE (reg_last_reload_reg[regno]),
5811 enum reg_class class = rld[r].class, last_class;
5812 rtx last_reg = reg_last_reload_reg[regno];
5813 enum machine_mode need_mode;
5815 i = REGNO (last_reg);
5816 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5817 last_class = REGNO_REG_CLASS (i);
5823 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5824 + byte * BITS_PER_UNIT,
5825 GET_MODE_CLASS (mode));
5827 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5828 >= GET_MODE_SIZE (need_mode))
5829 && reg_reloaded_contents[i] == regno
5830 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5831 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5832 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5833 /* Even if we can't use this register as a reload
5834 register, we might use it for reload_override_in,
5835 if copying it to the desired class is cheap
5837 || ((REGISTER_MOVE_COST (mode, last_class, class)
5838 < MEMORY_MOVE_COST (mode, class, 1))
5839 && (secondary_reload_class (1, class, mode,
5842 #ifdef SECONDARY_MEMORY_NEEDED
5843 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5848 && (rld[r].nregs == max_group_size
5849 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5851 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5852 rld[r].when_needed, rld[r].in,
5855 /* If a group is needed, verify that all the subsequent
5856 registers still have their values intact. */
5857 int nr = hard_regno_nregs[i][rld[r].mode];
5860 for (k = 1; k < nr; k++)
5861 if (reg_reloaded_contents[i + k] != regno
5862 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5870 last_reg = (GET_MODE (last_reg) == mode
5871 ? last_reg : gen_rtx_REG (mode, i));
5874 for (k = 0; k < nr; k++)
5875 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5878 /* We found a register that contains the
5879 value we need. If this register is the
5880 same as an `earlyclobber' operand of the
5881 current insn, just mark it as a place to
5882 reload from since we can't use it as the
5883 reload register itself. */
5885 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5886 if (reg_overlap_mentioned_for_reload_p
5887 (reg_last_reload_reg[regno],
5888 reload_earlyclobbers[i1]))
5891 if (i1 != n_earlyclobbers
5892 || ! (free_for_value_p (i, rld[r].mode,
5894 rld[r].when_needed, rld[r].in,
5896 /* Don't use it if we'd clobber a pseudo reg. */
5897 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5899 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5900 /* Don't clobber the frame pointer. */
5901 || (i == HARD_FRAME_POINTER_REGNUM
5902 && frame_pointer_needed
5904 /* Don't really use the inherited spill reg
5905 if we need it wider than we've got it. */
5906 || (GET_MODE_SIZE (rld[r].mode)
5907 > GET_MODE_SIZE (mode))
5910 /* If find_reloads chose reload_out as reload
5911 register, stay with it - that leaves the
5912 inherited register for subsequent reloads. */
5913 || (rld[r].out && rld[r].reg_rtx
5914 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5916 if (! rld[r].optional)
5918 reload_override_in[r] = last_reg;
5919 reload_inheritance_insn[r]
5920 = reg_reloaded_insn[i];
5926 /* We can use this as a reload reg. */
5927 /* Mark the register as in use for this part of
5929 mark_reload_reg_in_use (i,
5933 rld[r].reg_rtx = last_reg;
5934 reload_inherited[r] = 1;
5935 reload_inheritance_insn[r]
5936 = reg_reloaded_insn[i];
5937 reload_spill_index[r] = i;
5938 for (k = 0; k < nr; k++)
5939 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5947 /* Here's another way to see if the value is already lying around. */
5950 && ! reload_inherited[r]
5952 && (CONSTANT_P (rld[r].in)
5953 || GET_CODE (rld[r].in) == PLUS
5954 || REG_P (rld[r].in)
5955 || MEM_P (rld[r].in))
5956 && (rld[r].nregs == max_group_size
5957 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5958 search_equiv = rld[r].in;
5959 /* If this is an output reload from a simple move insn, look
5960 if an equivalence for the input is available. */
5961 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5963 rtx set = single_set (insn);
5966 && rtx_equal_p (rld[r].out, SET_DEST (set))
5967 && CONSTANT_P (SET_SRC (set)))
5968 search_equiv = SET_SRC (set);
5974 = find_equiv_reg (search_equiv, insn, rld[r].class,
5975 -1, NULL, 0, rld[r].mode);
5981 regno = REGNO (equiv);
5984 /* This must be a SUBREG of a hard register.
5985 Make a new REG since this might be used in an
5986 address and not all machines support SUBREGs
5988 gcc_assert (GET_CODE (equiv) == SUBREG);
5989 regno = subreg_regno (equiv);
5990 equiv = gen_rtx_REG (rld[r].mode, regno);
5991 /* If we choose EQUIV as the reload register, but the
5992 loop below decides to cancel the inheritance, we'll
5993 end up reloading EQUIV in rld[r].mode, not the mode
5994 it had originally. That isn't safe when EQUIV isn't
5995 available as a spill register since its value might
5996 still be live at this point. */
5997 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5998 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6003 /* If we found a spill reg, reject it unless it is free
6004 and of the desired class. */
6008 int bad_for_class = 0;
6009 int max_regno = regno + rld[r].nregs;
6011 for (i = regno; i < max_regno; i++)
6013 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6015 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6020 && ! free_for_value_p (regno, rld[r].mode,
6021 rld[r].opnum, rld[r].when_needed,
6022 rld[r].in, rld[r].out, r, 1))
6027 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6030 /* We found a register that contains the value we need.
6031 If this register is the same as an `earlyclobber' operand
6032 of the current insn, just mark it as a place to reload from
6033 since we can't use it as the reload register itself. */
6036 for (i = 0; i < n_earlyclobbers; i++)
6037 if (reg_overlap_mentioned_for_reload_p (equiv,
6038 reload_earlyclobbers[i]))
6040 if (! rld[r].optional)
6041 reload_override_in[r] = equiv;
6046 /* If the equiv register we have found is explicitly clobbered
6047 in the current insn, it depends on the reload type if we
6048 can use it, use it for reload_override_in, or not at all.
6049 In particular, we then can't use EQUIV for a
6050 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6054 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6055 switch (rld[r].when_needed)
6057 case RELOAD_FOR_OTHER_ADDRESS:
6058 case RELOAD_FOR_INPADDR_ADDRESS:
6059 case RELOAD_FOR_INPUT_ADDRESS:
6060 case RELOAD_FOR_OPADDR_ADDR:
6063 case RELOAD_FOR_INPUT:
6064 case RELOAD_FOR_OPERAND_ADDRESS:
6065 if (! rld[r].optional)
6066 reload_override_in[r] = equiv;
6072 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6073 switch (rld[r].when_needed)
6075 case RELOAD_FOR_OTHER_ADDRESS:
6076 case RELOAD_FOR_INPADDR_ADDRESS:
6077 case RELOAD_FOR_INPUT_ADDRESS:
6078 case RELOAD_FOR_OPADDR_ADDR:
6079 case RELOAD_FOR_OPERAND_ADDRESS:
6080 case RELOAD_FOR_INPUT:
6083 if (! rld[r].optional)
6084 reload_override_in[r] = equiv;
6092 /* If we found an equivalent reg, say no code need be generated
6093 to load it, and use it as our reload reg. */
6095 && (regno != HARD_FRAME_POINTER_REGNUM
6096 || !frame_pointer_needed))
6098 int nr = hard_regno_nregs[regno][rld[r].mode];
6100 rld[r].reg_rtx = equiv;
6101 reload_inherited[r] = 1;
6103 /* If reg_reloaded_valid is not set for this register,
6104 there might be a stale spill_reg_store lying around.
6105 We must clear it, since otherwise emit_reload_insns
6106 might delete the store. */
6107 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6108 spill_reg_store[regno] = NULL_RTX;
6109 /* If any of the hard registers in EQUIV are spill
6110 registers, mark them as in use for this insn. */
6111 for (k = 0; k < nr; k++)
6113 i = spill_reg_order[regno + k];
6116 mark_reload_reg_in_use (regno, rld[r].opnum,
6119 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6126 /* If we found a register to use already, or if this is an optional
6127 reload, we are done. */
6128 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6132 /* No longer needed for correct operation. Might or might
6133 not give better code on the average. Want to experiment? */
6135 /* See if there is a later reload that has a class different from our
6136 class that intersects our class or that requires less register
6137 than our reload. If so, we must allocate a register to this
6138 reload now, since that reload might inherit a previous reload
6139 and take the only available register in our class. Don't do this
6140 for optional reloads since they will force all previous reloads
6141 to be allocated. Also don't do this for reloads that have been
6144 for (i = j + 1; i < n_reloads; i++)
6146 int s = reload_order[i];
6148 if ((rld[s].in == 0 && rld[s].out == 0
6149 && ! rld[s].secondary_p)
6153 if ((rld[s].class != rld[r].class
6154 && reg_classes_intersect_p (rld[r].class,
6156 || rld[s].nregs < rld[r].nregs)
6163 allocate_reload_reg (chain, r, j == n_reloads - 1);
6167 /* Now allocate reload registers for anything non-optional that
6168 didn't get one yet. */
6169 for (j = 0; j < n_reloads; j++)
6171 int r = reload_order[j];
6173 /* Ignore reloads that got marked inoperative. */
6174 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6177 /* Skip reloads that already have a register allocated or are
6179 if (rld[r].reg_rtx != 0 || rld[r].optional)
6182 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6186 /* If that loop got all the way, we have won. */
6193 /* Loop around and try without any inheritance. */
6198 /* First undo everything done by the failed attempt
6199 to allocate with inheritance. */
6200 choose_reload_regs_init (chain, save_reload_reg_rtx);
6202 /* Some sanity tests to verify that the reloads found in the first
6203 pass are identical to the ones we have now. */
6204 gcc_assert (chain->n_reloads == n_reloads);
6206 for (i = 0; i < n_reloads; i++)
6208 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6210 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6211 for (j = 0; j < n_spills; j++)
6212 if (spill_regs[j] == chain->rld[i].regno)
6213 if (! set_reload_reg (j, i))
6214 failed_reload (chain->insn, i);
6218 /* If we thought we could inherit a reload, because it seemed that
6219 nothing else wanted the same reload register earlier in the insn,
6220 verify that assumption, now that all reloads have been assigned.
6221 Likewise for reloads where reload_override_in has been set. */
6223 /* If doing expensive optimizations, do one preliminary pass that doesn't
6224 cancel any inheritance, but removes reloads that have been needed only
6225 for reloads that we know can be inherited. */
6226 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6228 for (j = 0; j < n_reloads; j++)
6230 int r = reload_order[j];
6232 if (reload_inherited[r] && rld[r].reg_rtx)
6233 check_reg = rld[r].reg_rtx;
6234 else if (reload_override_in[r]
6235 && (REG_P (reload_override_in[r])
6236 || GET_CODE (reload_override_in[r]) == SUBREG))
6237 check_reg = reload_override_in[r];
6240 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6241 rld[r].opnum, rld[r].when_needed, rld[r].in,
6242 (reload_inherited[r]
6243 ? rld[r].out : const0_rtx),
6248 reload_inherited[r] = 0;
6249 reload_override_in[r] = 0;
6251 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6252 reload_override_in, then we do not need its related
6253 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6254 likewise for other reload types.
6255 We handle this by removing a reload when its only replacement
6256 is mentioned in reload_in of the reload we are going to inherit.
6257 A special case are auto_inc expressions; even if the input is
6258 inherited, we still need the address for the output. We can
6259 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6260 If we succeeded removing some reload and we are doing a preliminary
6261 pass just to remove such reloads, make another pass, since the
6262 removal of one reload might allow us to inherit another one. */
6264 && rld[r].out != rld[r].in
6265 && remove_address_replacements (rld[r].in) && pass)
6270 /* Now that reload_override_in is known valid,
6271 actually override reload_in. */
6272 for (j = 0; j < n_reloads; j++)
6273 if (reload_override_in[j])
6274 rld[j].in = reload_override_in[j];
6276 /* If this reload won't be done because it has been canceled or is
6277 optional and not inherited, clear reload_reg_rtx so other
6278 routines (such as subst_reloads) don't get confused. */
6279 for (j = 0; j < n_reloads; j++)
6280 if (rld[j].reg_rtx != 0
6281 && ((rld[j].optional && ! reload_inherited[j])
6282 || (rld[j].in == 0 && rld[j].out == 0
6283 && ! rld[j].secondary_p)))
6285 int regno = true_regnum (rld[j].reg_rtx);
6287 if (spill_reg_order[regno] >= 0)
6288 clear_reload_reg_in_use (regno, rld[j].opnum,
6289 rld[j].when_needed, rld[j].mode);
6291 reload_spill_index[j] = -1;
6294 /* Record which pseudos and which spill regs have output reloads. */
6295 for (j = 0; j < n_reloads; j++)
6297 int r = reload_order[j];
6299 i = reload_spill_index[r];
6301 /* I is nonneg if this reload uses a register.
6302 If rld[r].reg_rtx is 0, this is an optional reload
6303 that we opted to ignore. */
6304 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6305 && rld[r].reg_rtx != 0)
6307 int nregno = REGNO (rld[r].out_reg);
6310 if (nregno < FIRST_PSEUDO_REGISTER)
6311 nr = hard_regno_nregs[nregno][rld[r].mode];
6314 SET_REGNO_REG_SET (®_has_output_reload,
6319 nr = hard_regno_nregs[i][rld[r].mode];
6321 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6324 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6325 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6326 || rld[r].when_needed == RELOAD_FOR_INSN);
6331 /* Deallocate the reload register for reload R. This is called from
6332 remove_address_replacements. */
6335 deallocate_reload_reg (int r)
6339 if (! rld[r].reg_rtx)
6341 regno = true_regnum (rld[r].reg_rtx);
6343 if (spill_reg_order[regno] >= 0)
6344 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6346 reload_spill_index[r] = -1;
6349 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6350 reloads of the same item for fear that we might not have enough reload
6351 registers. However, normally they will get the same reload register
6352 and hence actually need not be loaded twice.
6354 Here we check for the most common case of this phenomenon: when we have
6355 a number of reloads for the same object, each of which were allocated
6356 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6357 reload, and is not modified in the insn itself. If we find such,
6358 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6359 This will not increase the number of spill registers needed and will
6360 prevent redundant code. */
6363 merge_assigned_reloads (rtx insn)
6367 /* Scan all the reloads looking for ones that only load values and
6368 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6369 assigned and not modified by INSN. */
6371 for (i = 0; i < n_reloads; i++)
6373 int conflicting_input = 0;
6374 int max_input_address_opnum = -1;
6375 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6377 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6378 || rld[i].out != 0 || rld[i].reg_rtx == 0
6379 || reg_set_p (rld[i].reg_rtx, insn))
6382 /* Look at all other reloads. Ensure that the only use of this
6383 reload_reg_rtx is in a reload that just loads the same value
6384 as we do. Note that any secondary reloads must be of the identical
6385 class since the values, modes, and result registers are the
6386 same, so we need not do anything with any secondary reloads. */
6388 for (j = 0; j < n_reloads; j++)
6390 if (i == j || rld[j].reg_rtx == 0
6391 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6395 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6396 && rld[j].opnum > max_input_address_opnum)
6397 max_input_address_opnum = rld[j].opnum;
6399 /* If the reload regs aren't exactly the same (e.g, different modes)
6400 or if the values are different, we can't merge this reload.
6401 But if it is an input reload, we might still merge
6402 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6404 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6405 || rld[j].out != 0 || rld[j].in == 0
6406 || ! rtx_equal_p (rld[i].in, rld[j].in))
6408 if (rld[j].when_needed != RELOAD_FOR_INPUT
6409 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6410 || rld[i].opnum > rld[j].opnum)
6411 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6413 conflicting_input = 1;
6414 if (min_conflicting_input_opnum > rld[j].opnum)
6415 min_conflicting_input_opnum = rld[j].opnum;
6419 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6420 we, in fact, found any matching reloads. */
6423 && max_input_address_opnum <= min_conflicting_input_opnum)
6425 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6427 for (j = 0; j < n_reloads; j++)
6428 if (i != j && rld[j].reg_rtx != 0
6429 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6430 && (! conflicting_input
6431 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6432 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6434 rld[i].when_needed = RELOAD_OTHER;
6436 reload_spill_index[j] = -1;
6437 transfer_replacements (i, j);
6440 /* If this is now RELOAD_OTHER, look for any reloads that
6441 load parts of this operand and set them to
6442 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6443 RELOAD_OTHER for outputs. Note that this test is
6444 equivalent to looking for reloads for this operand
6447 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6448 it may share registers with a RELOAD_FOR_INPUT, so we can
6449 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6450 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6452 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6453 instruction is assigned the same register as the earlier
6454 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6455 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6456 instruction to be deleted later on. */
6458 if (rld[i].when_needed == RELOAD_OTHER)
6459 for (j = 0; j < n_reloads; j++)
6461 && rld[j].when_needed != RELOAD_OTHER
6462 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6463 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6464 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6465 && (! conflicting_input
6466 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6467 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6468 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6474 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6475 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6476 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6478 /* Check to see if we accidentally converted two
6479 reloads that use the same reload register with
6480 different inputs to the same type. If so, the
6481 resulting code won't work. */
6483 for (k = 0; k < j; k++)
6484 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6485 || rld[k].when_needed != rld[j].when_needed
6486 || !rtx_equal_p (rld[k].reg_rtx,
6488 || rtx_equal_p (rld[k].in,
6495 /* These arrays are filled by emit_reload_insns and its subroutines. */
6496 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6497 static rtx other_input_address_reload_insns = 0;
6498 static rtx other_input_reload_insns = 0;
6499 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6500 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6501 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6502 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6503 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6504 static rtx operand_reload_insns = 0;
6505 static rtx other_operand_reload_insns = 0;
6506 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6508 /* Values to be put in spill_reg_store are put here first. */
6509 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6510 static HARD_REG_SET reg_reloaded_died;
6512 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6513 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6514 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6515 adjusted register, and return true. Otherwise, return false. */
6517 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6518 enum reg_class new_class,
6519 enum machine_mode new_mode)
6524 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6526 unsigned regno = REGNO (reg);
6528 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6530 if (GET_MODE (reg) != new_mode)
6532 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6534 if (hard_regno_nregs[regno][new_mode]
6535 > hard_regno_nregs[regno][GET_MODE (reg)])
6537 reg = reload_adjust_reg_for_mode (reg, new_mode);
6545 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6546 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6547 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6548 adjusted register, and return true. Otherwise, return false. */
6550 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6551 enum insn_code icode)
6554 enum reg_class new_class = scratch_reload_class (icode);
6555 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6557 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6558 new_class, new_mode);
6561 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6562 has the number J. OLD contains the value to be used as input. */
6565 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6568 rtx insn = chain->insn;
6570 rtx oldequiv_reg = 0;
6573 enum machine_mode mode;
6576 /* delete_output_reload is only invoked properly if old contains
6577 the original pseudo register. Since this is replaced with a
6578 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6579 find the pseudo in RELOAD_IN_REG. */
6580 if (reload_override_in[j]
6581 && REG_P (rl->in_reg))
6588 else if (REG_P (oldequiv))
6589 oldequiv_reg = oldequiv;
6590 else if (GET_CODE (oldequiv) == SUBREG)
6591 oldequiv_reg = SUBREG_REG (oldequiv);
6593 reloadreg = reload_reg_rtx_for_input[j];
6594 mode = GET_MODE (reloadreg);
6596 /* If we are reloading from a register that was recently stored in
6597 with an output-reload, see if we can prove there was
6598 actually no need to store the old value in it. */
6600 if (optimize && REG_P (oldequiv)
6601 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6602 && spill_reg_store[REGNO (oldequiv)]
6604 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6605 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6607 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6609 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6612 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6613 oldequiv = SUBREG_REG (oldequiv);
6614 if (GET_MODE (oldequiv) != VOIDmode
6615 && mode != GET_MODE (oldequiv))
6616 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6618 /* Switch to the right place to emit the reload insns. */
6619 switch (rl->when_needed)
6622 where = &other_input_reload_insns;
6624 case RELOAD_FOR_INPUT:
6625 where = &input_reload_insns[rl->opnum];
6627 case RELOAD_FOR_INPUT_ADDRESS:
6628 where = &input_address_reload_insns[rl->opnum];
6630 case RELOAD_FOR_INPADDR_ADDRESS:
6631 where = &inpaddr_address_reload_insns[rl->opnum];
6633 case RELOAD_FOR_OUTPUT_ADDRESS:
6634 where = &output_address_reload_insns[rl->opnum];
6636 case RELOAD_FOR_OUTADDR_ADDRESS:
6637 where = &outaddr_address_reload_insns[rl->opnum];
6639 case RELOAD_FOR_OPERAND_ADDRESS:
6640 where = &operand_reload_insns;
6642 case RELOAD_FOR_OPADDR_ADDR:
6643 where = &other_operand_reload_insns;
6645 case RELOAD_FOR_OTHER_ADDRESS:
6646 where = &other_input_address_reload_insns;
6652 push_to_sequence (*where);
6654 /* Auto-increment addresses must be reloaded in a special way. */
6655 if (rl->out && ! rl->out_reg)
6657 /* We are not going to bother supporting the case where a
6658 incremented register can't be copied directly from
6659 OLDEQUIV since this seems highly unlikely. */
6660 gcc_assert (rl->secondary_in_reload < 0);
6662 if (reload_inherited[j])
6663 oldequiv = reloadreg;
6665 old = XEXP (rl->in_reg, 0);
6667 if (optimize && REG_P (oldequiv)
6668 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6669 && spill_reg_store[REGNO (oldequiv)]
6671 && (dead_or_set_p (insn,
6672 spill_reg_stored_to[REGNO (oldequiv)])
6673 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6675 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6677 /* Prevent normal processing of this reload. */
6679 /* Output a special code sequence for this case. */
6680 new_spill_reg_store[REGNO (reloadreg)]
6681 = inc_for_reload (reloadreg, oldequiv, rl->out,
6685 /* If we are reloading a pseudo-register that was set by the previous
6686 insn, see if we can get rid of that pseudo-register entirely
6687 by redirecting the previous insn into our reload register. */
6689 else if (optimize && REG_P (old)
6690 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6691 && dead_or_set_p (insn, old)
6692 /* This is unsafe if some other reload
6693 uses the same reg first. */
6694 && ! conflicts_with_override (reloadreg)
6695 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6696 rl->when_needed, old, rl->out, j, 0))
6698 rtx temp = PREV_INSN (insn);
6699 while (temp && NOTE_P (temp))
6700 temp = PREV_INSN (temp);
6702 && NONJUMP_INSN_P (temp)
6703 && GET_CODE (PATTERN (temp)) == SET
6704 && SET_DEST (PATTERN (temp)) == old
6705 /* Make sure we can access insn_operand_constraint. */
6706 && asm_noperands (PATTERN (temp)) < 0
6707 /* This is unsafe if operand occurs more than once in current
6708 insn. Perhaps some occurrences aren't reloaded. */
6709 && count_occurrences (PATTERN (insn), old, 0) == 1)
6711 rtx old = SET_DEST (PATTERN (temp));
6712 /* Store into the reload register instead of the pseudo. */
6713 SET_DEST (PATTERN (temp)) = reloadreg;
6715 /* Verify that resulting insn is valid. */
6716 extract_insn (temp);
6717 if (constrain_operands (1))
6719 /* If the previous insn is an output reload, the source is
6720 a reload register, and its spill_reg_store entry will
6721 contain the previous destination. This is now
6723 if (REG_P (SET_SRC (PATTERN (temp)))
6724 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6726 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6727 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6730 /* If these are the only uses of the pseudo reg,
6731 pretend for GDB it lives in the reload reg we used. */
6732 if (REG_N_DEATHS (REGNO (old)) == 1
6733 && REG_N_SETS (REGNO (old)) == 1)
6735 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6736 alter_reg (REGNO (old), -1);
6742 SET_DEST (PATTERN (temp)) = old;
6747 /* We can't do that, so output an insn to load RELOADREG. */
6749 /* If we have a secondary reload, pick up the secondary register
6750 and icode, if any. If OLDEQUIV and OLD are different or
6751 if this is an in-out reload, recompute whether or not we
6752 still need a secondary register and what the icode should
6753 be. If we still need a secondary register and the class or
6754 icode is different, go back to reloading from OLD if using
6755 OLDEQUIV means that we got the wrong type of register. We
6756 cannot have different class or icode due to an in-out reload
6757 because we don't make such reloads when both the input and
6758 output need secondary reload registers. */
6760 if (! special && rl->secondary_in_reload >= 0)
6762 rtx second_reload_reg = 0;
6763 rtx third_reload_reg = 0;
6764 int secondary_reload = rl->secondary_in_reload;
6765 rtx real_oldequiv = oldequiv;
6768 enum insn_code icode;
6769 enum insn_code tertiary_icode = CODE_FOR_nothing;
6771 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6772 and similarly for OLD.
6773 See comments in get_secondary_reload in reload.c. */
6774 /* If it is a pseudo that cannot be replaced with its
6775 equivalent MEM, we must fall back to reload_in, which
6776 will have all the necessary substitutions registered.
6777 Likewise for a pseudo that can't be replaced with its
6778 equivalent constant.
6780 Take extra care for subregs of such pseudos. Note that
6781 we cannot use reg_equiv_mem in this case because it is
6782 not in the right mode. */
6785 if (GET_CODE (tmp) == SUBREG)
6786 tmp = SUBREG_REG (tmp);
6788 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6789 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6790 || reg_equiv_constant[REGNO (tmp)] != 0))
6792 if (! reg_equiv_mem[REGNO (tmp)]
6793 || num_not_at_initial_offset
6794 || GET_CODE (oldequiv) == SUBREG)
6795 real_oldequiv = rl->in;
6797 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6801 if (GET_CODE (tmp) == SUBREG)
6802 tmp = SUBREG_REG (tmp);
6804 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6805 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6806 || reg_equiv_constant[REGNO (tmp)] != 0))
6808 if (! reg_equiv_mem[REGNO (tmp)]
6809 || num_not_at_initial_offset
6810 || GET_CODE (old) == SUBREG)
6813 real_old = reg_equiv_mem[REGNO (tmp)];
6816 second_reload_reg = rld[secondary_reload].reg_rtx;
6817 if (rld[secondary_reload].secondary_in_reload >= 0)
6819 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6821 third_reload_reg = rld[tertiary_reload].reg_rtx;
6822 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6823 /* We'd have to add more code for quartary reloads. */
6824 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6826 icode = rl->secondary_in_icode;
6828 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6829 || (rl->in != 0 && rl->out != 0))
6831 secondary_reload_info sri, sri2;
6832 enum reg_class new_class, new_t_class;
6834 sri.icode = CODE_FOR_nothing;
6835 sri.prev_sri = NULL;
6836 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6839 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6840 second_reload_reg = 0;
6841 else if (new_class == NO_REGS)
6843 if (reload_adjust_reg_for_icode (&second_reload_reg,
6844 third_reload_reg, sri.icode))
6845 icode = sri.icode, third_reload_reg = 0;
6847 oldequiv = old, real_oldequiv = real_old;
6849 else if (sri.icode != CODE_FOR_nothing)
6850 /* We currently lack a way to express this in reloads. */
6854 sri2.icode = CODE_FOR_nothing;
6855 sri2.prev_sri = &sri;
6856 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6857 new_class, mode, &sri);
6858 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6860 if (reload_adjust_reg_for_temp (&second_reload_reg,
6863 third_reload_reg = 0, tertiary_icode = sri2.icode;
6865 oldequiv = old, real_oldequiv = real_old;
6867 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6869 rtx intermediate = second_reload_reg;
6871 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6873 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6876 second_reload_reg = intermediate;
6877 tertiary_icode = sri2.icode;
6880 oldequiv = old, real_oldequiv = real_old;
6882 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6884 rtx intermediate = second_reload_reg;
6886 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6888 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6891 second_reload_reg = intermediate;
6892 tertiary_icode = sri2.icode;
6895 oldequiv = old, real_oldequiv = real_old;
6898 /* This could be handled more intelligently too. */
6899 oldequiv = old, real_oldequiv = real_old;
6903 /* If we still need a secondary reload register, check
6904 to see if it is being used as a scratch or intermediate
6905 register and generate code appropriately. If we need
6906 a scratch register, use REAL_OLDEQUIV since the form of
6907 the insn may depend on the actual address if it is
6910 if (second_reload_reg)
6912 if (icode != CODE_FOR_nothing)
6914 /* We'd have to add extra code to handle this case. */
6915 gcc_assert (!third_reload_reg);
6917 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6918 second_reload_reg));
6923 /* See if we need a scratch register to load the
6924 intermediate register (a tertiary reload). */
6925 if (tertiary_icode != CODE_FOR_nothing)
6927 emit_insn ((GEN_FCN (tertiary_icode)
6928 (second_reload_reg, real_oldequiv,
6929 third_reload_reg)));
6931 else if (third_reload_reg)
6933 gen_reload (third_reload_reg, real_oldequiv,
6936 gen_reload (second_reload_reg, third_reload_reg,
6941 gen_reload (second_reload_reg, real_oldequiv,
6945 oldequiv = second_reload_reg;
6950 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6952 rtx real_oldequiv = oldequiv;
6954 if ((REG_P (oldequiv)
6955 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6956 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6957 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6958 || (GET_CODE (oldequiv) == SUBREG
6959 && REG_P (SUBREG_REG (oldequiv))
6960 && (REGNO (SUBREG_REG (oldequiv))
6961 >= FIRST_PSEUDO_REGISTER)
6962 && ((reg_equiv_memory_loc
6963 [REGNO (SUBREG_REG (oldequiv))] != 0)
6964 || (reg_equiv_constant
6965 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6966 || (CONSTANT_P (oldequiv)
6967 && (PREFERRED_RELOAD_CLASS (oldequiv,
6968 REGNO_REG_CLASS (REGNO (reloadreg)))
6970 real_oldequiv = rl->in;
6971 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6975 if (flag_non_call_exceptions)
6976 copy_eh_notes (insn, get_insns ());
6978 /* End this sequence. */
6979 *where = get_insns ();
6982 /* Update reload_override_in so that delete_address_reloads_1
6983 can see the actual register usage. */
6985 reload_override_in[j] = oldequiv;
6988 /* Generate insns to for the output reload RL, which is for the insn described
6989 by CHAIN and has the number J. */
6991 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6995 rtx insn = chain->insn;
6998 enum machine_mode mode;
7002 if (rl->when_needed == RELOAD_OTHER)
7005 push_to_sequence (output_reload_insns[rl->opnum]);
7007 rl_reg_rtx = reload_reg_rtx_for_output[j];
7008 mode = GET_MODE (rl_reg_rtx);
7010 reloadreg = rl_reg_rtx;
7012 /* If we need two reload regs, set RELOADREG to the intermediate
7013 one, since it will be stored into OLD. We might need a secondary
7014 register only for an input reload, so check again here. */
7016 if (rl->secondary_out_reload >= 0)
7019 int secondary_reload = rl->secondary_out_reload;
7020 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7022 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7023 && reg_equiv_mem[REGNO (old)] != 0)
7024 real_old = reg_equiv_mem[REGNO (old)];
7026 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7028 rtx second_reloadreg = reloadreg;
7029 reloadreg = rld[secondary_reload].reg_rtx;
7031 /* See if RELOADREG is to be used as a scratch register
7032 or as an intermediate register. */
7033 if (rl->secondary_out_icode != CODE_FOR_nothing)
7035 /* We'd have to add extra code to handle this case. */
7036 gcc_assert (tertiary_reload < 0);
7038 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7039 (real_old, second_reloadreg, reloadreg)));
7044 /* See if we need both a scratch and intermediate reload
7047 enum insn_code tertiary_icode
7048 = rld[secondary_reload].secondary_out_icode;
7050 /* We'd have to add more code for quartary reloads. */
7051 gcc_assert (tertiary_reload < 0
7052 || rld[tertiary_reload].secondary_out_reload < 0);
7054 if (GET_MODE (reloadreg) != mode)
7055 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7057 if (tertiary_icode != CODE_FOR_nothing)
7059 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7062 /* Copy primary reload reg to secondary reload reg.
7063 (Note that these have been swapped above, then
7064 secondary reload reg to OLD using our insn.) */
7066 /* If REAL_OLD is a paradoxical SUBREG, remove it
7067 and try to put the opposite SUBREG on
7069 if (GET_CODE (real_old) == SUBREG
7070 && (GET_MODE_SIZE (GET_MODE (real_old))
7071 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7072 && 0 != (tem = gen_lowpart_common
7073 (GET_MODE (SUBREG_REG (real_old)),
7075 real_old = SUBREG_REG (real_old), reloadreg = tem;
7077 gen_reload (reloadreg, second_reloadreg,
7078 rl->opnum, rl->when_needed);
7079 emit_insn ((GEN_FCN (tertiary_icode)
7080 (real_old, reloadreg, third_reloadreg)));
7086 /* Copy between the reload regs here and then to
7089 gen_reload (reloadreg, second_reloadreg,
7090 rl->opnum, rl->when_needed);
7091 if (tertiary_reload >= 0)
7093 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7095 gen_reload (third_reloadreg, reloadreg,
7096 rl->opnum, rl->when_needed);
7097 reloadreg = third_reloadreg;
7104 /* Output the last reload insn. */
7109 /* Don't output the last reload if OLD is not the dest of
7110 INSN and is in the src and is clobbered by INSN. */
7111 if (! flag_expensive_optimizations
7113 || !(set = single_set (insn))
7114 || rtx_equal_p (old, SET_DEST (set))
7115 || !reg_mentioned_p (old, SET_SRC (set))
7116 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7117 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7118 gen_reload (old, reloadreg, rl->opnum,
7122 /* Look at all insns we emitted, just to be safe. */
7123 for (p = get_insns (); p; p = NEXT_INSN (p))
7126 rtx pat = PATTERN (p);
7128 /* If this output reload doesn't come from a spill reg,
7129 clear any memory of reloaded copies of the pseudo reg.
7130 If this output reload comes from a spill reg,
7131 reg_has_output_reload will make this do nothing. */
7132 note_stores (pat, forget_old_reloads_1, NULL);
7134 if (reg_mentioned_p (rl_reg_rtx, pat))
7136 rtx set = single_set (insn);
7137 if (reload_spill_index[j] < 0
7139 && SET_SRC (set) == rl_reg_rtx)
7141 int src = REGNO (SET_SRC (set));
7143 reload_spill_index[j] = src;
7144 SET_HARD_REG_BIT (reg_is_output_reload, src);
7145 if (find_regno_note (insn, REG_DEAD, src))
7146 SET_HARD_REG_BIT (reg_reloaded_died, src);
7148 if (HARD_REGISTER_P (rl_reg_rtx))
7150 int s = rl->secondary_out_reload;
7151 set = single_set (p);
7152 /* If this reload copies only to the secondary reload
7153 register, the secondary reload does the actual
7155 if (s >= 0 && set == NULL_RTX)
7156 /* We can't tell what function the secondary reload
7157 has and where the actual store to the pseudo is
7158 made; leave new_spill_reg_store alone. */
7161 && SET_SRC (set) == rl_reg_rtx
7162 && SET_DEST (set) == rld[s].reg_rtx)
7164 /* Usually the next instruction will be the
7165 secondary reload insn; if we can confirm
7166 that it is, setting new_spill_reg_store to
7167 that insn will allow an extra optimization. */
7168 rtx s_reg = rld[s].reg_rtx;
7169 rtx next = NEXT_INSN (p);
7170 rld[s].out = rl->out;
7171 rld[s].out_reg = rl->out_reg;
7172 set = single_set (next);
7173 if (set && SET_SRC (set) == s_reg
7174 && ! new_spill_reg_store[REGNO (s_reg)])
7176 SET_HARD_REG_BIT (reg_is_output_reload,
7178 new_spill_reg_store[REGNO (s_reg)] = next;
7182 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7187 if (rl->when_needed == RELOAD_OTHER)
7189 emit_insn (other_output_reload_insns[rl->opnum]);
7190 other_output_reload_insns[rl->opnum] = get_insns ();
7193 output_reload_insns[rl->opnum] = get_insns ();
7195 if (flag_non_call_exceptions)
7196 copy_eh_notes (insn, get_insns ());
7201 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7202 and has the number J. */
7204 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7206 rtx insn = chain->insn;
7207 rtx old = (rl->in && MEM_P (rl->in)
7208 ? rl->in_reg : rl->in);
7209 rtx reg_rtx = rl->reg_rtx;
7213 enum machine_mode mode;
7215 /* Determine the mode to reload in.
7216 This is very tricky because we have three to choose from.
7217 There is the mode the insn operand wants (rl->inmode).
7218 There is the mode of the reload register RELOADREG.
7219 There is the intrinsic mode of the operand, which we could find
7220 by stripping some SUBREGs.
7221 It turns out that RELOADREG's mode is irrelevant:
7222 we can change that arbitrarily.
7224 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7225 then the reload reg may not support QImode moves, so use SImode.
7226 If foo is in memory due to spilling a pseudo reg, this is safe,
7227 because the QImode value is in the least significant part of a
7228 slot big enough for a SImode. If foo is some other sort of
7229 memory reference, then it is impossible to reload this case,
7230 so previous passes had better make sure this never happens.
7232 Then consider a one-word union which has SImode and one of its
7233 members is a float, being fetched as (SUBREG:SF union:SI).
7234 We must fetch that as SFmode because we could be loading into
7235 a float-only register. In this case OLD's mode is correct.
7237 Consider an immediate integer: it has VOIDmode. Here we need
7238 to get a mode from something else.
7240 In some cases, there is a fourth mode, the operand's
7241 containing mode. If the insn specifies a containing mode for
7242 this operand, it overrides all others.
7244 I am not sure whether the algorithm here is always right,
7245 but it does the right things in those cases. */
7247 mode = GET_MODE (old);
7248 if (mode == VOIDmode)
7251 /* We cannot use gen_lowpart_common since it can do the wrong thing
7252 when REG_RTX has a multi-word mode. Note that REG_RTX must
7253 always be a REG here. */
7254 if (GET_MODE (reg_rtx) != mode)
7255 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7257 reload_reg_rtx_for_input[j] = reg_rtx;
7260 /* AUTO_INC reloads need to be handled even if inherited. We got an
7261 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7262 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7263 && ! rtx_equal_p (reg_rtx, old)
7265 emit_input_reload_insns (chain, rld + j, old, j);
7267 /* When inheriting a wider reload, we have a MEM in rl->in,
7268 e.g. inheriting a SImode output reload for
7269 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7270 if (optimize && reload_inherited[j] && rl->in
7272 && MEM_P (rl->in_reg)
7273 && reload_spill_index[j] >= 0
7274 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7275 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7277 /* If we are reloading a register that was recently stored in with an
7278 output-reload, see if we can prove there was
7279 actually no need to store the old value in it. */
7282 && (reload_inherited[j] || reload_override_in[j])
7285 && spill_reg_store[REGNO (reg_rtx)] != 0
7287 /* There doesn't seem to be any reason to restrict this to pseudos
7288 and doing so loses in the case where we are copying from a
7289 register of the wrong class. */
7290 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7292 /* The insn might have already some references to stackslots
7293 replaced by MEMs, while reload_out_reg still names the
7295 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7296 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7297 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7300 /* Do output reloading for reload RL, which is for the insn described by
7301 CHAIN and has the number J.
7302 ??? At some point we need to support handling output reloads of
7303 JUMP_INSNs or insns that set cc0. */
7305 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7308 rtx insn = chain->insn;
7309 /* If this is an output reload that stores something that is
7310 not loaded in this same reload, see if we can eliminate a previous
7312 rtx pseudo = rl->out_reg;
7313 rtx reg_rtx = rl->reg_rtx;
7315 if (rl->out && reg_rtx)
7317 enum machine_mode mode;
7319 /* Determine the mode to reload in.
7320 See comments above (for input reloading). */
7321 mode = GET_MODE (rl->out);
7322 if (mode == VOIDmode)
7324 /* VOIDmode should never happen for an output. */
7325 if (asm_noperands (PATTERN (insn)) < 0)
7326 /* It's the compiler's fault. */
7327 fatal_insn ("VOIDmode on an output", insn);
7328 error_for_asm (insn, "output operand is constant in %<asm%>");
7329 /* Prevent crash--use something we know is valid. */
7331 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7333 if (GET_MODE (reg_rtx) != mode)
7334 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7336 reload_reg_rtx_for_output[j] = reg_rtx;
7341 && ! rtx_equal_p (rl->in_reg, pseudo)
7342 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7343 && reg_last_reload_reg[REGNO (pseudo)])
7345 int pseudo_no = REGNO (pseudo);
7346 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7348 /* We don't need to test full validity of last_regno for
7349 inherit here; we only want to know if the store actually
7350 matches the pseudo. */
7351 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7352 && reg_reloaded_contents[last_regno] == pseudo_no
7353 && spill_reg_store[last_regno]
7354 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7355 delete_output_reload (insn, j, last_regno, reg_rtx);
7361 || rtx_equal_p (old, reg_rtx))
7364 /* An output operand that dies right away does need a reload,
7365 but need not be copied from it. Show the new location in the
7367 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7368 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7370 XEXP (note, 0) = reg_rtx;
7373 /* Likewise for a SUBREG of an operand that dies. */
7374 else if (GET_CODE (old) == SUBREG
7375 && REG_P (SUBREG_REG (old))
7376 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7379 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7382 else if (GET_CODE (old) == SCRATCH)
7383 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7384 but we don't want to make an output reload. */
7387 /* If is a JUMP_INSN, we can't support output reloads yet. */
7388 gcc_assert (NONJUMP_INSN_P (insn));
7390 emit_output_reload_insns (chain, rld + j, j);
7393 /* A reload copies values of MODE from register SRC to register DEST.
7394 Return true if it can be treated for inheritance purposes like a
7395 group of reloads, each one reloading a single hard register. The
7396 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7397 occupy the same number of hard registers. */
7400 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7401 int src ATTRIBUTE_UNUSED,
7402 enum machine_mode mode ATTRIBUTE_UNUSED)
7404 #ifdef CANNOT_CHANGE_MODE_CLASS
7405 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7406 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7412 /* Output insns to reload values in and out of the chosen reload regs. */
7415 emit_reload_insns (struct insn_chain *chain)
7417 rtx insn = chain->insn;
7421 CLEAR_HARD_REG_SET (reg_reloaded_died);
7423 for (j = 0; j < reload_n_operands; j++)
7424 input_reload_insns[j] = input_address_reload_insns[j]
7425 = inpaddr_address_reload_insns[j]
7426 = output_reload_insns[j] = output_address_reload_insns[j]
7427 = outaddr_address_reload_insns[j]
7428 = other_output_reload_insns[j] = 0;
7429 other_input_address_reload_insns = 0;
7430 other_input_reload_insns = 0;
7431 operand_reload_insns = 0;
7432 other_operand_reload_insns = 0;
7434 /* Dump reloads into the dump file. */
7437 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7438 debug_reload_to_stream (dump_file);
7441 /* Now output the instructions to copy the data into and out of the
7442 reload registers. Do these in the order that the reloads were reported,
7443 since reloads of base and index registers precede reloads of operands
7444 and the operands may need the base and index registers reloaded. */
7446 for (j = 0; j < n_reloads; j++)
7448 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7452 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7453 new_spill_reg_store[i] = 0;
7456 do_input_reload (chain, rld + j, j);
7457 do_output_reload (chain, rld + j, j);
7460 /* Now write all the insns we made for reloads in the order expected by
7461 the allocation functions. Prior to the insn being reloaded, we write
7462 the following reloads:
7464 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7466 RELOAD_OTHER reloads.
7468 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7469 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7470 RELOAD_FOR_INPUT reload for the operand.
7472 RELOAD_FOR_OPADDR_ADDRS reloads.
7474 RELOAD_FOR_OPERAND_ADDRESS reloads.
7476 After the insn being reloaded, we write the following:
7478 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7479 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7480 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7481 reloads for the operand. The RELOAD_OTHER output reloads are
7482 output in descending order by reload number. */
7484 emit_insn_before (other_input_address_reload_insns, insn);
7485 emit_insn_before (other_input_reload_insns, insn);
7487 for (j = 0; j < reload_n_operands; j++)
7489 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7490 emit_insn_before (input_address_reload_insns[j], insn);
7491 emit_insn_before (input_reload_insns[j], insn);
7494 emit_insn_before (other_operand_reload_insns, insn);
7495 emit_insn_before (operand_reload_insns, insn);
7497 for (j = 0; j < reload_n_operands; j++)
7499 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7500 x = emit_insn_after (output_address_reload_insns[j], x);
7501 x = emit_insn_after (output_reload_insns[j], x);
7502 emit_insn_after (other_output_reload_insns[j], x);
7505 /* For all the spill regs newly reloaded in this instruction,
7506 record what they were reloaded from, so subsequent instructions
7507 can inherit the reloads.
7509 Update spill_reg_store for the reloads of this insn.
7510 Copy the elements that were updated in the loop above. */
7512 for (j = 0; j < n_reloads; j++)
7514 int r = reload_order[j];
7515 int i = reload_spill_index[r];
7517 /* If this is a non-inherited input reload from a pseudo, we must
7518 clear any memory of a previous store to the same pseudo. Only do
7519 something if there will not be an output reload for the pseudo
7521 if (rld[r].in_reg != 0
7522 && ! (reload_inherited[r] || reload_override_in[r]))
7524 rtx reg = rld[r].in_reg;
7526 if (GET_CODE (reg) == SUBREG)
7527 reg = SUBREG_REG (reg);
7530 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7531 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7533 int nregno = REGNO (reg);
7535 if (reg_last_reload_reg[nregno])
7537 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7539 if (reg_reloaded_contents[last_regno] == nregno)
7540 spill_reg_store[last_regno] = 0;
7545 /* I is nonneg if this reload used a register.
7546 If rld[r].reg_rtx is 0, this is an optional reload
7547 that we opted to ignore. */
7549 if (i >= 0 && rld[r].reg_rtx != 0)
7551 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7554 /* For a multi register reload, we need to check if all or part
7555 of the value lives to the end. */
7556 for (k = 0; k < nr; k++)
7557 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7558 rld[r].when_needed))
7559 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7561 /* Maybe the spill reg contains a copy of reload_out. */
7563 && (REG_P (rld[r].out)
7567 || REG_P (rld[r].out_reg)))
7570 enum machine_mode mode;
7573 reg = reload_reg_rtx_for_output[r];
7574 mode = GET_MODE (reg);
7575 regno = REGNO (reg);
7576 nregs = hard_regno_nregs[regno][mode];
7577 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7578 rld[r].when_needed))
7580 rtx out = (REG_P (rld[r].out)
7584 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7585 int out_regno = REGNO (out);
7586 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7587 : hard_regno_nregs[out_regno][mode]);
7590 spill_reg_store[regno] = new_spill_reg_store[regno];
7591 spill_reg_stored_to[regno] = out;
7592 reg_last_reload_reg[out_regno] = reg;
7594 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7595 && nregs == out_nregs
7596 && inherit_piecemeal_p (out_regno, regno, mode));
7598 /* If OUT_REGNO is a hard register, it may occupy more than
7599 one register. If it does, say what is in the
7600 rest of the registers assuming that both registers
7601 agree on how many words the object takes. If not,
7602 invalidate the subsequent registers. */
7604 if (HARD_REGISTER_NUM_P (out_regno))
7605 for (k = 1; k < out_nregs; k++)
7606 reg_last_reload_reg[out_regno + k]
7607 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7609 /* Now do the inverse operation. */
7610 for (k = 0; k < nregs; k++)
7612 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7613 reg_reloaded_contents[regno + k]
7614 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7617 reg_reloaded_insn[regno + k] = insn;
7618 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7619 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7620 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7623 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7628 /* Maybe the spill reg contains a copy of reload_in. Only do
7629 something if there will not be an output reload for
7630 the register being reloaded. */
7631 else if (rld[r].out_reg == 0
7633 && ((REG_P (rld[r].in)
7634 && !HARD_REGISTER_P (rld[r].in)
7635 && !REGNO_REG_SET_P (®_has_output_reload,
7637 || (REG_P (rld[r].in_reg)
7638 && !REGNO_REG_SET_P (®_has_output_reload,
7639 REGNO (rld[r].in_reg))))
7640 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7643 enum machine_mode mode;
7646 reg = reload_reg_rtx_for_input[r];
7647 mode = GET_MODE (reg);
7648 regno = REGNO (reg);
7649 nregs = hard_regno_nregs[regno][mode];
7650 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7651 rld[r].when_needed))
7658 if (REG_P (rld[r].in)
7659 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7661 else if (REG_P (rld[r].in_reg))
7664 in = XEXP (rld[r].in_reg, 0);
7665 in_regno = REGNO (in);
7667 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7668 : hard_regno_nregs[in_regno][mode]);
7670 reg_last_reload_reg[in_regno] = reg;
7672 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7673 && nregs == in_nregs
7674 && inherit_piecemeal_p (regno, in_regno, mode));
7676 if (HARD_REGISTER_NUM_P (in_regno))
7677 for (k = 1; k < in_nregs; k++)
7678 reg_last_reload_reg[in_regno + k]
7679 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7681 /* Unless we inherited this reload, show we haven't
7682 recently done a store.
7683 Previous stores of inherited auto_inc expressions
7684 also have to be discarded. */
7685 if (! reload_inherited[r]
7686 || (rld[r].out && ! rld[r].out_reg))
7687 spill_reg_store[regno] = 0;
7689 for (k = 0; k < nregs; k++)
7691 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7692 reg_reloaded_contents[regno + k]
7693 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7696 reg_reloaded_insn[regno + k] = insn;
7697 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7698 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7699 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7702 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7709 /* The following if-statement was #if 0'd in 1.34 (or before...).
7710 It's reenabled in 1.35 because supposedly nothing else
7711 deals with this problem. */
7713 /* If a register gets output-reloaded from a non-spill register,
7714 that invalidates any previous reloaded copy of it.
7715 But forget_old_reloads_1 won't get to see it, because
7716 it thinks only about the original insn. So invalidate it here.
7717 Also do the same thing for RELOAD_OTHER constraints where the
7718 output is discarded. */
7720 && ((rld[r].out != 0
7721 && (REG_P (rld[r].out)
7722 || (MEM_P (rld[r].out)
7723 && REG_P (rld[r].out_reg))))
7724 || (rld[r].out == 0 && rld[r].out_reg
7725 && REG_P (rld[r].out_reg))))
7727 rtx out = ((rld[r].out && REG_P (rld[r].out))
7728 ? rld[r].out : rld[r].out_reg);
7729 int out_regno = REGNO (out);
7730 enum machine_mode mode = GET_MODE (out);
7732 /* REG_RTX is now set or clobbered by the main instruction.
7733 As the comment above explains, forget_old_reloads_1 only
7734 sees the original instruction, and there is no guarantee
7735 that the original instruction also clobbered REG_RTX.
7736 For example, if find_reloads sees that the input side of
7737 a matched operand pair dies in this instruction, it may
7738 use the input register as the reload register.
7740 Calling forget_old_reloads_1 is a waste of effort if
7741 REG_RTX is also the output register.
7743 If we know that REG_RTX holds the value of a pseudo
7744 register, the code after the call will record that fact. */
7745 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7746 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7748 if (!HARD_REGISTER_NUM_P (out_regno))
7750 rtx src_reg, store_insn = NULL_RTX;
7752 reg_last_reload_reg[out_regno] = 0;
7754 /* If we can find a hard register that is stored, record
7755 the storing insn so that we may delete this insn with
7756 delete_output_reload. */
7757 src_reg = reload_reg_rtx_for_output[r];
7759 /* If this is an optional reload, try to find the source reg
7760 from an input reload. */
7763 rtx set = single_set (insn);
7764 if (set && SET_DEST (set) == rld[r].out)
7768 src_reg = SET_SRC (set);
7770 for (k = 0; k < n_reloads; k++)
7772 if (rld[k].in == src_reg)
7774 src_reg = reload_reg_rtx_for_input[k];
7781 store_insn = new_spill_reg_store[REGNO (src_reg)];
7782 if (src_reg && REG_P (src_reg)
7783 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7785 int src_regno, src_nregs, k;
7788 gcc_assert (GET_MODE (src_reg) == mode);
7789 src_regno = REGNO (src_reg);
7790 src_nregs = hard_regno_nregs[src_regno][mode];
7791 /* The place where to find a death note varies with
7792 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7793 necessarily checked exactly in the code that moves
7794 notes, so just check both locations. */
7795 note = find_regno_note (insn, REG_DEAD, src_regno);
7796 if (! note && store_insn)
7797 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7798 for (k = 0; k < src_nregs; k++)
7800 spill_reg_store[src_regno + k] = store_insn;
7801 spill_reg_stored_to[src_regno + k] = out;
7802 reg_reloaded_contents[src_regno + k] = out_regno;
7803 reg_reloaded_insn[src_regno + k] = store_insn;
7804 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
7805 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
7806 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
7808 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7811 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7813 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
7815 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7817 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7819 reg_last_reload_reg[out_regno] = src_reg;
7820 /* We have to set reg_has_output_reload here, or else
7821 forget_old_reloads_1 will clear reg_last_reload_reg
7823 SET_REGNO_REG_SET (®_has_output_reload,
7829 int k, out_nregs = hard_regno_nregs[out_regno][mode];
7831 for (k = 0; k < out_nregs; k++)
7832 reg_last_reload_reg[out_regno + k] = 0;
7836 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7839 /* Go through the motions to emit INSN and test if it is strictly valid.
7840 Return the emitted insn if valid, else return NULL. */
7843 emit_insn_if_valid_for_reload (rtx insn)
7845 rtx last = get_last_insn ();
7848 insn = emit_insn (insn);
7849 code = recog_memoized (insn);
7853 extract_insn (insn);
7854 /* We want constrain operands to treat this insn strictly in its
7855 validity determination, i.e., the way it would after reload has
7857 if (constrain_operands (1))
7861 delete_insns_since (last);
7865 /* Emit code to perform a reload from IN (which may be a reload register) to
7866 OUT (which may also be a reload register). IN or OUT is from operand
7867 OPNUM with reload type TYPE.
7869 Returns first insn emitted. */
7872 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7874 rtx last = get_last_insn ();
7877 /* If IN is a paradoxical SUBREG, remove it and try to put the
7878 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7879 if (GET_CODE (in) == SUBREG
7880 && (GET_MODE_SIZE (GET_MODE (in))
7881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7882 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7883 in = SUBREG_REG (in), out = tem;
7884 else if (GET_CODE (out) == SUBREG
7885 && (GET_MODE_SIZE (GET_MODE (out))
7886 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7887 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7888 out = SUBREG_REG (out), in = tem;
7890 /* How to do this reload can get quite tricky. Normally, we are being
7891 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7892 register that didn't get a hard register. In that case we can just
7893 call emit_move_insn.
7895 We can also be asked to reload a PLUS that adds a register or a MEM to
7896 another register, constant or MEM. This can occur during frame pointer
7897 elimination and while reloading addresses. This case is handled by
7898 trying to emit a single insn to perform the add. If it is not valid,
7899 we use a two insn sequence.
7901 Or we can be asked to reload an unary operand that was a fragment of
7902 an addressing mode, into a register. If it isn't recognized as-is,
7903 we try making the unop operand and the reload-register the same:
7904 (set reg:X (unop:X expr:Y))
7905 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7907 Finally, we could be called to handle an 'o' constraint by putting
7908 an address into a register. In that case, we first try to do this
7909 with a named pattern of "reload_load_address". If no such pattern
7910 exists, we just emit a SET insn and hope for the best (it will normally
7911 be valid on machines that use 'o').
7913 This entire process is made complex because reload will never
7914 process the insns we generate here and so we must ensure that
7915 they will fit their constraints and also by the fact that parts of
7916 IN might be being reloaded separately and replaced with spill registers.
7917 Because of this, we are, in some sense, just guessing the right approach
7918 here. The one listed above seems to work.
7920 ??? At some point, this whole thing needs to be rethought. */
7922 if (GET_CODE (in) == PLUS
7923 && (REG_P (XEXP (in, 0))
7924 || GET_CODE (XEXP (in, 0)) == SUBREG
7925 || MEM_P (XEXP (in, 0)))
7926 && (REG_P (XEXP (in, 1))
7927 || GET_CODE (XEXP (in, 1)) == SUBREG
7928 || CONSTANT_P (XEXP (in, 1))
7929 || MEM_P (XEXP (in, 1))))
7931 /* We need to compute the sum of a register or a MEM and another
7932 register, constant, or MEM, and put it into the reload
7933 register. The best possible way of doing this is if the machine
7934 has a three-operand ADD insn that accepts the required operands.
7936 The simplest approach is to try to generate such an insn and see if it
7937 is recognized and matches its constraints. If so, it can be used.
7939 It might be better not to actually emit the insn unless it is valid,
7940 but we need to pass the insn as an operand to `recog' and
7941 `extract_insn' and it is simpler to emit and then delete the insn if
7942 not valid than to dummy things up. */
7944 rtx op0, op1, tem, insn;
7947 op0 = find_replacement (&XEXP (in, 0));
7948 op1 = find_replacement (&XEXP (in, 1));
7950 /* Since constraint checking is strict, commutativity won't be
7951 checked, so we need to do that here to avoid spurious failure
7952 if the add instruction is two-address and the second operand
7953 of the add is the same as the reload reg, which is frequently
7954 the case. If the insn would be A = B + A, rearrange it so
7955 it will be A = A + B as constrain_operands expects. */
7957 if (REG_P (XEXP (in, 1))
7958 && REGNO (out) == REGNO (XEXP (in, 1)))
7959 tem = op0, op0 = op1, op1 = tem;
7961 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7962 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7964 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7968 /* If that failed, we must use a conservative two-insn sequence.
7970 Use a move to copy one operand into the reload register. Prefer
7971 to reload a constant, MEM or pseudo since the move patterns can
7972 handle an arbitrary operand. If OP1 is not a constant, MEM or
7973 pseudo and OP1 is not a valid operand for an add instruction, then
7976 After reloading one of the operands into the reload register, add
7977 the reload register to the output register.
7979 If there is another way to do this for a specific machine, a
7980 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7983 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7985 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7987 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7988 || (code != CODE_FOR_nothing
7989 && ! ((*insn_data[code].operand[2].predicate)
7990 (op1, insn_data[code].operand[2].mode))))
7991 tem = op0, op0 = op1, op1 = tem;
7993 gen_reload (out, op0, opnum, type);
7995 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7996 This fixes a problem on the 32K where the stack pointer cannot
7997 be used as an operand of an add insn. */
7999 if (rtx_equal_p (op0, op1))
8002 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8005 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8006 set_unique_reg_note (insn, REG_EQUIV, in);
8010 /* If that failed, copy the address register to the reload register.
8011 Then add the constant to the reload register. */
8013 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8014 gen_reload (out, op1, opnum, type);
8015 insn = emit_insn (gen_add2_insn (out, op0));
8016 set_unique_reg_note (insn, REG_EQUIV, in);
8019 #ifdef SECONDARY_MEMORY_NEEDED
8020 /* If we need a memory location to do the move, do it that way. */
8021 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
8022 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8023 && (REG_P (out) || GET_CODE (out) == SUBREG)
8024 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8025 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8026 REGNO_REG_CLASS (reg_or_subregno (out)),
8029 /* Get the memory to use and rewrite both registers to its mode. */
8030 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8032 if (GET_MODE (loc) != GET_MODE (out))
8033 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8035 if (GET_MODE (loc) != GET_MODE (in))
8036 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8038 gen_reload (loc, in, opnum, type);
8039 gen_reload (out, loc, opnum, type);
8042 else if (REG_P (out) && UNARY_P (in))
8049 op1 = find_replacement (&XEXP (in, 0));
8050 if (op1 != XEXP (in, 0))
8051 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8053 /* First, try a plain SET. */
8054 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8058 /* If that failed, move the inner operand to the reload
8059 register, and try the same unop with the inner expression
8060 replaced with the reload register. */
8062 if (GET_MODE (op1) != GET_MODE (out))
8063 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8067 gen_reload (out_moded, op1, opnum, type);
8070 = gen_rtx_SET (VOIDmode, out,
8071 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8073 insn = emit_insn_if_valid_for_reload (insn);
8076 set_unique_reg_note (insn, REG_EQUIV, in);
8080 fatal_insn ("Failure trying to reload:", set);
8082 /* If IN is a simple operand, use gen_move_insn. */
8083 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8085 tem = emit_insn (gen_move_insn (out, in));
8086 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8087 mark_jump_label (in, tem, 0);
8090 #ifdef HAVE_reload_load_address
8091 else if (HAVE_reload_load_address)
8092 emit_insn (gen_reload_load_address (out, in));
8095 /* Otherwise, just write (set OUT IN) and hope for the best. */
8097 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8099 /* Return the first insn emitted.
8100 We can not just return get_last_insn, because there may have
8101 been multiple instructions emitted. Also note that gen_move_insn may
8102 emit more than one insn itself, so we can not assume that there is one
8103 insn emitted per emit_insn_before call. */
8105 return last ? NEXT_INSN (last) : get_insns ();
8108 /* Delete a previously made output-reload whose result we now believe
8109 is not needed. First we double-check.
8111 INSN is the insn now being processed.
8112 LAST_RELOAD_REG is the hard register number for which we want to delete
8113 the last output reload.
8114 J is the reload-number that originally used REG. The caller has made
8115 certain that reload J doesn't use REG any longer for input.
8116 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8119 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8121 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8122 rtx reg = spill_reg_stored_to[last_reload_reg];
8125 int n_inherited = 0;
8129 /* It is possible that this reload has been only used to set another reload
8130 we eliminated earlier and thus deleted this instruction too. */
8131 if (INSN_DELETED_P (output_reload_insn))
8134 /* Get the raw pseudo-register referred to. */
8136 while (GET_CODE (reg) == SUBREG)
8137 reg = SUBREG_REG (reg);
8138 substed = reg_equiv_memory_loc[REGNO (reg)];
8140 /* This is unsafe if the operand occurs more often in the current
8141 insn than it is inherited. */
8142 for (k = n_reloads - 1; k >= 0; k--)
8144 rtx reg2 = rld[k].in;
8147 if (MEM_P (reg2) || reload_override_in[k])
8148 reg2 = rld[k].in_reg;
8150 if (rld[k].out && ! rld[k].out_reg)
8151 reg2 = XEXP (rld[k].in_reg, 0);
8153 while (GET_CODE (reg2) == SUBREG)
8154 reg2 = SUBREG_REG (reg2);
8155 if (rtx_equal_p (reg2, reg))
8157 if (reload_inherited[k] || reload_override_in[k] || k == j)
8163 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8164 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8165 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8168 n_occurrences += count_occurrences (PATTERN (insn),
8169 eliminate_regs (substed, 0,
8171 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8173 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8174 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8176 if (n_occurrences > n_inherited)
8179 /* If the pseudo-reg we are reloading is no longer referenced
8180 anywhere between the store into it and here,
8181 and we're within the same basic block, then the value can only
8182 pass through the reload reg and end up here.
8183 Otherwise, give up--return. */
8184 for (i1 = NEXT_INSN (output_reload_insn);
8185 i1 != insn; i1 = NEXT_INSN (i1))
8187 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8189 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8190 && reg_mentioned_p (reg, PATTERN (i1)))
8192 /* If this is USE in front of INSN, we only have to check that
8193 there are no more references than accounted for by inheritance. */
8194 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8196 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8197 i1 = NEXT_INSN (i1);
8199 if (n_occurrences <= n_inherited && i1 == insn)
8205 /* We will be deleting the insn. Remove the spill reg information. */
8206 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8208 spill_reg_store[last_reload_reg + k] = 0;
8209 spill_reg_stored_to[last_reload_reg + k] = 0;
8212 /* The caller has already checked that REG dies or is set in INSN.
8213 It has also checked that we are optimizing, and thus some
8214 inaccuracies in the debugging information are acceptable.
8215 So we could just delete output_reload_insn. But in some cases
8216 we can improve the debugging information without sacrificing
8217 optimization - maybe even improving the code: See if the pseudo
8218 reg has been completely replaced with reload regs. If so, delete
8219 the store insn and forget we had a stack slot for the pseudo. */
8220 if (rld[j].out != rld[j].in
8221 && REG_N_DEATHS (REGNO (reg)) == 1
8222 && REG_N_SETS (REGNO (reg)) == 1
8223 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8224 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8228 /* We know that it was used only between here and the beginning of
8229 the current basic block. (We also know that the last use before
8230 INSN was the output reload we are thinking of deleting, but never
8231 mind that.) Search that range; see if any ref remains. */
8232 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8234 rtx set = single_set (i2);
8236 /* Uses which just store in the pseudo don't count,
8237 since if they are the only uses, they are dead. */
8238 if (set != 0 && SET_DEST (set) == reg)
8243 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8244 && reg_mentioned_p (reg, PATTERN (i2)))
8246 /* Some other ref remains; just delete the output reload we
8248 delete_address_reloads (output_reload_insn, insn);
8249 delete_insn (output_reload_insn);
8254 /* Delete the now-dead stores into this pseudo. Note that this
8255 loop also takes care of deleting output_reload_insn. */
8256 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8258 rtx set = single_set (i2);
8260 if (set != 0 && SET_DEST (set) == reg)
8262 delete_address_reloads (i2, insn);
8270 /* For the debugging info, say the pseudo lives in this reload reg. */
8271 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8272 alter_reg (REGNO (reg), -1);
8276 delete_address_reloads (output_reload_insn, insn);
8277 delete_insn (output_reload_insn);
8281 /* We are going to delete DEAD_INSN. Recursively delete loads of
8282 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8283 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8285 delete_address_reloads (rtx dead_insn, rtx current_insn)
8287 rtx set = single_set (dead_insn);
8288 rtx set2, dst, prev, next;
8291 rtx dst = SET_DEST (set);
8293 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8295 /* If we deleted the store from a reloaded post_{in,de}c expression,
8296 we can delete the matching adds. */
8297 prev = PREV_INSN (dead_insn);
8298 next = NEXT_INSN (dead_insn);
8299 if (! prev || ! next)
8301 set = single_set (next);
8302 set2 = single_set (prev);
8304 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8305 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8306 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8308 dst = SET_DEST (set);
8309 if (! rtx_equal_p (dst, SET_DEST (set2))
8310 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8311 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8312 || (INTVAL (XEXP (SET_SRC (set), 1))
8313 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8315 delete_related_insns (prev);
8316 delete_related_insns (next);
8319 /* Subfunction of delete_address_reloads: process registers found in X. */
8321 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8323 rtx prev, set, dst, i2;
8325 enum rtx_code code = GET_CODE (x);
8329 const char *fmt = GET_RTX_FORMAT (code);
8330 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8333 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8334 else if (fmt[i] == 'E')
8336 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8337 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8344 if (spill_reg_order[REGNO (x)] < 0)
8347 /* Scan backwards for the insn that sets x. This might be a way back due
8349 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8351 code = GET_CODE (prev);
8352 if (code == CODE_LABEL || code == JUMP_INSN)
8356 if (reg_set_p (x, PATTERN (prev)))
8358 if (reg_referenced_p (x, PATTERN (prev)))
8361 if (! prev || INSN_UID (prev) < reload_first_uid)
8363 /* Check that PREV only sets the reload register. */
8364 set = single_set (prev);
8367 dst = SET_DEST (set);
8369 || ! rtx_equal_p (dst, x))
8371 if (! reg_set_p (dst, PATTERN (dead_insn)))
8373 /* Check if DST was used in a later insn -
8374 it might have been inherited. */
8375 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8381 if (reg_referenced_p (dst, PATTERN (i2)))
8383 /* If there is a reference to the register in the current insn,
8384 it might be loaded in a non-inherited reload. If no other
8385 reload uses it, that means the register is set before
8387 if (i2 == current_insn)
8389 for (j = n_reloads - 1; j >= 0; j--)
8390 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8391 || reload_override_in[j] == dst)
8393 for (j = n_reloads - 1; j >= 0; j--)
8394 if (rld[j].in && rld[j].reg_rtx == dst)
8403 /* If DST is still live at CURRENT_INSN, check if it is used for
8404 any reload. Note that even if CURRENT_INSN sets DST, we still
8405 have to check the reloads. */
8406 if (i2 == current_insn)
8408 for (j = n_reloads - 1; j >= 0; j--)
8409 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8410 || reload_override_in[j] == dst)
8412 /* ??? We can't finish the loop here, because dst might be
8413 allocated to a pseudo in this block if no reload in this
8414 block needs any of the classes containing DST - see
8415 spill_hard_reg. There is no easy way to tell this, so we
8416 have to scan till the end of the basic block. */
8418 if (reg_set_p (dst, PATTERN (i2)))
8422 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8423 reg_reloaded_contents[REGNO (dst)] = -1;
8427 /* Output reload-insns to reload VALUE into RELOADREG.
8428 VALUE is an autoincrement or autodecrement RTX whose operand
8429 is a register or memory location;
8430 so reloading involves incrementing that location.
8431 IN is either identical to VALUE, or some cheaper place to reload from.
8433 INC_AMOUNT is the number to increment or decrement by (always positive).
8434 This cannot be deduced from VALUE.
8436 Return the instruction that stores into RELOADREG. */
8439 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8441 /* REG or MEM to be copied and incremented. */
8442 rtx incloc = find_replacement (&XEXP (value, 0));
8443 /* Nonzero if increment after copying. */
8444 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8445 || GET_CODE (value) == POST_MODIFY);
8451 rtx real_in = in == value ? incloc : in;
8453 /* No hard register is equivalent to this register after
8454 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8455 we could inc/dec that register as well (maybe even using it for
8456 the source), but I'm not sure it's worth worrying about. */
8458 reg_last_reload_reg[REGNO (incloc)] = 0;
8460 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8462 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8463 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8467 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8468 inc_amount = -inc_amount;
8470 inc = GEN_INT (inc_amount);
8473 /* If this is post-increment, first copy the location to the reload reg. */
8474 if (post && real_in != reloadreg)
8475 emit_insn (gen_move_insn (reloadreg, real_in));
8479 /* See if we can directly increment INCLOC. Use a method similar to
8480 that in gen_reload. */
8482 last = get_last_insn ();
8483 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8484 gen_rtx_PLUS (GET_MODE (incloc),
8487 code = recog_memoized (add_insn);
8490 extract_insn (add_insn);
8491 if (constrain_operands (1))
8493 /* If this is a pre-increment and we have incremented the value
8494 where it lives, copy the incremented value to RELOADREG to
8495 be used as an address. */
8498 emit_insn (gen_move_insn (reloadreg, incloc));
8503 delete_insns_since (last);
8506 /* If couldn't do the increment directly, must increment in RELOADREG.
8507 The way we do this depends on whether this is pre- or post-increment.
8508 For pre-increment, copy INCLOC to the reload register, increment it
8509 there, then save back. */
8513 if (in != reloadreg)
8514 emit_insn (gen_move_insn (reloadreg, real_in));
8515 emit_insn (gen_add2_insn (reloadreg, inc));
8516 store = emit_insn (gen_move_insn (incloc, reloadreg));
8521 Because this might be a jump insn or a compare, and because RELOADREG
8522 may not be available after the insn in an input reload, we must do
8523 the incrementation before the insn being reloaded for.
8525 We have already copied IN to RELOADREG. Increment the copy in
8526 RELOADREG, save that back, then decrement RELOADREG so it has
8527 the original value. */
8529 emit_insn (gen_add2_insn (reloadreg, inc));
8530 store = emit_insn (gen_move_insn (incloc, reloadreg));
8531 if (GET_CODE (inc) == CONST_INT)
8532 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8534 emit_insn (gen_sub2_insn (reloadreg, inc));
8542 add_auto_inc_notes (rtx insn, rtx x)
8544 enum rtx_code code = GET_CODE (x);
8548 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8551 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8555 /* Scan all the operand sub-expressions. */
8556 fmt = GET_RTX_FORMAT (code);
8557 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8560 add_auto_inc_notes (insn, XEXP (x, i));
8561 else if (fmt[i] == 'E')
8562 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8563 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8568 /* Copy EH notes from an insn to its reloads. */
8570 copy_eh_notes (rtx insn, rtx x)
8572 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8575 for (; x != 0; x = NEXT_INSN (x))
8577 if (may_trap_p (PATTERN (x)))
8579 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8585 /* This is used by reload pass, that does emit some instructions after
8586 abnormal calls moving basic block end, but in fact it wants to emit
8587 them on the edge. Looks for abnormal call edges, find backward the
8588 proper call and fix the damage.
8590 Similar handle instructions throwing exceptions internally. */
8592 fixup_abnormal_edges (void)
8594 bool inserted = false;
8602 /* Look for cases we are interested in - calls or instructions causing
8604 FOR_EACH_EDGE (e, ei, bb->succs)
8606 if (e->flags & EDGE_ABNORMAL_CALL)
8608 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8609 == (EDGE_ABNORMAL | EDGE_EH))
8612 if (e && !CALL_P (BB_END (bb))
8613 && !can_throw_internal (BB_END (bb)))
8617 /* Get past the new insns generated. Allow notes, as the insns
8618 may be already deleted. */
8620 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8621 && !can_throw_internal (insn)
8622 && insn != BB_HEAD (bb))
8623 insn = PREV_INSN (insn);
8625 if (CALL_P (insn) || can_throw_internal (insn))
8629 stop = NEXT_INSN (BB_END (bb));
8631 insn = NEXT_INSN (insn);
8633 FOR_EACH_EDGE (e, ei, bb->succs)
8634 if (e->flags & EDGE_FALLTHRU)
8637 while (insn && insn != stop)
8639 next = NEXT_INSN (insn);
8644 /* Sometimes there's still the return value USE.
8645 If it's placed after a trapping call (i.e. that
8646 call is the last insn anyway), we have no fallthru
8647 edge. Simply delete this use and don't try to insert
8648 on the non-existent edge. */
8649 if (GET_CODE (PATTERN (insn)) != USE)
8651 /* We're not deleting it, we're moving it. */
8652 INSN_DELETED_P (insn) = 0;
8653 PREV_INSN (insn) = NULL_RTX;
8654 NEXT_INSN (insn) = NULL_RTX;
8656 insert_insn_on_edge (insn, e);
8660 else if (!BARRIER_P (insn))
8661 set_block_for_insn (insn, NULL);
8666 /* It may be that we don't find any such trapping insn. In this
8667 case we discovered quite late that the insn that had been
8668 marked as can_throw_internal in fact couldn't trap at all.
8669 So we should in fact delete the EH edges out of the block. */
8671 purge_dead_edges (bb);
8675 /* We've possibly turned single trapping insn into multiple ones. */
8676 if (flag_non_call_exceptions)
8679 blocks = sbitmap_alloc (last_basic_block);
8680 sbitmap_ones (blocks);
8681 find_many_sub_basic_blocks (blocks);
8682 sbitmap_free (blocks);
8686 commit_edge_insertions ();
8688 #ifdef ENABLE_CHECKING
8689 /* Verify that we didn't turn one trapping insn into many, and that
8690 we found and corrected all of the problems wrt fixups on the
8692 verify_flow_info ();