1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
548 /* reload_combine uses the information from
549 BASIC_BLOCK->global_live_at_start, which might still
550 contain registers that have not actually been allocated
551 since they have an equivalence. */
552 gcc_assert (reload_completed);
555 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
559 /* Replace all pseudos found in LOC with their corresponding
563 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
576 unsigned int regno = REGNO (x);
578 if (regno < FIRST_PSEUDO_REGISTER)
581 x = eliminate_regs (x, mem_mode, usage);
585 replace_pseudos_in (loc, mem_mode, usage);
589 if (reg_equiv_constant[regno])
590 *loc = reg_equiv_constant[regno];
591 else if (reg_equiv_mem[regno])
592 *loc = reg_equiv_mem[regno];
593 else if (reg_equiv_address[regno])
594 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
597 gcc_assert (!REG_P (regno_reg_rtx[regno])
598 || REGNO (regno_reg_rtx[regno]) != regno);
599 *loc = regno_reg_rtx[regno];
604 else if (code == MEM)
606 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
610 /* Process each of our operands recursively. */
611 fmt = GET_RTX_FORMAT (code);
612 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
614 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
615 else if (*fmt == 'E')
616 for (j = 0; j < XVECLEN (x, i); j++)
617 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
620 /* Determine if the current function has an exception receiver block
621 that reaches the exit block via non-exceptional edges */
624 has_nonexceptional_receiver (void)
628 basic_block *tos, *worklist, bb;
630 /* If we're not optimizing, then just err on the safe side. */
634 /* First determine which blocks can reach exit via normal paths. */
635 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
638 bb->flags &= ~BB_REACHABLE;
640 /* Place the exit block on our worklist. */
641 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
642 *tos++ = EXIT_BLOCK_PTR;
644 /* Iterate: find everything reachable from what we've already seen. */
645 while (tos != worklist)
649 FOR_EACH_EDGE (e, ei, bb->preds)
650 if (!(e->flags & EDGE_ABNORMAL))
652 basic_block src = e->src;
654 if (!(src->flags & BB_REACHABLE))
656 src->flags |= BB_REACHABLE;
663 /* Now see if there's a reachable block with an exceptional incoming
666 if (bb->flags & BB_REACHABLE)
667 FOR_EACH_EDGE (e, ei, bb->preds)
668 if (e->flags & EDGE_ABNORMAL)
671 /* No exceptional block reached exit unexceptionally. */
676 /* Global variables used by reload and its subroutines. */
678 /* Set during calculate_needs if an insn needs register elimination. */
679 static int something_needs_elimination;
680 /* Set during calculate_needs if an insn needs an operand changed. */
681 static int something_needs_operands_changed;
683 /* Nonzero means we couldn't get enough spill regs. */
686 /* Main entry point for the reload pass.
688 FIRST is the first insn of the function being compiled.
690 GLOBAL nonzero means we were called from global_alloc
691 and should attempt to reallocate any pseudoregs that we
692 displace from hard regs we will use for reloads.
693 If GLOBAL is zero, we do not have enough information to do that,
694 so any pseudo reg that is spilled must go to the stack.
696 Return value is nonzero if reload failed
697 and we must not do any more for this function. */
700 reload (rtx first, int global)
704 struct elim_table *ep;
707 /* Make sure even insns with volatile mem refs are recognizable. */
712 reload_firstobj = obstack_alloc (&reload_obstack, 0);
714 /* Make sure that the last insn in the chain
715 is not something that needs reloading. */
716 emit_note (NOTE_INSN_DELETED);
718 /* Enable find_equiv_reg to distinguish insns made by reload. */
719 reload_first_uid = get_max_uid ();
721 #ifdef SECONDARY_MEMORY_NEEDED
722 /* Initialize the secondary memory table. */
723 clear_secondary_mem ();
726 /* We don't have a stack slot for any spill reg yet. */
727 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
728 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
730 /* Initialize the save area information for caller-save, in case some
734 /* Compute which hard registers are now in use
735 as homes for pseudo registers.
736 This is done here rather than (eg) in global_alloc
737 because this point is reached even if not optimizing. */
738 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
741 /* A function that has a nonlocal label that can reach the exit
742 block via non-exceptional paths must save all call-saved
744 if (current_function_calls_unwind_init
745 || (current_function_has_nonlocal_label
746 && has_nonexceptional_receiver ()))
747 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
748 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
749 regs_ever_live[i] = 1;
751 /* Find all the pseudo registers that didn't get hard regs
752 but do have known equivalent constants or memory slots.
753 These include parameters (known equivalent to parameter slots)
754 and cse'd or loop-moved constant memory addresses.
756 Record constant equivalents in reg_equiv_constant
757 so they will be substituted by find_reloads.
758 Record memory equivalents in reg_mem_equiv so they can
759 be substituted eventually by altering the REG-rtx's. */
761 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
762 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
763 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
764 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
765 reg_equiv_address = XCNEWVEC (rtx, max_regno);
766 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
767 reg_old_renumber = XCNEWVEC (short, max_regno);
768 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
769 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
770 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
772 CLEAR_HARD_REG_SET (bad_spill_regs_global);
774 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
775 to. Also find all paradoxical subregs and find largest such for
778 num_eliminable_invariants = 0;
779 for (insn = first; insn; insn = NEXT_INSN (insn))
781 rtx set = single_set (insn);
783 /* We may introduce USEs that we want to remove at the end, so
784 we'll mark them with QImode. Make sure there are no
785 previously-marked insns left by say regmove. */
786 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
787 && GET_MODE (insn) != VOIDmode)
788 PUT_MODE (insn, VOIDmode);
791 scan_paradoxical_subregs (PATTERN (insn));
793 if (set != 0 && REG_P (SET_DEST (set)))
795 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
801 i = REGNO (SET_DEST (set));
804 if (i <= LAST_VIRTUAL_REGISTER)
807 if (! function_invariant_p (x)
809 /* A function invariant is often CONSTANT_P but may
810 include a register. We promise to only pass
811 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
813 && LEGITIMATE_PIC_OPERAND_P (x)))
815 /* It can happen that a REG_EQUIV note contains a MEM
816 that is not a legitimate memory operand. As later
817 stages of reload assume that all addresses found
818 in the reg_equiv_* arrays were originally legitimate,
819 we ignore such REG_EQUIV notes. */
820 if (memory_operand (x, VOIDmode))
822 /* Always unshare the equivalence, so we can
823 substitute into this insn without touching the
825 reg_equiv_memory_loc[i] = copy_rtx (x);
827 else if (function_invariant_p (x))
829 if (GET_CODE (x) == PLUS)
831 /* This is PLUS of frame pointer and a constant,
832 and might be shared. Unshare it. */
833 reg_equiv_invariant[i] = copy_rtx (x);
834 num_eliminable_invariants++;
836 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
838 reg_equiv_invariant[i] = x;
839 num_eliminable_invariants++;
841 else if (LEGITIMATE_CONSTANT_P (x))
842 reg_equiv_constant[i] = x;
845 reg_equiv_memory_loc[i]
846 = force_const_mem (GET_MODE (SET_DEST (set)), x);
847 if (! reg_equiv_memory_loc[i])
848 reg_equiv_init[i] = NULL_RTX;
853 reg_equiv_init[i] = NULL_RTX;
858 reg_equiv_init[i] = NULL_RTX;
863 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
864 if (reg_equiv_init[i])
866 fprintf (dump_file, "init_insns for %u: ", i);
867 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
868 fprintf (dump_file, "\n");
873 first_label_num = get_first_label_num ();
874 num_labels = max_label_num () - first_label_num;
876 /* Allocate the tables used to store offset information at labels. */
877 /* We used to use alloca here, but the size of what it would try to
878 allocate would occasionally cause it to exceed the stack limit and
879 cause a core dump. */
880 offsets_known_at = XNEWVEC (char, num_labels);
881 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
883 /* Alter each pseudo-reg rtx to contain its hard reg number.
884 Assign stack slots to the pseudos that lack hard regs or equivalents.
885 Do not touch virtual registers. */
887 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
890 /* If we have some registers we think can be eliminated, scan all insns to
891 see if there is an insn that sets one of these registers to something
892 other than itself plus a constant. If so, the register cannot be
893 eliminated. Doing this scan here eliminates an extra pass through the
894 main reload loop in the most common case where register elimination
896 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
898 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
900 maybe_fix_stack_asms ();
902 insns_need_reload = 0;
903 something_needs_elimination = 0;
905 /* Initialize to -1, which means take the first spill register. */
908 /* Spill any hard regs that we know we can't eliminate. */
909 CLEAR_HARD_REG_SET (used_spill_regs);
910 /* There can be multiple ways to eliminate a register;
911 they should be listed adjacently.
912 Elimination for any register fails only if all possible ways fail. */
913 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
916 int can_eliminate = 0;
919 can_eliminate |= ep->can_eliminate;
922 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
924 spill_hard_reg (from, 1);
927 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
928 if (frame_pointer_needed)
929 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
931 finish_spills (global);
933 /* From now on, we may need to generate moves differently. We may also
934 allow modifications of insns which cause them to not be recognized.
935 Any such modifications will be cleaned up during reload itself. */
936 reload_in_progress = 1;
938 /* This loop scans the entire function each go-round
939 and repeats until one repetition spills no additional hard regs. */
942 int something_changed;
944 HOST_WIDE_INT starting_frame_size;
946 starting_frame_size = get_frame_size ();
948 set_initial_elim_offsets ();
949 set_initial_label_offsets ();
951 /* For each pseudo register that has an equivalent location defined,
952 try to eliminate any eliminable registers (such as the frame pointer)
953 assuming initial offsets for the replacement register, which
956 If the resulting location is directly addressable, substitute
957 the MEM we just got directly for the old REG.
959 If it is not addressable but is a constant or the sum of a hard reg
960 and constant, it is probably not addressable because the constant is
961 out of range, in that case record the address; we will generate
962 hairy code to compute the address in a register each time it is
963 needed. Similarly if it is a hard register, but one that is not
964 valid as an address register.
966 If the location is not addressable, but does not have one of the
967 above forms, assign a stack slot. We have to do this to avoid the
968 potential of producing lots of reloads if, e.g., a location involves
969 a pseudo that didn't get a hard register and has an equivalent memory
970 location that also involves a pseudo that didn't get a hard register.
972 Perhaps at some point we will improve reload_when_needed handling
973 so this problem goes away. But that's very hairy. */
975 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
976 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
978 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
980 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
982 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
983 else if (CONSTANT_P (XEXP (x, 0))
984 || (REG_P (XEXP (x, 0))
985 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
986 || (GET_CODE (XEXP (x, 0)) == PLUS
987 && REG_P (XEXP (XEXP (x, 0), 0))
988 && (REGNO (XEXP (XEXP (x, 0), 0))
989 < FIRST_PSEUDO_REGISTER)
990 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
991 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
994 /* Make a new stack slot. Then indicate that something
995 changed so we go back and recompute offsets for
996 eliminable registers because the allocation of memory
997 below might change some offset. reg_equiv_{mem,address}
998 will be set up for this pseudo on the next pass around
1000 reg_equiv_memory_loc[i] = 0;
1001 reg_equiv_init[i] = 0;
1006 if (caller_save_needed)
1007 setup_save_areas ();
1009 /* If we allocated another stack slot, redo elimination bookkeeping. */
1010 if (starting_frame_size != get_frame_size ())
1012 if (starting_frame_size && cfun->stack_alignment_needed)
1014 /* If we have a stack frame, we must align it now. The
1015 stack size may be a part of the offset computation for
1016 register elimination. So if this changes the stack size,
1017 then repeat the elimination bookkeeping. We don't
1018 realign when there is no stack, as that will cause a
1019 stack frame when none is needed should
1020 STARTING_FRAME_OFFSET not be already aligned to
1022 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
1023 if (starting_frame_size != get_frame_size ())
1027 if (caller_save_needed)
1029 save_call_clobbered_regs ();
1030 /* That might have allocated new insn_chain structures. */
1031 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1034 calculate_needs_all_insns (global);
1036 CLEAR_REG_SET (&spilled_pseudos);
1039 something_changed = 0;
1041 /* If we allocated any new memory locations, make another pass
1042 since it might have changed elimination offsets. */
1043 if (starting_frame_size != get_frame_size ())
1044 something_changed = 1;
1046 /* Even if the frame size remained the same, we might still have
1047 changed elimination offsets, e.g. if find_reloads called
1048 force_const_mem requiring the back end to allocate a constant
1049 pool base register that needs to be saved on the stack. */
1050 else if (!verify_initial_elim_offsets ())
1051 something_changed = 1;
1054 HARD_REG_SET to_spill;
1055 CLEAR_HARD_REG_SET (to_spill);
1056 update_eliminables (&to_spill);
1057 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1059 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1060 if (TEST_HARD_REG_BIT (to_spill, i))
1062 spill_hard_reg (i, 1);
1065 /* Regardless of the state of spills, if we previously had
1066 a register that we thought we could eliminate, but now can
1067 not eliminate, we must run another pass.
1069 Consider pseudos which have an entry in reg_equiv_* which
1070 reference an eliminable register. We must make another pass
1071 to update reg_equiv_* so that we do not substitute in the
1072 old value from when we thought the elimination could be
1074 something_changed = 1;
1078 select_reload_regs ();
1082 if (insns_need_reload != 0 || did_spill)
1083 something_changed |= finish_spills (global);
1085 if (! something_changed)
1088 if (caller_save_needed)
1089 delete_caller_save_insns ();
1091 obstack_free (&reload_obstack, reload_firstobj);
1094 /* If global-alloc was run, notify it of any register eliminations we have
1097 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1098 if (ep->can_eliminate)
1099 mark_elimination (ep->from, ep->to);
1101 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1102 If that insn didn't set the register (i.e., it copied the register to
1103 memory), just delete that insn instead of the equivalencing insn plus
1104 anything now dead. If we call delete_dead_insn on that insn, we may
1105 delete the insn that actually sets the register if the register dies
1106 there and that is incorrect. */
1108 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1110 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1113 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1115 rtx equiv_insn = XEXP (list, 0);
1117 /* If we already deleted the insn or if it may trap, we can't
1118 delete it. The latter case shouldn't happen, but can
1119 if an insn has a variable address, gets a REG_EH_REGION
1120 note added to it, and then gets converted into a load
1121 from a constant address. */
1122 if (NOTE_P (equiv_insn)
1123 || can_throw_internal (equiv_insn))
1125 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1126 delete_dead_insn (equiv_insn);
1128 SET_INSN_DELETED (equiv_insn);
1133 /* Use the reload registers where necessary
1134 by generating move instructions to move the must-be-register
1135 values into or out of the reload registers. */
1137 if (insns_need_reload != 0 || something_needs_elimination
1138 || something_needs_operands_changed)
1140 HOST_WIDE_INT old_frame_size = get_frame_size ();
1142 reload_as_needed (global);
1144 gcc_assert (old_frame_size == get_frame_size ());
1146 gcc_assert (verify_initial_elim_offsets ());
1149 /* If we were able to eliminate the frame pointer, show that it is no
1150 longer live at the start of any basic block. If it ls live by
1151 virtue of being in a pseudo, that pseudo will be marked live
1152 and hence the frame pointer will be known to be live via that
1155 if (! frame_pointer_needed)
1157 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1158 HARD_FRAME_POINTER_REGNUM);
1160 /* Come here (with failure set nonzero) if we can't get enough spill
1164 CLEAR_REG_SET (&spilled_pseudos);
1165 reload_in_progress = 0;
1167 /* Now eliminate all pseudo regs by modifying them into
1168 their equivalent memory references.
1169 The REG-rtx's for the pseudos are modified in place,
1170 so all insns that used to refer to them now refer to memory.
1172 For a reg that has a reg_equiv_address, all those insns
1173 were changed by reloading so that no insns refer to it any longer;
1174 but the DECL_RTL of a variable decl may refer to it,
1175 and if so this causes the debugging info to mention the variable. */
1177 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1181 if (reg_equiv_mem[i])
1182 addr = XEXP (reg_equiv_mem[i], 0);
1184 if (reg_equiv_address[i])
1185 addr = reg_equiv_address[i];
1189 if (reg_renumber[i] < 0)
1191 rtx reg = regno_reg_rtx[i];
1193 REG_USERVAR_P (reg) = 0;
1194 PUT_CODE (reg, MEM);
1195 XEXP (reg, 0) = addr;
1196 if (reg_equiv_memory_loc[i])
1197 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1200 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1201 MEM_ATTRS (reg) = 0;
1203 MEM_NOTRAP_P (reg) = 1;
1205 else if (reg_equiv_mem[i])
1206 XEXP (reg_equiv_mem[i], 0) = addr;
1210 /* We must set reload_completed now since the cleanup_subreg_operands call
1211 below will re-recognize each insn and reload may have generated insns
1212 which are only valid during and after reload. */
1213 reload_completed = 1;
1215 /* Make a pass over all the insns and delete all USEs which we inserted
1216 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1217 notes. Delete all CLOBBER insns, except those that refer to the return
1218 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1219 from misarranging variable-array code, and simplify (subreg (reg))
1220 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1221 are no longer useful or accurate. Strip and regenerate REG_INC notes
1222 that may have been moved around. */
1224 for (insn = first; insn; insn = NEXT_INSN (insn))
1230 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1231 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1233 if ((GET_CODE (PATTERN (insn)) == USE
1234 /* We mark with QImode USEs introduced by reload itself. */
1235 && (GET_MODE (insn) == QImode
1236 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1237 || (GET_CODE (PATTERN (insn)) == CLOBBER
1238 && (!MEM_P (XEXP (PATTERN (insn), 0))
1239 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1240 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1241 && XEXP (XEXP (PATTERN (insn), 0), 0)
1242 != stack_pointer_rtx))
1243 && (!REG_P (XEXP (PATTERN (insn), 0))
1244 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1250 /* Some CLOBBERs may survive until here and still reference unassigned
1251 pseudos with const equivalent, which may in turn cause ICE in later
1252 passes if the reference remains in place. */
1253 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1254 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1255 VOIDmode, PATTERN (insn));
1257 /* Discard obvious no-ops, even without -O. This optimization
1258 is fast and doesn't interfere with debugging. */
1259 if (NONJUMP_INSN_P (insn)
1260 && GET_CODE (PATTERN (insn)) == SET
1261 && REG_P (SET_SRC (PATTERN (insn)))
1262 && REG_P (SET_DEST (PATTERN (insn)))
1263 && (REGNO (SET_SRC (PATTERN (insn)))
1264 == REGNO (SET_DEST (PATTERN (insn)))))
1270 pnote = ®_NOTES (insn);
1273 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1274 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1275 || REG_NOTE_KIND (*pnote) == REG_INC
1276 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1277 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1278 *pnote = XEXP (*pnote, 1);
1280 pnote = &XEXP (*pnote, 1);
1284 add_auto_inc_notes (insn, PATTERN (insn));
1287 /* Simplify (subreg (reg)) if it appears as an operand. */
1288 cleanup_subreg_operands (insn);
1290 /* Clean up invalid ASMs so that they don't confuse later passes.
1292 if (asm_noperands (PATTERN (insn)) >= 0)
1294 extract_insn (insn);
1295 if (!constrain_operands (1))
1297 error_for_asm (insn,
1298 "%<asm%> operand has impossible constraints");
1305 /* If we are doing stack checking, give a warning if this function's
1306 frame size is larger than we expect. */
1307 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1309 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1310 static int verbose_warned = 0;
1312 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1313 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1314 size += UNITS_PER_WORD;
1316 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1318 warning (0, "frame size too large for reliable stack checking");
1319 if (! verbose_warned)
1321 warning (0, "try reducing the number of local variables");
1327 /* Indicate that we no longer have known memory locations or constants. */
1328 if (reg_equiv_constant)
1329 free (reg_equiv_constant);
1330 if (reg_equiv_invariant)
1331 free (reg_equiv_invariant);
1332 reg_equiv_constant = 0;
1333 reg_equiv_invariant = 0;
1334 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1335 reg_equiv_memory_loc = 0;
1337 if (offsets_known_at)
1338 free (offsets_known_at);
1342 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1343 if (reg_equiv_alt_mem_list[i])
1344 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1345 free (reg_equiv_alt_mem_list);
1347 free (reg_equiv_mem);
1349 free (reg_equiv_address);
1350 free (reg_max_ref_width);
1351 free (reg_old_renumber);
1352 free (pseudo_previous_regs);
1353 free (pseudo_forbidden_regs);
1355 CLEAR_HARD_REG_SET (used_spill_regs);
1356 for (i = 0; i < n_spills; i++)
1357 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1359 /* Free all the insn_chain structures at once. */
1360 obstack_free (&reload_obstack, reload_startobj);
1361 unused_insn_chains = 0;
1362 fixup_abnormal_edges ();
1364 /* Replacing pseudos with their memory equivalents might have
1365 created shared rtx. Subsequent passes would get confused
1366 by this, so unshare everything here. */
1367 unshare_all_rtl_again (first);
1369 #ifdef STACK_BOUNDARY
1370 /* init_emit has set the alignment of the hard frame pointer
1371 to STACK_BOUNDARY. It is very likely no longer valid if
1372 the hard frame pointer was used for register allocation. */
1373 if (!frame_pointer_needed)
1374 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1380 /* Yet another special case. Unfortunately, reg-stack forces people to
1381 write incorrect clobbers in asm statements. These clobbers must not
1382 cause the register to appear in bad_spill_regs, otherwise we'll call
1383 fatal_insn later. We clear the corresponding regnos in the live
1384 register sets to avoid this.
1385 The whole thing is rather sick, I'm afraid. */
1388 maybe_fix_stack_asms (void)
1391 const char *constraints[MAX_RECOG_OPERANDS];
1392 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1393 struct insn_chain *chain;
1395 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1398 HARD_REG_SET clobbered, allowed;
1401 if (! INSN_P (chain->insn)
1402 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1404 pat = PATTERN (chain->insn);
1405 if (GET_CODE (pat) != PARALLEL)
1408 CLEAR_HARD_REG_SET (clobbered);
1409 CLEAR_HARD_REG_SET (allowed);
1411 /* First, make a mask of all stack regs that are clobbered. */
1412 for (i = 0; i < XVECLEN (pat, 0); i++)
1414 rtx t = XVECEXP (pat, 0, i);
1415 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1416 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1419 /* Get the operand values and constraints out of the insn. */
1420 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1421 constraints, operand_mode, NULL);
1423 /* For every operand, see what registers are allowed. */
1424 for (i = 0; i < noperands; i++)
1426 const char *p = constraints[i];
1427 /* For every alternative, we compute the class of registers allowed
1428 for reloading in CLS, and merge its contents into the reg set
1430 int cls = (int) NO_REGS;
1436 if (c == '\0' || c == ',' || c == '#')
1438 /* End of one alternative - mark the regs in the current
1439 class, and reset the class. */
1440 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1446 } while (c != '\0' && c != ',');
1454 case '=': case '+': case '*': case '%': case '?': case '!':
1455 case '0': case '1': case '2': case '3': case '4': case 'm':
1456 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1457 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1458 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1463 cls = (int) reg_class_subunion[cls]
1464 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1469 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1473 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1474 cls = (int) reg_class_subunion[cls]
1475 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1477 cls = (int) reg_class_subunion[cls]
1478 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1480 p += CONSTRAINT_LEN (c, p);
1483 /* Those of the registers which are clobbered, but allowed by the
1484 constraints, must be usable as reload registers. So clear them
1485 out of the life information. */
1486 AND_HARD_REG_SET (allowed, clobbered);
1487 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1488 if (TEST_HARD_REG_BIT (allowed, i))
1490 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1491 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1498 /* Copy the global variables n_reloads and rld into the corresponding elts
1501 copy_reloads (struct insn_chain *chain)
1503 chain->n_reloads = n_reloads;
1504 chain->rld = obstack_alloc (&reload_obstack,
1505 n_reloads * sizeof (struct reload));
1506 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1507 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1510 /* Walk the chain of insns, and determine for each whether it needs reloads
1511 and/or eliminations. Build the corresponding insns_need_reload list, and
1512 set something_needs_elimination as appropriate. */
1514 calculate_needs_all_insns (int global)
1516 struct insn_chain **pprev_reload = &insns_need_reload;
1517 struct insn_chain *chain, *next = 0;
1519 something_needs_elimination = 0;
1521 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1522 for (chain = reload_insn_chain; chain != 0; chain = next)
1524 rtx insn = chain->insn;
1528 /* Clear out the shortcuts. */
1529 chain->n_reloads = 0;
1530 chain->need_elim = 0;
1531 chain->need_reload = 0;
1532 chain->need_operand_change = 0;
1534 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1535 include REG_LABEL), we need to see what effects this has on the
1536 known offsets at labels. */
1538 if (LABEL_P (insn) || JUMP_P (insn)
1539 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1540 set_label_offsets (insn, insn, 0);
1544 rtx old_body = PATTERN (insn);
1545 int old_code = INSN_CODE (insn);
1546 rtx old_notes = REG_NOTES (insn);
1547 int did_elimination = 0;
1548 int operands_changed = 0;
1549 rtx set = single_set (insn);
1551 /* Skip insns that only set an equivalence. */
1552 if (set && REG_P (SET_DEST (set))
1553 && reg_renumber[REGNO (SET_DEST (set))] < 0
1554 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1555 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1556 && reg_equiv_init[REGNO (SET_DEST (set))])
1559 /* If needed, eliminate any eliminable registers. */
1560 if (num_eliminable || num_eliminable_invariants)
1561 did_elimination = eliminate_regs_in_insn (insn, 0);
1563 /* Analyze the instruction. */
1564 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1565 global, spill_reg_order);
1567 /* If a no-op set needs more than one reload, this is likely
1568 to be something that needs input address reloads. We
1569 can't get rid of this cleanly later, and it is of no use
1570 anyway, so discard it now.
1571 We only do this when expensive_optimizations is enabled,
1572 since this complements reload inheritance / output
1573 reload deletion, and it can make debugging harder. */
1574 if (flag_expensive_optimizations && n_reloads > 1)
1576 rtx set = single_set (insn);
1578 && SET_SRC (set) == SET_DEST (set)
1579 && REG_P (SET_SRC (set))
1580 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1583 /* Delete it from the reload chain. */
1585 chain->prev->next = next;
1587 reload_insn_chain = next;
1589 next->prev = chain->prev;
1590 chain->next = unused_insn_chains;
1591 unused_insn_chains = chain;
1596 update_eliminable_offsets ();
1598 /* Remember for later shortcuts which insns had any reloads or
1599 register eliminations. */
1600 chain->need_elim = did_elimination;
1601 chain->need_reload = n_reloads > 0;
1602 chain->need_operand_change = operands_changed;
1604 /* Discard any register replacements done. */
1605 if (did_elimination)
1607 obstack_free (&reload_obstack, reload_insn_firstobj);
1608 PATTERN (insn) = old_body;
1609 INSN_CODE (insn) = old_code;
1610 REG_NOTES (insn) = old_notes;
1611 something_needs_elimination = 1;
1614 something_needs_operands_changed |= operands_changed;
1618 copy_reloads (chain);
1619 *pprev_reload = chain;
1620 pprev_reload = &chain->next_need_reload;
1627 /* Comparison function for qsort to decide which of two reloads
1628 should be handled first. *P1 and *P2 are the reload numbers. */
1631 reload_reg_class_lower (const void *r1p, const void *r2p)
1633 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1636 /* Consider required reloads before optional ones. */
1637 t = rld[r1].optional - rld[r2].optional;
1641 /* Count all solitary classes before non-solitary ones. */
1642 t = ((reg_class_size[(int) rld[r2].class] == 1)
1643 - (reg_class_size[(int) rld[r1].class] == 1));
1647 /* Aside from solitaires, consider all multi-reg groups first. */
1648 t = rld[r2].nregs - rld[r1].nregs;
1652 /* Consider reloads in order of increasing reg-class number. */
1653 t = (int) rld[r1].class - (int) rld[r2].class;
1657 /* If reloads are equally urgent, sort by reload number,
1658 so that the results of qsort leave nothing to chance. */
1662 /* The cost of spilling each hard reg. */
1663 static int spill_cost[FIRST_PSEUDO_REGISTER];
1665 /* When spilling multiple hard registers, we use SPILL_COST for the first
1666 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1667 only the first hard reg for a multi-reg pseudo. */
1668 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1670 /* Update the spill cost arrays, considering that pseudo REG is live. */
1673 count_pseudo (int reg)
1675 int freq = REG_FREQ (reg);
1676 int r = reg_renumber[reg];
1679 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1680 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1683 SET_REGNO_REG_SET (&pseudos_counted, reg);
1685 gcc_assert (r >= 0);
1687 spill_add_cost[r] += freq;
1689 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1691 spill_cost[r + nregs] += freq;
1694 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1695 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1698 order_regs_for_reload (struct insn_chain *chain)
1701 HARD_REG_SET used_by_pseudos;
1702 HARD_REG_SET used_by_pseudos2;
1703 reg_set_iterator rsi;
1705 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1707 memset (spill_cost, 0, sizeof spill_cost);
1708 memset (spill_add_cost, 0, sizeof spill_add_cost);
1710 /* Count number of uses of each hard reg by pseudo regs allocated to it
1711 and then order them by decreasing use. First exclude hard registers
1712 that are live in or across this insn. */
1714 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1715 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1716 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1717 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1719 /* Now find out which pseudos are allocated to it, and update
1721 CLEAR_REG_SET (&pseudos_counted);
1723 EXECUTE_IF_SET_IN_REG_SET
1724 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1728 EXECUTE_IF_SET_IN_REG_SET
1729 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1733 CLEAR_REG_SET (&pseudos_counted);
1736 /* Vector of reload-numbers showing the order in which the reloads should
1738 static short reload_order[MAX_RELOADS];
1740 /* This is used to keep track of the spill regs used in one insn. */
1741 static HARD_REG_SET used_spill_regs_local;
1743 /* We decided to spill hard register SPILLED, which has a size of
1744 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1745 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1746 update SPILL_COST/SPILL_ADD_COST. */
1749 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1751 int r = reg_renumber[reg];
1752 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1754 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1755 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1758 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1760 spill_add_cost[r] -= REG_FREQ (reg);
1762 spill_cost[r + nregs] -= REG_FREQ (reg);
1765 /* Find reload register to use for reload number ORDER. */
1768 find_reg (struct insn_chain *chain, int order)
1770 int rnum = reload_order[order];
1771 struct reload *rl = rld + rnum;
1772 int best_cost = INT_MAX;
1776 HARD_REG_SET not_usable;
1777 HARD_REG_SET used_by_other_reload;
1778 reg_set_iterator rsi;
1780 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1781 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1782 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1784 CLEAR_HARD_REG_SET (used_by_other_reload);
1785 for (k = 0; k < order; k++)
1787 int other = reload_order[k];
1789 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1790 for (j = 0; j < rld[other].nregs; j++)
1791 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1794 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1796 unsigned int regno = i;
1798 if (! TEST_HARD_REG_BIT (not_usable, regno)
1799 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1800 && HARD_REGNO_MODE_OK (regno, rl->mode))
1802 int this_cost = spill_cost[regno];
1804 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1806 for (j = 1; j < this_nregs; j++)
1808 this_cost += spill_add_cost[regno + j];
1809 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1810 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1815 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1817 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1819 if (this_cost < best_cost
1820 /* Among registers with equal cost, prefer caller-saved ones, or
1821 use REG_ALLOC_ORDER if it is defined. */
1822 || (this_cost == best_cost
1823 #ifdef REG_ALLOC_ORDER
1824 && (inv_reg_alloc_order[regno]
1825 < inv_reg_alloc_order[best_reg])
1827 && call_used_regs[regno]
1828 && ! call_used_regs[best_reg]
1833 best_cost = this_cost;
1841 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1843 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1844 rl->regno = best_reg;
1846 EXECUTE_IF_SET_IN_REG_SET
1847 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1849 count_spilled_pseudo (best_reg, rl->nregs, j);
1852 EXECUTE_IF_SET_IN_REG_SET
1853 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1855 count_spilled_pseudo (best_reg, rl->nregs, j);
1858 for (i = 0; i < rl->nregs; i++)
1860 gcc_assert (spill_cost[best_reg + i] == 0);
1861 gcc_assert (spill_add_cost[best_reg + i] == 0);
1862 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1867 /* Find more reload regs to satisfy the remaining need of an insn, which
1869 Do it by ascending class number, since otherwise a reg
1870 might be spilled for a big class and might fail to count
1871 for a smaller class even though it belongs to that class. */
1874 find_reload_regs (struct insn_chain *chain)
1878 /* In order to be certain of getting the registers we need,
1879 we must sort the reloads into order of increasing register class.
1880 Then our grabbing of reload registers will parallel the process
1881 that provided the reload registers. */
1882 for (i = 0; i < chain->n_reloads; i++)
1884 /* Show whether this reload already has a hard reg. */
1885 if (chain->rld[i].reg_rtx)
1887 int regno = REGNO (chain->rld[i].reg_rtx);
1888 chain->rld[i].regno = regno;
1890 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1893 chain->rld[i].regno = -1;
1894 reload_order[i] = i;
1897 n_reloads = chain->n_reloads;
1898 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1900 CLEAR_HARD_REG_SET (used_spill_regs_local);
1903 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1905 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1907 /* Compute the order of preference for hard registers to spill. */
1909 order_regs_for_reload (chain);
1911 for (i = 0; i < n_reloads; i++)
1913 int r = reload_order[i];
1915 /* Ignore reloads that got marked inoperative. */
1916 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1917 && ! rld[r].optional
1918 && rld[r].regno == -1)
1919 if (! find_reg (chain, i))
1922 fprintf (dump_file, "reload failure for reload %d\n", r);
1923 spill_failure (chain->insn, rld[r].class);
1929 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1930 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1932 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1936 select_reload_regs (void)
1938 struct insn_chain *chain;
1940 /* Try to satisfy the needs for each insn. */
1941 for (chain = insns_need_reload; chain != 0;
1942 chain = chain->next_need_reload)
1943 find_reload_regs (chain);
1946 /* Delete all insns that were inserted by emit_caller_save_insns during
1949 delete_caller_save_insns (void)
1951 struct insn_chain *c = reload_insn_chain;
1955 while (c != 0 && c->is_caller_save_insn)
1957 struct insn_chain *next = c->next;
1960 if (c == reload_insn_chain)
1961 reload_insn_chain = next;
1965 next->prev = c->prev;
1967 c->prev->next = next;
1968 c->next = unused_insn_chains;
1969 unused_insn_chains = c;
1977 /* Handle the failure to find a register to spill.
1978 INSN should be one of the insns which needed this particular spill reg. */
1981 spill_failure (rtx insn, enum reg_class class)
1983 if (asm_noperands (PATTERN (insn)) >= 0)
1984 error_for_asm (insn, "can't find a register in class %qs while "
1985 "reloading %<asm%>",
1986 reg_class_names[class]);
1989 error ("unable to find a register to spill in class %qs",
1990 reg_class_names[class]);
1994 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1995 debug_reload_to_stream (dump_file);
1997 fatal_insn ("this is the insn:", insn);
2001 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2002 data that is dead in INSN. */
2005 delete_dead_insn (rtx insn)
2007 rtx prev = prev_real_insn (insn);
2010 /* If the previous insn sets a register that dies in our insn, delete it
2012 if (prev && GET_CODE (PATTERN (prev)) == SET
2013 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2014 && reg_mentioned_p (prev_dest, PATTERN (insn))
2015 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2016 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2017 delete_dead_insn (prev);
2019 SET_INSN_DELETED (insn);
2022 /* Modify the home of pseudo-reg I.
2023 The new home is present in reg_renumber[I].
2025 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2026 or it may be -1, meaning there is none or it is not relevant.
2027 This is used so that all pseudos spilled from a given hard reg
2028 can share one stack slot. */
2031 alter_reg (int i, int from_reg)
2033 /* When outputting an inline function, this can happen
2034 for a reg that isn't actually used. */
2035 if (regno_reg_rtx[i] == 0)
2038 /* If the reg got changed to a MEM at rtl-generation time,
2040 if (!REG_P (regno_reg_rtx[i]))
2043 /* Modify the reg-rtx to contain the new hard reg
2044 number or else to contain its pseudo reg number. */
2045 REGNO (regno_reg_rtx[i])
2046 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2048 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2049 allocate a stack slot for it. */
2051 if (reg_renumber[i] < 0
2052 && REG_N_REFS (i) > 0
2053 && reg_equiv_constant[i] == 0
2054 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2055 && reg_equiv_memory_loc[i] == 0)
2058 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2059 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2060 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2061 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2062 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2065 /* Each pseudo reg has an inherent size which comes from its own mode,
2066 and a total size which provides room for paradoxical subregs
2067 which refer to the pseudo reg in wider modes.
2069 We can use a slot already allocated if it provides both
2070 enough inherent space and enough total space.
2071 Otherwise, we allocate a new slot, making sure that it has no less
2072 inherent space, and no less total space, then the previous slot. */
2075 /* No known place to spill from => no slot to reuse. */
2076 x = assign_stack_local (mode, total_size,
2077 min_align > inherent_align
2078 || total_size > inherent_size ? -1 : 0);
2079 if (BYTES_BIG_ENDIAN)
2080 /* Cancel the big-endian correction done in assign_stack_local.
2081 Get the address of the beginning of the slot.
2082 This is so we can do a big-endian correction unconditionally
2084 adjust = inherent_size - total_size;
2086 /* Nothing can alias this slot except this pseudo. */
2087 set_mem_alias_set (x, new_alias_set ());
2090 /* Reuse a stack slot if possible. */
2091 else if (spill_stack_slot[from_reg] != 0
2092 && spill_stack_slot_width[from_reg] >= total_size
2093 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2095 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2096 x = spill_stack_slot[from_reg];
2098 /* Allocate a bigger slot. */
2101 /* Compute maximum size needed, both for inherent size
2102 and for total size. */
2105 if (spill_stack_slot[from_reg])
2107 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2109 mode = GET_MODE (spill_stack_slot[from_reg]);
2110 if (spill_stack_slot_width[from_reg] > total_size)
2111 total_size = spill_stack_slot_width[from_reg];
2112 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2113 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2116 /* Make a slot with that size. */
2117 x = assign_stack_local (mode, total_size,
2118 min_align > inherent_align
2119 || total_size > inherent_size ? -1 : 0);
2122 /* All pseudos mapped to this slot can alias each other. */
2123 if (spill_stack_slot[from_reg])
2124 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2126 set_mem_alias_set (x, new_alias_set ());
2128 if (BYTES_BIG_ENDIAN)
2130 /* Cancel the big-endian correction done in assign_stack_local.
2131 Get the address of the beginning of the slot.
2132 This is so we can do a big-endian correction unconditionally
2134 adjust = GET_MODE_SIZE (mode) - total_size;
2137 = adjust_address_nv (x, mode_for_size (total_size
2143 spill_stack_slot[from_reg] = stack_slot;
2144 spill_stack_slot_width[from_reg] = total_size;
2147 /* On a big endian machine, the "address" of the slot
2148 is the address of the low part that fits its inherent mode. */
2149 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2150 adjust += (total_size - inherent_size);
2152 /* If we have any adjustment to make, or if the stack slot is the
2153 wrong mode, make a new stack slot. */
2154 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2156 /* If we have a decl for the original register, set it for the
2157 memory. If this is a shared MEM, make a copy. */
2158 if (REG_EXPR (regno_reg_rtx[i])
2159 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2161 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2163 /* We can do this only for the DECLs home pseudo, not for
2164 any copies of it, since otherwise when the stack slot
2165 is reused, nonoverlapping_memrefs_p might think they
2167 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2169 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2172 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2176 /* Save the stack slot for later. */
2177 reg_equiv_memory_loc[i] = x;
2181 /* Mark the slots in regs_ever_live for the hard regs
2182 used by pseudo-reg number REGNO. */
2185 mark_home_live (int regno)
2189 i = reg_renumber[regno];
2192 lim = end_hard_regno (PSEUDO_REGNO_MODE (regno), i);
2194 regs_ever_live[i++] = 1;
2197 /* This function handles the tracking of elimination offsets around branches.
2199 X is a piece of RTL being scanned.
2201 INSN is the insn that it came from, if any.
2203 INITIAL_P is nonzero if we are to set the offset to be the initial
2204 offset and zero if we are setting the offset of the label to be the
2208 set_label_offsets (rtx x, rtx insn, int initial_p)
2210 enum rtx_code code = GET_CODE (x);
2213 struct elim_table *p;
2218 if (LABEL_REF_NONLOCAL_P (x))
2223 /* ... fall through ... */
2226 /* If we know nothing about this label, set the desired offsets. Note
2227 that this sets the offset at a label to be the offset before a label
2228 if we don't know anything about the label. This is not correct for
2229 the label after a BARRIER, but is the best guess we can make. If
2230 we guessed wrong, we will suppress an elimination that might have
2231 been possible had we been able to guess correctly. */
2233 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2235 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2236 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2237 = (initial_p ? reg_eliminate[i].initial_offset
2238 : reg_eliminate[i].offset);
2239 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2242 /* Otherwise, if this is the definition of a label and it is
2243 preceded by a BARRIER, set our offsets to the known offset of
2247 && (tem = prev_nonnote_insn (insn)) != 0
2249 set_offsets_for_label (insn);
2251 /* If neither of the above cases is true, compare each offset
2252 with those previously recorded and suppress any eliminations
2253 where the offsets disagree. */
2255 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2256 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2257 != (initial_p ? reg_eliminate[i].initial_offset
2258 : reg_eliminate[i].offset))
2259 reg_eliminate[i].can_eliminate = 0;
2264 set_label_offsets (PATTERN (insn), insn, initial_p);
2266 /* ... fall through ... */
2270 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2271 and hence must have all eliminations at their initial offsets. */
2272 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2273 if (REG_NOTE_KIND (tem) == REG_LABEL)
2274 set_label_offsets (XEXP (tem, 0), insn, 1);
2280 /* Each of the labels in the parallel or address vector must be
2281 at their initial offsets. We want the first field for PARALLEL
2282 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2284 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2285 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2290 /* We only care about setting PC. If the source is not RETURN,
2291 IF_THEN_ELSE, or a label, disable any eliminations not at
2292 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2293 isn't one of those possibilities. For branches to a label,
2294 call ourselves recursively.
2296 Note that this can disable elimination unnecessarily when we have
2297 a non-local goto since it will look like a non-constant jump to
2298 someplace in the current function. This isn't a significant
2299 problem since such jumps will normally be when all elimination
2300 pairs are back to their initial offsets. */
2302 if (SET_DEST (x) != pc_rtx)
2305 switch (GET_CODE (SET_SRC (x)))
2312 set_label_offsets (SET_SRC (x), insn, initial_p);
2316 tem = XEXP (SET_SRC (x), 1);
2317 if (GET_CODE (tem) == LABEL_REF)
2318 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2319 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2322 tem = XEXP (SET_SRC (x), 2);
2323 if (GET_CODE (tem) == LABEL_REF)
2324 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2325 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2333 /* If we reach here, all eliminations must be at their initial
2334 offset because we are doing a jump to a variable address. */
2335 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2336 if (p->offset != p->initial_offset)
2337 p->can_eliminate = 0;
2345 /* Scan X and replace any eliminable registers (such as fp) with a
2346 replacement (such as sp), plus an offset.
2348 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2349 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2350 MEM, we are allowed to replace a sum of a register and the constant zero
2351 with the register, which we cannot do outside a MEM. In addition, we need
2352 to record the fact that a register is referenced outside a MEM.
2354 If INSN is an insn, it is the insn containing X. If we replace a REG
2355 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2356 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2357 the REG is being modified.
2359 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2360 That's used when we eliminate in expressions stored in notes.
2361 This means, do not set ref_outside_mem even if the reference
2364 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2365 replacements done assuming all offsets are at their initial values. If
2366 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2367 encounter, return the actual location so that find_reloads will do
2368 the proper thing. */
2371 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2372 bool may_use_invariant)
2374 enum rtx_code code = GET_CODE (x);
2375 struct elim_table *ep;
2382 if (! current_function_decl)
2404 /* First handle the case where we encounter a bare register that
2405 is eliminable. Replace it with a PLUS. */
2406 if (regno < FIRST_PSEUDO_REGISTER)
2408 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2410 if (ep->from_rtx == x && ep->can_eliminate)
2411 return plus_constant (ep->to_rtx, ep->previous_offset);
2414 else if (reg_renumber && reg_renumber[regno] < 0
2415 && reg_equiv_invariant && reg_equiv_invariant[regno])
2417 if (may_use_invariant)
2418 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2419 mem_mode, insn, true);
2420 /* There exists at least one use of REGNO that cannot be
2421 eliminated. Prevent the defining insn from being deleted. */
2422 reg_equiv_init[regno] = NULL_RTX;
2423 alter_reg (regno, -1);
2427 /* You might think handling MINUS in a manner similar to PLUS is a
2428 good idea. It is not. It has been tried multiple times and every
2429 time the change has had to have been reverted.
2431 Other parts of reload know a PLUS is special (gen_reload for example)
2432 and require special code to handle code a reloaded PLUS operand.
2434 Also consider backends where the flags register is clobbered by a
2435 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2436 lea instruction comes to mind). If we try to reload a MINUS, we
2437 may kill the flags register that was holding a useful value.
2439 So, please before trying to handle MINUS, consider reload as a
2440 whole instead of this little section as well as the backend issues. */
2442 /* If this is the sum of an eliminable register and a constant, rework
2444 if (REG_P (XEXP (x, 0))
2445 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2446 && CONSTANT_P (XEXP (x, 1)))
2448 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2450 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2452 /* The only time we want to replace a PLUS with a REG (this
2453 occurs when the constant operand of the PLUS is the negative
2454 of the offset) is when we are inside a MEM. We won't want
2455 to do so at other times because that would change the
2456 structure of the insn in a way that reload can't handle.
2457 We special-case the commonest situation in
2458 eliminate_regs_in_insn, so just replace a PLUS with a
2459 PLUS here, unless inside a MEM. */
2460 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2461 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2464 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2465 plus_constant (XEXP (x, 1),
2466 ep->previous_offset));
2469 /* If the register is not eliminable, we are done since the other
2470 operand is a constant. */
2474 /* If this is part of an address, we want to bring any constant to the
2475 outermost PLUS. We will do this by doing register replacement in
2476 our operands and seeing if a constant shows up in one of them.
2478 Note that there is no risk of modifying the structure of the insn,
2479 since we only get called for its operands, thus we are either
2480 modifying the address inside a MEM, or something like an address
2481 operand of a load-address insn. */
2484 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2485 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2487 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2489 /* If one side is a PLUS and the other side is a pseudo that
2490 didn't get a hard register but has a reg_equiv_constant,
2491 we must replace the constant here since it may no longer
2492 be in the position of any operand. */
2493 if (GET_CODE (new0) == PLUS && REG_P (new1)
2494 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2495 && reg_renumber[REGNO (new1)] < 0
2496 && reg_equiv_constant != 0
2497 && reg_equiv_constant[REGNO (new1)] != 0)
2498 new1 = reg_equiv_constant[REGNO (new1)];
2499 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2500 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2501 && reg_renumber[REGNO (new0)] < 0
2502 && reg_equiv_constant[REGNO (new0)] != 0)
2503 new0 = reg_equiv_constant[REGNO (new0)];
2505 new = form_sum (new0, new1);
2507 /* As above, if we are not inside a MEM we do not want to
2508 turn a PLUS into something else. We might try to do so here
2509 for an addition of 0 if we aren't optimizing. */
2510 if (! mem_mode && GET_CODE (new) != PLUS)
2511 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2519 /* If this is the product of an eliminable register and a
2520 constant, apply the distribute law and move the constant out
2521 so that we have (plus (mult ..) ..). This is needed in order
2522 to keep load-address insns valid. This case is pathological.
2523 We ignore the possibility of overflow here. */
2524 if (REG_P (XEXP (x, 0))
2525 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2526 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2527 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2529 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2532 /* Refs inside notes don't count for this purpose. */
2533 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2534 || GET_CODE (insn) == INSN_LIST)))
2535 ep->ref_outside_mem = 1;
2538 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2539 ep->previous_offset * INTVAL (XEXP (x, 1)));
2542 /* ... fall through ... */
2546 /* See comments before PLUS about handling MINUS. */
2548 case DIV: case UDIV:
2549 case MOD: case UMOD:
2550 case AND: case IOR: case XOR:
2551 case ROTATERT: case ROTATE:
2552 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2554 case GE: case GT: case GEU: case GTU:
2555 case LE: case LT: case LEU: case LTU:
2557 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2558 rtx new1 = XEXP (x, 1)
2559 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2561 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2562 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2567 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2570 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2571 if (new != XEXP (x, 0))
2573 /* If this is a REG_DEAD note, it is not valid anymore.
2574 Using the eliminated version could result in creating a
2575 REG_DEAD note for the stack or frame pointer. */
2576 if (GET_MODE (x) == REG_DEAD)
2578 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2581 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2585 /* ... fall through ... */
2588 /* Now do eliminations in the rest of the chain. If this was
2589 an EXPR_LIST, this might result in allocating more memory than is
2590 strictly needed, but it simplifies the code. */
2593 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2594 if (new != XEXP (x, 1))
2596 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2604 /* We do not support elimination of a register that is modified.
2605 elimination_effects has already make sure that this does not
2611 /* We do not support elimination of a register that is modified.
2612 elimination_effects has already make sure that this does not
2613 happen. The only remaining case we need to consider here is
2614 that the increment value may be an eliminable register. */
2615 if (GET_CODE (XEXP (x, 1)) == PLUS
2616 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2618 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2621 if (new != XEXP (XEXP (x, 1), 1))
2622 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2623 gen_rtx_PLUS (GET_MODE (x),
2628 case STRICT_LOW_PART:
2630 case SIGN_EXTEND: case ZERO_EXTEND:
2631 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2632 case FLOAT: case FIX:
2633 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2642 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2643 if (new != XEXP (x, 0))
2644 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2648 /* Similar to above processing, but preserve SUBREG_BYTE.
2649 Convert (subreg (mem)) to (mem) if not paradoxical.
2650 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2651 pseudo didn't get a hard reg, we must replace this with the
2652 eliminated version of the memory location because push_reload
2653 may do the replacement in certain circumstances. */
2654 if (REG_P (SUBREG_REG (x))
2655 && (GET_MODE_SIZE (GET_MODE (x))
2656 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2657 && reg_equiv_memory_loc != 0
2658 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2660 new = SUBREG_REG (x);
2663 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2665 if (new != SUBREG_REG (x))
2667 int x_size = GET_MODE_SIZE (GET_MODE (x));
2668 int new_size = GET_MODE_SIZE (GET_MODE (new));
2671 && ((x_size < new_size
2672 #ifdef WORD_REGISTER_OPERATIONS
2673 /* On these machines, combine can create rtl of the form
2674 (set (subreg:m1 (reg:m2 R) 0) ...)
2675 where m1 < m2, and expects something interesting to
2676 happen to the entire word. Moreover, it will use the
2677 (reg:m2 R) later, expecting all bits to be preserved.
2678 So if the number of words is the same, preserve the
2679 subreg so that push_reload can see it. */
2680 && ! ((x_size - 1) / UNITS_PER_WORD
2681 == (new_size -1 ) / UNITS_PER_WORD)
2684 || x_size == new_size)
2686 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2688 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2694 /* Our only special processing is to pass the mode of the MEM to our
2695 recursive call and copy the flags. While we are here, handle this
2696 case more efficiently. */
2698 replace_equiv_address_nv (x,
2699 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2703 /* Handle insn_list USE that a call to a pure function may generate. */
2704 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2705 if (new != XEXP (x, 0))
2706 return gen_rtx_USE (GET_MODE (x), new);
2718 /* Process each of our operands recursively. If any have changed, make a
2720 fmt = GET_RTX_FORMAT (code);
2721 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2725 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2726 if (new != XEXP (x, i) && ! copied)
2728 x = shallow_copy_rtx (x);
2733 else if (*fmt == 'E')
2736 for (j = 0; j < XVECLEN (x, i); j++)
2738 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2739 if (new != XVECEXP (x, i, j) && ! copied_vec)
2741 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2745 x = shallow_copy_rtx (x);
2748 XVEC (x, i) = new_v;
2751 XVECEXP (x, i, j) = new;
2760 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2762 return eliminate_regs_1 (x, mem_mode, insn, false);
2765 /* Scan rtx X for modifications of elimination target registers. Update
2766 the table of eliminables to reflect the changed state. MEM_MODE is
2767 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2770 elimination_effects (rtx x, enum machine_mode mem_mode)
2772 enum rtx_code code = GET_CODE (x);
2773 struct elim_table *ep;
2797 /* First handle the case where we encounter a bare register that
2798 is eliminable. Replace it with a PLUS. */
2799 if (regno < FIRST_PSEUDO_REGISTER)
2801 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2803 if (ep->from_rtx == x && ep->can_eliminate)
2806 ep->ref_outside_mem = 1;
2811 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2812 && reg_equiv_constant[regno]
2813 && ! function_invariant_p (reg_equiv_constant[regno]))
2814 elimination_effects (reg_equiv_constant[regno], mem_mode);
2823 /* If we modify the source of an elimination rule, disable it. */
2824 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2825 if (ep->from_rtx == XEXP (x, 0))
2826 ep->can_eliminate = 0;
2828 /* If we modify the target of an elimination rule by adding a constant,
2829 update its offset. If we modify the target in any other way, we'll
2830 have to disable the rule as well. */
2831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2832 if (ep->to_rtx == XEXP (x, 0))
2834 int size = GET_MODE_SIZE (mem_mode);
2836 /* If more bytes than MEM_MODE are pushed, account for them. */
2837 #ifdef PUSH_ROUNDING
2838 if (ep->to_rtx == stack_pointer_rtx)
2839 size = PUSH_ROUNDING (size);
2841 if (code == PRE_DEC || code == POST_DEC)
2843 else if (code == PRE_INC || code == POST_INC)
2845 else if (code == PRE_MODIFY || code == POST_MODIFY)
2847 if (GET_CODE (XEXP (x, 1)) == PLUS
2848 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2849 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2850 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2852 ep->can_eliminate = 0;
2856 /* These two aren't unary operators. */
2857 if (code == POST_MODIFY || code == PRE_MODIFY)
2860 /* Fall through to generic unary operation case. */
2861 case STRICT_LOW_PART:
2863 case SIGN_EXTEND: case ZERO_EXTEND:
2864 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2865 case FLOAT: case FIX:
2866 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2875 elimination_effects (XEXP (x, 0), mem_mode);
2879 if (REG_P (SUBREG_REG (x))
2880 && (GET_MODE_SIZE (GET_MODE (x))
2881 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2882 && reg_equiv_memory_loc != 0
2883 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2886 elimination_effects (SUBREG_REG (x), mem_mode);
2890 /* If using a register that is the source of an eliminate we still
2891 think can be performed, note it cannot be performed since we don't
2892 know how this register is used. */
2893 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2894 if (ep->from_rtx == XEXP (x, 0))
2895 ep->can_eliminate = 0;
2897 elimination_effects (XEXP (x, 0), mem_mode);
2901 /* If clobbering a register that is the replacement register for an
2902 elimination we still think can be performed, note that it cannot
2903 be performed. Otherwise, we need not be concerned about it. */
2904 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2905 if (ep->to_rtx == XEXP (x, 0))
2906 ep->can_eliminate = 0;
2908 elimination_effects (XEXP (x, 0), mem_mode);
2912 /* Check for setting a register that we know about. */
2913 if (REG_P (SET_DEST (x)))
2915 /* See if this is setting the replacement register for an
2918 If DEST is the hard frame pointer, we do nothing because we
2919 assume that all assignments to the frame pointer are for
2920 non-local gotos and are being done at a time when they are valid
2921 and do not disturb anything else. Some machines want to
2922 eliminate a fake argument pointer (or even a fake frame pointer)
2923 with either the real frame or the stack pointer. Assignments to
2924 the hard frame pointer must not prevent this elimination. */
2926 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2928 if (ep->to_rtx == SET_DEST (x)
2929 && SET_DEST (x) != hard_frame_pointer_rtx)
2931 /* If it is being incremented, adjust the offset. Otherwise,
2932 this elimination can't be done. */
2933 rtx src = SET_SRC (x);
2935 if (GET_CODE (src) == PLUS
2936 && XEXP (src, 0) == SET_DEST (x)
2937 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2938 ep->offset -= INTVAL (XEXP (src, 1));
2940 ep->can_eliminate = 0;
2944 elimination_effects (SET_DEST (x), 0);
2945 elimination_effects (SET_SRC (x), 0);
2949 /* Our only special processing is to pass the mode of the MEM to our
2951 elimination_effects (XEXP (x, 0), GET_MODE (x));
2958 fmt = GET_RTX_FORMAT (code);
2959 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2962 elimination_effects (XEXP (x, i), mem_mode);
2963 else if (*fmt == 'E')
2964 for (j = 0; j < XVECLEN (x, i); j++)
2965 elimination_effects (XVECEXP (x, i, j), mem_mode);
2969 /* Descend through rtx X and verify that no references to eliminable registers
2970 remain. If any do remain, mark the involved register as not
2974 check_eliminable_occurrences (rtx x)
2983 code = GET_CODE (x);
2985 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2987 struct elim_table *ep;
2989 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2990 if (ep->from_rtx == x)
2991 ep->can_eliminate = 0;
2995 fmt = GET_RTX_FORMAT (code);
2996 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2999 check_eliminable_occurrences (XEXP (x, i));
3000 else if (*fmt == 'E')
3003 for (j = 0; j < XVECLEN (x, i); j++)
3004 check_eliminable_occurrences (XVECEXP (x, i, j));
3009 /* Scan INSN and eliminate all eliminable registers in it.
3011 If REPLACE is nonzero, do the replacement destructively. Also
3012 delete the insn as dead it if it is setting an eliminable register.
3014 If REPLACE is zero, do all our allocations in reload_obstack.
3016 If no eliminations were done and this insn doesn't require any elimination
3017 processing (these are not identical conditions: it might be updating sp,
3018 but not referencing fp; this needs to be seen during reload_as_needed so
3019 that the offset between fp and sp can be taken into consideration), zero
3020 is returned. Otherwise, 1 is returned. */
3023 eliminate_regs_in_insn (rtx insn, int replace)
3025 int icode = recog_memoized (insn);
3026 rtx old_body = PATTERN (insn);
3027 int insn_is_asm = asm_noperands (old_body) >= 0;
3028 rtx old_set = single_set (insn);
3032 rtx substed_operand[MAX_RECOG_OPERANDS];
3033 rtx orig_operand[MAX_RECOG_OPERANDS];
3034 struct elim_table *ep;
3035 rtx plus_src, plus_cst_src;
3037 if (! insn_is_asm && icode < 0)
3039 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3040 || GET_CODE (PATTERN (insn)) == CLOBBER
3041 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3042 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3043 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3047 if (old_set != 0 && REG_P (SET_DEST (old_set))
3048 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3050 /* Check for setting an eliminable register. */
3051 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3052 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3054 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3055 /* If this is setting the frame pointer register to the
3056 hardware frame pointer register and this is an elimination
3057 that will be done (tested above), this insn is really
3058 adjusting the frame pointer downward to compensate for
3059 the adjustment done before a nonlocal goto. */
3060 if (ep->from == FRAME_POINTER_REGNUM
3061 && ep->to == HARD_FRAME_POINTER_REGNUM)
3063 rtx base = SET_SRC (old_set);
3064 rtx base_insn = insn;
3065 HOST_WIDE_INT offset = 0;
3067 while (base != ep->to_rtx)
3069 rtx prev_insn, prev_set;
3071 if (GET_CODE (base) == PLUS
3072 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3074 offset += INTVAL (XEXP (base, 1));
3075 base = XEXP (base, 0);
3077 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3078 && (prev_set = single_set (prev_insn)) != 0
3079 && rtx_equal_p (SET_DEST (prev_set), base))
3081 base = SET_SRC (prev_set);
3082 base_insn = prev_insn;
3088 if (base == ep->to_rtx)
3091 = plus_constant (ep->to_rtx, offset - ep->offset);
3093 new_body = old_body;
3096 new_body = copy_insn (old_body);
3097 if (REG_NOTES (insn))
3098 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3100 PATTERN (insn) = new_body;
3101 old_set = single_set (insn);
3103 /* First see if this insn remains valid when we
3104 make the change. If not, keep the INSN_CODE
3105 the same and let reload fit it up. */
3106 validate_change (insn, &SET_SRC (old_set), src, 1);
3107 validate_change (insn, &SET_DEST (old_set),
3109 if (! apply_change_group ())
3111 SET_SRC (old_set) = src;
3112 SET_DEST (old_set) = ep->to_rtx;
3121 /* In this case this insn isn't serving a useful purpose. We
3122 will delete it in reload_as_needed once we know that this
3123 elimination is, in fact, being done.
3125 If REPLACE isn't set, we can't delete this insn, but needn't
3126 process it since it won't be used unless something changes. */
3129 delete_dead_insn (insn);
3137 /* We allow one special case which happens to work on all machines we
3138 currently support: a single set with the source or a REG_EQUAL
3139 note being a PLUS of an eliminable register and a constant. */
3140 plus_src = plus_cst_src = 0;
3141 if (old_set && REG_P (SET_DEST (old_set)))
3143 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3144 plus_src = SET_SRC (old_set);
3145 /* First see if the source is of the form (plus (...) CST). */
3147 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3148 plus_cst_src = plus_src;
3149 else if (REG_P (SET_SRC (old_set))
3152 /* Otherwise, see if we have a REG_EQUAL note of the form
3153 (plus (...) CST). */
3155 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3157 if ((REG_NOTE_KIND (links) == REG_EQUAL
3158 || REG_NOTE_KIND (links) == REG_EQUIV)
3159 && GET_CODE (XEXP (links, 0)) == PLUS
3160 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3162 plus_cst_src = XEXP (links, 0);
3168 /* Check that the first operand of the PLUS is a hard reg or
3169 the lowpart subreg of one. */
3172 rtx reg = XEXP (plus_cst_src, 0);
3173 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3174 reg = SUBREG_REG (reg);
3176 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3182 rtx reg = XEXP (plus_cst_src, 0);
3183 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3185 if (GET_CODE (reg) == SUBREG)
3186 reg = SUBREG_REG (reg);
3188 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3189 if (ep->from_rtx == reg && ep->can_eliminate)
3191 rtx to_rtx = ep->to_rtx;
3192 offset += ep->offset;
3193 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3195 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3196 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3198 /* If we have a nonzero offset, and the source is already
3199 a simple REG, the following transformation would
3200 increase the cost of the insn by replacing a simple REG
3201 with (plus (reg sp) CST). So try only when we already
3202 had a PLUS before. */
3203 if (offset == 0 || plus_src)
3205 rtx new_src = plus_constant (to_rtx, offset);
3207 new_body = old_body;
3210 new_body = copy_insn (old_body);
3211 if (REG_NOTES (insn))
3212 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3214 PATTERN (insn) = new_body;
3215 old_set = single_set (insn);
3217 /* First see if this insn remains valid when we make the
3218 change. If not, try to replace the whole pattern with
3219 a simple set (this may help if the original insn was a
3220 PARALLEL that was only recognized as single_set due to
3221 REG_UNUSED notes). If this isn't valid either, keep
3222 the INSN_CODE the same and let reload fix it up. */
3223 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3225 rtx new_pat = gen_rtx_SET (VOIDmode,
3226 SET_DEST (old_set), new_src);
3228 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3229 SET_SRC (old_set) = new_src;
3236 /* This can't have an effect on elimination offsets, so skip right
3242 /* Determine the effects of this insn on elimination offsets. */
3243 elimination_effects (old_body, 0);
3245 /* Eliminate all eliminable registers occurring in operands that
3246 can be handled by reload. */
3247 extract_insn (insn);
3248 for (i = 0; i < recog_data.n_operands; i++)
3250 orig_operand[i] = recog_data.operand[i];
3251 substed_operand[i] = recog_data.operand[i];
3253 /* For an asm statement, every operand is eliminable. */
3254 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3256 bool is_set_src, in_plus;
3258 /* Check for setting a register that we know about. */
3259 if (recog_data.operand_type[i] != OP_IN
3260 && REG_P (orig_operand[i]))
3262 /* If we are assigning to a register that can be eliminated, it
3263 must be as part of a PARALLEL, since the code above handles
3264 single SETs. We must indicate that we can no longer
3265 eliminate this reg. */
3266 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3268 if (ep->from_rtx == orig_operand[i])
3269 ep->can_eliminate = 0;
3272 /* Companion to the above plus substitution, we can allow
3273 invariants as the source of a plain move. */
3275 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3279 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3280 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3284 = eliminate_regs_1 (recog_data.operand[i], 0,
3285 replace ? insn : NULL_RTX,
3286 is_set_src || in_plus);
3287 if (substed_operand[i] != orig_operand[i])
3289 /* Terminate the search in check_eliminable_occurrences at
3291 *recog_data.operand_loc[i] = 0;
3293 /* If an output operand changed from a REG to a MEM and INSN is an
3294 insn, write a CLOBBER insn. */
3295 if (recog_data.operand_type[i] != OP_IN
3296 && REG_P (orig_operand[i])
3297 && MEM_P (substed_operand[i])
3299 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3304 for (i = 0; i < recog_data.n_dups; i++)
3305 *recog_data.dup_loc[i]
3306 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3308 /* If any eliminable remain, they aren't eliminable anymore. */
3309 check_eliminable_occurrences (old_body);
3311 /* Substitute the operands; the new values are in the substed_operand
3313 for (i = 0; i < recog_data.n_operands; i++)
3314 *recog_data.operand_loc[i] = substed_operand[i];
3315 for (i = 0; i < recog_data.n_dups; i++)
3316 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3318 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3319 re-recognize the insn. We do this in case we had a simple addition
3320 but now can do this as a load-address. This saves an insn in this
3322 If re-recognition fails, the old insn code number will still be used,
3323 and some register operands may have changed into PLUS expressions.
3324 These will be handled by find_reloads by loading them into a register
3329 /* If we aren't replacing things permanently and we changed something,
3330 make another copy to ensure that all the RTL is new. Otherwise
3331 things can go wrong if find_reload swaps commutative operands
3332 and one is inside RTL that has been copied while the other is not. */
3333 new_body = old_body;
3336 new_body = copy_insn (old_body);
3337 if (REG_NOTES (insn))
3338 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3340 PATTERN (insn) = new_body;
3342 /* If we had a move insn but now we don't, rerecognize it. This will
3343 cause spurious re-recognition if the old move had a PARALLEL since
3344 the new one still will, but we can't call single_set without
3345 having put NEW_BODY into the insn and the re-recognition won't
3346 hurt in this rare case. */
3347 /* ??? Why this huge if statement - why don't we just rerecognize the
3351 && ((REG_P (SET_SRC (old_set))
3352 && (GET_CODE (new_body) != SET
3353 || !REG_P (SET_SRC (new_body))))
3354 /* If this was a load from or store to memory, compare
3355 the MEM in recog_data.operand to the one in the insn.
3356 If they are not equal, then rerecognize the insn. */
3358 && ((MEM_P (SET_SRC (old_set))
3359 && SET_SRC (old_set) != recog_data.operand[1])
3360 || (MEM_P (SET_DEST (old_set))
3361 && SET_DEST (old_set) != recog_data.operand[0])))
3362 /* If this was an add insn before, rerecognize. */
3363 || GET_CODE (SET_SRC (old_set)) == PLUS))
3365 int new_icode = recog (PATTERN (insn), insn, 0);
3367 INSN_CODE (insn) = new_icode;
3371 /* Restore the old body. If there were any changes to it, we made a copy
3372 of it while the changes were still in place, so we'll correctly return
3373 a modified insn below. */
3376 /* Restore the old body. */
3377 for (i = 0; i < recog_data.n_operands; i++)
3378 *recog_data.operand_loc[i] = orig_operand[i];
3379 for (i = 0; i < recog_data.n_dups; i++)
3380 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3383 /* Update all elimination pairs to reflect the status after the current
3384 insn. The changes we make were determined by the earlier call to
3385 elimination_effects.
3387 We also detect cases where register elimination cannot be done,
3388 namely, if a register would be both changed and referenced outside a MEM
3389 in the resulting insn since such an insn is often undefined and, even if
3390 not, we cannot know what meaning will be given to it. Note that it is
3391 valid to have a register used in an address in an insn that changes it
3392 (presumably with a pre- or post-increment or decrement).
3394 If anything changes, return nonzero. */
3396 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3398 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3399 ep->can_eliminate = 0;
3401 ep->ref_outside_mem = 0;
3403 if (ep->previous_offset != ep->offset)
3408 /* If we changed something, perform elimination in REG_NOTES. This is
3409 needed even when REPLACE is zero because a REG_DEAD note might refer
3410 to a register that we eliminate and could cause a different number
3411 of spill registers to be needed in the final reload pass than in
3413 if (val && REG_NOTES (insn) != 0)
3415 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3420 /* Loop through all elimination pairs.
3421 Recalculate the number not at initial offset.
3423 Compute the maximum offset (minimum offset if the stack does not
3424 grow downward) for each elimination pair. */
3427 update_eliminable_offsets (void)
3429 struct elim_table *ep;
3431 num_not_at_initial_offset = 0;
3432 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3434 ep->previous_offset = ep->offset;
3435 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3436 num_not_at_initial_offset++;
3440 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3441 replacement we currently believe is valid, mark it as not eliminable if X
3442 modifies DEST in any way other than by adding a constant integer to it.
3444 If DEST is the frame pointer, we do nothing because we assume that
3445 all assignments to the hard frame pointer are nonlocal gotos and are being
3446 done at a time when they are valid and do not disturb anything else.
3447 Some machines want to eliminate a fake argument pointer with either the
3448 frame or stack pointer. Assignments to the hard frame pointer must not
3449 prevent this elimination.
3451 Called via note_stores from reload before starting its passes to scan
3452 the insns of the function. */
3455 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3459 /* A SUBREG of a hard register here is just changing its mode. We should
3460 not see a SUBREG of an eliminable hard register, but check just in
3462 if (GET_CODE (dest) == SUBREG)
3463 dest = SUBREG_REG (dest);
3465 if (dest == hard_frame_pointer_rtx)
3468 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3469 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3470 && (GET_CODE (x) != SET
3471 || GET_CODE (SET_SRC (x)) != PLUS
3472 || XEXP (SET_SRC (x), 0) != dest
3473 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3475 reg_eliminate[i].can_eliminate_previous
3476 = reg_eliminate[i].can_eliminate = 0;
3481 /* Verify that the initial elimination offsets did not change since the
3482 last call to set_initial_elim_offsets. This is used to catch cases
3483 where something illegal happened during reload_as_needed that could
3484 cause incorrect code to be generated if we did not check for it. */
3487 verify_initial_elim_offsets (void)
3491 if (!num_eliminable)
3494 #ifdef ELIMINABLE_REGS
3496 struct elim_table *ep;
3498 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3500 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3501 if (t != ep->initial_offset)
3506 INITIAL_FRAME_POINTER_OFFSET (t);
3507 if (t != reg_eliminate[0].initial_offset)
3514 /* Reset all offsets on eliminable registers to their initial values. */
3517 set_initial_elim_offsets (void)
3519 struct elim_table *ep = reg_eliminate;
3521 #ifdef ELIMINABLE_REGS
3522 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3524 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3525 ep->previous_offset = ep->offset = ep->initial_offset;
3528 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3529 ep->previous_offset = ep->offset = ep->initial_offset;
3532 num_not_at_initial_offset = 0;
3535 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3538 set_initial_eh_label_offset (rtx label)
3540 set_label_offsets (label, NULL_RTX, 1);
3543 /* Initialize the known label offsets.
3544 Set a known offset for each forced label to be at the initial offset
3545 of each elimination. We do this because we assume that all
3546 computed jumps occur from a location where each elimination is
3547 at its initial offset.
3548 For all other labels, show that we don't know the offsets. */
3551 set_initial_label_offsets (void)
3554 memset (offsets_known_at, 0, num_labels);
3556 for (x = forced_labels; x; x = XEXP (x, 1))
3558 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3560 for_each_eh_label (set_initial_eh_label_offset);
3563 /* Set all elimination offsets to the known values for the code label given
3567 set_offsets_for_label (rtx insn)
3570 int label_nr = CODE_LABEL_NUMBER (insn);
3571 struct elim_table *ep;
3573 num_not_at_initial_offset = 0;
3574 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3576 ep->offset = ep->previous_offset
3577 = offsets_at[label_nr - first_label_num][i];
3578 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3579 num_not_at_initial_offset++;
3583 /* See if anything that happened changes which eliminations are valid.
3584 For example, on the SPARC, whether or not the frame pointer can
3585 be eliminated can depend on what registers have been used. We need
3586 not check some conditions again (such as flag_omit_frame_pointer)
3587 since they can't have changed. */
3590 update_eliminables (HARD_REG_SET *pset)
3592 int previous_frame_pointer_needed = frame_pointer_needed;
3593 struct elim_table *ep;
3595 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3596 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3597 #ifdef ELIMINABLE_REGS
3598 || ! CAN_ELIMINATE (ep->from, ep->to)
3601 ep->can_eliminate = 0;
3603 /* Look for the case where we have discovered that we can't replace
3604 register A with register B and that means that we will now be
3605 trying to replace register A with register C. This means we can
3606 no longer replace register C with register B and we need to disable
3607 such an elimination, if it exists. This occurs often with A == ap,
3608 B == sp, and C == fp. */
3610 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3612 struct elim_table *op;
3615 if (! ep->can_eliminate && ep->can_eliminate_previous)
3617 /* Find the current elimination for ep->from, if there is a
3619 for (op = reg_eliminate;
3620 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3621 if (op->from == ep->from && op->can_eliminate)
3627 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3629 for (op = reg_eliminate;
3630 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3631 if (op->from == new_to && op->to == ep->to)
3632 op->can_eliminate = 0;
3636 /* See if any registers that we thought we could eliminate the previous
3637 time are no longer eliminable. If so, something has changed and we
3638 must spill the register. Also, recompute the number of eliminable
3639 registers and see if the frame pointer is needed; it is if there is
3640 no elimination of the frame pointer that we can perform. */
3642 frame_pointer_needed = 1;
3643 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3645 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3646 && ep->to != HARD_FRAME_POINTER_REGNUM)
3647 frame_pointer_needed = 0;
3649 if (! ep->can_eliminate && ep->can_eliminate_previous)
3651 ep->can_eliminate_previous = 0;
3652 SET_HARD_REG_BIT (*pset, ep->from);
3657 /* If we didn't need a frame pointer last time, but we do now, spill
3658 the hard frame pointer. */
3659 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3660 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3663 /* Return true if X is used as the target register of an elimination. */
3666 elimination_target_reg_p (rtx x)
3668 struct elim_table *ep;
3670 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3671 if (ep->to_rtx == x && ep->can_eliminate)
3677 /* Initialize the table of registers to eliminate. */
3680 init_elim_table (void)
3682 struct elim_table *ep;
3683 #ifdef ELIMINABLE_REGS
3684 const struct elim_table_1 *ep1;
3688 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3690 /* Does this function require a frame pointer? */
3692 frame_pointer_needed = (! flag_omit_frame_pointer
3693 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3694 and restore sp for alloca. So we can't eliminate
3695 the frame pointer in that case. At some point,
3696 we should improve this by emitting the
3697 sp-adjusting insns for this case. */
3698 || (current_function_calls_alloca
3699 && EXIT_IGNORE_STACK)
3700 || current_function_accesses_prior_frames
3701 || FRAME_POINTER_REQUIRED);
3705 #ifdef ELIMINABLE_REGS
3706 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3707 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3709 ep->from = ep1->from;
3711 ep->can_eliminate = ep->can_eliminate_previous
3712 = (CAN_ELIMINATE (ep->from, ep->to)
3713 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3716 reg_eliminate[0].from = reg_eliminate_1[0].from;
3717 reg_eliminate[0].to = reg_eliminate_1[0].to;
3718 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3719 = ! frame_pointer_needed;
3722 /* Count the number of eliminable registers and build the FROM and TO
3723 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3724 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3725 We depend on this. */
3726 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3728 num_eliminable += ep->can_eliminate;
3729 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3730 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3734 /* Kick all pseudos out of hard register REGNO.
3736 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3737 because we found we can't eliminate some register. In the case, no pseudos
3738 are allowed to be in the register, even if they are only in a block that
3739 doesn't require spill registers, unlike the case when we are spilling this
3740 hard reg to produce another spill register.
3742 Return nonzero if any pseudos needed to be kicked out. */
3745 spill_hard_reg (unsigned int regno, int cant_eliminate)
3751 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3752 regs_ever_live[regno] = 1;
3755 /* Spill every pseudo reg that was allocated to this reg
3756 or to something that overlaps this reg. */
3758 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3759 if (reg_renumber[i] >= 0
3760 && (unsigned int) reg_renumber[i] <= regno
3761 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3762 SET_REGNO_REG_SET (&spilled_pseudos, i);
3765 /* After find_reload_regs has been run for all insn that need reloads,
3766 and/or spill_hard_regs was called, this function is used to actually
3767 spill pseudo registers and try to reallocate them. It also sets up the
3768 spill_regs array for use by choose_reload_regs. */
3771 finish_spills (int global)
3773 struct insn_chain *chain;
3774 int something_changed = 0;
3776 reg_set_iterator rsi;
3778 /* Build the spill_regs array for the function. */
3779 /* If there are some registers still to eliminate and one of the spill regs
3780 wasn't ever used before, additional stack space may have to be
3781 allocated to store this register. Thus, we may have changed the offset
3782 between the stack and frame pointers, so mark that something has changed.
3784 One might think that we need only set VAL to 1 if this is a call-used
3785 register. However, the set of registers that must be saved by the
3786 prologue is not identical to the call-used set. For example, the
3787 register used by the call insn for the return PC is a call-used register,
3788 but must be saved by the prologue. */
3791 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3792 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3794 spill_reg_order[i] = n_spills;
3795 spill_regs[n_spills++] = i;
3796 if (num_eliminable && ! regs_ever_live[i])
3797 something_changed = 1;
3798 regs_ever_live[i] = 1;
3801 spill_reg_order[i] = -1;
3803 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3805 /* Record the current hard register the pseudo is allocated to in
3806 pseudo_previous_regs so we avoid reallocating it to the same
3807 hard reg in a later pass. */
3808 gcc_assert (reg_renumber[i] >= 0);
3810 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3811 /* Mark it as no longer having a hard register home. */
3812 reg_renumber[i] = -1;
3813 /* We will need to scan everything again. */
3814 something_changed = 1;
3817 /* Retry global register allocation if possible. */
3820 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3821 /* For every insn that needs reloads, set the registers used as spill
3822 regs in pseudo_forbidden_regs for every pseudo live across the
3824 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3826 EXECUTE_IF_SET_IN_REG_SET
3827 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3829 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3830 chain->used_spill_regs);
3832 EXECUTE_IF_SET_IN_REG_SET
3833 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3835 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3836 chain->used_spill_regs);
3840 /* Retry allocating the spilled pseudos. For each reg, merge the
3841 various reg sets that indicate which hard regs can't be used,
3842 and call retry_global_alloc.
3843 We change spill_pseudos here to only contain pseudos that did not
3844 get a new hard register. */
3845 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3846 if (reg_old_renumber[i] != reg_renumber[i])
3848 HARD_REG_SET forbidden;
3849 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3850 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3851 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3852 retry_global_alloc (i, forbidden);
3853 if (reg_renumber[i] >= 0)
3854 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3858 /* Fix up the register information in the insn chain.
3859 This involves deleting those of the spilled pseudos which did not get
3860 a new hard register home from the live_{before,after} sets. */
3861 for (chain = reload_insn_chain; chain; chain = chain->next)
3863 HARD_REG_SET used_by_pseudos;
3864 HARD_REG_SET used_by_pseudos2;
3866 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3867 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3869 /* Mark any unallocated hard regs as available for spills. That
3870 makes inheritance work somewhat better. */
3871 if (chain->need_reload)
3873 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3874 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3875 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3877 /* Save the old value for the sanity test below. */
3878 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3880 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3881 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3882 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3883 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3885 /* Make sure we only enlarge the set. */
3886 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3887 chain->used_spill_regs));
3891 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3892 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3894 int regno = reg_renumber[i];
3895 if (reg_old_renumber[i] == regno)
3898 alter_reg (i, reg_old_renumber[i]);
3899 reg_old_renumber[i] = regno;
3903 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3905 fprintf (dump_file, " Register %d now in %d.\n\n",
3906 i, reg_renumber[i]);
3910 return something_changed;
3913 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3916 scan_paradoxical_subregs (rtx x)
3920 enum rtx_code code = GET_CODE (x);
3930 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3938 if (REG_P (SUBREG_REG (x))
3939 && (GET_MODE_SIZE (GET_MODE (x))
3940 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3941 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3942 = GET_MODE_SIZE (GET_MODE (x));
3949 fmt = GET_RTX_FORMAT (code);
3950 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3953 scan_paradoxical_subregs (XEXP (x, i));
3954 else if (fmt[i] == 'E')
3957 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3958 scan_paradoxical_subregs (XVECEXP (x, i, j));
3963 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3964 examine all of the reload insns between PREV and NEXT exclusive, and
3965 annotate all that may trap. */
3968 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3970 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3971 unsigned int trap_count;
3977 if (may_trap_p (PATTERN (insn)))
3981 remove_note (insn, note);
3985 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3986 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3990 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3994 /* Reload pseudo-registers into hard regs around each insn as needed.
3995 Additional register load insns are output before the insn that needs it
3996 and perhaps store insns after insns that modify the reloaded pseudo reg.
3998 reg_last_reload_reg and reg_reloaded_contents keep track of
3999 which registers are already available in reload registers.
4000 We update these for the reloads that we perform,
4001 as the insns are scanned. */
4004 reload_as_needed (int live_known)
4006 struct insn_chain *chain;
4007 #if defined (AUTO_INC_DEC)
4012 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4013 memset (spill_reg_store, 0, sizeof spill_reg_store);
4014 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4015 INIT_REG_SET (®_has_output_reload);
4016 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4017 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4019 set_initial_elim_offsets ();
4021 for (chain = reload_insn_chain; chain; chain = chain->next)
4024 rtx insn = chain->insn;
4025 rtx old_next = NEXT_INSN (insn);
4027 /* If we pass a label, copy the offsets from the label information
4028 into the current offsets of each elimination. */
4030 set_offsets_for_label (insn);
4032 else if (INSN_P (insn))
4034 regset_head regs_to_forget;
4035 INIT_REG_SET (®s_to_forget);
4036 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4038 /* If this is a USE and CLOBBER of a MEM, ensure that any
4039 references to eliminable registers have been removed. */
4041 if ((GET_CODE (PATTERN (insn)) == USE
4042 || GET_CODE (PATTERN (insn)) == CLOBBER)
4043 && MEM_P (XEXP (PATTERN (insn), 0)))
4044 XEXP (XEXP (PATTERN (insn), 0), 0)
4045 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4046 GET_MODE (XEXP (PATTERN (insn), 0)),
4049 /* If we need to do register elimination processing, do so.
4050 This might delete the insn, in which case we are done. */
4051 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4053 eliminate_regs_in_insn (insn, 1);
4056 update_eliminable_offsets ();
4057 CLEAR_REG_SET (®s_to_forget);
4062 /* If need_elim is nonzero but need_reload is zero, one might think
4063 that we could simply set n_reloads to 0. However, find_reloads
4064 could have done some manipulation of the insn (such as swapping
4065 commutative operands), and these manipulations are lost during
4066 the first pass for every insn that needs register elimination.
4067 So the actions of find_reloads must be redone here. */
4069 if (! chain->need_elim && ! chain->need_reload
4070 && ! chain->need_operand_change)
4072 /* First find the pseudo regs that must be reloaded for this insn.
4073 This info is returned in the tables reload_... (see reload.h).
4074 Also modify the body of INSN by substituting RELOAD
4075 rtx's for those pseudo regs. */
4078 CLEAR_REG_SET (®_has_output_reload);
4079 CLEAR_HARD_REG_SET (reg_is_output_reload);
4081 find_reloads (insn, 1, spill_indirect_levels, live_known,
4087 rtx next = NEXT_INSN (insn);
4090 prev = PREV_INSN (insn);
4092 /* Now compute which reload regs to reload them into. Perhaps
4093 reusing reload regs from previous insns, or else output
4094 load insns to reload them. Maybe output store insns too.
4095 Record the choices of reload reg in reload_reg_rtx. */
4096 choose_reload_regs (chain);
4098 /* Merge any reloads that we didn't combine for fear of
4099 increasing the number of spill registers needed but now
4100 discover can be safely merged. */
4101 if (SMALL_REGISTER_CLASSES)
4102 merge_assigned_reloads (insn);
4104 /* Generate the insns to reload operands into or out of
4105 their reload regs. */
4106 emit_reload_insns (chain);
4108 /* Substitute the chosen reload regs from reload_reg_rtx
4109 into the insn's body (or perhaps into the bodies of other
4110 load and store insn that we just made for reloading
4111 and that we moved the structure into). */
4112 subst_reloads (insn);
4114 /* Adjust the exception region notes for loads and stores. */
4115 if (flag_non_call_exceptions && !CALL_P (insn))
4116 fixup_eh_region_note (insn, prev, next);
4118 /* If this was an ASM, make sure that all the reload insns
4119 we have generated are valid. If not, give an error
4121 if (asm_noperands (PATTERN (insn)) >= 0)
4122 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4123 if (p != insn && INSN_P (p)
4124 && GET_CODE (PATTERN (p)) != USE
4125 && (recog_memoized (p) < 0
4126 || (extract_insn (p), ! constrain_operands (1))))
4128 error_for_asm (insn,
4129 "%<asm%> operand requires "
4130 "impossible reload");
4135 if (num_eliminable && chain->need_elim)
4136 update_eliminable_offsets ();
4138 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4139 is no longer validly lying around to save a future reload.
4140 Note that this does not detect pseudos that were reloaded
4141 for this insn in order to be stored in
4142 (obeying register constraints). That is correct; such reload
4143 registers ARE still valid. */
4144 forget_marked_reloads (®s_to_forget);
4145 CLEAR_REG_SET (®s_to_forget);
4147 /* There may have been CLOBBER insns placed after INSN. So scan
4148 between INSN and NEXT and use them to forget old reloads. */
4149 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4150 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4151 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4154 /* Likewise for regs altered by auto-increment in this insn.
4155 REG_INC notes have been changed by reloading:
4156 find_reloads_address_1 records substitutions for them,
4157 which have been performed by subst_reloads above. */
4158 for (i = n_reloads - 1; i >= 0; i--)
4160 rtx in_reg = rld[i].in_reg;
4163 enum rtx_code code = GET_CODE (in_reg);
4164 /* PRE_INC / PRE_DEC will have the reload register ending up
4165 with the same value as the stack slot, but that doesn't
4166 hold true for POST_INC / POST_DEC. Either we have to
4167 convert the memory access to a true POST_INC / POST_DEC,
4168 or we can't use the reload register for inheritance. */
4169 if ((code == POST_INC || code == POST_DEC)
4170 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4171 REGNO (rld[i].reg_rtx))
4172 /* Make sure it is the inc/dec pseudo, and not
4173 some other (e.g. output operand) pseudo. */
4174 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4175 == REGNO (XEXP (in_reg, 0))))
4178 rtx reload_reg = rld[i].reg_rtx;
4179 enum machine_mode mode = GET_MODE (reload_reg);
4183 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4185 /* We really want to ignore REG_INC notes here, so
4186 use PATTERN (p) as argument to reg_set_p . */
4187 if (reg_set_p (reload_reg, PATTERN (p)))
4189 n = count_occurrences (PATTERN (p), reload_reg, 0);
4194 n = validate_replace_rtx (reload_reg,
4195 gen_rtx_fmt_e (code,
4200 /* We must also verify that the constraints
4201 are met after the replacement. */
4204 n = constrain_operands (1);
4208 /* If the constraints were not met, then
4209 undo the replacement. */
4212 validate_replace_rtx (gen_rtx_fmt_e (code,
4225 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4227 /* Mark this as having an output reload so that the
4228 REG_INC processing code below won't invalidate
4229 the reload for inheritance. */
4230 SET_HARD_REG_BIT (reg_is_output_reload,
4231 REGNO (reload_reg));
4232 SET_REGNO_REG_SET (®_has_output_reload,
4233 REGNO (XEXP (in_reg, 0)));
4236 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4239 else if ((code == PRE_INC || code == PRE_DEC)
4240 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4241 REGNO (rld[i].reg_rtx))
4242 /* Make sure it is the inc/dec pseudo, and not
4243 some other (e.g. output operand) pseudo. */
4244 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4245 == REGNO (XEXP (in_reg, 0))))
4247 SET_HARD_REG_BIT (reg_is_output_reload,
4248 REGNO (rld[i].reg_rtx));
4249 SET_REGNO_REG_SET (®_has_output_reload,
4250 REGNO (XEXP (in_reg, 0)));
4254 /* If a pseudo that got a hard register is auto-incremented,
4255 we must purge records of copying it into pseudos without
4257 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4258 if (REG_NOTE_KIND (x) == REG_INC)
4260 /* See if this pseudo reg was reloaded in this insn.
4261 If so, its last-reload info is still valid
4262 because it is based on this insn's reload. */
4263 for (i = 0; i < n_reloads; i++)
4264 if (rld[i].out == XEXP (x, 0))
4268 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4272 /* A reload reg's contents are unknown after a label. */
4274 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4276 /* Don't assume a reload reg is still good after a call insn
4277 if it is a call-used reg, or if it contains a value that will
4278 be partially clobbered by the call. */
4279 else if (CALL_P (insn))
4281 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4282 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4287 free (reg_last_reload_reg);
4288 CLEAR_REG_SET (®_has_output_reload);
4291 /* Discard all record of any value reloaded from X,
4292 or reloaded in X from someplace else;
4293 unless X is an output reload reg of the current insn.
4295 X may be a hard reg (the reload reg)
4296 or it may be a pseudo reg that was reloaded from.
4298 When DATA is non-NULL just mark the registers in regset
4299 to be forgotten later. */
4302 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4307 regset regs = (regset) data;
4309 /* note_stores does give us subregs of hard regs,
4310 subreg_regno_offset requires a hard reg. */
4311 while (GET_CODE (x) == SUBREG)
4313 /* We ignore the subreg offset when calculating the regno,
4314 because we are using the entire underlying hard register
4324 if (regno >= FIRST_PSEUDO_REGISTER)
4330 nr = hard_regno_nregs[regno][GET_MODE (x)];
4331 /* Storing into a spilled-reg invalidates its contents.
4332 This can happen if a block-local pseudo is allocated to that reg
4333 and it wasn't spilled because this block's total need is 0.
4334 Then some insn might have an optional reload and use this reg. */
4336 for (i = 0; i < nr; i++)
4337 /* But don't do this if the reg actually serves as an output
4338 reload reg in the current instruction. */
4340 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4342 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4343 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4344 spill_reg_store[regno + i] = 0;
4350 SET_REGNO_REG_SET (regs, regno + nr);
4353 /* Since value of X has changed,
4354 forget any value previously copied from it. */
4357 /* But don't forget a copy if this is the output reload
4358 that establishes the copy's validity. */
4360 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4361 reg_last_reload_reg[regno + nr] = 0;
4365 /* Forget the reloads marked in regset by previous function. */
4367 forget_marked_reloads (regset regs)
4370 reg_set_iterator rsi;
4371 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4373 if (reg < FIRST_PSEUDO_REGISTER
4374 /* But don't do this if the reg actually serves as an output
4375 reload reg in the current instruction. */
4377 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4379 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4380 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4381 spill_reg_store[reg] = 0;
4384 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4385 reg_last_reload_reg[reg] = 0;
4389 /* The following HARD_REG_SETs indicate when each hard register is
4390 used for a reload of various parts of the current insn. */
4392 /* If reg is unavailable for all reloads. */
4393 static HARD_REG_SET reload_reg_unavailable;
4394 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4395 static HARD_REG_SET reload_reg_used;
4396 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4397 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4398 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4399 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4400 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4401 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4402 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4403 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4404 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4405 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4406 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4407 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4408 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4409 static HARD_REG_SET reload_reg_used_in_op_addr;
4410 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4411 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4412 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4413 static HARD_REG_SET reload_reg_used_in_insn;
4414 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4415 static HARD_REG_SET reload_reg_used_in_other_addr;
4417 /* If reg is in use as a reload reg for any sort of reload. */
4418 static HARD_REG_SET reload_reg_used_at_all;
4420 /* If reg is use as an inherited reload. We just mark the first register
4422 static HARD_REG_SET reload_reg_used_for_inherit;
4424 /* Records which hard regs are used in any way, either as explicit use or
4425 by being allocated to a pseudo during any point of the current insn. */
4426 static HARD_REG_SET reg_used_in_insn;
4428 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4429 TYPE. MODE is used to indicate how many consecutive regs are
4433 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4434 enum machine_mode mode)
4436 unsigned int nregs = hard_regno_nregs[regno][mode];
4439 for (i = regno; i < nregs + regno; i++)
4444 SET_HARD_REG_BIT (reload_reg_used, i);
4447 case RELOAD_FOR_INPUT_ADDRESS:
4448 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4451 case RELOAD_FOR_INPADDR_ADDRESS:
4452 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4455 case RELOAD_FOR_OUTPUT_ADDRESS:
4456 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4459 case RELOAD_FOR_OUTADDR_ADDRESS:
4460 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4463 case RELOAD_FOR_OPERAND_ADDRESS:
4464 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4467 case RELOAD_FOR_OPADDR_ADDR:
4468 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4471 case RELOAD_FOR_OTHER_ADDRESS:
4472 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4475 case RELOAD_FOR_INPUT:
4476 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4479 case RELOAD_FOR_OUTPUT:
4480 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4483 case RELOAD_FOR_INSN:
4484 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4488 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4492 /* Similarly, but show REGNO is no longer in use for a reload. */
4495 clear_reload_reg_in_use (unsigned int regno, int opnum,
4496 enum reload_type type, enum machine_mode mode)
4498 unsigned int nregs = hard_regno_nregs[regno][mode];
4499 unsigned int start_regno, end_regno, r;
4501 /* A complication is that for some reload types, inheritance might
4502 allow multiple reloads of the same types to share a reload register.
4503 We set check_opnum if we have to check only reloads with the same
4504 operand number, and check_any if we have to check all reloads. */
4505 int check_opnum = 0;
4507 HARD_REG_SET *used_in_set;
4512 used_in_set = &reload_reg_used;
4515 case RELOAD_FOR_INPUT_ADDRESS:
4516 used_in_set = &reload_reg_used_in_input_addr[opnum];
4519 case RELOAD_FOR_INPADDR_ADDRESS:
4521 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4524 case RELOAD_FOR_OUTPUT_ADDRESS:
4525 used_in_set = &reload_reg_used_in_output_addr[opnum];
4528 case RELOAD_FOR_OUTADDR_ADDRESS:
4530 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4533 case RELOAD_FOR_OPERAND_ADDRESS:
4534 used_in_set = &reload_reg_used_in_op_addr;
4537 case RELOAD_FOR_OPADDR_ADDR:
4539 used_in_set = &reload_reg_used_in_op_addr_reload;
4542 case RELOAD_FOR_OTHER_ADDRESS:
4543 used_in_set = &reload_reg_used_in_other_addr;
4547 case RELOAD_FOR_INPUT:
4548 used_in_set = &reload_reg_used_in_input[opnum];
4551 case RELOAD_FOR_OUTPUT:
4552 used_in_set = &reload_reg_used_in_output[opnum];
4555 case RELOAD_FOR_INSN:
4556 used_in_set = &reload_reg_used_in_insn;
4561 /* We resolve conflicts with remaining reloads of the same type by
4562 excluding the intervals of reload registers by them from the
4563 interval of freed reload registers. Since we only keep track of
4564 one set of interval bounds, we might have to exclude somewhat
4565 more than what would be necessary if we used a HARD_REG_SET here.
4566 But this should only happen very infrequently, so there should
4567 be no reason to worry about it. */
4569 start_regno = regno;
4570 end_regno = regno + nregs;
4571 if (check_opnum || check_any)
4573 for (i = n_reloads - 1; i >= 0; i--)
4575 if (rld[i].when_needed == type
4576 && (check_any || rld[i].opnum == opnum)
4579 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4580 unsigned int conflict_end
4581 = end_hard_regno (rld[i].mode, conflict_start);
4583 /* If there is an overlap with the first to-be-freed register,
4584 adjust the interval start. */
4585 if (conflict_start <= start_regno && conflict_end > start_regno)
4586 start_regno = conflict_end;
4587 /* Otherwise, if there is a conflict with one of the other
4588 to-be-freed registers, adjust the interval end. */
4589 if (conflict_start > start_regno && conflict_start < end_regno)
4590 end_regno = conflict_start;
4595 for (r = start_regno; r < end_regno; r++)
4596 CLEAR_HARD_REG_BIT (*used_in_set, r);
4599 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4600 specified by OPNUM and TYPE. */
4603 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4607 /* In use for a RELOAD_OTHER means it's not available for anything. */
4608 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4609 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4615 /* In use for anything means we can't use it for RELOAD_OTHER. */
4616 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4622 for (i = 0; i < reload_n_operands; i++)
4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4624 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4625 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4626 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4627 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4628 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4633 case RELOAD_FOR_INPUT:
4634 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4635 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4641 /* If it is used for some other input, can't use it. */
4642 for (i = 0; i < reload_n_operands; i++)
4643 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4646 /* If it is used in a later operand's address, can't use it. */
4647 for (i = opnum + 1; i < reload_n_operands; i++)
4648 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4649 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4654 case RELOAD_FOR_INPUT_ADDRESS:
4655 /* Can't use a register if it is used for an input address for this
4656 operand or used as an input in an earlier one. */
4657 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4658 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4661 for (i = 0; i < opnum; i++)
4662 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4667 case RELOAD_FOR_INPADDR_ADDRESS:
4668 /* Can't use a register if it is used for an input address
4669 for this operand or used as an input in an earlier
4671 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4674 for (i = 0; i < opnum; i++)
4675 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4680 case RELOAD_FOR_OUTPUT_ADDRESS:
4681 /* Can't use a register if it is used for an output address for this
4682 operand or used as an output in this or a later operand. Note
4683 that multiple output operands are emitted in reverse order, so
4684 the conflicting ones are those with lower indices. */
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4688 for (i = 0; i <= opnum; i++)
4689 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4694 case RELOAD_FOR_OUTADDR_ADDRESS:
4695 /* Can't use a register if it is used for an output address
4696 for this operand or used as an output in this or a
4697 later operand. Note that multiple output operands are
4698 emitted in reverse order, so the conflicting ones are
4699 those with lower indices. */
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4703 for (i = 0; i <= opnum; i++)
4704 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4709 case RELOAD_FOR_OPERAND_ADDRESS:
4710 for (i = 0; i < reload_n_operands; i++)
4711 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4714 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4715 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4717 case RELOAD_FOR_OPADDR_ADDR:
4718 for (i = 0; i < reload_n_operands; i++)
4719 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4722 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4724 case RELOAD_FOR_OUTPUT:
4725 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4726 outputs, or an operand address for this or an earlier output.
4727 Note that multiple output operands are emitted in reverse order,
4728 so the conflicting ones are those with higher indices. */
4729 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4732 for (i = 0; i < reload_n_operands; i++)
4733 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4736 for (i = opnum; i < reload_n_operands; i++)
4737 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4738 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4743 case RELOAD_FOR_INSN:
4744 for (i = 0; i < reload_n_operands; i++)
4745 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4746 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4749 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4750 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4752 case RELOAD_FOR_OTHER_ADDRESS:
4753 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4760 /* Return 1 if the value in reload reg REGNO, as used by a reload
4761 needed for the part of the insn specified by OPNUM and TYPE,
4762 is still available in REGNO at the end of the insn.
4764 We can assume that the reload reg was already tested for availability
4765 at the time it is needed, and we should not check this again,
4766 in case the reg has already been marked in use. */
4769 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4776 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4777 its value must reach the end. */
4780 /* If this use is for part of the insn,
4781 its value reaches if no subsequent part uses the same register.
4782 Just like the above function, don't try to do this with lots
4785 case RELOAD_FOR_OTHER_ADDRESS:
4786 /* Here we check for everything else, since these don't conflict
4787 with anything else and everything comes later. */
4789 for (i = 0; i < reload_n_operands; i++)
4790 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4791 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4792 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4793 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4794 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4795 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4798 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4799 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4800 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4801 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4803 case RELOAD_FOR_INPUT_ADDRESS:
4804 case RELOAD_FOR_INPADDR_ADDRESS:
4805 /* Similar, except that we check only for this and subsequent inputs
4806 and the address of only subsequent inputs and we do not need
4807 to check for RELOAD_OTHER objects since they are known not to
4810 for (i = opnum; i < reload_n_operands; i++)
4811 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4814 for (i = opnum + 1; i < reload_n_operands; i++)
4815 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4816 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4819 for (i = 0; i < reload_n_operands; i++)
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4825 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4828 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4829 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4830 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4832 case RELOAD_FOR_INPUT:
4833 /* Similar to input address, except we start at the next operand for
4834 both input and input address and we do not check for
4835 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4838 for (i = opnum + 1; i < reload_n_operands; i++)
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4841 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4844 /* ... fall through ... */
4846 case RELOAD_FOR_OPERAND_ADDRESS:
4847 /* Check outputs and their addresses. */
4849 for (i = 0; i < reload_n_operands; i++)
4850 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4851 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4852 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4855 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4857 case RELOAD_FOR_OPADDR_ADDR:
4858 for (i = 0; i < reload_n_operands; i++)
4859 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4860 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4861 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4864 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4865 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4866 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4868 case RELOAD_FOR_INSN:
4869 /* These conflict with other outputs with RELOAD_OTHER. So
4870 we need only check for output addresses. */
4872 opnum = reload_n_operands;
4874 /* ... fall through ... */
4876 case RELOAD_FOR_OUTPUT:
4877 case RELOAD_FOR_OUTPUT_ADDRESS:
4878 case RELOAD_FOR_OUTADDR_ADDRESS:
4879 /* We already know these can't conflict with a later output. So the
4880 only thing to check are later output addresses.
4881 Note that multiple output operands are emitted in reverse order,
4882 so the conflicting ones are those with lower indices. */
4883 for (i = 0; i < opnum; i++)
4884 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4885 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4896 /* Returns whether R1 and R2 are uniquely chained: the value of one
4897 is used by the other, and that value is not used by any other
4898 reload for this insn. This is used to partially undo the decision
4899 made in find_reloads when in the case of multiple
4900 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4901 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4902 reloads. This code tries to avoid the conflict created by that
4903 change. It might be cleaner to explicitly keep track of which
4904 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4905 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4906 this after the fact. */
4908 reloads_unique_chain_p (int r1, int r2)
4912 /* We only check input reloads. */
4913 if (! rld[r1].in || ! rld[r2].in)
4916 /* Avoid anything with output reloads. */
4917 if (rld[r1].out || rld[r2].out)
4920 /* "chained" means one reload is a component of the other reload,
4921 not the same as the other reload. */
4922 if (rld[r1].opnum != rld[r2].opnum
4923 || rtx_equal_p (rld[r1].in, rld[r2].in)
4924 || rld[r1].optional || rld[r2].optional
4925 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4926 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4929 for (i = 0; i < n_reloads; i ++)
4930 /* Look for input reloads that aren't our two */
4931 if (i != r1 && i != r2 && rld[i].in)
4933 /* If our reload is mentioned at all, it isn't a simple chain. */
4934 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4940 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4943 This function uses the same algorithm as reload_reg_free_p above. */
4946 reloads_conflict (int r1, int r2)
4948 enum reload_type r1_type = rld[r1].when_needed;
4949 enum reload_type r2_type = rld[r2].when_needed;
4950 int r1_opnum = rld[r1].opnum;
4951 int r2_opnum = rld[r2].opnum;
4953 /* RELOAD_OTHER conflicts with everything. */
4954 if (r2_type == RELOAD_OTHER)
4957 /* Otherwise, check conflicts differently for each type. */
4961 case RELOAD_FOR_INPUT:
4962 return (r2_type == RELOAD_FOR_INSN
4963 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4964 || r2_type == RELOAD_FOR_OPADDR_ADDR
4965 || r2_type == RELOAD_FOR_INPUT
4966 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4967 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4968 && r2_opnum > r1_opnum));
4970 case RELOAD_FOR_INPUT_ADDRESS:
4971 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4972 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4974 case RELOAD_FOR_INPADDR_ADDRESS:
4975 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4976 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4978 case RELOAD_FOR_OUTPUT_ADDRESS:
4979 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4980 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4982 case RELOAD_FOR_OUTADDR_ADDRESS:
4983 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4984 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4986 case RELOAD_FOR_OPERAND_ADDRESS:
4987 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4988 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
4989 && !reloads_unique_chain_p (r1, r2)));
4991 case RELOAD_FOR_OPADDR_ADDR:
4992 return (r2_type == RELOAD_FOR_INPUT
4993 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4995 case RELOAD_FOR_OUTPUT:
4996 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4997 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4998 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4999 && r2_opnum >= r1_opnum));
5001 case RELOAD_FOR_INSN:
5002 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5003 || r2_type == RELOAD_FOR_INSN
5004 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5006 case RELOAD_FOR_OTHER_ADDRESS:
5007 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5017 /* Indexed by reload number, 1 if incoming value
5018 inherited from previous insns. */
5019 static char reload_inherited[MAX_RELOADS];
5021 /* For an inherited reload, this is the insn the reload was inherited from,
5022 if we know it. Otherwise, this is 0. */
5023 static rtx reload_inheritance_insn[MAX_RELOADS];
5025 /* If nonzero, this is a place to get the value of the reload,
5026 rather than using reload_in. */
5027 static rtx reload_override_in[MAX_RELOADS];
5029 /* For each reload, the hard register number of the register used,
5030 or -1 if we did not need a register for this reload. */
5031 static int reload_spill_index[MAX_RELOADS];
5033 /* Subroutine of free_for_value_p, used to check a single register.
5034 START_REGNO is the starting regno of the full reload register
5035 (possibly comprising multiple hard registers) that we are considering. */
5038 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5039 enum reload_type type, rtx value, rtx out,
5040 int reloadnum, int ignore_address_reloads)
5043 /* Set if we see an input reload that must not share its reload register
5044 with any new earlyclobber, but might otherwise share the reload
5045 register with an output or input-output reload. */
5046 int check_earlyclobber = 0;
5050 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5053 if (out == const0_rtx)
5059 /* We use some pseudo 'time' value to check if the lifetimes of the
5060 new register use would overlap with the one of a previous reload
5061 that is not read-only or uses a different value.
5062 The 'time' used doesn't have to be linear in any shape or form, just
5064 Some reload types use different 'buckets' for each operand.
5065 So there are MAX_RECOG_OPERANDS different time values for each
5067 We compute TIME1 as the time when the register for the prospective
5068 new reload ceases to be live, and TIME2 for each existing
5069 reload as the time when that the reload register of that reload
5071 Where there is little to be gained by exact lifetime calculations,
5072 we just make conservative assumptions, i.e. a longer lifetime;
5073 this is done in the 'default:' cases. */
5076 case RELOAD_FOR_OTHER_ADDRESS:
5077 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5078 time1 = copy ? 0 : 1;
5081 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5083 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5084 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5085 respectively, to the time values for these, we get distinct time
5086 values. To get distinct time values for each operand, we have to
5087 multiply opnum by at least three. We round that up to four because
5088 multiply by four is often cheaper. */
5089 case RELOAD_FOR_INPADDR_ADDRESS:
5090 time1 = opnum * 4 + 2;
5092 case RELOAD_FOR_INPUT_ADDRESS:
5093 time1 = opnum * 4 + 3;
5095 case RELOAD_FOR_INPUT:
5096 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5097 executes (inclusive). */
5098 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5100 case RELOAD_FOR_OPADDR_ADDR:
5102 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5103 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5105 case RELOAD_FOR_OPERAND_ADDRESS:
5106 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5108 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5110 case RELOAD_FOR_OUTADDR_ADDRESS:
5111 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5113 case RELOAD_FOR_OUTPUT_ADDRESS:
5114 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5117 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5120 for (i = 0; i < n_reloads; i++)
5122 rtx reg = rld[i].reg_rtx;
5123 if (reg && REG_P (reg)
5124 && ((unsigned) regno - true_regnum (reg)
5125 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5128 rtx other_input = rld[i].in;
5130 /* If the other reload loads the same input value, that
5131 will not cause a conflict only if it's loading it into
5132 the same register. */
5133 if (true_regnum (reg) != start_regno)
5134 other_input = NULL_RTX;
5135 if (! other_input || ! rtx_equal_p (other_input, value)
5136 || rld[i].out || out)
5139 switch (rld[i].when_needed)
5141 case RELOAD_FOR_OTHER_ADDRESS:
5144 case RELOAD_FOR_INPADDR_ADDRESS:
5145 /* find_reloads makes sure that a
5146 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5147 by at most one - the first -
5148 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5149 address reload is inherited, the address address reload
5150 goes away, so we can ignore this conflict. */
5151 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5152 && ignore_address_reloads
5153 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5154 Then the address address is still needed to store
5155 back the new address. */
5156 && ! rld[reloadnum].out)
5158 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5159 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5161 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5162 && ignore_address_reloads
5163 /* Unless we are reloading an auto_inc expression. */
5164 && ! rld[reloadnum].out)
5166 time2 = rld[i].opnum * 4 + 2;
5168 case RELOAD_FOR_INPUT_ADDRESS:
5169 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5170 && ignore_address_reloads
5171 && ! rld[reloadnum].out)
5173 time2 = rld[i].opnum * 4 + 3;
5175 case RELOAD_FOR_INPUT:
5176 time2 = rld[i].opnum * 4 + 4;
5177 check_earlyclobber = 1;
5179 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5180 == MAX_RECOG_OPERAND * 4 */
5181 case RELOAD_FOR_OPADDR_ADDR:
5182 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5183 && ignore_address_reloads
5184 && ! rld[reloadnum].out)
5186 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5188 case RELOAD_FOR_OPERAND_ADDRESS:
5189 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5190 check_earlyclobber = 1;
5192 case RELOAD_FOR_INSN:
5193 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5195 case RELOAD_FOR_OUTPUT:
5196 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5197 instruction is executed. */
5198 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5200 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5201 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5203 case RELOAD_FOR_OUTADDR_ADDRESS:
5204 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5205 && ignore_address_reloads
5206 && ! rld[reloadnum].out)
5208 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5210 case RELOAD_FOR_OUTPUT_ADDRESS:
5211 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5214 /* If there is no conflict in the input part, handle this
5215 like an output reload. */
5216 if (! rld[i].in || rtx_equal_p (other_input, value))
5218 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5219 /* Earlyclobbered outputs must conflict with inputs. */
5220 if (earlyclobber_operand_p (rld[i].out))
5221 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5226 /* RELOAD_OTHER might be live beyond instruction execution,
5227 but this is not obvious when we set time2 = 1. So check
5228 here if there might be a problem with the new reload
5229 clobbering the register used by the RELOAD_OTHER. */
5237 && (! rld[i].in || rld[i].out
5238 || ! rtx_equal_p (other_input, value)))
5239 || (out && rld[reloadnum].out_reg
5240 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5246 /* Earlyclobbered outputs must conflict with inputs. */
5247 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5253 /* Return 1 if the value in reload reg REGNO, as used by a reload
5254 needed for the part of the insn specified by OPNUM and TYPE,
5255 may be used to load VALUE into it.
5257 MODE is the mode in which the register is used, this is needed to
5258 determine how many hard regs to test.
5260 Other read-only reloads with the same value do not conflict
5261 unless OUT is nonzero and these other reloads have to live while
5262 output reloads live.
5263 If OUT is CONST0_RTX, this is a special case: it means that the
5264 test should not be for using register REGNO as reload register, but
5265 for copying from register REGNO into the reload register.
5267 RELOADNUM is the number of the reload we want to load this value for;
5268 a reload does not conflict with itself.
5270 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5271 reloads that load an address for the very reload we are considering.
5273 The caller has to make sure that there is no conflict with the return
5277 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5278 enum reload_type type, rtx value, rtx out, int reloadnum,
5279 int ignore_address_reloads)
5281 int nregs = hard_regno_nregs[regno][mode];
5283 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5284 value, out, reloadnum,
5285 ignore_address_reloads))
5290 /* Return nonzero if the rtx X is invariant over the current function. */
5291 /* ??? Actually, the places where we use this expect exactly what is
5292 tested here, and not everything that is function invariant. In
5293 particular, the frame pointer and arg pointer are special cased;
5294 pic_offset_table_rtx is not, and we must not spill these things to
5298 function_invariant_p (rtx x)
5302 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5304 if (GET_CODE (x) == PLUS
5305 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5306 && CONSTANT_P (XEXP (x, 1)))
5311 /* Determine whether the reload reg X overlaps any rtx'es used for
5312 overriding inheritance. Return nonzero if so. */
5315 conflicts_with_override (rtx x)
5318 for (i = 0; i < n_reloads; i++)
5319 if (reload_override_in[i]
5320 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5325 /* Give an error message saying we failed to find a reload for INSN,
5326 and clear out reload R. */
5328 failed_reload (rtx insn, int r)
5330 if (asm_noperands (PATTERN (insn)) < 0)
5331 /* It's the compiler's fault. */
5332 fatal_insn ("could not find a spill register", insn);
5334 /* It's the user's fault; the operand's mode and constraint
5335 don't match. Disable this reload so we don't crash in final. */
5336 error_for_asm (insn,
5337 "%<asm%> operand constraint incompatible with operand size");
5341 rld[r].optional = 1;
5342 rld[r].secondary_p = 1;
5345 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5346 for reload R. If it's valid, get an rtx for it. Return nonzero if
5349 set_reload_reg (int i, int r)
5352 rtx reg = spill_reg_rtx[i];
5354 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5355 spill_reg_rtx[i] = reg
5356 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5358 regno = true_regnum (reg);
5360 /* Detect when the reload reg can't hold the reload mode.
5361 This used to be one `if', but Sequent compiler can't handle that. */
5362 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5364 enum machine_mode test_mode = VOIDmode;
5366 test_mode = GET_MODE (rld[r].in);
5367 /* If rld[r].in has VOIDmode, it means we will load it
5368 in whatever mode the reload reg has: to wit, rld[r].mode.
5369 We have already tested that for validity. */
5370 /* Aside from that, we need to test that the expressions
5371 to reload from or into have modes which are valid for this
5372 reload register. Otherwise the reload insns would be invalid. */
5373 if (! (rld[r].in != 0 && test_mode != VOIDmode
5374 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5375 if (! (rld[r].out != 0
5376 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5378 /* The reg is OK. */
5381 /* Mark as in use for this insn the reload regs we use
5383 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5384 rld[r].when_needed, rld[r].mode);
5386 rld[r].reg_rtx = reg;
5387 reload_spill_index[r] = spill_regs[i];
5394 /* Find a spill register to use as a reload register for reload R.
5395 LAST_RELOAD is nonzero if this is the last reload for the insn being
5398 Set rld[R].reg_rtx to the register allocated.
5400 We return 1 if successful, or 0 if we couldn't find a spill reg and
5401 we didn't change anything. */
5404 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5409 /* If we put this reload ahead, thinking it is a group,
5410 then insist on finding a group. Otherwise we can grab a
5411 reg that some other reload needs.
5412 (That can happen when we have a 68000 DATA_OR_FP_REG
5413 which is a group of data regs or one fp reg.)
5414 We need not be so restrictive if there are no more reloads
5417 ??? Really it would be nicer to have smarter handling
5418 for that kind of reg class, where a problem like this is normal.
5419 Perhaps those classes should be avoided for reloading
5420 by use of more alternatives. */
5422 int force_group = rld[r].nregs > 1 && ! last_reload;
5424 /* If we want a single register and haven't yet found one,
5425 take any reg in the right class and not in use.
5426 If we want a consecutive group, here is where we look for it.
5428 We use two passes so we can first look for reload regs to
5429 reuse, which are already in use for other reloads in this insn,
5430 and only then use additional registers.
5431 I think that maximizing reuse is needed to make sure we don't
5432 run out of reload regs. Suppose we have three reloads, and
5433 reloads A and B can share regs. These need two regs.
5434 Suppose A and B are given different regs.
5435 That leaves none for C. */
5436 for (pass = 0; pass < 2; pass++)
5438 /* I is the index in spill_regs.
5439 We advance it round-robin between insns to use all spill regs
5440 equally, so that inherited reloads have a chance
5441 of leapfrogging each other. */
5445 for (count = 0; count < n_spills; count++)
5447 int class = (int) rld[r].class;
5453 regnum = spill_regs[i];
5455 if ((reload_reg_free_p (regnum, rld[r].opnum,
5458 /* We check reload_reg_used to make sure we
5459 don't clobber the return register. */
5460 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5461 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5462 rld[r].when_needed, rld[r].in,
5464 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5465 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5466 /* Look first for regs to share, then for unshared. But
5467 don't share regs used for inherited reloads; they are
5468 the ones we want to preserve. */
5470 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5472 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5475 int nr = hard_regno_nregs[regnum][rld[r].mode];
5476 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5477 (on 68000) got us two FP regs. If NR is 1,
5478 we would reject both of them. */
5481 /* If we need only one reg, we have already won. */
5484 /* But reject a single reg if we demand a group. */
5489 /* Otherwise check that as many consecutive regs as we need
5490 are available here. */
5493 int regno = regnum + nr - 1;
5494 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5495 && spill_reg_order[regno] >= 0
5496 && reload_reg_free_p (regno, rld[r].opnum,
5497 rld[r].when_needed)))
5506 /* If we found something on pass 1, omit pass 2. */
5507 if (count < n_spills)
5511 /* We should have found a spill register by now. */
5512 if (count >= n_spills)
5515 /* I is the index in SPILL_REG_RTX of the reload register we are to
5516 allocate. Get an rtx for it and find its register number. */
5518 return set_reload_reg (i, r);
5521 /* Initialize all the tables needed to allocate reload registers.
5522 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5523 is the array we use to restore the reg_rtx field for every reload. */
5526 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5530 for (i = 0; i < n_reloads; i++)
5531 rld[i].reg_rtx = save_reload_reg_rtx[i];
5533 memset (reload_inherited, 0, MAX_RELOADS);
5534 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5535 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5537 CLEAR_HARD_REG_SET (reload_reg_used);
5538 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5539 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5540 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5541 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5542 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5544 CLEAR_HARD_REG_SET (reg_used_in_insn);
5547 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5548 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5549 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5550 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5551 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5552 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5555 for (i = 0; i < reload_n_operands; i++)
5557 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5558 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5559 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5560 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5561 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5562 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5565 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5567 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5569 for (i = 0; i < n_reloads; i++)
5570 /* If we have already decided to use a certain register,
5571 don't use it in another way. */
5573 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5574 rld[i].when_needed, rld[i].mode);
5577 /* Assign hard reg targets for the pseudo-registers we must reload
5578 into hard regs for this insn.
5579 Also output the instructions to copy them in and out of the hard regs.
5581 For machines with register classes, we are responsible for
5582 finding a reload reg in the proper class. */
5585 choose_reload_regs (struct insn_chain *chain)
5587 rtx insn = chain->insn;
5589 unsigned int max_group_size = 1;
5590 enum reg_class group_class = NO_REGS;
5591 int pass, win, inheritance;
5593 rtx save_reload_reg_rtx[MAX_RELOADS];
5595 /* In order to be certain of getting the registers we need,
5596 we must sort the reloads into order of increasing register class.
5597 Then our grabbing of reload registers will parallel the process
5598 that provided the reload registers.
5600 Also note whether any of the reloads wants a consecutive group of regs.
5601 If so, record the maximum size of the group desired and what
5602 register class contains all the groups needed by this insn. */
5604 for (j = 0; j < n_reloads; j++)
5606 reload_order[j] = j;
5607 reload_spill_index[j] = -1;
5609 if (rld[j].nregs > 1)
5611 max_group_size = MAX (rld[j].nregs, max_group_size);
5613 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5616 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5620 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5622 /* If -O, try first with inheritance, then turning it off.
5623 If not -O, don't do inheritance.
5624 Using inheritance when not optimizing leads to paradoxes
5625 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5626 because one side of the comparison might be inherited. */
5628 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5630 choose_reload_regs_init (chain, save_reload_reg_rtx);
5632 /* Process the reloads in order of preference just found.
5633 Beyond this point, subregs can be found in reload_reg_rtx.
5635 This used to look for an existing reloaded home for all of the
5636 reloads, and only then perform any new reloads. But that could lose
5637 if the reloads were done out of reg-class order because a later
5638 reload with a looser constraint might have an old home in a register
5639 needed by an earlier reload with a tighter constraint.
5641 To solve this, we make two passes over the reloads, in the order
5642 described above. In the first pass we try to inherit a reload
5643 from a previous insn. If there is a later reload that needs a
5644 class that is a proper subset of the class being processed, we must
5645 also allocate a spill register during the first pass.
5647 Then make a second pass over the reloads to allocate any reloads
5648 that haven't been given registers yet. */
5650 for (j = 0; j < n_reloads; j++)
5652 int r = reload_order[j];
5653 rtx search_equiv = NULL_RTX;
5655 /* Ignore reloads that got marked inoperative. */
5656 if (rld[r].out == 0 && rld[r].in == 0
5657 && ! rld[r].secondary_p)
5660 /* If find_reloads chose to use reload_in or reload_out as a reload
5661 register, we don't need to chose one. Otherwise, try even if it
5662 found one since we might save an insn if we find the value lying
5664 Try also when reload_in is a pseudo without a hard reg. */
5665 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5666 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5667 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5668 && !MEM_P (rld[r].in)
5669 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5672 #if 0 /* No longer needed for correct operation.
5673 It might give better code, or might not; worth an experiment? */
5674 /* If this is an optional reload, we can't inherit from earlier insns
5675 until we are sure that any non-optional reloads have been allocated.
5676 The following code takes advantage of the fact that optional reloads
5677 are at the end of reload_order. */
5678 if (rld[r].optional != 0)
5679 for (i = 0; i < j; i++)
5680 if ((rld[reload_order[i]].out != 0
5681 || rld[reload_order[i]].in != 0
5682 || rld[reload_order[i]].secondary_p)
5683 && ! rld[reload_order[i]].optional
5684 && rld[reload_order[i]].reg_rtx == 0)
5685 allocate_reload_reg (chain, reload_order[i], 0);
5688 /* First see if this pseudo is already available as reloaded
5689 for a previous insn. We cannot try to inherit for reloads
5690 that are smaller than the maximum number of registers needed
5691 for groups unless the register we would allocate cannot be used
5694 We could check here to see if this is a secondary reload for
5695 an object that is already in a register of the desired class.
5696 This would avoid the need for the secondary reload register.
5697 But this is complex because we can't easily determine what
5698 objects might want to be loaded via this reload. So let a
5699 register be allocated here. In `emit_reload_insns' we suppress
5700 one of the loads in the case described above. */
5706 enum machine_mode mode = VOIDmode;
5710 else if (REG_P (rld[r].in))
5712 regno = REGNO (rld[r].in);
5713 mode = GET_MODE (rld[r].in);
5715 else if (REG_P (rld[r].in_reg))
5717 regno = REGNO (rld[r].in_reg);
5718 mode = GET_MODE (rld[r].in_reg);
5720 else if (GET_CODE (rld[r].in_reg) == SUBREG
5721 && REG_P (SUBREG_REG (rld[r].in_reg)))
5723 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5724 if (regno < FIRST_PSEUDO_REGISTER)
5725 regno = subreg_regno (rld[r].in_reg);
5727 byte = SUBREG_BYTE (rld[r].in_reg);
5728 mode = GET_MODE (rld[r].in_reg);
5731 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5732 && REG_P (XEXP (rld[r].in_reg, 0)))
5734 regno = REGNO (XEXP (rld[r].in_reg, 0));
5735 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5736 rld[r].out = rld[r].in;
5740 /* This won't work, since REGNO can be a pseudo reg number.
5741 Also, it takes much more hair to keep track of all the things
5742 that can invalidate an inherited reload of part of a pseudoreg. */
5743 else if (GET_CODE (rld[r].in) == SUBREG
5744 && REG_P (SUBREG_REG (rld[r].in)))
5745 regno = subreg_regno (rld[r].in);
5749 && reg_last_reload_reg[regno] != 0
5750 #ifdef CANNOT_CHANGE_MODE_CLASS
5751 /* Verify that the register it's in can be used in
5753 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5754 GET_MODE (reg_last_reload_reg[regno]),
5759 enum reg_class class = rld[r].class, last_class;
5760 rtx last_reg = reg_last_reload_reg[regno];
5761 enum machine_mode need_mode;
5763 i = REGNO (last_reg);
5764 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5765 last_class = REGNO_REG_CLASS (i);
5771 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5772 + byte * BITS_PER_UNIT,
5773 GET_MODE_CLASS (mode));
5775 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5776 >= GET_MODE_SIZE (need_mode))
5777 && reg_reloaded_contents[i] == regno
5778 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5779 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5780 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5781 /* Even if we can't use this register as a reload
5782 register, we might use it for reload_override_in,
5783 if copying it to the desired class is cheap
5785 || ((REGISTER_MOVE_COST (mode, last_class, class)
5786 < MEMORY_MOVE_COST (mode, class, 1))
5787 && (secondary_reload_class (1, class, mode,
5790 #ifdef SECONDARY_MEMORY_NEEDED
5791 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5796 && (rld[r].nregs == max_group_size
5797 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5799 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5800 rld[r].when_needed, rld[r].in,
5803 /* If a group is needed, verify that all the subsequent
5804 registers still have their values intact. */
5805 int nr = hard_regno_nregs[i][rld[r].mode];
5808 for (k = 1; k < nr; k++)
5809 if (reg_reloaded_contents[i + k] != regno
5810 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5818 last_reg = (GET_MODE (last_reg) == mode
5819 ? last_reg : gen_rtx_REG (mode, i));
5822 for (k = 0; k < nr; k++)
5823 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5826 /* We found a register that contains the
5827 value we need. If this register is the
5828 same as an `earlyclobber' operand of the
5829 current insn, just mark it as a place to
5830 reload from since we can't use it as the
5831 reload register itself. */
5833 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5834 if (reg_overlap_mentioned_for_reload_p
5835 (reg_last_reload_reg[regno],
5836 reload_earlyclobbers[i1]))
5839 if (i1 != n_earlyclobbers
5840 || ! (free_for_value_p (i, rld[r].mode,
5842 rld[r].when_needed, rld[r].in,
5844 /* Don't use it if we'd clobber a pseudo reg. */
5845 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5847 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5848 /* Don't clobber the frame pointer. */
5849 || (i == HARD_FRAME_POINTER_REGNUM
5850 && frame_pointer_needed
5852 /* Don't really use the inherited spill reg
5853 if we need it wider than we've got it. */
5854 || (GET_MODE_SIZE (rld[r].mode)
5855 > GET_MODE_SIZE (mode))
5858 /* If find_reloads chose reload_out as reload
5859 register, stay with it - that leaves the
5860 inherited register for subsequent reloads. */
5861 || (rld[r].out && rld[r].reg_rtx
5862 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5864 if (! rld[r].optional)
5866 reload_override_in[r] = last_reg;
5867 reload_inheritance_insn[r]
5868 = reg_reloaded_insn[i];
5874 /* We can use this as a reload reg. */
5875 /* Mark the register as in use for this part of
5877 mark_reload_reg_in_use (i,
5881 rld[r].reg_rtx = last_reg;
5882 reload_inherited[r] = 1;
5883 reload_inheritance_insn[r]
5884 = reg_reloaded_insn[i];
5885 reload_spill_index[r] = i;
5886 for (k = 0; k < nr; k++)
5887 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5895 /* Here's another way to see if the value is already lying around. */
5898 && ! reload_inherited[r]
5900 && (CONSTANT_P (rld[r].in)
5901 || GET_CODE (rld[r].in) == PLUS
5902 || REG_P (rld[r].in)
5903 || MEM_P (rld[r].in))
5904 && (rld[r].nregs == max_group_size
5905 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5906 search_equiv = rld[r].in;
5907 /* If this is an output reload from a simple move insn, look
5908 if an equivalence for the input is available. */
5909 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5911 rtx set = single_set (insn);
5914 && rtx_equal_p (rld[r].out, SET_DEST (set))
5915 && CONSTANT_P (SET_SRC (set)))
5916 search_equiv = SET_SRC (set);
5922 = find_equiv_reg (search_equiv, insn, rld[r].class,
5923 -1, NULL, 0, rld[r].mode);
5929 regno = REGNO (equiv);
5932 /* This must be a SUBREG of a hard register.
5933 Make a new REG since this might be used in an
5934 address and not all machines support SUBREGs
5936 gcc_assert (GET_CODE (equiv) == SUBREG);
5937 regno = subreg_regno (equiv);
5938 equiv = gen_rtx_REG (rld[r].mode, regno);
5939 /* If we choose EQUIV as the reload register, but the
5940 loop below decides to cancel the inheritance, we'll
5941 end up reloading EQUIV in rld[r].mode, not the mode
5942 it had originally. That isn't safe when EQUIV isn't
5943 available as a spill register since its value might
5944 still be live at this point. */
5945 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5946 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5951 /* If we found a spill reg, reject it unless it is free
5952 and of the desired class. */
5956 int bad_for_class = 0;
5957 int max_regno = regno + rld[r].nregs;
5959 for (i = regno; i < max_regno; i++)
5961 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5963 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5968 && ! free_for_value_p (regno, rld[r].mode,
5969 rld[r].opnum, rld[r].when_needed,
5970 rld[r].in, rld[r].out, r, 1))
5975 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5978 /* We found a register that contains the value we need.
5979 If this register is the same as an `earlyclobber' operand
5980 of the current insn, just mark it as a place to reload from
5981 since we can't use it as the reload register itself. */
5984 for (i = 0; i < n_earlyclobbers; i++)
5985 if (reg_overlap_mentioned_for_reload_p (equiv,
5986 reload_earlyclobbers[i]))
5988 if (! rld[r].optional)
5989 reload_override_in[r] = equiv;
5994 /* If the equiv register we have found is explicitly clobbered
5995 in the current insn, it depends on the reload type if we
5996 can use it, use it for reload_override_in, or not at all.
5997 In particular, we then can't use EQUIV for a
5998 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6002 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6003 switch (rld[r].when_needed)
6005 case RELOAD_FOR_OTHER_ADDRESS:
6006 case RELOAD_FOR_INPADDR_ADDRESS:
6007 case RELOAD_FOR_INPUT_ADDRESS:
6008 case RELOAD_FOR_OPADDR_ADDR:
6011 case RELOAD_FOR_INPUT:
6012 case RELOAD_FOR_OPERAND_ADDRESS:
6013 if (! rld[r].optional)
6014 reload_override_in[r] = equiv;
6020 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6021 switch (rld[r].when_needed)
6023 case RELOAD_FOR_OTHER_ADDRESS:
6024 case RELOAD_FOR_INPADDR_ADDRESS:
6025 case RELOAD_FOR_INPUT_ADDRESS:
6026 case RELOAD_FOR_OPADDR_ADDR:
6027 case RELOAD_FOR_OPERAND_ADDRESS:
6028 case RELOAD_FOR_INPUT:
6031 if (! rld[r].optional)
6032 reload_override_in[r] = equiv;
6040 /* If we found an equivalent reg, say no code need be generated
6041 to load it, and use it as our reload reg. */
6043 && (regno != HARD_FRAME_POINTER_REGNUM
6044 || !frame_pointer_needed))
6046 int nr = hard_regno_nregs[regno][rld[r].mode];
6048 rld[r].reg_rtx = equiv;
6049 reload_inherited[r] = 1;
6051 /* If reg_reloaded_valid is not set for this register,
6052 there might be a stale spill_reg_store lying around.
6053 We must clear it, since otherwise emit_reload_insns
6054 might delete the store. */
6055 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6056 spill_reg_store[regno] = NULL_RTX;
6057 /* If any of the hard registers in EQUIV are spill
6058 registers, mark them as in use for this insn. */
6059 for (k = 0; k < nr; k++)
6061 i = spill_reg_order[regno + k];
6064 mark_reload_reg_in_use (regno, rld[r].opnum,
6067 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6074 /* If we found a register to use already, or if this is an optional
6075 reload, we are done. */
6076 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6080 /* No longer needed for correct operation. Might or might
6081 not give better code on the average. Want to experiment? */
6083 /* See if there is a later reload that has a class different from our
6084 class that intersects our class or that requires less register
6085 than our reload. If so, we must allocate a register to this
6086 reload now, since that reload might inherit a previous reload
6087 and take the only available register in our class. Don't do this
6088 for optional reloads since they will force all previous reloads
6089 to be allocated. Also don't do this for reloads that have been
6092 for (i = j + 1; i < n_reloads; i++)
6094 int s = reload_order[i];
6096 if ((rld[s].in == 0 && rld[s].out == 0
6097 && ! rld[s].secondary_p)
6101 if ((rld[s].class != rld[r].class
6102 && reg_classes_intersect_p (rld[r].class,
6104 || rld[s].nregs < rld[r].nregs)
6111 allocate_reload_reg (chain, r, j == n_reloads - 1);
6115 /* Now allocate reload registers for anything non-optional that
6116 didn't get one yet. */
6117 for (j = 0; j < n_reloads; j++)
6119 int r = reload_order[j];
6121 /* Ignore reloads that got marked inoperative. */
6122 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6125 /* Skip reloads that already have a register allocated or are
6127 if (rld[r].reg_rtx != 0 || rld[r].optional)
6130 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6134 /* If that loop got all the way, we have won. */
6141 /* Loop around and try without any inheritance. */
6146 /* First undo everything done by the failed attempt
6147 to allocate with inheritance. */
6148 choose_reload_regs_init (chain, save_reload_reg_rtx);
6150 /* Some sanity tests to verify that the reloads found in the first
6151 pass are identical to the ones we have now. */
6152 gcc_assert (chain->n_reloads == n_reloads);
6154 for (i = 0; i < n_reloads; i++)
6156 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6158 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6159 for (j = 0; j < n_spills; j++)
6160 if (spill_regs[j] == chain->rld[i].regno)
6161 if (! set_reload_reg (j, i))
6162 failed_reload (chain->insn, i);
6166 /* If we thought we could inherit a reload, because it seemed that
6167 nothing else wanted the same reload register earlier in the insn,
6168 verify that assumption, now that all reloads have been assigned.
6169 Likewise for reloads where reload_override_in has been set. */
6171 /* If doing expensive optimizations, do one preliminary pass that doesn't
6172 cancel any inheritance, but removes reloads that have been needed only
6173 for reloads that we know can be inherited. */
6174 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6176 for (j = 0; j < n_reloads; j++)
6178 int r = reload_order[j];
6180 if (reload_inherited[r] && rld[r].reg_rtx)
6181 check_reg = rld[r].reg_rtx;
6182 else if (reload_override_in[r]
6183 && (REG_P (reload_override_in[r])
6184 || GET_CODE (reload_override_in[r]) == SUBREG))
6185 check_reg = reload_override_in[r];
6188 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6189 rld[r].opnum, rld[r].when_needed, rld[r].in,
6190 (reload_inherited[r]
6191 ? rld[r].out : const0_rtx),
6196 reload_inherited[r] = 0;
6197 reload_override_in[r] = 0;
6199 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6200 reload_override_in, then we do not need its related
6201 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6202 likewise for other reload types.
6203 We handle this by removing a reload when its only replacement
6204 is mentioned in reload_in of the reload we are going to inherit.
6205 A special case are auto_inc expressions; even if the input is
6206 inherited, we still need the address for the output. We can
6207 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6208 If we succeeded removing some reload and we are doing a preliminary
6209 pass just to remove such reloads, make another pass, since the
6210 removal of one reload might allow us to inherit another one. */
6212 && rld[r].out != rld[r].in
6213 && remove_address_replacements (rld[r].in) && pass)
6218 /* Now that reload_override_in is known valid,
6219 actually override reload_in. */
6220 for (j = 0; j < n_reloads; j++)
6221 if (reload_override_in[j])
6222 rld[j].in = reload_override_in[j];
6224 /* If this reload won't be done because it has been canceled or is
6225 optional and not inherited, clear reload_reg_rtx so other
6226 routines (such as subst_reloads) don't get confused. */
6227 for (j = 0; j < n_reloads; j++)
6228 if (rld[j].reg_rtx != 0
6229 && ((rld[j].optional && ! reload_inherited[j])
6230 || (rld[j].in == 0 && rld[j].out == 0
6231 && ! rld[j].secondary_p)))
6233 int regno = true_regnum (rld[j].reg_rtx);
6235 if (spill_reg_order[regno] >= 0)
6236 clear_reload_reg_in_use (regno, rld[j].opnum,
6237 rld[j].when_needed, rld[j].mode);
6239 reload_spill_index[j] = -1;
6242 /* Record which pseudos and which spill regs have output reloads. */
6243 for (j = 0; j < n_reloads; j++)
6245 int r = reload_order[j];
6247 i = reload_spill_index[r];
6249 /* I is nonneg if this reload uses a register.
6250 If rld[r].reg_rtx is 0, this is an optional reload
6251 that we opted to ignore. */
6252 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6253 && rld[r].reg_rtx != 0)
6255 int nregno = REGNO (rld[r].out_reg);
6258 if (nregno < FIRST_PSEUDO_REGISTER)
6259 nr = hard_regno_nregs[nregno][rld[r].mode];
6262 SET_REGNO_REG_SET (®_has_output_reload,
6267 nr = hard_regno_nregs[i][rld[r].mode];
6269 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6272 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6273 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6274 || rld[r].when_needed == RELOAD_FOR_INSN);
6279 /* Deallocate the reload register for reload R. This is called from
6280 remove_address_replacements. */
6283 deallocate_reload_reg (int r)
6287 if (! rld[r].reg_rtx)
6289 regno = true_regnum (rld[r].reg_rtx);
6291 if (spill_reg_order[regno] >= 0)
6292 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6294 reload_spill_index[r] = -1;
6297 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6298 reloads of the same item for fear that we might not have enough reload
6299 registers. However, normally they will get the same reload register
6300 and hence actually need not be loaded twice.
6302 Here we check for the most common case of this phenomenon: when we have
6303 a number of reloads for the same object, each of which were allocated
6304 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6305 reload, and is not modified in the insn itself. If we find such,
6306 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6307 This will not increase the number of spill registers needed and will
6308 prevent redundant code. */
6311 merge_assigned_reloads (rtx insn)
6315 /* Scan all the reloads looking for ones that only load values and
6316 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6317 assigned and not modified by INSN. */
6319 for (i = 0; i < n_reloads; i++)
6321 int conflicting_input = 0;
6322 int max_input_address_opnum = -1;
6323 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6325 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6326 || rld[i].out != 0 || rld[i].reg_rtx == 0
6327 || reg_set_p (rld[i].reg_rtx, insn))
6330 /* Look at all other reloads. Ensure that the only use of this
6331 reload_reg_rtx is in a reload that just loads the same value
6332 as we do. Note that any secondary reloads must be of the identical
6333 class since the values, modes, and result registers are the
6334 same, so we need not do anything with any secondary reloads. */
6336 for (j = 0; j < n_reloads; j++)
6338 if (i == j || rld[j].reg_rtx == 0
6339 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6343 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6344 && rld[j].opnum > max_input_address_opnum)
6345 max_input_address_opnum = rld[j].opnum;
6347 /* If the reload regs aren't exactly the same (e.g, different modes)
6348 or if the values are different, we can't merge this reload.
6349 But if it is an input reload, we might still merge
6350 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6352 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6353 || rld[j].out != 0 || rld[j].in == 0
6354 || ! rtx_equal_p (rld[i].in, rld[j].in))
6356 if (rld[j].when_needed != RELOAD_FOR_INPUT
6357 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6358 || rld[i].opnum > rld[j].opnum)
6359 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6361 conflicting_input = 1;
6362 if (min_conflicting_input_opnum > rld[j].opnum)
6363 min_conflicting_input_opnum = rld[j].opnum;
6367 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6368 we, in fact, found any matching reloads. */
6371 && max_input_address_opnum <= min_conflicting_input_opnum)
6373 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6375 for (j = 0; j < n_reloads; j++)
6376 if (i != j && rld[j].reg_rtx != 0
6377 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6378 && (! conflicting_input
6379 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6380 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6382 rld[i].when_needed = RELOAD_OTHER;
6384 reload_spill_index[j] = -1;
6385 transfer_replacements (i, j);
6388 /* If this is now RELOAD_OTHER, look for any reloads that
6389 load parts of this operand and set them to
6390 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6391 RELOAD_OTHER for outputs. Note that this test is
6392 equivalent to looking for reloads for this operand
6395 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6396 it may share registers with a RELOAD_FOR_INPUT, so we can
6397 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6398 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6400 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6401 instruction is assigned the same register as the earlier
6402 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6403 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6404 instruction to be deleted later on. */
6406 if (rld[i].when_needed == RELOAD_OTHER)
6407 for (j = 0; j < n_reloads; j++)
6409 && rld[j].when_needed != RELOAD_OTHER
6410 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6411 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6412 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6413 && (! conflicting_input
6414 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6415 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6416 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6422 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6423 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6424 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6426 /* Check to see if we accidentally converted two
6427 reloads that use the same reload register with
6428 different inputs to the same type. If so, the
6429 resulting code won't work. */
6431 for (k = 0; k < j; k++)
6432 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6433 || rld[k].when_needed != rld[j].when_needed
6434 || !rtx_equal_p (rld[k].reg_rtx,
6436 || rtx_equal_p (rld[k].in,
6443 /* These arrays are filled by emit_reload_insns and its subroutines. */
6444 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6445 static rtx other_input_address_reload_insns = 0;
6446 static rtx other_input_reload_insns = 0;
6447 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6448 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6449 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6450 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6451 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6452 static rtx operand_reload_insns = 0;
6453 static rtx other_operand_reload_insns = 0;
6454 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6456 /* Values to be put in spill_reg_store are put here first. */
6457 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6458 static HARD_REG_SET reg_reloaded_died;
6460 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6461 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6462 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6463 adjusted register, and return true. Otherwise, return false. */
6465 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6466 enum reg_class new_class,
6467 enum machine_mode new_mode)
6472 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6474 unsigned regno = REGNO (reg);
6476 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6478 if (GET_MODE (reg) != new_mode)
6480 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6482 if (hard_regno_nregs[regno][new_mode]
6483 > hard_regno_nregs[regno][GET_MODE (reg)])
6485 reg = reload_adjust_reg_for_mode (reg, new_mode);
6493 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6494 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6495 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6496 adjusted register, and return true. Otherwise, return false. */
6498 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6499 enum insn_code icode)
6502 enum reg_class new_class = scratch_reload_class (icode);
6503 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6505 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6506 new_class, new_mode);
6509 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6510 has the number J. OLD contains the value to be used as input. */
6513 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6516 rtx insn = chain->insn;
6517 rtx reloadreg = rl->reg_rtx;
6518 rtx oldequiv_reg = 0;
6521 enum machine_mode mode;
6524 /* Determine the mode to reload in.
6525 This is very tricky because we have three to choose from.
6526 There is the mode the insn operand wants (rl->inmode).
6527 There is the mode of the reload register RELOADREG.
6528 There is the intrinsic mode of the operand, which we could find
6529 by stripping some SUBREGs.
6530 It turns out that RELOADREG's mode is irrelevant:
6531 we can change that arbitrarily.
6533 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6534 then the reload reg may not support QImode moves, so use SImode.
6535 If foo is in memory due to spilling a pseudo reg, this is safe,
6536 because the QImode value is in the least significant part of a
6537 slot big enough for a SImode. If foo is some other sort of
6538 memory reference, then it is impossible to reload this case,
6539 so previous passes had better make sure this never happens.
6541 Then consider a one-word union which has SImode and one of its
6542 members is a float, being fetched as (SUBREG:SF union:SI).
6543 We must fetch that as SFmode because we could be loading into
6544 a float-only register. In this case OLD's mode is correct.
6546 Consider an immediate integer: it has VOIDmode. Here we need
6547 to get a mode from something else.
6549 In some cases, there is a fourth mode, the operand's
6550 containing mode. If the insn specifies a containing mode for
6551 this operand, it overrides all others.
6553 I am not sure whether the algorithm here is always right,
6554 but it does the right things in those cases. */
6556 mode = GET_MODE (old);
6557 if (mode == VOIDmode)
6560 /* delete_output_reload is only invoked properly if old contains
6561 the original pseudo register. Since this is replaced with a
6562 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6563 find the pseudo in RELOAD_IN_REG. */
6564 if (reload_override_in[j]
6565 && REG_P (rl->in_reg))
6572 else if (REG_P (oldequiv))
6573 oldequiv_reg = oldequiv;
6574 else if (GET_CODE (oldequiv) == SUBREG)
6575 oldequiv_reg = SUBREG_REG (oldequiv);
6577 /* If we are reloading from a register that was recently stored in
6578 with an output-reload, see if we can prove there was
6579 actually no need to store the old value in it. */
6581 if (optimize && REG_P (oldequiv)
6582 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6583 && spill_reg_store[REGNO (oldequiv)]
6585 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6586 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6588 delete_output_reload (insn, j, REGNO (oldequiv));
6590 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6591 then load RELOADREG from OLDEQUIV. Note that we cannot use
6592 gen_lowpart_common since it can do the wrong thing when
6593 RELOADREG has a multi-word mode. Note that RELOADREG
6594 must always be a REG here. */
6596 if (GET_MODE (reloadreg) != mode)
6597 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6598 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6599 oldequiv = SUBREG_REG (oldequiv);
6600 if (GET_MODE (oldequiv) != VOIDmode
6601 && mode != GET_MODE (oldequiv))
6602 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6604 /* Switch to the right place to emit the reload insns. */
6605 switch (rl->when_needed)
6608 where = &other_input_reload_insns;
6610 case RELOAD_FOR_INPUT:
6611 where = &input_reload_insns[rl->opnum];
6613 case RELOAD_FOR_INPUT_ADDRESS:
6614 where = &input_address_reload_insns[rl->opnum];
6616 case RELOAD_FOR_INPADDR_ADDRESS:
6617 where = &inpaddr_address_reload_insns[rl->opnum];
6619 case RELOAD_FOR_OUTPUT_ADDRESS:
6620 where = &output_address_reload_insns[rl->opnum];
6622 case RELOAD_FOR_OUTADDR_ADDRESS:
6623 where = &outaddr_address_reload_insns[rl->opnum];
6625 case RELOAD_FOR_OPERAND_ADDRESS:
6626 where = &operand_reload_insns;
6628 case RELOAD_FOR_OPADDR_ADDR:
6629 where = &other_operand_reload_insns;
6631 case RELOAD_FOR_OTHER_ADDRESS:
6632 where = &other_input_address_reload_insns;
6638 push_to_sequence (*where);
6640 /* Auto-increment addresses must be reloaded in a special way. */
6641 if (rl->out && ! rl->out_reg)
6643 /* We are not going to bother supporting the case where a
6644 incremented register can't be copied directly from
6645 OLDEQUIV since this seems highly unlikely. */
6646 gcc_assert (rl->secondary_in_reload < 0);
6648 if (reload_inherited[j])
6649 oldequiv = reloadreg;
6651 old = XEXP (rl->in_reg, 0);
6653 if (optimize && REG_P (oldequiv)
6654 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6655 && spill_reg_store[REGNO (oldequiv)]
6657 && (dead_or_set_p (insn,
6658 spill_reg_stored_to[REGNO (oldequiv)])
6659 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6661 delete_output_reload (insn, j, REGNO (oldequiv));
6663 /* Prevent normal processing of this reload. */
6665 /* Output a special code sequence for this case. */
6666 new_spill_reg_store[REGNO (reloadreg)]
6667 = inc_for_reload (reloadreg, oldequiv, rl->out,
6671 /* If we are reloading a pseudo-register that was set by the previous
6672 insn, see if we can get rid of that pseudo-register entirely
6673 by redirecting the previous insn into our reload register. */
6675 else if (optimize && REG_P (old)
6676 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6677 && dead_or_set_p (insn, old)
6678 /* This is unsafe if some other reload
6679 uses the same reg first. */
6680 && ! conflicts_with_override (reloadreg)
6681 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6682 rl->when_needed, old, rl->out, j, 0))
6684 rtx temp = PREV_INSN (insn);
6685 while (temp && NOTE_P (temp))
6686 temp = PREV_INSN (temp);
6688 && NONJUMP_INSN_P (temp)
6689 && GET_CODE (PATTERN (temp)) == SET
6690 && SET_DEST (PATTERN (temp)) == old
6691 /* Make sure we can access insn_operand_constraint. */
6692 && asm_noperands (PATTERN (temp)) < 0
6693 /* This is unsafe if operand occurs more than once in current
6694 insn. Perhaps some occurrences aren't reloaded. */
6695 && count_occurrences (PATTERN (insn), old, 0) == 1)
6697 rtx old = SET_DEST (PATTERN (temp));
6698 /* Store into the reload register instead of the pseudo. */
6699 SET_DEST (PATTERN (temp)) = reloadreg;
6701 /* Verify that resulting insn is valid. */
6702 extract_insn (temp);
6703 if (constrain_operands (1))
6705 /* If the previous insn is an output reload, the source is
6706 a reload register, and its spill_reg_store entry will
6707 contain the previous destination. This is now
6709 if (REG_P (SET_SRC (PATTERN (temp)))
6710 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6712 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6713 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6716 /* If these are the only uses of the pseudo reg,
6717 pretend for GDB it lives in the reload reg we used. */
6718 if (REG_N_DEATHS (REGNO (old)) == 1
6719 && REG_N_SETS (REGNO (old)) == 1)
6721 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6722 alter_reg (REGNO (old), -1);
6728 SET_DEST (PATTERN (temp)) = old;
6733 /* We can't do that, so output an insn to load RELOADREG. */
6735 /* If we have a secondary reload, pick up the secondary register
6736 and icode, if any. If OLDEQUIV and OLD are different or
6737 if this is an in-out reload, recompute whether or not we
6738 still need a secondary register and what the icode should
6739 be. If we still need a secondary register and the class or
6740 icode is different, go back to reloading from OLD if using
6741 OLDEQUIV means that we got the wrong type of register. We
6742 cannot have different class or icode due to an in-out reload
6743 because we don't make such reloads when both the input and
6744 output need secondary reload registers. */
6746 if (! special && rl->secondary_in_reload >= 0)
6748 rtx second_reload_reg = 0;
6749 rtx third_reload_reg = 0;
6750 int secondary_reload = rl->secondary_in_reload;
6751 rtx real_oldequiv = oldequiv;
6754 enum insn_code icode;
6755 enum insn_code tertiary_icode = CODE_FOR_nothing;
6757 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6758 and similarly for OLD.
6759 See comments in get_secondary_reload in reload.c. */
6760 /* If it is a pseudo that cannot be replaced with its
6761 equivalent MEM, we must fall back to reload_in, which
6762 will have all the necessary substitutions registered.
6763 Likewise for a pseudo that can't be replaced with its
6764 equivalent constant.
6766 Take extra care for subregs of such pseudos. Note that
6767 we cannot use reg_equiv_mem in this case because it is
6768 not in the right mode. */
6771 if (GET_CODE (tmp) == SUBREG)
6772 tmp = SUBREG_REG (tmp);
6774 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6775 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6776 || reg_equiv_constant[REGNO (tmp)] != 0))
6778 if (! reg_equiv_mem[REGNO (tmp)]
6779 || num_not_at_initial_offset
6780 || GET_CODE (oldequiv) == SUBREG)
6781 real_oldequiv = rl->in;
6783 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6787 if (GET_CODE (tmp) == SUBREG)
6788 tmp = SUBREG_REG (tmp);
6790 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6791 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6792 || reg_equiv_constant[REGNO (tmp)] != 0))
6794 if (! reg_equiv_mem[REGNO (tmp)]
6795 || num_not_at_initial_offset
6796 || GET_CODE (old) == SUBREG)
6799 real_old = reg_equiv_mem[REGNO (tmp)];
6802 second_reload_reg = rld[secondary_reload].reg_rtx;
6803 if (rld[secondary_reload].secondary_in_reload >= 0)
6805 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6807 third_reload_reg = rld[tertiary_reload].reg_rtx;
6808 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6809 /* We'd have to add more code for quartary reloads. */
6810 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6812 icode = rl->secondary_in_icode;
6814 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6815 || (rl->in != 0 && rl->out != 0))
6817 secondary_reload_info sri, sri2;
6818 enum reg_class new_class, new_t_class;
6820 sri.icode = CODE_FOR_nothing;
6821 sri.prev_sri = NULL;
6822 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6825 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6826 second_reload_reg = 0;
6827 else if (new_class == NO_REGS)
6829 if (reload_adjust_reg_for_icode (&second_reload_reg,
6830 third_reload_reg, sri.icode))
6831 icode = sri.icode, third_reload_reg = 0;
6833 oldequiv = old, real_oldequiv = real_old;
6835 else if (sri.icode != CODE_FOR_nothing)
6836 /* We currently lack a way to express this in reloads. */
6840 sri2.icode = CODE_FOR_nothing;
6841 sri2.prev_sri = &sri;
6842 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6843 new_class, mode, &sri);
6844 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6846 if (reload_adjust_reg_for_temp (&second_reload_reg,
6849 third_reload_reg = 0, tertiary_icode = sri2.icode;
6851 oldequiv = old, real_oldequiv = real_old;
6853 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6855 rtx intermediate = second_reload_reg;
6857 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6859 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6862 second_reload_reg = intermediate;
6863 tertiary_icode = sri2.icode;
6866 oldequiv = old, real_oldequiv = real_old;
6868 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6870 rtx intermediate = second_reload_reg;
6872 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6874 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6877 second_reload_reg = intermediate;
6878 tertiary_icode = sri2.icode;
6881 oldequiv = old, real_oldequiv = real_old;
6884 /* This could be handled more intelligently too. */
6885 oldequiv = old, real_oldequiv = real_old;
6889 /* If we still need a secondary reload register, check
6890 to see if it is being used as a scratch or intermediate
6891 register and generate code appropriately. If we need
6892 a scratch register, use REAL_OLDEQUIV since the form of
6893 the insn may depend on the actual address if it is
6896 if (second_reload_reg)
6898 if (icode != CODE_FOR_nothing)
6900 /* We'd have to add extra code to handle this case. */
6901 gcc_assert (!third_reload_reg);
6903 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6904 second_reload_reg));
6909 /* See if we need a scratch register to load the
6910 intermediate register (a tertiary reload). */
6911 if (tertiary_icode != CODE_FOR_nothing)
6913 emit_insn ((GEN_FCN (tertiary_icode)
6914 (second_reload_reg, real_oldequiv,
6915 third_reload_reg)));
6917 else if (third_reload_reg)
6919 gen_reload (third_reload_reg, real_oldequiv,
6922 gen_reload (second_reload_reg, third_reload_reg,
6927 gen_reload (second_reload_reg, real_oldequiv,
6931 oldequiv = second_reload_reg;
6936 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6938 rtx real_oldequiv = oldequiv;
6940 if ((REG_P (oldequiv)
6941 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6942 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6943 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6944 || (GET_CODE (oldequiv) == SUBREG
6945 && REG_P (SUBREG_REG (oldequiv))
6946 && (REGNO (SUBREG_REG (oldequiv))
6947 >= FIRST_PSEUDO_REGISTER)
6948 && ((reg_equiv_memory_loc
6949 [REGNO (SUBREG_REG (oldequiv))] != 0)
6950 || (reg_equiv_constant
6951 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6952 || (CONSTANT_P (oldequiv)
6953 && (PREFERRED_RELOAD_CLASS (oldequiv,
6954 REGNO_REG_CLASS (REGNO (reloadreg)))
6956 real_oldequiv = rl->in;
6957 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6961 if (flag_non_call_exceptions)
6962 copy_eh_notes (insn, get_insns ());
6964 /* End this sequence. */
6965 *where = get_insns ();
6968 /* Update reload_override_in so that delete_address_reloads_1
6969 can see the actual register usage. */
6971 reload_override_in[j] = oldequiv;
6974 /* Generate insns to for the output reload RL, which is for the insn described
6975 by CHAIN and has the number J. */
6977 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6980 rtx reloadreg = rl->reg_rtx;
6981 rtx insn = chain->insn;
6984 enum machine_mode mode = GET_MODE (old);
6987 if (rl->when_needed == RELOAD_OTHER)
6990 push_to_sequence (output_reload_insns[rl->opnum]);
6992 /* Determine the mode to reload in.
6993 See comments above (for input reloading). */
6995 if (mode == VOIDmode)
6997 /* VOIDmode should never happen for an output. */
6998 if (asm_noperands (PATTERN (insn)) < 0)
6999 /* It's the compiler's fault. */
7000 fatal_insn ("VOIDmode on an output", insn);
7001 error_for_asm (insn, "output operand is constant in %<asm%>");
7002 /* Prevent crash--use something we know is valid. */
7004 old = gen_rtx_REG (mode, REGNO (reloadreg));
7007 if (GET_MODE (reloadreg) != mode)
7008 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7010 /* If we need two reload regs, set RELOADREG to the intermediate
7011 one, since it will be stored into OLD. We might need a secondary
7012 register only for an input reload, so check again here. */
7014 if (rl->secondary_out_reload >= 0)
7017 int secondary_reload = rl->secondary_out_reload;
7018 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7020 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7021 && reg_equiv_mem[REGNO (old)] != 0)
7022 real_old = reg_equiv_mem[REGNO (old)];
7024 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7026 rtx second_reloadreg = reloadreg;
7027 reloadreg = rld[secondary_reload].reg_rtx;
7029 /* See if RELOADREG is to be used as a scratch register
7030 or as an intermediate register. */
7031 if (rl->secondary_out_icode != CODE_FOR_nothing)
7033 /* We'd have to add extra code to handle this case. */
7034 gcc_assert (tertiary_reload < 0);
7036 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7037 (real_old, second_reloadreg, reloadreg)));
7042 /* See if we need both a scratch and intermediate reload
7045 enum insn_code tertiary_icode
7046 = rld[secondary_reload].secondary_out_icode;
7048 /* We'd have to add more code for quartary reloads. */
7049 gcc_assert (tertiary_reload < 0
7050 || rld[tertiary_reload].secondary_out_reload < 0);
7052 if (GET_MODE (reloadreg) != mode)
7053 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7055 if (tertiary_icode != CODE_FOR_nothing)
7057 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7060 /* Copy primary reload reg to secondary reload reg.
7061 (Note that these have been swapped above, then
7062 secondary reload reg to OLD using our insn.) */
7064 /* If REAL_OLD is a paradoxical SUBREG, remove it
7065 and try to put the opposite SUBREG on
7067 if (GET_CODE (real_old) == SUBREG
7068 && (GET_MODE_SIZE (GET_MODE (real_old))
7069 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7070 && 0 != (tem = gen_lowpart_common
7071 (GET_MODE (SUBREG_REG (real_old)),
7073 real_old = SUBREG_REG (real_old), reloadreg = tem;
7075 gen_reload (reloadreg, second_reloadreg,
7076 rl->opnum, rl->when_needed);
7077 emit_insn ((GEN_FCN (tertiary_icode)
7078 (real_old, reloadreg, third_reloadreg)));
7084 /* Copy between the reload regs here and then to
7087 gen_reload (reloadreg, second_reloadreg,
7088 rl->opnum, rl->when_needed);
7089 if (tertiary_reload >= 0)
7091 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7093 gen_reload (third_reloadreg, reloadreg,
7094 rl->opnum, rl->when_needed);
7095 reloadreg = third_reloadreg;
7102 /* Output the last reload insn. */
7107 /* Don't output the last reload if OLD is not the dest of
7108 INSN and is in the src and is clobbered by INSN. */
7109 if (! flag_expensive_optimizations
7111 || !(set = single_set (insn))
7112 || rtx_equal_p (old, SET_DEST (set))
7113 || !reg_mentioned_p (old, SET_SRC (set))
7114 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7115 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7116 gen_reload (old, reloadreg, rl->opnum,
7120 /* Look at all insns we emitted, just to be safe. */
7121 for (p = get_insns (); p; p = NEXT_INSN (p))
7124 rtx pat = PATTERN (p);
7126 /* If this output reload doesn't come from a spill reg,
7127 clear any memory of reloaded copies of the pseudo reg.
7128 If this output reload comes from a spill reg,
7129 reg_has_output_reload will make this do nothing. */
7130 note_stores (pat, forget_old_reloads_1, NULL);
7132 if (reg_mentioned_p (rl->reg_rtx, pat))
7134 rtx set = single_set (insn);
7135 if (reload_spill_index[j] < 0
7137 && SET_SRC (set) == rl->reg_rtx)
7139 int src = REGNO (SET_SRC (set));
7141 reload_spill_index[j] = src;
7142 SET_HARD_REG_BIT (reg_is_output_reload, src);
7143 if (find_regno_note (insn, REG_DEAD, src))
7144 SET_HARD_REG_BIT (reg_reloaded_died, src);
7146 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7148 int s = rl->secondary_out_reload;
7149 set = single_set (p);
7150 /* If this reload copies only to the secondary reload
7151 register, the secondary reload does the actual
7153 if (s >= 0 && set == NULL_RTX)
7154 /* We can't tell what function the secondary reload
7155 has and where the actual store to the pseudo is
7156 made; leave new_spill_reg_store alone. */
7159 && SET_SRC (set) == rl->reg_rtx
7160 && SET_DEST (set) == rld[s].reg_rtx)
7162 /* Usually the next instruction will be the
7163 secondary reload insn; if we can confirm
7164 that it is, setting new_spill_reg_store to
7165 that insn will allow an extra optimization. */
7166 rtx s_reg = rld[s].reg_rtx;
7167 rtx next = NEXT_INSN (p);
7168 rld[s].out = rl->out;
7169 rld[s].out_reg = rl->out_reg;
7170 set = single_set (next);
7171 if (set && SET_SRC (set) == s_reg
7172 && ! new_spill_reg_store[REGNO (s_reg)])
7174 SET_HARD_REG_BIT (reg_is_output_reload,
7176 new_spill_reg_store[REGNO (s_reg)] = next;
7180 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7185 if (rl->when_needed == RELOAD_OTHER)
7187 emit_insn (other_output_reload_insns[rl->opnum]);
7188 other_output_reload_insns[rl->opnum] = get_insns ();
7191 output_reload_insns[rl->opnum] = get_insns ();
7193 if (flag_non_call_exceptions)
7194 copy_eh_notes (insn, get_insns ());
7199 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7200 and has the number J. */
7202 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7204 rtx insn = chain->insn;
7205 rtx old = (rl->in && MEM_P (rl->in)
7206 ? rl->in_reg : rl->in);
7209 /* AUTO_INC reloads need to be handled even if inherited. We got an
7210 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7211 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7212 && ! rtx_equal_p (rl->reg_rtx, old)
7213 && rl->reg_rtx != 0)
7214 emit_input_reload_insns (chain, rld + j, old, j);
7216 /* When inheriting a wider reload, we have a MEM in rl->in,
7217 e.g. inheriting a SImode output reload for
7218 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7219 if (optimize && reload_inherited[j] && rl->in
7221 && MEM_P (rl->in_reg)
7222 && reload_spill_index[j] >= 0
7223 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7224 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7226 /* If we are reloading a register that was recently stored in with an
7227 output-reload, see if we can prove there was
7228 actually no need to store the old value in it. */
7231 && (reload_inherited[j] || reload_override_in[j])
7233 && REG_P (rl->reg_rtx)
7234 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7236 /* There doesn't seem to be any reason to restrict this to pseudos
7237 and doing so loses in the case where we are copying from a
7238 register of the wrong class. */
7239 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7240 >= FIRST_PSEUDO_REGISTER)
7242 /* The insn might have already some references to stackslots
7243 replaced by MEMs, while reload_out_reg still names the
7245 && (dead_or_set_p (insn,
7246 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7247 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7249 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7252 /* Do output reloading for reload RL, which is for the insn described by
7253 CHAIN and has the number J.
7254 ??? At some point we need to support handling output reloads of
7255 JUMP_INSNs or insns that set cc0. */
7257 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7260 rtx insn = chain->insn;
7261 /* If this is an output reload that stores something that is
7262 not loaded in this same reload, see if we can eliminate a previous
7264 rtx pseudo = rl->out_reg;
7269 && ! rtx_equal_p (rl->in_reg, pseudo)
7270 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7271 && reg_last_reload_reg[REGNO (pseudo)])
7273 int pseudo_no = REGNO (pseudo);
7274 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7276 /* We don't need to test full validity of last_regno for
7277 inherit here; we only want to know if the store actually
7278 matches the pseudo. */
7279 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7280 && reg_reloaded_contents[last_regno] == pseudo_no
7281 && spill_reg_store[last_regno]
7282 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7283 delete_output_reload (insn, j, last_regno);
7288 || rl->reg_rtx == old
7289 || rl->reg_rtx == 0)
7292 /* An output operand that dies right away does need a reload,
7293 but need not be copied from it. Show the new location in the
7295 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7296 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7298 XEXP (note, 0) = rl->reg_rtx;
7301 /* Likewise for a SUBREG of an operand that dies. */
7302 else if (GET_CODE (old) == SUBREG
7303 && REG_P (SUBREG_REG (old))
7304 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7307 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7311 else if (GET_CODE (old) == SCRATCH)
7312 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7313 but we don't want to make an output reload. */
7316 /* If is a JUMP_INSN, we can't support output reloads yet. */
7317 gcc_assert (NONJUMP_INSN_P (insn));
7319 emit_output_reload_insns (chain, rld + j, j);
7322 /* Reload number R reloads from or to a group of hard registers starting at
7323 register REGNO. Return true if it can be treated for inheritance purposes
7324 like a group of reloads, each one reloading a single hard register.
7325 The caller has already checked that the spill register and REGNO use
7326 the same number of registers to store the reload value. */
7329 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7331 #ifdef CANNOT_CHANGE_MODE_CLASS
7332 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7333 GET_MODE (rld[r].reg_rtx),
7334 reg_raw_mode[reload_spill_index[r]])
7335 && !REG_CANNOT_CHANGE_MODE_P (regno,
7336 GET_MODE (rld[r].reg_rtx),
7337 reg_raw_mode[regno]));
7343 /* Output insns to reload values in and out of the chosen reload regs. */
7346 emit_reload_insns (struct insn_chain *chain)
7348 rtx insn = chain->insn;
7352 CLEAR_HARD_REG_SET (reg_reloaded_died);
7354 for (j = 0; j < reload_n_operands; j++)
7355 input_reload_insns[j] = input_address_reload_insns[j]
7356 = inpaddr_address_reload_insns[j]
7357 = output_reload_insns[j] = output_address_reload_insns[j]
7358 = outaddr_address_reload_insns[j]
7359 = other_output_reload_insns[j] = 0;
7360 other_input_address_reload_insns = 0;
7361 other_input_reload_insns = 0;
7362 operand_reload_insns = 0;
7363 other_operand_reload_insns = 0;
7365 /* Dump reloads into the dump file. */
7368 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7369 debug_reload_to_stream (dump_file);
7372 /* Now output the instructions to copy the data into and out of the
7373 reload registers. Do these in the order that the reloads were reported,
7374 since reloads of base and index registers precede reloads of operands
7375 and the operands may need the base and index registers reloaded. */
7377 for (j = 0; j < n_reloads; j++)
7380 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7381 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7383 do_input_reload (chain, rld + j, j);
7384 do_output_reload (chain, rld + j, j);
7387 /* Now write all the insns we made for reloads in the order expected by
7388 the allocation functions. Prior to the insn being reloaded, we write
7389 the following reloads:
7391 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7393 RELOAD_OTHER reloads.
7395 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7396 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7397 RELOAD_FOR_INPUT reload for the operand.
7399 RELOAD_FOR_OPADDR_ADDRS reloads.
7401 RELOAD_FOR_OPERAND_ADDRESS reloads.
7403 After the insn being reloaded, we write the following:
7405 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7406 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7407 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7408 reloads for the operand. The RELOAD_OTHER output reloads are
7409 output in descending order by reload number. */
7411 emit_insn_before (other_input_address_reload_insns, insn);
7412 emit_insn_before (other_input_reload_insns, insn);
7414 for (j = 0; j < reload_n_operands; j++)
7416 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7417 emit_insn_before (input_address_reload_insns[j], insn);
7418 emit_insn_before (input_reload_insns[j], insn);
7421 emit_insn_before (other_operand_reload_insns, insn);
7422 emit_insn_before (operand_reload_insns, insn);
7424 for (j = 0; j < reload_n_operands; j++)
7426 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7427 x = emit_insn_after (output_address_reload_insns[j], x);
7428 x = emit_insn_after (output_reload_insns[j], x);
7429 emit_insn_after (other_output_reload_insns[j], x);
7432 /* For all the spill regs newly reloaded in this instruction,
7433 record what they were reloaded from, so subsequent instructions
7434 can inherit the reloads.
7436 Update spill_reg_store for the reloads of this insn.
7437 Copy the elements that were updated in the loop above. */
7439 for (j = 0; j < n_reloads; j++)
7441 int r = reload_order[j];
7442 int i = reload_spill_index[r];
7444 /* If this is a non-inherited input reload from a pseudo, we must
7445 clear any memory of a previous store to the same pseudo. Only do
7446 something if there will not be an output reload for the pseudo
7448 if (rld[r].in_reg != 0
7449 && ! (reload_inherited[r] || reload_override_in[r]))
7451 rtx reg = rld[r].in_reg;
7453 if (GET_CODE (reg) == SUBREG)
7454 reg = SUBREG_REG (reg);
7457 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7458 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7460 int nregno = REGNO (reg);
7462 if (reg_last_reload_reg[nregno])
7464 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7466 if (reg_reloaded_contents[last_regno] == nregno)
7467 spill_reg_store[last_regno] = 0;
7472 /* I is nonneg if this reload used a register.
7473 If rld[r].reg_rtx is 0, this is an optional reload
7474 that we opted to ignore. */
7476 if (i >= 0 && rld[r].reg_rtx != 0)
7478 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7480 int part_reaches_end = 0;
7481 int all_reaches_end = 1;
7483 /* For a multi register reload, we need to check if all or part
7484 of the value lives to the end. */
7485 for (k = 0; k < nr; k++)
7487 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7488 rld[r].when_needed))
7489 part_reaches_end = 1;
7491 all_reaches_end = 0;
7494 /* Ignore reloads that don't reach the end of the insn in
7496 if (all_reaches_end)
7498 /* First, clear out memory of what used to be in this spill reg.
7499 If consecutive registers are used, clear them all. */
7501 for (k = 0; k < nr; k++)
7503 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7504 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7507 /* Maybe the spill reg contains a copy of reload_out. */
7509 && (REG_P (rld[r].out)
7513 || REG_P (rld[r].out_reg)))
7515 rtx out = (REG_P (rld[r].out)
7519 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7520 int nregno = REGNO (out);
7521 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7522 : hard_regno_nregs[nregno]
7523 [GET_MODE (rld[r].reg_rtx)]);
7526 spill_reg_store[i] = new_spill_reg_store[i];
7527 spill_reg_stored_to[i] = out;
7528 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7530 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7532 && inherit_piecemeal_p (r, nregno));
7534 /* If NREGNO is a hard register, it may occupy more than
7535 one register. If it does, say what is in the
7536 rest of the registers assuming that both registers
7537 agree on how many words the object takes. If not,
7538 invalidate the subsequent registers. */
7540 if (nregno < FIRST_PSEUDO_REGISTER)
7541 for (k = 1; k < nnr; k++)
7542 reg_last_reload_reg[nregno + k]
7544 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7547 /* Now do the inverse operation. */
7548 for (k = 0; k < nr; k++)
7550 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7551 reg_reloaded_contents[i + k]
7552 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7555 reg_reloaded_insn[i + k] = insn;
7556 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7557 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7558 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7562 /* Maybe the spill reg contains a copy of reload_in. Only do
7563 something if there will not be an output reload for
7564 the register being reloaded. */
7565 else if (rld[r].out_reg == 0
7567 && ((REG_P (rld[r].in)
7568 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7569 && !REGNO_REG_SET_P (®_has_output_reload,
7571 || (REG_P (rld[r].in_reg)
7572 && !REGNO_REG_SET_P (®_has_output_reload,
7573 REGNO (rld[r].in_reg))))
7574 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7581 if (REG_P (rld[r].in)
7582 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7584 else if (REG_P (rld[r].in_reg))
7587 in = XEXP (rld[r].in_reg, 0);
7588 nregno = REGNO (in);
7590 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7591 : hard_regno_nregs[nregno]
7592 [GET_MODE (rld[r].reg_rtx)]);
7594 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7596 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7598 && inherit_piecemeal_p (r, nregno));
7600 if (nregno < FIRST_PSEUDO_REGISTER)
7601 for (k = 1; k < nnr; k++)
7602 reg_last_reload_reg[nregno + k]
7604 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7607 /* Unless we inherited this reload, show we haven't
7608 recently done a store.
7609 Previous stores of inherited auto_inc expressions
7610 also have to be discarded. */
7611 if (! reload_inherited[r]
7612 || (rld[r].out && ! rld[r].out_reg))
7613 spill_reg_store[i] = 0;
7615 for (k = 0; k < nr; k++)
7617 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7618 reg_reloaded_contents[i + k]
7619 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7622 reg_reloaded_insn[i + k] = insn;
7623 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7624 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7625 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7630 /* However, if part of the reload reaches the end, then we must
7631 invalidate the old info for the part that survives to the end. */
7632 else if (part_reaches_end)
7634 for (k = 0; k < nr; k++)
7635 if (reload_reg_reaches_end_p (i + k,
7637 rld[r].when_needed))
7638 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7642 /* The following if-statement was #if 0'd in 1.34 (or before...).
7643 It's reenabled in 1.35 because supposedly nothing else
7644 deals with this problem. */
7646 /* If a register gets output-reloaded from a non-spill register,
7647 that invalidates any previous reloaded copy of it.
7648 But forget_old_reloads_1 won't get to see it, because
7649 it thinks only about the original insn. So invalidate it here.
7650 Also do the same thing for RELOAD_OTHER constraints where the
7651 output is discarded. */
7653 && ((rld[r].out != 0
7654 && (REG_P (rld[r].out)
7655 || (MEM_P (rld[r].out)
7656 && REG_P (rld[r].out_reg))))
7657 || (rld[r].out == 0 && rld[r].out_reg
7658 && REG_P (rld[r].out_reg))))
7660 rtx out = ((rld[r].out && REG_P (rld[r].out))
7661 ? rld[r].out : rld[r].out_reg);
7662 int nregno = REGNO (out);
7664 /* REG_RTX is now set or clobbered by the main instruction.
7665 As the comment above explains, forget_old_reloads_1 only
7666 sees the original instruction, and there is no guarantee
7667 that the original instruction also clobbered REG_RTX.
7668 For example, if find_reloads sees that the input side of
7669 a matched operand pair dies in this instruction, it may
7670 use the input register as the reload register.
7672 Calling forget_old_reloads_1 is a waste of effort if
7673 REG_RTX is also the output register.
7675 If we know that REG_RTX holds the value of a pseudo
7676 register, the code after the call will record that fact. */
7677 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7678 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7680 if (nregno >= FIRST_PSEUDO_REGISTER)
7682 rtx src_reg, store_insn = NULL_RTX;
7684 reg_last_reload_reg[nregno] = 0;
7686 /* If we can find a hard register that is stored, record
7687 the storing insn so that we may delete this insn with
7688 delete_output_reload. */
7689 src_reg = rld[r].reg_rtx;
7691 /* If this is an optional reload, try to find the source reg
7692 from an input reload. */
7695 rtx set = single_set (insn);
7696 if (set && SET_DEST (set) == rld[r].out)
7700 src_reg = SET_SRC (set);
7702 for (k = 0; k < n_reloads; k++)
7704 if (rld[k].in == src_reg)
7706 src_reg = rld[k].reg_rtx;
7713 store_insn = new_spill_reg_store[REGNO (src_reg)];
7714 if (src_reg && REG_P (src_reg)
7715 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7717 int src_regno = REGNO (src_reg);
7718 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7719 /* The place where to find a death note varies with
7720 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7721 necessarily checked exactly in the code that moves
7722 notes, so just check both locations. */
7723 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7724 if (! note && store_insn)
7725 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7728 spill_reg_store[src_regno + nr] = store_insn;
7729 spill_reg_stored_to[src_regno + nr] = out;
7730 reg_reloaded_contents[src_regno + nr] = nregno;
7731 reg_reloaded_insn[src_regno + nr] = store_insn;
7732 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7733 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7734 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7735 GET_MODE (src_reg)))
7736 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7738 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7740 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7742 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7744 reg_last_reload_reg[nregno] = src_reg;
7745 /* We have to set reg_has_output_reload here, or else
7746 forget_old_reloads_1 will clear reg_last_reload_reg
7748 SET_REGNO_REG_SET (®_has_output_reload,
7754 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7756 while (num_regs-- > 0)
7757 reg_last_reload_reg[nregno + num_regs] = 0;
7761 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7764 /* Go through the motions to emit INSN and test if it is strictly valid.
7765 Return the emitted insn if valid, else return NULL. */
7768 emit_insn_if_valid_for_reload (rtx insn)
7770 rtx last = get_last_insn ();
7773 insn = emit_insn (insn);
7774 code = recog_memoized (insn);
7778 extract_insn (insn);
7779 /* We want constrain operands to treat this insn strictly in its
7780 validity determination, i.e., the way it would after reload has
7782 if (constrain_operands (1))
7786 delete_insns_since (last);
7790 /* Emit code to perform a reload from IN (which may be a reload register) to
7791 OUT (which may also be a reload register). IN or OUT is from operand
7792 OPNUM with reload type TYPE.
7794 Returns first insn emitted. */
7797 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7799 rtx last = get_last_insn ();
7802 /* If IN is a paradoxical SUBREG, remove it and try to put the
7803 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7804 if (GET_CODE (in) == SUBREG
7805 && (GET_MODE_SIZE (GET_MODE (in))
7806 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7807 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7808 in = SUBREG_REG (in), out = tem;
7809 else if (GET_CODE (out) == SUBREG
7810 && (GET_MODE_SIZE (GET_MODE (out))
7811 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7812 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7813 out = SUBREG_REG (out), in = tem;
7815 /* How to do this reload can get quite tricky. Normally, we are being
7816 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7817 register that didn't get a hard register. In that case we can just
7818 call emit_move_insn.
7820 We can also be asked to reload a PLUS that adds a register or a MEM to
7821 another register, constant or MEM. This can occur during frame pointer
7822 elimination and while reloading addresses. This case is handled by
7823 trying to emit a single insn to perform the add. If it is not valid,
7824 we use a two insn sequence.
7826 Or we can be asked to reload an unary operand that was a fragment of
7827 an addressing mode, into a register. If it isn't recognized as-is,
7828 we try making the unop operand and the reload-register the same:
7829 (set reg:X (unop:X expr:Y))
7830 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7832 Finally, we could be called to handle an 'o' constraint by putting
7833 an address into a register. In that case, we first try to do this
7834 with a named pattern of "reload_load_address". If no such pattern
7835 exists, we just emit a SET insn and hope for the best (it will normally
7836 be valid on machines that use 'o').
7838 This entire process is made complex because reload will never
7839 process the insns we generate here and so we must ensure that
7840 they will fit their constraints and also by the fact that parts of
7841 IN might be being reloaded separately and replaced with spill registers.
7842 Because of this, we are, in some sense, just guessing the right approach
7843 here. The one listed above seems to work.
7845 ??? At some point, this whole thing needs to be rethought. */
7847 if (GET_CODE (in) == PLUS
7848 && (REG_P (XEXP (in, 0))
7849 || GET_CODE (XEXP (in, 0)) == SUBREG
7850 || MEM_P (XEXP (in, 0)))
7851 && (REG_P (XEXP (in, 1))
7852 || GET_CODE (XEXP (in, 1)) == SUBREG
7853 || CONSTANT_P (XEXP (in, 1))
7854 || MEM_P (XEXP (in, 1))))
7856 /* We need to compute the sum of a register or a MEM and another
7857 register, constant, or MEM, and put it into the reload
7858 register. The best possible way of doing this is if the machine
7859 has a three-operand ADD insn that accepts the required operands.
7861 The simplest approach is to try to generate such an insn and see if it
7862 is recognized and matches its constraints. If so, it can be used.
7864 It might be better not to actually emit the insn unless it is valid,
7865 but we need to pass the insn as an operand to `recog' and
7866 `extract_insn' and it is simpler to emit and then delete the insn if
7867 not valid than to dummy things up. */
7869 rtx op0, op1, tem, insn;
7872 op0 = find_replacement (&XEXP (in, 0));
7873 op1 = find_replacement (&XEXP (in, 1));
7875 /* Since constraint checking is strict, commutativity won't be
7876 checked, so we need to do that here to avoid spurious failure
7877 if the add instruction is two-address and the second operand
7878 of the add is the same as the reload reg, which is frequently
7879 the case. If the insn would be A = B + A, rearrange it so
7880 it will be A = A + B as constrain_operands expects. */
7882 if (REG_P (XEXP (in, 1))
7883 && REGNO (out) == REGNO (XEXP (in, 1)))
7884 tem = op0, op0 = op1, op1 = tem;
7886 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7887 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7889 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7893 /* If that failed, we must use a conservative two-insn sequence.
7895 Use a move to copy one operand into the reload register. Prefer
7896 to reload a constant, MEM or pseudo since the move patterns can
7897 handle an arbitrary operand. If OP1 is not a constant, MEM or
7898 pseudo and OP1 is not a valid operand for an add instruction, then
7901 After reloading one of the operands into the reload register, add
7902 the reload register to the output register.
7904 If there is another way to do this for a specific machine, a
7905 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7908 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7910 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7912 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7913 || (code != CODE_FOR_nothing
7914 && ! ((*insn_data[code].operand[2].predicate)
7915 (op1, insn_data[code].operand[2].mode))))
7916 tem = op0, op0 = op1, op1 = tem;
7918 gen_reload (out, op0, opnum, type);
7920 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7921 This fixes a problem on the 32K where the stack pointer cannot
7922 be used as an operand of an add insn. */
7924 if (rtx_equal_p (op0, op1))
7927 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7930 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7931 set_unique_reg_note (insn, REG_EQUIV, in);
7935 /* If that failed, copy the address register to the reload register.
7936 Then add the constant to the reload register. */
7938 gcc_assert (!reg_overlap_mentioned_p (out, op0));
7939 gen_reload (out, op1, opnum, type);
7940 insn = emit_insn (gen_add2_insn (out, op0));
7941 set_unique_reg_note (insn, REG_EQUIV, in);
7944 #ifdef SECONDARY_MEMORY_NEEDED
7945 /* If we need a memory location to do the move, do it that way. */
7946 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7947 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7948 && (REG_P (out) || GET_CODE (out) == SUBREG)
7949 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7950 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7951 REGNO_REG_CLASS (reg_or_subregno (out)),
7954 /* Get the memory to use and rewrite both registers to its mode. */
7955 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7957 if (GET_MODE (loc) != GET_MODE (out))
7958 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7960 if (GET_MODE (loc) != GET_MODE (in))
7961 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7963 gen_reload (loc, in, opnum, type);
7964 gen_reload (out, loc, opnum, type);
7967 else if (REG_P (out) && UNARY_P (in))
7974 op1 = find_replacement (&XEXP (in, 0));
7975 if (op1 != XEXP (in, 0))
7976 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7978 /* First, try a plain SET. */
7979 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7983 /* If that failed, move the inner operand to the reload
7984 register, and try the same unop with the inner expression
7985 replaced with the reload register. */
7987 if (GET_MODE (op1) != GET_MODE (out))
7988 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7992 gen_reload (out_moded, op1, opnum, type);
7995 = gen_rtx_SET (VOIDmode, out,
7996 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7998 insn = emit_insn_if_valid_for_reload (insn);
8001 set_unique_reg_note (insn, REG_EQUIV, in);
8005 fatal_insn ("Failure trying to reload:", set);
8007 /* If IN is a simple operand, use gen_move_insn. */
8008 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8010 tem = emit_insn (gen_move_insn (out, in));
8011 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
8012 mark_jump_label (in, tem, 0);
8015 #ifdef HAVE_reload_load_address
8016 else if (HAVE_reload_load_address)
8017 emit_insn (gen_reload_load_address (out, in));
8020 /* Otherwise, just write (set OUT IN) and hope for the best. */
8022 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8024 /* Return the first insn emitted.
8025 We can not just return get_last_insn, because there may have
8026 been multiple instructions emitted. Also note that gen_move_insn may
8027 emit more than one insn itself, so we can not assume that there is one
8028 insn emitted per emit_insn_before call. */
8030 return last ? NEXT_INSN (last) : get_insns ();
8033 /* Delete a previously made output-reload whose result we now believe
8034 is not needed. First we double-check.
8036 INSN is the insn now being processed.
8037 LAST_RELOAD_REG is the hard register number for which we want to delete
8038 the last output reload.
8039 J is the reload-number that originally used REG. The caller has made
8040 certain that reload J doesn't use REG any longer for input. */
8043 delete_output_reload (rtx insn, int j, int last_reload_reg)
8045 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8046 rtx reg = spill_reg_stored_to[last_reload_reg];
8049 int n_inherited = 0;
8053 /* It is possible that this reload has been only used to set another reload
8054 we eliminated earlier and thus deleted this instruction too. */
8055 if (INSN_DELETED_P (output_reload_insn))
8058 /* Get the raw pseudo-register referred to. */
8060 while (GET_CODE (reg) == SUBREG)
8061 reg = SUBREG_REG (reg);
8062 substed = reg_equiv_memory_loc[REGNO (reg)];
8064 /* This is unsafe if the operand occurs more often in the current
8065 insn than it is inherited. */
8066 for (k = n_reloads - 1; k >= 0; k--)
8068 rtx reg2 = rld[k].in;
8071 if (MEM_P (reg2) || reload_override_in[k])
8072 reg2 = rld[k].in_reg;
8074 if (rld[k].out && ! rld[k].out_reg)
8075 reg2 = XEXP (rld[k].in_reg, 0);
8077 while (GET_CODE (reg2) == SUBREG)
8078 reg2 = SUBREG_REG (reg2);
8079 if (rtx_equal_p (reg2, reg))
8081 if (reload_inherited[k] || reload_override_in[k] || k == j)
8087 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8088 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8089 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8092 n_occurrences += count_occurrences (PATTERN (insn),
8093 eliminate_regs (substed, 0,
8095 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8097 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8098 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8100 if (n_occurrences > n_inherited)
8103 /* If the pseudo-reg we are reloading is no longer referenced
8104 anywhere between the store into it and here,
8105 and we're within the same basic block, then the value can only
8106 pass through the reload reg and end up here.
8107 Otherwise, give up--return. */
8108 for (i1 = NEXT_INSN (output_reload_insn);
8109 i1 != insn; i1 = NEXT_INSN (i1))
8111 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8113 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8114 && reg_mentioned_p (reg, PATTERN (i1)))
8116 /* If this is USE in front of INSN, we only have to check that
8117 there are no more references than accounted for by inheritance. */
8118 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8120 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8121 i1 = NEXT_INSN (i1);
8123 if (n_occurrences <= n_inherited && i1 == insn)
8129 /* We will be deleting the insn. Remove the spill reg information. */
8130 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8132 spill_reg_store[last_reload_reg + k] = 0;
8133 spill_reg_stored_to[last_reload_reg + k] = 0;
8136 /* The caller has already checked that REG dies or is set in INSN.
8137 It has also checked that we are optimizing, and thus some
8138 inaccuracies in the debugging information are acceptable.
8139 So we could just delete output_reload_insn. But in some cases
8140 we can improve the debugging information without sacrificing
8141 optimization - maybe even improving the code: See if the pseudo
8142 reg has been completely replaced with reload regs. If so, delete
8143 the store insn and forget we had a stack slot for the pseudo. */
8144 if (rld[j].out != rld[j].in
8145 && REG_N_DEATHS (REGNO (reg)) == 1
8146 && REG_N_SETS (REGNO (reg)) == 1
8147 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8148 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8152 /* We know that it was used only between here and the beginning of
8153 the current basic block. (We also know that the last use before
8154 INSN was the output reload we are thinking of deleting, but never
8155 mind that.) Search that range; see if any ref remains. */
8156 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8158 rtx set = single_set (i2);
8160 /* Uses which just store in the pseudo don't count,
8161 since if they are the only uses, they are dead. */
8162 if (set != 0 && SET_DEST (set) == reg)
8167 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8168 && reg_mentioned_p (reg, PATTERN (i2)))
8170 /* Some other ref remains; just delete the output reload we
8172 delete_address_reloads (output_reload_insn, insn);
8173 delete_insn (output_reload_insn);
8178 /* Delete the now-dead stores into this pseudo. Note that this
8179 loop also takes care of deleting output_reload_insn. */
8180 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8182 rtx set = single_set (i2);
8184 if (set != 0 && SET_DEST (set) == reg)
8186 delete_address_reloads (i2, insn);
8194 /* For the debugging info, say the pseudo lives in this reload reg. */
8195 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8196 alter_reg (REGNO (reg), -1);
8200 delete_address_reloads (output_reload_insn, insn);
8201 delete_insn (output_reload_insn);
8205 /* We are going to delete DEAD_INSN. Recursively delete loads of
8206 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8207 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8209 delete_address_reloads (rtx dead_insn, rtx current_insn)
8211 rtx set = single_set (dead_insn);
8212 rtx set2, dst, prev, next;
8215 rtx dst = SET_DEST (set);
8217 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8219 /* If we deleted the store from a reloaded post_{in,de}c expression,
8220 we can delete the matching adds. */
8221 prev = PREV_INSN (dead_insn);
8222 next = NEXT_INSN (dead_insn);
8223 if (! prev || ! next)
8225 set = single_set (next);
8226 set2 = single_set (prev);
8228 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8229 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8230 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8232 dst = SET_DEST (set);
8233 if (! rtx_equal_p (dst, SET_DEST (set2))
8234 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8235 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8236 || (INTVAL (XEXP (SET_SRC (set), 1))
8237 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8239 delete_related_insns (prev);
8240 delete_related_insns (next);
8243 /* Subfunction of delete_address_reloads: process registers found in X. */
8245 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8247 rtx prev, set, dst, i2;
8249 enum rtx_code code = GET_CODE (x);
8253 const char *fmt = GET_RTX_FORMAT (code);
8254 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8257 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8258 else if (fmt[i] == 'E')
8260 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8261 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8268 if (spill_reg_order[REGNO (x)] < 0)
8271 /* Scan backwards for the insn that sets x. This might be a way back due
8273 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8275 code = GET_CODE (prev);
8276 if (code == CODE_LABEL || code == JUMP_INSN)
8280 if (reg_set_p (x, PATTERN (prev)))
8282 if (reg_referenced_p (x, PATTERN (prev)))
8285 if (! prev || INSN_UID (prev) < reload_first_uid)
8287 /* Check that PREV only sets the reload register. */
8288 set = single_set (prev);
8291 dst = SET_DEST (set);
8293 || ! rtx_equal_p (dst, x))
8295 if (! reg_set_p (dst, PATTERN (dead_insn)))
8297 /* Check if DST was used in a later insn -
8298 it might have been inherited. */
8299 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8305 if (reg_referenced_p (dst, PATTERN (i2)))
8307 /* If there is a reference to the register in the current insn,
8308 it might be loaded in a non-inherited reload. If no other
8309 reload uses it, that means the register is set before
8311 if (i2 == current_insn)
8313 for (j = n_reloads - 1; j >= 0; j--)
8314 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8315 || reload_override_in[j] == dst)
8317 for (j = n_reloads - 1; j >= 0; j--)
8318 if (rld[j].in && rld[j].reg_rtx == dst)
8327 /* If DST is still live at CURRENT_INSN, check if it is used for
8328 any reload. Note that even if CURRENT_INSN sets DST, we still
8329 have to check the reloads. */
8330 if (i2 == current_insn)
8332 for (j = n_reloads - 1; j >= 0; j--)
8333 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8334 || reload_override_in[j] == dst)
8336 /* ??? We can't finish the loop here, because dst might be
8337 allocated to a pseudo in this block if no reload in this
8338 block needs any of the classes containing DST - see
8339 spill_hard_reg. There is no easy way to tell this, so we
8340 have to scan till the end of the basic block. */
8342 if (reg_set_p (dst, PATTERN (i2)))
8346 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8347 reg_reloaded_contents[REGNO (dst)] = -1;
8351 /* Output reload-insns to reload VALUE into RELOADREG.
8352 VALUE is an autoincrement or autodecrement RTX whose operand
8353 is a register or memory location;
8354 so reloading involves incrementing that location.
8355 IN is either identical to VALUE, or some cheaper place to reload from.
8357 INC_AMOUNT is the number to increment or decrement by (always positive).
8358 This cannot be deduced from VALUE.
8360 Return the instruction that stores into RELOADREG. */
8363 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8365 /* REG or MEM to be copied and incremented. */
8366 rtx incloc = find_replacement (&XEXP (value, 0));
8367 /* Nonzero if increment after copying. */
8368 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8369 || GET_CODE (value) == POST_MODIFY);
8375 rtx real_in = in == value ? incloc : in;
8377 /* No hard register is equivalent to this register after
8378 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8379 we could inc/dec that register as well (maybe even using it for
8380 the source), but I'm not sure it's worth worrying about. */
8382 reg_last_reload_reg[REGNO (incloc)] = 0;
8384 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8386 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8387 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8391 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8392 inc_amount = -inc_amount;
8394 inc = GEN_INT (inc_amount);
8397 /* If this is post-increment, first copy the location to the reload reg. */
8398 if (post && real_in != reloadreg)
8399 emit_insn (gen_move_insn (reloadreg, real_in));
8403 /* See if we can directly increment INCLOC. Use a method similar to
8404 that in gen_reload. */
8406 last = get_last_insn ();
8407 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8408 gen_rtx_PLUS (GET_MODE (incloc),
8411 code = recog_memoized (add_insn);
8414 extract_insn (add_insn);
8415 if (constrain_operands (1))
8417 /* If this is a pre-increment and we have incremented the value
8418 where it lives, copy the incremented value to RELOADREG to
8419 be used as an address. */
8422 emit_insn (gen_move_insn (reloadreg, incloc));
8427 delete_insns_since (last);
8430 /* If couldn't do the increment directly, must increment in RELOADREG.
8431 The way we do this depends on whether this is pre- or post-increment.
8432 For pre-increment, copy INCLOC to the reload register, increment it
8433 there, then save back. */
8437 if (in != reloadreg)
8438 emit_insn (gen_move_insn (reloadreg, real_in));
8439 emit_insn (gen_add2_insn (reloadreg, inc));
8440 store = emit_insn (gen_move_insn (incloc, reloadreg));
8445 Because this might be a jump insn or a compare, and because RELOADREG
8446 may not be available after the insn in an input reload, we must do
8447 the incrementation before the insn being reloaded for.
8449 We have already copied IN to RELOADREG. Increment the copy in
8450 RELOADREG, save that back, then decrement RELOADREG so it has
8451 the original value. */
8453 emit_insn (gen_add2_insn (reloadreg, inc));
8454 store = emit_insn (gen_move_insn (incloc, reloadreg));
8455 if (GET_CODE (inc) == CONST_INT)
8456 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8458 emit_insn (gen_sub2_insn (reloadreg, inc));
8466 add_auto_inc_notes (rtx insn, rtx x)
8468 enum rtx_code code = GET_CODE (x);
8472 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8475 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8479 /* Scan all the operand sub-expressions. */
8480 fmt = GET_RTX_FORMAT (code);
8481 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8484 add_auto_inc_notes (insn, XEXP (x, i));
8485 else if (fmt[i] == 'E')
8486 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8487 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8492 /* Copy EH notes from an insn to its reloads. */
8494 copy_eh_notes (rtx insn, rtx x)
8496 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8499 for (; x != 0; x = NEXT_INSN (x))
8501 if (may_trap_p (PATTERN (x)))
8503 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8509 /* This is used by reload pass, that does emit some instructions after
8510 abnormal calls moving basic block end, but in fact it wants to emit
8511 them on the edge. Looks for abnormal call edges, find backward the
8512 proper call and fix the damage.
8514 Similar handle instructions throwing exceptions internally. */
8516 fixup_abnormal_edges (void)
8518 bool inserted = false;
8526 /* Look for cases we are interested in - calls or instructions causing
8528 FOR_EACH_EDGE (e, ei, bb->succs)
8530 if (e->flags & EDGE_ABNORMAL_CALL)
8532 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8533 == (EDGE_ABNORMAL | EDGE_EH))
8536 if (e && !CALL_P (BB_END (bb))
8537 && !can_throw_internal (BB_END (bb)))
8541 /* Get past the new insns generated. Allow notes, as the insns
8542 may be already deleted. */
8544 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8545 && !can_throw_internal (insn)
8546 && insn != BB_HEAD (bb))
8547 insn = PREV_INSN (insn);
8549 if (CALL_P (insn) || can_throw_internal (insn))
8553 stop = NEXT_INSN (BB_END (bb));
8555 insn = NEXT_INSN (insn);
8557 FOR_EACH_EDGE (e, ei, bb->succs)
8558 if (e->flags & EDGE_FALLTHRU)
8561 while (insn && insn != stop)
8563 next = NEXT_INSN (insn);
8568 /* Sometimes there's still the return value USE.
8569 If it's placed after a trapping call (i.e. that
8570 call is the last insn anyway), we have no fallthru
8571 edge. Simply delete this use and don't try to insert
8572 on the non-existent edge. */
8573 if (GET_CODE (PATTERN (insn)) != USE)
8575 /* We're not deleting it, we're moving it. */
8576 INSN_DELETED_P (insn) = 0;
8577 PREV_INSN (insn) = NULL_RTX;
8578 NEXT_INSN (insn) = NULL_RTX;
8580 insert_insn_on_edge (insn, e);
8588 /* It may be that we don't find any such trapping insn. In this
8589 case we discovered quite late that the insn that had been
8590 marked as can_throw_internal in fact couldn't trap at all.
8591 So we should in fact delete the EH edges out of the block. */
8593 purge_dead_edges (bb);
8597 /* We've possibly turned single trapping insn into multiple ones. */
8598 if (flag_non_call_exceptions)
8601 blocks = sbitmap_alloc (last_basic_block);
8602 sbitmap_ones (blocks);
8603 find_many_sub_basic_blocks (blocks);
8607 commit_edge_insertions ();
8609 #ifdef ENABLE_CHECKING
8610 /* Verify that we didn't turn one trapping insn into many, and that
8611 we found and corrected all of the problems wrt fixups on the
8613 verify_flow_info ();
projects / platform / upstream / gcc.git / blob