1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
36 #include "rtl-error.h"
38 #include "addresses.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 struct target_reload default_target_reload;
82 struct target_reload *this_target_reload = &default_target_reload;
85 #define spill_indirect_levels \
86 (this_target_reload->x_spill_indirect_levels)
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx *reg_last_reload_reg;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static regset_head reg_has_output_reload;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload;
100 /* Widest mode in which each pseudo reg is referred to (via subreg). */
101 static machine_mode *reg_max_ref_mode;
103 /* Vector to remember old contents of reg_renumber before spilling. */
104 static short *reg_old_renumber;
106 /* During reload_as_needed, element N contains the last pseudo regno reloaded
107 into hard register N. If that pseudo reg occupied more than one register,
108 reg_reloaded_contents points to that pseudo for each spill register in
109 use; all of these must remain set for an inheritance to occur. */
110 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
112 /* During reload_as_needed, element N contains the insn for which
113 hard register N was last used. Its contents are significant only
114 when reg_reloaded_valid is set for this register. */
115 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
117 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
118 static HARD_REG_SET reg_reloaded_valid;
119 /* Indicate if the register was dead at the end of the reload.
120 This is only valid if reg_reloaded_contents is set and valid. */
121 static HARD_REG_SET reg_reloaded_dead;
123 /* Indicate whether the register's current value is one that is not
124 safe to retain across a call, even for registers that are normally
125 call-saved. This is only meaningful for members of reg_reloaded_valid. */
126 static HARD_REG_SET reg_reloaded_call_part_clobbered;
128 /* Number of spill-regs so far; number of valid elements of spill_regs. */
131 /* In parallel with spill_regs, contains REG rtx's for those regs.
132 Holds the last rtx used for any given reg, or 0 if it has never
133 been used for spilling yet. This rtx is reused, provided it has
135 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
137 /* In parallel with spill_regs, contains nonzero for a spill reg
138 that was stored after the last time it was used.
139 The precise value is the insn generated to do the store. */
140 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
142 /* This is the register that was stored with spill_reg_store. This is a
143 copy of reload_out / reload_out_reg when the value was stored; if
144 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
147 /* This table is the inverse mapping of spill_regs:
148 indexed by hard reg number,
149 it contains the position of that reg in spill_regs,
150 or -1 for something that is not in spill_regs.
152 ?!? This is no longer accurate. */
153 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
155 /* This reg set indicates registers that can't be used as spill registers for
156 the currently processed insn. These are the hard registers which are live
157 during the insn, but not allocated to pseudos, as well as fixed
159 static HARD_REG_SET bad_spill_regs;
161 /* These are the hard registers that can't be used as spill register for any
162 insn. This includes registers used for user variables and registers that
163 we can't eliminate. A register that appears in this set also can't be used
164 to retry register allocation. */
165 static HARD_REG_SET bad_spill_regs_global;
167 /* Describes order of use of registers for reloading
168 of spilled pseudo-registers. `n_spills' is the number of
169 elements that are actually valid; new ones are added at the end.
171 Both spill_regs and spill_reg_order are used on two occasions:
172 once during find_reload_regs, where they keep track of the spill registers
173 for a single insn, but also during reload_as_needed where they show all
174 the registers ever used by reload. For the latter case, the information
175 is calculated during finish_spills. */
176 static short spill_regs[FIRST_PSEUDO_REGISTER];
178 /* This vector of reg sets indicates, for each pseudo, which hard registers
179 may not be used for retrying global allocation because the register was
180 formerly spilled from one of them. If we allowed reallocating a pseudo to
181 a register that it was already allocated to, reload might not
183 static HARD_REG_SET *pseudo_previous_regs;
185 /* This vector of reg sets indicates, for each pseudo, which hard
186 registers may not be used for retrying global allocation because they
187 are used as spill registers during one of the insns in which the
189 static HARD_REG_SET *pseudo_forbidden_regs;
191 /* All hard regs that have been used as spill registers for any insn are
192 marked in this set. */
193 static HARD_REG_SET used_spill_regs;
195 /* Index of last register assigned as a spill register. We allocate in
196 a round-robin fashion. */
197 static int last_spill_reg;
199 /* Record the stack slot for each spilled hard register. */
200 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
202 /* Width allocated so far for that stack slot. */
203 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
205 /* Record which pseudos needed to be spilled. */
206 static regset_head spilled_pseudos;
208 /* Record which pseudos changed their allocation in finish_spills. */
209 static regset_head changed_allocation_pseudos;
211 /* Used for communication between order_regs_for_reload and count_pseudo.
212 Used to avoid counting one pseudo twice. */
213 static regset_head pseudos_counted;
215 /* First uid used by insns created by reload in this function.
216 Used in find_equiv_reg. */
217 int reload_first_uid;
219 /* Flag set by local-alloc or global-alloc if anything is live in
220 a call-clobbered reg across calls. */
221 int caller_save_needed;
223 /* Set to 1 while reload_as_needed is operating.
224 Required by some machines to handle any generated moves differently. */
225 int reload_in_progress = 0;
227 /* This obstack is used for allocation of rtl during register elimination.
228 The allocated storage can be freed once find_reloads has processed the
230 static struct obstack reload_obstack;
232 /* Points to the beginning of the reload_obstack. All insn_chain structures
233 are allocated first. */
234 static char *reload_startobj;
236 /* The point after all insn_chain structures. Used to quickly deallocate
237 memory allocated in copy_reloads during calculate_needs_all_insns. */
238 static char *reload_firstobj;
240 /* This points before all local rtl generated by register elimination.
241 Used to quickly free all memory after processing one insn. */
242 static char *reload_insn_firstobj;
244 /* List of insn_chain instructions, one for every insn that reload needs to
246 struct insn_chain *reload_insn_chain;
248 /* TRUE if we potentially left dead insns in the insn stream and want to
249 run DCE immediately after reload, FALSE otherwise. */
250 static bool need_dce;
252 /* List of all insns needing reloads. */
253 static struct insn_chain *insns_need_reload;
255 /* This structure is used to record information about register eliminations.
256 Each array entry describes one possible way of eliminating a register
257 in favor of another. If there is more than one way of eliminating a
258 particular register, the most preferred should be specified first. */
262 int from; /* Register number to be eliminated. */
263 int to; /* Register number used as replacement. */
264 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
265 int can_eliminate; /* Nonzero if this elimination can be done. */
266 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
267 target hook in previous scan over insns
269 HOST_WIDE_INT offset; /* Current offset between the two regs. */
270 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
271 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
272 rtx from_rtx; /* REG rtx for the register to be eliminated.
273 We cannot simply compare the number since
274 we might then spuriously replace a hard
275 register corresponding to a pseudo
276 assigned to the reg to be eliminated. */
277 rtx to_rtx; /* REG rtx for the replacement. */
280 static struct elim_table *reg_eliminate = 0;
282 /* This is an intermediate structure to initialize the table. It has
283 exactly the members provided by ELIMINABLE_REGS. */
284 static const struct elim_table_1
288 } reg_eliminate_1[] =
292 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
294 /* Record the number of pending eliminations that have an offset not equal
295 to their initial offset. If nonzero, we use a new copy of each
296 replacement result in any insns encountered. */
297 int num_not_at_initial_offset;
299 /* Count the number of registers that we may be able to eliminate. */
300 static int num_eliminable;
301 /* And the number of registers that are equivalent to a constant that
302 can be eliminated to frame_pointer / arg_pointer + constant. */
303 static int num_eliminable_invariants;
305 /* For each label, we record the offset of each elimination. If we reach
306 a label by more than one path and an offset differs, we cannot do the
307 elimination. This information is indexed by the difference of the
308 number of the label and the first label number. We can't offset the
309 pointer itself as this can cause problems on machines with segmented
310 memory. The first table is an array of flags that records whether we
311 have yet encountered a label and the second table is an array of arrays,
312 one entry in the latter array for each elimination. */
314 static int first_label_num;
315 static char *offsets_known_at;
316 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
318 vec<reg_equivs_t, va_gc> *reg_equivs;
320 /* Stack of addresses where an rtx has been changed. We can undo the
321 changes by popping items off the stack and restoring the original
322 value at each location.
324 We use this simplistic undo capability rather than copy_rtx as copy_rtx
325 will not make a deep copy of a normally sharable rtx, such as
326 (const (plus (symbol_ref) (const_int))). If such an expression appears
327 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
328 rtx expression would be changed. See PR 42431. */
331 static vec<rtx_p> substitute_stack;
333 /* Number of labels in the current function. */
335 static int num_labels;
337 static void replace_pseudos_in (rtx *, machine_mode, rtx);
338 static void maybe_fix_stack_asms (void);
339 static void copy_reloads (struct insn_chain *);
340 static void calculate_needs_all_insns (int);
341 static int find_reg (struct insn_chain *, int);
342 static void find_reload_regs (struct insn_chain *);
343 static void select_reload_regs (void);
344 static void delete_caller_save_insns (void);
346 static void spill_failure (rtx_insn *, enum reg_class);
347 static void count_spilled_pseudo (int, int, int);
348 static void delete_dead_insn (rtx_insn *);
349 static void alter_reg (int, int, bool);
350 static void set_label_offsets (rtx, rtx_insn *, int);
351 static void check_eliminable_occurrences (rtx);
352 static void elimination_effects (rtx, machine_mode);
353 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
354 static int eliminate_regs_in_insn (rtx_insn *, int);
355 static void update_eliminable_offsets (void);
356 static void mark_not_eliminable (rtx, const_rtx, void *);
357 static void set_initial_elim_offsets (void);
358 static bool verify_initial_elim_offsets (void);
359 static void set_initial_label_offsets (void);
360 static void set_offsets_for_label (rtx_insn *);
361 static void init_eliminable_invariants (rtx_insn *, bool);
362 static void init_elim_table (void);
363 static void free_reg_equiv (void);
364 static void update_eliminables (HARD_REG_SET *);
365 static bool update_eliminables_and_spill (void);
366 static void elimination_costs_in_insn (rtx_insn *);
367 static void spill_hard_reg (unsigned int, int);
368 static int finish_spills (int);
369 static void scan_paradoxical_subregs (rtx);
370 static void count_pseudo (int);
371 static void order_regs_for_reload (struct insn_chain *);
372 static void reload_as_needed (int);
373 static void forget_old_reloads_1 (rtx, const_rtx, void *);
374 static void forget_marked_reloads (regset);
375 static int reload_reg_class_lower (const void *, const void *);
376 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
378 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
380 static int reload_reg_free_p (unsigned int, int, enum reload_type);
381 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
383 static int free_for_value_p (int, machine_mode, int, enum reload_type,
385 static int allocate_reload_reg (struct insn_chain *, int, int);
386 static int conflicts_with_override (rtx);
387 static void failed_reload (rtx_insn *, int);
388 static int set_reload_reg (int, int);
389 static void choose_reload_regs_init (struct insn_chain *, rtx *);
390 static void choose_reload_regs (struct insn_chain *);
391 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
393 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
395 static void do_input_reload (struct insn_chain *, struct reload *, int);
396 static void do_output_reload (struct insn_chain *, struct reload *, int);
397 static void emit_reload_insns (struct insn_chain *);
398 static void delete_output_reload (rtx_insn *, int, int, rtx);
399 static void delete_address_reloads (rtx_insn *, rtx_insn *);
400 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
401 static void inc_for_reload (rtx, rtx, rtx, int);
402 static void add_auto_inc_notes (rtx_insn *, rtx);
403 static void substitute (rtx *, const_rtx, rtx);
404 static bool gen_reload_chain_without_interm_reg_p (int, int);
405 static int reloads_conflict (int, int);
406 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
407 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
409 /* Initialize the reload pass. This is called at the beginning of compilation
410 and may be called again if the target is reinitialized. */
417 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
418 Set spill_indirect_levels to the number of levels such addressing is
419 permitted, zero if it is not permitted at all. */
422 = gen_rtx_MEM (Pmode,
425 LAST_VIRTUAL_REGISTER + 1),
426 gen_int_mode (4, Pmode)));
427 spill_indirect_levels = 0;
429 while (memory_address_p (QImode, tem))
431 spill_indirect_levels++;
432 tem = gen_rtx_MEM (Pmode, tem);
435 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
438 indirect_symref_ok = memory_address_p (QImode, tem);
440 /* See if reg+reg is a valid (and offsettable) address. */
442 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
444 tem = gen_rtx_PLUS (Pmode,
445 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
446 gen_rtx_REG (Pmode, i));
448 /* This way, we make sure that reg+reg is an offsettable address. */
449 tem = plus_constant (Pmode, tem, 4);
451 for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
452 if (!double_reg_address_ok[mode]
453 && memory_address_p ((enum machine_mode)mode, tem))
454 double_reg_address_ok[mode] = 1;
457 /* Initialize obstack for our rtl allocation. */
458 if (reload_startobj == NULL)
460 gcc_obstack_init (&reload_obstack);
461 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
464 INIT_REG_SET (&spilled_pseudos);
465 INIT_REG_SET (&changed_allocation_pseudos);
466 INIT_REG_SET (&pseudos_counted);
469 /* List of insn chains that are currently unused. */
470 static struct insn_chain *unused_insn_chains = 0;
472 /* Allocate an empty insn_chain structure. */
474 new_insn_chain (void)
476 struct insn_chain *c;
478 if (unused_insn_chains == 0)
480 c = XOBNEW (&reload_obstack, struct insn_chain);
481 INIT_REG_SET (&c->live_throughout);
482 INIT_REG_SET (&c->dead_or_set);
486 c = unused_insn_chains;
487 unused_insn_chains = c->next;
489 c->is_caller_save_insn = 0;
490 c->need_operand_change = 0;
496 /* Small utility function to set all regs in hard reg set TO which are
497 allocated to pseudos in regset FROM. */
500 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
503 reg_set_iterator rsi;
505 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
507 int r = reg_renumber[regno];
511 /* reload_combine uses the information from DF_LIVE_IN,
512 which might still contain registers that have not
513 actually been allocated since they have an
515 gcc_assert (ira_conflicts_p || reload_completed);
518 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
522 /* Replace all pseudos found in LOC with their corresponding
526 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
539 unsigned int regno = REGNO (x);
541 if (regno < FIRST_PSEUDO_REGISTER)
544 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
548 replace_pseudos_in (loc, mem_mode, usage);
552 if (reg_equiv_constant (regno))
553 *loc = reg_equiv_constant (regno);
554 else if (reg_equiv_invariant (regno))
555 *loc = reg_equiv_invariant (regno);
556 else if (reg_equiv_mem (regno))
557 *loc = reg_equiv_mem (regno);
558 else if (reg_equiv_address (regno))
559 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
562 gcc_assert (!REG_P (regno_reg_rtx[regno])
563 || REGNO (regno_reg_rtx[regno]) != regno);
564 *loc = regno_reg_rtx[regno];
569 else if (code == MEM)
571 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
575 /* Process each of our operands recursively. */
576 fmt = GET_RTX_FORMAT (code);
577 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
579 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
580 else if (*fmt == 'E')
581 for (j = 0; j < XVECLEN (x, i); j++)
582 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
585 /* Determine if the current function has an exception receiver block
586 that reaches the exit block via non-exceptional edges */
589 has_nonexceptional_receiver (void)
593 basic_block *tos, *worklist, bb;
595 /* If we're not optimizing, then just err on the safe side. */
599 /* First determine which blocks can reach exit via normal paths. */
600 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
602 FOR_EACH_BB_FN (bb, cfun)
603 bb->flags &= ~BB_REACHABLE;
605 /* Place the exit block on our worklist. */
606 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
607 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
609 /* Iterate: find everything reachable from what we've already seen. */
610 while (tos != worklist)
614 FOR_EACH_EDGE (e, ei, bb->preds)
615 if (!(e->flags & EDGE_ABNORMAL))
617 basic_block src = e->src;
619 if (!(src->flags & BB_REACHABLE))
621 src->flags |= BB_REACHABLE;
628 /* Now see if there's a reachable block with an exceptional incoming
630 FOR_EACH_BB_FN (bb, cfun)
631 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
634 /* No exceptional block reached exit unexceptionally. */
638 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
639 zero elements) to MAX_REG_NUM elements.
641 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
643 grow_reg_equivs (void)
645 int old_size = vec_safe_length (reg_equivs);
646 int max_regno = max_reg_num ();
650 memset (&ze, 0, sizeof (reg_equivs_t));
651 vec_safe_reserve (reg_equivs, max_regno);
652 for (i = old_size; i < max_regno; i++)
653 reg_equivs->quick_insert (i, ze);
657 /* Global variables used by reload and its subroutines. */
659 /* The current basic block while in calculate_elim_costs_all_insns. */
660 static basic_block elim_bb;
662 /* Set during calculate_needs if an insn needs register elimination. */
663 static int something_needs_elimination;
664 /* Set during calculate_needs if an insn needs an operand changed. */
665 static int something_needs_operands_changed;
666 /* Set by alter_regs if we spilled a register to the stack. */
667 static bool something_was_spilled;
669 /* Nonzero means we couldn't get enough spill regs. */
672 /* Temporary array of pseudo-register number. */
673 static int *temp_pseudo_reg_arr;
675 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
676 If that insn didn't set the register (i.e., it copied the register to
677 memory), just delete that insn instead of the equivalencing insn plus
678 anything now dead. If we call delete_dead_insn on that insn, we may
679 delete the insn that actually sets the register if the register dies
680 there and that is incorrect. */
684 for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
686 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
689 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
691 rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
693 /* If we already deleted the insn or if it may trap, we can't
694 delete it. The latter case shouldn't happen, but can
695 if an insn has a variable address, gets a REG_EH_REGION
696 note added to it, and then gets converted into a load
697 from a constant address. */
698 if (NOTE_P (equiv_insn)
699 || can_throw_internal (equiv_insn))
701 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
702 delete_dead_insn (equiv_insn);
704 SET_INSN_DELETED (equiv_insn);
710 /* Return true if remove_init_insns will delete INSN. */
712 will_delete_init_insn_p (rtx_insn *insn)
714 rtx set = single_set (insn);
715 if (!set || !REG_P (SET_DEST (set)))
717 unsigned regno = REGNO (SET_DEST (set));
719 if (can_throw_internal (insn))
722 if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
725 for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
727 rtx equiv_insn = XEXP (list, 0);
728 if (equiv_insn == insn)
734 /* Main entry point for the reload pass.
736 FIRST is the first insn of the function being compiled.
738 GLOBAL nonzero means we were called from global_alloc
739 and should attempt to reallocate any pseudoregs that we
740 displace from hard regs we will use for reloads.
741 If GLOBAL is zero, we do not have enough information to do that,
742 so any pseudo reg that is spilled must go to the stack.
744 Return value is TRUE if reload likely left dead insns in the
745 stream and a DCE pass should be run to elimiante them. Else the
746 return value is FALSE. */
749 reload (rtx_insn *first, int global)
753 struct elim_table *ep;
757 /* Make sure even insns with volatile mem refs are recognizable. */
762 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
764 /* Make sure that the last insn in the chain
765 is not something that needs reloading. */
766 emit_note (NOTE_INSN_DELETED);
768 /* Enable find_equiv_reg to distinguish insns made by reload. */
769 reload_first_uid = get_max_uid ();
771 /* Initialize the secondary memory table. */
772 clear_secondary_mem ();
774 /* We don't have a stack slot for any spill reg yet. */
775 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
776 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
778 /* Initialize the save area information for caller-save, in case some
782 /* Compute which hard registers are now in use
783 as homes for pseudo registers.
784 This is done here rather than (eg) in global_alloc
785 because this point is reached even if not optimizing. */
786 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
789 /* A function that has a nonlocal label that can reach the exit
790 block via non-exceptional paths must save all call-saved
792 if (cfun->has_nonlocal_label
793 && has_nonexceptional_receiver ())
794 crtl->saves_all_registers = 1;
796 if (crtl->saves_all_registers)
797 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
798 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
799 df_set_regs_ever_live (i, true);
801 /* Find all the pseudo registers that didn't get hard regs
802 but do have known equivalent constants or memory slots.
803 These include parameters (known equivalent to parameter slots)
804 and cse'd or loop-moved constant memory addresses.
806 Record constant equivalents in reg_equiv_constant
807 so they will be substituted by find_reloads.
808 Record memory equivalents in reg_mem_equiv so they can
809 be substituted eventually by altering the REG-rtx's. */
812 reg_old_renumber = XCNEWVEC (short, max_regno);
813 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
814 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
815 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
817 CLEAR_HARD_REG_SET (bad_spill_regs_global);
819 init_eliminable_invariants (first, true);
822 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
823 stack slots to the pseudos that lack hard regs or equivalents.
824 Do not touch virtual registers. */
826 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
827 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
828 temp_pseudo_reg_arr[n++] = i;
831 /* Ask IRA to order pseudo-registers for better stack slot
833 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);
835 for (i = 0; i < n; i++)
836 alter_reg (temp_pseudo_reg_arr[i], -1, false);
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
844 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
846 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
848 maybe_fix_stack_asms ();
850 insns_need_reload = 0;
851 something_needs_elimination = 0;
853 /* Initialize to -1, which means take the first spill register. */
856 /* Spill any hard regs that we know we can't eliminate. */
857 CLEAR_HARD_REG_SET (used_spill_regs);
858 /* There can be multiple ways to eliminate a register;
859 they should be listed adjacently.
860 Elimination for any register fails only if all possible ways fail. */
861 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
864 int can_eliminate = 0;
867 can_eliminate |= ep->can_eliminate;
870 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
872 spill_hard_reg (from, 1);
875 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
890 HOST_WIDE_INT starting_frame_size;
892 starting_frame_size = get_frame_size ();
893 something_was_spilled = false;
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
925 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
928 if (strict_memory_address_addr_space_p
929 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
931 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
932 else if (CONSTANT_P (XEXP (x, 0))
933 || (REG_P (XEXP (x, 0))
934 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
935 || (GET_CODE (XEXP (x, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x, 0), 0))
937 && (REGNO (XEXP (XEXP (x, 0), 0))
938 < FIRST_PSEUDO_REGISTER)
939 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
940 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
949 reg_equiv_memory_loc (i) = 0;
950 reg_equiv_init (i) = 0;
951 alter_reg (i, -1, true);
955 if (caller_save_needed)
958 if (starting_frame_size && crtl->stack_alignment_needed)
960 /* If we have a stack frame, we must align it now. The
961 stack size may be a part of the offset computation for
962 register elimination. So if this changes the stack size,
963 then repeat the elimination bookkeeping. We don't
964 realign when there is no stack, as that will cause a
965 stack frame when none is needed should
966 TARGET_STARTING_FRAME_OFFSET not be already aligned to
968 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
970 /* If we allocated another stack slot, redo elimination bookkeeping. */
971 if (something_was_spilled || starting_frame_size != get_frame_size ())
973 if (update_eliminables_and_spill ())
978 if (caller_save_needed)
980 save_call_clobbered_regs ();
981 /* That might have allocated new insn_chain structures. */
982 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
985 calculate_needs_all_insns (global);
987 if (! ira_conflicts_p)
988 /* Don't do it for IRA. We need this info because we don't
989 change live_throughout and dead_or_set for chains when IRA
991 CLEAR_REG_SET (&spilled_pseudos);
993 something_changed = 0;
995 /* If we allocated any new memory locations, make another pass
996 since it might have changed elimination offsets. */
997 if (something_was_spilled || starting_frame_size != get_frame_size ())
998 something_changed = 1;
1000 /* Even if the frame size remained the same, we might still have
1001 changed elimination offsets, e.g. if find_reloads called
1002 force_const_mem requiring the back end to allocate a constant
1003 pool base register that needs to be saved on the stack. */
1004 else if (!verify_initial_elim_offsets ())
1005 something_changed = 1;
1007 if (update_eliminables_and_spill ())
1010 something_changed = 1;
1014 select_reload_regs ();
1017 if (insns_need_reload)
1018 something_changed |= finish_spills (global);
1021 if (! something_changed)
1024 if (caller_save_needed)
1025 delete_caller_save_insns ();
1027 obstack_free (&reload_obstack, reload_firstobj);
1030 /* If global-alloc was run, notify it of any register eliminations we have
1033 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1034 if (ep->can_eliminate)
1035 mark_elimination (ep->from, ep->to);
1037 remove_init_insns ();
1039 /* Use the reload registers where necessary
1040 by generating move instructions to move the must-be-register
1041 values into or out of the reload registers. */
1043 if (insns_need_reload != 0 || something_needs_elimination
1044 || something_needs_operands_changed)
1046 HOST_WIDE_INT old_frame_size = get_frame_size ();
1048 reload_as_needed (global);
1050 gcc_assert (old_frame_size == get_frame_size ());
1052 gcc_assert (verify_initial_elim_offsets ());
1055 /* If we were able to eliminate the frame pointer, show that it is no
1056 longer live at the start of any basic block. If it ls live by
1057 virtue of being in a pseudo, that pseudo will be marked live
1058 and hence the frame pointer will be known to be live via that
1061 if (! frame_pointer_needed)
1062 FOR_EACH_BB_FN (bb, cfun)
1063 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1065 /* Come here (with failure set nonzero) if we can't get enough spill
1069 CLEAR_REG_SET (&changed_allocation_pseudos);
1070 CLEAR_REG_SET (&spilled_pseudos);
1071 reload_in_progress = 0;
1073 /* Now eliminate all pseudo regs by modifying them into
1074 their equivalent memory references.
1075 The REG-rtx's for the pseudos are modified in place,
1076 so all insns that used to refer to them now refer to memory.
1078 For a reg that has a reg_equiv_address, all those insns
1079 were changed by reloading so that no insns refer to it any longer;
1080 but the DECL_RTL of a variable decl may refer to it,
1081 and if so this causes the debugging info to mention the variable. */
1083 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1087 if (reg_equiv_mem (i))
1088 addr = XEXP (reg_equiv_mem (i), 0);
1090 if (reg_equiv_address (i))
1091 addr = reg_equiv_address (i);
1095 if (reg_renumber[i] < 0)
1097 rtx reg = regno_reg_rtx[i];
1099 REG_USERVAR_P (reg) = 0;
1100 PUT_CODE (reg, MEM);
1101 XEXP (reg, 0) = addr;
1102 if (reg_equiv_memory_loc (i))
1103 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1105 MEM_ATTRS (reg) = 0;
1106 MEM_NOTRAP_P (reg) = 1;
1108 else if (reg_equiv_mem (i))
1109 XEXP (reg_equiv_mem (i), 0) = addr;
1112 /* We don't want complex addressing modes in debug insns
1113 if simpler ones will do, so delegitimize equivalences
1115 if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0)
1117 rtx reg = regno_reg_rtx[i];
1121 if (reg_equiv_constant (i))
1122 equiv = reg_equiv_constant (i);
1123 else if (reg_equiv_invariant (i))
1124 equiv = reg_equiv_invariant (i);
1125 else if (reg && MEM_P (reg))
1126 equiv = targetm.delegitimize_address (reg);
1127 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1133 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1135 insn = DF_REF_INSN (use);
1137 /* Make sure the next ref is for a different instruction,
1138 so that we're not affected by the rescan. */
1139 next = DF_REF_NEXT_REG (use);
1140 while (next && DF_REF_INSN (next) == insn)
1141 next = DF_REF_NEXT_REG (next);
1143 if (DEBUG_BIND_INSN_P (insn))
1147 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1148 df_insn_rescan_debug_internal (insn);
1151 INSN_VAR_LOCATION_LOC (insn)
1152 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1159 /* We must set reload_completed now since the cleanup_subreg_operands call
1160 below will re-recognize each insn and reload may have generated insns
1161 which are only valid during and after reload. */
1162 reload_completed = 1;
1164 /* Make a pass over all the insns and delete all USEs which we inserted
1165 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1166 notes. Delete all CLOBBER insns, except those that refer to the return
1167 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1168 from misarranging variable-array code, and simplify (subreg (reg))
1169 operands. Strip and regenerate REG_INC notes that may have been moved
1172 for (insn = first; insn; insn = NEXT_INSN (insn))
1178 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1179 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1181 if ((GET_CODE (PATTERN (insn)) == USE
1182 /* We mark with QImode USEs introduced by reload itself. */
1183 && (GET_MODE (insn) == QImode
1184 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1185 || (GET_CODE (PATTERN (insn)) == CLOBBER
1186 && (!MEM_P (XEXP (PATTERN (insn), 0))
1187 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1188 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1189 && XEXP (XEXP (PATTERN (insn), 0), 0)
1190 != stack_pointer_rtx))
1191 && (!REG_P (XEXP (PATTERN (insn), 0))
1192 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1198 /* Some CLOBBERs may survive until here and still reference unassigned
1199 pseudos with const equivalent, which may in turn cause ICE in later
1200 passes if the reference remains in place. */
1201 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1202 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1203 VOIDmode, PATTERN (insn));
1205 /* Discard obvious no-ops, even without -O. This optimization
1206 is fast and doesn't interfere with debugging. */
1207 if (NONJUMP_INSN_P (insn)
1208 && GET_CODE (PATTERN (insn)) == SET
1209 && REG_P (SET_SRC (PATTERN (insn)))
1210 && REG_P (SET_DEST (PATTERN (insn)))
1211 && (REGNO (SET_SRC (PATTERN (insn)))
1212 == REGNO (SET_DEST (PATTERN (insn)))))
1218 pnote = ®_NOTES (insn);
1221 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1222 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1223 || REG_NOTE_KIND (*pnote) == REG_INC)
1224 *pnote = XEXP (*pnote, 1);
1226 pnote = &XEXP (*pnote, 1);
1230 add_auto_inc_notes (insn, PATTERN (insn));
1232 /* Simplify (subreg (reg)) if it appears as an operand. */
1233 cleanup_subreg_operands (insn);
1235 /* Clean up invalid ASMs so that they don't confuse later passes.
1237 if (asm_noperands (PATTERN (insn)) >= 0)
1239 extract_insn (insn);
1240 if (!constrain_operands (1, get_enabled_alternatives (insn)))
1242 error_for_asm (insn,
1243 "%<asm%> operand has impossible constraints");
1250 free (temp_pseudo_reg_arr);
1252 /* Indicate that we no longer have known memory locations or constants. */
1255 free (reg_max_ref_mode);
1256 free (reg_old_renumber);
1257 free (pseudo_previous_regs);
1258 free (pseudo_forbidden_regs);
1260 CLEAR_HARD_REG_SET (used_spill_regs);
1261 for (i = 0; i < n_spills; i++)
1262 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1264 /* Free all the insn_chain structures at once. */
1265 obstack_free (&reload_obstack, reload_startobj);
1266 unused_insn_chains = 0;
1268 inserted = fixup_abnormal_edges ();
1270 /* We've possibly turned single trapping insn into multiple ones. */
1271 if (cfun->can_throw_non_call_exceptions)
1273 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
1274 bitmap_ones (blocks);
1275 find_many_sub_basic_blocks (blocks);
1279 commit_edge_insertions ();
1281 /* Replacing pseudos with their memory equivalents might have
1282 created shared rtx. Subsequent passes would get confused
1283 by this, so unshare everything here. */
1284 unshare_all_rtl_again (first);
1286 #ifdef STACK_BOUNDARY
1287 /* init_emit has set the alignment of the hard frame pointer
1288 to STACK_BOUNDARY. It is very likely no longer valid if
1289 the hard frame pointer was used for register allocation. */
1290 if (!frame_pointer_needed)
1291 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1294 substitute_stack.release ();
1296 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1298 reload_completed = !failure;
1303 /* Yet another special case. Unfortunately, reg-stack forces people to
1304 write incorrect clobbers in asm statements. These clobbers must not
1305 cause the register to appear in bad_spill_regs, otherwise we'll call
1306 fatal_insn later. We clear the corresponding regnos in the live
1307 register sets to avoid this.
1308 The whole thing is rather sick, I'm afraid. */
1311 maybe_fix_stack_asms (void)
1314 const char *constraints[MAX_RECOG_OPERANDS];
1315 machine_mode operand_mode[MAX_RECOG_OPERANDS];
1316 struct insn_chain *chain;
1318 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1321 HARD_REG_SET clobbered, allowed;
1324 if (! INSN_P (chain->insn)
1325 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1327 pat = PATTERN (chain->insn);
1328 if (GET_CODE (pat) != PARALLEL)
1331 CLEAR_HARD_REG_SET (clobbered);
1332 CLEAR_HARD_REG_SET (allowed);
1334 /* First, make a mask of all stack regs that are clobbered. */
1335 for (i = 0; i < XVECLEN (pat, 0); i++)
1337 rtx t = XVECEXP (pat, 0, i);
1338 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1339 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1342 /* Get the operand values and constraints out of the insn. */
1343 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1344 constraints, operand_mode, NULL);
1346 /* For every operand, see what registers are allowed. */
1347 for (i = 0; i < noperands; i++)
1349 const char *p = constraints[i];
1350 /* For every alternative, we compute the class of registers allowed
1351 for reloading in CLS, and merge its contents into the reg set
1353 int cls = (int) NO_REGS;
1359 if (c == '\0' || c == ',' || c == '#')
1361 /* End of one alternative - mark the regs in the current
1362 class, and reset the class. */
1363 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1369 } while (c != '\0' && c != ',');
1378 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1382 enum constraint_num cn = lookup_constraint (p);
1383 if (insn_extra_address_constraint (cn))
1384 cls = (int) reg_class_subunion[cls]
1385 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1388 cls = (int) reg_class_subunion[cls]
1389 [reg_class_for_constraint (cn)];
1392 p += CONSTRAINT_LEN (c, p);
1395 /* Those of the registers which are clobbered, but allowed by the
1396 constraints, must be usable as reload registers. So clear them
1397 out of the life information. */
1398 AND_HARD_REG_SET (allowed, clobbered);
1399 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1400 if (TEST_HARD_REG_BIT (allowed, i))
1402 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1403 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1410 /* Copy the global variables n_reloads and rld into the corresponding elts
1413 copy_reloads (struct insn_chain *chain)
1415 chain->n_reloads = n_reloads;
1416 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1417 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1418 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1421 /* Walk the chain of insns, and determine for each whether it needs reloads
1422 and/or eliminations. Build the corresponding insns_need_reload list, and
1423 set something_needs_elimination as appropriate. */
1425 calculate_needs_all_insns (int global)
1427 struct insn_chain **pprev_reload = &insns_need_reload;
1428 struct insn_chain *chain, *next = 0;
1430 something_needs_elimination = 0;
1432 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1433 for (chain = reload_insn_chain; chain != 0; chain = next)
1435 rtx_insn *insn = chain->insn;
1439 /* Clear out the shortcuts. */
1440 chain->n_reloads = 0;
1441 chain->need_elim = 0;
1442 chain->need_reload = 0;
1443 chain->need_operand_change = 0;
1445 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1446 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1447 what effects this has on the known offsets at labels. */
1449 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1450 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1451 set_label_offsets (insn, insn, 0);
1455 rtx old_body = PATTERN (insn);
1456 int old_code = INSN_CODE (insn);
1457 rtx old_notes = REG_NOTES (insn);
1458 int did_elimination = 0;
1459 int operands_changed = 0;
1461 /* Skip insns that only set an equivalence. */
1462 if (will_delete_init_insn_p (insn))
1465 /* If needed, eliminate any eliminable registers. */
1466 if (num_eliminable || num_eliminable_invariants)
1467 did_elimination = eliminate_regs_in_insn (insn, 0);
1469 /* Analyze the instruction. */
1470 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1471 global, spill_reg_order);
1473 /* If a no-op set needs more than one reload, this is likely
1474 to be something that needs input address reloads. We
1475 can't get rid of this cleanly later, and it is of no use
1476 anyway, so discard it now.
1477 We only do this when expensive_optimizations is enabled,
1478 since this complements reload inheritance / output
1479 reload deletion, and it can make debugging harder. */
1480 if (flag_expensive_optimizations && n_reloads > 1)
1482 rtx set = single_set (insn);
1485 ((SET_SRC (set) == SET_DEST (set)
1486 && REG_P (SET_SRC (set))
1487 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1488 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1489 && reg_renumber[REGNO (SET_SRC (set))] < 0
1490 && reg_renumber[REGNO (SET_DEST (set))] < 0
1491 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1492 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1493 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1494 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1496 if (ira_conflicts_p)
1497 /* Inform IRA about the insn deletion. */
1498 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1499 REGNO (SET_SRC (set)));
1501 /* Delete it from the reload chain. */
1503 chain->prev->next = next;
1505 reload_insn_chain = next;
1507 next->prev = chain->prev;
1508 chain->next = unused_insn_chains;
1509 unused_insn_chains = chain;
1514 update_eliminable_offsets ();
1516 /* Remember for later shortcuts which insns had any reloads or
1517 register eliminations. */
1518 chain->need_elim = did_elimination;
1519 chain->need_reload = n_reloads > 0;
1520 chain->need_operand_change = operands_changed;
1522 /* Discard any register replacements done. */
1523 if (did_elimination)
1525 obstack_free (&reload_obstack, reload_insn_firstobj);
1526 PATTERN (insn) = old_body;
1527 INSN_CODE (insn) = old_code;
1528 REG_NOTES (insn) = old_notes;
1529 something_needs_elimination = 1;
1532 something_needs_operands_changed |= operands_changed;
1536 copy_reloads (chain);
1537 *pprev_reload = chain;
1538 pprev_reload = &chain->next_need_reload;
1545 /* This function is called from the register allocator to set up estimates
1546 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1547 an invariant. The structure is similar to calculate_needs_all_insns. */
1550 calculate_elim_costs_all_insns (void)
1552 int *reg_equiv_init_cost;
1556 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1558 init_eliminable_invariants (get_insns (), false);
1560 set_initial_elim_offsets ();
1561 set_initial_label_offsets ();
1563 FOR_EACH_BB_FN (bb, cfun)
1568 FOR_BB_INSNS (bb, insn)
1570 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1571 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1572 what effects this has on the known offsets at labels. */
1574 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1575 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1576 set_label_offsets (insn, insn, 0);
1580 rtx set = single_set (insn);
1582 /* Skip insns that only set an equivalence. */
1583 if (set && REG_P (SET_DEST (set))
1584 && reg_renumber[REGNO (SET_DEST (set))] < 0
1585 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1586 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1588 unsigned regno = REGNO (SET_DEST (set));
1589 rtx_insn_list *init = reg_equiv_init (regno);
1592 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1594 machine_mode mode = GET_MODE (SET_DEST (set));
1595 int cost = set_src_cost (t, mode,
1596 optimize_bb_for_speed_p (bb));
1597 int freq = REG_FREQ_FROM_BB (bb);
1599 reg_equiv_init_cost[regno] = cost * freq;
1603 /* If needed, eliminate any eliminable registers. */
1604 if (num_eliminable || num_eliminable_invariants)
1605 elimination_costs_in_insn (insn);
1608 update_eliminable_offsets ();
1612 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1614 if (reg_equiv_invariant (i))
1616 if (reg_equiv_init (i))
1618 int cost = reg_equiv_init_cost[i];
1621 "Reg %d has equivalence, initial gains %d\n", i, cost);
1623 ira_adjust_equiv_reg_cost (i, cost);
1629 "Reg %d had equivalence, but can't be eliminated\n",
1631 ira_adjust_equiv_reg_cost (i, 0);
1636 free (reg_equiv_init_cost);
1637 free (offsets_known_at);
1640 offsets_known_at = NULL;
1643 /* Comparison function for qsort to decide which of two reloads
1644 should be handled first. *P1 and *P2 are the reload numbers. */
1647 reload_reg_class_lower (const void *r1p, const void *r2p)
1649 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1652 /* Consider required reloads before optional ones. */
1653 t = rld[r1].optional - rld[r2].optional;
1657 /* Count all solitary classes before non-solitary ones. */
1658 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1659 - (reg_class_size[(int) rld[r1].rclass] == 1));
1663 /* Aside from solitaires, consider all multi-reg groups first. */
1664 t = rld[r2].nregs - rld[r1].nregs;
1668 /* Consider reloads in order of increasing reg-class number. */
1669 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1673 /* If reloads are equally urgent, sort by reload number,
1674 so that the results of qsort leave nothing to chance. */
1678 /* The cost of spilling each hard reg. */
1679 static int spill_cost[FIRST_PSEUDO_REGISTER];
1681 /* When spilling multiple hard registers, we use SPILL_COST for the first
1682 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1683 only the first hard reg for a multi-reg pseudo. */
1684 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1686 /* Map of hard regno to pseudo regno currently occupying the hard
1688 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1690 /* Update the spill cost arrays, considering that pseudo REG is live. */
1693 count_pseudo (int reg)
1695 int freq = REG_FREQ (reg);
1696 int r = reg_renumber[reg];
1699 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1700 if (ira_conflicts_p && r < 0)
1703 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1704 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1707 SET_REGNO_REG_SET (&pseudos_counted, reg);
1709 gcc_assert (r >= 0);
1711 spill_add_cost[r] += freq;
1712 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1715 hard_regno_to_pseudo_regno[r + nregs] = reg;
1716 spill_cost[r + nregs] += freq;
1720 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1721 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1724 order_regs_for_reload (struct insn_chain *chain)
1727 HARD_REG_SET used_by_pseudos;
1728 HARD_REG_SET used_by_pseudos2;
1729 reg_set_iterator rsi;
1731 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1733 memset (spill_cost, 0, sizeof spill_cost);
1734 memset (spill_add_cost, 0, sizeof spill_add_cost);
1735 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1736 hard_regno_to_pseudo_regno[i] = -1;
1738 /* Count number of uses of each hard reg by pseudo regs allocated to it
1739 and then order them by decreasing use. First exclude hard registers
1740 that are live in or across this insn. */
1742 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1743 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1744 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1745 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1747 /* Now find out which pseudos are allocated to it, and update
1749 CLEAR_REG_SET (&pseudos_counted);
1751 EXECUTE_IF_SET_IN_REG_SET
1752 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1756 EXECUTE_IF_SET_IN_REG_SET
1757 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1761 CLEAR_REG_SET (&pseudos_counted);
1764 /* Vector of reload-numbers showing the order in which the reloads should
1766 static short reload_order[MAX_RELOADS];
1768 /* This is used to keep track of the spill regs used in one insn. */
1769 static HARD_REG_SET used_spill_regs_local;
1771 /* We decided to spill hard register SPILLED, which has a size of
1772 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1773 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1774 update SPILL_COST/SPILL_ADD_COST. */
1777 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1779 int freq = REG_FREQ (reg);
1780 int r = reg_renumber[reg];
1783 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1784 if (ira_conflicts_p && r < 0)
1787 gcc_assert (r >= 0);
1789 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1791 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1792 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1795 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1797 spill_add_cost[r] -= freq;
1800 hard_regno_to_pseudo_regno[r + nregs] = -1;
1801 spill_cost[r + nregs] -= freq;
1805 /* Find reload register to use for reload number ORDER. */
1808 find_reg (struct insn_chain *chain, int order)
1810 int rnum = reload_order[order];
1811 struct reload *rl = rld + rnum;
1812 int best_cost = INT_MAX;
1814 unsigned int i, j, n;
1816 HARD_REG_SET not_usable;
1817 HARD_REG_SET used_by_other_reload;
1818 reg_set_iterator rsi;
1819 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1820 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1822 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1823 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1824 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1826 CLEAR_HARD_REG_SET (used_by_other_reload);
1827 for (k = 0; k < order; k++)
1829 int other = reload_order[k];
1831 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1832 for (j = 0; j < rld[other].nregs; j++)
1833 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1836 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1838 #ifdef REG_ALLOC_ORDER
1839 unsigned int regno = reg_alloc_order[i];
1841 unsigned int regno = i;
1844 if (! TEST_HARD_REG_BIT (not_usable, regno)
1845 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1846 && targetm.hard_regno_mode_ok (regno, rl->mode))
1848 int this_cost = spill_cost[regno];
1850 unsigned int this_nregs = hard_regno_nregs (regno, rl->mode);
1852 for (j = 1; j < this_nregs; j++)
1854 this_cost += spill_add_cost[regno + j];
1855 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1856 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1862 if (ira_conflicts_p)
1864 /* Ask IRA to find a better pseudo-register for
1866 for (n = j = 0; j < this_nregs; j++)
1868 int r = hard_regno_to_pseudo_regno[regno + j];
1872 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1873 regno_pseudo_regs[n++] = r;
1875 regno_pseudo_regs[n++] = -1;
1877 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1878 best_regno_pseudo_regs,
1885 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1886 if (regno_pseudo_regs[j] < 0)
1893 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1895 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1897 if (this_cost < best_cost
1898 /* Among registers with equal cost, prefer caller-saved ones, or
1899 use REG_ALLOC_ORDER if it is defined. */
1900 || (this_cost == best_cost
1901 #ifdef REG_ALLOC_ORDER
1902 && (inv_reg_alloc_order[regno]
1903 < inv_reg_alloc_order[best_reg])
1905 && call_used_regs[regno]
1906 && ! call_used_regs[best_reg]
1911 best_cost = this_cost;
1919 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1921 rl->nregs = hard_regno_nregs (best_reg, rl->mode);
1922 rl->regno = best_reg;
1924 EXECUTE_IF_SET_IN_REG_SET
1925 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1927 count_spilled_pseudo (best_reg, rl->nregs, j);
1930 EXECUTE_IF_SET_IN_REG_SET
1931 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1933 count_spilled_pseudo (best_reg, rl->nregs, j);
1936 for (i = 0; i < rl->nregs; i++)
1938 gcc_assert (spill_cost[best_reg + i] == 0);
1939 gcc_assert (spill_add_cost[best_reg + i] == 0);
1940 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1941 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1946 /* Find more reload regs to satisfy the remaining need of an insn, which
1948 Do it by ascending class number, since otherwise a reg
1949 might be spilled for a big class and might fail to count
1950 for a smaller class even though it belongs to that class. */
1953 find_reload_regs (struct insn_chain *chain)
1957 /* In order to be certain of getting the registers we need,
1958 we must sort the reloads into order of increasing register class.
1959 Then our grabbing of reload registers will parallel the process
1960 that provided the reload registers. */
1961 for (i = 0; i < chain->n_reloads; i++)
1963 /* Show whether this reload already has a hard reg. */
1964 if (chain->rld[i].reg_rtx)
1966 chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx);
1967 chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx);
1970 chain->rld[i].regno = -1;
1971 reload_order[i] = i;
1974 n_reloads = chain->n_reloads;
1975 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1977 CLEAR_HARD_REG_SET (used_spill_regs_local);
1980 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1982 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1984 /* Compute the order of preference for hard registers to spill. */
1986 order_regs_for_reload (chain);
1988 for (i = 0; i < n_reloads; i++)
1990 int r = reload_order[i];
1992 /* Ignore reloads that got marked inoperative. */
1993 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1994 && ! rld[r].optional
1995 && rld[r].regno == -1)
1996 if (! find_reg (chain, i))
1999 fprintf (dump_file, "reload failure for reload %d\n", r);
2000 spill_failure (chain->insn, rld[r].rclass);
2006 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2007 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2009 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2013 select_reload_regs (void)
2015 struct insn_chain *chain;
2017 /* Try to satisfy the needs for each insn. */
2018 for (chain = insns_need_reload; chain != 0;
2019 chain = chain->next_need_reload)
2020 find_reload_regs (chain);
2023 /* Delete all insns that were inserted by emit_caller_save_insns during
2026 delete_caller_save_insns (void)
2028 struct insn_chain *c = reload_insn_chain;
2032 while (c != 0 && c->is_caller_save_insn)
2034 struct insn_chain *next = c->next;
2035 rtx_insn *insn = c->insn;
2037 if (c == reload_insn_chain)
2038 reload_insn_chain = next;
2042 next->prev = c->prev;
2044 c->prev->next = next;
2045 c->next = unused_insn_chains;
2046 unused_insn_chains = c;
2054 /* Handle the failure to find a register to spill.
2055 INSN should be one of the insns which needed this particular spill reg. */
2058 spill_failure (rtx_insn *insn, enum reg_class rclass)
2060 if (asm_noperands (PATTERN (insn)) >= 0)
2061 error_for_asm (insn, "can%'t find a register in class %qs while "
2062 "reloading %<asm%>",
2063 reg_class_names[rclass]);
2066 error ("unable to find a register to spill in class %qs",
2067 reg_class_names[rclass]);
2071 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2072 debug_reload_to_stream (dump_file);
2074 fatal_insn ("this is the insn:", insn);
2078 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2079 data that is dead in INSN. */
2082 delete_dead_insn (rtx_insn *insn)
2084 rtx_insn *prev = prev_active_insn (insn);
2087 /* If the previous insn sets a register that dies in our insn make
2088 a note that we want to run DCE immediately after reload.
2090 We used to delete the previous insn & recurse, but that's wrong for
2091 block local equivalences. Instead of trying to figure out the exact
2092 circumstances where we can delete the potentially dead insns, just
2093 let DCE do the job. */
2094 if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2095 && GET_CODE (PATTERN (prev)) == SET
2096 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2097 && reg_mentioned_p (prev_dest, PATTERN (insn))
2098 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2099 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2102 SET_INSN_DELETED (insn);
2105 /* Modify the home of pseudo-reg I.
2106 The new home is present in reg_renumber[I].
2108 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2109 or it may be -1, meaning there is none or it is not relevant.
2110 This is used so that all pseudos spilled from a given hard reg
2111 can share one stack slot. */
2114 alter_reg (int i, int from_reg, bool dont_share_p)
2116 /* When outputting an inline function, this can happen
2117 for a reg that isn't actually used. */
2118 if (regno_reg_rtx[i] == 0)
2121 /* If the reg got changed to a MEM at rtl-generation time,
2123 if (!REG_P (regno_reg_rtx[i]))
2126 /* Modify the reg-rtx to contain the new hard reg
2127 number or else to contain its pseudo reg number. */
2128 SET_REGNO (regno_reg_rtx[i],
2129 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2131 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2132 allocate a stack slot for it. */
2134 if (reg_renumber[i] < 0
2135 && REG_N_REFS (i) > 0
2136 && reg_equiv_constant (i) == 0
2137 && (reg_equiv_invariant (i) == 0
2138 || reg_equiv_init (i) == 0)
2139 && reg_equiv_memory_loc (i) == 0)
2142 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2143 unsigned HOST_WIDE_INT inherent_size = PSEUDO_REGNO_BYTES (i);
2144 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2145 machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
2146 unsigned HOST_WIDE_INT total_size = GET_MODE_SIZE (wider_mode);
2147 unsigned int min_align = GET_MODE_BITSIZE (reg_max_ref_mode[i]);
2148 poly_int64 adjust = 0;
2150 something_was_spilled = true;
2152 if (ira_conflicts_p)
2154 /* Mark the spill for IRA. */
2155 SET_REGNO_REG_SET (&spilled_pseudos, i);
2157 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2163 /* Each pseudo reg has an inherent size which comes from its own mode,
2164 and a total size which provides room for paradoxical subregs
2165 which refer to the pseudo reg in wider modes.
2167 We can use a slot already allocated if it provides both
2168 enough inherent space and enough total space.
2169 Otherwise, we allocate a new slot, making sure that it has no less
2170 inherent space, and no less total space, then the previous slot. */
2171 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2175 /* No known place to spill from => no slot to reuse. */
2176 x = assign_stack_local (mode, total_size,
2177 min_align > inherent_align
2178 || total_size > inherent_size ? -1 : 0);
2182 /* Cancel the big-endian correction done in assign_stack_local.
2183 Get the address of the beginning of the slot. This is so we
2184 can do a big-endian correction unconditionally below. */
2185 if (BYTES_BIG_ENDIAN)
2187 adjust = inherent_size - total_size;
2188 if (maybe_ne (adjust, 0))
2190 unsigned int total_bits = total_size * BITS_PER_UNIT;
2191 machine_mode mem_mode
2192 = int_mode_for_size (total_bits, 1).else_blk ();
2193 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2197 if (! dont_share_p && ira_conflicts_p)
2198 /* Inform IRA about allocation a new stack slot. */
2199 ira_mark_new_stack_slot (stack_slot, i, total_size);
2202 /* Reuse a stack slot if possible. */
2203 else if (spill_stack_slot[from_reg] != 0
2204 && spill_stack_slot_width[from_reg] >= total_size
2205 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2207 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2208 x = spill_stack_slot[from_reg];
2210 /* Allocate a bigger slot. */
2213 /* Compute maximum size needed, both for inherent size
2214 and for total size. */
2217 if (spill_stack_slot[from_reg])
2219 if (partial_subreg_p (mode,
2220 GET_MODE (spill_stack_slot[from_reg])))
2221 mode = GET_MODE (spill_stack_slot[from_reg]);
2222 if (spill_stack_slot_width[from_reg] > total_size)
2223 total_size = spill_stack_slot_width[from_reg];
2224 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2225 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2228 /* Make a slot with that size. */
2229 x = assign_stack_local (mode, total_size,
2230 min_align > inherent_align
2231 || total_size > inherent_size ? -1 : 0);
2234 /* Cancel the big-endian correction done in assign_stack_local.
2235 Get the address of the beginning of the slot. This is so we
2236 can do a big-endian correction unconditionally below. */
2237 if (BYTES_BIG_ENDIAN)
2239 adjust = GET_MODE_SIZE (mode) - total_size;
2240 if (maybe_ne (adjust, 0))
2242 unsigned int total_bits = total_size * BITS_PER_UNIT;
2243 machine_mode mem_mode
2244 = int_mode_for_size (total_bits, 1).else_blk ();
2245 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2249 spill_stack_slot[from_reg] = stack_slot;
2250 spill_stack_slot_width[from_reg] = total_size;
2253 /* On a big endian machine, the "address" of the slot
2254 is the address of the low part that fits its inherent mode. */
2255 adjust += subreg_size_lowpart_offset (inherent_size, total_size);
2257 /* If we have any adjustment to make, or if the stack slot is the
2258 wrong mode, make a new stack slot. */
2259 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2261 /* Set all of the memory attributes as appropriate for a spill. */
2262 set_mem_attrs_for_spill (x);
2264 /* Save the stack slot for later. */
2265 reg_equiv_memory_loc (i) = x;
2269 /* Mark the slots in regs_ever_live for the hard regs used by
2270 pseudo-reg number REGNO, accessed in MODE. */
2273 mark_home_live_1 (int regno, machine_mode mode)
2277 i = reg_renumber[regno];
2280 lim = end_hard_regno (mode, i);
2282 df_set_regs_ever_live (i++, true);
2285 /* Mark the slots in regs_ever_live for the hard regs
2286 used by pseudo-reg number REGNO. */
2289 mark_home_live (int regno)
2291 if (reg_renumber[regno] >= 0)
2292 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2295 /* This function handles the tracking of elimination offsets around branches.
2297 X is a piece of RTL being scanned.
2299 INSN is the insn that it came from, if any.
2301 INITIAL_P is nonzero if we are to set the offset to be the initial
2302 offset and zero if we are setting the offset of the label to be the
2306 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2308 enum rtx_code code = GET_CODE (x);
2311 struct elim_table *p;
2316 if (LABEL_REF_NONLOCAL_P (x))
2319 x = label_ref_label (x);
2324 /* If we know nothing about this label, set the desired offsets. Note
2325 that this sets the offset at a label to be the offset before a label
2326 if we don't know anything about the label. This is not correct for
2327 the label after a BARRIER, but is the best guess we can make. If
2328 we guessed wrong, we will suppress an elimination that might have
2329 been possible had we been able to guess correctly. */
2331 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2333 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2334 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2335 = (initial_p ? reg_eliminate[i].initial_offset
2336 : reg_eliminate[i].offset);
2337 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2340 /* Otherwise, if this is the definition of a label and it is
2341 preceded by a BARRIER, set our offsets to the known offset of
2345 && (tem = prev_nonnote_insn (insn)) != 0
2347 set_offsets_for_label (insn);
2349 /* If neither of the above cases is true, compare each offset
2350 with those previously recorded and suppress any eliminations
2351 where the offsets disagree. */
2353 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2354 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2355 != (initial_p ? reg_eliminate[i].initial_offset
2356 : reg_eliminate[i].offset))
2357 reg_eliminate[i].can_eliminate = 0;
2361 case JUMP_TABLE_DATA:
2362 set_label_offsets (PATTERN (insn), insn, initial_p);
2366 set_label_offsets (PATTERN (insn), insn, initial_p);
2372 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2373 to indirectly and hence must have all eliminations at their
2375 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2376 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2377 set_label_offsets (XEXP (tem, 0), insn, 1);
2383 /* Each of the labels in the parallel or address vector must be
2384 at their initial offsets. We want the first field for PARALLEL
2385 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2387 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2388 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2393 /* We only care about setting PC. If the source is not RETURN,
2394 IF_THEN_ELSE, or a label, disable any eliminations not at
2395 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2396 isn't one of those possibilities. For branches to a label,
2397 call ourselves recursively.
2399 Note that this can disable elimination unnecessarily when we have
2400 a non-local goto since it will look like a non-constant jump to
2401 someplace in the current function. This isn't a significant
2402 problem since such jumps will normally be when all elimination
2403 pairs are back to their initial offsets. */
2405 if (SET_DEST (x) != pc_rtx)
2408 switch (GET_CODE (SET_SRC (x)))
2415 set_label_offsets (SET_SRC (x), insn, initial_p);
2419 tem = XEXP (SET_SRC (x), 1);
2420 if (GET_CODE (tem) == LABEL_REF)
2421 set_label_offsets (label_ref_label (tem), insn, initial_p);
2422 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2425 tem = XEXP (SET_SRC (x), 2);
2426 if (GET_CODE (tem) == LABEL_REF)
2427 set_label_offsets (label_ref_label (tem), insn, initial_p);
2428 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2436 /* If we reach here, all eliminations must be at their initial
2437 offset because we are doing a jump to a variable address. */
2438 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2439 if (p->offset != p->initial_offset)
2440 p->can_eliminate = 0;
2448 /* This function examines every reg that occurs in X and adjusts the
2449 costs for its elimination which are gathered by IRA. INSN is the
2450 insn in which X occurs. We do not recurse into MEM expressions. */
2453 note_reg_elim_costly (const_rtx x, rtx insn)
2455 subrtx_iterator::array_type array;
2456 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2458 const_rtx x = *iter;
2460 iter.skip_subrtxes ();
2462 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2463 && reg_equiv_init (REGNO (x))
2464 && reg_equiv_invariant (REGNO (x)))
2466 rtx t = reg_equiv_invariant (REGNO (x));
2467 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2468 int cost = set_src_cost (new_rtx, Pmode,
2469 optimize_bb_for_speed_p (elim_bb));
2470 int freq = REG_FREQ_FROM_BB (elim_bb);
2473 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2478 /* Scan X and replace any eliminable registers (such as fp) with a
2479 replacement (such as sp), plus an offset.
2481 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2482 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2483 MEM, we are allowed to replace a sum of a register and the constant zero
2484 with the register, which we cannot do outside a MEM. In addition, we need
2485 to record the fact that a register is referenced outside a MEM.
2487 If INSN is an insn, it is the insn containing X. If we replace a REG
2488 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2489 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2490 the REG is being modified.
2492 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2493 That's used when we eliminate in expressions stored in notes.
2494 This means, do not set ref_outside_mem even if the reference
2497 If FOR_COSTS is true, we are being called before reload in order to
2498 estimate the costs of keeping registers with an equivalence unallocated.
2500 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2501 replacements done assuming all offsets are at their initial values. If
2502 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2503 encounter, return the actual location so that find_reloads will do
2504 the proper thing. */
2507 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2508 bool may_use_invariant, bool for_costs)
2510 enum rtx_code code = GET_CODE (x);
2511 struct elim_table *ep;
2518 if (! current_function_decl)
2538 /* First handle the case where we encounter a bare register that
2539 is eliminable. Replace it with a PLUS. */
2540 if (regno < FIRST_PSEUDO_REGISTER)
2542 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2544 if (ep->from_rtx == x && ep->can_eliminate)
2545 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2548 else if (reg_renumber && reg_renumber[regno] < 0
2550 && reg_equiv_invariant (regno))
2552 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2553 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2554 mem_mode, insn, true, for_costs);
2555 /* There exists at least one use of REGNO that cannot be
2556 eliminated. Prevent the defining insn from being deleted. */
2557 reg_equiv_init (regno) = NULL;
2559 alter_reg (regno, -1, true);
2563 /* You might think handling MINUS in a manner similar to PLUS is a
2564 good idea. It is not. It has been tried multiple times and every
2565 time the change has had to have been reverted.
2567 Other parts of reload know a PLUS is special (gen_reload for example)
2568 and require special code to handle code a reloaded PLUS operand.
2570 Also consider backends where the flags register is clobbered by a
2571 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2572 lea instruction comes to mind). If we try to reload a MINUS, we
2573 may kill the flags register that was holding a useful value.
2575 So, please before trying to handle MINUS, consider reload as a
2576 whole instead of this little section as well as the backend issues. */
2578 /* If this is the sum of an eliminable register and a constant, rework
2580 if (REG_P (XEXP (x, 0))
2581 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2582 && CONSTANT_P (XEXP (x, 1)))
2584 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2586 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2588 /* The only time we want to replace a PLUS with a REG (this
2589 occurs when the constant operand of the PLUS is the negative
2590 of the offset) is when we are inside a MEM. We won't want
2591 to do so at other times because that would change the
2592 structure of the insn in a way that reload can't handle.
2593 We special-case the commonest situation in
2594 eliminate_regs_in_insn, so just replace a PLUS with a
2595 PLUS here, unless inside a MEM. */
2596 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2597 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2600 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2601 plus_constant (Pmode, XEXP (x, 1),
2602 ep->previous_offset));
2605 /* If the register is not eliminable, we are done since the other
2606 operand is a constant. */
2610 /* If this is part of an address, we want to bring any constant to the
2611 outermost PLUS. We will do this by doing register replacement in
2612 our operands and seeing if a constant shows up in one of them.
2614 Note that there is no risk of modifying the structure of the insn,
2615 since we only get called for its operands, thus we are either
2616 modifying the address inside a MEM, or something like an address
2617 operand of a load-address insn. */
2620 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2622 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2625 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2627 /* If one side is a PLUS and the other side is a pseudo that
2628 didn't get a hard register but has a reg_equiv_constant,
2629 we must replace the constant here since it may no longer
2630 be in the position of any operand. */
2631 if (GET_CODE (new0) == PLUS && REG_P (new1)
2632 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2633 && reg_renumber[REGNO (new1)] < 0
2635 && reg_equiv_constant (REGNO (new1)) != 0)
2636 new1 = reg_equiv_constant (REGNO (new1));
2637 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2638 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2639 && reg_renumber[REGNO (new0)] < 0
2640 && reg_equiv_constant (REGNO (new0)) != 0)
2641 new0 = reg_equiv_constant (REGNO (new0));
2643 new_rtx = form_sum (GET_MODE (x), new0, new1);
2645 /* As above, if we are not inside a MEM we do not want to
2646 turn a PLUS into something else. We might try to do so here
2647 for an addition of 0 if we aren't optimizing. */
2648 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2649 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2657 /* If this is the product of an eliminable register and a
2658 constant, apply the distribute law and move the constant out
2659 so that we have (plus (mult ..) ..). This is needed in order
2660 to keep load-address insns valid. This case is pathological.
2661 We ignore the possibility of overflow here. */
2662 if (REG_P (XEXP (x, 0))
2663 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2664 && CONST_INT_P (XEXP (x, 1)))
2665 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2667 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2670 /* Refs inside notes or in DEBUG_INSNs don't count for
2672 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2673 || GET_CODE (insn) == INSN_LIST
2674 || DEBUG_INSN_P (insn))))
2675 ep->ref_outside_mem = 1;
2678 plus_constant (Pmode,
2679 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2680 ep->previous_offset * INTVAL (XEXP (x, 1)));
2687 /* See comments before PLUS about handling MINUS. */
2689 case DIV: case UDIV:
2690 case MOD: case UMOD:
2691 case AND: case IOR: case XOR:
2692 case ROTATERT: case ROTATE:
2693 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2695 case GE: case GT: case GEU: case GTU:
2696 case LE: case LT: case LEU: case LTU:
2698 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2700 rtx new1 = XEXP (x, 1)
2701 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2704 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2705 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2710 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2713 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2715 if (new_rtx != XEXP (x, 0))
2717 /* If this is a REG_DEAD note, it is not valid anymore.
2718 Using the eliminated version could result in creating a
2719 REG_DEAD note for the stack or frame pointer. */
2720 if (REG_NOTE_KIND (x) == REG_DEAD)
2722 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2726 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2734 /* Now do eliminations in the rest of the chain. If this was
2735 an EXPR_LIST, this might result in allocating more memory than is
2736 strictly needed, but it simplifies the code. */
2739 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2741 if (new_rtx != XEXP (x, 1))
2743 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2751 /* We do not support elimination of a register that is modified.
2752 elimination_effects has already make sure that this does not
2758 /* We do not support elimination of a register that is modified.
2759 elimination_effects has already make sure that this does not
2760 happen. The only remaining case we need to consider here is
2761 that the increment value may be an eliminable register. */
2762 if (GET_CODE (XEXP (x, 1)) == PLUS
2763 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2765 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2766 insn, true, for_costs);
2768 if (new_rtx != XEXP (XEXP (x, 1), 1))
2769 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2770 gen_rtx_PLUS (GET_MODE (x),
2771 XEXP (x, 0), new_rtx));
2775 case STRICT_LOW_PART:
2777 case SIGN_EXTEND: case ZERO_EXTEND:
2778 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2779 case FLOAT: case FIX:
2780 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2789 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2791 if (new_rtx != XEXP (x, 0))
2792 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2796 /* Similar to above processing, but preserve SUBREG_BYTE.
2797 Convert (subreg (mem)) to (mem) if not paradoxical.
2798 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2799 pseudo didn't get a hard reg, we must replace this with the
2800 eliminated version of the memory location because push_reload
2801 may do the replacement in certain circumstances. */
2802 if (REG_P (SUBREG_REG (x))
2803 && !paradoxical_subreg_p (x)
2805 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2807 new_rtx = SUBREG_REG (x);
2810 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2812 if (new_rtx != SUBREG_REG (x))
2814 int x_size = GET_MODE_SIZE (GET_MODE (x));
2815 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2818 && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx))
2819 /* On RISC machines, combine can create rtl of the form
2820 (set (subreg:m1 (reg:m2 R) 0) ...)
2821 where m1 < m2, and expects something interesting to
2822 happen to the entire word. Moreover, it will use the
2823 (reg:m2 R) later, expecting all bits to be preserved.
2824 So if the number of words is the same, preserve the
2825 subreg so that push_reload can see it. */
2826 && !(WORD_REGISTER_OPERATIONS
2827 && (x_size - 1) / UNITS_PER_WORD
2828 == (new_size -1 ) / UNITS_PER_WORD))
2829 || x_size == new_size)
2831 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2832 else if (insn && GET_CODE (insn) == DEBUG_INSN)
2833 return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2835 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2841 /* Our only special processing is to pass the mode of the MEM to our
2842 recursive call and copy the flags. While we are here, handle this
2843 case more efficiently. */
2845 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2848 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2849 && !memory_address_p (GET_MODE (x), new_rtx))
2850 note_reg_elim_costly (XEXP (x, 0), insn);
2852 return replace_equiv_address_nv (x, new_rtx);
2855 /* Handle insn_list USE that a call to a pure function may generate. */
2856 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2858 if (new_rtx != XEXP (x, 0))
2859 return gen_rtx_USE (GET_MODE (x), new_rtx);
2864 gcc_assert (insn && DEBUG_INSN_P (insn));
2874 /* Process each of our operands recursively. If any have changed, make a
2876 fmt = GET_RTX_FORMAT (code);
2877 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2881 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2883 if (new_rtx != XEXP (x, i) && ! copied)
2885 x = shallow_copy_rtx (x);
2888 XEXP (x, i) = new_rtx;
2890 else if (*fmt == 'E')
2893 for (j = 0; j < XVECLEN (x, i); j++)
2895 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2897 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2899 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2903 x = shallow_copy_rtx (x);
2906 XVEC (x, i) = new_v;
2909 XVECEXP (x, i, j) = new_rtx;
2918 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2920 if (reg_eliminate == NULL)
2922 gcc_assert (targetm.no_register_allocation);
2925 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2928 /* Scan rtx X for modifications of elimination target registers. Update
2929 the table of eliminables to reflect the changed state. MEM_MODE is
2930 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2933 elimination_effects (rtx x, machine_mode mem_mode)
2935 enum rtx_code code = GET_CODE (x);
2936 struct elim_table *ep;
2958 /* First handle the case where we encounter a bare register that
2959 is eliminable. Replace it with a PLUS. */
2960 if (regno < FIRST_PSEUDO_REGISTER)
2962 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2964 if (ep->from_rtx == x && ep->can_eliminate)
2967 ep->ref_outside_mem = 1;
2972 else if (reg_renumber[regno] < 0
2974 && reg_equiv_constant (regno)
2975 && ! function_invariant_p (reg_equiv_constant (regno)))
2976 elimination_effects (reg_equiv_constant (regno), mem_mode);
2985 /* If we modify the source of an elimination rule, disable it. */
2986 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2987 if (ep->from_rtx == XEXP (x, 0))
2988 ep->can_eliminate = 0;
2990 /* If we modify the target of an elimination rule by adding a constant,
2991 update its offset. If we modify the target in any other way, we'll
2992 have to disable the rule as well. */
2993 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2994 if (ep->to_rtx == XEXP (x, 0))
2996 int size = GET_MODE_SIZE (mem_mode);
2998 /* If more bytes than MEM_MODE are pushed, account for them. */
2999 #ifdef PUSH_ROUNDING
3000 if (ep->to_rtx == stack_pointer_rtx)
3001 size = PUSH_ROUNDING (size);
3003 if (code == PRE_DEC || code == POST_DEC)
3005 else if (code == PRE_INC || code == POST_INC)
3007 else if (code == PRE_MODIFY || code == POST_MODIFY)
3009 if (GET_CODE (XEXP (x, 1)) == PLUS
3010 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3011 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3012 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3014 ep->can_eliminate = 0;
3018 /* These two aren't unary operators. */
3019 if (code == POST_MODIFY || code == PRE_MODIFY)
3022 /* Fall through to generic unary operation case. */
3024 case STRICT_LOW_PART:
3026 case SIGN_EXTEND: case ZERO_EXTEND:
3027 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3028 case FLOAT: case FIX:
3029 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3038 elimination_effects (XEXP (x, 0), mem_mode);
3042 if (REG_P (SUBREG_REG (x))
3043 && !paradoxical_subreg_p (x)
3045 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3048 elimination_effects (SUBREG_REG (x), mem_mode);
3052 /* If using a register that is the source of an eliminate we still
3053 think can be performed, note it cannot be performed since we don't
3054 know how this register is used. */
3055 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3056 if (ep->from_rtx == XEXP (x, 0))
3057 ep->can_eliminate = 0;
3059 elimination_effects (XEXP (x, 0), mem_mode);
3063 /* If clobbering a register that is the replacement register for an
3064 elimination we still think can be performed, note that it cannot
3065 be performed. Otherwise, we need not be concerned about it. */
3066 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3067 if (ep->to_rtx == XEXP (x, 0))
3068 ep->can_eliminate = 0;
3070 elimination_effects (XEXP (x, 0), mem_mode);
3074 /* Check for setting a register that we know about. */
3075 if (REG_P (SET_DEST (x)))
3077 /* See if this is setting the replacement register for an
3080 If DEST is the hard frame pointer, we do nothing because we
3081 assume that all assignments to the frame pointer are for
3082 non-local gotos and are being done at a time when they are valid
3083 and do not disturb anything else. Some machines want to
3084 eliminate a fake argument pointer (or even a fake frame pointer)
3085 with either the real frame or the stack pointer. Assignments to
3086 the hard frame pointer must not prevent this elimination. */
3088 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3090 if (ep->to_rtx == SET_DEST (x)
3091 && SET_DEST (x) != hard_frame_pointer_rtx)
3093 /* If it is being incremented, adjust the offset. Otherwise,
3094 this elimination can't be done. */
3095 rtx src = SET_SRC (x);
3097 if (GET_CODE (src) == PLUS
3098 && XEXP (src, 0) == SET_DEST (x)
3099 && CONST_INT_P (XEXP (src, 1)))
3100 ep->offset -= INTVAL (XEXP (src, 1));
3102 ep->can_eliminate = 0;
3106 elimination_effects (SET_DEST (x), VOIDmode);
3107 elimination_effects (SET_SRC (x), VOIDmode);
3111 /* Our only special processing is to pass the mode of the MEM to our
3113 elimination_effects (XEXP (x, 0), GET_MODE (x));
3120 fmt = GET_RTX_FORMAT (code);
3121 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3124 elimination_effects (XEXP (x, i), mem_mode);
3125 else if (*fmt == 'E')
3126 for (j = 0; j < XVECLEN (x, i); j++)
3127 elimination_effects (XVECEXP (x, i, j), mem_mode);
3131 /* Descend through rtx X and verify that no references to eliminable registers
3132 remain. If any do remain, mark the involved register as not
3136 check_eliminable_occurrences (rtx x)
3145 code = GET_CODE (x);
3147 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3149 struct elim_table *ep;
3151 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3152 if (ep->from_rtx == x)
3153 ep->can_eliminate = 0;
3157 fmt = GET_RTX_FORMAT (code);
3158 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3161 check_eliminable_occurrences (XEXP (x, i));
3162 else if (*fmt == 'E')
3165 for (j = 0; j < XVECLEN (x, i); j++)
3166 check_eliminable_occurrences (XVECEXP (x, i, j));
3171 /* Scan INSN and eliminate all eliminable registers in it.
3173 If REPLACE is nonzero, do the replacement destructively. Also
3174 delete the insn as dead it if it is setting an eliminable register.
3176 If REPLACE is zero, do all our allocations in reload_obstack.
3178 If no eliminations were done and this insn doesn't require any elimination
3179 processing (these are not identical conditions: it might be updating sp,
3180 but not referencing fp; this needs to be seen during reload_as_needed so
3181 that the offset between fp and sp can be taken into consideration), zero
3182 is returned. Otherwise, 1 is returned. */
3185 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3187 int icode = recog_memoized (insn);
3188 rtx old_body = PATTERN (insn);
3189 int insn_is_asm = asm_noperands (old_body) >= 0;
3190 rtx old_set = single_set (insn);
3194 rtx substed_operand[MAX_RECOG_OPERANDS];
3195 rtx orig_operand[MAX_RECOG_OPERANDS];
3196 struct elim_table *ep;
3197 rtx plus_src, plus_cst_src;
3199 if (! insn_is_asm && icode < 0)
3201 gcc_assert (DEBUG_INSN_P (insn)
3202 || GET_CODE (PATTERN (insn)) == USE
3203 || GET_CODE (PATTERN (insn)) == CLOBBER
3204 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3205 if (DEBUG_BIND_INSN_P (insn))
3206 INSN_VAR_LOCATION_LOC (insn)
3207 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3211 if (old_set != 0 && REG_P (SET_DEST (old_set))
3212 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3214 /* Check for setting an eliminable register. */
3215 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3216 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3218 /* If this is setting the frame pointer register to the
3219 hardware frame pointer register and this is an elimination
3220 that will be done (tested above), this insn is really
3221 adjusting the frame pointer downward to compensate for
3222 the adjustment done before a nonlocal goto. */
3223 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3224 && ep->from == FRAME_POINTER_REGNUM
3225 && ep->to == HARD_FRAME_POINTER_REGNUM)
3227 rtx base = SET_SRC (old_set);
3228 rtx_insn *base_insn = insn;
3229 HOST_WIDE_INT offset = 0;
3231 while (base != ep->to_rtx)
3233 rtx_insn *prev_insn;
3236 if (GET_CODE (base) == PLUS
3237 && CONST_INT_P (XEXP (base, 1)))
3239 offset += INTVAL (XEXP (base, 1));
3240 base = XEXP (base, 0);
3242 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3243 && (prev_set = single_set (prev_insn)) != 0
3244 && rtx_equal_p (SET_DEST (prev_set), base))
3246 base = SET_SRC (prev_set);
3247 base_insn = prev_insn;
3253 if (base == ep->to_rtx)
3255 rtx src = plus_constant (Pmode, ep->to_rtx,
3256 offset - ep->offset);
3258 new_body = old_body;
3261 new_body = copy_insn (old_body);
3262 if (REG_NOTES (insn))
3263 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3265 PATTERN (insn) = new_body;
3266 old_set = single_set (insn);
3268 /* First see if this insn remains valid when we
3269 make the change. If not, keep the INSN_CODE
3270 the same and let reload fit it up. */
3271 validate_change (insn, &SET_SRC (old_set), src, 1);
3272 validate_change (insn, &SET_DEST (old_set),
3274 if (! apply_change_group ())
3276 SET_SRC (old_set) = src;
3277 SET_DEST (old_set) = ep->to_rtx;
3285 /* In this case this insn isn't serving a useful purpose. We
3286 will delete it in reload_as_needed once we know that this
3287 elimination is, in fact, being done.
3289 If REPLACE isn't set, we can't delete this insn, but needn't
3290 process it since it won't be used unless something changes. */
3293 delete_dead_insn (insn);
3301 /* We allow one special case which happens to work on all machines we
3302 currently support: a single set with the source or a REG_EQUAL
3303 note being a PLUS of an eliminable register and a constant. */
3304 plus_src = plus_cst_src = 0;
3305 if (old_set && REG_P (SET_DEST (old_set)))
3307 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3308 plus_src = SET_SRC (old_set);
3309 /* First see if the source is of the form (plus (...) CST). */
3311 && CONST_INT_P (XEXP (plus_src, 1)))
3312 plus_cst_src = plus_src;
3313 else if (REG_P (SET_SRC (old_set))
3316 /* Otherwise, see if we have a REG_EQUAL note of the form
3317 (plus (...) CST). */
3319 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3321 if ((REG_NOTE_KIND (links) == REG_EQUAL
3322 || REG_NOTE_KIND (links) == REG_EQUIV)
3323 && GET_CODE (XEXP (links, 0)) == PLUS
3324 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3326 plus_cst_src = XEXP (links, 0);
3332 /* Check that the first operand of the PLUS is a hard reg or
3333 the lowpart subreg of one. */
3336 rtx reg = XEXP (plus_cst_src, 0);
3337 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3338 reg = SUBREG_REG (reg);
3340 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3346 rtx reg = XEXP (plus_cst_src, 0);
3347 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3349 if (GET_CODE (reg) == SUBREG)
3350 reg = SUBREG_REG (reg);
3352 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3353 if (ep->from_rtx == reg && ep->can_eliminate)
3355 rtx to_rtx = ep->to_rtx;
3356 offset += ep->offset;
3357 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3359 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3360 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3362 /* If we have a nonzero offset, and the source is already
3363 a simple REG, the following transformation would
3364 increase the cost of the insn by replacing a simple REG
3365 with (plus (reg sp) CST). So try only when we already
3366 had a PLUS before. */
3367 if (offset == 0 || plus_src)
3369 rtx new_src = plus_constant (GET_MODE (to_rtx),
3372 new_body = old_body;
3375 new_body = copy_insn (old_body);
3376 if (REG_NOTES (insn))
3377 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3379 PATTERN (insn) = new_body;
3380 old_set = single_set (insn);
3382 /* First see if this insn remains valid when we make the
3383 change. If not, try to replace the whole pattern with
3384 a simple set (this may help if the original insn was a
3385 PARALLEL that was only recognized as single_set due to
3386 REG_UNUSED notes). If this isn't valid either, keep
3387 the INSN_CODE the same and let reload fix it up. */
3388 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3390 rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3392 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3393 SET_SRC (old_set) = new_src;
3400 /* This can't have an effect on elimination offsets, so skip right
3406 /* Determine the effects of this insn on elimination offsets. */
3407 elimination_effects (old_body, VOIDmode);
3409 /* Eliminate all eliminable registers occurring in operands that
3410 can be handled by reload. */
3411 extract_insn (insn);
3412 for (i = 0; i < recog_data.n_operands; i++)
3414 orig_operand[i] = recog_data.operand[i];
3415 substed_operand[i] = recog_data.operand[i];
3417 /* For an asm statement, every operand is eliminable. */
3418 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3420 bool is_set_src, in_plus;
3422 /* Check for setting a register that we know about. */
3423 if (recog_data.operand_type[i] != OP_IN
3424 && REG_P (orig_operand[i]))
3426 /* If we are assigning to a register that can be eliminated, it
3427 must be as part of a PARALLEL, since the code above handles
3428 single SETs. We must indicate that we can no longer
3429 eliminate this reg. */
3430 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3432 if (ep->from_rtx == orig_operand[i])
3433 ep->can_eliminate = 0;
3436 /* Companion to the above plus substitution, we can allow
3437 invariants as the source of a plain move. */
3440 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3444 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3445 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3449 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3450 replace ? insn : NULL_RTX,
3451 is_set_src || in_plus, false);
3452 if (substed_operand[i] != orig_operand[i])
3454 /* Terminate the search in check_eliminable_occurrences at
3456 *recog_data.operand_loc[i] = 0;
3458 /* If an output operand changed from a REG to a MEM and INSN is an
3459 insn, write a CLOBBER insn. */
3460 if (recog_data.operand_type[i] != OP_IN
3461 && REG_P (orig_operand[i])
3462 && MEM_P (substed_operand[i])
3464 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3468 for (i = 0; i < recog_data.n_dups; i++)
3469 *recog_data.dup_loc[i]
3470 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3472 /* If any eliminable remain, they aren't eliminable anymore. */
3473 check_eliminable_occurrences (old_body);
3475 /* Substitute the operands; the new values are in the substed_operand
3477 for (i = 0; i < recog_data.n_operands; i++)
3478 *recog_data.operand_loc[i] = substed_operand[i];
3479 for (i = 0; i < recog_data.n_dups; i++)
3480 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3482 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3483 re-recognize the insn. We do this in case we had a simple addition
3484 but now can do this as a load-address. This saves an insn in this
3486 If re-recognition fails, the old insn code number will still be used,
3487 and some register operands may have changed into PLUS expressions.
3488 These will be handled by find_reloads by loading them into a register
3493 /* If we aren't replacing things permanently and we changed something,
3494 make another copy to ensure that all the RTL is new. Otherwise
3495 things can go wrong if find_reload swaps commutative operands
3496 and one is inside RTL that has been copied while the other is not. */
3497 new_body = old_body;
3500 new_body = copy_insn (old_body);
3501 if (REG_NOTES (insn))
3502 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3504 PATTERN (insn) = new_body;
3506 /* If we had a move insn but now we don't, rerecognize it. This will
3507 cause spurious re-recognition if the old move had a PARALLEL since
3508 the new one still will, but we can't call single_set without
3509 having put NEW_BODY into the insn and the re-recognition won't
3510 hurt in this rare case. */
3511 /* ??? Why this huge if statement - why don't we just rerecognize the
3515 && ((REG_P (SET_SRC (old_set))
3516 && (GET_CODE (new_body) != SET
3517 || !REG_P (SET_SRC (new_body))))
3518 /* If this was a load from or store to memory, compare
3519 the MEM in recog_data.operand to the one in the insn.
3520 If they are not equal, then rerecognize the insn. */
3522 && ((MEM_P (SET_SRC (old_set))
3523 && SET_SRC (old_set) != recog_data.operand[1])
3524 || (MEM_P (SET_DEST (old_set))
3525 && SET_DEST (old_set) != recog_data.operand[0])))
3526 /* If this was an add insn before, rerecognize. */
3527 || GET_CODE (SET_SRC (old_set)) == PLUS))
3529 int new_icode = recog (PATTERN (insn), insn, 0);
3531 INSN_CODE (insn) = new_icode;
3535 /* Restore the old body. If there were any changes to it, we made a copy
3536 of it while the changes were still in place, so we'll correctly return
3537 a modified insn below. */
3540 /* Restore the old body. */
3541 for (i = 0; i < recog_data.n_operands; i++)
3542 /* Restoring a top-level match_parallel would clobber the new_body
3543 we installed in the insn. */
3544 if (recog_data.operand_loc[i] != &PATTERN (insn))
3545 *recog_data.operand_loc[i] = orig_operand[i];
3546 for (i = 0; i < recog_data.n_dups; i++)
3547 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3550 /* Update all elimination pairs to reflect the status after the current
3551 insn. The changes we make were determined by the earlier call to
3552 elimination_effects.
3554 We also detect cases where register elimination cannot be done,
3555 namely, if a register would be both changed and referenced outside a MEM
3556 in the resulting insn since such an insn is often undefined and, even if
3557 not, we cannot know what meaning will be given to it. Note that it is
3558 valid to have a register used in an address in an insn that changes it
3559 (presumably with a pre- or post-increment or decrement).
3561 If anything changes, return nonzero. */
3563 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3565 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3566 ep->can_eliminate = 0;
3568 ep->ref_outside_mem = 0;
3570 if (ep->previous_offset != ep->offset)
3575 /* If we changed something, perform elimination in REG_NOTES. This is
3576 needed even when REPLACE is zero because a REG_DEAD note might refer
3577 to a register that we eliminate and could cause a different number
3578 of spill registers to be needed in the final reload pass than in
3580 if (val && REG_NOTES (insn) != 0)
3582 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3588 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3589 register allocator. INSN is the instruction we need to examine, we perform
3590 eliminations in its operands and record cases where eliminating a reg with
3591 an invariant equivalence would add extra cost. */
3593 #pragma GCC diagnostic push
3594 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3596 elimination_costs_in_insn (rtx_insn *insn)
3598 int icode = recog_memoized (insn);
3599 rtx old_body = PATTERN (insn);
3600 int insn_is_asm = asm_noperands (old_body) >= 0;
3601 rtx old_set = single_set (insn);
3603 rtx orig_operand[MAX_RECOG_OPERANDS];
3604 rtx orig_dup[MAX_RECOG_OPERANDS];
3605 struct elim_table *ep;
3606 rtx plus_src, plus_cst_src;
3609 if (! insn_is_asm && icode < 0)
3611 gcc_assert (DEBUG_INSN_P (insn)
3612 || GET_CODE (PATTERN (insn)) == USE
3613 || GET_CODE (PATTERN (insn)) == CLOBBER
3614 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3618 if (old_set != 0 && REG_P (SET_DEST (old_set))
3619 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3621 /* Check for setting an eliminable register. */
3622 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3623 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3627 /* We allow one special case which happens to work on all machines we
3628 currently support: a single set with the source or a REG_EQUAL
3629 note being a PLUS of an eliminable register and a constant. */
3630 plus_src = plus_cst_src = 0;
3632 if (old_set && REG_P (SET_DEST (old_set)))
3635 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3636 plus_src = SET_SRC (old_set);
3637 /* First see if the source is of the form (plus (...) CST). */
3639 && CONST_INT_P (XEXP (plus_src, 1)))
3640 plus_cst_src = plus_src;
3641 else if (REG_P (SET_SRC (old_set))
3644 /* Otherwise, see if we have a REG_EQUAL note of the form
3645 (plus (...) CST). */
3647 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3649 if ((REG_NOTE_KIND (links) == REG_EQUAL
3650 || REG_NOTE_KIND (links) == REG_EQUIV)
3651 && GET_CODE (XEXP (links, 0)) == PLUS
3652 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3654 plus_cst_src = XEXP (links, 0);
3661 /* Determine the effects of this insn on elimination offsets. */
3662 elimination_effects (old_body, VOIDmode);
3664 /* Eliminate all eliminable registers occurring in operands that
3665 can be handled by reload. */
3666 extract_insn (insn);
3667 int n_dups = recog_data.n_dups;
3668 for (i = 0; i < n_dups; i++)
3669 orig_dup[i] = *recog_data.dup_loc[i];
3671 int n_operands = recog_data.n_operands;
3672 for (i = 0; i < n_operands; i++)
3674 orig_operand[i] = recog_data.operand[i];
3676 /* For an asm statement, every operand is eliminable. */
3677 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3679 bool is_set_src, in_plus;
3681 /* Check for setting a register that we know about. */
3682 if (recog_data.operand_type[i] != OP_IN
3683 && REG_P (orig_operand[i]))
3685 /* If we are assigning to a register that can be eliminated, it
3686 must be as part of a PARALLEL, since the code above handles
3687 single SETs. We must indicate that we can no longer
3688 eliminate this reg. */
3689 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3691 if (ep->from_rtx == orig_operand[i])
3692 ep->can_eliminate = 0;
3695 /* Companion to the above plus substitution, we can allow
3696 invariants as the source of a plain move. */
3698 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3700 if (is_set_src && !sets_reg_p)
3701 note_reg_elim_costly (SET_SRC (old_set), insn);
3703 if (plus_src && sets_reg_p
3704 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3705 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3708 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3710 is_set_src || in_plus, true);
3711 /* Terminate the search in check_eliminable_occurrences at
3713 *recog_data.operand_loc[i] = 0;
3717 for (i = 0; i < n_dups; i++)
3718 *recog_data.dup_loc[i]
3719 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3721 /* If any eliminable remain, they aren't eliminable anymore. */
3722 check_eliminable_occurrences (old_body);
3724 /* Restore the old body. */
3725 for (i = 0; i < n_operands; i++)
3726 *recog_data.operand_loc[i] = orig_operand[i];
3727 for (i = 0; i < n_dups; i++)
3728 *recog_data.dup_loc[i] = orig_dup[i];
3730 /* Update all elimination pairs to reflect the status after the current
3731 insn. The changes we make were determined by the earlier call to
3732 elimination_effects. */
3734 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3736 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3737 ep->can_eliminate = 0;
3739 ep->ref_outside_mem = 0;
3744 #pragma GCC diagnostic pop
3746 /* Loop through all elimination pairs.
3747 Recalculate the number not at initial offset.
3749 Compute the maximum offset (minimum offset if the stack does not
3750 grow downward) for each elimination pair. */
3753 update_eliminable_offsets (void)
3755 struct elim_table *ep;
3757 num_not_at_initial_offset = 0;
3758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3760 ep->previous_offset = ep->offset;
3761 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3762 num_not_at_initial_offset++;
3766 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3767 replacement we currently believe is valid, mark it as not eliminable if X
3768 modifies DEST in any way other than by adding a constant integer to it.
3770 If DEST is the frame pointer, we do nothing because we assume that
3771 all assignments to the hard frame pointer are nonlocal gotos and are being
3772 done at a time when they are valid and do not disturb anything else.
3773 Some machines want to eliminate a fake argument pointer with either the
3774 frame or stack pointer. Assignments to the hard frame pointer must not
3775 prevent this elimination.
3777 Called via note_stores from reload before starting its passes to scan
3778 the insns of the function. */
3781 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3785 /* A SUBREG of a hard register here is just changing its mode. We should
3786 not see a SUBREG of an eliminable hard register, but check just in
3788 if (GET_CODE (dest) == SUBREG)
3789 dest = SUBREG_REG (dest);
3791 if (dest == hard_frame_pointer_rtx)
3794 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3795 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3796 && (GET_CODE (x) != SET
3797 || GET_CODE (SET_SRC (x)) != PLUS
3798 || XEXP (SET_SRC (x), 0) != dest
3799 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3801 reg_eliminate[i].can_eliminate_previous
3802 = reg_eliminate[i].can_eliminate = 0;
3807 /* Verify that the initial elimination offsets did not change since the
3808 last call to set_initial_elim_offsets. This is used to catch cases
3809 where something illegal happened during reload_as_needed that could
3810 cause incorrect code to be generated if we did not check for it. */
3813 verify_initial_elim_offsets (void)
3816 struct elim_table *ep;
3818 if (!num_eliminable)
3821 targetm.compute_frame_layout ();
3822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3824 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3825 if (t != ep->initial_offset)
3832 /* Reset all offsets on eliminable registers to their initial values. */
3835 set_initial_elim_offsets (void)
3837 struct elim_table *ep = reg_eliminate;
3839 targetm.compute_frame_layout ();
3840 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3842 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3843 ep->previous_offset = ep->offset = ep->initial_offset;
3846 num_not_at_initial_offset = 0;
3849 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3852 set_initial_eh_label_offset (rtx label)
3854 set_label_offsets (label, NULL, 1);
3857 /* Initialize the known label offsets.
3858 Set a known offset for each forced label to be at the initial offset
3859 of each elimination. We do this because we assume that all
3860 computed jumps occur from a location where each elimination is
3861 at its initial offset.
3862 For all other labels, show that we don't know the offsets. */
3865 set_initial_label_offsets (void)
3867 memset (offsets_known_at, 0, num_labels);
3871 FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn)
3872 set_label_offsets (insn, NULL, 1);
3874 for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3876 set_label_offsets (x->insn (), NULL, 1);
3878 for_each_eh_label (set_initial_eh_label_offset);
3881 /* Set all elimination offsets to the known values for the code label given
3885 set_offsets_for_label (rtx_insn *insn)
3888 int label_nr = CODE_LABEL_NUMBER (insn);
3889 struct elim_table *ep;
3891 num_not_at_initial_offset = 0;
3892 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3894 ep->offset = ep->previous_offset
3895 = offsets_at[label_nr - first_label_num][i];
3896 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3897 num_not_at_initial_offset++;
3901 /* See if anything that happened changes which eliminations are valid.
3902 For example, on the SPARC, whether or not the frame pointer can
3903 be eliminated can depend on what registers have been used. We need
3904 not check some conditions again (such as flag_omit_frame_pointer)
3905 since they can't have changed. */
3908 update_eliminables (HARD_REG_SET *pset)
3910 int previous_frame_pointer_needed = frame_pointer_needed;
3911 struct elim_table *ep;
3913 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3914 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3915 && targetm.frame_pointer_required ())
3916 || ! targetm.can_eliminate (ep->from, ep->to)
3918 ep->can_eliminate = 0;
3920 /* Look for the case where we have discovered that we can't replace
3921 register A with register B and that means that we will now be
3922 trying to replace register A with register C. This means we can
3923 no longer replace register C with register B and we need to disable
3924 such an elimination, if it exists. This occurs often with A == ap,
3925 B == sp, and C == fp. */
3927 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3929 struct elim_table *op;
3932 if (! ep->can_eliminate && ep->can_eliminate_previous)
3934 /* Find the current elimination for ep->from, if there is a
3936 for (op = reg_eliminate;
3937 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3938 if (op->from == ep->from && op->can_eliminate)
3944 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3946 for (op = reg_eliminate;
3947 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3948 if (op->from == new_to && op->to == ep->to)
3949 op->can_eliminate = 0;
3953 /* See if any registers that we thought we could eliminate the previous
3954 time are no longer eliminable. If so, something has changed and we
3955 must spill the register. Also, recompute the number of eliminable
3956 registers and see if the frame pointer is needed; it is if there is
3957 no elimination of the frame pointer that we can perform. */
3959 frame_pointer_needed = 1;
3960 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3962 if (ep->can_eliminate
3963 && ep->from == FRAME_POINTER_REGNUM
3964 && ep->to != HARD_FRAME_POINTER_REGNUM
3965 && (! SUPPORTS_STACK_ALIGNMENT
3966 || ! crtl->stack_realign_needed))
3967 frame_pointer_needed = 0;
3969 if (! ep->can_eliminate && ep->can_eliminate_previous)
3971 ep->can_eliminate_previous = 0;
3972 SET_HARD_REG_BIT (*pset, ep->from);
3977 /* If we didn't need a frame pointer last time, but we do now, spill
3978 the hard frame pointer. */
3979 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3980 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3983 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3984 Return true iff a register was spilled. */
3987 update_eliminables_and_spill (void)
3990 bool did_spill = false;
3991 HARD_REG_SET to_spill;
3992 CLEAR_HARD_REG_SET (to_spill);
3993 update_eliminables (&to_spill);
3994 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
3996 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3997 if (TEST_HARD_REG_BIT (to_spill, i))
3999 spill_hard_reg (i, 1);
4002 /* Regardless of the state of spills, if we previously had
4003 a register that we thought we could eliminate, but now can
4004 not eliminate, we must run another pass.
4006 Consider pseudos which have an entry in reg_equiv_* which
4007 reference an eliminable register. We must make another pass
4008 to update reg_equiv_* so that we do not substitute in the
4009 old value from when we thought the elimination could be
4015 /* Return true if X is used as the target register of an elimination. */
4018 elimination_target_reg_p (rtx x)
4020 struct elim_table *ep;
4022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4023 if (ep->to_rtx == x && ep->can_eliminate)
4029 /* Initialize the table of registers to eliminate.
4030 Pre-condition: global flag frame_pointer_needed has been set before
4031 calling this function. */
4034 init_elim_table (void)
4036 struct elim_table *ep;
4037 const struct elim_table_1 *ep1;
4040 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4044 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4045 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4047 ep->from = ep1->from;
4049 ep->can_eliminate = ep->can_eliminate_previous
4050 = (targetm.can_eliminate (ep->from, ep->to)
4051 && ! (ep->to == STACK_POINTER_REGNUM
4052 && frame_pointer_needed
4053 && (! SUPPORTS_STACK_ALIGNMENT
4054 || ! stack_realign_fp)));
4057 /* Count the number of eliminable registers and build the FROM and TO
4058 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4059 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4060 We depend on this. */
4061 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4063 num_eliminable += ep->can_eliminate;
4064 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4065 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4069 /* Find all the pseudo registers that didn't get hard regs
4070 but do have known equivalent constants or memory slots.
4071 These include parameters (known equivalent to parameter slots)
4072 and cse'd or loop-moved constant memory addresses.
4074 Record constant equivalents in reg_equiv_constant
4075 so they will be substituted by find_reloads.
4076 Record memory equivalents in reg_mem_equiv so they can
4077 be substituted eventually by altering the REG-rtx's. */
4080 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4087 reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno);
4089 reg_max_ref_mode = NULL;
4091 num_eliminable_invariants = 0;
4093 first_label_num = get_first_label_num ();
4094 num_labels = max_label_num () - first_label_num;
4096 /* Allocate the tables used to store offset information at labels. */
4097 offsets_known_at = XNEWVEC (char, num_labels);
4098 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4100 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4101 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4102 find largest such for each pseudo. FIRST is the head of the insn
4105 for (insn = first; insn; insn = NEXT_INSN (insn))
4107 rtx set = single_set (insn);
4109 /* We may introduce USEs that we want to remove at the end, so
4110 we'll mark them with QImode. Make sure there are no
4111 previously-marked insns left by say regmove. */
4112 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4113 && GET_MODE (insn) != VOIDmode)
4114 PUT_MODE (insn, VOIDmode);
4116 if (do_subregs && NONDEBUG_INSN_P (insn))
4117 scan_paradoxical_subregs (PATTERN (insn));
4119 if (set != 0 && REG_P (SET_DEST (set)))
4121 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4127 i = REGNO (SET_DEST (set));
4130 if (i <= LAST_VIRTUAL_REGISTER)
4133 /* If flag_pic and we have constant, verify it's legitimate. */
4135 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4137 /* It can happen that a REG_EQUIV note contains a MEM
4138 that is not a legitimate memory operand. As later
4139 stages of reload assume that all addresses found
4140 in the reg_equiv_* arrays were originally legitimate,
4141 we ignore such REG_EQUIV notes. */
4142 if (memory_operand (x, VOIDmode))
4144 /* Always unshare the equivalence, so we can
4145 substitute into this insn without touching the
4147 reg_equiv_memory_loc (i) = copy_rtx (x);
4149 else if (function_invariant_p (x))
4153 mode = GET_MODE (SET_DEST (set));
4154 if (GET_CODE (x) == PLUS)
4156 /* This is PLUS of frame pointer and a constant,
4157 and might be shared. Unshare it. */
4158 reg_equiv_invariant (i) = copy_rtx (x);
4159 num_eliminable_invariants++;
4161 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4163 reg_equiv_invariant (i) = x;
4164 num_eliminable_invariants++;
4166 else if (targetm.legitimate_constant_p (mode, x))
4167 reg_equiv_constant (i) = x;
4170 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4171 if (! reg_equiv_memory_loc (i))
4172 reg_equiv_init (i) = NULL;
4177 reg_equiv_init (i) = NULL;
4182 reg_equiv_init (i) = NULL;
4187 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4188 if (reg_equiv_init (i))
4190 fprintf (dump_file, "init_insns for %u: ", i);
4191 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4192 fprintf (dump_file, "\n");
4196 /* Indicate that we no longer have known memory locations or constants.
4197 Free all data involved in tracking these. */
4200 free_reg_equiv (void)
4204 free (offsets_known_at);
4207 offsets_known_at = 0;
4209 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4210 if (reg_equiv_alt_mem_list (i))
4211 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4212 vec_free (reg_equivs);
4215 /* Kick all pseudos out of hard register REGNO.
4217 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4218 because we found we can't eliminate some register. In the case, no pseudos
4219 are allowed to be in the register, even if they are only in a block that
4220 doesn't require spill registers, unlike the case when we are spilling this
4221 hard reg to produce another spill register.
4223 Return nonzero if any pseudos needed to be kicked out. */
4226 spill_hard_reg (unsigned int regno, int cant_eliminate)
4232 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4233 df_set_regs_ever_live (regno, true);
4236 /* Spill every pseudo reg that was allocated to this reg
4237 or to something that overlaps this reg. */
4239 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4240 if (reg_renumber[i] >= 0
4241 && (unsigned int) reg_renumber[i] <= regno
4242 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4243 SET_REGNO_REG_SET (&spilled_pseudos, i);
4246 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4247 insns that need reloads, this function is used to actually spill pseudo
4248 registers and try to reallocate them. It also sets up the spill_regs
4249 array for use by choose_reload_regs.
4251 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4252 that we displace from hard registers. */
4255 finish_spills (int global)
4257 struct insn_chain *chain;
4258 int something_changed = 0;
4260 reg_set_iterator rsi;
4262 /* Build the spill_regs array for the function. */
4263 /* If there are some registers still to eliminate and one of the spill regs
4264 wasn't ever used before, additional stack space may have to be
4265 allocated to store this register. Thus, we may have changed the offset
4266 between the stack and frame pointers, so mark that something has changed.
4268 One might think that we need only set VAL to 1 if this is a call-used
4269 register. However, the set of registers that must be saved by the
4270 prologue is not identical to the call-used set. For example, the
4271 register used by the call insn for the return PC is a call-used register,
4272 but must be saved by the prologue. */
4275 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4276 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4278 spill_reg_order[i] = n_spills;
4279 spill_regs[n_spills++] = i;
4280 if (num_eliminable && ! df_regs_ever_live_p (i))
4281 something_changed = 1;
4282 df_set_regs_ever_live (i, true);
4285 spill_reg_order[i] = -1;
4287 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4288 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4290 /* Record the current hard register the pseudo is allocated to
4291 in pseudo_previous_regs so we avoid reallocating it to the
4292 same hard reg in a later pass. */
4293 gcc_assert (reg_renumber[i] >= 0);
4295 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4296 /* Mark it as no longer having a hard register home. */
4297 reg_renumber[i] = -1;
4298 if (ira_conflicts_p)
4299 /* Inform IRA about the change. */
4300 ira_mark_allocation_change (i);
4301 /* We will need to scan everything again. */
4302 something_changed = 1;
4305 /* Retry global register allocation if possible. */
4306 if (global && ira_conflicts_p)
4310 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4311 /* For every insn that needs reloads, set the registers used as spill
4312 regs in pseudo_forbidden_regs for every pseudo live across the
4314 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4316 EXECUTE_IF_SET_IN_REG_SET
4317 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4319 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4320 chain->used_spill_regs);
4322 EXECUTE_IF_SET_IN_REG_SET
4323 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4325 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4326 chain->used_spill_regs);
4330 /* Retry allocating the pseudos spilled in IRA and the
4331 reload. For each reg, merge the various reg sets that
4332 indicate which hard regs can't be used, and call
4333 ira_reassign_pseudos. */
4334 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4335 if (reg_old_renumber[i] != reg_renumber[i])
4337 if (reg_renumber[i] < 0)
4338 temp_pseudo_reg_arr[n++] = i;
4340 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4342 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4343 bad_spill_regs_global,
4344 pseudo_forbidden_regs, pseudo_previous_regs,
4346 something_changed = 1;
4348 /* Fix up the register information in the insn chain.
4349 This involves deleting those of the spilled pseudos which did not get
4350 a new hard register home from the live_{before,after} sets. */
4351 for (chain = reload_insn_chain; chain; chain = chain->next)
4353 HARD_REG_SET used_by_pseudos;
4354 HARD_REG_SET used_by_pseudos2;
4356 if (! ira_conflicts_p)
4358 /* Don't do it for IRA because IRA and the reload still can
4359 assign hard registers to the spilled pseudos on next
4360 reload iterations. */
4361 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4362 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4364 /* Mark any unallocated hard regs as available for spills. That
4365 makes inheritance work somewhat better. */
4366 if (chain->need_reload)
4368 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4369 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4370 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4372 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4373 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4374 /* Value of chain->used_spill_regs from previous iteration
4375 may be not included in the value calculated here because
4376 of possible removing caller-saves insns (see function
4377 delete_caller_save_insns. */
4378 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4379 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4383 CLEAR_REG_SET (&changed_allocation_pseudos);
4384 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4385 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4387 int regno = reg_renumber[i];
4388 if (reg_old_renumber[i] == regno)
4391 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4393 alter_reg (i, reg_old_renumber[i], false);
4394 reg_old_renumber[i] = regno;
4398 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4400 fprintf (dump_file, " Register %d now in %d.\n\n",
4401 i, reg_renumber[i]);
4405 return something_changed;
4408 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4411 scan_paradoxical_subregs (rtx x)
4415 enum rtx_code code = GET_CODE (x);
4431 if (REG_P (SUBREG_REG (x)))
4433 unsigned int regno = REGNO (SUBREG_REG (x));
4434 if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)))
4436 reg_max_ref_mode[regno] = GET_MODE (x);
4437 mark_home_live_1 (regno, GET_MODE (x));
4446 fmt = GET_RTX_FORMAT (code);
4447 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4450 scan_paradoxical_subregs (XEXP (x, i));
4451 else if (fmt[i] == 'E')
4454 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4455 scan_paradoxical_subregs (XVECEXP (x, i, j));
4460 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4461 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4462 and apply the corresponding narrowing subreg to *OTHER_PTR.
4463 Return true if the operands were changed, false otherwise. */
4466 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4468 rtx op, inner, other, tem;
4471 if (!paradoxical_subreg_p (op))
4473 inner = SUBREG_REG (op);
4476 tem = gen_lowpart_common (GET_MODE (inner), other);
4480 /* If the lowpart operation turned a hard register into a subreg,
4481 rather than simplifying it to another hard register, then the
4482 mode change cannot be properly represented. For example, OTHER
4483 might be valid in its current mode, but not in the new one. */
4484 if (GET_CODE (tem) == SUBREG
4486 && HARD_REGISTER_P (other))
4494 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4495 examine all of the reload insns between PREV and NEXT exclusive, and
4496 annotate all that may trap. */
4499 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4501 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4504 if (!insn_could_throw_p (insn))
4505 remove_note (insn, note);
4506 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4509 /* Reload pseudo-registers into hard regs around each insn as needed.
4510 Additional register load insns are output before the insn that needs it
4511 and perhaps store insns after insns that modify the reloaded pseudo reg.
4513 reg_last_reload_reg and reg_reloaded_contents keep track of
4514 which registers are already available in reload registers.
4515 We update these for the reloads that we perform,
4516 as the insns are scanned. */
4519 reload_as_needed (int live_known)
4521 struct insn_chain *chain;
4527 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4528 memset (spill_reg_store, 0, sizeof spill_reg_store);
4529 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4530 INIT_REG_SET (®_has_output_reload);
4531 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4532 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4534 set_initial_elim_offsets ();
4536 /* Generate a marker insn that we will move around. */
4537 marker = emit_note (NOTE_INSN_DELETED);
4538 unlink_insn_chain (marker, marker);
4540 for (chain = reload_insn_chain; chain; chain = chain->next)
4543 rtx_insn *insn = chain->insn;
4544 rtx_insn *old_next = NEXT_INSN (insn);
4546 rtx_insn *old_prev = PREV_INSN (insn);
4549 if (will_delete_init_insn_p (insn))
4552 /* If we pass a label, copy the offsets from the label information
4553 into the current offsets of each elimination. */
4555 set_offsets_for_label (insn);
4557 else if (INSN_P (insn))
4559 regset_head regs_to_forget;
4560 INIT_REG_SET (®s_to_forget);
4561 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4563 /* If this is a USE and CLOBBER of a MEM, ensure that any
4564 references to eliminable registers have been removed. */
4566 if ((GET_CODE (PATTERN (insn)) == USE
4567 || GET_CODE (PATTERN (insn)) == CLOBBER)
4568 && MEM_P (XEXP (PATTERN (insn), 0)))
4569 XEXP (XEXP (PATTERN (insn), 0), 0)
4570 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4571 GET_MODE (XEXP (PATTERN (insn), 0)),
4574 /* If we need to do register elimination processing, do so.
4575 This might delete the insn, in which case we are done. */
4576 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4578 eliminate_regs_in_insn (insn, 1);
4581 update_eliminable_offsets ();
4582 CLEAR_REG_SET (®s_to_forget);
4587 /* If need_elim is nonzero but need_reload is zero, one might think
4588 that we could simply set n_reloads to 0. However, find_reloads
4589 could have done some manipulation of the insn (such as swapping
4590 commutative operands), and these manipulations are lost during
4591 the first pass for every insn that needs register elimination.
4592 So the actions of find_reloads must be redone here. */
4594 if (! chain->need_elim && ! chain->need_reload
4595 && ! chain->need_operand_change)
4597 /* First find the pseudo regs that must be reloaded for this insn.
4598 This info is returned in the tables reload_... (see reload.h).
4599 Also modify the body of INSN by substituting RELOAD
4600 rtx's for those pseudo regs. */
4603 CLEAR_REG_SET (®_has_output_reload);
4604 CLEAR_HARD_REG_SET (reg_is_output_reload);
4606 find_reloads (insn, 1, spill_indirect_levels, live_known,
4612 rtx_insn *next = NEXT_INSN (insn);
4614 /* ??? PREV can get deleted by reload inheritance.
4615 Work around this by emitting a marker note. */
4616 prev = PREV_INSN (insn);
4617 reorder_insns_nobb (marker, marker, prev);
4619 /* Now compute which reload regs to reload them into. Perhaps
4620 reusing reload regs from previous insns, or else output
4621 load insns to reload them. Maybe output store insns too.
4622 Record the choices of reload reg in reload_reg_rtx. */
4623 choose_reload_regs (chain);
4625 /* Generate the insns to reload operands into or out of
4626 their reload regs. */
4627 emit_reload_insns (chain);
4629 /* Substitute the chosen reload regs from reload_reg_rtx
4630 into the insn's body (or perhaps into the bodies of other
4631 load and store insn that we just made for reloading
4632 and that we moved the structure into). */
4633 subst_reloads (insn);
4635 prev = PREV_INSN (marker);
4636 unlink_insn_chain (marker, marker);
4638 /* Adjust the exception region notes for loads and stores. */
4639 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4640 fixup_eh_region_note (insn, prev, next);
4642 /* Adjust the location of REG_ARGS_SIZE. */
4643 rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4646 remove_note (insn, p);
4647 fixup_args_size_notes (prev, PREV_INSN (next),
4648 INTVAL (XEXP (p, 0)));
4651 /* If this was an ASM, make sure that all the reload insns
4652 we have generated are valid. If not, give an error
4654 if (asm_noperands (PATTERN (insn)) >= 0)
4655 for (rtx_insn *p = NEXT_INSN (prev);
4658 if (p != insn && INSN_P (p)
4659 && GET_CODE (PATTERN (p)) != USE
4660 && (recog_memoized (p) < 0
4661 || (extract_insn (p),
4662 !(constrain_operands (1,
4663 get_enabled_alternatives (p))))))
4665 error_for_asm (insn,
4666 "%<asm%> operand requires "
4667 "impossible reload");
4672 if (num_eliminable && chain->need_elim)
4673 update_eliminable_offsets ();
4675 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4676 is no longer validly lying around to save a future reload.
4677 Note that this does not detect pseudos that were reloaded
4678 for this insn in order to be stored in
4679 (obeying register constraints). That is correct; such reload
4680 registers ARE still valid. */
4681 forget_marked_reloads (®s_to_forget);
4682 CLEAR_REG_SET (®s_to_forget);
4684 /* There may have been CLOBBER insns placed after INSN. So scan
4685 between INSN and NEXT and use them to forget old reloads. */
4686 for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4687 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4688 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4691 /* Likewise for regs altered by auto-increment in this insn.
4692 REG_INC notes have been changed by reloading:
4693 find_reloads_address_1 records substitutions for them,
4694 which have been performed by subst_reloads above. */
4695 for (i = n_reloads - 1; i >= 0; i--)
4697 rtx in_reg = rld[i].in_reg;
4700 enum rtx_code code = GET_CODE (in_reg);
4701 /* PRE_INC / PRE_DEC will have the reload register ending up
4702 with the same value as the stack slot, but that doesn't
4703 hold true for POST_INC / POST_DEC. Either we have to
4704 convert the memory access to a true POST_INC / POST_DEC,
4705 or we can't use the reload register for inheritance. */
4706 if ((code == POST_INC || code == POST_DEC)
4707 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4708 REGNO (rld[i].reg_rtx))
4709 /* Make sure it is the inc/dec pseudo, and not
4710 some other (e.g. output operand) pseudo. */
4711 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4712 == REGNO (XEXP (in_reg, 0))))
4715 rtx reload_reg = rld[i].reg_rtx;
4716 machine_mode mode = GET_MODE (reload_reg);
4720 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4722 /* We really want to ignore REG_INC notes here, so
4723 use PATTERN (p) as argument to reg_set_p . */
4724 if (reg_set_p (reload_reg, PATTERN (p)))
4726 n = count_occurrences (PATTERN (p), reload_reg, 0);
4732 = gen_rtx_fmt_e (code, mode, reload_reg);
4734 validate_replace_rtx_group (reload_reg,
4736 n = verify_changes (0);
4738 /* We must also verify that the constraints
4739 are met after the replacement. Make sure
4740 extract_insn is only called for an insn
4741 where the replacements were found to be
4746 n = constrain_operands (1,
4747 get_enabled_alternatives (p));
4750 /* If the constraints were not met, then
4751 undo the replacement, else confirm it. */
4755 confirm_change_group ();
4761 add_reg_note (p, REG_INC, reload_reg);
4762 /* Mark this as having an output reload so that the
4763 REG_INC processing code below won't invalidate
4764 the reload for inheritance. */
4765 SET_HARD_REG_BIT (reg_is_output_reload,
4766 REGNO (reload_reg));
4767 SET_REGNO_REG_SET (®_has_output_reload,
4768 REGNO (XEXP (in_reg, 0)));
4771 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4774 else if ((code == PRE_INC || code == PRE_DEC)
4775 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4776 REGNO (rld[i].reg_rtx))
4777 /* Make sure it is the inc/dec pseudo, and not
4778 some other (e.g. output operand) pseudo. */
4779 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4780 == REGNO (XEXP (in_reg, 0))))
4782 SET_HARD_REG_BIT (reg_is_output_reload,
4783 REGNO (rld[i].reg_rtx));
4784 SET_REGNO_REG_SET (®_has_output_reload,
4785 REGNO (XEXP (in_reg, 0)));
4787 else if (code == PRE_INC || code == PRE_DEC
4788 || code == POST_INC || code == POST_DEC)
4790 int in_regno = REGNO (XEXP (in_reg, 0));
4792 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4795 bool forget_p = true;
4797 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4798 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4801 for (rtx_insn *x = (old_prev ?
4802 NEXT_INSN (old_prev) : insn);
4805 if (x == reg_reloaded_insn[in_hard_regno])
4811 /* If for some reasons, we didn't set up
4812 reg_last_reload_reg in this insn,
4813 invalidate inheritance from previous
4814 insns for the incremented/decremented
4815 register. Such registers will be not in
4816 reg_has_output_reload. Invalidate it
4817 also if the corresponding element in
4818 reg_reloaded_insn is also
4821 forget_old_reloads_1 (XEXP (in_reg, 0),
4827 /* If a pseudo that got a hard register is auto-incremented,
4828 we must purge records of copying it into pseudos without
4830 for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4831 if (REG_NOTE_KIND (x) == REG_INC)
4833 /* See if this pseudo reg was reloaded in this insn.
4834 If so, its last-reload info is still valid
4835 because it is based on this insn's reload. */
4836 for (i = 0; i < n_reloads; i++)
4837 if (rld[i].out == XEXP (x, 0))
4841 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4845 /* A reload reg's contents are unknown after a label. */
4847 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4849 /* Don't assume a reload reg is still good after a call insn
4850 if it is a call-used reg, or if it contains a value that will
4851 be partially clobbered by the call. */
4852 else if (CALL_P (insn))
4854 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4855 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4857 /* If this is a call to a setjmp-type function, we must not
4858 reuse any reload reg contents across the call; that will
4859 just be clobbered by other uses of the register in later
4860 code, before the longjmp. */
4861 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4862 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4867 free (reg_last_reload_reg);
4868 CLEAR_REG_SET (®_has_output_reload);
4871 /* Discard all record of any value reloaded from X,
4872 or reloaded in X from someplace else;
4873 unless X is an output reload reg of the current insn.
4875 X may be a hard reg (the reload reg)
4876 or it may be a pseudo reg that was reloaded from.
4878 When DATA is non-NULL just mark the registers in regset
4879 to be forgotten later. */
4882 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4887 regset regs = (regset) data;
4889 /* note_stores does give us subregs of hard regs,
4890 subreg_regno_offset requires a hard reg. */
4891 while (GET_CODE (x) == SUBREG)
4893 /* We ignore the subreg offset when calculating the regno,
4894 because we are using the entire underlying hard register
4904 if (regno >= FIRST_PSEUDO_REGISTER)
4911 /* Storing into a spilled-reg invalidates its contents.
4912 This can happen if a block-local pseudo is allocated to that reg
4913 and it wasn't spilled because this block's total need is 0.
4914 Then some insn might have an optional reload and use this reg. */
4916 for (i = 0; i < nr; i++)
4917 /* But don't do this if the reg actually serves as an output
4918 reload reg in the current instruction. */
4920 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4922 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4923 spill_reg_store[regno + i] = 0;
4929 SET_REGNO_REG_SET (regs, regno + nr);
4932 /* Since value of X has changed,
4933 forget any value previously copied from it. */
4936 /* But don't forget a copy if this is the output reload
4937 that establishes the copy's validity. */
4939 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4940 reg_last_reload_reg[regno + nr] = 0;
4944 /* Forget the reloads marked in regset by previous function. */
4946 forget_marked_reloads (regset regs)
4949 reg_set_iterator rsi;
4950 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4952 if (reg < FIRST_PSEUDO_REGISTER
4953 /* But don't do this if the reg actually serves as an output
4954 reload reg in the current instruction. */
4956 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4958 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4959 spill_reg_store[reg] = 0;
4962 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4963 reg_last_reload_reg[reg] = 0;
4967 /* The following HARD_REG_SETs indicate when each hard register is
4968 used for a reload of various parts of the current insn. */
4970 /* If reg is unavailable for all reloads. */
4971 static HARD_REG_SET reload_reg_unavailable;
4972 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4973 static HARD_REG_SET reload_reg_used;
4974 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4975 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4976 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4977 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4978 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4979 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4980 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4981 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4982 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4983 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4984 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4985 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4986 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4987 static HARD_REG_SET reload_reg_used_in_op_addr;
4988 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4989 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4990 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4991 static HARD_REG_SET reload_reg_used_in_insn;
4992 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4993 static HARD_REG_SET reload_reg_used_in_other_addr;
4995 /* If reg is in use as a reload reg for any sort of reload. */
4996 static HARD_REG_SET reload_reg_used_at_all;
4998 /* If reg is use as an inherited reload. We just mark the first register
5000 static HARD_REG_SET reload_reg_used_for_inherit;
5002 /* Records which hard regs are used in any way, either as explicit use or
5003 by being allocated to a pseudo during any point of the current insn. */
5004 static HARD_REG_SET reg_used_in_insn;
5006 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5007 TYPE. MODE is used to indicate how many consecutive regs are
5011 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5017 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5020 case RELOAD_FOR_INPUT_ADDRESS:
5021 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5024 case RELOAD_FOR_INPADDR_ADDRESS:
5025 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5028 case RELOAD_FOR_OUTPUT_ADDRESS:
5029 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5032 case RELOAD_FOR_OUTADDR_ADDRESS:
5033 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5036 case RELOAD_FOR_OPERAND_ADDRESS:
5037 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5040 case RELOAD_FOR_OPADDR_ADDR:
5041 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5044 case RELOAD_FOR_OTHER_ADDRESS:
5045 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5048 case RELOAD_FOR_INPUT:
5049 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5052 case RELOAD_FOR_OUTPUT:
5053 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5056 case RELOAD_FOR_INSN:
5057 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5061 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5064 /* Similarly, but show REGNO is no longer in use for a reload. */
5067 clear_reload_reg_in_use (unsigned int regno, int opnum,
5068 enum reload_type type, machine_mode mode)
5070 unsigned int nregs = hard_regno_nregs (regno, mode);
5071 unsigned int start_regno, end_regno, r;
5073 /* A complication is that for some reload types, inheritance might
5074 allow multiple reloads of the same types to share a reload register.
5075 We set check_opnum if we have to check only reloads with the same
5076 operand number, and check_any if we have to check all reloads. */
5077 int check_opnum = 0;
5079 HARD_REG_SET *used_in_set;
5084 used_in_set = &reload_reg_used;
5087 case RELOAD_FOR_INPUT_ADDRESS:
5088 used_in_set = &reload_reg_used_in_input_addr[opnum];
5091 case RELOAD_FOR_INPADDR_ADDRESS:
5093 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5096 case RELOAD_FOR_OUTPUT_ADDRESS:
5097 used_in_set = &reload_reg_used_in_output_addr[opnum];
5100 case RELOAD_FOR_OUTADDR_ADDRESS:
5102 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5105 case RELOAD_FOR_OPERAND_ADDRESS:
5106 used_in_set = &reload_reg_used_in_op_addr;
5109 case RELOAD_FOR_OPADDR_ADDR:
5111 used_in_set = &reload_reg_used_in_op_addr_reload;
5114 case RELOAD_FOR_OTHER_ADDRESS:
5115 used_in_set = &reload_reg_used_in_other_addr;
5119 case RELOAD_FOR_INPUT:
5120 used_in_set = &reload_reg_used_in_input[opnum];
5123 case RELOAD_FOR_OUTPUT:
5124 used_in_set = &reload_reg_used_in_output[opnum];
5127 case RELOAD_FOR_INSN:
5128 used_in_set = &reload_reg_used_in_insn;
5133 /* We resolve conflicts with remaining reloads of the same type by
5134 excluding the intervals of reload registers by them from the
5135 interval of freed reload registers. Since we only keep track of
5136 one set of interval bounds, we might have to exclude somewhat
5137 more than what would be necessary if we used a HARD_REG_SET here.
5138 But this should only happen very infrequently, so there should
5139 be no reason to worry about it. */
5141 start_regno = regno;
5142 end_regno = regno + nregs;
5143 if (check_opnum || check_any)
5145 for (i = n_reloads - 1; i >= 0; i--)
5147 if (rld[i].when_needed == type
5148 && (check_any || rld[i].opnum == opnum)
5151 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5152 unsigned int conflict_end
5153 = end_hard_regno (rld[i].mode, conflict_start);
5155 /* If there is an overlap with the first to-be-freed register,
5156 adjust the interval start. */
5157 if (conflict_start <= start_regno && conflict_end > start_regno)
5158 start_regno = conflict_end;
5159 /* Otherwise, if there is a conflict with one of the other
5160 to-be-freed registers, adjust the interval end. */
5161 if (conflict_start > start_regno && conflict_start < end_regno)
5162 end_regno = conflict_start;
5167 for (r = start_regno; r < end_regno; r++)
5168 CLEAR_HARD_REG_BIT (*used_in_set, r);
5171 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5172 specified by OPNUM and TYPE. */
5175 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5179 /* In use for a RELOAD_OTHER means it's not available for anything. */
5180 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5181 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5187 /* In use for anything means we can't use it for RELOAD_OTHER. */
5188 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5189 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5190 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5191 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5194 for (i = 0; i < reload_n_operands; i++)
5195 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5196 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5197 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5198 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5199 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5200 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5205 case RELOAD_FOR_INPUT:
5206 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5207 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5210 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5213 /* If it is used for some other input, can't use it. */
5214 for (i = 0; i < reload_n_operands; i++)
5215 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5218 /* If it is used in a later operand's address, can't use it. */
5219 for (i = opnum + 1; i < reload_n_operands; i++)
5220 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5221 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5226 case RELOAD_FOR_INPUT_ADDRESS:
5227 /* Can't use a register if it is used for an input address for this
5228 operand or used as an input in an earlier one. */
5229 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5230 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5233 for (i = 0; i < opnum; i++)
5234 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5239 case RELOAD_FOR_INPADDR_ADDRESS:
5240 /* Can't use a register if it is used for an input address
5241 for this operand or used as an input in an earlier
5243 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5246 for (i = 0; i < opnum; i++)
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5252 case RELOAD_FOR_OUTPUT_ADDRESS:
5253 /* Can't use a register if it is used for an output address for this
5254 operand or used as an output in this or a later operand. Note
5255 that multiple output operands are emitted in reverse order, so
5256 the conflicting ones are those with lower indices. */
5257 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5260 for (i = 0; i <= opnum; i++)
5261 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5266 case RELOAD_FOR_OUTADDR_ADDRESS:
5267 /* Can't use a register if it is used for an output address
5268 for this operand or used as an output in this or a
5269 later operand. Note that multiple output operands are
5270 emitted in reverse order, so the conflicting ones are
5271 those with lower indices. */
5272 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5275 for (i = 0; i <= opnum; i++)
5276 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5281 case RELOAD_FOR_OPERAND_ADDRESS:
5282 for (i = 0; i < reload_n_operands; i++)
5283 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5286 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5287 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5289 case RELOAD_FOR_OPADDR_ADDR:
5290 for (i = 0; i < reload_n_operands; i++)
5291 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5294 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5296 case RELOAD_FOR_OUTPUT:
5297 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5298 outputs, or an operand address for this or an earlier output.
5299 Note that multiple output operands are emitted in reverse order,
5300 so the conflicting ones are those with higher indices. */
5301 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5304 for (i = 0; i < reload_n_operands; i++)
5305 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5308 for (i = opnum; i < reload_n_operands; i++)
5309 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5310 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5315 case RELOAD_FOR_INSN:
5316 for (i = 0; i < reload_n_operands; i++)
5317 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5318 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5321 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5322 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5324 case RELOAD_FOR_OTHER_ADDRESS:
5325 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5332 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5333 the number RELOADNUM, is still available in REGNO at the end of the insn.
5335 We can assume that the reload reg was already tested for availability
5336 at the time it is needed, and we should not check this again,
5337 in case the reg has already been marked in use. */
5340 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5342 int opnum = rld[reloadnum].opnum;
5343 enum reload_type type = rld[reloadnum].when_needed;
5346 /* See if there is a reload with the same type for this operand, using
5347 the same register. This case is not handled by the code below. */
5348 for (i = reloadnum + 1; i < n_reloads; i++)
5352 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5354 reg = rld[i].reg_rtx;
5355 if (reg == NULL_RTX)
5357 if (regno >= REGNO (reg) && regno < END_REGNO (reg))
5364 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5365 its value must reach the end. */
5368 /* If this use is for part of the insn,
5369 its value reaches if no subsequent part uses the same register.
5370 Just like the above function, don't try to do this with lots
5373 case RELOAD_FOR_OTHER_ADDRESS:
5374 /* Here we check for everything else, since these don't conflict
5375 with anything else and everything comes later. */
5377 for (i = 0; i < reload_n_operands; i++)
5378 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5379 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5380 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5381 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5382 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5383 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5386 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5387 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5388 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5389 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5391 case RELOAD_FOR_INPUT_ADDRESS:
5392 case RELOAD_FOR_INPADDR_ADDRESS:
5393 /* Similar, except that we check only for this and subsequent inputs
5394 and the address of only subsequent inputs and we do not need
5395 to check for RELOAD_OTHER objects since they are known not to
5398 for (i = opnum; i < reload_n_operands; i++)
5399 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5402 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5403 could be killed if the register is also used by reload with type
5404 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5405 if (type == RELOAD_FOR_INPADDR_ADDRESS
5406 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5409 for (i = opnum + 1; i < reload_n_operands; i++)
5410 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5411 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5414 for (i = 0; i < reload_n_operands; i++)
5415 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5416 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5417 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5420 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5423 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5424 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5425 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5427 case RELOAD_FOR_INPUT:
5428 /* Similar to input address, except we start at the next operand for
5429 both input and input address and we do not check for
5430 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5433 for (i = opnum + 1; i < reload_n_operands; i++)
5434 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5435 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5436 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5439 /* ... fall through ... */
5441 case RELOAD_FOR_OPERAND_ADDRESS:
5442 /* Check outputs and their addresses. */
5444 for (i = 0; i < reload_n_operands; i++)
5445 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5446 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5447 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5450 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5452 case RELOAD_FOR_OPADDR_ADDR:
5453 for (i = 0; i < reload_n_operands; i++)
5454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5455 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5456 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5459 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5460 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5461 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5463 case RELOAD_FOR_INSN:
5464 /* These conflict with other outputs with RELOAD_OTHER. So
5465 we need only check for output addresses. */
5467 opnum = reload_n_operands;
5471 case RELOAD_FOR_OUTPUT:
5472 case RELOAD_FOR_OUTPUT_ADDRESS:
5473 case RELOAD_FOR_OUTADDR_ADDRESS:
5474 /* We already know these can't conflict with a later output. So the
5475 only thing to check are later output addresses.
5476 Note that multiple output operands are emitted in reverse order,
5477 so the conflicting ones are those with lower indices. */
5478 for (i = 0; i < opnum; i++)
5479 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5480 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5483 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5484 could be killed if the register is also used by reload with type
5485 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5486 if (type == RELOAD_FOR_OUTADDR_ADDRESS
5487 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5497 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5498 every register in REG. */
5501 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5505 for (i = REGNO (reg); i < END_REGNO (reg); i++)
5506 if (!reload_reg_reaches_end_p (i, reloadnum))
5512 /* Returns whether R1 and R2 are uniquely chained: the value of one
5513 is used by the other, and that value is not used by any other
5514 reload for this insn. This is used to partially undo the decision
5515 made in find_reloads when in the case of multiple
5516 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5517 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5518 reloads. This code tries to avoid the conflict created by that
5519 change. It might be cleaner to explicitly keep track of which
5520 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5521 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5522 this after the fact. */
5524 reloads_unique_chain_p (int r1, int r2)
5528 /* We only check input reloads. */
5529 if (! rld[r1].in || ! rld[r2].in)
5532 /* Avoid anything with output reloads. */
5533 if (rld[r1].out || rld[r2].out)
5536 /* "chained" means one reload is a component of the other reload,
5537 not the same as the other reload. */
5538 if (rld[r1].opnum != rld[r2].opnum
5539 || rtx_equal_p (rld[r1].in, rld[r2].in)
5540 || rld[r1].optional || rld[r2].optional
5541 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5542 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5545 /* The following loop assumes that r1 is the reload that feeds r2. */
5549 for (i = 0; i < n_reloads; i ++)
5550 /* Look for input reloads that aren't our two */
5551 if (i != r1 && i != r2 && rld[i].in)
5553 /* If our reload is mentioned at all, it isn't a simple chain. */
5554 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5560 /* The recursive function change all occurrences of WHAT in *WHERE
5563 substitute (rtx *where, const_rtx what, rtx repl)
5572 if (*where == what || rtx_equal_p (*where, what))
5574 /* Record the location of the changed rtx. */
5575 substitute_stack.safe_push (where);
5580 code = GET_CODE (*where);
5581 fmt = GET_RTX_FORMAT (code);
5582 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5588 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5589 substitute (&XVECEXP (*where, i, j), what, repl);
5591 else if (fmt[i] == 'e')
5592 substitute (&XEXP (*where, i), what, repl);
5596 /* The function returns TRUE if chain of reload R1 and R2 (in any
5597 order) can be evaluated without usage of intermediate register for
5598 the reload containing another reload. It is important to see
5599 gen_reload to understand what the function is trying to do. As an
5600 example, let us have reload chain
5603 r1: <something> + const
5605 and reload R2 got reload reg HR. The function returns true if
5606 there is a correct insn HR = HR + <something>. Otherwise,
5607 gen_reload will use intermediate register (and this is the reload
5608 reg for R1) to reload <something>.
5610 We need this function to find a conflict for chain reloads. In our
5611 example, if HR = HR + <something> is incorrect insn, then we cannot
5612 use HR as a reload register for R2. If we do use it then we get a
5621 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5623 /* Assume other cases in gen_reload are not possible for
5624 chain reloads or do need an intermediate hard registers. */
5629 rtx_insn *last = get_last_insn ();
5631 /* Make r2 a component of r1. */
5632 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5635 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5636 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5637 gcc_assert (regno >= 0);
5638 out = gen_rtx_REG (rld[r1].mode, regno);
5640 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5642 /* If IN is a paradoxical SUBREG, remove it and try to put the
5643 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5644 strip_paradoxical_subreg (&in, &out);
5646 if (GET_CODE (in) == PLUS
5647 && (REG_P (XEXP (in, 0))
5648 || GET_CODE (XEXP (in, 0)) == SUBREG
5649 || MEM_P (XEXP (in, 0)))
5650 && (REG_P (XEXP (in, 1))
5651 || GET_CODE (XEXP (in, 1)) == SUBREG
5652 || CONSTANT_P (XEXP (in, 1))
5653 || MEM_P (XEXP (in, 1))))
5655 insn = emit_insn (gen_rtx_SET (out, in));
5656 code = recog_memoized (insn);
5661 extract_insn (insn);
5662 /* We want constrain operands to treat this insn strictly in
5663 its validity determination, i.e., the way it would after
5664 reload has completed. */
5665 result = constrain_operands (1, get_enabled_alternatives (insn));
5668 delete_insns_since (last);
5671 /* Restore the original value at each changed address within R1. */
5672 while (!substitute_stack.is_empty ())
5674 rtx *where = substitute_stack.pop ();
5675 *where = rld[r2].in;
5681 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5684 This function uses the same algorithm as reload_reg_free_p above. */
5687 reloads_conflict (int r1, int r2)
5689 enum reload_type r1_type = rld[r1].when_needed;
5690 enum reload_type r2_type = rld[r2].when_needed;
5691 int r1_opnum = rld[r1].opnum;
5692 int r2_opnum = rld[r2].opnum;
5694 /* RELOAD_OTHER conflicts with everything. */
5695 if (r2_type == RELOAD_OTHER)
5698 /* Otherwise, check conflicts differently for each type. */
5702 case RELOAD_FOR_INPUT:
5703 return (r2_type == RELOAD_FOR_INSN
5704 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5705 || r2_type == RELOAD_FOR_OPADDR_ADDR
5706 || r2_type == RELOAD_FOR_INPUT
5707 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5708 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5709 && r2_opnum > r1_opnum));
5711 case RELOAD_FOR_INPUT_ADDRESS:
5712 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5713 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5715 case RELOAD_FOR_INPADDR_ADDRESS:
5716 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5717 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5719 case RELOAD_FOR_OUTPUT_ADDRESS:
5720 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5721 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5723 case RELOAD_FOR_OUTADDR_ADDRESS:
5724 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5725 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5727 case RELOAD_FOR_OPERAND_ADDRESS:
5728 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5729 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5730 && (!reloads_unique_chain_p (r1, r2)
5731 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5733 case RELOAD_FOR_OPADDR_ADDR:
5734 return (r2_type == RELOAD_FOR_INPUT
5735 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5737 case RELOAD_FOR_OUTPUT:
5738 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5739 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5740 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5741 && r2_opnum >= r1_opnum));
5743 case RELOAD_FOR_INSN:
5744 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5745 || r2_type == RELOAD_FOR_INSN
5746 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5748 case RELOAD_FOR_OTHER_ADDRESS:
5749 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5759 /* Indexed by reload number, 1 if incoming value
5760 inherited from previous insns. */
5761 static char reload_inherited[MAX_RELOADS];
5763 /* For an inherited reload, this is the insn the reload was inherited from,
5764 if we know it. Otherwise, this is 0. */
5765 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5767 /* If nonzero, this is a place to get the value of the reload,
5768 rather than using reload_in. */
5769 static rtx reload_override_in[MAX_RELOADS];
5771 /* For each reload, the hard register number of the register used,
5772 or -1 if we did not need a register for this reload. */
5773 static int reload_spill_index[MAX_RELOADS];
5775 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5776 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5778 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5779 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5781 /* Subroutine of free_for_value_p, used to check a single register.
5782 START_REGNO is the starting regno of the full reload register
5783 (possibly comprising multiple hard registers) that we are considering. */
5786 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5787 enum reload_type type, rtx value, rtx out,
5788 int reloadnum, int ignore_address_reloads)
5791 /* Set if we see an input reload that must not share its reload register
5792 with any new earlyclobber, but might otherwise share the reload
5793 register with an output or input-output reload. */
5794 int check_earlyclobber = 0;
5798 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5801 if (out == const0_rtx)
5807 /* We use some pseudo 'time' value to check if the lifetimes of the
5808 new register use would overlap with the one of a previous reload
5809 that is not read-only or uses a different value.
5810 The 'time' used doesn't have to be linear in any shape or form, just
5812 Some reload types use different 'buckets' for each operand.
5813 So there are MAX_RECOG_OPERANDS different time values for each
5815 We compute TIME1 as the time when the register for the prospective
5816 new reload ceases to be live, and TIME2 for each existing
5817 reload as the time when that the reload register of that reload
5819 Where there is little to be gained by exact lifetime calculations,
5820 we just make conservative assumptions, i.e. a longer lifetime;
5821 this is done in the 'default:' cases. */
5824 case RELOAD_FOR_OTHER_ADDRESS:
5825 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5826 time1 = copy ? 0 : 1;
5829 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5831 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5832 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5833 respectively, to the time values for these, we get distinct time
5834 values. To get distinct time values for each operand, we have to
5835 multiply opnum by at least three. We round that up to four because
5836 multiply by four is often cheaper. */
5837 case RELOAD_FOR_INPADDR_ADDRESS:
5838 time1 = opnum * 4 + 2;
5840 case RELOAD_FOR_INPUT_ADDRESS:
5841 time1 = opnum * 4 + 3;
5843 case RELOAD_FOR_INPUT:
5844 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5845 executes (inclusive). */
5846 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5848 case RELOAD_FOR_OPADDR_ADDR:
5850 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5851 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5853 case RELOAD_FOR_OPERAND_ADDRESS:
5854 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5856 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5858 case RELOAD_FOR_OUTADDR_ADDRESS:
5859 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5861 case RELOAD_FOR_OUTPUT_ADDRESS:
5862 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5865 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5868 for (i = 0; i < n_reloads; i++)
5870 rtx reg = rld[i].reg_rtx;
5871 if (reg && REG_P (reg)
5872 && (unsigned) regno - true_regnum (reg) < REG_NREGS (reg)
5875 rtx other_input = rld[i].in;
5877 /* If the other reload loads the same input value, that
5878 will not cause a conflict only if it's loading it into
5879 the same register. */
5880 if (true_regnum (reg) != start_regno)
5881 other_input = NULL_RTX;
5882 if (! other_input || ! rtx_equal_p (other_input, value)
5883 || rld[i].out || out)
5886 switch (rld[i].when_needed)
5888 case RELOAD_FOR_OTHER_ADDRESS:
5891 case RELOAD_FOR_INPADDR_ADDRESS:
5892 /* find_reloads makes sure that a
5893 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5894 by at most one - the first -
5895 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5896 address reload is inherited, the address address reload
5897 goes away, so we can ignore this conflict. */
5898 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5899 && ignore_address_reloads
5900 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5901 Then the address address is still needed to store
5902 back the new address. */
5903 && ! rld[reloadnum].out)
5905 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5906 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5908 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5909 && ignore_address_reloads
5910 /* Unless we are reloading an auto_inc expression. */
5911 && ! rld[reloadnum].out)
5913 time2 = rld[i].opnum * 4 + 2;
5915 case RELOAD_FOR_INPUT_ADDRESS:
5916 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5917 && ignore_address_reloads
5918 && ! rld[reloadnum].out)
5920 time2 = rld[i].opnum * 4 + 3;
5922 case RELOAD_FOR_INPUT:
5923 time2 = rld[i].opnum * 4 + 4;
5924 check_earlyclobber = 1;
5926 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5927 == MAX_RECOG_OPERAND * 4 */
5928 case RELOAD_FOR_OPADDR_ADDR:
5929 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5930 && ignore_address_reloads
5931 && ! rld[reloadnum].out)
5933 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5935 case RELOAD_FOR_OPERAND_ADDRESS:
5936 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5937 check_earlyclobber = 1;
5939 case RELOAD_FOR_INSN:
5940 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5942 case RELOAD_FOR_OUTPUT:
5943 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5944 instruction is executed. */
5945 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5947 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5948 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5950 case RELOAD_FOR_OUTADDR_ADDRESS:
5951 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5952 && ignore_address_reloads
5953 && ! rld[reloadnum].out)
5955 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5957 case RELOAD_FOR_OUTPUT_ADDRESS:
5958 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5961 /* If there is no conflict in the input part, handle this
5962 like an output reload. */
5963 if (! rld[i].in || rtx_equal_p (other_input, value))
5965 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5966 /* Earlyclobbered outputs must conflict with inputs. */
5967 if (earlyclobber_operand_p (rld[i].out))
5968 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5973 /* RELOAD_OTHER might be live beyond instruction execution,
5974 but this is not obvious when we set time2 = 1. So check
5975 here if there might be a problem with the new reload
5976 clobbering the register used by the RELOAD_OTHER. */
5984 && (! rld[i].in || rld[i].out
5985 || ! rtx_equal_p (other_input, value)))
5986 || (out && rld[reloadnum].out_reg
5987 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5993 /* Earlyclobbered outputs must conflict with inputs. */
5994 if (check_earlyclobber && out && earlyclobber_operand_p (out))
6000 /* Return 1 if the value in reload reg REGNO, as used by a reload
6001 needed for the part of the insn specified by OPNUM and TYPE,
6002 may be used to load VALUE into it.
6004 MODE is the mode in which the register is used, this is needed to
6005 determine how many hard regs to test.
6007 Other read-only reloads with the same value do not conflict
6008 unless OUT is nonzero and these other reloads have to live while
6009 output reloads live.
6010 If OUT is CONST0_RTX, this is a special case: it means that the
6011 test should not be for using register REGNO as reload register, but
6012 for copying from register REGNO into the reload register.
6014 RELOADNUM is the number of the reload we want to load this value for;
6015 a reload does not conflict with itself.
6017 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6018 reloads that load an address for the very reload we are considering.
6020 The caller has to make sure that there is no conflict with the return
6024 free_for_value_p (int regno, machine_mode mode, int opnum,
6025 enum reload_type type, rtx value, rtx out, int reloadnum,
6026 int ignore_address_reloads)
6028 int nregs = hard_regno_nregs (regno, mode);
6030 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6031 value, out, reloadnum,
6032 ignore_address_reloads))
6037 /* Return nonzero if the rtx X is invariant over the current function. */
6038 /* ??? Actually, the places where we use this expect exactly what is
6039 tested here, and not everything that is function invariant. In
6040 particular, the frame pointer and arg pointer are special cased;
6041 pic_offset_table_rtx is not, and we must not spill these things to
6045 function_invariant_p (const_rtx x)
6049 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6051 if (GET_CODE (x) == PLUS
6052 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6053 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6058 /* Determine whether the reload reg X overlaps any rtx'es used for
6059 overriding inheritance. Return nonzero if so. */
6062 conflicts_with_override (rtx x)
6065 for (i = 0; i < n_reloads; i++)
6066 if (reload_override_in[i]
6067 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6072 /* Give an error message saying we failed to find a reload for INSN,
6073 and clear out reload R. */
6075 failed_reload (rtx_insn *insn, int r)
6077 if (asm_noperands (PATTERN (insn)) < 0)
6078 /* It's the compiler's fault. */
6079 fatal_insn ("could not find a spill register", insn);
6081 /* It's the user's fault; the operand's mode and constraint
6082 don't match. Disable this reload so we don't crash in final. */
6083 error_for_asm (insn,
6084 "%<asm%> operand constraint incompatible with operand size");
6088 rld[r].optional = 1;
6089 rld[r].secondary_p = 1;
6092 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6093 for reload R. If it's valid, get an rtx for it. Return nonzero if
6096 set_reload_reg (int i, int r)
6099 rtx reg = spill_reg_rtx[i];
6101 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6102 spill_reg_rtx[i] = reg
6103 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6105 regno = true_regnum (reg);
6107 /* Detect when the reload reg can't hold the reload mode.
6108 This used to be one `if', but Sequent compiler can't handle that. */
6109 if (targetm.hard_regno_mode_ok (regno, rld[r].mode))
6111 machine_mode test_mode = VOIDmode;
6113 test_mode = GET_MODE (rld[r].in);
6114 /* If rld[r].in has VOIDmode, it means we will load it
6115 in whatever mode the reload reg has: to wit, rld[r].mode.
6116 We have already tested that for validity. */
6117 /* Aside from that, we need to test that the expressions
6118 to reload from or into have modes which are valid for this
6119 reload register. Otherwise the reload insns would be invalid. */
6120 if (! (rld[r].in != 0 && test_mode != VOIDmode
6121 && !targetm.hard_regno_mode_ok (regno, test_mode)))
6122 if (! (rld[r].out != 0
6123 && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out))))
6125 /* The reg is OK. */
6128 /* Mark as in use for this insn the reload regs we use
6130 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6131 rld[r].when_needed, rld[r].mode);
6133 rld[r].reg_rtx = reg;
6134 reload_spill_index[r] = spill_regs[i];
6141 /* Find a spill register to use as a reload register for reload R.
6142 LAST_RELOAD is nonzero if this is the last reload for the insn being
6145 Set rld[R].reg_rtx to the register allocated.
6147 We return 1 if successful, or 0 if we couldn't find a spill reg and
6148 we didn't change anything. */
6151 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6156 /* If we put this reload ahead, thinking it is a group,
6157 then insist on finding a group. Otherwise we can grab a
6158 reg that some other reload needs.
6159 (That can happen when we have a 68000 DATA_OR_FP_REG
6160 which is a group of data regs or one fp reg.)
6161 We need not be so restrictive if there are no more reloads
6164 ??? Really it would be nicer to have smarter handling
6165 for that kind of reg class, where a problem like this is normal.
6166 Perhaps those classes should be avoided for reloading
6167 by use of more alternatives. */
6169 int force_group = rld[r].nregs > 1 && ! last_reload;
6171 /* If we want a single register and haven't yet found one,
6172 take any reg in the right class and not in use.
6173 If we want a consecutive group, here is where we look for it.
6175 We use three passes so we can first look for reload regs to
6176 reuse, which are already in use for other reloads in this insn,
6177 and only then use additional registers which are not "bad", then
6178 finally any register.
6180 I think that maximizing reuse is needed to make sure we don't
6181 run out of reload regs. Suppose we have three reloads, and
6182 reloads A and B can share regs. These need two regs.
6183 Suppose A and B are given different regs.
6184 That leaves none for C. */
6185 for (pass = 0; pass < 3; pass++)
6187 /* I is the index in spill_regs.
6188 We advance it round-robin between insns to use all spill regs
6189 equally, so that inherited reloads have a chance
6190 of leapfrogging each other. */
6194 for (count = 0; count < n_spills; count++)
6196 int rclass = (int) rld[r].rclass;
6202 regnum = spill_regs[i];
6204 if ((reload_reg_free_p (regnum, rld[r].opnum,
6207 /* We check reload_reg_used to make sure we
6208 don't clobber the return register. */
6209 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6210 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6211 rld[r].when_needed, rld[r].in,
6213 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6214 && targetm.hard_regno_mode_ok (regnum, rld[r].mode)
6215 /* Look first for regs to share, then for unshared. But
6216 don't share regs used for inherited reloads; they are
6217 the ones we want to preserve. */
6219 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6221 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6224 int nr = hard_regno_nregs (regnum, rld[r].mode);
6226 /* During the second pass we want to avoid reload registers
6227 which are "bad" for this reload. */
6229 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6232 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6233 (on 68000) got us two FP regs. If NR is 1,
6234 we would reject both of them. */
6237 /* If we need only one reg, we have already won. */
6240 /* But reject a single reg if we demand a group. */
6245 /* Otherwise check that as many consecutive regs as we need
6246 are available here. */
6249 int regno = regnum + nr - 1;
6250 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6251 && spill_reg_order[regno] >= 0
6252 && reload_reg_free_p (regno, rld[r].opnum,
6253 rld[r].when_needed)))
6262 /* If we found something on the current pass, omit later passes. */
6263 if (count < n_spills)
6267 /* We should have found a spill register by now. */
6268 if (count >= n_spills)
6271 /* I is the index in SPILL_REG_RTX of the reload register we are to
6272 allocate. Get an rtx for it and find its register number. */
6274 return set_reload_reg (i, r);
6277 /* Initialize all the tables needed to allocate reload registers.
6278 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6279 is the array we use to restore the reg_rtx field for every reload. */
6282 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6286 for (i = 0; i < n_reloads; i++)
6287 rld[i].reg_rtx = save_reload_reg_rtx[i];
6289 memset (reload_inherited, 0, MAX_RELOADS);
6290 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6291 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6293 CLEAR_HARD_REG_SET (reload_reg_used);
6294 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6295 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6296 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6297 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6298 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6300 CLEAR_HARD_REG_SET (reg_used_in_insn);
6303 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6304 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6305 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6306 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6307 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6308 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6311 for (i = 0; i < reload_n_operands; i++)
6313 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6314 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6315 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6316 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6317 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6318 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6321 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6323 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6325 for (i = 0; i < n_reloads; i++)
6326 /* If we have already decided to use a certain register,
6327 don't use it in another way. */
6329 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6330 rld[i].when_needed, rld[i].mode);
6333 /* If X is not a subreg, return it unmodified. If it is a subreg,
6334 look up whether we made a replacement for the SUBREG_REG. Return
6335 either the replacement or the SUBREG_REG. */
6338 replaced_subreg (rtx x)
6340 if (GET_CODE (x) == SUBREG)
6341 return find_replacement (&SUBREG_REG (x));
6345 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6346 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6347 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6348 otherwise it is NULL. */
6351 compute_reload_subreg_offset (machine_mode outermode,
6353 machine_mode innermode)
6355 poly_int64 outer_offset;
6356 machine_mode middlemode;
6359 return subreg_lowpart_offset (outermode, innermode);
6361 outer_offset = SUBREG_BYTE (subreg);
6362 middlemode = GET_MODE (SUBREG_REG (subreg));
6364 /* If SUBREG is paradoxical then return the normal lowpart offset
6365 for OUTERMODE and INNERMODE. Our caller has already checked
6366 that OUTERMODE fits in INNERMODE. */
6367 if (paradoxical_subreg_p (outermode, middlemode))
6368 return subreg_lowpart_offset (outermode, innermode);
6370 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6371 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6372 return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6375 /* Assign hard reg targets for the pseudo-registers we must reload
6376 into hard regs for this insn.
6377 Also output the instructions to copy them in and out of the hard regs.
6379 For machines with register classes, we are responsible for
6380 finding a reload reg in the proper class. */
6383 choose_reload_regs (struct insn_chain *chain)
6385 rtx_insn *insn = chain->insn;
6387 unsigned int max_group_size = 1;
6388 enum reg_class group_class = NO_REGS;
6389 int pass, win, inheritance;
6391 rtx save_reload_reg_rtx[MAX_RELOADS];
6393 /* In order to be certain of getting the registers we need,
6394 we must sort the reloads into order of increasing register class.
6395 Then our grabbing of reload registers will parallel the process
6396 that provided the reload registers.
6398 Also note whether any of the reloads wants a consecutive group of regs.
6399 If so, record the maximum size of the group desired and what
6400 register class contains all the groups needed by this insn. */
6402 for (j = 0; j < n_reloads; j++)
6404 reload_order[j] = j;
6405 if (rld[j].reg_rtx != NULL_RTX)
6407 gcc_assert (REG_P (rld[j].reg_rtx)
6408 && HARD_REGISTER_P (rld[j].reg_rtx));
6409 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6412 reload_spill_index[j] = -1;
6414 if (rld[j].nregs > 1)
6416 max_group_size = MAX (rld[j].nregs, max_group_size);
6418 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6421 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6425 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6427 /* If -O, try first with inheritance, then turning it off.
6428 If not -O, don't do inheritance.
6429 Using inheritance when not optimizing leads to paradoxes
6430 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6431 because one side of the comparison might be inherited. */
6433 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6435 choose_reload_regs_init (chain, save_reload_reg_rtx);
6437 /* Process the reloads in order of preference just found.
6438 Beyond this point, subregs can be found in reload_reg_rtx.
6440 This used to look for an existing reloaded home for all of the
6441 reloads, and only then perform any new reloads. But that could lose
6442 if the reloads were done out of reg-class order because a later
6443 reload with a looser constraint might have an old home in a register
6444 needed by an earlier reload with a tighter constraint.
6446 To solve this, we make two passes over the reloads, in the order
6447 described above. In the first pass we try to inherit a reload
6448 from a previous insn. If there is a later reload that needs a
6449 class that is a proper subset of the class being processed, we must
6450 also allocate a spill register during the first pass.
6452 Then make a second pass over the reloads to allocate any reloads
6453 that haven't been given registers yet. */
6455 for (j = 0; j < n_reloads; j++)
6457 int r = reload_order[j];
6458 rtx search_equiv = NULL_RTX;
6460 /* Ignore reloads that got marked inoperative. */
6461 if (rld[r].out == 0 && rld[r].in == 0
6462 && ! rld[r].secondary_p)
6465 /* If find_reloads chose to use reload_in or reload_out as a reload
6466 register, we don't need to chose one. Otherwise, try even if it
6467 found one since we might save an insn if we find the value lying
6469 Try also when reload_in is a pseudo without a hard reg. */
6470 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6471 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6472 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6473 && !MEM_P (rld[r].in)
6474 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6477 #if 0 /* No longer needed for correct operation.
6478 It might give better code, or might not; worth an experiment? */
6479 /* If this is an optional reload, we can't inherit from earlier insns
6480 until we are sure that any non-optional reloads have been allocated.
6481 The following code takes advantage of the fact that optional reloads
6482 are at the end of reload_order. */
6483 if (rld[r].optional != 0)
6484 for (i = 0; i < j; i++)
6485 if ((rld[reload_order[i]].out != 0
6486 || rld[reload_order[i]].in != 0
6487 || rld[reload_order[i]].secondary_p)
6488 && ! rld[reload_order[i]].optional
6489 && rld[reload_order[i]].reg_rtx == 0)
6490 allocate_reload_reg (chain, reload_order[i], 0);
6493 /* First see if this pseudo is already available as reloaded
6494 for a previous insn. We cannot try to inherit for reloads
6495 that are smaller than the maximum number of registers needed
6496 for groups unless the register we would allocate cannot be used
6499 We could check here to see if this is a secondary reload for
6500 an object that is already in a register of the desired class.
6501 This would avoid the need for the secondary reload register.
6502 But this is complex because we can't easily determine what
6503 objects might want to be loaded via this reload. So let a
6504 register be allocated here. In `emit_reload_insns' we suppress
6505 one of the loads in the case described above. */
6509 poly_int64 byte = 0;
6511 machine_mode mode = VOIDmode;
6512 rtx subreg = NULL_RTX;
6516 else if (REG_P (rld[r].in))
6518 regno = REGNO (rld[r].in);
6519 mode = GET_MODE (rld[r].in);
6521 else if (REG_P (rld[r].in_reg))
6523 regno = REGNO (rld[r].in_reg);
6524 mode = GET_MODE (rld[r].in_reg);
6526 else if (GET_CODE (rld[r].in_reg) == SUBREG
6527 && REG_P (SUBREG_REG (rld[r].in_reg)))
6529 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6530 if (regno < FIRST_PSEUDO_REGISTER)
6531 regno = subreg_regno (rld[r].in_reg);
6534 subreg = rld[r].in_reg;
6535 byte = SUBREG_BYTE (subreg);
6537 mode = GET_MODE (rld[r].in_reg);
6540 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6541 && REG_P (XEXP (rld[r].in_reg, 0)))
6543 regno = REGNO (XEXP (rld[r].in_reg, 0));
6544 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6545 rld[r].out = rld[r].in;
6549 /* This won't work, since REGNO can be a pseudo reg number.
6550 Also, it takes much more hair to keep track of all the things
6551 that can invalidate an inherited reload of part of a pseudoreg. */
6552 else if (GET_CODE (rld[r].in) == SUBREG
6553 && REG_P (SUBREG_REG (rld[r].in)))
6554 regno = subreg_regno (rld[r].in);
6558 && reg_last_reload_reg[regno] != 0
6560 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])),
6561 GET_MODE_SIZE (mode) + byte))
6562 /* Verify that the register it's in can be used in
6564 && (REG_CAN_CHANGE_MODE_P
6565 (REGNO (reg_last_reload_reg[regno]),
6566 GET_MODE (reg_last_reload_reg[regno]),
6569 enum reg_class rclass = rld[r].rclass, last_class;
6570 rtx last_reg = reg_last_reload_reg[regno];
6572 i = REGNO (last_reg);
6573 byte = compute_reload_subreg_offset (mode,
6575 GET_MODE (last_reg));
6576 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6577 last_class = REGNO_REG_CLASS (i);
6579 if (reg_reloaded_contents[i] == regno
6580 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6581 && targetm.hard_regno_mode_ok (i, rld[r].mode)
6582 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6583 /* Even if we can't use this register as a reload
6584 register, we might use it for reload_override_in,
6585 if copying it to the desired class is cheap
6587 || ((register_move_cost (mode, last_class, rclass)
6588 < memory_move_cost (mode, rclass, true))
6589 && (secondary_reload_class (1, rclass, mode,
6592 && !(targetm.secondary_memory_needed
6593 (mode, last_class, rclass))))
6594 && (rld[r].nregs == max_group_size
6595 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6597 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6598 rld[r].when_needed, rld[r].in,
6601 /* If a group is needed, verify that all the subsequent
6602 registers still have their values intact. */
6603 int nr = hard_regno_nregs (i, rld[r].mode);
6606 for (k = 1; k < nr; k++)
6607 if (reg_reloaded_contents[i + k] != regno
6608 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6616 last_reg = (GET_MODE (last_reg) == mode
6617 ? last_reg : gen_rtx_REG (mode, i));
6620 for (k = 0; k < nr; k++)
6621 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6624 /* We found a register that contains the
6625 value we need. If this register is the
6626 same as an `earlyclobber' operand of the
6627 current insn, just mark it as a place to
6628 reload from since we can't use it as the
6629 reload register itself. */
6631 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6632 if (reg_overlap_mentioned_for_reload_p
6633 (reg_last_reload_reg[regno],
6634 reload_earlyclobbers[i1]))
6637 if (i1 != n_earlyclobbers
6638 || ! (free_for_value_p (i, rld[r].mode,
6640 rld[r].when_needed, rld[r].in,
6642 /* Don't use it if we'd clobber a pseudo reg. */
6643 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6645 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6646 /* Don't clobber the frame pointer. */
6647 || (i == HARD_FRAME_POINTER_REGNUM
6648 && frame_pointer_needed
6650 /* Don't really use the inherited spill reg
6651 if we need it wider than we've got it. */
6652 || paradoxical_subreg_p (rld[r].mode, mode)
6655 /* If find_reloads chose reload_out as reload
6656 register, stay with it - that leaves the
6657 inherited register for subsequent reloads. */
6658 || (rld[r].out && rld[r].reg_rtx
6659 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6661 if (! rld[r].optional)
6663 reload_override_in[r] = last_reg;
6664 reload_inheritance_insn[r]
6665 = reg_reloaded_insn[i];
6671 /* We can use this as a reload reg. */
6672 /* Mark the register as in use for this part of
6674 mark_reload_reg_in_use (i,
6678 rld[r].reg_rtx = last_reg;
6679 reload_inherited[r] = 1;
6680 reload_inheritance_insn[r]
6681 = reg_reloaded_insn[i];
6682 reload_spill_index[r] = i;
6683 for (k = 0; k < nr; k++)
6684 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6692 /* Here's another way to see if the value is already lying around. */
6695 && ! reload_inherited[r]
6697 && (CONSTANT_P (rld[r].in)
6698 || GET_CODE (rld[r].in) == PLUS
6699 || REG_P (rld[r].in)
6700 || MEM_P (rld[r].in))
6701 && (rld[r].nregs == max_group_size
6702 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6703 search_equiv = rld[r].in;
6708 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6709 -1, NULL, 0, rld[r].mode);
6715 regno = REGNO (equiv);
6718 /* This must be a SUBREG of a hard register.
6719 Make a new REG since this might be used in an
6720 address and not all machines support SUBREGs
6722 gcc_assert (GET_CODE (equiv) == SUBREG);
6723 regno = subreg_regno (equiv);
6724 equiv = gen_rtx_REG (rld[r].mode, regno);
6725 /* If we choose EQUIV as the reload register, but the
6726 loop below decides to cancel the inheritance, we'll
6727 end up reloading EQUIV in rld[r].mode, not the mode
6728 it had originally. That isn't safe when EQUIV isn't
6729 available as a spill register since its value might
6730 still be live at this point. */
6731 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6732 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6737 /* If we found a spill reg, reject it unless it is free
6738 and of the desired class. */
6742 int bad_for_class = 0;
6743 int max_regno = regno + rld[r].nregs;
6745 for (i = regno; i < max_regno; i++)
6747 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6749 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6754 && ! free_for_value_p (regno, rld[r].mode,
6755 rld[r].opnum, rld[r].when_needed,
6756 rld[r].in, rld[r].out, r, 1))
6762 && !targetm.hard_regno_mode_ok (regno, rld[r].mode))
6765 /* We found a register that contains the value we need.
6766 If this register is the same as an `earlyclobber' operand
6767 of the current insn, just mark it as a place to reload from
6768 since we can't use it as the reload register itself. */
6771 for (i = 0; i < n_earlyclobbers; i++)
6772 if (reg_overlap_mentioned_for_reload_p (equiv,
6773 reload_earlyclobbers[i]))
6775 if (! rld[r].optional)
6776 reload_override_in[r] = equiv;
6781 /* If the equiv register we have found is explicitly clobbered
6782 in the current insn, it depends on the reload type if we
6783 can use it, use it for reload_override_in, or not at all.
6784 In particular, we then can't use EQUIV for a
6785 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6789 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6790 switch (rld[r].when_needed)
6792 case RELOAD_FOR_OTHER_ADDRESS:
6793 case RELOAD_FOR_INPADDR_ADDRESS:
6794 case RELOAD_FOR_INPUT_ADDRESS:
6795 case RELOAD_FOR_OPADDR_ADDR:
6798 case RELOAD_FOR_INPUT:
6799 case RELOAD_FOR_OPERAND_ADDRESS:
6800 if (! rld[r].optional)
6801 reload_override_in[r] = equiv;
6807 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6808 switch (rld[r].when_needed)
6810 case RELOAD_FOR_OTHER_ADDRESS:
6811 case RELOAD_FOR_INPADDR_ADDRESS:
6812 case RELOAD_FOR_INPUT_ADDRESS:
6813 case RELOAD_FOR_OPADDR_ADDR:
6814 case RELOAD_FOR_OPERAND_ADDRESS:
6815 case RELOAD_FOR_INPUT:
6818 if (! rld[r].optional)
6819 reload_override_in[r] = equiv;
6827 /* If we found an equivalent reg, say no code need be generated
6828 to load it, and use it as our reload reg. */
6830 && (regno != HARD_FRAME_POINTER_REGNUM
6831 || !frame_pointer_needed))
6833 int nr = hard_regno_nregs (regno, rld[r].mode);
6835 rld[r].reg_rtx = equiv;
6836 reload_spill_index[r] = regno;
6837 reload_inherited[r] = 1;
6839 /* If reg_reloaded_valid is not set for this register,
6840 there might be a stale spill_reg_store lying around.
6841 We must clear it, since otherwise emit_reload_insns
6842 might delete the store. */
6843 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6844 spill_reg_store[regno] = NULL;
6845 /* If any of the hard registers in EQUIV are spill
6846 registers, mark them as in use for this insn. */
6847 for (k = 0; k < nr; k++)
6849 i = spill_reg_order[regno + k];
6852 mark_reload_reg_in_use (regno, rld[r].opnum,
6855 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6862 /* If we found a register to use already, or if this is an optional
6863 reload, we are done. */
6864 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6868 /* No longer needed for correct operation. Might or might
6869 not give better code on the average. Want to experiment? */
6871 /* See if there is a later reload that has a class different from our
6872 class that intersects our class or that requires less register
6873 than our reload. If so, we must allocate a register to this
6874 reload now, since that reload might inherit a previous reload
6875 and take the only available register in our class. Don't do this
6876 for optional reloads since they will force all previous reloads
6877 to be allocated. Also don't do this for reloads that have been
6880 for (i = j + 1; i < n_reloads; i++)
6882 int s = reload_order[i];
6884 if ((rld[s].in == 0 && rld[s].out == 0
6885 && ! rld[s].secondary_p)
6889 if ((rld[s].rclass != rld[r].rclass
6890 && reg_classes_intersect_p (rld[r].rclass,
6892 || rld[s].nregs < rld[r].nregs)
6899 allocate_reload_reg (chain, r, j == n_reloads - 1);
6903 /* Now allocate reload registers for anything non-optional that
6904 didn't get one yet. */
6905 for (j = 0; j < n_reloads; j++)
6907 int r = reload_order[j];
6909 /* Ignore reloads that got marked inoperative. */
6910 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6913 /* Skip reloads that already have a register allocated or are
6915 if (rld[r].reg_rtx != 0 || rld[r].optional)
6918 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6922 /* If that loop got all the way, we have won. */
6929 /* Loop around and try without any inheritance. */
6934 /* First undo everything done by the failed attempt
6935 to allocate with inheritance. */
6936 choose_reload_regs_init (chain, save_reload_reg_rtx);
6938 /* Some sanity tests to verify that the reloads found in the first
6939 pass are identical to the ones we have now. */
6940 gcc_assert (chain->n_reloads == n_reloads);
6942 for (i = 0; i < n_reloads; i++)
6944 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6946 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6947 for (j = 0; j < n_spills; j++)
6948 if (spill_regs[j] == chain->rld[i].regno)
6949 if (! set_reload_reg (j, i))
6950 failed_reload (chain->insn, i);
6954 /* If we thought we could inherit a reload, because it seemed that
6955 nothing else wanted the same reload register earlier in the insn,
6956 verify that assumption, now that all reloads have been assigned.
6957 Likewise for reloads where reload_override_in has been set. */
6959 /* If doing expensive optimizations, do one preliminary pass that doesn't
6960 cancel any inheritance, but removes reloads that have been needed only
6961 for reloads that we know can be inherited. */
6962 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6964 for (j = 0; j < n_reloads; j++)
6966 int r = reload_order[j];
6969 if (reload_inherited[r] && rld[r].reg_rtx)
6970 check_reg = rld[r].reg_rtx;
6971 else if (reload_override_in[r]
6972 && (REG_P (reload_override_in[r])
6973 || GET_CODE (reload_override_in[r]) == SUBREG))
6974 check_reg = reload_override_in[r];
6977 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6978 rld[r].opnum, rld[r].when_needed, rld[r].in,
6979 (reload_inherited[r]
6980 ? rld[r].out : const0_rtx),
6985 reload_inherited[r] = 0;
6986 reload_override_in[r] = 0;
6988 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6989 reload_override_in, then we do not need its related
6990 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6991 likewise for other reload types.
6992 We handle this by removing a reload when its only replacement
6993 is mentioned in reload_in of the reload we are going to inherit.
6994 A special case are auto_inc expressions; even if the input is
6995 inherited, we still need the address for the output. We can
6996 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6997 If we succeeded removing some reload and we are doing a preliminary
6998 pass just to remove such reloads, make another pass, since the
6999 removal of one reload might allow us to inherit another one. */
7001 && rld[r].out != rld[r].in
7002 && remove_address_replacements (rld[r].in))
7007 /* If we needed a memory location for the reload, we also have to
7008 remove its related reloads. */
7010 && rld[r].out != rld[r].in
7011 && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7012 && REGNO (tem) < FIRST_PSEUDO_REGISTER
7013 && (targetm.secondary_memory_needed
7014 (rld[r].inmode, REGNO_REG_CLASS (REGNO (tem)),
7016 && remove_address_replacements
7017 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7018 rld[r].when_needed)))
7026 /* Now that reload_override_in is known valid,
7027 actually override reload_in. */
7028 for (j = 0; j < n_reloads; j++)
7029 if (reload_override_in[j])
7030 rld[j].in = reload_override_in[j];
7032 /* If this reload won't be done because it has been canceled or is
7033 optional and not inherited, clear reload_reg_rtx so other
7034 routines (such as subst_reloads) don't get confused. */
7035 for (j = 0; j < n_reloads; j++)
7036 if (rld[j].reg_rtx != 0
7037 && ((rld[j].optional && ! reload_inherited[j])
7038 || (rld[j].in == 0 && rld[j].out == 0
7039 && ! rld[j].secondary_p)))
7041 int regno = true_regnum (rld[j].reg_rtx);
7043 if (spill_reg_order[regno] >= 0)
7044 clear_reload_reg_in_use (regno, rld[j].opnum,
7045 rld[j].when_needed, rld[j].mode);
7047 reload_spill_index[j] = -1;
7050 /* Record which pseudos and which spill regs have output reloads. */
7051 for (j = 0; j < n_reloads; j++)
7053 int r = reload_order[j];
7055 i = reload_spill_index[r];
7057 /* I is nonneg if this reload uses a register.
7058 If rld[r].reg_rtx is 0, this is an optional reload
7059 that we opted to ignore. */
7060 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7061 && rld[r].reg_rtx != 0)
7063 int nregno = REGNO (rld[r].out_reg);
7066 if (nregno < FIRST_PSEUDO_REGISTER)
7067 nr = hard_regno_nregs (nregno, rld[r].mode);
7070 SET_REGNO_REG_SET (®_has_output_reload,
7074 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7076 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7077 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7078 || rld[r].when_needed == RELOAD_FOR_INSN);
7083 /* Deallocate the reload register for reload R. This is called from
7084 remove_address_replacements. */
7087 deallocate_reload_reg (int r)
7091 if (! rld[r].reg_rtx)
7093 regno = true_regnum (rld[r].reg_rtx);
7095 if (spill_reg_order[regno] >= 0)
7096 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7098 reload_spill_index[r] = -1;
7101 /* These arrays are filled by emit_reload_insns and its subroutines. */
7102 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7103 static rtx_insn *other_input_address_reload_insns = 0;
7104 static rtx_insn *other_input_reload_insns = 0;
7105 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7106 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7107 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7108 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7109 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7110 static rtx_insn *operand_reload_insns = 0;
7111 static rtx_insn *other_operand_reload_insns = 0;
7112 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7114 /* Values to be put in spill_reg_store are put here first. Instructions
7115 must only be placed here if the associated reload register reaches
7116 the end of the instruction's reload sequence. */
7117 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7118 static HARD_REG_SET reg_reloaded_died;
7120 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7121 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7122 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7123 adjusted register, and return true. Otherwise, return false. */
7125 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7126 enum reg_class new_class,
7127 machine_mode new_mode)
7132 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7134 unsigned regno = REGNO (reg);
7136 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7138 if (GET_MODE (reg) != new_mode)
7140 if (!targetm.hard_regno_mode_ok (regno, new_mode))
7142 if (hard_regno_nregs (regno, new_mode) > REG_NREGS (reg))
7144 reg = reload_adjust_reg_for_mode (reg, new_mode);
7152 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7153 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7154 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7155 adjusted register, and return true. Otherwise, return false. */
7157 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7158 enum insn_code icode)
7161 enum reg_class new_class = scratch_reload_class (icode);
7162 machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7164 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7165 new_class, new_mode);
7168 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7169 has the number J. OLD contains the value to be used as input. */
7172 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7175 rtx_insn *insn = chain->insn;
7177 rtx oldequiv_reg = 0;
7183 /* delete_output_reload is only invoked properly if old contains
7184 the original pseudo register. Since this is replaced with a
7185 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7186 find the pseudo in RELOAD_IN_REG. This is also used to
7187 determine whether a secondary reload is needed. */
7188 if (reload_override_in[j]
7189 && (REG_P (rl->in_reg)
7190 || (GET_CODE (rl->in_reg) == SUBREG
7191 && REG_P (SUBREG_REG (rl->in_reg)))))
7198 else if (REG_P (oldequiv))
7199 oldequiv_reg = oldequiv;
7200 else if (GET_CODE (oldequiv) == SUBREG)
7201 oldequiv_reg = SUBREG_REG (oldequiv);
7203 reloadreg = reload_reg_rtx_for_input[j];
7204 mode = GET_MODE (reloadreg);
7206 /* If we are reloading from a register that was recently stored in
7207 with an output-reload, see if we can prove there was
7208 actually no need to store the old value in it. */
7210 if (optimize && REG_P (oldequiv)
7211 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7212 && spill_reg_store[REGNO (oldequiv)]
7214 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7215 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7217 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7219 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7222 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7223 oldequiv = SUBREG_REG (oldequiv);
7224 if (GET_MODE (oldequiv) != VOIDmode
7225 && mode != GET_MODE (oldequiv))
7226 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7228 /* Switch to the right place to emit the reload insns. */
7229 switch (rl->when_needed)
7232 where = &other_input_reload_insns;
7234 case RELOAD_FOR_INPUT:
7235 where = &input_reload_insns[rl->opnum];
7237 case RELOAD_FOR_INPUT_ADDRESS:
7238 where = &input_address_reload_insns[rl->opnum];
7240 case RELOAD_FOR_INPADDR_ADDRESS:
7241 where = &inpaddr_address_reload_insns[rl->opnum];
7243 case RELOAD_FOR_OUTPUT_ADDRESS:
7244 where = &output_address_reload_insns[rl->opnum];
7246 case RELOAD_FOR_OUTADDR_ADDRESS:
7247 where = &outaddr_address_reload_insns[rl->opnum];
7249 case RELOAD_FOR_OPERAND_ADDRESS:
7250 where = &operand_reload_insns;
7252 case RELOAD_FOR_OPADDR_ADDR:
7253 where = &other_operand_reload_insns;
7255 case RELOAD_FOR_OTHER_ADDRESS:
7256 where = &other_input_address_reload_insns;
7262 push_to_sequence (*where);
7264 /* Auto-increment addresses must be reloaded in a special way. */
7265 if (rl->out && ! rl->out_reg)
7267 /* We are not going to bother supporting the case where a
7268 incremented register can't be copied directly from
7269 OLDEQUIV since this seems highly unlikely. */
7270 gcc_assert (rl->secondary_in_reload < 0);
7272 if (reload_inherited[j])
7273 oldequiv = reloadreg;
7275 old = XEXP (rl->in_reg, 0);
7277 /* Prevent normal processing of this reload. */
7279 /* Output a special code sequence for this case. */
7280 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7283 /* If we are reloading a pseudo-register that was set by the previous
7284 insn, see if we can get rid of that pseudo-register entirely
7285 by redirecting the previous insn into our reload register. */
7287 else if (optimize && REG_P (old)
7288 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7289 && dead_or_set_p (insn, old)
7290 /* This is unsafe if some other reload
7291 uses the same reg first. */
7292 && ! conflicts_with_override (reloadreg)
7293 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7294 rl->when_needed, old, rl->out, j, 0))
7296 rtx_insn *temp = PREV_INSN (insn);
7297 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7298 temp = PREV_INSN (temp);
7300 && NONJUMP_INSN_P (temp)
7301 && GET_CODE (PATTERN (temp)) == SET
7302 && SET_DEST (PATTERN (temp)) == old
7303 /* Make sure we can access insn_operand_constraint. */
7304 && asm_noperands (PATTERN (temp)) < 0
7305 /* This is unsafe if operand occurs more than once in current
7306 insn. Perhaps some occurrences aren't reloaded. */
7307 && count_occurrences (PATTERN (insn), old, 0) == 1)
7309 rtx old = SET_DEST (PATTERN (temp));
7310 /* Store into the reload register instead of the pseudo. */
7311 SET_DEST (PATTERN (temp)) = reloadreg;
7313 /* Verify that resulting insn is valid.
7315 Note that we have replaced the destination of TEMP with
7316 RELOADREG. If TEMP references RELOADREG within an
7317 autoincrement addressing mode, then the resulting insn
7318 is ill-formed and we must reject this optimization. */
7319 extract_insn (temp);
7320 if (constrain_operands (1, get_enabled_alternatives (temp))
7321 && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
7323 /* If the previous insn is an output reload, the source is
7324 a reload register, and its spill_reg_store entry will
7325 contain the previous destination. This is now
7327 if (REG_P (SET_SRC (PATTERN (temp)))
7328 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7330 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7331 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7334 /* If these are the only uses of the pseudo reg,
7335 pretend for GDB it lives in the reload reg we used. */
7336 if (REG_N_DEATHS (REGNO (old)) == 1
7337 && REG_N_SETS (REGNO (old)) == 1)
7339 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7340 if (ira_conflicts_p)
7341 /* Inform IRA about the change. */
7342 ira_mark_allocation_change (REGNO (old));
7343 alter_reg (REGNO (old), -1, false);
7347 /* Adjust any debug insns between temp and insn. */
7348 while ((temp = NEXT_INSN (temp)) != insn)
7349 if (DEBUG_BIND_INSN_P (temp))
7350 INSN_VAR_LOCATION_LOC (temp)
7351 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp),
7354 gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp));
7358 SET_DEST (PATTERN (temp)) = old;
7363 /* We can't do that, so output an insn to load RELOADREG. */
7365 /* If we have a secondary reload, pick up the secondary register
7366 and icode, if any. If OLDEQUIV and OLD are different or
7367 if this is an in-out reload, recompute whether or not we
7368 still need a secondary register and what the icode should
7369 be. If we still need a secondary register and the class or
7370 icode is different, go back to reloading from OLD if using
7371 OLDEQUIV means that we got the wrong type of register. We
7372 cannot have different class or icode due to an in-out reload
7373 because we don't make such reloads when both the input and
7374 output need secondary reload registers. */
7376 if (! special && rl->secondary_in_reload >= 0)
7378 rtx second_reload_reg = 0;
7379 rtx third_reload_reg = 0;
7380 int secondary_reload = rl->secondary_in_reload;
7381 rtx real_oldequiv = oldequiv;
7384 enum insn_code icode;
7385 enum insn_code tertiary_icode = CODE_FOR_nothing;
7387 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7388 and similarly for OLD.
7389 See comments in get_secondary_reload in reload.c. */
7390 /* If it is a pseudo that cannot be replaced with its
7391 equivalent MEM, we must fall back to reload_in, which
7392 will have all the necessary substitutions registered.
7393 Likewise for a pseudo that can't be replaced with its
7394 equivalent constant.
7396 Take extra care for subregs of such pseudos. Note that
7397 we cannot use reg_equiv_mem in this case because it is
7398 not in the right mode. */
7401 if (GET_CODE (tmp) == SUBREG)
7402 tmp = SUBREG_REG (tmp);
7404 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7405 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7406 || reg_equiv_constant (REGNO (tmp)) != 0))
7408 if (! reg_equiv_mem (REGNO (tmp))
7409 || num_not_at_initial_offset
7410 || GET_CODE (oldequiv) == SUBREG)
7411 real_oldequiv = rl->in;
7413 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7417 if (GET_CODE (tmp) == SUBREG)
7418 tmp = SUBREG_REG (tmp);
7420 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7421 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7422 || reg_equiv_constant (REGNO (tmp)) != 0))
7424 if (! reg_equiv_mem (REGNO (tmp))
7425 || num_not_at_initial_offset
7426 || GET_CODE (old) == SUBREG)
7429 real_old = reg_equiv_mem (REGNO (tmp));
7432 second_reload_reg = rld[secondary_reload].reg_rtx;
7433 if (rld[secondary_reload].secondary_in_reload >= 0)
7435 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7437 third_reload_reg = rld[tertiary_reload].reg_rtx;
7438 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7439 /* We'd have to add more code for quartary reloads. */
7440 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7442 icode = rl->secondary_in_icode;
7444 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7445 || (rl->in != 0 && rl->out != 0))
7447 secondary_reload_info sri, sri2;
7448 enum reg_class new_class, new_t_class;
7450 sri.icode = CODE_FOR_nothing;
7451 sri.prev_sri = NULL;
7453 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7457 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7458 second_reload_reg = 0;
7459 else if (new_class == NO_REGS)
7461 if (reload_adjust_reg_for_icode (&second_reload_reg,
7463 (enum insn_code) sri.icode))
7465 icode = (enum insn_code) sri.icode;
7466 third_reload_reg = 0;
7471 real_oldequiv = real_old;
7474 else if (sri.icode != CODE_FOR_nothing)
7475 /* We currently lack a way to express this in reloads. */
7479 sri2.icode = CODE_FOR_nothing;
7480 sri2.prev_sri = &sri;
7482 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7485 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7487 if (reload_adjust_reg_for_temp (&second_reload_reg,
7491 third_reload_reg = 0;
7492 tertiary_icode = (enum insn_code) sri2.icode;
7497 real_oldequiv = real_old;
7500 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7502 rtx intermediate = second_reload_reg;
7504 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7506 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7510 second_reload_reg = intermediate;
7511 tertiary_icode = (enum insn_code) sri2.icode;
7516 real_oldequiv = real_old;
7519 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7521 rtx intermediate = second_reload_reg;
7523 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7525 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7528 second_reload_reg = intermediate;
7529 tertiary_icode = (enum insn_code) sri2.icode;
7534 real_oldequiv = real_old;
7539 /* This could be handled more intelligently too. */
7541 real_oldequiv = real_old;
7546 /* If we still need a secondary reload register, check
7547 to see if it is being used as a scratch or intermediate
7548 register and generate code appropriately. If we need
7549 a scratch register, use REAL_OLDEQUIV since the form of
7550 the insn may depend on the actual address if it is
7553 if (second_reload_reg)
7555 if (icode != CODE_FOR_nothing)
7557 /* We'd have to add extra code to handle this case. */
7558 gcc_assert (!third_reload_reg);
7560 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7561 second_reload_reg));
7566 /* See if we need a scratch register to load the
7567 intermediate register (a tertiary reload). */
7568 if (tertiary_icode != CODE_FOR_nothing)
7570 emit_insn ((GEN_FCN (tertiary_icode)
7571 (second_reload_reg, real_oldequiv,
7572 third_reload_reg)));
7574 else if (third_reload_reg)
7576 gen_reload (third_reload_reg, real_oldequiv,
7579 gen_reload (second_reload_reg, third_reload_reg,
7584 gen_reload (second_reload_reg, real_oldequiv,
7588 oldequiv = second_reload_reg;
7593 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7595 rtx real_oldequiv = oldequiv;
7597 if ((REG_P (oldequiv)
7598 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7599 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7600 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7601 || (GET_CODE (oldequiv) == SUBREG
7602 && REG_P (SUBREG_REG (oldequiv))
7603 && (REGNO (SUBREG_REG (oldequiv))
7604 >= FIRST_PSEUDO_REGISTER)
7605 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7606 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7607 || (CONSTANT_P (oldequiv)
7608 && (targetm.preferred_reload_class (oldequiv,
7609 REGNO_REG_CLASS (REGNO (reloadreg)))
7611 real_oldequiv = rl->in;
7612 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7616 if (cfun->can_throw_non_call_exceptions)
7617 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7619 /* End this sequence. */
7620 *where = get_insns ();
7623 /* Update reload_override_in so that delete_address_reloads_1
7624 can see the actual register usage. */
7626 reload_override_in[j] = oldequiv;
7629 /* Generate insns to for the output reload RL, which is for the insn described
7630 by CHAIN and has the number J. */
7632 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7636 rtx_insn *insn = chain->insn;
7643 if (rl->when_needed == RELOAD_OTHER)
7646 push_to_sequence (output_reload_insns[rl->opnum]);
7648 rl_reg_rtx = reload_reg_rtx_for_output[j];
7649 mode = GET_MODE (rl_reg_rtx);
7651 reloadreg = rl_reg_rtx;
7653 /* If we need two reload regs, set RELOADREG to the intermediate
7654 one, since it will be stored into OLD. We might need a secondary
7655 register only for an input reload, so check again here. */
7657 if (rl->secondary_out_reload >= 0)
7660 int secondary_reload = rl->secondary_out_reload;
7661 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7663 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7664 && reg_equiv_mem (REGNO (old)) != 0)
7665 real_old = reg_equiv_mem (REGNO (old));
7667 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7669 rtx second_reloadreg = reloadreg;
7670 reloadreg = rld[secondary_reload].reg_rtx;
7672 /* See if RELOADREG is to be used as a scratch register
7673 or as an intermediate register. */
7674 if (rl->secondary_out_icode != CODE_FOR_nothing)
7676 /* We'd have to add extra code to handle this case. */
7677 gcc_assert (tertiary_reload < 0);
7679 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7680 (real_old, second_reloadreg, reloadreg)));
7685 /* See if we need both a scratch and intermediate reload
7688 enum insn_code tertiary_icode
7689 = rld[secondary_reload].secondary_out_icode;
7691 /* We'd have to add more code for quartary reloads. */
7692 gcc_assert (tertiary_reload < 0
7693 || rld[tertiary_reload].secondary_out_reload < 0);
7695 if (GET_MODE (reloadreg) != mode)
7696 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7698 if (tertiary_icode != CODE_FOR_nothing)
7700 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7702 /* Copy primary reload reg to secondary reload reg.
7703 (Note that these have been swapped above, then
7704 secondary reload reg to OLD using our insn.) */
7706 /* If REAL_OLD is a paradoxical SUBREG, remove it
7707 and try to put the opposite SUBREG on
7709 strip_paradoxical_subreg (&real_old, &reloadreg);
7711 gen_reload (reloadreg, second_reloadreg,
7712 rl->opnum, rl->when_needed);
7713 emit_insn ((GEN_FCN (tertiary_icode)
7714 (real_old, reloadreg, third_reloadreg)));
7720 /* Copy between the reload regs here and then to
7723 gen_reload (reloadreg, second_reloadreg,
7724 rl->opnum, rl->when_needed);
7725 if (tertiary_reload >= 0)
7727 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7729 gen_reload (third_reloadreg, reloadreg,
7730 rl->opnum, rl->when_needed);
7731 reloadreg = third_reloadreg;
7738 /* Output the last reload insn. */
7743 /* Don't output the last reload if OLD is not the dest of
7744 INSN and is in the src and is clobbered by INSN. */
7745 if (! flag_expensive_optimizations
7747 || !(set = single_set (insn))
7748 || rtx_equal_p (old, SET_DEST (set))
7749 || !reg_mentioned_p (old, SET_SRC (set))
7750 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7751 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7752 gen_reload (old, reloadreg, rl->opnum,
7756 /* Look at all insns we emitted, just to be safe. */
7757 for (p = get_insns (); p; p = NEXT_INSN (p))
7760 rtx pat = PATTERN (p);
7762 /* If this output reload doesn't come from a spill reg,
7763 clear any memory of reloaded copies of the pseudo reg.
7764 If this output reload comes from a spill reg,
7765 reg_has_output_reload will make this do nothing. */
7766 note_stores (pat, forget_old_reloads_1, NULL);
7768 if (reg_mentioned_p (rl_reg_rtx, pat))
7770 rtx set = single_set (insn);
7771 if (reload_spill_index[j] < 0
7773 && SET_SRC (set) == rl_reg_rtx)
7775 int src = REGNO (SET_SRC (set));
7777 reload_spill_index[j] = src;
7778 SET_HARD_REG_BIT (reg_is_output_reload, src);
7779 if (find_regno_note (insn, REG_DEAD, src))
7780 SET_HARD_REG_BIT (reg_reloaded_died, src);
7782 if (HARD_REGISTER_P (rl_reg_rtx))
7784 int s = rl->secondary_out_reload;
7785 set = single_set (p);
7786 /* If this reload copies only to the secondary reload
7787 register, the secondary reload does the actual
7789 if (s >= 0 && set == NULL_RTX)
7790 /* We can't tell what function the secondary reload
7791 has and where the actual store to the pseudo is
7792 made; leave new_spill_reg_store alone. */
7795 && SET_SRC (set) == rl_reg_rtx
7796 && SET_DEST (set) == rld[s].reg_rtx)
7798 /* Usually the next instruction will be the
7799 secondary reload insn; if we can confirm
7800 that it is, setting new_spill_reg_store to
7801 that insn will allow an extra optimization. */
7802 rtx s_reg = rld[s].reg_rtx;
7803 rtx_insn *next = NEXT_INSN (p);
7804 rld[s].out = rl->out;
7805 rld[s].out_reg = rl->out_reg;
7806 set = single_set (next);
7807 if (set && SET_SRC (set) == s_reg
7808 && reload_reg_rtx_reaches_end_p (s_reg, s))
7810 SET_HARD_REG_BIT (reg_is_output_reload,
7812 new_spill_reg_store[REGNO (s_reg)] = next;
7815 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7816 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7821 if (rl->when_needed == RELOAD_OTHER)
7823 emit_insn (other_output_reload_insns[rl->opnum]);
7824 other_output_reload_insns[rl->opnum] = get_insns ();
7827 output_reload_insns[rl->opnum] = get_insns ();
7829 if (cfun->can_throw_non_call_exceptions)
7830 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7835 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7836 and has the number J. */
7838 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7840 rtx_insn *insn = chain->insn;
7841 rtx old = (rl->in && MEM_P (rl->in)
7842 ? rl->in_reg : rl->in);
7843 rtx reg_rtx = rl->reg_rtx;
7849 /* Determine the mode to reload in.
7850 This is very tricky because we have three to choose from.
7851 There is the mode the insn operand wants (rl->inmode).
7852 There is the mode of the reload register RELOADREG.
7853 There is the intrinsic mode of the operand, which we could find
7854 by stripping some SUBREGs.
7855 It turns out that RELOADREG's mode is irrelevant:
7856 we can change that arbitrarily.
7858 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7859 then the reload reg may not support QImode moves, so use SImode.
7860 If foo is in memory due to spilling a pseudo reg, this is safe,
7861 because the QImode value is in the least significant part of a
7862 slot big enough for a SImode. If foo is some other sort of
7863 memory reference, then it is impossible to reload this case,
7864 so previous passes had better make sure this never happens.
7866 Then consider a one-word union which has SImode and one of its
7867 members is a float, being fetched as (SUBREG:SF union:SI).
7868 We must fetch that as SFmode because we could be loading into
7869 a float-only register. In this case OLD's mode is correct.
7871 Consider an immediate integer: it has VOIDmode. Here we need
7872 to get a mode from something else.
7874 In some cases, there is a fourth mode, the operand's
7875 containing mode. If the insn specifies a containing mode for
7876 this operand, it overrides all others.
7878 I am not sure whether the algorithm here is always right,
7879 but it does the right things in those cases. */
7881 mode = GET_MODE (old);
7882 if (mode == VOIDmode)
7885 /* We cannot use gen_lowpart_common since it can do the wrong thing
7886 when REG_RTX has a multi-word mode. Note that REG_RTX must
7887 always be a REG here. */
7888 if (GET_MODE (reg_rtx) != mode)
7889 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7891 reload_reg_rtx_for_input[j] = reg_rtx;
7894 /* AUTO_INC reloads need to be handled even if inherited. We got an
7895 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7896 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7897 && ! rtx_equal_p (reg_rtx, old)
7899 emit_input_reload_insns (chain, rld + j, old, j);
7901 /* When inheriting a wider reload, we have a MEM in rl->in,
7902 e.g. inheriting a SImode output reload for
7903 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7904 if (optimize && reload_inherited[j] && rl->in
7906 && MEM_P (rl->in_reg)
7907 && reload_spill_index[j] >= 0
7908 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7909 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7911 /* If we are reloading a register that was recently stored in with an
7912 output-reload, see if we can prove there was
7913 actually no need to store the old value in it. */
7916 && (reload_inherited[j] || reload_override_in[j])
7919 && spill_reg_store[REGNO (reg_rtx)] != 0
7921 /* There doesn't seem to be any reason to restrict this to pseudos
7922 and doing so loses in the case where we are copying from a
7923 register of the wrong class. */
7924 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7926 /* The insn might have already some references to stackslots
7927 replaced by MEMs, while reload_out_reg still names the
7929 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7930 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7931 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7934 /* Do output reloading for reload RL, which is for the insn described by
7935 CHAIN and has the number J.
7936 ??? At some point we need to support handling output reloads of
7937 JUMP_INSNs or insns that set cc0. */
7939 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7942 rtx_insn *insn = chain->insn;
7943 /* If this is an output reload that stores something that is
7944 not loaded in this same reload, see if we can eliminate a previous
7946 rtx pseudo = rl->out_reg;
7947 rtx reg_rtx = rl->reg_rtx;
7949 if (rl->out && reg_rtx)
7953 /* Determine the mode to reload in.
7954 See comments above (for input reloading). */
7955 mode = GET_MODE (rl->out);
7956 if (mode == VOIDmode)
7958 /* VOIDmode should never happen for an output. */
7959 if (asm_noperands (PATTERN (insn)) < 0)
7960 /* It's the compiler's fault. */
7961 fatal_insn ("VOIDmode on an output", insn);
7962 error_for_asm (insn, "output operand is constant in %<asm%>");
7963 /* Prevent crash--use something we know is valid. */
7965 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7967 if (GET_MODE (reg_rtx) != mode)
7968 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7970 reload_reg_rtx_for_output[j] = reg_rtx;
7975 && ! rtx_equal_p (rl->in_reg, pseudo)
7976 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7977 && reg_last_reload_reg[REGNO (pseudo)])
7979 int pseudo_no = REGNO (pseudo);
7980 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7982 /* We don't need to test full validity of last_regno for
7983 inherit here; we only want to know if the store actually
7984 matches the pseudo. */
7985 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7986 && reg_reloaded_contents[last_regno] == pseudo_no
7987 && spill_reg_store[last_regno]
7988 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7989 delete_output_reload (insn, j, last_regno, reg_rtx);
7995 || rtx_equal_p (old, reg_rtx))
7998 /* An output operand that dies right away does need a reload,
7999 but need not be copied from it. Show the new location in the
8001 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8002 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8004 XEXP (note, 0) = reg_rtx;
8007 /* Likewise for a SUBREG of an operand that dies. */
8008 else if (GET_CODE (old) == SUBREG
8009 && REG_P (SUBREG_REG (old))
8010 && (note = find_reg_note (insn, REG_UNUSED,
8011 SUBREG_REG (old))) != 0)
8013 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8016 else if (GET_CODE (old) == SCRATCH)
8017 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8018 but we don't want to make an output reload. */
8021 /* If is a JUMP_INSN, we can't support output reloads yet. */
8022 gcc_assert (NONJUMP_INSN_P (insn));
8024 emit_output_reload_insns (chain, rld + j, j);
8027 /* A reload copies values of MODE from register SRC to register DEST.
8028 Return true if it can be treated for inheritance purposes like a
8029 group of reloads, each one reloading a single hard register. The
8030 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8031 occupy the same number of hard registers. */
8034 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8035 int src ATTRIBUTE_UNUSED,
8036 machine_mode mode ATTRIBUTE_UNUSED)
8038 return (REG_CAN_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8039 && REG_CAN_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8042 /* Output insns to reload values in and out of the chosen reload regs. */
8045 emit_reload_insns (struct insn_chain *chain)
8047 rtx_insn *insn = chain->insn;
8051 CLEAR_HARD_REG_SET (reg_reloaded_died);
8053 for (j = 0; j < reload_n_operands; j++)
8054 input_reload_insns[j] = input_address_reload_insns[j]
8055 = inpaddr_address_reload_insns[j]
8056 = output_reload_insns[j] = output_address_reload_insns[j]
8057 = outaddr_address_reload_insns[j]
8058 = other_output_reload_insns[j] = 0;
8059 other_input_address_reload_insns = 0;
8060 other_input_reload_insns = 0;
8061 operand_reload_insns = 0;
8062 other_operand_reload_insns = 0;
8064 /* Dump reloads into the dump file. */
8067 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8068 debug_reload_to_stream (dump_file);
8071 for (j = 0; j < n_reloads; j++)
8072 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8076 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8077 new_spill_reg_store[i] = 0;
8080 /* Now output the instructions to copy the data into and out of the
8081 reload registers. Do these in the order that the reloads were reported,
8082 since reloads of base and index registers precede reloads of operands
8083 and the operands may need the base and index registers reloaded. */
8085 for (j = 0; j < n_reloads; j++)
8087 do_input_reload (chain, rld + j, j);
8088 do_output_reload (chain, rld + j, j);
8091 /* Now write all the insns we made for reloads in the order expected by
8092 the allocation functions. Prior to the insn being reloaded, we write
8093 the following reloads:
8095 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8097 RELOAD_OTHER reloads.
8099 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8100 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8101 RELOAD_FOR_INPUT reload for the operand.
8103 RELOAD_FOR_OPADDR_ADDRS reloads.
8105 RELOAD_FOR_OPERAND_ADDRESS reloads.
8107 After the insn being reloaded, we write the following:
8109 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8110 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8111 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8112 reloads for the operand. The RELOAD_OTHER output reloads are
8113 output in descending order by reload number. */
8115 emit_insn_before (other_input_address_reload_insns, insn);
8116 emit_insn_before (other_input_reload_insns, insn);
8118 for (j = 0; j < reload_n_operands; j++)
8120 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8121 emit_insn_before (input_address_reload_insns[j], insn);
8122 emit_insn_before (input_reload_insns[j], insn);
8125 emit_insn_before (other_operand_reload_insns, insn);
8126 emit_insn_before (operand_reload_insns, insn);
8128 for (j = 0; j < reload_n_operands; j++)
8130 rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8131 x = emit_insn_after (output_address_reload_insns[j], x);
8132 x = emit_insn_after (output_reload_insns[j], x);
8133 emit_insn_after (other_output_reload_insns[j], x);
8136 /* For all the spill regs newly reloaded in this instruction,
8137 record what they were reloaded from, so subsequent instructions
8138 can inherit the reloads.
8140 Update spill_reg_store for the reloads of this insn.
8141 Copy the elements that were updated in the loop above. */
8143 for (j = 0; j < n_reloads; j++)
8145 int r = reload_order[j];
8146 int i = reload_spill_index[r];
8148 /* If this is a non-inherited input reload from a pseudo, we must
8149 clear any memory of a previous store to the same pseudo. Only do
8150 something if there will not be an output reload for the pseudo
8152 if (rld[r].in_reg != 0
8153 && ! (reload_inherited[r] || reload_override_in[r]))
8155 rtx reg = rld[r].in_reg;
8157 if (GET_CODE (reg) == SUBREG)
8158 reg = SUBREG_REG (reg);
8161 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8162 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8164 int nregno = REGNO (reg);
8166 if (reg_last_reload_reg[nregno])
8168 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8170 if (reg_reloaded_contents[last_regno] == nregno)
8171 spill_reg_store[last_regno] = 0;
8176 /* I is nonneg if this reload used a register.
8177 If rld[r].reg_rtx is 0, this is an optional reload
8178 that we opted to ignore. */
8180 if (i >= 0 && rld[r].reg_rtx != 0)
8182 int nr = hard_regno_nregs (i, GET_MODE (rld[r].reg_rtx));
8185 /* For a multi register reload, we need to check if all or part
8186 of the value lives to the end. */
8187 for (k = 0; k < nr; k++)
8188 if (reload_reg_reaches_end_p (i + k, r))
8189 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8191 /* Maybe the spill reg contains a copy of reload_out. */
8193 && (REG_P (rld[r].out)
8195 ? REG_P (rld[r].out_reg)
8196 /* The reload value is an auto-modification of
8197 some kind. For PRE_INC, POST_INC, PRE_DEC
8198 and POST_DEC, we record an equivalence
8199 between the reload register and the operand
8200 on the optimistic assumption that we can make
8201 the equivalence hold. reload_as_needed must
8202 then either make it hold or invalidate the
8205 PRE_MODIFY and POST_MODIFY addresses are reloaded
8206 somewhat differently, and allowing them here leads
8208 : (GET_CODE (rld[r].out) != POST_MODIFY
8209 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8213 reg = reload_reg_rtx_for_output[r];
8214 if (reload_reg_rtx_reaches_end_p (reg, r))
8216 machine_mode mode = GET_MODE (reg);
8217 int regno = REGNO (reg);
8218 int nregs = REG_NREGS (reg);
8219 rtx out = (REG_P (rld[r].out)
8223 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8224 int out_regno = REGNO (out);
8225 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8226 : hard_regno_nregs (out_regno, mode));
8229 spill_reg_store[regno] = new_spill_reg_store[regno];
8230 spill_reg_stored_to[regno] = out;
8231 reg_last_reload_reg[out_regno] = reg;
8233 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8234 && nregs == out_nregs
8235 && inherit_piecemeal_p (out_regno, regno, mode));
8237 /* If OUT_REGNO is a hard register, it may occupy more than
8238 one register. If it does, say what is in the
8239 rest of the registers assuming that both registers
8240 agree on how many words the object takes. If not,
8241 invalidate the subsequent registers. */
8243 if (HARD_REGISTER_NUM_P (out_regno))
8244 for (k = 1; k < out_nregs; k++)
8245 reg_last_reload_reg[out_regno + k]
8246 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8248 /* Now do the inverse operation. */
8249 for (k = 0; k < nregs; k++)
8251 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8252 reg_reloaded_contents[regno + k]
8253 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8256 reg_reloaded_insn[regno + k] = insn;
8257 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8258 if (targetm.hard_regno_call_part_clobbered (regno + k,
8260 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8263 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8268 /* Maybe the spill reg contains a copy of reload_in. Only do
8269 something if there will not be an output reload for
8270 the register being reloaded. */
8271 else if (rld[r].out_reg == 0
8273 && ((REG_P (rld[r].in)
8274 && !HARD_REGISTER_P (rld[r].in)
8275 && !REGNO_REG_SET_P (®_has_output_reload,
8277 || (REG_P (rld[r].in_reg)
8278 && !REGNO_REG_SET_P (®_has_output_reload,
8279 REGNO (rld[r].in_reg))))
8280 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8284 reg = reload_reg_rtx_for_input[r];
8285 if (reload_reg_rtx_reaches_end_p (reg, r))
8295 mode = GET_MODE (reg);
8296 regno = REGNO (reg);
8297 nregs = REG_NREGS (reg);
8298 if (REG_P (rld[r].in)
8299 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8301 else if (REG_P (rld[r].in_reg))
8304 in = XEXP (rld[r].in_reg, 0);
8305 in_regno = REGNO (in);
8307 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8308 : hard_regno_nregs (in_regno, mode));
8310 reg_last_reload_reg[in_regno] = reg;
8312 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8313 && nregs == in_nregs
8314 && inherit_piecemeal_p (regno, in_regno, mode));
8316 if (HARD_REGISTER_NUM_P (in_regno))
8317 for (k = 1; k < in_nregs; k++)
8318 reg_last_reload_reg[in_regno + k]
8319 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8321 /* Unless we inherited this reload, show we haven't
8322 recently done a store.
8323 Previous stores of inherited auto_inc expressions
8324 also have to be discarded. */
8325 if (! reload_inherited[r]
8326 || (rld[r].out && ! rld[r].out_reg))
8327 spill_reg_store[regno] = 0;
8329 for (k = 0; k < nregs; k++)
8331 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8332 reg_reloaded_contents[regno + k]
8333 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8336 reg_reloaded_insn[regno + k] = insn;
8337 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8338 if (targetm.hard_regno_call_part_clobbered (regno + k,
8340 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8343 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8350 /* The following if-statement was #if 0'd in 1.34 (or before...).
8351 It's reenabled in 1.35 because supposedly nothing else
8352 deals with this problem. */
8354 /* If a register gets output-reloaded from a non-spill register,
8355 that invalidates any previous reloaded copy of it.
8356 But forget_old_reloads_1 won't get to see it, because
8357 it thinks only about the original insn. So invalidate it here.
8358 Also do the same thing for RELOAD_OTHER constraints where the
8359 output is discarded. */
8361 && ((rld[r].out != 0
8362 && (REG_P (rld[r].out)
8363 || (MEM_P (rld[r].out)
8364 && REG_P (rld[r].out_reg))))
8365 || (rld[r].out == 0 && rld[r].out_reg
8366 && REG_P (rld[r].out_reg))))
8368 rtx out = ((rld[r].out && REG_P (rld[r].out))
8369 ? rld[r].out : rld[r].out_reg);
8370 int out_regno = REGNO (out);
8371 machine_mode mode = GET_MODE (out);
8373 /* REG_RTX is now set or clobbered by the main instruction.
8374 As the comment above explains, forget_old_reloads_1 only
8375 sees the original instruction, and there is no guarantee
8376 that the original instruction also clobbered REG_RTX.
8377 For example, if find_reloads sees that the input side of
8378 a matched operand pair dies in this instruction, it may
8379 use the input register as the reload register.
8381 Calling forget_old_reloads_1 is a waste of effort if
8382 REG_RTX is also the output register.
8384 If we know that REG_RTX holds the value of a pseudo
8385 register, the code after the call will record that fact. */
8386 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8387 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8389 if (!HARD_REGISTER_NUM_P (out_regno))
8392 rtx_insn *store_insn = NULL;
8394 reg_last_reload_reg[out_regno] = 0;
8396 /* If we can find a hard register that is stored, record
8397 the storing insn so that we may delete this insn with
8398 delete_output_reload. */
8399 src_reg = reload_reg_rtx_for_output[r];
8403 if (reload_reg_rtx_reaches_end_p (src_reg, r))
8404 store_insn = new_spill_reg_store[REGNO (src_reg)];
8410 /* If this is an optional reload, try to find the
8411 source reg from an input reload. */
8412 rtx set = single_set (insn);
8413 if (set && SET_DEST (set) == rld[r].out)
8417 src_reg = SET_SRC (set);
8419 for (k = 0; k < n_reloads; k++)
8421 if (rld[k].in == src_reg)
8423 src_reg = reload_reg_rtx_for_input[k];
8429 if (src_reg && REG_P (src_reg)
8430 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8432 int src_regno, src_nregs, k;
8435 gcc_assert (GET_MODE (src_reg) == mode);
8436 src_regno = REGNO (src_reg);
8437 src_nregs = hard_regno_nregs (src_regno, mode);
8438 /* The place where to find a death note varies with
8439 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8440 necessarily checked exactly in the code that moves
8441 notes, so just check both locations. */
8442 note = find_regno_note (insn, REG_DEAD, src_regno);
8443 if (! note && store_insn)
8444 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8445 for (k = 0; k < src_nregs; k++)
8447 spill_reg_store[src_regno + k] = store_insn;
8448 spill_reg_stored_to[src_regno + k] = out;
8449 reg_reloaded_contents[src_regno + k] = out_regno;
8450 reg_reloaded_insn[src_regno + k] = store_insn;
8451 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8452 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8453 if (targetm.hard_regno_call_part_clobbered
8454 (src_regno + k, mode))
8455 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8458 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8460 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8462 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8464 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8466 reg_last_reload_reg[out_regno] = src_reg;
8467 /* We have to set reg_has_output_reload here, or else
8468 forget_old_reloads_1 will clear reg_last_reload_reg
8470 SET_REGNO_REG_SET (®_has_output_reload,
8476 int k, out_nregs = hard_regno_nregs (out_regno, mode);
8478 for (k = 0; k < out_nregs; k++)
8479 reg_last_reload_reg[out_regno + k] = 0;
8483 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8486 /* Go through the motions to emit INSN and test if it is strictly valid.
8487 Return the emitted insn if valid, else return NULL. */
8490 emit_insn_if_valid_for_reload (rtx pat)
8492 rtx_insn *last = get_last_insn ();
8495 rtx_insn *insn = emit_insn (pat);
8496 code = recog_memoized (insn);
8500 extract_insn (insn);
8501 /* We want constrain operands to treat this insn strictly in its
8502 validity determination, i.e., the way it would after reload has
8504 if (constrain_operands (1, get_enabled_alternatives (insn)))
8508 delete_insns_since (last);
8512 /* Emit code to perform a reload from IN (which may be a reload register) to
8513 OUT (which may also be a reload register). IN or OUT is from operand
8514 OPNUM with reload type TYPE.
8516 Returns first insn emitted. */
8519 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8521 rtx_insn *last = get_last_insn ();
8525 /* If IN is a paradoxical SUBREG, remove it and try to put the
8526 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8527 if (!strip_paradoxical_subreg (&in, &out))
8528 strip_paradoxical_subreg (&out, &in);
8530 /* How to do this reload can get quite tricky. Normally, we are being
8531 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8532 register that didn't get a hard register. In that case we can just
8533 call emit_move_insn.
8535 We can also be asked to reload a PLUS that adds a register or a MEM to
8536 another register, constant or MEM. This can occur during frame pointer
8537 elimination and while reloading addresses. This case is handled by
8538 trying to emit a single insn to perform the add. If it is not valid,
8539 we use a two insn sequence.
8541 Or we can be asked to reload an unary operand that was a fragment of
8542 an addressing mode, into a register. If it isn't recognized as-is,
8543 we try making the unop operand and the reload-register the same:
8544 (set reg:X (unop:X expr:Y))
8545 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8547 Finally, we could be called to handle an 'o' constraint by putting
8548 an address into a register. In that case, we first try to do this
8549 with a named pattern of "reload_load_address". If no such pattern
8550 exists, we just emit a SET insn and hope for the best (it will normally
8551 be valid on machines that use 'o').
8553 This entire process is made complex because reload will never
8554 process the insns we generate here and so we must ensure that
8555 they will fit their constraints and also by the fact that parts of
8556 IN might be being reloaded separately and replaced with spill registers.
8557 Because of this, we are, in some sense, just guessing the right approach
8558 here. The one listed above seems to work.
8560 ??? At some point, this whole thing needs to be rethought. */
8562 if (GET_CODE (in) == PLUS
8563 && (REG_P (XEXP (in, 0))
8564 || GET_CODE (XEXP (in, 0)) == SUBREG
8565 || MEM_P (XEXP (in, 0)))
8566 && (REG_P (XEXP (in, 1))
8567 || GET_CODE (XEXP (in, 1)) == SUBREG
8568 || CONSTANT_P (XEXP (in, 1))
8569 || MEM_P (XEXP (in, 1))))
8571 /* We need to compute the sum of a register or a MEM and another
8572 register, constant, or MEM, and put it into the reload
8573 register. The best possible way of doing this is if the machine
8574 has a three-operand ADD insn that accepts the required operands.
8576 The simplest approach is to try to generate such an insn and see if it
8577 is recognized and matches its constraints. If so, it can be used.
8579 It might be better not to actually emit the insn unless it is valid,
8580 but we need to pass the insn as an operand to `recog' and
8581 `extract_insn' and it is simpler to emit and then delete the insn if
8582 not valid than to dummy things up. */
8586 enum insn_code code;
8588 op0 = find_replacement (&XEXP (in, 0));
8589 op1 = find_replacement (&XEXP (in, 1));
8591 /* Since constraint checking is strict, commutativity won't be
8592 checked, so we need to do that here to avoid spurious failure
8593 if the add instruction is two-address and the second operand
8594 of the add is the same as the reload reg, which is frequently
8595 the case. If the insn would be A = B + A, rearrange it so
8596 it will be A = A + B as constrain_operands expects. */
8598 if (REG_P (XEXP (in, 1))
8599 && REGNO (out) == REGNO (XEXP (in, 1)))
8600 tem = op0, op0 = op1, op1 = tem;
8602 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8603 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8605 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8609 /* If that failed, we must use a conservative two-insn sequence.
8611 Use a move to copy one operand into the reload register. Prefer
8612 to reload a constant, MEM or pseudo since the move patterns can
8613 handle an arbitrary operand. If OP1 is not a constant, MEM or
8614 pseudo and OP1 is not a valid operand for an add instruction, then
8617 After reloading one of the operands into the reload register, add
8618 the reload register to the output register.
8620 If there is another way to do this for a specific machine, a
8621 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8624 code = optab_handler (add_optab, GET_MODE (out));
8626 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8628 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8629 || (code != CODE_FOR_nothing
8630 && !insn_operand_matches (code, 2, op1)))
8631 tem = op0, op0 = op1, op1 = tem;
8633 gen_reload (out, op0, opnum, type);
8635 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8636 This fixes a problem on the 32K where the stack pointer cannot
8637 be used as an operand of an add insn. */
8639 if (rtx_equal_p (op0, op1))
8642 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8645 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8646 set_dst_reg_note (insn, REG_EQUIV, in, out);
8650 /* If that failed, copy the address register to the reload register.
8651 Then add the constant to the reload register. */
8653 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8654 gen_reload (out, op1, opnum, type);
8655 insn = emit_insn (gen_add2_insn (out, op0));
8656 set_dst_reg_note (insn, REG_EQUIV, in, out);
8659 /* If we need a memory location to do the move, do it that way. */
8660 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8661 (REG_P (tem1) && REG_P (tem2)))
8662 && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8663 && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8664 && targetm.secondary_memory_needed (GET_MODE (out),
8665 REGNO_REG_CLASS (REGNO (tem1)),
8666 REGNO_REG_CLASS (REGNO (tem2))))
8668 /* Get the memory to use and rewrite both registers to its mode. */
8669 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8671 if (GET_MODE (loc) != GET_MODE (out))
8672 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8674 if (GET_MODE (loc) != GET_MODE (in))
8675 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8677 gen_reload (loc, in, opnum, type);
8678 gen_reload (out, loc, opnum, type);
8680 else if (REG_P (out) && UNARY_P (in))
8686 op1 = find_replacement (&XEXP (in, 0));
8687 if (op1 != XEXP (in, 0))
8688 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8690 /* First, try a plain SET. */
8691 set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8695 /* If that failed, move the inner operand to the reload
8696 register, and try the same unop with the inner expression
8697 replaced with the reload register. */
8699 if (GET_MODE (op1) != GET_MODE (out))
8700 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8704 gen_reload (out_moded, op1, opnum, type);
8706 rtx temp = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8708 rtx_insn *insn = emit_insn_if_valid_for_reload (temp);
8711 set_unique_reg_note (insn, REG_EQUIV, in);
8715 fatal_insn ("failure trying to reload:", set);
8717 /* If IN is a simple operand, use gen_move_insn. */
8718 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8720 tem = emit_insn (gen_move_insn (out, in));
8721 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8722 mark_jump_label (in, tem, 0);
8725 else if (targetm.have_reload_load_address ())
8726 emit_insn (targetm.gen_reload_load_address (out, in));
8728 /* Otherwise, just write (set OUT IN) and hope for the best. */
8730 emit_insn (gen_rtx_SET (out, in));
8732 /* Return the first insn emitted.
8733 We can not just return get_last_insn, because there may have
8734 been multiple instructions emitted. Also note that gen_move_insn may
8735 emit more than one insn itself, so we can not assume that there is one
8736 insn emitted per emit_insn_before call. */
8738 return last ? NEXT_INSN (last) : get_insns ();
8741 /* Delete a previously made output-reload whose result we now believe
8742 is not needed. First we double-check.
8744 INSN is the insn now being processed.
8745 LAST_RELOAD_REG is the hard register number for which we want to delete
8746 the last output reload.
8747 J is the reload-number that originally used REG. The caller has made
8748 certain that reload J doesn't use REG any longer for input.
8749 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8752 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8755 rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8756 rtx reg = spill_reg_stored_to[last_reload_reg];
8759 int n_inherited = 0;
8764 /* It is possible that this reload has been only used to set another reload
8765 we eliminated earlier and thus deleted this instruction too. */
8766 if (output_reload_insn->deleted ())
8769 /* Get the raw pseudo-register referred to. */
8771 while (GET_CODE (reg) == SUBREG)
8772 reg = SUBREG_REG (reg);
8773 substed = reg_equiv_memory_loc (REGNO (reg));
8775 /* This is unsafe if the operand occurs more often in the current
8776 insn than it is inherited. */
8777 for (k = n_reloads - 1; k >= 0; k--)
8779 rtx reg2 = rld[k].in;
8782 if (MEM_P (reg2) || reload_override_in[k])
8783 reg2 = rld[k].in_reg;
8785 if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
8786 reg2 = XEXP (rld[k].in_reg, 0);
8788 while (GET_CODE (reg2) == SUBREG)
8789 reg2 = SUBREG_REG (reg2);
8790 if (rtx_equal_p (reg2, reg))
8792 if (reload_inherited[k] || reload_override_in[k] || k == j)
8798 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8799 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8800 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8803 n_occurrences += count_occurrences (PATTERN (insn),
8804 eliminate_regs (substed, VOIDmode,
8806 for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8808 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8809 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8811 if (n_occurrences > n_inherited)
8814 regno = REGNO (reg);
8815 nregs = REG_NREGS (reg);
8817 /* If the pseudo-reg we are reloading is no longer referenced
8818 anywhere between the store into it and here,
8819 and we're within the same basic block, then the value can only
8820 pass through the reload reg and end up here.
8821 Otherwise, give up--return. */
8822 for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8823 i1 != insn; i1 = NEXT_INSN (i1))
8825 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8827 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8828 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8830 /* If this is USE in front of INSN, we only have to check that
8831 there are no more references than accounted for by inheritance. */
8832 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8834 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8835 i1 = NEXT_INSN (i1);
8837 if (n_occurrences <= n_inherited && i1 == insn)
8843 /* We will be deleting the insn. Remove the spill reg information. */
8844 for (k = hard_regno_nregs (last_reload_reg, GET_MODE (reg)); k-- > 0; )
8846 spill_reg_store[last_reload_reg + k] = 0;
8847 spill_reg_stored_to[last_reload_reg + k] = 0;
8850 /* The caller has already checked that REG dies or is set in INSN.
8851 It has also checked that we are optimizing, and thus some
8852 inaccuracies in the debugging information are acceptable.
8853 So we could just delete output_reload_insn. But in some cases
8854 we can improve the debugging information without sacrificing
8855 optimization - maybe even improving the code: See if the pseudo
8856 reg has been completely replaced with reload regs. If so, delete
8857 the store insn and forget we had a stack slot for the pseudo. */
8858 if (rld[j].out != rld[j].in
8859 && REG_N_DEATHS (REGNO (reg)) == 1
8860 && REG_N_SETS (REGNO (reg)) == 1
8861 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8862 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8866 /* We know that it was used only between here and the beginning of
8867 the current basic block. (We also know that the last use before
8868 INSN was the output reload we are thinking of deleting, but never
8869 mind that.) Search that range; see if any ref remains. */
8870 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8872 rtx set = single_set (i2);
8874 /* Uses which just store in the pseudo don't count,
8875 since if they are the only uses, they are dead. */
8876 if (set != 0 && SET_DEST (set) == reg)
8878 if (LABEL_P (i2) || JUMP_P (i2))
8880 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8881 && reg_mentioned_p (reg, PATTERN (i2)))
8883 /* Some other ref remains; just delete the output reload we
8885 delete_address_reloads (output_reload_insn, insn);
8886 delete_insn (output_reload_insn);
8891 /* Delete the now-dead stores into this pseudo. Note that this
8892 loop also takes care of deleting output_reload_insn. */
8893 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8895 rtx set = single_set (i2);
8897 if (set != 0 && SET_DEST (set) == reg)
8899 delete_address_reloads (i2, insn);
8902 if (LABEL_P (i2) || JUMP_P (i2))
8906 /* For the debugging info, say the pseudo lives in this reload reg. */
8907 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8908 if (ira_conflicts_p)
8909 /* Inform IRA about the change. */
8910 ira_mark_allocation_change (REGNO (reg));
8911 alter_reg (REGNO (reg), -1, false);
8915 delete_address_reloads (output_reload_insn, insn);
8916 delete_insn (output_reload_insn);
8920 /* We are going to delete DEAD_INSN. Recursively delete loads of
8921 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8922 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8924 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
8926 rtx set = single_set (dead_insn);
8928 rtx_insn *prev, *next;
8931 rtx dst = SET_DEST (set);
8933 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8935 /* If we deleted the store from a reloaded post_{in,de}c expression,
8936 we can delete the matching adds. */
8937 prev = PREV_INSN (dead_insn);
8938 next = NEXT_INSN (dead_insn);
8939 if (! prev || ! next)
8941 set = single_set (next);
8942 set2 = single_set (prev);
8944 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8945 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8946 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8948 dst = SET_DEST (set);
8949 if (! rtx_equal_p (dst, SET_DEST (set2))
8950 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8951 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8952 || (INTVAL (XEXP (SET_SRC (set), 1))
8953 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8955 delete_related_insns (prev);
8956 delete_related_insns (next);
8959 /* Subfunction of delete_address_reloads: process registers found in X. */
8961 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
8963 rtx_insn *prev, *i2;
8966 enum rtx_code code = GET_CODE (x);
8970 const char *fmt = GET_RTX_FORMAT (code);
8971 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8974 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8975 else if (fmt[i] == 'E')
8977 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8978 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8985 if (spill_reg_order[REGNO (x)] < 0)
8988 /* Scan backwards for the insn that sets x. This might be a way back due
8990 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8992 code = GET_CODE (prev);
8993 if (code == CODE_LABEL || code == JUMP_INSN)
8997 if (reg_set_p (x, PATTERN (prev)))
8999 if (reg_referenced_p (x, PATTERN (prev)))
9002 if (! prev || INSN_UID (prev) < reload_first_uid)
9004 /* Check that PREV only sets the reload register. */
9005 set = single_set (prev);
9008 dst = SET_DEST (set);
9010 || ! rtx_equal_p (dst, x))
9012 if (! reg_set_p (dst, PATTERN (dead_insn)))
9014 /* Check if DST was used in a later insn -
9015 it might have been inherited. */
9016 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9022 if (reg_referenced_p (dst, PATTERN (i2)))
9024 /* If there is a reference to the register in the current insn,
9025 it might be loaded in a non-inherited reload. If no other
9026 reload uses it, that means the register is set before
9028 if (i2 == current_insn)
9030 for (j = n_reloads - 1; j >= 0; j--)
9031 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9032 || reload_override_in[j] == dst)
9034 for (j = n_reloads - 1; j >= 0; j--)
9035 if (rld[j].in && rld[j].reg_rtx == dst)
9044 /* If DST is still live at CURRENT_INSN, check if it is used for
9045 any reload. Note that even if CURRENT_INSN sets DST, we still
9046 have to check the reloads. */
9047 if (i2 == current_insn)
9049 for (j = n_reloads - 1; j >= 0; j--)
9050 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9051 || reload_override_in[j] == dst)
9053 /* ??? We can't finish the loop here, because dst might be
9054 allocated to a pseudo in this block if no reload in this
9055 block needs any of the classes containing DST - see
9056 spill_hard_reg. There is no easy way to tell this, so we
9057 have to scan till the end of the basic block. */
9059 if (reg_set_p (dst, PATTERN (i2)))
9063 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9064 reg_reloaded_contents[REGNO (dst)] = -1;
9068 /* Output reload-insns to reload VALUE into RELOADREG.
9069 VALUE is an autoincrement or autodecrement RTX whose operand
9070 is a register or memory location;
9071 so reloading involves incrementing that location.
9072 IN is either identical to VALUE, or some cheaper place to reload from.
9074 INC_AMOUNT is the number to increment or decrement by (always positive).
9075 This cannot be deduced from VALUE. */
9078 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9080 /* REG or MEM to be copied and incremented. */
9081 rtx incloc = find_replacement (&XEXP (value, 0));
9082 /* Nonzero if increment after copying. */
9083 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9084 || GET_CODE (value) == POST_MODIFY);
9089 rtx real_in = in == value ? incloc : in;
9091 /* No hard register is equivalent to this register after
9092 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9093 we could inc/dec that register as well (maybe even using it for
9094 the source), but I'm not sure it's worth worrying about. */
9096 reg_last_reload_reg[REGNO (incloc)] = 0;
9098 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9100 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9101 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9105 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9106 inc_amount = -inc_amount;
9108 inc = GEN_INT (inc_amount);
9111 /* If this is post-increment, first copy the location to the reload reg. */
9112 if (post && real_in != reloadreg)
9113 emit_insn (gen_move_insn (reloadreg, real_in));
9117 /* See if we can directly increment INCLOC. Use a method similar to
9118 that in gen_reload. */
9120 last = get_last_insn ();
9121 add_insn = emit_insn (gen_rtx_SET (incloc,
9122 gen_rtx_PLUS (GET_MODE (incloc),
9125 code = recog_memoized (add_insn);
9128 extract_insn (add_insn);
9129 if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9131 /* If this is a pre-increment and we have incremented the value
9132 where it lives, copy the incremented value to RELOADREG to
9133 be used as an address. */
9136 emit_insn (gen_move_insn (reloadreg, incloc));
9140 delete_insns_since (last);
9143 /* If couldn't do the increment directly, must increment in RELOADREG.
9144 The way we do this depends on whether this is pre- or post-increment.
9145 For pre-increment, copy INCLOC to the reload register, increment it
9146 there, then save back. */
9150 if (in != reloadreg)
9151 emit_insn (gen_move_insn (reloadreg, real_in));
9152 emit_insn (gen_add2_insn (reloadreg, inc));
9153 emit_insn (gen_move_insn (incloc, reloadreg));
9158 Because this might be a jump insn or a compare, and because RELOADREG
9159 may not be available after the insn in an input reload, we must do
9160 the incrementation before the insn being reloaded for.
9162 We have already copied IN to RELOADREG. Increment the copy in
9163 RELOADREG, save that back, then decrement RELOADREG so it has
9164 the original value. */
9166 emit_insn (gen_add2_insn (reloadreg, inc));
9167 emit_insn (gen_move_insn (incloc, reloadreg));
9168 if (CONST_INT_P (inc))
9169 emit_insn (gen_add2_insn (reloadreg,
9170 gen_int_mode (-INTVAL (inc),
9171 GET_MODE (reloadreg))));
9173 emit_insn (gen_sub2_insn (reloadreg, inc));
9178 add_auto_inc_notes (rtx_insn *insn, rtx x)
9180 enum rtx_code code = GET_CODE (x);
9184 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9186 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9190 /* Scan all the operand sub-expressions. */
9191 fmt = GET_RTX_FORMAT (code);
9192 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9195 add_auto_inc_notes (insn, XEXP (x, i));
9196 else if (fmt[i] == 'E')
9197 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9198 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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