1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
27 #include "rtl-error.h"
30 #include "insn-config.h"
37 #include "addresses.h"
38 #include "basic-block.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 struct target_reload default_target_reload;
85 struct target_reload *this_target_reload = &default_target_reload;
88 #define spill_indirect_levels \
89 (this_target_reload->x_spill_indirect_levels)
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static regset_head reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static unsigned int *reg_max_ref_width;
106 /* Vector to remember old contents of reg_renumber before spilling. */
107 static short *reg_old_renumber;
109 /* During reload_as_needed, element N contains the last pseudo regno reloaded
110 into hard register N. If that pseudo reg occupied more than one register,
111 reg_reloaded_contents points to that pseudo for each spill register in
112 use; all of these must remain set for an inheritance to occur. */
113 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
115 /* During reload_as_needed, element N contains the insn for which
116 hard register N was last used. Its contents are significant only
117 when reg_reloaded_valid is set for this register. */
118 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
120 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
121 static HARD_REG_SET reg_reloaded_valid;
122 /* Indicate if the register was dead at the end of the reload.
123 This is only valid if reg_reloaded_contents is set and valid. */
124 static HARD_REG_SET reg_reloaded_dead;
126 /* Indicate whether the register's current value is one that is not
127 safe to retain across a call, even for registers that are normally
128 call-saved. This is only meaningful for members of reg_reloaded_valid. */
129 static HARD_REG_SET reg_reloaded_call_part_clobbered;
131 /* Number of spill-regs so far; number of valid elements of spill_regs. */
134 /* In parallel with spill_regs, contains REG rtx's for those regs.
135 Holds the last rtx used for any given reg, or 0 if it has never
136 been used for spilling yet. This rtx is reused, provided it has
138 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
140 /* In parallel with spill_regs, contains nonzero for a spill reg
141 that was stored after the last time it was used.
142 The precise value is the insn generated to do the store. */
143 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
145 /* This is the register that was stored with spill_reg_store. This is a
146 copy of reload_out / reload_out_reg when the value was stored; if
147 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
148 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
150 /* This table is the inverse mapping of spill_regs:
151 indexed by hard reg number,
152 it contains the position of that reg in spill_regs,
153 or -1 for something that is not in spill_regs.
155 ?!? This is no longer accurate. */
156 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
158 /* This reg set indicates registers that can't be used as spill registers for
159 the currently processed insn. These are the hard registers which are live
160 during the insn, but not allocated to pseudos, as well as fixed
162 static HARD_REG_SET bad_spill_regs;
164 /* These are the hard registers that can't be used as spill register for any
165 insn. This includes registers used for user variables and registers that
166 we can't eliminate. A register that appears in this set also can't be used
167 to retry register allocation. */
168 static HARD_REG_SET bad_spill_regs_global;
170 /* Describes order of use of registers for reloading
171 of spilled pseudo-registers. `n_spills' is the number of
172 elements that are actually valid; new ones are added at the end.
174 Both spill_regs and spill_reg_order are used on two occasions:
175 once during find_reload_regs, where they keep track of the spill registers
176 for a single insn, but also during reload_as_needed where they show all
177 the registers ever used by reload. For the latter case, the information
178 is calculated during finish_spills. */
179 static short spill_regs[FIRST_PSEUDO_REGISTER];
181 /* This vector of reg sets indicates, for each pseudo, which hard registers
182 may not be used for retrying global allocation because the register was
183 formerly spilled from one of them. If we allowed reallocating a pseudo to
184 a register that it was already allocated to, reload might not
186 static HARD_REG_SET *pseudo_previous_regs;
188 /* This vector of reg sets indicates, for each pseudo, which hard
189 registers may not be used for retrying global allocation because they
190 are used as spill registers during one of the insns in which the
192 static HARD_REG_SET *pseudo_forbidden_regs;
194 /* All hard regs that have been used as spill registers for any insn are
195 marked in this set. */
196 static HARD_REG_SET used_spill_regs;
198 /* Index of last register assigned as a spill register. We allocate in
199 a round-robin fashion. */
200 static int last_spill_reg;
202 /* Record the stack slot for each spilled hard register. */
203 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
205 /* Width allocated so far for that stack slot. */
206 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
208 /* Record which pseudos needed to be spilled. */
209 static regset_head spilled_pseudos;
211 /* Record which pseudos changed their allocation in finish_spills. */
212 static regset_head changed_allocation_pseudos;
214 /* Used for communication between order_regs_for_reload and count_pseudo.
215 Used to avoid counting one pseudo twice. */
216 static regset_head pseudos_counted;
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
224 int caller_save_needed;
226 /* Set to 1 while reload_as_needed is operating.
227 Required by some machines to handle any generated moves differently. */
228 int reload_in_progress = 0;
230 /* This obstack is used for allocation of rtl during register elimination.
231 The allocated storage can be freed once find_reloads has processed the
233 static struct obstack reload_obstack;
235 /* Points to the beginning of the reload_obstack. All insn_chain structures
236 are allocated first. */
237 static char *reload_startobj;
239 /* The point after all insn_chain structures. Used to quickly deallocate
240 memory allocated in copy_reloads during calculate_needs_all_insns. */
241 static char *reload_firstobj;
243 /* This points before all local rtl generated by register elimination.
244 Used to quickly free all memory after processing one insn. */
245 static char *reload_insn_firstobj;
247 /* List of insn_chain instructions, one for every insn that reload needs to
249 struct insn_chain *reload_insn_chain;
251 /* TRUE if we potentially left dead insns in the insn stream and want to
252 run DCE immediately after reload, FALSE otherwise. */
253 static bool need_dce;
255 /* List of all insns needing reloads. */
256 static struct insn_chain *insns_need_reload;
258 /* This structure is used to record information about register eliminations.
259 Each array entry describes one possible way of eliminating a register
260 in favor of another. If there is more than one way of eliminating a
261 particular register, the most preferred should be specified first. */
265 int from; /* Register number to be eliminated. */
266 int to; /* Register number used as replacement. */
267 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
268 int can_eliminate; /* Nonzero if this elimination can be done. */
269 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
270 target hook in previous scan over insns
272 HOST_WIDE_INT offset; /* Current offset between the two regs. */
273 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
274 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
275 rtx from_rtx; /* REG rtx for the register to be eliminated.
276 We cannot simply compare the number since
277 we might then spuriously replace a hard
278 register corresponding to a pseudo
279 assigned to the reg to be eliminated. */
280 rtx to_rtx; /* REG rtx for the replacement. */
283 static struct elim_table *reg_eliminate = 0;
285 /* This is an intermediate structure to initialize the table. It has
286 exactly the members provided by ELIMINABLE_REGS. */
287 static const struct elim_table_1
291 } reg_eliminate_1[] =
293 /* If a set of eliminable registers was specified, define the table from it.
294 Otherwise, default to the normal case of the frame pointer being
295 replaced by the stack pointer. */
297 #ifdef ELIMINABLE_REGS
300 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
303 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
305 /* Record the number of pending eliminations that have an offset not equal
306 to their initial offset. If nonzero, we use a new copy of each
307 replacement result in any insns encountered. */
308 int num_not_at_initial_offset;
310 /* Count the number of registers that we may be able to eliminate. */
311 static int num_eliminable;
312 /* And the number of registers that are equivalent to a constant that
313 can be eliminated to frame_pointer / arg_pointer + constant. */
314 static int num_eliminable_invariants;
316 /* For each label, we record the offset of each elimination. If we reach
317 a label by more than one path and an offset differs, we cannot do the
318 elimination. This information is indexed by the difference of the
319 number of the label and the first label number. We can't offset the
320 pointer itself as this can cause problems on machines with segmented
321 memory. The first table is an array of flags that records whether we
322 have yet encountered a label and the second table is an array of arrays,
323 one entry in the latter array for each elimination. */
325 static int first_label_num;
326 static char *offsets_known_at;
327 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
329 vec<reg_equivs_t, va_gc> *reg_equivs;
331 /* Stack of addresses where an rtx has been changed. We can undo the
332 changes by popping items off the stack and restoring the original
333 value at each location.
335 We use this simplistic undo capability rather than copy_rtx as copy_rtx
336 will not make a deep copy of a normally sharable rtx, such as
337 (const (plus (symbol_ref) (const_int))). If such an expression appears
338 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
339 rtx expression would be changed. See PR 42431. */
342 static vec<rtx_p> substitute_stack;
344 /* Number of labels in the current function. */
346 static int num_labels;
348 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
349 static void maybe_fix_stack_asms (void);
350 static void copy_reloads (struct insn_chain *);
351 static void calculate_needs_all_insns (int);
352 static int find_reg (struct insn_chain *, int);
353 static void find_reload_regs (struct insn_chain *);
354 static void select_reload_regs (void);
355 static void delete_caller_save_insns (void);
357 static void spill_failure (rtx, enum reg_class);
358 static void count_spilled_pseudo (int, int, int);
359 static void delete_dead_insn (rtx);
360 static void alter_reg (int, int, bool);
361 static void set_label_offsets (rtx, rtx, int);
362 static void check_eliminable_occurrences (rtx);
363 static void elimination_effects (rtx, enum machine_mode);
364 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
365 static int eliminate_regs_in_insn (rtx, int);
366 static void update_eliminable_offsets (void);
367 static void mark_not_eliminable (rtx, const_rtx, void *);
368 static void set_initial_elim_offsets (void);
369 static bool verify_initial_elim_offsets (void);
370 static void set_initial_label_offsets (void);
371 static void set_offsets_for_label (rtx);
372 static void init_eliminable_invariants (rtx, bool);
373 static void init_elim_table (void);
374 static void free_reg_equiv (void);
375 static void update_eliminables (HARD_REG_SET *);
376 static void elimination_costs_in_insn (rtx);
377 static void spill_hard_reg (unsigned int, int);
378 static int finish_spills (int);
379 static void scan_paradoxical_subregs (rtx);
380 static void count_pseudo (int);
381 static void order_regs_for_reload (struct insn_chain *);
382 static void reload_as_needed (int);
383 static void forget_old_reloads_1 (rtx, const_rtx, void *);
384 static void forget_marked_reloads (regset);
385 static int reload_reg_class_lower (const void *, const void *);
386 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
388 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
390 static int reload_reg_free_p (unsigned int, int, enum reload_type);
391 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
393 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
395 static int allocate_reload_reg (struct insn_chain *, int, int);
396 static int conflicts_with_override (rtx);
397 static void failed_reload (rtx, int);
398 static int set_reload_reg (int, int);
399 static void choose_reload_regs_init (struct insn_chain *, rtx *);
400 static void choose_reload_regs (struct insn_chain *);
401 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
403 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
405 static void do_input_reload (struct insn_chain *, struct reload *, int);
406 static void do_output_reload (struct insn_chain *, struct reload *, int);
407 static void emit_reload_insns (struct insn_chain *);
408 static void delete_output_reload (rtx, int, int, rtx);
409 static void delete_address_reloads (rtx, rtx);
410 static void delete_address_reloads_1 (rtx, rtx, rtx);
411 static void inc_for_reload (rtx, rtx, rtx, int);
413 static void add_auto_inc_notes (rtx, rtx);
415 static void substitute (rtx *, const_rtx, rtx);
416 static bool gen_reload_chain_without_interm_reg_p (int, int);
417 static int reloads_conflict (int, int);
418 static rtx gen_reload (rtx, rtx, int, enum reload_type);
419 static rtx emit_insn_if_valid_for_reload (rtx);
421 /* Initialize the reload pass. This is called at the beginning of compilation
422 and may be called again if the target is reinitialized. */
429 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
430 Set spill_indirect_levels to the number of levels such addressing is
431 permitted, zero if it is not permitted at all. */
434 = gen_rtx_MEM (Pmode,
437 LAST_VIRTUAL_REGISTER + 1),
439 spill_indirect_levels = 0;
441 while (memory_address_p (QImode, tem))
443 spill_indirect_levels++;
444 tem = gen_rtx_MEM (Pmode, tem);
447 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
449 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
450 indirect_symref_ok = memory_address_p (QImode, tem);
452 /* See if reg+reg is a valid (and offsettable) address. */
454 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
456 tem = gen_rtx_PLUS (Pmode,
457 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
458 gen_rtx_REG (Pmode, i));
460 /* This way, we make sure that reg+reg is an offsettable address. */
461 tem = plus_constant (Pmode, tem, 4);
463 if (memory_address_p (QImode, tem))
465 double_reg_address_ok = 1;
470 /* Initialize obstack for our rtl allocation. */
471 if (reload_startobj == NULL)
473 gcc_obstack_init (&reload_obstack);
474 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
477 INIT_REG_SET (&spilled_pseudos);
478 INIT_REG_SET (&changed_allocation_pseudos);
479 INIT_REG_SET (&pseudos_counted);
482 /* List of insn chains that are currently unused. */
483 static struct insn_chain *unused_insn_chains = 0;
485 /* Allocate an empty insn_chain structure. */
487 new_insn_chain (void)
489 struct insn_chain *c;
491 if (unused_insn_chains == 0)
493 c = XOBNEW (&reload_obstack, struct insn_chain);
494 INIT_REG_SET (&c->live_throughout);
495 INIT_REG_SET (&c->dead_or_set);
499 c = unused_insn_chains;
500 unused_insn_chains = c->next;
502 c->is_caller_save_insn = 0;
503 c->need_operand_change = 0;
509 /* Small utility function to set all regs in hard reg set TO which are
510 allocated to pseudos in regset FROM. */
513 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
516 reg_set_iterator rsi;
518 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
520 int r = reg_renumber[regno];
524 /* reload_combine uses the information from DF_LIVE_IN,
525 which might still contain registers that have not
526 actually been allocated since they have an
528 gcc_assert (ira_conflicts_p || reload_completed);
531 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
535 /* Replace all pseudos found in LOC with their corresponding
539 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
552 unsigned int regno = REGNO (x);
554 if (regno < FIRST_PSEUDO_REGISTER)
557 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
561 replace_pseudos_in (loc, mem_mode, usage);
565 if (reg_equiv_constant (regno))
566 *loc = reg_equiv_constant (regno);
567 else if (reg_equiv_invariant (regno))
568 *loc = reg_equiv_invariant (regno);
569 else if (reg_equiv_mem (regno))
570 *loc = reg_equiv_mem (regno);
571 else if (reg_equiv_address (regno))
572 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
575 gcc_assert (!REG_P (regno_reg_rtx[regno])
576 || REGNO (regno_reg_rtx[regno]) != regno);
577 *loc = regno_reg_rtx[regno];
582 else if (code == MEM)
584 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
588 /* Process each of our operands recursively. */
589 fmt = GET_RTX_FORMAT (code);
590 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
592 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
593 else if (*fmt == 'E')
594 for (j = 0; j < XVECLEN (x, i); j++)
595 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
598 /* Determine if the current function has an exception receiver block
599 that reaches the exit block via non-exceptional edges */
602 has_nonexceptional_receiver (void)
606 basic_block *tos, *worklist, bb;
608 /* If we're not optimizing, then just err on the safe side. */
612 /* First determine which blocks can reach exit via normal paths. */
613 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
616 bb->flags &= ~BB_REACHABLE;
618 /* Place the exit block on our worklist. */
619 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
620 *tos++ = EXIT_BLOCK_PTR;
622 /* Iterate: find everything reachable from what we've already seen. */
623 while (tos != worklist)
627 FOR_EACH_EDGE (e, ei, bb->preds)
628 if (!(e->flags & EDGE_ABNORMAL))
630 basic_block src = e->src;
632 if (!(src->flags & BB_REACHABLE))
634 src->flags |= BB_REACHABLE;
641 /* Now see if there's a reachable block with an exceptional incoming
644 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
647 /* No exceptional block reached exit unexceptionally. */
651 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
652 zero elements) to MAX_REG_NUM elements.
654 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
656 grow_reg_equivs (void)
658 int old_size = vec_safe_length (reg_equivs);
659 int max_regno = max_reg_num ();
663 memset (&ze, 0, sizeof (reg_equivs_t));
664 vec_safe_reserve (reg_equivs, max_regno);
665 for (i = old_size; i < max_regno; i++)
666 reg_equivs->quick_insert (i, ze);
670 /* Global variables used by reload and its subroutines. */
672 /* The current basic block while in calculate_elim_costs_all_insns. */
673 static basic_block elim_bb;
675 /* Set during calculate_needs if an insn needs register elimination. */
676 static int something_needs_elimination;
677 /* Set during calculate_needs if an insn needs an operand changed. */
678 static int something_needs_operands_changed;
679 /* Set by alter_regs if we spilled a register to the stack. */
680 static bool something_was_spilled;
682 /* Nonzero means we couldn't get enough spill regs. */
685 /* Temporary array of pseudo-register number. */
686 static int *temp_pseudo_reg_arr;
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is TRUE if reload likely left dead insns in the
699 stream and a DCE pass should be run to elimiante them. Else the
700 return value is FALSE. */
703 reload (rtx first, int global)
707 struct elim_table *ep;
711 /* Make sure even insns with volatile mem refs are recognizable. */
716 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
718 /* Make sure that the last insn in the chain
719 is not something that needs reloading. */
720 emit_note (NOTE_INSN_DELETED);
722 /* Enable find_equiv_reg to distinguish insns made by reload. */
723 reload_first_uid = get_max_uid ();
725 #ifdef SECONDARY_MEMORY_NEEDED
726 /* Initialize the secondary memory table. */
727 clear_secondary_mem ();
730 /* We don't have a stack slot for any spill reg yet. */
731 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
732 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
734 /* Initialize the save area information for caller-save, in case some
738 /* Compute which hard registers are now in use
739 as homes for pseudo registers.
740 This is done here rather than (eg) in global_alloc
741 because this point is reached even if not optimizing. */
742 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
745 /* A function that has a nonlocal label that can reach the exit
746 block via non-exceptional paths must save all call-saved
748 if (cfun->has_nonlocal_label
749 && has_nonexceptional_receiver ())
750 crtl->saves_all_registers = 1;
752 if (crtl->saves_all_registers)
753 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
754 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
755 df_set_regs_ever_live (i, true);
757 /* Find all the pseudo registers that didn't get hard regs
758 but do have known equivalent constants or memory slots.
759 These include parameters (known equivalent to parameter slots)
760 and cse'd or loop-moved constant memory addresses.
762 Record constant equivalents in reg_equiv_constant
763 so they will be substituted by find_reloads.
764 Record memory equivalents in reg_mem_equiv so they can
765 be substituted eventually by altering the REG-rtx's. */
768 reg_old_renumber = XCNEWVEC (short, max_regno);
769 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
770 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
771 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
773 CLEAR_HARD_REG_SET (bad_spill_regs_global);
775 init_eliminable_invariants (first, true);
778 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
779 stack slots to the pseudos that lack hard regs or equivalents.
780 Do not touch virtual registers. */
782 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
783 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
784 temp_pseudo_reg_arr[n++] = i;
787 /* Ask IRA to order pseudo-registers for better stack slot
789 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
791 for (i = 0; i < n; i++)
792 alter_reg (temp_pseudo_reg_arr[i], -1, false);
794 /* If we have some registers we think can be eliminated, scan all insns to
795 see if there is an insn that sets one of these registers to something
796 other than itself plus a constant. If so, the register cannot be
797 eliminated. Doing this scan here eliminates an extra pass through the
798 main reload loop in the most common case where register elimination
800 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
802 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
804 maybe_fix_stack_asms ();
806 insns_need_reload = 0;
807 something_needs_elimination = 0;
809 /* Initialize to -1, which means take the first spill register. */
812 /* Spill any hard regs that we know we can't eliminate. */
813 CLEAR_HARD_REG_SET (used_spill_regs);
814 /* There can be multiple ways to eliminate a register;
815 they should be listed adjacently.
816 Elimination for any register fails only if all possible ways fail. */
817 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
820 int can_eliminate = 0;
823 can_eliminate |= ep->can_eliminate;
826 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
828 spill_hard_reg (from, 1);
831 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
832 if (frame_pointer_needed)
833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
835 finish_spills (global);
837 /* From now on, we may need to generate moves differently. We may also
838 allow modifications of insns which cause them to not be recognized.
839 Any such modifications will be cleaned up during reload itself. */
840 reload_in_progress = 1;
842 /* This loop scans the entire function each go-round
843 and repeats until one repetition spills no additional hard regs. */
846 int something_changed;
848 HOST_WIDE_INT starting_frame_size;
850 starting_frame_size = get_frame_size ();
851 something_was_spilled = false;
853 set_initial_elim_offsets ();
854 set_initial_label_offsets ();
856 /* For each pseudo register that has an equivalent location defined,
857 try to eliminate any eliminable registers (such as the frame pointer)
858 assuming initial offsets for the replacement register, which
861 If the resulting location is directly addressable, substitute
862 the MEM we just got directly for the old REG.
864 If it is not addressable but is a constant or the sum of a hard reg
865 and constant, it is probably not addressable because the constant is
866 out of range, in that case record the address; we will generate
867 hairy code to compute the address in a register each time it is
868 needed. Similarly if it is a hard register, but one that is not
869 valid as an address register.
871 If the location is not addressable, but does not have one of the
872 above forms, assign a stack slot. We have to do this to avoid the
873 potential of producing lots of reloads if, e.g., a location involves
874 a pseudo that didn't get a hard register and has an equivalent memory
875 location that also involves a pseudo that didn't get a hard register.
877 Perhaps at some point we will improve reload_when_needed handling
878 so this problem goes away. But that's very hairy. */
880 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
881 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
883 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
886 if (strict_memory_address_addr_space_p
887 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
889 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
890 else if (CONSTANT_P (XEXP (x, 0))
891 || (REG_P (XEXP (x, 0))
892 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
893 || (GET_CODE (XEXP (x, 0)) == PLUS
894 && REG_P (XEXP (XEXP (x, 0), 0))
895 && (REGNO (XEXP (XEXP (x, 0), 0))
896 < FIRST_PSEUDO_REGISTER)
897 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
898 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
901 /* Make a new stack slot. Then indicate that something
902 changed so we go back and recompute offsets for
903 eliminable registers because the allocation of memory
904 below might change some offset. reg_equiv_{mem,address}
905 will be set up for this pseudo on the next pass around
907 reg_equiv_memory_loc (i) = 0;
908 reg_equiv_init (i) = 0;
909 alter_reg (i, -1, true);
913 if (caller_save_needed)
916 /* If we allocated another stack slot, redo elimination bookkeeping. */
917 if (something_was_spilled || starting_frame_size != get_frame_size ())
919 if (starting_frame_size && crtl->stack_alignment_needed)
921 /* If we have a stack frame, we must align it now. The
922 stack size may be a part of the offset computation for
923 register elimination. So if this changes the stack size,
924 then repeat the elimination bookkeeping. We don't
925 realign when there is no stack, as that will cause a
926 stack frame when none is needed should
927 STARTING_FRAME_OFFSET not be already aligned to
929 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
930 if (starting_frame_size != get_frame_size ())
934 if (caller_save_needed)
936 save_call_clobbered_regs ();
937 /* That might have allocated new insn_chain structures. */
938 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
941 calculate_needs_all_insns (global);
943 if (! ira_conflicts_p)
944 /* Don't do it for IRA. We need this info because we don't
945 change live_throughout and dead_or_set for chains when IRA
947 CLEAR_REG_SET (&spilled_pseudos);
951 something_changed = 0;
953 /* If we allocated any new memory locations, make another pass
954 since it might have changed elimination offsets. */
955 if (something_was_spilled || starting_frame_size != get_frame_size ())
956 something_changed = 1;
958 /* Even if the frame size remained the same, we might still have
959 changed elimination offsets, e.g. if find_reloads called
960 force_const_mem requiring the back end to allocate a constant
961 pool base register that needs to be saved on the stack. */
962 else if (!verify_initial_elim_offsets ())
963 something_changed = 1;
966 HARD_REG_SET to_spill;
967 CLEAR_HARD_REG_SET (to_spill);
968 update_eliminables (&to_spill);
969 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
972 if (TEST_HARD_REG_BIT (to_spill, i))
974 spill_hard_reg (i, 1);
977 /* Regardless of the state of spills, if we previously had
978 a register that we thought we could eliminate, but now can
979 not eliminate, we must run another pass.
981 Consider pseudos which have an entry in reg_equiv_* which
982 reference an eliminable register. We must make another pass
983 to update reg_equiv_* so that we do not substitute in the
984 old value from when we thought the elimination could be
986 something_changed = 1;
990 select_reload_regs ();
994 if (insns_need_reload != 0 || did_spill)
995 something_changed |= finish_spills (global);
997 if (! something_changed)
1000 if (caller_save_needed)
1001 delete_caller_save_insns ();
1003 obstack_free (&reload_obstack, reload_firstobj);
1006 /* If global-alloc was run, notify it of any register eliminations we have
1009 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1010 if (ep->can_eliminate)
1011 mark_elimination (ep->from, ep->to);
1013 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1014 If that insn didn't set the register (i.e., it copied the register to
1015 memory), just delete that insn instead of the equivalencing insn plus
1016 anything now dead. If we call delete_dead_insn on that insn, we may
1017 delete the insn that actually sets the register if the register dies
1018 there and that is incorrect. */
1020 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1022 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1025 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1027 rtx equiv_insn = XEXP (list, 0);
1029 /* If we already deleted the insn or if it may trap, we can't
1030 delete it. The latter case shouldn't happen, but can
1031 if an insn has a variable address, gets a REG_EH_REGION
1032 note added to it, and then gets converted into a load
1033 from a constant address. */
1034 if (NOTE_P (equiv_insn)
1035 || can_throw_internal (equiv_insn))
1037 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1038 delete_dead_insn (equiv_insn);
1040 SET_INSN_DELETED (equiv_insn);
1045 /* Use the reload registers where necessary
1046 by generating move instructions to move the must-be-register
1047 values into or out of the reload registers. */
1049 if (insns_need_reload != 0 || something_needs_elimination
1050 || something_needs_operands_changed)
1052 HOST_WIDE_INT old_frame_size = get_frame_size ();
1054 reload_as_needed (global);
1056 gcc_assert (old_frame_size == get_frame_size ());
1058 gcc_assert (verify_initial_elim_offsets ());
1061 /* If we were able to eliminate the frame pointer, show that it is no
1062 longer live at the start of any basic block. If it ls live by
1063 virtue of being in a pseudo, that pseudo will be marked live
1064 and hence the frame pointer will be known to be live via that
1067 if (! frame_pointer_needed)
1069 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1071 /* Come here (with failure set nonzero) if we can't get enough spill
1075 CLEAR_REG_SET (&changed_allocation_pseudos);
1076 CLEAR_REG_SET (&spilled_pseudos);
1077 reload_in_progress = 0;
1079 /* Now eliminate all pseudo regs by modifying them into
1080 their equivalent memory references.
1081 The REG-rtx's for the pseudos are modified in place,
1082 so all insns that used to refer to them now refer to memory.
1084 For a reg that has a reg_equiv_address, all those insns
1085 were changed by reloading so that no insns refer to it any longer;
1086 but the DECL_RTL of a variable decl may refer to it,
1087 and if so this causes the debugging info to mention the variable. */
1089 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1093 if (reg_equiv_mem (i))
1094 addr = XEXP (reg_equiv_mem (i), 0);
1096 if (reg_equiv_address (i))
1097 addr = reg_equiv_address (i);
1101 if (reg_renumber[i] < 0)
1103 rtx reg = regno_reg_rtx[i];
1105 REG_USERVAR_P (reg) = 0;
1106 PUT_CODE (reg, MEM);
1107 XEXP (reg, 0) = addr;
1108 if (reg_equiv_memory_loc (i))
1109 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1111 MEM_ATTRS (reg) = 0;
1112 MEM_NOTRAP_P (reg) = 1;
1114 else if (reg_equiv_mem (i))
1115 XEXP (reg_equiv_mem (i), 0) = addr;
1118 /* We don't want complex addressing modes in debug insns
1119 if simpler ones will do, so delegitimize equivalences
1121 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1123 rtx reg = regno_reg_rtx[i];
1127 if (reg_equiv_constant (i))
1128 equiv = reg_equiv_constant (i);
1129 else if (reg_equiv_invariant (i))
1130 equiv = reg_equiv_invariant (i);
1131 else if (reg && MEM_P (reg))
1132 equiv = targetm.delegitimize_address (reg);
1133 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1139 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1141 insn = DF_REF_INSN (use);
1143 /* Make sure the next ref is for a different instruction,
1144 so that we're not affected by the rescan. */
1145 next = DF_REF_NEXT_REG (use);
1146 while (next && DF_REF_INSN (next) == insn)
1147 next = DF_REF_NEXT_REG (next);
1149 if (DEBUG_INSN_P (insn))
1153 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1154 df_insn_rescan_debug_internal (insn);
1157 INSN_VAR_LOCATION_LOC (insn)
1158 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1165 /* We must set reload_completed now since the cleanup_subreg_operands call
1166 below will re-recognize each insn and reload may have generated insns
1167 which are only valid during and after reload. */
1168 reload_completed = 1;
1170 /* Make a pass over all the insns and delete all USEs which we inserted
1171 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1172 notes. Delete all CLOBBER insns, except those that refer to the return
1173 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1174 from misarranging variable-array code, and simplify (subreg (reg))
1175 operands. Strip and regenerate REG_INC notes that may have been moved
1178 for (insn = first; insn; insn = NEXT_INSN (insn))
1184 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1185 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1187 if ((GET_CODE (PATTERN (insn)) == USE
1188 /* We mark with QImode USEs introduced by reload itself. */
1189 && (GET_MODE (insn) == QImode
1190 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1191 || (GET_CODE (PATTERN (insn)) == CLOBBER
1192 && (!MEM_P (XEXP (PATTERN (insn), 0))
1193 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1194 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1195 && XEXP (XEXP (PATTERN (insn), 0), 0)
1196 != stack_pointer_rtx))
1197 && (!REG_P (XEXP (PATTERN (insn), 0))
1198 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1204 /* Some CLOBBERs may survive until here and still reference unassigned
1205 pseudos with const equivalent, which may in turn cause ICE in later
1206 passes if the reference remains in place. */
1207 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1208 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1209 VOIDmode, PATTERN (insn));
1211 /* Discard obvious no-ops, even without -O. This optimization
1212 is fast and doesn't interfere with debugging. */
1213 if (NONJUMP_INSN_P (insn)
1214 && GET_CODE (PATTERN (insn)) == SET
1215 && REG_P (SET_SRC (PATTERN (insn)))
1216 && REG_P (SET_DEST (PATTERN (insn)))
1217 && (REGNO (SET_SRC (PATTERN (insn)))
1218 == REGNO (SET_DEST (PATTERN (insn)))))
1224 pnote = ®_NOTES (insn);
1227 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1228 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1229 || REG_NOTE_KIND (*pnote) == REG_INC)
1230 *pnote = XEXP (*pnote, 1);
1232 pnote = &XEXP (*pnote, 1);
1236 add_auto_inc_notes (insn, PATTERN (insn));
1239 /* Simplify (subreg (reg)) if it appears as an operand. */
1240 cleanup_subreg_operands (insn);
1242 /* Clean up invalid ASMs so that they don't confuse later passes.
1244 if (asm_noperands (PATTERN (insn)) >= 0)
1246 extract_insn (insn);
1247 if (!constrain_operands (1))
1249 error_for_asm (insn,
1250 "%<asm%> operand has impossible constraints");
1257 /* If we are doing generic stack checking, give a warning if this
1258 function's frame size is larger than we expect. */
1259 if (flag_stack_check == GENERIC_STACK_CHECK)
1261 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1262 static int verbose_warned = 0;
1264 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1265 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1266 size += UNITS_PER_WORD;
1268 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1270 warning (0, "frame size too large for reliable stack checking");
1271 if (! verbose_warned)
1273 warning (0, "try reducing the number of local variables");
1279 free (temp_pseudo_reg_arr);
1281 /* Indicate that we no longer have known memory locations or constants. */
1284 free (reg_max_ref_width);
1285 free (reg_old_renumber);
1286 free (pseudo_previous_regs);
1287 free (pseudo_forbidden_regs);
1289 CLEAR_HARD_REG_SET (used_spill_regs);
1290 for (i = 0; i < n_spills; i++)
1291 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1293 /* Free all the insn_chain structures at once. */
1294 obstack_free (&reload_obstack, reload_startobj);
1295 unused_insn_chains = 0;
1297 inserted = fixup_abnormal_edges ();
1299 /* We've possibly turned single trapping insn into multiple ones. */
1300 if (cfun->can_throw_non_call_exceptions)
1303 blocks = sbitmap_alloc (last_basic_block);
1304 bitmap_ones (blocks);
1305 find_many_sub_basic_blocks (blocks);
1306 sbitmap_free (blocks);
1310 commit_edge_insertions ();
1312 /* Replacing pseudos with their memory equivalents might have
1313 created shared rtx. Subsequent passes would get confused
1314 by this, so unshare everything here. */
1315 unshare_all_rtl_again (first);
1317 #ifdef STACK_BOUNDARY
1318 /* init_emit has set the alignment of the hard frame pointer
1319 to STACK_BOUNDARY. It is very likely no longer valid if
1320 the hard frame pointer was used for register allocation. */
1321 if (!frame_pointer_needed)
1322 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1325 substitute_stack.release ();
1327 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1329 reload_completed = !failure;
1334 /* Yet another special case. Unfortunately, reg-stack forces people to
1335 write incorrect clobbers in asm statements. These clobbers must not
1336 cause the register to appear in bad_spill_regs, otherwise we'll call
1337 fatal_insn later. We clear the corresponding regnos in the live
1338 register sets to avoid this.
1339 The whole thing is rather sick, I'm afraid. */
1342 maybe_fix_stack_asms (void)
1345 const char *constraints[MAX_RECOG_OPERANDS];
1346 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1347 struct insn_chain *chain;
1349 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1352 HARD_REG_SET clobbered, allowed;
1355 if (! INSN_P (chain->insn)
1356 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1358 pat = PATTERN (chain->insn);
1359 if (GET_CODE (pat) != PARALLEL)
1362 CLEAR_HARD_REG_SET (clobbered);
1363 CLEAR_HARD_REG_SET (allowed);
1365 /* First, make a mask of all stack regs that are clobbered. */
1366 for (i = 0; i < XVECLEN (pat, 0); i++)
1368 rtx t = XVECEXP (pat, 0, i);
1369 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1370 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1373 /* Get the operand values and constraints out of the insn. */
1374 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1375 constraints, operand_mode, NULL);
1377 /* For every operand, see what registers are allowed. */
1378 for (i = 0; i < noperands; i++)
1380 const char *p = constraints[i];
1381 /* For every alternative, we compute the class of registers allowed
1382 for reloading in CLS, and merge its contents into the reg set
1384 int cls = (int) NO_REGS;
1390 if (c == '\0' || c == ',' || c == '#')
1392 /* End of one alternative - mark the regs in the current
1393 class, and reset the class. */
1394 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1400 } while (c != '\0' && c != ',');
1408 case '=': case '+': case '*': case '%': case '?': case '!':
1409 case '0': case '1': case '2': case '3': case '4': case '<':
1410 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1411 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1412 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1413 case TARGET_MEM_CONSTRAINT:
1417 cls = (int) reg_class_subunion[cls]
1418 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1424 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1428 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1429 cls = (int) reg_class_subunion[cls]
1430 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1433 cls = (int) reg_class_subunion[cls]
1434 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1436 p += CONSTRAINT_LEN (c, p);
1439 /* Those of the registers which are clobbered, but allowed by the
1440 constraints, must be usable as reload registers. So clear them
1441 out of the life information. */
1442 AND_HARD_REG_SET (allowed, clobbered);
1443 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1444 if (TEST_HARD_REG_BIT (allowed, i))
1446 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1447 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1454 /* Copy the global variables n_reloads and rld into the corresponding elts
1457 copy_reloads (struct insn_chain *chain)
1459 chain->n_reloads = n_reloads;
1460 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1461 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1462 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1465 /* Walk the chain of insns, and determine for each whether it needs reloads
1466 and/or eliminations. Build the corresponding insns_need_reload list, and
1467 set something_needs_elimination as appropriate. */
1469 calculate_needs_all_insns (int global)
1471 struct insn_chain **pprev_reload = &insns_need_reload;
1472 struct insn_chain *chain, *next = 0;
1474 something_needs_elimination = 0;
1476 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1477 for (chain = reload_insn_chain; chain != 0; chain = next)
1479 rtx insn = chain->insn;
1483 /* Clear out the shortcuts. */
1484 chain->n_reloads = 0;
1485 chain->need_elim = 0;
1486 chain->need_reload = 0;
1487 chain->need_operand_change = 0;
1489 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1490 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1491 what effects this has on the known offsets at labels. */
1493 if (LABEL_P (insn) || JUMP_P (insn)
1494 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1495 set_label_offsets (insn, insn, 0);
1499 rtx old_body = PATTERN (insn);
1500 int old_code = INSN_CODE (insn);
1501 rtx old_notes = REG_NOTES (insn);
1502 int did_elimination = 0;
1503 int operands_changed = 0;
1504 rtx set = single_set (insn);
1506 /* Skip insns that only set an equivalence. */
1507 if (set && REG_P (SET_DEST (set))
1508 && reg_renumber[REGNO (SET_DEST (set))] < 0
1509 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1510 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1511 && reg_equiv_init (REGNO (SET_DEST (set))))
1514 /* If needed, eliminate any eliminable registers. */
1515 if (num_eliminable || num_eliminable_invariants)
1516 did_elimination = eliminate_regs_in_insn (insn, 0);
1518 /* Analyze the instruction. */
1519 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1520 global, spill_reg_order);
1522 /* If a no-op set needs more than one reload, this is likely
1523 to be something that needs input address reloads. We
1524 can't get rid of this cleanly later, and it is of no use
1525 anyway, so discard it now.
1526 We only do this when expensive_optimizations is enabled,
1527 since this complements reload inheritance / output
1528 reload deletion, and it can make debugging harder. */
1529 if (flag_expensive_optimizations && n_reloads > 1)
1531 rtx set = single_set (insn);
1534 ((SET_SRC (set) == SET_DEST (set)
1535 && REG_P (SET_SRC (set))
1536 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1537 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1538 && reg_renumber[REGNO (SET_SRC (set))] < 0
1539 && reg_renumber[REGNO (SET_DEST (set))] < 0
1540 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1541 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1542 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1543 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1545 if (ira_conflicts_p)
1546 /* Inform IRA about the insn deletion. */
1547 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1548 REGNO (SET_SRC (set)));
1550 /* Delete it from the reload chain. */
1552 chain->prev->next = next;
1554 reload_insn_chain = next;
1556 next->prev = chain->prev;
1557 chain->next = unused_insn_chains;
1558 unused_insn_chains = chain;
1563 update_eliminable_offsets ();
1565 /* Remember for later shortcuts which insns had any reloads or
1566 register eliminations. */
1567 chain->need_elim = did_elimination;
1568 chain->need_reload = n_reloads > 0;
1569 chain->need_operand_change = operands_changed;
1571 /* Discard any register replacements done. */
1572 if (did_elimination)
1574 obstack_free (&reload_obstack, reload_insn_firstobj);
1575 PATTERN (insn) = old_body;
1576 INSN_CODE (insn) = old_code;
1577 REG_NOTES (insn) = old_notes;
1578 something_needs_elimination = 1;
1581 something_needs_operands_changed |= operands_changed;
1585 copy_reloads (chain);
1586 *pprev_reload = chain;
1587 pprev_reload = &chain->next_need_reload;
1594 /* This function is called from the register allocator to set up estimates
1595 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1596 an invariant. The structure is similar to calculate_needs_all_insns. */
1599 calculate_elim_costs_all_insns (void)
1601 int *reg_equiv_init_cost;
1605 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1607 init_eliminable_invariants (get_insns (), false);
1609 set_initial_elim_offsets ();
1610 set_initial_label_offsets ();
1617 FOR_BB_INSNS (bb, insn)
1619 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1620 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1621 what effects this has on the known offsets at labels. */
1623 if (LABEL_P (insn) || JUMP_P (insn)
1624 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1625 set_label_offsets (insn, insn, 0);
1629 rtx set = single_set (insn);
1631 /* Skip insns that only set an equivalence. */
1632 if (set && REG_P (SET_DEST (set))
1633 && reg_renumber[REGNO (SET_DEST (set))] < 0
1634 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1635 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1637 unsigned regno = REGNO (SET_DEST (set));
1638 rtx init = reg_equiv_init (regno);
1641 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1643 int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1644 int freq = REG_FREQ_FROM_BB (bb);
1646 reg_equiv_init_cost[regno] = cost * freq;
1650 /* If needed, eliminate any eliminable registers. */
1651 if (num_eliminable || num_eliminable_invariants)
1652 elimination_costs_in_insn (insn);
1655 update_eliminable_offsets ();
1659 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1661 if (reg_equiv_invariant (i))
1663 if (reg_equiv_init (i))
1665 int cost = reg_equiv_init_cost[i];
1668 "Reg %d has equivalence, initial gains %d\n", i, cost);
1670 ira_adjust_equiv_reg_cost (i, cost);
1676 "Reg %d had equivalence, but can't be eliminated\n",
1678 ira_adjust_equiv_reg_cost (i, 0);
1683 free (reg_equiv_init_cost);
1684 free (offsets_known_at);
1687 offsets_known_at = NULL;
1690 /* Comparison function for qsort to decide which of two reloads
1691 should be handled first. *P1 and *P2 are the reload numbers. */
1694 reload_reg_class_lower (const void *r1p, const void *r2p)
1696 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1699 /* Consider required reloads before optional ones. */
1700 t = rld[r1].optional - rld[r2].optional;
1704 /* Count all solitary classes before non-solitary ones. */
1705 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1706 - (reg_class_size[(int) rld[r1].rclass] == 1));
1710 /* Aside from solitaires, consider all multi-reg groups first. */
1711 t = rld[r2].nregs - rld[r1].nregs;
1715 /* Consider reloads in order of increasing reg-class number. */
1716 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1720 /* If reloads are equally urgent, sort by reload number,
1721 so that the results of qsort leave nothing to chance. */
1725 /* The cost of spilling each hard reg. */
1726 static int spill_cost[FIRST_PSEUDO_REGISTER];
1728 /* When spilling multiple hard registers, we use SPILL_COST for the first
1729 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1730 only the first hard reg for a multi-reg pseudo. */
1731 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1733 /* Map of hard regno to pseudo regno currently occupying the hard
1735 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1737 /* Update the spill cost arrays, considering that pseudo REG is live. */
1740 count_pseudo (int reg)
1742 int freq = REG_FREQ (reg);
1743 int r = reg_renumber[reg];
1746 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1747 if (ira_conflicts_p && r < 0)
1750 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1751 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1754 SET_REGNO_REG_SET (&pseudos_counted, reg);
1756 gcc_assert (r >= 0);
1758 spill_add_cost[r] += freq;
1759 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1762 hard_regno_to_pseudo_regno[r + nregs] = reg;
1763 spill_cost[r + nregs] += freq;
1767 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1768 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1771 order_regs_for_reload (struct insn_chain *chain)
1774 HARD_REG_SET used_by_pseudos;
1775 HARD_REG_SET used_by_pseudos2;
1776 reg_set_iterator rsi;
1778 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1780 memset (spill_cost, 0, sizeof spill_cost);
1781 memset (spill_add_cost, 0, sizeof spill_add_cost);
1782 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1783 hard_regno_to_pseudo_regno[i] = -1;
1785 /* Count number of uses of each hard reg by pseudo regs allocated to it
1786 and then order them by decreasing use. First exclude hard registers
1787 that are live in or across this insn. */
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1790 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1791 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1792 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1794 /* Now find out which pseudos are allocated to it, and update
1796 CLEAR_REG_SET (&pseudos_counted);
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1808 CLEAR_REG_SET (&pseudos_counted);
1811 /* Vector of reload-numbers showing the order in which the reloads should
1813 static short reload_order[MAX_RELOADS];
1815 /* This is used to keep track of the spill regs used in one insn. */
1816 static HARD_REG_SET used_spill_regs_local;
1818 /* We decided to spill hard register SPILLED, which has a size of
1819 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1820 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1821 update SPILL_COST/SPILL_ADD_COST. */
1824 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1826 int freq = REG_FREQ (reg);
1827 int r = reg_renumber[reg];
1830 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1831 if (ira_conflicts_p && r < 0)
1834 gcc_assert (r >= 0);
1836 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1838 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1839 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1842 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1844 spill_add_cost[r] -= freq;
1847 hard_regno_to_pseudo_regno[r + nregs] = -1;
1848 spill_cost[r + nregs] -= freq;
1852 /* Find reload register to use for reload number ORDER. */
1855 find_reg (struct insn_chain *chain, int order)
1857 int rnum = reload_order[order];
1858 struct reload *rl = rld + rnum;
1859 int best_cost = INT_MAX;
1861 unsigned int i, j, n;
1863 HARD_REG_SET not_usable;
1864 HARD_REG_SET used_by_other_reload;
1865 reg_set_iterator rsi;
1866 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1867 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1869 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1870 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1871 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1873 CLEAR_HARD_REG_SET (used_by_other_reload);
1874 for (k = 0; k < order; k++)
1876 int other = reload_order[k];
1878 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1879 for (j = 0; j < rld[other].nregs; j++)
1880 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1883 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1885 #ifdef REG_ALLOC_ORDER
1886 unsigned int regno = reg_alloc_order[i];
1888 unsigned int regno = i;
1891 if (! TEST_HARD_REG_BIT (not_usable, regno)
1892 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1893 && HARD_REGNO_MODE_OK (regno, rl->mode))
1895 int this_cost = spill_cost[regno];
1897 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1899 for (j = 1; j < this_nregs; j++)
1901 this_cost += spill_add_cost[regno + j];
1902 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1903 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1909 if (ira_conflicts_p)
1911 /* Ask IRA to find a better pseudo-register for
1913 for (n = j = 0; j < this_nregs; j++)
1915 int r = hard_regno_to_pseudo_regno[regno + j];
1919 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1920 regno_pseudo_regs[n++] = r;
1922 regno_pseudo_regs[n++] = -1;
1924 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1925 best_regno_pseudo_regs,
1932 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1933 if (regno_pseudo_regs[j] < 0)
1940 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1942 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1944 if (this_cost < best_cost
1945 /* Among registers with equal cost, prefer caller-saved ones, or
1946 use REG_ALLOC_ORDER if it is defined. */
1947 || (this_cost == best_cost
1948 #ifdef REG_ALLOC_ORDER
1949 && (inv_reg_alloc_order[regno]
1950 < inv_reg_alloc_order[best_reg])
1952 && call_used_regs[regno]
1953 && ! call_used_regs[best_reg]
1958 best_cost = this_cost;
1966 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1968 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1969 rl->regno = best_reg;
1971 EXECUTE_IF_SET_IN_REG_SET
1972 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1974 count_spilled_pseudo (best_reg, rl->nregs, j);
1977 EXECUTE_IF_SET_IN_REG_SET
1978 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1980 count_spilled_pseudo (best_reg, rl->nregs, j);
1983 for (i = 0; i < rl->nregs; i++)
1985 gcc_assert (spill_cost[best_reg + i] == 0);
1986 gcc_assert (spill_add_cost[best_reg + i] == 0);
1987 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1988 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1993 /* Find more reload regs to satisfy the remaining need of an insn, which
1995 Do it by ascending class number, since otherwise a reg
1996 might be spilled for a big class and might fail to count
1997 for a smaller class even though it belongs to that class. */
2000 find_reload_regs (struct insn_chain *chain)
2004 /* In order to be certain of getting the registers we need,
2005 we must sort the reloads into order of increasing register class.
2006 Then our grabbing of reload registers will parallel the process
2007 that provided the reload registers. */
2008 for (i = 0; i < chain->n_reloads; i++)
2010 /* Show whether this reload already has a hard reg. */
2011 if (chain->rld[i].reg_rtx)
2013 int regno = REGNO (chain->rld[i].reg_rtx);
2014 chain->rld[i].regno = regno;
2016 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2019 chain->rld[i].regno = -1;
2020 reload_order[i] = i;
2023 n_reloads = chain->n_reloads;
2024 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2026 CLEAR_HARD_REG_SET (used_spill_regs_local);
2029 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2031 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2033 /* Compute the order of preference for hard registers to spill. */
2035 order_regs_for_reload (chain);
2037 for (i = 0; i < n_reloads; i++)
2039 int r = reload_order[i];
2041 /* Ignore reloads that got marked inoperative. */
2042 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2043 && ! rld[r].optional
2044 && rld[r].regno == -1)
2045 if (! find_reg (chain, i))
2048 fprintf (dump_file, "reload failure for reload %d\n", r);
2049 spill_failure (chain->insn, rld[r].rclass);
2055 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2056 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2058 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2062 select_reload_regs (void)
2064 struct insn_chain *chain;
2066 /* Try to satisfy the needs for each insn. */
2067 for (chain = insns_need_reload; chain != 0;
2068 chain = chain->next_need_reload)
2069 find_reload_regs (chain);
2072 /* Delete all insns that were inserted by emit_caller_save_insns during
2075 delete_caller_save_insns (void)
2077 struct insn_chain *c = reload_insn_chain;
2081 while (c != 0 && c->is_caller_save_insn)
2083 struct insn_chain *next = c->next;
2086 if (c == reload_insn_chain)
2087 reload_insn_chain = next;
2091 next->prev = c->prev;
2093 c->prev->next = next;
2094 c->next = unused_insn_chains;
2095 unused_insn_chains = c;
2103 /* Handle the failure to find a register to spill.
2104 INSN should be one of the insns which needed this particular spill reg. */
2107 spill_failure (rtx insn, enum reg_class rclass)
2109 if (asm_noperands (PATTERN (insn)) >= 0)
2110 error_for_asm (insn, "can%'t find a register in class %qs while "
2111 "reloading %<asm%>",
2112 reg_class_names[rclass]);
2115 error ("unable to find a register to spill in class %qs",
2116 reg_class_names[rclass]);
2120 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2121 debug_reload_to_stream (dump_file);
2123 fatal_insn ("this is the insn:", insn);
2127 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2128 data that is dead in INSN. */
2131 delete_dead_insn (rtx insn)
2133 rtx prev = prev_active_insn (insn);
2136 /* If the previous insn sets a register that dies in our insn make
2137 a note that we want to run DCE immediately after reload.
2139 We used to delete the previous insn & recurse, but that's wrong for
2140 block local equivalences. Instead of trying to figure out the exact
2141 circumstances where we can delete the potentially dead insns, just
2142 let DCE do the job. */
2143 if (prev && GET_CODE (PATTERN (prev)) == SET
2144 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2145 && reg_mentioned_p (prev_dest, PATTERN (insn))
2146 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2147 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2150 SET_INSN_DELETED (insn);
2153 /* Modify the home of pseudo-reg I.
2154 The new home is present in reg_renumber[I].
2156 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2157 or it may be -1, meaning there is none or it is not relevant.
2158 This is used so that all pseudos spilled from a given hard reg
2159 can share one stack slot. */
2162 alter_reg (int i, int from_reg, bool dont_share_p)
2164 /* When outputting an inline function, this can happen
2165 for a reg that isn't actually used. */
2166 if (regno_reg_rtx[i] == 0)
2169 /* If the reg got changed to a MEM at rtl-generation time,
2171 if (!REG_P (regno_reg_rtx[i]))
2174 /* Modify the reg-rtx to contain the new hard reg
2175 number or else to contain its pseudo reg number. */
2176 SET_REGNO (regno_reg_rtx[i],
2177 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2179 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2180 allocate a stack slot for it. */
2182 if (reg_renumber[i] < 0
2183 && REG_N_REFS (i) > 0
2184 && reg_equiv_constant (i) == 0
2185 && (reg_equiv_invariant (i) == 0
2186 || reg_equiv_init (i) == 0)
2187 && reg_equiv_memory_loc (i) == 0)
2190 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2191 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2192 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2193 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2194 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2197 something_was_spilled = true;
2199 if (ira_conflicts_p)
2201 /* Mark the spill for IRA. */
2202 SET_REGNO_REG_SET (&spilled_pseudos, i);
2204 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2210 /* Each pseudo reg has an inherent size which comes from its own mode,
2211 and a total size which provides room for paradoxical subregs
2212 which refer to the pseudo reg in wider modes.
2214 We can use a slot already allocated if it provides both
2215 enough inherent space and enough total space.
2216 Otherwise, we allocate a new slot, making sure that it has no less
2217 inherent space, and no less total space, then the previous slot. */
2218 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2222 /* No known place to spill from => no slot to reuse. */
2223 x = assign_stack_local (mode, total_size,
2224 min_align > inherent_align
2225 || total_size > inherent_size ? -1 : 0);
2229 /* Cancel the big-endian correction done in assign_stack_local.
2230 Get the address of the beginning of the slot. This is so we
2231 can do a big-endian correction unconditionally below. */
2232 if (BYTES_BIG_ENDIAN)
2234 adjust = inherent_size - total_size;
2237 = adjust_address_nv (x, mode_for_size (total_size
2243 if (! dont_share_p && ira_conflicts_p)
2244 /* Inform IRA about allocation a new stack slot. */
2245 ira_mark_new_stack_slot (stack_slot, i, total_size);
2248 /* Reuse a stack slot if possible. */
2249 else if (spill_stack_slot[from_reg] != 0
2250 && spill_stack_slot_width[from_reg] >= total_size
2251 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2253 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2254 x = spill_stack_slot[from_reg];
2256 /* Allocate a bigger slot. */
2259 /* Compute maximum size needed, both for inherent size
2260 and for total size. */
2263 if (spill_stack_slot[from_reg])
2265 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2267 mode = GET_MODE (spill_stack_slot[from_reg]);
2268 if (spill_stack_slot_width[from_reg] > total_size)
2269 total_size = spill_stack_slot_width[from_reg];
2270 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2271 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2274 /* Make a slot with that size. */
2275 x = assign_stack_local (mode, total_size,
2276 min_align > inherent_align
2277 || total_size > inherent_size ? -1 : 0);
2280 /* Cancel the big-endian correction done in assign_stack_local.
2281 Get the address of the beginning of the slot. This is so we
2282 can do a big-endian correction unconditionally below. */
2283 if (BYTES_BIG_ENDIAN)
2285 adjust = GET_MODE_SIZE (mode) - total_size;
2288 = adjust_address_nv (x, mode_for_size (total_size
2294 spill_stack_slot[from_reg] = stack_slot;
2295 spill_stack_slot_width[from_reg] = total_size;
2298 /* On a big endian machine, the "address" of the slot
2299 is the address of the low part that fits its inherent mode. */
2300 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2301 adjust += (total_size - inherent_size);
2303 /* If we have any adjustment to make, or if the stack slot is the
2304 wrong mode, make a new stack slot. */
2305 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2307 /* Set all of the memory attributes as appropriate for a spill. */
2308 set_mem_attrs_for_spill (x);
2310 /* Save the stack slot for later. */
2311 reg_equiv_memory_loc (i) = x;
2315 /* Mark the slots in regs_ever_live for the hard regs used by
2316 pseudo-reg number REGNO, accessed in MODE. */
2319 mark_home_live_1 (int regno, enum machine_mode mode)
2323 i = reg_renumber[regno];
2326 lim = end_hard_regno (mode, i);
2328 df_set_regs_ever_live(i++, true);
2331 /* Mark the slots in regs_ever_live for the hard regs
2332 used by pseudo-reg number REGNO. */
2335 mark_home_live (int regno)
2337 if (reg_renumber[regno] >= 0)
2338 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2341 /* This function handles the tracking of elimination offsets around branches.
2343 X is a piece of RTL being scanned.
2345 INSN is the insn that it came from, if any.
2347 INITIAL_P is nonzero if we are to set the offset to be the initial
2348 offset and zero if we are setting the offset of the label to be the
2352 set_label_offsets (rtx x, rtx insn, int initial_p)
2354 enum rtx_code code = GET_CODE (x);
2357 struct elim_table *p;
2362 if (LABEL_REF_NONLOCAL_P (x))
2367 /* ... fall through ... */
2370 /* If we know nothing about this label, set the desired offsets. Note
2371 that this sets the offset at a label to be the offset before a label
2372 if we don't know anything about the label. This is not correct for
2373 the label after a BARRIER, but is the best guess we can make. If
2374 we guessed wrong, we will suppress an elimination that might have
2375 been possible had we been able to guess correctly. */
2377 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2379 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2380 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2381 = (initial_p ? reg_eliminate[i].initial_offset
2382 : reg_eliminate[i].offset);
2383 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2386 /* Otherwise, if this is the definition of a label and it is
2387 preceded by a BARRIER, set our offsets to the known offset of
2391 && (tem = prev_nonnote_insn (insn)) != 0
2393 set_offsets_for_label (insn);
2395 /* If neither of the above cases is true, compare each offset
2396 with those previously recorded and suppress any eliminations
2397 where the offsets disagree. */
2399 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2400 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2401 != (initial_p ? reg_eliminate[i].initial_offset
2402 : reg_eliminate[i].offset))
2403 reg_eliminate[i].can_eliminate = 0;
2408 set_label_offsets (PATTERN (insn), insn, initial_p);
2410 /* ... fall through ... */
2414 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2415 to indirectly and hence must have all eliminations at their
2417 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2418 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2419 set_label_offsets (XEXP (tem, 0), insn, 1);
2425 /* Each of the labels in the parallel or address vector must be
2426 at their initial offsets. We want the first field for PARALLEL
2427 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2429 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2430 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2435 /* We only care about setting PC. If the source is not RETURN,
2436 IF_THEN_ELSE, or a label, disable any eliminations not at
2437 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2438 isn't one of those possibilities. For branches to a label,
2439 call ourselves recursively.
2441 Note that this can disable elimination unnecessarily when we have
2442 a non-local goto since it will look like a non-constant jump to
2443 someplace in the current function. This isn't a significant
2444 problem since such jumps will normally be when all elimination
2445 pairs are back to their initial offsets. */
2447 if (SET_DEST (x) != pc_rtx)
2450 switch (GET_CODE (SET_SRC (x)))
2457 set_label_offsets (SET_SRC (x), insn, initial_p);
2461 tem = XEXP (SET_SRC (x), 1);
2462 if (GET_CODE (tem) == LABEL_REF)
2463 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2464 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2467 tem = XEXP (SET_SRC (x), 2);
2468 if (GET_CODE (tem) == LABEL_REF)
2469 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2470 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2478 /* If we reach here, all eliminations must be at their initial
2479 offset because we are doing a jump to a variable address. */
2480 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2481 if (p->offset != p->initial_offset)
2482 p->can_eliminate = 0;
2490 /* Called through for_each_rtx, this function examines every reg that occurs
2491 in PX and adjusts the costs for its elimination which are gathered by IRA.
2492 DATA is the insn in which PX occurs. We do not recurse into MEM
2496 note_reg_elim_costly (rtx *px, void *data)
2498 rtx insn = (rtx)data;
2505 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2506 && reg_equiv_init (REGNO (x))
2507 && reg_equiv_invariant (REGNO (x)))
2509 rtx t = reg_equiv_invariant (REGNO (x));
2510 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2511 int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2512 int freq = REG_FREQ_FROM_BB (elim_bb);
2515 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2520 /* Scan X and replace any eliminable registers (such as fp) with a
2521 replacement (such as sp), plus an offset.
2523 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2524 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2525 MEM, we are allowed to replace a sum of a register and the constant zero
2526 with the register, which we cannot do outside a MEM. In addition, we need
2527 to record the fact that a register is referenced outside a MEM.
2529 If INSN is an insn, it is the insn containing X. If we replace a REG
2530 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2531 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2532 the REG is being modified.
2534 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2535 That's used when we eliminate in expressions stored in notes.
2536 This means, do not set ref_outside_mem even if the reference
2539 If FOR_COSTS is true, we are being called before reload in order to
2540 estimate the costs of keeping registers with an equivalence unallocated.
2542 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2543 replacements done assuming all offsets are at their initial values. If
2544 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2545 encounter, return the actual location so that find_reloads will do
2546 the proper thing. */
2549 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2550 bool may_use_invariant, bool for_costs)
2552 enum rtx_code code = GET_CODE (x);
2553 struct elim_table *ep;
2560 if (! current_function_decl)
2580 /* First handle the case where we encounter a bare register that
2581 is eliminable. Replace it with a PLUS. */
2582 if (regno < FIRST_PSEUDO_REGISTER)
2584 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2586 if (ep->from_rtx == x && ep->can_eliminate)
2587 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2590 else if (reg_renumber && reg_renumber[regno] < 0
2592 && reg_equiv_invariant (regno))
2594 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2595 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2596 mem_mode, insn, true, for_costs);
2597 /* There exists at least one use of REGNO that cannot be
2598 eliminated. Prevent the defining insn from being deleted. */
2599 reg_equiv_init (regno) = NULL_RTX;
2601 alter_reg (regno, -1, true);
2605 /* You might think handling MINUS in a manner similar to PLUS is a
2606 good idea. It is not. It has been tried multiple times and every
2607 time the change has had to have been reverted.
2609 Other parts of reload know a PLUS is special (gen_reload for example)
2610 and require special code to handle code a reloaded PLUS operand.
2612 Also consider backends where the flags register is clobbered by a
2613 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2614 lea instruction comes to mind). If we try to reload a MINUS, we
2615 may kill the flags register that was holding a useful value.
2617 So, please before trying to handle MINUS, consider reload as a
2618 whole instead of this little section as well as the backend issues. */
2620 /* If this is the sum of an eliminable register and a constant, rework
2622 if (REG_P (XEXP (x, 0))
2623 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2624 && CONSTANT_P (XEXP (x, 1)))
2626 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2628 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2630 /* The only time we want to replace a PLUS with a REG (this
2631 occurs when the constant operand of the PLUS is the negative
2632 of the offset) is when we are inside a MEM. We won't want
2633 to do so at other times because that would change the
2634 structure of the insn in a way that reload can't handle.
2635 We special-case the commonest situation in
2636 eliminate_regs_in_insn, so just replace a PLUS with a
2637 PLUS here, unless inside a MEM. */
2638 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2639 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2642 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2643 plus_constant (Pmode, XEXP (x, 1),
2644 ep->previous_offset));
2647 /* If the register is not eliminable, we are done since the other
2648 operand is a constant. */
2652 /* If this is part of an address, we want to bring any constant to the
2653 outermost PLUS. We will do this by doing register replacement in
2654 our operands and seeing if a constant shows up in one of them.
2656 Note that there is no risk of modifying the structure of the insn,
2657 since we only get called for its operands, thus we are either
2658 modifying the address inside a MEM, or something like an address
2659 operand of a load-address insn. */
2662 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2664 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2667 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2669 /* If one side is a PLUS and the other side is a pseudo that
2670 didn't get a hard register but has a reg_equiv_constant,
2671 we must replace the constant here since it may no longer
2672 be in the position of any operand. */
2673 if (GET_CODE (new0) == PLUS && REG_P (new1)
2674 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2675 && reg_renumber[REGNO (new1)] < 0
2677 && reg_equiv_constant (REGNO (new1)) != 0)
2678 new1 = reg_equiv_constant (REGNO (new1));
2679 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2680 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2681 && reg_renumber[REGNO (new0)] < 0
2682 && reg_equiv_constant (REGNO (new0)) != 0)
2683 new0 = reg_equiv_constant (REGNO (new0));
2685 new_rtx = form_sum (GET_MODE (x), new0, new1);
2687 /* As above, if we are not inside a MEM we do not want to
2688 turn a PLUS into something else. We might try to do so here
2689 for an addition of 0 if we aren't optimizing. */
2690 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2691 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2699 /* If this is the product of an eliminable register and a
2700 constant, apply the distribute law and move the constant out
2701 so that we have (plus (mult ..) ..). This is needed in order
2702 to keep load-address insns valid. This case is pathological.
2703 We ignore the possibility of overflow here. */
2704 if (REG_P (XEXP (x, 0))
2705 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2706 && CONST_INT_P (XEXP (x, 1)))
2707 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2709 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2712 /* Refs inside notes or in DEBUG_INSNs don't count for
2714 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2715 || GET_CODE (insn) == INSN_LIST
2716 || DEBUG_INSN_P (insn))))
2717 ep->ref_outside_mem = 1;
2720 plus_constant (Pmode,
2721 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2722 ep->previous_offset * INTVAL (XEXP (x, 1)));
2725 /* ... fall through ... */
2729 /* See comments before PLUS about handling MINUS. */
2731 case DIV: case UDIV:
2732 case MOD: case UMOD:
2733 case AND: case IOR: case XOR:
2734 case ROTATERT: case ROTATE:
2735 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2737 case GE: case GT: case GEU: case GTU:
2738 case LE: case LT: case LEU: case LTU:
2740 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2742 rtx new1 = XEXP (x, 1)
2743 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2746 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2747 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2752 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2755 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2757 if (new_rtx != XEXP (x, 0))
2759 /* If this is a REG_DEAD note, it is not valid anymore.
2760 Using the eliminated version could result in creating a
2761 REG_DEAD note for the stack or frame pointer. */
2762 if (REG_NOTE_KIND (x) == REG_DEAD)
2764 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2768 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2772 /* ... fall through ... */
2775 /* Now do eliminations in the rest of the chain. If this was
2776 an EXPR_LIST, this might result in allocating more memory than is
2777 strictly needed, but it simplifies the code. */
2780 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2782 if (new_rtx != XEXP (x, 1))
2784 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2792 /* We do not support elimination of a register that is modified.
2793 elimination_effects has already make sure that this does not
2799 /* We do not support elimination of a register that is modified.
2800 elimination_effects has already make sure that this does not
2801 happen. The only remaining case we need to consider here is
2802 that the increment value may be an eliminable register. */
2803 if (GET_CODE (XEXP (x, 1)) == PLUS
2804 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2806 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2807 insn, true, for_costs);
2809 if (new_rtx != XEXP (XEXP (x, 1), 1))
2810 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2811 gen_rtx_PLUS (GET_MODE (x),
2812 XEXP (x, 0), new_rtx));
2816 case STRICT_LOW_PART:
2818 case SIGN_EXTEND: case ZERO_EXTEND:
2819 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2820 case FLOAT: case FIX:
2821 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2830 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2832 if (new_rtx != XEXP (x, 0))
2833 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2837 /* Similar to above processing, but preserve SUBREG_BYTE.
2838 Convert (subreg (mem)) to (mem) if not paradoxical.
2839 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2840 pseudo didn't get a hard reg, we must replace this with the
2841 eliminated version of the memory location because push_reload
2842 may do the replacement in certain circumstances. */
2843 if (REG_P (SUBREG_REG (x))
2844 && !paradoxical_subreg_p (x)
2846 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2848 new_rtx = SUBREG_REG (x);
2851 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2853 if (new_rtx != SUBREG_REG (x))
2855 int x_size = GET_MODE_SIZE (GET_MODE (x));
2856 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2859 && ((x_size < new_size
2860 #ifdef WORD_REGISTER_OPERATIONS
2861 /* On these machines, combine can create rtl of the form
2862 (set (subreg:m1 (reg:m2 R) 0) ...)
2863 where m1 < m2, and expects something interesting to
2864 happen to the entire word. Moreover, it will use the
2865 (reg:m2 R) later, expecting all bits to be preserved.
2866 So if the number of words is the same, preserve the
2867 subreg so that push_reload can see it. */
2868 && ! ((x_size - 1) / UNITS_PER_WORD
2869 == (new_size -1 ) / UNITS_PER_WORD)
2872 || x_size == new_size)
2874 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2876 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2882 /* Our only special processing is to pass the mode of the MEM to our
2883 recursive call and copy the flags. While we are here, handle this
2884 case more efficiently. */
2886 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2889 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2890 && !memory_address_p (GET_MODE (x), new_rtx))
2891 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2893 return replace_equiv_address_nv (x, new_rtx);
2896 /* Handle insn_list USE that a call to a pure function may generate. */
2897 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2899 if (new_rtx != XEXP (x, 0))
2900 return gen_rtx_USE (GET_MODE (x), new_rtx);
2905 gcc_assert (insn && DEBUG_INSN_P (insn));
2915 /* Process each of our operands recursively. If any have changed, make a
2917 fmt = GET_RTX_FORMAT (code);
2918 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2922 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2924 if (new_rtx != XEXP (x, i) && ! copied)
2926 x = shallow_copy_rtx (x);
2929 XEXP (x, i) = new_rtx;
2931 else if (*fmt == 'E')
2934 for (j = 0; j < XVECLEN (x, i); j++)
2936 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2938 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2940 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2944 x = shallow_copy_rtx (x);
2947 XVEC (x, i) = new_v;
2950 XVECEXP (x, i, j) = new_rtx;
2959 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2961 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2964 /* Scan rtx X for modifications of elimination target registers. Update
2965 the table of eliminables to reflect the changed state. MEM_MODE is
2966 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2969 elimination_effects (rtx x, enum machine_mode mem_mode)
2971 enum rtx_code code = GET_CODE (x);
2972 struct elim_table *ep;
2994 /* First handle the case where we encounter a bare register that
2995 is eliminable. Replace it with a PLUS. */
2996 if (regno < FIRST_PSEUDO_REGISTER)
2998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3000 if (ep->from_rtx == x && ep->can_eliminate)
3003 ep->ref_outside_mem = 1;
3008 else if (reg_renumber[regno] < 0
3010 && reg_equiv_constant (regno)
3011 && ! function_invariant_p (reg_equiv_constant (regno)))
3012 elimination_effects (reg_equiv_constant (regno), mem_mode);
3021 /* If we modify the source of an elimination rule, disable it. */
3022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3023 if (ep->from_rtx == XEXP (x, 0))
3024 ep->can_eliminate = 0;
3026 /* If we modify the target of an elimination rule by adding a constant,
3027 update its offset. If we modify the target in any other way, we'll
3028 have to disable the rule as well. */
3029 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3030 if (ep->to_rtx == XEXP (x, 0))
3032 int size = GET_MODE_SIZE (mem_mode);
3034 /* If more bytes than MEM_MODE are pushed, account for them. */
3035 #ifdef PUSH_ROUNDING
3036 if (ep->to_rtx == stack_pointer_rtx)
3037 size = PUSH_ROUNDING (size);
3039 if (code == PRE_DEC || code == POST_DEC)
3041 else if (code == PRE_INC || code == POST_INC)
3043 else if (code == PRE_MODIFY || code == POST_MODIFY)
3045 if (GET_CODE (XEXP (x, 1)) == PLUS
3046 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3047 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3048 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3050 ep->can_eliminate = 0;
3054 /* These two aren't unary operators. */
3055 if (code == POST_MODIFY || code == PRE_MODIFY)
3058 /* Fall through to generic unary operation case. */
3059 case STRICT_LOW_PART:
3061 case SIGN_EXTEND: case ZERO_EXTEND:
3062 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3063 case FLOAT: case FIX:
3064 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3073 elimination_effects (XEXP (x, 0), mem_mode);
3077 if (REG_P (SUBREG_REG (x))
3078 && (GET_MODE_SIZE (GET_MODE (x))
3079 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3081 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3084 elimination_effects (SUBREG_REG (x), mem_mode);
3088 /* If using a register that is the source of an eliminate we still
3089 think can be performed, note it cannot be performed since we don't
3090 know how this register is used. */
3091 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3092 if (ep->from_rtx == XEXP (x, 0))
3093 ep->can_eliminate = 0;
3095 elimination_effects (XEXP (x, 0), mem_mode);
3099 /* If clobbering a register that is the replacement register for an
3100 elimination we still think can be performed, note that it cannot
3101 be performed. Otherwise, we need not be concerned about it. */
3102 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3103 if (ep->to_rtx == XEXP (x, 0))
3104 ep->can_eliminate = 0;
3106 elimination_effects (XEXP (x, 0), mem_mode);
3110 /* Check for setting a register that we know about. */
3111 if (REG_P (SET_DEST (x)))
3113 /* See if this is setting the replacement register for an
3116 If DEST is the hard frame pointer, we do nothing because we
3117 assume that all assignments to the frame pointer are for
3118 non-local gotos and are being done at a time when they are valid
3119 and do not disturb anything else. Some machines want to
3120 eliminate a fake argument pointer (or even a fake frame pointer)
3121 with either the real frame or the stack pointer. Assignments to
3122 the hard frame pointer must not prevent this elimination. */
3124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3126 if (ep->to_rtx == SET_DEST (x)
3127 && SET_DEST (x) != hard_frame_pointer_rtx)
3129 /* If it is being incremented, adjust the offset. Otherwise,
3130 this elimination can't be done. */
3131 rtx src = SET_SRC (x);
3133 if (GET_CODE (src) == PLUS
3134 && XEXP (src, 0) == SET_DEST (x)
3135 && CONST_INT_P (XEXP (src, 1)))
3136 ep->offset -= INTVAL (XEXP (src, 1));
3138 ep->can_eliminate = 0;
3142 elimination_effects (SET_DEST (x), VOIDmode);
3143 elimination_effects (SET_SRC (x), VOIDmode);
3147 /* Our only special processing is to pass the mode of the MEM to our
3149 elimination_effects (XEXP (x, 0), GET_MODE (x));
3156 fmt = GET_RTX_FORMAT (code);
3157 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3160 elimination_effects (XEXP (x, i), mem_mode);
3161 else if (*fmt == 'E')
3162 for (j = 0; j < XVECLEN (x, i); j++)
3163 elimination_effects (XVECEXP (x, i, j), mem_mode);
3167 /* Descend through rtx X and verify that no references to eliminable registers
3168 remain. If any do remain, mark the involved register as not
3172 check_eliminable_occurrences (rtx x)
3181 code = GET_CODE (x);
3183 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3185 struct elim_table *ep;
3187 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3188 if (ep->from_rtx == x)
3189 ep->can_eliminate = 0;
3193 fmt = GET_RTX_FORMAT (code);
3194 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3197 check_eliminable_occurrences (XEXP (x, i));
3198 else if (*fmt == 'E')
3201 for (j = 0; j < XVECLEN (x, i); j++)
3202 check_eliminable_occurrences (XVECEXP (x, i, j));
3207 /* Scan INSN and eliminate all eliminable registers in it.
3209 If REPLACE is nonzero, do the replacement destructively. Also
3210 delete the insn as dead it if it is setting an eliminable register.
3212 If REPLACE is zero, do all our allocations in reload_obstack.
3214 If no eliminations were done and this insn doesn't require any elimination
3215 processing (these are not identical conditions: it might be updating sp,
3216 but not referencing fp; this needs to be seen during reload_as_needed so
3217 that the offset between fp and sp can be taken into consideration), zero
3218 is returned. Otherwise, 1 is returned. */
3221 eliminate_regs_in_insn (rtx insn, int replace)
3223 int icode = recog_memoized (insn);
3224 rtx old_body = PATTERN (insn);
3225 int insn_is_asm = asm_noperands (old_body) >= 0;
3226 rtx old_set = single_set (insn);
3230 rtx substed_operand[MAX_RECOG_OPERANDS];
3231 rtx orig_operand[MAX_RECOG_OPERANDS];
3232 struct elim_table *ep;
3233 rtx plus_src, plus_cst_src;
3235 if (! insn_is_asm && icode < 0)
3237 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3238 || GET_CODE (PATTERN (insn)) == CLOBBER
3239 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3240 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3241 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3242 || DEBUG_INSN_P (insn));
3243 if (DEBUG_INSN_P (insn))
3244 INSN_VAR_LOCATION_LOC (insn)
3245 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3249 if (old_set != 0 && REG_P (SET_DEST (old_set))
3250 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3252 /* Check for setting an eliminable register. */
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3256 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3257 /* If this is setting the frame pointer register to the
3258 hardware frame pointer register and this is an elimination
3259 that will be done (tested above), this insn is really
3260 adjusting the frame pointer downward to compensate for
3261 the adjustment done before a nonlocal goto. */
3262 if (ep->from == FRAME_POINTER_REGNUM
3263 && ep->to == HARD_FRAME_POINTER_REGNUM)
3265 rtx base = SET_SRC (old_set);
3266 rtx base_insn = insn;
3267 HOST_WIDE_INT offset = 0;
3269 while (base != ep->to_rtx)
3271 rtx prev_insn, prev_set;
3273 if (GET_CODE (base) == PLUS
3274 && CONST_INT_P (XEXP (base, 1)))
3276 offset += INTVAL (XEXP (base, 1));
3277 base = XEXP (base, 0);
3279 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3280 && (prev_set = single_set (prev_insn)) != 0
3281 && rtx_equal_p (SET_DEST (prev_set), base))
3283 base = SET_SRC (prev_set);
3284 base_insn = prev_insn;
3290 if (base == ep->to_rtx)
3292 rtx src = plus_constant (Pmode, ep->to_rtx,
3293 offset - ep->offset);
3295 new_body = old_body;
3298 new_body = copy_insn (old_body);
3299 if (REG_NOTES (insn))
3300 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3302 PATTERN (insn) = new_body;
3303 old_set = single_set (insn);
3305 /* First see if this insn remains valid when we
3306 make the change. If not, keep the INSN_CODE
3307 the same and let reload fit it up. */
3308 validate_change (insn, &SET_SRC (old_set), src, 1);
3309 validate_change (insn, &SET_DEST (old_set),
3311 if (! apply_change_group ())
3313 SET_SRC (old_set) = src;
3314 SET_DEST (old_set) = ep->to_rtx;
3323 /* In this case this insn isn't serving a useful purpose. We
3324 will delete it in reload_as_needed once we know that this
3325 elimination is, in fact, being done.
3327 If REPLACE isn't set, we can't delete this insn, but needn't
3328 process it since it won't be used unless something changes. */
3331 delete_dead_insn (insn);
3339 /* We allow one special case which happens to work on all machines we
3340 currently support: a single set with the source or a REG_EQUAL
3341 note being a PLUS of an eliminable register and a constant. */
3342 plus_src = plus_cst_src = 0;
3343 if (old_set && REG_P (SET_DEST (old_set)))
3345 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3346 plus_src = SET_SRC (old_set);
3347 /* First see if the source is of the form (plus (...) CST). */
3349 && CONST_INT_P (XEXP (plus_src, 1)))
3350 plus_cst_src = plus_src;
3351 else if (REG_P (SET_SRC (old_set))
3354 /* Otherwise, see if we have a REG_EQUAL note of the form
3355 (plus (...) CST). */
3357 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3359 if ((REG_NOTE_KIND (links) == REG_EQUAL
3360 || REG_NOTE_KIND (links) == REG_EQUIV)
3361 && GET_CODE (XEXP (links, 0)) == PLUS
3362 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3364 plus_cst_src = XEXP (links, 0);
3370 /* Check that the first operand of the PLUS is a hard reg or
3371 the lowpart subreg of one. */
3374 rtx reg = XEXP (plus_cst_src, 0);
3375 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3376 reg = SUBREG_REG (reg);
3378 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3384 rtx reg = XEXP (plus_cst_src, 0);
3385 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3387 if (GET_CODE (reg) == SUBREG)
3388 reg = SUBREG_REG (reg);
3390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3391 if (ep->from_rtx == reg && ep->can_eliminate)
3393 rtx to_rtx = ep->to_rtx;
3394 offset += ep->offset;
3395 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3397 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3398 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3400 /* If we have a nonzero offset, and the source is already
3401 a simple REG, the following transformation would
3402 increase the cost of the insn by replacing a simple REG
3403 with (plus (reg sp) CST). So try only when we already
3404 had a PLUS before. */
3405 if (offset == 0 || plus_src)
3407 rtx new_src = plus_constant (GET_MODE (to_rtx),
3410 new_body = old_body;
3413 new_body = copy_insn (old_body);
3414 if (REG_NOTES (insn))
3415 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3417 PATTERN (insn) = new_body;
3418 old_set = single_set (insn);
3420 /* First see if this insn remains valid when we make the
3421 change. If not, try to replace the whole pattern with
3422 a simple set (this may help if the original insn was a
3423 PARALLEL that was only recognized as single_set due to
3424 REG_UNUSED notes). If this isn't valid either, keep
3425 the INSN_CODE the same and let reload fix it up. */
3426 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3428 rtx new_pat = gen_rtx_SET (VOIDmode,
3429 SET_DEST (old_set), new_src);
3431 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3432 SET_SRC (old_set) = new_src;
3439 /* This can't have an effect on elimination offsets, so skip right
3445 /* Determine the effects of this insn on elimination offsets. */
3446 elimination_effects (old_body, VOIDmode);
3448 /* Eliminate all eliminable registers occurring in operands that
3449 can be handled by reload. */
3450 extract_insn (insn);
3451 for (i = 0; i < recog_data.n_operands; i++)
3453 orig_operand[i] = recog_data.operand[i];
3454 substed_operand[i] = recog_data.operand[i];
3456 /* For an asm statement, every operand is eliminable. */
3457 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3459 bool is_set_src, in_plus;
3461 /* Check for setting a register that we know about. */
3462 if (recog_data.operand_type[i] != OP_IN
3463 && REG_P (orig_operand[i]))
3465 /* If we are assigning to a register that can be eliminated, it
3466 must be as part of a PARALLEL, since the code above handles
3467 single SETs. We must indicate that we can no longer
3468 eliminate this reg. */
3469 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3471 if (ep->from_rtx == orig_operand[i])
3472 ep->can_eliminate = 0;
3475 /* Companion to the above plus substitution, we can allow
3476 invariants as the source of a plain move. */
3479 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3483 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3484 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3488 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3489 replace ? insn : NULL_RTX,
3490 is_set_src || in_plus, false);
3491 if (substed_operand[i] != orig_operand[i])
3493 /* Terminate the search in check_eliminable_occurrences at
3495 *recog_data.operand_loc[i] = 0;
3497 /* If an output operand changed from a REG to a MEM and INSN is an
3498 insn, write a CLOBBER insn. */
3499 if (recog_data.operand_type[i] != OP_IN
3500 && REG_P (orig_operand[i])
3501 && MEM_P (substed_operand[i])
3503 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3507 for (i = 0; i < recog_data.n_dups; i++)
3508 *recog_data.dup_loc[i]
3509 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3511 /* If any eliminable remain, they aren't eliminable anymore. */
3512 check_eliminable_occurrences (old_body);
3514 /* Substitute the operands; the new values are in the substed_operand
3516 for (i = 0; i < recog_data.n_operands; i++)
3517 *recog_data.operand_loc[i] = substed_operand[i];
3518 for (i = 0; i < recog_data.n_dups; i++)
3519 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3521 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3522 re-recognize the insn. We do this in case we had a simple addition
3523 but now can do this as a load-address. This saves an insn in this
3525 If re-recognition fails, the old insn code number will still be used,
3526 and some register operands may have changed into PLUS expressions.
3527 These will be handled by find_reloads by loading them into a register
3532 /* If we aren't replacing things permanently and we changed something,
3533 make another copy to ensure that all the RTL is new. Otherwise
3534 things can go wrong if find_reload swaps commutative operands
3535 and one is inside RTL that has been copied while the other is not. */
3536 new_body = old_body;
3539 new_body = copy_insn (old_body);
3540 if (REG_NOTES (insn))
3541 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3543 PATTERN (insn) = new_body;
3545 /* If we had a move insn but now we don't, rerecognize it. This will
3546 cause spurious re-recognition if the old move had a PARALLEL since
3547 the new one still will, but we can't call single_set without
3548 having put NEW_BODY into the insn and the re-recognition won't
3549 hurt in this rare case. */
3550 /* ??? Why this huge if statement - why don't we just rerecognize the
3554 && ((REG_P (SET_SRC (old_set))
3555 && (GET_CODE (new_body) != SET
3556 || !REG_P (SET_SRC (new_body))))
3557 /* If this was a load from or store to memory, compare
3558 the MEM in recog_data.operand to the one in the insn.
3559 If they are not equal, then rerecognize the insn. */
3561 && ((MEM_P (SET_SRC (old_set))
3562 && SET_SRC (old_set) != recog_data.operand[1])
3563 || (MEM_P (SET_DEST (old_set))
3564 && SET_DEST (old_set) != recog_data.operand[0])))
3565 /* If this was an add insn before, rerecognize. */
3566 || GET_CODE (SET_SRC (old_set)) == PLUS))
3568 int new_icode = recog (PATTERN (insn), insn, 0);
3570 INSN_CODE (insn) = new_icode;
3574 /* Restore the old body. If there were any changes to it, we made a copy
3575 of it while the changes were still in place, so we'll correctly return
3576 a modified insn below. */
3579 /* Restore the old body. */
3580 for (i = 0; i < recog_data.n_operands; i++)
3581 /* Restoring a top-level match_parallel would clobber the new_body
3582 we installed in the insn. */
3583 if (recog_data.operand_loc[i] != &PATTERN (insn))
3584 *recog_data.operand_loc[i] = orig_operand[i];
3585 for (i = 0; i < recog_data.n_dups; i++)
3586 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3589 /* Update all elimination pairs to reflect the status after the current
3590 insn. The changes we make were determined by the earlier call to
3591 elimination_effects.
3593 We also detect cases where register elimination cannot be done,
3594 namely, if a register would be both changed and referenced outside a MEM
3595 in the resulting insn since such an insn is often undefined and, even if
3596 not, we cannot know what meaning will be given to it. Note that it is
3597 valid to have a register used in an address in an insn that changes it
3598 (presumably with a pre- or post-increment or decrement).
3600 If anything changes, return nonzero. */
3602 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3604 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3605 ep->can_eliminate = 0;
3607 ep->ref_outside_mem = 0;
3609 if (ep->previous_offset != ep->offset)
3614 /* If we changed something, perform elimination in REG_NOTES. This is
3615 needed even when REPLACE is zero because a REG_DEAD note might refer
3616 to a register that we eliminate and could cause a different number
3617 of spill registers to be needed in the final reload pass than in
3619 if (val && REG_NOTES (insn) != 0)
3621 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3627 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3628 register allocator. INSN is the instruction we need to examine, we perform
3629 eliminations in its operands and record cases where eliminating a reg with
3630 an invariant equivalence would add extra cost. */
3633 elimination_costs_in_insn (rtx insn)
3635 int icode = recog_memoized (insn);
3636 rtx old_body = PATTERN (insn);
3637 int insn_is_asm = asm_noperands (old_body) >= 0;
3638 rtx old_set = single_set (insn);
3640 rtx orig_operand[MAX_RECOG_OPERANDS];
3641 rtx orig_dup[MAX_RECOG_OPERANDS];
3642 struct elim_table *ep;
3643 rtx plus_src, plus_cst_src;
3646 if (! insn_is_asm && icode < 0)
3648 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3649 || GET_CODE (PATTERN (insn)) == CLOBBER
3650 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3651 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3652 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3653 || DEBUG_INSN_P (insn));
3657 if (old_set != 0 && REG_P (SET_DEST (old_set))
3658 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3660 /* Check for setting an eliminable register. */
3661 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3662 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3666 /* We allow one special case which happens to work on all machines we
3667 currently support: a single set with the source or a REG_EQUAL
3668 note being a PLUS of an eliminable register and a constant. */
3669 plus_src = plus_cst_src = 0;
3671 if (old_set && REG_P (SET_DEST (old_set)))
3674 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3675 plus_src = SET_SRC (old_set);
3676 /* First see if the source is of the form (plus (...) CST). */
3678 && CONST_INT_P (XEXP (plus_src, 1)))
3679 plus_cst_src = plus_src;
3680 else if (REG_P (SET_SRC (old_set))
3683 /* Otherwise, see if we have a REG_EQUAL note of the form
3684 (plus (...) CST). */
3686 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3688 if ((REG_NOTE_KIND (links) == REG_EQUAL
3689 || REG_NOTE_KIND (links) == REG_EQUIV)
3690 && GET_CODE (XEXP (links, 0)) == PLUS
3691 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3693 plus_cst_src = XEXP (links, 0);
3700 /* Determine the effects of this insn on elimination offsets. */
3701 elimination_effects (old_body, VOIDmode);
3703 /* Eliminate all eliminable registers occurring in operands that
3704 can be handled by reload. */
3705 extract_insn (insn);
3706 for (i = 0; i < recog_data.n_dups; i++)
3707 orig_dup[i] = *recog_data.dup_loc[i];
3709 for (i = 0; i < recog_data.n_operands; i++)
3711 orig_operand[i] = recog_data.operand[i];
3713 /* For an asm statement, every operand is eliminable. */
3714 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3716 bool is_set_src, in_plus;
3718 /* Check for setting a register that we know about. */
3719 if (recog_data.operand_type[i] != OP_IN
3720 && REG_P (orig_operand[i]))
3722 /* If we are assigning to a register that can be eliminated, it
3723 must be as part of a PARALLEL, since the code above handles
3724 single SETs. We must indicate that we can no longer
3725 eliminate this reg. */
3726 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3728 if (ep->from_rtx == orig_operand[i])
3729 ep->can_eliminate = 0;
3732 /* Companion to the above plus substitution, we can allow
3733 invariants as the source of a plain move. */
3735 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3737 if (is_set_src && !sets_reg_p)
3738 note_reg_elim_costly (&SET_SRC (old_set), insn);
3740 if (plus_src && sets_reg_p
3741 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3742 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3745 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3747 is_set_src || in_plus, true);
3748 /* Terminate the search in check_eliminable_occurrences at
3750 *recog_data.operand_loc[i] = 0;
3754 for (i = 0; i < recog_data.n_dups; i++)
3755 *recog_data.dup_loc[i]
3756 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3758 /* If any eliminable remain, they aren't eliminable anymore. */
3759 check_eliminable_occurrences (old_body);
3761 /* Restore the old body. */
3762 for (i = 0; i < recog_data.n_operands; i++)
3763 *recog_data.operand_loc[i] = orig_operand[i];
3764 for (i = 0; i < recog_data.n_dups; i++)
3765 *recog_data.dup_loc[i] = orig_dup[i];
3767 /* Update all elimination pairs to reflect the status after the current
3768 insn. The changes we make were determined by the earlier call to
3769 elimination_effects. */
3771 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3773 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3774 ep->can_eliminate = 0;
3776 ep->ref_outside_mem = 0;
3782 /* Loop through all elimination pairs.
3783 Recalculate the number not at initial offset.
3785 Compute the maximum offset (minimum offset if the stack does not
3786 grow downward) for each elimination pair. */
3789 update_eliminable_offsets (void)
3791 struct elim_table *ep;
3793 num_not_at_initial_offset = 0;
3794 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3796 ep->previous_offset = ep->offset;
3797 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3798 num_not_at_initial_offset++;
3802 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3803 replacement we currently believe is valid, mark it as not eliminable if X
3804 modifies DEST in any way other than by adding a constant integer to it.
3806 If DEST is the frame pointer, we do nothing because we assume that
3807 all assignments to the hard frame pointer are nonlocal gotos and are being
3808 done at a time when they are valid and do not disturb anything else.
3809 Some machines want to eliminate a fake argument pointer with either the
3810 frame or stack pointer. Assignments to the hard frame pointer must not
3811 prevent this elimination.
3813 Called via note_stores from reload before starting its passes to scan
3814 the insns of the function. */
3817 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3821 /* A SUBREG of a hard register here is just changing its mode. We should
3822 not see a SUBREG of an eliminable hard register, but check just in
3824 if (GET_CODE (dest) == SUBREG)
3825 dest = SUBREG_REG (dest);
3827 if (dest == hard_frame_pointer_rtx)
3830 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3831 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3832 && (GET_CODE (x) != SET
3833 || GET_CODE (SET_SRC (x)) != PLUS
3834 || XEXP (SET_SRC (x), 0) != dest
3835 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3837 reg_eliminate[i].can_eliminate_previous
3838 = reg_eliminate[i].can_eliminate = 0;
3843 /* Verify that the initial elimination offsets did not change since the
3844 last call to set_initial_elim_offsets. This is used to catch cases
3845 where something illegal happened during reload_as_needed that could
3846 cause incorrect code to be generated if we did not check for it. */
3849 verify_initial_elim_offsets (void)
3853 if (!num_eliminable)
3856 #ifdef ELIMINABLE_REGS
3858 struct elim_table *ep;
3860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3862 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3863 if (t != ep->initial_offset)
3868 INITIAL_FRAME_POINTER_OFFSET (t);
3869 if (t != reg_eliminate[0].initial_offset)
3876 /* Reset all offsets on eliminable registers to their initial values. */
3879 set_initial_elim_offsets (void)
3881 struct elim_table *ep = reg_eliminate;
3883 #ifdef ELIMINABLE_REGS
3884 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3886 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3887 ep->previous_offset = ep->offset = ep->initial_offset;
3890 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3891 ep->previous_offset = ep->offset = ep->initial_offset;
3894 num_not_at_initial_offset = 0;
3897 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3900 set_initial_eh_label_offset (rtx label)
3902 set_label_offsets (label, NULL_RTX, 1);
3905 /* Initialize the known label offsets.
3906 Set a known offset for each forced label to be at the initial offset
3907 of each elimination. We do this because we assume that all
3908 computed jumps occur from a location where each elimination is
3909 at its initial offset.
3910 For all other labels, show that we don't know the offsets. */
3913 set_initial_label_offsets (void)
3916 memset (offsets_known_at, 0, num_labels);
3918 for (x = forced_labels; x; x = XEXP (x, 1))
3920 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3922 for (x = nonlocal_goto_handler_labels; x; x = XEXP (x, 1))
3924 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3926 for_each_eh_label (set_initial_eh_label_offset);
3929 /* Set all elimination offsets to the known values for the code label given
3933 set_offsets_for_label (rtx insn)
3936 int label_nr = CODE_LABEL_NUMBER (insn);
3937 struct elim_table *ep;
3939 num_not_at_initial_offset = 0;
3940 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3942 ep->offset = ep->previous_offset
3943 = offsets_at[label_nr - first_label_num][i];
3944 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3945 num_not_at_initial_offset++;
3949 /* See if anything that happened changes which eliminations are valid.
3950 For example, on the SPARC, whether or not the frame pointer can
3951 be eliminated can depend on what registers have been used. We need
3952 not check some conditions again (such as flag_omit_frame_pointer)
3953 since they can't have changed. */
3956 update_eliminables (HARD_REG_SET *pset)
3958 int previous_frame_pointer_needed = frame_pointer_needed;
3959 struct elim_table *ep;
3961 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3962 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3963 && targetm.frame_pointer_required ())
3964 #ifdef ELIMINABLE_REGS
3965 || ! targetm.can_eliminate (ep->from, ep->to)
3968 ep->can_eliminate = 0;
3970 /* Look for the case where we have discovered that we can't replace
3971 register A with register B and that means that we will now be
3972 trying to replace register A with register C. This means we can
3973 no longer replace register C with register B and we need to disable
3974 such an elimination, if it exists. This occurs often with A == ap,
3975 B == sp, and C == fp. */
3977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3979 struct elim_table *op;
3982 if (! ep->can_eliminate && ep->can_eliminate_previous)
3984 /* Find the current elimination for ep->from, if there is a
3986 for (op = reg_eliminate;
3987 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3988 if (op->from == ep->from && op->can_eliminate)
3994 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3996 for (op = reg_eliminate;
3997 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3998 if (op->from == new_to && op->to == ep->to)
3999 op->can_eliminate = 0;
4003 /* See if any registers that we thought we could eliminate the previous
4004 time are no longer eliminable. If so, something has changed and we
4005 must spill the register. Also, recompute the number of eliminable
4006 registers and see if the frame pointer is needed; it is if there is
4007 no elimination of the frame pointer that we can perform. */
4009 frame_pointer_needed = 1;
4010 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4012 if (ep->can_eliminate
4013 && ep->from == FRAME_POINTER_REGNUM
4014 && ep->to != HARD_FRAME_POINTER_REGNUM
4015 && (! SUPPORTS_STACK_ALIGNMENT
4016 || ! crtl->stack_realign_needed))
4017 frame_pointer_needed = 0;
4019 if (! ep->can_eliminate && ep->can_eliminate_previous)
4021 ep->can_eliminate_previous = 0;
4022 SET_HARD_REG_BIT (*pset, ep->from);
4027 /* If we didn't need a frame pointer last time, but we do now, spill
4028 the hard frame pointer. */
4029 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4030 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4033 /* Return true if X is used as the target register of an elimination. */
4036 elimination_target_reg_p (rtx x)
4038 struct elim_table *ep;
4040 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4041 if (ep->to_rtx == x && ep->can_eliminate)
4047 /* Initialize the table of registers to eliminate.
4048 Pre-condition: global flag frame_pointer_needed has been set before
4049 calling this function. */
4052 init_elim_table (void)
4054 struct elim_table *ep;
4055 #ifdef ELIMINABLE_REGS
4056 const struct elim_table_1 *ep1;
4060 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4064 #ifdef ELIMINABLE_REGS
4065 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4066 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4068 ep->from = ep1->from;
4070 ep->can_eliminate = ep->can_eliminate_previous
4071 = (targetm.can_eliminate (ep->from, ep->to)
4072 && ! (ep->to == STACK_POINTER_REGNUM
4073 && frame_pointer_needed
4074 && (! SUPPORTS_STACK_ALIGNMENT
4075 || ! stack_realign_fp)));
4078 reg_eliminate[0].from = reg_eliminate_1[0].from;
4079 reg_eliminate[0].to = reg_eliminate_1[0].to;
4080 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4081 = ! frame_pointer_needed;
4084 /* Count the number of eliminable registers and build the FROM and TO
4085 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4086 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4087 We depend on this. */
4088 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4090 num_eliminable += ep->can_eliminate;
4091 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4092 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4096 /* Find all the pseudo registers that didn't get hard regs
4097 but do have known equivalent constants or memory slots.
4098 These include parameters (known equivalent to parameter slots)
4099 and cse'd or loop-moved constant memory addresses.
4101 Record constant equivalents in reg_equiv_constant
4102 so they will be substituted by find_reloads.
4103 Record memory equivalents in reg_mem_equiv so they can
4104 be substituted eventually by altering the REG-rtx's. */
4107 init_eliminable_invariants (rtx first, bool do_subregs)
4114 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4116 reg_max_ref_width = NULL;
4118 num_eliminable_invariants = 0;
4120 first_label_num = get_first_label_num ();
4121 num_labels = max_label_num () - first_label_num;
4123 /* Allocate the tables used to store offset information at labels. */
4124 offsets_known_at = XNEWVEC (char, num_labels);
4125 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4127 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4128 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4129 find largest such for each pseudo. FIRST is the head of the insn
4132 for (insn = first; insn; insn = NEXT_INSN (insn))
4134 rtx set = single_set (insn);
4136 /* We may introduce USEs that we want to remove at the end, so
4137 we'll mark them with QImode. Make sure there are no
4138 previously-marked insns left by say regmove. */
4139 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4140 && GET_MODE (insn) != VOIDmode)
4141 PUT_MODE (insn, VOIDmode);
4143 if (do_subregs && NONDEBUG_INSN_P (insn))
4144 scan_paradoxical_subregs (PATTERN (insn));
4146 if (set != 0 && REG_P (SET_DEST (set)))
4148 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4154 i = REGNO (SET_DEST (set));
4157 if (i <= LAST_VIRTUAL_REGISTER)
4160 /* If flag_pic and we have constant, verify it's legitimate. */
4162 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4164 /* It can happen that a REG_EQUIV note contains a MEM
4165 that is not a legitimate memory operand. As later
4166 stages of reload assume that all addresses found
4167 in the reg_equiv_* arrays were originally legitimate,
4168 we ignore such REG_EQUIV notes. */
4169 if (memory_operand (x, VOIDmode))
4171 /* Always unshare the equivalence, so we can
4172 substitute into this insn without touching the
4174 reg_equiv_memory_loc (i) = copy_rtx (x);
4176 else if (function_invariant_p (x))
4178 enum machine_mode mode;
4180 mode = GET_MODE (SET_DEST (set));
4181 if (GET_CODE (x) == PLUS)
4183 /* This is PLUS of frame pointer and a constant,
4184 and might be shared. Unshare it. */
4185 reg_equiv_invariant (i) = copy_rtx (x);
4186 num_eliminable_invariants++;
4188 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4190 reg_equiv_invariant (i) = x;
4191 num_eliminable_invariants++;
4193 else if (targetm.legitimate_constant_p (mode, x))
4194 reg_equiv_constant (i) = x;
4197 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4198 if (! reg_equiv_memory_loc (i))
4199 reg_equiv_init (i) = NULL_RTX;
4204 reg_equiv_init (i) = NULL_RTX;
4209 reg_equiv_init (i) = NULL_RTX;
4214 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4215 if (reg_equiv_init (i))
4217 fprintf (dump_file, "init_insns for %u: ", i);
4218 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4219 fprintf (dump_file, "\n");
4223 /* Indicate that we no longer have known memory locations or constants.
4224 Free all data involved in tracking these. */
4227 free_reg_equiv (void)
4231 free (offsets_known_at);
4234 offsets_known_at = 0;
4236 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4237 if (reg_equiv_alt_mem_list (i))
4238 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4239 vec_free (reg_equivs);
4242 /* Kick all pseudos out of hard register REGNO.
4244 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4245 because we found we can't eliminate some register. In the case, no pseudos
4246 are allowed to be in the register, even if they are only in a block that
4247 doesn't require spill registers, unlike the case when we are spilling this
4248 hard reg to produce another spill register.
4250 Return nonzero if any pseudos needed to be kicked out. */
4253 spill_hard_reg (unsigned int regno, int cant_eliminate)
4259 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4260 df_set_regs_ever_live (regno, true);
4263 /* Spill every pseudo reg that was allocated to this reg
4264 or to something that overlaps this reg. */
4266 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4267 if (reg_renumber[i] >= 0
4268 && (unsigned int) reg_renumber[i] <= regno
4269 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4270 SET_REGNO_REG_SET (&spilled_pseudos, i);
4273 /* After find_reload_regs has been run for all insn that need reloads,
4274 and/or spill_hard_regs was called, this function is used to actually
4275 spill pseudo registers and try to reallocate them. It also sets up the
4276 spill_regs array for use by choose_reload_regs. */
4279 finish_spills (int global)
4281 struct insn_chain *chain;
4282 int something_changed = 0;
4284 reg_set_iterator rsi;
4286 /* Build the spill_regs array for the function. */
4287 /* If there are some registers still to eliminate and one of the spill regs
4288 wasn't ever used before, additional stack space may have to be
4289 allocated to store this register. Thus, we may have changed the offset
4290 between the stack and frame pointers, so mark that something has changed.
4292 One might think that we need only set VAL to 1 if this is a call-used
4293 register. However, the set of registers that must be saved by the
4294 prologue is not identical to the call-used set. For example, the
4295 register used by the call insn for the return PC is a call-used register,
4296 but must be saved by the prologue. */
4299 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4300 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4302 spill_reg_order[i] = n_spills;
4303 spill_regs[n_spills++] = i;
4304 if (num_eliminable && ! df_regs_ever_live_p (i))
4305 something_changed = 1;
4306 df_set_regs_ever_live (i, true);
4309 spill_reg_order[i] = -1;
4311 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4312 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4314 /* Record the current hard register the pseudo is allocated to
4315 in pseudo_previous_regs so we avoid reallocating it to the
4316 same hard reg in a later pass. */
4317 gcc_assert (reg_renumber[i] >= 0);
4319 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4320 /* Mark it as no longer having a hard register home. */
4321 reg_renumber[i] = -1;
4322 if (ira_conflicts_p)
4323 /* Inform IRA about the change. */
4324 ira_mark_allocation_change (i);
4325 /* We will need to scan everything again. */
4326 something_changed = 1;
4329 /* Retry global register allocation if possible. */
4330 if (global && ira_conflicts_p)
4334 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4335 /* For every insn that needs reloads, set the registers used as spill
4336 regs in pseudo_forbidden_regs for every pseudo live across the
4338 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4340 EXECUTE_IF_SET_IN_REG_SET
4341 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4343 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4344 chain->used_spill_regs);
4346 EXECUTE_IF_SET_IN_REG_SET
4347 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4349 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4350 chain->used_spill_regs);
4354 /* Retry allocating the pseudos spilled in IRA and the
4355 reload. For each reg, merge the various reg sets that
4356 indicate which hard regs can't be used, and call
4357 ira_reassign_pseudos. */
4358 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4359 if (reg_old_renumber[i] != reg_renumber[i])
4361 if (reg_renumber[i] < 0)
4362 temp_pseudo_reg_arr[n++] = i;
4364 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4366 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4367 bad_spill_regs_global,
4368 pseudo_forbidden_regs, pseudo_previous_regs,
4370 something_changed = 1;
4372 /* Fix up the register information in the insn chain.
4373 This involves deleting those of the spilled pseudos which did not get
4374 a new hard register home from the live_{before,after} sets. */
4375 for (chain = reload_insn_chain; chain; chain = chain->next)
4377 HARD_REG_SET used_by_pseudos;
4378 HARD_REG_SET used_by_pseudos2;
4380 if (! ira_conflicts_p)
4382 /* Don't do it for IRA because IRA and the reload still can
4383 assign hard registers to the spilled pseudos on next
4384 reload iterations. */
4385 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4386 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4388 /* Mark any unallocated hard regs as available for spills. That
4389 makes inheritance work somewhat better. */
4390 if (chain->need_reload)
4392 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4393 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4394 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4396 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4397 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4398 /* Value of chain->used_spill_regs from previous iteration
4399 may be not included in the value calculated here because
4400 of possible removing caller-saves insns (see function
4401 delete_caller_save_insns. */
4402 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4403 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4407 CLEAR_REG_SET (&changed_allocation_pseudos);
4408 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4409 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4411 int regno = reg_renumber[i];
4412 if (reg_old_renumber[i] == regno)
4415 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4417 alter_reg (i, reg_old_renumber[i], false);
4418 reg_old_renumber[i] = regno;
4422 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4424 fprintf (dump_file, " Register %d now in %d.\n\n",
4425 i, reg_renumber[i]);
4429 return something_changed;
4432 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4435 scan_paradoxical_subregs (rtx x)
4439 enum rtx_code code = GET_CODE (x);
4455 if (REG_P (SUBREG_REG (x))
4456 && (GET_MODE_SIZE (GET_MODE (x))
4457 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4459 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4460 = GET_MODE_SIZE (GET_MODE (x));
4461 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4469 fmt = GET_RTX_FORMAT (code);
4470 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4473 scan_paradoxical_subregs (XEXP (x, i));
4474 else if (fmt[i] == 'E')
4477 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4478 scan_paradoxical_subregs (XVECEXP (x, i, j));
4483 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4484 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4485 and apply the corresponding narrowing subreg to *OTHER_PTR.
4486 Return true if the operands were changed, false otherwise. */
4489 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4491 rtx op, inner, other, tem;
4494 if (!paradoxical_subreg_p (op))
4496 inner = SUBREG_REG (op);
4499 tem = gen_lowpart_common (GET_MODE (inner), other);
4503 /* If the lowpart operation turned a hard register into a subreg,
4504 rather than simplifying it to another hard register, then the
4505 mode change cannot be properly represented. For example, OTHER
4506 might be valid in its current mode, but not in the new one. */
4507 if (GET_CODE (tem) == SUBREG
4509 && HARD_REGISTER_P (other))
4517 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4518 examine all of the reload insns between PREV and NEXT exclusive, and
4519 annotate all that may trap. */
4522 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4524 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4527 if (!insn_could_throw_p (insn))
4528 remove_note (insn, note);
4529 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4532 /* Reload pseudo-registers into hard regs around each insn as needed.
4533 Additional register load insns are output before the insn that needs it
4534 and perhaps store insns after insns that modify the reloaded pseudo reg.
4536 reg_last_reload_reg and reg_reloaded_contents keep track of
4537 which registers are already available in reload registers.
4538 We update these for the reloads that we perform,
4539 as the insns are scanned. */
4542 reload_as_needed (int live_known)
4544 struct insn_chain *chain;
4545 #if defined (AUTO_INC_DEC)
4550 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4551 memset (spill_reg_store, 0, sizeof spill_reg_store);
4552 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4553 INIT_REG_SET (®_has_output_reload);
4554 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4555 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4557 set_initial_elim_offsets ();
4559 /* Generate a marker insn that we will move around. */
4560 marker = emit_note (NOTE_INSN_DELETED);
4561 unlink_insn_chain (marker, marker);
4563 for (chain = reload_insn_chain; chain; chain = chain->next)
4566 rtx insn = chain->insn;
4567 rtx old_next = NEXT_INSN (insn);
4569 rtx old_prev = PREV_INSN (insn);
4572 /* If we pass a label, copy the offsets from the label information
4573 into the current offsets of each elimination. */
4575 set_offsets_for_label (insn);
4577 else if (INSN_P (insn))
4579 regset_head regs_to_forget;
4580 INIT_REG_SET (®s_to_forget);
4581 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4583 /* If this is a USE and CLOBBER of a MEM, ensure that any
4584 references to eliminable registers have been removed. */
4586 if ((GET_CODE (PATTERN (insn)) == USE
4587 || GET_CODE (PATTERN (insn)) == CLOBBER)
4588 && MEM_P (XEXP (PATTERN (insn), 0)))
4589 XEXP (XEXP (PATTERN (insn), 0), 0)
4590 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4591 GET_MODE (XEXP (PATTERN (insn), 0)),
4594 /* If we need to do register elimination processing, do so.
4595 This might delete the insn, in which case we are done. */
4596 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4598 eliminate_regs_in_insn (insn, 1);
4601 update_eliminable_offsets ();
4602 CLEAR_REG_SET (®s_to_forget);
4607 /* If need_elim is nonzero but need_reload is zero, one might think
4608 that we could simply set n_reloads to 0. However, find_reloads
4609 could have done some manipulation of the insn (such as swapping
4610 commutative operands), and these manipulations are lost during
4611 the first pass for every insn that needs register elimination.
4612 So the actions of find_reloads must be redone here. */
4614 if (! chain->need_elim && ! chain->need_reload
4615 && ! chain->need_operand_change)
4617 /* First find the pseudo regs that must be reloaded for this insn.
4618 This info is returned in the tables reload_... (see reload.h).
4619 Also modify the body of INSN by substituting RELOAD
4620 rtx's for those pseudo regs. */
4623 CLEAR_REG_SET (®_has_output_reload);
4624 CLEAR_HARD_REG_SET (reg_is_output_reload);
4626 find_reloads (insn, 1, spill_indirect_levels, live_known,
4632 rtx next = NEXT_INSN (insn);
4635 /* ??? PREV can get deleted by reload inheritance.
4636 Work around this by emitting a marker note. */
4637 prev = PREV_INSN (insn);
4638 reorder_insns_nobb (marker, marker, prev);
4640 /* Now compute which reload regs to reload them into. Perhaps
4641 reusing reload regs from previous insns, or else output
4642 load insns to reload them. Maybe output store insns too.
4643 Record the choices of reload reg in reload_reg_rtx. */
4644 choose_reload_regs (chain);
4646 /* Generate the insns to reload operands into or out of
4647 their reload regs. */
4648 emit_reload_insns (chain);
4650 /* Substitute the chosen reload regs from reload_reg_rtx
4651 into the insn's body (or perhaps into the bodies of other
4652 load and store insn that we just made for reloading
4653 and that we moved the structure into). */
4654 subst_reloads (insn);
4656 prev = PREV_INSN (marker);
4657 unlink_insn_chain (marker, marker);
4659 /* Adjust the exception region notes for loads and stores. */
4660 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4661 fixup_eh_region_note (insn, prev, next);
4663 /* Adjust the location of REG_ARGS_SIZE. */
4664 p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4667 remove_note (insn, p);
4668 fixup_args_size_notes (prev, PREV_INSN (next),
4669 INTVAL (XEXP (p, 0)));
4672 /* If this was an ASM, make sure that all the reload insns
4673 we have generated are valid. If not, give an error
4675 if (asm_noperands (PATTERN (insn)) >= 0)
4676 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4677 if (p != insn && INSN_P (p)
4678 && GET_CODE (PATTERN (p)) != USE
4679 && (recog_memoized (p) < 0
4680 || (extract_insn (p), ! constrain_operands (1))))
4682 error_for_asm (insn,
4683 "%<asm%> operand requires "
4684 "impossible reload");
4689 if (num_eliminable && chain->need_elim)
4690 update_eliminable_offsets ();
4692 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4693 is no longer validly lying around to save a future reload.
4694 Note that this does not detect pseudos that were reloaded
4695 for this insn in order to be stored in
4696 (obeying register constraints). That is correct; such reload
4697 registers ARE still valid. */
4698 forget_marked_reloads (®s_to_forget);
4699 CLEAR_REG_SET (®s_to_forget);
4701 /* There may have been CLOBBER insns placed after INSN. So scan
4702 between INSN and NEXT and use them to forget old reloads. */
4703 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4704 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4705 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4708 /* Likewise for regs altered by auto-increment in this insn.
4709 REG_INC notes have been changed by reloading:
4710 find_reloads_address_1 records substitutions for them,
4711 which have been performed by subst_reloads above. */
4712 for (i = n_reloads - 1; i >= 0; i--)
4714 rtx in_reg = rld[i].in_reg;
4717 enum rtx_code code = GET_CODE (in_reg);
4718 /* PRE_INC / PRE_DEC will have the reload register ending up
4719 with the same value as the stack slot, but that doesn't
4720 hold true for POST_INC / POST_DEC. Either we have to
4721 convert the memory access to a true POST_INC / POST_DEC,
4722 or we can't use the reload register for inheritance. */
4723 if ((code == POST_INC || code == POST_DEC)
4724 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4725 REGNO (rld[i].reg_rtx))
4726 /* Make sure it is the inc/dec pseudo, and not
4727 some other (e.g. output operand) pseudo. */
4728 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4729 == REGNO (XEXP (in_reg, 0))))
4732 rtx reload_reg = rld[i].reg_rtx;
4733 enum machine_mode mode = GET_MODE (reload_reg);
4737 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4739 /* We really want to ignore REG_INC notes here, so
4740 use PATTERN (p) as argument to reg_set_p . */
4741 if (reg_set_p (reload_reg, PATTERN (p)))
4743 n = count_occurrences (PATTERN (p), reload_reg, 0);
4749 = gen_rtx_fmt_e (code, mode, reload_reg);
4751 validate_replace_rtx_group (reload_reg,
4753 n = verify_changes (0);
4755 /* We must also verify that the constraints
4756 are met after the replacement. Make sure
4757 extract_insn is only called for an insn
4758 where the replacements were found to be
4763 n = constrain_operands (1);
4766 /* If the constraints were not met, then
4767 undo the replacement, else confirm it. */
4771 confirm_change_group ();
4777 add_reg_note (p, REG_INC, reload_reg);
4778 /* Mark this as having an output reload so that the
4779 REG_INC processing code below won't invalidate
4780 the reload for inheritance. */
4781 SET_HARD_REG_BIT (reg_is_output_reload,
4782 REGNO (reload_reg));
4783 SET_REGNO_REG_SET (®_has_output_reload,
4784 REGNO (XEXP (in_reg, 0)));
4787 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4790 else if ((code == PRE_INC || code == PRE_DEC)
4791 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4792 REGNO (rld[i].reg_rtx))
4793 /* Make sure it is the inc/dec pseudo, and not
4794 some other (e.g. output operand) pseudo. */
4795 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4796 == REGNO (XEXP (in_reg, 0))))
4798 SET_HARD_REG_BIT (reg_is_output_reload,
4799 REGNO (rld[i].reg_rtx));
4800 SET_REGNO_REG_SET (®_has_output_reload,
4801 REGNO (XEXP (in_reg, 0)));
4803 else if (code == PRE_INC || code == PRE_DEC
4804 || code == POST_INC || code == POST_DEC)
4806 int in_regno = REGNO (XEXP (in_reg, 0));
4808 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4811 bool forget_p = true;
4813 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4814 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4817 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4820 if (x == reg_reloaded_insn[in_hard_regno])
4826 /* If for some reasons, we didn't set up
4827 reg_last_reload_reg in this insn,
4828 invalidate inheritance from previous
4829 insns for the incremented/decremented
4830 register. Such registers will be not in
4831 reg_has_output_reload. Invalidate it
4832 also if the corresponding element in
4833 reg_reloaded_insn is also
4836 forget_old_reloads_1 (XEXP (in_reg, 0),
4842 /* If a pseudo that got a hard register is auto-incremented,
4843 we must purge records of copying it into pseudos without
4845 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4846 if (REG_NOTE_KIND (x) == REG_INC)
4848 /* See if this pseudo reg was reloaded in this insn.
4849 If so, its last-reload info is still valid
4850 because it is based on this insn's reload. */
4851 for (i = 0; i < n_reloads; i++)
4852 if (rld[i].out == XEXP (x, 0))
4856 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4860 /* A reload reg's contents are unknown after a label. */
4862 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4864 /* Don't assume a reload reg is still good after a call insn
4865 if it is a call-used reg, or if it contains a value that will
4866 be partially clobbered by the call. */
4867 else if (CALL_P (insn))
4869 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4870 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4872 /* If this is a call to a setjmp-type function, we must not
4873 reuse any reload reg contents across the call; that will
4874 just be clobbered by other uses of the register in later
4875 code, before the longjmp. */
4876 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4877 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4882 free (reg_last_reload_reg);
4883 CLEAR_REG_SET (®_has_output_reload);
4886 /* Discard all record of any value reloaded from X,
4887 or reloaded in X from someplace else;
4888 unless X is an output reload reg of the current insn.
4890 X may be a hard reg (the reload reg)
4891 or it may be a pseudo reg that was reloaded from.
4893 When DATA is non-NULL just mark the registers in regset
4894 to be forgotten later. */
4897 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4902 regset regs = (regset) data;
4904 /* note_stores does give us subregs of hard regs,
4905 subreg_regno_offset requires a hard reg. */
4906 while (GET_CODE (x) == SUBREG)
4908 /* We ignore the subreg offset when calculating the regno,
4909 because we are using the entire underlying hard register
4919 if (regno >= FIRST_PSEUDO_REGISTER)
4925 nr = hard_regno_nregs[regno][GET_MODE (x)];
4926 /* Storing into a spilled-reg invalidates its contents.
4927 This can happen if a block-local pseudo is allocated to that reg
4928 and it wasn't spilled because this block's total need is 0.
4929 Then some insn might have an optional reload and use this reg. */
4931 for (i = 0; i < nr; i++)
4932 /* But don't do this if the reg actually serves as an output
4933 reload reg in the current instruction. */
4935 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4937 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4938 spill_reg_store[regno + i] = 0;
4944 SET_REGNO_REG_SET (regs, regno + nr);
4947 /* Since value of X has changed,
4948 forget any value previously copied from it. */
4951 /* But don't forget a copy if this is the output reload
4952 that establishes the copy's validity. */
4954 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4955 reg_last_reload_reg[regno + nr] = 0;
4959 /* Forget the reloads marked in regset by previous function. */
4961 forget_marked_reloads (regset regs)
4964 reg_set_iterator rsi;
4965 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4967 if (reg < FIRST_PSEUDO_REGISTER
4968 /* But don't do this if the reg actually serves as an output
4969 reload reg in the current instruction. */
4971 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4973 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4974 spill_reg_store[reg] = 0;
4977 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4978 reg_last_reload_reg[reg] = 0;
4982 /* The following HARD_REG_SETs indicate when each hard register is
4983 used for a reload of various parts of the current insn. */
4985 /* If reg is unavailable for all reloads. */
4986 static HARD_REG_SET reload_reg_unavailable;
4987 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4988 static HARD_REG_SET reload_reg_used;
4989 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4990 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4991 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4992 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4993 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4994 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4995 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4996 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4997 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4998 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4999 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5000 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5001 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5002 static HARD_REG_SET reload_reg_used_in_op_addr;
5003 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5004 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5005 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5006 static HARD_REG_SET reload_reg_used_in_insn;
5007 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5008 static HARD_REG_SET reload_reg_used_in_other_addr;
5010 /* If reg is in use as a reload reg for any sort of reload. */
5011 static HARD_REG_SET reload_reg_used_at_all;
5013 /* If reg is use as an inherited reload. We just mark the first register
5015 static HARD_REG_SET reload_reg_used_for_inherit;
5017 /* Records which hard regs are used in any way, either as explicit use or
5018 by being allocated to a pseudo during any point of the current insn. */
5019 static HARD_REG_SET reg_used_in_insn;
5021 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5022 TYPE. MODE is used to indicate how many consecutive regs are
5026 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5027 enum machine_mode mode)
5032 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5035 case RELOAD_FOR_INPUT_ADDRESS:
5036 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5039 case RELOAD_FOR_INPADDR_ADDRESS:
5040 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5043 case RELOAD_FOR_OUTPUT_ADDRESS:
5044 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5047 case RELOAD_FOR_OUTADDR_ADDRESS:
5048 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5051 case RELOAD_FOR_OPERAND_ADDRESS:
5052 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5055 case RELOAD_FOR_OPADDR_ADDR:
5056 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5059 case RELOAD_FOR_OTHER_ADDRESS:
5060 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5063 case RELOAD_FOR_INPUT:
5064 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5067 case RELOAD_FOR_OUTPUT:
5068 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5071 case RELOAD_FOR_INSN:
5072 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5076 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5079 /* Similarly, but show REGNO is no longer in use for a reload. */
5082 clear_reload_reg_in_use (unsigned int regno, int opnum,
5083 enum reload_type type, enum machine_mode mode)
5085 unsigned int nregs = hard_regno_nregs[regno][mode];
5086 unsigned int start_regno, end_regno, r;
5088 /* A complication is that for some reload types, inheritance might
5089 allow multiple reloads of the same types to share a reload register.
5090 We set check_opnum if we have to check only reloads with the same
5091 operand number, and check_any if we have to check all reloads. */
5092 int check_opnum = 0;
5094 HARD_REG_SET *used_in_set;
5099 used_in_set = &reload_reg_used;
5102 case RELOAD_FOR_INPUT_ADDRESS:
5103 used_in_set = &reload_reg_used_in_input_addr[opnum];
5106 case RELOAD_FOR_INPADDR_ADDRESS:
5108 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5111 case RELOAD_FOR_OUTPUT_ADDRESS:
5112 used_in_set = &reload_reg_used_in_output_addr[opnum];
5115 case RELOAD_FOR_OUTADDR_ADDRESS:
5117 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5120 case RELOAD_FOR_OPERAND_ADDRESS:
5121 used_in_set = &reload_reg_used_in_op_addr;
5124 case RELOAD_FOR_OPADDR_ADDR:
5126 used_in_set = &reload_reg_used_in_op_addr_reload;
5129 case RELOAD_FOR_OTHER_ADDRESS:
5130 used_in_set = &reload_reg_used_in_other_addr;
5134 case RELOAD_FOR_INPUT:
5135 used_in_set = &reload_reg_used_in_input[opnum];
5138 case RELOAD_FOR_OUTPUT:
5139 used_in_set = &reload_reg_used_in_output[opnum];
5142 case RELOAD_FOR_INSN:
5143 used_in_set = &reload_reg_used_in_insn;
5148 /* We resolve conflicts with remaining reloads of the same type by
5149 excluding the intervals of reload registers by them from the
5150 interval of freed reload registers. Since we only keep track of
5151 one set of interval bounds, we might have to exclude somewhat
5152 more than what would be necessary if we used a HARD_REG_SET here.
5153 But this should only happen very infrequently, so there should
5154 be no reason to worry about it. */
5156 start_regno = regno;
5157 end_regno = regno + nregs;
5158 if (check_opnum || check_any)
5160 for (i = n_reloads - 1; i >= 0; i--)
5162 if (rld[i].when_needed == type
5163 && (check_any || rld[i].opnum == opnum)
5166 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5167 unsigned int conflict_end
5168 = end_hard_regno (rld[i].mode, conflict_start);
5170 /* If there is an overlap with the first to-be-freed register,
5171 adjust the interval start. */
5172 if (conflict_start <= start_regno && conflict_end > start_regno)
5173 start_regno = conflict_end;
5174 /* Otherwise, if there is a conflict with one of the other
5175 to-be-freed registers, adjust the interval end. */
5176 if (conflict_start > start_regno && conflict_start < end_regno)
5177 end_regno = conflict_start;
5182 for (r = start_regno; r < end_regno; r++)
5183 CLEAR_HARD_REG_BIT (*used_in_set, r);
5186 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5187 specified by OPNUM and TYPE. */
5190 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5194 /* In use for a RELOAD_OTHER means it's not available for anything. */
5195 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5196 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5202 /* In use for anything means we can't use it for RELOAD_OTHER. */
5203 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5204 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5205 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5206 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5209 for (i = 0; i < reload_n_operands; i++)
5210 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5211 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5212 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5213 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5214 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5215 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5220 case RELOAD_FOR_INPUT:
5221 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5222 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5225 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5228 /* If it is used for some other input, can't use it. */
5229 for (i = 0; i < reload_n_operands; i++)
5230 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5233 /* If it is used in a later operand's address, can't use it. */
5234 for (i = opnum + 1; i < reload_n_operands; i++)
5235 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5236 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5241 case RELOAD_FOR_INPUT_ADDRESS:
5242 /* Can't use a register if it is used for an input address for this
5243 operand or used as an input in an earlier one. */
5244 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5245 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5248 for (i = 0; i < opnum; i++)
5249 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5254 case RELOAD_FOR_INPADDR_ADDRESS:
5255 /* Can't use a register if it is used for an input address
5256 for this operand or used as an input in an earlier
5258 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5261 for (i = 0; i < opnum; i++)
5262 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5267 case RELOAD_FOR_OUTPUT_ADDRESS:
5268 /* Can't use a register if it is used for an output address for this
5269 operand or used as an output in this or a later operand. Note
5270 that multiple output operands are emitted in reverse order, so
5271 the conflicting ones are those with lower indices. */
5272 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5275 for (i = 0; i <= opnum; i++)
5276 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5281 case RELOAD_FOR_OUTADDR_ADDRESS:
5282 /* Can't use a register if it is used for an output address
5283 for this operand or used as an output in this or a
5284 later operand. Note that multiple output operands are
5285 emitted in reverse order, so the conflicting ones are
5286 those with lower indices. */
5287 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5290 for (i = 0; i <= opnum; i++)
5291 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5296 case RELOAD_FOR_OPERAND_ADDRESS:
5297 for (i = 0; i < reload_n_operands; i++)
5298 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5301 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5302 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5304 case RELOAD_FOR_OPADDR_ADDR:
5305 for (i = 0; i < reload_n_operands; i++)
5306 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5309 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5311 case RELOAD_FOR_OUTPUT:
5312 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5313 outputs, or an operand address for this or an earlier output.
5314 Note that multiple output operands are emitted in reverse order,
5315 so the conflicting ones are those with higher indices. */
5316 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5319 for (i = 0; i < reload_n_operands; i++)
5320 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5323 for (i = opnum; i < reload_n_operands; i++)
5324 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5325 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5330 case RELOAD_FOR_INSN:
5331 for (i = 0; i < reload_n_operands; i++)
5332 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5333 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5336 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5337 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5339 case RELOAD_FOR_OTHER_ADDRESS:
5340 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5347 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5348 the number RELOADNUM, is still available in REGNO at the end of the insn.
5350 We can assume that the reload reg was already tested for availability
5351 at the time it is needed, and we should not check this again,
5352 in case the reg has already been marked in use. */
5355 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5357 int opnum = rld[reloadnum].opnum;
5358 enum reload_type type = rld[reloadnum].when_needed;
5361 /* See if there is a reload with the same type for this operand, using
5362 the same register. This case is not handled by the code below. */
5363 for (i = reloadnum + 1; i < n_reloads; i++)
5368 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5370 reg = rld[i].reg_rtx;
5371 if (reg == NULL_RTX)
5373 nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5374 if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5381 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5382 its value must reach the end. */
5385 /* If this use is for part of the insn,
5386 its value reaches if no subsequent part uses the same register.
5387 Just like the above function, don't try to do this with lots
5390 case RELOAD_FOR_OTHER_ADDRESS:
5391 /* Here we check for everything else, since these don't conflict
5392 with anything else and everything comes later. */
5394 for (i = 0; i < reload_n_operands; i++)
5395 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5396 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5397 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5398 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5399 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5400 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5403 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5404 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5405 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5406 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5408 case RELOAD_FOR_INPUT_ADDRESS:
5409 case RELOAD_FOR_INPADDR_ADDRESS:
5410 /* Similar, except that we check only for this and subsequent inputs
5411 and the address of only subsequent inputs and we do not need
5412 to check for RELOAD_OTHER objects since they are known not to
5415 for (i = opnum; i < reload_n_operands; i++)
5416 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5419 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5420 could be killed if the register is also used by reload with type
5421 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5422 if (type == RELOAD_FOR_INPADDR_ADDRESS
5423 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5426 for (i = opnum + 1; i < reload_n_operands; i++)
5427 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5428 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5431 for (i = 0; i < reload_n_operands; i++)
5432 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5433 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5434 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5437 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5440 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5441 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5442 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5444 case RELOAD_FOR_INPUT:
5445 /* Similar to input address, except we start at the next operand for
5446 both input and input address and we do not check for
5447 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5450 for (i = opnum + 1; i < reload_n_operands; i++)
5451 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5452 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5453 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5456 /* ... fall through ... */
5458 case RELOAD_FOR_OPERAND_ADDRESS:
5459 /* Check outputs and their addresses. */
5461 for (i = 0; i < reload_n_operands; i++)
5462 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5463 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5464 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5467 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5469 case RELOAD_FOR_OPADDR_ADDR:
5470 for (i = 0; i < reload_n_operands; i++)
5471 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5472 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5473 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5476 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5477 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5478 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5480 case RELOAD_FOR_INSN:
5481 /* These conflict with other outputs with RELOAD_OTHER. So
5482 we need only check for output addresses. */
5484 opnum = reload_n_operands;
5486 /* ... fall through ... */
5488 case RELOAD_FOR_OUTPUT:
5489 case RELOAD_FOR_OUTPUT_ADDRESS:
5490 case RELOAD_FOR_OUTADDR_ADDRESS:
5491 /* We already know these can't conflict with a later output. So the
5492 only thing to check are later output addresses.
5493 Note that multiple output operands are emitted in reverse order,
5494 so the conflicting ones are those with lower indices. */
5495 for (i = 0; i < opnum; i++)
5496 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5497 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5500 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5501 could be killed if the register is also used by reload with type
5502 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5503 if (type == RELOAD_FOR_OUTADDR_ADDRESS
5504 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5514 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5515 every register in REG. */
5518 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5522 for (i = REGNO (reg); i < END_REGNO (reg); i++)
5523 if (!reload_reg_reaches_end_p (i, reloadnum))
5529 /* Returns whether R1 and R2 are uniquely chained: the value of one
5530 is used by the other, and that value is not used by any other
5531 reload for this insn. This is used to partially undo the decision
5532 made in find_reloads when in the case of multiple
5533 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5534 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5535 reloads. This code tries to avoid the conflict created by that
5536 change. It might be cleaner to explicitly keep track of which
5537 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5538 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5539 this after the fact. */
5541 reloads_unique_chain_p (int r1, int r2)
5545 /* We only check input reloads. */
5546 if (! rld[r1].in || ! rld[r2].in)
5549 /* Avoid anything with output reloads. */
5550 if (rld[r1].out || rld[r2].out)
5553 /* "chained" means one reload is a component of the other reload,
5554 not the same as the other reload. */
5555 if (rld[r1].opnum != rld[r2].opnum
5556 || rtx_equal_p (rld[r1].in, rld[r2].in)
5557 || rld[r1].optional || rld[r2].optional
5558 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5559 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5562 for (i = 0; i < n_reloads; i ++)
5563 /* Look for input reloads that aren't our two */
5564 if (i != r1 && i != r2 && rld[i].in)
5566 /* If our reload is mentioned at all, it isn't a simple chain. */
5567 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5573 /* The recursive function change all occurrences of WHAT in *WHERE
5576 substitute (rtx *where, const_rtx what, rtx repl)
5585 if (*where == what || rtx_equal_p (*where, what))
5587 /* Record the location of the changed rtx. */
5588 substitute_stack.safe_push (where);
5593 code = GET_CODE (*where);
5594 fmt = GET_RTX_FORMAT (code);
5595 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5601 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5602 substitute (&XVECEXP (*where, i, j), what, repl);
5604 else if (fmt[i] == 'e')
5605 substitute (&XEXP (*where, i), what, repl);
5609 /* The function returns TRUE if chain of reload R1 and R2 (in any
5610 order) can be evaluated without usage of intermediate register for
5611 the reload containing another reload. It is important to see
5612 gen_reload to understand what the function is trying to do. As an
5613 example, let us have reload chain
5616 r1: <something> + const
5618 and reload R2 got reload reg HR. The function returns true if
5619 there is a correct insn HR = HR + <something>. Otherwise,
5620 gen_reload will use intermediate register (and this is the reload
5621 reg for R1) to reload <something>.
5623 We need this function to find a conflict for chain reloads. In our
5624 example, if HR = HR + <something> is incorrect insn, then we cannot
5625 use HR as a reload register for R2. If we do use it then we get a
5634 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5636 /* Assume other cases in gen_reload are not possible for
5637 chain reloads or do need an intermediate hard registers. */
5641 rtx last = get_last_insn ();
5643 /* Make r2 a component of r1. */
5644 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5650 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5651 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5652 gcc_assert (regno >= 0);
5653 out = gen_rtx_REG (rld[r1].mode, regno);
5655 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5657 /* If IN is a paradoxical SUBREG, remove it and try to put the
5658 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5659 strip_paradoxical_subreg (&in, &out);
5661 if (GET_CODE (in) == PLUS
5662 && (REG_P (XEXP (in, 0))
5663 || GET_CODE (XEXP (in, 0)) == SUBREG
5664 || MEM_P (XEXP (in, 0)))
5665 && (REG_P (XEXP (in, 1))
5666 || GET_CODE (XEXP (in, 1)) == SUBREG
5667 || CONSTANT_P (XEXP (in, 1))
5668 || MEM_P (XEXP (in, 1))))
5670 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5671 code = recog_memoized (insn);
5676 extract_insn (insn);
5677 /* We want constrain operands to treat this insn strictly in
5678 its validity determination, i.e., the way it would after
5679 reload has completed. */
5680 result = constrain_operands (1);
5683 delete_insns_since (last);
5686 /* Restore the original value at each changed address within R1. */
5687 while (!substitute_stack.is_empty ())
5689 rtx *where = substitute_stack.pop ();
5690 *where = rld[r2].in;
5696 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5699 This function uses the same algorithm as reload_reg_free_p above. */
5702 reloads_conflict (int r1, int r2)
5704 enum reload_type r1_type = rld[r1].when_needed;
5705 enum reload_type r2_type = rld[r2].when_needed;
5706 int r1_opnum = rld[r1].opnum;
5707 int r2_opnum = rld[r2].opnum;
5709 /* RELOAD_OTHER conflicts with everything. */
5710 if (r2_type == RELOAD_OTHER)
5713 /* Otherwise, check conflicts differently for each type. */
5717 case RELOAD_FOR_INPUT:
5718 return (r2_type == RELOAD_FOR_INSN
5719 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5720 || r2_type == RELOAD_FOR_OPADDR_ADDR
5721 || r2_type == RELOAD_FOR_INPUT
5722 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5723 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5724 && r2_opnum > r1_opnum));
5726 case RELOAD_FOR_INPUT_ADDRESS:
5727 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5728 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5730 case RELOAD_FOR_INPADDR_ADDRESS:
5731 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5732 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5734 case RELOAD_FOR_OUTPUT_ADDRESS:
5735 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5736 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5738 case RELOAD_FOR_OUTADDR_ADDRESS:
5739 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5740 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5742 case RELOAD_FOR_OPERAND_ADDRESS:
5743 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5744 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5745 && (!reloads_unique_chain_p (r1, r2)
5746 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5748 case RELOAD_FOR_OPADDR_ADDR:
5749 return (r2_type == RELOAD_FOR_INPUT
5750 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5752 case RELOAD_FOR_OUTPUT:
5753 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5754 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5755 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5756 && r2_opnum >= r1_opnum));
5758 case RELOAD_FOR_INSN:
5759 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5760 || r2_type == RELOAD_FOR_INSN
5761 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5763 case RELOAD_FOR_OTHER_ADDRESS:
5764 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5774 /* Indexed by reload number, 1 if incoming value
5775 inherited from previous insns. */
5776 static char reload_inherited[MAX_RELOADS];
5778 /* For an inherited reload, this is the insn the reload was inherited from,
5779 if we know it. Otherwise, this is 0. */
5780 static rtx reload_inheritance_insn[MAX_RELOADS];
5782 /* If nonzero, this is a place to get the value of the reload,
5783 rather than using reload_in. */
5784 static rtx reload_override_in[MAX_RELOADS];
5786 /* For each reload, the hard register number of the register used,
5787 or -1 if we did not need a register for this reload. */
5788 static int reload_spill_index[MAX_RELOADS];
5790 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5791 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5793 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5794 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5796 /* Subroutine of free_for_value_p, used to check a single register.
5797 START_REGNO is the starting regno of the full reload register
5798 (possibly comprising multiple hard registers) that we are considering. */
5801 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5802 enum reload_type type, rtx value, rtx out,
5803 int reloadnum, int ignore_address_reloads)
5806 /* Set if we see an input reload that must not share its reload register
5807 with any new earlyclobber, but might otherwise share the reload
5808 register with an output or input-output reload. */
5809 int check_earlyclobber = 0;
5813 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5816 if (out == const0_rtx)
5822 /* We use some pseudo 'time' value to check if the lifetimes of the
5823 new register use would overlap with the one of a previous reload
5824 that is not read-only or uses a different value.
5825 The 'time' used doesn't have to be linear in any shape or form, just
5827 Some reload types use different 'buckets' for each operand.
5828 So there are MAX_RECOG_OPERANDS different time values for each
5830 We compute TIME1 as the time when the register for the prospective
5831 new reload ceases to be live, and TIME2 for each existing
5832 reload as the time when that the reload register of that reload
5834 Where there is little to be gained by exact lifetime calculations,
5835 we just make conservative assumptions, i.e. a longer lifetime;
5836 this is done in the 'default:' cases. */
5839 case RELOAD_FOR_OTHER_ADDRESS:
5840 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5841 time1 = copy ? 0 : 1;
5844 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5846 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5847 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5848 respectively, to the time values for these, we get distinct time
5849 values. To get distinct time values for each operand, we have to
5850 multiply opnum by at least three. We round that up to four because
5851 multiply by four is often cheaper. */
5852 case RELOAD_FOR_INPADDR_ADDRESS:
5853 time1 = opnum * 4 + 2;
5855 case RELOAD_FOR_INPUT_ADDRESS:
5856 time1 = opnum * 4 + 3;
5858 case RELOAD_FOR_INPUT:
5859 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5860 executes (inclusive). */
5861 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5863 case RELOAD_FOR_OPADDR_ADDR:
5865 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5866 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5868 case RELOAD_FOR_OPERAND_ADDRESS:
5869 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5871 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5873 case RELOAD_FOR_OUTADDR_ADDRESS:
5874 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5876 case RELOAD_FOR_OUTPUT_ADDRESS:
5877 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5880 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5883 for (i = 0; i < n_reloads; i++)
5885 rtx reg = rld[i].reg_rtx;
5886 if (reg && REG_P (reg)
5887 && ((unsigned) regno - true_regnum (reg)
5888 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5891 rtx other_input = rld[i].in;
5893 /* If the other reload loads the same input value, that
5894 will not cause a conflict only if it's loading it into
5895 the same register. */
5896 if (true_regnum (reg) != start_regno)
5897 other_input = NULL_RTX;
5898 if (! other_input || ! rtx_equal_p (other_input, value)
5899 || rld[i].out || out)
5902 switch (rld[i].when_needed)
5904 case RELOAD_FOR_OTHER_ADDRESS:
5907 case RELOAD_FOR_INPADDR_ADDRESS:
5908 /* find_reloads makes sure that a
5909 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5910 by at most one - the first -
5911 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5912 address reload is inherited, the address address reload
5913 goes away, so we can ignore this conflict. */
5914 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5915 && ignore_address_reloads
5916 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5917 Then the address address is still needed to store
5918 back the new address. */
5919 && ! rld[reloadnum].out)
5921 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5922 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5924 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5925 && ignore_address_reloads
5926 /* Unless we are reloading an auto_inc expression. */
5927 && ! rld[reloadnum].out)
5929 time2 = rld[i].opnum * 4 + 2;
5931 case RELOAD_FOR_INPUT_ADDRESS:
5932 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5933 && ignore_address_reloads
5934 && ! rld[reloadnum].out)
5936 time2 = rld[i].opnum * 4 + 3;
5938 case RELOAD_FOR_INPUT:
5939 time2 = rld[i].opnum * 4 + 4;
5940 check_earlyclobber = 1;
5942 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5943 == MAX_RECOG_OPERAND * 4 */
5944 case RELOAD_FOR_OPADDR_ADDR:
5945 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5946 && ignore_address_reloads
5947 && ! rld[reloadnum].out)
5949 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5951 case RELOAD_FOR_OPERAND_ADDRESS:
5952 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5953 check_earlyclobber = 1;
5955 case RELOAD_FOR_INSN:
5956 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5958 case RELOAD_FOR_OUTPUT:
5959 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5960 instruction is executed. */
5961 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5963 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5964 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5966 case RELOAD_FOR_OUTADDR_ADDRESS:
5967 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5968 && ignore_address_reloads
5969 && ! rld[reloadnum].out)
5971 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5973 case RELOAD_FOR_OUTPUT_ADDRESS:
5974 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5977 /* If there is no conflict in the input part, handle this
5978 like an output reload. */
5979 if (! rld[i].in || rtx_equal_p (other_input, value))
5981 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5982 /* Earlyclobbered outputs must conflict with inputs. */
5983 if (earlyclobber_operand_p (rld[i].out))
5984 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5989 /* RELOAD_OTHER might be live beyond instruction execution,
5990 but this is not obvious when we set time2 = 1. So check
5991 here if there might be a problem with the new reload
5992 clobbering the register used by the RELOAD_OTHER. */
6000 && (! rld[i].in || rld[i].out
6001 || ! rtx_equal_p (other_input, value)))
6002 || (out && rld[reloadnum].out_reg
6003 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6009 /* Earlyclobbered outputs must conflict with inputs. */
6010 if (check_earlyclobber && out && earlyclobber_operand_p (out))
6016 /* Return 1 if the value in reload reg REGNO, as used by a reload
6017 needed for the part of the insn specified by OPNUM and TYPE,
6018 may be used to load VALUE into it.
6020 MODE is the mode in which the register is used, this is needed to
6021 determine how many hard regs to test.
6023 Other read-only reloads with the same value do not conflict
6024 unless OUT is nonzero and these other reloads have to live while
6025 output reloads live.
6026 If OUT is CONST0_RTX, this is a special case: it means that the
6027 test should not be for using register REGNO as reload register, but
6028 for copying from register REGNO into the reload register.
6030 RELOADNUM is the number of the reload we want to load this value for;
6031 a reload does not conflict with itself.
6033 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6034 reloads that load an address for the very reload we are considering.
6036 The caller has to make sure that there is no conflict with the return
6040 free_for_value_p (int regno, enum machine_mode mode, int opnum,
6041 enum reload_type type, rtx value, rtx out, int reloadnum,
6042 int ignore_address_reloads)
6044 int nregs = hard_regno_nregs[regno][mode];
6046 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6047 value, out, reloadnum,
6048 ignore_address_reloads))
6053 /* Return nonzero if the rtx X is invariant over the current function. */
6054 /* ??? Actually, the places where we use this expect exactly what is
6055 tested here, and not everything that is function invariant. In
6056 particular, the frame pointer and arg pointer are special cased;
6057 pic_offset_table_rtx is not, and we must not spill these things to
6061 function_invariant_p (const_rtx x)
6065 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6067 if (GET_CODE (x) == PLUS
6068 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6069 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6074 /* Determine whether the reload reg X overlaps any rtx'es used for
6075 overriding inheritance. Return nonzero if so. */
6078 conflicts_with_override (rtx x)
6081 for (i = 0; i < n_reloads; i++)
6082 if (reload_override_in[i]
6083 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6088 /* Give an error message saying we failed to find a reload for INSN,
6089 and clear out reload R. */
6091 failed_reload (rtx insn, int r)
6093 if (asm_noperands (PATTERN (insn)) < 0)
6094 /* It's the compiler's fault. */
6095 fatal_insn ("could not find a spill register", insn);
6097 /* It's the user's fault; the operand's mode and constraint
6098 don't match. Disable this reload so we don't crash in final. */
6099 error_for_asm (insn,
6100 "%<asm%> operand constraint incompatible with operand size");
6104 rld[r].optional = 1;
6105 rld[r].secondary_p = 1;
6108 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6109 for reload R. If it's valid, get an rtx for it. Return nonzero if
6112 set_reload_reg (int i, int r)
6114 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6116 int regno ATTRIBUTE_UNUSED;
6117 rtx reg = spill_reg_rtx[i];
6119 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6120 spill_reg_rtx[i] = reg
6121 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6123 regno = true_regnum (reg);
6125 /* Detect when the reload reg can't hold the reload mode.
6126 This used to be one `if', but Sequent compiler can't handle that. */
6127 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6129 enum machine_mode test_mode = VOIDmode;
6131 test_mode = GET_MODE (rld[r].in);
6132 /* If rld[r].in has VOIDmode, it means we will load it
6133 in whatever mode the reload reg has: to wit, rld[r].mode.
6134 We have already tested that for validity. */
6135 /* Aside from that, we need to test that the expressions
6136 to reload from or into have modes which are valid for this
6137 reload register. Otherwise the reload insns would be invalid. */
6138 if (! (rld[r].in != 0 && test_mode != VOIDmode
6139 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6140 if (! (rld[r].out != 0
6141 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6143 /* The reg is OK. */
6146 /* Mark as in use for this insn the reload regs we use
6148 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6149 rld[r].when_needed, rld[r].mode);
6151 rld[r].reg_rtx = reg;
6152 reload_spill_index[r] = spill_regs[i];
6159 /* Find a spill register to use as a reload register for reload R.
6160 LAST_RELOAD is nonzero if this is the last reload for the insn being
6163 Set rld[R].reg_rtx to the register allocated.
6165 We return 1 if successful, or 0 if we couldn't find a spill reg and
6166 we didn't change anything. */
6169 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6174 /* If we put this reload ahead, thinking it is a group,
6175 then insist on finding a group. Otherwise we can grab a
6176 reg that some other reload needs.
6177 (That can happen when we have a 68000 DATA_OR_FP_REG
6178 which is a group of data regs or one fp reg.)
6179 We need not be so restrictive if there are no more reloads
6182 ??? Really it would be nicer to have smarter handling
6183 for that kind of reg class, where a problem like this is normal.
6184 Perhaps those classes should be avoided for reloading
6185 by use of more alternatives. */
6187 int force_group = rld[r].nregs > 1 && ! last_reload;
6189 /* If we want a single register and haven't yet found one,
6190 take any reg in the right class and not in use.
6191 If we want a consecutive group, here is where we look for it.
6193 We use three passes so we can first look for reload regs to
6194 reuse, which are already in use for other reloads in this insn,
6195 and only then use additional registers which are not "bad", then
6196 finally any register.
6198 I think that maximizing reuse is needed to make sure we don't
6199 run out of reload regs. Suppose we have three reloads, and
6200 reloads A and B can share regs. These need two regs.
6201 Suppose A and B are given different regs.
6202 That leaves none for C. */
6203 for (pass = 0; pass < 3; pass++)
6205 /* I is the index in spill_regs.
6206 We advance it round-robin between insns to use all spill regs
6207 equally, so that inherited reloads have a chance
6208 of leapfrogging each other. */
6212 for (count = 0; count < n_spills; count++)
6214 int rclass = (int) rld[r].rclass;
6220 regnum = spill_regs[i];
6222 if ((reload_reg_free_p (regnum, rld[r].opnum,
6225 /* We check reload_reg_used to make sure we
6226 don't clobber the return register. */
6227 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6228 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6229 rld[r].when_needed, rld[r].in,
6231 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6232 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6233 /* Look first for regs to share, then for unshared. But
6234 don't share regs used for inherited reloads; they are
6235 the ones we want to preserve. */
6237 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6239 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6242 int nr = hard_regno_nregs[regnum][rld[r].mode];
6244 /* During the second pass we want to avoid reload registers
6245 which are "bad" for this reload. */
6247 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6250 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6251 (on 68000) got us two FP regs. If NR is 1,
6252 we would reject both of them. */
6255 /* If we need only one reg, we have already won. */
6258 /* But reject a single reg if we demand a group. */
6263 /* Otherwise check that as many consecutive regs as we need
6264 are available here. */
6267 int regno = regnum + nr - 1;
6268 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6269 && spill_reg_order[regno] >= 0
6270 && reload_reg_free_p (regno, rld[r].opnum,
6271 rld[r].when_needed)))
6280 /* If we found something on the current pass, omit later passes. */
6281 if (count < n_spills)
6285 /* We should have found a spill register by now. */
6286 if (count >= n_spills)
6289 /* I is the index in SPILL_REG_RTX of the reload register we are to
6290 allocate. Get an rtx for it and find its register number. */
6292 return set_reload_reg (i, r);
6295 /* Initialize all the tables needed to allocate reload registers.
6296 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6297 is the array we use to restore the reg_rtx field for every reload. */
6300 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6304 for (i = 0; i < n_reloads; i++)
6305 rld[i].reg_rtx = save_reload_reg_rtx[i];
6307 memset (reload_inherited, 0, MAX_RELOADS);
6308 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6309 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6311 CLEAR_HARD_REG_SET (reload_reg_used);
6312 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6313 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6314 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6315 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6316 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6318 CLEAR_HARD_REG_SET (reg_used_in_insn);
6321 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6322 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6323 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6324 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6325 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6326 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6329 for (i = 0; i < reload_n_operands; i++)
6331 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6332 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6333 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6334 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6335 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6336 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6339 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6341 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6343 for (i = 0; i < n_reloads; i++)
6344 /* If we have already decided to use a certain register,
6345 don't use it in another way. */
6347 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6348 rld[i].when_needed, rld[i].mode);
6351 #ifdef SECONDARY_MEMORY_NEEDED
6352 /* If X is not a subreg, return it unmodified. If it is a subreg,
6353 look up whether we made a replacement for the SUBREG_REG. Return
6354 either the replacement or the SUBREG_REG. */
6357 replaced_subreg (rtx x)
6359 if (GET_CODE (x) == SUBREG)
6360 return find_replacement (&SUBREG_REG (x));
6365 /* Assign hard reg targets for the pseudo-registers we must reload
6366 into hard regs for this insn.
6367 Also output the instructions to copy them in and out of the hard regs.
6369 For machines with register classes, we are responsible for
6370 finding a reload reg in the proper class. */
6373 choose_reload_regs (struct insn_chain *chain)
6375 rtx insn = chain->insn;
6377 unsigned int max_group_size = 1;
6378 enum reg_class group_class = NO_REGS;
6379 int pass, win, inheritance;
6381 rtx save_reload_reg_rtx[MAX_RELOADS];
6383 /* In order to be certain of getting the registers we need,
6384 we must sort the reloads into order of increasing register class.
6385 Then our grabbing of reload registers will parallel the process
6386 that provided the reload registers.
6388 Also note whether any of the reloads wants a consecutive group of regs.
6389 If so, record the maximum size of the group desired and what
6390 register class contains all the groups needed by this insn. */
6392 for (j = 0; j < n_reloads; j++)
6394 reload_order[j] = j;
6395 if (rld[j].reg_rtx != NULL_RTX)
6397 gcc_assert (REG_P (rld[j].reg_rtx)
6398 && HARD_REGISTER_P (rld[j].reg_rtx));
6399 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6402 reload_spill_index[j] = -1;
6404 if (rld[j].nregs > 1)
6406 max_group_size = MAX (rld[j].nregs, max_group_size);
6408 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6411 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6415 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6417 /* If -O, try first with inheritance, then turning it off.
6418 If not -O, don't do inheritance.
6419 Using inheritance when not optimizing leads to paradoxes
6420 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6421 because one side of the comparison might be inherited. */
6423 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6425 choose_reload_regs_init (chain, save_reload_reg_rtx);
6427 /* Process the reloads in order of preference just found.
6428 Beyond this point, subregs can be found in reload_reg_rtx.
6430 This used to look for an existing reloaded home for all of the
6431 reloads, and only then perform any new reloads. But that could lose
6432 if the reloads were done out of reg-class order because a later
6433 reload with a looser constraint might have an old home in a register
6434 needed by an earlier reload with a tighter constraint.
6436 To solve this, we make two passes over the reloads, in the order
6437 described above. In the first pass we try to inherit a reload
6438 from a previous insn. If there is a later reload that needs a
6439 class that is a proper subset of the class being processed, we must
6440 also allocate a spill register during the first pass.
6442 Then make a second pass over the reloads to allocate any reloads
6443 that haven't been given registers yet. */
6445 for (j = 0; j < n_reloads; j++)
6447 int r = reload_order[j];
6448 rtx search_equiv = NULL_RTX;
6450 /* Ignore reloads that got marked inoperative. */
6451 if (rld[r].out == 0 && rld[r].in == 0
6452 && ! rld[r].secondary_p)
6455 /* If find_reloads chose to use reload_in or reload_out as a reload
6456 register, we don't need to chose one. Otherwise, try even if it
6457 found one since we might save an insn if we find the value lying
6459 Try also when reload_in is a pseudo without a hard reg. */
6460 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6461 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6462 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6463 && !MEM_P (rld[r].in)
6464 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6467 #if 0 /* No longer needed for correct operation.
6468 It might give better code, or might not; worth an experiment? */
6469 /* If this is an optional reload, we can't inherit from earlier insns
6470 until we are sure that any non-optional reloads have been allocated.
6471 The following code takes advantage of the fact that optional reloads
6472 are at the end of reload_order. */
6473 if (rld[r].optional != 0)
6474 for (i = 0; i < j; i++)
6475 if ((rld[reload_order[i]].out != 0
6476 || rld[reload_order[i]].in != 0
6477 || rld[reload_order[i]].secondary_p)
6478 && ! rld[reload_order[i]].optional
6479 && rld[reload_order[i]].reg_rtx == 0)
6480 allocate_reload_reg (chain, reload_order[i], 0);
6483 /* First see if this pseudo is already available as reloaded
6484 for a previous insn. We cannot try to inherit for reloads
6485 that are smaller than the maximum number of registers needed
6486 for groups unless the register we would allocate cannot be used
6489 We could check here to see if this is a secondary reload for
6490 an object that is already in a register of the desired class.
6491 This would avoid the need for the secondary reload register.
6492 But this is complex because we can't easily determine what
6493 objects might want to be loaded via this reload. So let a
6494 register be allocated here. In `emit_reload_insns' we suppress
6495 one of the loads in the case described above. */
6501 enum machine_mode mode = VOIDmode;
6505 else if (REG_P (rld[r].in))
6507 regno = REGNO (rld[r].in);
6508 mode = GET_MODE (rld[r].in);
6510 else if (REG_P (rld[r].in_reg))
6512 regno = REGNO (rld[r].in_reg);
6513 mode = GET_MODE (rld[r].in_reg);
6515 else if (GET_CODE (rld[r].in_reg) == SUBREG
6516 && REG_P (SUBREG_REG (rld[r].in_reg)))
6518 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6519 if (regno < FIRST_PSEUDO_REGISTER)
6520 regno = subreg_regno (rld[r].in_reg);
6522 byte = SUBREG_BYTE (rld[r].in_reg);
6523 mode = GET_MODE (rld[r].in_reg);
6526 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6527 && REG_P (XEXP (rld[r].in_reg, 0)))
6529 regno = REGNO (XEXP (rld[r].in_reg, 0));
6530 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6531 rld[r].out = rld[r].in;
6535 /* This won't work, since REGNO can be a pseudo reg number.
6536 Also, it takes much more hair to keep track of all the things
6537 that can invalidate an inherited reload of part of a pseudoreg. */
6538 else if (GET_CODE (rld[r].in) == SUBREG
6539 && REG_P (SUBREG_REG (rld[r].in)))
6540 regno = subreg_regno (rld[r].in);
6544 && reg_last_reload_reg[regno] != 0
6545 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6546 >= GET_MODE_SIZE (mode) + byte)
6547 #ifdef CANNOT_CHANGE_MODE_CLASS
6548 /* Verify that the register it's in can be used in
6550 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6551 GET_MODE (reg_last_reload_reg[regno]),
6556 enum reg_class rclass = rld[r].rclass, last_class;
6557 rtx last_reg = reg_last_reload_reg[regno];
6559 i = REGNO (last_reg);
6560 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6561 last_class = REGNO_REG_CLASS (i);
6563 if (reg_reloaded_contents[i] == regno
6564 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6565 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6566 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6567 /* Even if we can't use this register as a reload
6568 register, we might use it for reload_override_in,
6569 if copying it to the desired class is cheap
6571 || ((register_move_cost (mode, last_class, rclass)
6572 < memory_move_cost (mode, rclass, true))
6573 && (secondary_reload_class (1, rclass, mode,
6576 #ifdef SECONDARY_MEMORY_NEEDED
6577 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6582 && (rld[r].nregs == max_group_size
6583 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6585 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6586 rld[r].when_needed, rld[r].in,
6589 /* If a group is needed, verify that all the subsequent
6590 registers still have their values intact. */
6591 int nr = hard_regno_nregs[i][rld[r].mode];
6594 for (k = 1; k < nr; k++)
6595 if (reg_reloaded_contents[i + k] != regno
6596 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6604 last_reg = (GET_MODE (last_reg) == mode
6605 ? last_reg : gen_rtx_REG (mode, i));
6608 for (k = 0; k < nr; k++)
6609 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6612 /* We found a register that contains the
6613 value we need. If this register is the
6614 same as an `earlyclobber' operand of the
6615 current insn, just mark it as a place to
6616 reload from since we can't use it as the
6617 reload register itself. */
6619 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6620 if (reg_overlap_mentioned_for_reload_p
6621 (reg_last_reload_reg[regno],
6622 reload_earlyclobbers[i1]))
6625 if (i1 != n_earlyclobbers
6626 || ! (free_for_value_p (i, rld[r].mode,
6628 rld[r].when_needed, rld[r].in,
6630 /* Don't use it if we'd clobber a pseudo reg. */
6631 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6633 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6634 /* Don't clobber the frame pointer. */
6635 || (i == HARD_FRAME_POINTER_REGNUM
6636 && frame_pointer_needed
6638 /* Don't really use the inherited spill reg
6639 if we need it wider than we've got it. */
6640 || (GET_MODE_SIZE (rld[r].mode)
6641 > GET_MODE_SIZE (mode))
6644 /* If find_reloads chose reload_out as reload
6645 register, stay with it - that leaves the
6646 inherited register for subsequent reloads. */
6647 || (rld[r].out && rld[r].reg_rtx
6648 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6650 if (! rld[r].optional)
6652 reload_override_in[r] = last_reg;
6653 reload_inheritance_insn[r]
6654 = reg_reloaded_insn[i];
6660 /* We can use this as a reload reg. */
6661 /* Mark the register as in use for this part of
6663 mark_reload_reg_in_use (i,
6667 rld[r].reg_rtx = last_reg;
6668 reload_inherited[r] = 1;
6669 reload_inheritance_insn[r]
6670 = reg_reloaded_insn[i];
6671 reload_spill_index[r] = i;
6672 for (k = 0; k < nr; k++)
6673 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6681 /* Here's another way to see if the value is already lying around. */
6684 && ! reload_inherited[r]
6686 && (CONSTANT_P (rld[r].in)
6687 || GET_CODE (rld[r].in) == PLUS
6688 || REG_P (rld[r].in)
6689 || MEM_P (rld[r].in))
6690 && (rld[r].nregs == max_group_size
6691 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6692 search_equiv = rld[r].in;
6697 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6698 -1, NULL, 0, rld[r].mode);
6704 regno = REGNO (equiv);
6707 /* This must be a SUBREG of a hard register.
6708 Make a new REG since this might be used in an
6709 address and not all machines support SUBREGs
6711 gcc_assert (GET_CODE (equiv) == SUBREG);
6712 regno = subreg_regno (equiv);
6713 equiv = gen_rtx_REG (rld[r].mode, regno);
6714 /* If we choose EQUIV as the reload register, but the
6715 loop below decides to cancel the inheritance, we'll
6716 end up reloading EQUIV in rld[r].mode, not the mode
6717 it had originally. That isn't safe when EQUIV isn't
6718 available as a spill register since its value might
6719 still be live at this point. */
6720 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6721 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6726 /* If we found a spill reg, reject it unless it is free
6727 and of the desired class. */
6731 int bad_for_class = 0;
6732 int max_regno = regno + rld[r].nregs;
6734 for (i = regno; i < max_regno; i++)
6736 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6738 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6743 && ! free_for_value_p (regno, rld[r].mode,
6744 rld[r].opnum, rld[r].when_needed,
6745 rld[r].in, rld[r].out, r, 1))
6750 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6753 /* We found a register that contains the value we need.
6754 If this register is the same as an `earlyclobber' operand
6755 of the current insn, just mark it as a place to reload from
6756 since we can't use it as the reload register itself. */
6759 for (i = 0; i < n_earlyclobbers; i++)
6760 if (reg_overlap_mentioned_for_reload_p (equiv,
6761 reload_earlyclobbers[i]))
6763 if (! rld[r].optional)
6764 reload_override_in[r] = equiv;
6769 /* If the equiv register we have found is explicitly clobbered
6770 in the current insn, it depends on the reload type if we
6771 can use it, use it for reload_override_in, or not at all.
6772 In particular, we then can't use EQUIV for a
6773 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6777 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6778 switch (rld[r].when_needed)
6780 case RELOAD_FOR_OTHER_ADDRESS:
6781 case RELOAD_FOR_INPADDR_ADDRESS:
6782 case RELOAD_FOR_INPUT_ADDRESS:
6783 case RELOAD_FOR_OPADDR_ADDR:
6786 case RELOAD_FOR_INPUT:
6787 case RELOAD_FOR_OPERAND_ADDRESS:
6788 if (! rld[r].optional)
6789 reload_override_in[r] = equiv;
6795 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6796 switch (rld[r].when_needed)
6798 case RELOAD_FOR_OTHER_ADDRESS:
6799 case RELOAD_FOR_INPADDR_ADDRESS:
6800 case RELOAD_FOR_INPUT_ADDRESS:
6801 case RELOAD_FOR_OPADDR_ADDR:
6802 case RELOAD_FOR_OPERAND_ADDRESS:
6803 case RELOAD_FOR_INPUT:
6806 if (! rld[r].optional)
6807 reload_override_in[r] = equiv;
6815 /* If we found an equivalent reg, say no code need be generated
6816 to load it, and use it as our reload reg. */
6818 && (regno != HARD_FRAME_POINTER_REGNUM
6819 || !frame_pointer_needed))
6821 int nr = hard_regno_nregs[regno][rld[r].mode];
6823 rld[r].reg_rtx = equiv;
6824 reload_spill_index[r] = regno;
6825 reload_inherited[r] = 1;
6827 /* If reg_reloaded_valid is not set for this register,
6828 there might be a stale spill_reg_store lying around.
6829 We must clear it, since otherwise emit_reload_insns
6830 might delete the store. */
6831 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6832 spill_reg_store[regno] = NULL_RTX;
6833 /* If any of the hard registers in EQUIV are spill
6834 registers, mark them as in use for this insn. */
6835 for (k = 0; k < nr; k++)
6837 i = spill_reg_order[regno + k];
6840 mark_reload_reg_in_use (regno, rld[r].opnum,
6843 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6850 /* If we found a register to use already, or if this is an optional
6851 reload, we are done. */
6852 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6856 /* No longer needed for correct operation. Might or might
6857 not give better code on the average. Want to experiment? */
6859 /* See if there is a later reload that has a class different from our
6860 class that intersects our class or that requires less register
6861 than our reload. If so, we must allocate a register to this
6862 reload now, since that reload might inherit a previous reload
6863 and take the only available register in our class. Don't do this
6864 for optional reloads since they will force all previous reloads
6865 to be allocated. Also don't do this for reloads that have been
6868 for (i = j + 1; i < n_reloads; i++)
6870 int s = reload_order[i];
6872 if ((rld[s].in == 0 && rld[s].out == 0
6873 && ! rld[s].secondary_p)
6877 if ((rld[s].rclass != rld[r].rclass
6878 && reg_classes_intersect_p (rld[r].rclass,
6880 || rld[s].nregs < rld[r].nregs)
6887 allocate_reload_reg (chain, r, j == n_reloads - 1);
6891 /* Now allocate reload registers for anything non-optional that
6892 didn't get one yet. */
6893 for (j = 0; j < n_reloads; j++)
6895 int r = reload_order[j];
6897 /* Ignore reloads that got marked inoperative. */
6898 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6901 /* Skip reloads that already have a register allocated or are
6903 if (rld[r].reg_rtx != 0 || rld[r].optional)
6906 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6910 /* If that loop got all the way, we have won. */
6917 /* Loop around and try without any inheritance. */
6922 /* First undo everything done by the failed attempt
6923 to allocate with inheritance. */
6924 choose_reload_regs_init (chain, save_reload_reg_rtx);
6926 /* Some sanity tests to verify that the reloads found in the first
6927 pass are identical to the ones we have now. */
6928 gcc_assert (chain->n_reloads == n_reloads);
6930 for (i = 0; i < n_reloads; i++)
6932 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6934 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6935 for (j = 0; j < n_spills; j++)
6936 if (spill_regs[j] == chain->rld[i].regno)
6937 if (! set_reload_reg (j, i))
6938 failed_reload (chain->insn, i);
6942 /* If we thought we could inherit a reload, because it seemed that
6943 nothing else wanted the same reload register earlier in the insn,
6944 verify that assumption, now that all reloads have been assigned.
6945 Likewise for reloads where reload_override_in has been set. */
6947 /* If doing expensive optimizations, do one preliminary pass that doesn't
6948 cancel any inheritance, but removes reloads that have been needed only
6949 for reloads that we know can be inherited. */
6950 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6952 for (j = 0; j < n_reloads; j++)
6954 int r = reload_order[j];
6956 #ifdef SECONDARY_MEMORY_NEEDED
6959 if (reload_inherited[r] && rld[r].reg_rtx)
6960 check_reg = rld[r].reg_rtx;
6961 else if (reload_override_in[r]
6962 && (REG_P (reload_override_in[r])
6963 || GET_CODE (reload_override_in[r]) == SUBREG))
6964 check_reg = reload_override_in[r];
6967 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6968 rld[r].opnum, rld[r].when_needed, rld[r].in,
6969 (reload_inherited[r]
6970 ? rld[r].out : const0_rtx),
6975 reload_inherited[r] = 0;
6976 reload_override_in[r] = 0;
6978 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6979 reload_override_in, then we do not need its related
6980 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6981 likewise for other reload types.
6982 We handle this by removing a reload when its only replacement
6983 is mentioned in reload_in of the reload we are going to inherit.
6984 A special case are auto_inc expressions; even if the input is
6985 inherited, we still need the address for the output. We can
6986 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6987 If we succeeded removing some reload and we are doing a preliminary
6988 pass just to remove such reloads, make another pass, since the
6989 removal of one reload might allow us to inherit another one. */
6991 && rld[r].out != rld[r].in
6992 && remove_address_replacements (rld[r].in))
6997 #ifdef SECONDARY_MEMORY_NEEDED
6998 /* If we needed a memory location for the reload, we also have to
6999 remove its related reloads. */
7001 && rld[r].out != rld[r].in
7002 && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7003 && REGNO (tem) < FIRST_PSEUDO_REGISTER
7004 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem)),
7005 rld[r].rclass, rld[r].inmode)
7006 && remove_address_replacements
7007 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7008 rld[r].when_needed)))
7017 /* Now that reload_override_in is known valid,
7018 actually override reload_in. */
7019 for (j = 0; j < n_reloads; j++)
7020 if (reload_override_in[j])
7021 rld[j].in = reload_override_in[j];
7023 /* If this reload won't be done because it has been canceled or is
7024 optional and not inherited, clear reload_reg_rtx so other
7025 routines (such as subst_reloads) don't get confused. */
7026 for (j = 0; j < n_reloads; j++)
7027 if (rld[j].reg_rtx != 0
7028 && ((rld[j].optional && ! reload_inherited[j])
7029 || (rld[j].in == 0 && rld[j].out == 0
7030 && ! rld[j].secondary_p)))
7032 int regno = true_regnum (rld[j].reg_rtx);
7034 if (spill_reg_order[regno] >= 0)
7035 clear_reload_reg_in_use (regno, rld[j].opnum,
7036 rld[j].when_needed, rld[j].mode);
7038 reload_spill_index[j] = -1;
7041 /* Record which pseudos and which spill regs have output reloads. */
7042 for (j = 0; j < n_reloads; j++)
7044 int r = reload_order[j];
7046 i = reload_spill_index[r];
7048 /* I is nonneg if this reload uses a register.
7049 If rld[r].reg_rtx is 0, this is an optional reload
7050 that we opted to ignore. */
7051 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7052 && rld[r].reg_rtx != 0)
7054 int nregno = REGNO (rld[r].out_reg);
7057 if (nregno < FIRST_PSEUDO_REGISTER)
7058 nr = hard_regno_nregs[nregno][rld[r].mode];
7061 SET_REGNO_REG_SET (®_has_output_reload,
7065 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7067 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7068 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7069 || rld[r].when_needed == RELOAD_FOR_INSN);
7074 /* Deallocate the reload register for reload R. This is called from
7075 remove_address_replacements. */
7078 deallocate_reload_reg (int r)
7082 if (! rld[r].reg_rtx)
7084 regno = true_regnum (rld[r].reg_rtx);
7086 if (spill_reg_order[regno] >= 0)
7087 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7089 reload_spill_index[r] = -1;
7092 /* These arrays are filled by emit_reload_insns and its subroutines. */
7093 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7094 static rtx other_input_address_reload_insns = 0;
7095 static rtx other_input_reload_insns = 0;
7096 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7097 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7098 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7099 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7100 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7101 static rtx operand_reload_insns = 0;
7102 static rtx other_operand_reload_insns = 0;
7103 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7105 /* Values to be put in spill_reg_store are put here first. Instructions
7106 must only be placed here if the associated reload register reaches
7107 the end of the instruction's reload sequence. */
7108 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7109 static HARD_REG_SET reg_reloaded_died;
7111 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7112 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7113 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7114 adjusted register, and return true. Otherwise, return false. */
7116 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7117 enum reg_class new_class,
7118 enum machine_mode new_mode)
7123 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7125 unsigned regno = REGNO (reg);
7127 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7129 if (GET_MODE (reg) != new_mode)
7131 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7133 if (hard_regno_nregs[regno][new_mode]
7134 > hard_regno_nregs[regno][GET_MODE (reg)])
7136 reg = reload_adjust_reg_for_mode (reg, new_mode);
7144 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7145 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7146 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7147 adjusted register, and return true. Otherwise, return false. */
7149 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7150 enum insn_code icode)
7153 enum reg_class new_class = scratch_reload_class (icode);
7154 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7156 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7157 new_class, new_mode);
7160 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7161 has the number J. OLD contains the value to be used as input. */
7164 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7167 rtx insn = chain->insn;
7169 rtx oldequiv_reg = 0;
7172 enum machine_mode mode;
7175 /* delete_output_reload is only invoked properly if old contains
7176 the original pseudo register. Since this is replaced with a
7177 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7178 find the pseudo in RELOAD_IN_REG. */
7179 if (reload_override_in[j]
7180 && REG_P (rl->in_reg))
7187 else if (REG_P (oldequiv))
7188 oldequiv_reg = oldequiv;
7189 else if (GET_CODE (oldequiv) == SUBREG)
7190 oldequiv_reg = SUBREG_REG (oldequiv);
7192 reloadreg = reload_reg_rtx_for_input[j];
7193 mode = GET_MODE (reloadreg);
7195 /* If we are reloading from a register that was recently stored in
7196 with an output-reload, see if we can prove there was
7197 actually no need to store the old value in it. */
7199 if (optimize && REG_P (oldequiv)
7200 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7201 && spill_reg_store[REGNO (oldequiv)]
7203 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7204 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7206 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7208 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7211 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7212 oldequiv = SUBREG_REG (oldequiv);
7213 if (GET_MODE (oldequiv) != VOIDmode
7214 && mode != GET_MODE (oldequiv))
7215 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7217 /* Switch to the right place to emit the reload insns. */
7218 switch (rl->when_needed)
7221 where = &other_input_reload_insns;
7223 case RELOAD_FOR_INPUT:
7224 where = &input_reload_insns[rl->opnum];
7226 case RELOAD_FOR_INPUT_ADDRESS:
7227 where = &input_address_reload_insns[rl->opnum];
7229 case RELOAD_FOR_INPADDR_ADDRESS:
7230 where = &inpaddr_address_reload_insns[rl->opnum];
7232 case RELOAD_FOR_OUTPUT_ADDRESS:
7233 where = &output_address_reload_insns[rl->opnum];
7235 case RELOAD_FOR_OUTADDR_ADDRESS:
7236 where = &outaddr_address_reload_insns[rl->opnum];
7238 case RELOAD_FOR_OPERAND_ADDRESS:
7239 where = &operand_reload_insns;
7241 case RELOAD_FOR_OPADDR_ADDR:
7242 where = &other_operand_reload_insns;
7244 case RELOAD_FOR_OTHER_ADDRESS:
7245 where = &other_input_address_reload_insns;
7251 push_to_sequence (*where);
7253 /* Auto-increment addresses must be reloaded in a special way. */
7254 if (rl->out && ! rl->out_reg)
7256 /* We are not going to bother supporting the case where a
7257 incremented register can't be copied directly from
7258 OLDEQUIV since this seems highly unlikely. */
7259 gcc_assert (rl->secondary_in_reload < 0);
7261 if (reload_inherited[j])
7262 oldequiv = reloadreg;
7264 old = XEXP (rl->in_reg, 0);
7266 /* Prevent normal processing of this reload. */
7268 /* Output a special code sequence for this case. */
7269 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7272 /* If we are reloading a pseudo-register that was set by the previous
7273 insn, see if we can get rid of that pseudo-register entirely
7274 by redirecting the previous insn into our reload register. */
7276 else if (optimize && REG_P (old)
7277 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7278 && dead_or_set_p (insn, old)
7279 /* This is unsafe if some other reload
7280 uses the same reg first. */
7281 && ! conflicts_with_override (reloadreg)
7282 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7283 rl->when_needed, old, rl->out, j, 0))
7285 rtx temp = PREV_INSN (insn);
7286 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7287 temp = PREV_INSN (temp);
7289 && NONJUMP_INSN_P (temp)
7290 && GET_CODE (PATTERN (temp)) == SET
7291 && SET_DEST (PATTERN (temp)) == old
7292 /* Make sure we can access insn_operand_constraint. */
7293 && asm_noperands (PATTERN (temp)) < 0
7294 /* This is unsafe if operand occurs more than once in current
7295 insn. Perhaps some occurrences aren't reloaded. */
7296 && count_occurrences (PATTERN (insn), old, 0) == 1)
7298 rtx old = SET_DEST (PATTERN (temp));
7299 /* Store into the reload register instead of the pseudo. */
7300 SET_DEST (PATTERN (temp)) = reloadreg;
7302 /* Verify that resulting insn is valid. */
7303 extract_insn (temp);
7304 if (constrain_operands (1))
7306 /* If the previous insn is an output reload, the source is
7307 a reload register, and its spill_reg_store entry will
7308 contain the previous destination. This is now
7310 if (REG_P (SET_SRC (PATTERN (temp)))
7311 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7313 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7314 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7317 /* If these are the only uses of the pseudo reg,
7318 pretend for GDB it lives in the reload reg we used. */
7319 if (REG_N_DEATHS (REGNO (old)) == 1
7320 && REG_N_SETS (REGNO (old)) == 1)
7322 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7323 if (ira_conflicts_p)
7324 /* Inform IRA about the change. */
7325 ira_mark_allocation_change (REGNO (old));
7326 alter_reg (REGNO (old), -1, false);
7330 /* Adjust any debug insns between temp and insn. */
7331 while ((temp = NEXT_INSN (temp)) != insn)
7332 if (DEBUG_INSN_P (temp))
7333 replace_rtx (PATTERN (temp), old, reloadreg);
7335 gcc_assert (NOTE_P (temp));
7339 SET_DEST (PATTERN (temp)) = old;
7344 /* We can't do that, so output an insn to load RELOADREG. */
7346 /* If we have a secondary reload, pick up the secondary register
7347 and icode, if any. If OLDEQUIV and OLD are different or
7348 if this is an in-out reload, recompute whether or not we
7349 still need a secondary register and what the icode should
7350 be. If we still need a secondary register and the class or
7351 icode is different, go back to reloading from OLD if using
7352 OLDEQUIV means that we got the wrong type of register. We
7353 cannot have different class or icode due to an in-out reload
7354 because we don't make such reloads when both the input and
7355 output need secondary reload registers. */
7357 if (! special && rl->secondary_in_reload >= 0)
7359 rtx second_reload_reg = 0;
7360 rtx third_reload_reg = 0;
7361 int secondary_reload = rl->secondary_in_reload;
7362 rtx real_oldequiv = oldequiv;
7365 enum insn_code icode;
7366 enum insn_code tertiary_icode = CODE_FOR_nothing;
7368 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7369 and similarly for OLD.
7370 See comments in get_secondary_reload in reload.c. */
7371 /* If it is a pseudo that cannot be replaced with its
7372 equivalent MEM, we must fall back to reload_in, which
7373 will have all the necessary substitutions registered.
7374 Likewise for a pseudo that can't be replaced with its
7375 equivalent constant.
7377 Take extra care for subregs of such pseudos. Note that
7378 we cannot use reg_equiv_mem in this case because it is
7379 not in the right mode. */
7382 if (GET_CODE (tmp) == SUBREG)
7383 tmp = SUBREG_REG (tmp);
7385 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7386 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7387 || reg_equiv_constant (REGNO (tmp)) != 0))
7389 if (! reg_equiv_mem (REGNO (tmp))
7390 || num_not_at_initial_offset
7391 || GET_CODE (oldequiv) == SUBREG)
7392 real_oldequiv = rl->in;
7394 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7398 if (GET_CODE (tmp) == SUBREG)
7399 tmp = SUBREG_REG (tmp);
7401 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7402 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7403 || reg_equiv_constant (REGNO (tmp)) != 0))
7405 if (! reg_equiv_mem (REGNO (tmp))
7406 || num_not_at_initial_offset
7407 || GET_CODE (old) == SUBREG)
7410 real_old = reg_equiv_mem (REGNO (tmp));
7413 second_reload_reg = rld[secondary_reload].reg_rtx;
7414 if (rld[secondary_reload].secondary_in_reload >= 0)
7416 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7418 third_reload_reg = rld[tertiary_reload].reg_rtx;
7419 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7420 /* We'd have to add more code for quartary reloads. */
7421 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7423 icode = rl->secondary_in_icode;
7425 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7426 || (rl->in != 0 && rl->out != 0))
7428 secondary_reload_info sri, sri2;
7429 enum reg_class new_class, new_t_class;
7431 sri.icode = CODE_FOR_nothing;
7432 sri.prev_sri = NULL;
7434 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7438 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7439 second_reload_reg = 0;
7440 else if (new_class == NO_REGS)
7442 if (reload_adjust_reg_for_icode (&second_reload_reg,
7444 (enum insn_code) sri.icode))
7446 icode = (enum insn_code) sri.icode;
7447 third_reload_reg = 0;
7452 real_oldequiv = real_old;
7455 else if (sri.icode != CODE_FOR_nothing)
7456 /* We currently lack a way to express this in reloads. */
7460 sri2.icode = CODE_FOR_nothing;
7461 sri2.prev_sri = &sri;
7463 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7466 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7468 if (reload_adjust_reg_for_temp (&second_reload_reg,
7472 third_reload_reg = 0;
7473 tertiary_icode = (enum insn_code) sri2.icode;
7478 real_oldequiv = real_old;
7481 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7483 rtx intermediate = second_reload_reg;
7485 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7487 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7491 second_reload_reg = intermediate;
7492 tertiary_icode = (enum insn_code) sri2.icode;
7497 real_oldequiv = real_old;
7500 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7502 rtx intermediate = second_reload_reg;
7504 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7506 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7509 second_reload_reg = intermediate;
7510 tertiary_icode = (enum insn_code) sri2.icode;
7515 real_oldequiv = real_old;
7520 /* This could be handled more intelligently too. */
7522 real_oldequiv = real_old;
7527 /* If we still need a secondary reload register, check
7528 to see if it is being used as a scratch or intermediate
7529 register and generate code appropriately. If we need
7530 a scratch register, use REAL_OLDEQUIV since the form of
7531 the insn may depend on the actual address if it is
7534 if (second_reload_reg)
7536 if (icode != CODE_FOR_nothing)
7538 /* We'd have to add extra code to handle this case. */
7539 gcc_assert (!third_reload_reg);
7541 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7542 second_reload_reg));
7547 /* See if we need a scratch register to load the
7548 intermediate register (a tertiary reload). */
7549 if (tertiary_icode != CODE_FOR_nothing)
7551 emit_insn ((GEN_FCN (tertiary_icode)
7552 (second_reload_reg, real_oldequiv,
7553 third_reload_reg)));
7555 else if (third_reload_reg)
7557 gen_reload (third_reload_reg, real_oldequiv,
7560 gen_reload (second_reload_reg, third_reload_reg,
7565 gen_reload (second_reload_reg, real_oldequiv,
7569 oldequiv = second_reload_reg;
7574 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7576 rtx real_oldequiv = oldequiv;
7578 if ((REG_P (oldequiv)
7579 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7580 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7581 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7582 || (GET_CODE (oldequiv) == SUBREG
7583 && REG_P (SUBREG_REG (oldequiv))
7584 && (REGNO (SUBREG_REG (oldequiv))
7585 >= FIRST_PSEUDO_REGISTER)
7586 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7587 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7588 || (CONSTANT_P (oldequiv)
7589 && (targetm.preferred_reload_class (oldequiv,
7590 REGNO_REG_CLASS (REGNO (reloadreg)))
7592 real_oldequiv = rl->in;
7593 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7597 if (cfun->can_throw_non_call_exceptions)
7598 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7600 /* End this sequence. */
7601 *where = get_insns ();
7604 /* Update reload_override_in so that delete_address_reloads_1
7605 can see the actual register usage. */
7607 reload_override_in[j] = oldequiv;
7610 /* Generate insns to for the output reload RL, which is for the insn described
7611 by CHAIN and has the number J. */
7613 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7617 rtx insn = chain->insn;
7620 enum machine_mode mode;
7624 if (rl->when_needed == RELOAD_OTHER)
7627 push_to_sequence (output_reload_insns[rl->opnum]);
7629 rl_reg_rtx = reload_reg_rtx_for_output[j];
7630 mode = GET_MODE (rl_reg_rtx);
7632 reloadreg = rl_reg_rtx;
7634 /* If we need two reload regs, set RELOADREG to the intermediate
7635 one, since it will be stored into OLD. We might need a secondary
7636 register only for an input reload, so check again here. */
7638 if (rl->secondary_out_reload >= 0)
7641 int secondary_reload = rl->secondary_out_reload;
7642 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7644 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7645 && reg_equiv_mem (REGNO (old)) != 0)
7646 real_old = reg_equiv_mem (REGNO (old));
7648 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7650 rtx second_reloadreg = reloadreg;
7651 reloadreg = rld[secondary_reload].reg_rtx;
7653 /* See if RELOADREG is to be used as a scratch register
7654 or as an intermediate register. */
7655 if (rl->secondary_out_icode != CODE_FOR_nothing)
7657 /* We'd have to add extra code to handle this case. */
7658 gcc_assert (tertiary_reload < 0);
7660 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7661 (real_old, second_reloadreg, reloadreg)));
7666 /* See if we need both a scratch and intermediate reload
7669 enum insn_code tertiary_icode
7670 = rld[secondary_reload].secondary_out_icode;
7672 /* We'd have to add more code for quartary reloads. */
7673 gcc_assert (tertiary_reload < 0
7674 || rld[tertiary_reload].secondary_out_reload < 0);
7676 if (GET_MODE (reloadreg) != mode)
7677 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7679 if (tertiary_icode != CODE_FOR_nothing)
7681 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7683 /* Copy primary reload reg to secondary reload reg.
7684 (Note that these have been swapped above, then
7685 secondary reload reg to OLD using our insn.) */
7687 /* If REAL_OLD is a paradoxical SUBREG, remove it
7688 and try to put the opposite SUBREG on
7690 strip_paradoxical_subreg (&real_old, &reloadreg);
7692 gen_reload (reloadreg, second_reloadreg,
7693 rl->opnum, rl->when_needed);
7694 emit_insn ((GEN_FCN (tertiary_icode)
7695 (real_old, reloadreg, third_reloadreg)));
7701 /* Copy between the reload regs here and then to
7704 gen_reload (reloadreg, second_reloadreg,
7705 rl->opnum, rl->when_needed);
7706 if (tertiary_reload >= 0)
7708 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7710 gen_reload (third_reloadreg, reloadreg,
7711 rl->opnum, rl->when_needed);
7712 reloadreg = third_reloadreg;
7719 /* Output the last reload insn. */
7724 /* Don't output the last reload if OLD is not the dest of
7725 INSN and is in the src and is clobbered by INSN. */
7726 if (! flag_expensive_optimizations
7728 || !(set = single_set (insn))
7729 || rtx_equal_p (old, SET_DEST (set))
7730 || !reg_mentioned_p (old, SET_SRC (set))
7731 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7732 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7733 gen_reload (old, reloadreg, rl->opnum,
7737 /* Look at all insns we emitted, just to be safe. */
7738 for (p = get_insns (); p; p = NEXT_INSN (p))
7741 rtx pat = PATTERN (p);
7743 /* If this output reload doesn't come from a spill reg,
7744 clear any memory of reloaded copies of the pseudo reg.
7745 If this output reload comes from a spill reg,
7746 reg_has_output_reload will make this do nothing. */
7747 note_stores (pat, forget_old_reloads_1, NULL);
7749 if (reg_mentioned_p (rl_reg_rtx, pat))
7751 rtx set = single_set (insn);
7752 if (reload_spill_index[j] < 0
7754 && SET_SRC (set) == rl_reg_rtx)
7756 int src = REGNO (SET_SRC (set));
7758 reload_spill_index[j] = src;
7759 SET_HARD_REG_BIT (reg_is_output_reload, src);
7760 if (find_regno_note (insn, REG_DEAD, src))
7761 SET_HARD_REG_BIT (reg_reloaded_died, src);
7763 if (HARD_REGISTER_P (rl_reg_rtx))
7765 int s = rl->secondary_out_reload;
7766 set = single_set (p);
7767 /* If this reload copies only to the secondary reload
7768 register, the secondary reload does the actual
7770 if (s >= 0 && set == NULL_RTX)
7771 /* We can't tell what function the secondary reload
7772 has and where the actual store to the pseudo is
7773 made; leave new_spill_reg_store alone. */
7776 && SET_SRC (set) == rl_reg_rtx
7777 && SET_DEST (set) == rld[s].reg_rtx)
7779 /* Usually the next instruction will be the
7780 secondary reload insn; if we can confirm
7781 that it is, setting new_spill_reg_store to
7782 that insn will allow an extra optimization. */
7783 rtx s_reg = rld[s].reg_rtx;
7784 rtx next = NEXT_INSN (p);
7785 rld[s].out = rl->out;
7786 rld[s].out_reg = rl->out_reg;
7787 set = single_set (next);
7788 if (set && SET_SRC (set) == s_reg
7789 && reload_reg_rtx_reaches_end_p (s_reg, s))
7791 SET_HARD_REG_BIT (reg_is_output_reload,
7793 new_spill_reg_store[REGNO (s_reg)] = next;
7796 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7797 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7802 if (rl->when_needed == RELOAD_OTHER)
7804 emit_insn (other_output_reload_insns[rl->opnum]);
7805 other_output_reload_insns[rl->opnum] = get_insns ();
7808 output_reload_insns[rl->opnum] = get_insns ();
7810 if (cfun->can_throw_non_call_exceptions)
7811 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7816 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7817 and has the number J. */
7819 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7821 rtx insn = chain->insn;
7822 rtx old = (rl->in && MEM_P (rl->in)
7823 ? rl->in_reg : rl->in);
7824 rtx reg_rtx = rl->reg_rtx;
7828 enum machine_mode mode;
7830 /* Determine the mode to reload in.
7831 This is very tricky because we have three to choose from.
7832 There is the mode the insn operand wants (rl->inmode).
7833 There is the mode of the reload register RELOADREG.
7834 There is the intrinsic mode of the operand, which we could find
7835 by stripping some SUBREGs.
7836 It turns out that RELOADREG's mode is irrelevant:
7837 we can change that arbitrarily.
7839 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7840 then the reload reg may not support QImode moves, so use SImode.
7841 If foo is in memory due to spilling a pseudo reg, this is safe,
7842 because the QImode value is in the least significant part of a
7843 slot big enough for a SImode. If foo is some other sort of
7844 memory reference, then it is impossible to reload this case,
7845 so previous passes had better make sure this never happens.
7847 Then consider a one-word union which has SImode and one of its
7848 members is a float, being fetched as (SUBREG:SF union:SI).
7849 We must fetch that as SFmode because we could be loading into
7850 a float-only register. In this case OLD's mode is correct.
7852 Consider an immediate integer: it has VOIDmode. Here we need
7853 to get a mode from something else.
7855 In some cases, there is a fourth mode, the operand's
7856 containing mode. If the insn specifies a containing mode for
7857 this operand, it overrides all others.
7859 I am not sure whether the algorithm here is always right,
7860 but it does the right things in those cases. */
7862 mode = GET_MODE (old);
7863 if (mode == VOIDmode)
7866 /* We cannot use gen_lowpart_common since it can do the wrong thing
7867 when REG_RTX has a multi-word mode. Note that REG_RTX must
7868 always be a REG here. */
7869 if (GET_MODE (reg_rtx) != mode)
7870 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7872 reload_reg_rtx_for_input[j] = reg_rtx;
7875 /* AUTO_INC reloads need to be handled even if inherited. We got an
7876 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7877 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7878 && ! rtx_equal_p (reg_rtx, old)
7880 emit_input_reload_insns (chain, rld + j, old, j);
7882 /* When inheriting a wider reload, we have a MEM in rl->in,
7883 e.g. inheriting a SImode output reload for
7884 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7885 if (optimize && reload_inherited[j] && rl->in
7887 && MEM_P (rl->in_reg)
7888 && reload_spill_index[j] >= 0
7889 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7890 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7892 /* If we are reloading a register that was recently stored in with an
7893 output-reload, see if we can prove there was
7894 actually no need to store the old value in it. */
7897 && (reload_inherited[j] || reload_override_in[j])
7900 && spill_reg_store[REGNO (reg_rtx)] != 0
7902 /* There doesn't seem to be any reason to restrict this to pseudos
7903 and doing so loses in the case where we are copying from a
7904 register of the wrong class. */
7905 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7907 /* The insn might have already some references to stackslots
7908 replaced by MEMs, while reload_out_reg still names the
7910 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7911 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7912 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7915 /* Do output reloading for reload RL, which is for the insn described by
7916 CHAIN and has the number J.
7917 ??? At some point we need to support handling output reloads of
7918 JUMP_INSNs or insns that set cc0. */
7920 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7923 rtx insn = chain->insn;
7924 /* If this is an output reload that stores something that is
7925 not loaded in this same reload, see if we can eliminate a previous
7927 rtx pseudo = rl->out_reg;
7928 rtx reg_rtx = rl->reg_rtx;
7930 if (rl->out && reg_rtx)
7932 enum machine_mode mode;
7934 /* Determine the mode to reload in.
7935 See comments above (for input reloading). */
7936 mode = GET_MODE (rl->out);
7937 if (mode == VOIDmode)
7939 /* VOIDmode should never happen for an output. */
7940 if (asm_noperands (PATTERN (insn)) < 0)
7941 /* It's the compiler's fault. */
7942 fatal_insn ("VOIDmode on an output", insn);
7943 error_for_asm (insn, "output operand is constant in %<asm%>");
7944 /* Prevent crash--use something we know is valid. */
7946 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7948 if (GET_MODE (reg_rtx) != mode)
7949 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7951 reload_reg_rtx_for_output[j] = reg_rtx;
7956 && ! rtx_equal_p (rl->in_reg, pseudo)
7957 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7958 && reg_last_reload_reg[REGNO (pseudo)])
7960 int pseudo_no = REGNO (pseudo);
7961 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7963 /* We don't need to test full validity of last_regno for
7964 inherit here; we only want to know if the store actually
7965 matches the pseudo. */
7966 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7967 && reg_reloaded_contents[last_regno] == pseudo_no
7968 && spill_reg_store[last_regno]
7969 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7970 delete_output_reload (insn, j, last_regno, reg_rtx);
7976 || rtx_equal_p (old, reg_rtx))
7979 /* An output operand that dies right away does need a reload,
7980 but need not be copied from it. Show the new location in the
7982 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7983 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7985 XEXP (note, 0) = reg_rtx;
7988 /* Likewise for a SUBREG of an operand that dies. */
7989 else if (GET_CODE (old) == SUBREG
7990 && REG_P (SUBREG_REG (old))
7991 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7994 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7997 else if (GET_CODE (old) == SCRATCH)
7998 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7999 but we don't want to make an output reload. */
8002 /* If is a JUMP_INSN, we can't support output reloads yet. */
8003 gcc_assert (NONJUMP_INSN_P (insn));
8005 emit_output_reload_insns (chain, rld + j, j);
8008 /* A reload copies values of MODE from register SRC to register DEST.
8009 Return true if it can be treated for inheritance purposes like a
8010 group of reloads, each one reloading a single hard register. The
8011 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8012 occupy the same number of hard registers. */
8015 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8016 int src ATTRIBUTE_UNUSED,
8017 enum machine_mode mode ATTRIBUTE_UNUSED)
8019 #ifdef CANNOT_CHANGE_MODE_CLASS
8020 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8021 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8027 /* Output insns to reload values in and out of the chosen reload regs. */
8030 emit_reload_insns (struct insn_chain *chain)
8032 rtx insn = chain->insn;
8036 CLEAR_HARD_REG_SET (reg_reloaded_died);
8038 for (j = 0; j < reload_n_operands; j++)
8039 input_reload_insns[j] = input_address_reload_insns[j]
8040 = inpaddr_address_reload_insns[j]
8041 = output_reload_insns[j] = output_address_reload_insns[j]
8042 = outaddr_address_reload_insns[j]
8043 = other_output_reload_insns[j] = 0;
8044 other_input_address_reload_insns = 0;
8045 other_input_reload_insns = 0;
8046 operand_reload_insns = 0;
8047 other_operand_reload_insns = 0;
8049 /* Dump reloads into the dump file. */
8052 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8053 debug_reload_to_stream (dump_file);
8056 for (j = 0; j < n_reloads; j++)
8057 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8061 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8062 new_spill_reg_store[i] = 0;
8065 /* Now output the instructions to copy the data into and out of the
8066 reload registers. Do these in the order that the reloads were reported,
8067 since reloads of base and index registers precede reloads of operands
8068 and the operands may need the base and index registers reloaded. */
8070 for (j = 0; j < n_reloads; j++)
8072 do_input_reload (chain, rld + j, j);
8073 do_output_reload (chain, rld + j, j);
8076 /* Now write all the insns we made for reloads in the order expected by
8077 the allocation functions. Prior to the insn being reloaded, we write
8078 the following reloads:
8080 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8082 RELOAD_OTHER reloads.
8084 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8085 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8086 RELOAD_FOR_INPUT reload for the operand.
8088 RELOAD_FOR_OPADDR_ADDRS reloads.
8090 RELOAD_FOR_OPERAND_ADDRESS reloads.
8092 After the insn being reloaded, we write the following:
8094 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8095 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8096 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8097 reloads for the operand. The RELOAD_OTHER output reloads are
8098 output in descending order by reload number. */
8100 emit_insn_before (other_input_address_reload_insns, insn);
8101 emit_insn_before (other_input_reload_insns, insn);
8103 for (j = 0; j < reload_n_operands; j++)
8105 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8106 emit_insn_before (input_address_reload_insns[j], insn);
8107 emit_insn_before (input_reload_insns[j], insn);
8110 emit_insn_before (other_operand_reload_insns, insn);
8111 emit_insn_before (operand_reload_insns, insn);
8113 for (j = 0; j < reload_n_operands; j++)
8115 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8116 x = emit_insn_after (output_address_reload_insns[j], x);
8117 x = emit_insn_after (output_reload_insns[j], x);
8118 emit_insn_after (other_output_reload_insns[j], x);
8121 /* For all the spill regs newly reloaded in this instruction,
8122 record what they were reloaded from, so subsequent instructions
8123 can inherit the reloads.
8125 Update spill_reg_store for the reloads of this insn.
8126 Copy the elements that were updated in the loop above. */
8128 for (j = 0; j < n_reloads; j++)
8130 int r = reload_order[j];
8131 int i = reload_spill_index[r];
8133 /* If this is a non-inherited input reload from a pseudo, we must
8134 clear any memory of a previous store to the same pseudo. Only do
8135 something if there will not be an output reload for the pseudo
8137 if (rld[r].in_reg != 0
8138 && ! (reload_inherited[r] || reload_override_in[r]))
8140 rtx reg = rld[r].in_reg;
8142 if (GET_CODE (reg) == SUBREG)
8143 reg = SUBREG_REG (reg);
8146 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8147 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8149 int nregno = REGNO (reg);
8151 if (reg_last_reload_reg[nregno])
8153 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8155 if (reg_reloaded_contents[last_regno] == nregno)
8156 spill_reg_store[last_regno] = 0;
8161 /* I is nonneg if this reload used a register.
8162 If rld[r].reg_rtx is 0, this is an optional reload
8163 that we opted to ignore. */
8165 if (i >= 0 && rld[r].reg_rtx != 0)
8167 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8170 /* For a multi register reload, we need to check if all or part
8171 of the value lives to the end. */
8172 for (k = 0; k < nr; k++)
8173 if (reload_reg_reaches_end_p (i + k, r))
8174 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8176 /* Maybe the spill reg contains a copy of reload_out. */
8178 && (REG_P (rld[r].out)
8180 ? REG_P (rld[r].out_reg)
8181 /* The reload value is an auto-modification of
8182 some kind. For PRE_INC, POST_INC, PRE_DEC
8183 and POST_DEC, we record an equivalence
8184 between the reload register and the operand
8185 on the optimistic assumption that we can make
8186 the equivalence hold. reload_as_needed must
8187 then either make it hold or invalidate the
8190 PRE_MODIFY and POST_MODIFY addresses are reloaded
8191 somewhat differently, and allowing them here leads
8193 : (GET_CODE (rld[r].out) != POST_MODIFY
8194 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8198 reg = reload_reg_rtx_for_output[r];
8199 if (reload_reg_rtx_reaches_end_p (reg, r))
8201 enum machine_mode mode = GET_MODE (reg);
8202 int regno = REGNO (reg);
8203 int nregs = hard_regno_nregs[regno][mode];
8204 rtx out = (REG_P (rld[r].out)
8208 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8209 int out_regno = REGNO (out);
8210 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8211 : hard_regno_nregs[out_regno][mode]);
8214 spill_reg_store[regno] = new_spill_reg_store[regno];
8215 spill_reg_stored_to[regno] = out;
8216 reg_last_reload_reg[out_regno] = reg;
8218 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8219 && nregs == out_nregs
8220 && inherit_piecemeal_p (out_regno, regno, mode));
8222 /* If OUT_REGNO is a hard register, it may occupy more than
8223 one register. If it does, say what is in the
8224 rest of the registers assuming that both registers
8225 agree on how many words the object takes. If not,
8226 invalidate the subsequent registers. */
8228 if (HARD_REGISTER_NUM_P (out_regno))
8229 for (k = 1; k < out_nregs; k++)
8230 reg_last_reload_reg[out_regno + k]
8231 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8233 /* Now do the inverse operation. */
8234 for (k = 0; k < nregs; k++)
8236 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8237 reg_reloaded_contents[regno + k]
8238 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8241 reg_reloaded_insn[regno + k] = insn;
8242 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8243 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8244 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8247 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8252 /* Maybe the spill reg contains a copy of reload_in. Only do
8253 something if there will not be an output reload for
8254 the register being reloaded. */
8255 else if (rld[r].out_reg == 0
8257 && ((REG_P (rld[r].in)
8258 && !HARD_REGISTER_P (rld[r].in)
8259 && !REGNO_REG_SET_P (®_has_output_reload,
8261 || (REG_P (rld[r].in_reg)
8262 && !REGNO_REG_SET_P (®_has_output_reload,
8263 REGNO (rld[r].in_reg))))
8264 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8268 reg = reload_reg_rtx_for_input[r];
8269 if (reload_reg_rtx_reaches_end_p (reg, r))
8271 enum machine_mode mode;
8279 mode = GET_MODE (reg);
8280 regno = REGNO (reg);
8281 nregs = hard_regno_nregs[regno][mode];
8282 if (REG_P (rld[r].in)
8283 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8285 else if (REG_P (rld[r].in_reg))
8288 in = XEXP (rld[r].in_reg, 0);
8289 in_regno = REGNO (in);
8291 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8292 : hard_regno_nregs[in_regno][mode]);
8294 reg_last_reload_reg[in_regno] = reg;
8296 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8297 && nregs == in_nregs
8298 && inherit_piecemeal_p (regno, in_regno, mode));
8300 if (HARD_REGISTER_NUM_P (in_regno))
8301 for (k = 1; k < in_nregs; k++)
8302 reg_last_reload_reg[in_regno + k]
8303 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8305 /* Unless we inherited this reload, show we haven't
8306 recently done a store.
8307 Previous stores of inherited auto_inc expressions
8308 also have to be discarded. */
8309 if (! reload_inherited[r]
8310 || (rld[r].out && ! rld[r].out_reg))
8311 spill_reg_store[regno] = 0;
8313 for (k = 0; k < nregs; k++)
8315 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8316 reg_reloaded_contents[regno + k]
8317 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8320 reg_reloaded_insn[regno + k] = insn;
8321 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8322 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8323 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8326 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8333 /* The following if-statement was #if 0'd in 1.34 (or before...).
8334 It's reenabled in 1.35 because supposedly nothing else
8335 deals with this problem. */
8337 /* If a register gets output-reloaded from a non-spill register,
8338 that invalidates any previous reloaded copy of it.
8339 But forget_old_reloads_1 won't get to see it, because
8340 it thinks only about the original insn. So invalidate it here.
8341 Also do the same thing for RELOAD_OTHER constraints where the
8342 output is discarded. */
8344 && ((rld[r].out != 0
8345 && (REG_P (rld[r].out)
8346 || (MEM_P (rld[r].out)
8347 && REG_P (rld[r].out_reg))))
8348 || (rld[r].out == 0 && rld[r].out_reg
8349 && REG_P (rld[r].out_reg))))
8351 rtx out = ((rld[r].out && REG_P (rld[r].out))
8352 ? rld[r].out : rld[r].out_reg);
8353 int out_regno = REGNO (out);
8354 enum machine_mode mode = GET_MODE (out);
8356 /* REG_RTX is now set or clobbered by the main instruction.
8357 As the comment above explains, forget_old_reloads_1 only
8358 sees the original instruction, and there is no guarantee
8359 that the original instruction also clobbered REG_RTX.
8360 For example, if find_reloads sees that the input side of
8361 a matched operand pair dies in this instruction, it may
8362 use the input register as the reload register.
8364 Calling forget_old_reloads_1 is a waste of effort if
8365 REG_RTX is also the output register.
8367 If we know that REG_RTX holds the value of a pseudo
8368 register, the code after the call will record that fact. */
8369 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8370 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8372 if (!HARD_REGISTER_NUM_P (out_regno))
8374 rtx src_reg, store_insn = NULL_RTX;
8376 reg_last_reload_reg[out_regno] = 0;
8378 /* If we can find a hard register that is stored, record
8379 the storing insn so that we may delete this insn with
8380 delete_output_reload. */
8381 src_reg = reload_reg_rtx_for_output[r];
8385 if (reload_reg_rtx_reaches_end_p (src_reg, r))
8386 store_insn = new_spill_reg_store[REGNO (src_reg)];
8392 /* If this is an optional reload, try to find the
8393 source reg from an input reload. */
8394 rtx set = single_set (insn);
8395 if (set && SET_DEST (set) == rld[r].out)
8399 src_reg = SET_SRC (set);
8401 for (k = 0; k < n_reloads; k++)
8403 if (rld[k].in == src_reg)
8405 src_reg = reload_reg_rtx_for_input[k];
8411 if (src_reg && REG_P (src_reg)
8412 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8414 int src_regno, src_nregs, k;
8417 gcc_assert (GET_MODE (src_reg) == mode);
8418 src_regno = REGNO (src_reg);
8419 src_nregs = hard_regno_nregs[src_regno][mode];
8420 /* The place where to find a death note varies with
8421 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8422 necessarily checked exactly in the code that moves
8423 notes, so just check both locations. */
8424 note = find_regno_note (insn, REG_DEAD, src_regno);
8425 if (! note && store_insn)
8426 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8427 for (k = 0; k < src_nregs; k++)
8429 spill_reg_store[src_regno + k] = store_insn;
8430 spill_reg_stored_to[src_regno + k] = out;
8431 reg_reloaded_contents[src_regno + k] = out_regno;
8432 reg_reloaded_insn[src_regno + k] = store_insn;
8433 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8434 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8435 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8437 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8440 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8442 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8444 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8446 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8448 reg_last_reload_reg[out_regno] = src_reg;
8449 /* We have to set reg_has_output_reload here, or else
8450 forget_old_reloads_1 will clear reg_last_reload_reg
8452 SET_REGNO_REG_SET (®_has_output_reload,
8458 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8460 for (k = 0; k < out_nregs; k++)
8461 reg_last_reload_reg[out_regno + k] = 0;
8465 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8468 /* Go through the motions to emit INSN and test if it is strictly valid.
8469 Return the emitted insn if valid, else return NULL. */
8472 emit_insn_if_valid_for_reload (rtx insn)
8474 rtx last = get_last_insn ();
8477 insn = emit_insn (insn);
8478 code = recog_memoized (insn);
8482 extract_insn (insn);
8483 /* We want constrain operands to treat this insn strictly in its
8484 validity determination, i.e., the way it would after reload has
8486 if (constrain_operands (1))
8490 delete_insns_since (last);
8494 /* Emit code to perform a reload from IN (which may be a reload register) to
8495 OUT (which may also be a reload register). IN or OUT is from operand
8496 OPNUM with reload type TYPE.
8498 Returns first insn emitted. */
8501 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8503 rtx last = get_last_insn ();
8505 #ifdef SECONDARY_MEMORY_NEEDED
8509 /* If IN is a paradoxical SUBREG, remove it and try to put the
8510 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8511 if (!strip_paradoxical_subreg (&in, &out))
8512 strip_paradoxical_subreg (&out, &in);
8514 /* How to do this reload can get quite tricky. Normally, we are being
8515 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8516 register that didn't get a hard register. In that case we can just
8517 call emit_move_insn.
8519 We can also be asked to reload a PLUS that adds a register or a MEM to
8520 another register, constant or MEM. This can occur during frame pointer
8521 elimination and while reloading addresses. This case is handled by
8522 trying to emit a single insn to perform the add. If it is not valid,
8523 we use a two insn sequence.
8525 Or we can be asked to reload an unary operand that was a fragment of
8526 an addressing mode, into a register. If it isn't recognized as-is,
8527 we try making the unop operand and the reload-register the same:
8528 (set reg:X (unop:X expr:Y))
8529 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8531 Finally, we could be called to handle an 'o' constraint by putting
8532 an address into a register. In that case, we first try to do this
8533 with a named pattern of "reload_load_address". If no such pattern
8534 exists, we just emit a SET insn and hope for the best (it will normally
8535 be valid on machines that use 'o').
8537 This entire process is made complex because reload will never
8538 process the insns we generate here and so we must ensure that
8539 they will fit their constraints and also by the fact that parts of
8540 IN might be being reloaded separately and replaced with spill registers.
8541 Because of this, we are, in some sense, just guessing the right approach
8542 here. The one listed above seems to work.
8544 ??? At some point, this whole thing needs to be rethought. */
8546 if (GET_CODE (in) == PLUS
8547 && (REG_P (XEXP (in, 0))
8548 || GET_CODE (XEXP (in, 0)) == SUBREG
8549 || MEM_P (XEXP (in, 0)))
8550 && (REG_P (XEXP (in, 1))
8551 || GET_CODE (XEXP (in, 1)) == SUBREG
8552 || CONSTANT_P (XEXP (in, 1))
8553 || MEM_P (XEXP (in, 1))))
8555 /* We need to compute the sum of a register or a MEM and another
8556 register, constant, or MEM, and put it into the reload
8557 register. The best possible way of doing this is if the machine
8558 has a three-operand ADD insn that accepts the required operands.
8560 The simplest approach is to try to generate such an insn and see if it
8561 is recognized and matches its constraints. If so, it can be used.
8563 It might be better not to actually emit the insn unless it is valid,
8564 but we need to pass the insn as an operand to `recog' and
8565 `extract_insn' and it is simpler to emit and then delete the insn if
8566 not valid than to dummy things up. */
8568 rtx op0, op1, tem, insn;
8569 enum insn_code code;
8571 op0 = find_replacement (&XEXP (in, 0));
8572 op1 = find_replacement (&XEXP (in, 1));
8574 /* Since constraint checking is strict, commutativity won't be
8575 checked, so we need to do that here to avoid spurious failure
8576 if the add instruction is two-address and the second operand
8577 of the add is the same as the reload reg, which is frequently
8578 the case. If the insn would be A = B + A, rearrange it so
8579 it will be A = A + B as constrain_operands expects. */
8581 if (REG_P (XEXP (in, 1))
8582 && REGNO (out) == REGNO (XEXP (in, 1)))
8583 tem = op0, op0 = op1, op1 = tem;
8585 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8586 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8588 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8592 /* If that failed, we must use a conservative two-insn sequence.
8594 Use a move to copy one operand into the reload register. Prefer
8595 to reload a constant, MEM or pseudo since the move patterns can
8596 handle an arbitrary operand. If OP1 is not a constant, MEM or
8597 pseudo and OP1 is not a valid operand for an add instruction, then
8600 After reloading one of the operands into the reload register, add
8601 the reload register to the output register.
8603 If there is another way to do this for a specific machine, a
8604 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8607 code = optab_handler (add_optab, GET_MODE (out));
8609 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8611 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8612 || (code != CODE_FOR_nothing
8613 && !insn_operand_matches (code, 2, op1)))
8614 tem = op0, op0 = op1, op1 = tem;
8616 gen_reload (out, op0, opnum, type);
8618 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8619 This fixes a problem on the 32K where the stack pointer cannot
8620 be used as an operand of an add insn. */
8622 if (rtx_equal_p (op0, op1))
8625 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8628 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8629 set_dst_reg_note (insn, REG_EQUIV, in, out);
8633 /* If that failed, copy the address register to the reload register.
8634 Then add the constant to the reload register. */
8636 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8637 gen_reload (out, op1, opnum, type);
8638 insn = emit_insn (gen_add2_insn (out, op0));
8639 set_dst_reg_note (insn, REG_EQUIV, in, out);
8642 #ifdef SECONDARY_MEMORY_NEEDED
8643 /* If we need a memory location to do the move, do it that way. */
8644 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8645 (REG_P (tem1) && REG_P (tem2)))
8646 && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8647 && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8648 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1)),
8649 REGNO_REG_CLASS (REGNO (tem2)),
8652 /* Get the memory to use and rewrite both registers to its mode. */
8653 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8655 if (GET_MODE (loc) != GET_MODE (out))
8656 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8658 if (GET_MODE (loc) != GET_MODE (in))
8659 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8661 gen_reload (loc, in, opnum, type);
8662 gen_reload (out, loc, opnum, type);
8665 else if (REG_P (out) && UNARY_P (in))
8672 op1 = find_replacement (&XEXP (in, 0));
8673 if (op1 != XEXP (in, 0))
8674 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8676 /* First, try a plain SET. */
8677 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8681 /* If that failed, move the inner operand to the reload
8682 register, and try the same unop with the inner expression
8683 replaced with the reload register. */
8685 if (GET_MODE (op1) != GET_MODE (out))
8686 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8690 gen_reload (out_moded, op1, opnum, type);
8693 = gen_rtx_SET (VOIDmode, out,
8694 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8696 insn = emit_insn_if_valid_for_reload (insn);
8699 set_unique_reg_note (insn, REG_EQUIV, in);
8703 fatal_insn ("failure trying to reload:", set);
8705 /* If IN is a simple operand, use gen_move_insn. */
8706 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8708 tem = emit_insn (gen_move_insn (out, in));
8709 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8710 mark_jump_label (in, tem, 0);
8713 #ifdef HAVE_reload_load_address
8714 else if (HAVE_reload_load_address)
8715 emit_insn (gen_reload_load_address (out, in));
8718 /* Otherwise, just write (set OUT IN) and hope for the best. */
8720 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8722 /* Return the first insn emitted.
8723 We can not just return get_last_insn, because there may have
8724 been multiple instructions emitted. Also note that gen_move_insn may
8725 emit more than one insn itself, so we can not assume that there is one
8726 insn emitted per emit_insn_before call. */
8728 return last ? NEXT_INSN (last) : get_insns ();
8731 /* Delete a previously made output-reload whose result we now believe
8732 is not needed. First we double-check.
8734 INSN is the insn now being processed.
8735 LAST_RELOAD_REG is the hard register number for which we want to delete
8736 the last output reload.
8737 J is the reload-number that originally used REG. The caller has made
8738 certain that reload J doesn't use REG any longer for input.
8739 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8742 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8744 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8745 rtx reg = spill_reg_stored_to[last_reload_reg];
8748 int n_inherited = 0;
8754 /* It is possible that this reload has been only used to set another reload
8755 we eliminated earlier and thus deleted this instruction too. */
8756 if (INSN_DELETED_P (output_reload_insn))
8759 /* Get the raw pseudo-register referred to. */
8761 while (GET_CODE (reg) == SUBREG)
8762 reg = SUBREG_REG (reg);
8763 substed = reg_equiv_memory_loc (REGNO (reg));
8765 /* This is unsafe if the operand occurs more often in the current
8766 insn than it is inherited. */
8767 for (k = n_reloads - 1; k >= 0; k--)
8769 rtx reg2 = rld[k].in;
8772 if (MEM_P (reg2) || reload_override_in[k])
8773 reg2 = rld[k].in_reg;
8775 if (rld[k].out && ! rld[k].out_reg)
8776 reg2 = XEXP (rld[k].in_reg, 0);
8778 while (GET_CODE (reg2) == SUBREG)
8779 reg2 = SUBREG_REG (reg2);
8780 if (rtx_equal_p (reg2, reg))
8782 if (reload_inherited[k] || reload_override_in[k] || k == j)
8788 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8789 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8790 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8793 n_occurrences += count_occurrences (PATTERN (insn),
8794 eliminate_regs (substed, VOIDmode,
8796 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8798 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8799 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8801 if (n_occurrences > n_inherited)
8804 regno = REGNO (reg);
8805 if (regno >= FIRST_PSEUDO_REGISTER)
8808 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8810 /* If the pseudo-reg we are reloading is no longer referenced
8811 anywhere between the store into it and here,
8812 and we're within the same basic block, then the value can only
8813 pass through the reload reg and end up here.
8814 Otherwise, give up--return. */
8815 for (i1 = NEXT_INSN (output_reload_insn);
8816 i1 != insn; i1 = NEXT_INSN (i1))
8818 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8820 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8821 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8823 /* If this is USE in front of INSN, we only have to check that
8824 there are no more references than accounted for by inheritance. */
8825 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8827 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8828 i1 = NEXT_INSN (i1);
8830 if (n_occurrences <= n_inherited && i1 == insn)
8836 /* We will be deleting the insn. Remove the spill reg information. */
8837 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8839 spill_reg_store[last_reload_reg + k] = 0;
8840 spill_reg_stored_to[last_reload_reg + k] = 0;
8843 /* The caller has already checked that REG dies or is set in INSN.
8844 It has also checked that we are optimizing, and thus some
8845 inaccuracies in the debugging information are acceptable.
8846 So we could just delete output_reload_insn. But in some cases
8847 we can improve the debugging information without sacrificing
8848 optimization - maybe even improving the code: See if the pseudo
8849 reg has been completely replaced with reload regs. If so, delete
8850 the store insn and forget we had a stack slot for the pseudo. */
8851 if (rld[j].out != rld[j].in
8852 && REG_N_DEATHS (REGNO (reg)) == 1
8853 && REG_N_SETS (REGNO (reg)) == 1
8854 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8855 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8859 /* We know that it was used only between here and the beginning of
8860 the current basic block. (We also know that the last use before
8861 INSN was the output reload we are thinking of deleting, but never
8862 mind that.) Search that range; see if any ref remains. */
8863 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8865 rtx set = single_set (i2);
8867 /* Uses which just store in the pseudo don't count,
8868 since if they are the only uses, they are dead. */
8869 if (set != 0 && SET_DEST (set) == reg)
8874 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8875 && reg_mentioned_p (reg, PATTERN (i2)))
8877 /* Some other ref remains; just delete the output reload we
8879 delete_address_reloads (output_reload_insn, insn);
8880 delete_insn (output_reload_insn);
8885 /* Delete the now-dead stores into this pseudo. Note that this
8886 loop also takes care of deleting output_reload_insn. */
8887 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8889 rtx set = single_set (i2);
8891 if (set != 0 && SET_DEST (set) == reg)
8893 delete_address_reloads (i2, insn);
8901 /* For the debugging info, say the pseudo lives in this reload reg. */
8902 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8903 if (ira_conflicts_p)
8904 /* Inform IRA about the change. */
8905 ira_mark_allocation_change (REGNO (reg));
8906 alter_reg (REGNO (reg), -1, false);
8910 delete_address_reloads (output_reload_insn, insn);
8911 delete_insn (output_reload_insn);
8915 /* We are going to delete DEAD_INSN. Recursively delete loads of
8916 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8917 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8919 delete_address_reloads (rtx dead_insn, rtx current_insn)
8921 rtx set = single_set (dead_insn);
8922 rtx set2, dst, prev, next;
8925 rtx dst = SET_DEST (set);
8927 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8929 /* If we deleted the store from a reloaded post_{in,de}c expression,
8930 we can delete the matching adds. */
8931 prev = PREV_INSN (dead_insn);
8932 next = NEXT_INSN (dead_insn);
8933 if (! prev || ! next)
8935 set = single_set (next);
8936 set2 = single_set (prev);
8938 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8939 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8940 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8942 dst = SET_DEST (set);
8943 if (! rtx_equal_p (dst, SET_DEST (set2))
8944 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8945 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8946 || (INTVAL (XEXP (SET_SRC (set), 1))
8947 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8949 delete_related_insns (prev);
8950 delete_related_insns (next);
8953 /* Subfunction of delete_address_reloads: process registers found in X. */
8955 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8957 rtx prev, set, dst, i2;
8959 enum rtx_code code = GET_CODE (x);
8963 const char *fmt = GET_RTX_FORMAT (code);
8964 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8967 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8968 else if (fmt[i] == 'E')
8970 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8971 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8978 if (spill_reg_order[REGNO (x)] < 0)
8981 /* Scan backwards for the insn that sets x. This might be a way back due
8983 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8985 code = GET_CODE (prev);
8986 if (code == CODE_LABEL || code == JUMP_INSN)
8990 if (reg_set_p (x, PATTERN (prev)))
8992 if (reg_referenced_p (x, PATTERN (prev)))
8995 if (! prev || INSN_UID (prev) < reload_first_uid)
8997 /* Check that PREV only sets the reload register. */
8998 set = single_set (prev);
9001 dst = SET_DEST (set);
9003 || ! rtx_equal_p (dst, x))
9005 if (! reg_set_p (dst, PATTERN (dead_insn)))
9007 /* Check if DST was used in a later insn -
9008 it might have been inherited. */
9009 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9015 if (reg_referenced_p (dst, PATTERN (i2)))
9017 /* If there is a reference to the register in the current insn,
9018 it might be loaded in a non-inherited reload. If no other
9019 reload uses it, that means the register is set before
9021 if (i2 == current_insn)
9023 for (j = n_reloads - 1; j >= 0; j--)
9024 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9025 || reload_override_in[j] == dst)
9027 for (j = n_reloads - 1; j >= 0; j--)
9028 if (rld[j].in && rld[j].reg_rtx == dst)
9037 /* If DST is still live at CURRENT_INSN, check if it is used for
9038 any reload. Note that even if CURRENT_INSN sets DST, we still
9039 have to check the reloads. */
9040 if (i2 == current_insn)
9042 for (j = n_reloads - 1; j >= 0; j--)
9043 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9044 || reload_override_in[j] == dst)
9046 /* ??? We can't finish the loop here, because dst might be
9047 allocated to a pseudo in this block if no reload in this
9048 block needs any of the classes containing DST - see
9049 spill_hard_reg. There is no easy way to tell this, so we
9050 have to scan till the end of the basic block. */
9052 if (reg_set_p (dst, PATTERN (i2)))
9056 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9057 reg_reloaded_contents[REGNO (dst)] = -1;
9061 /* Output reload-insns to reload VALUE into RELOADREG.
9062 VALUE is an autoincrement or autodecrement RTX whose operand
9063 is a register or memory location;
9064 so reloading involves incrementing that location.
9065 IN is either identical to VALUE, or some cheaper place to reload from.
9067 INC_AMOUNT is the number to increment or decrement by (always positive).
9068 This cannot be deduced from VALUE. */
9071 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9073 /* REG or MEM to be copied and incremented. */
9074 rtx incloc = find_replacement (&XEXP (value, 0));
9075 /* Nonzero if increment after copying. */
9076 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9077 || GET_CODE (value) == POST_MODIFY);
9082 rtx real_in = in == value ? incloc : in;
9084 /* No hard register is equivalent to this register after
9085 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9086 we could inc/dec that register as well (maybe even using it for
9087 the source), but I'm not sure it's worth worrying about. */
9089 reg_last_reload_reg[REGNO (incloc)] = 0;
9091 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9093 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9094 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9098 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9099 inc_amount = -inc_amount;
9101 inc = GEN_INT (inc_amount);
9104 /* If this is post-increment, first copy the location to the reload reg. */
9105 if (post && real_in != reloadreg)
9106 emit_insn (gen_move_insn (reloadreg, real_in));
9110 /* See if we can directly increment INCLOC. Use a method similar to
9111 that in gen_reload. */
9113 last = get_last_insn ();
9114 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9115 gen_rtx_PLUS (GET_MODE (incloc),
9118 code = recog_memoized (add_insn);
9121 extract_insn (add_insn);
9122 if (constrain_operands (1))
9124 /* If this is a pre-increment and we have incremented the value
9125 where it lives, copy the incremented value to RELOADREG to
9126 be used as an address. */
9129 emit_insn (gen_move_insn (reloadreg, incloc));
9133 delete_insns_since (last);
9136 /* If couldn't do the increment directly, must increment in RELOADREG.
9137 The way we do this depends on whether this is pre- or post-increment.
9138 For pre-increment, copy INCLOC to the reload register, increment it
9139 there, then save back. */
9143 if (in != reloadreg)
9144 emit_insn (gen_move_insn (reloadreg, real_in));
9145 emit_insn (gen_add2_insn (reloadreg, inc));
9146 emit_insn (gen_move_insn (incloc, reloadreg));
9151 Because this might be a jump insn or a compare, and because RELOADREG
9152 may not be available after the insn in an input reload, we must do
9153 the incrementation before the insn being reloaded for.
9155 We have already copied IN to RELOADREG. Increment the copy in
9156 RELOADREG, save that back, then decrement RELOADREG so it has
9157 the original value. */
9159 emit_insn (gen_add2_insn (reloadreg, inc));
9160 emit_insn (gen_move_insn (incloc, reloadreg));
9161 if (CONST_INT_P (inc))
9162 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9164 emit_insn (gen_sub2_insn (reloadreg, inc));
9170 add_auto_inc_notes (rtx insn, rtx x)
9172 enum rtx_code code = GET_CODE (x);
9176 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9178 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9182 /* Scan all the operand sub-expressions. */
9183 fmt = GET_RTX_FORMAT (code);
9184 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9187 add_auto_inc_notes (insn, XEXP (x, i));
9188 else if (fmt[i] == 'E')
9189 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9190 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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