1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
29 #include "rtl-error.h"
31 #include "insn-config.h"
42 #include "insn-codes.h"
45 #include "addresses.h"
56 /* This file contains the reload pass of the compiler, which is
57 run after register allocation has been done. It checks that
58 each insn is valid (operands required to be in registers really
59 are in registers of the proper class) and fixes up invalid ones
60 by copying values temporarily into registers for the insns
63 The results of register allocation are described by the vector
64 reg_renumber; the insns still contain pseudo regs, but reg_renumber
65 can be used to find which hard reg, if any, a pseudo reg is in.
67 The technique we always use is to free up a few hard regs that are
68 called ``reload regs'', and for each place where a pseudo reg
69 must be in a hard reg, copy it temporarily into one of the reload regs.
71 Reload regs are allocated locally for every instruction that needs
72 reloads. When there are pseudos which are allocated to a register that
73 has been chosen as a reload reg, such pseudos must be ``spilled''.
74 This means that they go to other hard regs, or to stack slots if no other
75 available hard regs can be found. Spilling can invalidate more
76 insns, requiring additional need for reloads, so we must keep checking
77 until the process stabilizes.
79 For machines with different classes of registers, we must keep track
80 of the register class needed for each reload, and make sure that
81 we allocate enough reload registers of each class.
83 The file reload.c contains the code that checks one insn for
84 validity and reports the reloads that it needs. This file
85 is in charge of scanning the entire rtl code, accumulating the
86 reload needs, spilling, assigning reload registers to use for
87 fixing up each insn, and generating the new insns to copy values
88 into the reload registers. */
90 struct target_reload default_target_reload;
92 struct target_reload *this_target_reload = &default_target_reload;
95 #define spill_indirect_levels \
96 (this_target_reload->x_spill_indirect_levels)
98 /* During reload_as_needed, element N contains a REG rtx for the hard reg
99 into which reg N has been reloaded (perhaps for a previous insn). */
100 static rtx *reg_last_reload_reg;
102 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
103 for an output reload that stores into reg N. */
104 static regset_head reg_has_output_reload;
106 /* Indicates which hard regs are reload-registers for an output reload
107 in the current insn. */
108 static HARD_REG_SET reg_is_output_reload;
110 /* Widest width in which each pseudo reg is referred to (via subreg). */
111 static unsigned int *reg_max_ref_width;
113 /* Vector to remember old contents of reg_renumber before spilling. */
114 static short *reg_old_renumber;
116 /* During reload_as_needed, element N contains the last pseudo regno reloaded
117 into hard register N. If that pseudo reg occupied more than one register,
118 reg_reloaded_contents points to that pseudo for each spill register in
119 use; all of these must remain set for an inheritance to occur. */
120 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
122 /* During reload_as_needed, element N contains the insn for which
123 hard register N was last used. Its contents are significant only
124 when reg_reloaded_valid is set for this register. */
125 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
127 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
128 static HARD_REG_SET reg_reloaded_valid;
129 /* Indicate if the register was dead at the end of the reload.
130 This is only valid if reg_reloaded_contents is set and valid. */
131 static HARD_REG_SET reg_reloaded_dead;
133 /* Indicate whether the register's current value is one that is not
134 safe to retain across a call, even for registers that are normally
135 call-saved. This is only meaningful for members of reg_reloaded_valid. */
136 static HARD_REG_SET reg_reloaded_call_part_clobbered;
138 /* Number of spill-regs so far; number of valid elements of spill_regs. */
141 /* In parallel with spill_regs, contains REG rtx's for those regs.
142 Holds the last rtx used for any given reg, or 0 if it has never
143 been used for spilling yet. This rtx is reused, provided it has
145 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
147 /* In parallel with spill_regs, contains nonzero for a spill reg
148 that was stored after the last time it was used.
149 The precise value is the insn generated to do the store. */
150 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
152 /* This is the register that was stored with spill_reg_store. This is a
153 copy of reload_out / reload_out_reg when the value was stored; if
154 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
155 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
157 /* This table is the inverse mapping of spill_regs:
158 indexed by hard reg number,
159 it contains the position of that reg in spill_regs,
160 or -1 for something that is not in spill_regs.
162 ?!? This is no longer accurate. */
163 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
165 /* This reg set indicates registers that can't be used as spill registers for
166 the currently processed insn. These are the hard registers which are live
167 during the insn, but not allocated to pseudos, as well as fixed
169 static HARD_REG_SET bad_spill_regs;
171 /* These are the hard registers that can't be used as spill register for any
172 insn. This includes registers used for user variables and registers that
173 we can't eliminate. A register that appears in this set also can't be used
174 to retry register allocation. */
175 static HARD_REG_SET bad_spill_regs_global;
177 /* Describes order of use of registers for reloading
178 of spilled pseudo-registers. `n_spills' is the number of
179 elements that are actually valid; new ones are added at the end.
181 Both spill_regs and spill_reg_order are used on two occasions:
182 once during find_reload_regs, where they keep track of the spill registers
183 for a single insn, but also during reload_as_needed where they show all
184 the registers ever used by reload. For the latter case, the information
185 is calculated during finish_spills. */
186 static short spill_regs[FIRST_PSEUDO_REGISTER];
188 /* This vector of reg sets indicates, for each pseudo, which hard registers
189 may not be used for retrying global allocation because the register was
190 formerly spilled from one of them. If we allowed reallocating a pseudo to
191 a register that it was already allocated to, reload might not
193 static HARD_REG_SET *pseudo_previous_regs;
195 /* This vector of reg sets indicates, for each pseudo, which hard
196 registers may not be used for retrying global allocation because they
197 are used as spill registers during one of the insns in which the
199 static HARD_REG_SET *pseudo_forbidden_regs;
201 /* All hard regs that have been used as spill registers for any insn are
202 marked in this set. */
203 static HARD_REG_SET used_spill_regs;
205 /* Index of last register assigned as a spill register. We allocate in
206 a round-robin fashion. */
207 static int last_spill_reg;
209 /* Record the stack slot for each spilled hard register. */
210 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
212 /* Width allocated so far for that stack slot. */
213 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
215 /* Record which pseudos needed to be spilled. */
216 static regset_head spilled_pseudos;
218 /* Record which pseudos changed their allocation in finish_spills. */
219 static regset_head changed_allocation_pseudos;
221 /* Used for communication between order_regs_for_reload and count_pseudo.
222 Used to avoid counting one pseudo twice. */
223 static regset_head pseudos_counted;
225 /* First uid used by insns created by reload in this function.
226 Used in find_equiv_reg. */
227 int reload_first_uid;
229 /* Flag set by local-alloc or global-alloc if anything is live in
230 a call-clobbered reg across calls. */
231 int caller_save_needed;
233 /* Set to 1 while reload_as_needed is operating.
234 Required by some machines to handle any generated moves differently. */
235 int reload_in_progress = 0;
237 /* This obstack is used for allocation of rtl during register elimination.
238 The allocated storage can be freed once find_reloads has processed the
240 static struct obstack reload_obstack;
242 /* Points to the beginning of the reload_obstack. All insn_chain structures
243 are allocated first. */
244 static char *reload_startobj;
246 /* The point after all insn_chain structures. Used to quickly deallocate
247 memory allocated in copy_reloads during calculate_needs_all_insns. */
248 static char *reload_firstobj;
250 /* This points before all local rtl generated by register elimination.
251 Used to quickly free all memory after processing one insn. */
252 static char *reload_insn_firstobj;
254 /* List of insn_chain instructions, one for every insn that reload needs to
256 struct insn_chain *reload_insn_chain;
258 /* TRUE if we potentially left dead insns in the insn stream and want to
259 run DCE immediately after reload, FALSE otherwise. */
260 static bool need_dce;
262 /* List of all insns needing reloads. */
263 static struct insn_chain *insns_need_reload;
265 /* This structure is used to record information about register eliminations.
266 Each array entry describes one possible way of eliminating a register
267 in favor of another. If there is more than one way of eliminating a
268 particular register, the most preferred should be specified first. */
272 int from; /* Register number to be eliminated. */
273 int to; /* Register number used as replacement. */
274 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
275 int can_eliminate; /* Nonzero if this elimination can be done. */
276 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
277 target hook in previous scan over insns
279 HOST_WIDE_INT offset; /* Current offset between the two regs. */
280 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
281 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
282 rtx from_rtx; /* REG rtx for the register to be eliminated.
283 We cannot simply compare the number since
284 we might then spuriously replace a hard
285 register corresponding to a pseudo
286 assigned to the reg to be eliminated. */
287 rtx to_rtx; /* REG rtx for the replacement. */
290 static struct elim_table *reg_eliminate = 0;
292 /* This is an intermediate structure to initialize the table. It has
293 exactly the members provided by ELIMINABLE_REGS. */
294 static const struct elim_table_1
298 } reg_eliminate_1[] =
300 /* If a set of eliminable registers was specified, define the table from it.
301 Otherwise, default to the normal case of the frame pointer being
302 replaced by the stack pointer. */
304 #ifdef ELIMINABLE_REGS
307 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
310 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
312 /* Record the number of pending eliminations that have an offset not equal
313 to their initial offset. If nonzero, we use a new copy of each
314 replacement result in any insns encountered. */
315 int num_not_at_initial_offset;
317 /* Count the number of registers that we may be able to eliminate. */
318 static int num_eliminable;
319 /* And the number of registers that are equivalent to a constant that
320 can be eliminated to frame_pointer / arg_pointer + constant. */
321 static int num_eliminable_invariants;
323 /* For each label, we record the offset of each elimination. If we reach
324 a label by more than one path and an offset differs, we cannot do the
325 elimination. This information is indexed by the difference of the
326 number of the label and the first label number. We can't offset the
327 pointer itself as this can cause problems on machines with segmented
328 memory. The first table is an array of flags that records whether we
329 have yet encountered a label and the second table is an array of arrays,
330 one entry in the latter array for each elimination. */
332 static int first_label_num;
333 static char *offsets_known_at;
334 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
336 vec<reg_equivs_t, va_gc> *reg_equivs;
338 /* Stack of addresses where an rtx has been changed. We can undo the
339 changes by popping items off the stack and restoring the original
340 value at each location.
342 We use this simplistic undo capability rather than copy_rtx as copy_rtx
343 will not make a deep copy of a normally sharable rtx, such as
344 (const (plus (symbol_ref) (const_int))). If such an expression appears
345 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
346 rtx expression would be changed. See PR 42431. */
349 static vec<rtx_p> substitute_stack;
351 /* Number of labels in the current function. */
353 static int num_labels;
355 static void replace_pseudos_in (rtx *, machine_mode, rtx);
356 static void maybe_fix_stack_asms (void);
357 static void copy_reloads (struct insn_chain *);
358 static void calculate_needs_all_insns (int);
359 static int find_reg (struct insn_chain *, int);
360 static void find_reload_regs (struct insn_chain *);
361 static void select_reload_regs (void);
362 static void delete_caller_save_insns (void);
364 static void spill_failure (rtx_insn *, enum reg_class);
365 static void count_spilled_pseudo (int, int, int);
366 static void delete_dead_insn (rtx_insn *);
367 static void alter_reg (int, int, bool);
368 static void set_label_offsets (rtx, rtx_insn *, int);
369 static void check_eliminable_occurrences (rtx);
370 static void elimination_effects (rtx, machine_mode);
371 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
372 static int eliminate_regs_in_insn (rtx_insn *, int);
373 static void update_eliminable_offsets (void);
374 static void mark_not_eliminable (rtx, const_rtx, void *);
375 static void set_initial_elim_offsets (void);
376 static bool verify_initial_elim_offsets (void);
377 static void set_initial_label_offsets (void);
378 static void set_offsets_for_label (rtx_insn *);
379 static void init_eliminable_invariants (rtx_insn *, bool);
380 static void init_elim_table (void);
381 static void free_reg_equiv (void);
382 static void update_eliminables (HARD_REG_SET *);
383 static bool update_eliminables_and_spill (void);
384 static void elimination_costs_in_insn (rtx_insn *);
385 static void spill_hard_reg (unsigned int, int);
386 static int finish_spills (int);
387 static void scan_paradoxical_subregs (rtx);
388 static void count_pseudo (int);
389 static void order_regs_for_reload (struct insn_chain *);
390 static void reload_as_needed (int);
391 static void forget_old_reloads_1 (rtx, const_rtx, void *);
392 static void forget_marked_reloads (regset);
393 static int reload_reg_class_lower (const void *, const void *);
394 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
396 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
398 static int reload_reg_free_p (unsigned int, int, enum reload_type);
399 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
401 static int free_for_value_p (int, machine_mode, int, enum reload_type,
403 static int allocate_reload_reg (struct insn_chain *, int, int);
404 static int conflicts_with_override (rtx);
405 static void failed_reload (rtx_insn *, int);
406 static int set_reload_reg (int, int);
407 static void choose_reload_regs_init (struct insn_chain *, rtx *);
408 static void choose_reload_regs (struct insn_chain *);
409 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
411 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
413 static void do_input_reload (struct insn_chain *, struct reload *, int);
414 static void do_output_reload (struct insn_chain *, struct reload *, int);
415 static void emit_reload_insns (struct insn_chain *);
416 static void delete_output_reload (rtx_insn *, int, int, rtx);
417 static void delete_address_reloads (rtx_insn *, rtx_insn *);
418 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
419 static void inc_for_reload (rtx, rtx, rtx, int);
420 static void add_auto_inc_notes (rtx_insn *, rtx);
421 static void substitute (rtx *, const_rtx, rtx);
422 static bool gen_reload_chain_without_interm_reg_p (int, int);
423 static int reloads_conflict (int, int);
424 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
425 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
427 /* Initialize the reload pass. This is called at the beginning of compilation
428 and may be called again if the target is reinitialized. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode,
443 LAST_VIRTUAL_REGISTER + 1),
444 gen_int_mode (4, Pmode)));
445 spill_indirect_levels = 0;
447 while (memory_address_p (QImode, tem))
449 spill_indirect_levels++;
450 tem = gen_rtx_MEM (Pmode, tem);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
456 indirect_symref_ok = memory_address_p (QImode, tem);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
462 tem = gen_rtx_PLUS (Pmode,
463 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
464 gen_rtx_REG (Pmode, i));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem = plus_constant (Pmode, tem, 4);
469 if (memory_address_p (QImode, tem))
471 double_reg_address_ok = 1;
476 /* Initialize obstack for our rtl allocation. */
477 if (reload_startobj == NULL)
479 gcc_obstack_init (&reload_obstack);
480 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
483 INIT_REG_SET (&spilled_pseudos);
484 INIT_REG_SET (&changed_allocation_pseudos);
485 INIT_REG_SET (&pseudos_counted);
488 /* List of insn chains that are currently unused. */
489 static struct insn_chain *unused_insn_chains = 0;
491 /* Allocate an empty insn_chain structure. */
493 new_insn_chain (void)
495 struct insn_chain *c;
497 if (unused_insn_chains == 0)
499 c = XOBNEW (&reload_obstack, struct insn_chain);
500 INIT_REG_SET (&c->live_throughout);
501 INIT_REG_SET (&c->dead_or_set);
505 c = unused_insn_chains;
506 unused_insn_chains = c->next;
508 c->is_caller_save_insn = 0;
509 c->need_operand_change = 0;
515 /* Small utility function to set all regs in hard reg set TO which are
516 allocated to pseudos in regset FROM. */
519 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
522 reg_set_iterator rsi;
524 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
526 int r = reg_renumber[regno];
530 /* reload_combine uses the information from DF_LIVE_IN,
531 which might still contain registers that have not
532 actually been allocated since they have an
534 gcc_assert (ira_conflicts_p || reload_completed);
537 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
541 /* Replace all pseudos found in LOC with their corresponding
545 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
558 unsigned int regno = REGNO (x);
560 if (regno < FIRST_PSEUDO_REGISTER)
563 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
567 replace_pseudos_in (loc, mem_mode, usage);
571 if (reg_equiv_constant (regno))
572 *loc = reg_equiv_constant (regno);
573 else if (reg_equiv_invariant (regno))
574 *loc = reg_equiv_invariant (regno);
575 else if (reg_equiv_mem (regno))
576 *loc = reg_equiv_mem (regno);
577 else if (reg_equiv_address (regno))
578 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
581 gcc_assert (!REG_P (regno_reg_rtx[regno])
582 || REGNO (regno_reg_rtx[regno]) != regno);
583 *loc = regno_reg_rtx[regno];
588 else if (code == MEM)
590 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
594 /* Process each of our operands recursively. */
595 fmt = GET_RTX_FORMAT (code);
596 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
598 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
599 else if (*fmt == 'E')
600 for (j = 0; j < XVECLEN (x, i); j++)
601 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
604 /* Determine if the current function has an exception receiver block
605 that reaches the exit block via non-exceptional edges */
608 has_nonexceptional_receiver (void)
612 basic_block *tos, *worklist, bb;
614 /* If we're not optimizing, then just err on the safe side. */
618 /* First determine which blocks can reach exit via normal paths. */
619 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
621 FOR_EACH_BB_FN (bb, cfun)
622 bb->flags &= ~BB_REACHABLE;
624 /* Place the exit block on our worklist. */
625 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
626 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
628 /* Iterate: find everything reachable from what we've already seen. */
629 while (tos != worklist)
633 FOR_EACH_EDGE (e, ei, bb->preds)
634 if (!(e->flags & EDGE_ABNORMAL))
636 basic_block src = e->src;
638 if (!(src->flags & BB_REACHABLE))
640 src->flags |= BB_REACHABLE;
647 /* Now see if there's a reachable block with an exceptional incoming
649 FOR_EACH_BB_FN (bb, cfun)
650 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
653 /* No exceptional block reached exit unexceptionally. */
657 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
658 zero elements) to MAX_REG_NUM elements.
660 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
662 grow_reg_equivs (void)
664 int old_size = vec_safe_length (reg_equivs);
665 int max_regno = max_reg_num ();
669 memset (&ze, 0, sizeof (reg_equivs_t));
670 vec_safe_reserve (reg_equivs, max_regno);
671 for (i = old_size; i < max_regno; i++)
672 reg_equivs->quick_insert (i, ze);
676 /* Global variables used by reload and its subroutines. */
678 /* The current basic block while in calculate_elim_costs_all_insns. */
679 static basic_block elim_bb;
681 /* Set during calculate_needs if an insn needs register elimination. */
682 static int something_needs_elimination;
683 /* Set during calculate_needs if an insn needs an operand changed. */
684 static int something_needs_operands_changed;
685 /* Set by alter_regs if we spilled a register to the stack. */
686 static bool something_was_spilled;
688 /* Nonzero means we couldn't get enough spill regs. */
691 /* Temporary array of pseudo-register number. */
692 static int *temp_pseudo_reg_arr;
694 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
695 If that insn didn't set the register (i.e., it copied the register to
696 memory), just delete that insn instead of the equivalencing insn plus
697 anything now dead. If we call delete_dead_insn on that insn, we may
698 delete the insn that actually sets the register if the register dies
699 there and that is incorrect. */
703 for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
705 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
708 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
710 rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
712 /* If we already deleted the insn or if it may trap, we can't
713 delete it. The latter case shouldn't happen, but can
714 if an insn has a variable address, gets a REG_EH_REGION
715 note added to it, and then gets converted into a load
716 from a constant address. */
717 if (NOTE_P (equiv_insn)
718 || can_throw_internal (equiv_insn))
720 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
721 delete_dead_insn (equiv_insn);
723 SET_INSN_DELETED (equiv_insn);
729 /* Return true if remove_init_insns will delete INSN. */
731 will_delete_init_insn_p (rtx_insn *insn)
733 rtx set = single_set (insn);
734 if (!set || !REG_P (SET_DEST (set)))
736 unsigned regno = REGNO (SET_DEST (set));
738 if (can_throw_internal (insn))
741 if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
744 for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
746 rtx equiv_insn = XEXP (list, 0);
747 if (equiv_insn == insn)
753 /* Main entry point for the reload pass.
755 FIRST is the first insn of the function being compiled.
757 GLOBAL nonzero means we were called from global_alloc
758 and should attempt to reallocate any pseudoregs that we
759 displace from hard regs we will use for reloads.
760 If GLOBAL is zero, we do not have enough information to do that,
761 so any pseudo reg that is spilled must go to the stack.
763 Return value is TRUE if reload likely left dead insns in the
764 stream and a DCE pass should be run to elimiante them. Else the
765 return value is FALSE. */
768 reload (rtx_insn *first, int global)
772 struct elim_table *ep;
776 /* Make sure even insns with volatile mem refs are recognizable. */
781 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
783 /* Make sure that the last insn in the chain
784 is not something that needs reloading. */
785 emit_note (NOTE_INSN_DELETED);
787 /* Enable find_equiv_reg to distinguish insns made by reload. */
788 reload_first_uid = get_max_uid ();
790 #ifdef SECONDARY_MEMORY_NEEDED
791 /* Initialize the secondary memory table. */
792 clear_secondary_mem ();
795 /* We don't have a stack slot for any spill reg yet. */
796 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
797 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
799 /* Initialize the save area information for caller-save, in case some
803 /* Compute which hard registers are now in use
804 as homes for pseudo registers.
805 This is done here rather than (eg) in global_alloc
806 because this point is reached even if not optimizing. */
807 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
810 /* A function that has a nonlocal label that can reach the exit
811 block via non-exceptional paths must save all call-saved
813 if (cfun->has_nonlocal_label
814 && has_nonexceptional_receiver ())
815 crtl->saves_all_registers = 1;
817 if (crtl->saves_all_registers)
818 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
819 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
820 df_set_regs_ever_live (i, true);
822 /* Find all the pseudo registers that didn't get hard regs
823 but do have known equivalent constants or memory slots.
824 These include parameters (known equivalent to parameter slots)
825 and cse'd or loop-moved constant memory addresses.
827 Record constant equivalents in reg_equiv_constant
828 so they will be substituted by find_reloads.
829 Record memory equivalents in reg_mem_equiv so they can
830 be substituted eventually by altering the REG-rtx's. */
833 reg_old_renumber = XCNEWVEC (short, max_regno);
834 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
835 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
836 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
838 CLEAR_HARD_REG_SET (bad_spill_regs_global);
840 init_eliminable_invariants (first, true);
843 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
844 stack slots to the pseudos that lack hard regs or equivalents.
845 Do not touch virtual registers. */
847 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
848 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
849 temp_pseudo_reg_arr[n++] = i;
852 /* Ask IRA to order pseudo-registers for better stack slot
854 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
856 for (i = 0; i < n; i++)
857 alter_reg (temp_pseudo_reg_arr[i], -1, false);
859 /* If we have some registers we think can be eliminated, scan all insns to
860 see if there is an insn that sets one of these registers to something
861 other than itself plus a constant. If so, the register cannot be
862 eliminated. Doing this scan here eliminates an extra pass through the
863 main reload loop in the most common case where register elimination
865 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
867 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
869 maybe_fix_stack_asms ();
871 insns_need_reload = 0;
872 something_needs_elimination = 0;
874 /* Initialize to -1, which means take the first spill register. */
877 /* Spill any hard regs that we know we can't eliminate. */
878 CLEAR_HARD_REG_SET (used_spill_regs);
879 /* There can be multiple ways to eliminate a register;
880 they should be listed adjacently.
881 Elimination for any register fails only if all possible ways fail. */
882 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
885 int can_eliminate = 0;
888 can_eliminate |= ep->can_eliminate;
891 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
893 spill_hard_reg (from, 1);
896 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
897 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
899 finish_spills (global);
901 /* From now on, we may need to generate moves differently. We may also
902 allow modifications of insns which cause them to not be recognized.
903 Any such modifications will be cleaned up during reload itself. */
904 reload_in_progress = 1;
906 /* This loop scans the entire function each go-round
907 and repeats until one repetition spills no additional hard regs. */
910 int something_changed;
912 HOST_WIDE_INT starting_frame_size;
914 starting_frame_size = get_frame_size ();
915 something_was_spilled = false;
917 set_initial_elim_offsets ();
918 set_initial_label_offsets ();
920 /* For each pseudo register that has an equivalent location defined,
921 try to eliminate any eliminable registers (such as the frame pointer)
922 assuming initial offsets for the replacement register, which
925 If the resulting location is directly addressable, substitute
926 the MEM we just got directly for the old REG.
928 If it is not addressable but is a constant or the sum of a hard reg
929 and constant, it is probably not addressable because the constant is
930 out of range, in that case record the address; we will generate
931 hairy code to compute the address in a register each time it is
932 needed. Similarly if it is a hard register, but one that is not
933 valid as an address register.
935 If the location is not addressable, but does not have one of the
936 above forms, assign a stack slot. We have to do this to avoid the
937 potential of producing lots of reloads if, e.g., a location involves
938 a pseudo that didn't get a hard register and has an equivalent memory
939 location that also involves a pseudo that didn't get a hard register.
941 Perhaps at some point we will improve reload_when_needed handling
942 so this problem goes away. But that's very hairy. */
944 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
945 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
947 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
950 if (strict_memory_address_addr_space_p
951 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
953 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
954 else if (CONSTANT_P (XEXP (x, 0))
955 || (REG_P (XEXP (x, 0))
956 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
957 || (GET_CODE (XEXP (x, 0)) == PLUS
958 && REG_P (XEXP (XEXP (x, 0), 0))
959 && (REGNO (XEXP (XEXP (x, 0), 0))
960 < FIRST_PSEUDO_REGISTER)
961 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
962 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
965 /* Make a new stack slot. Then indicate that something
966 changed so we go back and recompute offsets for
967 eliminable registers because the allocation of memory
968 below might change some offset. reg_equiv_{mem,address}
969 will be set up for this pseudo on the next pass around
971 reg_equiv_memory_loc (i) = 0;
972 reg_equiv_init (i) = 0;
973 alter_reg (i, -1, true);
977 if (caller_save_needed)
980 if (starting_frame_size && crtl->stack_alignment_needed)
982 /* If we have a stack frame, we must align it now. The
983 stack size may be a part of the offset computation for
984 register elimination. So if this changes the stack size,
985 then repeat the elimination bookkeeping. We don't
986 realign when there is no stack, as that will cause a
987 stack frame when none is needed should
988 STARTING_FRAME_OFFSET not be already aligned to
990 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
992 /* If we allocated another stack slot, redo elimination bookkeeping. */
993 if (something_was_spilled || starting_frame_size != get_frame_size ())
995 update_eliminables_and_spill ();
999 if (caller_save_needed)
1001 save_call_clobbered_regs ();
1002 /* That might have allocated new insn_chain structures. */
1003 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1006 calculate_needs_all_insns (global);
1008 if (! ira_conflicts_p)
1009 /* Don't do it for IRA. We need this info because we don't
1010 change live_throughout and dead_or_set for chains when IRA
1012 CLEAR_REG_SET (&spilled_pseudos);
1016 something_changed = 0;
1018 /* If we allocated any new memory locations, make another pass
1019 since it might have changed elimination offsets. */
1020 if (something_was_spilled || starting_frame_size != get_frame_size ())
1021 something_changed = 1;
1023 /* Even if the frame size remained the same, we might still have
1024 changed elimination offsets, e.g. if find_reloads called
1025 force_const_mem requiring the back end to allocate a constant
1026 pool base register that needs to be saved on the stack. */
1027 else if (!verify_initial_elim_offsets ())
1028 something_changed = 1;
1030 if (update_eliminables_and_spill ())
1033 something_changed = 1;
1036 select_reload_regs ();
1040 if (insns_need_reload != 0 || did_spill)
1041 something_changed |= finish_spills (global);
1043 if (! something_changed)
1046 if (caller_save_needed)
1047 delete_caller_save_insns ();
1049 obstack_free (&reload_obstack, reload_firstobj);
1052 /* If global-alloc was run, notify it of any register eliminations we have
1055 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1056 if (ep->can_eliminate)
1057 mark_elimination (ep->from, ep->to);
1059 remove_init_insns ();
1061 /* Use the reload registers where necessary
1062 by generating move instructions to move the must-be-register
1063 values into or out of the reload registers. */
1065 if (insns_need_reload != 0 || something_needs_elimination
1066 || something_needs_operands_changed)
1068 HOST_WIDE_INT old_frame_size = get_frame_size ();
1070 reload_as_needed (global);
1072 gcc_assert (old_frame_size == get_frame_size ());
1074 gcc_assert (verify_initial_elim_offsets ());
1077 /* If we were able to eliminate the frame pointer, show that it is no
1078 longer live at the start of any basic block. If it ls live by
1079 virtue of being in a pseudo, that pseudo will be marked live
1080 and hence the frame pointer will be known to be live via that
1083 if (! frame_pointer_needed)
1084 FOR_EACH_BB_FN (bb, cfun)
1085 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1087 /* Come here (with failure set nonzero) if we can't get enough spill
1091 CLEAR_REG_SET (&changed_allocation_pseudos);
1092 CLEAR_REG_SET (&spilled_pseudos);
1093 reload_in_progress = 0;
1095 /* Now eliminate all pseudo regs by modifying them into
1096 their equivalent memory references.
1097 The REG-rtx's for the pseudos are modified in place,
1098 so all insns that used to refer to them now refer to memory.
1100 For a reg that has a reg_equiv_address, all those insns
1101 were changed by reloading so that no insns refer to it any longer;
1102 but the DECL_RTL of a variable decl may refer to it,
1103 and if so this causes the debugging info to mention the variable. */
1105 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1109 if (reg_equiv_mem (i))
1110 addr = XEXP (reg_equiv_mem (i), 0);
1112 if (reg_equiv_address (i))
1113 addr = reg_equiv_address (i);
1117 if (reg_renumber[i] < 0)
1119 rtx reg = regno_reg_rtx[i];
1121 REG_USERVAR_P (reg) = 0;
1122 PUT_CODE (reg, MEM);
1123 XEXP (reg, 0) = addr;
1124 if (reg_equiv_memory_loc (i))
1125 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1127 MEM_ATTRS (reg) = 0;
1128 MEM_NOTRAP_P (reg) = 1;
1130 else if (reg_equiv_mem (i))
1131 XEXP (reg_equiv_mem (i), 0) = addr;
1134 /* We don't want complex addressing modes in debug insns
1135 if simpler ones will do, so delegitimize equivalences
1137 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1139 rtx reg = regno_reg_rtx[i];
1143 if (reg_equiv_constant (i))
1144 equiv = reg_equiv_constant (i);
1145 else if (reg_equiv_invariant (i))
1146 equiv = reg_equiv_invariant (i);
1147 else if (reg && MEM_P (reg))
1148 equiv = targetm.delegitimize_address (reg);
1149 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1155 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1157 insn = DF_REF_INSN (use);
1159 /* Make sure the next ref is for a different instruction,
1160 so that we're not affected by the rescan. */
1161 next = DF_REF_NEXT_REG (use);
1162 while (next && DF_REF_INSN (next) == insn)
1163 next = DF_REF_NEXT_REG (next);
1165 if (DEBUG_INSN_P (insn))
1169 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1170 df_insn_rescan_debug_internal (insn);
1173 INSN_VAR_LOCATION_LOC (insn)
1174 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1181 /* We must set reload_completed now since the cleanup_subreg_operands call
1182 below will re-recognize each insn and reload may have generated insns
1183 which are only valid during and after reload. */
1184 reload_completed = 1;
1186 /* Make a pass over all the insns and delete all USEs which we inserted
1187 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1188 notes. Delete all CLOBBER insns, except those that refer to the return
1189 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1190 from misarranging variable-array code, and simplify (subreg (reg))
1191 operands. Strip and regenerate REG_INC notes that may have been moved
1194 for (insn = first; insn; insn = NEXT_INSN (insn))
1200 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1201 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1203 if ((GET_CODE (PATTERN (insn)) == USE
1204 /* We mark with QImode USEs introduced by reload itself. */
1205 && (GET_MODE (insn) == QImode
1206 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1207 || (GET_CODE (PATTERN (insn)) == CLOBBER
1208 && (!MEM_P (XEXP (PATTERN (insn), 0))
1209 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1210 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1211 && XEXP (XEXP (PATTERN (insn), 0), 0)
1212 != stack_pointer_rtx))
1213 && (!REG_P (XEXP (PATTERN (insn), 0))
1214 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1220 /* Some CLOBBERs may survive until here and still reference unassigned
1221 pseudos with const equivalent, which may in turn cause ICE in later
1222 passes if the reference remains in place. */
1223 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1224 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1225 VOIDmode, PATTERN (insn));
1227 /* Discard obvious no-ops, even without -O. This optimization
1228 is fast and doesn't interfere with debugging. */
1229 if (NONJUMP_INSN_P (insn)
1230 && GET_CODE (PATTERN (insn)) == SET
1231 && REG_P (SET_SRC (PATTERN (insn)))
1232 && REG_P (SET_DEST (PATTERN (insn)))
1233 && (REGNO (SET_SRC (PATTERN (insn)))
1234 == REGNO (SET_DEST (PATTERN (insn)))))
1240 pnote = ®_NOTES (insn);
1243 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1244 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1245 || REG_NOTE_KIND (*pnote) == REG_INC)
1246 *pnote = XEXP (*pnote, 1);
1248 pnote = &XEXP (*pnote, 1);
1252 add_auto_inc_notes (insn, PATTERN (insn));
1254 /* Simplify (subreg (reg)) if it appears as an operand. */
1255 cleanup_subreg_operands (insn);
1257 /* Clean up invalid ASMs so that they don't confuse later passes.
1259 if (asm_noperands (PATTERN (insn)) >= 0)
1261 extract_insn (insn);
1262 if (!constrain_operands (1, get_enabled_alternatives (insn)))
1264 error_for_asm (insn,
1265 "%<asm%> operand has impossible constraints");
1272 /* If we are doing generic stack checking, give a warning if this
1273 function's frame size is larger than we expect. */
1274 if (flag_stack_check == GENERIC_STACK_CHECK)
1276 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1277 static int verbose_warned = 0;
1279 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1280 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1281 size += UNITS_PER_WORD;
1283 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1285 warning (0, "frame size too large for reliable stack checking");
1286 if (! verbose_warned)
1288 warning (0, "try reducing the number of local variables");
1294 free (temp_pseudo_reg_arr);
1296 /* Indicate that we no longer have known memory locations or constants. */
1299 free (reg_max_ref_width);
1300 free (reg_old_renumber);
1301 free (pseudo_previous_regs);
1302 free (pseudo_forbidden_regs);
1304 CLEAR_HARD_REG_SET (used_spill_regs);
1305 for (i = 0; i < n_spills; i++)
1306 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1308 /* Free all the insn_chain structures at once. */
1309 obstack_free (&reload_obstack, reload_startobj);
1310 unused_insn_chains = 0;
1312 inserted = fixup_abnormal_edges ();
1314 /* We've possibly turned single trapping insn into multiple ones. */
1315 if (cfun->can_throw_non_call_exceptions)
1318 blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
1319 bitmap_ones (blocks);
1320 find_many_sub_basic_blocks (blocks);
1321 sbitmap_free (blocks);
1325 commit_edge_insertions ();
1327 /* Replacing pseudos with their memory equivalents might have
1328 created shared rtx. Subsequent passes would get confused
1329 by this, so unshare everything here. */
1330 unshare_all_rtl_again (first);
1332 #ifdef STACK_BOUNDARY
1333 /* init_emit has set the alignment of the hard frame pointer
1334 to STACK_BOUNDARY. It is very likely no longer valid if
1335 the hard frame pointer was used for register allocation. */
1336 if (!frame_pointer_needed)
1337 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1340 substitute_stack.release ();
1342 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1344 reload_completed = !failure;
1349 /* Yet another special case. Unfortunately, reg-stack forces people to
1350 write incorrect clobbers in asm statements. These clobbers must not
1351 cause the register to appear in bad_spill_regs, otherwise we'll call
1352 fatal_insn later. We clear the corresponding regnos in the live
1353 register sets to avoid this.
1354 The whole thing is rather sick, I'm afraid. */
1357 maybe_fix_stack_asms (void)
1360 const char *constraints[MAX_RECOG_OPERANDS];
1361 machine_mode operand_mode[MAX_RECOG_OPERANDS];
1362 struct insn_chain *chain;
1364 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1367 HARD_REG_SET clobbered, allowed;
1370 if (! INSN_P (chain->insn)
1371 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1373 pat = PATTERN (chain->insn);
1374 if (GET_CODE (pat) != PARALLEL)
1377 CLEAR_HARD_REG_SET (clobbered);
1378 CLEAR_HARD_REG_SET (allowed);
1380 /* First, make a mask of all stack regs that are clobbered. */
1381 for (i = 0; i < XVECLEN (pat, 0); i++)
1383 rtx t = XVECEXP (pat, 0, i);
1384 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1385 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1388 /* Get the operand values and constraints out of the insn. */
1389 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1390 constraints, operand_mode, NULL);
1392 /* For every operand, see what registers are allowed. */
1393 for (i = 0; i < noperands; i++)
1395 const char *p = constraints[i];
1396 /* For every alternative, we compute the class of registers allowed
1397 for reloading in CLS, and merge its contents into the reg set
1399 int cls = (int) NO_REGS;
1405 if (c == '\0' || c == ',' || c == '#')
1407 /* End of one alternative - mark the regs in the current
1408 class, and reset the class. */
1409 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1415 } while (c != '\0' && c != ',');
1424 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1428 enum constraint_num cn = lookup_constraint (p);
1429 if (insn_extra_address_constraint (cn))
1430 cls = (int) reg_class_subunion[cls]
1431 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1434 cls = (int) reg_class_subunion[cls]
1435 [reg_class_for_constraint (cn)];
1438 p += CONSTRAINT_LEN (c, p);
1441 /* Those of the registers which are clobbered, but allowed by the
1442 constraints, must be usable as reload registers. So clear them
1443 out of the life information. */
1444 AND_HARD_REG_SET (allowed, clobbered);
1445 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1446 if (TEST_HARD_REG_BIT (allowed, i))
1448 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1449 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1456 /* Copy the global variables n_reloads and rld into the corresponding elts
1459 copy_reloads (struct insn_chain *chain)
1461 chain->n_reloads = n_reloads;
1462 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1463 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1464 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1467 /* Walk the chain of insns, and determine for each whether it needs reloads
1468 and/or eliminations. Build the corresponding insns_need_reload list, and
1469 set something_needs_elimination as appropriate. */
1471 calculate_needs_all_insns (int global)
1473 struct insn_chain **pprev_reload = &insns_need_reload;
1474 struct insn_chain *chain, *next = 0;
1476 something_needs_elimination = 0;
1478 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1479 for (chain = reload_insn_chain; chain != 0; chain = next)
1481 rtx_insn *insn = chain->insn;
1485 /* Clear out the shortcuts. */
1486 chain->n_reloads = 0;
1487 chain->need_elim = 0;
1488 chain->need_reload = 0;
1489 chain->need_operand_change = 0;
1491 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1492 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1493 what effects this has on the known offsets at labels. */
1495 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1496 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1497 set_label_offsets (insn, insn, 0);
1501 rtx old_body = PATTERN (insn);
1502 int old_code = INSN_CODE (insn);
1503 rtx old_notes = REG_NOTES (insn);
1504 int did_elimination = 0;
1505 int operands_changed = 0;
1507 /* Skip insns that only set an equivalence. */
1508 if (will_delete_init_insn_p (insn))
1511 /* If needed, eliminate any eliminable registers. */
1512 if (num_eliminable || num_eliminable_invariants)
1513 did_elimination = eliminate_regs_in_insn (insn, 0);
1515 /* Analyze the instruction. */
1516 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1517 global, spill_reg_order);
1519 /* If a no-op set needs more than one reload, this is likely
1520 to be something that needs input address reloads. We
1521 can't get rid of this cleanly later, and it is of no use
1522 anyway, so discard it now.
1523 We only do this when expensive_optimizations is enabled,
1524 since this complements reload inheritance / output
1525 reload deletion, and it can make debugging harder. */
1526 if (flag_expensive_optimizations && n_reloads > 1)
1528 rtx set = single_set (insn);
1531 ((SET_SRC (set) == SET_DEST (set)
1532 && REG_P (SET_SRC (set))
1533 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1534 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1535 && reg_renumber[REGNO (SET_SRC (set))] < 0
1536 && reg_renumber[REGNO (SET_DEST (set))] < 0
1537 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1538 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1539 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1540 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1542 if (ira_conflicts_p)
1543 /* Inform IRA about the insn deletion. */
1544 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1545 REGNO (SET_SRC (set)));
1547 /* Delete it from the reload chain. */
1549 chain->prev->next = next;
1551 reload_insn_chain = next;
1553 next->prev = chain->prev;
1554 chain->next = unused_insn_chains;
1555 unused_insn_chains = chain;
1560 update_eliminable_offsets ();
1562 /* Remember for later shortcuts which insns had any reloads or
1563 register eliminations. */
1564 chain->need_elim = did_elimination;
1565 chain->need_reload = n_reloads > 0;
1566 chain->need_operand_change = operands_changed;
1568 /* Discard any register replacements done. */
1569 if (did_elimination)
1571 obstack_free (&reload_obstack, reload_insn_firstobj);
1572 PATTERN (insn) = old_body;
1573 INSN_CODE (insn) = old_code;
1574 REG_NOTES (insn) = old_notes;
1575 something_needs_elimination = 1;
1578 something_needs_operands_changed |= operands_changed;
1582 copy_reloads (chain);
1583 *pprev_reload = chain;
1584 pprev_reload = &chain->next_need_reload;
1591 /* This function is called from the register allocator to set up estimates
1592 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1593 an invariant. The structure is similar to calculate_needs_all_insns. */
1596 calculate_elim_costs_all_insns (void)
1598 int *reg_equiv_init_cost;
1602 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1604 init_eliminable_invariants (get_insns (), false);
1606 set_initial_elim_offsets ();
1607 set_initial_label_offsets ();
1609 FOR_EACH_BB_FN (bb, cfun)
1614 FOR_BB_INSNS (bb, insn)
1616 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1617 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1618 what effects this has on the known offsets at labels. */
1620 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1621 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1622 set_label_offsets (insn, insn, 0);
1626 rtx set = single_set (insn);
1628 /* Skip insns that only set an equivalence. */
1629 if (set && REG_P (SET_DEST (set))
1630 && reg_renumber[REGNO (SET_DEST (set))] < 0
1631 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1632 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1634 unsigned regno = REGNO (SET_DEST (set));
1635 rtx_insn_list *init = reg_equiv_init (regno);
1638 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1640 machine_mode mode = GET_MODE (SET_DEST (set));
1641 int cost = set_src_cost (t, mode,
1642 optimize_bb_for_speed_p (bb));
1643 int freq = REG_FREQ_FROM_BB (bb);
1645 reg_equiv_init_cost[regno] = cost * freq;
1649 /* If needed, eliminate any eliminable registers. */
1650 if (num_eliminable || num_eliminable_invariants)
1651 elimination_costs_in_insn (insn);
1654 update_eliminable_offsets ();
1658 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1660 if (reg_equiv_invariant (i))
1662 if (reg_equiv_init (i))
1664 int cost = reg_equiv_init_cost[i];
1667 "Reg %d has equivalence, initial gains %d\n", i, cost);
1669 ira_adjust_equiv_reg_cost (i, cost);
1675 "Reg %d had equivalence, but can't be eliminated\n",
1677 ira_adjust_equiv_reg_cost (i, 0);
1682 free (reg_equiv_init_cost);
1683 free (offsets_known_at);
1686 offsets_known_at = NULL;
1689 /* Comparison function for qsort to decide which of two reloads
1690 should be handled first. *P1 and *P2 are the reload numbers. */
1693 reload_reg_class_lower (const void *r1p, const void *r2p)
1695 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1698 /* Consider required reloads before optional ones. */
1699 t = rld[r1].optional - rld[r2].optional;
1703 /* Count all solitary classes before non-solitary ones. */
1704 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1705 - (reg_class_size[(int) rld[r1].rclass] == 1));
1709 /* Aside from solitaires, consider all multi-reg groups first. */
1710 t = rld[r2].nregs - rld[r1].nregs;
1714 /* Consider reloads in order of increasing reg-class number. */
1715 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1719 /* If reloads are equally urgent, sort by reload number,
1720 so that the results of qsort leave nothing to chance. */
1724 /* The cost of spilling each hard reg. */
1725 static int spill_cost[FIRST_PSEUDO_REGISTER];
1727 /* When spilling multiple hard registers, we use SPILL_COST for the first
1728 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1729 only the first hard reg for a multi-reg pseudo. */
1730 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1732 /* Map of hard regno to pseudo regno currently occupying the hard
1734 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1736 /* Update the spill cost arrays, considering that pseudo REG is live. */
1739 count_pseudo (int reg)
1741 int freq = REG_FREQ (reg);
1742 int r = reg_renumber[reg];
1745 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1746 if (ira_conflicts_p && r < 0)
1749 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1750 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1753 SET_REGNO_REG_SET (&pseudos_counted, reg);
1755 gcc_assert (r >= 0);
1757 spill_add_cost[r] += freq;
1758 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1761 hard_regno_to_pseudo_regno[r + nregs] = reg;
1762 spill_cost[r + nregs] += freq;
1766 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1767 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1770 order_regs_for_reload (struct insn_chain *chain)
1773 HARD_REG_SET used_by_pseudos;
1774 HARD_REG_SET used_by_pseudos2;
1775 reg_set_iterator rsi;
1777 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1779 memset (spill_cost, 0, sizeof spill_cost);
1780 memset (spill_add_cost, 0, sizeof spill_add_cost);
1781 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1782 hard_regno_to_pseudo_regno[i] = -1;
1784 /* Count number of uses of each hard reg by pseudo regs allocated to it
1785 and then order them by decreasing use. First exclude hard registers
1786 that are live in or across this insn. */
1788 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1790 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1791 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1793 /* Now find out which pseudos are allocated to it, and update
1795 CLEAR_REG_SET (&pseudos_counted);
1797 EXECUTE_IF_SET_IN_REG_SET
1798 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1802 EXECUTE_IF_SET_IN_REG_SET
1803 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1807 CLEAR_REG_SET (&pseudos_counted);
1810 /* Vector of reload-numbers showing the order in which the reloads should
1812 static short reload_order[MAX_RELOADS];
1814 /* This is used to keep track of the spill regs used in one insn. */
1815 static HARD_REG_SET used_spill_regs_local;
1817 /* We decided to spill hard register SPILLED, which has a size of
1818 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1819 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1820 update SPILL_COST/SPILL_ADD_COST. */
1823 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1825 int freq = REG_FREQ (reg);
1826 int r = reg_renumber[reg];
1829 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1830 if (ira_conflicts_p && r < 0)
1833 gcc_assert (r >= 0);
1835 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1837 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1838 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1841 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1843 spill_add_cost[r] -= freq;
1846 hard_regno_to_pseudo_regno[r + nregs] = -1;
1847 spill_cost[r + nregs] -= freq;
1851 /* Find reload register to use for reload number ORDER. */
1854 find_reg (struct insn_chain *chain, int order)
1856 int rnum = reload_order[order];
1857 struct reload *rl = rld + rnum;
1858 int best_cost = INT_MAX;
1860 unsigned int i, j, n;
1862 HARD_REG_SET not_usable;
1863 HARD_REG_SET used_by_other_reload;
1864 reg_set_iterator rsi;
1865 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1866 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1868 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1869 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1870 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1872 CLEAR_HARD_REG_SET (used_by_other_reload);
1873 for (k = 0; k < order; k++)
1875 int other = reload_order[k];
1877 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1878 for (j = 0; j < rld[other].nregs; j++)
1879 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1882 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1884 #ifdef REG_ALLOC_ORDER
1885 unsigned int regno = reg_alloc_order[i];
1887 unsigned int regno = i;
1890 if (! TEST_HARD_REG_BIT (not_usable, regno)
1891 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1892 && HARD_REGNO_MODE_OK (regno, rl->mode))
1894 int this_cost = spill_cost[regno];
1896 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1898 for (j = 1; j < this_nregs; j++)
1900 this_cost += spill_add_cost[regno + j];
1901 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1902 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1908 if (ira_conflicts_p)
1910 /* Ask IRA to find a better pseudo-register for
1912 for (n = j = 0; j < this_nregs; j++)
1914 int r = hard_regno_to_pseudo_regno[regno + j];
1918 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1919 regno_pseudo_regs[n++] = r;
1921 regno_pseudo_regs[n++] = -1;
1923 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1924 best_regno_pseudo_regs,
1931 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1932 if (regno_pseudo_regs[j] < 0)
1939 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1941 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1943 if (this_cost < best_cost
1944 /* Among registers with equal cost, prefer caller-saved ones, or
1945 use REG_ALLOC_ORDER if it is defined. */
1946 || (this_cost == best_cost
1947 #ifdef REG_ALLOC_ORDER
1948 && (inv_reg_alloc_order[regno]
1949 < inv_reg_alloc_order[best_reg])
1951 && call_used_regs[regno]
1952 && ! call_used_regs[best_reg]
1957 best_cost = this_cost;
1965 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1967 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1968 rl->regno = best_reg;
1970 EXECUTE_IF_SET_IN_REG_SET
1971 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1973 count_spilled_pseudo (best_reg, rl->nregs, j);
1976 EXECUTE_IF_SET_IN_REG_SET
1977 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1979 count_spilled_pseudo (best_reg, rl->nregs, j);
1982 for (i = 0; i < rl->nregs; i++)
1984 gcc_assert (spill_cost[best_reg + i] == 0);
1985 gcc_assert (spill_add_cost[best_reg + i] == 0);
1986 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1987 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1992 /* Find more reload regs to satisfy the remaining need of an insn, which
1994 Do it by ascending class number, since otherwise a reg
1995 might be spilled for a big class and might fail to count
1996 for a smaller class even though it belongs to that class. */
1999 find_reload_regs (struct insn_chain *chain)
2003 /* In order to be certain of getting the registers we need,
2004 we must sort the reloads into order of increasing register class.
2005 Then our grabbing of reload registers will parallel the process
2006 that provided the reload registers. */
2007 for (i = 0; i < chain->n_reloads; i++)
2009 /* Show whether this reload already has a hard reg. */
2010 if (chain->rld[i].reg_rtx)
2012 int regno = REGNO (chain->rld[i].reg_rtx);
2013 chain->rld[i].regno = regno;
2015 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2018 chain->rld[i].regno = -1;
2019 reload_order[i] = i;
2022 n_reloads = chain->n_reloads;
2023 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2025 CLEAR_HARD_REG_SET (used_spill_regs_local);
2028 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2030 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2032 /* Compute the order of preference for hard registers to spill. */
2034 order_regs_for_reload (chain);
2036 for (i = 0; i < n_reloads; i++)
2038 int r = reload_order[i];
2040 /* Ignore reloads that got marked inoperative. */
2041 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2042 && ! rld[r].optional
2043 && rld[r].regno == -1)
2044 if (! find_reg (chain, i))
2047 fprintf (dump_file, "reload failure for reload %d\n", r);
2048 spill_failure (chain->insn, rld[r].rclass);
2054 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2055 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2057 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2061 select_reload_regs (void)
2063 struct insn_chain *chain;
2065 /* Try to satisfy the needs for each insn. */
2066 for (chain = insns_need_reload; chain != 0;
2067 chain = chain->next_need_reload)
2068 find_reload_regs (chain);
2071 /* Delete all insns that were inserted by emit_caller_save_insns during
2074 delete_caller_save_insns (void)
2076 struct insn_chain *c = reload_insn_chain;
2080 while (c != 0 && c->is_caller_save_insn)
2082 struct insn_chain *next = c->next;
2083 rtx_insn *insn = c->insn;
2085 if (c == reload_insn_chain)
2086 reload_insn_chain = next;
2090 next->prev = c->prev;
2092 c->prev->next = next;
2093 c->next = unused_insn_chains;
2094 unused_insn_chains = c;
2102 /* Handle the failure to find a register to spill.
2103 INSN should be one of the insns which needed this particular spill reg. */
2106 spill_failure (rtx_insn *insn, enum reg_class rclass)
2108 if (asm_noperands (PATTERN (insn)) >= 0)
2109 error_for_asm (insn, "can%'t find a register in class %qs while "
2110 "reloading %<asm%>",
2111 reg_class_names[rclass]);
2114 error ("unable to find a register to spill in class %qs",
2115 reg_class_names[rclass]);
2119 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2120 debug_reload_to_stream (dump_file);
2122 fatal_insn ("this is the insn:", insn);
2126 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2127 data that is dead in INSN. */
2130 delete_dead_insn (rtx_insn *insn)
2132 rtx_insn *prev = prev_active_insn (insn);
2135 /* If the previous insn sets a register that dies in our insn make
2136 a note that we want to run DCE immediately after reload.
2138 We used to delete the previous insn & recurse, but that's wrong for
2139 block local equivalences. Instead of trying to figure out the exact
2140 circumstances where we can delete the potentially dead insns, just
2141 let DCE do the job. */
2142 if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2143 && GET_CODE (PATTERN (prev)) == SET
2144 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2145 && reg_mentioned_p (prev_dest, PATTERN (insn))
2146 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2147 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2150 SET_INSN_DELETED (insn);
2153 /* Modify the home of pseudo-reg I.
2154 The new home is present in reg_renumber[I].
2156 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2157 or it may be -1, meaning there is none or it is not relevant.
2158 This is used so that all pseudos spilled from a given hard reg
2159 can share one stack slot. */
2162 alter_reg (int i, int from_reg, bool dont_share_p)
2164 /* When outputting an inline function, this can happen
2165 for a reg that isn't actually used. */
2166 if (regno_reg_rtx[i] == 0)
2169 /* If the reg got changed to a MEM at rtl-generation time,
2171 if (!REG_P (regno_reg_rtx[i]))
2174 /* Modify the reg-rtx to contain the new hard reg
2175 number or else to contain its pseudo reg number. */
2176 SET_REGNO (regno_reg_rtx[i],
2177 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2179 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2180 allocate a stack slot for it. */
2182 if (reg_renumber[i] < 0
2183 && REG_N_REFS (i) > 0
2184 && reg_equiv_constant (i) == 0
2185 && (reg_equiv_invariant (i) == 0
2186 || reg_equiv_init (i) == 0)
2187 && reg_equiv_memory_loc (i) == 0)
2190 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2191 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2192 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2193 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2194 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2197 something_was_spilled = true;
2199 if (ira_conflicts_p)
2201 /* Mark the spill for IRA. */
2202 SET_REGNO_REG_SET (&spilled_pseudos, i);
2204 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2210 /* Each pseudo reg has an inherent size which comes from its own mode,
2211 and a total size which provides room for paradoxical subregs
2212 which refer to the pseudo reg in wider modes.
2214 We can use a slot already allocated if it provides both
2215 enough inherent space and enough total space.
2216 Otherwise, we allocate a new slot, making sure that it has no less
2217 inherent space, and no less total space, then the previous slot. */
2218 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2222 /* No known place to spill from => no slot to reuse. */
2223 x = assign_stack_local (mode, total_size,
2224 min_align > inherent_align
2225 || total_size > inherent_size ? -1 : 0);
2229 /* Cancel the big-endian correction done in assign_stack_local.
2230 Get the address of the beginning of the slot. This is so we
2231 can do a big-endian correction unconditionally below. */
2232 if (BYTES_BIG_ENDIAN)
2234 adjust = inherent_size - total_size;
2237 = adjust_address_nv (x, mode_for_size (total_size
2243 if (! dont_share_p && ira_conflicts_p)
2244 /* Inform IRA about allocation a new stack slot. */
2245 ira_mark_new_stack_slot (stack_slot, i, total_size);
2248 /* Reuse a stack slot if possible. */
2249 else if (spill_stack_slot[from_reg] != 0
2250 && spill_stack_slot_width[from_reg] >= total_size
2251 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2253 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2254 x = spill_stack_slot[from_reg];
2256 /* Allocate a bigger slot. */
2259 /* Compute maximum size needed, both for inherent size
2260 and for total size. */
2263 if (spill_stack_slot[from_reg])
2265 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2267 mode = GET_MODE (spill_stack_slot[from_reg]);
2268 if (spill_stack_slot_width[from_reg] > total_size)
2269 total_size = spill_stack_slot_width[from_reg];
2270 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2271 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2274 /* Make a slot with that size. */
2275 x = assign_stack_local (mode, total_size,
2276 min_align > inherent_align
2277 || total_size > inherent_size ? -1 : 0);
2280 /* Cancel the big-endian correction done in assign_stack_local.
2281 Get the address of the beginning of the slot. This is so we
2282 can do a big-endian correction unconditionally below. */
2283 if (BYTES_BIG_ENDIAN)
2285 adjust = GET_MODE_SIZE (mode) - total_size;
2288 = adjust_address_nv (x, mode_for_size (total_size
2294 spill_stack_slot[from_reg] = stack_slot;
2295 spill_stack_slot_width[from_reg] = total_size;
2298 /* On a big endian machine, the "address" of the slot
2299 is the address of the low part that fits its inherent mode. */
2300 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2301 adjust += (total_size - inherent_size);
2303 /* If we have any adjustment to make, or if the stack slot is the
2304 wrong mode, make a new stack slot. */
2305 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2307 /* Set all of the memory attributes as appropriate for a spill. */
2308 set_mem_attrs_for_spill (x);
2310 /* Save the stack slot for later. */
2311 reg_equiv_memory_loc (i) = x;
2315 /* Mark the slots in regs_ever_live for the hard regs used by
2316 pseudo-reg number REGNO, accessed in MODE. */
2319 mark_home_live_1 (int regno, machine_mode mode)
2323 i = reg_renumber[regno];
2326 lim = end_hard_regno (mode, i);
2328 df_set_regs_ever_live (i++, true);
2331 /* Mark the slots in regs_ever_live for the hard regs
2332 used by pseudo-reg number REGNO. */
2335 mark_home_live (int regno)
2337 if (reg_renumber[regno] >= 0)
2338 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2341 /* This function handles the tracking of elimination offsets around branches.
2343 X is a piece of RTL being scanned.
2345 INSN is the insn that it came from, if any.
2347 INITIAL_P is nonzero if we are to set the offset to be the initial
2348 offset and zero if we are setting the offset of the label to be the
2352 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2354 enum rtx_code code = GET_CODE (x);
2357 struct elim_table *p;
2362 if (LABEL_REF_NONLOCAL_P (x))
2365 x = LABEL_REF_LABEL (x);
2367 /* ... fall through ... */
2370 /* If we know nothing about this label, set the desired offsets. Note
2371 that this sets the offset at a label to be the offset before a label
2372 if we don't know anything about the label. This is not correct for
2373 the label after a BARRIER, but is the best guess we can make. If
2374 we guessed wrong, we will suppress an elimination that might have
2375 been possible had we been able to guess correctly. */
2377 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2379 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2380 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2381 = (initial_p ? reg_eliminate[i].initial_offset
2382 : reg_eliminate[i].offset);
2383 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2386 /* Otherwise, if this is the definition of a label and it is
2387 preceded by a BARRIER, set our offsets to the known offset of
2391 && (tem = prev_nonnote_insn (insn)) != 0
2393 set_offsets_for_label (insn);
2395 /* If neither of the above cases is true, compare each offset
2396 with those previously recorded and suppress any eliminations
2397 where the offsets disagree. */
2399 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2400 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2401 != (initial_p ? reg_eliminate[i].initial_offset
2402 : reg_eliminate[i].offset))
2403 reg_eliminate[i].can_eliminate = 0;
2407 case JUMP_TABLE_DATA:
2408 set_label_offsets (PATTERN (insn), insn, initial_p);
2412 set_label_offsets (PATTERN (insn), insn, initial_p);
2414 /* ... fall through ... */
2418 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2419 to indirectly and hence must have all eliminations at their
2421 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2422 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2423 set_label_offsets (XEXP (tem, 0), insn, 1);
2429 /* Each of the labels in the parallel or address vector must be
2430 at their initial offsets. We want the first field for PARALLEL
2431 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2433 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2434 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2439 /* We only care about setting PC. If the source is not RETURN,
2440 IF_THEN_ELSE, or a label, disable any eliminations not at
2441 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2442 isn't one of those possibilities. For branches to a label,
2443 call ourselves recursively.
2445 Note that this can disable elimination unnecessarily when we have
2446 a non-local goto since it will look like a non-constant jump to
2447 someplace in the current function. This isn't a significant
2448 problem since such jumps will normally be when all elimination
2449 pairs are back to their initial offsets. */
2451 if (SET_DEST (x) != pc_rtx)
2454 switch (GET_CODE (SET_SRC (x)))
2461 set_label_offsets (SET_SRC (x), insn, initial_p);
2465 tem = XEXP (SET_SRC (x), 1);
2466 if (GET_CODE (tem) == LABEL_REF)
2467 set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2468 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2471 tem = XEXP (SET_SRC (x), 2);
2472 if (GET_CODE (tem) == LABEL_REF)
2473 set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2474 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2482 /* If we reach here, all eliminations must be at their initial
2483 offset because we are doing a jump to a variable address. */
2484 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2485 if (p->offset != p->initial_offset)
2486 p->can_eliminate = 0;
2494 /* This function examines every reg that occurs in X and adjusts the
2495 costs for its elimination which are gathered by IRA. INSN is the
2496 insn in which X occurs. We do not recurse into MEM expressions. */
2499 note_reg_elim_costly (const_rtx x, rtx insn)
2501 subrtx_iterator::array_type array;
2502 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2504 const_rtx x = *iter;
2506 iter.skip_subrtxes ();
2508 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2509 && reg_equiv_init (REGNO (x))
2510 && reg_equiv_invariant (REGNO (x)))
2512 rtx t = reg_equiv_invariant (REGNO (x));
2513 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2514 int cost = set_src_cost (new_rtx, Pmode,
2515 optimize_bb_for_speed_p (elim_bb));
2516 int freq = REG_FREQ_FROM_BB (elim_bb);
2519 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2524 /* Scan X and replace any eliminable registers (such as fp) with a
2525 replacement (such as sp), plus an offset.
2527 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2528 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2529 MEM, we are allowed to replace a sum of a register and the constant zero
2530 with the register, which we cannot do outside a MEM. In addition, we need
2531 to record the fact that a register is referenced outside a MEM.
2533 If INSN is an insn, it is the insn containing X. If we replace a REG
2534 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2535 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2536 the REG is being modified.
2538 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2539 That's used when we eliminate in expressions stored in notes.
2540 This means, do not set ref_outside_mem even if the reference
2543 If FOR_COSTS is true, we are being called before reload in order to
2544 estimate the costs of keeping registers with an equivalence unallocated.
2546 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2547 replacements done assuming all offsets are at their initial values. If
2548 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2549 encounter, return the actual location so that find_reloads will do
2550 the proper thing. */
2553 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2554 bool may_use_invariant, bool for_costs)
2556 enum rtx_code code = GET_CODE (x);
2557 struct elim_table *ep;
2564 if (! current_function_decl)
2584 /* First handle the case where we encounter a bare register that
2585 is eliminable. Replace it with a PLUS. */
2586 if (regno < FIRST_PSEUDO_REGISTER)
2588 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2590 if (ep->from_rtx == x && ep->can_eliminate)
2591 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2594 else if (reg_renumber && reg_renumber[regno] < 0
2596 && reg_equiv_invariant (regno))
2598 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2599 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2600 mem_mode, insn, true, for_costs);
2601 /* There exists at least one use of REGNO that cannot be
2602 eliminated. Prevent the defining insn from being deleted. */
2603 reg_equiv_init (regno) = NULL;
2605 alter_reg (regno, -1, true);
2609 /* You might think handling MINUS in a manner similar to PLUS is a
2610 good idea. It is not. It has been tried multiple times and every
2611 time the change has had to have been reverted.
2613 Other parts of reload know a PLUS is special (gen_reload for example)
2614 and require special code to handle code a reloaded PLUS operand.
2616 Also consider backends where the flags register is clobbered by a
2617 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2618 lea instruction comes to mind). If we try to reload a MINUS, we
2619 may kill the flags register that was holding a useful value.
2621 So, please before trying to handle MINUS, consider reload as a
2622 whole instead of this little section as well as the backend issues. */
2624 /* If this is the sum of an eliminable register and a constant, rework
2626 if (REG_P (XEXP (x, 0))
2627 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2628 && CONSTANT_P (XEXP (x, 1)))
2630 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2632 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2634 /* The only time we want to replace a PLUS with a REG (this
2635 occurs when the constant operand of the PLUS is the negative
2636 of the offset) is when we are inside a MEM. We won't want
2637 to do so at other times because that would change the
2638 structure of the insn in a way that reload can't handle.
2639 We special-case the commonest situation in
2640 eliminate_regs_in_insn, so just replace a PLUS with a
2641 PLUS here, unless inside a MEM. */
2642 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2643 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2646 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2647 plus_constant (Pmode, XEXP (x, 1),
2648 ep->previous_offset));
2651 /* If the register is not eliminable, we are done since the other
2652 operand is a constant. */
2656 /* If this is part of an address, we want to bring any constant to the
2657 outermost PLUS. We will do this by doing register replacement in
2658 our operands and seeing if a constant shows up in one of them.
2660 Note that there is no risk of modifying the structure of the insn,
2661 since we only get called for its operands, thus we are either
2662 modifying the address inside a MEM, or something like an address
2663 operand of a load-address insn. */
2666 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2668 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2671 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2673 /* If one side is a PLUS and the other side is a pseudo that
2674 didn't get a hard register but has a reg_equiv_constant,
2675 we must replace the constant here since it may no longer
2676 be in the position of any operand. */
2677 if (GET_CODE (new0) == PLUS && REG_P (new1)
2678 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2679 && reg_renumber[REGNO (new1)] < 0
2681 && reg_equiv_constant (REGNO (new1)) != 0)
2682 new1 = reg_equiv_constant (REGNO (new1));
2683 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2684 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2685 && reg_renumber[REGNO (new0)] < 0
2686 && reg_equiv_constant (REGNO (new0)) != 0)
2687 new0 = reg_equiv_constant (REGNO (new0));
2689 new_rtx = form_sum (GET_MODE (x), new0, new1);
2691 /* As above, if we are not inside a MEM we do not want to
2692 turn a PLUS into something else. We might try to do so here
2693 for an addition of 0 if we aren't optimizing. */
2694 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2695 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2703 /* If this is the product of an eliminable register and a
2704 constant, apply the distribute law and move the constant out
2705 so that we have (plus (mult ..) ..). This is needed in order
2706 to keep load-address insns valid. This case is pathological.
2707 We ignore the possibility of overflow here. */
2708 if (REG_P (XEXP (x, 0))
2709 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2710 && CONST_INT_P (XEXP (x, 1)))
2711 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2713 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2716 /* Refs inside notes or in DEBUG_INSNs don't count for
2718 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2719 || GET_CODE (insn) == INSN_LIST
2720 || DEBUG_INSN_P (insn))))
2721 ep->ref_outside_mem = 1;
2724 plus_constant (Pmode,
2725 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2726 ep->previous_offset * INTVAL (XEXP (x, 1)));
2729 /* ... fall through ... */
2733 /* See comments before PLUS about handling MINUS. */
2735 case DIV: case UDIV:
2736 case MOD: case UMOD:
2737 case AND: case IOR: case XOR:
2738 case ROTATERT: case ROTATE:
2739 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2741 case GE: case GT: case GEU: case GTU:
2742 case LE: case LT: case LEU: case LTU:
2744 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2746 rtx new1 = XEXP (x, 1)
2747 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2750 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2751 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2756 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2759 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2761 if (new_rtx != XEXP (x, 0))
2763 /* If this is a REG_DEAD note, it is not valid anymore.
2764 Using the eliminated version could result in creating a
2765 REG_DEAD note for the stack or frame pointer. */
2766 if (REG_NOTE_KIND (x) == REG_DEAD)
2768 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2772 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2776 /* ... fall through ... */
2780 /* Now do eliminations in the rest of the chain. If this was
2781 an EXPR_LIST, this might result in allocating more memory than is
2782 strictly needed, but it simplifies the code. */
2785 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2787 if (new_rtx != XEXP (x, 1))
2789 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2797 /* We do not support elimination of a register that is modified.
2798 elimination_effects has already make sure that this does not
2804 /* We do not support elimination of a register that is modified.
2805 elimination_effects has already make sure that this does not
2806 happen. The only remaining case we need to consider here is
2807 that the increment value may be an eliminable register. */
2808 if (GET_CODE (XEXP (x, 1)) == PLUS
2809 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2811 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2812 insn, true, for_costs);
2814 if (new_rtx != XEXP (XEXP (x, 1), 1))
2815 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2816 gen_rtx_PLUS (GET_MODE (x),
2817 XEXP (x, 0), new_rtx));
2821 case STRICT_LOW_PART:
2823 case SIGN_EXTEND: case ZERO_EXTEND:
2824 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2825 case FLOAT: case FIX:
2826 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2835 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2837 if (new_rtx != XEXP (x, 0))
2838 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2842 /* Similar to above processing, but preserve SUBREG_BYTE.
2843 Convert (subreg (mem)) to (mem) if not paradoxical.
2844 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2845 pseudo didn't get a hard reg, we must replace this with the
2846 eliminated version of the memory location because push_reload
2847 may do the replacement in certain circumstances. */
2848 if (REG_P (SUBREG_REG (x))
2849 && !paradoxical_subreg_p (x)
2851 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2853 new_rtx = SUBREG_REG (x);
2856 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2858 if (new_rtx != SUBREG_REG (x))
2860 int x_size = GET_MODE_SIZE (GET_MODE (x));
2861 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2864 && ((x_size < new_size
2865 #if WORD_REGISTER_OPERATIONS
2866 /* On these machines, combine can create rtl of the form
2867 (set (subreg:m1 (reg:m2 R) 0) ...)
2868 where m1 < m2, and expects something interesting to
2869 happen to the entire word. Moreover, it will use the
2870 (reg:m2 R) later, expecting all bits to be preserved.
2871 So if the number of words is the same, preserve the
2872 subreg so that push_reload can see it. */
2873 && ! ((x_size - 1) / UNITS_PER_WORD
2874 == (new_size -1 ) / UNITS_PER_WORD)
2877 || x_size == new_size)
2879 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2881 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2887 /* Our only special processing is to pass the mode of the MEM to our
2888 recursive call and copy the flags. While we are here, handle this
2889 case more efficiently. */
2891 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2894 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2895 && !memory_address_p (GET_MODE (x), new_rtx))
2896 note_reg_elim_costly (XEXP (x, 0), insn);
2898 return replace_equiv_address_nv (x, new_rtx);
2901 /* Handle insn_list USE that a call to a pure function may generate. */
2902 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2904 if (new_rtx != XEXP (x, 0))
2905 return gen_rtx_USE (GET_MODE (x), new_rtx);
2910 gcc_assert (insn && DEBUG_INSN_P (insn));
2920 /* Process each of our operands recursively. If any have changed, make a
2922 fmt = GET_RTX_FORMAT (code);
2923 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2927 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2929 if (new_rtx != XEXP (x, i) && ! copied)
2931 x = shallow_copy_rtx (x);
2934 XEXP (x, i) = new_rtx;
2936 else if (*fmt == 'E')
2939 for (j = 0; j < XVECLEN (x, i); j++)
2941 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2943 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2945 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2949 x = shallow_copy_rtx (x);
2952 XVEC (x, i) = new_v;
2955 XVECEXP (x, i, j) = new_rtx;
2964 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2966 if (reg_eliminate == NULL)
2968 gcc_assert (targetm.no_register_allocation);
2971 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2974 /* Scan rtx X for modifications of elimination target registers. Update
2975 the table of eliminables to reflect the changed state. MEM_MODE is
2976 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2979 elimination_effects (rtx x, machine_mode mem_mode)
2981 enum rtx_code code = GET_CODE (x);
2982 struct elim_table *ep;
3004 /* First handle the case where we encounter a bare register that
3005 is eliminable. Replace it with a PLUS. */
3006 if (regno < FIRST_PSEUDO_REGISTER)
3008 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3010 if (ep->from_rtx == x && ep->can_eliminate)
3013 ep->ref_outside_mem = 1;
3018 else if (reg_renumber[regno] < 0
3020 && reg_equiv_constant (regno)
3021 && ! function_invariant_p (reg_equiv_constant (regno)))
3022 elimination_effects (reg_equiv_constant (regno), mem_mode);
3031 /* If we modify the source of an elimination rule, disable it. */
3032 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3033 if (ep->from_rtx == XEXP (x, 0))
3034 ep->can_eliminate = 0;
3036 /* If we modify the target of an elimination rule by adding a constant,
3037 update its offset. If we modify the target in any other way, we'll
3038 have to disable the rule as well. */
3039 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3040 if (ep->to_rtx == XEXP (x, 0))
3042 int size = GET_MODE_SIZE (mem_mode);
3044 /* If more bytes than MEM_MODE are pushed, account for them. */
3045 #ifdef PUSH_ROUNDING
3046 if (ep->to_rtx == stack_pointer_rtx)
3047 size = PUSH_ROUNDING (size);
3049 if (code == PRE_DEC || code == POST_DEC)
3051 else if (code == PRE_INC || code == POST_INC)
3053 else if (code == PRE_MODIFY || code == POST_MODIFY)
3055 if (GET_CODE (XEXP (x, 1)) == PLUS
3056 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3057 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3058 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3060 ep->can_eliminate = 0;
3064 /* These two aren't unary operators. */
3065 if (code == POST_MODIFY || code == PRE_MODIFY)
3068 /* Fall through to generic unary operation case. */
3069 case STRICT_LOW_PART:
3071 case SIGN_EXTEND: case ZERO_EXTEND:
3072 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3073 case FLOAT: case FIX:
3074 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3083 elimination_effects (XEXP (x, 0), mem_mode);
3087 if (REG_P (SUBREG_REG (x))
3088 && (GET_MODE_SIZE (GET_MODE (x))
3089 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3091 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3094 elimination_effects (SUBREG_REG (x), mem_mode);
3098 /* If using a register that is the source of an eliminate we still
3099 think can be performed, note it cannot be performed since we don't
3100 know how this register is used. */
3101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3102 if (ep->from_rtx == XEXP (x, 0))
3103 ep->can_eliminate = 0;
3105 elimination_effects (XEXP (x, 0), mem_mode);
3109 /* If clobbering a register that is the replacement register for an
3110 elimination we still think can be performed, note that it cannot
3111 be performed. Otherwise, we need not be concerned about it. */
3112 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3113 if (ep->to_rtx == XEXP (x, 0))
3114 ep->can_eliminate = 0;
3116 elimination_effects (XEXP (x, 0), mem_mode);
3120 /* Check for setting a register that we know about. */
3121 if (REG_P (SET_DEST (x)))
3123 /* See if this is setting the replacement register for an
3126 If DEST is the hard frame pointer, we do nothing because we
3127 assume that all assignments to the frame pointer are for
3128 non-local gotos and are being done at a time when they are valid
3129 and do not disturb anything else. Some machines want to
3130 eliminate a fake argument pointer (or even a fake frame pointer)
3131 with either the real frame or the stack pointer. Assignments to
3132 the hard frame pointer must not prevent this elimination. */
3134 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3136 if (ep->to_rtx == SET_DEST (x)
3137 && SET_DEST (x) != hard_frame_pointer_rtx)
3139 /* If it is being incremented, adjust the offset. Otherwise,
3140 this elimination can't be done. */
3141 rtx src = SET_SRC (x);
3143 if (GET_CODE (src) == PLUS
3144 && XEXP (src, 0) == SET_DEST (x)
3145 && CONST_INT_P (XEXP (src, 1)))
3146 ep->offset -= INTVAL (XEXP (src, 1));
3148 ep->can_eliminate = 0;
3152 elimination_effects (SET_DEST (x), VOIDmode);
3153 elimination_effects (SET_SRC (x), VOIDmode);
3157 /* Our only special processing is to pass the mode of the MEM to our
3159 elimination_effects (XEXP (x, 0), GET_MODE (x));
3166 fmt = GET_RTX_FORMAT (code);
3167 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3170 elimination_effects (XEXP (x, i), mem_mode);
3171 else if (*fmt == 'E')
3172 for (j = 0; j < XVECLEN (x, i); j++)
3173 elimination_effects (XVECEXP (x, i, j), mem_mode);
3177 /* Descend through rtx X and verify that no references to eliminable registers
3178 remain. If any do remain, mark the involved register as not
3182 check_eliminable_occurrences (rtx x)
3191 code = GET_CODE (x);
3193 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3195 struct elim_table *ep;
3197 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3198 if (ep->from_rtx == x)
3199 ep->can_eliminate = 0;
3203 fmt = GET_RTX_FORMAT (code);
3204 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3207 check_eliminable_occurrences (XEXP (x, i));
3208 else if (*fmt == 'E')
3211 for (j = 0; j < XVECLEN (x, i); j++)
3212 check_eliminable_occurrences (XVECEXP (x, i, j));
3217 /* Scan INSN and eliminate all eliminable registers in it.
3219 If REPLACE is nonzero, do the replacement destructively. Also
3220 delete the insn as dead it if it is setting an eliminable register.
3222 If REPLACE is zero, do all our allocations in reload_obstack.
3224 If no eliminations were done and this insn doesn't require any elimination
3225 processing (these are not identical conditions: it might be updating sp,
3226 but not referencing fp; this needs to be seen during reload_as_needed so
3227 that the offset between fp and sp can be taken into consideration), zero
3228 is returned. Otherwise, 1 is returned. */
3231 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3233 int icode = recog_memoized (insn);
3234 rtx old_body = PATTERN (insn);
3235 int insn_is_asm = asm_noperands (old_body) >= 0;
3236 rtx old_set = single_set (insn);
3240 rtx substed_operand[MAX_RECOG_OPERANDS];
3241 rtx orig_operand[MAX_RECOG_OPERANDS];
3242 struct elim_table *ep;
3243 rtx plus_src, plus_cst_src;
3245 if (! insn_is_asm && icode < 0)
3247 gcc_assert (DEBUG_INSN_P (insn)
3248 || GET_CODE (PATTERN (insn)) == USE
3249 || GET_CODE (PATTERN (insn)) == CLOBBER
3250 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3251 if (DEBUG_INSN_P (insn))
3252 INSN_VAR_LOCATION_LOC (insn)
3253 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3257 if (old_set != 0 && REG_P (SET_DEST (old_set))
3258 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3260 /* Check for setting an eliminable register. */
3261 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3262 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3264 /* If this is setting the frame pointer register to the
3265 hardware frame pointer register and this is an elimination
3266 that will be done (tested above), this insn is really
3267 adjusting the frame pointer downward to compensate for
3268 the adjustment done before a nonlocal goto. */
3269 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3270 && ep->from == FRAME_POINTER_REGNUM
3271 && ep->to == HARD_FRAME_POINTER_REGNUM)
3273 rtx base = SET_SRC (old_set);
3274 rtx_insn *base_insn = insn;
3275 HOST_WIDE_INT offset = 0;
3277 while (base != ep->to_rtx)
3279 rtx_insn *prev_insn;
3282 if (GET_CODE (base) == PLUS
3283 && CONST_INT_P (XEXP (base, 1)))
3285 offset += INTVAL (XEXP (base, 1));
3286 base = XEXP (base, 0);
3288 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3289 && (prev_set = single_set (prev_insn)) != 0
3290 && rtx_equal_p (SET_DEST (prev_set), base))
3292 base = SET_SRC (prev_set);
3293 base_insn = prev_insn;
3299 if (base == ep->to_rtx)
3301 rtx src = plus_constant (Pmode, ep->to_rtx,
3302 offset - ep->offset);
3304 new_body = old_body;
3307 new_body = copy_insn (old_body);
3308 if (REG_NOTES (insn))
3309 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3311 PATTERN (insn) = new_body;
3312 old_set = single_set (insn);
3314 /* First see if this insn remains valid when we
3315 make the change. If not, keep the INSN_CODE
3316 the same and let reload fit it up. */
3317 validate_change (insn, &SET_SRC (old_set), src, 1);
3318 validate_change (insn, &SET_DEST (old_set),
3320 if (! apply_change_group ())
3322 SET_SRC (old_set) = src;
3323 SET_DEST (old_set) = ep->to_rtx;
3331 /* In this case this insn isn't serving a useful purpose. We
3332 will delete it in reload_as_needed once we know that this
3333 elimination is, in fact, being done.
3335 If REPLACE isn't set, we can't delete this insn, but needn't
3336 process it since it won't be used unless something changes. */
3339 delete_dead_insn (insn);
3347 /* We allow one special case which happens to work on all machines we
3348 currently support: a single set with the source or a REG_EQUAL
3349 note being a PLUS of an eliminable register and a constant. */
3350 plus_src = plus_cst_src = 0;
3351 if (old_set && REG_P (SET_DEST (old_set)))
3353 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3354 plus_src = SET_SRC (old_set);
3355 /* First see if the source is of the form (plus (...) CST). */
3357 && CONST_INT_P (XEXP (plus_src, 1)))
3358 plus_cst_src = plus_src;
3359 else if (REG_P (SET_SRC (old_set))
3362 /* Otherwise, see if we have a REG_EQUAL note of the form
3363 (plus (...) CST). */
3365 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3367 if ((REG_NOTE_KIND (links) == REG_EQUAL
3368 || REG_NOTE_KIND (links) == REG_EQUIV)
3369 && GET_CODE (XEXP (links, 0)) == PLUS
3370 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3372 plus_cst_src = XEXP (links, 0);
3378 /* Check that the first operand of the PLUS is a hard reg or
3379 the lowpart subreg of one. */
3382 rtx reg = XEXP (plus_cst_src, 0);
3383 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3384 reg = SUBREG_REG (reg);
3386 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3392 rtx reg = XEXP (plus_cst_src, 0);
3393 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3395 if (GET_CODE (reg) == SUBREG)
3396 reg = SUBREG_REG (reg);
3398 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3399 if (ep->from_rtx == reg && ep->can_eliminate)
3401 rtx to_rtx = ep->to_rtx;
3402 offset += ep->offset;
3403 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3405 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3406 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3408 /* If we have a nonzero offset, and the source is already
3409 a simple REG, the following transformation would
3410 increase the cost of the insn by replacing a simple REG
3411 with (plus (reg sp) CST). So try only when we already
3412 had a PLUS before. */
3413 if (offset == 0 || plus_src)
3415 rtx new_src = plus_constant (GET_MODE (to_rtx),
3418 new_body = old_body;
3421 new_body = copy_insn (old_body);
3422 if (REG_NOTES (insn))
3423 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3425 PATTERN (insn) = new_body;
3426 old_set = single_set (insn);
3428 /* First see if this insn remains valid when we make the
3429 change. If not, try to replace the whole pattern with
3430 a simple set (this may help if the original insn was a
3431 PARALLEL that was only recognized as single_set due to
3432 REG_UNUSED notes). If this isn't valid either, keep
3433 the INSN_CODE the same and let reload fix it up. */
3434 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3436 rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3438 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3439 SET_SRC (old_set) = new_src;
3446 /* This can't have an effect on elimination offsets, so skip right
3452 /* Determine the effects of this insn on elimination offsets. */
3453 elimination_effects (old_body, VOIDmode);
3455 /* Eliminate all eliminable registers occurring in operands that
3456 can be handled by reload. */
3457 extract_insn (insn);
3458 for (i = 0; i < recog_data.n_operands; i++)
3460 orig_operand[i] = recog_data.operand[i];
3461 substed_operand[i] = recog_data.operand[i];
3463 /* For an asm statement, every operand is eliminable. */
3464 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3466 bool is_set_src, in_plus;
3468 /* Check for setting a register that we know about. */
3469 if (recog_data.operand_type[i] != OP_IN
3470 && REG_P (orig_operand[i]))
3472 /* If we are assigning to a register that can be eliminated, it
3473 must be as part of a PARALLEL, since the code above handles
3474 single SETs. We must indicate that we can no longer
3475 eliminate this reg. */
3476 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3478 if (ep->from_rtx == orig_operand[i])
3479 ep->can_eliminate = 0;
3482 /* Companion to the above plus substitution, we can allow
3483 invariants as the source of a plain move. */
3486 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3490 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3491 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3495 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3496 replace ? insn : NULL_RTX,
3497 is_set_src || in_plus, false);
3498 if (substed_operand[i] != orig_operand[i])
3500 /* Terminate the search in check_eliminable_occurrences at
3502 *recog_data.operand_loc[i] = 0;
3504 /* If an output operand changed from a REG to a MEM and INSN is an
3505 insn, write a CLOBBER insn. */
3506 if (recog_data.operand_type[i] != OP_IN
3507 && REG_P (orig_operand[i])
3508 && MEM_P (substed_operand[i])
3510 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3514 for (i = 0; i < recog_data.n_dups; i++)
3515 *recog_data.dup_loc[i]
3516 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3518 /* If any eliminable remain, they aren't eliminable anymore. */
3519 check_eliminable_occurrences (old_body);
3521 /* Substitute the operands; the new values are in the substed_operand
3523 for (i = 0; i < recog_data.n_operands; i++)
3524 *recog_data.operand_loc[i] = substed_operand[i];
3525 for (i = 0; i < recog_data.n_dups; i++)
3526 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3528 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3529 re-recognize the insn. We do this in case we had a simple addition
3530 but now can do this as a load-address. This saves an insn in this
3532 If re-recognition fails, the old insn code number will still be used,
3533 and some register operands may have changed into PLUS expressions.
3534 These will be handled by find_reloads by loading them into a register
3539 /* If we aren't replacing things permanently and we changed something,
3540 make another copy to ensure that all the RTL is new. Otherwise
3541 things can go wrong if find_reload swaps commutative operands
3542 and one is inside RTL that has been copied while the other is not. */
3543 new_body = old_body;
3546 new_body = copy_insn (old_body);
3547 if (REG_NOTES (insn))
3548 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3550 PATTERN (insn) = new_body;
3552 /* If we had a move insn but now we don't, rerecognize it. This will
3553 cause spurious re-recognition if the old move had a PARALLEL since
3554 the new one still will, but we can't call single_set without
3555 having put NEW_BODY into the insn and the re-recognition won't
3556 hurt in this rare case. */
3557 /* ??? Why this huge if statement - why don't we just rerecognize the
3561 && ((REG_P (SET_SRC (old_set))
3562 && (GET_CODE (new_body) != SET
3563 || !REG_P (SET_SRC (new_body))))
3564 /* If this was a load from or store to memory, compare
3565 the MEM in recog_data.operand to the one in the insn.
3566 If they are not equal, then rerecognize the insn. */
3568 && ((MEM_P (SET_SRC (old_set))
3569 && SET_SRC (old_set) != recog_data.operand[1])
3570 || (MEM_P (SET_DEST (old_set))
3571 && SET_DEST (old_set) != recog_data.operand[0])))
3572 /* If this was an add insn before, rerecognize. */
3573 || GET_CODE (SET_SRC (old_set)) == PLUS))
3575 int new_icode = recog (PATTERN (insn), insn, 0);
3577 INSN_CODE (insn) = new_icode;
3581 /* Restore the old body. If there were any changes to it, we made a copy
3582 of it while the changes were still in place, so we'll correctly return
3583 a modified insn below. */
3586 /* Restore the old body. */
3587 for (i = 0; i < recog_data.n_operands; i++)
3588 /* Restoring a top-level match_parallel would clobber the new_body
3589 we installed in the insn. */
3590 if (recog_data.operand_loc[i] != &PATTERN (insn))
3591 *recog_data.operand_loc[i] = orig_operand[i];
3592 for (i = 0; i < recog_data.n_dups; i++)
3593 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3596 /* Update all elimination pairs to reflect the status after the current
3597 insn. The changes we make were determined by the earlier call to
3598 elimination_effects.
3600 We also detect cases where register elimination cannot be done,
3601 namely, if a register would be both changed and referenced outside a MEM
3602 in the resulting insn since such an insn is often undefined and, even if
3603 not, we cannot know what meaning will be given to it. Note that it is
3604 valid to have a register used in an address in an insn that changes it
3605 (presumably with a pre- or post-increment or decrement).
3607 If anything changes, return nonzero. */
3609 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3611 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3612 ep->can_eliminate = 0;
3614 ep->ref_outside_mem = 0;
3616 if (ep->previous_offset != ep->offset)
3621 /* If we changed something, perform elimination in REG_NOTES. This is
3622 needed even when REPLACE is zero because a REG_DEAD note might refer
3623 to a register that we eliminate and could cause a different number
3624 of spill registers to be needed in the final reload pass than in
3626 if (val && REG_NOTES (insn) != 0)
3628 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3634 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3635 register allocator. INSN is the instruction we need to examine, we perform
3636 eliminations in its operands and record cases where eliminating a reg with
3637 an invariant equivalence would add extra cost. */
3639 #pragma GCC diagnostic push
3640 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3642 elimination_costs_in_insn (rtx_insn *insn)
3644 int icode = recog_memoized (insn);
3645 rtx old_body = PATTERN (insn);
3646 int insn_is_asm = asm_noperands (old_body) >= 0;
3647 rtx old_set = single_set (insn);
3649 rtx orig_operand[MAX_RECOG_OPERANDS];
3650 rtx orig_dup[MAX_RECOG_OPERANDS];
3651 struct elim_table *ep;
3652 rtx plus_src, plus_cst_src;
3655 if (! insn_is_asm && icode < 0)
3657 gcc_assert (DEBUG_INSN_P (insn)
3658 || GET_CODE (PATTERN (insn)) == USE
3659 || GET_CODE (PATTERN (insn)) == CLOBBER
3660 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3664 if (old_set != 0 && REG_P (SET_DEST (old_set))
3665 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3667 /* Check for setting an eliminable register. */
3668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3669 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3673 /* We allow one special case which happens to work on all machines we
3674 currently support: a single set with the source or a REG_EQUAL
3675 note being a PLUS of an eliminable register and a constant. */
3676 plus_src = plus_cst_src = 0;
3678 if (old_set && REG_P (SET_DEST (old_set)))
3681 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3682 plus_src = SET_SRC (old_set);
3683 /* First see if the source is of the form (plus (...) CST). */
3685 && CONST_INT_P (XEXP (plus_src, 1)))
3686 plus_cst_src = plus_src;
3687 else if (REG_P (SET_SRC (old_set))
3690 /* Otherwise, see if we have a REG_EQUAL note of the form
3691 (plus (...) CST). */
3693 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3695 if ((REG_NOTE_KIND (links) == REG_EQUAL
3696 || REG_NOTE_KIND (links) == REG_EQUIV)
3697 && GET_CODE (XEXP (links, 0)) == PLUS
3698 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3700 plus_cst_src = XEXP (links, 0);
3707 /* Determine the effects of this insn on elimination offsets. */
3708 elimination_effects (old_body, VOIDmode);
3710 /* Eliminate all eliminable registers occurring in operands that
3711 can be handled by reload. */
3712 extract_insn (insn);
3713 int n_dups = recog_data.n_dups;
3714 for (i = 0; i < n_dups; i++)
3715 orig_dup[i] = *recog_data.dup_loc[i];
3717 int n_operands = recog_data.n_operands;
3718 for (i = 0; i < n_operands; i++)
3720 orig_operand[i] = recog_data.operand[i];
3722 /* For an asm statement, every operand is eliminable. */
3723 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3725 bool is_set_src, in_plus;
3727 /* Check for setting a register that we know about. */
3728 if (recog_data.operand_type[i] != OP_IN
3729 && REG_P (orig_operand[i]))
3731 /* If we are assigning to a register that can be eliminated, it
3732 must be as part of a PARALLEL, since the code above handles
3733 single SETs. We must indicate that we can no longer
3734 eliminate this reg. */
3735 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3737 if (ep->from_rtx == orig_operand[i])
3738 ep->can_eliminate = 0;
3741 /* Companion to the above plus substitution, we can allow
3742 invariants as the source of a plain move. */
3744 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3746 if (is_set_src && !sets_reg_p)
3747 note_reg_elim_costly (SET_SRC (old_set), insn);
3749 if (plus_src && sets_reg_p
3750 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3751 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3754 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3756 is_set_src || in_plus, true);
3757 /* Terminate the search in check_eliminable_occurrences at
3759 *recog_data.operand_loc[i] = 0;
3763 for (i = 0; i < n_dups; i++)
3764 *recog_data.dup_loc[i]
3765 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3767 /* If any eliminable remain, they aren't eliminable anymore. */
3768 check_eliminable_occurrences (old_body);
3770 /* Restore the old body. */
3771 for (i = 0; i < n_operands; i++)
3772 *recog_data.operand_loc[i] = orig_operand[i];
3773 for (i = 0; i < n_dups; i++)
3774 *recog_data.dup_loc[i] = orig_dup[i];
3776 /* Update all elimination pairs to reflect the status after the current
3777 insn. The changes we make were determined by the earlier call to
3778 elimination_effects. */
3780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3782 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3783 ep->can_eliminate = 0;
3785 ep->ref_outside_mem = 0;
3790 #pragma GCC diagnostic pop
3792 /* Loop through all elimination pairs.
3793 Recalculate the number not at initial offset.
3795 Compute the maximum offset (minimum offset if the stack does not
3796 grow downward) for each elimination pair. */
3799 update_eliminable_offsets (void)
3801 struct elim_table *ep;
3803 num_not_at_initial_offset = 0;
3804 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3806 ep->previous_offset = ep->offset;
3807 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3808 num_not_at_initial_offset++;
3812 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3813 replacement we currently believe is valid, mark it as not eliminable if X
3814 modifies DEST in any way other than by adding a constant integer to it.
3816 If DEST is the frame pointer, we do nothing because we assume that
3817 all assignments to the hard frame pointer are nonlocal gotos and are being
3818 done at a time when they are valid and do not disturb anything else.
3819 Some machines want to eliminate a fake argument pointer with either the
3820 frame or stack pointer. Assignments to the hard frame pointer must not
3821 prevent this elimination.
3823 Called via note_stores from reload before starting its passes to scan
3824 the insns of the function. */
3827 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3831 /* A SUBREG of a hard register here is just changing its mode. We should
3832 not see a SUBREG of an eliminable hard register, but check just in
3834 if (GET_CODE (dest) == SUBREG)
3835 dest = SUBREG_REG (dest);
3837 if (dest == hard_frame_pointer_rtx)
3840 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3841 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3842 && (GET_CODE (x) != SET
3843 || GET_CODE (SET_SRC (x)) != PLUS
3844 || XEXP (SET_SRC (x), 0) != dest
3845 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3847 reg_eliminate[i].can_eliminate_previous
3848 = reg_eliminate[i].can_eliminate = 0;
3853 /* Verify that the initial elimination offsets did not change since the
3854 last call to set_initial_elim_offsets. This is used to catch cases
3855 where something illegal happened during reload_as_needed that could
3856 cause incorrect code to be generated if we did not check for it. */
3859 verify_initial_elim_offsets (void)
3863 if (!num_eliminable)
3866 #ifdef ELIMINABLE_REGS
3868 struct elim_table *ep;
3870 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3872 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3873 if (t != ep->initial_offset)
3878 INITIAL_FRAME_POINTER_OFFSET (t);
3879 if (t != reg_eliminate[0].initial_offset)
3886 /* Reset all offsets on eliminable registers to their initial values. */
3889 set_initial_elim_offsets (void)
3891 struct elim_table *ep = reg_eliminate;
3893 #ifdef ELIMINABLE_REGS
3894 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3896 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3897 ep->previous_offset = ep->offset = ep->initial_offset;
3900 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3901 ep->previous_offset = ep->offset = ep->initial_offset;
3904 num_not_at_initial_offset = 0;
3907 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3910 set_initial_eh_label_offset (rtx label)
3912 set_label_offsets (label, NULL, 1);
3915 /* Initialize the known label offsets.
3916 Set a known offset for each forced label to be at the initial offset
3917 of each elimination. We do this because we assume that all
3918 computed jumps occur from a location where each elimination is
3919 at its initial offset.
3920 For all other labels, show that we don't know the offsets. */
3923 set_initial_label_offsets (void)
3925 memset (offsets_known_at, 0, num_labels);
3927 for (rtx_insn_list *x = forced_labels; x; x = x->next ())
3929 set_label_offsets (x->insn (), NULL, 1);
3931 for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3933 set_label_offsets (x->insn (), NULL, 1);
3935 for_each_eh_label (set_initial_eh_label_offset);
3938 /* Set all elimination offsets to the known values for the code label given
3942 set_offsets_for_label (rtx_insn *insn)
3945 int label_nr = CODE_LABEL_NUMBER (insn);
3946 struct elim_table *ep;
3948 num_not_at_initial_offset = 0;
3949 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3951 ep->offset = ep->previous_offset
3952 = offsets_at[label_nr - first_label_num][i];
3953 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3954 num_not_at_initial_offset++;
3958 /* See if anything that happened changes which eliminations are valid.
3959 For example, on the SPARC, whether or not the frame pointer can
3960 be eliminated can depend on what registers have been used. We need
3961 not check some conditions again (such as flag_omit_frame_pointer)
3962 since they can't have changed. */
3965 update_eliminables (HARD_REG_SET *pset)
3967 int previous_frame_pointer_needed = frame_pointer_needed;
3968 struct elim_table *ep;
3970 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3971 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3972 && targetm.frame_pointer_required ())
3973 #ifdef ELIMINABLE_REGS
3974 || ! targetm.can_eliminate (ep->from, ep->to)
3977 ep->can_eliminate = 0;
3979 /* Look for the case where we have discovered that we can't replace
3980 register A with register B and that means that we will now be
3981 trying to replace register A with register C. This means we can
3982 no longer replace register C with register B and we need to disable
3983 such an elimination, if it exists. This occurs often with A == ap,
3984 B == sp, and C == fp. */
3986 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3988 struct elim_table *op;
3991 if (! ep->can_eliminate && ep->can_eliminate_previous)
3993 /* Find the current elimination for ep->from, if there is a
3995 for (op = reg_eliminate;
3996 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3997 if (op->from == ep->from && op->can_eliminate)
4003 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
4005 for (op = reg_eliminate;
4006 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
4007 if (op->from == new_to && op->to == ep->to)
4008 op->can_eliminate = 0;
4012 /* See if any registers that we thought we could eliminate the previous
4013 time are no longer eliminable. If so, something has changed and we
4014 must spill the register. Also, recompute the number of eliminable
4015 registers and see if the frame pointer is needed; it is if there is
4016 no elimination of the frame pointer that we can perform. */
4018 frame_pointer_needed = 1;
4019 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4021 if (ep->can_eliminate
4022 && ep->from == FRAME_POINTER_REGNUM
4023 && ep->to != HARD_FRAME_POINTER_REGNUM
4024 && (! SUPPORTS_STACK_ALIGNMENT
4025 || ! crtl->stack_realign_needed))
4026 frame_pointer_needed = 0;
4028 if (! ep->can_eliminate && ep->can_eliminate_previous)
4030 ep->can_eliminate_previous = 0;
4031 SET_HARD_REG_BIT (*pset, ep->from);
4036 /* If we didn't need a frame pointer last time, but we do now, spill
4037 the hard frame pointer. */
4038 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4039 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4042 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4043 Return true iff a register was spilled. */
4046 update_eliminables_and_spill (void)
4049 bool did_spill = false;
4050 HARD_REG_SET to_spill;
4051 CLEAR_HARD_REG_SET (to_spill);
4052 update_eliminables (&to_spill);
4053 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
4055 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4056 if (TEST_HARD_REG_BIT (to_spill, i))
4058 spill_hard_reg (i, 1);
4061 /* Regardless of the state of spills, if we previously had
4062 a register that we thought we could eliminate, but now can
4063 not eliminate, we must run another pass.
4065 Consider pseudos which have an entry in reg_equiv_* which
4066 reference an eliminable register. We must make another pass
4067 to update reg_equiv_* so that we do not substitute in the
4068 old value from when we thought the elimination could be
4074 /* Return true if X is used as the target register of an elimination. */
4077 elimination_target_reg_p (rtx x)
4079 struct elim_table *ep;
4081 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4082 if (ep->to_rtx == x && ep->can_eliminate)
4088 /* Initialize the table of registers to eliminate.
4089 Pre-condition: global flag frame_pointer_needed has been set before
4090 calling this function. */
4093 init_elim_table (void)
4095 struct elim_table *ep;
4096 #ifdef ELIMINABLE_REGS
4097 const struct elim_table_1 *ep1;
4101 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4105 #ifdef ELIMINABLE_REGS
4106 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4107 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4109 ep->from = ep1->from;
4111 ep->can_eliminate = ep->can_eliminate_previous
4112 = (targetm.can_eliminate (ep->from, ep->to)
4113 && ! (ep->to == STACK_POINTER_REGNUM
4114 && frame_pointer_needed
4115 && (! SUPPORTS_STACK_ALIGNMENT
4116 || ! stack_realign_fp)));
4119 reg_eliminate[0].from = reg_eliminate_1[0].from;
4120 reg_eliminate[0].to = reg_eliminate_1[0].to;
4121 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4122 = ! frame_pointer_needed;
4125 /* Count the number of eliminable registers and build the FROM and TO
4126 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4127 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4128 We depend on this. */
4129 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4131 num_eliminable += ep->can_eliminate;
4132 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4133 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4137 /* Find all the pseudo registers that didn't get hard regs
4138 but do have known equivalent constants or memory slots.
4139 These include parameters (known equivalent to parameter slots)
4140 and cse'd or loop-moved constant memory addresses.
4142 Record constant equivalents in reg_equiv_constant
4143 so they will be substituted by find_reloads.
4144 Record memory equivalents in reg_mem_equiv so they can
4145 be substituted eventually by altering the REG-rtx's. */
4148 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4155 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4157 reg_max_ref_width = NULL;
4159 num_eliminable_invariants = 0;
4161 first_label_num = get_first_label_num ();
4162 num_labels = max_label_num () - first_label_num;
4164 /* Allocate the tables used to store offset information at labels. */
4165 offsets_known_at = XNEWVEC (char, num_labels);
4166 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4168 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4169 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4170 find largest such for each pseudo. FIRST is the head of the insn
4173 for (insn = first; insn; insn = NEXT_INSN (insn))
4175 rtx set = single_set (insn);
4177 /* We may introduce USEs that we want to remove at the end, so
4178 we'll mark them with QImode. Make sure there are no
4179 previously-marked insns left by say regmove. */
4180 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4181 && GET_MODE (insn) != VOIDmode)
4182 PUT_MODE (insn, VOIDmode);
4184 if (do_subregs && NONDEBUG_INSN_P (insn))
4185 scan_paradoxical_subregs (PATTERN (insn));
4187 if (set != 0 && REG_P (SET_DEST (set)))
4189 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4195 i = REGNO (SET_DEST (set));
4198 if (i <= LAST_VIRTUAL_REGISTER)
4201 /* If flag_pic and we have constant, verify it's legitimate. */
4203 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4205 /* It can happen that a REG_EQUIV note contains a MEM
4206 that is not a legitimate memory operand. As later
4207 stages of reload assume that all addresses found
4208 in the reg_equiv_* arrays were originally legitimate,
4209 we ignore such REG_EQUIV notes. */
4210 if (memory_operand (x, VOIDmode))
4212 /* Always unshare the equivalence, so we can
4213 substitute into this insn without touching the
4215 reg_equiv_memory_loc (i) = copy_rtx (x);
4217 else if (function_invariant_p (x))
4221 mode = GET_MODE (SET_DEST (set));
4222 if (GET_CODE (x) == PLUS)
4224 /* This is PLUS of frame pointer and a constant,
4225 and might be shared. Unshare it. */
4226 reg_equiv_invariant (i) = copy_rtx (x);
4227 num_eliminable_invariants++;
4229 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4231 reg_equiv_invariant (i) = x;
4232 num_eliminable_invariants++;
4234 else if (targetm.legitimate_constant_p (mode, x))
4235 reg_equiv_constant (i) = x;
4238 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4239 if (! reg_equiv_memory_loc (i))
4240 reg_equiv_init (i) = NULL;
4245 reg_equiv_init (i) = NULL;
4250 reg_equiv_init (i) = NULL;
4255 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4256 if (reg_equiv_init (i))
4258 fprintf (dump_file, "init_insns for %u: ", i);
4259 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4260 fprintf (dump_file, "\n");
4264 /* Indicate that we no longer have known memory locations or constants.
4265 Free all data involved in tracking these. */
4268 free_reg_equiv (void)
4272 free (offsets_known_at);
4275 offsets_known_at = 0;
4277 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4278 if (reg_equiv_alt_mem_list (i))
4279 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4280 vec_free (reg_equivs);
4283 /* Kick all pseudos out of hard register REGNO.
4285 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4286 because we found we can't eliminate some register. In the case, no pseudos
4287 are allowed to be in the register, even if they are only in a block that
4288 doesn't require spill registers, unlike the case when we are spilling this
4289 hard reg to produce another spill register.
4291 Return nonzero if any pseudos needed to be kicked out. */
4294 spill_hard_reg (unsigned int regno, int cant_eliminate)
4300 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4301 df_set_regs_ever_live (regno, true);
4304 /* Spill every pseudo reg that was allocated to this reg
4305 or to something that overlaps this reg. */
4307 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4308 if (reg_renumber[i] >= 0
4309 && (unsigned int) reg_renumber[i] <= regno
4310 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4311 SET_REGNO_REG_SET (&spilled_pseudos, i);
4314 /* After find_reload_regs has been run for all insn that need reloads,
4315 and/or spill_hard_regs was called, this function is used to actually
4316 spill pseudo registers and try to reallocate them. It also sets up the
4317 spill_regs array for use by choose_reload_regs. */
4320 finish_spills (int global)
4322 struct insn_chain *chain;
4323 int something_changed = 0;
4325 reg_set_iterator rsi;
4327 /* Build the spill_regs array for the function. */
4328 /* If there are some registers still to eliminate and one of the spill regs
4329 wasn't ever used before, additional stack space may have to be
4330 allocated to store this register. Thus, we may have changed the offset
4331 between the stack and frame pointers, so mark that something has changed.
4333 One might think that we need only set VAL to 1 if this is a call-used
4334 register. However, the set of registers that must be saved by the
4335 prologue is not identical to the call-used set. For example, the
4336 register used by the call insn for the return PC is a call-used register,
4337 but must be saved by the prologue. */
4340 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4341 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4343 spill_reg_order[i] = n_spills;
4344 spill_regs[n_spills++] = i;
4345 if (num_eliminable && ! df_regs_ever_live_p (i))
4346 something_changed = 1;
4347 df_set_regs_ever_live (i, true);
4350 spill_reg_order[i] = -1;
4352 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4353 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4355 /* Record the current hard register the pseudo is allocated to
4356 in pseudo_previous_regs so we avoid reallocating it to the
4357 same hard reg in a later pass. */
4358 gcc_assert (reg_renumber[i] >= 0);
4360 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4361 /* Mark it as no longer having a hard register home. */
4362 reg_renumber[i] = -1;
4363 if (ira_conflicts_p)
4364 /* Inform IRA about the change. */
4365 ira_mark_allocation_change (i);
4366 /* We will need to scan everything again. */
4367 something_changed = 1;
4370 /* Retry global register allocation if possible. */
4371 if (global && ira_conflicts_p)
4375 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4376 /* For every insn that needs reloads, set the registers used as spill
4377 regs in pseudo_forbidden_regs for every pseudo live across the
4379 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4381 EXECUTE_IF_SET_IN_REG_SET
4382 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4384 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4385 chain->used_spill_regs);
4387 EXECUTE_IF_SET_IN_REG_SET
4388 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4390 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4391 chain->used_spill_regs);
4395 /* Retry allocating the pseudos spilled in IRA and the
4396 reload. For each reg, merge the various reg sets that
4397 indicate which hard regs can't be used, and call
4398 ira_reassign_pseudos. */
4399 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4400 if (reg_old_renumber[i] != reg_renumber[i])
4402 if (reg_renumber[i] < 0)
4403 temp_pseudo_reg_arr[n++] = i;
4405 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4407 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4408 bad_spill_regs_global,
4409 pseudo_forbidden_regs, pseudo_previous_regs,
4411 something_changed = 1;
4413 /* Fix up the register information in the insn chain.
4414 This involves deleting those of the spilled pseudos which did not get
4415 a new hard register home from the live_{before,after} sets. */
4416 for (chain = reload_insn_chain; chain; chain = chain->next)
4418 HARD_REG_SET used_by_pseudos;
4419 HARD_REG_SET used_by_pseudos2;
4421 if (! ira_conflicts_p)
4423 /* Don't do it for IRA because IRA and the reload still can
4424 assign hard registers to the spilled pseudos on next
4425 reload iterations. */
4426 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4427 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4429 /* Mark any unallocated hard regs as available for spills. That
4430 makes inheritance work somewhat better. */
4431 if (chain->need_reload)
4433 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4434 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4435 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4437 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4438 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4439 /* Value of chain->used_spill_regs from previous iteration
4440 may be not included in the value calculated here because
4441 of possible removing caller-saves insns (see function
4442 delete_caller_save_insns. */
4443 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4444 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4448 CLEAR_REG_SET (&changed_allocation_pseudos);
4449 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4450 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4452 int regno = reg_renumber[i];
4453 if (reg_old_renumber[i] == regno)
4456 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4458 alter_reg (i, reg_old_renumber[i], false);
4459 reg_old_renumber[i] = regno;
4463 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4465 fprintf (dump_file, " Register %d now in %d.\n\n",
4466 i, reg_renumber[i]);
4470 return something_changed;
4473 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4476 scan_paradoxical_subregs (rtx x)
4480 enum rtx_code code = GET_CODE (x);
4496 if (REG_P (SUBREG_REG (x))
4497 && (GET_MODE_SIZE (GET_MODE (x))
4498 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4500 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4501 = GET_MODE_SIZE (GET_MODE (x));
4502 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4510 fmt = GET_RTX_FORMAT (code);
4511 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4514 scan_paradoxical_subregs (XEXP (x, i));
4515 else if (fmt[i] == 'E')
4518 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4519 scan_paradoxical_subregs (XVECEXP (x, i, j));
4524 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4525 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4526 and apply the corresponding narrowing subreg to *OTHER_PTR.
4527 Return true if the operands were changed, false otherwise. */
4530 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4532 rtx op, inner, other, tem;
4535 if (!paradoxical_subreg_p (op))
4537 inner = SUBREG_REG (op);
4540 tem = gen_lowpart_common (GET_MODE (inner), other);
4544 /* If the lowpart operation turned a hard register into a subreg,
4545 rather than simplifying it to another hard register, then the
4546 mode change cannot be properly represented. For example, OTHER
4547 might be valid in its current mode, but not in the new one. */
4548 if (GET_CODE (tem) == SUBREG
4550 && HARD_REGISTER_P (other))
4558 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4559 examine all of the reload insns between PREV and NEXT exclusive, and
4560 annotate all that may trap. */
4563 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4565 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4568 if (!insn_could_throw_p (insn))
4569 remove_note (insn, note);
4570 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4573 /* Reload pseudo-registers into hard regs around each insn as needed.
4574 Additional register load insns are output before the insn that needs it
4575 and perhaps store insns after insns that modify the reloaded pseudo reg.
4577 reg_last_reload_reg and reg_reloaded_contents keep track of
4578 which registers are already available in reload registers.
4579 We update these for the reloads that we perform,
4580 as the insns are scanned. */
4583 reload_as_needed (int live_known)
4585 struct insn_chain *chain;
4591 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4592 memset (spill_reg_store, 0, sizeof spill_reg_store);
4593 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4594 INIT_REG_SET (®_has_output_reload);
4595 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4596 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4598 set_initial_elim_offsets ();
4600 /* Generate a marker insn that we will move around. */
4601 marker = emit_note (NOTE_INSN_DELETED);
4602 unlink_insn_chain (marker, marker);
4604 for (chain = reload_insn_chain; chain; chain = chain->next)
4607 rtx_insn *insn = chain->insn;
4608 rtx_insn *old_next = NEXT_INSN (insn);
4610 rtx_insn *old_prev = PREV_INSN (insn);
4613 if (will_delete_init_insn_p (insn))
4616 /* If we pass a label, copy the offsets from the label information
4617 into the current offsets of each elimination. */
4619 set_offsets_for_label (insn);
4621 else if (INSN_P (insn))
4623 regset_head regs_to_forget;
4624 INIT_REG_SET (®s_to_forget);
4625 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4627 /* If this is a USE and CLOBBER of a MEM, ensure that any
4628 references to eliminable registers have been removed. */
4630 if ((GET_CODE (PATTERN (insn)) == USE
4631 || GET_CODE (PATTERN (insn)) == CLOBBER)
4632 && MEM_P (XEXP (PATTERN (insn), 0)))
4633 XEXP (XEXP (PATTERN (insn), 0), 0)
4634 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4635 GET_MODE (XEXP (PATTERN (insn), 0)),
4638 /* If we need to do register elimination processing, do so.
4639 This might delete the insn, in which case we are done. */
4640 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4642 eliminate_regs_in_insn (insn, 1);
4645 update_eliminable_offsets ();
4646 CLEAR_REG_SET (®s_to_forget);
4651 /* If need_elim is nonzero but need_reload is zero, one might think
4652 that we could simply set n_reloads to 0. However, find_reloads
4653 could have done some manipulation of the insn (such as swapping
4654 commutative operands), and these manipulations are lost during
4655 the first pass for every insn that needs register elimination.
4656 So the actions of find_reloads must be redone here. */
4658 if (! chain->need_elim && ! chain->need_reload
4659 && ! chain->need_operand_change)
4661 /* First find the pseudo regs that must be reloaded for this insn.
4662 This info is returned in the tables reload_... (see reload.h).
4663 Also modify the body of INSN by substituting RELOAD
4664 rtx's for those pseudo regs. */
4667 CLEAR_REG_SET (®_has_output_reload);
4668 CLEAR_HARD_REG_SET (reg_is_output_reload);
4670 find_reloads (insn, 1, spill_indirect_levels, live_known,
4676 rtx_insn *next = NEXT_INSN (insn);
4678 /* ??? PREV can get deleted by reload inheritance.
4679 Work around this by emitting a marker note. */
4680 prev = PREV_INSN (insn);
4681 reorder_insns_nobb (marker, marker, prev);
4683 /* Now compute which reload regs to reload them into. Perhaps
4684 reusing reload regs from previous insns, or else output
4685 load insns to reload them. Maybe output store insns too.
4686 Record the choices of reload reg in reload_reg_rtx. */
4687 choose_reload_regs (chain);
4689 /* Generate the insns to reload operands into or out of
4690 their reload regs. */
4691 emit_reload_insns (chain);
4693 /* Substitute the chosen reload regs from reload_reg_rtx
4694 into the insn's body (or perhaps into the bodies of other
4695 load and store insn that we just made for reloading
4696 and that we moved the structure into). */
4697 subst_reloads (insn);
4699 prev = PREV_INSN (marker);
4700 unlink_insn_chain (marker, marker);
4702 /* Adjust the exception region notes for loads and stores. */
4703 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4704 fixup_eh_region_note (insn, prev, next);
4706 /* Adjust the location of REG_ARGS_SIZE. */
4707 rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4710 remove_note (insn, p);
4711 fixup_args_size_notes (prev, PREV_INSN (next),
4712 INTVAL (XEXP (p, 0)));
4715 /* If this was an ASM, make sure that all the reload insns
4716 we have generated are valid. If not, give an error
4718 if (asm_noperands (PATTERN (insn)) >= 0)
4719 for (rtx_insn *p = NEXT_INSN (prev);
4722 if (p != insn && INSN_P (p)
4723 && GET_CODE (PATTERN (p)) != USE
4724 && (recog_memoized (p) < 0
4725 || (extract_insn (p),
4726 !(constrain_operands (1,
4727 get_enabled_alternatives (p))))))
4729 error_for_asm (insn,
4730 "%<asm%> operand requires "
4731 "impossible reload");
4736 if (num_eliminable && chain->need_elim)
4737 update_eliminable_offsets ();
4739 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4740 is no longer validly lying around to save a future reload.
4741 Note that this does not detect pseudos that were reloaded
4742 for this insn in order to be stored in
4743 (obeying register constraints). That is correct; such reload
4744 registers ARE still valid. */
4745 forget_marked_reloads (®s_to_forget);
4746 CLEAR_REG_SET (®s_to_forget);
4748 /* There may have been CLOBBER insns placed after INSN. So scan
4749 between INSN and NEXT and use them to forget old reloads. */
4750 for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4751 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4752 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4755 /* Likewise for regs altered by auto-increment in this insn.
4756 REG_INC notes have been changed by reloading:
4757 find_reloads_address_1 records substitutions for them,
4758 which have been performed by subst_reloads above. */
4759 for (i = n_reloads - 1; i >= 0; i--)
4761 rtx in_reg = rld[i].in_reg;
4764 enum rtx_code code = GET_CODE (in_reg);
4765 /* PRE_INC / PRE_DEC will have the reload register ending up
4766 with the same value as the stack slot, but that doesn't
4767 hold true for POST_INC / POST_DEC. Either we have to
4768 convert the memory access to a true POST_INC / POST_DEC,
4769 or we can't use the reload register for inheritance. */
4770 if ((code == POST_INC || code == POST_DEC)
4771 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4772 REGNO (rld[i].reg_rtx))
4773 /* Make sure it is the inc/dec pseudo, and not
4774 some other (e.g. output operand) pseudo. */
4775 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4776 == REGNO (XEXP (in_reg, 0))))
4779 rtx reload_reg = rld[i].reg_rtx;
4780 machine_mode mode = GET_MODE (reload_reg);
4784 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4786 /* We really want to ignore REG_INC notes here, so
4787 use PATTERN (p) as argument to reg_set_p . */
4788 if (reg_set_p (reload_reg, PATTERN (p)))
4790 n = count_occurrences (PATTERN (p), reload_reg, 0);
4796 = gen_rtx_fmt_e (code, mode, reload_reg);
4798 validate_replace_rtx_group (reload_reg,
4800 n = verify_changes (0);
4802 /* We must also verify that the constraints
4803 are met after the replacement. Make sure
4804 extract_insn is only called for an insn
4805 where the replacements were found to be
4810 n = constrain_operands (1,
4811 get_enabled_alternatives (p));
4814 /* If the constraints were not met, then
4815 undo the replacement, else confirm it. */
4819 confirm_change_group ();
4825 add_reg_note (p, REG_INC, reload_reg);
4826 /* Mark this as having an output reload so that the
4827 REG_INC processing code below won't invalidate
4828 the reload for inheritance. */
4829 SET_HARD_REG_BIT (reg_is_output_reload,
4830 REGNO (reload_reg));
4831 SET_REGNO_REG_SET (®_has_output_reload,
4832 REGNO (XEXP (in_reg, 0)));
4835 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4838 else if ((code == PRE_INC || code == PRE_DEC)
4839 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4840 REGNO (rld[i].reg_rtx))
4841 /* Make sure it is the inc/dec pseudo, and not
4842 some other (e.g. output operand) pseudo. */
4843 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4844 == REGNO (XEXP (in_reg, 0))))
4846 SET_HARD_REG_BIT (reg_is_output_reload,
4847 REGNO (rld[i].reg_rtx));
4848 SET_REGNO_REG_SET (®_has_output_reload,
4849 REGNO (XEXP (in_reg, 0)));
4851 else if (code == PRE_INC || code == PRE_DEC
4852 || code == POST_INC || code == POST_DEC)
4854 int in_regno = REGNO (XEXP (in_reg, 0));
4856 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4859 bool forget_p = true;
4861 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4862 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4865 for (rtx_insn *x = (old_prev ?
4866 NEXT_INSN (old_prev) : insn);
4869 if (x == reg_reloaded_insn[in_hard_regno])
4875 /* If for some reasons, we didn't set up
4876 reg_last_reload_reg in this insn,
4877 invalidate inheritance from previous
4878 insns for the incremented/decremented
4879 register. Such registers will be not in
4880 reg_has_output_reload. Invalidate it
4881 also if the corresponding element in
4882 reg_reloaded_insn is also
4885 forget_old_reloads_1 (XEXP (in_reg, 0),
4891 /* If a pseudo that got a hard register is auto-incremented,
4892 we must purge records of copying it into pseudos without
4894 for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4895 if (REG_NOTE_KIND (x) == REG_INC)
4897 /* See if this pseudo reg was reloaded in this insn.
4898 If so, its last-reload info is still valid
4899 because it is based on this insn's reload. */
4900 for (i = 0; i < n_reloads; i++)
4901 if (rld[i].out == XEXP (x, 0))
4905 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4909 /* A reload reg's contents are unknown after a label. */
4911 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4913 /* Don't assume a reload reg is still good after a call insn
4914 if it is a call-used reg, or if it contains a value that will
4915 be partially clobbered by the call. */
4916 else if (CALL_P (insn))
4918 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4919 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4921 /* If this is a call to a setjmp-type function, we must not
4922 reuse any reload reg contents across the call; that will
4923 just be clobbered by other uses of the register in later
4924 code, before the longjmp. */
4925 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4926 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4931 free (reg_last_reload_reg);
4932 CLEAR_REG_SET (®_has_output_reload);
4935 /* Discard all record of any value reloaded from X,
4936 or reloaded in X from someplace else;
4937 unless X is an output reload reg of the current insn.
4939 X may be a hard reg (the reload reg)
4940 or it may be a pseudo reg that was reloaded from.
4942 When DATA is non-NULL just mark the registers in regset
4943 to be forgotten later. */
4946 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4951 regset regs = (regset) data;
4953 /* note_stores does give us subregs of hard regs,
4954 subreg_regno_offset requires a hard reg. */
4955 while (GET_CODE (x) == SUBREG)
4957 /* We ignore the subreg offset when calculating the regno,
4958 because we are using the entire underlying hard register
4968 if (regno >= FIRST_PSEUDO_REGISTER)
4974 nr = hard_regno_nregs[regno][GET_MODE (x)];
4975 /* Storing into a spilled-reg invalidates its contents.
4976 This can happen if a block-local pseudo is allocated to that reg
4977 and it wasn't spilled because this block's total need is 0.
4978 Then some insn might have an optional reload and use this reg. */
4980 for (i = 0; i < nr; i++)
4981 /* But don't do this if the reg actually serves as an output
4982 reload reg in the current instruction. */
4984 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4986 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4987 spill_reg_store[regno + i] = 0;
4993 SET_REGNO_REG_SET (regs, regno + nr);
4996 /* Since value of X has changed,
4997 forget any value previously copied from it. */
5000 /* But don't forget a copy if this is the output reload
5001 that establishes the copy's validity. */
5003 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
5004 reg_last_reload_reg[regno + nr] = 0;
5008 /* Forget the reloads marked in regset by previous function. */
5010 forget_marked_reloads (regset regs)
5013 reg_set_iterator rsi;
5014 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
5016 if (reg < FIRST_PSEUDO_REGISTER
5017 /* But don't do this if the reg actually serves as an output
5018 reload reg in the current instruction. */
5020 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
5022 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
5023 spill_reg_store[reg] = 0;
5026 || !REGNO_REG_SET_P (®_has_output_reload, reg))
5027 reg_last_reload_reg[reg] = 0;
5031 /* The following HARD_REG_SETs indicate when each hard register is
5032 used for a reload of various parts of the current insn. */
5034 /* If reg is unavailable for all reloads. */
5035 static HARD_REG_SET reload_reg_unavailable;
5036 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5037 static HARD_REG_SET reload_reg_used;
5038 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5039 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5040 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5041 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5042 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5043 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5044 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5045 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5046 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5047 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5048 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5049 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5050 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5051 static HARD_REG_SET reload_reg_used_in_op_addr;
5052 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5053 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5054 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5055 static HARD_REG_SET reload_reg_used_in_insn;
5056 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5057 static HARD_REG_SET reload_reg_used_in_other_addr;
5059 /* If reg is in use as a reload reg for any sort of reload. */
5060 static HARD_REG_SET reload_reg_used_at_all;
5062 /* If reg is use as an inherited reload. We just mark the first register
5064 static HARD_REG_SET reload_reg_used_for_inherit;
5066 /* Records which hard regs are used in any way, either as explicit use or
5067 by being allocated to a pseudo during any point of the current insn. */
5068 static HARD_REG_SET reg_used_in_insn;
5070 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5071 TYPE. MODE is used to indicate how many consecutive regs are
5075 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5081 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5084 case RELOAD_FOR_INPUT_ADDRESS:
5085 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5088 case RELOAD_FOR_INPADDR_ADDRESS:
5089 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5092 case RELOAD_FOR_OUTPUT_ADDRESS:
5093 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5096 case RELOAD_FOR_OUTADDR_ADDRESS:
5097 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5100 case RELOAD_FOR_OPERAND_ADDRESS:
5101 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5104 case RELOAD_FOR_OPADDR_ADDR:
5105 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5108 case RELOAD_FOR_OTHER_ADDRESS:
5109 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5112 case RELOAD_FOR_INPUT:
5113 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5116 case RELOAD_FOR_OUTPUT:
5117 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5120 case RELOAD_FOR_INSN:
5121 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5125 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5128 /* Similarly, but show REGNO is no longer in use for a reload. */
5131 clear_reload_reg_in_use (unsigned int regno, int opnum,
5132 enum reload_type type, machine_mode mode)
5134 unsigned int nregs = hard_regno_nregs[regno][mode];
5135 unsigned int start_regno, end_regno, r;
5137 /* A complication is that for some reload types, inheritance might
5138 allow multiple reloads of the same types to share a reload register.
5139 We set check_opnum if we have to check only reloads with the same
5140 operand number, and check_any if we have to check all reloads. */
5141 int check_opnum = 0;
5143 HARD_REG_SET *used_in_set;
5148 used_in_set = &reload_reg_used;
5151 case RELOAD_FOR_INPUT_ADDRESS:
5152 used_in_set = &reload_reg_used_in_input_addr[opnum];
5155 case RELOAD_FOR_INPADDR_ADDRESS:
5157 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5160 case RELOAD_FOR_OUTPUT_ADDRESS:
5161 used_in_set = &reload_reg_used_in_output_addr[opnum];
5164 case RELOAD_FOR_OUTADDR_ADDRESS:
5166 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5169 case RELOAD_FOR_OPERAND_ADDRESS:
5170 used_in_set = &reload_reg_used_in_op_addr;
5173 case RELOAD_FOR_OPADDR_ADDR:
5175 used_in_set = &reload_reg_used_in_op_addr_reload;
5178 case RELOAD_FOR_OTHER_ADDRESS:
5179 used_in_set = &reload_reg_used_in_other_addr;
5183 case RELOAD_FOR_INPUT:
5184 used_in_set = &reload_reg_used_in_input[opnum];
5187 case RELOAD_FOR_OUTPUT:
5188 used_in_set = &reload_reg_used_in_output[opnum];
5191 case RELOAD_FOR_INSN:
5192 used_in_set = &reload_reg_used_in_insn;
5197 /* We resolve conflicts with remaining reloads of the same type by
5198 excluding the intervals of reload registers by them from the
5199 interval of freed reload registers. Since we only keep track of
5200 one set of interval bounds, we might have to exclude somewhat
5201 more than what would be necessary if we used a HARD_REG_SET here.
5202 But this should only happen very infrequently, so there should
5203 be no reason to worry about it. */
5205 start_regno = regno;
5206 end_regno = regno + nregs;
5207 if (check_opnum || check_any)
5209 for (i = n_reloads - 1; i >= 0; i--)
5211 if (rld[i].when_needed == type
5212 && (check_any || rld[i].opnum == opnum)
5215 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5216 unsigned int conflict_end
5217 = end_hard_regno (rld[i].mode, conflict_start);
5219 /* If there is an overlap with the first to-be-freed register,
5220 adjust the interval start. */
5221 if (conflict_start <= start_regno && conflict_end > start_regno)
5222 start_regno = conflict_end;
5223 /* Otherwise, if there is a conflict with one of the other
5224 to-be-freed registers, adjust the interval end. */
5225 if (conflict_start > start_regno && conflict_start < end_regno)
5226 end_regno = conflict_start;
5231 for (r = start_regno; r < end_regno; r++)
5232 CLEAR_HARD_REG_BIT (*used_in_set, r);
5235 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5236 specified by OPNUM and TYPE. */
5239 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5243 /* In use for a RELOAD_OTHER means it's not available for anything. */
5244 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5245 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5251 /* In use for anything means we can't use it for RELOAD_OTHER. */
5252 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5253 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5254 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5255 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5258 for (i = 0; i < reload_n_operands; i++)
5259 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5260 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5261 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5262 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5263 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5264 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5269 case RELOAD_FOR_INPUT:
5270 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5271 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5274 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5277 /* If it is used for some other input, can't use it. */
5278 for (i = 0; i < reload_n_operands; i++)
5279 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5282 /* If it is used in a later operand's address, can't use it. */
5283 for (i = opnum + 1; i < reload_n_operands; i++)
5284 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5285 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5290 case RELOAD_FOR_INPUT_ADDRESS:
5291 /* Can't use a register if it is used for an input address for this
5292 operand or used as an input in an earlier one. */
5293 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5294 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5297 for (i = 0; i < opnum; i++)
5298 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5303 case RELOAD_FOR_INPADDR_ADDRESS:
5304 /* Can't use a register if it is used for an input address
5305 for this operand or used as an input in an earlier
5307 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5310 for (i = 0; i < opnum; i++)
5311 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5316 case RELOAD_FOR_OUTPUT_ADDRESS:
5317 /* Can't use a register if it is used for an output address for this
5318 operand or used as an output in this or a later operand. Note
5319 that multiple output operands are emitted in reverse order, so
5320 the conflicting ones are those with lower indices. */
5321 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5324 for (i = 0; i <= opnum; i++)
5325 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5330 case RELOAD_FOR_OUTADDR_ADDRESS:
5331 /* Can't use a register if it is used for an output address
5332 for this operand or used as an output in this or a
5333 later operand. Note that multiple output operands are
5334 emitted in reverse order, so the conflicting ones are
5335 those with lower indices. */
5336 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5339 for (i = 0; i <= opnum; i++)
5340 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5345 case RELOAD_FOR_OPERAND_ADDRESS:
5346 for (i = 0; i < reload_n_operands; i++)
5347 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5350 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5351 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5353 case RELOAD_FOR_OPADDR_ADDR:
5354 for (i = 0; i < reload_n_operands; i++)
5355 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5358 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5360 case RELOAD_FOR_OUTPUT:
5361 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5362 outputs, or an operand address for this or an earlier output.
5363 Note that multiple output operands are emitted in reverse order,
5364 so the conflicting ones are those with higher indices. */
5365 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5368 for (i = 0; i < reload_n_operands; i++)
5369 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5372 for (i = opnum; i < reload_n_operands; i++)
5373 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5374 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5379 case RELOAD_FOR_INSN:
5380 for (i = 0; i < reload_n_operands; i++)
5381 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5382 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5385 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5386 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5388 case RELOAD_FOR_OTHER_ADDRESS:
5389 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5396 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5397 the number RELOADNUM, is still available in REGNO at the end of the insn.
5399 We can assume that the reload reg was already tested for availability
5400 at the time it is needed, and we should not check this again,
5401 in case the reg has already been marked in use. */
5404 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5406 int opnum = rld[reloadnum].opnum;
5407 enum reload_type type = rld[reloadnum].when_needed;
5410 /* See if there is a reload with the same type for this operand, using
5411 the same register. This case is not handled by the code below. */
5412 for (i = reloadnum + 1; i < n_reloads; i++)
5417 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5419 reg = rld[i].reg_rtx;
5420 if (reg == NULL_RTX)
5422 nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5423 if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5430 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5431 its value must reach the end. */
5434 /* If this use is for part of the insn,
5435 its value reaches if no subsequent part uses the same register.
5436 Just like the above function, don't try to do this with lots
5439 case RELOAD_FOR_OTHER_ADDRESS:
5440 /* Here we check for everything else, since these don't conflict
5441 with anything else and everything comes later. */
5443 for (i = 0; i < reload_n_operands; i++)
5444 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5445 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5446 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5447 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5448 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5449 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5452 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5453 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5454 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5455 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5457 case RELOAD_FOR_INPUT_ADDRESS:
5458 case RELOAD_FOR_INPADDR_ADDRESS:
5459 /* Similar, except that we check only for this and subsequent inputs
5460 and the address of only subsequent inputs and we do not need
5461 to check for RELOAD_OTHER objects since they are known not to
5464 for (i = opnum; i < reload_n_operands; i++)
5465 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5468 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5469 could be killed if the register is also used by reload with type
5470 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5471 if (type == RELOAD_FOR_INPADDR_ADDRESS
5472 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5475 for (i = opnum + 1; i < reload_n_operands; i++)
5476 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5477 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5480 for (i = 0; i < reload_n_operands; i++)
5481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5482 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5483 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5486 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5489 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5490 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5491 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5493 case RELOAD_FOR_INPUT:
5494 /* Similar to input address, except we start at the next operand for
5495 both input and input address and we do not check for
5496 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5499 for (i = opnum + 1; i < reload_n_operands; i++)
5500 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5501 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5502 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5505 /* ... fall through ... */
5507 case RELOAD_FOR_OPERAND_ADDRESS:
5508 /* Check outputs and their addresses. */
5510 for (i = 0; i < reload_n_operands; i++)
5511 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5512 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5513 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5516 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5518 case RELOAD_FOR_OPADDR_ADDR:
5519 for (i = 0; i < reload_n_operands; i++)
5520 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5521 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5522 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5525 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5526 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5527 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5529 case RELOAD_FOR_INSN:
5530 /* These conflict with other outputs with RELOAD_OTHER. So
5531 we need only check for output addresses. */
5533 opnum = reload_n_operands;
5535 /* ... fall through ... */
5537 case RELOAD_FOR_OUTPUT:
5538 case RELOAD_FOR_OUTPUT_ADDRESS:
5539 case RELOAD_FOR_OUTADDR_ADDRESS:
5540 /* We already know these can't conflict with a later output. So the
5541 only thing to check are later output addresses.
5542 Note that multiple output operands are emitted in reverse order,
5543 so the conflicting ones are those with lower indices. */
5544 for (i = 0; i < opnum; i++)
5545 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5546 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5549 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5550 could be killed if the register is also used by reload with type
5551 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5552 if (type == RELOAD_FOR_OUTADDR_ADDRESS
5553 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5563 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5564 every register in REG. */
5567 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5571 for (i = REGNO (reg); i < END_REGNO (reg); i++)
5572 if (!reload_reg_reaches_end_p (i, reloadnum))
5578 /* Returns whether R1 and R2 are uniquely chained: the value of one
5579 is used by the other, and that value is not used by any other
5580 reload for this insn. This is used to partially undo the decision
5581 made in find_reloads when in the case of multiple
5582 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5583 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5584 reloads. This code tries to avoid the conflict created by that
5585 change. It might be cleaner to explicitly keep track of which
5586 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5587 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5588 this after the fact. */
5590 reloads_unique_chain_p (int r1, int r2)
5594 /* We only check input reloads. */
5595 if (! rld[r1].in || ! rld[r2].in)
5598 /* Avoid anything with output reloads. */
5599 if (rld[r1].out || rld[r2].out)
5602 /* "chained" means one reload is a component of the other reload,
5603 not the same as the other reload. */
5604 if (rld[r1].opnum != rld[r2].opnum
5605 || rtx_equal_p (rld[r1].in, rld[r2].in)
5606 || rld[r1].optional || rld[r2].optional
5607 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5608 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5611 /* The following loop assumes that r1 is the reload that feeds r2. */
5615 for (i = 0; i < n_reloads; i ++)
5616 /* Look for input reloads that aren't our two */
5617 if (i != r1 && i != r2 && rld[i].in)
5619 /* If our reload is mentioned at all, it isn't a simple chain. */
5620 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5626 /* The recursive function change all occurrences of WHAT in *WHERE
5629 substitute (rtx *where, const_rtx what, rtx repl)
5638 if (*where == what || rtx_equal_p (*where, what))
5640 /* Record the location of the changed rtx. */
5641 substitute_stack.safe_push (where);
5646 code = GET_CODE (*where);
5647 fmt = GET_RTX_FORMAT (code);
5648 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5654 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5655 substitute (&XVECEXP (*where, i, j), what, repl);
5657 else if (fmt[i] == 'e')
5658 substitute (&XEXP (*where, i), what, repl);
5662 /* The function returns TRUE if chain of reload R1 and R2 (in any
5663 order) can be evaluated without usage of intermediate register for
5664 the reload containing another reload. It is important to see
5665 gen_reload to understand what the function is trying to do. As an
5666 example, let us have reload chain
5669 r1: <something> + const
5671 and reload R2 got reload reg HR. The function returns true if
5672 there is a correct insn HR = HR + <something>. Otherwise,
5673 gen_reload will use intermediate register (and this is the reload
5674 reg for R1) to reload <something>.
5676 We need this function to find a conflict for chain reloads. In our
5677 example, if HR = HR + <something> is incorrect insn, then we cannot
5678 use HR as a reload register for R2. If we do use it then we get a
5687 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5689 /* Assume other cases in gen_reload are not possible for
5690 chain reloads or do need an intermediate hard registers. */
5695 rtx_insn *last = get_last_insn ();
5697 /* Make r2 a component of r1. */
5698 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5701 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5702 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5703 gcc_assert (regno >= 0);
5704 out = gen_rtx_REG (rld[r1].mode, regno);
5706 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5708 /* If IN is a paradoxical SUBREG, remove it and try to put the
5709 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5710 strip_paradoxical_subreg (&in, &out);
5712 if (GET_CODE (in) == PLUS
5713 && (REG_P (XEXP (in, 0))
5714 || GET_CODE (XEXP (in, 0)) == SUBREG
5715 || MEM_P (XEXP (in, 0)))
5716 && (REG_P (XEXP (in, 1))
5717 || GET_CODE (XEXP (in, 1)) == SUBREG
5718 || CONSTANT_P (XEXP (in, 1))
5719 || MEM_P (XEXP (in, 1))))
5721 insn = emit_insn (gen_rtx_SET (out, in));
5722 code = recog_memoized (insn);
5727 extract_insn (insn);
5728 /* We want constrain operands to treat this insn strictly in
5729 its validity determination, i.e., the way it would after
5730 reload has completed. */
5731 result = constrain_operands (1, get_enabled_alternatives (insn));
5734 delete_insns_since (last);
5737 /* Restore the original value at each changed address within R1. */
5738 while (!substitute_stack.is_empty ())
5740 rtx *where = substitute_stack.pop ();
5741 *where = rld[r2].in;
5747 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5750 This function uses the same algorithm as reload_reg_free_p above. */
5753 reloads_conflict (int r1, int r2)
5755 enum reload_type r1_type = rld[r1].when_needed;
5756 enum reload_type r2_type = rld[r2].when_needed;
5757 int r1_opnum = rld[r1].opnum;
5758 int r2_opnum = rld[r2].opnum;
5760 /* RELOAD_OTHER conflicts with everything. */
5761 if (r2_type == RELOAD_OTHER)
5764 /* Otherwise, check conflicts differently for each type. */
5768 case RELOAD_FOR_INPUT:
5769 return (r2_type == RELOAD_FOR_INSN
5770 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5771 || r2_type == RELOAD_FOR_OPADDR_ADDR
5772 || r2_type == RELOAD_FOR_INPUT
5773 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5774 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5775 && r2_opnum > r1_opnum));
5777 case RELOAD_FOR_INPUT_ADDRESS:
5778 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5779 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5781 case RELOAD_FOR_INPADDR_ADDRESS:
5782 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5783 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5785 case RELOAD_FOR_OUTPUT_ADDRESS:
5786 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5787 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5789 case RELOAD_FOR_OUTADDR_ADDRESS:
5790 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5791 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5793 case RELOAD_FOR_OPERAND_ADDRESS:
5794 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5795 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5796 && (!reloads_unique_chain_p (r1, r2)
5797 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5799 case RELOAD_FOR_OPADDR_ADDR:
5800 return (r2_type == RELOAD_FOR_INPUT
5801 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5803 case RELOAD_FOR_OUTPUT:
5804 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5805 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5806 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5807 && r2_opnum >= r1_opnum));
5809 case RELOAD_FOR_INSN:
5810 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5811 || r2_type == RELOAD_FOR_INSN
5812 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5814 case RELOAD_FOR_OTHER_ADDRESS:
5815 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5825 /* Indexed by reload number, 1 if incoming value
5826 inherited from previous insns. */
5827 static char reload_inherited[MAX_RELOADS];
5829 /* For an inherited reload, this is the insn the reload was inherited from,
5830 if we know it. Otherwise, this is 0. */
5831 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5833 /* If nonzero, this is a place to get the value of the reload,
5834 rather than using reload_in. */
5835 static rtx reload_override_in[MAX_RELOADS];
5837 /* For each reload, the hard register number of the register used,
5838 or -1 if we did not need a register for this reload. */
5839 static int reload_spill_index[MAX_RELOADS];
5841 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5842 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5844 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5845 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5847 /* Subroutine of free_for_value_p, used to check a single register.
5848 START_REGNO is the starting regno of the full reload register
5849 (possibly comprising multiple hard registers) that we are considering. */
5852 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5853 enum reload_type type, rtx value, rtx out,
5854 int reloadnum, int ignore_address_reloads)
5857 /* Set if we see an input reload that must not share its reload register
5858 with any new earlyclobber, but might otherwise share the reload
5859 register with an output or input-output reload. */
5860 int check_earlyclobber = 0;
5864 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5867 if (out == const0_rtx)
5873 /* We use some pseudo 'time' value to check if the lifetimes of the
5874 new register use would overlap with the one of a previous reload
5875 that is not read-only or uses a different value.
5876 The 'time' used doesn't have to be linear in any shape or form, just
5878 Some reload types use different 'buckets' for each operand.
5879 So there are MAX_RECOG_OPERANDS different time values for each
5881 We compute TIME1 as the time when the register for the prospective
5882 new reload ceases to be live, and TIME2 for each existing
5883 reload as the time when that the reload register of that reload
5885 Where there is little to be gained by exact lifetime calculations,
5886 we just make conservative assumptions, i.e. a longer lifetime;
5887 this is done in the 'default:' cases. */
5890 case RELOAD_FOR_OTHER_ADDRESS:
5891 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5892 time1 = copy ? 0 : 1;
5895 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5897 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5898 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5899 respectively, to the time values for these, we get distinct time
5900 values. To get distinct time values for each operand, we have to
5901 multiply opnum by at least three. We round that up to four because
5902 multiply by four is often cheaper. */
5903 case RELOAD_FOR_INPADDR_ADDRESS:
5904 time1 = opnum * 4 + 2;
5906 case RELOAD_FOR_INPUT_ADDRESS:
5907 time1 = opnum * 4 + 3;
5909 case RELOAD_FOR_INPUT:
5910 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5911 executes (inclusive). */
5912 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5914 case RELOAD_FOR_OPADDR_ADDR:
5916 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5917 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5919 case RELOAD_FOR_OPERAND_ADDRESS:
5920 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5922 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5924 case RELOAD_FOR_OUTADDR_ADDRESS:
5925 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5927 case RELOAD_FOR_OUTPUT_ADDRESS:
5928 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5931 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5934 for (i = 0; i < n_reloads; i++)
5936 rtx reg = rld[i].reg_rtx;
5937 if (reg && REG_P (reg)
5938 && ((unsigned) regno - true_regnum (reg)
5939 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5942 rtx other_input = rld[i].in;
5944 /* If the other reload loads the same input value, that
5945 will not cause a conflict only if it's loading it into
5946 the same register. */
5947 if (true_regnum (reg) != start_regno)
5948 other_input = NULL_RTX;
5949 if (! other_input || ! rtx_equal_p (other_input, value)
5950 || rld[i].out || out)
5953 switch (rld[i].when_needed)
5955 case RELOAD_FOR_OTHER_ADDRESS:
5958 case RELOAD_FOR_INPADDR_ADDRESS:
5959 /* find_reloads makes sure that a
5960 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5961 by at most one - the first -
5962 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5963 address reload is inherited, the address address reload
5964 goes away, so we can ignore this conflict. */
5965 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5966 && ignore_address_reloads
5967 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5968 Then the address address is still needed to store
5969 back the new address. */
5970 && ! rld[reloadnum].out)
5972 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5973 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5975 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5976 && ignore_address_reloads
5977 /* Unless we are reloading an auto_inc expression. */
5978 && ! rld[reloadnum].out)
5980 time2 = rld[i].opnum * 4 + 2;
5982 case RELOAD_FOR_INPUT_ADDRESS:
5983 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5984 && ignore_address_reloads
5985 && ! rld[reloadnum].out)
5987 time2 = rld[i].opnum * 4 + 3;
5989 case RELOAD_FOR_INPUT:
5990 time2 = rld[i].opnum * 4 + 4;
5991 check_earlyclobber = 1;
5993 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5994 == MAX_RECOG_OPERAND * 4 */
5995 case RELOAD_FOR_OPADDR_ADDR:
5996 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5997 && ignore_address_reloads
5998 && ! rld[reloadnum].out)
6000 time2 = MAX_RECOG_OPERANDS * 4 + 1;
6002 case RELOAD_FOR_OPERAND_ADDRESS:
6003 time2 = MAX_RECOG_OPERANDS * 4 + 2;
6004 check_earlyclobber = 1;
6006 case RELOAD_FOR_INSN:
6007 time2 = MAX_RECOG_OPERANDS * 4 + 3;
6009 case RELOAD_FOR_OUTPUT:
6010 /* All RELOAD_FOR_OUTPUT reloads become live just after the
6011 instruction is executed. */
6012 time2 = MAX_RECOG_OPERANDS * 4 + 4;
6014 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6015 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6017 case RELOAD_FOR_OUTADDR_ADDRESS:
6018 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
6019 && ignore_address_reloads
6020 && ! rld[reloadnum].out)
6022 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
6024 case RELOAD_FOR_OUTPUT_ADDRESS:
6025 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
6028 /* If there is no conflict in the input part, handle this
6029 like an output reload. */
6030 if (! rld[i].in || rtx_equal_p (other_input, value))
6032 time2 = MAX_RECOG_OPERANDS * 4 + 4;
6033 /* Earlyclobbered outputs must conflict with inputs. */
6034 if (earlyclobber_operand_p (rld[i].out))
6035 time2 = MAX_RECOG_OPERANDS * 4 + 3;
6040 /* RELOAD_OTHER might be live beyond instruction execution,
6041 but this is not obvious when we set time2 = 1. So check
6042 here if there might be a problem with the new reload
6043 clobbering the register used by the RELOAD_OTHER. */
6051 && (! rld[i].in || rld[i].out
6052 || ! rtx_equal_p (other_input, value)))
6053 || (out && rld[reloadnum].out_reg
6054 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6060 /* Earlyclobbered outputs must conflict with inputs. */
6061 if (check_earlyclobber && out && earlyclobber_operand_p (out))
6067 /* Return 1 if the value in reload reg REGNO, as used by a reload
6068 needed for the part of the insn specified by OPNUM and TYPE,
6069 may be used to load VALUE into it.
6071 MODE is the mode in which the register is used, this is needed to
6072 determine how many hard regs to test.
6074 Other read-only reloads with the same value do not conflict
6075 unless OUT is nonzero and these other reloads have to live while
6076 output reloads live.
6077 If OUT is CONST0_RTX, this is a special case: it means that the
6078 test should not be for using register REGNO as reload register, but
6079 for copying from register REGNO into the reload register.
6081 RELOADNUM is the number of the reload we want to load this value for;
6082 a reload does not conflict with itself.
6084 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6085 reloads that load an address for the very reload we are considering.
6087 The caller has to make sure that there is no conflict with the return
6091 free_for_value_p (int regno, machine_mode mode, int opnum,
6092 enum reload_type type, rtx value, rtx out, int reloadnum,
6093 int ignore_address_reloads)
6095 int nregs = hard_regno_nregs[regno][mode];
6097 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6098 value, out, reloadnum,
6099 ignore_address_reloads))
6104 /* Return nonzero if the rtx X is invariant over the current function. */
6105 /* ??? Actually, the places where we use this expect exactly what is
6106 tested here, and not everything that is function invariant. In
6107 particular, the frame pointer and arg pointer are special cased;
6108 pic_offset_table_rtx is not, and we must not spill these things to
6112 function_invariant_p (const_rtx x)
6116 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6118 if (GET_CODE (x) == PLUS
6119 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6120 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6125 /* Determine whether the reload reg X overlaps any rtx'es used for
6126 overriding inheritance. Return nonzero if so. */
6129 conflicts_with_override (rtx x)
6132 for (i = 0; i < n_reloads; i++)
6133 if (reload_override_in[i]
6134 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6139 /* Give an error message saying we failed to find a reload for INSN,
6140 and clear out reload R. */
6142 failed_reload (rtx_insn *insn, int r)
6144 if (asm_noperands (PATTERN (insn)) < 0)
6145 /* It's the compiler's fault. */
6146 fatal_insn ("could not find a spill register", insn);
6148 /* It's the user's fault; the operand's mode and constraint
6149 don't match. Disable this reload so we don't crash in final. */
6150 error_for_asm (insn,
6151 "%<asm%> operand constraint incompatible with operand size");
6155 rld[r].optional = 1;
6156 rld[r].secondary_p = 1;
6159 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6160 for reload R. If it's valid, get an rtx for it. Return nonzero if
6163 set_reload_reg (int i, int r)
6165 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6167 int regno ATTRIBUTE_UNUSED;
6168 rtx reg = spill_reg_rtx[i];
6170 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6171 spill_reg_rtx[i] = reg
6172 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6174 regno = true_regnum (reg);
6176 /* Detect when the reload reg can't hold the reload mode.
6177 This used to be one `if', but Sequent compiler can't handle that. */
6178 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6180 machine_mode test_mode = VOIDmode;
6182 test_mode = GET_MODE (rld[r].in);
6183 /* If rld[r].in has VOIDmode, it means we will load it
6184 in whatever mode the reload reg has: to wit, rld[r].mode.
6185 We have already tested that for validity. */
6186 /* Aside from that, we need to test that the expressions
6187 to reload from or into have modes which are valid for this
6188 reload register. Otherwise the reload insns would be invalid. */
6189 if (! (rld[r].in != 0 && test_mode != VOIDmode
6190 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6191 if (! (rld[r].out != 0
6192 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6194 /* The reg is OK. */
6197 /* Mark as in use for this insn the reload regs we use
6199 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6200 rld[r].when_needed, rld[r].mode);
6202 rld[r].reg_rtx = reg;
6203 reload_spill_index[r] = spill_regs[i];
6210 /* Find a spill register to use as a reload register for reload R.
6211 LAST_RELOAD is nonzero if this is the last reload for the insn being
6214 Set rld[R].reg_rtx to the register allocated.
6216 We return 1 if successful, or 0 if we couldn't find a spill reg and
6217 we didn't change anything. */
6220 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6225 /* If we put this reload ahead, thinking it is a group,
6226 then insist on finding a group. Otherwise we can grab a
6227 reg that some other reload needs.
6228 (That can happen when we have a 68000 DATA_OR_FP_REG
6229 which is a group of data regs or one fp reg.)
6230 We need not be so restrictive if there are no more reloads
6233 ??? Really it would be nicer to have smarter handling
6234 for that kind of reg class, where a problem like this is normal.
6235 Perhaps those classes should be avoided for reloading
6236 by use of more alternatives. */
6238 int force_group = rld[r].nregs > 1 && ! last_reload;
6240 /* If we want a single register and haven't yet found one,
6241 take any reg in the right class and not in use.
6242 If we want a consecutive group, here is where we look for it.
6244 We use three passes so we can first look for reload regs to
6245 reuse, which are already in use for other reloads in this insn,
6246 and only then use additional registers which are not "bad", then
6247 finally any register.
6249 I think that maximizing reuse is needed to make sure we don't
6250 run out of reload regs. Suppose we have three reloads, and
6251 reloads A and B can share regs. These need two regs.
6252 Suppose A and B are given different regs.
6253 That leaves none for C. */
6254 for (pass = 0; pass < 3; pass++)
6256 /* I is the index in spill_regs.
6257 We advance it round-robin between insns to use all spill regs
6258 equally, so that inherited reloads have a chance
6259 of leapfrogging each other. */
6263 for (count = 0; count < n_spills; count++)
6265 int rclass = (int) rld[r].rclass;
6271 regnum = spill_regs[i];
6273 if ((reload_reg_free_p (regnum, rld[r].opnum,
6276 /* We check reload_reg_used to make sure we
6277 don't clobber the return register. */
6278 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6279 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6280 rld[r].when_needed, rld[r].in,
6282 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6283 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6284 /* Look first for regs to share, then for unshared. But
6285 don't share regs used for inherited reloads; they are
6286 the ones we want to preserve. */
6288 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6290 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6293 int nr = hard_regno_nregs[regnum][rld[r].mode];
6295 /* During the second pass we want to avoid reload registers
6296 which are "bad" for this reload. */
6298 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6301 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6302 (on 68000) got us two FP regs. If NR is 1,
6303 we would reject both of them. */
6306 /* If we need only one reg, we have already won. */
6309 /* But reject a single reg if we demand a group. */
6314 /* Otherwise check that as many consecutive regs as we need
6315 are available here. */
6318 int regno = regnum + nr - 1;
6319 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6320 && spill_reg_order[regno] >= 0
6321 && reload_reg_free_p (regno, rld[r].opnum,
6322 rld[r].when_needed)))
6331 /* If we found something on the current pass, omit later passes. */
6332 if (count < n_spills)
6336 /* We should have found a spill register by now. */
6337 if (count >= n_spills)
6340 /* I is the index in SPILL_REG_RTX of the reload register we are to
6341 allocate. Get an rtx for it and find its register number. */
6343 return set_reload_reg (i, r);
6346 /* Initialize all the tables needed to allocate reload registers.
6347 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6348 is the array we use to restore the reg_rtx field for every reload. */
6351 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6355 for (i = 0; i < n_reloads; i++)
6356 rld[i].reg_rtx = save_reload_reg_rtx[i];
6358 memset (reload_inherited, 0, MAX_RELOADS);
6359 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6360 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6362 CLEAR_HARD_REG_SET (reload_reg_used);
6363 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6364 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6365 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6366 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6367 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6369 CLEAR_HARD_REG_SET (reg_used_in_insn);
6372 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6373 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6374 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6375 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6376 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6377 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6380 for (i = 0; i < reload_n_operands; i++)
6382 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6383 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6384 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6385 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6386 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6387 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6390 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6392 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6394 for (i = 0; i < n_reloads; i++)
6395 /* If we have already decided to use a certain register,
6396 don't use it in another way. */
6398 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6399 rld[i].when_needed, rld[i].mode);
6402 #ifdef SECONDARY_MEMORY_NEEDED
6403 /* If X is not a subreg, return it unmodified. If it is a subreg,
6404 look up whether we made a replacement for the SUBREG_REG. Return
6405 either the replacement or the SUBREG_REG. */
6408 replaced_subreg (rtx x)
6410 if (GET_CODE (x) == SUBREG)
6411 return find_replacement (&SUBREG_REG (x));
6416 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6417 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6418 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6419 otherwise it is NULL. */
6422 compute_reload_subreg_offset (machine_mode outermode,
6424 machine_mode innermode)
6427 machine_mode middlemode;
6430 return subreg_lowpart_offset (outermode, innermode);
6432 outer_offset = SUBREG_BYTE (subreg);
6433 middlemode = GET_MODE (SUBREG_REG (subreg));
6435 /* If SUBREG is paradoxical then return the normal lowpart offset
6436 for OUTERMODE and INNERMODE. Our caller has already checked
6437 that OUTERMODE fits in INNERMODE. */
6438 if (outer_offset == 0
6439 && GET_MODE_SIZE (outermode) > GET_MODE_SIZE (middlemode))
6440 return subreg_lowpart_offset (outermode, innermode);
6442 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6443 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6444 return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6447 /* Assign hard reg targets for the pseudo-registers we must reload
6448 into hard regs for this insn.
6449 Also output the instructions to copy them in and out of the hard regs.
6451 For machines with register classes, we are responsible for
6452 finding a reload reg in the proper class. */
6455 choose_reload_regs (struct insn_chain *chain)
6457 rtx_insn *insn = chain->insn;
6459 unsigned int max_group_size = 1;
6460 enum reg_class group_class = NO_REGS;
6461 int pass, win, inheritance;
6463 rtx save_reload_reg_rtx[MAX_RELOADS];
6465 /* In order to be certain of getting the registers we need,
6466 we must sort the reloads into order of increasing register class.
6467 Then our grabbing of reload registers will parallel the process
6468 that provided the reload registers.
6470 Also note whether any of the reloads wants a consecutive group of regs.
6471 If so, record the maximum size of the group desired and what
6472 register class contains all the groups needed by this insn. */
6474 for (j = 0; j < n_reloads; j++)
6476 reload_order[j] = j;
6477 if (rld[j].reg_rtx != NULL_RTX)
6479 gcc_assert (REG_P (rld[j].reg_rtx)
6480 && HARD_REGISTER_P (rld[j].reg_rtx));
6481 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6484 reload_spill_index[j] = -1;
6486 if (rld[j].nregs > 1)
6488 max_group_size = MAX (rld[j].nregs, max_group_size);
6490 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6493 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6497 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6499 /* If -O, try first with inheritance, then turning it off.
6500 If not -O, don't do inheritance.
6501 Using inheritance when not optimizing leads to paradoxes
6502 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6503 because one side of the comparison might be inherited. */
6505 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6507 choose_reload_regs_init (chain, save_reload_reg_rtx);
6509 /* Process the reloads in order of preference just found.
6510 Beyond this point, subregs can be found in reload_reg_rtx.
6512 This used to look for an existing reloaded home for all of the
6513 reloads, and only then perform any new reloads. But that could lose
6514 if the reloads were done out of reg-class order because a later
6515 reload with a looser constraint might have an old home in a register
6516 needed by an earlier reload with a tighter constraint.
6518 To solve this, we make two passes over the reloads, in the order
6519 described above. In the first pass we try to inherit a reload
6520 from a previous insn. If there is a later reload that needs a
6521 class that is a proper subset of the class being processed, we must
6522 also allocate a spill register during the first pass.
6524 Then make a second pass over the reloads to allocate any reloads
6525 that haven't been given registers yet. */
6527 for (j = 0; j < n_reloads; j++)
6529 int r = reload_order[j];
6530 rtx search_equiv = NULL_RTX;
6532 /* Ignore reloads that got marked inoperative. */
6533 if (rld[r].out == 0 && rld[r].in == 0
6534 && ! rld[r].secondary_p)
6537 /* If find_reloads chose to use reload_in or reload_out as a reload
6538 register, we don't need to chose one. Otherwise, try even if it
6539 found one since we might save an insn if we find the value lying
6541 Try also when reload_in is a pseudo without a hard reg. */
6542 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6543 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6544 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6545 && !MEM_P (rld[r].in)
6546 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6549 #if 0 /* No longer needed for correct operation.
6550 It might give better code, or might not; worth an experiment? */
6551 /* If this is an optional reload, we can't inherit from earlier insns
6552 until we are sure that any non-optional reloads have been allocated.
6553 The following code takes advantage of the fact that optional reloads
6554 are at the end of reload_order. */
6555 if (rld[r].optional != 0)
6556 for (i = 0; i < j; i++)
6557 if ((rld[reload_order[i]].out != 0
6558 || rld[reload_order[i]].in != 0
6559 || rld[reload_order[i]].secondary_p)
6560 && ! rld[reload_order[i]].optional
6561 && rld[reload_order[i]].reg_rtx == 0)
6562 allocate_reload_reg (chain, reload_order[i], 0);
6565 /* First see if this pseudo is already available as reloaded
6566 for a previous insn. We cannot try to inherit for reloads
6567 that are smaller than the maximum number of registers needed
6568 for groups unless the register we would allocate cannot be used
6571 We could check here to see if this is a secondary reload for
6572 an object that is already in a register of the desired class.
6573 This would avoid the need for the secondary reload register.
6574 But this is complex because we can't easily determine what
6575 objects might want to be loaded via this reload. So let a
6576 register be allocated here. In `emit_reload_insns' we suppress
6577 one of the loads in the case described above. */
6583 machine_mode mode = VOIDmode;
6584 rtx subreg = NULL_RTX;
6588 else if (REG_P (rld[r].in))
6590 regno = REGNO (rld[r].in);
6591 mode = GET_MODE (rld[r].in);
6593 else if (REG_P (rld[r].in_reg))
6595 regno = REGNO (rld[r].in_reg);
6596 mode = GET_MODE (rld[r].in_reg);
6598 else if (GET_CODE (rld[r].in_reg) == SUBREG
6599 && REG_P (SUBREG_REG (rld[r].in_reg)))
6601 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6602 if (regno < FIRST_PSEUDO_REGISTER)
6603 regno = subreg_regno (rld[r].in_reg);
6606 subreg = rld[r].in_reg;
6607 byte = SUBREG_BYTE (subreg);
6609 mode = GET_MODE (rld[r].in_reg);
6612 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6613 && REG_P (XEXP (rld[r].in_reg, 0)))
6615 regno = REGNO (XEXP (rld[r].in_reg, 0));
6616 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6617 rld[r].out = rld[r].in;
6621 /* This won't work, since REGNO can be a pseudo reg number.
6622 Also, it takes much more hair to keep track of all the things
6623 that can invalidate an inherited reload of part of a pseudoreg. */
6624 else if (GET_CODE (rld[r].in) == SUBREG
6625 && REG_P (SUBREG_REG (rld[r].in)))
6626 regno = subreg_regno (rld[r].in);
6630 && reg_last_reload_reg[regno] != 0
6631 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6632 >= GET_MODE_SIZE (mode) + byte)
6633 #ifdef CANNOT_CHANGE_MODE_CLASS
6634 /* Verify that the register it's in can be used in
6636 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6637 GET_MODE (reg_last_reload_reg[regno]),
6642 enum reg_class rclass = rld[r].rclass, last_class;
6643 rtx last_reg = reg_last_reload_reg[regno];
6645 i = REGNO (last_reg);
6646 byte = compute_reload_subreg_offset (mode,
6648 GET_MODE (last_reg));
6649 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6650 last_class = REGNO_REG_CLASS (i);
6652 if (reg_reloaded_contents[i] == regno
6653 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6654 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6655 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6656 /* Even if we can't use this register as a reload
6657 register, we might use it for reload_override_in,
6658 if copying it to the desired class is cheap
6660 || ((register_move_cost (mode, last_class, rclass)
6661 < memory_move_cost (mode, rclass, true))
6662 && (secondary_reload_class (1, rclass, mode,
6665 #ifdef SECONDARY_MEMORY_NEEDED
6666 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6671 && (rld[r].nregs == max_group_size
6672 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6674 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6675 rld[r].when_needed, rld[r].in,
6678 /* If a group is needed, verify that all the subsequent
6679 registers still have their values intact. */
6680 int nr = hard_regno_nregs[i][rld[r].mode];
6683 for (k = 1; k < nr; k++)
6684 if (reg_reloaded_contents[i + k] != regno
6685 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6693 last_reg = (GET_MODE (last_reg) == mode
6694 ? last_reg : gen_rtx_REG (mode, i));
6697 for (k = 0; k < nr; k++)
6698 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6701 /* We found a register that contains the
6702 value we need. If this register is the
6703 same as an `earlyclobber' operand of the
6704 current insn, just mark it as a place to
6705 reload from since we can't use it as the
6706 reload register itself. */
6708 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6709 if (reg_overlap_mentioned_for_reload_p
6710 (reg_last_reload_reg[regno],
6711 reload_earlyclobbers[i1]))
6714 if (i1 != n_earlyclobbers
6715 || ! (free_for_value_p (i, rld[r].mode,
6717 rld[r].when_needed, rld[r].in,
6719 /* Don't use it if we'd clobber a pseudo reg. */
6720 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6722 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6723 /* Don't clobber the frame pointer. */
6724 || (i == HARD_FRAME_POINTER_REGNUM
6725 && frame_pointer_needed
6727 /* Don't really use the inherited spill reg
6728 if we need it wider than we've got it. */
6729 || (GET_MODE_SIZE (rld[r].mode)
6730 > GET_MODE_SIZE (mode))
6733 /* If find_reloads chose reload_out as reload
6734 register, stay with it - that leaves the
6735 inherited register for subsequent reloads. */
6736 || (rld[r].out && rld[r].reg_rtx
6737 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6739 if (! rld[r].optional)
6741 reload_override_in[r] = last_reg;
6742 reload_inheritance_insn[r]
6743 = reg_reloaded_insn[i];
6749 /* We can use this as a reload reg. */
6750 /* Mark the register as in use for this part of
6752 mark_reload_reg_in_use (i,
6756 rld[r].reg_rtx = last_reg;
6757 reload_inherited[r] = 1;
6758 reload_inheritance_insn[r]
6759 = reg_reloaded_insn[i];
6760 reload_spill_index[r] = i;
6761 for (k = 0; k < nr; k++)
6762 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6770 /* Here's another way to see if the value is already lying around. */
6773 && ! reload_inherited[r]
6775 && (CONSTANT_P (rld[r].in)
6776 || GET_CODE (rld[r].in) == PLUS
6777 || REG_P (rld[r].in)
6778 || MEM_P (rld[r].in))
6779 && (rld[r].nregs == max_group_size
6780 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6781 search_equiv = rld[r].in;
6786 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6787 -1, NULL, 0, rld[r].mode);
6793 regno = REGNO (equiv);
6796 /* This must be a SUBREG of a hard register.
6797 Make a new REG since this might be used in an
6798 address and not all machines support SUBREGs
6800 gcc_assert (GET_CODE (equiv) == SUBREG);
6801 regno = subreg_regno (equiv);
6802 equiv = gen_rtx_REG (rld[r].mode, regno);
6803 /* If we choose EQUIV as the reload register, but the
6804 loop below decides to cancel the inheritance, we'll
6805 end up reloading EQUIV in rld[r].mode, not the mode
6806 it had originally. That isn't safe when EQUIV isn't
6807 available as a spill register since its value might
6808 still be live at this point. */
6809 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6810 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6815 /* If we found a spill reg, reject it unless it is free
6816 and of the desired class. */
6820 int bad_for_class = 0;
6821 int max_regno = regno + rld[r].nregs;
6823 for (i = regno; i < max_regno; i++)
6825 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6827 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6832 && ! free_for_value_p (regno, rld[r].mode,
6833 rld[r].opnum, rld[r].when_needed,
6834 rld[r].in, rld[r].out, r, 1))
6839 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6842 /* We found a register that contains the value we need.
6843 If this register is the same as an `earlyclobber' operand
6844 of the current insn, just mark it as a place to reload from
6845 since we can't use it as the reload register itself. */
6848 for (i = 0; i < n_earlyclobbers; i++)
6849 if (reg_overlap_mentioned_for_reload_p (equiv,
6850 reload_earlyclobbers[i]))
6852 if (! rld[r].optional)
6853 reload_override_in[r] = equiv;
6858 /* If the equiv register we have found is explicitly clobbered
6859 in the current insn, it depends on the reload type if we
6860 can use it, use it for reload_override_in, or not at all.
6861 In particular, we then can't use EQUIV for a
6862 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6866 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6867 switch (rld[r].when_needed)
6869 case RELOAD_FOR_OTHER_ADDRESS:
6870 case RELOAD_FOR_INPADDR_ADDRESS:
6871 case RELOAD_FOR_INPUT_ADDRESS:
6872 case RELOAD_FOR_OPADDR_ADDR:
6875 case RELOAD_FOR_INPUT:
6876 case RELOAD_FOR_OPERAND_ADDRESS:
6877 if (! rld[r].optional)
6878 reload_override_in[r] = equiv;
6884 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6885 switch (rld[r].when_needed)
6887 case RELOAD_FOR_OTHER_ADDRESS:
6888 case RELOAD_FOR_INPADDR_ADDRESS:
6889 case RELOAD_FOR_INPUT_ADDRESS:
6890 case RELOAD_FOR_OPADDR_ADDR:
6891 case RELOAD_FOR_OPERAND_ADDRESS:
6892 case RELOAD_FOR_INPUT:
6895 if (! rld[r].optional)
6896 reload_override_in[r] = equiv;
6904 /* If we found an equivalent reg, say no code need be generated
6905 to load it, and use it as our reload reg. */
6907 && (regno != HARD_FRAME_POINTER_REGNUM
6908 || !frame_pointer_needed))
6910 int nr = hard_regno_nregs[regno][rld[r].mode];
6912 rld[r].reg_rtx = equiv;
6913 reload_spill_index[r] = regno;
6914 reload_inherited[r] = 1;
6916 /* If reg_reloaded_valid is not set for this register,
6917 there might be a stale spill_reg_store lying around.
6918 We must clear it, since otherwise emit_reload_insns
6919 might delete the store. */
6920 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6921 spill_reg_store[regno] = NULL;
6922 /* If any of the hard registers in EQUIV are spill
6923 registers, mark them as in use for this insn. */
6924 for (k = 0; k < nr; k++)
6926 i = spill_reg_order[regno + k];
6929 mark_reload_reg_in_use (regno, rld[r].opnum,
6932 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6939 /* If we found a register to use already, or if this is an optional
6940 reload, we are done. */
6941 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6945 /* No longer needed for correct operation. Might or might
6946 not give better code on the average. Want to experiment? */
6948 /* See if there is a later reload that has a class different from our
6949 class that intersects our class or that requires less register
6950 than our reload. If so, we must allocate a register to this
6951 reload now, since that reload might inherit a previous reload
6952 and take the only available register in our class. Don't do this
6953 for optional reloads since they will force all previous reloads
6954 to be allocated. Also don't do this for reloads that have been
6957 for (i = j + 1; i < n_reloads; i++)
6959 int s = reload_order[i];
6961 if ((rld[s].in == 0 && rld[s].out == 0
6962 && ! rld[s].secondary_p)
6966 if ((rld[s].rclass != rld[r].rclass
6967 && reg_classes_intersect_p (rld[r].rclass,
6969 || rld[s].nregs < rld[r].nregs)
6976 allocate_reload_reg (chain, r, j == n_reloads - 1);
6980 /* Now allocate reload registers for anything non-optional that
6981 didn't get one yet. */
6982 for (j = 0; j < n_reloads; j++)
6984 int r = reload_order[j];
6986 /* Ignore reloads that got marked inoperative. */
6987 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6990 /* Skip reloads that already have a register allocated or are
6992 if (rld[r].reg_rtx != 0 || rld[r].optional)
6995 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6999 /* If that loop got all the way, we have won. */
7006 /* Loop around and try without any inheritance. */
7011 /* First undo everything done by the failed attempt
7012 to allocate with inheritance. */
7013 choose_reload_regs_init (chain, save_reload_reg_rtx);
7015 /* Some sanity tests to verify that the reloads found in the first
7016 pass are identical to the ones we have now. */
7017 gcc_assert (chain->n_reloads == n_reloads);
7019 for (i = 0; i < n_reloads; i++)
7021 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
7023 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
7024 for (j = 0; j < n_spills; j++)
7025 if (spill_regs[j] == chain->rld[i].regno)
7026 if (! set_reload_reg (j, i))
7027 failed_reload (chain->insn, i);
7031 /* If we thought we could inherit a reload, because it seemed that
7032 nothing else wanted the same reload register earlier in the insn,
7033 verify that assumption, now that all reloads have been assigned.
7034 Likewise for reloads where reload_override_in has been set. */
7036 /* If doing expensive optimizations, do one preliminary pass that doesn't
7037 cancel any inheritance, but removes reloads that have been needed only
7038 for reloads that we know can be inherited. */
7039 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
7041 for (j = 0; j < n_reloads; j++)
7043 int r = reload_order[j];
7045 #ifdef SECONDARY_MEMORY_NEEDED
7048 if (reload_inherited[r] && rld[r].reg_rtx)
7049 check_reg = rld[r].reg_rtx;
7050 else if (reload_override_in[r]
7051 && (REG_P (reload_override_in[r])
7052 || GET_CODE (reload_override_in[r]) == SUBREG))
7053 check_reg = reload_override_in[r];
7056 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
7057 rld[r].opnum, rld[r].when_needed, rld[r].in,
7058 (reload_inherited[r]
7059 ? rld[r].out : const0_rtx),
7064 reload_inherited[r] = 0;
7065 reload_override_in[r] = 0;
7067 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7068 reload_override_in, then we do not need its related
7069 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7070 likewise for other reload types.
7071 We handle this by removing a reload when its only replacement
7072 is mentioned in reload_in of the reload we are going to inherit.
7073 A special case are auto_inc expressions; even if the input is
7074 inherited, we still need the address for the output. We can
7075 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7076 If we succeeded removing some reload and we are doing a preliminary
7077 pass just to remove such reloads, make another pass, since the
7078 removal of one reload might allow us to inherit another one. */
7080 && rld[r].out != rld[r].in
7081 && remove_address_replacements (rld[r].in))
7086 #ifdef SECONDARY_MEMORY_NEEDED
7087 /* If we needed a memory location for the reload, we also have to
7088 remove its related reloads. */
7090 && rld[r].out != rld[r].in
7091 && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7092 && REGNO (tem) < FIRST_PSEUDO_REGISTER
7093 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem)),
7094 rld[r].rclass, rld[r].inmode)
7095 && remove_address_replacements
7096 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7097 rld[r].when_needed)))
7106 /* Now that reload_override_in is known valid,
7107 actually override reload_in. */
7108 for (j = 0; j < n_reloads; j++)
7109 if (reload_override_in[j])
7110 rld[j].in = reload_override_in[j];
7112 /* If this reload won't be done because it has been canceled or is
7113 optional and not inherited, clear reload_reg_rtx so other
7114 routines (such as subst_reloads) don't get confused. */
7115 for (j = 0; j < n_reloads; j++)
7116 if (rld[j].reg_rtx != 0
7117 && ((rld[j].optional && ! reload_inherited[j])
7118 || (rld[j].in == 0 && rld[j].out == 0
7119 && ! rld[j].secondary_p)))
7121 int regno = true_regnum (rld[j].reg_rtx);
7123 if (spill_reg_order[regno] >= 0)
7124 clear_reload_reg_in_use (regno, rld[j].opnum,
7125 rld[j].when_needed, rld[j].mode);
7127 reload_spill_index[j] = -1;
7130 /* Record which pseudos and which spill regs have output reloads. */
7131 for (j = 0; j < n_reloads; j++)
7133 int r = reload_order[j];
7135 i = reload_spill_index[r];
7137 /* I is nonneg if this reload uses a register.
7138 If rld[r].reg_rtx is 0, this is an optional reload
7139 that we opted to ignore. */
7140 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7141 && rld[r].reg_rtx != 0)
7143 int nregno = REGNO (rld[r].out_reg);
7146 if (nregno < FIRST_PSEUDO_REGISTER)
7147 nr = hard_regno_nregs[nregno][rld[r].mode];
7150 SET_REGNO_REG_SET (®_has_output_reload,
7154 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7156 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7157 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7158 || rld[r].when_needed == RELOAD_FOR_INSN);
7163 /* Deallocate the reload register for reload R. This is called from
7164 remove_address_replacements. */
7167 deallocate_reload_reg (int r)
7171 if (! rld[r].reg_rtx)
7173 regno = true_regnum (rld[r].reg_rtx);
7175 if (spill_reg_order[regno] >= 0)
7176 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7178 reload_spill_index[r] = -1;
7181 /* These arrays are filled by emit_reload_insns and its subroutines. */
7182 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7183 static rtx_insn *other_input_address_reload_insns = 0;
7184 static rtx_insn *other_input_reload_insns = 0;
7185 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7186 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7187 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7188 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7189 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7190 static rtx_insn *operand_reload_insns = 0;
7191 static rtx_insn *other_operand_reload_insns = 0;
7192 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7194 /* Values to be put in spill_reg_store are put here first. Instructions
7195 must only be placed here if the associated reload register reaches
7196 the end of the instruction's reload sequence. */
7197 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7198 static HARD_REG_SET reg_reloaded_died;
7200 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7201 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7202 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7203 adjusted register, and return true. Otherwise, return false. */
7205 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7206 enum reg_class new_class,
7207 machine_mode new_mode)
7212 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7214 unsigned regno = REGNO (reg);
7216 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7218 if (GET_MODE (reg) != new_mode)
7220 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7222 if (hard_regno_nregs[regno][new_mode]
7223 > hard_regno_nregs[regno][GET_MODE (reg)])
7225 reg = reload_adjust_reg_for_mode (reg, new_mode);
7233 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7234 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7235 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7236 adjusted register, and return true. Otherwise, return false. */
7238 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7239 enum insn_code icode)
7242 enum reg_class new_class = scratch_reload_class (icode);
7243 machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7245 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7246 new_class, new_mode);
7249 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7250 has the number J. OLD contains the value to be used as input. */
7253 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7256 rtx_insn *insn = chain->insn;
7258 rtx oldequiv_reg = 0;
7264 /* delete_output_reload is only invoked properly if old contains
7265 the original pseudo register. Since this is replaced with a
7266 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7267 find the pseudo in RELOAD_IN_REG. This is also used to
7268 determine whether a secondary reload is needed. */
7269 if (reload_override_in[j]
7270 && (REG_P (rl->in_reg)
7271 || (GET_CODE (rl->in_reg) == SUBREG
7272 && REG_P (SUBREG_REG (rl->in_reg)))))
7279 else if (REG_P (oldequiv))
7280 oldequiv_reg = oldequiv;
7281 else if (GET_CODE (oldequiv) == SUBREG)
7282 oldequiv_reg = SUBREG_REG (oldequiv);
7284 reloadreg = reload_reg_rtx_for_input[j];
7285 mode = GET_MODE (reloadreg);
7287 /* If we are reloading from a register that was recently stored in
7288 with an output-reload, see if we can prove there was
7289 actually no need to store the old value in it. */
7291 if (optimize && REG_P (oldequiv)
7292 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7293 && spill_reg_store[REGNO (oldequiv)]
7295 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7296 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7298 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7300 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7303 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7304 oldequiv = SUBREG_REG (oldequiv);
7305 if (GET_MODE (oldequiv) != VOIDmode
7306 && mode != GET_MODE (oldequiv))
7307 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7309 /* Switch to the right place to emit the reload insns. */
7310 switch (rl->when_needed)
7313 where = &other_input_reload_insns;
7315 case RELOAD_FOR_INPUT:
7316 where = &input_reload_insns[rl->opnum];
7318 case RELOAD_FOR_INPUT_ADDRESS:
7319 where = &input_address_reload_insns[rl->opnum];
7321 case RELOAD_FOR_INPADDR_ADDRESS:
7322 where = &inpaddr_address_reload_insns[rl->opnum];
7324 case RELOAD_FOR_OUTPUT_ADDRESS:
7325 where = &output_address_reload_insns[rl->opnum];
7327 case RELOAD_FOR_OUTADDR_ADDRESS:
7328 where = &outaddr_address_reload_insns[rl->opnum];
7330 case RELOAD_FOR_OPERAND_ADDRESS:
7331 where = &operand_reload_insns;
7333 case RELOAD_FOR_OPADDR_ADDR:
7334 where = &other_operand_reload_insns;
7336 case RELOAD_FOR_OTHER_ADDRESS:
7337 where = &other_input_address_reload_insns;
7343 push_to_sequence (*where);
7345 /* Auto-increment addresses must be reloaded in a special way. */
7346 if (rl->out && ! rl->out_reg)
7348 /* We are not going to bother supporting the case where a
7349 incremented register can't be copied directly from
7350 OLDEQUIV since this seems highly unlikely. */
7351 gcc_assert (rl->secondary_in_reload < 0);
7353 if (reload_inherited[j])
7354 oldequiv = reloadreg;
7356 old = XEXP (rl->in_reg, 0);
7358 /* Prevent normal processing of this reload. */
7360 /* Output a special code sequence for this case. */
7361 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7364 /* If we are reloading a pseudo-register that was set by the previous
7365 insn, see if we can get rid of that pseudo-register entirely
7366 by redirecting the previous insn into our reload register. */
7368 else if (optimize && REG_P (old)
7369 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7370 && dead_or_set_p (insn, old)
7371 /* This is unsafe if some other reload
7372 uses the same reg first. */
7373 && ! conflicts_with_override (reloadreg)
7374 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7375 rl->when_needed, old, rl->out, j, 0))
7377 rtx_insn *temp = PREV_INSN (insn);
7378 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7379 temp = PREV_INSN (temp);
7381 && NONJUMP_INSN_P (temp)
7382 && GET_CODE (PATTERN (temp)) == SET
7383 && SET_DEST (PATTERN (temp)) == old
7384 /* Make sure we can access insn_operand_constraint. */
7385 && asm_noperands (PATTERN (temp)) < 0
7386 /* This is unsafe if operand occurs more than once in current
7387 insn. Perhaps some occurrences aren't reloaded. */
7388 && count_occurrences (PATTERN (insn), old, 0) == 1)
7390 rtx old = SET_DEST (PATTERN (temp));
7391 /* Store into the reload register instead of the pseudo. */
7392 SET_DEST (PATTERN (temp)) = reloadreg;
7394 /* Verify that resulting insn is valid.
7396 Note that we have replaced the destination of TEMP with
7397 RELOADREG. If TEMP references RELOADREG within an
7398 autoincrement addressing mode, then the resulting insn
7399 is ill-formed and we must reject this optimization. */
7400 extract_insn (temp);
7401 if (constrain_operands (1, get_enabled_alternatives (temp))
7402 && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
7404 /* If the previous insn is an output reload, the source is
7405 a reload register, and its spill_reg_store entry will
7406 contain the previous destination. This is now
7408 if (REG_P (SET_SRC (PATTERN (temp)))
7409 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7411 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7412 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7415 /* If these are the only uses of the pseudo reg,
7416 pretend for GDB it lives in the reload reg we used. */
7417 if (REG_N_DEATHS (REGNO (old)) == 1
7418 && REG_N_SETS (REGNO (old)) == 1)
7420 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7421 if (ira_conflicts_p)
7422 /* Inform IRA about the change. */
7423 ira_mark_allocation_change (REGNO (old));
7424 alter_reg (REGNO (old), -1, false);
7428 /* Adjust any debug insns between temp and insn. */
7429 while ((temp = NEXT_INSN (temp)) != insn)
7430 if (DEBUG_INSN_P (temp))
7431 replace_rtx (PATTERN (temp), old, reloadreg);
7433 gcc_assert (NOTE_P (temp));
7437 SET_DEST (PATTERN (temp)) = old;
7442 /* We can't do that, so output an insn to load RELOADREG. */
7444 /* If we have a secondary reload, pick up the secondary register
7445 and icode, if any. If OLDEQUIV and OLD are different or
7446 if this is an in-out reload, recompute whether or not we
7447 still need a secondary register and what the icode should
7448 be. If we still need a secondary register and the class or
7449 icode is different, go back to reloading from OLD if using
7450 OLDEQUIV means that we got the wrong type of register. We
7451 cannot have different class or icode due to an in-out reload
7452 because we don't make such reloads when both the input and
7453 output need secondary reload registers. */
7455 if (! special && rl->secondary_in_reload >= 0)
7457 rtx second_reload_reg = 0;
7458 rtx third_reload_reg = 0;
7459 int secondary_reload = rl->secondary_in_reload;
7460 rtx real_oldequiv = oldequiv;
7463 enum insn_code icode;
7464 enum insn_code tertiary_icode = CODE_FOR_nothing;
7466 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7467 and similarly for OLD.
7468 See comments in get_secondary_reload in reload.c. */
7469 /* If it is a pseudo that cannot be replaced with its
7470 equivalent MEM, we must fall back to reload_in, which
7471 will have all the necessary substitutions registered.
7472 Likewise for a pseudo that can't be replaced with its
7473 equivalent constant.
7475 Take extra care for subregs of such pseudos. Note that
7476 we cannot use reg_equiv_mem in this case because it is
7477 not in the right mode. */
7480 if (GET_CODE (tmp) == SUBREG)
7481 tmp = SUBREG_REG (tmp);
7483 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7484 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7485 || reg_equiv_constant (REGNO (tmp)) != 0))
7487 if (! reg_equiv_mem (REGNO (tmp))
7488 || num_not_at_initial_offset
7489 || GET_CODE (oldequiv) == SUBREG)
7490 real_oldequiv = rl->in;
7492 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7496 if (GET_CODE (tmp) == SUBREG)
7497 tmp = SUBREG_REG (tmp);
7499 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7500 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7501 || reg_equiv_constant (REGNO (tmp)) != 0))
7503 if (! reg_equiv_mem (REGNO (tmp))
7504 || num_not_at_initial_offset
7505 || GET_CODE (old) == SUBREG)
7508 real_old = reg_equiv_mem (REGNO (tmp));
7511 second_reload_reg = rld[secondary_reload].reg_rtx;
7512 if (rld[secondary_reload].secondary_in_reload >= 0)
7514 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7516 third_reload_reg = rld[tertiary_reload].reg_rtx;
7517 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7518 /* We'd have to add more code for quartary reloads. */
7519 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7521 icode = rl->secondary_in_icode;
7523 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7524 || (rl->in != 0 && rl->out != 0))
7526 secondary_reload_info sri, sri2;
7527 enum reg_class new_class, new_t_class;
7529 sri.icode = CODE_FOR_nothing;
7530 sri.prev_sri = NULL;
7532 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7536 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7537 second_reload_reg = 0;
7538 else if (new_class == NO_REGS)
7540 if (reload_adjust_reg_for_icode (&second_reload_reg,
7542 (enum insn_code) sri.icode))
7544 icode = (enum insn_code) sri.icode;
7545 third_reload_reg = 0;
7550 real_oldequiv = real_old;
7553 else if (sri.icode != CODE_FOR_nothing)
7554 /* We currently lack a way to express this in reloads. */
7558 sri2.icode = CODE_FOR_nothing;
7559 sri2.prev_sri = &sri;
7561 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7564 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7566 if (reload_adjust_reg_for_temp (&second_reload_reg,
7570 third_reload_reg = 0;
7571 tertiary_icode = (enum insn_code) sri2.icode;
7576 real_oldequiv = real_old;
7579 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7581 rtx intermediate = second_reload_reg;
7583 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7585 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7589 second_reload_reg = intermediate;
7590 tertiary_icode = (enum insn_code) sri2.icode;
7595 real_oldequiv = real_old;
7598 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7600 rtx intermediate = second_reload_reg;
7602 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7604 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7607 second_reload_reg = intermediate;
7608 tertiary_icode = (enum insn_code) sri2.icode;
7613 real_oldequiv = real_old;
7618 /* This could be handled more intelligently too. */
7620 real_oldequiv = real_old;
7625 /* If we still need a secondary reload register, check
7626 to see if it is being used as a scratch or intermediate
7627 register and generate code appropriately. If we need
7628 a scratch register, use REAL_OLDEQUIV since the form of
7629 the insn may depend on the actual address if it is
7632 if (second_reload_reg)
7634 if (icode != CODE_FOR_nothing)
7636 /* We'd have to add extra code to handle this case. */
7637 gcc_assert (!third_reload_reg);
7639 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7640 second_reload_reg));
7645 /* See if we need a scratch register to load the
7646 intermediate register (a tertiary reload). */
7647 if (tertiary_icode != CODE_FOR_nothing)
7649 emit_insn ((GEN_FCN (tertiary_icode)
7650 (second_reload_reg, real_oldequiv,
7651 third_reload_reg)));
7653 else if (third_reload_reg)
7655 gen_reload (third_reload_reg, real_oldequiv,
7658 gen_reload (second_reload_reg, third_reload_reg,
7663 gen_reload (second_reload_reg, real_oldequiv,
7667 oldequiv = second_reload_reg;
7672 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7674 rtx real_oldequiv = oldequiv;
7676 if ((REG_P (oldequiv)
7677 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7678 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7679 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7680 || (GET_CODE (oldequiv) == SUBREG
7681 && REG_P (SUBREG_REG (oldequiv))
7682 && (REGNO (SUBREG_REG (oldequiv))
7683 >= FIRST_PSEUDO_REGISTER)
7684 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7685 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7686 || (CONSTANT_P (oldequiv)
7687 && (targetm.preferred_reload_class (oldequiv,
7688 REGNO_REG_CLASS (REGNO (reloadreg)))
7690 real_oldequiv = rl->in;
7691 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7695 if (cfun->can_throw_non_call_exceptions)
7696 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7698 /* End this sequence. */
7699 *where = get_insns ();
7702 /* Update reload_override_in so that delete_address_reloads_1
7703 can see the actual register usage. */
7705 reload_override_in[j] = oldequiv;
7708 /* Generate insns to for the output reload RL, which is for the insn described
7709 by CHAIN and has the number J. */
7711 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7715 rtx_insn *insn = chain->insn;
7722 if (rl->when_needed == RELOAD_OTHER)
7725 push_to_sequence (output_reload_insns[rl->opnum]);
7727 rl_reg_rtx = reload_reg_rtx_for_output[j];
7728 mode = GET_MODE (rl_reg_rtx);
7730 reloadreg = rl_reg_rtx;
7732 /* If we need two reload regs, set RELOADREG to the intermediate
7733 one, since it will be stored into OLD. We might need a secondary
7734 register only for an input reload, so check again here. */
7736 if (rl->secondary_out_reload >= 0)
7739 int secondary_reload = rl->secondary_out_reload;
7740 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7742 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7743 && reg_equiv_mem (REGNO (old)) != 0)
7744 real_old = reg_equiv_mem (REGNO (old));
7746 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7748 rtx second_reloadreg = reloadreg;
7749 reloadreg = rld[secondary_reload].reg_rtx;
7751 /* See if RELOADREG is to be used as a scratch register
7752 or as an intermediate register. */
7753 if (rl->secondary_out_icode != CODE_FOR_nothing)
7755 /* We'd have to add extra code to handle this case. */
7756 gcc_assert (tertiary_reload < 0);
7758 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7759 (real_old, second_reloadreg, reloadreg)));
7764 /* See if we need both a scratch and intermediate reload
7767 enum insn_code tertiary_icode
7768 = rld[secondary_reload].secondary_out_icode;
7770 /* We'd have to add more code for quartary reloads. */
7771 gcc_assert (tertiary_reload < 0
7772 || rld[tertiary_reload].secondary_out_reload < 0);
7774 if (GET_MODE (reloadreg) != mode)
7775 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7777 if (tertiary_icode != CODE_FOR_nothing)
7779 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7781 /* Copy primary reload reg to secondary reload reg.
7782 (Note that these have been swapped above, then
7783 secondary reload reg to OLD using our insn.) */
7785 /* If REAL_OLD is a paradoxical SUBREG, remove it
7786 and try to put the opposite SUBREG on
7788 strip_paradoxical_subreg (&real_old, &reloadreg);
7790 gen_reload (reloadreg, second_reloadreg,
7791 rl->opnum, rl->when_needed);
7792 emit_insn ((GEN_FCN (tertiary_icode)
7793 (real_old, reloadreg, third_reloadreg)));
7799 /* Copy between the reload regs here and then to
7802 gen_reload (reloadreg, second_reloadreg,
7803 rl->opnum, rl->when_needed);
7804 if (tertiary_reload >= 0)
7806 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7808 gen_reload (third_reloadreg, reloadreg,
7809 rl->opnum, rl->when_needed);
7810 reloadreg = third_reloadreg;
7817 /* Output the last reload insn. */
7822 /* Don't output the last reload if OLD is not the dest of
7823 INSN and is in the src and is clobbered by INSN. */
7824 if (! flag_expensive_optimizations
7826 || !(set = single_set (insn))
7827 || rtx_equal_p (old, SET_DEST (set))
7828 || !reg_mentioned_p (old, SET_SRC (set))
7829 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7830 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7831 gen_reload (old, reloadreg, rl->opnum,
7835 /* Look at all insns we emitted, just to be safe. */
7836 for (p = get_insns (); p; p = NEXT_INSN (p))
7839 rtx pat = PATTERN (p);
7841 /* If this output reload doesn't come from a spill reg,
7842 clear any memory of reloaded copies of the pseudo reg.
7843 If this output reload comes from a spill reg,
7844 reg_has_output_reload will make this do nothing. */
7845 note_stores (pat, forget_old_reloads_1, NULL);
7847 if (reg_mentioned_p (rl_reg_rtx, pat))
7849 rtx set = single_set (insn);
7850 if (reload_spill_index[j] < 0
7852 && SET_SRC (set) == rl_reg_rtx)
7854 int src = REGNO (SET_SRC (set));
7856 reload_spill_index[j] = src;
7857 SET_HARD_REG_BIT (reg_is_output_reload, src);
7858 if (find_regno_note (insn, REG_DEAD, src))
7859 SET_HARD_REG_BIT (reg_reloaded_died, src);
7861 if (HARD_REGISTER_P (rl_reg_rtx))
7863 int s = rl->secondary_out_reload;
7864 set = single_set (p);
7865 /* If this reload copies only to the secondary reload
7866 register, the secondary reload does the actual
7868 if (s >= 0 && set == NULL_RTX)
7869 /* We can't tell what function the secondary reload
7870 has and where the actual store to the pseudo is
7871 made; leave new_spill_reg_store alone. */
7874 && SET_SRC (set) == rl_reg_rtx
7875 && SET_DEST (set) == rld[s].reg_rtx)
7877 /* Usually the next instruction will be the
7878 secondary reload insn; if we can confirm
7879 that it is, setting new_spill_reg_store to
7880 that insn will allow an extra optimization. */
7881 rtx s_reg = rld[s].reg_rtx;
7882 rtx_insn *next = NEXT_INSN (p);
7883 rld[s].out = rl->out;
7884 rld[s].out_reg = rl->out_reg;
7885 set = single_set (next);
7886 if (set && SET_SRC (set) == s_reg
7887 && reload_reg_rtx_reaches_end_p (s_reg, s))
7889 SET_HARD_REG_BIT (reg_is_output_reload,
7891 new_spill_reg_store[REGNO (s_reg)] = next;
7894 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7895 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7900 if (rl->when_needed == RELOAD_OTHER)
7902 emit_insn (other_output_reload_insns[rl->opnum]);
7903 other_output_reload_insns[rl->opnum] = get_insns ();
7906 output_reload_insns[rl->opnum] = get_insns ();
7908 if (cfun->can_throw_non_call_exceptions)
7909 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7914 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7915 and has the number J. */
7917 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7919 rtx_insn *insn = chain->insn;
7920 rtx old = (rl->in && MEM_P (rl->in)
7921 ? rl->in_reg : rl->in);
7922 rtx reg_rtx = rl->reg_rtx;
7928 /* Determine the mode to reload in.
7929 This is very tricky because we have three to choose from.
7930 There is the mode the insn operand wants (rl->inmode).
7931 There is the mode of the reload register RELOADREG.
7932 There is the intrinsic mode of the operand, which we could find
7933 by stripping some SUBREGs.
7934 It turns out that RELOADREG's mode is irrelevant:
7935 we can change that arbitrarily.
7937 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7938 then the reload reg may not support QImode moves, so use SImode.
7939 If foo is in memory due to spilling a pseudo reg, this is safe,
7940 because the QImode value is in the least significant part of a
7941 slot big enough for a SImode. If foo is some other sort of
7942 memory reference, then it is impossible to reload this case,
7943 so previous passes had better make sure this never happens.
7945 Then consider a one-word union which has SImode and one of its
7946 members is a float, being fetched as (SUBREG:SF union:SI).
7947 We must fetch that as SFmode because we could be loading into
7948 a float-only register. In this case OLD's mode is correct.
7950 Consider an immediate integer: it has VOIDmode. Here we need
7951 to get a mode from something else.
7953 In some cases, there is a fourth mode, the operand's
7954 containing mode. If the insn specifies a containing mode for
7955 this operand, it overrides all others.
7957 I am not sure whether the algorithm here is always right,
7958 but it does the right things in those cases. */
7960 mode = GET_MODE (old);
7961 if (mode == VOIDmode)
7964 /* We cannot use gen_lowpart_common since it can do the wrong thing
7965 when REG_RTX has a multi-word mode. Note that REG_RTX must
7966 always be a REG here. */
7967 if (GET_MODE (reg_rtx) != mode)
7968 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7970 reload_reg_rtx_for_input[j] = reg_rtx;
7973 /* AUTO_INC reloads need to be handled even if inherited. We got an
7974 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7975 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7976 && ! rtx_equal_p (reg_rtx, old)
7978 emit_input_reload_insns (chain, rld + j, old, j);
7980 /* When inheriting a wider reload, we have a MEM in rl->in,
7981 e.g. inheriting a SImode output reload for
7982 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7983 if (optimize && reload_inherited[j] && rl->in
7985 && MEM_P (rl->in_reg)
7986 && reload_spill_index[j] >= 0
7987 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7988 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7990 /* If we are reloading a register that was recently stored in with an
7991 output-reload, see if we can prove there was
7992 actually no need to store the old value in it. */
7995 && (reload_inherited[j] || reload_override_in[j])
7998 && spill_reg_store[REGNO (reg_rtx)] != 0
8000 /* There doesn't seem to be any reason to restrict this to pseudos
8001 and doing so loses in the case where we are copying from a
8002 register of the wrong class. */
8003 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
8005 /* The insn might have already some references to stackslots
8006 replaced by MEMs, while reload_out_reg still names the
8008 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
8009 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
8010 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
8013 /* Do output reloading for reload RL, which is for the insn described by
8014 CHAIN and has the number J.
8015 ??? At some point we need to support handling output reloads of
8016 JUMP_INSNs or insns that set cc0. */
8018 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
8021 rtx_insn *insn = chain->insn;
8022 /* If this is an output reload that stores something that is
8023 not loaded in this same reload, see if we can eliminate a previous
8025 rtx pseudo = rl->out_reg;
8026 rtx reg_rtx = rl->reg_rtx;
8028 if (rl->out && reg_rtx)
8032 /* Determine the mode to reload in.
8033 See comments above (for input reloading). */
8034 mode = GET_MODE (rl->out);
8035 if (mode == VOIDmode)
8037 /* VOIDmode should never happen for an output. */
8038 if (asm_noperands (PATTERN (insn)) < 0)
8039 /* It's the compiler's fault. */
8040 fatal_insn ("VOIDmode on an output", insn);
8041 error_for_asm (insn, "output operand is constant in %<asm%>");
8042 /* Prevent crash--use something we know is valid. */
8044 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
8046 if (GET_MODE (reg_rtx) != mode)
8047 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
8049 reload_reg_rtx_for_output[j] = reg_rtx;
8054 && ! rtx_equal_p (rl->in_reg, pseudo)
8055 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
8056 && reg_last_reload_reg[REGNO (pseudo)])
8058 int pseudo_no = REGNO (pseudo);
8059 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
8061 /* We don't need to test full validity of last_regno for
8062 inherit here; we only want to know if the store actually
8063 matches the pseudo. */
8064 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
8065 && reg_reloaded_contents[last_regno] == pseudo_no
8066 && spill_reg_store[last_regno]
8067 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
8068 delete_output_reload (insn, j, last_regno, reg_rtx);
8074 || rtx_equal_p (old, reg_rtx))
8077 /* An output operand that dies right away does need a reload,
8078 but need not be copied from it. Show the new location in the
8080 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8081 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8083 XEXP (note, 0) = reg_rtx;
8086 /* Likewise for a SUBREG of an operand that dies. */
8087 else if (GET_CODE (old) == SUBREG
8088 && REG_P (SUBREG_REG (old))
8089 && 0 != (note = find_reg_note (insn, REG_UNUSED,
8092 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8095 else if (GET_CODE (old) == SCRATCH)
8096 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8097 but we don't want to make an output reload. */
8100 /* If is a JUMP_INSN, we can't support output reloads yet. */
8101 gcc_assert (NONJUMP_INSN_P (insn));
8103 emit_output_reload_insns (chain, rld + j, j);
8106 /* A reload copies values of MODE from register SRC to register DEST.
8107 Return true if it can be treated for inheritance purposes like a
8108 group of reloads, each one reloading a single hard register. The
8109 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8110 occupy the same number of hard registers. */
8113 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8114 int src ATTRIBUTE_UNUSED,
8115 machine_mode mode ATTRIBUTE_UNUSED)
8117 #ifdef CANNOT_CHANGE_MODE_CLASS
8118 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8119 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8125 /* Output insns to reload values in and out of the chosen reload regs. */
8128 emit_reload_insns (struct insn_chain *chain)
8130 rtx_insn *insn = chain->insn;
8134 CLEAR_HARD_REG_SET (reg_reloaded_died);
8136 for (j = 0; j < reload_n_operands; j++)
8137 input_reload_insns[j] = input_address_reload_insns[j]
8138 = inpaddr_address_reload_insns[j]
8139 = output_reload_insns[j] = output_address_reload_insns[j]
8140 = outaddr_address_reload_insns[j]
8141 = other_output_reload_insns[j] = 0;
8142 other_input_address_reload_insns = 0;
8143 other_input_reload_insns = 0;
8144 operand_reload_insns = 0;
8145 other_operand_reload_insns = 0;
8147 /* Dump reloads into the dump file. */
8150 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8151 debug_reload_to_stream (dump_file);
8154 for (j = 0; j < n_reloads; j++)
8155 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8159 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8160 new_spill_reg_store[i] = 0;
8163 /* Now output the instructions to copy the data into and out of the
8164 reload registers. Do these in the order that the reloads were reported,
8165 since reloads of base and index registers precede reloads of operands
8166 and the operands may need the base and index registers reloaded. */
8168 for (j = 0; j < n_reloads; j++)
8170 do_input_reload (chain, rld + j, j);
8171 do_output_reload (chain, rld + j, j);
8174 /* Now write all the insns we made for reloads in the order expected by
8175 the allocation functions. Prior to the insn being reloaded, we write
8176 the following reloads:
8178 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8180 RELOAD_OTHER reloads.
8182 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8183 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8184 RELOAD_FOR_INPUT reload for the operand.
8186 RELOAD_FOR_OPADDR_ADDRS reloads.
8188 RELOAD_FOR_OPERAND_ADDRESS reloads.
8190 After the insn being reloaded, we write the following:
8192 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8193 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8194 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8195 reloads for the operand. The RELOAD_OTHER output reloads are
8196 output in descending order by reload number. */
8198 emit_insn_before (other_input_address_reload_insns, insn);
8199 emit_insn_before (other_input_reload_insns, insn);
8201 for (j = 0; j < reload_n_operands; j++)
8203 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8204 emit_insn_before (input_address_reload_insns[j], insn);
8205 emit_insn_before (input_reload_insns[j], insn);
8208 emit_insn_before (other_operand_reload_insns, insn);
8209 emit_insn_before (operand_reload_insns, insn);
8211 for (j = 0; j < reload_n_operands; j++)
8213 rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8214 x = emit_insn_after (output_address_reload_insns[j], x);
8215 x = emit_insn_after (output_reload_insns[j], x);
8216 emit_insn_after (other_output_reload_insns[j], x);
8219 /* For all the spill regs newly reloaded in this instruction,
8220 record what they were reloaded from, so subsequent instructions
8221 can inherit the reloads.
8223 Update spill_reg_store for the reloads of this insn.
8224 Copy the elements that were updated in the loop above. */
8226 for (j = 0; j < n_reloads; j++)
8228 int r = reload_order[j];
8229 int i = reload_spill_index[r];
8231 /* If this is a non-inherited input reload from a pseudo, we must
8232 clear any memory of a previous store to the same pseudo. Only do
8233 something if there will not be an output reload for the pseudo
8235 if (rld[r].in_reg != 0
8236 && ! (reload_inherited[r] || reload_override_in[r]))
8238 rtx reg = rld[r].in_reg;
8240 if (GET_CODE (reg) == SUBREG)
8241 reg = SUBREG_REG (reg);
8244 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8245 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8247 int nregno = REGNO (reg);
8249 if (reg_last_reload_reg[nregno])
8251 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8253 if (reg_reloaded_contents[last_regno] == nregno)
8254 spill_reg_store[last_regno] = 0;
8259 /* I is nonneg if this reload used a register.
8260 If rld[r].reg_rtx is 0, this is an optional reload
8261 that we opted to ignore. */
8263 if (i >= 0 && rld[r].reg_rtx != 0)
8265 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8268 /* For a multi register reload, we need to check if all or part
8269 of the value lives to the end. */
8270 for (k = 0; k < nr; k++)
8271 if (reload_reg_reaches_end_p (i + k, r))
8272 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8274 /* Maybe the spill reg contains a copy of reload_out. */
8276 && (REG_P (rld[r].out)
8278 ? REG_P (rld[r].out_reg)
8279 /* The reload value is an auto-modification of
8280 some kind. For PRE_INC, POST_INC, PRE_DEC
8281 and POST_DEC, we record an equivalence
8282 between the reload register and the operand
8283 on the optimistic assumption that we can make
8284 the equivalence hold. reload_as_needed must
8285 then either make it hold or invalidate the
8288 PRE_MODIFY and POST_MODIFY addresses are reloaded
8289 somewhat differently, and allowing them here leads
8291 : (GET_CODE (rld[r].out) != POST_MODIFY
8292 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8296 reg = reload_reg_rtx_for_output[r];
8297 if (reload_reg_rtx_reaches_end_p (reg, r))
8299 machine_mode mode = GET_MODE (reg);
8300 int regno = REGNO (reg);
8301 int nregs = hard_regno_nregs[regno][mode];
8302 rtx out = (REG_P (rld[r].out)
8306 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8307 int out_regno = REGNO (out);
8308 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8309 : hard_regno_nregs[out_regno][mode]);
8312 spill_reg_store[regno] = new_spill_reg_store[regno];
8313 spill_reg_stored_to[regno] = out;
8314 reg_last_reload_reg[out_regno] = reg;
8316 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8317 && nregs == out_nregs
8318 && inherit_piecemeal_p (out_regno, regno, mode));
8320 /* If OUT_REGNO is a hard register, it may occupy more than
8321 one register. If it does, say what is in the
8322 rest of the registers assuming that both registers
8323 agree on how many words the object takes. If not,
8324 invalidate the subsequent registers. */
8326 if (HARD_REGISTER_NUM_P (out_regno))
8327 for (k = 1; k < out_nregs; k++)
8328 reg_last_reload_reg[out_regno + k]
8329 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8331 /* Now do the inverse operation. */
8332 for (k = 0; k < nregs; k++)
8334 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8335 reg_reloaded_contents[regno + k]
8336 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8339 reg_reloaded_insn[regno + k] = insn;
8340 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8341 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8342 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8345 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8350 /* Maybe the spill reg contains a copy of reload_in. Only do
8351 something if there will not be an output reload for
8352 the register being reloaded. */
8353 else if (rld[r].out_reg == 0
8355 && ((REG_P (rld[r].in)
8356 && !HARD_REGISTER_P (rld[r].in)
8357 && !REGNO_REG_SET_P (®_has_output_reload,
8359 || (REG_P (rld[r].in_reg)
8360 && !REGNO_REG_SET_P (®_has_output_reload,
8361 REGNO (rld[r].in_reg))))
8362 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8366 reg = reload_reg_rtx_for_input[r];
8367 if (reload_reg_rtx_reaches_end_p (reg, r))
8377 mode = GET_MODE (reg);
8378 regno = REGNO (reg);
8379 nregs = hard_regno_nregs[regno][mode];
8380 if (REG_P (rld[r].in)
8381 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8383 else if (REG_P (rld[r].in_reg))
8386 in = XEXP (rld[r].in_reg, 0);
8387 in_regno = REGNO (in);
8389 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8390 : hard_regno_nregs[in_regno][mode]);
8392 reg_last_reload_reg[in_regno] = reg;
8394 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8395 && nregs == in_nregs
8396 && inherit_piecemeal_p (regno, in_regno, mode));
8398 if (HARD_REGISTER_NUM_P (in_regno))
8399 for (k = 1; k < in_nregs; k++)
8400 reg_last_reload_reg[in_regno + k]
8401 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8403 /* Unless we inherited this reload, show we haven't
8404 recently done a store.
8405 Previous stores of inherited auto_inc expressions
8406 also have to be discarded. */
8407 if (! reload_inherited[r]
8408 || (rld[r].out && ! rld[r].out_reg))
8409 spill_reg_store[regno] = 0;
8411 for (k = 0; k < nregs; k++)
8413 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8414 reg_reloaded_contents[regno + k]
8415 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8418 reg_reloaded_insn[regno + k] = insn;
8419 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8420 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8421 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8424 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8431 /* The following if-statement was #if 0'd in 1.34 (or before...).
8432 It's reenabled in 1.35 because supposedly nothing else
8433 deals with this problem. */
8435 /* If a register gets output-reloaded from a non-spill register,
8436 that invalidates any previous reloaded copy of it.
8437 But forget_old_reloads_1 won't get to see it, because
8438 it thinks only about the original insn. So invalidate it here.
8439 Also do the same thing for RELOAD_OTHER constraints where the
8440 output is discarded. */
8442 && ((rld[r].out != 0
8443 && (REG_P (rld[r].out)
8444 || (MEM_P (rld[r].out)
8445 && REG_P (rld[r].out_reg))))
8446 || (rld[r].out == 0 && rld[r].out_reg
8447 && REG_P (rld[r].out_reg))))
8449 rtx out = ((rld[r].out && REG_P (rld[r].out))
8450 ? rld[r].out : rld[r].out_reg);
8451 int out_regno = REGNO (out);
8452 machine_mode mode = GET_MODE (out);
8454 /* REG_RTX is now set or clobbered by the main instruction.
8455 As the comment above explains, forget_old_reloads_1 only
8456 sees the original instruction, and there is no guarantee
8457 that the original instruction also clobbered REG_RTX.
8458 For example, if find_reloads sees that the input side of
8459 a matched operand pair dies in this instruction, it may
8460 use the input register as the reload register.
8462 Calling forget_old_reloads_1 is a waste of effort if
8463 REG_RTX is also the output register.
8465 If we know that REG_RTX holds the value of a pseudo
8466 register, the code after the call will record that fact. */
8467 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8468 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8470 if (!HARD_REGISTER_NUM_P (out_regno))
8473 rtx_insn *store_insn = NULL;
8475 reg_last_reload_reg[out_regno] = 0;
8477 /* If we can find a hard register that is stored, record
8478 the storing insn so that we may delete this insn with
8479 delete_output_reload. */
8480 src_reg = reload_reg_rtx_for_output[r];
8484 if (reload_reg_rtx_reaches_end_p (src_reg, r))
8485 store_insn = new_spill_reg_store[REGNO (src_reg)];
8491 /* If this is an optional reload, try to find the
8492 source reg from an input reload. */
8493 rtx set = single_set (insn);
8494 if (set && SET_DEST (set) == rld[r].out)
8498 src_reg = SET_SRC (set);
8500 for (k = 0; k < n_reloads; k++)
8502 if (rld[k].in == src_reg)
8504 src_reg = reload_reg_rtx_for_input[k];
8510 if (src_reg && REG_P (src_reg)
8511 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8513 int src_regno, src_nregs, k;
8516 gcc_assert (GET_MODE (src_reg) == mode);
8517 src_regno = REGNO (src_reg);
8518 src_nregs = hard_regno_nregs[src_regno][mode];
8519 /* The place where to find a death note varies with
8520 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8521 necessarily checked exactly in the code that moves
8522 notes, so just check both locations. */
8523 note = find_regno_note (insn, REG_DEAD, src_regno);
8524 if (! note && store_insn)
8525 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8526 for (k = 0; k < src_nregs; k++)
8528 spill_reg_store[src_regno + k] = store_insn;
8529 spill_reg_stored_to[src_regno + k] = out;
8530 reg_reloaded_contents[src_regno + k] = out_regno;
8531 reg_reloaded_insn[src_regno + k] = store_insn;
8532 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8533 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8534 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8536 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8539 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8541 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8543 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8545 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8547 reg_last_reload_reg[out_regno] = src_reg;
8548 /* We have to set reg_has_output_reload here, or else
8549 forget_old_reloads_1 will clear reg_last_reload_reg
8551 SET_REGNO_REG_SET (®_has_output_reload,
8557 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8559 for (k = 0; k < out_nregs; k++)
8560 reg_last_reload_reg[out_regno + k] = 0;
8564 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8567 /* Go through the motions to emit INSN and test if it is strictly valid.
8568 Return the emitted insn if valid, else return NULL. */
8571 emit_insn_if_valid_for_reload (rtx pat)
8573 rtx_insn *last = get_last_insn ();
8576 rtx_insn *insn = emit_insn (pat);
8577 code = recog_memoized (insn);
8581 extract_insn (insn);
8582 /* We want constrain operands to treat this insn strictly in its
8583 validity determination, i.e., the way it would after reload has
8585 if (constrain_operands (1, get_enabled_alternatives (insn)))
8589 delete_insns_since (last);
8593 /* Emit code to perform a reload from IN (which may be a reload register) to
8594 OUT (which may also be a reload register). IN or OUT is from operand
8595 OPNUM with reload type TYPE.
8597 Returns first insn emitted. */
8600 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8602 rtx_insn *last = get_last_insn ();
8604 #ifdef SECONDARY_MEMORY_NEEDED
8608 /* If IN is a paradoxical SUBREG, remove it and try to put the
8609 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8610 if (!strip_paradoxical_subreg (&in, &out))
8611 strip_paradoxical_subreg (&out, &in);
8613 /* How to do this reload can get quite tricky. Normally, we are being
8614 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8615 register that didn't get a hard register. In that case we can just
8616 call emit_move_insn.
8618 We can also be asked to reload a PLUS that adds a register or a MEM to
8619 another register, constant or MEM. This can occur during frame pointer
8620 elimination and while reloading addresses. This case is handled by
8621 trying to emit a single insn to perform the add. If it is not valid,
8622 we use a two insn sequence.
8624 Or we can be asked to reload an unary operand that was a fragment of
8625 an addressing mode, into a register. If it isn't recognized as-is,
8626 we try making the unop operand and the reload-register the same:
8627 (set reg:X (unop:X expr:Y))
8628 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8630 Finally, we could be called to handle an 'o' constraint by putting
8631 an address into a register. In that case, we first try to do this
8632 with a named pattern of "reload_load_address". If no such pattern
8633 exists, we just emit a SET insn and hope for the best (it will normally
8634 be valid on machines that use 'o').
8636 This entire process is made complex because reload will never
8637 process the insns we generate here and so we must ensure that
8638 they will fit their constraints and also by the fact that parts of
8639 IN might be being reloaded separately and replaced with spill registers.
8640 Because of this, we are, in some sense, just guessing the right approach
8641 here. The one listed above seems to work.
8643 ??? At some point, this whole thing needs to be rethought. */
8645 if (GET_CODE (in) == PLUS
8646 && (REG_P (XEXP (in, 0))
8647 || GET_CODE (XEXP (in, 0)) == SUBREG
8648 || MEM_P (XEXP (in, 0)))
8649 && (REG_P (XEXP (in, 1))
8650 || GET_CODE (XEXP (in, 1)) == SUBREG
8651 || CONSTANT_P (XEXP (in, 1))
8652 || MEM_P (XEXP (in, 1))))
8654 /* We need to compute the sum of a register or a MEM and another
8655 register, constant, or MEM, and put it into the reload
8656 register. The best possible way of doing this is if the machine
8657 has a three-operand ADD insn that accepts the required operands.
8659 The simplest approach is to try to generate such an insn and see if it
8660 is recognized and matches its constraints. If so, it can be used.
8662 It might be better not to actually emit the insn unless it is valid,
8663 but we need to pass the insn as an operand to `recog' and
8664 `extract_insn' and it is simpler to emit and then delete the insn if
8665 not valid than to dummy things up. */
8669 enum insn_code code;
8671 op0 = find_replacement (&XEXP (in, 0));
8672 op1 = find_replacement (&XEXP (in, 1));
8674 /* Since constraint checking is strict, commutativity won't be
8675 checked, so we need to do that here to avoid spurious failure
8676 if the add instruction is two-address and the second operand
8677 of the add is the same as the reload reg, which is frequently
8678 the case. If the insn would be A = B + A, rearrange it so
8679 it will be A = A + B as constrain_operands expects. */
8681 if (REG_P (XEXP (in, 1))
8682 && REGNO (out) == REGNO (XEXP (in, 1)))
8683 tem = op0, op0 = op1, op1 = tem;
8685 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8686 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8688 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8692 /* If that failed, we must use a conservative two-insn sequence.
8694 Use a move to copy one operand into the reload register. Prefer
8695 to reload a constant, MEM or pseudo since the move patterns can
8696 handle an arbitrary operand. If OP1 is not a constant, MEM or
8697 pseudo and OP1 is not a valid operand for an add instruction, then
8700 After reloading one of the operands into the reload register, add
8701 the reload register to the output register.
8703 If there is another way to do this for a specific machine, a
8704 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8707 code = optab_handler (add_optab, GET_MODE (out));
8709 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8711 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8712 || (code != CODE_FOR_nothing
8713 && !insn_operand_matches (code, 2, op1)))
8714 tem = op0, op0 = op1, op1 = tem;
8716 gen_reload (out, op0, opnum, type);
8718 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8719 This fixes a problem on the 32K where the stack pointer cannot
8720 be used as an operand of an add insn. */
8722 if (rtx_equal_p (op0, op1))
8725 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8728 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8729 set_dst_reg_note (insn, REG_EQUIV, in, out);
8733 /* If that failed, copy the address register to the reload register.
8734 Then add the constant to the reload register. */
8736 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8737 gen_reload (out, op1, opnum, type);
8738 insn = emit_insn (gen_add2_insn (out, op0));
8739 set_dst_reg_note (insn, REG_EQUIV, in, out);
8742 #ifdef SECONDARY_MEMORY_NEEDED
8743 /* If we need a memory location to do the move, do it that way. */
8744 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8745 (REG_P (tem1) && REG_P (tem2)))
8746 && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8747 && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8748 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1)),
8749 REGNO_REG_CLASS (REGNO (tem2)),
8752 /* Get the memory to use and rewrite both registers to its mode. */
8753 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8755 if (GET_MODE (loc) != GET_MODE (out))
8756 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8758 if (GET_MODE (loc) != GET_MODE (in))
8759 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8761 gen_reload (loc, in, opnum, type);
8762 gen_reload (out, loc, opnum, type);
8765 else if (REG_P (out) && UNARY_P (in))
8772 op1 = find_replacement (&XEXP (in, 0));
8773 if (op1 != XEXP (in, 0))
8774 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8776 /* First, try a plain SET. */
8777 set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8781 /* If that failed, move the inner operand to the reload
8782 register, and try the same unop with the inner expression
8783 replaced with the reload register. */
8785 if (GET_MODE (op1) != GET_MODE (out))
8786 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8790 gen_reload (out_moded, op1, opnum, type);
8792 insn = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8794 insn = emit_insn_if_valid_for_reload (insn);
8797 set_unique_reg_note (insn, REG_EQUIV, in);
8798 return as_a <rtx_insn *> (insn);
8801 fatal_insn ("failure trying to reload:", set);
8803 /* If IN is a simple operand, use gen_move_insn. */
8804 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8806 tem = emit_insn (gen_move_insn (out, in));
8807 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8808 mark_jump_label (in, tem, 0);
8811 else if (targetm.have_reload_load_address ())
8812 emit_insn (targetm.gen_reload_load_address (out, in));
8814 /* Otherwise, just write (set OUT IN) and hope for the best. */
8816 emit_insn (gen_rtx_SET (out, in));
8818 /* Return the first insn emitted.
8819 We can not just return get_last_insn, because there may have
8820 been multiple instructions emitted. Also note that gen_move_insn may
8821 emit more than one insn itself, so we can not assume that there is one
8822 insn emitted per emit_insn_before call. */
8824 return last ? NEXT_INSN (last) : get_insns ();
8827 /* Delete a previously made output-reload whose result we now believe
8828 is not needed. First we double-check.
8830 INSN is the insn now being processed.
8831 LAST_RELOAD_REG is the hard register number for which we want to delete
8832 the last output reload.
8833 J is the reload-number that originally used REG. The caller has made
8834 certain that reload J doesn't use REG any longer for input.
8835 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8838 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8841 rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8842 rtx reg = spill_reg_stored_to[last_reload_reg];
8845 int n_inherited = 0;
8850 /* It is possible that this reload has been only used to set another reload
8851 we eliminated earlier and thus deleted this instruction too. */
8852 if (output_reload_insn->deleted ())
8855 /* Get the raw pseudo-register referred to. */
8857 while (GET_CODE (reg) == SUBREG)
8858 reg = SUBREG_REG (reg);
8859 substed = reg_equiv_memory_loc (REGNO (reg));
8861 /* This is unsafe if the operand occurs more often in the current
8862 insn than it is inherited. */
8863 for (k = n_reloads - 1; k >= 0; k--)
8865 rtx reg2 = rld[k].in;
8868 if (MEM_P (reg2) || reload_override_in[k])
8869 reg2 = rld[k].in_reg;
8871 if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
8872 reg2 = XEXP (rld[k].in_reg, 0);
8874 while (GET_CODE (reg2) == SUBREG)
8875 reg2 = SUBREG_REG (reg2);
8876 if (rtx_equal_p (reg2, reg))
8878 if (reload_inherited[k] || reload_override_in[k] || k == j)
8884 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8885 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8886 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8889 n_occurrences += count_occurrences (PATTERN (insn),
8890 eliminate_regs (substed, VOIDmode,
8892 for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8894 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8895 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8897 if (n_occurrences > n_inherited)
8900 regno = REGNO (reg);
8901 if (regno >= FIRST_PSEUDO_REGISTER)
8904 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8906 /* If the pseudo-reg we are reloading is no longer referenced
8907 anywhere between the store into it and here,
8908 and we're within the same basic block, then the value can only
8909 pass through the reload reg and end up here.
8910 Otherwise, give up--return. */
8911 for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8912 i1 != insn; i1 = NEXT_INSN (i1))
8914 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8916 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8917 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8919 /* If this is USE in front of INSN, we only have to check that
8920 there are no more references than accounted for by inheritance. */
8921 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8923 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8924 i1 = NEXT_INSN (i1);
8926 if (n_occurrences <= n_inherited && i1 == insn)
8932 /* We will be deleting the insn. Remove the spill reg information. */
8933 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8935 spill_reg_store[last_reload_reg + k] = 0;
8936 spill_reg_stored_to[last_reload_reg + k] = 0;
8939 /* The caller has already checked that REG dies or is set in INSN.
8940 It has also checked that we are optimizing, and thus some
8941 inaccuracies in the debugging information are acceptable.
8942 So we could just delete output_reload_insn. But in some cases
8943 we can improve the debugging information without sacrificing
8944 optimization - maybe even improving the code: See if the pseudo
8945 reg has been completely replaced with reload regs. If so, delete
8946 the store insn and forget we had a stack slot for the pseudo. */
8947 if (rld[j].out != rld[j].in
8948 && REG_N_DEATHS (REGNO (reg)) == 1
8949 && REG_N_SETS (REGNO (reg)) == 1
8950 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8951 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8955 /* We know that it was used only between here and the beginning of
8956 the current basic block. (We also know that the last use before
8957 INSN was the output reload we are thinking of deleting, but never
8958 mind that.) Search that range; see if any ref remains. */
8959 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8961 rtx set = single_set (i2);
8963 /* Uses which just store in the pseudo don't count,
8964 since if they are the only uses, they are dead. */
8965 if (set != 0 && SET_DEST (set) == reg)
8967 if (LABEL_P (i2) || JUMP_P (i2))
8969 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8970 && reg_mentioned_p (reg, PATTERN (i2)))
8972 /* Some other ref remains; just delete the output reload we
8974 delete_address_reloads (output_reload_insn, insn);
8975 delete_insn (output_reload_insn);
8980 /* Delete the now-dead stores into this pseudo. Note that this
8981 loop also takes care of deleting output_reload_insn. */
8982 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8984 rtx set = single_set (i2);
8986 if (set != 0 && SET_DEST (set) == reg)
8988 delete_address_reloads (i2, insn);
8991 if (LABEL_P (i2) || JUMP_P (i2))
8995 /* For the debugging info, say the pseudo lives in this reload reg. */
8996 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8997 if (ira_conflicts_p)
8998 /* Inform IRA about the change. */
8999 ira_mark_allocation_change (REGNO (reg));
9000 alter_reg (REGNO (reg), -1, false);
9004 delete_address_reloads (output_reload_insn, insn);
9005 delete_insn (output_reload_insn);
9009 /* We are going to delete DEAD_INSN. Recursively delete loads of
9010 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9011 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
9013 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
9015 rtx set = single_set (dead_insn);
9017 rtx_insn *prev, *next;
9020 rtx dst = SET_DEST (set);
9022 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
9024 /* If we deleted the store from a reloaded post_{in,de}c expression,
9025 we can delete the matching adds. */
9026 prev = PREV_INSN (dead_insn);
9027 next = NEXT_INSN (dead_insn);
9028 if (! prev || ! next)
9030 set = single_set (next);
9031 set2 = single_set (prev);
9033 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
9034 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
9035 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
9037 dst = SET_DEST (set);
9038 if (! rtx_equal_p (dst, SET_DEST (set2))
9039 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
9040 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
9041 || (INTVAL (XEXP (SET_SRC (set), 1))
9042 != -INTVAL (XEXP (SET_SRC (set2), 1))))
9044 delete_related_insns (prev);
9045 delete_related_insns (next);
9048 /* Subfunction of delete_address_reloads: process registers found in X. */
9050 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
9052 rtx_insn *prev, *i2;
9055 enum rtx_code code = GET_CODE (x);
9059 const char *fmt = GET_RTX_FORMAT (code);
9060 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9063 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
9064 else if (fmt[i] == 'E')
9066 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9067 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
9074 if (spill_reg_order[REGNO (x)] < 0)
9077 /* Scan backwards for the insn that sets x. This might be a way back due
9079 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
9081 code = GET_CODE (prev);
9082 if (code == CODE_LABEL || code == JUMP_INSN)
9086 if (reg_set_p (x, PATTERN (prev)))
9088 if (reg_referenced_p (x, PATTERN (prev)))
9091 if (! prev || INSN_UID (prev) < reload_first_uid)
9093 /* Check that PREV only sets the reload register. */
9094 set = single_set (prev);
9097 dst = SET_DEST (set);
9099 || ! rtx_equal_p (dst, x))
9101 if (! reg_set_p (dst, PATTERN (dead_insn)))
9103 /* Check if DST was used in a later insn -
9104 it might have been inherited. */
9105 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9111 if (reg_referenced_p (dst, PATTERN (i2)))
9113 /* If there is a reference to the register in the current insn,
9114 it might be loaded in a non-inherited reload. If no other
9115 reload uses it, that means the register is set before
9117 if (i2 == current_insn)
9119 for (j = n_reloads - 1; j >= 0; j--)
9120 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9121 || reload_override_in[j] == dst)
9123 for (j = n_reloads - 1; j >= 0; j--)
9124 if (rld[j].in && rld[j].reg_rtx == dst)
9133 /* If DST is still live at CURRENT_INSN, check if it is used for
9134 any reload. Note that even if CURRENT_INSN sets DST, we still
9135 have to check the reloads. */
9136 if (i2 == current_insn)
9138 for (j = n_reloads - 1; j >= 0; j--)
9139 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9140 || reload_override_in[j] == dst)
9142 /* ??? We can't finish the loop here, because dst might be
9143 allocated to a pseudo in this block if no reload in this
9144 block needs any of the classes containing DST - see
9145 spill_hard_reg. There is no easy way to tell this, so we
9146 have to scan till the end of the basic block. */
9148 if (reg_set_p (dst, PATTERN (i2)))
9152 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9153 reg_reloaded_contents[REGNO (dst)] = -1;
9157 /* Output reload-insns to reload VALUE into RELOADREG.
9158 VALUE is an autoincrement or autodecrement RTX whose operand
9159 is a register or memory location;
9160 so reloading involves incrementing that location.
9161 IN is either identical to VALUE, or some cheaper place to reload from.
9163 INC_AMOUNT is the number to increment or decrement by (always positive).
9164 This cannot be deduced from VALUE. */
9167 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9169 /* REG or MEM to be copied and incremented. */
9170 rtx incloc = find_replacement (&XEXP (value, 0));
9171 /* Nonzero if increment after copying. */
9172 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9173 || GET_CODE (value) == POST_MODIFY);
9178 rtx real_in = in == value ? incloc : in;
9180 /* No hard register is equivalent to this register after
9181 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9182 we could inc/dec that register as well (maybe even using it for
9183 the source), but I'm not sure it's worth worrying about. */
9185 reg_last_reload_reg[REGNO (incloc)] = 0;
9187 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9189 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9190 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9194 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9195 inc_amount = -inc_amount;
9197 inc = GEN_INT (inc_amount);
9200 /* If this is post-increment, first copy the location to the reload reg. */
9201 if (post && real_in != reloadreg)
9202 emit_insn (gen_move_insn (reloadreg, real_in));
9206 /* See if we can directly increment INCLOC. Use a method similar to
9207 that in gen_reload. */
9209 last = get_last_insn ();
9210 add_insn = emit_insn (gen_rtx_SET (incloc,
9211 gen_rtx_PLUS (GET_MODE (incloc),
9214 code = recog_memoized (add_insn);
9217 extract_insn (add_insn);
9218 if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9220 /* If this is a pre-increment and we have incremented the value
9221 where it lives, copy the incremented value to RELOADREG to
9222 be used as an address. */
9225 emit_insn (gen_move_insn (reloadreg, incloc));
9229 delete_insns_since (last);
9232 /* If couldn't do the increment directly, must increment in RELOADREG.
9233 The way we do this depends on whether this is pre- or post-increment.
9234 For pre-increment, copy INCLOC to the reload register, increment it
9235 there, then save back. */
9239 if (in != reloadreg)
9240 emit_insn (gen_move_insn (reloadreg, real_in));
9241 emit_insn (gen_add2_insn (reloadreg, inc));
9242 emit_insn (gen_move_insn (incloc, reloadreg));
9247 Because this might be a jump insn or a compare, and because RELOADREG
9248 may not be available after the insn in an input reload, we must do
9249 the incrementation before the insn being reloaded for.
9251 We have already copied IN to RELOADREG. Increment the copy in
9252 RELOADREG, save that back, then decrement RELOADREG so it has
9253 the original value. */
9255 emit_insn (gen_add2_insn (reloadreg, inc));
9256 emit_insn (gen_move_insn (incloc, reloadreg));
9257 if (CONST_INT_P (inc))
9258 emit_insn (gen_add2_insn (reloadreg,
9259 gen_int_mode (-INTVAL (inc),
9260 GET_MODE (reloadreg))));
9262 emit_insn (gen_sub2_insn (reloadreg, inc));
9267 add_auto_inc_notes (rtx_insn *insn, rtx x)
9269 enum rtx_code code = GET_CODE (x);
9273 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9275 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9279 /* Scan all the operand sub-expressions. */
9280 fmt = GET_RTX_FORMAT (code);
9281 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9284 add_auto_inc_notes (insn, XEXP (x, i));
9285 else if (fmt[i] == 'E')
9286 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9287 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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