1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
36 #include "rtl-error.h"
38 #include "addresses.h"
45 #include "function-abi.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 struct target_reload default_target_reload;
83 struct target_reload *this_target_reload = &default_target_reload;
86 #define spill_indirect_levels \
87 (this_target_reload->x_spill_indirect_levels)
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static regset_head reg_has_output_reload;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
101 /* Widest mode in which each pseudo reg is referred to (via subreg). */
102 static machine_mode *reg_max_ref_mode;
104 /* Vector to remember old contents of reg_renumber before spilling. */
105 static short *reg_old_renumber;
107 /* During reload_as_needed, element N contains the last pseudo regno reloaded
108 into hard register N. If that pseudo reg occupied more than one register,
109 reg_reloaded_contents points to that pseudo for each spill register in
110 use; all of these must remain set for an inheritance to occur. */
111 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
113 /* During reload_as_needed, element N contains the insn for which
114 hard register N was last used. Its contents are significant only
115 when reg_reloaded_valid is set for this register. */
116 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
118 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
119 static HARD_REG_SET reg_reloaded_valid;
120 /* Indicate if the register was dead at the end of the reload.
121 This is only valid if reg_reloaded_contents is set and valid. */
122 static HARD_REG_SET reg_reloaded_dead;
124 /* Number of spill-regs so far; number of valid elements of spill_regs. */
127 /* In parallel with spill_regs, contains REG rtx's for those regs.
128 Holds the last rtx used for any given reg, or 0 if it has never
129 been used for spilling yet. This rtx is reused, provided it has
131 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
133 /* In parallel with spill_regs, contains nonzero for a spill reg
134 that was stored after the last time it was used.
135 The precise value is the insn generated to do the store. */
136 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
138 /* This is the register that was stored with spill_reg_store. This is a
139 copy of reload_out / reload_out_reg when the value was stored; if
140 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
143 /* This table is the inverse mapping of spill_regs:
144 indexed by hard reg number,
145 it contains the position of that reg in spill_regs,
146 or -1 for something that is not in spill_regs.
148 ?!? This is no longer accurate. */
149 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
151 /* This reg set indicates registers that can't be used as spill registers for
152 the currently processed insn. These are the hard registers which are live
153 during the insn, but not allocated to pseudos, as well as fixed
155 static HARD_REG_SET bad_spill_regs;
157 /* These are the hard registers that can't be used as spill register for any
158 insn. This includes registers used for user variables and registers that
159 we can't eliminate. A register that appears in this set also can't be used
160 to retry register allocation. */
161 static HARD_REG_SET bad_spill_regs_global;
163 /* Describes order of use of registers for reloading
164 of spilled pseudo-registers. `n_spills' is the number of
165 elements that are actually valid; new ones are added at the end.
167 Both spill_regs and spill_reg_order are used on two occasions:
168 once during find_reload_regs, where they keep track of the spill registers
169 for a single insn, but also during reload_as_needed where they show all
170 the registers ever used by reload. For the latter case, the information
171 is calculated during finish_spills. */
172 static short spill_regs[FIRST_PSEUDO_REGISTER];
174 /* This vector of reg sets indicates, for each pseudo, which hard registers
175 may not be used for retrying global allocation because the register was
176 formerly spilled from one of them. If we allowed reallocating a pseudo to
177 a register that it was already allocated to, reload might not
179 static HARD_REG_SET *pseudo_previous_regs;
181 /* This vector of reg sets indicates, for each pseudo, which hard
182 registers may not be used for retrying global allocation because they
183 are used as spill registers during one of the insns in which the
185 static HARD_REG_SET *pseudo_forbidden_regs;
187 /* All hard regs that have been used as spill registers for any insn are
188 marked in this set. */
189 static HARD_REG_SET used_spill_regs;
191 /* Index of last register assigned as a spill register. We allocate in
192 a round-robin fashion. */
193 static int last_spill_reg;
195 /* Record the stack slot for each spilled hard register. */
196 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
198 /* Width allocated so far for that stack slot. */
199 static poly_uint64_pod spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
201 /* Record which pseudos needed to be spilled. */
202 static regset_head spilled_pseudos;
204 /* Record which pseudos changed their allocation in finish_spills. */
205 static regset_head changed_allocation_pseudos;
207 /* Used for communication between order_regs_for_reload and count_pseudo.
208 Used to avoid counting one pseudo twice. */
209 static regset_head pseudos_counted;
211 /* First uid used by insns created by reload in this function.
212 Used in find_equiv_reg. */
213 int reload_first_uid;
215 /* Flag set by local-alloc or global-alloc if anything is live in
216 a call-clobbered reg across calls. */
217 int caller_save_needed;
219 /* Set to 1 while reload_as_needed is operating.
220 Required by some machines to handle any generated moves differently. */
221 int reload_in_progress = 0;
223 /* This obstack is used for allocation of rtl during register elimination.
224 The allocated storage can be freed once find_reloads has processed the
226 static struct obstack reload_obstack;
228 /* Points to the beginning of the reload_obstack. All insn_chain structures
229 are allocated first. */
230 static char *reload_startobj;
232 /* The point after all insn_chain structures. Used to quickly deallocate
233 memory allocated in copy_reloads during calculate_needs_all_insns. */
234 static char *reload_firstobj;
236 /* This points before all local rtl generated by register elimination.
237 Used to quickly free all memory after processing one insn. */
238 static char *reload_insn_firstobj;
240 /* List of insn_chain instructions, one for every insn that reload needs to
242 class insn_chain *reload_insn_chain;
244 /* TRUE if we potentially left dead insns in the insn stream and want to
245 run DCE immediately after reload, FALSE otherwise. */
246 static bool need_dce;
248 /* List of all insns needing reloads. */
249 static class insn_chain *insns_need_reload;
251 /* This structure is used to record information about register eliminations.
252 Each array entry describes one possible way of eliminating a register
253 in favor of another. If there is more than one way of eliminating a
254 particular register, the most preferred should be specified first. */
258 int from; /* Register number to be eliminated. */
259 int to; /* Register number used as replacement. */
260 poly_int64_pod initial_offset; /* Initial difference between values. */
261 int can_eliminate; /* Nonzero if this elimination can be done. */
262 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
263 target hook in previous scan over insns
265 poly_int64_pod offset; /* Current offset between the two regs. */
266 poly_int64_pod previous_offset; /* Offset at end of previous insn. */
267 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
268 rtx from_rtx; /* REG rtx for the register to be eliminated.
269 We cannot simply compare the number since
270 we might then spuriously replace a hard
271 register corresponding to a pseudo
272 assigned to the reg to be eliminated. */
273 rtx to_rtx; /* REG rtx for the replacement. */
276 static struct elim_table *reg_eliminate = 0;
278 /* This is an intermediate structure to initialize the table. It has
279 exactly the members provided by ELIMINABLE_REGS. */
280 static const struct elim_table_1
284 } reg_eliminate_1[] =
288 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
290 /* Record the number of pending eliminations that have an offset not equal
291 to their initial offset. If nonzero, we use a new copy of each
292 replacement result in any insns encountered. */
293 int num_not_at_initial_offset;
295 /* Count the number of registers that we may be able to eliminate. */
296 static int num_eliminable;
297 /* And the number of registers that are equivalent to a constant that
298 can be eliminated to frame_pointer / arg_pointer + constant. */
299 static int num_eliminable_invariants;
301 /* For each label, we record the offset of each elimination. If we reach
302 a label by more than one path and an offset differs, we cannot do the
303 elimination. This information is indexed by the difference of the
304 number of the label and the first label number. We can't offset the
305 pointer itself as this can cause problems on machines with segmented
306 memory. The first table is an array of flags that records whether we
307 have yet encountered a label and the second table is an array of arrays,
308 one entry in the latter array for each elimination. */
310 static int first_label_num;
311 static char *offsets_known_at;
312 static poly_int64_pod (*offsets_at)[NUM_ELIMINABLE_REGS];
314 vec<reg_equivs_t, va_gc> *reg_equivs;
316 /* Stack of addresses where an rtx has been changed. We can undo the
317 changes by popping items off the stack and restoring the original
318 value at each location.
320 We use this simplistic undo capability rather than copy_rtx as copy_rtx
321 will not make a deep copy of a normally sharable rtx, such as
322 (const (plus (symbol_ref) (const_int))). If such an expression appears
323 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
324 rtx expression would be changed. See PR 42431. */
327 static vec<rtx_p> substitute_stack;
329 /* Number of labels in the current function. */
331 static int num_labels;
333 static void replace_pseudos_in (rtx *, machine_mode, rtx);
334 static void maybe_fix_stack_asms (void);
335 static void copy_reloads (class insn_chain *);
336 static void calculate_needs_all_insns (int);
337 static int find_reg (class insn_chain *, int);
338 static void find_reload_regs (class insn_chain *);
339 static void select_reload_regs (void);
340 static void delete_caller_save_insns (void);
342 static void spill_failure (rtx_insn *, enum reg_class);
343 static void count_spilled_pseudo (int, int, int);
344 static void delete_dead_insn (rtx_insn *);
345 static void alter_reg (int, int, bool);
346 static void set_label_offsets (rtx, rtx_insn *, int);
347 static void check_eliminable_occurrences (rtx);
348 static void elimination_effects (rtx, machine_mode);
349 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
350 static int eliminate_regs_in_insn (rtx_insn *, int);
351 static void update_eliminable_offsets (void);
352 static void mark_not_eliminable (rtx, const_rtx, void *);
353 static void set_initial_elim_offsets (void);
354 static bool verify_initial_elim_offsets (void);
355 static void set_initial_label_offsets (void);
356 static void set_offsets_for_label (rtx_insn *);
357 static void init_eliminable_invariants (rtx_insn *, bool);
358 static void init_elim_table (void);
359 static void free_reg_equiv (void);
360 static void update_eliminables (HARD_REG_SET *);
361 static bool update_eliminables_and_spill (void);
362 static void elimination_costs_in_insn (rtx_insn *);
363 static void spill_hard_reg (unsigned int, int);
364 static int finish_spills (int);
365 static void scan_paradoxical_subregs (rtx);
366 static void count_pseudo (int);
367 static void order_regs_for_reload (class insn_chain *);
368 static void reload_as_needed (int);
369 static void forget_old_reloads_1 (rtx, const_rtx, void *);
370 static void forget_marked_reloads (regset);
371 static int reload_reg_class_lower (const void *, const void *);
372 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
374 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
376 static int reload_reg_free_p (unsigned int, int, enum reload_type);
377 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
379 static int free_for_value_p (int, machine_mode, int, enum reload_type,
381 static int allocate_reload_reg (class insn_chain *, int, int);
382 static int conflicts_with_override (rtx);
383 static void failed_reload (rtx_insn *, int);
384 static int set_reload_reg (int, int);
385 static void choose_reload_regs_init (class insn_chain *, rtx *);
386 static void choose_reload_regs (class insn_chain *);
387 static void emit_input_reload_insns (class insn_chain *, struct reload *,
389 static void emit_output_reload_insns (class insn_chain *, struct reload *,
391 static void do_input_reload (class insn_chain *, struct reload *, int);
392 static void do_output_reload (class insn_chain *, struct reload *, int);
393 static void emit_reload_insns (class insn_chain *);
394 static void delete_output_reload (rtx_insn *, int, int, rtx);
395 static void delete_address_reloads (rtx_insn *, rtx_insn *);
396 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
397 static void inc_for_reload (rtx, rtx, rtx, poly_int64);
398 static void add_auto_inc_notes (rtx_insn *, rtx);
399 static void substitute (rtx *, const_rtx, rtx);
400 static bool gen_reload_chain_without_interm_reg_p (int, int);
401 static int reloads_conflict (int, int);
402 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
403 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
405 /* Initialize the reload pass. This is called at the beginning of compilation
406 and may be called again if the target is reinitialized. */
413 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
414 Set spill_indirect_levels to the number of levels such addressing is
415 permitted, zero if it is not permitted at all. */
418 = gen_rtx_MEM (Pmode,
421 LAST_VIRTUAL_REGISTER + 1),
422 gen_int_mode (4, Pmode)));
423 spill_indirect_levels = 0;
425 while (memory_address_p (QImode, tem))
427 spill_indirect_levels++;
428 tem = gen_rtx_MEM (Pmode, tem);
431 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
433 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
434 indirect_symref_ok = memory_address_p (QImode, tem);
436 /* See if reg+reg is a valid (and offsettable) address. */
438 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
440 tem = gen_rtx_PLUS (Pmode,
441 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
442 gen_rtx_REG (Pmode, i));
444 /* This way, we make sure that reg+reg is an offsettable address. */
445 tem = plus_constant (Pmode, tem, 4);
447 for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
448 if (!double_reg_address_ok[mode]
449 && memory_address_p ((enum machine_mode)mode, tem))
450 double_reg_address_ok[mode] = 1;
453 /* Initialize obstack for our rtl allocation. */
454 if (reload_startobj == NULL)
456 gcc_obstack_init (&reload_obstack);
457 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
460 INIT_REG_SET (&spilled_pseudos);
461 INIT_REG_SET (&changed_allocation_pseudos);
462 INIT_REG_SET (&pseudos_counted);
465 /* List of insn chains that are currently unused. */
466 static class insn_chain *unused_insn_chains = 0;
468 /* Allocate an empty insn_chain structure. */
470 new_insn_chain (void)
474 if (unused_insn_chains == 0)
476 c = XOBNEW (&reload_obstack, class insn_chain);
477 INIT_REG_SET (&c->live_throughout);
478 INIT_REG_SET (&c->dead_or_set);
482 c = unused_insn_chains;
483 unused_insn_chains = c->next;
485 c->is_caller_save_insn = 0;
486 c->need_operand_change = 0;
492 /* Small utility function to set all regs in hard reg set TO which are
493 allocated to pseudos in regset FROM. */
496 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
499 reg_set_iterator rsi;
501 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
503 int r = reg_renumber[regno];
507 /* reload_combine uses the information from DF_LIVE_IN,
508 which might still contain registers that have not
509 actually been allocated since they have an
511 gcc_assert (ira_conflicts_p || reload_completed);
514 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
518 /* Replace all pseudos found in LOC with their corresponding
522 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
535 unsigned int regno = REGNO (x);
537 if (regno < FIRST_PSEUDO_REGISTER)
540 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
544 replace_pseudos_in (loc, mem_mode, usage);
548 if (reg_equiv_constant (regno))
549 *loc = reg_equiv_constant (regno);
550 else if (reg_equiv_invariant (regno))
551 *loc = reg_equiv_invariant (regno);
552 else if (reg_equiv_mem (regno))
553 *loc = reg_equiv_mem (regno);
554 else if (reg_equiv_address (regno))
555 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
558 gcc_assert (!REG_P (regno_reg_rtx[regno])
559 || REGNO (regno_reg_rtx[regno]) != regno);
560 *loc = regno_reg_rtx[regno];
565 else if (code == MEM)
567 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
571 /* Process each of our operands recursively. */
572 fmt = GET_RTX_FORMAT (code);
573 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
575 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
576 else if (*fmt == 'E')
577 for (j = 0; j < XVECLEN (x, i); j++)
578 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
581 /* Determine if the current function has an exception receiver block
582 that reaches the exit block via non-exceptional edges */
585 has_nonexceptional_receiver (void)
589 basic_block *tos, *worklist, bb;
591 /* If we're not optimizing, then just err on the safe side. */
595 /* First determine which blocks can reach exit via normal paths. */
596 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
598 FOR_EACH_BB_FN (bb, cfun)
599 bb->flags &= ~BB_REACHABLE;
601 /* Place the exit block on our worklist. */
602 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
603 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
605 /* Iterate: find everything reachable from what we've already seen. */
606 while (tos != worklist)
610 FOR_EACH_EDGE (e, ei, bb->preds)
611 if (!(e->flags & EDGE_ABNORMAL))
613 basic_block src = e->src;
615 if (!(src->flags & BB_REACHABLE))
617 src->flags |= BB_REACHABLE;
624 /* Now see if there's a reachable block with an exceptional incoming
626 FOR_EACH_BB_FN (bb, cfun)
627 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
630 /* No exceptional block reached exit unexceptionally. */
634 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
635 zero elements) to MAX_REG_NUM elements.
637 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
639 grow_reg_equivs (void)
641 int old_size = vec_safe_length (reg_equivs);
642 int max_regno = max_reg_num ();
646 memset (&ze, 0, sizeof (reg_equivs_t));
647 vec_safe_reserve (reg_equivs, max_regno);
648 for (i = old_size; i < max_regno; i++)
649 reg_equivs->quick_insert (i, ze);
653 /* Global variables used by reload and its subroutines. */
655 /* The current basic block while in calculate_elim_costs_all_insns. */
656 static basic_block elim_bb;
658 /* Set during calculate_needs if an insn needs register elimination. */
659 static int something_needs_elimination;
660 /* Set during calculate_needs if an insn needs an operand changed. */
661 static int something_needs_operands_changed;
662 /* Set by alter_regs if we spilled a register to the stack. */
663 static bool something_was_spilled;
665 /* Nonzero means we couldn't get enough spill regs. */
668 /* Temporary array of pseudo-register number. */
669 static int *temp_pseudo_reg_arr;
671 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
672 If that insn didn't set the register (i.e., it copied the register to
673 memory), just delete that insn instead of the equivalencing insn plus
674 anything now dead. If we call delete_dead_insn on that insn, we may
675 delete the insn that actually sets the register if the register dies
676 there and that is incorrect. */
680 for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
682 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
685 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
687 rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
689 /* If we already deleted the insn or if it may trap, we can't
690 delete it. The latter case shouldn't happen, but can
691 if an insn has a variable address, gets a REG_EH_REGION
692 note added to it, and then gets converted into a load
693 from a constant address. */
694 if (NOTE_P (equiv_insn)
695 || can_throw_internal (equiv_insn))
697 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
698 delete_dead_insn (equiv_insn);
700 SET_INSN_DELETED (equiv_insn);
706 /* Return true if remove_init_insns will delete INSN. */
708 will_delete_init_insn_p (rtx_insn *insn)
710 rtx set = single_set (insn);
711 if (!set || !REG_P (SET_DEST (set)))
713 unsigned regno = REGNO (SET_DEST (set));
715 if (can_throw_internal (insn))
718 if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
721 for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
723 rtx equiv_insn = XEXP (list, 0);
724 if (equiv_insn == insn)
730 /* Main entry point for the reload pass.
732 FIRST is the first insn of the function being compiled.
734 GLOBAL nonzero means we were called from global_alloc
735 and should attempt to reallocate any pseudoregs that we
736 displace from hard regs we will use for reloads.
737 If GLOBAL is zero, we do not have enough information to do that,
738 so any pseudo reg that is spilled must go to the stack.
740 Return value is TRUE if reload likely left dead insns in the
741 stream and a DCE pass should be run to elimiante them. Else the
742 return value is FALSE. */
745 reload (rtx_insn *first, int global)
749 struct elim_table *ep;
753 /* Make sure even insns with volatile mem refs are recognizable. */
758 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
760 /* Make sure that the last insn in the chain
761 is not something that needs reloading. */
762 emit_note (NOTE_INSN_DELETED);
764 /* Enable find_equiv_reg to distinguish insns made by reload. */
765 reload_first_uid = get_max_uid ();
767 /* Initialize the secondary memory table. */
768 clear_secondary_mem ();
770 /* We don't have a stack slot for any spill reg yet. */
771 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
772 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
774 /* Initialize the save area information for caller-save, in case some
778 /* Compute which hard registers are now in use
779 as homes for pseudo registers.
780 This is done here rather than (eg) in global_alloc
781 because this point is reached even if not optimizing. */
782 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
785 /* A function that has a nonlocal label that can reach the exit
786 block via non-exceptional paths must save all call-saved
788 if (cfun->has_nonlocal_label
789 && has_nonexceptional_receiver ())
790 crtl->saves_all_registers = 1;
792 if (crtl->saves_all_registers)
793 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
794 if (! crtl->abi->clobbers_full_reg_p (i)
796 && ! LOCAL_REGNO (i))
797 df_set_regs_ever_live (i, true);
799 /* Find all the pseudo registers that didn't get hard regs
800 but do have known equivalent constants or memory slots.
801 These include parameters (known equivalent to parameter slots)
802 and cse'd or loop-moved constant memory addresses.
804 Record constant equivalents in reg_equiv_constant
805 so they will be substituted by find_reloads.
806 Record memory equivalents in reg_mem_equiv so they can
807 be substituted eventually by altering the REG-rtx's. */
810 reg_old_renumber = XCNEWVEC (short, max_regno);
811 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
812 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
813 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
815 CLEAR_HARD_REG_SET (bad_spill_regs_global);
817 init_eliminable_invariants (first, true);
820 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
821 stack slots to the pseudos that lack hard regs or equivalents.
822 Do not touch virtual registers. */
824 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
825 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
826 temp_pseudo_reg_arr[n++] = i;
829 /* Ask IRA to order pseudo-registers for better stack slot
831 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);
833 for (i = 0; i < n; i++)
834 alter_reg (temp_pseudo_reg_arr[i], -1, false);
836 /* If we have some registers we think can be eliminated, scan all insns to
837 see if there is an insn that sets one of these registers to something
838 other than itself plus a constant. If so, the register cannot be
839 eliminated. Doing this scan here eliminates an extra pass through the
840 main reload loop in the most common case where register elimination
842 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
844 note_pattern_stores (PATTERN (insn), mark_not_eliminable, NULL);
846 maybe_fix_stack_asms ();
848 insns_need_reload = 0;
849 something_needs_elimination = 0;
851 /* Initialize to -1, which means take the first spill register. */
854 /* Spill any hard regs that we know we can't eliminate. */
855 CLEAR_HARD_REG_SET (used_spill_regs);
856 /* There can be multiple ways to eliminate a register;
857 they should be listed adjacently.
858 Elimination for any register fails only if all possible ways fail. */
859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
862 int can_eliminate = 0;
865 can_eliminate |= ep->can_eliminate;
868 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
870 spill_hard_reg (from, 1);
873 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
874 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
876 finish_spills (global);
878 /* From now on, we may need to generate moves differently. We may also
879 allow modifications of insns which cause them to not be recognized.
880 Any such modifications will be cleaned up during reload itself. */
881 reload_in_progress = 1;
883 /* This loop scans the entire function each go-round
884 and repeats until one repetition spills no additional hard regs. */
887 int something_changed;
888 poly_int64 starting_frame_size;
890 starting_frame_size = get_frame_size ();
891 something_was_spilled = false;
893 set_initial_elim_offsets ();
894 set_initial_label_offsets ();
896 /* For each pseudo register that has an equivalent location defined,
897 try to eliminate any eliminable registers (such as the frame pointer)
898 assuming initial offsets for the replacement register, which
901 If the resulting location is directly addressable, substitute
902 the MEM we just got directly for the old REG.
904 If it is not addressable but is a constant or the sum of a hard reg
905 and constant, it is probably not addressable because the constant is
906 out of range, in that case record the address; we will generate
907 hairy code to compute the address in a register each time it is
908 needed. Similarly if it is a hard register, but one that is not
909 valid as an address register.
911 If the location is not addressable, but does not have one of the
912 above forms, assign a stack slot. We have to do this to avoid the
913 potential of producing lots of reloads if, e.g., a location involves
914 a pseudo that didn't get a hard register and has an equivalent memory
915 location that also involves a pseudo that didn't get a hard register.
917 Perhaps at some point we will improve reload_when_needed handling
918 so this problem goes away. But that's very hairy. */
920 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
921 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
923 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
926 if (strict_memory_address_addr_space_p
927 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
929 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
930 else if (CONSTANT_P (XEXP (x, 0))
931 || (REG_P (XEXP (x, 0))
932 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
933 || (GET_CODE (XEXP (x, 0)) == PLUS
934 && REG_P (XEXP (XEXP (x, 0), 0))
935 && (REGNO (XEXP (XEXP (x, 0), 0))
936 < FIRST_PSEUDO_REGISTER)
937 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
938 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
941 /* Make a new stack slot. Then indicate that something
942 changed so we go back and recompute offsets for
943 eliminable registers because the allocation of memory
944 below might change some offset. reg_equiv_{mem,address}
945 will be set up for this pseudo on the next pass around
947 reg_equiv_memory_loc (i) = 0;
948 reg_equiv_init (i) = 0;
949 alter_reg (i, -1, true);
953 if (caller_save_needed)
956 if (maybe_ne (starting_frame_size, 0) && crtl->stack_alignment_needed)
958 /* If we have a stack frame, we must align it now. The
959 stack size may be a part of the offset computation for
960 register elimination. So if this changes the stack size,
961 then repeat the elimination bookkeeping. We don't
962 realign when there is no stack, as that will cause a
963 stack frame when none is needed should
964 TARGET_STARTING_FRAME_OFFSET not be already aligned to
966 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
968 /* If we allocated another stack slot, redo elimination bookkeeping. */
969 if (something_was_spilled
970 || maybe_ne (starting_frame_size, get_frame_size ()))
972 if (update_eliminables_and_spill ())
977 if (caller_save_needed)
979 save_call_clobbered_regs ();
980 /* That might have allocated new insn_chain structures. */
981 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
984 calculate_needs_all_insns (global);
986 if (! ira_conflicts_p)
987 /* Don't do it for IRA. We need this info because we don't
988 change live_throughout and dead_or_set for chains when IRA
990 CLEAR_REG_SET (&spilled_pseudos);
992 something_changed = 0;
994 /* If we allocated any new memory locations, make another pass
995 since it might have changed elimination offsets. */
996 if (something_was_spilled
997 || maybe_ne (starting_frame_size, get_frame_size ()))
998 something_changed = 1;
1000 /* Even if the frame size remained the same, we might still have
1001 changed elimination offsets, e.g. if find_reloads called
1002 force_const_mem requiring the back end to allocate a constant
1003 pool base register that needs to be saved on the stack. */
1004 else if (!verify_initial_elim_offsets ())
1005 something_changed = 1;
1007 if (update_eliminables_and_spill ())
1010 something_changed = 1;
1014 select_reload_regs ();
1017 if (insns_need_reload)
1018 something_changed |= finish_spills (global);
1021 if (! something_changed)
1024 if (caller_save_needed)
1025 delete_caller_save_insns ();
1027 obstack_free (&reload_obstack, reload_firstobj);
1030 /* If global-alloc was run, notify it of any register eliminations we have
1033 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1034 if (ep->can_eliminate)
1035 mark_elimination (ep->from, ep->to);
1037 remove_init_insns ();
1039 /* Use the reload registers where necessary
1040 by generating move instructions to move the must-be-register
1041 values into or out of the reload registers. */
1043 if (insns_need_reload != 0 || something_needs_elimination
1044 || something_needs_operands_changed)
1046 poly_int64 old_frame_size = get_frame_size ();
1048 reload_as_needed (global);
1050 gcc_assert (known_eq (old_frame_size, get_frame_size ()));
1052 gcc_assert (verify_initial_elim_offsets ());
1055 /* If we were able to eliminate the frame pointer, show that it is no
1056 longer live at the start of any basic block. If it ls live by
1057 virtue of being in a pseudo, that pseudo will be marked live
1058 and hence the frame pointer will be known to be live via that
1061 if (! frame_pointer_needed)
1062 FOR_EACH_BB_FN (bb, cfun)
1063 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1065 /* Come here (with failure set nonzero) if we can't get enough spill
1069 CLEAR_REG_SET (&changed_allocation_pseudos);
1070 CLEAR_REG_SET (&spilled_pseudos);
1071 reload_in_progress = 0;
1073 /* Now eliminate all pseudo regs by modifying them into
1074 their equivalent memory references.
1075 The REG-rtx's for the pseudos are modified in place,
1076 so all insns that used to refer to them now refer to memory.
1078 For a reg that has a reg_equiv_address, all those insns
1079 were changed by reloading so that no insns refer to it any longer;
1080 but the DECL_RTL of a variable decl may refer to it,
1081 and if so this causes the debugging info to mention the variable. */
1083 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1087 if (reg_equiv_mem (i))
1088 addr = XEXP (reg_equiv_mem (i), 0);
1090 if (reg_equiv_address (i))
1091 addr = reg_equiv_address (i);
1095 if (reg_renumber[i] < 0)
1097 rtx reg = regno_reg_rtx[i];
1099 REG_USERVAR_P (reg) = 0;
1100 PUT_CODE (reg, MEM);
1101 XEXP (reg, 0) = addr;
1102 if (reg_equiv_memory_loc (i))
1103 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1105 MEM_ATTRS (reg) = 0;
1106 MEM_NOTRAP_P (reg) = 1;
1108 else if (reg_equiv_mem (i))
1109 XEXP (reg_equiv_mem (i), 0) = addr;
1112 /* We don't want complex addressing modes in debug insns
1113 if simpler ones will do, so delegitimize equivalences
1115 if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0)
1117 rtx reg = regno_reg_rtx[i];
1121 if (reg_equiv_constant (i))
1122 equiv = reg_equiv_constant (i);
1123 else if (reg_equiv_invariant (i))
1124 equiv = reg_equiv_invariant (i);
1125 else if (reg && MEM_P (reg))
1126 equiv = targetm.delegitimize_address (reg);
1127 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1133 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1135 insn = DF_REF_INSN (use);
1137 /* Make sure the next ref is for a different instruction,
1138 so that we're not affected by the rescan. */
1139 next = DF_REF_NEXT_REG (use);
1140 while (next && DF_REF_INSN (next) == insn)
1141 next = DF_REF_NEXT_REG (next);
1143 if (DEBUG_BIND_INSN_P (insn))
1147 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1148 df_insn_rescan_debug_internal (insn);
1151 INSN_VAR_LOCATION_LOC (insn)
1152 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1159 /* We must set reload_completed now since the cleanup_subreg_operands call
1160 below will re-recognize each insn and reload may have generated insns
1161 which are only valid during and after reload. */
1162 reload_completed = 1;
1164 /* Make a pass over all the insns and delete all USEs which we inserted
1165 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1166 notes. Delete all CLOBBER insns, except those that refer to the return
1167 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1168 from misarranging variable-array code, and simplify (subreg (reg))
1169 operands. Strip and regenerate REG_INC notes that may have been moved
1172 for (insn = first; insn; insn = NEXT_INSN (insn))
1178 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1179 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1181 if ((GET_CODE (PATTERN (insn)) == USE
1182 /* We mark with QImode USEs introduced by reload itself. */
1183 && (GET_MODE (insn) == QImode
1184 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1185 || (GET_CODE (PATTERN (insn)) == CLOBBER
1186 && (!MEM_P (XEXP (PATTERN (insn), 0))
1187 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1188 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1189 && XEXP (XEXP (PATTERN (insn), 0), 0)
1190 != stack_pointer_rtx))
1191 && (!REG_P (XEXP (PATTERN (insn), 0))
1192 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1198 /* Some CLOBBERs may survive until here and still reference unassigned
1199 pseudos with const equivalent, which may in turn cause ICE in later
1200 passes if the reference remains in place. */
1201 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1202 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1203 VOIDmode, PATTERN (insn));
1205 /* Discard obvious no-ops, even without -O. This optimization
1206 is fast and doesn't interfere with debugging. */
1207 if (NONJUMP_INSN_P (insn)
1208 && GET_CODE (PATTERN (insn)) == SET
1209 && REG_P (SET_SRC (PATTERN (insn)))
1210 && REG_P (SET_DEST (PATTERN (insn)))
1211 && (REGNO (SET_SRC (PATTERN (insn)))
1212 == REGNO (SET_DEST (PATTERN (insn)))))
1218 pnote = ®_NOTES (insn);
1221 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1222 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1223 || REG_NOTE_KIND (*pnote) == REG_INC)
1224 *pnote = XEXP (*pnote, 1);
1226 pnote = &XEXP (*pnote, 1);
1230 add_auto_inc_notes (insn, PATTERN (insn));
1232 /* Simplify (subreg (reg)) if it appears as an operand. */
1233 cleanup_subreg_operands (insn);
1235 /* Clean up invalid ASMs so that they don't confuse later passes.
1237 if (asm_noperands (PATTERN (insn)) >= 0)
1239 extract_insn (insn);
1240 if (!constrain_operands (1, get_enabled_alternatives (insn)))
1242 error_for_asm (insn,
1243 "%<asm%> operand has impossible constraints");
1250 free (temp_pseudo_reg_arr);
1252 /* Indicate that we no longer have known memory locations or constants. */
1255 free (reg_max_ref_mode);
1256 free (reg_old_renumber);
1257 free (pseudo_previous_regs);
1258 free (pseudo_forbidden_regs);
1260 CLEAR_HARD_REG_SET (used_spill_regs);
1261 for (i = 0; i < n_spills; i++)
1262 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1264 /* Free all the insn_chain structures at once. */
1265 obstack_free (&reload_obstack, reload_startobj);
1266 unused_insn_chains = 0;
1268 inserted = fixup_abnormal_edges ();
1270 /* We've possibly turned single trapping insn into multiple ones. */
1271 if (cfun->can_throw_non_call_exceptions)
1273 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
1274 bitmap_ones (blocks);
1275 find_many_sub_basic_blocks (blocks);
1279 commit_edge_insertions ();
1281 /* Replacing pseudos with their memory equivalents might have
1282 created shared rtx. Subsequent passes would get confused
1283 by this, so unshare everything here. */
1284 unshare_all_rtl_again (first);
1286 #ifdef STACK_BOUNDARY
1287 /* init_emit has set the alignment of the hard frame pointer
1288 to STACK_BOUNDARY. It is very likely no longer valid if
1289 the hard frame pointer was used for register allocation. */
1290 if (!frame_pointer_needed)
1291 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1294 substitute_stack.release ();
1296 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1298 reload_completed = !failure;
1303 /* Yet another special case. Unfortunately, reg-stack forces people to
1304 write incorrect clobbers in asm statements. These clobbers must not
1305 cause the register to appear in bad_spill_regs, otherwise we'll call
1306 fatal_insn later. We clear the corresponding regnos in the live
1307 register sets to avoid this.
1308 The whole thing is rather sick, I'm afraid. */
1311 maybe_fix_stack_asms (void)
1314 const char *constraints[MAX_RECOG_OPERANDS];
1315 machine_mode operand_mode[MAX_RECOG_OPERANDS];
1316 class insn_chain *chain;
1318 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1321 HARD_REG_SET clobbered, allowed;
1324 if (! INSN_P (chain->insn)
1325 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1327 pat = PATTERN (chain->insn);
1328 if (GET_CODE (pat) != PARALLEL)
1331 CLEAR_HARD_REG_SET (clobbered);
1332 CLEAR_HARD_REG_SET (allowed);
1334 /* First, make a mask of all stack regs that are clobbered. */
1335 for (i = 0; i < XVECLEN (pat, 0); i++)
1337 rtx t = XVECEXP (pat, 0, i);
1338 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1339 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1340 /* CLOBBER_HIGH is only supported for LRA. */
1341 gcc_assert (GET_CODE (t) != CLOBBER_HIGH);
1344 /* Get the operand values and constraints out of the insn. */
1345 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1346 constraints, operand_mode, NULL);
1348 /* For every operand, see what registers are allowed. */
1349 for (i = 0; i < noperands; i++)
1351 const char *p = constraints[i];
1352 /* For every alternative, we compute the class of registers allowed
1353 for reloading in CLS, and merge its contents into the reg set
1355 int cls = (int) NO_REGS;
1361 if (c == '\0' || c == ',' || c == '#')
1363 /* End of one alternative - mark the regs in the current
1364 class, and reset the class. */
1365 allowed |= reg_class_contents[cls];
1371 } while (c != '\0' && c != ',');
1380 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1384 enum constraint_num cn = lookup_constraint (p);
1385 if (insn_extra_address_constraint (cn))
1386 cls = (int) reg_class_subunion[cls]
1387 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1390 cls = (int) reg_class_subunion[cls]
1391 [reg_class_for_constraint (cn)];
1394 p += CONSTRAINT_LEN (c, p);
1397 /* Those of the registers which are clobbered, but allowed by the
1398 constraints, must be usable as reload registers. So clear them
1399 out of the life information. */
1400 allowed &= clobbered;
1401 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1402 if (TEST_HARD_REG_BIT (allowed, i))
1404 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1405 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1412 /* Copy the global variables n_reloads and rld into the corresponding elts
1415 copy_reloads (class insn_chain *chain)
1417 chain->n_reloads = n_reloads;
1418 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1419 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1420 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1423 /* Walk the chain of insns, and determine for each whether it needs reloads
1424 and/or eliminations. Build the corresponding insns_need_reload list, and
1425 set something_needs_elimination as appropriate. */
1427 calculate_needs_all_insns (int global)
1429 class insn_chain **pprev_reload = &insns_need_reload;
1430 class insn_chain *chain, *next = 0;
1432 something_needs_elimination = 0;
1434 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1435 for (chain = reload_insn_chain; chain != 0; chain = next)
1437 rtx_insn *insn = chain->insn;
1441 /* Clear out the shortcuts. */
1442 chain->n_reloads = 0;
1443 chain->need_elim = 0;
1444 chain->need_reload = 0;
1445 chain->need_operand_change = 0;
1447 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1448 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1449 what effects this has on the known offsets at labels. */
1451 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1452 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1453 set_label_offsets (insn, insn, 0);
1457 rtx old_body = PATTERN (insn);
1458 int old_code = INSN_CODE (insn);
1459 rtx old_notes = REG_NOTES (insn);
1460 int did_elimination = 0;
1461 int operands_changed = 0;
1463 /* Skip insns that only set an equivalence. */
1464 if (will_delete_init_insn_p (insn))
1467 /* If needed, eliminate any eliminable registers. */
1468 if (num_eliminable || num_eliminable_invariants)
1469 did_elimination = eliminate_regs_in_insn (insn, 0);
1471 /* Analyze the instruction. */
1472 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1473 global, spill_reg_order);
1475 /* If a no-op set needs more than one reload, this is likely
1476 to be something that needs input address reloads. We
1477 can't get rid of this cleanly later, and it is of no use
1478 anyway, so discard it now.
1479 We only do this when expensive_optimizations is enabled,
1480 since this complements reload inheritance / output
1481 reload deletion, and it can make debugging harder. */
1482 if (flag_expensive_optimizations && n_reloads > 1)
1484 rtx set = single_set (insn);
1487 ((SET_SRC (set) == SET_DEST (set)
1488 && REG_P (SET_SRC (set))
1489 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1490 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1491 && reg_renumber[REGNO (SET_SRC (set))] < 0
1492 && reg_renumber[REGNO (SET_DEST (set))] < 0
1493 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1494 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1495 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1496 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1498 if (ira_conflicts_p)
1499 /* Inform IRA about the insn deletion. */
1500 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1501 REGNO (SET_SRC (set)));
1503 /* Delete it from the reload chain. */
1505 chain->prev->next = next;
1507 reload_insn_chain = next;
1509 next->prev = chain->prev;
1510 chain->next = unused_insn_chains;
1511 unused_insn_chains = chain;
1516 update_eliminable_offsets ();
1518 /* Remember for later shortcuts which insns had any reloads or
1519 register eliminations. */
1520 chain->need_elim = did_elimination;
1521 chain->need_reload = n_reloads > 0;
1522 chain->need_operand_change = operands_changed;
1524 /* Discard any register replacements done. */
1525 if (did_elimination)
1527 obstack_free (&reload_obstack, reload_insn_firstobj);
1528 PATTERN (insn) = old_body;
1529 INSN_CODE (insn) = old_code;
1530 REG_NOTES (insn) = old_notes;
1531 something_needs_elimination = 1;
1534 something_needs_operands_changed |= operands_changed;
1538 copy_reloads (chain);
1539 *pprev_reload = chain;
1540 pprev_reload = &chain->next_need_reload;
1547 /* This function is called from the register allocator to set up estimates
1548 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1549 an invariant. The structure is similar to calculate_needs_all_insns. */
1552 calculate_elim_costs_all_insns (void)
1554 int *reg_equiv_init_cost;
1558 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1560 init_eliminable_invariants (get_insns (), false);
1562 set_initial_elim_offsets ();
1563 set_initial_label_offsets ();
1565 FOR_EACH_BB_FN (bb, cfun)
1570 FOR_BB_INSNS (bb, insn)
1572 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1573 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1574 what effects this has on the known offsets at labels. */
1576 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1577 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1578 set_label_offsets (insn, insn, 0);
1582 rtx set = single_set (insn);
1584 /* Skip insns that only set an equivalence. */
1585 if (set && REG_P (SET_DEST (set))
1586 && reg_renumber[REGNO (SET_DEST (set))] < 0
1587 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1588 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1590 unsigned regno = REGNO (SET_DEST (set));
1591 rtx_insn_list *init = reg_equiv_init (regno);
1594 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1596 machine_mode mode = GET_MODE (SET_DEST (set));
1597 int cost = set_src_cost (t, mode,
1598 optimize_bb_for_speed_p (bb));
1599 int freq = REG_FREQ_FROM_BB (bb);
1601 reg_equiv_init_cost[regno] = cost * freq;
1605 /* If needed, eliminate any eliminable registers. */
1606 if (num_eliminable || num_eliminable_invariants)
1607 elimination_costs_in_insn (insn);
1610 update_eliminable_offsets ();
1614 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1616 if (reg_equiv_invariant (i))
1618 if (reg_equiv_init (i))
1620 int cost = reg_equiv_init_cost[i];
1623 "Reg %d has equivalence, initial gains %d\n", i, cost);
1625 ira_adjust_equiv_reg_cost (i, cost);
1631 "Reg %d had equivalence, but can't be eliminated\n",
1633 ira_adjust_equiv_reg_cost (i, 0);
1638 free (reg_equiv_init_cost);
1639 free (offsets_known_at);
1642 offsets_known_at = NULL;
1645 /* Comparison function for qsort to decide which of two reloads
1646 should be handled first. *P1 and *P2 are the reload numbers. */
1649 reload_reg_class_lower (const void *r1p, const void *r2p)
1651 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1654 /* Consider required reloads before optional ones. */
1655 t = rld[r1].optional - rld[r2].optional;
1659 /* Count all solitary classes before non-solitary ones. */
1660 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1661 - (reg_class_size[(int) rld[r1].rclass] == 1));
1665 /* Aside from solitaires, consider all multi-reg groups first. */
1666 t = rld[r2].nregs - rld[r1].nregs;
1670 /* Consider reloads in order of increasing reg-class number. */
1671 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1675 /* If reloads are equally urgent, sort by reload number,
1676 so that the results of qsort leave nothing to chance. */
1680 /* The cost of spilling each hard reg. */
1681 static int spill_cost[FIRST_PSEUDO_REGISTER];
1683 /* When spilling multiple hard registers, we use SPILL_COST for the first
1684 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1685 only the first hard reg for a multi-reg pseudo. */
1686 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1688 /* Map of hard regno to pseudo regno currently occupying the hard
1690 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1692 /* Update the spill cost arrays, considering that pseudo REG is live. */
1695 count_pseudo (int reg)
1697 int freq = REG_FREQ (reg);
1698 int r = reg_renumber[reg];
1701 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1702 if (ira_conflicts_p && r < 0)
1705 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1706 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1709 SET_REGNO_REG_SET (&pseudos_counted, reg);
1711 gcc_assert (r >= 0);
1713 spill_add_cost[r] += freq;
1714 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1717 hard_regno_to_pseudo_regno[r + nregs] = reg;
1718 spill_cost[r + nregs] += freq;
1722 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1723 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1726 order_regs_for_reload (class insn_chain *chain)
1729 HARD_REG_SET used_by_pseudos;
1730 HARD_REG_SET used_by_pseudos2;
1731 reg_set_iterator rsi;
1733 bad_spill_regs = fixed_reg_set;
1735 memset (spill_cost, 0, sizeof spill_cost);
1736 memset (spill_add_cost, 0, sizeof spill_add_cost);
1737 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1738 hard_regno_to_pseudo_regno[i] = -1;
1740 /* Count number of uses of each hard reg by pseudo regs allocated to it
1741 and then order them by decreasing use. First exclude hard registers
1742 that are live in or across this insn. */
1744 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1745 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1746 bad_spill_regs |= used_by_pseudos;
1747 bad_spill_regs |= used_by_pseudos2;
1749 /* Now find out which pseudos are allocated to it, and update
1751 CLEAR_REG_SET (&pseudos_counted);
1753 EXECUTE_IF_SET_IN_REG_SET
1754 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1758 EXECUTE_IF_SET_IN_REG_SET
1759 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1763 CLEAR_REG_SET (&pseudos_counted);
1766 /* Vector of reload-numbers showing the order in which the reloads should
1768 static short reload_order[MAX_RELOADS];
1770 /* This is used to keep track of the spill regs used in one insn. */
1771 static HARD_REG_SET used_spill_regs_local;
1773 /* We decided to spill hard register SPILLED, which has a size of
1774 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1775 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1776 update SPILL_COST/SPILL_ADD_COST. */
1779 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1781 int freq = REG_FREQ (reg);
1782 int r = reg_renumber[reg];
1785 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1786 if (ira_conflicts_p && r < 0)
1789 gcc_assert (r >= 0);
1791 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1793 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1794 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1797 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1799 spill_add_cost[r] -= freq;
1802 hard_regno_to_pseudo_regno[r + nregs] = -1;
1803 spill_cost[r + nregs] -= freq;
1807 /* Find reload register to use for reload number ORDER. */
1810 find_reg (class insn_chain *chain, int order)
1812 int rnum = reload_order[order];
1813 struct reload *rl = rld + rnum;
1814 int best_cost = INT_MAX;
1816 unsigned int i, j, n;
1818 HARD_REG_SET not_usable;
1819 HARD_REG_SET used_by_other_reload;
1820 reg_set_iterator rsi;
1821 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1822 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1824 not_usable = (bad_spill_regs
1825 | bad_spill_regs_global
1826 | ~reg_class_contents[rl->rclass]);
1828 CLEAR_HARD_REG_SET (used_by_other_reload);
1829 for (k = 0; k < order; k++)
1831 int other = reload_order[k];
1833 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1834 for (j = 0; j < rld[other].nregs; j++)
1835 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1838 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1840 #ifdef REG_ALLOC_ORDER
1841 unsigned int regno = reg_alloc_order[i];
1843 unsigned int regno = i;
1846 if (! TEST_HARD_REG_BIT (not_usable, regno)
1847 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1848 && targetm.hard_regno_mode_ok (regno, rl->mode))
1850 int this_cost = spill_cost[regno];
1852 unsigned int this_nregs = hard_regno_nregs (regno, rl->mode);
1854 for (j = 1; j < this_nregs; j++)
1856 this_cost += spill_add_cost[regno + j];
1857 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1858 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1864 if (ira_conflicts_p)
1866 /* Ask IRA to find a better pseudo-register for
1868 for (n = j = 0; j < this_nregs; j++)
1870 int r = hard_regno_to_pseudo_regno[regno + j];
1874 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1875 regno_pseudo_regs[n++] = r;
1877 regno_pseudo_regs[n++] = -1;
1879 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1880 best_regno_pseudo_regs,
1887 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1888 if (regno_pseudo_regs[j] < 0)
1895 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1897 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1899 if (this_cost < best_cost
1900 /* Among registers with equal cost, prefer caller-saved ones, or
1901 use REG_ALLOC_ORDER if it is defined. */
1902 || (this_cost == best_cost
1903 #ifdef REG_ALLOC_ORDER
1904 && (inv_reg_alloc_order[regno]
1905 < inv_reg_alloc_order[best_reg])
1907 && crtl->abi->clobbers_full_reg_p (regno)
1908 && !crtl->abi->clobbers_full_reg_p (best_reg)
1913 best_cost = this_cost;
1921 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1923 rl->nregs = hard_regno_nregs (best_reg, rl->mode);
1924 rl->regno = best_reg;
1926 EXECUTE_IF_SET_IN_REG_SET
1927 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1929 count_spilled_pseudo (best_reg, rl->nregs, j);
1932 EXECUTE_IF_SET_IN_REG_SET
1933 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1935 count_spilled_pseudo (best_reg, rl->nregs, j);
1938 for (i = 0; i < rl->nregs; i++)
1940 gcc_assert (spill_cost[best_reg + i] == 0);
1941 gcc_assert (spill_add_cost[best_reg + i] == 0);
1942 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1943 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1948 /* Find more reload regs to satisfy the remaining need of an insn, which
1950 Do it by ascending class number, since otherwise a reg
1951 might be spilled for a big class and might fail to count
1952 for a smaller class even though it belongs to that class. */
1955 find_reload_regs (class insn_chain *chain)
1959 /* In order to be certain of getting the registers we need,
1960 we must sort the reloads into order of increasing register class.
1961 Then our grabbing of reload registers will parallel the process
1962 that provided the reload registers. */
1963 for (i = 0; i < chain->n_reloads; i++)
1965 /* Show whether this reload already has a hard reg. */
1966 if (chain->rld[i].reg_rtx)
1968 chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx);
1969 chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx);
1972 chain->rld[i].regno = -1;
1973 reload_order[i] = i;
1976 n_reloads = chain->n_reloads;
1977 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1979 CLEAR_HARD_REG_SET (used_spill_regs_local);
1982 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1984 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1986 /* Compute the order of preference for hard registers to spill. */
1988 order_regs_for_reload (chain);
1990 for (i = 0; i < n_reloads; i++)
1992 int r = reload_order[i];
1994 /* Ignore reloads that got marked inoperative. */
1995 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1996 && ! rld[r].optional
1997 && rld[r].regno == -1)
1998 if (! find_reg (chain, i))
2001 fprintf (dump_file, "reload failure for reload %d\n", r);
2002 spill_failure (chain->insn, rld[r].rclass);
2008 chain->used_spill_regs = used_spill_regs_local;
2009 used_spill_regs |= used_spill_regs_local;
2011 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2015 select_reload_regs (void)
2017 class insn_chain *chain;
2019 /* Try to satisfy the needs for each insn. */
2020 for (chain = insns_need_reload; chain != 0;
2021 chain = chain->next_need_reload)
2022 find_reload_regs (chain);
2025 /* Delete all insns that were inserted by emit_caller_save_insns during
2028 delete_caller_save_insns (void)
2030 class insn_chain *c = reload_insn_chain;
2034 while (c != 0 && c->is_caller_save_insn)
2036 class insn_chain *next = c->next;
2037 rtx_insn *insn = c->insn;
2039 if (c == reload_insn_chain)
2040 reload_insn_chain = next;
2044 next->prev = c->prev;
2046 c->prev->next = next;
2047 c->next = unused_insn_chains;
2048 unused_insn_chains = c;
2056 /* Handle the failure to find a register to spill.
2057 INSN should be one of the insns which needed this particular spill reg. */
2060 spill_failure (rtx_insn *insn, enum reg_class rclass)
2062 if (asm_noperands (PATTERN (insn)) >= 0)
2063 error_for_asm (insn, "cannot find a register in class %qs while "
2064 "reloading %<asm%>",
2065 reg_class_names[rclass]);
2068 error ("unable to find a register to spill in class %qs",
2069 reg_class_names[rclass]);
2073 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2074 debug_reload_to_stream (dump_file);
2076 fatal_insn ("this is the insn:", insn);
2080 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2081 data that is dead in INSN. */
2084 delete_dead_insn (rtx_insn *insn)
2086 rtx_insn *prev = prev_active_insn (insn);
2089 /* If the previous insn sets a register that dies in our insn make
2090 a note that we want to run DCE immediately after reload.
2092 We used to delete the previous insn & recurse, but that's wrong for
2093 block local equivalences. Instead of trying to figure out the exact
2094 circumstances where we can delete the potentially dead insns, just
2095 let DCE do the job. */
2096 if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2097 && GET_CODE (PATTERN (prev)) == SET
2098 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2099 && reg_mentioned_p (prev_dest, PATTERN (insn))
2100 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2101 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2104 SET_INSN_DELETED (insn);
2107 /* Modify the home of pseudo-reg I.
2108 The new home is present in reg_renumber[I].
2110 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2111 or it may be -1, meaning there is none or it is not relevant.
2112 This is used so that all pseudos spilled from a given hard reg
2113 can share one stack slot. */
2116 alter_reg (int i, int from_reg, bool dont_share_p)
2118 /* When outputting an inline function, this can happen
2119 for a reg that isn't actually used. */
2120 if (regno_reg_rtx[i] == 0)
2123 /* If the reg got changed to a MEM at rtl-generation time,
2125 if (!REG_P (regno_reg_rtx[i]))
2128 /* Modify the reg-rtx to contain the new hard reg
2129 number or else to contain its pseudo reg number. */
2130 SET_REGNO (regno_reg_rtx[i],
2131 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2133 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2134 allocate a stack slot for it. */
2136 if (reg_renumber[i] < 0
2137 && REG_N_REFS (i) > 0
2138 && reg_equiv_constant (i) == 0
2139 && (reg_equiv_invariant (i) == 0
2140 || reg_equiv_init (i) == 0)
2141 && reg_equiv_memory_loc (i) == 0)
2144 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2145 poly_uint64 inherent_size = GET_MODE_SIZE (mode);
2146 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2147 machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
2148 poly_uint64 total_size = GET_MODE_SIZE (wider_mode);
2149 /* ??? Seems strange to derive the minimum alignment from the size,
2150 but that's the traditional behavior. For polynomial-size modes,
2151 the natural extension is to use the minimum possible size. */
2152 unsigned int min_align
2153 = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode[i]));
2154 poly_int64 adjust = 0;
2156 something_was_spilled = true;
2158 if (ira_conflicts_p)
2160 /* Mark the spill for IRA. */
2161 SET_REGNO_REG_SET (&spilled_pseudos, i);
2163 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2169 /* Each pseudo reg has an inherent size which comes from its own mode,
2170 and a total size which provides room for paradoxical subregs
2171 which refer to the pseudo reg in wider modes.
2173 We can use a slot already allocated if it provides both
2174 enough inherent space and enough total space.
2175 Otherwise, we allocate a new slot, making sure that it has no less
2176 inherent space, and no less total space, then the previous slot. */
2177 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2181 /* The sizes are taken from a subreg operation, which guarantees
2182 that they're ordered. */
2183 gcc_checking_assert (ordered_p (total_size, inherent_size));
2185 /* No known place to spill from => no slot to reuse. */
2186 x = assign_stack_local (mode, total_size,
2187 min_align > inherent_align
2188 || maybe_gt (total_size, inherent_size)
2193 /* Cancel the big-endian correction done in assign_stack_local.
2194 Get the address of the beginning of the slot. This is so we
2195 can do a big-endian correction unconditionally below. */
2196 if (BYTES_BIG_ENDIAN)
2198 adjust = inherent_size - total_size;
2199 if (maybe_ne (adjust, 0))
2201 poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2202 machine_mode mem_mode
2203 = int_mode_for_size (total_bits, 1).else_blk ();
2204 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2208 if (! dont_share_p && ira_conflicts_p)
2209 /* Inform IRA about allocation a new stack slot. */
2210 ira_mark_new_stack_slot (stack_slot, i, total_size);
2213 /* Reuse a stack slot if possible. */
2214 else if (spill_stack_slot[from_reg] != 0
2215 && known_ge (spill_stack_slot_width[from_reg], total_size)
2216 && known_ge (GET_MODE_SIZE
2217 (GET_MODE (spill_stack_slot[from_reg])),
2219 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2220 x = spill_stack_slot[from_reg];
2222 /* Allocate a bigger slot. */
2225 /* Compute maximum size needed, both for inherent size
2226 and for total size. */
2229 if (spill_stack_slot[from_reg])
2231 if (partial_subreg_p (mode,
2232 GET_MODE (spill_stack_slot[from_reg])))
2233 mode = GET_MODE (spill_stack_slot[from_reg]);
2234 total_size = ordered_max (total_size,
2235 spill_stack_slot_width[from_reg]);
2236 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2237 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2240 /* The sizes are taken from a subreg operation, which guarantees
2241 that they're ordered. */
2242 gcc_checking_assert (ordered_p (total_size, inherent_size));
2244 /* Make a slot with that size. */
2245 x = assign_stack_local (mode, total_size,
2246 min_align > inherent_align
2247 || maybe_gt (total_size, inherent_size)
2251 /* Cancel the big-endian correction done in assign_stack_local.
2252 Get the address of the beginning of the slot. This is so we
2253 can do a big-endian correction unconditionally below. */
2254 if (BYTES_BIG_ENDIAN)
2256 adjust = GET_MODE_SIZE (mode) - total_size;
2257 if (maybe_ne (adjust, 0))
2259 poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2260 machine_mode mem_mode
2261 = int_mode_for_size (total_bits, 1).else_blk ();
2262 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2266 spill_stack_slot[from_reg] = stack_slot;
2267 spill_stack_slot_width[from_reg] = total_size;
2270 /* On a big endian machine, the "address" of the slot
2271 is the address of the low part that fits its inherent mode. */
2272 adjust += subreg_size_lowpart_offset (inherent_size, total_size);
2274 /* If we have any adjustment to make, or if the stack slot is the
2275 wrong mode, make a new stack slot. */
2276 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2278 /* Set all of the memory attributes as appropriate for a spill. */
2279 set_mem_attrs_for_spill (x);
2281 /* Save the stack slot for later. */
2282 reg_equiv_memory_loc (i) = x;
2286 /* Mark the slots in regs_ever_live for the hard regs used by
2287 pseudo-reg number REGNO, accessed in MODE. */
2290 mark_home_live_1 (int regno, machine_mode mode)
2294 i = reg_renumber[regno];
2297 lim = end_hard_regno (mode, i);
2299 df_set_regs_ever_live (i++, true);
2302 /* Mark the slots in regs_ever_live for the hard regs
2303 used by pseudo-reg number REGNO. */
2306 mark_home_live (int regno)
2308 if (reg_renumber[regno] >= 0)
2309 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2312 /* This function handles the tracking of elimination offsets around branches.
2314 X is a piece of RTL being scanned.
2316 INSN is the insn that it came from, if any.
2318 INITIAL_P is nonzero if we are to set the offset to be the initial
2319 offset and zero if we are setting the offset of the label to be the
2323 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2325 enum rtx_code code = GET_CODE (x);
2328 struct elim_table *p;
2333 if (LABEL_REF_NONLOCAL_P (x))
2336 x = label_ref_label (x);
2341 /* If we know nothing about this label, set the desired offsets. Note
2342 that this sets the offset at a label to be the offset before a label
2343 if we don't know anything about the label. This is not correct for
2344 the label after a BARRIER, but is the best guess we can make. If
2345 we guessed wrong, we will suppress an elimination that might have
2346 been possible had we been able to guess correctly. */
2348 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2350 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2351 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2352 = (initial_p ? reg_eliminate[i].initial_offset
2353 : reg_eliminate[i].offset);
2354 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2357 /* Otherwise, if this is the definition of a label and it is
2358 preceded by a BARRIER, set our offsets to the known offset of
2362 && (tem = prev_nonnote_insn (insn)) != 0
2364 set_offsets_for_label (insn);
2366 /* If neither of the above cases is true, compare each offset
2367 with those previously recorded and suppress any eliminations
2368 where the offsets disagree. */
2370 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2371 if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i],
2372 (initial_p ? reg_eliminate[i].initial_offset
2373 : reg_eliminate[i].offset)))
2374 reg_eliminate[i].can_eliminate = 0;
2378 case JUMP_TABLE_DATA:
2379 set_label_offsets (PATTERN (insn), insn, initial_p);
2383 set_label_offsets (PATTERN (insn), insn, initial_p);
2389 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2390 to indirectly and hence must have all eliminations at their
2392 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2393 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2394 set_label_offsets (XEXP (tem, 0), insn, 1);
2400 /* Each of the labels in the parallel or address vector must be
2401 at their initial offsets. We want the first field for PARALLEL
2402 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2404 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2405 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2410 /* We only care about setting PC. If the source is not RETURN,
2411 IF_THEN_ELSE, or a label, disable any eliminations not at
2412 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2413 isn't one of those possibilities. For branches to a label,
2414 call ourselves recursively.
2416 Note that this can disable elimination unnecessarily when we have
2417 a non-local goto since it will look like a non-constant jump to
2418 someplace in the current function. This isn't a significant
2419 problem since such jumps will normally be when all elimination
2420 pairs are back to their initial offsets. */
2422 if (SET_DEST (x) != pc_rtx)
2425 switch (GET_CODE (SET_SRC (x)))
2432 set_label_offsets (SET_SRC (x), insn, initial_p);
2436 tem = XEXP (SET_SRC (x), 1);
2437 if (GET_CODE (tem) == LABEL_REF)
2438 set_label_offsets (label_ref_label (tem), insn, initial_p);
2439 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2442 tem = XEXP (SET_SRC (x), 2);
2443 if (GET_CODE (tem) == LABEL_REF)
2444 set_label_offsets (label_ref_label (tem), insn, initial_p);
2445 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2453 /* If we reach here, all eliminations must be at their initial
2454 offset because we are doing a jump to a variable address. */
2455 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2456 if (maybe_ne (p->offset, p->initial_offset))
2457 p->can_eliminate = 0;
2465 /* This function examines every reg that occurs in X and adjusts the
2466 costs for its elimination which are gathered by IRA. INSN is the
2467 insn in which X occurs. We do not recurse into MEM expressions. */
2470 note_reg_elim_costly (const_rtx x, rtx insn)
2472 subrtx_iterator::array_type array;
2473 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2475 const_rtx x = *iter;
2477 iter.skip_subrtxes ();
2479 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2480 && reg_equiv_init (REGNO (x))
2481 && reg_equiv_invariant (REGNO (x)))
2483 rtx t = reg_equiv_invariant (REGNO (x));
2484 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2485 int cost = set_src_cost (new_rtx, Pmode,
2486 optimize_bb_for_speed_p (elim_bb));
2487 int freq = REG_FREQ_FROM_BB (elim_bb);
2490 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2495 /* Scan X and replace any eliminable registers (such as fp) with a
2496 replacement (such as sp), plus an offset.
2498 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2499 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2500 MEM, we are allowed to replace a sum of a register and the constant zero
2501 with the register, which we cannot do outside a MEM. In addition, we need
2502 to record the fact that a register is referenced outside a MEM.
2504 If INSN is an insn, it is the insn containing X. If we replace a REG
2505 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2506 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2507 the REG is being modified.
2509 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2510 That's used when we eliminate in expressions stored in notes.
2511 This means, do not set ref_outside_mem even if the reference
2514 If FOR_COSTS is true, we are being called before reload in order to
2515 estimate the costs of keeping registers with an equivalence unallocated.
2517 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2518 replacements done assuming all offsets are at their initial values. If
2519 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2520 encounter, return the actual location so that find_reloads will do
2521 the proper thing. */
2524 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2525 bool may_use_invariant, bool for_costs)
2527 enum rtx_code code = GET_CODE (x);
2528 struct elim_table *ep;
2535 if (! current_function_decl)
2555 /* First handle the case where we encounter a bare register that
2556 is eliminable. Replace it with a PLUS. */
2557 if (regno < FIRST_PSEUDO_REGISTER)
2559 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2561 if (ep->from_rtx == x && ep->can_eliminate)
2562 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2565 else if (reg_renumber && reg_renumber[regno] < 0
2567 && reg_equiv_invariant (regno))
2569 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2570 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2571 mem_mode, insn, true, for_costs);
2572 /* There exists at least one use of REGNO that cannot be
2573 eliminated. Prevent the defining insn from being deleted. */
2574 reg_equiv_init (regno) = NULL;
2576 alter_reg (regno, -1, true);
2580 /* You might think handling MINUS in a manner similar to PLUS is a
2581 good idea. It is not. It has been tried multiple times and every
2582 time the change has had to have been reverted.
2584 Other parts of reload know a PLUS is special (gen_reload for example)
2585 and require special code to handle code a reloaded PLUS operand.
2587 Also consider backends where the flags register is clobbered by a
2588 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2589 lea instruction comes to mind). If we try to reload a MINUS, we
2590 may kill the flags register that was holding a useful value.
2592 So, please before trying to handle MINUS, consider reload as a
2593 whole instead of this little section as well as the backend issues. */
2595 /* If this is the sum of an eliminable register and a constant, rework
2597 if (REG_P (XEXP (x, 0))
2598 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2599 && CONSTANT_P (XEXP (x, 1)))
2601 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2603 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2605 /* The only time we want to replace a PLUS with a REG (this
2606 occurs when the constant operand of the PLUS is the negative
2607 of the offset) is when we are inside a MEM. We won't want
2608 to do so at other times because that would change the
2609 structure of the insn in a way that reload can't handle.
2610 We special-case the commonest situation in
2611 eliminate_regs_in_insn, so just replace a PLUS with a
2612 PLUS here, unless inside a MEM. */
2614 && CONST_INT_P (XEXP (x, 1))
2615 && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset))
2618 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2619 plus_constant (Pmode, XEXP (x, 1),
2620 ep->previous_offset));
2623 /* If the register is not eliminable, we are done since the other
2624 operand is a constant. */
2628 /* If this is part of an address, we want to bring any constant to the
2629 outermost PLUS. We will do this by doing register replacement in
2630 our operands and seeing if a constant shows up in one of them.
2632 Note that there is no risk of modifying the structure of the insn,
2633 since we only get called for its operands, thus we are either
2634 modifying the address inside a MEM, or something like an address
2635 operand of a load-address insn. */
2638 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2640 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2643 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2645 /* If one side is a PLUS and the other side is a pseudo that
2646 didn't get a hard register but has a reg_equiv_constant,
2647 we must replace the constant here since it may no longer
2648 be in the position of any operand. */
2649 if (GET_CODE (new0) == PLUS && REG_P (new1)
2650 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2651 && reg_renumber[REGNO (new1)] < 0
2653 && reg_equiv_constant (REGNO (new1)) != 0)
2654 new1 = reg_equiv_constant (REGNO (new1));
2655 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2656 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2657 && reg_renumber[REGNO (new0)] < 0
2658 && reg_equiv_constant (REGNO (new0)) != 0)
2659 new0 = reg_equiv_constant (REGNO (new0));
2661 new_rtx = form_sum (GET_MODE (x), new0, new1);
2663 /* As above, if we are not inside a MEM we do not want to
2664 turn a PLUS into something else. We might try to do so here
2665 for an addition of 0 if we aren't optimizing. */
2666 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2667 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2675 /* If this is the product of an eliminable register and a
2676 constant, apply the distribute law and move the constant out
2677 so that we have (plus (mult ..) ..). This is needed in order
2678 to keep load-address insns valid. This case is pathological.
2679 We ignore the possibility of overflow here. */
2680 if (REG_P (XEXP (x, 0))
2681 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2682 && CONST_INT_P (XEXP (x, 1)))
2683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2685 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2688 /* Refs inside notes or in DEBUG_INSNs don't count for
2690 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2691 || GET_CODE (insn) == INSN_LIST
2692 || DEBUG_INSN_P (insn))))
2693 ep->ref_outside_mem = 1;
2696 plus_constant (Pmode,
2697 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2698 ep->previous_offset * INTVAL (XEXP (x, 1)));
2705 /* See comments before PLUS about handling MINUS. */
2707 case DIV: case UDIV:
2708 case MOD: case UMOD:
2709 case AND: case IOR: case XOR:
2710 case ROTATERT: case ROTATE:
2711 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2713 case GE: case GT: case GEU: case GTU:
2714 case LE: case LT: case LEU: case LTU:
2716 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2718 rtx new1 = XEXP (x, 1)
2719 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2722 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2723 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2728 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2731 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2733 if (new_rtx != XEXP (x, 0))
2735 /* If this is a REG_DEAD note, it is not valid anymore.
2736 Using the eliminated version could result in creating a
2737 REG_DEAD note for the stack or frame pointer. */
2738 if (REG_NOTE_KIND (x) == REG_DEAD)
2740 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2744 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2752 /* Now do eliminations in the rest of the chain. If this was
2753 an EXPR_LIST, this might result in allocating more memory than is
2754 strictly needed, but it simplifies the code. */
2757 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2759 if (new_rtx != XEXP (x, 1))
2761 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2769 /* We do not support elimination of a register that is modified.
2770 elimination_effects has already make sure that this does not
2776 /* We do not support elimination of a register that is modified.
2777 elimination_effects has already make sure that this does not
2778 happen. The only remaining case we need to consider here is
2779 that the increment value may be an eliminable register. */
2780 if (GET_CODE (XEXP (x, 1)) == PLUS
2781 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2783 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2784 insn, true, for_costs);
2786 if (new_rtx != XEXP (XEXP (x, 1), 1))
2787 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2788 gen_rtx_PLUS (GET_MODE (x),
2789 XEXP (x, 0), new_rtx));
2793 case STRICT_LOW_PART:
2795 case SIGN_EXTEND: case ZERO_EXTEND:
2796 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2797 case FLOAT: case FIX:
2798 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2807 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2809 if (new_rtx != XEXP (x, 0))
2810 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2814 /* Similar to above processing, but preserve SUBREG_BYTE.
2815 Convert (subreg (mem)) to (mem) if not paradoxical.
2816 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2817 pseudo didn't get a hard reg, we must replace this with the
2818 eliminated version of the memory location because push_reload
2819 may do the replacement in certain circumstances. */
2820 if (REG_P (SUBREG_REG (x))
2821 && !paradoxical_subreg_p (x)
2823 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2825 new_rtx = SUBREG_REG (x);
2828 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2830 if (new_rtx != SUBREG_REG (x))
2832 poly_int64 x_size = GET_MODE_SIZE (GET_MODE (x));
2833 poly_int64 new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2836 && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx))
2837 /* On RISC machines, combine can create rtl of the form
2838 (set (subreg:m1 (reg:m2 R) 0) ...)
2839 where m1 < m2, and expects something interesting to
2840 happen to the entire word. Moreover, it will use the
2841 (reg:m2 R) later, expecting all bits to be preserved.
2842 So if the number of words is the same, preserve the
2843 subreg so that push_reload can see it. */
2844 && !(WORD_REGISTER_OPERATIONS
2845 && known_equal_after_align_down (x_size - 1,
2848 || known_eq (x_size, new_size))
2850 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2851 else if (insn && GET_CODE (insn) == DEBUG_INSN)
2852 return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2854 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2860 /* Our only special processing is to pass the mode of the MEM to our
2861 recursive call and copy the flags. While we are here, handle this
2862 case more efficiently. */
2864 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2867 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2868 && !memory_address_p (GET_MODE (x), new_rtx))
2869 note_reg_elim_costly (XEXP (x, 0), insn);
2871 return replace_equiv_address_nv (x, new_rtx);
2874 /* Handle insn_list USE that a call to a pure function may generate. */
2875 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2877 if (new_rtx != XEXP (x, 0))
2878 return gen_rtx_USE (GET_MODE (x), new_rtx);
2884 gcc_assert (insn && DEBUG_INSN_P (insn));
2894 /* Process each of our operands recursively. If any have changed, make a
2896 fmt = GET_RTX_FORMAT (code);
2897 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2901 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2903 if (new_rtx != XEXP (x, i) && ! copied)
2905 x = shallow_copy_rtx (x);
2908 XEXP (x, i) = new_rtx;
2910 else if (*fmt == 'E')
2913 for (j = 0; j < XVECLEN (x, i); j++)
2915 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2917 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2919 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2923 x = shallow_copy_rtx (x);
2926 XVEC (x, i) = new_v;
2929 XVECEXP (x, i, j) = new_rtx;
2938 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2940 if (reg_eliminate == NULL)
2942 gcc_assert (targetm.no_register_allocation);
2945 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2948 /* Scan rtx X for modifications of elimination target registers. Update
2949 the table of eliminables to reflect the changed state. MEM_MODE is
2950 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2953 elimination_effects (rtx x, machine_mode mem_mode)
2955 enum rtx_code code = GET_CODE (x);
2956 struct elim_table *ep;
2978 /* First handle the case where we encounter a bare register that
2979 is eliminable. Replace it with a PLUS. */
2980 if (regno < FIRST_PSEUDO_REGISTER)
2982 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2984 if (ep->from_rtx == x && ep->can_eliminate)
2987 ep->ref_outside_mem = 1;
2992 else if (reg_renumber[regno] < 0
2994 && reg_equiv_constant (regno)
2995 && ! function_invariant_p (reg_equiv_constant (regno)))
2996 elimination_effects (reg_equiv_constant (regno), mem_mode);
3005 /* If we modify the source of an elimination rule, disable it. */
3006 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3007 if (ep->from_rtx == XEXP (x, 0))
3008 ep->can_eliminate = 0;
3010 /* If we modify the target of an elimination rule by adding a constant,
3011 update its offset. If we modify the target in any other way, we'll
3012 have to disable the rule as well. */
3013 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3014 if (ep->to_rtx == XEXP (x, 0))
3016 poly_int64 size = GET_MODE_SIZE (mem_mode);
3018 /* If more bytes than MEM_MODE are pushed, account for them. */
3019 #ifdef PUSH_ROUNDING
3020 if (ep->to_rtx == stack_pointer_rtx)
3021 size = PUSH_ROUNDING (size);
3023 if (code == PRE_DEC || code == POST_DEC)
3025 else if (code == PRE_INC || code == POST_INC)
3027 else if (code == PRE_MODIFY || code == POST_MODIFY)
3029 if (GET_CODE (XEXP (x, 1)) == PLUS
3030 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3031 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3032 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3034 ep->can_eliminate = 0;
3038 /* These two aren't unary operators. */
3039 if (code == POST_MODIFY || code == PRE_MODIFY)
3042 /* Fall through to generic unary operation case. */
3044 case STRICT_LOW_PART:
3046 case SIGN_EXTEND: case ZERO_EXTEND:
3047 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3048 case FLOAT: case FIX:
3049 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3058 elimination_effects (XEXP (x, 0), mem_mode);
3062 if (REG_P (SUBREG_REG (x))
3063 && !paradoxical_subreg_p (x)
3065 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3068 elimination_effects (SUBREG_REG (x), mem_mode);
3072 /* If using a register that is the source of an eliminate we still
3073 think can be performed, note it cannot be performed since we don't
3074 know how this register is used. */
3075 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3076 if (ep->from_rtx == XEXP (x, 0))
3077 ep->can_eliminate = 0;
3079 elimination_effects (XEXP (x, 0), mem_mode);
3083 /* If clobbering a register that is the replacement register for an
3084 elimination we still think can be performed, note that it cannot
3085 be performed. Otherwise, we need not be concerned about it. */
3086 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3087 if (ep->to_rtx == XEXP (x, 0))
3088 ep->can_eliminate = 0;
3090 elimination_effects (XEXP (x, 0), mem_mode);
3094 /* CLOBBER_HIGH is only supported for LRA. */
3098 /* Check for setting a register that we know about. */
3099 if (REG_P (SET_DEST (x)))
3101 /* See if this is setting the replacement register for an
3104 If DEST is the hard frame pointer, we do nothing because we
3105 assume that all assignments to the frame pointer are for
3106 non-local gotos and are being done at a time when they are valid
3107 and do not disturb anything else. Some machines want to
3108 eliminate a fake argument pointer (or even a fake frame pointer)
3109 with either the real frame or the stack pointer. Assignments to
3110 the hard frame pointer must not prevent this elimination. */
3112 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3114 if (ep->to_rtx == SET_DEST (x)
3115 && SET_DEST (x) != hard_frame_pointer_rtx)
3117 /* If it is being incremented, adjust the offset. Otherwise,
3118 this elimination can't be done. */
3119 rtx src = SET_SRC (x);
3121 if (GET_CODE (src) == PLUS
3122 && XEXP (src, 0) == SET_DEST (x)
3123 && CONST_INT_P (XEXP (src, 1)))
3124 ep->offset -= INTVAL (XEXP (src, 1));
3126 ep->can_eliminate = 0;
3130 elimination_effects (SET_DEST (x), VOIDmode);
3131 elimination_effects (SET_SRC (x), VOIDmode);
3135 /* Our only special processing is to pass the mode of the MEM to our
3137 elimination_effects (XEXP (x, 0), GET_MODE (x));
3144 fmt = GET_RTX_FORMAT (code);
3145 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3148 elimination_effects (XEXP (x, i), mem_mode);
3149 else if (*fmt == 'E')
3150 for (j = 0; j < XVECLEN (x, i); j++)
3151 elimination_effects (XVECEXP (x, i, j), mem_mode);
3155 /* Descend through rtx X and verify that no references to eliminable registers
3156 remain. If any do remain, mark the involved register as not
3160 check_eliminable_occurrences (rtx x)
3169 code = GET_CODE (x);
3171 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3173 struct elim_table *ep;
3175 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3176 if (ep->from_rtx == x)
3177 ep->can_eliminate = 0;
3181 fmt = GET_RTX_FORMAT (code);
3182 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3185 check_eliminable_occurrences (XEXP (x, i));
3186 else if (*fmt == 'E')
3189 for (j = 0; j < XVECLEN (x, i); j++)
3190 check_eliminable_occurrences (XVECEXP (x, i, j));
3195 /* Scan INSN and eliminate all eliminable registers in it.
3197 If REPLACE is nonzero, do the replacement destructively. Also
3198 delete the insn as dead it if it is setting an eliminable register.
3200 If REPLACE is zero, do all our allocations in reload_obstack.
3202 If no eliminations were done and this insn doesn't require any elimination
3203 processing (these are not identical conditions: it might be updating sp,
3204 but not referencing fp; this needs to be seen during reload_as_needed so
3205 that the offset between fp and sp can be taken into consideration), zero
3206 is returned. Otherwise, 1 is returned. */
3209 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3211 int icode = recog_memoized (insn);
3212 rtx old_body = PATTERN (insn);
3213 int insn_is_asm = asm_noperands (old_body) >= 0;
3214 rtx old_set = single_set (insn);
3218 rtx substed_operand[MAX_RECOG_OPERANDS];
3219 rtx orig_operand[MAX_RECOG_OPERANDS];
3220 struct elim_table *ep;
3221 rtx plus_src, plus_cst_src;
3223 if (! insn_is_asm && icode < 0)
3225 gcc_assert (DEBUG_INSN_P (insn)
3226 || GET_CODE (PATTERN (insn)) == USE
3227 || GET_CODE (PATTERN (insn)) == CLOBBER
3228 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3229 if (DEBUG_BIND_INSN_P (insn))
3230 INSN_VAR_LOCATION_LOC (insn)
3231 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3235 /* We allow one special case which happens to work on all machines we
3236 currently support: a single set with the source or a REG_EQUAL
3237 note being a PLUS of an eliminable register and a constant. */
3238 plus_src = plus_cst_src = 0;
3239 if (old_set && REG_P (SET_DEST (old_set)))
3241 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3242 plus_src = SET_SRC (old_set);
3243 /* First see if the source is of the form (plus (...) CST). */
3245 && CONST_INT_P (XEXP (plus_src, 1)))
3246 plus_cst_src = plus_src;
3247 else if (REG_P (SET_SRC (old_set))
3250 /* Otherwise, see if we have a REG_EQUAL note of the form
3251 (plus (...) CST). */
3253 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3255 if ((REG_NOTE_KIND (links) == REG_EQUAL
3256 || REG_NOTE_KIND (links) == REG_EQUIV)
3257 && GET_CODE (XEXP (links, 0)) == PLUS
3258 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3260 plus_cst_src = XEXP (links, 0);
3266 /* Check that the first operand of the PLUS is a hard reg or
3267 the lowpart subreg of one. */
3270 rtx reg = XEXP (plus_cst_src, 0);
3271 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3272 reg = SUBREG_REG (reg);
3274 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3280 rtx reg = XEXP (plus_cst_src, 0);
3281 poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
3283 if (GET_CODE (reg) == SUBREG)
3284 reg = SUBREG_REG (reg);
3286 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3287 if (ep->from_rtx == reg && ep->can_eliminate)
3289 rtx to_rtx = ep->to_rtx;
3290 offset += ep->offset;
3291 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3293 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3294 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3296 /* If we have a nonzero offset, and the source is already
3297 a simple REG, the following transformation would
3298 increase the cost of the insn by replacing a simple REG
3299 with (plus (reg sp) CST). So try only when we already
3300 had a PLUS before. */
3301 if (known_eq (offset, 0) || plus_src)
3303 rtx new_src = plus_constant (GET_MODE (to_rtx),
3306 new_body = old_body;
3309 new_body = copy_insn (old_body);
3310 if (REG_NOTES (insn))
3311 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3313 PATTERN (insn) = new_body;
3314 old_set = single_set (insn);
3316 /* First see if this insn remains valid when we make the
3317 change. If not, try to replace the whole pattern with
3318 a simple set (this may help if the original insn was a
3319 PARALLEL that was only recognized as single_set due to
3320 REG_UNUSED notes). If this isn't valid either, keep
3321 the INSN_CODE the same and let reload fix it up. */
3322 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3324 rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3326 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3327 SET_SRC (old_set) = new_src;
3334 /* This can't have an effect on elimination offsets, so skip right
3340 /* Determine the effects of this insn on elimination offsets. */
3341 elimination_effects (old_body, VOIDmode);
3343 /* Eliminate all eliminable registers occurring in operands that
3344 can be handled by reload. */
3345 extract_insn (insn);
3346 for (i = 0; i < recog_data.n_operands; i++)
3348 orig_operand[i] = recog_data.operand[i];
3349 substed_operand[i] = recog_data.operand[i];
3351 /* For an asm statement, every operand is eliminable. */
3352 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3354 bool is_set_src, in_plus;
3356 /* Check for setting a register that we know about. */
3357 if (recog_data.operand_type[i] != OP_IN
3358 && REG_P (orig_operand[i]))
3360 /* If we are assigning to a register that can be eliminated, it
3361 must be as part of a PARALLEL, since the code above handles
3362 single SETs. We must indicate that we can no longer
3363 eliminate this reg. */
3364 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3366 if (ep->from_rtx == orig_operand[i])
3367 ep->can_eliminate = 0;
3370 /* Companion to the above plus substitution, we can allow
3371 invariants as the source of a plain move. */
3374 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3378 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3379 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3383 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3384 replace ? insn : NULL_RTX,
3385 is_set_src || in_plus, false);
3386 if (substed_operand[i] != orig_operand[i])
3388 /* Terminate the search in check_eliminable_occurrences at
3390 *recog_data.operand_loc[i] = 0;
3392 /* If an output operand changed from a REG to a MEM and INSN is an
3393 insn, write a CLOBBER insn. */
3394 if (recog_data.operand_type[i] != OP_IN
3395 && REG_P (orig_operand[i])
3396 && MEM_P (substed_operand[i])
3398 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3402 for (i = 0; i < recog_data.n_dups; i++)
3403 *recog_data.dup_loc[i]
3404 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3406 /* If any eliminable remain, they aren't eliminable anymore. */
3407 check_eliminable_occurrences (old_body);
3409 /* Substitute the operands; the new values are in the substed_operand
3411 for (i = 0; i < recog_data.n_operands; i++)
3412 *recog_data.operand_loc[i] = substed_operand[i];
3413 for (i = 0; i < recog_data.n_dups; i++)
3414 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3416 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3417 re-recognize the insn. We do this in case we had a simple addition
3418 but now can do this as a load-address. This saves an insn in this
3420 If re-recognition fails, the old insn code number will still be used,
3421 and some register operands may have changed into PLUS expressions.
3422 These will be handled by find_reloads by loading them into a register
3427 /* If we aren't replacing things permanently and we changed something,
3428 make another copy to ensure that all the RTL is new. Otherwise
3429 things can go wrong if find_reload swaps commutative operands
3430 and one is inside RTL that has been copied while the other is not. */
3431 new_body = old_body;
3434 new_body = copy_insn (old_body);
3435 if (REG_NOTES (insn))
3436 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3438 PATTERN (insn) = new_body;
3440 /* If we had a move insn but now we don't, rerecognize it. This will
3441 cause spurious re-recognition if the old move had a PARALLEL since
3442 the new one still will, but we can't call single_set without
3443 having put NEW_BODY into the insn and the re-recognition won't
3444 hurt in this rare case. */
3445 /* ??? Why this huge if statement - why don't we just rerecognize the
3449 && ((REG_P (SET_SRC (old_set))
3450 && (GET_CODE (new_body) != SET
3451 || !REG_P (SET_SRC (new_body))))
3452 /* If this was a load from or store to memory, compare
3453 the MEM in recog_data.operand to the one in the insn.
3454 If they are not equal, then rerecognize the insn. */
3456 && ((MEM_P (SET_SRC (old_set))
3457 && SET_SRC (old_set) != recog_data.operand[1])
3458 || (MEM_P (SET_DEST (old_set))
3459 && SET_DEST (old_set) != recog_data.operand[0])))
3460 /* If this was an add insn before, rerecognize. */
3461 || GET_CODE (SET_SRC (old_set)) == PLUS))
3463 int new_icode = recog (PATTERN (insn), insn, 0);
3465 INSN_CODE (insn) = new_icode;
3469 /* Restore the old body. If there were any changes to it, we made a copy
3470 of it while the changes were still in place, so we'll correctly return
3471 a modified insn below. */
3474 /* Restore the old body. */
3475 for (i = 0; i < recog_data.n_operands; i++)
3476 /* Restoring a top-level match_parallel would clobber the new_body
3477 we installed in the insn. */
3478 if (recog_data.operand_loc[i] != &PATTERN (insn))
3479 *recog_data.operand_loc[i] = orig_operand[i];
3480 for (i = 0; i < recog_data.n_dups; i++)
3481 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3484 /* Update all elimination pairs to reflect the status after the current
3485 insn. The changes we make were determined by the earlier call to
3486 elimination_effects.
3488 We also detect cases where register elimination cannot be done,
3489 namely, if a register would be both changed and referenced outside a MEM
3490 in the resulting insn since such an insn is often undefined and, even if
3491 not, we cannot know what meaning will be given to it. Note that it is
3492 valid to have a register used in an address in an insn that changes it
3493 (presumably with a pre- or post-increment or decrement).
3495 If anything changes, return nonzero. */
3497 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3499 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3500 ep->can_eliminate = 0;
3502 ep->ref_outside_mem = 0;
3504 if (maybe_ne (ep->previous_offset, ep->offset))
3509 /* If we changed something, perform elimination in REG_NOTES. This is
3510 needed even when REPLACE is zero because a REG_DEAD note might refer
3511 to a register that we eliminate and could cause a different number
3512 of spill registers to be needed in the final reload pass than in
3514 if (val && REG_NOTES (insn) != 0)
3516 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3522 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3523 register allocator. INSN is the instruction we need to examine, we perform
3524 eliminations in its operands and record cases where eliminating a reg with
3525 an invariant equivalence would add extra cost. */
3527 #pragma GCC diagnostic push
3528 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3530 elimination_costs_in_insn (rtx_insn *insn)
3532 int icode = recog_memoized (insn);
3533 rtx old_body = PATTERN (insn);
3534 int insn_is_asm = asm_noperands (old_body) >= 0;
3535 rtx old_set = single_set (insn);
3537 rtx orig_operand[MAX_RECOG_OPERANDS];
3538 rtx orig_dup[MAX_RECOG_OPERANDS];
3539 struct elim_table *ep;
3540 rtx plus_src, plus_cst_src;
3543 if (! insn_is_asm && icode < 0)
3545 gcc_assert (DEBUG_INSN_P (insn)
3546 || GET_CODE (PATTERN (insn)) == USE
3547 || GET_CODE (PATTERN (insn)) == CLOBBER
3548 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3552 if (old_set != 0 && REG_P (SET_DEST (old_set))
3553 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3555 /* Check for setting an eliminable register. */
3556 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3557 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3561 /* We allow one special case which happens to work on all machines we
3562 currently support: a single set with the source or a REG_EQUAL
3563 note being a PLUS of an eliminable register and a constant. */
3564 plus_src = plus_cst_src = 0;
3566 if (old_set && REG_P (SET_DEST (old_set)))
3569 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3570 plus_src = SET_SRC (old_set);
3571 /* First see if the source is of the form (plus (...) CST). */
3573 && CONST_INT_P (XEXP (plus_src, 1)))
3574 plus_cst_src = plus_src;
3575 else if (REG_P (SET_SRC (old_set))
3578 /* Otherwise, see if we have a REG_EQUAL note of the form
3579 (plus (...) CST). */
3581 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3583 if ((REG_NOTE_KIND (links) == REG_EQUAL
3584 || REG_NOTE_KIND (links) == REG_EQUIV)
3585 && GET_CODE (XEXP (links, 0)) == PLUS
3586 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3588 plus_cst_src = XEXP (links, 0);
3595 /* Determine the effects of this insn on elimination offsets. */
3596 elimination_effects (old_body, VOIDmode);
3598 /* Eliminate all eliminable registers occurring in operands that
3599 can be handled by reload. */
3600 extract_insn (insn);
3601 int n_dups = recog_data.n_dups;
3602 for (i = 0; i < n_dups; i++)
3603 orig_dup[i] = *recog_data.dup_loc[i];
3605 int n_operands = recog_data.n_operands;
3606 for (i = 0; i < n_operands; i++)
3608 orig_operand[i] = recog_data.operand[i];
3610 /* For an asm statement, every operand is eliminable. */
3611 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3613 bool is_set_src, in_plus;
3615 /* Check for setting a register that we know about. */
3616 if (recog_data.operand_type[i] != OP_IN
3617 && REG_P (orig_operand[i]))
3619 /* If we are assigning to a register that can be eliminated, it
3620 must be as part of a PARALLEL, since the code above handles
3621 single SETs. We must indicate that we can no longer
3622 eliminate this reg. */
3623 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3625 if (ep->from_rtx == orig_operand[i])
3626 ep->can_eliminate = 0;
3629 /* Companion to the above plus substitution, we can allow
3630 invariants as the source of a plain move. */
3632 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3634 if (is_set_src && !sets_reg_p)
3635 note_reg_elim_costly (SET_SRC (old_set), insn);
3637 if (plus_src && sets_reg_p
3638 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3639 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3642 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3644 is_set_src || in_plus, true);
3645 /* Terminate the search in check_eliminable_occurrences at
3647 *recog_data.operand_loc[i] = 0;
3651 for (i = 0; i < n_dups; i++)
3652 *recog_data.dup_loc[i]
3653 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3655 /* If any eliminable remain, they aren't eliminable anymore. */
3656 check_eliminable_occurrences (old_body);
3658 /* Restore the old body. */
3659 for (i = 0; i < n_operands; i++)
3660 *recog_data.operand_loc[i] = orig_operand[i];
3661 for (i = 0; i < n_dups; i++)
3662 *recog_data.dup_loc[i] = orig_dup[i];
3664 /* Update all elimination pairs to reflect the status after the current
3665 insn. The changes we make were determined by the earlier call to
3666 elimination_effects. */
3668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3670 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3671 ep->can_eliminate = 0;
3673 ep->ref_outside_mem = 0;
3678 #pragma GCC diagnostic pop
3680 /* Loop through all elimination pairs.
3681 Recalculate the number not at initial offset.
3683 Compute the maximum offset (minimum offset if the stack does not
3684 grow downward) for each elimination pair. */
3687 update_eliminable_offsets (void)
3689 struct elim_table *ep;
3691 num_not_at_initial_offset = 0;
3692 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3694 ep->previous_offset = ep->offset;
3695 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3696 num_not_at_initial_offset++;
3700 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3701 replacement we currently believe is valid, mark it as not eliminable if X
3702 modifies DEST in any way other than by adding a constant integer to it.
3704 If DEST is the frame pointer, we do nothing because we assume that
3705 all assignments to the hard frame pointer are nonlocal gotos and are being
3706 done at a time when they are valid and do not disturb anything else.
3707 Some machines want to eliminate a fake argument pointer with either the
3708 frame or stack pointer. Assignments to the hard frame pointer must not
3709 prevent this elimination.
3711 Called via note_stores from reload before starting its passes to scan
3712 the insns of the function. */
3715 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3719 /* A SUBREG of a hard register here is just changing its mode. We should
3720 not see a SUBREG of an eliminable hard register, but check just in
3722 if (GET_CODE (dest) == SUBREG)
3723 dest = SUBREG_REG (dest);
3725 if (dest == hard_frame_pointer_rtx)
3728 /* CLOBBER_HIGH is only supported for LRA. */
3729 gcc_assert (GET_CODE (x) != CLOBBER_HIGH);
3731 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3732 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3733 && (GET_CODE (x) != SET
3734 || GET_CODE (SET_SRC (x)) != PLUS
3735 || XEXP (SET_SRC (x), 0) != dest
3736 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3738 reg_eliminate[i].can_eliminate_previous
3739 = reg_eliminate[i].can_eliminate = 0;
3744 /* Verify that the initial elimination offsets did not change since the
3745 last call to set_initial_elim_offsets. This is used to catch cases
3746 where something illegal happened during reload_as_needed that could
3747 cause incorrect code to be generated if we did not check for it. */
3750 verify_initial_elim_offsets (void)
3753 struct elim_table *ep;
3755 if (!num_eliminable)
3758 targetm.compute_frame_layout ();
3759 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3761 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3762 if (maybe_ne (t, ep->initial_offset))
3769 /* Reset all offsets on eliminable registers to their initial values. */
3772 set_initial_elim_offsets (void)
3774 struct elim_table *ep = reg_eliminate;
3776 targetm.compute_frame_layout ();
3777 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3779 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3780 ep->previous_offset = ep->offset = ep->initial_offset;
3783 num_not_at_initial_offset = 0;
3786 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3789 set_initial_eh_label_offset (rtx label)
3791 set_label_offsets (label, NULL, 1);
3794 /* Initialize the known label offsets.
3795 Set a known offset for each forced label to be at the initial offset
3796 of each elimination. We do this because we assume that all
3797 computed jumps occur from a location where each elimination is
3798 at its initial offset.
3799 For all other labels, show that we don't know the offsets. */
3802 set_initial_label_offsets (void)
3804 memset (offsets_known_at, 0, num_labels);
3808 FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn)
3809 set_label_offsets (insn, NULL, 1);
3811 for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3813 set_label_offsets (x->insn (), NULL, 1);
3815 for_each_eh_label (set_initial_eh_label_offset);
3818 /* Set all elimination offsets to the known values for the code label given
3822 set_offsets_for_label (rtx_insn *insn)
3825 int label_nr = CODE_LABEL_NUMBER (insn);
3826 struct elim_table *ep;
3828 num_not_at_initial_offset = 0;
3829 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3831 ep->offset = ep->previous_offset
3832 = offsets_at[label_nr - first_label_num][i];
3833 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3834 num_not_at_initial_offset++;
3838 /* See if anything that happened changes which eliminations are valid.
3839 For example, on the SPARC, whether or not the frame pointer can
3840 be eliminated can depend on what registers have been used. We need
3841 not check some conditions again (such as flag_omit_frame_pointer)
3842 since they can't have changed. */
3845 update_eliminables (HARD_REG_SET *pset)
3847 int previous_frame_pointer_needed = frame_pointer_needed;
3848 struct elim_table *ep;
3850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3851 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3852 && targetm.frame_pointer_required ())
3853 || ! targetm.can_eliminate (ep->from, ep->to)
3855 ep->can_eliminate = 0;
3857 /* Look for the case where we have discovered that we can't replace
3858 register A with register B and that means that we will now be
3859 trying to replace register A with register C. This means we can
3860 no longer replace register C with register B and we need to disable
3861 such an elimination, if it exists. This occurs often with A == ap,
3862 B == sp, and C == fp. */
3864 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3866 struct elim_table *op;
3869 if (! ep->can_eliminate && ep->can_eliminate_previous)
3871 /* Find the current elimination for ep->from, if there is a
3873 for (op = reg_eliminate;
3874 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3875 if (op->from == ep->from && op->can_eliminate)
3881 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3883 for (op = reg_eliminate;
3884 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3885 if (op->from == new_to && op->to == ep->to)
3886 op->can_eliminate = 0;
3890 /* See if any registers that we thought we could eliminate the previous
3891 time are no longer eliminable. If so, something has changed and we
3892 must spill the register. Also, recompute the number of eliminable
3893 registers and see if the frame pointer is needed; it is if there is
3894 no elimination of the frame pointer that we can perform. */
3896 frame_pointer_needed = 1;
3897 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3899 if (ep->can_eliminate
3900 && ep->from == FRAME_POINTER_REGNUM
3901 && ep->to != HARD_FRAME_POINTER_REGNUM
3902 && (! SUPPORTS_STACK_ALIGNMENT
3903 || ! crtl->stack_realign_needed))
3904 frame_pointer_needed = 0;
3906 if (! ep->can_eliminate && ep->can_eliminate_previous)
3908 ep->can_eliminate_previous = 0;
3909 SET_HARD_REG_BIT (*pset, ep->from);
3914 /* If we didn't need a frame pointer last time, but we do now, spill
3915 the hard frame pointer. */
3916 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3917 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3920 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3921 Return true iff a register was spilled. */
3924 update_eliminables_and_spill (void)
3927 bool did_spill = false;
3928 HARD_REG_SET to_spill;
3929 CLEAR_HARD_REG_SET (to_spill);
3930 update_eliminables (&to_spill);
3931 used_spill_regs &= ~to_spill;
3933 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3934 if (TEST_HARD_REG_BIT (to_spill, i))
3936 spill_hard_reg (i, 1);
3939 /* Regardless of the state of spills, if we previously had
3940 a register that we thought we could eliminate, but now
3941 cannot eliminate, we must run another pass.
3943 Consider pseudos which have an entry in reg_equiv_* which
3944 reference an eliminable register. We must make another pass
3945 to update reg_equiv_* so that we do not substitute in the
3946 old value from when we thought the elimination could be
3952 /* Return true if X is used as the target register of an elimination. */
3955 elimination_target_reg_p (rtx x)
3957 struct elim_table *ep;
3959 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3960 if (ep->to_rtx == x && ep->can_eliminate)
3966 /* Initialize the table of registers to eliminate.
3967 Pre-condition: global flag frame_pointer_needed has been set before
3968 calling this function. */
3971 init_elim_table (void)
3973 struct elim_table *ep;
3974 const struct elim_table_1 *ep1;
3977 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3981 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3982 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3984 ep->from = ep1->from;
3986 ep->can_eliminate = ep->can_eliminate_previous
3987 = (targetm.can_eliminate (ep->from, ep->to)
3988 && ! (ep->to == STACK_POINTER_REGNUM
3989 && frame_pointer_needed
3990 && (! SUPPORTS_STACK_ALIGNMENT
3991 || ! stack_realign_fp)));
3994 /* Count the number of eliminable registers and build the FROM and TO
3995 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3996 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3997 We depend on this. */
3998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4000 num_eliminable += ep->can_eliminate;
4001 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4002 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4006 /* Find all the pseudo registers that didn't get hard regs
4007 but do have known equivalent constants or memory slots.
4008 These include parameters (known equivalent to parameter slots)
4009 and cse'd or loop-moved constant memory addresses.
4011 Record constant equivalents in reg_equiv_constant
4012 so they will be substituted by find_reloads.
4013 Record memory equivalents in reg_mem_equiv so they can
4014 be substituted eventually by altering the REG-rtx's. */
4017 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4024 reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno);
4026 reg_max_ref_mode = NULL;
4028 num_eliminable_invariants = 0;
4030 first_label_num = get_first_label_num ();
4031 num_labels = max_label_num () - first_label_num;
4033 /* Allocate the tables used to store offset information at labels. */
4034 offsets_known_at = XNEWVEC (char, num_labels);
4035 offsets_at = (poly_int64_pod (*)[NUM_ELIMINABLE_REGS])
4036 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (poly_int64));
4038 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4039 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4040 find largest such for each pseudo. FIRST is the head of the insn
4043 for (insn = first; insn; insn = NEXT_INSN (insn))
4045 rtx set = single_set (insn);
4047 /* We may introduce USEs that we want to remove at the end, so
4048 we'll mark them with QImode. Make sure there are no
4049 previously-marked insns left by say regmove. */
4050 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4051 && GET_MODE (insn) != VOIDmode)
4052 PUT_MODE (insn, VOIDmode);
4054 if (do_subregs && NONDEBUG_INSN_P (insn))
4055 scan_paradoxical_subregs (PATTERN (insn));
4057 if (set != 0 && REG_P (SET_DEST (set)))
4059 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4065 i = REGNO (SET_DEST (set));
4068 if (i <= LAST_VIRTUAL_REGISTER)
4071 /* If flag_pic and we have constant, verify it's legitimate. */
4073 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4075 /* It can happen that a REG_EQUIV note contains a MEM
4076 that is not a legitimate memory operand. As later
4077 stages of reload assume that all addresses found
4078 in the reg_equiv_* arrays were originally legitimate,
4079 we ignore such REG_EQUIV notes. */
4080 if (memory_operand (x, VOIDmode))
4082 /* Always unshare the equivalence, so we can
4083 substitute into this insn without touching the
4085 reg_equiv_memory_loc (i) = copy_rtx (x);
4087 else if (function_invariant_p (x))
4091 mode = GET_MODE (SET_DEST (set));
4092 if (GET_CODE (x) == PLUS)
4094 /* This is PLUS of frame pointer and a constant,
4095 and might be shared. Unshare it. */
4096 reg_equiv_invariant (i) = copy_rtx (x);
4097 num_eliminable_invariants++;
4099 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4101 reg_equiv_invariant (i) = x;
4102 num_eliminable_invariants++;
4104 else if (targetm.legitimate_constant_p (mode, x))
4105 reg_equiv_constant (i) = x;
4108 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4109 if (! reg_equiv_memory_loc (i))
4110 reg_equiv_init (i) = NULL;
4115 reg_equiv_init (i) = NULL;
4120 reg_equiv_init (i) = NULL;
4125 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4126 if (reg_equiv_init (i))
4128 fprintf (dump_file, "init_insns for %u: ", i);
4129 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4130 fprintf (dump_file, "\n");
4134 /* Indicate that we no longer have known memory locations or constants.
4135 Free all data involved in tracking these. */
4138 free_reg_equiv (void)
4142 free (offsets_known_at);
4145 offsets_known_at = 0;
4147 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4148 if (reg_equiv_alt_mem_list (i))
4149 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4150 vec_free (reg_equivs);
4153 /* Kick all pseudos out of hard register REGNO.
4155 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4156 because we found we can't eliminate some register. In the case, no pseudos
4157 are allowed to be in the register, even if they are only in a block that
4158 doesn't require spill registers, unlike the case when we are spilling this
4159 hard reg to produce another spill register.
4161 Return nonzero if any pseudos needed to be kicked out. */
4164 spill_hard_reg (unsigned int regno, int cant_eliminate)
4170 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4171 df_set_regs_ever_live (regno, true);
4174 /* Spill every pseudo reg that was allocated to this reg
4175 or to something that overlaps this reg. */
4177 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4178 if (reg_renumber[i] >= 0
4179 && (unsigned int) reg_renumber[i] <= regno
4180 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4181 SET_REGNO_REG_SET (&spilled_pseudos, i);
4184 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4185 insns that need reloads, this function is used to actually spill pseudo
4186 registers and try to reallocate them. It also sets up the spill_regs
4187 array for use by choose_reload_regs.
4189 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4190 that we displace from hard registers. */
4193 finish_spills (int global)
4195 class insn_chain *chain;
4196 int something_changed = 0;
4198 reg_set_iterator rsi;
4200 /* Build the spill_regs array for the function. */
4201 /* If there are some registers still to eliminate and one of the spill regs
4202 wasn't ever used before, additional stack space may have to be
4203 allocated to store this register. Thus, we may have changed the offset
4204 between the stack and frame pointers, so mark that something has changed.
4206 One might think that we need only set VAL to 1 if this is a call-used
4207 register. However, the set of registers that must be saved by the
4208 prologue is not identical to the call-used set. For example, the
4209 register used by the call insn for the return PC is a call-used register,
4210 but must be saved by the prologue. */
4213 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4214 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4216 spill_reg_order[i] = n_spills;
4217 spill_regs[n_spills++] = i;
4218 if (num_eliminable && ! df_regs_ever_live_p (i))
4219 something_changed = 1;
4220 df_set_regs_ever_live (i, true);
4223 spill_reg_order[i] = -1;
4225 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4226 if (reg_renumber[i] >= 0)
4228 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4229 /* Mark it as no longer having a hard register home. */
4230 reg_renumber[i] = -1;
4231 if (ira_conflicts_p)
4232 /* Inform IRA about the change. */
4233 ira_mark_allocation_change (i);
4234 /* We will need to scan everything again. */
4235 something_changed = 1;
4238 /* Retry global register allocation if possible. */
4239 if (global && ira_conflicts_p)
4243 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4244 /* For every insn that needs reloads, set the registers used as spill
4245 regs in pseudo_forbidden_regs for every pseudo live across the
4247 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4249 EXECUTE_IF_SET_IN_REG_SET
4250 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4252 pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4254 EXECUTE_IF_SET_IN_REG_SET
4255 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4257 pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4261 /* Retry allocating the pseudos spilled in IRA and the
4262 reload. For each reg, merge the various reg sets that
4263 indicate which hard regs can't be used, and call
4264 ira_reassign_pseudos. */
4265 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4266 if (reg_old_renumber[i] != reg_renumber[i])
4268 if (reg_renumber[i] < 0)
4269 temp_pseudo_reg_arr[n++] = i;
4271 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4273 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4274 bad_spill_regs_global,
4275 pseudo_forbidden_regs, pseudo_previous_regs,
4277 something_changed = 1;
4279 /* Fix up the register information in the insn chain.
4280 This involves deleting those of the spilled pseudos which did not get
4281 a new hard register home from the live_{before,after} sets. */
4282 for (chain = reload_insn_chain; chain; chain = chain->next)
4284 HARD_REG_SET used_by_pseudos;
4285 HARD_REG_SET used_by_pseudos2;
4287 if (! ira_conflicts_p)
4289 /* Don't do it for IRA because IRA and the reload still can
4290 assign hard registers to the spilled pseudos on next
4291 reload iterations. */
4292 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4293 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4295 /* Mark any unallocated hard regs as available for spills. That
4296 makes inheritance work somewhat better. */
4297 if (chain->need_reload)
4299 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4300 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4301 used_by_pseudos |= used_by_pseudos2;
4303 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4304 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4305 /* Value of chain->used_spill_regs from previous iteration
4306 may be not included in the value calculated here because
4307 of possible removing caller-saves insns (see function
4308 delete_caller_save_insns. */
4309 chain->used_spill_regs = ~used_by_pseudos & used_spill_regs;
4313 CLEAR_REG_SET (&changed_allocation_pseudos);
4314 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4315 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4317 int regno = reg_renumber[i];
4318 if (reg_old_renumber[i] == regno)
4321 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4323 alter_reg (i, reg_old_renumber[i], false);
4324 reg_old_renumber[i] = regno;
4328 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4330 fprintf (dump_file, " Register %d now in %d.\n\n",
4331 i, reg_renumber[i]);
4335 return something_changed;
4338 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4341 scan_paradoxical_subregs (rtx x)
4345 enum rtx_code code = GET_CODE (x);
4362 if (REG_P (SUBREG_REG (x)))
4364 unsigned int regno = REGNO (SUBREG_REG (x));
4365 if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)))
4367 reg_max_ref_mode[regno] = GET_MODE (x);
4368 mark_home_live_1 (regno, GET_MODE (x));
4377 fmt = GET_RTX_FORMAT (code);
4378 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4381 scan_paradoxical_subregs (XEXP (x, i));
4382 else if (fmt[i] == 'E')
4385 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4386 scan_paradoxical_subregs (XVECEXP (x, i, j));
4391 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4392 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4393 and apply the corresponding narrowing subreg to *OTHER_PTR.
4394 Return true if the operands were changed, false otherwise. */
4397 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4399 rtx op, inner, other, tem;
4402 if (!paradoxical_subreg_p (op))
4404 inner = SUBREG_REG (op);
4407 tem = gen_lowpart_common (GET_MODE (inner), other);
4411 /* If the lowpart operation turned a hard register into a subreg,
4412 rather than simplifying it to another hard register, then the
4413 mode change cannot be properly represented. For example, OTHER
4414 might be valid in its current mode, but not in the new one. */
4415 if (GET_CODE (tem) == SUBREG
4417 && HARD_REGISTER_P (other))
4425 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4426 examine all of the reload insns between PREV and NEXT exclusive, and
4427 annotate all that may trap. */
4430 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4432 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4435 if (!insn_could_throw_p (insn))
4436 remove_note (insn, note);
4437 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4440 /* Reload pseudo-registers into hard regs around each insn as needed.
4441 Additional register load insns are output before the insn that needs it
4442 and perhaps store insns after insns that modify the reloaded pseudo reg.
4444 reg_last_reload_reg and reg_reloaded_contents keep track of
4445 which registers are already available in reload registers.
4446 We update these for the reloads that we perform,
4447 as the insns are scanned. */
4450 reload_as_needed (int live_known)
4452 class insn_chain *chain;
4458 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4459 memset (spill_reg_store, 0, sizeof spill_reg_store);
4460 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4461 INIT_REG_SET (®_has_output_reload);
4462 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4464 set_initial_elim_offsets ();
4466 /* Generate a marker insn that we will move around. */
4467 marker = emit_note (NOTE_INSN_DELETED);
4468 unlink_insn_chain (marker, marker);
4470 for (chain = reload_insn_chain; chain; chain = chain->next)
4473 rtx_insn *insn = chain->insn;
4474 rtx_insn *old_next = NEXT_INSN (insn);
4476 rtx_insn *old_prev = PREV_INSN (insn);
4479 if (will_delete_init_insn_p (insn))
4482 /* If we pass a label, copy the offsets from the label information
4483 into the current offsets of each elimination. */
4485 set_offsets_for_label (insn);
4487 else if (INSN_P (insn))
4489 regset_head regs_to_forget;
4490 INIT_REG_SET (®s_to_forget);
4491 note_stores (insn, forget_old_reloads_1, ®s_to_forget);
4493 /* If this is a USE and CLOBBER of a MEM, ensure that any
4494 references to eliminable registers have been removed. */
4496 if ((GET_CODE (PATTERN (insn)) == USE
4497 || GET_CODE (PATTERN (insn)) == CLOBBER)
4498 && MEM_P (XEXP (PATTERN (insn), 0)))
4499 XEXP (XEXP (PATTERN (insn), 0), 0)
4500 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4501 GET_MODE (XEXP (PATTERN (insn), 0)),
4504 /* If we need to do register elimination processing, do so.
4505 This might delete the insn, in which case we are done. */
4506 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4508 eliminate_regs_in_insn (insn, 1);
4511 update_eliminable_offsets ();
4512 CLEAR_REG_SET (®s_to_forget);
4517 /* If need_elim is nonzero but need_reload is zero, one might think
4518 that we could simply set n_reloads to 0. However, find_reloads
4519 could have done some manipulation of the insn (such as swapping
4520 commutative operands), and these manipulations are lost during
4521 the first pass for every insn that needs register elimination.
4522 So the actions of find_reloads must be redone here. */
4524 if (! chain->need_elim && ! chain->need_reload
4525 && ! chain->need_operand_change)
4527 /* First find the pseudo regs that must be reloaded for this insn.
4528 This info is returned in the tables reload_... (see reload.h).
4529 Also modify the body of INSN by substituting RELOAD
4530 rtx's for those pseudo regs. */
4533 CLEAR_REG_SET (®_has_output_reload);
4534 CLEAR_HARD_REG_SET (reg_is_output_reload);
4536 find_reloads (insn, 1, spill_indirect_levels, live_known,
4542 rtx_insn *next = NEXT_INSN (insn);
4544 /* ??? PREV can get deleted by reload inheritance.
4545 Work around this by emitting a marker note. */
4546 prev = PREV_INSN (insn);
4547 reorder_insns_nobb (marker, marker, prev);
4549 /* Now compute which reload regs to reload them into. Perhaps
4550 reusing reload regs from previous insns, or else output
4551 load insns to reload them. Maybe output store insns too.
4552 Record the choices of reload reg in reload_reg_rtx. */
4553 choose_reload_regs (chain);
4555 /* Generate the insns to reload operands into or out of
4556 their reload regs. */
4557 emit_reload_insns (chain);
4559 /* Substitute the chosen reload regs from reload_reg_rtx
4560 into the insn's body (or perhaps into the bodies of other
4561 load and store insn that we just made for reloading
4562 and that we moved the structure into). */
4563 subst_reloads (insn);
4565 prev = PREV_INSN (marker);
4566 unlink_insn_chain (marker, marker);
4568 /* Adjust the exception region notes for loads and stores. */
4569 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4570 fixup_eh_region_note (insn, prev, next);
4572 /* Adjust the location of REG_ARGS_SIZE. */
4573 rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4576 remove_note (insn, p);
4577 fixup_args_size_notes (prev, PREV_INSN (next),
4581 /* If this was an ASM, make sure that all the reload insns
4582 we have generated are valid. If not, give an error
4584 if (asm_noperands (PATTERN (insn)) >= 0)
4585 for (rtx_insn *p = NEXT_INSN (prev);
4588 if (p != insn && INSN_P (p)
4589 && GET_CODE (PATTERN (p)) != USE
4590 && (recog_memoized (p) < 0
4591 || (extract_insn (p),
4592 !(constrain_operands (1,
4593 get_enabled_alternatives (p))))))
4595 error_for_asm (insn,
4596 "%<asm%> operand requires "
4597 "impossible reload");
4602 if (num_eliminable && chain->need_elim)
4603 update_eliminable_offsets ();
4605 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4606 is no longer validly lying around to save a future reload.
4607 Note that this does not detect pseudos that were reloaded
4608 for this insn in order to be stored in
4609 (obeying register constraints). That is correct; such reload
4610 registers ARE still valid. */
4611 forget_marked_reloads (®s_to_forget);
4612 CLEAR_REG_SET (®s_to_forget);
4614 /* There may have been CLOBBER insns placed after INSN. So scan
4615 between INSN and NEXT and use them to forget old reloads. */
4616 for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4617 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4618 note_stores (x, forget_old_reloads_1, NULL);
4621 /* Likewise for regs altered by auto-increment in this insn.
4622 REG_INC notes have been changed by reloading:
4623 find_reloads_address_1 records substitutions for them,
4624 which have been performed by subst_reloads above. */
4625 for (i = n_reloads - 1; i >= 0; i--)
4627 rtx in_reg = rld[i].in_reg;
4630 enum rtx_code code = GET_CODE (in_reg);
4631 /* PRE_INC / PRE_DEC will have the reload register ending up
4632 with the same value as the stack slot, but that doesn't
4633 hold true for POST_INC / POST_DEC. Either we have to
4634 convert the memory access to a true POST_INC / POST_DEC,
4635 or we can't use the reload register for inheritance. */
4636 if ((code == POST_INC || code == POST_DEC)
4637 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4638 REGNO (rld[i].reg_rtx))
4639 /* Make sure it is the inc/dec pseudo, and not
4640 some other (e.g. output operand) pseudo. */
4641 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4642 == REGNO (XEXP (in_reg, 0))))
4645 rtx reload_reg = rld[i].reg_rtx;
4646 machine_mode mode = GET_MODE (reload_reg);
4650 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4652 /* We really want to ignore REG_INC notes here, so
4653 use PATTERN (p) as argument to reg_set_p . */
4654 if (reg_set_p (reload_reg, PATTERN (p)))
4656 n = count_occurrences (PATTERN (p), reload_reg, 0);
4662 = gen_rtx_fmt_e (code, mode, reload_reg);
4664 validate_replace_rtx_group (reload_reg,
4666 n = verify_changes (0);
4668 /* We must also verify that the constraints
4669 are met after the replacement. Make sure
4670 extract_insn is only called for an insn
4671 where the replacements were found to be
4676 n = constrain_operands (1,
4677 get_enabled_alternatives (p));
4680 /* If the constraints were not met, then
4681 undo the replacement, else confirm it. */
4685 confirm_change_group ();
4691 add_reg_note (p, REG_INC, reload_reg);
4692 /* Mark this as having an output reload so that the
4693 REG_INC processing code below won't invalidate
4694 the reload for inheritance. */
4695 SET_HARD_REG_BIT (reg_is_output_reload,
4696 REGNO (reload_reg));
4697 SET_REGNO_REG_SET (®_has_output_reload,
4698 REGNO (XEXP (in_reg, 0)));
4701 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4704 else if ((code == PRE_INC || code == PRE_DEC)
4705 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4706 REGNO (rld[i].reg_rtx))
4707 /* Make sure it is the inc/dec pseudo, and not
4708 some other (e.g. output operand) pseudo. */
4709 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4710 == REGNO (XEXP (in_reg, 0))))
4712 SET_HARD_REG_BIT (reg_is_output_reload,
4713 REGNO (rld[i].reg_rtx));
4714 SET_REGNO_REG_SET (®_has_output_reload,
4715 REGNO (XEXP (in_reg, 0)));
4717 else if (code == PRE_INC || code == PRE_DEC
4718 || code == POST_INC || code == POST_DEC)
4720 int in_regno = REGNO (XEXP (in_reg, 0));
4722 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4725 bool forget_p = true;
4727 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4728 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4731 for (rtx_insn *x = (old_prev ?
4732 NEXT_INSN (old_prev) : insn);
4735 if (x == reg_reloaded_insn[in_hard_regno])
4741 /* If for some reasons, we didn't set up
4742 reg_last_reload_reg in this insn,
4743 invalidate inheritance from previous
4744 insns for the incremented/decremented
4745 register. Such registers will be not in
4746 reg_has_output_reload. Invalidate it
4747 also if the corresponding element in
4748 reg_reloaded_insn is also
4751 forget_old_reloads_1 (XEXP (in_reg, 0),
4757 /* If a pseudo that got a hard register is auto-incremented,
4758 we must purge records of copying it into pseudos without
4760 for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4761 if (REG_NOTE_KIND (x) == REG_INC)
4763 /* See if this pseudo reg was reloaded in this insn.
4764 If so, its last-reload info is still valid
4765 because it is based on this insn's reload. */
4766 for (i = 0; i < n_reloads; i++)
4767 if (rld[i].out == XEXP (x, 0))
4771 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4775 /* A reload reg's contents are unknown after a label. */
4777 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4779 /* Don't assume a reload reg is still good after a call insn
4780 if it is a call-used reg, or if it contains a value that will
4781 be partially clobbered by the call. */
4782 else if (CALL_P (insn))
4785 &= ~insn_callee_abi (insn).full_and_partial_reg_clobbers ();
4787 /* If this is a call to a setjmp-type function, we must not
4788 reuse any reload reg contents across the call; that will
4789 just be clobbered by other uses of the register in later
4790 code, before the longjmp. */
4791 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4792 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4797 free (reg_last_reload_reg);
4798 CLEAR_REG_SET (®_has_output_reload);
4801 /* Discard all record of any value reloaded from X,
4802 or reloaded in X from someplace else;
4803 unless X is an output reload reg of the current insn.
4805 X may be a hard reg (the reload reg)
4806 or it may be a pseudo reg that was reloaded from.
4808 When DATA is non-NULL just mark the registers in regset
4809 to be forgotten later. */
4812 forget_old_reloads_1 (rtx x, const_rtx setter,
4817 regset regs = (regset) data;
4819 /* note_stores does give us subregs of hard regs,
4820 subreg_regno_offset requires a hard reg. */
4821 while (GET_CODE (x) == SUBREG)
4823 /* We ignore the subreg offset when calculating the regno,
4824 because we are using the entire underlying hard register
4832 /* CLOBBER_HIGH is only supported for LRA. */
4833 gcc_assert (setter == NULL_RTX || GET_CODE (setter) != CLOBBER_HIGH);
4837 if (regno >= FIRST_PSEUDO_REGISTER)
4844 /* Storing into a spilled-reg invalidates its contents.
4845 This can happen if a block-local pseudo is allocated to that reg
4846 and it wasn't spilled because this block's total need is 0.
4847 Then some insn might have an optional reload and use this reg. */
4849 for (i = 0; i < nr; i++)
4850 /* But don't do this if the reg actually serves as an output
4851 reload reg in the current instruction. */
4853 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4855 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4856 spill_reg_store[regno + i] = 0;
4862 SET_REGNO_REG_SET (regs, regno + nr);
4865 /* Since value of X has changed,
4866 forget any value previously copied from it. */
4869 /* But don't forget a copy if this is the output reload
4870 that establishes the copy's validity. */
4872 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4873 reg_last_reload_reg[regno + nr] = 0;
4877 /* Forget the reloads marked in regset by previous function. */
4879 forget_marked_reloads (regset regs)
4882 reg_set_iterator rsi;
4883 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4885 if (reg < FIRST_PSEUDO_REGISTER
4886 /* But don't do this if the reg actually serves as an output
4887 reload reg in the current instruction. */
4889 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4891 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4892 spill_reg_store[reg] = 0;
4895 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4896 reg_last_reload_reg[reg] = 0;
4900 /* The following HARD_REG_SETs indicate when each hard register is
4901 used for a reload of various parts of the current insn. */
4903 /* If reg is unavailable for all reloads. */
4904 static HARD_REG_SET reload_reg_unavailable;
4905 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4906 static HARD_REG_SET reload_reg_used;
4907 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4908 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4909 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4910 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4911 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4912 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4913 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4914 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4915 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4916 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4917 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4918 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4919 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4920 static HARD_REG_SET reload_reg_used_in_op_addr;
4921 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4922 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4923 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4924 static HARD_REG_SET reload_reg_used_in_insn;
4925 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4926 static HARD_REG_SET reload_reg_used_in_other_addr;
4928 /* If reg is in use as a reload reg for any sort of reload. */
4929 static HARD_REG_SET reload_reg_used_at_all;
4931 /* If reg is use as an inherited reload. We just mark the first register
4933 static HARD_REG_SET reload_reg_used_for_inherit;
4935 /* Records which hard regs are used in any way, either as explicit use or
4936 by being allocated to a pseudo during any point of the current insn. */
4937 static HARD_REG_SET reg_used_in_insn;
4939 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4940 TYPE. MODE is used to indicate how many consecutive regs are
4944 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4950 add_to_hard_reg_set (&reload_reg_used, mode, regno);
4953 case RELOAD_FOR_INPUT_ADDRESS:
4954 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
4957 case RELOAD_FOR_INPADDR_ADDRESS:
4958 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
4961 case RELOAD_FOR_OUTPUT_ADDRESS:
4962 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
4965 case RELOAD_FOR_OUTADDR_ADDRESS:
4966 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
4969 case RELOAD_FOR_OPERAND_ADDRESS:
4970 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
4973 case RELOAD_FOR_OPADDR_ADDR:
4974 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
4977 case RELOAD_FOR_OTHER_ADDRESS:
4978 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
4981 case RELOAD_FOR_INPUT:
4982 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
4985 case RELOAD_FOR_OUTPUT:
4986 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
4989 case RELOAD_FOR_INSN:
4990 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
4994 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
4997 /* Similarly, but show REGNO is no longer in use for a reload. */
5000 clear_reload_reg_in_use (unsigned int regno, int opnum,
5001 enum reload_type type, machine_mode mode)
5003 unsigned int nregs = hard_regno_nregs (regno, mode);
5004 unsigned int start_regno, end_regno, r;
5006 /* A complication is that for some reload types, inheritance might
5007 allow multiple reloads of the same types to share a reload register.
5008 We set check_opnum if we have to check only reloads with the same
5009 operand number, and check_any if we have to check all reloads. */
5010 int check_opnum = 0;
5012 HARD_REG_SET *used_in_set;
5017 used_in_set = &reload_reg_used;
5020 case RELOAD_FOR_INPUT_ADDRESS:
5021 used_in_set = &reload_reg_used_in_input_addr[opnum];
5024 case RELOAD_FOR_INPADDR_ADDRESS:
5026 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5029 case RELOAD_FOR_OUTPUT_ADDRESS:
5030 used_in_set = &reload_reg_used_in_output_addr[opnum];
5033 case RELOAD_FOR_OUTADDR_ADDRESS:
5035 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5038 case RELOAD_FOR_OPERAND_ADDRESS:
5039 used_in_set = &reload_reg_used_in_op_addr;
5042 case RELOAD_FOR_OPADDR_ADDR:
5044 used_in_set = &reload_reg_used_in_op_addr_reload;
5047 case RELOAD_FOR_OTHER_ADDRESS:
5048 used_in_set = &reload_reg_used_in_other_addr;
5052 case RELOAD_FOR_INPUT:
5053 used_in_set = &reload_reg_used_in_input[opnum];
5056 case RELOAD_FOR_OUTPUT:
5057 used_in_set = &reload_reg_used_in_output[opnum];
5060 case RELOAD_FOR_INSN:
5061 used_in_set = &reload_reg_used_in_insn;
5066 /* We resolve conflicts with remaining reloads of the same type by
5067 excluding the intervals of reload registers by them from the
5068 interval of freed reload registers. Since we only keep track of
5069 one set of interval bounds, we might have to exclude somewhat
5070 more than what would be necessary if we used a HARD_REG_SET here.
5071 But this should only happen very infrequently, so there should
5072 be no reason to worry about it. */
5074 start_regno = regno;
5075 end_regno = regno + nregs;
5076 if (check_opnum || check_any)
5078 for (i = n_reloads - 1; i >= 0; i--)
5080 if (rld[i].when_needed == type
5081 && (check_any || rld[i].opnum == opnum)
5084 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5085 unsigned int conflict_end
5086 = end_hard_regno (rld[i].mode, conflict_start);
5088 /* If there is an overlap with the first to-be-freed register,
5089 adjust the interval start. */
5090 if (conflict_start <= start_regno && conflict_end > start_regno)
5091 start_regno = conflict_end;
5092 /* Otherwise, if there is a conflict with one of the other
5093 to-be-freed registers, adjust the interval end. */
5094 if (conflict_start > start_regno && conflict_start < end_regno)
5095 end_regno = conflict_start;
5100 for (r = start_regno; r < end_regno; r++)
5101 CLEAR_HARD_REG_BIT (*used_in_set, r);
5104 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5105 specified by OPNUM and TYPE. */
5108 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5112 /* In use for a RELOAD_OTHER means it's not available for anything. */
5113 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5114 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5120 /* In use for anything means we can't use it for RELOAD_OTHER. */
5121 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5122 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5123 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5124 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5127 for (i = 0; i < reload_n_operands; i++)
5128 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5129 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5130 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5131 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5132 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5133 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5138 case RELOAD_FOR_INPUT:
5139 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5140 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5143 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5146 /* If it is used for some other input, can't use it. */
5147 for (i = 0; i < reload_n_operands; i++)
5148 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5151 /* If it is used in a later operand's address, can't use it. */
5152 for (i = opnum + 1; i < reload_n_operands; i++)
5153 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5154 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5159 case RELOAD_FOR_INPUT_ADDRESS:
5160 /* Can't use a register if it is used for an input address for this
5161 operand or used as an input in an earlier one. */
5162 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5163 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5166 for (i = 0; i < opnum; i++)
5167 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5172 case RELOAD_FOR_INPADDR_ADDRESS:
5173 /* Can't use a register if it is used for an input address
5174 for this operand or used as an input in an earlier
5176 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5179 for (i = 0; i < opnum; i++)
5180 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5185 case RELOAD_FOR_OUTPUT_ADDRESS:
5186 /* Can't use a register if it is used for an output address for this
5187 operand or used as an output in this or a later operand. Note
5188 that multiple output operands are emitted in reverse order, so
5189 the conflicting ones are those with lower indices. */
5190 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5193 for (i = 0; i <= opnum; i++)
5194 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5199 case RELOAD_FOR_OUTADDR_ADDRESS:
5200 /* Can't use a register if it is used for an output address
5201 for this operand or used as an output in this or a
5202 later operand. Note that multiple output operands are
5203 emitted in reverse order, so the conflicting ones are
5204 those with lower indices. */
5205 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5208 for (i = 0; i <= opnum; i++)
5209 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5214 case RELOAD_FOR_OPERAND_ADDRESS:
5215 for (i = 0; i < reload_n_operands; i++)
5216 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5219 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5220 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5222 case RELOAD_FOR_OPADDR_ADDR:
5223 for (i = 0; i < reload_n_operands; i++)
5224 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5227 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5229 case RELOAD_FOR_OUTPUT:
5230 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5231 outputs, or an operand address for this or an earlier output.
5232 Note that multiple output operands are emitted in reverse order,
5233 so the conflicting ones are those with higher indices. */
5234 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5237 for (i = 0; i < reload_n_operands; i++)
5238 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5241 for (i = opnum; i < reload_n_operands; i++)
5242 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5243 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5248 case RELOAD_FOR_INSN:
5249 for (i = 0; i < reload_n_operands; i++)
5250 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5251 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5254 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5255 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5257 case RELOAD_FOR_OTHER_ADDRESS:
5258 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5265 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5266 the number RELOADNUM, is still available in REGNO at the end of the insn.
5268 We can assume that the reload reg was already tested for availability
5269 at the time it is needed, and we should not check this again,
5270 in case the reg has already been marked in use. */
5273 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5275 int opnum = rld[reloadnum].opnum;
5276 enum reload_type type = rld[reloadnum].when_needed;
5279 /* See if there is a reload with the same type for this operand, using
5280 the same register. This case is not handled by the code below. */
5281 for (i = reloadnum + 1; i < n_reloads; i++)
5285 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5287 reg = rld[i].reg_rtx;
5288 if (reg == NULL_RTX)
5290 if (regno >= REGNO (reg) && regno < END_REGNO (reg))
5297 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5298 its value must reach the end. */
5301 /* If this use is for part of the insn,
5302 its value reaches if no subsequent part uses the same register.
5303 Just like the above function, don't try to do this with lots
5306 case RELOAD_FOR_OTHER_ADDRESS:
5307 /* Here we check for everything else, since these don't conflict
5308 with anything else and everything comes later. */
5310 for (i = 0; i < reload_n_operands; i++)
5311 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5312 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5313 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5314 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5315 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5316 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5319 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5320 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5321 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5322 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5324 case RELOAD_FOR_INPUT_ADDRESS:
5325 case RELOAD_FOR_INPADDR_ADDRESS:
5326 /* Similar, except that we check only for this and subsequent inputs
5327 and the address of only subsequent inputs and we do not need
5328 to check for RELOAD_OTHER objects since they are known not to
5331 for (i = opnum; i < reload_n_operands; i++)
5332 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5335 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5336 could be killed if the register is also used by reload with type
5337 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5338 if (type == RELOAD_FOR_INPADDR_ADDRESS
5339 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5342 for (i = opnum + 1; i < reload_n_operands; i++)
5343 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5344 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5347 for (i = 0; i < reload_n_operands; i++)
5348 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5349 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5350 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5353 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5356 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5357 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5358 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5360 case RELOAD_FOR_INPUT:
5361 /* Similar to input address, except we start at the next operand for
5362 both input and input address and we do not check for
5363 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5366 for (i = opnum + 1; i < reload_n_operands; i++)
5367 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5368 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5369 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5372 /* ... fall through ... */
5374 case RELOAD_FOR_OPERAND_ADDRESS:
5375 /* Check outputs and their addresses. */
5377 for (i = 0; i < reload_n_operands; i++)
5378 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5379 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5380 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5383 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5385 case RELOAD_FOR_OPADDR_ADDR:
5386 for (i = 0; i < reload_n_operands; i++)
5387 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5388 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5389 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5392 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5393 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5394 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5396 case RELOAD_FOR_INSN:
5397 /* These conflict with other outputs with RELOAD_OTHER. So
5398 we need only check for output addresses. */
5400 opnum = reload_n_operands;
5404 case RELOAD_FOR_OUTPUT:
5405 case RELOAD_FOR_OUTPUT_ADDRESS:
5406 case RELOAD_FOR_OUTADDR_ADDRESS:
5407 /* We already know these can't conflict with a later output. So the
5408 only thing to check are later output addresses.
5409 Note that multiple output operands are emitted in reverse order,
5410 so the conflicting ones are those with lower indices. */
5411 for (i = 0; i < opnum; i++)
5412 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5413 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5416 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5417 could be killed if the register is also used by reload with type
5418 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5419 if (type == RELOAD_FOR_OUTADDR_ADDRESS
5420 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5430 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5431 every register in REG. */
5434 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5438 for (i = REGNO (reg); i < END_REGNO (reg); i++)
5439 if (!reload_reg_reaches_end_p (i, reloadnum))
5445 /* Returns whether R1 and R2 are uniquely chained: the value of one
5446 is used by the other, and that value is not used by any other
5447 reload for this insn. This is used to partially undo the decision
5448 made in find_reloads when in the case of multiple
5449 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5450 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5451 reloads. This code tries to avoid the conflict created by that
5452 change. It might be cleaner to explicitly keep track of which
5453 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5454 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5455 this after the fact. */
5457 reloads_unique_chain_p (int r1, int r2)
5461 /* We only check input reloads. */
5462 if (! rld[r1].in || ! rld[r2].in)
5465 /* Avoid anything with output reloads. */
5466 if (rld[r1].out || rld[r2].out)
5469 /* "chained" means one reload is a component of the other reload,
5470 not the same as the other reload. */
5471 if (rld[r1].opnum != rld[r2].opnum
5472 || rtx_equal_p (rld[r1].in, rld[r2].in)
5473 || rld[r1].optional || rld[r2].optional
5474 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5475 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5478 /* The following loop assumes that r1 is the reload that feeds r2. */
5482 for (i = 0; i < n_reloads; i ++)
5483 /* Look for input reloads that aren't our two */
5484 if (i != r1 && i != r2 && rld[i].in)
5486 /* If our reload is mentioned at all, it isn't a simple chain. */
5487 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5493 /* The recursive function change all occurrences of WHAT in *WHERE
5496 substitute (rtx *where, const_rtx what, rtx repl)
5505 if (*where == what || rtx_equal_p (*where, what))
5507 /* Record the location of the changed rtx. */
5508 substitute_stack.safe_push (where);
5513 code = GET_CODE (*where);
5514 fmt = GET_RTX_FORMAT (code);
5515 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5521 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5522 substitute (&XVECEXP (*where, i, j), what, repl);
5524 else if (fmt[i] == 'e')
5525 substitute (&XEXP (*where, i), what, repl);
5529 /* The function returns TRUE if chain of reload R1 and R2 (in any
5530 order) can be evaluated without usage of intermediate register for
5531 the reload containing another reload. It is important to see
5532 gen_reload to understand what the function is trying to do. As an
5533 example, let us have reload chain
5536 r1: <something> + const
5538 and reload R2 got reload reg HR. The function returns true if
5539 there is a correct insn HR = HR + <something>. Otherwise,
5540 gen_reload will use intermediate register (and this is the reload
5541 reg for R1) to reload <something>.
5543 We need this function to find a conflict for chain reloads. In our
5544 example, if HR = HR + <something> is incorrect insn, then we cannot
5545 use HR as a reload register for R2. If we do use it then we get a
5554 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5556 /* Assume other cases in gen_reload are not possible for
5557 chain reloads or do need an intermediate hard registers. */
5562 rtx_insn *last = get_last_insn ();
5564 /* Make r2 a component of r1. */
5565 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5568 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5569 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5570 gcc_assert (regno >= 0);
5571 out = gen_rtx_REG (rld[r1].mode, regno);
5573 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5575 /* If IN is a paradoxical SUBREG, remove it and try to put the
5576 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5577 strip_paradoxical_subreg (&in, &out);
5579 if (GET_CODE (in) == PLUS
5580 && (REG_P (XEXP (in, 0))
5581 || GET_CODE (XEXP (in, 0)) == SUBREG
5582 || MEM_P (XEXP (in, 0)))
5583 && (REG_P (XEXP (in, 1))
5584 || GET_CODE (XEXP (in, 1)) == SUBREG
5585 || CONSTANT_P (XEXP (in, 1))
5586 || MEM_P (XEXP (in, 1))))
5588 insn = emit_insn (gen_rtx_SET (out, in));
5589 code = recog_memoized (insn);
5594 extract_insn (insn);
5595 /* We want constrain operands to treat this insn strictly in
5596 its validity determination, i.e., the way it would after
5597 reload has completed. */
5598 result = constrain_operands (1, get_enabled_alternatives (insn));
5601 delete_insns_since (last);
5604 /* Restore the original value at each changed address within R1. */
5605 while (!substitute_stack.is_empty ())
5607 rtx *where = substitute_stack.pop ();
5608 *where = rld[r2].in;
5614 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5617 This function uses the same algorithm as reload_reg_free_p above. */
5620 reloads_conflict (int r1, int r2)
5622 enum reload_type r1_type = rld[r1].when_needed;
5623 enum reload_type r2_type = rld[r2].when_needed;
5624 int r1_opnum = rld[r1].opnum;
5625 int r2_opnum = rld[r2].opnum;
5627 /* RELOAD_OTHER conflicts with everything. */
5628 if (r2_type == RELOAD_OTHER)
5631 /* Otherwise, check conflicts differently for each type. */
5635 case RELOAD_FOR_INPUT:
5636 return (r2_type == RELOAD_FOR_INSN
5637 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5638 || r2_type == RELOAD_FOR_OPADDR_ADDR
5639 || r2_type == RELOAD_FOR_INPUT
5640 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5641 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5642 && r2_opnum > r1_opnum));
5644 case RELOAD_FOR_INPUT_ADDRESS:
5645 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5646 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5648 case RELOAD_FOR_INPADDR_ADDRESS:
5649 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5650 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5652 case RELOAD_FOR_OUTPUT_ADDRESS:
5653 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5654 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5656 case RELOAD_FOR_OUTADDR_ADDRESS:
5657 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5658 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5660 case RELOAD_FOR_OPERAND_ADDRESS:
5661 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5662 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5663 && (!reloads_unique_chain_p (r1, r2)
5664 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5666 case RELOAD_FOR_OPADDR_ADDR:
5667 return (r2_type == RELOAD_FOR_INPUT
5668 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5670 case RELOAD_FOR_OUTPUT:
5671 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5672 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5673 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5674 && r2_opnum >= r1_opnum));
5676 case RELOAD_FOR_INSN:
5677 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5678 || r2_type == RELOAD_FOR_INSN
5679 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5681 case RELOAD_FOR_OTHER_ADDRESS:
5682 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5692 /* Indexed by reload number, 1 if incoming value
5693 inherited from previous insns. */
5694 static char reload_inherited[MAX_RELOADS];
5696 /* For an inherited reload, this is the insn the reload was inherited from,
5697 if we know it. Otherwise, this is 0. */
5698 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5700 /* If nonzero, this is a place to get the value of the reload,
5701 rather than using reload_in. */
5702 static rtx reload_override_in[MAX_RELOADS];
5704 /* For each reload, the hard register number of the register used,
5705 or -1 if we did not need a register for this reload. */
5706 static int reload_spill_index[MAX_RELOADS];
5708 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5709 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5711 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5712 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5714 /* Subroutine of free_for_value_p, used to check a single register.
5715 START_REGNO is the starting regno of the full reload register
5716 (possibly comprising multiple hard registers) that we are considering. */
5719 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5720 enum reload_type type, rtx value, rtx out,
5721 int reloadnum, int ignore_address_reloads)
5724 /* Set if we see an input reload that must not share its reload register
5725 with any new earlyclobber, but might otherwise share the reload
5726 register with an output or input-output reload. */
5727 int check_earlyclobber = 0;
5731 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5734 if (out == const0_rtx)
5740 /* We use some pseudo 'time' value to check if the lifetimes of the
5741 new register use would overlap with the one of a previous reload
5742 that is not read-only or uses a different value.
5743 The 'time' used doesn't have to be linear in any shape or form, just
5745 Some reload types use different 'buckets' for each operand.
5746 So there are MAX_RECOG_OPERANDS different time values for each
5748 We compute TIME1 as the time when the register for the prospective
5749 new reload ceases to be live, and TIME2 for each existing
5750 reload as the time when that the reload register of that reload
5752 Where there is little to be gained by exact lifetime calculations,
5753 we just make conservative assumptions, i.e. a longer lifetime;
5754 this is done in the 'default:' cases. */
5757 case RELOAD_FOR_OTHER_ADDRESS:
5758 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5759 time1 = copy ? 0 : 1;
5762 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5764 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5765 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5766 respectively, to the time values for these, we get distinct time
5767 values. To get distinct time values for each operand, we have to
5768 multiply opnum by at least three. We round that up to four because
5769 multiply by four is often cheaper. */
5770 case RELOAD_FOR_INPADDR_ADDRESS:
5771 time1 = opnum * 4 + 2;
5773 case RELOAD_FOR_INPUT_ADDRESS:
5774 time1 = opnum * 4 + 3;
5776 case RELOAD_FOR_INPUT:
5777 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5778 executes (inclusive). */
5779 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5781 case RELOAD_FOR_OPADDR_ADDR:
5783 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5784 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5786 case RELOAD_FOR_OPERAND_ADDRESS:
5787 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5789 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5791 case RELOAD_FOR_OUTADDR_ADDRESS:
5792 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5794 case RELOAD_FOR_OUTPUT_ADDRESS:
5795 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5798 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5801 for (i = 0; i < n_reloads; i++)
5803 rtx reg = rld[i].reg_rtx;
5804 if (reg && REG_P (reg)
5805 && (unsigned) regno - true_regnum (reg) < REG_NREGS (reg)
5808 rtx other_input = rld[i].in;
5810 /* If the other reload loads the same input value, that
5811 will not cause a conflict only if it's loading it into
5812 the same register. */
5813 if (true_regnum (reg) != start_regno)
5814 other_input = NULL_RTX;
5815 if (! other_input || ! rtx_equal_p (other_input, value)
5816 || rld[i].out || out)
5819 switch (rld[i].when_needed)
5821 case RELOAD_FOR_OTHER_ADDRESS:
5824 case RELOAD_FOR_INPADDR_ADDRESS:
5825 /* find_reloads makes sure that a
5826 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5827 by at most one - the first -
5828 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5829 address reload is inherited, the address address reload
5830 goes away, so we can ignore this conflict. */
5831 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5832 && ignore_address_reloads
5833 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5834 Then the address address is still needed to store
5835 back the new address. */
5836 && ! rld[reloadnum].out)
5838 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5839 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5841 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5842 && ignore_address_reloads
5843 /* Unless we are reloading an auto_inc expression. */
5844 && ! rld[reloadnum].out)
5846 time2 = rld[i].opnum * 4 + 2;
5848 case RELOAD_FOR_INPUT_ADDRESS:
5849 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5850 && ignore_address_reloads
5851 && ! rld[reloadnum].out)
5853 time2 = rld[i].opnum * 4 + 3;
5855 case RELOAD_FOR_INPUT:
5856 time2 = rld[i].opnum * 4 + 4;
5857 check_earlyclobber = 1;
5859 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5860 == MAX_RECOG_OPERAND * 4 */
5861 case RELOAD_FOR_OPADDR_ADDR:
5862 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5863 && ignore_address_reloads
5864 && ! rld[reloadnum].out)
5866 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5868 case RELOAD_FOR_OPERAND_ADDRESS:
5869 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5870 check_earlyclobber = 1;
5872 case RELOAD_FOR_INSN:
5873 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5875 case RELOAD_FOR_OUTPUT:
5876 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5877 instruction is executed. */
5878 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5880 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5881 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5883 case RELOAD_FOR_OUTADDR_ADDRESS:
5884 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5885 && ignore_address_reloads
5886 && ! rld[reloadnum].out)
5888 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5890 case RELOAD_FOR_OUTPUT_ADDRESS:
5891 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5894 /* If there is no conflict in the input part, handle this
5895 like an output reload. */
5896 if (! rld[i].in || rtx_equal_p (other_input, value))
5898 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5899 /* Earlyclobbered outputs must conflict with inputs. */
5900 if (earlyclobber_operand_p (rld[i].out))
5901 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5906 /* RELOAD_OTHER might be live beyond instruction execution,
5907 but this is not obvious when we set time2 = 1. So check
5908 here if there might be a problem with the new reload
5909 clobbering the register used by the RELOAD_OTHER. */
5917 && (! rld[i].in || rld[i].out
5918 || ! rtx_equal_p (other_input, value)))
5919 || (out && rld[reloadnum].out_reg
5920 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5926 /* Earlyclobbered outputs must conflict with inputs. */
5927 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5933 /* Return 1 if the value in reload reg REGNO, as used by a reload
5934 needed for the part of the insn specified by OPNUM and TYPE,
5935 may be used to load VALUE into it.
5937 MODE is the mode in which the register is used, this is needed to
5938 determine how many hard regs to test.
5940 Other read-only reloads with the same value do not conflict
5941 unless OUT is nonzero and these other reloads have to live while
5942 output reloads live.
5943 If OUT is CONST0_RTX, this is a special case: it means that the
5944 test should not be for using register REGNO as reload register, but
5945 for copying from register REGNO into the reload register.
5947 RELOADNUM is the number of the reload we want to load this value for;
5948 a reload does not conflict with itself.
5950 When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with
5951 reloads that load an address for the very reload we are considering.
5953 The caller has to make sure that there is no conflict with the return
5957 free_for_value_p (int regno, machine_mode mode, int opnum,
5958 enum reload_type type, rtx value, rtx out, int reloadnum,
5959 int ignore_address_reloads)
5961 int nregs = hard_regno_nregs (regno, mode);
5963 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5964 value, out, reloadnum,
5965 ignore_address_reloads))
5970 /* Return nonzero if the rtx X is invariant over the current function. */
5971 /* ??? Actually, the places where we use this expect exactly what is
5972 tested here, and not everything that is function invariant. In
5973 particular, the frame pointer and arg pointer are special cased;
5974 pic_offset_table_rtx is not, and we must not spill these things to
5978 function_invariant_p (const_rtx x)
5982 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5984 if (GET_CODE (x) == PLUS
5985 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5986 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5991 /* Determine whether the reload reg X overlaps any rtx'es used for
5992 overriding inheritance. Return nonzero if so. */
5995 conflicts_with_override (rtx x)
5998 for (i = 0; i < n_reloads; i++)
5999 if (reload_override_in[i]
6000 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6005 /* Give an error message saying we failed to find a reload for INSN,
6006 and clear out reload R. */
6008 failed_reload (rtx_insn *insn, int r)
6010 if (asm_noperands (PATTERN (insn)) < 0)
6011 /* It's the compiler's fault. */
6012 fatal_insn ("could not find a spill register", insn);
6014 /* It's the user's fault; the operand's mode and constraint
6015 don't match. Disable this reload so we don't crash in final. */
6016 error_for_asm (insn,
6017 "%<asm%> operand constraint incompatible with operand size");
6021 rld[r].optional = 1;
6022 rld[r].secondary_p = 1;
6025 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6026 for reload R. If it's valid, get an rtx for it. Return nonzero if
6029 set_reload_reg (int i, int r)
6032 rtx reg = spill_reg_rtx[i];
6034 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6035 spill_reg_rtx[i] = reg
6036 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6038 regno = true_regnum (reg);
6040 /* Detect when the reload reg can't hold the reload mode.
6041 This used to be one `if', but Sequent compiler can't handle that. */
6042 if (targetm.hard_regno_mode_ok (regno, rld[r].mode))
6044 machine_mode test_mode = VOIDmode;
6046 test_mode = GET_MODE (rld[r].in);
6047 /* If rld[r].in has VOIDmode, it means we will load it
6048 in whatever mode the reload reg has: to wit, rld[r].mode.
6049 We have already tested that for validity. */
6050 /* Aside from that, we need to test that the expressions
6051 to reload from or into have modes which are valid for this
6052 reload register. Otherwise the reload insns would be invalid. */
6053 if (! (rld[r].in != 0 && test_mode != VOIDmode
6054 && !targetm.hard_regno_mode_ok (regno, test_mode)))
6055 if (! (rld[r].out != 0
6056 && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out))))
6058 /* The reg is OK. */
6061 /* Mark as in use for this insn the reload regs we use
6063 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6064 rld[r].when_needed, rld[r].mode);
6066 rld[r].reg_rtx = reg;
6067 reload_spill_index[r] = spill_regs[i];
6074 /* Find a spill register to use as a reload register for reload R.
6075 LAST_RELOAD is nonzero if this is the last reload for the insn being
6078 Set rld[R].reg_rtx to the register allocated.
6080 We return 1 if successful, or 0 if we couldn't find a spill reg and
6081 we didn't change anything. */
6084 allocate_reload_reg (class insn_chain *chain ATTRIBUTE_UNUSED, int r,
6089 /* If we put this reload ahead, thinking it is a group,
6090 then insist on finding a group. Otherwise we can grab a
6091 reg that some other reload needs.
6092 (That can happen when we have a 68000 DATA_OR_FP_REG
6093 which is a group of data regs or one fp reg.)
6094 We need not be so restrictive if there are no more reloads
6097 ??? Really it would be nicer to have smarter handling
6098 for that kind of reg class, where a problem like this is normal.
6099 Perhaps those classes should be avoided for reloading
6100 by use of more alternatives. */
6102 int force_group = rld[r].nregs > 1 && ! last_reload;
6104 /* If we want a single register and haven't yet found one,
6105 take any reg in the right class and not in use.
6106 If we want a consecutive group, here is where we look for it.
6108 We use three passes so we can first look for reload regs to
6109 reuse, which are already in use for other reloads in this insn,
6110 and only then use additional registers which are not "bad", then
6111 finally any register.
6113 I think that maximizing reuse is needed to make sure we don't
6114 run out of reload regs. Suppose we have three reloads, and
6115 reloads A and B can share regs. These need two regs.
6116 Suppose A and B are given different regs.
6117 That leaves none for C. */
6118 for (pass = 0; pass < 3; pass++)
6120 /* I is the index in spill_regs.
6121 We advance it round-robin between insns to use all spill regs
6122 equally, so that inherited reloads have a chance
6123 of leapfrogging each other. */
6127 for (count = 0; count < n_spills; count++)
6129 int rclass = (int) rld[r].rclass;
6135 regnum = spill_regs[i];
6137 if ((reload_reg_free_p (regnum, rld[r].opnum,
6140 /* We check reload_reg_used to make sure we
6141 don't clobber the return register. */
6142 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6143 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6144 rld[r].when_needed, rld[r].in,
6146 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6147 && targetm.hard_regno_mode_ok (regnum, rld[r].mode)
6148 /* Look first for regs to share, then for unshared. But
6149 don't share regs used for inherited reloads; they are
6150 the ones we want to preserve. */
6152 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6154 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6157 int nr = hard_regno_nregs (regnum, rld[r].mode);
6159 /* During the second pass we want to avoid reload registers
6160 which are "bad" for this reload. */
6162 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6165 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6166 (on 68000) got us two FP regs. If NR is 1,
6167 we would reject both of them. */
6170 /* If we need only one reg, we have already won. */
6173 /* But reject a single reg if we demand a group. */
6178 /* Otherwise check that as many consecutive regs as we need
6179 are available here. */
6182 int regno = regnum + nr - 1;
6183 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6184 && spill_reg_order[regno] >= 0
6185 && reload_reg_free_p (regno, rld[r].opnum,
6186 rld[r].when_needed)))
6195 /* If we found something on the current pass, omit later passes. */
6196 if (count < n_spills)
6200 /* We should have found a spill register by now. */
6201 if (count >= n_spills)
6204 /* I is the index in SPILL_REG_RTX of the reload register we are to
6205 allocate. Get an rtx for it and find its register number. */
6207 return set_reload_reg (i, r);
6210 /* Initialize all the tables needed to allocate reload registers.
6211 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6212 is the array we use to restore the reg_rtx field for every reload. */
6215 choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
6219 for (i = 0; i < n_reloads; i++)
6220 rld[i].reg_rtx = save_reload_reg_rtx[i];
6222 memset (reload_inherited, 0, MAX_RELOADS);
6223 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6224 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6226 CLEAR_HARD_REG_SET (reload_reg_used);
6227 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6228 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6229 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6230 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6231 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6233 CLEAR_HARD_REG_SET (reg_used_in_insn);
6236 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6237 reg_used_in_insn |= tmp;
6238 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6239 reg_used_in_insn |= tmp;
6240 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6241 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6244 for (i = 0; i < reload_n_operands; i++)
6246 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6247 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6248 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6249 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6250 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6251 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6254 reload_reg_unavailable = ~chain->used_spill_regs;
6256 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6258 for (i = 0; i < n_reloads; i++)
6259 /* If we have already decided to use a certain register,
6260 don't use it in another way. */
6262 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6263 rld[i].when_needed, rld[i].mode);
6266 /* If X is not a subreg, return it unmodified. If it is a subreg,
6267 look up whether we made a replacement for the SUBREG_REG. Return
6268 either the replacement or the SUBREG_REG. */
6271 replaced_subreg (rtx x)
6273 if (GET_CODE (x) == SUBREG)
6274 return find_replacement (&SUBREG_REG (x));
6278 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6279 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6280 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6281 otherwise it is NULL. */
6284 compute_reload_subreg_offset (machine_mode outermode,
6286 machine_mode innermode)
6288 poly_int64 outer_offset;
6289 machine_mode middlemode;
6292 return subreg_lowpart_offset (outermode, innermode);
6294 outer_offset = SUBREG_BYTE (subreg);
6295 middlemode = GET_MODE (SUBREG_REG (subreg));
6297 /* If SUBREG is paradoxical then return the normal lowpart offset
6298 for OUTERMODE and INNERMODE. Our caller has already checked
6299 that OUTERMODE fits in INNERMODE. */
6300 if (paradoxical_subreg_p (outermode, middlemode))
6301 return subreg_lowpart_offset (outermode, innermode);
6303 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6304 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6305 return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6308 /* Assign hard reg targets for the pseudo-registers we must reload
6309 into hard regs for this insn.
6310 Also output the instructions to copy them in and out of the hard regs.
6312 For machines with register classes, we are responsible for
6313 finding a reload reg in the proper class. */
6316 choose_reload_regs (class insn_chain *chain)
6318 rtx_insn *insn = chain->insn;
6320 unsigned int max_group_size = 1;
6321 enum reg_class group_class = NO_REGS;
6322 int pass, win, inheritance;
6324 rtx save_reload_reg_rtx[MAX_RELOADS];
6326 /* In order to be certain of getting the registers we need,
6327 we must sort the reloads into order of increasing register class.
6328 Then our grabbing of reload registers will parallel the process
6329 that provided the reload registers.
6331 Also note whether any of the reloads wants a consecutive group of regs.
6332 If so, record the maximum size of the group desired and what
6333 register class contains all the groups needed by this insn. */
6335 for (j = 0; j < n_reloads; j++)
6337 reload_order[j] = j;
6338 if (rld[j].reg_rtx != NULL_RTX)
6340 gcc_assert (REG_P (rld[j].reg_rtx)
6341 && HARD_REGISTER_P (rld[j].reg_rtx));
6342 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6345 reload_spill_index[j] = -1;
6347 if (rld[j].nregs > 1)
6349 max_group_size = MAX (rld[j].nregs, max_group_size);
6351 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6354 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6358 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6360 /* If -O, try first with inheritance, then turning it off.
6361 If not -O, don't do inheritance.
6362 Using inheritance when not optimizing leads to paradoxes
6363 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6364 because one side of the comparison might be inherited. */
6366 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6368 choose_reload_regs_init (chain, save_reload_reg_rtx);
6370 /* Process the reloads in order of preference just found.
6371 Beyond this point, subregs can be found in reload_reg_rtx.
6373 This used to look for an existing reloaded home for all of the
6374 reloads, and only then perform any new reloads. But that could lose
6375 if the reloads were done out of reg-class order because a later
6376 reload with a looser constraint might have an old home in a register
6377 needed by an earlier reload with a tighter constraint.
6379 To solve this, we make two passes over the reloads, in the order
6380 described above. In the first pass we try to inherit a reload
6381 from a previous insn. If there is a later reload that needs a
6382 class that is a proper subset of the class being processed, we must
6383 also allocate a spill register during the first pass.
6385 Then make a second pass over the reloads to allocate any reloads
6386 that haven't been given registers yet. */
6388 for (j = 0; j < n_reloads; j++)
6390 int r = reload_order[j];
6391 rtx search_equiv = NULL_RTX;
6393 /* Ignore reloads that got marked inoperative. */
6394 if (rld[r].out == 0 && rld[r].in == 0
6395 && ! rld[r].secondary_p)
6398 /* If find_reloads chose to use reload_in or reload_out as a reload
6399 register, we don't need to chose one. Otherwise, try even if it
6400 found one since we might save an insn if we find the value lying
6402 Try also when reload_in is a pseudo without a hard reg. */
6403 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6404 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6405 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6406 && !MEM_P (rld[r].in)
6407 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6410 #if 0 /* No longer needed for correct operation.
6411 It might give better code, or might not; worth an experiment? */
6412 /* If this is an optional reload, we can't inherit from earlier insns
6413 until we are sure that any non-optional reloads have been allocated.
6414 The following code takes advantage of the fact that optional reloads
6415 are at the end of reload_order. */
6416 if (rld[r].optional != 0)
6417 for (i = 0; i < j; i++)
6418 if ((rld[reload_order[i]].out != 0
6419 || rld[reload_order[i]].in != 0
6420 || rld[reload_order[i]].secondary_p)
6421 && ! rld[reload_order[i]].optional
6422 && rld[reload_order[i]].reg_rtx == 0)
6423 allocate_reload_reg (chain, reload_order[i], 0);
6426 /* First see if this pseudo is already available as reloaded
6427 for a previous insn. We cannot try to inherit for reloads
6428 that are smaller than the maximum number of registers needed
6429 for groups unless the register we would allocate cannot be used
6432 We could check here to see if this is a secondary reload for
6433 an object that is already in a register of the desired class.
6434 This would avoid the need for the secondary reload register.
6435 But this is complex because we can't easily determine what
6436 objects might want to be loaded via this reload. So let a
6437 register be allocated here. In `emit_reload_insns' we suppress
6438 one of the loads in the case described above. */
6442 poly_int64 byte = 0;
6444 machine_mode mode = VOIDmode;
6445 rtx subreg = NULL_RTX;
6449 else if (REG_P (rld[r].in))
6451 regno = REGNO (rld[r].in);
6452 mode = GET_MODE (rld[r].in);
6454 else if (REG_P (rld[r].in_reg))
6456 regno = REGNO (rld[r].in_reg);
6457 mode = GET_MODE (rld[r].in_reg);
6459 else if (GET_CODE (rld[r].in_reg) == SUBREG
6460 && REG_P (SUBREG_REG (rld[r].in_reg)))
6462 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6463 if (regno < FIRST_PSEUDO_REGISTER)
6464 regno = subreg_regno (rld[r].in_reg);
6467 subreg = rld[r].in_reg;
6468 byte = SUBREG_BYTE (subreg);
6470 mode = GET_MODE (rld[r].in_reg);
6473 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6474 && REG_P (XEXP (rld[r].in_reg, 0)))
6476 regno = REGNO (XEXP (rld[r].in_reg, 0));
6477 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6478 rld[r].out = rld[r].in;
6482 /* This won't work, since REGNO can be a pseudo reg number.
6483 Also, it takes much more hair to keep track of all the things
6484 that can invalidate an inherited reload of part of a pseudoreg. */
6485 else if (GET_CODE (rld[r].in) == SUBREG
6486 && REG_P (SUBREG_REG (rld[r].in)))
6487 regno = subreg_regno (rld[r].in);
6491 && reg_last_reload_reg[regno] != 0
6493 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])),
6494 GET_MODE_SIZE (mode) + byte))
6495 /* Verify that the register it's in can be used in
6497 && (REG_CAN_CHANGE_MODE_P
6498 (REGNO (reg_last_reload_reg[regno]),
6499 GET_MODE (reg_last_reload_reg[regno]),
6502 enum reg_class rclass = rld[r].rclass, last_class;
6503 rtx last_reg = reg_last_reload_reg[regno];
6505 i = REGNO (last_reg);
6506 byte = compute_reload_subreg_offset (mode,
6508 GET_MODE (last_reg));
6509 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6510 last_class = REGNO_REG_CLASS (i);
6512 if (reg_reloaded_contents[i] == regno
6513 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6514 && targetm.hard_regno_mode_ok (i, rld[r].mode)
6515 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6516 /* Even if we can't use this register as a reload
6517 register, we might use it for reload_override_in,
6518 if copying it to the desired class is cheap
6520 || ((register_move_cost (mode, last_class, rclass)
6521 < memory_move_cost (mode, rclass, true))
6522 && (secondary_reload_class (1, rclass, mode,
6525 && !(targetm.secondary_memory_needed
6526 (mode, last_class, rclass))))
6527 && (rld[r].nregs == max_group_size
6528 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6530 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6531 rld[r].when_needed, rld[r].in,
6534 /* If a group is needed, verify that all the subsequent
6535 registers still have their values intact. */
6536 int nr = hard_regno_nregs (i, rld[r].mode);
6539 for (k = 1; k < nr; k++)
6540 if (reg_reloaded_contents[i + k] != regno
6541 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6549 last_reg = (GET_MODE (last_reg) == mode
6550 ? last_reg : gen_rtx_REG (mode, i));
6553 for (k = 0; k < nr; k++)
6554 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6557 /* We found a register that contains the
6558 value we need. If this register is the
6559 same as an `earlyclobber' operand of the
6560 current insn, just mark it as a place to
6561 reload from since we can't use it as the
6562 reload register itself. */
6564 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6565 if (reg_overlap_mentioned_for_reload_p
6566 (reg_last_reload_reg[regno],
6567 reload_earlyclobbers[i1]))
6570 if (i1 != n_earlyclobbers
6571 || ! (free_for_value_p (i, rld[r].mode,
6573 rld[r].when_needed, rld[r].in,
6575 /* Don't use it if we'd clobber a pseudo reg. */
6576 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6578 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6579 /* Don't clobber the frame pointer. */
6580 || (i == HARD_FRAME_POINTER_REGNUM
6581 && frame_pointer_needed
6583 /* Don't really use the inherited spill reg
6584 if we need it wider than we've got it. */
6585 || paradoxical_subreg_p (rld[r].mode, mode)
6588 /* If find_reloads chose reload_out as reload
6589 register, stay with it - that leaves the
6590 inherited register for subsequent reloads. */
6591 || (rld[r].out && rld[r].reg_rtx
6592 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6594 if (! rld[r].optional)
6596 reload_override_in[r] = last_reg;
6597 reload_inheritance_insn[r]
6598 = reg_reloaded_insn[i];
6604 /* We can use this as a reload reg. */
6605 /* Mark the register as in use for this part of
6607 mark_reload_reg_in_use (i,
6611 rld[r].reg_rtx = last_reg;
6612 reload_inherited[r] = 1;
6613 reload_inheritance_insn[r]
6614 = reg_reloaded_insn[i];
6615 reload_spill_index[r] = i;
6616 for (k = 0; k < nr; k++)
6617 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6625 /* Here's another way to see if the value is already lying around. */
6628 && ! reload_inherited[r]
6630 && (CONSTANT_P (rld[r].in)
6631 || GET_CODE (rld[r].in) == PLUS
6632 || REG_P (rld[r].in)
6633 || MEM_P (rld[r].in))
6634 && (rld[r].nregs == max_group_size
6635 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6636 search_equiv = rld[r].in;
6641 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6642 -1, NULL, 0, rld[r].mode);
6648 regno = REGNO (equiv);
6651 /* This must be a SUBREG of a hard register.
6652 Make a new REG since this might be used in an
6653 address and not all machines support SUBREGs
6655 gcc_assert (GET_CODE (equiv) == SUBREG);
6656 regno = subreg_regno (equiv);
6657 equiv = gen_rtx_REG (rld[r].mode, regno);
6658 /* If we choose EQUIV as the reload register, but the
6659 loop below decides to cancel the inheritance, we'll
6660 end up reloading EQUIV in rld[r].mode, not the mode
6661 it had originally. That isn't safe when EQUIV isn't
6662 available as a spill register since its value might
6663 still be live at this point. */
6664 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6665 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6670 /* If we found a spill reg, reject it unless it is free
6671 and of the desired class. */
6675 int bad_for_class = 0;
6676 int max_regno = regno + rld[r].nregs;
6678 for (i = regno; i < max_regno; i++)
6680 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6682 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6687 && ! free_for_value_p (regno, rld[r].mode,
6688 rld[r].opnum, rld[r].when_needed,
6689 rld[r].in, rld[r].out, r, 1))
6695 && !targetm.hard_regno_mode_ok (regno, rld[r].mode))
6698 /* We found a register that contains the value we need.
6699 If this register is the same as an `earlyclobber' operand
6700 of the current insn, just mark it as a place to reload from
6701 since we can't use it as the reload register itself. */
6704 for (i = 0; i < n_earlyclobbers; i++)
6705 if (reg_overlap_mentioned_for_reload_p (equiv,
6706 reload_earlyclobbers[i]))
6708 if (! rld[r].optional)
6709 reload_override_in[r] = equiv;
6714 /* If the equiv register we have found is explicitly clobbered
6715 in the current insn, it depends on the reload type if we
6716 can use it, use it for reload_override_in, or not at all.
6717 In particular, we then can't use EQUIV for a
6718 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6722 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6723 switch (rld[r].when_needed)
6725 case RELOAD_FOR_OTHER_ADDRESS:
6726 case RELOAD_FOR_INPADDR_ADDRESS:
6727 case RELOAD_FOR_INPUT_ADDRESS:
6728 case RELOAD_FOR_OPADDR_ADDR:
6731 case RELOAD_FOR_INPUT:
6732 case RELOAD_FOR_OPERAND_ADDRESS:
6733 if (! rld[r].optional)
6734 reload_override_in[r] = equiv;
6740 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6741 switch (rld[r].when_needed)
6743 case RELOAD_FOR_OTHER_ADDRESS:
6744 case RELOAD_FOR_INPADDR_ADDRESS:
6745 case RELOAD_FOR_INPUT_ADDRESS:
6746 case RELOAD_FOR_OPADDR_ADDR:
6747 case RELOAD_FOR_OPERAND_ADDRESS:
6748 case RELOAD_FOR_INPUT:
6751 if (! rld[r].optional)
6752 reload_override_in[r] = equiv;
6760 /* If we found an equivalent reg, say no code need be generated
6761 to load it, and use it as our reload reg. */
6763 && (regno != HARD_FRAME_POINTER_REGNUM
6764 || !frame_pointer_needed))
6766 int nr = hard_regno_nregs (regno, rld[r].mode);
6768 rld[r].reg_rtx = equiv;
6769 reload_spill_index[r] = regno;
6770 reload_inherited[r] = 1;
6772 /* If reg_reloaded_valid is not set for this register,
6773 there might be a stale spill_reg_store lying around.
6774 We must clear it, since otherwise emit_reload_insns
6775 might delete the store. */
6776 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6777 spill_reg_store[regno] = NULL;
6778 /* If any of the hard registers in EQUIV are spill
6779 registers, mark them as in use for this insn. */
6780 for (k = 0; k < nr; k++)
6782 i = spill_reg_order[regno + k];
6785 mark_reload_reg_in_use (regno, rld[r].opnum,
6788 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6795 /* If we found a register to use already, or if this is an optional
6796 reload, we are done. */
6797 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6801 /* No longer needed for correct operation. Might or might
6802 not give better code on the average. Want to experiment? */
6804 /* See if there is a later reload that has a class different from our
6805 class that intersects our class or that requires less register
6806 than our reload. If so, we must allocate a register to this
6807 reload now, since that reload might inherit a previous reload
6808 and take the only available register in our class. Don't do this
6809 for optional reloads since they will force all previous reloads
6810 to be allocated. Also don't do this for reloads that have been
6813 for (i = j + 1; i < n_reloads; i++)
6815 int s = reload_order[i];
6817 if ((rld[s].in == 0 && rld[s].out == 0
6818 && ! rld[s].secondary_p)
6822 if ((rld[s].rclass != rld[r].rclass
6823 && reg_classes_intersect_p (rld[r].rclass,
6825 || rld[s].nregs < rld[r].nregs)
6832 allocate_reload_reg (chain, r, j == n_reloads - 1);
6836 /* Now allocate reload registers for anything non-optional that
6837 didn't get one yet. */
6838 for (j = 0; j < n_reloads; j++)
6840 int r = reload_order[j];
6842 /* Ignore reloads that got marked inoperative. */
6843 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6846 /* Skip reloads that already have a register allocated or are
6848 if (rld[r].reg_rtx != 0 || rld[r].optional)
6851 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6855 /* If that loop got all the way, we have won. */
6862 /* Loop around and try without any inheritance. */
6867 /* First undo everything done by the failed attempt
6868 to allocate with inheritance. */
6869 choose_reload_regs_init (chain, save_reload_reg_rtx);
6871 /* Some sanity tests to verify that the reloads found in the first
6872 pass are identical to the ones we have now. */
6873 gcc_assert (chain->n_reloads == n_reloads);
6875 for (i = 0; i < n_reloads; i++)
6877 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6879 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6880 for (j = 0; j < n_spills; j++)
6881 if (spill_regs[j] == chain->rld[i].regno)
6882 if (! set_reload_reg (j, i))
6883 failed_reload (chain->insn, i);
6887 /* If we thought we could inherit a reload, because it seemed that
6888 nothing else wanted the same reload register earlier in the insn,
6889 verify that assumption, now that all reloads have been assigned.
6890 Likewise for reloads where reload_override_in has been set. */
6892 /* If doing expensive optimizations, do one preliminary pass that doesn't
6893 cancel any inheritance, but removes reloads that have been needed only
6894 for reloads that we know can be inherited. */
6895 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6897 for (j = 0; j < n_reloads; j++)
6899 int r = reload_order[j];
6902 if (reload_inherited[r] && rld[r].reg_rtx)
6903 check_reg = rld[r].reg_rtx;
6904 else if (reload_override_in[r]
6905 && (REG_P (reload_override_in[r])
6906 || GET_CODE (reload_override_in[r]) == SUBREG))
6907 check_reg = reload_override_in[r];
6910 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6911 rld[r].opnum, rld[r].when_needed, rld[r].in,
6912 (reload_inherited[r]
6913 ? rld[r].out : const0_rtx),
6918 reload_inherited[r] = 0;
6919 reload_override_in[r] = 0;
6921 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6922 reload_override_in, then we do not need its related
6923 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6924 likewise for other reload types.
6925 We handle this by removing a reload when its only replacement
6926 is mentioned in reload_in of the reload we are going to inherit.
6927 A special case are auto_inc expressions; even if the input is
6928 inherited, we still need the address for the output. We can
6929 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6930 If we succeeded removing some reload and we are doing a preliminary
6931 pass just to remove such reloads, make another pass, since the
6932 removal of one reload might allow us to inherit another one. */
6934 && rld[r].out != rld[r].in
6935 && remove_address_replacements (rld[r].in))
6940 /* If we needed a memory location for the reload, we also have to
6941 remove its related reloads. */
6943 && rld[r].out != rld[r].in
6944 && (tem = replaced_subreg (rld[r].in), REG_P (tem))
6945 && REGNO (tem) < FIRST_PSEUDO_REGISTER
6946 && (targetm.secondary_memory_needed
6947 (rld[r].inmode, REGNO_REG_CLASS (REGNO (tem)),
6949 && remove_address_replacements
6950 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
6951 rld[r].when_needed)))
6959 /* Now that reload_override_in is known valid,
6960 actually override reload_in. */
6961 for (j = 0; j < n_reloads; j++)
6962 if (reload_override_in[j])
6963 rld[j].in = reload_override_in[j];
6965 /* If this reload won't be done because it has been canceled or is
6966 optional and not inherited, clear reload_reg_rtx so other
6967 routines (such as subst_reloads) don't get confused. */
6968 for (j = 0; j < n_reloads; j++)
6969 if (rld[j].reg_rtx != 0
6970 && ((rld[j].optional && ! reload_inherited[j])
6971 || (rld[j].in == 0 && rld[j].out == 0
6972 && ! rld[j].secondary_p)))
6974 int regno = true_regnum (rld[j].reg_rtx);
6976 if (spill_reg_order[regno] >= 0)
6977 clear_reload_reg_in_use (regno, rld[j].opnum,
6978 rld[j].when_needed, rld[j].mode);
6980 reload_spill_index[j] = -1;
6983 /* Record which pseudos and which spill regs have output reloads. */
6984 for (j = 0; j < n_reloads; j++)
6986 int r = reload_order[j];
6988 i = reload_spill_index[r];
6990 /* I is nonneg if this reload uses a register.
6991 If rld[r].reg_rtx is 0, this is an optional reload
6992 that we opted to ignore. */
6993 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6994 && rld[r].reg_rtx != 0)
6996 int nregno = REGNO (rld[r].out_reg);
6999 if (nregno < FIRST_PSEUDO_REGISTER)
7000 nr = hard_regno_nregs (nregno, rld[r].mode);
7003 SET_REGNO_REG_SET (®_has_output_reload,
7007 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7009 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7010 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7011 || rld[r].when_needed == RELOAD_FOR_INSN);
7016 /* Deallocate the reload register for reload R. This is called from
7017 remove_address_replacements. */
7020 deallocate_reload_reg (int r)
7024 if (! rld[r].reg_rtx)
7026 regno = true_regnum (rld[r].reg_rtx);
7028 if (spill_reg_order[regno] >= 0)
7029 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7031 reload_spill_index[r] = -1;
7034 /* These arrays are filled by emit_reload_insns and its subroutines. */
7035 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7036 static rtx_insn *other_input_address_reload_insns = 0;
7037 static rtx_insn *other_input_reload_insns = 0;
7038 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7039 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7040 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7041 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7042 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7043 static rtx_insn *operand_reload_insns = 0;
7044 static rtx_insn *other_operand_reload_insns = 0;
7045 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7047 /* Values to be put in spill_reg_store are put here first. Instructions
7048 must only be placed here if the associated reload register reaches
7049 the end of the instruction's reload sequence. */
7050 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7051 static HARD_REG_SET reg_reloaded_died;
7053 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7054 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7055 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7056 adjusted register, and return true. Otherwise, return false. */
7058 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7059 enum reg_class new_class,
7060 machine_mode new_mode)
7065 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7067 unsigned regno = REGNO (reg);
7069 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7071 if (GET_MODE (reg) != new_mode)
7073 if (!targetm.hard_regno_mode_ok (regno, new_mode))
7075 if (hard_regno_nregs (regno, new_mode) > REG_NREGS (reg))
7077 reg = reload_adjust_reg_for_mode (reg, new_mode);
7085 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7086 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7087 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7088 adjusted register, and return true. Otherwise, return false. */
7090 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7091 enum insn_code icode)
7094 enum reg_class new_class = scratch_reload_class (icode);
7095 machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7097 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7098 new_class, new_mode);
7101 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7102 has the number J. OLD contains the value to be used as input. */
7105 emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
7108 rtx_insn *insn = chain->insn;
7110 rtx oldequiv_reg = 0;
7116 /* delete_output_reload is only invoked properly if old contains
7117 the original pseudo register. Since this is replaced with a
7118 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7119 find the pseudo in RELOAD_IN_REG. This is also used to
7120 determine whether a secondary reload is needed. */
7121 if (reload_override_in[j]
7122 && (REG_P (rl->in_reg)
7123 || (GET_CODE (rl->in_reg) == SUBREG
7124 && REG_P (SUBREG_REG (rl->in_reg)))))
7131 else if (REG_P (oldequiv))
7132 oldequiv_reg = oldequiv;
7133 else if (GET_CODE (oldequiv) == SUBREG)
7134 oldequiv_reg = SUBREG_REG (oldequiv);
7136 reloadreg = reload_reg_rtx_for_input[j];
7137 mode = GET_MODE (reloadreg);
7139 /* If we are reloading from a register that was recently stored in
7140 with an output-reload, see if we can prove there was
7141 actually no need to store the old value in it. */
7143 if (optimize && REG_P (oldequiv)
7144 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7145 && spill_reg_store[REGNO (oldequiv)]
7147 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7148 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7150 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7152 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7155 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7156 oldequiv = SUBREG_REG (oldequiv);
7157 if (GET_MODE (oldequiv) != VOIDmode
7158 && mode != GET_MODE (oldequiv))
7159 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7161 /* Switch to the right place to emit the reload insns. */
7162 switch (rl->when_needed)
7165 where = &other_input_reload_insns;
7167 case RELOAD_FOR_INPUT:
7168 where = &input_reload_insns[rl->opnum];
7170 case RELOAD_FOR_INPUT_ADDRESS:
7171 where = &input_address_reload_insns[rl->opnum];
7173 case RELOAD_FOR_INPADDR_ADDRESS:
7174 where = &inpaddr_address_reload_insns[rl->opnum];
7176 case RELOAD_FOR_OUTPUT_ADDRESS:
7177 where = &output_address_reload_insns[rl->opnum];
7179 case RELOAD_FOR_OUTADDR_ADDRESS:
7180 where = &outaddr_address_reload_insns[rl->opnum];
7182 case RELOAD_FOR_OPERAND_ADDRESS:
7183 where = &operand_reload_insns;
7185 case RELOAD_FOR_OPADDR_ADDR:
7186 where = &other_operand_reload_insns;
7188 case RELOAD_FOR_OTHER_ADDRESS:
7189 where = &other_input_address_reload_insns;
7195 push_to_sequence (*where);
7197 /* Auto-increment addresses must be reloaded in a special way. */
7198 if (rl->out && ! rl->out_reg)
7200 /* We are not going to bother supporting the case where a
7201 incremented register can't be copied directly from
7202 OLDEQUIV since this seems highly unlikely. */
7203 gcc_assert (rl->secondary_in_reload < 0);
7205 if (reload_inherited[j])
7206 oldequiv = reloadreg;
7208 old = XEXP (rl->in_reg, 0);
7210 /* Prevent normal processing of this reload. */
7212 /* Output a special code sequence for this case. */
7213 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7216 /* If we are reloading a pseudo-register that was set by the previous
7217 insn, see if we can get rid of that pseudo-register entirely
7218 by redirecting the previous insn into our reload register. */
7220 else if (optimize && REG_P (old)
7221 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7222 && dead_or_set_p (insn, old)
7223 /* This is unsafe if some other reload
7224 uses the same reg first. */
7225 && ! conflicts_with_override (reloadreg)
7226 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7227 rl->when_needed, old, rl->out, j, 0))
7229 rtx_insn *temp = PREV_INSN (insn);
7230 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7231 temp = PREV_INSN (temp);
7233 && NONJUMP_INSN_P (temp)
7234 && GET_CODE (PATTERN (temp)) == SET
7235 && SET_DEST (PATTERN (temp)) == old
7236 /* Make sure we can access insn_operand_constraint. */
7237 && asm_noperands (PATTERN (temp)) < 0
7238 /* This is unsafe if operand occurs more than once in current
7239 insn. Perhaps some occurrences aren't reloaded. */
7240 && count_occurrences (PATTERN (insn), old, 0) == 1)
7242 rtx old = SET_DEST (PATTERN (temp));
7243 /* Store into the reload register instead of the pseudo. */
7244 SET_DEST (PATTERN (temp)) = reloadreg;
7246 /* Verify that resulting insn is valid.
7248 Note that we have replaced the destination of TEMP with
7249 RELOADREG. If TEMP references RELOADREG within an
7250 autoincrement addressing mode, then the resulting insn
7251 is ill-formed and we must reject this optimization. */
7252 extract_insn (temp);
7253 if (constrain_operands (1, get_enabled_alternatives (temp))
7254 && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
7256 /* If the previous insn is an output reload, the source is
7257 a reload register, and its spill_reg_store entry will
7258 contain the previous destination. This is now
7260 if (REG_P (SET_SRC (PATTERN (temp)))
7261 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7263 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7264 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7267 /* If these are the only uses of the pseudo reg,
7268 pretend for GDB it lives in the reload reg we used. */
7269 if (REG_N_DEATHS (REGNO (old)) == 1
7270 && REG_N_SETS (REGNO (old)) == 1)
7272 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7273 if (ira_conflicts_p)
7274 /* Inform IRA about the change. */
7275 ira_mark_allocation_change (REGNO (old));
7276 alter_reg (REGNO (old), -1, false);
7280 /* Adjust any debug insns between temp and insn. */
7281 while ((temp = NEXT_INSN (temp)) != insn)
7282 if (DEBUG_BIND_INSN_P (temp))
7283 INSN_VAR_LOCATION_LOC (temp)
7284 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp),
7287 gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp));
7291 SET_DEST (PATTERN (temp)) = old;
7296 /* We can't do that, so output an insn to load RELOADREG. */
7298 /* If we have a secondary reload, pick up the secondary register
7299 and icode, if any. If OLDEQUIV and OLD are different or
7300 if this is an in-out reload, recompute whether or not we
7301 still need a secondary register and what the icode should
7302 be. If we still need a secondary register and the class or
7303 icode is different, go back to reloading from OLD if using
7304 OLDEQUIV means that we got the wrong type of register. We
7305 cannot have different class or icode due to an in-out reload
7306 because we don't make such reloads when both the input and
7307 output need secondary reload registers. */
7309 if (! special && rl->secondary_in_reload >= 0)
7311 rtx second_reload_reg = 0;
7312 rtx third_reload_reg = 0;
7313 int secondary_reload = rl->secondary_in_reload;
7314 rtx real_oldequiv = oldequiv;
7317 enum insn_code icode;
7318 enum insn_code tertiary_icode = CODE_FOR_nothing;
7320 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7321 and similarly for OLD.
7322 See comments in get_secondary_reload in reload.c. */
7323 /* If it is a pseudo that cannot be replaced with its
7324 equivalent MEM, we must fall back to reload_in, which
7325 will have all the necessary substitutions registered.
7326 Likewise for a pseudo that can't be replaced with its
7327 equivalent constant.
7329 Take extra care for subregs of such pseudos. Note that
7330 we cannot use reg_equiv_mem in this case because it is
7331 not in the right mode. */
7334 if (GET_CODE (tmp) == SUBREG)
7335 tmp = SUBREG_REG (tmp);
7337 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7338 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7339 || reg_equiv_constant (REGNO (tmp)) != 0))
7341 if (! reg_equiv_mem (REGNO (tmp))
7342 || num_not_at_initial_offset
7343 || GET_CODE (oldequiv) == SUBREG)
7344 real_oldequiv = rl->in;
7346 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7350 if (GET_CODE (tmp) == SUBREG)
7351 tmp = SUBREG_REG (tmp);
7353 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7354 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7355 || reg_equiv_constant (REGNO (tmp)) != 0))
7357 if (! reg_equiv_mem (REGNO (tmp))
7358 || num_not_at_initial_offset
7359 || GET_CODE (old) == SUBREG)
7362 real_old = reg_equiv_mem (REGNO (tmp));
7365 second_reload_reg = rld[secondary_reload].reg_rtx;
7366 if (rld[secondary_reload].secondary_in_reload >= 0)
7368 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7370 third_reload_reg = rld[tertiary_reload].reg_rtx;
7371 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7372 /* We'd have to add more code for quartary reloads. */
7373 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7375 icode = rl->secondary_in_icode;
7377 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7378 || (rl->in != 0 && rl->out != 0))
7380 secondary_reload_info sri, sri2;
7381 enum reg_class new_class, new_t_class;
7383 sri.icode = CODE_FOR_nothing;
7384 sri.prev_sri = NULL;
7386 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7390 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7391 second_reload_reg = 0;
7392 else if (new_class == NO_REGS)
7394 if (reload_adjust_reg_for_icode (&second_reload_reg,
7396 (enum insn_code) sri.icode))
7398 icode = (enum insn_code) sri.icode;
7399 third_reload_reg = 0;
7404 real_oldequiv = real_old;
7407 else if (sri.icode != CODE_FOR_nothing)
7408 /* We currently lack a way to express this in reloads. */
7412 sri2.icode = CODE_FOR_nothing;
7413 sri2.prev_sri = &sri;
7415 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7418 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7420 if (reload_adjust_reg_for_temp (&second_reload_reg,
7424 third_reload_reg = 0;
7425 tertiary_icode = (enum insn_code) sri2.icode;
7430 real_oldequiv = real_old;
7433 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7435 rtx intermediate = second_reload_reg;
7437 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7439 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7443 second_reload_reg = intermediate;
7444 tertiary_icode = (enum insn_code) sri2.icode;
7449 real_oldequiv = real_old;
7452 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7454 rtx intermediate = second_reload_reg;
7456 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7458 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7461 second_reload_reg = intermediate;
7462 tertiary_icode = (enum insn_code) sri2.icode;
7467 real_oldequiv = real_old;
7472 /* This could be handled more intelligently too. */
7474 real_oldequiv = real_old;
7479 /* If we still need a secondary reload register, check
7480 to see if it is being used as a scratch or intermediate
7481 register and generate code appropriately. If we need
7482 a scratch register, use REAL_OLDEQUIV since the form of
7483 the insn may depend on the actual address if it is
7486 if (second_reload_reg)
7488 if (icode != CODE_FOR_nothing)
7490 /* We'd have to add extra code to handle this case. */
7491 gcc_assert (!third_reload_reg);
7493 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7494 second_reload_reg));
7499 /* See if we need a scratch register to load the
7500 intermediate register (a tertiary reload). */
7501 if (tertiary_icode != CODE_FOR_nothing)
7503 emit_insn ((GEN_FCN (tertiary_icode)
7504 (second_reload_reg, real_oldequiv,
7505 third_reload_reg)));
7507 else if (third_reload_reg)
7509 gen_reload (third_reload_reg, real_oldequiv,
7512 gen_reload (second_reload_reg, third_reload_reg,
7517 gen_reload (second_reload_reg, real_oldequiv,
7521 oldequiv = second_reload_reg;
7526 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7528 rtx real_oldequiv = oldequiv;
7530 if ((REG_P (oldequiv)
7531 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7532 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7533 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7534 || (GET_CODE (oldequiv) == SUBREG
7535 && REG_P (SUBREG_REG (oldequiv))
7536 && (REGNO (SUBREG_REG (oldequiv))
7537 >= FIRST_PSEUDO_REGISTER)
7538 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7539 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7540 || (CONSTANT_P (oldequiv)
7541 && (targetm.preferred_reload_class (oldequiv,
7542 REGNO_REG_CLASS (REGNO (reloadreg)))
7544 real_oldequiv = rl->in;
7545 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7549 if (cfun->can_throw_non_call_exceptions)
7550 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7552 /* End this sequence. */
7553 *where = get_insns ();
7556 /* Update reload_override_in so that delete_address_reloads_1
7557 can see the actual register usage. */
7559 reload_override_in[j] = oldequiv;
7562 /* Generate insns to for the output reload RL, which is for the insn described
7563 by CHAIN and has the number J. */
7565 emit_output_reload_insns (class insn_chain *chain, struct reload *rl,
7569 rtx_insn *insn = chain->insn;
7576 if (rl->when_needed == RELOAD_OTHER)
7579 push_to_sequence (output_reload_insns[rl->opnum]);
7581 rl_reg_rtx = reload_reg_rtx_for_output[j];
7582 mode = GET_MODE (rl_reg_rtx);
7584 reloadreg = rl_reg_rtx;
7586 /* If we need two reload regs, set RELOADREG to the intermediate
7587 one, since it will be stored into OLD. We might need a secondary
7588 register only for an input reload, so check again here. */
7590 if (rl->secondary_out_reload >= 0)
7593 int secondary_reload = rl->secondary_out_reload;
7594 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7596 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7597 && reg_equiv_mem (REGNO (old)) != 0)
7598 real_old = reg_equiv_mem (REGNO (old));
7600 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7602 rtx second_reloadreg = reloadreg;
7603 reloadreg = rld[secondary_reload].reg_rtx;
7605 /* See if RELOADREG is to be used as a scratch register
7606 or as an intermediate register. */
7607 if (rl->secondary_out_icode != CODE_FOR_nothing)
7609 /* We'd have to add extra code to handle this case. */
7610 gcc_assert (tertiary_reload < 0);
7612 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7613 (real_old, second_reloadreg, reloadreg)));
7618 /* See if we need both a scratch and intermediate reload
7621 enum insn_code tertiary_icode
7622 = rld[secondary_reload].secondary_out_icode;
7624 /* We'd have to add more code for quartary reloads. */
7625 gcc_assert (tertiary_reload < 0
7626 || rld[tertiary_reload].secondary_out_reload < 0);
7628 if (GET_MODE (reloadreg) != mode)
7629 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7631 if (tertiary_icode != CODE_FOR_nothing)
7633 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7635 /* Copy primary reload reg to secondary reload reg.
7636 (Note that these have been swapped above, then
7637 secondary reload reg to OLD using our insn.) */
7639 /* If REAL_OLD is a paradoxical SUBREG, remove it
7640 and try to put the opposite SUBREG on
7642 strip_paradoxical_subreg (&real_old, &reloadreg);
7644 gen_reload (reloadreg, second_reloadreg,
7645 rl->opnum, rl->when_needed);
7646 emit_insn ((GEN_FCN (tertiary_icode)
7647 (real_old, reloadreg, third_reloadreg)));
7653 /* Copy between the reload regs here and then to
7656 gen_reload (reloadreg, second_reloadreg,
7657 rl->opnum, rl->when_needed);
7658 if (tertiary_reload >= 0)
7660 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7662 gen_reload (third_reloadreg, reloadreg,
7663 rl->opnum, rl->when_needed);
7664 reloadreg = third_reloadreg;
7671 /* Output the last reload insn. */
7676 /* Don't output the last reload if OLD is not the dest of
7677 INSN and is in the src and is clobbered by INSN. */
7678 if (! flag_expensive_optimizations
7680 || !(set = single_set (insn))
7681 || rtx_equal_p (old, SET_DEST (set))
7682 || !reg_mentioned_p (old, SET_SRC (set))
7683 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7684 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7685 gen_reload (old, reloadreg, rl->opnum,
7689 /* Look at all insns we emitted, just to be safe. */
7690 for (p = get_insns (); p; p = NEXT_INSN (p))
7693 rtx pat = PATTERN (p);
7695 /* If this output reload doesn't come from a spill reg,
7696 clear any memory of reloaded copies of the pseudo reg.
7697 If this output reload comes from a spill reg,
7698 reg_has_output_reload will make this do nothing. */
7699 note_stores (p, forget_old_reloads_1, NULL);
7701 if (reg_mentioned_p (rl_reg_rtx, pat))
7703 rtx set = single_set (insn);
7704 if (reload_spill_index[j] < 0
7706 && SET_SRC (set) == rl_reg_rtx)
7708 int src = REGNO (SET_SRC (set));
7710 reload_spill_index[j] = src;
7711 SET_HARD_REG_BIT (reg_is_output_reload, src);
7712 if (find_regno_note (insn, REG_DEAD, src))
7713 SET_HARD_REG_BIT (reg_reloaded_died, src);
7715 if (HARD_REGISTER_P (rl_reg_rtx))
7717 int s = rl->secondary_out_reload;
7718 set = single_set (p);
7719 /* If this reload copies only to the secondary reload
7720 register, the secondary reload does the actual
7722 if (s >= 0 && set == NULL_RTX)
7723 /* We can't tell what function the secondary reload
7724 has and where the actual store to the pseudo is
7725 made; leave new_spill_reg_store alone. */
7728 && SET_SRC (set) == rl_reg_rtx
7729 && SET_DEST (set) == rld[s].reg_rtx)
7731 /* Usually the next instruction will be the
7732 secondary reload insn; if we can confirm
7733 that it is, setting new_spill_reg_store to
7734 that insn will allow an extra optimization. */
7735 rtx s_reg = rld[s].reg_rtx;
7736 rtx_insn *next = NEXT_INSN (p);
7737 rld[s].out = rl->out;
7738 rld[s].out_reg = rl->out_reg;
7739 set = single_set (next);
7740 if (set && SET_SRC (set) == s_reg
7741 && reload_reg_rtx_reaches_end_p (s_reg, s))
7743 SET_HARD_REG_BIT (reg_is_output_reload,
7745 new_spill_reg_store[REGNO (s_reg)] = next;
7748 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7749 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7754 if (rl->when_needed == RELOAD_OTHER)
7756 emit_insn (other_output_reload_insns[rl->opnum]);
7757 other_output_reload_insns[rl->opnum] = get_insns ();
7760 output_reload_insns[rl->opnum] = get_insns ();
7762 if (cfun->can_throw_non_call_exceptions)
7763 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7768 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7769 and has the number J. */
7771 do_input_reload (class insn_chain *chain, struct reload *rl, int j)
7773 rtx_insn *insn = chain->insn;
7774 rtx old = (rl->in && MEM_P (rl->in)
7775 ? rl->in_reg : rl->in);
7776 rtx reg_rtx = rl->reg_rtx;
7782 /* Determine the mode to reload in.
7783 This is very tricky because we have three to choose from.
7784 There is the mode the insn operand wants (rl->inmode).
7785 There is the mode of the reload register RELOADREG.
7786 There is the intrinsic mode of the operand, which we could find
7787 by stripping some SUBREGs.
7788 It turns out that RELOADREG's mode is irrelevant:
7789 we can change that arbitrarily.
7791 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7792 then the reload reg may not support QImode moves, so use SImode.
7793 If foo is in memory due to spilling a pseudo reg, this is safe,
7794 because the QImode value is in the least significant part of a
7795 slot big enough for a SImode. If foo is some other sort of
7796 memory reference, then it is impossible to reload this case,
7797 so previous passes had better make sure this never happens.
7799 Then consider a one-word union which has SImode and one of its
7800 members is a float, being fetched as (SUBREG:SF union:SI).
7801 We must fetch that as SFmode because we could be loading into
7802 a float-only register. In this case OLD's mode is correct.
7804 Consider an immediate integer: it has VOIDmode. Here we need
7805 to get a mode from something else.
7807 In some cases, there is a fourth mode, the operand's
7808 containing mode. If the insn specifies a containing mode for
7809 this operand, it overrides all others.
7811 I am not sure whether the algorithm here is always right,
7812 but it does the right things in those cases. */
7814 mode = GET_MODE (old);
7815 if (mode == VOIDmode)
7818 /* We cannot use gen_lowpart_common since it can do the wrong thing
7819 when REG_RTX has a multi-word mode. Note that REG_RTX must
7820 always be a REG here. */
7821 if (GET_MODE (reg_rtx) != mode)
7822 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7824 reload_reg_rtx_for_input[j] = reg_rtx;
7827 /* AUTO_INC reloads need to be handled even if inherited. We got an
7828 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7829 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7830 && ! rtx_equal_p (reg_rtx, old)
7832 emit_input_reload_insns (chain, rld + j, old, j);
7834 /* When inheriting a wider reload, we have a MEM in rl->in,
7835 e.g. inheriting a SImode output reload for
7836 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7837 if (optimize && reload_inherited[j] && rl->in
7839 && MEM_P (rl->in_reg)
7840 && reload_spill_index[j] >= 0
7841 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7842 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7844 /* If we are reloading a register that was recently stored in with an
7845 output-reload, see if we can prove there was
7846 actually no need to store the old value in it. */
7849 && (reload_inherited[j] || reload_override_in[j])
7852 && spill_reg_store[REGNO (reg_rtx)] != 0
7854 /* There doesn't seem to be any reason to restrict this to pseudos
7855 and doing so loses in the case where we are copying from a
7856 register of the wrong class. */
7857 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7859 /* The insn might have already some references to stackslots
7860 replaced by MEMs, while reload_out_reg still names the
7862 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7863 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7864 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7867 /* Do output reloading for reload RL, which is for the insn described by
7868 CHAIN and has the number J.
7869 ??? At some point we need to support handling output reloads of
7870 JUMP_INSNs or insns that set cc0. */
7872 do_output_reload (class insn_chain *chain, struct reload *rl, int j)
7875 rtx_insn *insn = chain->insn;
7876 /* If this is an output reload that stores something that is
7877 not loaded in this same reload, see if we can eliminate a previous
7879 rtx pseudo = rl->out_reg;
7880 rtx reg_rtx = rl->reg_rtx;
7882 if (rl->out && reg_rtx)
7886 /* Determine the mode to reload in.
7887 See comments above (for input reloading). */
7888 mode = GET_MODE (rl->out);
7889 if (mode == VOIDmode)
7891 /* VOIDmode should never happen for an output. */
7892 if (asm_noperands (PATTERN (insn)) < 0)
7893 /* It's the compiler's fault. */
7894 fatal_insn ("VOIDmode on an output", insn);
7895 error_for_asm (insn, "output operand is constant in %<asm%>");
7896 /* Prevent crash--use something we know is valid. */
7898 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7900 if (GET_MODE (reg_rtx) != mode)
7901 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7903 reload_reg_rtx_for_output[j] = reg_rtx;
7908 && ! rtx_equal_p (rl->in_reg, pseudo)
7909 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7910 && reg_last_reload_reg[REGNO (pseudo)])
7912 int pseudo_no = REGNO (pseudo);
7913 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7915 /* We don't need to test full validity of last_regno for
7916 inherit here; we only want to know if the store actually
7917 matches the pseudo. */
7918 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7919 && reg_reloaded_contents[last_regno] == pseudo_no
7920 && spill_reg_store[last_regno]
7921 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7922 delete_output_reload (insn, j, last_regno, reg_rtx);
7928 || rtx_equal_p (old, reg_rtx))
7931 /* An output operand that dies right away does need a reload,
7932 but need not be copied from it. Show the new location in the
7934 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7935 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7937 XEXP (note, 0) = reg_rtx;
7940 /* Likewise for a SUBREG of an operand that dies. */
7941 else if (GET_CODE (old) == SUBREG
7942 && REG_P (SUBREG_REG (old))
7943 && (note = find_reg_note (insn, REG_UNUSED,
7944 SUBREG_REG (old))) != 0)
7946 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7949 else if (GET_CODE (old) == SCRATCH)
7950 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7951 but we don't want to make an output reload. */
7954 /* If is a JUMP_INSN, we can't support output reloads yet. */
7955 gcc_assert (NONJUMP_INSN_P (insn));
7957 emit_output_reload_insns (chain, rld + j, j);
7960 /* A reload copies values of MODE from register SRC to register DEST.
7961 Return true if it can be treated for inheritance purposes like a
7962 group of reloads, each one reloading a single hard register. The
7963 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7964 occupy the same number of hard registers. */
7967 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7968 int src ATTRIBUTE_UNUSED,
7969 machine_mode mode ATTRIBUTE_UNUSED)
7971 return (REG_CAN_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7972 && REG_CAN_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7975 /* Output insns to reload values in and out of the chosen reload regs. */
7978 emit_reload_insns (class insn_chain *chain)
7980 rtx_insn *insn = chain->insn;
7984 CLEAR_HARD_REG_SET (reg_reloaded_died);
7986 for (j = 0; j < reload_n_operands; j++)
7987 input_reload_insns[j] = input_address_reload_insns[j]
7988 = inpaddr_address_reload_insns[j]
7989 = output_reload_insns[j] = output_address_reload_insns[j]
7990 = outaddr_address_reload_insns[j]
7991 = other_output_reload_insns[j] = 0;
7992 other_input_address_reload_insns = 0;
7993 other_input_reload_insns = 0;
7994 operand_reload_insns = 0;
7995 other_operand_reload_insns = 0;
7997 /* Dump reloads into the dump file. */
8000 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8001 debug_reload_to_stream (dump_file);
8004 for (j = 0; j < n_reloads; j++)
8005 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8009 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8010 new_spill_reg_store[i] = 0;
8013 /* Now output the instructions to copy the data into and out of the
8014 reload registers. Do these in the order that the reloads were reported,
8015 since reloads of base and index registers precede reloads of operands
8016 and the operands may need the base and index registers reloaded. */
8018 for (j = 0; j < n_reloads; j++)
8020 do_input_reload (chain, rld + j, j);
8021 do_output_reload (chain, rld + j, j);
8024 /* Now write all the insns we made for reloads in the order expected by
8025 the allocation functions. Prior to the insn being reloaded, we write
8026 the following reloads:
8028 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8030 RELOAD_OTHER reloads.
8032 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8033 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8034 RELOAD_FOR_INPUT reload for the operand.
8036 RELOAD_FOR_OPADDR_ADDRS reloads.
8038 RELOAD_FOR_OPERAND_ADDRESS reloads.
8040 After the insn being reloaded, we write the following:
8042 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8043 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8044 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8045 reloads for the operand. The RELOAD_OTHER output reloads are
8046 output in descending order by reload number. */
8048 emit_insn_before (other_input_address_reload_insns, insn);
8049 emit_insn_before (other_input_reload_insns, insn);
8051 for (j = 0; j < reload_n_operands; j++)
8053 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8054 emit_insn_before (input_address_reload_insns[j], insn);
8055 emit_insn_before (input_reload_insns[j], insn);
8058 emit_insn_before (other_operand_reload_insns, insn);
8059 emit_insn_before (operand_reload_insns, insn);
8061 for (j = 0; j < reload_n_operands; j++)
8063 rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8064 x = emit_insn_after (output_address_reload_insns[j], x);
8065 x = emit_insn_after (output_reload_insns[j], x);
8066 emit_insn_after (other_output_reload_insns[j], x);
8069 /* For all the spill regs newly reloaded in this instruction,
8070 record what they were reloaded from, so subsequent instructions
8071 can inherit the reloads.
8073 Update spill_reg_store for the reloads of this insn.
8074 Copy the elements that were updated in the loop above. */
8076 for (j = 0; j < n_reloads; j++)
8078 int r = reload_order[j];
8079 int i = reload_spill_index[r];
8081 /* If this is a non-inherited input reload from a pseudo, we must
8082 clear any memory of a previous store to the same pseudo. Only do
8083 something if there will not be an output reload for the pseudo
8085 if (rld[r].in_reg != 0
8086 && ! (reload_inherited[r] || reload_override_in[r]))
8088 rtx reg = rld[r].in_reg;
8090 if (GET_CODE (reg) == SUBREG)
8091 reg = SUBREG_REG (reg);
8094 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8095 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8097 int nregno = REGNO (reg);
8099 if (reg_last_reload_reg[nregno])
8101 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8103 if (reg_reloaded_contents[last_regno] == nregno)
8104 spill_reg_store[last_regno] = 0;
8109 /* I is nonneg if this reload used a register.
8110 If rld[r].reg_rtx is 0, this is an optional reload
8111 that we opted to ignore. */
8113 if (i >= 0 && rld[r].reg_rtx != 0)
8115 int nr = hard_regno_nregs (i, GET_MODE (rld[r].reg_rtx));
8118 /* For a multi register reload, we need to check if all or part
8119 of the value lives to the end. */
8120 for (k = 0; k < nr; k++)
8121 if (reload_reg_reaches_end_p (i + k, r))
8122 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8124 /* Maybe the spill reg contains a copy of reload_out. */
8126 && (REG_P (rld[r].out)
8128 ? REG_P (rld[r].out_reg)
8129 /* The reload value is an auto-modification of
8130 some kind. For PRE_INC, POST_INC, PRE_DEC
8131 and POST_DEC, we record an equivalence
8132 between the reload register and the operand
8133 on the optimistic assumption that we can make
8134 the equivalence hold. reload_as_needed must
8135 then either make it hold or invalidate the
8138 PRE_MODIFY and POST_MODIFY addresses are reloaded
8139 somewhat differently, and allowing them here leads
8141 : (GET_CODE (rld[r].out) != POST_MODIFY
8142 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8146 reg = reload_reg_rtx_for_output[r];
8147 if (reload_reg_rtx_reaches_end_p (reg, r))
8149 machine_mode mode = GET_MODE (reg);
8150 int regno = REGNO (reg);
8151 int nregs = REG_NREGS (reg);
8152 rtx out = (REG_P (rld[r].out)
8156 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8157 int out_regno = REGNO (out);
8158 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8159 : hard_regno_nregs (out_regno, mode));
8162 spill_reg_store[regno] = new_spill_reg_store[regno];
8163 spill_reg_stored_to[regno] = out;
8164 reg_last_reload_reg[out_regno] = reg;
8166 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8167 && nregs == out_nregs
8168 && inherit_piecemeal_p (out_regno, regno, mode));
8170 /* If OUT_REGNO is a hard register, it may occupy more than
8171 one register. If it does, say what is in the
8172 rest of the registers assuming that both registers
8173 agree on how many words the object takes. If not,
8174 invalidate the subsequent registers. */
8176 if (HARD_REGISTER_NUM_P (out_regno))
8177 for (k = 1; k < out_nregs; k++)
8178 reg_last_reload_reg[out_regno + k]
8179 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8181 /* Now do the inverse operation. */
8182 for (k = 0; k < nregs; k++)
8184 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8185 reg_reloaded_contents[regno + k]
8186 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8189 reg_reloaded_insn[regno + k] = insn;
8190 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8194 /* Maybe the spill reg contains a copy of reload_in. Only do
8195 something if there will not be an output reload for
8196 the register being reloaded. */
8197 else if (rld[r].out_reg == 0
8199 && ((REG_P (rld[r].in)
8200 && !HARD_REGISTER_P (rld[r].in)
8201 && !REGNO_REG_SET_P (®_has_output_reload,
8203 || (REG_P (rld[r].in_reg)
8204 && !REGNO_REG_SET_P (®_has_output_reload,
8205 REGNO (rld[r].in_reg))))
8206 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8210 reg = reload_reg_rtx_for_input[r];
8211 if (reload_reg_rtx_reaches_end_p (reg, r))
8221 mode = GET_MODE (reg);
8222 regno = REGNO (reg);
8223 nregs = REG_NREGS (reg);
8224 if (REG_P (rld[r].in)
8225 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8227 else if (REG_P (rld[r].in_reg))
8230 in = XEXP (rld[r].in_reg, 0);
8231 in_regno = REGNO (in);
8233 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8234 : hard_regno_nregs (in_regno, mode));
8236 reg_last_reload_reg[in_regno] = reg;
8238 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8239 && nregs == in_nregs
8240 && inherit_piecemeal_p (regno, in_regno, mode));
8242 if (HARD_REGISTER_NUM_P (in_regno))
8243 for (k = 1; k < in_nregs; k++)
8244 reg_last_reload_reg[in_regno + k]
8245 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8247 /* Unless we inherited this reload, show we haven't
8248 recently done a store.
8249 Previous stores of inherited auto_inc expressions
8250 also have to be discarded. */
8251 if (! reload_inherited[r]
8252 || (rld[r].out && ! rld[r].out_reg))
8253 spill_reg_store[regno] = 0;
8255 for (k = 0; k < nregs; k++)
8257 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8258 reg_reloaded_contents[regno + k]
8259 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8262 reg_reloaded_insn[regno + k] = insn;
8263 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8269 /* The following if-statement was #if 0'd in 1.34 (or before...).
8270 It's reenabled in 1.35 because supposedly nothing else
8271 deals with this problem. */
8273 /* If a register gets output-reloaded from a non-spill register,
8274 that invalidates any previous reloaded copy of it.
8275 But forget_old_reloads_1 won't get to see it, because
8276 it thinks only about the original insn. So invalidate it here.
8277 Also do the same thing for RELOAD_OTHER constraints where the
8278 output is discarded. */
8280 && ((rld[r].out != 0
8281 && (REG_P (rld[r].out)
8282 || (MEM_P (rld[r].out)
8283 && REG_P (rld[r].out_reg))))
8284 || (rld[r].out == 0 && rld[r].out_reg
8285 && REG_P (rld[r].out_reg))))
8287 rtx out = ((rld[r].out && REG_P (rld[r].out))
8288 ? rld[r].out : rld[r].out_reg);
8289 int out_regno = REGNO (out);
8290 machine_mode mode = GET_MODE (out);
8292 /* REG_RTX is now set or clobbered by the main instruction.
8293 As the comment above explains, forget_old_reloads_1 only
8294 sees the original instruction, and there is no guarantee
8295 that the original instruction also clobbered REG_RTX.
8296 For example, if find_reloads sees that the input side of
8297 a matched operand pair dies in this instruction, it may
8298 use the input register as the reload register.
8300 Calling forget_old_reloads_1 is a waste of effort if
8301 REG_RTX is also the output register.
8303 If we know that REG_RTX holds the value of a pseudo
8304 register, the code after the call will record that fact. */
8305 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8306 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8308 if (!HARD_REGISTER_NUM_P (out_regno))
8311 rtx_insn *store_insn = NULL;
8313 reg_last_reload_reg[out_regno] = 0;
8315 /* If we can find a hard register that is stored, record
8316 the storing insn so that we may delete this insn with
8317 delete_output_reload. */
8318 src_reg = reload_reg_rtx_for_output[r];
8322 if (reload_reg_rtx_reaches_end_p (src_reg, r))
8323 store_insn = new_spill_reg_store[REGNO (src_reg)];
8329 /* If this is an optional reload, try to find the
8330 source reg from an input reload. */
8331 rtx set = single_set (insn);
8332 if (set && SET_DEST (set) == rld[r].out)
8336 src_reg = SET_SRC (set);
8338 for (k = 0; k < n_reloads; k++)
8340 if (rld[k].in == src_reg)
8342 src_reg = reload_reg_rtx_for_input[k];
8348 if (src_reg && REG_P (src_reg)
8349 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8351 int src_regno, src_nregs, k;
8354 gcc_assert (GET_MODE (src_reg) == mode);
8355 src_regno = REGNO (src_reg);
8356 src_nregs = hard_regno_nregs (src_regno, mode);
8357 /* The place where to find a death note varies with
8358 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8359 necessarily checked exactly in the code that moves
8360 notes, so just check both locations. */
8361 note = find_regno_note (insn, REG_DEAD, src_regno);
8362 if (! note && store_insn)
8363 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8364 for (k = 0; k < src_nregs; k++)
8366 spill_reg_store[src_regno + k] = store_insn;
8367 spill_reg_stored_to[src_regno + k] = out;
8368 reg_reloaded_contents[src_regno + k] = out_regno;
8369 reg_reloaded_insn[src_regno + k] = store_insn;
8370 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8371 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8372 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8374 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8376 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8378 reg_last_reload_reg[out_regno] = src_reg;
8379 /* We have to set reg_has_output_reload here, or else
8380 forget_old_reloads_1 will clear reg_last_reload_reg
8382 SET_REGNO_REG_SET (®_has_output_reload,
8388 int k, out_nregs = hard_regno_nregs (out_regno, mode);
8390 for (k = 0; k < out_nregs; k++)
8391 reg_last_reload_reg[out_regno + k] = 0;
8395 reg_reloaded_dead |= reg_reloaded_died;
8398 /* Go through the motions to emit INSN and test if it is strictly valid.
8399 Return the emitted insn if valid, else return NULL. */
8402 emit_insn_if_valid_for_reload (rtx pat)
8404 rtx_insn *last = get_last_insn ();
8407 rtx_insn *insn = emit_insn (pat);
8408 code = recog_memoized (insn);
8412 extract_insn (insn);
8413 /* We want constrain operands to treat this insn strictly in its
8414 validity determination, i.e., the way it would after reload has
8416 if (constrain_operands (1, get_enabled_alternatives (insn)))
8420 delete_insns_since (last);
8424 /* Emit code to perform a reload from IN (which may be a reload register) to
8425 OUT (which may also be a reload register). IN or OUT is from operand
8426 OPNUM with reload type TYPE.
8428 Returns first insn emitted. */
8431 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8433 rtx_insn *last = get_last_insn ();
8437 /* If IN is a paradoxical SUBREG, remove it and try to put the
8438 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8439 if (!strip_paradoxical_subreg (&in, &out))
8440 strip_paradoxical_subreg (&out, &in);
8442 /* How to do this reload can get quite tricky. Normally, we are being
8443 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8444 register that didn't get a hard register. In that case we can just
8445 call emit_move_insn.
8447 We can also be asked to reload a PLUS that adds a register or a MEM to
8448 another register, constant or MEM. This can occur during frame pointer
8449 elimination and while reloading addresses. This case is handled by
8450 trying to emit a single insn to perform the add. If it is not valid,
8451 we use a two insn sequence.
8453 Or we can be asked to reload an unary operand that was a fragment of
8454 an addressing mode, into a register. If it isn't recognized as-is,
8455 we try making the unop operand and the reload-register the same:
8456 (set reg:X (unop:X expr:Y))
8457 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8459 Finally, we could be called to handle an 'o' constraint by putting
8460 an address into a register. In that case, we first try to do this
8461 with a named pattern of "reload_load_address". If no such pattern
8462 exists, we just emit a SET insn and hope for the best (it will normally
8463 be valid on machines that use 'o').
8465 This entire process is made complex because reload will never
8466 process the insns we generate here and so we must ensure that
8467 they will fit their constraints and also by the fact that parts of
8468 IN might be being reloaded separately and replaced with spill registers.
8469 Because of this, we are, in some sense, just guessing the right approach
8470 here. The one listed above seems to work.
8472 ??? At some point, this whole thing needs to be rethought. */
8474 if (GET_CODE (in) == PLUS
8475 && (REG_P (XEXP (in, 0))
8476 || GET_CODE (XEXP (in, 0)) == SUBREG
8477 || MEM_P (XEXP (in, 0)))
8478 && (REG_P (XEXP (in, 1))
8479 || GET_CODE (XEXP (in, 1)) == SUBREG
8480 || CONSTANT_P (XEXP (in, 1))
8481 || MEM_P (XEXP (in, 1))))
8483 /* We need to compute the sum of a register or a MEM and another
8484 register, constant, or MEM, and put it into the reload
8485 register. The best possible way of doing this is if the machine
8486 has a three-operand ADD insn that accepts the required operands.
8488 The simplest approach is to try to generate such an insn and see if it
8489 is recognized and matches its constraints. If so, it can be used.
8491 It might be better not to actually emit the insn unless it is valid,
8492 but we need to pass the insn as an operand to `recog' and
8493 `extract_insn' and it is simpler to emit and then delete the insn if
8494 not valid than to dummy things up. */
8498 enum insn_code code;
8500 op0 = find_replacement (&XEXP (in, 0));
8501 op1 = find_replacement (&XEXP (in, 1));
8503 /* Since constraint checking is strict, commutativity won't be
8504 checked, so we need to do that here to avoid spurious failure
8505 if the add instruction is two-address and the second operand
8506 of the add is the same as the reload reg, which is frequently
8507 the case. If the insn would be A = B + A, rearrange it so
8508 it will be A = A + B as constrain_operands expects. */
8510 if (REG_P (XEXP (in, 1))
8511 && REGNO (out) == REGNO (XEXP (in, 1)))
8512 tem = op0, op0 = op1, op1 = tem;
8514 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8515 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8517 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8521 /* If that failed, we must use a conservative two-insn sequence.
8523 Use a move to copy one operand into the reload register. Prefer
8524 to reload a constant, MEM or pseudo since the move patterns can
8525 handle an arbitrary operand. If OP1 is not a constant, MEM or
8526 pseudo and OP1 is not a valid operand for an add instruction, then
8529 After reloading one of the operands into the reload register, add
8530 the reload register to the output register.
8532 If there is another way to do this for a specific machine, a
8533 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8536 code = optab_handler (add_optab, GET_MODE (out));
8538 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8540 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8541 || (code != CODE_FOR_nothing
8542 && !insn_operand_matches (code, 2, op1)))
8543 tem = op0, op0 = op1, op1 = tem;
8545 gen_reload (out, op0, opnum, type);
8547 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8548 This fixes a problem on the 32K where the stack pointer cannot
8549 be used as an operand of an add insn. */
8551 if (rtx_equal_p (op0, op1))
8554 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8557 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8558 set_dst_reg_note (insn, REG_EQUIV, in, out);
8562 /* If that failed, copy the address register to the reload register.
8563 Then add the constant to the reload register. */
8565 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8566 gen_reload (out, op1, opnum, type);
8567 insn = emit_insn (gen_add2_insn (out, op0));
8568 set_dst_reg_note (insn, REG_EQUIV, in, out);
8571 /* If we need a memory location to do the move, do it that way. */
8572 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8573 (REG_P (tem1) && REG_P (tem2)))
8574 && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8575 && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8576 && targetm.secondary_memory_needed (GET_MODE (out),
8577 REGNO_REG_CLASS (REGNO (tem1)),
8578 REGNO_REG_CLASS (REGNO (tem2))))
8580 /* Get the memory to use and rewrite both registers to its mode. */
8581 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8583 if (GET_MODE (loc) != GET_MODE (out))
8584 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8586 if (GET_MODE (loc) != GET_MODE (in))
8587 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8589 gen_reload (loc, in, opnum, type);
8590 gen_reload (out, loc, opnum, type);
8592 else if (REG_P (out) && UNARY_P (in))
8598 op1 = find_replacement (&XEXP (in, 0));
8599 if (op1 != XEXP (in, 0))
8600 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8602 /* First, try a plain SET. */
8603 set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8607 /* If that failed, move the inner operand to the reload
8608 register, and try the same unop with the inner expression
8609 replaced with the reload register. */
8611 if (GET_MODE (op1) != GET_MODE (out))
8612 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8616 gen_reload (out_moded, op1, opnum, type);
8618 rtx temp = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8620 rtx_insn *insn = emit_insn_if_valid_for_reload (temp);
8623 set_unique_reg_note (insn, REG_EQUIV, in);
8627 fatal_insn ("failure trying to reload:", set);
8629 /* If IN is a simple operand, use gen_move_insn. */
8630 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8632 tem = emit_insn (gen_move_insn (out, in));
8633 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8634 mark_jump_label (in, tem, 0);
8637 else if (targetm.have_reload_load_address ())
8638 emit_insn (targetm.gen_reload_load_address (out, in));
8640 /* Otherwise, just write (set OUT IN) and hope for the best. */
8642 emit_insn (gen_rtx_SET (out, in));
8644 /* Return the first insn emitted.
8645 We cannot just return get_last_insn, because there may have
8646 been multiple instructions emitted. Also note that gen_move_insn may
8647 emit more than one insn itself, so we cannot assume that there is one
8648 insn emitted per emit_insn_before call. */
8650 return last ? NEXT_INSN (last) : get_insns ();
8653 /* Delete a previously made output-reload whose result we now believe
8654 is not needed. First we double-check.
8656 INSN is the insn now being processed.
8657 LAST_RELOAD_REG is the hard register number for which we want to delete
8658 the last output reload.
8659 J is the reload-number that originally used REG. The caller has made
8660 certain that reload J doesn't use REG any longer for input.
8661 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8664 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8667 rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8668 rtx reg = spill_reg_stored_to[last_reload_reg];
8671 int n_inherited = 0;
8676 /* It is possible that this reload has been only used to set another reload
8677 we eliminated earlier and thus deleted this instruction too. */
8678 if (output_reload_insn->deleted ())
8681 /* Get the raw pseudo-register referred to. */
8683 while (GET_CODE (reg) == SUBREG)
8684 reg = SUBREG_REG (reg);
8685 substed = reg_equiv_memory_loc (REGNO (reg));
8687 /* This is unsafe if the operand occurs more often in the current
8688 insn than it is inherited. */
8689 for (k = n_reloads - 1; k >= 0; k--)
8691 rtx reg2 = rld[k].in;
8694 if (MEM_P (reg2) || reload_override_in[k])
8695 reg2 = rld[k].in_reg;
8697 if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
8698 reg2 = XEXP (rld[k].in_reg, 0);
8700 while (GET_CODE (reg2) == SUBREG)
8701 reg2 = SUBREG_REG (reg2);
8702 if (rtx_equal_p (reg2, reg))
8704 if (reload_inherited[k] || reload_override_in[k] || k == j)
8710 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8711 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8712 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8715 n_occurrences += count_occurrences (PATTERN (insn),
8716 eliminate_regs (substed, VOIDmode,
8718 for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8720 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8721 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8723 if (n_occurrences > n_inherited)
8726 regno = REGNO (reg);
8727 nregs = REG_NREGS (reg);
8729 /* If the pseudo-reg we are reloading is no longer referenced
8730 anywhere between the store into it and here,
8731 and we're within the same basic block, then the value can only
8732 pass through the reload reg and end up here.
8733 Otherwise, give up--return. */
8734 for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8735 i1 != insn; i1 = NEXT_INSN (i1))
8737 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8739 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8740 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8742 /* If this is USE in front of INSN, we only have to check that
8743 there are no more references than accounted for by inheritance. */
8744 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8746 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8747 i1 = NEXT_INSN (i1);
8749 if (n_occurrences <= n_inherited && i1 == insn)
8755 /* We will be deleting the insn. Remove the spill reg information. */
8756 for (k = hard_regno_nregs (last_reload_reg, GET_MODE (reg)); k-- > 0; )
8758 spill_reg_store[last_reload_reg + k] = 0;
8759 spill_reg_stored_to[last_reload_reg + k] = 0;
8762 /* The caller has already checked that REG dies or is set in INSN.
8763 It has also checked that we are optimizing, and thus some
8764 inaccuracies in the debugging information are acceptable.
8765 So we could just delete output_reload_insn. But in some cases
8766 we can improve the debugging information without sacrificing
8767 optimization - maybe even improving the code: See if the pseudo
8768 reg has been completely replaced with reload regs. If so, delete
8769 the store insn and forget we had a stack slot for the pseudo. */
8770 if (rld[j].out != rld[j].in
8771 && REG_N_DEATHS (REGNO (reg)) == 1
8772 && REG_N_SETS (REGNO (reg)) == 1
8773 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8774 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8778 /* We know that it was used only between here and the beginning of
8779 the current basic block. (We also know that the last use before
8780 INSN was the output reload we are thinking of deleting, but never
8781 mind that.) Search that range; see if any ref remains. */
8782 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8784 rtx set = single_set (i2);
8786 /* Uses which just store in the pseudo don't count,
8787 since if they are the only uses, they are dead. */
8788 if (set != 0 && SET_DEST (set) == reg)
8790 if (LABEL_P (i2) || JUMP_P (i2))
8792 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8793 && reg_mentioned_p (reg, PATTERN (i2)))
8795 /* Some other ref remains; just delete the output reload we
8797 delete_address_reloads (output_reload_insn, insn);
8798 delete_insn (output_reload_insn);
8803 /* Delete the now-dead stores into this pseudo. Note that this
8804 loop also takes care of deleting output_reload_insn. */
8805 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8807 rtx set = single_set (i2);
8809 if (set != 0 && SET_DEST (set) == reg)
8811 delete_address_reloads (i2, insn);
8814 if (LABEL_P (i2) || JUMP_P (i2))
8818 /* For the debugging info, say the pseudo lives in this reload reg. */
8819 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8820 if (ira_conflicts_p)
8821 /* Inform IRA about the change. */
8822 ira_mark_allocation_change (REGNO (reg));
8823 alter_reg (REGNO (reg), -1, false);
8827 delete_address_reloads (output_reload_insn, insn);
8828 delete_insn (output_reload_insn);
8832 /* We are going to delete DEAD_INSN. Recursively delete loads of
8833 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8834 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8836 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
8838 rtx set = single_set (dead_insn);
8840 rtx_insn *prev, *next;
8843 rtx dst = SET_DEST (set);
8845 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8847 /* If we deleted the store from a reloaded post_{in,de}c expression,
8848 we can delete the matching adds. */
8849 prev = PREV_INSN (dead_insn);
8850 next = NEXT_INSN (dead_insn);
8851 if (! prev || ! next)
8853 set = single_set (next);
8854 set2 = single_set (prev);
8856 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8857 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8858 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8860 dst = SET_DEST (set);
8861 if (! rtx_equal_p (dst, SET_DEST (set2))
8862 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8863 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8864 || (INTVAL (XEXP (SET_SRC (set), 1))
8865 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8867 delete_related_insns (prev);
8868 delete_related_insns (next);
8871 /* Subfunction of delete_address_reloads: process registers found in X. */
8873 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
8875 rtx_insn *prev, *i2;
8878 enum rtx_code code = GET_CODE (x);
8882 const char *fmt = GET_RTX_FORMAT (code);
8883 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8886 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8887 else if (fmt[i] == 'E')
8889 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8890 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8897 if (spill_reg_order[REGNO (x)] < 0)
8900 /* Scan backwards for the insn that sets x. This might be a way back due
8902 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8904 code = GET_CODE (prev);
8905 if (code == CODE_LABEL || code == JUMP_INSN)
8909 if (reg_set_p (x, PATTERN (prev)))
8911 if (reg_referenced_p (x, PATTERN (prev)))
8914 if (! prev || INSN_UID (prev) < reload_first_uid)
8916 /* Check that PREV only sets the reload register. */
8917 set = single_set (prev);
8920 dst = SET_DEST (set);
8922 || ! rtx_equal_p (dst, x))
8924 if (! reg_set_p (dst, PATTERN (dead_insn)))
8926 /* Check if DST was used in a later insn -
8927 it might have been inherited. */
8928 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8934 if (reg_referenced_p (dst, PATTERN (i2)))
8936 /* If there is a reference to the register in the current insn,
8937 it might be loaded in a non-inherited reload. If no other
8938 reload uses it, that means the register is set before
8940 if (i2 == current_insn)
8942 for (j = n_reloads - 1; j >= 0; j--)
8943 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8944 || reload_override_in[j] == dst)
8946 for (j = n_reloads - 1; j >= 0; j--)
8947 if (rld[j].in && rld[j].reg_rtx == dst)
8956 /* If DST is still live at CURRENT_INSN, check if it is used for
8957 any reload. Note that even if CURRENT_INSN sets DST, we still
8958 have to check the reloads. */
8959 if (i2 == current_insn)
8961 for (j = n_reloads - 1; j >= 0; j--)
8962 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8963 || reload_override_in[j] == dst)
8965 /* ??? We can't finish the loop here, because dst might be
8966 allocated to a pseudo in this block if no reload in this
8967 block needs any of the classes containing DST - see
8968 spill_hard_reg. There is no easy way to tell this, so we
8969 have to scan till the end of the basic block. */
8971 if (reg_set_p (dst, PATTERN (i2)))
8975 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8976 reg_reloaded_contents[REGNO (dst)] = -1;
8980 /* Output reload-insns to reload VALUE into RELOADREG.
8981 VALUE is an autoincrement or autodecrement RTX whose operand
8982 is a register or memory location;
8983 so reloading involves incrementing that location.
8984 IN is either identical to VALUE, or some cheaper place to reload from.
8986 INC_AMOUNT is the number to increment or decrement by (always positive).
8987 This cannot be deduced from VALUE. */
8990 inc_for_reload (rtx reloadreg, rtx in, rtx value, poly_int64 inc_amount)
8992 /* REG or MEM to be copied and incremented. */
8993 rtx incloc = find_replacement (&XEXP (value, 0));
8994 /* Nonzero if increment after copying. */
8995 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8996 || GET_CODE (value) == POST_MODIFY);
9001 rtx real_in = in == value ? incloc : in;
9003 /* No hard register is equivalent to this register after
9004 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9005 we could inc/dec that register as well (maybe even using it for
9006 the source), but I'm not sure it's worth worrying about. */
9008 reg_last_reload_reg[REGNO (incloc)] = 0;
9010 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9012 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9013 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9017 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9018 inc_amount = -inc_amount;
9020 inc = gen_int_mode (inc_amount, Pmode);
9023 /* If this is post-increment, first copy the location to the reload reg. */
9024 if (post && real_in != reloadreg)
9025 emit_insn (gen_move_insn (reloadreg, real_in));
9029 /* See if we can directly increment INCLOC. Use a method similar to
9030 that in gen_reload. */
9032 last = get_last_insn ();
9033 add_insn = emit_insn (gen_rtx_SET (incloc,
9034 gen_rtx_PLUS (GET_MODE (incloc),
9037 code = recog_memoized (add_insn);
9040 extract_insn (add_insn);
9041 if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9043 /* If this is a pre-increment and we have incremented the value
9044 where it lives, copy the incremented value to RELOADREG to
9045 be used as an address. */
9048 emit_insn (gen_move_insn (reloadreg, incloc));
9052 delete_insns_since (last);
9055 /* If couldn't do the increment directly, must increment in RELOADREG.
9056 The way we do this depends on whether this is pre- or post-increment.
9057 For pre-increment, copy INCLOC to the reload register, increment it
9058 there, then save back. */
9062 if (in != reloadreg)
9063 emit_insn (gen_move_insn (reloadreg, real_in));
9064 emit_insn (gen_add2_insn (reloadreg, inc));
9065 emit_insn (gen_move_insn (incloc, reloadreg));
9070 Because this might be a jump insn or a compare, and because RELOADREG
9071 may not be available after the insn in an input reload, we must do
9072 the incrementation before the insn being reloaded for.
9074 We have already copied IN to RELOADREG. Increment the copy in
9075 RELOADREG, save that back, then decrement RELOADREG so it has
9076 the original value. */
9078 emit_insn (gen_add2_insn (reloadreg, inc));
9079 emit_insn (gen_move_insn (incloc, reloadreg));
9080 if (CONST_INT_P (inc))
9081 emit_insn (gen_add2_insn (reloadreg,
9082 gen_int_mode (-INTVAL (inc),
9083 GET_MODE (reloadreg))));
9085 emit_insn (gen_sub2_insn (reloadreg, inc));
9090 add_auto_inc_notes (rtx_insn *insn, rtx x)
9092 enum rtx_code code = GET_CODE (x);
9096 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9098 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9102 /* Scan all the operand sub-expressions. */
9103 fmt = GET_RTX_FORMAT (code);
9104 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9107 add_auto_inc_notes (insn, XEXP (x, i));
9108 else if (fmt[i] == 'E')
9109 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9110 add_auto_inc_notes (insn, XVECEXP (x, i, j));