1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(x, y) 2
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs[FIRST_PSEUDO_REGISTER];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs[] = FIXED_REGISTERS;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs[FIRST_PSEUDO_REGISTER];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs[FIRST_PSEUDO_REGISTER];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
139 = REG_CLASS_CONTENTS;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size[N_REG_CLASSES];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names[] = REGISTER_NAMES;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
177 /* Maximum cost of moving from a register in one class to a register in
178 another class. Based on REGISTER_MOVE_COST. */
180 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
182 /* Similar, but here we don't have to move if the first index is a subset
183 of the second so in that case the cost is zero. */
185 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
187 /* Similar, but here we don't have to move if the first index is a superset
188 of the second so in that case the cost is zero. */
190 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
192 #ifdef FORBIDDEN_INC_DEC_CLASSES
194 /* These are the classes that regs which are auto-incremented or decremented
197 static int forbidden_inc_dec_class[N_REG_CLASSES];
199 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
202 static char *in_inc_dec;
204 #endif /* FORBIDDEN_INC_DEC_CLASSES */
206 #ifdef CLASS_CANNOT_CHANGE_MODE
208 /* These are the classes containing only registers that can be used in
209 a SUBREG expression that changes the mode of the register in some
210 way that is illegal. */
212 static int class_can_change_mode[N_REG_CLASSES];
214 /* Registers, including pseudos, which change modes in some way that
217 static regset reg_changes_mode;
219 #endif /* CLASS_CANNOT_CHANGE_MODE */
221 #ifdef HAVE_SECONDARY_RELOADS
223 /* Sample MEM values for use by memory_move_secondary_cost. */
225 static rtx top_of_stack[MAX_MACHINE_MODE];
227 #endif /* HAVE_SECONDARY_RELOADS */
229 /* Linked list of reg_info structures allocated for reg_n_info array.
230 Grouping all of the allocated structures together in one lump
231 means only one call to bzero to clear them, rather than n smaller
233 struct reg_info_data {
234 struct reg_info_data *next; /* next set of reg_info structures */
235 size_t min_index; /* minimum index # */
236 size_t max_index; /* maximum index # */
237 char used_p; /* non-zero if this has been used previously */
238 reg_info data[1]; /* beginning of the reg_info data */
241 static struct reg_info_data *reg_info_head;
243 /* No more global register variables may be declared; true once
244 regclass has been initialized. */
246 static int no_global_reg_vars = 0;
249 /* Function called only once to initialize the above data on reg usage.
250 Once this is done, various switches may override. */
257 /* First copy the register information from the initial int form into
260 for (i = 0; i < N_REG_CLASSES; i++)
262 CLEAR_HARD_REG_SET (reg_class_contents[i]);
264 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
265 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
266 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
267 SET_HARD_REG_BIT (reg_class_contents[i], j);
270 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
271 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
272 bzero (global_regs, sizeof global_regs);
274 /* Do any additional initialization regsets may need */
275 INIT_ONCE_REG_SET ();
277 #ifdef REG_ALLOC_ORDER
278 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
279 inv_reg_alloc_order[reg_alloc_order[i]] = i;
283 /* After switches have been processed, which perhaps alter
284 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
289 register unsigned int i, j;
291 /* This macro allows the fixed or call-used registers
292 and the register classes to depend on target flags. */
294 #ifdef CONDITIONAL_REGISTER_USAGE
295 CONDITIONAL_REGISTER_USAGE;
298 /* Compute number of hard regs in each class. */
300 bzero ((char *) reg_class_size, sizeof reg_class_size);
301 for (i = 0; i < N_REG_CLASSES; i++)
302 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
303 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
306 /* Initialize the table of subunions.
307 reg_class_subunion[I][J] gets the largest-numbered reg-class
308 that is contained in the union of classes I and J. */
310 for (i = 0; i < N_REG_CLASSES; i++)
312 for (j = 0; j < N_REG_CLASSES; j++)
315 register /* Declare it register if it's a scalar. */
320 COPY_HARD_REG_SET (c, reg_class_contents[i]);
321 IOR_HARD_REG_SET (c, reg_class_contents[j]);
322 for (k = 0; k < N_REG_CLASSES; k++)
324 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
329 /* keep the largest subclass */ /* SPEE 900308 */
330 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
331 reg_class_contents[(int) reg_class_subunion[i][j]],
333 reg_class_subunion[i][j] = (enum reg_class) k;
340 /* Initialize the table of superunions.
341 reg_class_superunion[I][J] gets the smallest-numbered reg-class
342 containing the union of classes I and J. */
344 for (i = 0; i < N_REG_CLASSES; i++)
346 for (j = 0; j < N_REG_CLASSES; j++)
349 register /* Declare it register if it's a scalar. */
354 COPY_HARD_REG_SET (c, reg_class_contents[i]);
355 IOR_HARD_REG_SET (c, reg_class_contents[j]);
356 for (k = 0; k < N_REG_CLASSES; k++)
357 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
360 reg_class_superunion[i][j] = (enum reg_class) k;
364 /* Initialize the tables of subclasses and superclasses of each reg class.
365 First clear the whole table, then add the elements as they are found. */
367 for (i = 0; i < N_REG_CLASSES; i++)
369 for (j = 0; j < N_REG_CLASSES; j++)
371 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
372 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
376 for (i = 0; i < N_REG_CLASSES; i++)
378 if (i == (int) NO_REGS)
381 for (j = i + 1; j < N_REG_CLASSES; j++)
385 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
389 /* Reg class I is a subclass of J.
390 Add J to the table of superclasses of I. */
391 p = ®_class_superclasses[i][0];
392 while (*p != LIM_REG_CLASSES) p++;
393 *p = (enum reg_class) j;
394 /* Add I to the table of superclasses of J. */
395 p = ®_class_subclasses[j][0];
396 while (*p != LIM_REG_CLASSES) p++;
397 *p = (enum reg_class) i;
401 /* Initialize "constant" tables. */
403 CLEAR_HARD_REG_SET (fixed_reg_set);
404 CLEAR_HARD_REG_SET (call_used_reg_set);
405 CLEAR_HARD_REG_SET (call_fixed_reg_set);
407 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
409 n_non_fixed_regs = 0;
411 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
414 SET_HARD_REG_BIT (fixed_reg_set, i);
418 if (call_used_regs[i])
419 SET_HARD_REG_BIT (call_used_reg_set, i);
420 if (call_fixed_regs[i])
421 SET_HARD_REG_BIT (call_fixed_reg_set, i);
422 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
423 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
426 /* Initialize the move cost table. Find every subset of each class
427 and take the maximum cost of moving any subset to any other. */
429 for (i = 0; i < N_REG_CLASSES; i++)
430 for (j = 0; j < N_REG_CLASSES; j++)
432 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
433 enum reg_class *p1, *p2;
435 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
437 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
439 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
442 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
444 for (p2 = ®_class_subclasses[j][0];
445 *p2 != LIM_REG_CLASSES; p2++)
447 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
450 move_cost[i][j] = cost;
452 if (reg_class_subset_p (i, j))
453 may_move_in_cost[i][j] = 0;
455 may_move_in_cost[i][j] = cost;
457 if (reg_class_subset_p (j, i))
458 may_move_out_cost[i][j] = 0;
460 may_move_out_cost[i][j] = cost;
463 #ifdef CLASS_CANNOT_CHANGE_MODE
466 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
468 for (i = 0; i < N_REG_CLASSES; i++)
470 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
471 class_can_change_mode [i] = 0;
474 class_can_change_mode [i] = 1;
477 #endif /* CLASS_CANNOT_CHANGE_MODE */
480 /* Compute the table of register modes.
481 These values are used to record death information for individual registers
482 (as opposed to a multi-register mode). */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
493 /* If we couldn't find a valid mode, just use the previous mode.
494 ??? One situation in which we need to do this is on the mips where
495 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
496 to use DF mode for the even registers and VOIDmode for the odd
497 (for the cpu models where the odd ones are inaccessible). */
498 if (reg_raw_mode[i] == VOIDmode)
499 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
503 /* Finish initializing the register sets and
504 initialize the register modes. */
509 /* This finishes what was started by init_reg_sets, but couldn't be done
510 until after register usage was specified. */
515 #ifdef HAVE_SECONDARY_RELOADS
517 /* Make some fake stack-frame MEM references for use in
518 memory_move_secondary_cost. */
521 for (i = 0; i < MAX_MACHINE_MODE; i++)
522 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
523 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
528 #ifdef HAVE_SECONDARY_RELOADS
530 /* Compute extra cost of moving registers to/from memory due to reloads.
531 Only needed if secondary reloads are required for memory moves. */
534 memory_move_secondary_cost (mode, class, in)
535 enum machine_mode mode;
536 enum reg_class class;
539 enum reg_class altclass;
540 int partial_cost = 0;
541 /* We need a memory reference to feed to SECONDARY... macros. */
542 /* mem may be unused even if the SECONDARY_ macros are defined. */
543 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
548 #ifdef SECONDARY_INPUT_RELOAD_CLASS
549 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
556 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
557 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
563 if (altclass == NO_REGS)
567 partial_cost = REGISTER_MOVE_COST (altclass, class);
569 partial_cost = REGISTER_MOVE_COST (class, altclass);
571 if (class == altclass)
572 /* This isn't simply a copy-to-temporary situation. Can't guess
573 what it is, so MEMORY_MOVE_COST really ought not to be calling
576 I'm tempted to put in an abort here, but returning this will
577 probably only give poor estimates, which is what we would've
578 had before this code anyways. */
581 /* Check if the secondary reload register will also need a
583 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
587 /* Return a machine mode that is legitimate for hard reg REGNO and large
588 enough to save nregs. If we can't find one, return VOIDmode. */
591 choose_hard_reg_mode (regno, nregs)
592 unsigned int regno ATTRIBUTE_UNUSED;
595 enum machine_mode found_mode = VOIDmode, mode;
597 /* We first look for the largest integer mode that can be validly
598 held in REGNO. If none, we look for the largest floating-point mode.
599 If we still didn't find a valid mode, try CCmode. */
601 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
603 mode = GET_MODE_WIDER_MODE (mode))
604 if (HARD_REGNO_NREGS (regno, mode) == nregs
605 && HARD_REGNO_MODE_OK (regno, mode))
608 if (found_mode != VOIDmode)
611 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
613 mode = GET_MODE_WIDER_MODE (mode))
614 if (HARD_REGNO_NREGS (regno, mode) == nregs
615 && HARD_REGNO_MODE_OK (regno, mode))
618 if (found_mode != VOIDmode)
621 /* Iterate over all of the CCmodes. */
622 for (mode = CCmode; mode < NUM_MACHINE_MODES; ++mode)
623 if (HARD_REGNO_NREGS (regno, mode) == nregs
624 && HARD_REGNO_MODE_OK (regno, mode))
627 /* We can't find a mode valid for this register. */
631 /* Specify the usage characteristics of the register named NAME.
632 It should be a fixed register if FIXED and a
633 call-used register if CALL_USED. */
636 fix_register (name, fixed, call_used)
638 int fixed, call_used;
642 /* Decode the name and update the primary form of
643 the register info. */
645 if ((i = decode_reg_name (name)) >= 0)
647 if ((i == STACK_POINTER_REGNUM
648 #ifdef HARD_FRAME_POINTER_REGNUM
649 || i == HARD_FRAME_POINTER_REGNUM
651 || i == FRAME_POINTER_REGNUM
654 && (fixed == 0 || call_used == 0))
656 static const char * const what_option[2][2] = {
657 { "call-saved", "call-used" },
658 { "no-such-option", "fixed" }};
660 error ("can't use '%s' as a %s register", name,
661 what_option[fixed][call_used]);
665 fixed_regs[i] = fixed;
666 call_used_regs[i] = call_used;
671 warning ("unknown register name: %s", name);
675 /* Mark register number I as global. */
681 if (fixed_regs[i] == 0 && no_global_reg_vars)
682 error ("global register variable follows a function definition");
686 warning ("register used for two global register variables");
690 if (call_used_regs[i] && ! fixed_regs[i])
691 warning ("call-clobbered register used for global register variable");
695 /* If already fixed, nothing else to do. */
699 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
702 SET_HARD_REG_BIT (fixed_reg_set, i);
703 SET_HARD_REG_BIT (call_used_reg_set, i);
704 SET_HARD_REG_BIT (call_fixed_reg_set, i);
707 /* Now the data and code for the `regclass' pass, which happens
708 just before local-alloc. */
710 /* The `costs' struct records the cost of using a hard register of each class
711 and of using memory for each pseudo. We use this data to set up
712 register class preferences. */
716 int cost[N_REG_CLASSES];
720 /* Structure used to record preferrences of given pseudo. */
723 /* (enum reg_class) prefclass is the preferred class. */
726 /* altclass is a register class that we should use for allocating
727 pseudo if no register in the preferred class is available.
728 If no register in this class is available, memory is preferred.
730 It might appear to be more general to have a bitmask of classes here,
731 but since it is recommended that there be a class corresponding to the
732 union of most major pair of classes, that generality is not required. */
736 /* Record the cost of each class for each pseudo. */
738 static struct costs *costs;
740 /* Initialized once, and used to initialize cost values for each insn. */
742 static struct costs init_cost;
744 /* Record preferrences of each pseudo.
745 This is available after `regclass' is run. */
747 static struct reg_pref *reg_pref;
749 /* Allocated buffers for reg_pref. */
751 static struct reg_pref *reg_pref_buffer;
753 /* Account for the fact that insns within a loop are executed very commonly,
754 but don't keep doing this as loops go too deep. */
756 static int loop_cost;
758 static rtx scan_one_insn PARAMS ((rtx, int));
759 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
760 static void dump_regclass PARAMS ((FILE *));
761 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
763 struct costs *, struct reg_pref *));
764 static int copy_cost PARAMS ((rtx, enum machine_mode,
765 enum reg_class, int));
766 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
767 #ifdef FORBIDDEN_INC_DEC_CLASSES
768 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
770 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
772 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
773 This function is sometimes called before the info has been computed.
774 When that happens, just return GENERAL_REGS, which is innocuous. */
777 reg_preferred_class (regno)
782 return (enum reg_class) reg_pref[regno].prefclass;
786 reg_alternate_class (regno)
792 return (enum reg_class) reg_pref[regno].altclass;
795 /* Initialize some global data for this pass. */
802 init_cost.mem_cost = 10000;
803 for (i = 0; i < N_REG_CLASSES; i++)
804 init_cost.cost[i] = 10000;
806 /* This prevents dump_flow_info from losing if called
807 before regclass is run. */
810 /* No more global register variables may be declared. */
811 no_global_reg_vars = 1;
814 /* Dump register costs. */
819 static const char *const reg_class_names[] = REG_CLASS_NAMES;
821 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
823 enum reg_class class;
826 fprintf (dump, " Register %i costs:", i);
827 for (class = 0; class < N_REG_CLASSES; class++)
828 fprintf (dump, " %s:%i", reg_class_names[(int) class],
829 costs[i].cost[class]);
830 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
836 /* Calculate the costs of insn operands. */
839 record_operand_costs (insn, op_costs, reg_pref)
841 struct costs *op_costs;
842 struct reg_pref *reg_pref;
844 const char *constraints[MAX_RECOG_OPERANDS];
845 enum machine_mode modes[MAX_RECOG_OPERANDS];
848 for (i = 0; i < recog_data.n_operands; i++)
850 constraints[i] = recog_data.constraints[i];
851 modes[i] = recog_data.operand_mode[i];
854 /* If we get here, we are set up to record the costs of all the
855 operands for this insn. Start by initializing the costs.
856 Then handle any address registers. Finally record the desired
857 classes for any pseudos, doing it twice if some pair of
858 operands are commutative. */
860 for (i = 0; i < recog_data.n_operands; i++)
862 op_costs[i] = init_cost;
864 if (GET_CODE (recog_data.operand[i]) == SUBREG)
866 rtx inner = SUBREG_REG (recog_data.operand[i]);
867 #ifdef CLASS_CANNOT_CHANGE_MODE
868 if (GET_CODE (inner) == REG
869 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
870 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
872 recog_data.operand[i] = inner;
875 if (GET_CODE (recog_data.operand[i]) == MEM)
876 record_address_regs (XEXP (recog_data.operand[i], 0),
877 BASE_REG_CLASS, loop_cost * 2);
878 else if (constraints[i][0] == 'p')
879 record_address_regs (recog_data.operand[i],
880 BASE_REG_CLASS, loop_cost * 2);
883 /* Check for commutative in a separate loop so everything will
884 have been initialized. We must do this even if one operand
885 is a constant--see addsi3 in m68k.md. */
887 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
888 if (constraints[i][0] == '%')
890 const char *xconstraints[MAX_RECOG_OPERANDS];
893 /* Handle commutative operands by swapping the constraints.
894 We assume the modes are the same. */
896 for (j = 0; j < recog_data.n_operands; j++)
897 xconstraints[j] = constraints[j];
899 xconstraints[i] = constraints[i+1];
900 xconstraints[i+1] = constraints[i];
901 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
902 recog_data.operand, modes,
903 xconstraints, insn, op_costs, reg_pref);
906 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
907 recog_data.operand, modes,
908 constraints, insn, op_costs, reg_pref);
911 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
912 time it would save code to put a certain register in a certain class.
913 PASS, when nonzero, inhibits some optimizations which need only be done
915 Return the last insn processed, so that the scan can be continued from
919 scan_one_insn (insn, pass)
923 enum rtx_code code = GET_CODE (insn);
924 enum rtx_code pat_code;
927 struct costs op_costs[MAX_RECOG_OPERANDS];
929 if (GET_RTX_CLASS (code) != 'i')
932 pat_code = GET_CODE (PATTERN (insn));
934 || pat_code == CLOBBER
935 || pat_code == ASM_INPUT
936 || pat_code == ADDR_VEC
937 || pat_code == ADDR_DIFF_VEC)
940 set = single_set (insn);
943 /* If this insn loads a parameter from its stack slot, then
944 it represents a savings, rather than a cost, if the
945 parameter is stored in memory. Record this fact. */
947 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
948 && GET_CODE (SET_SRC (set)) == MEM
949 && (note = find_reg_note (insn, REG_EQUIV,
951 && GET_CODE (XEXP (note, 0)) == MEM)
953 costs[REGNO (SET_DEST (set))].mem_cost
954 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
957 record_address_regs (XEXP (SET_SRC (set), 0),
958 BASE_REG_CLASS, loop_cost * 2);
962 /* Improve handling of two-address insns such as
963 (set X (ashift CONST Y)) where CONST must be made to
964 match X. Change it into two insns: (set X CONST)
965 (set X (ashift X Y)). If we left this for reloading, it
966 would probably get three insns because X and Y might go
967 in the same place. This prevents X and Y from receiving
970 We can only do this if the modes of operands 0 and 1
971 (which might not be the same) are tieable and we only need
972 do this during our first pass. */
974 if (pass == 0 && optimize
975 && recog_data.n_operands >= 3
976 && recog_data.constraints[1][0] == '0'
977 && recog_data.constraints[1][1] == 0
978 && CONSTANT_P (recog_data.operand[1])
979 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
980 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
981 && GET_CODE (recog_data.operand[0]) == REG
982 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
983 recog_data.operand_mode[1]))
985 rtx previnsn = prev_real_insn (insn);
987 = gen_lowpart (recog_data.operand_mode[1],
988 recog_data.operand[0]);
990 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
992 /* If this insn was the start of a basic block,
993 include the new insn in that block.
994 We need not check for code_label here;
995 while a basic block can start with a code_label,
996 INSN could not be at the beginning of that block. */
997 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1000 for (b = 0; b < n_basic_blocks; b++)
1001 if (insn == BLOCK_HEAD (b))
1002 BLOCK_HEAD (b) = newinsn;
1005 /* This makes one more setting of new insns's dest. */
1006 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1008 *recog_data.operand_loc[1] = recog_data.operand[0];
1009 for (i = recog_data.n_dups - 1; i >= 0; i--)
1010 if (recog_data.dup_num[i] == 1)
1011 *recog_data.dup_loc[i] = recog_data.operand[0];
1013 return PREV_INSN (newinsn);
1016 record_operand_costs (insn, op_costs, reg_pref);
1018 /* Now add the cost for each operand to the total costs for
1021 for (i = 0; i < recog_data.n_operands; i++)
1022 if (GET_CODE (recog_data.operand[i]) == REG
1023 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1025 int regno = REGNO (recog_data.operand[i]);
1026 struct costs *p = &costs[regno], *q = &op_costs[i];
1028 p->mem_cost += q->mem_cost * loop_cost;
1029 for (j = 0; j < N_REG_CLASSES; j++)
1030 p->cost[j] += q->cost[j] * loop_cost;
1036 /* This is a pass of the compiler that scans all instructions
1037 and calculates the preferred class for each pseudo-register.
1038 This information can be accessed later by calling `reg_preferred_class'.
1039 This pass comes just before local register allocation. */
1042 regclass (f, nregs, dump)
1053 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1055 #ifdef CLASS_CANNOT_CHANGE_MODE
1056 reg_changes_mode = BITMAP_XMALLOC();
1059 #ifdef FORBIDDEN_INC_DEC_CLASSES
1061 in_inc_dec = (char *) xmalloc (nregs);
1063 /* Initialize information about which register classes can be used for
1064 pseudos that are auto-incremented or auto-decremented. It would
1065 seem better to put this in init_reg_sets, but we need to be able
1066 to allocate rtx, which we can't do that early. */
1068 for (i = 0; i < N_REG_CLASSES; i++)
1070 rtx r = gen_rtx_REG (VOIDmode, 0);
1071 enum machine_mode m;
1074 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1075 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1079 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1080 m = (enum machine_mode) ((int) m + 1))
1081 if (HARD_REGNO_MODE_OK (j, m))
1085 /* If a register is not directly suitable for an
1086 auto-increment or decrement addressing mode and
1087 requires secondary reloads, disallow its class from
1088 being used in such addresses. */
1091 #ifdef SECONDARY_RELOAD_CLASS
1092 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1095 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1096 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1099 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1100 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1105 && ! auto_inc_dec_reg_p (r, m))
1106 forbidden_inc_dec_class[i] = 1;
1110 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1112 /* Normally we scan the insns once and determine the best class to use for
1113 each register. However, if -fexpensive_optimizations are on, we do so
1114 twice, the second time using the tentative best classes to guide the
1117 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1122 fprintf (dump, "\n\nPass %i\n\n",pass);
1123 /* Zero out our accumulation of the cost of each class for each reg. */
1125 bzero ((char *) costs, nregs * sizeof (struct costs));
1127 #ifdef FORBIDDEN_INC_DEC_CLASSES
1128 bzero (in_inc_dec, nregs);
1131 /* Scan the instructions and record each time it would
1132 save code to put a certain register in a certain class. */
1137 for (insn = f; insn; insn = NEXT_INSN (insn))
1138 insn = scan_one_insn (insn, pass);
1141 for (index = 0; index < n_basic_blocks; index++)
1143 basic_block bb = BASIC_BLOCK (index);
1145 /* Show that an insn inside a loop is likely to be executed three
1146 times more than insns outside a loop. This is much more
1147 aggressive than the assumptions made elsewhere and is being
1148 tried as an experiment. */
1152 loop_cost = 1 << (2 * MIN (bb->loop_depth, 5));
1153 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1155 insn = scan_one_insn (insn, pass);
1156 if (insn == bb->end)
1161 /* Now for each register look at how desirable each class is
1162 and find which class is preferred. Store that in
1163 `prefclass'. Record in `altclass' the largest register
1164 class any of whose registers is better than memory. */
1167 reg_pref = reg_pref_buffer;
1171 dump_regclass (dump);
1172 fprintf (dump,"\n");
1174 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1176 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1177 enum reg_class best = ALL_REGS, alt = NO_REGS;
1178 /* This is an enum reg_class, but we call it an int
1179 to save lots of casts. */
1181 register struct costs *p = &costs[i];
1183 /* In non-optimizing compilation REG_N_REFS is not initialized
1185 if (optimize && !REG_N_REFS (i))
1188 for (class = (int) ALL_REGS - 1; class > 0; class--)
1190 /* Ignore classes that are too small for this operand or
1191 invalid for a operand that was auto-incremented. */
1192 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1193 > reg_class_size[class]
1194 #ifdef FORBIDDEN_INC_DEC_CLASSES
1195 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1197 #ifdef CLASS_CANNOT_CHANGE_MODE
1198 || (REGNO_REG_SET_P (reg_changes_mode, i)
1199 && ! class_can_change_mode [class])
1203 else if (p->cost[class] < best_cost)
1205 best_cost = p->cost[class];
1206 best = (enum reg_class) class;
1208 else if (p->cost[class] == best_cost)
1209 best = reg_class_subunion[(int)best][class];
1212 /* Record the alternate register class; i.e., a class for which
1213 every register in it is better than using memory. If adding a
1214 class would make a smaller class (i.e., no union of just those
1215 classes exists), skip that class. The major unions of classes
1216 should be provided as a register class. Don't do this if we
1217 will be doing it again later. */
1219 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1220 for (class = 0; class < N_REG_CLASSES; class++)
1221 if (p->cost[class] < p->mem_cost
1222 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1223 > reg_class_size[(int) alt])
1224 #ifdef FORBIDDEN_INC_DEC_CLASSES
1225 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1227 #ifdef CLASS_CANNOT_CHANGE_MODE
1228 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1229 && ! class_can_change_mode [class])
1232 alt = reg_class_subunion[(int) alt][class];
1234 /* If we don't add any classes, nothing to try. */
1239 && (reg_pref[i].prefclass != (int) best
1240 || reg_pref[i].altclass != (int) alt))
1242 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1243 fprintf (dump, " Register %i", i);
1244 if (alt == ALL_REGS || best == ALL_REGS)
1245 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1246 else if (alt == NO_REGS)
1247 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1249 fprintf (dump, " pref %s, else %s\n",
1250 reg_class_names[(int) best],
1251 reg_class_names[(int) alt]);
1254 /* We cast to (int) because (char) hits bugs in some compilers. */
1255 reg_pref[i].prefclass = (int) best;
1256 reg_pref[i].altclass = (int) alt;
1260 #ifdef FORBIDDEN_INC_DEC_CLASSES
1263 #ifdef CLASS_CANNOT_CHANGE_MODE
1264 BITMAP_XFREE (reg_changes_mode);
1269 /* Record the cost of using memory or registers of various classes for
1270 the operands in INSN.
1272 N_ALTS is the number of alternatives.
1274 N_OPS is the number of operands.
1276 OPS is an array of the operands.
1278 MODES are the modes of the operands, in case any are VOIDmode.
1280 CONSTRAINTS are the constraints to use for the operands. This array
1281 is modified by this procedure.
1283 This procedure works alternative by alternative. For each alternative
1284 we assume that we will be able to allocate all pseudos to their ideal
1285 register class and calculate the cost of using that alternative. Then
1286 we compute for each operand that is a pseudo-register, the cost of
1287 having the pseudo allocated to each register class and using it in that
1288 alternative. To this cost is added the cost of the alternative.
1290 The cost of each class for this insn is its lowest cost among all the
1294 record_reg_classes (n_alts, n_ops, ops, modes,
1295 constraints, insn, op_costs, reg_pref)
1299 enum machine_mode *modes;
1300 const char **constraints;
1302 struct costs *op_costs;
1303 struct reg_pref *reg_pref;
1309 /* Process each alternative, each time minimizing an operand's cost with
1310 the cost for each operand in that alternative. */
1312 for (alt = 0; alt < n_alts; alt++)
1314 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1317 enum reg_class classes[MAX_RECOG_OPERANDS];
1318 int allows_mem[MAX_RECOG_OPERANDS];
1321 for (i = 0; i < n_ops; i++)
1323 const char *p = constraints[i];
1325 enum machine_mode mode = modes[i];
1326 int allows_addr = 0;
1330 /* Initially show we know nothing about the register class. */
1331 classes[i] = NO_REGS;
1334 /* If this operand has no constraints at all, we can conclude
1335 nothing about it since anything is valid. */
1339 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1340 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1345 /* If this alternative is only relevant when this operand
1346 matches a previous operand, we do different things depending
1347 on whether this operand is a pseudo-reg or not. We must process
1348 any modifiers for the operand before we can make this test. */
1350 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1353 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1355 /* Copy class and whether memory is allowed from the matching
1356 alternative. Then perform any needed cost computations
1357 and/or adjustments. */
1359 classes[i] = classes[j];
1360 allows_mem[i] = allows_mem[j];
1362 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1364 /* If this matches the other operand, we have no added
1366 if (rtx_equal_p (ops[j], op))
1369 /* If we can put the other operand into a register, add to
1370 the cost of this alternative the cost to copy this
1371 operand to the register used for the other operand. */
1373 else if (classes[j] != NO_REGS)
1374 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1376 else if (GET_CODE (ops[j]) != REG
1377 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1379 /* This op is a pseudo but the one it matches is not. */
1381 /* If we can't put the other operand into a register, this
1382 alternative can't be used. */
1384 if (classes[j] == NO_REGS)
1387 /* Otherwise, add to the cost of this alternative the cost
1388 to copy the other operand to the register used for this
1392 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1396 /* The costs of this operand are not the same as the other
1397 operand since move costs are not symmetric. Moreover,
1398 if we cannot tie them, this alternative needs to do a
1399 copy, which is one instruction. */
1401 struct costs *pp = &this_op_costs[i];
1403 for (class = 0; class < N_REG_CLASSES; class++)
1405 = ((recog_data.operand_type[i] != OP_OUT
1406 ? may_move_in_cost[class][(int) classes[i]]
1408 + (recog_data.operand_type[i] != OP_IN
1409 ? may_move_out_cost[(int) classes[i]][class]
1412 /* If the alternative actually allows memory, make things
1413 a bit cheaper since we won't need an extra insn to
1417 = ((recog_data.operand_type[i] != OP_IN
1418 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1420 + (recog_data.operand_type[i] != OP_OUT
1421 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1422 : 0) - allows_mem[i]);
1424 /* If we have assigned a class to this register in our
1425 first pass, add a cost to this alternative corresponding
1426 to what we would add if this register were not in the
1427 appropriate class. */
1431 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1432 [(int) classes[i]]);
1434 if (REGNO (ops[i]) != REGNO (ops[j])
1435 && ! find_reg_note (insn, REG_DEAD, op))
1438 /* This is in place of ordinary cost computation
1439 for this operand, so skip to the end of the
1440 alternative (should be just one character). */
1441 while (*p && *p++ != ',')
1449 /* Scan all the constraint letters. See if the operand matches
1450 any of the constraints. Collect the valid register classes
1451 and see if this operand accepts memory. */
1453 while (*p && (c = *p++) != ',')
1457 /* Ignore the next letter for this pass. */
1463 case '!': case '#': case '&':
1464 case '0': case '1': case '2': case '3': case '4':
1465 case '5': case '6': case '7': case '8': case '9':
1470 win = address_operand (op, GET_MODE (op));
1471 /* We know this operand is an address, so we want it to be
1472 allocated to a register that can be the base of an
1473 address, ie BASE_REG_CLASS. */
1475 = reg_class_subunion[(int) classes[i]]
1476 [(int) BASE_REG_CLASS];
1479 case 'm': case 'o': case 'V':
1480 /* It doesn't seem worth distinguishing between offsettable
1481 and non-offsettable addresses here. */
1483 if (GET_CODE (op) == MEM)
1488 if (GET_CODE (op) == MEM
1489 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1490 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1495 if (GET_CODE (op) == MEM
1496 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1497 || GET_CODE (XEXP (op, 0)) == POST_INC))
1502 #ifndef REAL_ARITHMETIC
1503 /* Match any floating double constant, but only if
1504 we can examine the bits of it reliably. */
1505 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1506 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1507 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1510 if (GET_CODE (op) == CONST_DOUBLE)
1515 if (GET_CODE (op) == CONST_DOUBLE)
1521 if (GET_CODE (op) == CONST_DOUBLE
1522 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1527 if (GET_CODE (op) == CONST_INT
1528 || (GET_CODE (op) == CONST_DOUBLE
1529 && GET_MODE (op) == VOIDmode))
1533 #ifdef LEGITIMATE_PIC_OPERAND_P
1534 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1541 if (GET_CODE (op) == CONST_INT
1542 || (GET_CODE (op) == CONST_DOUBLE
1543 && GET_MODE (op) == VOIDmode))
1555 if (GET_CODE (op) == CONST_INT
1556 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1565 if (GET_CODE (op) == MEM
1567 #ifdef LEGITIMATE_PIC_OPERAND_P
1568 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1575 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1579 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1581 = reg_class_subunion[(int) classes[i]]
1582 [(int) REG_CLASS_FROM_LETTER (c)];
1583 #ifdef EXTRA_CONSTRAINT
1584 else if (EXTRA_CONSTRAINT (op, c))
1592 /* How we account for this operand now depends on whether it is a
1593 pseudo register or not. If it is, we first check if any
1594 register classes are valid. If not, we ignore this alternative,
1595 since we want to assume that all pseudos get allocated for
1596 register preferencing. If some register class is valid, compute
1597 the costs of moving the pseudo into that class. */
1599 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1601 if (classes[i] == NO_REGS)
1603 /* We must always fail if the operand is a REG, but
1604 we did not find a suitable class.
1606 Otherwise we may perform an uninitialized read
1607 from this_op_costs after the `continue' statement
1613 struct costs *pp = &this_op_costs[i];
1615 for (class = 0; class < N_REG_CLASSES; class++)
1617 = ((recog_data.operand_type[i] != OP_OUT
1618 ? may_move_in_cost[class][(int) classes[i]]
1620 + (recog_data.operand_type[i] != OP_IN
1621 ? may_move_out_cost[(int) classes[i]][class]
1624 /* If the alternative actually allows memory, make things
1625 a bit cheaper since we won't need an extra insn to
1629 = ((recog_data.operand_type[i] != OP_IN
1630 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1632 + (recog_data.operand_type[i] != OP_OUT
1633 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1634 : 0) - allows_mem[i]);
1636 /* If we have assigned a class to this register in our
1637 first pass, add a cost to this alternative corresponding
1638 to what we would add if this register were not in the
1639 appropriate class. */
1643 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1644 [(int) classes[i]]);
1648 /* Otherwise, if this alternative wins, either because we
1649 have already determined that or if we have a hard register of
1650 the proper class, there is no cost for this alternative. */
1653 || (GET_CODE (op) == REG
1654 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1657 /* If registers are valid, the cost of this alternative includes
1658 copying the object to and/or from a register. */
1660 else if (classes[i] != NO_REGS)
1662 if (recog_data.operand_type[i] != OP_OUT)
1663 alt_cost += copy_cost (op, mode, classes[i], 1);
1665 if (recog_data.operand_type[i] != OP_IN)
1666 alt_cost += copy_cost (op, mode, classes[i], 0);
1669 /* The only other way this alternative can be used is if this is a
1670 constant that could be placed into memory. */
1672 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1673 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1681 /* Finally, update the costs with the information we've calculated
1682 about this alternative. */
1684 for (i = 0; i < n_ops; i++)
1685 if (GET_CODE (ops[i]) == REG
1686 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1688 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1689 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1691 pp->mem_cost = MIN (pp->mem_cost,
1692 (qq->mem_cost + alt_cost) * scale);
1694 for (class = 0; class < N_REG_CLASSES; class++)
1695 pp->cost[class] = MIN (pp->cost[class],
1696 (qq->cost[class] + alt_cost) * scale);
1700 /* If this insn is a single set copying operand 1 to operand 0
1701 and one operand is a pseudo with the other a hard reg or a pseudo
1702 that prefers a register that is in its own register class then
1703 we may want to adjust the cost of that register class to -1.
1705 Avoid the adjustment if the source does not die to avoid stressing of
1706 register allocator by preferrencing two coliding registers into single
1709 Also avoid the adjustment if a copy between registers of the class
1710 is expensive (ten times the cost of a default copy is considered
1711 arbitrarily expensive). This avoids losing when the preferred class
1712 is very expensive as the source of a copy instruction. */
1714 if ((set = single_set (insn)) != 0
1715 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1716 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1717 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1718 for (i = 0; i <= 1; i++)
1719 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1721 unsigned int regno = REGNO (ops[!i]);
1722 enum machine_mode mode = GET_MODE (ops[!i]);
1726 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1728 enum reg_class pref = reg_pref[regno].prefclass;
1730 if ((reg_class_size[(unsigned char) pref]
1731 == CLASS_MAX_NREGS (pref, mode))
1732 && REGISTER_MOVE_COST (pref, pref) < 10 * 2)
1733 op_costs[i].cost[(unsigned char) pref] = -1;
1735 else if (regno < FIRST_PSEUDO_REGISTER)
1736 for (class = 0; class < N_REG_CLASSES; class++)
1737 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1738 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1740 if (reg_class_size[class] == 1)
1741 op_costs[i].cost[class] = -1;
1744 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1746 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1751 if (nr == HARD_REGNO_NREGS (regno,mode))
1752 op_costs[i].cost[class] = -1;
1758 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1759 TO_P is zero) a register of class CLASS in mode MODE.
1761 X must not be a pseudo. */
1764 copy_cost (x, mode, class, to_p)
1766 enum machine_mode mode ATTRIBUTE_UNUSED;
1767 enum reg_class class;
1768 int to_p ATTRIBUTE_UNUSED;
1770 #ifdef HAVE_SECONDARY_RELOADS
1771 enum reg_class secondary_class = NO_REGS;
1774 /* If X is a SCRATCH, there is actually nothing to move since we are
1775 assuming optimal allocation. */
1777 if (GET_CODE (x) == SCRATCH)
1780 /* Get the class we will actually use for a reload. */
1781 class = PREFERRED_RELOAD_CLASS (x, class);
1783 #ifdef HAVE_SECONDARY_RELOADS
1784 /* If we need a secondary reload (we assume here that we are using
1785 the secondary reload as an intermediate, not a scratch register), the
1786 cost is that to load the input into the intermediate register, then
1787 to copy them. We use a special value of TO_P to avoid recursion. */
1789 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1791 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1794 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1796 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1799 if (secondary_class != NO_REGS)
1800 return (move_cost[(int) secondary_class][(int) class]
1801 + copy_cost (x, mode, secondary_class, 2));
1802 #endif /* HAVE_SECONDARY_RELOADS */
1804 /* For memory, use the memory move cost, for (hard) registers, use the
1805 cost to move between the register classes, and use 2 for everything
1806 else (constants). */
1808 if (GET_CODE (x) == MEM || class == NO_REGS)
1809 return MEMORY_MOVE_COST (mode, class, to_p);
1811 else if (GET_CODE (x) == REG)
1812 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1815 /* If this is a constant, we may eventually want to call rtx_cost here. */
1819 /* Record the pseudo registers we must reload into hard registers
1820 in a subexpression of a memory address, X.
1822 CLASS is the class that the register needs to be in and is either
1823 BASE_REG_CLASS or INDEX_REG_CLASS.
1825 SCALE is twice the amount to multiply the cost by (it is twice so we
1826 can represent half-cost adjustments). */
1829 record_address_regs (x, class, scale)
1831 enum reg_class class;
1834 register enum rtx_code code = GET_CODE (x);
1847 /* When we have an address that is a sum,
1848 we must determine whether registers are "base" or "index" regs.
1849 If there is a sum of two registers, we must choose one to be
1850 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1851 to make a good choice most of the time. We only need to do this
1852 on machines that can have two registers in an address and where
1853 the base and index register classes are different.
1855 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1856 that seems bogus since it should only be set when we are sure
1857 the register is being used as a pointer. */
1860 rtx arg0 = XEXP (x, 0);
1861 rtx arg1 = XEXP (x, 1);
1862 register enum rtx_code code0 = GET_CODE (arg0);
1863 register enum rtx_code code1 = GET_CODE (arg1);
1865 /* Look inside subregs. */
1866 if (code0 == SUBREG)
1867 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1868 if (code1 == SUBREG)
1869 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1871 /* If this machine only allows one register per address, it must
1872 be in the first operand. */
1874 if (MAX_REGS_PER_ADDRESS == 1)
1875 record_address_regs (arg0, class, scale);
1877 /* If index and base registers are the same on this machine, just
1878 record registers in any non-constant operands. We assume here,
1879 as well as in the tests below, that all addresses are in
1882 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1884 record_address_regs (arg0, class, scale);
1885 if (! CONSTANT_P (arg1))
1886 record_address_regs (arg1, class, scale);
1889 /* If the second operand is a constant integer, it doesn't change
1890 what class the first operand must be. */
1892 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1893 record_address_regs (arg0, class, scale);
1895 /* If the second operand is a symbolic constant, the first operand
1896 must be an index register. */
1898 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1899 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1901 /* If both operands are registers but one is already a hard register
1902 of index or base class, give the other the class that the hard
1905 #ifdef REG_OK_FOR_BASE_P
1906 else if (code0 == REG && code1 == REG
1907 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1908 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1909 record_address_regs (arg1,
1910 REG_OK_FOR_BASE_P (arg0)
1911 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1913 else if (code0 == REG && code1 == REG
1914 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1915 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1916 record_address_regs (arg0,
1917 REG_OK_FOR_BASE_P (arg1)
1918 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1922 /* If one operand is known to be a pointer, it must be the base
1923 with the other operand the index. Likewise if the other operand
1926 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1929 record_address_regs (arg0, BASE_REG_CLASS, scale);
1930 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1932 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1935 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1936 record_address_regs (arg1, BASE_REG_CLASS, scale);
1939 /* Otherwise, count equal chances that each might be a base
1940 or index register. This case should be rare. */
1944 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1945 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1946 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1947 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1952 /* Double the importance of a pseudo register that is incremented
1953 or decremented, since it would take two extra insns
1954 if it ends up in the wrong place. */
1957 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
1958 if (REG_P (XEXP (XEXP (x, 1), 1)))
1959 record_address_regs (XEXP (XEXP (x, 1), 1),
1960 INDEX_REG_CLASS, 2 * scale);
1967 /* Double the importance of a pseudo register that is incremented
1968 or decremented, since it would take two extra insns
1969 if it ends up in the wrong place. If the operand is a pseudo,
1970 show it is being used in an INC_DEC context. */
1972 #ifdef FORBIDDEN_INC_DEC_CLASSES
1973 if (GET_CODE (XEXP (x, 0)) == REG
1974 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1975 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1978 record_address_regs (XEXP (x, 0), class, 2 * scale);
1983 register struct costs *pp = &costs[REGNO (x)];
1986 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1988 for (i = 0; i < N_REG_CLASSES; i++)
1989 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1995 register const char *fmt = GET_RTX_FORMAT (code);
1997 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1999 record_address_regs (XEXP (x, i), class, scale);
2004 #ifdef FORBIDDEN_INC_DEC_CLASSES
2006 /* Return 1 if REG is valid as an auto-increment memory reference
2007 to an object of MODE. */
2010 auto_inc_dec_reg_p (reg, mode)
2012 enum machine_mode mode;
2014 if (HAVE_POST_INCREMENT
2015 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2018 if (HAVE_POST_DECREMENT
2019 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2022 if (HAVE_PRE_INCREMENT
2023 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2026 if (HAVE_PRE_DECREMENT
2027 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2034 static short *renumber;
2035 static size_t regno_allocated;
2036 static unsigned int reg_n_max;
2038 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2039 reg_scan and flow_analysis that are indexed by the register number. If
2040 NEW_P is non zero, initialize all of the registers, otherwise only
2041 initialize the new registers allocated. The same table is kept from
2042 function to function, only reallocating it when we need more room. If
2043 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2046 allocate_reg_info (num_regs, new_p, renumber_p)
2052 size_t size_renumber;
2053 size_t min = (new_p) ? 0 : reg_n_max;
2054 struct reg_info_data *reg_data;
2056 if (num_regs > regno_allocated)
2058 size_t old_allocated = regno_allocated;
2060 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2061 size_renumber = regno_allocated * sizeof (short);
2065 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2066 renumber = (short *) xmalloc (size_renumber);
2067 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2068 * sizeof (struct reg_pref));
2073 VARRAY_GROW (reg_n_info, regno_allocated);
2075 if (new_p) /* if we're zapping everything, no need to realloc */
2077 free ((char *)renumber);
2078 free ((char *)reg_pref);
2079 renumber = (short *) xmalloc (size_renumber);
2080 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2081 * sizeof (struct reg_pref));
2086 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2087 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2089 * sizeof (struct reg_pref));
2093 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2094 + sizeof (struct reg_info_data) - sizeof (reg_info);
2095 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2096 reg_data->min_index = old_allocated;
2097 reg_data->max_index = regno_allocated - 1;
2098 reg_data->next = reg_info_head;
2099 reg_info_head = reg_data;
2102 reg_n_max = num_regs;
2105 /* Loop through each of the segments allocated for the actual
2106 reg_info pages, and set up the pointers, zero the pages, etc. */
2107 for (reg_data = reg_info_head;
2108 reg_data && reg_data->max_index >= min;
2109 reg_data = reg_data->next)
2111 size_t min_index = reg_data->min_index;
2112 size_t max_index = reg_data->max_index;
2113 size_t max = MIN (max_index, num_regs);
2114 size_t local_min = min - min_index;
2117 if (reg_data->min_index > num_regs)
2120 if (min < min_index)
2122 if (!reg_data->used_p) /* page just allocated with calloc */
2123 reg_data->used_p = 1; /* no need to zero */
2125 bzero ((char *) ®_data->data[local_min],
2126 sizeof (reg_info) * (max - min_index - local_min + 1));
2128 for (i = min_index+local_min; i <= max; i++)
2130 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2131 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2133 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2134 reg_pref_buffer[i].altclass = (char) NO_REGS;
2139 /* If {pref,alt}class have already been allocated, update the pointers to
2140 the newly realloced ones. */
2142 reg_pref = reg_pref_buffer;
2145 reg_renumber = renumber;
2147 /* Tell the regset code about the new number of registers */
2148 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2151 /* Free up the space allocated by allocate_reg_info. */
2157 struct reg_info_data *reg_data;
2158 struct reg_info_data *reg_next;
2160 VARRAY_FREE (reg_n_info);
2161 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2163 reg_next = reg_data->next;
2164 free ((char *)reg_data);
2167 free (reg_pref_buffer);
2168 reg_pref_buffer = (struct reg_pref *)0;
2169 reg_info_head = (struct reg_info_data *)0;
2170 renumber = (short *)0;
2172 regno_allocated = 0;
2176 /* This is the `regscan' pass of the compiler, run just before cse
2177 and again just before loop.
2179 It finds the first and last use of each pseudo-register
2180 and records them in the vectors regno_first_uid, regno_last_uid
2181 and counts the number of sets in the vector reg_n_sets.
2183 REPEAT is nonzero the second time this is called. */
2185 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2186 Always at least 3, since the combiner could put that many together
2187 and we want this to remain correct for all the remaining passes. */
2192 reg_scan (f, nregs, repeat)
2195 int repeat ATTRIBUTE_UNUSED;
2199 allocate_reg_info (nregs, TRUE, FALSE);
2202 for (insn = f; insn; insn = NEXT_INSN (insn))
2203 if (GET_CODE (insn) == INSN
2204 || GET_CODE (insn) == CALL_INSN
2205 || GET_CODE (insn) == JUMP_INSN)
2207 if (GET_CODE (PATTERN (insn)) == PARALLEL
2208 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2209 max_parallel = XVECLEN (PATTERN (insn), 0);
2210 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2212 if (REG_NOTES (insn))
2213 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2217 /* Update 'regscan' information by looking at the insns
2218 from FIRST to LAST. Some new REGs have been created,
2219 and any REG with number greater than OLD_MAX_REGNO is
2220 such a REG. We only update information for those. */
2223 reg_scan_update (first, last, old_max_regno)
2226 unsigned int old_max_regno;
2230 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2232 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2233 if (GET_CODE (insn) == INSN
2234 || GET_CODE (insn) == CALL_INSN
2235 || GET_CODE (insn) == JUMP_INSN)
2237 if (GET_CODE (PATTERN (insn)) == PARALLEL
2238 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2239 max_parallel = XVECLEN (PATTERN (insn), 0);
2240 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2242 if (REG_NOTES (insn))
2243 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2247 /* X is the expression to scan. INSN is the insn it appears in.
2248 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2249 We should only record information for REGs with numbers
2250 greater than or equal to MIN_REGNO. */
2253 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2257 unsigned int min_regno;
2259 register enum rtx_code code;
2263 code = GET_CODE (x);
2279 unsigned int regno = REGNO (x);
2281 if (regno >= min_regno)
2283 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2285 REGNO_LAST_UID (regno) = INSN_UID (insn);
2286 if (REGNO_FIRST_UID (regno) == 0)
2287 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2294 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2296 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2301 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2305 /* Count a set of the destination if it is a register. */
2306 for (dest = SET_DEST (x);
2307 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2308 || GET_CODE (dest) == ZERO_EXTEND;
2309 dest = XEXP (dest, 0))
2312 if (GET_CODE (dest) == REG
2313 && REGNO (dest) >= min_regno)
2314 REG_N_SETS (REGNO (dest))++;
2316 /* If this is setting a pseudo from another pseudo or the sum of a
2317 pseudo and a constant integer and the other pseudo is known to be
2318 a pointer, set the destination to be a pointer as well.
2320 Likewise if it is setting the destination from an address or from a
2321 value equivalent to an address or to the sum of an address and
2324 But don't do any of this if the pseudo corresponds to a user
2325 variable since it should have already been set as a pointer based
2328 if (GET_CODE (SET_DEST (x)) == REG
2329 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2330 && REGNO (SET_DEST (x)) >= min_regno
2331 /* If the destination pseudo is set more than once, then other
2332 sets might not be to a pointer value (consider access to a
2333 union in two threads of control in the presense of global
2334 optimizations). So only set REGNO_POINTER_FLAG on the destination
2335 pseudo if this is the only set of that pseudo. */
2336 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2337 && ! REG_USERVAR_P (SET_DEST (x))
2338 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2339 && ((GET_CODE (SET_SRC (x)) == REG
2340 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2341 || ((GET_CODE (SET_SRC (x)) == PLUS
2342 || GET_CODE (SET_SRC (x)) == LO_SUM)
2343 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2344 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2345 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2346 || GET_CODE (SET_SRC (x)) == CONST
2347 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2348 || GET_CODE (SET_SRC (x)) == LABEL_REF
2349 || (GET_CODE (SET_SRC (x)) == HIGH
2350 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2351 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2352 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2353 || ((GET_CODE (SET_SRC (x)) == PLUS
2354 || GET_CODE (SET_SRC (x)) == LO_SUM)
2355 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2356 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2357 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2358 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2359 && (GET_CODE (XEXP (note, 0)) == CONST
2360 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2361 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2362 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2364 /* ... fall through ... */
2368 register const char *fmt = GET_RTX_FORMAT (code);
2370 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2373 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2374 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2377 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2378 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2385 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2389 reg_class_subset_p (c1, c2)
2390 register enum reg_class c1;
2391 register enum reg_class c2;
2393 if (c1 == c2) return 1;
2398 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2399 reg_class_contents[(int)c2],
2404 /* Return nonzero if there is a register that is in both C1 and C2. */
2407 reg_classes_intersect_p (c1, c2)
2408 register enum reg_class c1;
2409 register enum reg_class c2;
2416 if (c1 == c2) return 1;
2418 if (c1 == ALL_REGS || c2 == ALL_REGS)
2421 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2422 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2424 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2431 /* Release any memory allocated by register sets. */
2434 regset_release_memory ()
2436 bitmap_release_memory ();