1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
32 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 #include "insn-config.h"
45 #ifndef REGISTER_MOVE_COST
46 #define REGISTER_MOVE_COST(m, x, y) 2
49 static void init_reg_sets_1 PARAMS ((void));
50 static void init_reg_modes PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs[FIRST_PSEUDO_REGISTER];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set;
75 /* Data for initializing the above. */
77 static char initial_fixed_regs[] = FIXED_REGISTERS;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs[FIRST_PSEUDO_REGISTER];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set;
94 /* Data for initializing the above. */
96 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
98 /* Indexed by hard register number, contains 1 for registers that are
99 fixed use or call used registers that cannot hold quantities across
100 calls even if we are willing to save and restore them. call fixed
101 registers are a subset of call used registers. */
103 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
105 /* The same info as a HARD_REG_SET. */
107 HARD_REG_SET call_fixed_reg_set;
109 /* Number of non-fixed registers. */
111 int n_non_fixed_regs;
113 /* Indexed by hard register number, contains 1 for registers
114 that are being used for global register decls.
115 These must be exempt from ordinary flow analysis
116 and are also considered fixed. */
118 char global_regs[FIRST_PSEUDO_REGISTER];
120 /* Contains 1 for registers that are set or clobbered by calls. */
121 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
122 for someone's bright idea to have call_used_regs strictly include
123 fixed_regs. Which leaves us guessing as to the set of fixed_regs
124 that are actually preserved. We know for sure that those associated
125 with the local stack frame are safe, but scant others. */
127 HARD_REG_SET regs_invalidated_by_call;
129 /* Table of register numbers in the order in which to try to use them. */
130 #ifdef REG_ALLOC_ORDER
131 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
133 /* The inverse of reg_alloc_order. */
134 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
137 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
139 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
141 /* The same information, but as an array of unsigned ints. We copy from
142 these unsigned ints to the table above. We do this so the tm.h files
143 do not have to be aware of the wordsize for machines with <= 64 regs. */
146 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
148 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
149 = REG_CLASS_CONTENTS;
151 /* For each reg class, number of regs it contains. */
153 unsigned int reg_class_size[N_REG_CLASSES];
155 /* For each reg class, table listing all the containing classes. */
157 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
159 /* For each reg class, table listing all the classes contained in it. */
161 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
163 /* For each pair of reg classes,
164 a largest reg class contained in their union. */
166 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
168 /* For each pair of reg classes,
169 the smallest reg class containing their union. */
171 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
173 /* Array containing all of the register names. Unless
174 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
176 #ifdef DEBUG_REGISTER_NAMES
177 const char * reg_names[] = REGISTER_NAMES;
180 /* For each hard register, the widest mode object that it can contain.
181 This will be a MODE_INT mode if the register can hold integers. Otherwise
182 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
185 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
187 /* 1 if class does contain register of given mode. */
189 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
191 /* Maximum cost of moving from a register in one class to a register in
192 another class. Based on REGISTER_MOVE_COST. */
194 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
196 /* Similar, but here we don't have to move if the first index is a subset
197 of the second so in that case the cost is zero. */
199 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
201 /* Similar, but here we don't have to move if the first index is a superset
202 of the second so in that case the cost is zero. */
204 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
206 #ifdef FORBIDDEN_INC_DEC_CLASSES
208 /* These are the classes that regs which are auto-incremented or decremented
211 static int forbidden_inc_dec_class[N_REG_CLASSES];
213 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
216 static char *in_inc_dec;
218 #endif /* FORBIDDEN_INC_DEC_CLASSES */
220 #ifdef CLASS_CANNOT_CHANGE_MODE
222 /* These are the classes containing only registers that can be used in
223 a SUBREG expression that changes the mode of the register in some
224 way that is illegal. */
226 static int class_can_change_mode[N_REG_CLASSES];
228 /* Registers, including pseudos, which change modes in some way that
231 static regset reg_changes_mode;
233 #endif /* CLASS_CANNOT_CHANGE_MODE */
235 #ifdef HAVE_SECONDARY_RELOADS
237 /* Sample MEM values for use by memory_move_secondary_cost. */
239 static rtx top_of_stack[MAX_MACHINE_MODE];
241 #endif /* HAVE_SECONDARY_RELOADS */
243 /* Linked list of reg_info structures allocated for reg_n_info array.
244 Grouping all of the allocated structures together in one lump
245 means only one call to bzero to clear them, rather than n smaller
247 struct reg_info_data {
248 struct reg_info_data *next; /* next set of reg_info structures */
249 size_t min_index; /* minimum index # */
250 size_t max_index; /* maximum index # */
251 char used_p; /* non-zero if this has been used previously */
252 reg_info data[1]; /* beginning of the reg_info data */
255 static struct reg_info_data *reg_info_head;
257 /* No more global register variables may be declared; true once
258 regclass has been initialized. */
260 static int no_global_reg_vars = 0;
263 /* Function called only once to initialize the above data on reg usage.
264 Once this is done, various switches may override. */
271 /* First copy the register information from the initial int form into
274 for (i = 0; i < N_REG_CLASSES; i++)
276 CLEAR_HARD_REG_SET (reg_class_contents[i]);
278 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
279 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
280 if (int_reg_class_contents[i][j / 32]
281 & ((unsigned) 1 << (j % 32)))
282 SET_HARD_REG_BIT (reg_class_contents[i], j);
285 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
286 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
287 memset (global_regs, 0, sizeof global_regs);
289 /* Do any additional initialization regsets may need */
290 INIT_ONCE_REG_SET ();
292 #ifdef REG_ALLOC_ORDER
293 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
294 inv_reg_alloc_order[reg_alloc_order[i]] = i;
298 /* After switches have been processed, which perhaps alter
299 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
304 register unsigned int i, j;
305 register unsigned int /* enum machine_mode */ m;
306 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
308 /* This macro allows the fixed or call-used registers
309 and the register classes to depend on target flags. */
311 #ifdef CONDITIONAL_REGISTER_USAGE
312 CONDITIONAL_REGISTER_USAGE;
315 /* Compute number of hard regs in each class. */
317 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
318 for (i = 0; i < N_REG_CLASSES; i++)
319 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
320 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
323 /* Initialize the table of subunions.
324 reg_class_subunion[I][J] gets the largest-numbered reg-class
325 that is contained in the union of classes I and J. */
327 for (i = 0; i < N_REG_CLASSES; i++)
329 for (j = 0; j < N_REG_CLASSES; j++)
332 register /* Declare it register if it's a scalar. */
337 COPY_HARD_REG_SET (c, reg_class_contents[i]);
338 IOR_HARD_REG_SET (c, reg_class_contents[j]);
339 for (k = 0; k < N_REG_CLASSES; k++)
341 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
346 /* keep the largest subclass */ /* SPEE 900308 */
347 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
348 reg_class_contents[(int) reg_class_subunion[i][j]],
350 reg_class_subunion[i][j] = (enum reg_class) k;
357 /* Initialize the table of superunions.
358 reg_class_superunion[I][J] gets the smallest-numbered reg-class
359 containing the union of classes I and J. */
361 for (i = 0; i < N_REG_CLASSES; i++)
363 for (j = 0; j < N_REG_CLASSES; j++)
366 register /* Declare it register if it's a scalar. */
371 COPY_HARD_REG_SET (c, reg_class_contents[i]);
372 IOR_HARD_REG_SET (c, reg_class_contents[j]);
373 for (k = 0; k < N_REG_CLASSES; k++)
374 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
377 reg_class_superunion[i][j] = (enum reg_class) k;
381 /* Initialize the tables of subclasses and superclasses of each reg class.
382 First clear the whole table, then add the elements as they are found. */
384 for (i = 0; i < N_REG_CLASSES; i++)
386 for (j = 0; j < N_REG_CLASSES; j++)
388 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
389 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
393 for (i = 0; i < N_REG_CLASSES; i++)
395 if (i == (int) NO_REGS)
398 for (j = i + 1; j < N_REG_CLASSES; j++)
402 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
406 /* Reg class I is a subclass of J.
407 Add J to the table of superclasses of I. */
408 p = ®_class_superclasses[i][0];
409 while (*p != LIM_REG_CLASSES) p++;
410 *p = (enum reg_class) j;
411 /* Add I to the table of superclasses of J. */
412 p = ®_class_subclasses[j][0];
413 while (*p != LIM_REG_CLASSES) p++;
414 *p = (enum reg_class) i;
418 /* Initialize "constant" tables. */
420 CLEAR_HARD_REG_SET (fixed_reg_set);
421 CLEAR_HARD_REG_SET (call_used_reg_set);
422 CLEAR_HARD_REG_SET (call_fixed_reg_set);
423 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
425 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
427 n_non_fixed_regs = 0;
429 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
432 SET_HARD_REG_BIT (fixed_reg_set, i);
436 if (call_used_regs[i])
437 SET_HARD_REG_BIT (call_used_reg_set, i);
438 if (call_fixed_regs[i])
439 SET_HARD_REG_BIT (call_fixed_reg_set, i);
440 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
441 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
443 /* There are a couple of fixed registers that we know are safe to
444 exclude from being clobbered by calls:
446 The frame pointer is always preserved across calls. The arg pointer
447 is if it is fixed. The stack pointer usually is, unless
448 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
449 If we are generating PIC code, the PIC offset table register is
450 preserved across calls, though the target can override that. */
452 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM)
454 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
455 else if (i == HARD_FRAME_POINTER_REGNUM)
458 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
459 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
462 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
463 else if (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
466 else if (call_used_regs[i] || global_regs[i])
467 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
470 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
471 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
472 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
473 for (i = 0; i < N_REG_CLASSES; i++)
474 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
475 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
476 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
477 && HARD_REGNO_MODE_OK (j, m))
479 contains_reg_of_mode [i][m] = 1;
480 allocatable_regs_of_mode [m] = 1;
484 /* Initialize the move cost table. Find every subset of each class
485 and take the maximum cost of moving any subset to any other. */
487 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
488 if (allocatable_regs_of_mode [m])
490 for (i = 0; i < N_REG_CLASSES; i++)
491 if (contains_reg_of_mode [i][m])
492 for (j = 0; j < N_REG_CLASSES; j++)
495 enum reg_class *p1, *p2;
497 if (!contains_reg_of_mode [j][m])
499 move_cost[m][i][j] = 65536;
500 may_move_in_cost[m][i][j] = 65536;
501 may_move_out_cost[m][i][j] = 65536;
505 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
507 for (p2 = ®_class_subclasses[j][0];
508 *p2 != LIM_REG_CLASSES;
510 if (*p2 != i && contains_reg_of_mode [*p2][m])
511 cost = MAX (cost, move_cost [m][i][*p2]);
513 for (p1 = ®_class_subclasses[i][0];
514 *p1 != LIM_REG_CLASSES;
516 if (*p1 != j && contains_reg_of_mode [*p1][m])
517 cost = MAX (cost, move_cost [m][*p1][j]);
519 move_cost[m][i][j] = cost;
521 if (reg_class_subset_p (i, j))
522 may_move_in_cost[m][i][j] = 0;
524 may_move_in_cost[m][i][j] = cost;
526 if (reg_class_subset_p (j, i))
527 may_move_out_cost[m][i][j] = 0;
529 may_move_out_cost[m][i][j] = cost;
533 for (j = 0; j < N_REG_CLASSES; j++)
535 move_cost[m][i][j] = 65536;
536 may_move_in_cost[m][i][j] = 65536;
537 may_move_out_cost[m][i][j] = 65536;
541 #ifdef CLASS_CANNOT_CHANGE_MODE
544 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
546 for (i = 0; i < N_REG_CLASSES; i++)
548 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
549 class_can_change_mode [i] = 0;
552 class_can_change_mode [i] = 1;
555 #endif /* CLASS_CANNOT_CHANGE_MODE */
558 /* Compute the table of register modes.
559 These values are used to record death information for individual registers
560 (as opposed to a multi-register mode). */
567 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
569 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
571 /* If we couldn't find a valid mode, just use the previous mode.
572 ??? One situation in which we need to do this is on the mips where
573 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
574 to use DF mode for the even registers and VOIDmode for the odd
575 (for the cpu models where the odd ones are inaccessible). */
576 if (reg_raw_mode[i] == VOIDmode)
577 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
581 /* Finish initializing the register sets and
582 initialize the register modes. */
587 /* This finishes what was started by init_reg_sets, but couldn't be done
588 until after register usage was specified. */
593 #ifdef HAVE_SECONDARY_RELOADS
595 /* Make some fake stack-frame MEM references for use in
596 memory_move_secondary_cost. */
599 for (i = 0; i < MAX_MACHINE_MODE; i++)
600 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
601 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
606 #ifdef HAVE_SECONDARY_RELOADS
608 /* Compute extra cost of moving registers to/from memory due to reloads.
609 Only needed if secondary reloads are required for memory moves. */
612 memory_move_secondary_cost (mode, class, in)
613 enum machine_mode mode;
614 enum reg_class class;
617 enum reg_class altclass;
618 int partial_cost = 0;
619 /* We need a memory reference to feed to SECONDARY... macros. */
620 /* mem may be unused even if the SECONDARY_ macros are defined. */
621 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
626 #ifdef SECONDARY_INPUT_RELOAD_CLASS
627 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
634 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
635 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
641 if (altclass == NO_REGS)
645 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
647 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
649 if (class == altclass)
650 /* This isn't simply a copy-to-temporary situation. Can't guess
651 what it is, so MEMORY_MOVE_COST really ought not to be calling
654 I'm tempted to put in an abort here, but returning this will
655 probably only give poor estimates, which is what we would've
656 had before this code anyways. */
659 /* Check if the secondary reload register will also need a
661 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
665 /* Return a machine mode that is legitimate for hard reg REGNO and large
666 enough to save nregs. If we can't find one, return VOIDmode. */
669 choose_hard_reg_mode (regno, nregs)
670 unsigned int regno ATTRIBUTE_UNUSED;
673 unsigned int /* enum machine_mode */ m;
674 enum machine_mode found_mode = VOIDmode, mode;
676 /* We first look for the largest integer mode that can be validly
677 held in REGNO. If none, we look for the largest floating-point mode.
678 If we still didn't find a valid mode, try CCmode. */
680 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
682 mode = GET_MODE_WIDER_MODE (mode))
683 if (HARD_REGNO_NREGS (regno, mode) == nregs
684 && HARD_REGNO_MODE_OK (regno, mode))
687 if (found_mode != VOIDmode)
690 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
692 mode = GET_MODE_WIDER_MODE (mode))
693 if (HARD_REGNO_NREGS (regno, mode) == nregs
694 && HARD_REGNO_MODE_OK (regno, mode))
697 if (found_mode != VOIDmode)
700 /* Iterate over all of the CCmodes. */
701 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
703 mode = (enum machine_mode) m;
704 if (HARD_REGNO_NREGS (regno, mode) == nregs
705 && HARD_REGNO_MODE_OK (regno, mode))
709 /* We can't find a mode valid for this register. */
713 /* Specify the usage characteristics of the register named NAME.
714 It should be a fixed register if FIXED and a
715 call-used register if CALL_USED. */
718 fix_register (name, fixed, call_used)
720 int fixed, call_used;
724 /* Decode the name and update the primary form of
725 the register info. */
727 if ((i = decode_reg_name (name)) >= 0)
729 if ((i == STACK_POINTER_REGNUM
730 #ifdef HARD_FRAME_POINTER_REGNUM
731 || i == HARD_FRAME_POINTER_REGNUM
733 || i == FRAME_POINTER_REGNUM
736 && (fixed == 0 || call_used == 0))
738 static const char * const what_option[2][2] = {
739 { "call-saved", "call-used" },
740 { "no-such-option", "fixed" }};
742 error ("can't use '%s' as a %s register", name,
743 what_option[fixed][call_used]);
747 fixed_regs[i] = fixed;
748 call_used_regs[i] = call_used;
753 warning ("unknown register name: %s", name);
757 /* Mark register number I as global. */
763 if (fixed_regs[i] == 0 && no_global_reg_vars)
764 error ("global register variable follows a function definition");
768 warning ("register used for two global register variables");
772 if (call_used_regs[i] && ! fixed_regs[i])
773 warning ("call-clobbered register used for global register variable");
777 /* If already fixed, nothing else to do. */
781 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
784 SET_HARD_REG_BIT (fixed_reg_set, i);
785 SET_HARD_REG_BIT (call_used_reg_set, i);
786 SET_HARD_REG_BIT (call_fixed_reg_set, i);
789 /* Now the data and code for the `regclass' pass, which happens
790 just before local-alloc. */
792 /* The `costs' struct records the cost of using a hard register of each class
793 and of using memory for each pseudo. We use this data to set up
794 register class preferences. */
798 int cost[N_REG_CLASSES];
802 /* Structure used to record preferrences of given pseudo. */
805 /* (enum reg_class) prefclass is the preferred class. */
808 /* altclass is a register class that we should use for allocating
809 pseudo if no register in the preferred class is available.
810 If no register in this class is available, memory is preferred.
812 It might appear to be more general to have a bitmask of classes here,
813 but since it is recommended that there be a class corresponding to the
814 union of most major pair of classes, that generality is not required. */
818 /* Record the cost of each class for each pseudo. */
820 static struct costs *costs;
822 /* Initialized once, and used to initialize cost values for each insn. */
824 static struct costs init_cost;
826 /* Record preferrences of each pseudo.
827 This is available after `regclass' is run. */
829 static struct reg_pref *reg_pref;
831 /* Allocated buffers for reg_pref. */
833 static struct reg_pref *reg_pref_buffer;
835 /* Frequency of executions of current insn. */
837 static int frequency;
839 static rtx scan_one_insn PARAMS ((rtx, int));
840 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
841 static void dump_regclass PARAMS ((FILE *));
842 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
844 struct costs *, struct reg_pref *));
845 static int copy_cost PARAMS ((rtx, enum machine_mode,
846 enum reg_class, int));
847 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
848 #ifdef FORBIDDEN_INC_DEC_CLASSES
849 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
851 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
853 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
854 This function is sometimes called before the info has been computed.
855 When that happens, just return GENERAL_REGS, which is innocuous. */
858 reg_preferred_class (regno)
863 return (enum reg_class) reg_pref[regno].prefclass;
867 reg_alternate_class (regno)
873 return (enum reg_class) reg_pref[regno].altclass;
876 /* Initialize some global data for this pass. */
883 init_cost.mem_cost = 10000;
884 for (i = 0; i < N_REG_CLASSES; i++)
885 init_cost.cost[i] = 10000;
887 /* This prevents dump_flow_info from losing if called
888 before regclass is run. */
891 /* No more global register variables may be declared. */
892 no_global_reg_vars = 1;
895 /* Dump register costs. */
900 static const char *const reg_class_names[] = REG_CLASS_NAMES;
902 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
904 int /* enum reg_class */ class;
907 fprintf (dump, " Register %i costs:", i);
908 for (class = 0; class < (int) N_REG_CLASSES; class++)
909 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
910 #ifdef FORBIDDEN_INC_DEC_CLASSES
912 || !forbidden_inc_dec_class[(enum reg_class) class])
914 #ifdef CLASS_CANNOT_CHANGE_MODE
915 && (!REGNO_REG_SET_P (reg_changes_mode, i)
916 || class_can_change_mode [(enum reg_class) class])
919 fprintf (dump, " %s:%i", reg_class_names[class],
920 costs[i].cost[(enum reg_class) class]);
921 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
927 /* Calculate the costs of insn operands. */
930 record_operand_costs (insn, op_costs, reg_pref)
932 struct costs *op_costs;
933 struct reg_pref *reg_pref;
935 const char *constraints[MAX_RECOG_OPERANDS];
936 enum machine_mode modes[MAX_RECOG_OPERANDS];
939 for (i = 0; i < recog_data.n_operands; i++)
941 constraints[i] = recog_data.constraints[i];
942 modes[i] = recog_data.operand_mode[i];
945 /* If we get here, we are set up to record the costs of all the
946 operands for this insn. Start by initializing the costs.
947 Then handle any address registers. Finally record the desired
948 classes for any pseudos, doing it twice if some pair of
949 operands are commutative. */
951 for (i = 0; i < recog_data.n_operands; i++)
953 op_costs[i] = init_cost;
955 if (GET_CODE (recog_data.operand[i]) == SUBREG)
957 rtx inner = SUBREG_REG (recog_data.operand[i]);
958 #ifdef CLASS_CANNOT_CHANGE_MODE
959 if (GET_CODE (inner) == REG
960 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
961 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
963 recog_data.operand[i] = inner;
966 if (GET_CODE (recog_data.operand[i]) == MEM)
967 record_address_regs (XEXP (recog_data.operand[i], 0),
968 BASE_REG_CLASS, frequency * 2);
969 else if (constraints[i][0] == 'p')
970 record_address_regs (recog_data.operand[i],
971 BASE_REG_CLASS, frequency * 2);
974 /* Check for commutative in a separate loop so everything will
975 have been initialized. We must do this even if one operand
976 is a constant--see addsi3 in m68k.md. */
978 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
979 if (constraints[i][0] == '%')
981 const char *xconstraints[MAX_RECOG_OPERANDS];
984 /* Handle commutative operands by swapping the constraints.
985 We assume the modes are the same. */
987 for (j = 0; j < recog_data.n_operands; j++)
988 xconstraints[j] = constraints[j];
990 xconstraints[i] = constraints[i+1];
991 xconstraints[i+1] = constraints[i];
992 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
993 recog_data.operand, modes,
994 xconstraints, insn, op_costs, reg_pref);
997 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
998 recog_data.operand, modes,
999 constraints, insn, op_costs, reg_pref);
1002 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1003 time it would save code to put a certain register in a certain class.
1004 PASS, when nonzero, inhibits some optimizations which need only be done
1006 Return the last insn processed, so that the scan can be continued from
1010 scan_one_insn (insn, pass)
1014 enum rtx_code code = GET_CODE (insn);
1015 enum rtx_code pat_code;
1018 struct costs op_costs[MAX_RECOG_OPERANDS];
1020 if (GET_RTX_CLASS (code) != 'i')
1023 pat_code = GET_CODE (PATTERN (insn));
1025 || pat_code == CLOBBER
1026 || pat_code == ASM_INPUT
1027 || pat_code == ADDR_VEC
1028 || pat_code == ADDR_DIFF_VEC)
1031 set = single_set (insn);
1032 extract_insn (insn);
1034 /* If this insn loads a parameter from its stack slot, then
1035 it represents a savings, rather than a cost, if the
1036 parameter is stored in memory. Record this fact. */
1038 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
1039 && GET_CODE (SET_SRC (set)) == MEM
1040 && (note = find_reg_note (insn, REG_EQUIV,
1042 && GET_CODE (XEXP (note, 0)) == MEM)
1044 costs[REGNO (SET_DEST (set))].mem_cost
1045 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1048 record_address_regs (XEXP (SET_SRC (set), 0),
1049 BASE_REG_CLASS, frequency * 2);
1053 /* Improve handling of two-address insns such as
1054 (set X (ashift CONST Y)) where CONST must be made to
1055 match X. Change it into two insns: (set X CONST)
1056 (set X (ashift X Y)). If we left this for reloading, it
1057 would probably get three insns because X and Y might go
1058 in the same place. This prevents X and Y from receiving
1061 We can only do this if the modes of operands 0 and 1
1062 (which might not be the same) are tieable and we only need
1063 do this during our first pass. */
1065 if (pass == 0 && optimize
1066 && recog_data.n_operands >= 3
1067 && recog_data.constraints[1][0] == '0'
1068 && recog_data.constraints[1][1] == 0
1069 && CONSTANT_P (recog_data.operand[1])
1070 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1071 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1072 && GET_CODE (recog_data.operand[0]) == REG
1073 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1074 recog_data.operand_mode[1]))
1076 rtx previnsn = prev_real_insn (insn);
1078 = gen_lowpart (recog_data.operand_mode[1],
1079 recog_data.operand[0]);
1081 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1083 /* If this insn was the start of a basic block,
1084 include the new insn in that block.
1085 We need not check for code_label here;
1086 while a basic block can start with a code_label,
1087 INSN could not be at the beginning of that block. */
1088 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1091 for (b = 0; b < n_basic_blocks; b++)
1092 if (insn == BLOCK_HEAD (b))
1093 BLOCK_HEAD (b) = newinsn;
1096 /* This makes one more setting of new insns's dest. */
1097 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1098 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1099 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1101 *recog_data.operand_loc[1] = recog_data.operand[0];
1102 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1103 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1104 for (i = recog_data.n_dups - 1; i >= 0; i--)
1105 if (recog_data.dup_num[i] == 1)
1107 *recog_data.dup_loc[i] = recog_data.operand[0];
1108 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1109 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1112 return PREV_INSN (newinsn);
1115 record_operand_costs (insn, op_costs, reg_pref);
1117 /* Now add the cost for each operand to the total costs for
1120 for (i = 0; i < recog_data.n_operands; i++)
1121 if (GET_CODE (recog_data.operand[i]) == REG
1122 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1124 int regno = REGNO (recog_data.operand[i]);
1125 struct costs *p = &costs[regno], *q = &op_costs[i];
1127 p->mem_cost += q->mem_cost * frequency;
1128 for (j = 0; j < N_REG_CLASSES; j++)
1129 p->cost[j] += q->cost[j] * frequency;
1135 /* This is a pass of the compiler that scans all instructions
1136 and calculates the preferred class for each pseudo-register.
1137 This information can be accessed later by calling `reg_preferred_class'.
1138 This pass comes just before local register allocation. */
1141 regclass (f, nregs, dump)
1152 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1154 #ifdef CLASS_CANNOT_CHANGE_MODE
1155 reg_changes_mode = BITMAP_XMALLOC();
1158 #ifdef FORBIDDEN_INC_DEC_CLASSES
1160 in_inc_dec = (char *) xmalloc (nregs);
1162 /* Initialize information about which register classes can be used for
1163 pseudos that are auto-incremented or auto-decremented. It would
1164 seem better to put this in init_reg_sets, but we need to be able
1165 to allocate rtx, which we can't do that early. */
1167 for (i = 0; i < N_REG_CLASSES; i++)
1169 rtx r = gen_rtx_REG (VOIDmode, 0);
1170 enum machine_mode m;
1173 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1174 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1178 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1179 m = (enum machine_mode) ((int) m + 1))
1180 if (HARD_REGNO_MODE_OK (j, m))
1184 /* If a register is not directly suitable for an
1185 auto-increment or decrement addressing mode and
1186 requires secondary reloads, disallow its class from
1187 being used in such addresses. */
1190 #ifdef SECONDARY_RELOAD_CLASS
1191 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1194 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1195 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1198 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1199 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1204 && ! auto_inc_dec_reg_p (r, m))
1205 forbidden_inc_dec_class[i] = 1;
1209 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1211 /* Normally we scan the insns once and determine the best class to use for
1212 each register. However, if -fexpensive_optimizations are on, we do so
1213 twice, the second time using the tentative best classes to guide the
1216 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1221 fprintf (dump, "\n\nPass %i\n\n",pass);
1222 /* Zero out our accumulation of the cost of each class for each reg. */
1224 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1226 #ifdef FORBIDDEN_INC_DEC_CLASSES
1227 memset (in_inc_dec, 0, nregs);
1230 /* Scan the instructions and record each time it would
1231 save code to put a certain register in a certain class. */
1236 for (insn = f; insn; insn = NEXT_INSN (insn))
1237 insn = scan_one_insn (insn, pass);
1240 for (index = 0; index < n_basic_blocks; index++)
1242 basic_block bb = BASIC_BLOCK (index);
1244 /* Show that an insn inside a loop is likely to be executed three
1245 times more than insns outside a loop. This is much more
1246 aggressive than the assumptions made elsewhere and is being
1247 tried as an experiment. */
1251 frequency = bb->frequency ? bb->frequency : 1;
1252 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1254 insn = scan_one_insn (insn, pass);
1255 if (insn == bb->end)
1260 /* Now for each register look at how desirable each class is
1261 and find which class is preferred. Store that in
1262 `prefclass'. Record in `altclass' the largest register
1263 class any of whose registers is better than memory. */
1266 reg_pref = reg_pref_buffer;
1270 dump_regclass (dump);
1271 fprintf (dump,"\n");
1273 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1275 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1276 enum reg_class best = ALL_REGS, alt = NO_REGS;
1277 /* This is an enum reg_class, but we call it an int
1278 to save lots of casts. */
1280 register struct costs *p = &costs[i];
1282 /* In non-optimizing compilation REG_N_REFS is not initialized
1284 if (optimize && !REG_N_REFS (i))
1287 for (class = (int) ALL_REGS - 1; class > 0; class--)
1289 /* Ignore classes that are too small for this operand or
1290 invalid for a operand that was auto-incremented. */
1291 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1292 #ifdef FORBIDDEN_INC_DEC_CLASSES
1293 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1295 #ifdef CLASS_CANNOT_CHANGE_MODE
1296 || (REGNO_REG_SET_P (reg_changes_mode, i)
1297 && ! class_can_change_mode [class])
1301 else if (p->cost[class] < best_cost)
1303 best_cost = p->cost[class];
1304 best = (enum reg_class) class;
1306 else if (p->cost[class] == best_cost)
1307 best = reg_class_subunion[(int)best][class];
1310 /* Record the alternate register class; i.e., a class for which
1311 every register in it is better than using memory. If adding a
1312 class would make a smaller class (i.e., no union of just those
1313 classes exists), skip that class. The major unions of classes
1314 should be provided as a register class. Don't do this if we
1315 will be doing it again later. */
1317 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1318 for (class = 0; class < N_REG_CLASSES; class++)
1319 if (p->cost[class] < p->mem_cost
1320 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1321 > reg_class_size[(int) alt])
1322 #ifdef FORBIDDEN_INC_DEC_CLASSES
1323 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1325 #ifdef CLASS_CANNOT_CHANGE_MODE
1326 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1327 && ! class_can_change_mode [class])
1330 alt = reg_class_subunion[(int) alt][class];
1332 /* If we don't add any classes, nothing to try. */
1337 && (reg_pref[i].prefclass != (int) best
1338 || reg_pref[i].altclass != (int) alt))
1340 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1341 fprintf (dump, " Register %i", i);
1342 if (alt == ALL_REGS || best == ALL_REGS)
1343 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1344 else if (alt == NO_REGS)
1345 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1347 fprintf (dump, " pref %s, else %s\n",
1348 reg_class_names[(int) best],
1349 reg_class_names[(int) alt]);
1352 /* We cast to (int) because (char) hits bugs in some compilers. */
1353 reg_pref[i].prefclass = (int) best;
1354 reg_pref[i].altclass = (int) alt;
1358 #ifdef FORBIDDEN_INC_DEC_CLASSES
1361 #ifdef CLASS_CANNOT_CHANGE_MODE
1362 BITMAP_XFREE (reg_changes_mode);
1367 /* Record the cost of using memory or registers of various classes for
1368 the operands in INSN.
1370 N_ALTS is the number of alternatives.
1372 N_OPS is the number of operands.
1374 OPS is an array of the operands.
1376 MODES are the modes of the operands, in case any are VOIDmode.
1378 CONSTRAINTS are the constraints to use for the operands. This array
1379 is modified by this procedure.
1381 This procedure works alternative by alternative. For each alternative
1382 we assume that we will be able to allocate all pseudos to their ideal
1383 register class and calculate the cost of using that alternative. Then
1384 we compute for each operand that is a pseudo-register, the cost of
1385 having the pseudo allocated to each register class and using it in that
1386 alternative. To this cost is added the cost of the alternative.
1388 The cost of each class for this insn is its lowest cost among all the
1392 record_reg_classes (n_alts, n_ops, ops, modes,
1393 constraints, insn, op_costs, reg_pref)
1397 enum machine_mode *modes;
1398 const char **constraints;
1400 struct costs *op_costs;
1401 struct reg_pref *reg_pref;
1407 /* Process each alternative, each time minimizing an operand's cost with
1408 the cost for each operand in that alternative. */
1410 for (alt = 0; alt < n_alts; alt++)
1412 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1415 enum reg_class classes[MAX_RECOG_OPERANDS];
1416 int allows_mem[MAX_RECOG_OPERANDS];
1419 for (i = 0; i < n_ops; i++)
1421 const char *p = constraints[i];
1423 enum machine_mode mode = modes[i];
1424 int allows_addr = 0;
1428 /* Initially show we know nothing about the register class. */
1429 classes[i] = NO_REGS;
1432 /* If this operand has no constraints at all, we can conclude
1433 nothing about it since anything is valid. */
1437 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1438 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1443 /* If this alternative is only relevant when this operand
1444 matches a previous operand, we do different things depending
1445 on whether this operand is a pseudo-reg or not. We must process
1446 any modifiers for the operand before we can make this test. */
1448 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1451 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1453 /* Copy class and whether memory is allowed from the matching
1454 alternative. Then perform any needed cost computations
1455 and/or adjustments. */
1457 classes[i] = classes[j];
1458 allows_mem[i] = allows_mem[j];
1460 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1462 /* If this matches the other operand, we have no added
1464 if (rtx_equal_p (ops[j], op))
1467 /* If we can put the other operand into a register, add to
1468 the cost of this alternative the cost to copy this
1469 operand to the register used for the other operand. */
1471 else if (classes[j] != NO_REGS)
1472 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1474 else if (GET_CODE (ops[j]) != REG
1475 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1477 /* This op is a pseudo but the one it matches is not. */
1479 /* If we can't put the other operand into a register, this
1480 alternative can't be used. */
1482 if (classes[j] == NO_REGS)
1485 /* Otherwise, add to the cost of this alternative the cost
1486 to copy the other operand to the register used for this
1490 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1494 /* The costs of this operand are not the same as the other
1495 operand since move costs are not symmetric. Moreover,
1496 if we cannot tie them, this alternative needs to do a
1497 copy, which is one instruction. */
1499 struct costs *pp = &this_op_costs[i];
1501 for (class = 0; class < N_REG_CLASSES; class++)
1503 = ((recog_data.operand_type[i] != OP_OUT
1504 ? may_move_in_cost[mode][class][(int) classes[i]]
1506 + (recog_data.operand_type[i] != OP_IN
1507 ? may_move_out_cost[mode][(int) classes[i]][class]
1510 /* If the alternative actually allows memory, make things
1511 a bit cheaper since we won't need an extra insn to
1515 = ((recog_data.operand_type[i] != OP_IN
1516 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1518 + (recog_data.operand_type[i] != OP_OUT
1519 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1520 : 0) - allows_mem[i]);
1522 /* If we have assigned a class to this register in our
1523 first pass, add a cost to this alternative corresponding
1524 to what we would add if this register were not in the
1525 appropriate class. */
1529 += (may_move_in_cost[mode]
1530 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1531 [(int) classes[i]]);
1533 if (REGNO (ops[i]) != REGNO (ops[j])
1534 && ! find_reg_note (insn, REG_DEAD, op))
1537 /* This is in place of ordinary cost computation
1538 for this operand, so skip to the end of the
1539 alternative (should be just one character). */
1540 while (*p && *p++ != ',')
1548 /* Scan all the constraint letters. See if the operand matches
1549 any of the constraints. Collect the valid register classes
1550 and see if this operand accepts memory. */
1552 while (*p && (c = *p++) != ',')
1556 /* Ignore the next letter for this pass. */
1562 case '!': case '#': case '&':
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1569 win = address_operand (op, GET_MODE (op));
1570 /* We know this operand is an address, so we want it to be
1571 allocated to a register that can be the base of an
1572 address, ie BASE_REG_CLASS. */
1574 = reg_class_subunion[(int) classes[i]]
1575 [(int) BASE_REG_CLASS];
1578 case 'm': case 'o': case 'V':
1579 /* It doesn't seem worth distinguishing between offsettable
1580 and non-offsettable addresses here. */
1582 if (GET_CODE (op) == MEM)
1587 if (GET_CODE (op) == MEM
1588 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1589 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1594 if (GET_CODE (op) == MEM
1595 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1596 || GET_CODE (XEXP (op, 0)) == POST_INC))
1601 #ifndef REAL_ARITHMETIC
1602 /* Match any floating double constant, but only if
1603 we can examine the bits of it reliably. */
1604 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1605 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1606 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1609 if (GET_CODE (op) == CONST_DOUBLE)
1614 if (GET_CODE (op) == CONST_DOUBLE)
1620 if (GET_CODE (op) == CONST_DOUBLE
1621 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1626 if (GET_CODE (op) == CONST_INT
1627 || (GET_CODE (op) == CONST_DOUBLE
1628 && GET_MODE (op) == VOIDmode))
1632 #ifdef LEGITIMATE_PIC_OPERAND_P
1633 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1640 if (GET_CODE (op) == CONST_INT
1641 || (GET_CODE (op) == CONST_DOUBLE
1642 && GET_MODE (op) == VOIDmode))
1654 if (GET_CODE (op) == CONST_INT
1655 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1664 if (GET_CODE (op) == MEM
1666 #ifdef LEGITIMATE_PIC_OPERAND_P
1667 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1674 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1678 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1680 = reg_class_subunion[(int) classes[i]]
1681 [(int) REG_CLASS_FROM_LETTER (c)];
1682 #ifdef EXTRA_CONSTRAINT
1683 else if (EXTRA_CONSTRAINT (op, c))
1691 /* How we account for this operand now depends on whether it is a
1692 pseudo register or not. If it is, we first check if any
1693 register classes are valid. If not, we ignore this alternative,
1694 since we want to assume that all pseudos get allocated for
1695 register preferencing. If some register class is valid, compute
1696 the costs of moving the pseudo into that class. */
1698 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1700 if (classes[i] == NO_REGS)
1702 /* We must always fail if the operand is a REG, but
1703 we did not find a suitable class.
1705 Otherwise we may perform an uninitialized read
1706 from this_op_costs after the `continue' statement
1712 struct costs *pp = &this_op_costs[i];
1714 for (class = 0; class < N_REG_CLASSES; class++)
1716 = ((recog_data.operand_type[i] != OP_OUT
1717 ? may_move_in_cost[mode][class][(int) classes[i]]
1719 + (recog_data.operand_type[i] != OP_IN
1720 ? may_move_out_cost[mode][(int) classes[i]][class]
1723 /* If the alternative actually allows memory, make things
1724 a bit cheaper since we won't need an extra insn to
1728 = ((recog_data.operand_type[i] != OP_IN
1729 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1731 + (recog_data.operand_type[i] != OP_OUT
1732 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1733 : 0) - allows_mem[i]);
1735 /* If we have assigned a class to this register in our
1736 first pass, add a cost to this alternative corresponding
1737 to what we would add if this register were not in the
1738 appropriate class. */
1742 += (may_move_in_cost[mode]
1743 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1744 [(int) classes[i]]);
1748 /* Otherwise, if this alternative wins, either because we
1749 have already determined that or if we have a hard register of
1750 the proper class, there is no cost for this alternative. */
1753 || (GET_CODE (op) == REG
1754 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1757 /* If registers are valid, the cost of this alternative includes
1758 copying the object to and/or from a register. */
1760 else if (classes[i] != NO_REGS)
1762 if (recog_data.operand_type[i] != OP_OUT)
1763 alt_cost += copy_cost (op, mode, classes[i], 1);
1765 if (recog_data.operand_type[i] != OP_IN)
1766 alt_cost += copy_cost (op, mode, classes[i], 0);
1769 /* The only other way this alternative can be used is if this is a
1770 constant that could be placed into memory. */
1772 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1773 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1781 /* Finally, update the costs with the information we've calculated
1782 about this alternative. */
1784 for (i = 0; i < n_ops; i++)
1785 if (GET_CODE (ops[i]) == REG
1786 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1788 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1789 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1791 pp->mem_cost = MIN (pp->mem_cost,
1792 (qq->mem_cost + alt_cost) * scale);
1794 for (class = 0; class < N_REG_CLASSES; class++)
1795 pp->cost[class] = MIN (pp->cost[class],
1796 (qq->cost[class] + alt_cost) * scale);
1800 /* If this insn is a single set copying operand 1 to operand 0
1801 and one operand is a pseudo with the other a hard reg or a pseudo
1802 that prefers a register that is in its own register class then
1803 we may want to adjust the cost of that register class to -1.
1805 Avoid the adjustment if the source does not die to avoid stressing of
1806 register allocator by preferrencing two coliding registers into single
1809 Also avoid the adjustment if a copy between registers of the class
1810 is expensive (ten times the cost of a default copy is considered
1811 arbitrarily expensive). This avoids losing when the preferred class
1812 is very expensive as the source of a copy instruction. */
1814 if ((set = single_set (insn)) != 0
1815 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1816 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1817 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1818 for (i = 0; i <= 1; i++)
1819 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1821 unsigned int regno = REGNO (ops[!i]);
1822 enum machine_mode mode = GET_MODE (ops[!i]);
1826 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1828 enum reg_class pref = reg_pref[regno].prefclass;
1830 if ((reg_class_size[(unsigned char) pref]
1831 == CLASS_MAX_NREGS (pref, mode))
1832 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1833 op_costs[i].cost[(unsigned char) pref] = -1;
1835 else if (regno < FIRST_PSEUDO_REGISTER)
1836 for (class = 0; class < N_REG_CLASSES; class++)
1837 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1838 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1840 if (reg_class_size[class] == 1)
1841 op_costs[i].cost[class] = -1;
1844 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1846 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1851 if (nr == HARD_REGNO_NREGS (regno,mode))
1852 op_costs[i].cost[class] = -1;
1858 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1859 TO_P is zero) a register of class CLASS in mode MODE.
1861 X must not be a pseudo. */
1864 copy_cost (x, mode, class, to_p)
1866 enum machine_mode mode ATTRIBUTE_UNUSED;
1867 enum reg_class class;
1868 int to_p ATTRIBUTE_UNUSED;
1870 #ifdef HAVE_SECONDARY_RELOADS
1871 enum reg_class secondary_class = NO_REGS;
1874 /* If X is a SCRATCH, there is actually nothing to move since we are
1875 assuming optimal allocation. */
1877 if (GET_CODE (x) == SCRATCH)
1880 /* Get the class we will actually use for a reload. */
1881 class = PREFERRED_RELOAD_CLASS (x, class);
1883 #ifdef HAVE_SECONDARY_RELOADS
1884 /* If we need a secondary reload (we assume here that we are using
1885 the secondary reload as an intermediate, not a scratch register), the
1886 cost is that to load the input into the intermediate register, then
1887 to copy them. We use a special value of TO_P to avoid recursion. */
1889 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1891 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1894 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1896 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1899 if (secondary_class != NO_REGS)
1900 return (move_cost[mode][(int) secondary_class][(int) class]
1901 + copy_cost (x, mode, secondary_class, 2));
1902 #endif /* HAVE_SECONDARY_RELOADS */
1904 /* For memory, use the memory move cost, for (hard) registers, use the
1905 cost to move between the register classes, and use 2 for everything
1906 else (constants). */
1908 if (GET_CODE (x) == MEM || class == NO_REGS)
1909 return MEMORY_MOVE_COST (mode, class, to_p);
1911 else if (GET_CODE (x) == REG)
1912 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1915 /* If this is a constant, we may eventually want to call rtx_cost here. */
1916 return COSTS_N_INSNS (1);
1919 /* Record the pseudo registers we must reload into hard registers
1920 in a subexpression of a memory address, X.
1922 CLASS is the class that the register needs to be in and is either
1923 BASE_REG_CLASS or INDEX_REG_CLASS.
1925 SCALE is twice the amount to multiply the cost by (it is twice so we
1926 can represent half-cost adjustments). */
1929 record_address_regs (x, class, scale)
1931 enum reg_class class;
1934 register enum rtx_code code = GET_CODE (x);
1947 /* When we have an address that is a sum,
1948 we must determine whether registers are "base" or "index" regs.
1949 If there is a sum of two registers, we must choose one to be
1950 the "base". Luckily, we can use the REG_POINTER to make a good
1951 choice most of the time. We only need to do this on machines
1952 that can have two registers in an address and where the base
1953 and index register classes are different.
1955 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1956 that seems bogus since it should only be set when we are sure
1957 the register is being used as a pointer. */
1960 rtx arg0 = XEXP (x, 0);
1961 rtx arg1 = XEXP (x, 1);
1962 register enum rtx_code code0 = GET_CODE (arg0);
1963 register enum rtx_code code1 = GET_CODE (arg1);
1965 /* Look inside subregs. */
1966 if (code0 == SUBREG)
1967 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1968 if (code1 == SUBREG)
1969 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1971 /* If this machine only allows one register per address, it must
1972 be in the first operand. */
1974 if (MAX_REGS_PER_ADDRESS == 1)
1975 record_address_regs (arg0, class, scale);
1977 /* If index and base registers are the same on this machine, just
1978 record registers in any non-constant operands. We assume here,
1979 as well as in the tests below, that all addresses are in
1982 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1984 record_address_regs (arg0, class, scale);
1985 if (! CONSTANT_P (arg1))
1986 record_address_regs (arg1, class, scale);
1989 /* If the second operand is a constant integer, it doesn't change
1990 what class the first operand must be. */
1992 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1993 record_address_regs (arg0, class, scale);
1995 /* If the second operand is a symbolic constant, the first operand
1996 must be an index register. */
1998 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1999 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2001 /* If both operands are registers but one is already a hard register
2002 of index or base class, give the other the class that the hard
2005 #ifdef REG_OK_FOR_BASE_P
2006 else if (code0 == REG && code1 == REG
2007 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2008 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
2009 record_address_regs (arg1,
2010 REG_OK_FOR_BASE_P (arg0)
2011 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2013 else if (code0 == REG && code1 == REG
2014 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2015 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
2016 record_address_regs (arg0,
2017 REG_OK_FOR_BASE_P (arg1)
2018 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2022 /* If one operand is known to be a pointer, it must be the base
2023 with the other operand the index. Likewise if the other operand
2026 else if ((code0 == REG && REG_POINTER (arg0))
2029 record_address_regs (arg0, BASE_REG_CLASS, scale);
2030 record_address_regs (arg1, INDEX_REG_CLASS, scale);
2032 else if ((code1 == REG && REG_POINTER (arg1))
2035 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2036 record_address_regs (arg1, BASE_REG_CLASS, scale);
2039 /* Otherwise, count equal chances that each might be a base
2040 or index register. This case should be rare. */
2044 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
2045 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
2046 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
2047 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2052 /* Double the importance of a pseudo register that is incremented
2053 or decremented, since it would take two extra insns
2054 if it ends up in the wrong place. */
2057 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
2058 if (REG_P (XEXP (XEXP (x, 1), 1)))
2059 record_address_regs (XEXP (XEXP (x, 1), 1),
2060 INDEX_REG_CLASS, 2 * scale);
2067 /* Double the importance of a pseudo register that is incremented
2068 or decremented, since it would take two extra insns
2069 if it ends up in the wrong place. If the operand is a pseudo,
2070 show it is being used in an INC_DEC context. */
2072 #ifdef FORBIDDEN_INC_DEC_CLASSES
2073 if (GET_CODE (XEXP (x, 0)) == REG
2074 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2075 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2078 record_address_regs (XEXP (x, 0), class, 2 * scale);
2083 register struct costs *pp = &costs[REGNO (x)];
2086 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2088 for (i = 0; i < N_REG_CLASSES; i++)
2089 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2095 register const char *fmt = GET_RTX_FORMAT (code);
2097 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2099 record_address_regs (XEXP (x, i), class, scale);
2104 #ifdef FORBIDDEN_INC_DEC_CLASSES
2106 /* Return 1 if REG is valid as an auto-increment memory reference
2107 to an object of MODE. */
2110 auto_inc_dec_reg_p (reg, mode)
2112 enum machine_mode mode;
2114 if (HAVE_POST_INCREMENT
2115 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2118 if (HAVE_POST_DECREMENT
2119 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2122 if (HAVE_PRE_INCREMENT
2123 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2126 if (HAVE_PRE_DECREMENT
2127 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2134 static short *renumber;
2135 static size_t regno_allocated;
2136 static unsigned int reg_n_max;
2138 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2139 reg_scan and flow_analysis that are indexed by the register number. If
2140 NEW_P is non zero, initialize all of the registers, otherwise only
2141 initialize the new registers allocated. The same table is kept from
2142 function to function, only reallocating it when we need more room. If
2143 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2146 allocate_reg_info (num_regs, new_p, renumber_p)
2152 size_t size_renumber;
2153 size_t min = (new_p) ? 0 : reg_n_max;
2154 struct reg_info_data *reg_data;
2156 if (num_regs > regno_allocated)
2158 size_t old_allocated = regno_allocated;
2160 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2161 size_renumber = regno_allocated * sizeof (short);
2165 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2166 renumber = (short *) xmalloc (size_renumber);
2167 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2168 * sizeof (struct reg_pref));
2173 VARRAY_GROW (reg_n_info, regno_allocated);
2175 if (new_p) /* if we're zapping everything, no need to realloc */
2177 free ((char *)renumber);
2178 free ((char *)reg_pref);
2179 renumber = (short *) xmalloc (size_renumber);
2180 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2181 * sizeof (struct reg_pref));
2186 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2187 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2189 * sizeof (struct reg_pref));
2193 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2194 + sizeof (struct reg_info_data) - sizeof (reg_info);
2195 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2196 reg_data->min_index = old_allocated;
2197 reg_data->max_index = regno_allocated - 1;
2198 reg_data->next = reg_info_head;
2199 reg_info_head = reg_data;
2202 reg_n_max = num_regs;
2205 /* Loop through each of the segments allocated for the actual
2206 reg_info pages, and set up the pointers, zero the pages, etc. */
2207 for (reg_data = reg_info_head;
2208 reg_data && reg_data->max_index >= min;
2209 reg_data = reg_data->next)
2211 size_t min_index = reg_data->min_index;
2212 size_t max_index = reg_data->max_index;
2213 size_t max = MIN (max_index, num_regs);
2214 size_t local_min = min - min_index;
2217 if (reg_data->min_index > num_regs)
2220 if (min < min_index)
2222 if (!reg_data->used_p) /* page just allocated with calloc */
2223 reg_data->used_p = 1; /* no need to zero */
2225 memset ((char *) ®_data->data[local_min], 0,
2226 sizeof (reg_info) * (max - min_index - local_min + 1));
2228 for (i = min_index+local_min; i <= max; i++)
2230 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2231 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2233 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2234 reg_pref_buffer[i].altclass = (char) NO_REGS;
2239 /* If {pref,alt}class have already been allocated, update the pointers to
2240 the newly realloced ones. */
2242 reg_pref = reg_pref_buffer;
2245 reg_renumber = renumber;
2247 /* Tell the regset code about the new number of registers */
2248 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2251 /* Free up the space allocated by allocate_reg_info. */
2257 struct reg_info_data *reg_data;
2258 struct reg_info_data *reg_next;
2260 VARRAY_FREE (reg_n_info);
2261 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2263 reg_next = reg_data->next;
2264 free ((char *)reg_data);
2267 free (reg_pref_buffer);
2268 reg_pref_buffer = (struct reg_pref *)0;
2269 reg_info_head = (struct reg_info_data *)0;
2270 renumber = (short *)0;
2272 regno_allocated = 0;
2276 /* This is the `regscan' pass of the compiler, run just before cse
2277 and again just before loop.
2279 It finds the first and last use of each pseudo-register
2280 and records them in the vectors regno_first_uid, regno_last_uid
2281 and counts the number of sets in the vector reg_n_sets.
2283 REPEAT is nonzero the second time this is called. */
2285 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2286 Always at least 3, since the combiner could put that many together
2287 and we want this to remain correct for all the remaining passes.
2288 This corresponds to the maximum number of times note_stores will call
2289 a function for any insn. */
2293 /* Used as a temporary to record the largest number of registers in
2294 PARALLEL in a SET_DEST. This is added to max_parallel. */
2296 static int max_set_parallel;
2299 reg_scan (f, nregs, repeat)
2302 int repeat ATTRIBUTE_UNUSED;
2306 allocate_reg_info (nregs, TRUE, FALSE);
2308 max_set_parallel = 0;
2310 for (insn = f; insn; insn = NEXT_INSN (insn))
2311 if (GET_CODE (insn) == INSN
2312 || GET_CODE (insn) == CALL_INSN
2313 || GET_CODE (insn) == JUMP_INSN)
2315 if (GET_CODE (PATTERN (insn)) == PARALLEL
2316 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2317 max_parallel = XVECLEN (PATTERN (insn), 0);
2318 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2320 if (REG_NOTES (insn))
2321 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2324 max_parallel += max_set_parallel;
2327 /* Update 'regscan' information by looking at the insns
2328 from FIRST to LAST. Some new REGs have been created,
2329 and any REG with number greater than OLD_MAX_REGNO is
2330 such a REG. We only update information for those. */
2333 reg_scan_update (first, last, old_max_regno)
2336 unsigned int old_max_regno;
2340 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2342 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2343 if (GET_CODE (insn) == INSN
2344 || GET_CODE (insn) == CALL_INSN
2345 || GET_CODE (insn) == JUMP_INSN)
2347 if (GET_CODE (PATTERN (insn)) == PARALLEL
2348 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2349 max_parallel = XVECLEN (PATTERN (insn), 0);
2350 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2352 if (REG_NOTES (insn))
2353 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2357 /* X is the expression to scan. INSN is the insn it appears in.
2358 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2359 We should only record information for REGs with numbers
2360 greater than or equal to MIN_REGNO. */
2363 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2367 unsigned int min_regno;
2369 register enum rtx_code code;
2373 code = GET_CODE (x);
2389 unsigned int regno = REGNO (x);
2391 if (regno >= min_regno)
2393 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2395 REGNO_LAST_UID (regno) = INSN_UID (insn);
2396 if (REGNO_FIRST_UID (regno) == 0)
2397 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2404 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2406 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2411 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2415 /* Count a set of the destination if it is a register. */
2416 for (dest = SET_DEST (x);
2417 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2418 || GET_CODE (dest) == ZERO_EXTEND;
2419 dest = XEXP (dest, 0))
2422 /* For a PARALLEL, record the number of things (less the usual one for a
2423 SET) that are set. */
2424 if (GET_CODE (dest) == PARALLEL)
2425 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2427 if (GET_CODE (dest) == REG
2428 && REGNO (dest) >= min_regno)
2429 REG_N_SETS (REGNO (dest))++;
2431 /* If this is setting a pseudo from another pseudo or the sum of a
2432 pseudo and a constant integer and the other pseudo is known to be
2433 a pointer, set the destination to be a pointer as well.
2435 Likewise if it is setting the destination from an address or from a
2436 value equivalent to an address or to the sum of an address and
2439 But don't do any of this if the pseudo corresponds to a user
2440 variable since it should have already been set as a pointer based
2443 if (GET_CODE (SET_DEST (x)) == REG
2444 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2445 && REGNO (SET_DEST (x)) >= min_regno
2446 /* If the destination pseudo is set more than once, then other
2447 sets might not be to a pointer value (consider access to a
2448 union in two threads of control in the presense of global
2449 optimizations). So only set REG_POINTER on the destination
2450 pseudo if this is the only set of that pseudo. */
2451 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2452 && ! REG_USERVAR_P (SET_DEST (x))
2453 && ! REG_POINTER (SET_DEST (x))
2454 && ((GET_CODE (SET_SRC (x)) == REG
2455 && REG_POINTER (SET_SRC (x)))
2456 || ((GET_CODE (SET_SRC (x)) == PLUS
2457 || GET_CODE (SET_SRC (x)) == LO_SUM)
2458 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2459 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2460 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2461 || GET_CODE (SET_SRC (x)) == CONST
2462 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2463 || GET_CODE (SET_SRC (x)) == LABEL_REF
2464 || (GET_CODE (SET_SRC (x)) == HIGH
2465 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2466 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2467 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2468 || ((GET_CODE (SET_SRC (x)) == PLUS
2469 || GET_CODE (SET_SRC (x)) == LO_SUM)
2470 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2471 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2472 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2473 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2474 && (GET_CODE (XEXP (note, 0)) == CONST
2475 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2476 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2477 REG_POINTER (SET_DEST (x)) = 1;
2479 /* ... fall through ... */
2483 register const char *fmt = GET_RTX_FORMAT (code);
2485 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2488 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2489 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2492 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2493 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2500 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2504 reg_class_subset_p (c1, c2)
2505 register enum reg_class c1;
2506 register enum reg_class c2;
2508 if (c1 == c2) return 1;
2513 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2514 reg_class_contents[(int)c2],
2519 /* Return nonzero if there is a register that is in both C1 and C2. */
2522 reg_classes_intersect_p (c1, c2)
2523 register enum reg_class c1;
2524 register enum reg_class c2;
2531 if (c1 == c2) return 1;
2533 if (c1 == ALL_REGS || c2 == ALL_REGS)
2536 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2537 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2539 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2546 /* Release any memory allocated by register sets. */
2549 regset_release_memory ()
2551 bitmap_release_memory ();