1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
43 #include "diagnostic-core.h"
48 #include "tree-pass.h"
52 static int reload_cse_noop_set_p (rtx);
53 static void reload_cse_simplify (rtx, rtx);
54 static void reload_cse_regs_1 (rtx);
55 static int reload_cse_simplify_set (rtx, rtx);
56 static int reload_cse_simplify_operands (rtx, rtx);
58 static void reload_combine (void);
59 static void reload_combine_note_use (rtx *, rtx, int, rtx);
60 static void reload_combine_note_store (rtx, const_rtx, void *);
62 static bool reload_cse_move2add (rtx);
63 static void move2add_note_store (rtx, const_rtx, void *);
65 /* Call cse / combine like post-reload optimization phases.
66 FIRST is the first instruction. */
68 reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
71 reload_cse_regs_1 (first);
73 moves_converted = reload_cse_move2add (first);
74 if (flag_expensive_optimizations)
78 reload_cse_regs_1 (first);
82 /* See whether a single set SET is a noop. */
84 reload_cse_noop_set_p (rtx set)
86 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
89 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
92 /* Try to simplify INSN. */
94 reload_cse_simplify (rtx insn, rtx testreg)
96 rtx body = PATTERN (insn);
98 if (GET_CODE (body) == SET)
102 /* Simplify even if we may think it is a no-op.
103 We may think a memory load of a value smaller than WORD_SIZE
104 is redundant because we haven't taken into account possible
105 implicit extension. reload_cse_simplify_set() will bring
106 this out, so it's safer to simplify before we delete. */
107 count += reload_cse_simplify_set (body, insn);
109 if (!count && reload_cse_noop_set_p (body))
111 rtx value = SET_DEST (body);
113 && ! REG_FUNCTION_VALUE_P (value))
115 delete_insn_and_edges (insn);
120 apply_change_group ();
122 reload_cse_simplify_operands (insn, testreg);
124 else if (GET_CODE (body) == PARALLEL)
128 rtx value = NULL_RTX;
130 /* Registers mentioned in the clobber list for an asm cannot be reused
131 within the body of the asm. Invalidate those registers now so that
132 we don't try to substitute values for them. */
133 if (asm_noperands (body) >= 0)
135 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
137 rtx part = XVECEXP (body, 0, i);
138 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
139 cselib_invalidate_rtx (XEXP (part, 0));
143 /* If every action in a PARALLEL is a noop, we can delete
144 the entire PARALLEL. */
145 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
147 rtx part = XVECEXP (body, 0, i);
148 if (GET_CODE (part) == SET)
150 if (! reload_cse_noop_set_p (part))
152 if (REG_P (SET_DEST (part))
153 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
157 value = SET_DEST (part);
160 else if (GET_CODE (part) != CLOBBER)
166 delete_insn_and_edges (insn);
167 /* We're done with this insn. */
171 /* It's not a no-op, but we can try to simplify it. */
172 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
173 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
174 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
177 apply_change_group ();
179 reload_cse_simplify_operands (insn, testreg);
183 /* Do a very simple CSE pass over the hard registers.
185 This function detects no-op moves where we happened to assign two
186 different pseudo-registers to the same hard register, and then
187 copied one to the other. Reload will generate a useless
188 instruction copying a register to itself.
190 This function also detects cases where we load a value from memory
191 into two different registers, and (if memory is more expensive than
192 registers) changes it to simply copy the first register into the
195 Another optimization is performed that scans the operands of each
196 instruction to see whether the value is already available in a
197 hard register. It then replaces the operand with the hard register
198 if possible, much like an optional reload would. */
201 reload_cse_regs_1 (rtx first)
204 rtx testreg = gen_rtx_REG (VOIDmode, -1);
206 cselib_init (CSELIB_RECORD_MEMORY);
207 init_alias_analysis ();
209 for (insn = first; insn; insn = NEXT_INSN (insn))
212 reload_cse_simplify (insn, testreg);
214 cselib_process_insn (insn);
218 end_alias_analysis ();
222 /* Try to simplify a single SET instruction. SET is the set pattern.
223 INSN is the instruction it came from.
224 This function only handles one case: if we set a register to a value
225 which is not a register, we try to find that value in some other register
226 and change the set into a register copy. */
229 reload_cse_simplify_set (rtx set, rtx insn)
234 enum reg_class dclass;
237 struct elt_loc_list *l;
238 #ifdef LOAD_EXTEND_OP
239 enum rtx_code extend_op = UNKNOWN;
241 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
243 dreg = true_regnum (SET_DEST (set));
248 if (side_effects_p (src) || true_regnum (src) >= 0)
251 dclass = REGNO_REG_CLASS (dreg);
253 #ifdef LOAD_EXTEND_OP
254 /* When replacing a memory with a register, we need to honor assumptions
255 that combine made wrt the contents of sign bits. We'll do this by
256 generating an extend instruction instead of a reg->reg copy. Thus
257 the destination must be a register that we can widen. */
259 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
260 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
261 && !REG_P (SET_DEST (set)))
265 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
269 /* If memory loads are cheaper than register copies, don't change them. */
271 old_cost = memory_move_cost (GET_MODE (src), dclass, true);
272 else if (REG_P (src))
273 old_cost = register_move_cost (GET_MODE (src),
274 REGNO_REG_CLASS (REGNO (src)), dclass);
276 old_cost = rtx_cost (src, SET, speed);
278 for (l = val->locs; l; l = l->next)
280 rtx this_rtx = l->loc;
283 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
285 #ifdef LOAD_EXTEND_OP
286 if (extend_op != UNKNOWN)
288 HOST_WIDE_INT this_val;
290 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
291 constants, such as SYMBOL_REF, cannot be extended. */
292 if (!CONST_INT_P (this_rtx))
295 this_val = INTVAL (this_rtx);
299 this_val &= GET_MODE_MASK (GET_MODE (src));
302 /* ??? In theory we're already extended. */
303 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
308 this_rtx = GEN_INT (this_val);
311 this_cost = rtx_cost (this_rtx, SET, speed);
313 else if (REG_P (this_rtx))
315 #ifdef LOAD_EXTEND_OP
316 if (extend_op != UNKNOWN)
318 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
319 this_cost = rtx_cost (this_rtx, SET, speed);
323 this_cost = register_move_cost (GET_MODE (this_rtx),
324 REGNO_REG_CLASS (REGNO (this_rtx)),
330 /* If equal costs, prefer registers over anything else. That
331 tends to lead to smaller instructions on some machines. */
332 if (this_cost < old_cost
333 || (this_cost == old_cost
335 && !REG_P (SET_SRC (set))))
337 #ifdef LOAD_EXTEND_OP
338 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
339 && extend_op != UNKNOWN
340 #ifdef CANNOT_CHANGE_MODE_CLASS
341 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
343 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
347 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
348 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
349 validate_change (insn, &SET_DEST (set), wide_dest, 1);
353 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
354 old_cost = this_cost, did_change = 1;
361 /* Try to replace operands in INSN with equivalent values that are already
362 in registers. This can be viewed as optional reloading.
364 For each non-register operand in the insn, see if any hard regs are
365 known to be equivalent to that operand. Record the alternatives which
366 can accept these hard registers. Among all alternatives, select the
367 ones which are better or equal to the one currently matching, where
368 "better" is in terms of '?' and '!' constraints. Among the remaining
369 alternatives, select the one which replaces most operands with
373 reload_cse_simplify_operands (rtx insn, rtx testreg)
377 /* For each operand, all registers that are equivalent to it. */
378 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
380 const char *constraints[MAX_RECOG_OPERANDS];
382 /* Vector recording how bad an alternative is. */
383 int *alternative_reject;
384 /* Vector recording how many registers can be introduced by choosing
386 int *alternative_nregs;
387 /* Array of vectors recording, for each operand and each alternative,
388 which hard register to substitute, or -1 if the operand should be
390 int *op_alt_regno[MAX_RECOG_OPERANDS];
391 /* Array of alternatives, sorted in order of decreasing desirability. */
392 int *alternative_order;
396 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
399 /* Figure out which alternative currently matches. */
400 if (! constrain_operands (1))
401 fatal_insn_not_found (insn);
403 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
404 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
405 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
406 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
407 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
409 /* For each operand, find out which regs are equivalent. */
410 for (i = 0; i < recog_data.n_operands; i++)
413 struct elt_loc_list *l;
416 CLEAR_HARD_REG_SET (equiv_regs[i]);
418 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
419 right, so avoid the problem here. Likewise if we have a constant
420 and the insn pattern doesn't tell us the mode we need. */
421 if (LABEL_P (recog_data.operand[i])
422 || (CONSTANT_P (recog_data.operand[i])
423 && recog_data.operand_mode[i] == VOIDmode))
426 op = recog_data.operand[i];
427 #ifdef LOAD_EXTEND_OP
429 && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
430 && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
432 rtx set = single_set (insn);
434 /* We might have multiple sets, some of which do implicit
435 extension. Punt on this for now. */
438 /* If the destination is also a MEM or a STRICT_LOW_PART, no
440 Also, if there is an explicit extension, we don't have to
441 worry about an implicit one. */
442 else if (MEM_P (SET_DEST (set))
443 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
444 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND
445 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
446 ; /* Continue ordinary processing. */
447 #ifdef CANNOT_CHANGE_MODE_CLASS
448 /* If the register cannot change mode to word_mode, it follows that
449 it cannot have been used in word_mode. */
450 else if (REG_P (SET_DEST (set))
451 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
453 REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
454 ; /* Continue ordinary processing. */
456 /* If this is a straight load, make the extension explicit. */
457 else if (REG_P (SET_DEST (set))
458 && recog_data.n_operands == 2
459 && SET_SRC (set) == op
460 && SET_DEST (set) == recog_data.operand[1-i])
462 validate_change (insn, recog_data.operand_loc[i],
463 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)),
466 validate_change (insn, recog_data.operand_loc[1-i],
467 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
469 if (! apply_change_group ())
471 return reload_cse_simplify_operands (insn, testreg);
474 /* ??? There might be arithmetic operations with memory that are
475 safe to optimize, but is it worth the trouble? */
478 #endif /* LOAD_EXTEND_OP */
479 v = cselib_lookup (op, recog_data.operand_mode[i], 0);
483 for (l = v->locs; l; l = l->next)
485 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
488 for (i = 0; i < recog_data.n_operands; i++)
490 enum machine_mode mode;
494 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
495 for (j = 0; j < recog_data.n_alternatives; j++)
496 op_alt_regno[i][j] = -1;
498 p = constraints[i] = recog_data.constraints[i];
499 mode = recog_data.operand_mode[i];
501 /* Add the reject values for each alternative given by the constraints
510 alternative_reject[j] += 3;
512 alternative_reject[j] += 300;
515 /* We won't change operands which are already registers. We
516 also don't want to modify output operands. */
517 regno = true_regnum (recog_data.operand[i]);
519 || constraints[i][0] == '='
520 || constraints[i][0] == '+')
523 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
525 enum reg_class rclass = NO_REGS;
527 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
530 SET_REGNO (testreg, regno);
531 PUT_MODE (testreg, mode);
533 /* We found a register equal to this operand. Now look for all
534 alternatives that can accept this register and have not been
535 assigned a register they can use yet. */
544 case '=': case '+': case '?':
545 case '#': case '&': case '!':
547 case '0': case '1': case '2': case '3': case '4':
548 case '5': case '6': case '7': case '8': case '9':
549 case '<': case '>': case 'V': case 'o':
550 case 'E': case 'F': case 'G': case 'H':
551 case 's': case 'i': case 'n':
552 case 'I': case 'J': case 'K': case 'L':
553 case 'M': case 'N': case 'O': case 'P':
554 case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
555 /* These don't say anything we care about. */
559 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
564 = (reg_class_subunion
566 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
570 /* See if REGNO fits this alternative, and set it up as the
571 replacement register if we don't have one for this
572 alternative yet and the operand being replaced is not
573 a cheap CONST_INT. */
574 if (op_alt_regno[i][j] == -1
575 && reg_fits_class_p (testreg, rclass, 0, mode)
576 && (!CONST_INT_P (recog_data.operand[i])
577 || (rtx_cost (recog_data.operand[i], SET,
578 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
579 > rtx_cost (testreg, SET,
580 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))))))
582 alternative_nregs[j]++;
583 op_alt_regno[i][j] = regno;
589 p += CONSTRAINT_LEN (c, p);
597 /* Record all alternatives which are better or equal to the currently
598 matching one in the alternative_order array. */
599 for (i = j = 0; i < recog_data.n_alternatives; i++)
600 if (alternative_reject[i] <= alternative_reject[which_alternative])
601 alternative_order[j++] = i;
602 recog_data.n_alternatives = j;
604 /* Sort it. Given a small number of alternatives, a dumb algorithm
605 won't hurt too much. */
606 for (i = 0; i < recog_data.n_alternatives - 1; i++)
609 int best_reject = alternative_reject[alternative_order[i]];
610 int best_nregs = alternative_nregs[alternative_order[i]];
613 for (j = i + 1; j < recog_data.n_alternatives; j++)
615 int this_reject = alternative_reject[alternative_order[j]];
616 int this_nregs = alternative_nregs[alternative_order[j]];
618 if (this_reject < best_reject
619 || (this_reject == best_reject && this_nregs > best_nregs))
622 best_reject = this_reject;
623 best_nregs = this_nregs;
627 tmp = alternative_order[best];
628 alternative_order[best] = alternative_order[i];
629 alternative_order[i] = tmp;
632 /* Substitute the operands as determined by op_alt_regno for the best
634 j = alternative_order[0];
636 for (i = 0; i < recog_data.n_operands; i++)
638 enum machine_mode mode = recog_data.operand_mode[i];
639 if (op_alt_regno[i][j] == -1)
642 validate_change (insn, recog_data.operand_loc[i],
643 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
646 for (i = recog_data.n_dups - 1; i >= 0; i--)
648 int op = recog_data.dup_num[i];
649 enum machine_mode mode = recog_data.operand_mode[op];
651 if (op_alt_regno[op][j] == -1)
654 validate_change (insn, recog_data.dup_loc[i],
655 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
658 return apply_change_group ();
661 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
663 This code might also be useful when reload gave up on reg+reg addressing
664 because of clashes between the return register and INDEX_REG_CLASS. */
666 /* The maximum number of uses of a register we can keep track of to
667 replace them with reg+reg addressing. */
668 #define RELOAD_COMBINE_MAX_USES 16
670 /* Describes a recorded use of a register. */
673 /* The insn where a register has been used. */
675 /* Points to the memory reference enclosing the use, if any, NULL_RTX
678 /* Location of the register withing INSN. */
680 /* The reverse uid of the insn. */
684 /* If the register is used in some unknown fashion, USE_INDEX is negative.
685 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
686 indicates where it is first set or clobbered.
687 Otherwise, USE_INDEX is the index of the last encountered use of the
688 register (which is first among these we have seen since we scan backwards).
689 USE_RUID indicates the first encountered, i.e. last, of these uses.
690 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
691 with a constant offset; OFFSET contains this constant in that case.
692 STORE_RUID is always meaningful if we only want to use a value in a
693 register in a different place: it denotes the next insn in the insn
694 stream (i.e. the last encountered) that sets or clobbers the register.
695 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
698 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
704 bool all_offsets_match;
705 } reg_state[FIRST_PSEUDO_REGISTER];
707 /* Reverse linear uid. This is increased in reload_combine while scanning
708 the instructions from last to first. It is used to set last_label_ruid
709 and the store_ruid / use_ruid fields in reg_state. */
710 static int reload_combine_ruid;
712 /* The RUID of the last label we encountered in reload_combine. */
713 static int last_label_ruid;
715 /* The RUID of the last jump we encountered in reload_combine. */
716 static int last_jump_ruid;
718 /* The register numbers of the first and last index register. A value of
719 -1 in LAST_INDEX_REG indicates that we've previously computed these
720 values and found no suitable index registers. */
721 static int first_index_reg = -1;
722 static int last_index_reg;
724 #define LABEL_LIVE(LABEL) \
725 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
727 /* Subroutine of reload_combine_split_ruids, called to fix up a single
728 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
731 reload_combine_split_one_ruid (int *pruid, int split_ruid)
733 if (*pruid > split_ruid)
737 /* Called when we insert a new insn in a position we've already passed in
738 the scan. Examine all our state, increasing all ruids that are higher
739 than SPLIT_RUID by one in order to make room for a new insn. */
742 reload_combine_split_ruids (int split_ruid)
746 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
747 reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
748 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
750 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
752 int j, idx = reg_state[i].use_index;
753 reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid);
754 reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid);
755 reload_combine_split_one_ruid (®_state[i].real_store_ruid,
759 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
761 reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid,
767 /* Called when we are about to rescan a previously encountered insn with
768 reload_combine_note_use after modifying some part of it. This clears all
769 information about uses in that particular insn. */
772 reload_combine_purge_insn_uses (rtx insn)
776 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
778 int j, k, idx = reg_state[i].use_index;
781 j = k = RELOAD_COMBINE_MAX_USES;
784 if (reg_state[i].reg_use[j].insn != insn)
788 reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
791 reg_state[i].use_index = k;
795 /* Called when we need to forget about all uses of REGNO after an insn
796 which is identified by RUID. */
799 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
801 int j, k, idx = reg_state[regno].use_index;
804 j = k = RELOAD_COMBINE_MAX_USES;
807 if (reg_state[regno].reg_use[j].ruid >= ruid)
811 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
814 reg_state[regno].use_index = k;
817 /* Find the use of REGNO with the ruid that is highest among those
818 lower than RUID_LIMIT, and return it if it is the only use of this
819 reg in the insn (or if the insn is a debug insn). Return NULL
822 static struct reg_use *
823 reload_combine_closest_single_use (unsigned regno, int ruid_limit)
825 int i, best_ruid = 0;
826 int use_idx = reg_state[regno].use_index;
827 struct reg_use *retval;
832 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
834 struct reg_use *use = reg_state[regno].reg_use + i;
835 int this_ruid = use->ruid;
836 if (this_ruid >= ruid_limit)
838 if (this_ruid > best_ruid)
840 best_ruid = this_ruid;
841 retval = reg_state[regno].reg_use + i;
843 else if (this_ruid == best_ruid && !DEBUG_INSN_P (use->insn))
846 if (last_label_ruid >= best_ruid)
851 /* After we've moved an add insn, fix up any debug insns that occur
852 between the old location of the add and the new location. REG is
853 the destination register of the add insn; REPLACEMENT is the
854 SET_SRC of the add. FROM and TO specify the range in which we
855 should make this change on debug insns. */
858 fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
861 for (insn = from; insn != to; insn = NEXT_INSN (insn))
865 if (!DEBUG_INSN_P (insn))
868 t = INSN_VAR_LOCATION_LOC (insn);
869 t = simplify_replace_rtx (t, reg, copy_rtx (replacement));
870 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
874 /* Called by reload_combine when scanning INSN. This function tries to detect
875 patterns where a constant is added to a register, and the result is used
877 Return true if no further processing is needed on INSN; false if it wasn't
878 recognized and should be handled normally. */
881 reload_combine_recognize_const_pattern (rtx insn)
883 int from_ruid = reload_combine_ruid;
884 rtx set, pat, reg, src, addreg;
888 rtx add_moved_after_insn = NULL_RTX;
889 int add_moved_after_ruid = 0;
890 int clobbered_regno = -1;
892 set = single_set (insn);
896 reg = SET_DEST (set);
899 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
900 || GET_MODE (reg) != Pmode
901 || reg == stack_pointer_rtx)
906 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
907 uses of REG1 inside an address, or inside another add insn. If
908 possible and profitable, merge the addition into subsequent
910 if (GET_CODE (src) != PLUS
911 || !REG_P (XEXP (src, 0))
912 || !CONSTANT_P (XEXP (src, 1)))
915 addreg = XEXP (src, 0);
916 must_move_add = rtx_equal_p (reg, addreg);
918 pat = PATTERN (insn);
919 if (must_move_add && set != pat)
921 /* We have to be careful when moving the add; apart from the
922 single_set there may also be clobbers. Recognize one special
923 case, that of one clobber alongside the set (likely a clobber
924 of the CC register). */
925 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
926 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
927 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
928 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
930 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
935 use = reload_combine_closest_single_use (regno, from_ruid);
938 /* Start the search for the next use from here. */
939 from_ruid = use->ruid;
941 /* We'll fix up DEBUG_INSNs after we're done. */
942 if (use && DEBUG_INSN_P (use->insn))
945 if (use && GET_MODE (*use->usep) == Pmode)
947 rtx use_insn = use->insn;
948 int use_ruid = use->ruid;
949 rtx mem = use->containing_mem;
950 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
952 /* Avoid moving the add insn past a jump. */
953 if (must_move_add && use_ruid <= last_jump_ruid)
956 /* If the add clobbers another hard reg in parallel, don't move
957 it past a real set of this hard reg. */
958 if (must_move_add && clobbered_regno >= 0
959 && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
962 /* Avoid moving a use of ADDREG past a point where it
964 if (reg_state[REGNO (addreg)].store_ruid >= use_ruid)
969 addr_space_t as = MEM_ADDR_SPACE (mem);
970 rtx oldaddr = XEXP (mem, 0);
971 rtx newaddr = NULL_RTX;
972 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
975 newaddr = simplify_replace_rtx (oldaddr, reg, copy_rtx (src));
976 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
978 XEXP (mem, 0) = newaddr;
979 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
980 XEXP (mem, 0) = oldaddr;
981 if (new_cost <= old_cost
982 && validate_change (use_insn,
983 &XEXP (mem, 0), newaddr, 0))
985 reload_combine_purge_insn_uses (use_insn);
986 reload_combine_note_use (&PATTERN (use_insn), use_insn,
991 add_moved_after_insn = use_insn;
992 add_moved_after_ruid = use_ruid;
1000 rtx new_set = single_set (use_insn);
1002 && REG_P (SET_DEST (new_set))
1003 && GET_CODE (SET_SRC (new_set)) == PLUS
1004 && REG_P (XEXP (SET_SRC (new_set), 0))
1005 && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
1008 int old_cost = rtx_cost (SET_SRC (new_set), SET, speed);
1010 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
1011 new_src = simplify_replace_rtx (SET_SRC (new_set), reg,
1014 if (rtx_cost (new_src, SET, speed) <= old_cost
1015 && validate_change (use_insn, &SET_SRC (new_set),
1018 reload_combine_purge_insn_uses (use_insn);
1019 reload_combine_note_use (&SET_SRC (new_set), use_insn,
1020 use_ruid, NULL_RTX);
1024 /* See if that took care of the add insn. */
1025 if (rtx_equal_p (SET_DEST (new_set), reg))
1032 add_moved_after_insn = use_insn;
1033 add_moved_after_ruid = use_ruid;
1040 /* If we get here, we couldn't handle this use. */
1047 if (!must_move_add || add_moved_after_insn == NULL_RTX)
1048 /* Process the add normally. */
1051 fixup_debug_insns (reg, src, insn, add_moved_after_insn);
1053 reorder_insns (insn, insn, add_moved_after_insn);
1054 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
1055 reload_combine_split_ruids (add_moved_after_ruid - 1);
1056 reload_combine_note_use (&PATTERN (insn), insn,
1057 add_moved_after_ruid, NULL_RTX);
1058 reg_state[regno].store_ruid = add_moved_after_ruid;
1063 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1064 can handle and improve. Return true if no further processing is needed on
1065 INSN; false if it wasn't recognized and should be handled normally. */
1068 reload_combine_recognize_pattern (rtx insn)
1073 set = single_set (insn);
1074 if (set == NULL_RTX)
1077 reg = SET_DEST (set);
1078 src = SET_SRC (set);
1080 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
1083 regno = REGNO (reg);
1085 /* Look for (set (REGX) (CONST_INT))
1086 (set (REGX) (PLUS (REGX) (REGY)))
1088 ... (MEM (REGX)) ...
1090 (set (REGZ) (CONST_INT))
1092 ... (MEM (PLUS (REGZ) (REGY)))... .
1094 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1095 and that we know all uses of REGX before it dies.
1096 Also, explicitly check that REGX != REGY; our life information
1097 does not yet show whether REGY changes in this insn. */
1099 if (GET_CODE (src) == PLUS
1100 && reg_state[regno].all_offsets_match
1101 && last_index_reg != -1
1102 && REG_P (XEXP (src, 1))
1103 && rtx_equal_p (XEXP (src, 0), reg)
1104 && !rtx_equal_p (XEXP (src, 1), reg)
1105 && last_label_ruid < reg_state[regno].use_ruid)
1107 rtx base = XEXP (src, 1);
1108 rtx prev = prev_nonnote_insn (insn);
1109 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1110 rtx index_reg = NULL_RTX;
1111 rtx reg_sum = NULL_RTX;
1114 /* Now we need to set INDEX_REG to an index register (denoted as
1115 REGZ in the illustration above) and REG_SUM to the expression
1116 register+register that we want to use to substitute uses of REG
1117 (typically in MEMs) with. First check REG and BASE for being
1118 index registers; we can use them even if they are not dead. */
1119 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1120 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1128 /* Otherwise, look for a free index register. Since we have
1129 checked above that neither REG nor BASE are index registers,
1130 if we find anything at all, it will be different from these
1132 for (i = first_index_reg; i <= last_index_reg; i++)
1134 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
1135 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1136 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1137 && hard_regno_nregs[i][GET_MODE (reg)] == 1)
1139 index_reg = gen_rtx_REG (GET_MODE (reg), i);
1140 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1146 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1147 (REGY), i.e. BASE, is not clobbered before the last use we'll
1151 && CONST_INT_P (SET_SRC (prev_set))
1152 && rtx_equal_p (SET_DEST (prev_set), reg)
1153 && reg_state[regno].use_index >= 0
1154 && (reg_state[REGNO (base)].store_ruid
1155 <= reg_state[regno].use_ruid))
1157 /* Change destination register and, if necessary, the constant
1158 value in PREV, the constant loading instruction. */
1159 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1160 if (reg_state[regno].offset != const0_rtx)
1161 validate_change (prev,
1162 &SET_SRC (prev_set),
1163 GEN_INT (INTVAL (SET_SRC (prev_set))
1164 + INTVAL (reg_state[regno].offset)),
1167 /* Now for every use of REG that we have recorded, replace REG
1169 for (i = reg_state[regno].use_index;
1170 i < RELOAD_COMBINE_MAX_USES; i++)
1171 validate_unshare_change (reg_state[regno].reg_use[i].insn,
1172 reg_state[regno].reg_use[i].usep,
1173 /* Each change must have its own
1177 if (apply_change_group ())
1179 struct reg_use *lowest_ruid = NULL;
1181 /* For every new use of REG_SUM, we have to record the use
1182 of BASE therein, i.e. operand 1. */
1183 for (i = reg_state[regno].use_index;
1184 i < RELOAD_COMBINE_MAX_USES; i++)
1186 struct reg_use *use = reg_state[regno].reg_use + i;
1187 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
1188 use->ruid, use->containing_mem);
1189 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
1193 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
1195 /* Delete the reg-reg addition. */
1198 if (reg_state[regno].offset != const0_rtx)
1199 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1201 remove_reg_equal_equiv_notes (prev);
1203 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1204 reg_state[REGNO (index_reg)].store_ruid
1205 = reload_combine_ruid;
1214 reload_combine (void)
1220 int min_labelno, n_labels;
1221 HARD_REG_SET ever_live_at_start, *label_live;
1223 /* To avoid wasting too much time later searching for an index register,
1224 determine the minimum and maximum index register numbers. */
1225 if (INDEX_REG_CLASS == NO_REGS)
1226 last_index_reg = -1;
1227 else if (first_index_reg == -1 && last_index_reg == 0)
1229 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1230 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1232 if (first_index_reg == -1)
1233 first_index_reg = r;
1238 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1239 to -1 so we'll know to quit early the next time we get here. */
1240 if (first_index_reg == -1)
1242 last_index_reg = -1;
1248 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
1249 reload has already used it where appropriate, so there is no use in
1250 trying to generate it now. */
1251 if (double_reg_address_ok || last_index_reg == -1)
1255 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1256 information is a bit fuzzy immediately after reload, but it's
1257 still good enough to determine which registers are live at a jump
1259 min_labelno = get_first_label_num ();
1260 n_labels = max_label_num () - min_labelno;
1261 label_live = XNEWVEC (HARD_REG_SET, n_labels);
1262 CLEAR_HARD_REG_SET (ever_live_at_start);
1264 FOR_EACH_BB_REVERSE (bb)
1266 insn = BB_HEAD (bb);
1270 bitmap live_in = df_get_live_in (bb);
1272 REG_SET_TO_HARD_REG_SET (live, live_in);
1273 compute_use_by_pseudos (&live, live_in);
1274 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
1275 IOR_HARD_REG_SET (ever_live_at_start, live);
1279 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1280 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1281 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1283 reg_state[r].store_ruid = 0;
1284 reg_state[r].real_store_ruid = 0;
1286 reg_state[r].use_index = -1;
1288 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1291 for (insn = get_last_insn (); insn; insn = prev)
1295 prev = PREV_INSN (insn);
1297 /* We cannot do our optimization across labels. Invalidating all the use
1298 information we have would be costly, so we just note where the label
1299 is and then later disable any optimization that would cross it. */
1301 last_label_ruid = reload_combine_ruid;
1302 else if (BARRIER_P (insn))
1303 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1304 if (! fixed_regs[r])
1305 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1307 if (! NONDEBUG_INSN_P (insn))
1310 reload_combine_ruid++;
1312 if (control_flow_insn_p (insn))
1313 last_jump_ruid = reload_combine_ruid;
1315 if (reload_combine_recognize_const_pattern (insn)
1316 || reload_combine_recognize_pattern (insn))
1319 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
1325 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1326 if (call_used_regs[r])
1328 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1329 reg_state[r].store_ruid = reload_combine_ruid;
1332 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
1333 link = XEXP (link, 1))
1335 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
1336 if (REG_P (usage_rtx))
1339 unsigned int start_reg = REGNO (usage_rtx);
1340 unsigned int num_regs =
1341 hard_regno_nregs[start_reg][GET_MODE (usage_rtx)];
1342 unsigned int end_reg = start_reg + num_regs - 1;
1343 for (i = start_reg; i <= end_reg; i++)
1344 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
1346 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1347 reg_state[i].store_ruid = reload_combine_ruid;
1350 reg_state[i].use_index = -1;
1355 else if (JUMP_P (insn)
1356 && GET_CODE (PATTERN (insn)) != RETURN)
1358 /* Non-spill registers might be used at the call destination in
1359 some unknown fashion, so we have to mark the unknown use. */
1362 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
1363 && JUMP_LABEL (insn))
1364 live = &LABEL_LIVE (JUMP_LABEL (insn));
1366 live = &ever_live_at_start;
1368 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
1369 if (TEST_HARD_REG_BIT (*live, i))
1370 reg_state[i].use_index = -1;
1373 reload_combine_note_use (&PATTERN (insn), insn,
1374 reload_combine_ruid, NULL_RTX);
1375 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1377 if (REG_NOTE_KIND (note) == REG_INC
1378 && REG_P (XEXP (note, 0)))
1380 int regno = REGNO (XEXP (note, 0));
1382 reg_state[regno].store_ruid = reload_combine_ruid;
1383 reg_state[regno].real_store_ruid = reload_combine_ruid;
1384 reg_state[regno].use_index = -1;
1392 /* Check if DST is a register or a subreg of a register; if it is,
1393 update store_ruid, real_store_ruid and use_index in the reg_state
1394 structure accordingly. Called via note_stores from reload_combine. */
1397 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1401 enum machine_mode mode = GET_MODE (dst);
1403 if (GET_CODE (dst) == SUBREG)
1405 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
1406 GET_MODE (SUBREG_REG (dst)),
1409 dst = SUBREG_REG (dst);
1413 regno += REGNO (dst);
1415 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1416 careful with registers / register parts that are not full words.
1417 Similarly for ZERO_EXTRACT. */
1418 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1419 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1421 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1423 reg_state[i].use_index = -1;
1424 reg_state[i].store_ruid = reload_combine_ruid;
1425 reg_state[i].real_store_ruid = reload_combine_ruid;
1430 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1432 reg_state[i].store_ruid = reload_combine_ruid;
1433 if (GET_CODE (set) == SET)
1434 reg_state[i].real_store_ruid = reload_combine_ruid;
1435 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1440 /* XP points to a piece of rtl that has to be checked for any uses of
1442 *XP is the pattern of INSN, or a part of it.
1443 Called from reload_combine, and recursively by itself. */
1445 reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
1448 enum rtx_code code = x->code;
1451 rtx offset = const0_rtx; /* For the REG case below. */
1456 if (REG_P (SET_DEST (x)))
1458 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1464 /* If this is the USE of a return value, we can't change it. */
1465 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
1467 /* Mark the return register as used in an unknown fashion. */
1468 rtx reg = XEXP (x, 0);
1469 int regno = REGNO (reg);
1470 int nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1472 while (--nregs >= 0)
1473 reg_state[regno + nregs].use_index = -1;
1479 if (REG_P (SET_DEST (x)))
1481 /* No spurious CLOBBERs of pseudo registers may remain. */
1482 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER);
1488 /* We are interested in (plus (reg) (const_int)) . */
1489 if (!REG_P (XEXP (x, 0))
1490 || !CONST_INT_P (XEXP (x, 1)))
1492 offset = XEXP (x, 1);
1497 int regno = REGNO (x);
1501 /* No spurious USEs of pseudo registers may remain. */
1502 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
1504 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1506 /* We can't substitute into multi-hard-reg uses. */
1509 while (--nregs >= 0)
1510 reg_state[regno + nregs].use_index = -1;
1514 /* If this register is already used in some unknown fashion, we
1516 If we decrement the index from zero to -1, we can't store more
1517 uses, so this register becomes used in an unknown fashion. */
1518 use_index = --reg_state[regno].use_index;
1522 if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1524 /* This is the first use of this register we have seen since we
1525 marked it as dead. */
1526 reg_state[regno].offset = offset;
1527 reg_state[regno].all_offsets_match = true;
1528 reg_state[regno].use_ruid = ruid;
1532 if (reg_state[regno].use_ruid > ruid)
1533 reg_state[regno].use_ruid = ruid;
1535 if (! rtx_equal_p (offset, reg_state[regno].offset))
1536 reg_state[regno].all_offsets_match = false;
1539 reg_state[regno].reg_use[use_index].insn = insn;
1540 reg_state[regno].reg_use[use_index].ruid = ruid;
1541 reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1542 reg_state[regno].reg_use[use_index].usep = xp;
1554 /* Recursively process the components of X. */
1555 fmt = GET_RTX_FORMAT (code);
1556 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1559 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1560 else if (fmt[i] == 'E')
1562 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1563 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1569 /* See if we can reduce the cost of a constant by replacing a move
1570 with an add. We track situations in which a register is set to a
1571 constant or to a register plus a constant. */
1572 /* We cannot do our optimization across labels. Invalidating all the
1573 information about register contents we have would be costly, so we
1574 use move2add_last_label_luid to note where the label is and then
1575 later disable any optimization that would cross it.
1576 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1577 are only valid if reg_set_luid[n] is greater than
1578 move2add_last_label_luid. */
1579 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
1581 /* If reg_base_reg[n] is negative, register n has been set to
1582 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1583 If reg_base_reg[n] is non-negative, register n has been set to the
1584 sum of reg_offset[n] and the value of register reg_base_reg[n]
1585 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1586 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1587 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
1588 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
1589 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
1591 /* move2add_luid is linearly increased while scanning the instructions
1592 from first to last. It is used to set reg_set_luid in
1593 reload_cse_move2add and move2add_note_store. */
1594 static int move2add_luid;
1596 /* move2add_last_label_luid is set whenever a label is found. Labels
1597 invalidate all previously collected reg_offset data. */
1598 static int move2add_last_label_luid;
1600 /* ??? We don't know how zero / sign extension is handled, hence we
1601 can't go from a narrower to a wider mode. */
1602 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1603 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1604 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1605 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
1606 GET_MODE_BITSIZE (INMODE))))
1608 /* This function is called with INSN that sets REG to (SYM + OFF),
1609 while REG is known to already have value (SYM + offset).
1610 This function tries to change INSN into an add instruction
1611 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1612 It also updates the information about REG's known value.
1613 Return true if we made a change. */
1616 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
1618 rtx pat = PATTERN (insn);
1619 rtx src = SET_SRC (pat);
1620 int regno = REGNO (reg);
1621 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
1623 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1624 bool changed = false;
1626 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1627 use (set (reg) (reg)) instead.
1628 We don't delete this insn, nor do we convert it into a
1629 note, to avoid losing register notes or the return
1630 value flag. jump2 already knows how to get rid of
1632 if (new_src == const0_rtx)
1634 /* If the constants are different, this is a
1635 truncation, that, if turned into (set (reg)
1636 (reg)), would be discarded. Maybe we should
1637 try a truncMN pattern? */
1638 if (INTVAL (off) == reg_offset [regno])
1639 changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1641 else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
1642 && have_add2_insn (reg, new_src))
1644 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1645 changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1647 else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
1649 enum machine_mode narrow_mode;
1650 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
1651 narrow_mode != VOIDmode
1652 && narrow_mode != GET_MODE (reg);
1653 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
1655 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
1656 && ((reg_offset[regno]
1657 & ~GET_MODE_MASK (narrow_mode))
1659 & ~GET_MODE_MASK (narrow_mode))))
1661 rtx narrow_reg = gen_rtx_REG (narrow_mode,
1663 rtx narrow_src = gen_int_mode (INTVAL (off),
1666 gen_rtx_SET (VOIDmode,
1667 gen_rtx_STRICT_LOW_PART (VOIDmode,
1670 changed = validate_change (insn, &PATTERN (insn),
1677 reg_set_luid[regno] = move2add_luid;
1678 reg_base_reg[regno] = -1;
1679 reg_mode[regno] = GET_MODE (reg);
1680 reg_symbol_ref[regno] = sym;
1681 reg_offset[regno] = INTVAL (off);
1686 /* This function is called with INSN that sets REG to (SYM + OFF),
1687 but REG doesn't have known value (SYM + offset). This function
1688 tries to find another register which is known to already have
1689 value (SYM + offset) and change INSN into an add instruction
1690 (set (REG) (plus (the found register) (OFF - offset))) if such
1691 a register is found. It also updates the information about
1693 Return true iff we made a change. */
1696 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
1698 rtx pat = PATTERN (insn);
1699 rtx src = SET_SRC (pat);
1700 int regno = REGNO (reg);
1701 int min_cost = INT_MAX;
1703 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1705 bool changed = false;
1707 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1708 if (reg_set_luid[i] > move2add_last_label_luid
1709 && reg_mode[i] == GET_MODE (reg)
1710 && reg_base_reg[i] < 0
1711 && reg_symbol_ref[i] != NULL_RTX
1712 && rtx_equal_p (sym, reg_symbol_ref[i]))
1714 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i],
1716 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1717 use (set (reg) (reg)) instead.
1718 We don't delete this insn, nor do we convert it into a
1719 note, to avoid losing register notes or the return
1720 value flag. jump2 already knows how to get rid of
1722 if (new_src == const0_rtx)
1730 int cost = rtx_cost (new_src, PLUS, speed);
1731 if (cost < min_cost)
1739 if (min_cost < rtx_cost (src, SET, speed))
1743 tem = gen_rtx_REG (GET_MODE (reg), min_regno);
1746 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno],
1748 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1750 if (validate_change (insn, &SET_SRC (pat), tem, 0))
1753 reg_set_luid[regno] = move2add_luid;
1754 reg_base_reg[regno] = -1;
1755 reg_mode[regno] = GET_MODE (reg);
1756 reg_symbol_ref[regno] = sym;
1757 reg_offset[regno] = INTVAL (off);
1761 /* Convert move insns with constant inputs to additions if they are cheaper.
1762 Return true if any changes were made. */
1764 reload_cse_move2add (rtx first)
1768 bool changed = false;
1770 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1772 reg_set_luid[i] = 0;
1774 reg_base_reg[i] = 0;
1775 reg_symbol_ref[i] = NULL_RTX;
1776 reg_mode[i] = VOIDmode;
1779 move2add_last_label_luid = 0;
1781 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
1787 move2add_last_label_luid = move2add_luid;
1788 /* We're going to increment move2add_luid twice after a
1789 label, so that we can use move2add_last_label_luid + 1 as
1790 the luid for constants. */
1794 if (! INSN_P (insn))
1796 pat = PATTERN (insn);
1797 /* For simplicity, we only perform this optimization on
1798 straightforward SETs. */
1799 if (GET_CODE (pat) == SET
1800 && REG_P (SET_DEST (pat)))
1802 rtx reg = SET_DEST (pat);
1803 int regno = REGNO (reg);
1804 rtx src = SET_SRC (pat);
1806 /* Check if we have valid information on the contents of this
1807 register in the mode of REG. */
1808 if (reg_set_luid[regno] > move2add_last_label_luid
1809 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
1810 && dbg_cnt (cse2_move2add))
1812 /* Try to transform (set (REGX) (CONST_INT A))
1814 (set (REGX) (CONST_INT B))
1816 (set (REGX) (CONST_INT A))
1818 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1820 (set (REGX) (CONST_INT A))
1822 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1825 if (CONST_INT_P (src)
1826 && reg_base_reg[regno] < 0
1827 && reg_symbol_ref[regno] == NULL_RTX)
1829 changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
1833 /* Try to transform (set (REGX) (REGY))
1834 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1837 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1840 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1842 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1843 else if (REG_P (src)
1844 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
1845 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
1846 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
1847 reg_mode[REGNO (src)]))
1849 rtx next = next_nonnote_insn (insn);
1852 set = single_set (next);
1854 && SET_DEST (set) == reg
1855 && GET_CODE (SET_SRC (set)) == PLUS
1856 && XEXP (SET_SRC (set), 0) == reg
1857 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
1859 rtx src3 = XEXP (SET_SRC (set), 1);
1860 HOST_WIDE_INT added_offset = INTVAL (src3);
1861 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
1862 HOST_WIDE_INT regno_offset = reg_offset[regno];
1864 gen_int_mode (added_offset
1868 bool success = false;
1869 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1871 if (new_src == const0_rtx)
1872 /* See above why we create (set (reg) (reg)) here. */
1874 = validate_change (next, &SET_SRC (set), reg, 0);
1875 else if ((rtx_cost (new_src, PLUS, speed)
1876 < COSTS_N_INSNS (1) + rtx_cost (src3, SET, speed))
1877 && have_add2_insn (reg, new_src))
1879 rtx newpat = gen_rtx_SET (VOIDmode,
1881 gen_rtx_PLUS (GET_MODE (reg),
1885 = validate_change (next, &PATTERN (next),
1892 reg_mode[regno] = GET_MODE (reg);
1894 trunc_int_for_mode (added_offset + base_offset,
1902 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1904 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
1906 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1908 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
1909 if ((GET_CODE (src) == SYMBOL_REF
1910 || (GET_CODE (src) == CONST
1911 && GET_CODE (XEXP (src, 0)) == PLUS
1912 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
1913 && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
1914 && dbg_cnt (cse2_move2add))
1918 if (GET_CODE (src) == SYMBOL_REF)
1925 sym = XEXP (XEXP (src, 0), 0);
1926 off = XEXP (XEXP (src, 0), 1);
1929 /* If the reg already contains the value which is sum of
1930 sym and some constant value, we can use an add2 insn. */
1931 if (reg_set_luid[regno] > move2add_last_label_luid
1932 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
1933 && reg_base_reg[regno] < 0
1934 && reg_symbol_ref[regno] != NULL_RTX
1935 && rtx_equal_p (sym, reg_symbol_ref[regno]))
1936 changed |= move2add_use_add2_insn (reg, sym, off, insn);
1938 /* Otherwise, we have to find a register whose value is sum
1939 of sym and some constant value. */
1941 changed |= move2add_use_add3_insn (reg, sym, off, insn);
1947 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1949 if (REG_NOTE_KIND (note) == REG_INC
1950 && REG_P (XEXP (note, 0)))
1952 /* Reset the information about this register. */
1953 int regno = REGNO (XEXP (note, 0));
1954 if (regno < FIRST_PSEUDO_REGISTER)
1955 reg_set_luid[regno] = 0;
1958 note_stores (PATTERN (insn), move2add_note_store, insn);
1960 /* If INSN is a conditional branch, we try to extract an
1961 implicit set out of it. */
1962 if (any_condjump_p (insn))
1964 rtx cnd = fis_get_condition (insn);
1967 && GET_CODE (cnd) == NE
1968 && REG_P (XEXP (cnd, 0))
1969 && !reg_set_p (XEXP (cnd, 0), insn)
1970 /* The following two checks, which are also in
1971 move2add_note_store, are intended to reduce the
1972 number of calls to gen_rtx_SET to avoid memory
1973 allocation if possible. */
1974 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
1975 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1
1976 && CONST_INT_P (XEXP (cnd, 1)))
1979 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
1980 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
1984 /* If this is a CALL_INSN, all call used registers are stored with
1988 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1990 if (call_used_regs[i])
1991 /* Reset the information about this register. */
1992 reg_set_luid[i] = 0;
1999 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2001 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2002 Called from reload_cse_move2add via note_stores. */
2005 move2add_note_store (rtx dst, const_rtx set, void *data)
2007 rtx insn = (rtx) data;
2008 unsigned int regno = 0;
2009 unsigned int nregs = 0;
2011 enum machine_mode mode = GET_MODE (dst);
2013 if (GET_CODE (dst) == SUBREG)
2015 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
2016 GET_MODE (SUBREG_REG (dst)),
2019 nregs = subreg_nregs (dst);
2020 dst = SUBREG_REG (dst);
2023 /* Some targets do argument pushes without adding REG_INC notes. */
2027 dst = XEXP (dst, 0);
2028 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
2029 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
2030 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
2036 regno += REGNO (dst);
2038 nregs = hard_regno_nregs[regno][mode];
2040 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2041 && nregs == 1 && GET_CODE (set) == SET)
2043 rtx note, sym = NULL_RTX;
2046 note = find_reg_equal_equiv_note (insn);
2047 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
2049 sym = XEXP (note, 0);
2052 else if (note && GET_CODE (XEXP (note, 0)) == CONST
2053 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
2054 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
2055 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
2057 sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
2058 off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1));
2061 if (sym != NULL_RTX)
2063 reg_base_reg[regno] = -1;
2064 reg_symbol_ref[regno] = sym;
2065 reg_offset[regno] = off;
2066 reg_mode[regno] = mode;
2067 reg_set_luid[regno] = move2add_luid;
2072 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2073 && nregs == 1 && GET_CODE (set) == SET
2074 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2075 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
2077 rtx src = SET_SRC (set);
2079 HOST_WIDE_INT offset;
2081 /* This may be different from mode, if SET_DEST (set) is a
2083 enum machine_mode dst_mode = GET_MODE (dst);
2085 switch (GET_CODE (src))
2088 if (REG_P (XEXP (src, 0)))
2090 base_reg = XEXP (src, 0);
2092 if (CONST_INT_P (XEXP (src, 1)))
2093 offset = INTVAL (XEXP (src, 1));
2094 else if (REG_P (XEXP (src, 1))
2095 && (reg_set_luid[REGNO (XEXP (src, 1))]
2096 > move2add_last_label_luid)
2097 && (MODES_OK_FOR_MOVE2ADD
2098 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
2100 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
2101 offset = reg_offset[REGNO (XEXP (src, 1))];
2102 /* Maybe the first register is known to be a
2104 else if (reg_set_luid[REGNO (base_reg)]
2105 > move2add_last_label_luid
2106 && (MODES_OK_FOR_MOVE2ADD
2107 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
2108 && reg_base_reg[REGNO (base_reg)] < 0)
2110 offset = reg_offset[REGNO (base_reg)];
2111 base_reg = XEXP (src, 1);
2130 /* Start tracking the register as a constant. */
2131 reg_base_reg[regno] = -1;
2132 reg_symbol_ref[regno] = NULL_RTX;
2133 reg_offset[regno] = INTVAL (SET_SRC (set));
2134 /* We assign the same luid to all registers set to constants. */
2135 reg_set_luid[regno] = move2add_last_label_luid + 1;
2136 reg_mode[regno] = mode;
2141 /* Invalidate the contents of the register. */
2142 reg_set_luid[regno] = 0;
2146 base_regno = REGNO (base_reg);
2147 /* If information about the base register is not valid, set it
2148 up as a new base register, pretending its value is known
2149 starting from the current insn. */
2150 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
2152 reg_base_reg[base_regno] = base_regno;
2153 reg_symbol_ref[base_regno] = NULL_RTX;
2154 reg_offset[base_regno] = 0;
2155 reg_set_luid[base_regno] = move2add_luid;
2156 reg_mode[base_regno] = mode;
2158 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
2159 reg_mode[base_regno]))
2162 reg_mode[regno] = mode;
2164 /* Copy base information from our base register. */
2165 reg_set_luid[regno] = reg_set_luid[base_regno];
2166 reg_base_reg[regno] = reg_base_reg[base_regno];
2167 reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
2169 /* Compute the sum of the offsets or constants. */
2170 reg_offset[regno] = trunc_int_for_mode (offset
2171 + reg_offset[base_regno],
2176 unsigned int endregno = regno + nregs;
2178 for (i = regno; i < endregno; i++)
2179 /* Reset the information about this register. */
2180 reg_set_luid[i] = 0;
2185 gate_handle_postreload (void)
2187 return (optimize > 0 && reload_completed);
2192 rest_of_handle_postreload (void)
2194 if (!dbg_cnt (postreload_cse))
2197 /* Do a very simple CSE pass over just the hard registers. */
2198 reload_cse_regs (get_insns ());
2199 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2200 Remove any EH edges associated with them. */
2201 if (cfun->can_throw_non_call_exceptions)
2202 purge_all_dead_edges ();
2207 struct rtl_opt_pass pass_postreload_cse =
2211 "postreload", /* name */
2212 gate_handle_postreload, /* gate */
2213 rest_of_handle_postreload, /* execute */
2216 0, /* static_pass_number */
2217 TV_RELOAD_CSE_REGS, /* tv_id */
2218 0, /* properties_required */
2219 0, /* properties_provided */
2220 0, /* properties_destroyed */
2221 0, /* todo_flags_start */
2222 TODO_df_finish | TODO_verify_rtl_sharing |
2223 TODO_dump_func /* todo_flags_finish */