1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
38 #include "cfgcleanup.h"
41 #include "tree-pass.h"
43 #include "function-abi.h"
45 static int reload_cse_noop_set_p (rtx);
46 static bool reload_cse_simplify (rtx_insn *, rtx);
47 static void reload_cse_regs_1 (void);
48 static int reload_cse_simplify_set (rtx, rtx_insn *);
49 static int reload_cse_simplify_operands (rtx_insn *, rtx);
51 static void reload_combine (void);
52 static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx);
53 static void reload_combine_note_store (rtx, const_rtx, void *);
55 static bool reload_cse_move2add (rtx_insn *);
56 static void move2add_note_store (rtx, const_rtx, void *);
58 /* Call cse / combine like post-reload optimization phases.
59 FIRST is the first instruction. */
62 reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED)
67 moves_converted = reload_cse_move2add (first);
68 if (flag_expensive_optimizations)
76 /* See whether a single set SET is a noop. */
78 reload_cse_noop_set_p (rtx set)
80 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
83 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
86 /* Try to simplify INSN. Return true if the CFG may have changed. */
88 reload_cse_simplify (rtx_insn *insn, rtx testreg)
90 rtx body = PATTERN (insn);
91 basic_block insn_bb = BLOCK_FOR_INSN (insn);
92 unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
94 /* If NO_FUNCTION_CSE has been set by the target, then we should not try
95 to cse function calls. */
96 if (NO_FUNCTION_CSE && CALL_P (insn))
99 if (GET_CODE (body) == SET)
103 /* Simplify even if we may think it is a no-op.
104 We may think a memory load of a value smaller than WORD_SIZE
105 is redundant because we haven't taken into account possible
106 implicit extension. reload_cse_simplify_set() will bring
107 this out, so it's safer to simplify before we delete. */
108 count += reload_cse_simplify_set (body, insn);
110 if (!count && reload_cse_noop_set_p (body))
112 if (check_for_inc_dec (insn))
113 delete_insn_and_edges (insn);
114 /* We're done with this insn. */
119 apply_change_group ();
121 reload_cse_simplify_operands (insn, testreg);
123 else if (GET_CODE (body) == PARALLEL)
127 rtx value = NULL_RTX;
129 /* Registers mentioned in the clobber list for an asm cannot be reused
130 within the body of the asm. Invalidate those registers now so that
131 we don't try to substitute values for them. */
132 if (asm_noperands (body) >= 0)
134 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
136 rtx part = XVECEXP (body, 0, i);
137 /* asms can only have full clobbers, not clobber_highs. */
138 gcc_assert (GET_CODE (part) != CLOBBER_HIGH);
139 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
140 cselib_invalidate_rtx (XEXP (part, 0));
144 /* If every action in a PARALLEL is a noop, we can delete
145 the entire PARALLEL. */
146 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
148 rtx part = XVECEXP (body, 0, i);
149 if (GET_CODE (part) == SET)
151 if (! reload_cse_noop_set_p (part))
153 if (REG_P (SET_DEST (part))
154 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
158 value = SET_DEST (part);
161 else if (GET_CODE (part) != CLOBBER
162 && GET_CODE (part) != CLOBBER_HIGH
163 && GET_CODE (part) != USE)
169 if (check_for_inc_dec (insn))
170 delete_insn_and_edges (insn);
171 /* We're done with this insn. */
175 /* It's not a no-op, but we can try to simplify it. */
176 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
177 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
178 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
181 apply_change_group ();
183 reload_cse_simplify_operands (insn, testreg);
187 return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs);
190 /* Do a very simple CSE pass over the hard registers.
192 This function detects no-op moves where we happened to assign two
193 different pseudo-registers to the same hard register, and then
194 copied one to the other. Reload will generate a useless
195 instruction copying a register to itself.
197 This function also detects cases where we load a value from memory
198 into two different registers, and (if memory is more expensive than
199 registers) changes it to simply copy the first register into the
202 Another optimization is performed that scans the operands of each
203 instruction to see whether the value is already available in a
204 hard register. It then replaces the operand with the hard register
205 if possible, much like an optional reload would. */
208 reload_cse_regs_1 (void)
210 bool cfg_changed = false;
213 rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1);
215 cselib_init (CSELIB_RECORD_MEMORY);
216 init_alias_analysis ();
218 FOR_EACH_BB_FN (bb, cfun)
219 FOR_BB_INSNS (bb, insn)
222 cfg_changed |= reload_cse_simplify (insn, testreg);
224 cselib_process_insn (insn);
228 end_alias_analysis ();
234 /* Try to simplify a single SET instruction. SET is the set pattern.
235 INSN is the instruction it came from.
236 This function only handles one case: if we set a register to a value
237 which is not a register, we try to find that value in some other register
238 and change the set into a register copy. */
241 reload_cse_simplify_set (rtx set, rtx_insn *insn)
249 struct elt_loc_list *l;
250 enum rtx_code extend_op = UNKNOWN;
251 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
253 dreg = true_regnum (SET_DEST (set));
258 if (side_effects_p (src) || true_regnum (src) >= 0)
261 dclass = REGNO_REG_CLASS (dreg);
263 /* When replacing a memory with a register, we need to honor assumptions
264 that combine made wrt the contents of sign bits. We'll do this by
265 generating an extend instruction instead of a reg->reg copy. Thus
266 the destination must be a register that we can widen. */
268 && (extend_op = load_extend_op (GET_MODE (src))) != UNKNOWN
269 && !REG_P (SET_DEST (set)))
272 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
276 /* If memory loads are cheaper than register copies, don't change them. */
278 old_cost = memory_move_cost (GET_MODE (src), dclass, true);
279 else if (REG_P (src))
280 old_cost = register_move_cost (GET_MODE (src),
281 REGNO_REG_CLASS (REGNO (src)), dclass);
283 old_cost = set_src_cost (src, GET_MODE (SET_DEST (set)), speed);
285 for (l = val->locs; l; l = l->next)
287 rtx this_rtx = l->loc;
290 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
292 if (extend_op != UNKNOWN)
296 if (!CONST_SCALAR_INT_P (this_rtx))
302 result = wide_int::from (rtx_mode_t (this_rtx,
304 BITS_PER_WORD, UNSIGNED);
307 result = wide_int::from (rtx_mode_t (this_rtx,
309 BITS_PER_WORD, SIGNED);
314 this_rtx = immed_wide_int_const (result, word_mode);
317 this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed);
319 else if (REG_P (this_rtx))
321 if (extend_op != UNKNOWN)
323 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
324 this_cost = set_src_cost (this_rtx, word_mode, speed);
327 this_cost = register_move_cost (GET_MODE (this_rtx),
328 REGNO_REG_CLASS (REGNO (this_rtx)),
334 /* If equal costs, prefer registers over anything else. That
335 tends to lead to smaller instructions on some machines. */
336 if (this_cost < old_cost
337 || (this_cost == old_cost
339 && !REG_P (SET_SRC (set))))
341 if (extend_op != UNKNOWN
342 && REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),
343 GET_MODE (SET_DEST (set)), word_mode))
345 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
346 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
347 validate_change (insn, &SET_DEST (set), wide_dest, 1);
350 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
351 old_cost = this_cost, did_change = 1;
358 /* Try to replace operands in INSN with equivalent values that are already
359 in registers. This can be viewed as optional reloading.
361 For each non-register operand in the insn, see if any hard regs are
362 known to be equivalent to that operand. Record the alternatives which
363 can accept these hard registers. Among all alternatives, select the
364 ones which are better or equal to the one currently matching, where
365 "better" is in terms of '?' and '!' constraints. Among the remaining
366 alternatives, select the one which replaces most operands with
370 reload_cse_simplify_operands (rtx_insn *insn, rtx testreg)
374 /* For each operand, all registers that are equivalent to it. */
375 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
377 const char *constraints[MAX_RECOG_OPERANDS];
379 /* Vector recording how bad an alternative is. */
380 int *alternative_reject;
381 /* Vector recording how many registers can be introduced by choosing
383 int *alternative_nregs;
384 /* Array of vectors recording, for each operand and each alternative,
385 which hard register to substitute, or -1 if the operand should be
387 int *op_alt_regno[MAX_RECOG_OPERANDS];
388 /* Array of alternatives, sorted in order of decreasing desirability. */
389 int *alternative_order;
391 extract_constrain_insn (insn);
393 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
396 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
397 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
398 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
399 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
400 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
402 /* For each operand, find out which regs are equivalent. */
403 for (i = 0; i < recog_data.n_operands; i++)
406 struct elt_loc_list *l;
409 CLEAR_HARD_REG_SET (equiv_regs[i]);
411 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
412 right, so avoid the problem here. Similarly NOTE_INSN_DELETED_LABEL.
413 Likewise if we have a constant and the insn pattern doesn't tell us
415 if (LABEL_P (recog_data.operand[i])
416 || (NOTE_P (recog_data.operand[i])
417 && NOTE_KIND (recog_data.operand[i]) == NOTE_INSN_DELETED_LABEL)
418 || (CONSTANT_P (recog_data.operand[i])
419 && recog_data.operand_mode[i] == VOIDmode))
422 op = recog_data.operand[i];
423 if (MEM_P (op) && load_extend_op (GET_MODE (op)) != UNKNOWN)
425 rtx set = single_set (insn);
427 /* We might have multiple sets, some of which do implicit
428 extension. Punt on this for now. */
431 /* If the destination is also a MEM or a STRICT_LOW_PART, no
433 Also, if there is an explicit extension, we don't have to
434 worry about an implicit one. */
435 else if (MEM_P (SET_DEST (set))
436 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
437 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND
438 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
439 ; /* Continue ordinary processing. */
440 /* If the register cannot change mode to word_mode, it follows that
441 it cannot have been used in word_mode. */
442 else if (REG_P (SET_DEST (set))
443 && !REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),
444 GET_MODE (SET_DEST (set)),
446 ; /* Continue ordinary processing. */
447 /* If this is a straight load, make the extension explicit. */
448 else if (REG_P (SET_DEST (set))
449 && recog_data.n_operands == 2
450 && SET_SRC (set) == op
451 && SET_DEST (set) == recog_data.operand[1-i])
453 validate_change (insn, recog_data.operand_loc[i],
454 gen_rtx_fmt_e (load_extend_op (GET_MODE (op)),
457 validate_change (insn, recog_data.operand_loc[1-i],
458 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
460 if (! apply_change_group ())
462 return reload_cse_simplify_operands (insn, testreg);
465 /* ??? There might be arithmetic operations with memory that are
466 safe to optimize, but is it worth the trouble? */
470 if (side_effects_p (op))
472 v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
476 for (l = v->locs; l; l = l->next)
478 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
481 alternative_mask preferred = get_preferred_alternatives (insn);
482 for (i = 0; i < recog_data.n_operands; i++)
488 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
489 for (j = 0; j < recog_data.n_alternatives; j++)
490 op_alt_regno[i][j] = -1;
492 p = constraints[i] = recog_data.constraints[i];
493 mode = recog_data.operand_mode[i];
495 /* Add the reject values for each alternative given by the constraints
504 alternative_reject[j] += 3;
506 alternative_reject[j] += 300;
509 /* We won't change operands which are already registers. We
510 also don't want to modify output operands. */
511 regno = true_regnum (recog_data.operand[i]);
513 || constraints[i][0] == '='
514 || constraints[i][0] == '+')
517 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
519 enum reg_class rclass = NO_REGS;
521 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
524 set_mode_and_regno (testreg, mode, regno);
526 /* We found a register equal to this operand. Now look for all
527 alternatives that can accept this register and have not been
528 assigned a register they can use yet. */
538 rclass = reg_class_subunion[rclass][GENERAL_REGS];
543 = (reg_class_subunion
545 [reg_class_for_constraint (lookup_constraint (p))]);
549 /* See if REGNO fits this alternative, and set it up as the
550 replacement register if we don't have one for this
551 alternative yet and the operand being replaced is not
552 a cheap CONST_INT. */
553 if (op_alt_regno[i][j] == -1
554 && TEST_BIT (preferred, j)
555 && reg_fits_class_p (testreg, rclass, 0, mode)
556 && (!CONST_INT_P (recog_data.operand[i])
557 || (set_src_cost (recog_data.operand[i], mode,
558 optimize_bb_for_speed_p
559 (BLOCK_FOR_INSN (insn)))
560 > set_src_cost (testreg, mode,
561 optimize_bb_for_speed_p
562 (BLOCK_FOR_INSN (insn))))))
564 alternative_nregs[j]++;
565 op_alt_regno[i][j] = regno;
571 p += CONSTRAINT_LEN (c, p);
579 /* Record all alternatives which are better or equal to the currently
580 matching one in the alternative_order array. */
581 for (i = j = 0; i < recog_data.n_alternatives; i++)
582 if (alternative_reject[i] <= alternative_reject[which_alternative])
583 alternative_order[j++] = i;
584 recog_data.n_alternatives = j;
586 /* Sort it. Given a small number of alternatives, a dumb algorithm
587 won't hurt too much. */
588 for (i = 0; i < recog_data.n_alternatives - 1; i++)
591 int best_reject = alternative_reject[alternative_order[i]];
592 int best_nregs = alternative_nregs[alternative_order[i]];
594 for (j = i + 1; j < recog_data.n_alternatives; j++)
596 int this_reject = alternative_reject[alternative_order[j]];
597 int this_nregs = alternative_nregs[alternative_order[j]];
599 if (this_reject < best_reject
600 || (this_reject == best_reject && this_nregs > best_nregs))
603 best_reject = this_reject;
604 best_nregs = this_nregs;
608 std::swap (alternative_order[best], alternative_order[i]);
611 /* Substitute the operands as determined by op_alt_regno for the best
613 j = alternative_order[0];
615 for (i = 0; i < recog_data.n_operands; i++)
617 machine_mode mode = recog_data.operand_mode[i];
618 if (op_alt_regno[i][j] == -1)
621 validate_change (insn, recog_data.operand_loc[i],
622 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
625 for (i = recog_data.n_dups - 1; i >= 0; i--)
627 int op = recog_data.dup_num[i];
628 machine_mode mode = recog_data.operand_mode[op];
630 if (op_alt_regno[op][j] == -1)
633 validate_change (insn, recog_data.dup_loc[i],
634 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
637 return apply_change_group ();
640 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
642 This code might also be useful when reload gave up on reg+reg addressing
643 because of clashes between the return register and INDEX_REG_CLASS. */
645 /* The maximum number of uses of a register we can keep track of to
646 replace them with reg+reg addressing. */
647 #define RELOAD_COMBINE_MAX_USES 16
649 /* Describes a recorded use of a register. */
652 /* The insn where a register has been used. */
654 /* Points to the memory reference enclosing the use, if any, NULL_RTX
657 /* Location of the register within INSN. */
659 /* The reverse uid of the insn. */
663 /* If the register is used in some unknown fashion, USE_INDEX is negative.
664 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
665 indicates where it is first set or clobbered.
666 Otherwise, USE_INDEX is the index of the last encountered use of the
667 register (which is first among these we have seen since we scan backwards).
668 USE_RUID indicates the first encountered, i.e. last, of these uses.
669 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
670 with a constant offset; OFFSET contains this constant in that case.
671 STORE_RUID is always meaningful if we only want to use a value in a
672 register in a different place: it denotes the next insn in the insn
673 stream (i.e. the last encountered) that sets or clobbers the register.
674 REAL_STORE_RUID is similar, but clobbers are ignored when updating it.
675 EXPR is the expression used when storing the register. */
678 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
684 bool all_offsets_match;
686 } reg_state[FIRST_PSEUDO_REGISTER];
688 /* Reverse linear uid. This is increased in reload_combine while scanning
689 the instructions from last to first. It is used to set last_label_ruid
690 and the store_ruid / use_ruid fields in reg_state. */
691 static int reload_combine_ruid;
693 /* The RUID of the last label we encountered in reload_combine. */
694 static int last_label_ruid;
696 /* The RUID of the last jump we encountered in reload_combine. */
697 static int last_jump_ruid;
699 /* The register numbers of the first and last index register. A value of
700 -1 in LAST_INDEX_REG indicates that we've previously computed these
701 values and found no suitable index registers. */
702 static int first_index_reg = -1;
703 static int last_index_reg;
705 #define LABEL_LIVE(LABEL) \
706 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
708 /* Subroutine of reload_combine_split_ruids, called to fix up a single
709 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
712 reload_combine_split_one_ruid (int *pruid, int split_ruid)
714 if (*pruid > split_ruid)
718 /* Called when we insert a new insn in a position we've already passed in
719 the scan. Examine all our state, increasing all ruids that are higher
720 than SPLIT_RUID by one in order to make room for a new insn. */
723 reload_combine_split_ruids (int split_ruid)
727 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
728 reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
729 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
731 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
733 int j, idx = reg_state[i].use_index;
734 reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid);
735 reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid);
736 reload_combine_split_one_ruid (®_state[i].real_store_ruid,
740 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
742 reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid,
748 /* Called when we are about to rescan a previously encountered insn with
749 reload_combine_note_use after modifying some part of it. This clears all
750 information about uses in that particular insn. */
753 reload_combine_purge_insn_uses (rtx_insn *insn)
757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
759 int j, k, idx = reg_state[i].use_index;
762 j = k = RELOAD_COMBINE_MAX_USES;
765 if (reg_state[i].reg_use[j].insn != insn)
769 reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
772 reg_state[i].use_index = k;
776 /* Called when we need to forget about all uses of REGNO after an insn
777 which is identified by RUID. */
780 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
782 int j, k, idx = reg_state[regno].use_index;
785 j = k = RELOAD_COMBINE_MAX_USES;
788 if (reg_state[regno].reg_use[j].ruid >= ruid)
792 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
795 reg_state[regno].use_index = k;
798 /* Find the use of REGNO with the ruid that is highest among those
799 lower than RUID_LIMIT, and return it if it is the only use of this
800 reg in the insn. Return NULL otherwise. */
802 static struct reg_use *
803 reload_combine_closest_single_use (unsigned regno, int ruid_limit)
805 int i, best_ruid = 0;
806 int use_idx = reg_state[regno].use_index;
807 struct reg_use *retval;
812 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
814 struct reg_use *use = reg_state[regno].reg_use + i;
815 int this_ruid = use->ruid;
816 if (this_ruid >= ruid_limit)
818 if (this_ruid > best_ruid)
820 best_ruid = this_ruid;
823 else if (this_ruid == best_ruid)
826 if (last_label_ruid >= best_ruid)
831 /* After we've moved an add insn, fix up any debug insns that occur
832 between the old location of the add and the new location. REG is
833 the destination register of the add insn; REPLACEMENT is the
834 SET_SRC of the add. FROM and TO specify the range in which we
835 should make this change on debug insns. */
838 fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to)
841 for (insn = from; insn != to; insn = NEXT_INSN (insn))
845 if (!DEBUG_BIND_INSN_P (insn))
848 t = INSN_VAR_LOCATION_LOC (insn);
849 t = simplify_replace_rtx (t, reg, replacement);
850 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
854 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
855 with SRC in the insn described by USE, taking costs into account. Return
856 true if we made the replacement. */
859 try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
861 rtx_insn *use_insn = use->insn;
862 rtx mem = use->containing_mem;
863 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
867 addr_space_t as = MEM_ADDR_SPACE (mem);
868 rtx oldaddr = XEXP (mem, 0);
869 rtx newaddr = NULL_RTX;
870 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
873 newaddr = simplify_replace_rtx (oldaddr, reg, src);
874 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
876 XEXP (mem, 0) = newaddr;
877 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
878 XEXP (mem, 0) = oldaddr;
879 if (new_cost <= old_cost
880 && validate_change (use_insn,
881 &XEXP (mem, 0), newaddr, 0))
887 rtx new_set = single_set (use_insn);
889 && REG_P (SET_DEST (new_set))
890 && GET_CODE (SET_SRC (new_set)) == PLUS
891 && REG_P (XEXP (SET_SRC (new_set), 0))
892 && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
895 machine_mode mode = GET_MODE (SET_DEST (new_set));
896 int old_cost = set_src_cost (SET_SRC (new_set), mode, speed);
898 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
899 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
901 if (set_src_cost (new_src, mode, speed) <= old_cost
902 && validate_change (use_insn, &SET_SRC (new_set),
910 /* Called by reload_combine when scanning INSN. This function tries to detect
911 patterns where a constant is added to a register, and the result is used
913 Return true if no further processing is needed on INSN; false if it wasn't
914 recognized and should be handled normally. */
917 reload_combine_recognize_const_pattern (rtx_insn *insn)
919 int from_ruid = reload_combine_ruid;
920 rtx set, pat, reg, src, addreg;
924 rtx_insn *add_moved_after_insn = NULL;
925 int add_moved_after_ruid = 0;
926 int clobbered_regno = -1;
928 set = single_set (insn);
932 reg = SET_DEST (set);
935 || REG_NREGS (reg) != 1
936 || GET_MODE (reg) != Pmode
937 || reg == stack_pointer_rtx)
942 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
943 uses of REG1 inside an address, or inside another add insn. If
944 possible and profitable, merge the addition into subsequent
946 if (GET_CODE (src) != PLUS
947 || !REG_P (XEXP (src, 0))
948 || !CONSTANT_P (XEXP (src, 1)))
951 addreg = XEXP (src, 0);
952 must_move_add = rtx_equal_p (reg, addreg);
954 pat = PATTERN (insn);
955 if (must_move_add && set != pat)
957 /* We have to be careful when moving the add; apart from the
958 single_set there may also be clobbers. Recognize one special
959 case, that of one clobber alongside the set (likely a clobber
960 of the CC register). */
961 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
962 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
963 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
964 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
966 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
971 use = reload_combine_closest_single_use (regno, from_ruid);
974 /* Start the search for the next use from here. */
975 from_ruid = use->ruid;
977 if (use && GET_MODE (*use->usep) == Pmode)
979 bool delete_add = false;
980 rtx_insn *use_insn = use->insn;
981 int use_ruid = use->ruid;
983 /* Avoid moving the add insn past a jump. */
984 if (must_move_add && use_ruid <= last_jump_ruid)
987 /* If the add clobbers another hard reg in parallel, don't move
988 it past a real set of this hard reg. */
989 if (must_move_add && clobbered_regno >= 0
990 && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
993 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
994 if (HAVE_cc0 && must_move_add && sets_cc0_p (PATTERN (use_insn)))
997 gcc_assert (reg_state[regno].store_ruid <= use_ruid);
998 /* Avoid moving a use of ADDREG past a point where it is stored. */
999 if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
1002 /* We also must not move the addition past an insn that sets
1003 the same register, unless we can combine two add insns. */
1004 if (must_move_add && reg_state[regno].store_ruid == use_ruid)
1006 if (use->containing_mem == NULL_RTX)
1012 if (try_replace_in_use (use, reg, src))
1014 reload_combine_purge_insn_uses (use_insn);
1015 reload_combine_note_use (&PATTERN (use_insn), use_insn,
1016 use_ruid, NULL_RTX);
1020 fixup_debug_insns (reg, src, insn, use_insn);
1026 add_moved_after_insn = use_insn;
1027 add_moved_after_ruid = use_ruid;
1032 /* If we get here, we couldn't handle this use. */
1038 if (!must_move_add || add_moved_after_insn == NULL_RTX)
1039 /* Process the add normally. */
1042 fixup_debug_insns (reg, src, insn, add_moved_after_insn);
1044 reorder_insns (insn, insn, add_moved_after_insn);
1045 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
1046 reload_combine_split_ruids (add_moved_after_ruid - 1);
1047 reload_combine_note_use (&PATTERN (insn), insn,
1048 add_moved_after_ruid, NULL_RTX);
1049 reg_state[regno].store_ruid = add_moved_after_ruid;
1054 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1055 can handle and improve. Return true if no further processing is needed on
1056 INSN; false if it wasn't recognized and should be handled normally. */
1059 reload_combine_recognize_pattern (rtx_insn *insn)
1063 set = single_set (insn);
1064 if (set == NULL_RTX)
1067 reg = SET_DEST (set);
1068 src = SET_SRC (set);
1069 if (!REG_P (reg) || REG_NREGS (reg) != 1)
1072 unsigned int regno = REGNO (reg);
1073 machine_mode mode = GET_MODE (reg);
1075 if (reg_state[regno].use_index < 0
1076 || reg_state[regno].use_index >= RELOAD_COMBINE_MAX_USES)
1079 for (int i = reg_state[regno].use_index;
1080 i < RELOAD_COMBINE_MAX_USES; i++)
1082 struct reg_use *use = reg_state[regno].reg_use + i;
1083 if (GET_MODE (*use->usep) != mode)
1087 /* Look for (set (REGX) (CONST_INT))
1088 (set (REGX) (PLUS (REGX) (REGY)))
1090 ... (MEM (REGX)) ...
1092 (set (REGZ) (CONST_INT))
1094 ... (MEM (PLUS (REGZ) (REGY)))... .
1096 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1097 and that we know all uses of REGX before it dies.
1098 Also, explicitly check that REGX != REGY; our life information
1099 does not yet show whether REGY changes in this insn. */
1101 if (GET_CODE (src) == PLUS
1102 && reg_state[regno].all_offsets_match
1103 && last_index_reg != -1
1104 && REG_P (XEXP (src, 1))
1105 && rtx_equal_p (XEXP (src, 0), reg)
1106 && !rtx_equal_p (XEXP (src, 1), reg)
1107 && last_label_ruid < reg_state[regno].use_ruid)
1109 rtx base = XEXP (src, 1);
1110 rtx_insn *prev = prev_nonnote_nondebug_insn (insn);
1111 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1112 rtx index_reg = NULL_RTX;
1113 rtx reg_sum = NULL_RTX;
1116 /* Now we need to set INDEX_REG to an index register (denoted as
1117 REGZ in the illustration above) and REG_SUM to the expression
1118 register+register that we want to use to substitute uses of REG
1119 (typically in MEMs) with. First check REG and BASE for being
1120 index registers; we can use them even if they are not dead. */
1121 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1122 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1130 /* Otherwise, look for a free index register. Since we have
1131 checked above that neither REG nor BASE are index registers,
1132 if we find anything at all, it will be different from these
1134 for (i = first_index_reg; i <= last_index_reg; i++)
1136 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
1137 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1138 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1139 && (crtl->abi->clobbers_full_reg_p (i)
1140 || df_regs_ever_live_p (i))
1141 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
1142 && !fixed_regs[i] && !global_regs[i]
1143 && hard_regno_nregs (i, GET_MODE (reg)) == 1
1144 && targetm.hard_regno_scratch_ok (i))
1146 index_reg = gen_rtx_REG (GET_MODE (reg), i);
1147 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1153 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1154 (REGY), i.e. BASE, is not clobbered before the last use we'll
1158 && CONST_INT_P (SET_SRC (prev_set))
1159 && rtx_equal_p (SET_DEST (prev_set), reg)
1160 && (reg_state[REGNO (base)].store_ruid
1161 <= reg_state[regno].use_ruid))
1163 /* Change destination register and, if necessary, the constant
1164 value in PREV, the constant loading instruction. */
1165 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1166 if (reg_state[regno].offset != const0_rtx)
1169 = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set))
1170 + UINTVAL (reg_state[regno].offset),
1171 GET_MODE (index_reg));
1172 validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1);
1175 /* Now for every use of REG that we have recorded, replace REG
1177 for (i = reg_state[regno].use_index;
1178 i < RELOAD_COMBINE_MAX_USES; i++)
1179 validate_unshare_change (reg_state[regno].reg_use[i].insn,
1180 reg_state[regno].reg_use[i].usep,
1181 /* Each change must have its own
1185 if (apply_change_group ())
1187 struct reg_use *lowest_ruid = NULL;
1189 /* For every new use of REG_SUM, we have to record the use
1190 of BASE therein, i.e. operand 1. */
1191 for (i = reg_state[regno].use_index;
1192 i < RELOAD_COMBINE_MAX_USES; i++)
1194 struct reg_use *use = reg_state[regno].reg_use + i;
1195 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
1196 use->ruid, use->containing_mem);
1197 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
1201 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
1203 /* Delete the reg-reg addition. */
1206 if (reg_state[regno].offset != const0_rtx
1207 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1209 && remove_reg_equal_equiv_notes (prev))
1210 df_notes_rescan (prev);
1212 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1221 reload_combine (void)
1223 rtx_insn *insn, *prev;
1226 int min_labelno, n_labels;
1227 HARD_REG_SET ever_live_at_start, *label_live;
1229 /* To avoid wasting too much time later searching for an index register,
1230 determine the minimum and maximum index register numbers. */
1231 if (INDEX_REG_CLASS == NO_REGS)
1232 last_index_reg = -1;
1233 else if (first_index_reg == -1 && last_index_reg == 0)
1235 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1236 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1238 if (first_index_reg == -1)
1239 first_index_reg = r;
1244 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1245 to -1 so we'll know to quit early the next time we get here. */
1246 if (first_index_reg == -1)
1248 last_index_reg = -1;
1253 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1254 information is a bit fuzzy immediately after reload, but it's
1255 still good enough to determine which registers are live at a jump
1257 min_labelno = get_first_label_num ();
1258 n_labels = max_label_num () - min_labelno;
1259 label_live = XNEWVEC (HARD_REG_SET, n_labels);
1260 CLEAR_HARD_REG_SET (ever_live_at_start);
1262 FOR_EACH_BB_REVERSE_FN (bb, cfun)
1264 insn = BB_HEAD (bb);
1268 bitmap live_in = df_get_live_in (bb);
1270 REG_SET_TO_HARD_REG_SET (live, live_in);
1271 compute_use_by_pseudos (&live, live_in);
1272 LABEL_LIVE (insn) = live;
1273 ever_live_at_start |= live;
1277 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1278 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1279 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1281 reg_state[r].store_ruid = 0;
1282 reg_state[r].real_store_ruid = 0;
1284 reg_state[r].use_index = -1;
1286 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1289 for (insn = get_last_insn (); insn; insn = prev)
1291 bool control_flow_insn;
1294 prev = PREV_INSN (insn);
1296 /* We cannot do our optimization across labels. Invalidating all the use
1297 information we have would be costly, so we just note where the label
1298 is and then later disable any optimization that would cross it. */
1300 last_label_ruid = reload_combine_ruid;
1301 else if (BARRIER_P (insn))
1303 /* Crossing a barrier resets all the use information. */
1304 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1305 if (! fixed_regs[r])
1306 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1308 else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn)))
1309 /* Optimizations across insns being marked as volatile must be
1310 prevented. All the usage information is invalidated
1312 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1314 && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES)
1315 reg_state[r].use_index = -1;
1317 if (! NONDEBUG_INSN_P (insn))
1320 reload_combine_ruid++;
1322 control_flow_insn = control_flow_insn_p (insn);
1323 if (control_flow_insn)
1324 last_jump_ruid = reload_combine_ruid;
1326 if (reload_combine_recognize_const_pattern (insn)
1327 || reload_combine_recognize_pattern (insn))
1330 note_stores (insn, reload_combine_note_store, NULL);
1335 HARD_REG_SET used_regs = insn_callee_abi (insn).full_reg_clobbers ();
1337 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1338 if (TEST_HARD_REG_BIT (used_regs, r))
1340 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1341 reg_state[r].store_ruid = reload_combine_ruid;
1344 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
1345 link = XEXP (link, 1))
1347 rtx setuse = XEXP (link, 0);
1348 rtx usage_rtx = XEXP (setuse, 0);
1350 if (GET_CODE (setuse) == USE && REG_P (usage_rtx))
1352 unsigned int end_regno = END_REGNO (usage_rtx);
1353 for (unsigned int i = REGNO (usage_rtx); i < end_regno; ++i)
1354 reg_state[i].use_index = -1;
1359 if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn)))
1361 /* Non-spill registers might be used at the call destination in
1362 some unknown fashion, so we have to mark the unknown use. */
1365 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
1366 && JUMP_LABEL (insn))
1368 if (ANY_RETURN_P (JUMP_LABEL (insn)))
1371 live = &LABEL_LIVE (JUMP_LABEL (insn));
1374 live = &ever_live_at_start;
1377 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1378 if (TEST_HARD_REG_BIT (*live, r))
1379 reg_state[r].use_index = -1;
1382 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
1385 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1387 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0)))
1389 int regno = REGNO (XEXP (note, 0));
1390 reg_state[regno].store_ruid = reload_combine_ruid;
1391 reg_state[regno].real_store_ruid = reload_combine_ruid;
1392 reg_state[regno].use_index = -1;
1400 /* Check if DST is a register or a subreg of a register; if it is,
1401 update store_ruid, real_store_ruid and use_index in the reg_state
1402 structure accordingly. Called via note_stores from reload_combine. */
1405 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1409 machine_mode mode = GET_MODE (dst);
1411 if (GET_CODE (dst) == SUBREG)
1413 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
1414 GET_MODE (SUBREG_REG (dst)),
1417 dst = SUBREG_REG (dst);
1420 /* Some targets do argument pushes without adding REG_INC notes. */
1424 dst = XEXP (dst, 0);
1425 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
1426 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC
1427 || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY)
1429 unsigned int end_regno = END_REGNO (XEXP (dst, 0));
1430 for (unsigned int i = REGNO (XEXP (dst, 0)); i < end_regno; ++i)
1432 /* We could probably do better, but for now mark the register
1433 as used in an unknown fashion and set/clobbered at this
1435 reg_state[i].use_index = -1;
1436 reg_state[i].store_ruid = reload_combine_ruid;
1437 reg_state[i].real_store_ruid = reload_combine_ruid;
1446 regno += REGNO (dst);
1448 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1449 careful with registers / register parts that are not full words.
1450 Similarly for ZERO_EXTRACT. */
1451 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1452 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1454 for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--)
1456 reg_state[i].use_index = -1;
1457 reg_state[i].store_ruid = reload_combine_ruid;
1458 reg_state[i].real_store_ruid = reload_combine_ruid;
1463 for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--)
1465 reg_state[i].store_ruid = reload_combine_ruid;
1466 if (GET_CODE (set) == SET)
1467 reg_state[i].real_store_ruid = reload_combine_ruid;
1468 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1473 /* XP points to a piece of rtl that has to be checked for any uses of
1475 *XP is the pattern of INSN, or a part of it.
1476 Called from reload_combine, and recursively by itself. */
1478 reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem)
1481 enum rtx_code code = x->code;
1484 rtx offset = const0_rtx; /* For the REG case below. */
1489 if (REG_P (SET_DEST (x)))
1491 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1497 /* If this is the USE of a return value, we can't change it. */
1498 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
1500 /* Mark the return register as used in an unknown fashion. */
1501 rtx reg = XEXP (x, 0);
1502 unsigned int end_regno = END_REGNO (reg);
1503 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
1504 reg_state[regno].use_index = -1;
1510 if (REG_P (SET_DEST (x)))
1512 /* No spurious CLOBBERs of pseudo registers may remain. */
1513 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER);
1519 gcc_assert (REG_P (SET_DEST (x)));
1523 /* We are interested in (plus (reg) (const_int)) . */
1524 if (!REG_P (XEXP (x, 0))
1525 || !CONST_INT_P (XEXP (x, 1)))
1527 offset = XEXP (x, 1);
1532 int regno = REGNO (x);
1536 /* No spurious USEs of pseudo registers may remain. */
1537 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
1539 nregs = REG_NREGS (x);
1541 /* We can't substitute into multi-hard-reg uses. */
1544 while (--nregs >= 0)
1545 reg_state[regno + nregs].use_index = -1;
1549 /* We may be called to update uses in previously seen insns.
1550 Don't add uses beyond the last store we saw. */
1551 if (ruid < reg_state[regno].store_ruid)
1554 /* If this register is already used in some unknown fashion, we
1556 If we decrement the index from zero to -1, we can't store more
1557 uses, so this register becomes used in an unknown fashion. */
1558 use_index = --reg_state[regno].use_index;
1562 if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1564 /* This is the first use of this register we have seen since we
1565 marked it as dead. */
1566 reg_state[regno].offset = offset;
1567 reg_state[regno].all_offsets_match = true;
1568 reg_state[regno].use_ruid = ruid;
1572 if (reg_state[regno].use_ruid > ruid)
1573 reg_state[regno].use_ruid = ruid;
1575 if (! rtx_equal_p (offset, reg_state[regno].offset))
1576 reg_state[regno].all_offsets_match = false;
1579 reg_state[regno].reg_use[use_index].insn = insn;
1580 reg_state[regno].reg_use[use_index].ruid = ruid;
1581 reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1582 reg_state[regno].reg_use[use_index].usep = xp;
1594 /* Recursively process the components of X. */
1595 fmt = GET_RTX_FORMAT (code);
1596 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1599 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1600 else if (fmt[i] == 'E')
1602 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1603 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1609 /* See if we can reduce the cost of a constant by replacing a move
1610 with an add. We track situations in which a register is set to a
1611 constant or to a register plus a constant. */
1612 /* We cannot do our optimization across labels. Invalidating all the
1613 information about register contents we have would be costly, so we
1614 use move2add_last_label_luid to note where the label is and then
1615 later disable any optimization that would cross it.
1616 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1617 are only valid if reg_set_luid[n] is greater than
1618 move2add_last_label_luid.
1619 For a set that established a new (potential) base register with
1620 non-constant value, we use move2add_luid from the place where the
1621 setting insn is encountered; registers based off that base then
1622 get the same reg_set_luid. Constants all get
1623 move2add_last_label_luid + 1 as their reg_set_luid. */
1624 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
1626 /* If reg_base_reg[n] is negative, register n has been set to
1627 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1628 If reg_base_reg[n] is non-negative, register n has been set to the
1629 sum of reg_offset[n] and the value of register reg_base_reg[n]
1630 before reg_set_luid[n], calculated in mode reg_mode[n] .
1631 For multi-hard-register registers, all but the first one are
1632 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1633 marks it as invalid. */
1634 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1635 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
1636 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
1637 static machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
1639 /* move2add_luid is linearly increased while scanning the instructions
1640 from first to last. It is used to set reg_set_luid in
1641 reload_cse_move2add and move2add_note_store. */
1642 static int move2add_luid;
1644 /* move2add_last_label_luid is set whenever a label is found. Labels
1645 invalidate all previously collected reg_offset data. */
1646 static int move2add_last_label_luid;
1648 /* ??? We don't know how zero / sign extension is handled, hence we
1649 can't go from a narrower to a wider mode. */
1650 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1651 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1652 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1653 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1655 /* Record that REG is being set to a value with the mode of REG. */
1658 move2add_record_mode (rtx reg)
1661 machine_mode mode = GET_MODE (reg);
1663 if (GET_CODE (reg) == SUBREG)
1665 regno = subreg_regno (reg);
1666 nregs = subreg_nregs (reg);
1668 else if (REG_P (reg))
1670 regno = REGNO (reg);
1671 nregs = REG_NREGS (reg);
1675 for (int i = nregs - 1; i > 0; i--)
1676 reg_mode[regno + i] = BLKmode;
1677 reg_mode[regno] = mode;
1680 /* Record that REG is being set to the sum of SYM and OFF. */
1683 move2add_record_sym_value (rtx reg, rtx sym, rtx off)
1685 int regno = REGNO (reg);
1687 move2add_record_mode (reg);
1688 reg_set_luid[regno] = move2add_luid;
1689 reg_base_reg[regno] = -1;
1690 reg_symbol_ref[regno] = sym;
1691 reg_offset[regno] = INTVAL (off);
1694 /* Check if REGNO contains a valid value in MODE. */
1697 move2add_valid_value_p (int regno, scalar_int_mode mode)
1699 if (reg_set_luid[regno] <= move2add_last_label_luid)
1702 if (mode != reg_mode[regno])
1704 scalar_int_mode old_mode;
1705 if (!is_a <scalar_int_mode> (reg_mode[regno], &old_mode)
1706 || !MODES_OK_FOR_MOVE2ADD (mode, old_mode))
1708 /* The value loaded into regno in reg_mode[regno] is also valid in
1709 mode after truncation only if (REG:mode regno) is the lowpart of
1710 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1711 regno of the lowpart might be different. */
1712 poly_int64 s_off = subreg_lowpart_offset (mode, old_mode);
1713 s_off = subreg_regno_offset (regno, old_mode, s_off, mode);
1714 if (maybe_ne (s_off, 0))
1715 /* We could in principle adjust regno, check reg_mode[regno] to be
1716 BLKmode, and return s_off to the caller (vs. -1 for failure),
1717 but we currently have no callers that could make use of this
1722 for (int i = end_hard_regno (mode, regno) - 1; i > regno; i--)
1723 if (reg_mode[i] != BLKmode)
1728 /* This function is called with INSN that sets REG (of mode MODE)
1729 to (SYM + OFF), while REG is known to already have value (SYM + offset).
1730 This function tries to change INSN into an add instruction
1731 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1732 It also updates the information about REG's known value.
1733 Return true if we made a change. */
1736 move2add_use_add2_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off,
1739 rtx pat = PATTERN (insn);
1740 rtx src = SET_SRC (pat);
1741 int regno = REGNO (reg);
1742 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], mode);
1743 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1744 bool changed = false;
1746 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1747 use (set (reg) (reg)) instead.
1748 We don't delete this insn, nor do we convert it into a
1749 note, to avoid losing register notes or the return
1750 value flag. jump2 already knows how to get rid of
1752 if (new_src == const0_rtx)
1754 /* If the constants are different, this is a
1755 truncation, that, if turned into (set (reg)
1756 (reg)), would be discarded. Maybe we should
1757 try a truncMN pattern? */
1758 if (INTVAL (off) == reg_offset [regno])
1759 changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1763 struct full_rtx_costs oldcst, newcst;
1764 rtx tem = gen_rtx_PLUS (mode, reg, new_src);
1766 get_full_set_rtx_cost (pat, &oldcst);
1767 SET_SRC (pat) = tem;
1768 get_full_set_rtx_cost (pat, &newcst);
1769 SET_SRC (pat) = src;
1771 if (costs_lt_p (&newcst, &oldcst, speed)
1772 && have_add2_insn (reg, new_src))
1773 changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1774 else if (sym == NULL_RTX && mode != BImode)
1776 scalar_int_mode narrow_mode;
1777 FOR_EACH_MODE_UNTIL (narrow_mode, mode)
1779 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
1780 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode))
1781 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode))))
1783 rtx narrow_reg = gen_lowpart_common (narrow_mode, reg);
1784 rtx narrow_src = gen_int_mode (INTVAL (off),
1787 = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode,
1790 get_full_set_rtx_cost (new_set, &newcst);
1791 if (costs_lt_p (&newcst, &oldcst, speed))
1793 changed = validate_change (insn, &PATTERN (insn),
1802 move2add_record_sym_value (reg, sym, off);
1807 /* This function is called with INSN that sets REG (of mode MODE) to
1808 (SYM + OFF), but REG doesn't have known value (SYM + offset). This
1809 function tries to find another register which is known to already have
1810 value (SYM + offset) and change INSN into an add instruction
1811 (set (REG) (plus (the found register) (OFF - offset))) if such
1812 a register is found. It also updates the information about
1814 Return true iff we made a change. */
1817 move2add_use_add3_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off,
1820 rtx pat = PATTERN (insn);
1821 rtx src = SET_SRC (pat);
1822 int regno = REGNO (reg);
1824 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1826 bool changed = false;
1827 struct full_rtx_costs oldcst, newcst, mincst;
1830 init_costs_to_max (&mincst);
1831 get_full_set_rtx_cost (pat, &oldcst);
1833 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx);
1834 SET_SRC (pat) = plus_expr;
1836 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1837 if (move2add_valid_value_p (i, mode)
1838 && reg_base_reg[i] < 0
1839 && reg_symbol_ref[i] != NULL_RTX
1840 && rtx_equal_p (sym, reg_symbol_ref[i]))
1842 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i],
1844 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1845 use (set (reg) (reg)) instead.
1846 We don't delete this insn, nor do we convert it into a
1847 note, to avoid losing register notes or the return
1848 value flag. jump2 already knows how to get rid of
1850 if (new_src == const0_rtx)
1852 init_costs_to_zero (&mincst);
1858 XEXP (plus_expr, 1) = new_src;
1859 get_full_set_rtx_cost (pat, &newcst);
1861 if (costs_lt_p (&newcst, &mincst, speed))
1868 SET_SRC (pat) = src;
1870 if (costs_lt_p (&mincst, &oldcst, speed))
1874 tem = gen_rtx_REG (GET_MODE (reg), min_regno);
1877 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno],
1879 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1881 if (validate_change (insn, &SET_SRC (pat), tem, 0))
1884 reg_set_luid[regno] = move2add_luid;
1885 move2add_record_sym_value (reg, sym, off);
1889 /* Convert move insns with constant inputs to additions if they are cheaper.
1890 Return true if any changes were made. */
1892 reload_cse_move2add (rtx_insn *first)
1896 bool changed = false;
1898 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1900 reg_set_luid[i] = 0;
1902 reg_base_reg[i] = 0;
1903 reg_symbol_ref[i] = NULL_RTX;
1904 reg_mode[i] = VOIDmode;
1907 move2add_last_label_luid = 0;
1909 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
1915 move2add_last_label_luid = move2add_luid;
1916 /* We're going to increment move2add_luid twice after a
1917 label, so that we can use move2add_last_label_luid + 1 as
1918 the luid for constants. */
1922 if (! INSN_P (insn))
1924 pat = PATTERN (insn);
1925 /* For simplicity, we only perform this optimization on
1926 straightforward SETs. */
1927 scalar_int_mode mode;
1928 if (GET_CODE (pat) == SET
1929 && REG_P (SET_DEST (pat))
1930 && is_a <scalar_int_mode> (GET_MODE (SET_DEST (pat)), &mode))
1932 rtx reg = SET_DEST (pat);
1933 int regno = REGNO (reg);
1934 rtx src = SET_SRC (pat);
1936 /* Check if we have valid information on the contents of this
1937 register in the mode of REG. */
1938 if (move2add_valid_value_p (regno, mode)
1939 && dbg_cnt (cse2_move2add))
1941 /* Try to transform (set (REGX) (CONST_INT A))
1943 (set (REGX) (CONST_INT B))
1945 (set (REGX) (CONST_INT A))
1947 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1949 (set (REGX) (CONST_INT A))
1951 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1954 if (CONST_INT_P (src)
1955 && reg_base_reg[regno] < 0
1956 && reg_symbol_ref[regno] == NULL_RTX)
1958 changed |= move2add_use_add2_insn (mode, reg, NULL_RTX,
1963 /* Try to transform (set (REGX) (REGY))
1964 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1967 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1970 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1972 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1973 else if (REG_P (src)
1974 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
1975 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
1976 && move2add_valid_value_p (REGNO (src), mode))
1978 rtx_insn *next = next_nonnote_nondebug_insn (insn);
1981 set = single_set (next);
1983 && SET_DEST (set) == reg
1984 && GET_CODE (SET_SRC (set)) == PLUS
1985 && XEXP (SET_SRC (set), 0) == reg
1986 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
1988 rtx src3 = XEXP (SET_SRC (set), 1);
1989 unsigned HOST_WIDE_INT added_offset = UINTVAL (src3);
1990 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
1991 HOST_WIDE_INT regno_offset = reg_offset[regno];
1993 gen_int_mode (added_offset
1997 bool success = false;
1998 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
2000 if (new_src == const0_rtx)
2001 /* See above why we create (set (reg) (reg)) here. */
2003 = validate_change (next, &SET_SRC (set), reg, 0);
2006 rtx old_src = SET_SRC (set);
2007 struct full_rtx_costs oldcst, newcst;
2008 rtx tem = gen_rtx_PLUS (mode, reg, new_src);
2010 get_full_set_rtx_cost (set, &oldcst);
2011 SET_SRC (set) = tem;
2012 get_full_set_src_cost (tem, mode, &newcst);
2013 SET_SRC (set) = old_src;
2014 costs_add_n_insns (&oldcst, 1);
2016 if (costs_lt_p (&newcst, &oldcst, speed)
2017 && have_add2_insn (reg, new_src))
2019 rtx newpat = gen_rtx_SET (reg, tem);
2021 = validate_change (next, &PATTERN (next),
2029 move2add_record_mode (reg);
2031 = trunc_int_for_mode (added_offset + base_offset,
2039 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2041 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2043 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2045 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2046 if ((GET_CODE (src) == SYMBOL_REF
2047 || (GET_CODE (src) == CONST
2048 && GET_CODE (XEXP (src, 0)) == PLUS
2049 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
2050 && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
2051 && dbg_cnt (cse2_move2add))
2055 if (GET_CODE (src) == SYMBOL_REF)
2062 sym = XEXP (XEXP (src, 0), 0);
2063 off = XEXP (XEXP (src, 0), 1);
2066 /* If the reg already contains the value which is sum of
2067 sym and some constant value, we can use an add2 insn. */
2068 if (move2add_valid_value_p (regno, mode)
2069 && reg_base_reg[regno] < 0
2070 && reg_symbol_ref[regno] != NULL_RTX
2071 && rtx_equal_p (sym, reg_symbol_ref[regno]))
2072 changed |= move2add_use_add2_insn (mode, reg, sym, off, insn);
2074 /* Otherwise, we have to find a register whose value is sum
2075 of sym and some constant value. */
2077 changed |= move2add_use_add3_insn (mode, reg, sym, off, insn);
2083 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2085 if (REG_NOTE_KIND (note) == REG_INC
2086 && REG_P (XEXP (note, 0)))
2088 /* Reset the information about this register. */
2089 int regno = REGNO (XEXP (note, 0));
2090 if (regno < FIRST_PSEUDO_REGISTER)
2092 move2add_record_mode (XEXP (note, 0));
2093 reg_mode[regno] = VOIDmode;
2097 note_stores (insn, move2add_note_store, insn);
2099 /* If INSN is a conditional branch, we try to extract an
2100 implicit set out of it. */
2101 if (any_condjump_p (insn))
2103 rtx cnd = fis_get_condition (insn);
2106 && GET_CODE (cnd) == NE
2107 && REG_P (XEXP (cnd, 0))
2108 && !reg_set_p (XEXP (cnd, 0), insn)
2109 /* The following two checks, which are also in
2110 move2add_note_store, are intended to reduce the
2111 number of calls to gen_rtx_SET to avoid memory
2112 allocation if possible. */
2113 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
2114 && REG_NREGS (XEXP (cnd, 0)) == 1
2115 && CONST_INT_P (XEXP (cnd, 1)))
2118 gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1));
2119 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
2123 /* If this is a CALL_INSN, all call used registers are stored with
2127 function_abi callee_abi = insn_callee_abi (insn);
2128 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
2129 if (reg_mode[i] != VOIDmode
2130 && reg_mode[i] != BLKmode
2131 && callee_abi.clobbers_reg_p (reg_mode[i], i))
2132 /* Reset the information about this register. */
2133 reg_mode[i] = VOIDmode;
2139 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2141 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2142 Called from reload_cse_move2add via note_stores. */
2145 move2add_note_store (rtx dst, const_rtx set, void *data)
2147 rtx_insn *insn = (rtx_insn *) data;
2148 unsigned int regno = 0;
2149 scalar_int_mode mode;
2151 /* Some targets do argument pushes without adding REG_INC notes. */
2155 dst = XEXP (dst, 0);
2156 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
2157 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
2158 reg_mode[REGNO (XEXP (dst, 0))] = VOIDmode;
2162 if (GET_CODE (dst) == SUBREG)
2163 regno = subreg_regno (dst);
2164 else if (REG_P (dst))
2165 regno = REGNO (dst);
2169 if (!is_a <scalar_int_mode> (GET_MODE (dst), &mode))
2172 if (GET_CODE (set) == SET)
2174 rtx note, sym = NULL_RTX;
2177 note = find_reg_equal_equiv_note (insn);
2178 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
2180 sym = XEXP (note, 0);
2183 else if (note && GET_CODE (XEXP (note, 0)) == CONST
2184 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
2185 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
2186 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
2188 sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
2189 off = XEXP (XEXP (XEXP (note, 0), 0), 1);
2192 if (sym != NULL_RTX)
2194 move2add_record_sym_value (dst, sym, off);
2199 if (GET_CODE (set) == SET
2200 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2201 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
2203 rtx src = SET_SRC (set);
2205 unsigned HOST_WIDE_INT offset;
2208 switch (GET_CODE (src))
2211 if (REG_P (XEXP (src, 0)))
2213 base_reg = XEXP (src, 0);
2215 if (CONST_INT_P (XEXP (src, 1)))
2216 offset = UINTVAL (XEXP (src, 1));
2217 else if (REG_P (XEXP (src, 1))
2218 && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode))
2220 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0
2221 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX)
2222 offset = reg_offset[REGNO (XEXP (src, 1))];
2223 /* Maybe the first register is known to be a
2225 else if (move2add_valid_value_p (REGNO (base_reg), mode)
2226 && reg_base_reg[REGNO (base_reg)] < 0
2227 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX)
2229 offset = reg_offset[REGNO (base_reg)];
2230 base_reg = XEXP (src, 1);
2249 /* Start tracking the register as a constant. */
2250 reg_base_reg[regno] = -1;
2251 reg_symbol_ref[regno] = NULL_RTX;
2252 reg_offset[regno] = INTVAL (SET_SRC (set));
2253 /* We assign the same luid to all registers set to constants. */
2254 reg_set_luid[regno] = move2add_last_label_luid + 1;
2255 move2add_record_mode (dst);
2262 base_regno = REGNO (base_reg);
2263 /* If information about the base register is not valid, set it
2264 up as a new base register, pretending its value is known
2265 starting from the current insn. */
2266 if (!move2add_valid_value_p (base_regno, mode))
2268 reg_base_reg[base_regno] = base_regno;
2269 reg_symbol_ref[base_regno] = NULL_RTX;
2270 reg_offset[base_regno] = 0;
2271 reg_set_luid[base_regno] = move2add_luid;
2272 gcc_assert (GET_MODE (base_reg) == mode);
2273 move2add_record_mode (base_reg);
2276 /* Copy base information from our base register. */
2277 reg_set_luid[regno] = reg_set_luid[base_regno];
2278 reg_base_reg[regno] = reg_base_reg[base_regno];
2279 reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
2281 /* Compute the sum of the offsets or constants. */
2283 = trunc_int_for_mode (offset + reg_offset[base_regno], mode);
2285 move2add_record_mode (dst);
2287 else if (GET_CODE (set) == CLOBBER_HIGH)
2289 /* Only invalidate if actually clobbered. */
2290 if (reg_mode[regno] == BLKmode
2291 || reg_is_clobbered_by_clobber_high (regno, reg_mode[regno], dst))
2297 /* Invalidate the contents of the register. */
2298 move2add_record_mode (dst);
2299 reg_mode[regno] = VOIDmode;
2305 const pass_data pass_data_postreload_cse =
2307 RTL_PASS, /* type */
2308 "postreload", /* name */
2309 OPTGROUP_NONE, /* optinfo_flags */
2310 TV_RELOAD_CSE_REGS, /* tv_id */
2311 0, /* properties_required */
2312 0, /* properties_provided */
2313 0, /* properties_destroyed */
2314 0, /* todo_flags_start */
2315 TODO_df_finish, /* todo_flags_finish */
2318 class pass_postreload_cse : public rtl_opt_pass
2321 pass_postreload_cse (gcc::context *ctxt)
2322 : rtl_opt_pass (pass_data_postreload_cse, ctxt)
2325 /* opt_pass methods: */
2326 virtual bool gate (function *) { return (optimize > 0 && reload_completed); }
2328 virtual unsigned int execute (function *);
2330 }; // class pass_postreload_cse
2333 pass_postreload_cse::execute (function *fun)
2335 if (!dbg_cnt (postreload_cse))
2338 /* Do a very simple CSE pass over just the hard registers. */
2339 reload_cse_regs (get_insns ());
2340 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2341 Remove any EH edges associated with them. */
2342 if (fun->can_throw_non_call_exceptions
2343 && purge_all_dead_edges ())
2352 make_pass_postreload_cse (gcc::context *ctxt)
2354 return new pass_postreload_cse (ctxt);