1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn;
142 static rtx curr_insn_set;
143 static basic_block curr_bb;
144 static lra_insn_recog_data_t curr_id;
145 static struct lra_static_insn_data *curr_static_id;
146 static enum machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start;
153 static int new_insn_uid_start;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx *loc)
159 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno)
168 enum reg_class rclass;
170 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
171 hard_regno = lra_get_regno_hard_regno (regno);
174 rclass = lra_get_allocno_class (regno);
175 if (rclass == NO_REGS)
177 return ira_class_hard_regs[rclass][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno, int offset)
188 hard_regno = lra_get_elimination_hard_regno (hard_regno);
189 return hard_regno + offset;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x)
199 int offset, hard_regno;
202 if (GET_CODE (x) == SUBREG)
203 reg = SUBREG_REG (x);
206 if ((hard_regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
207 hard_regno = lra_get_regno_hard_regno (hard_regno);
211 if (GET_CODE (x) == SUBREG)
212 offset += subreg_regno_offset (hard_regno, GET_MODE (reg),
213 SUBREG_BYTE (x), GET_MODE (x));
214 return get_final_hard_regno (hard_regno, offset);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno)
226 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
227 hard_regno = lra_get_regno_hard_regno (regno);
230 hard_regno = get_final_hard_regno (hard_regno, 0);
231 return REGNO_REG_CLASS (hard_regno);
233 if (regno >= new_regno_start)
234 return lra_get_allocno_class (regno);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
249 enum reg_class rclass, common_class;
250 enum machine_mode reg_mode;
251 int class_size, hard_regno, nregs, i, j;
252 int regno = REGNO (reg);
254 if (new_class != NULL)
255 *new_class = NO_REGS;
256 if (regno < FIRST_PSEUDO_REGISTER)
259 rtx *final_loc = &final_reg;
261 lra_eliminate_reg_if_possible (final_loc);
262 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
264 reg_mode = GET_MODE (reg);
265 rclass = get_reg_class (regno);
266 if (regno < new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn) >= new_insn_uid_start
273 && curr_insn_set != NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
276 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno >= new_regno_start && rclass == ALL_REGS)
282 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
283 && ! hard_reg_set_subset_p (reg_class_contents[cl],
284 lra_no_alloc_regs)));
287 common_class = ira_reg_class_subset[rclass][cl];
288 if (new_class != NULL)
289 *new_class = common_class;
290 if (hard_reg_set_subset_p (reg_class_contents[common_class],
293 /* Check that there are enough allocatable regs. */
294 class_size = ira_class_hard_regs_num[common_class];
295 for (i = 0; i < class_size; i++)
297 hard_regno = ira_class_hard_regs[common_class][i];
298 nregs = hard_regno_nregs[hard_regno][reg_mode];
301 for (j = 0; j < nregs; j++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
303 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno) == NO_REGS;
320 /* Initiate equivalences for LRA. As we keep original equivalences
321 before any elimination, we need to make copies otherwise any change
322 in insns might change the equivalences. */
324 lra_init_equiv (void)
326 ira_expand_reg_equiv ();
327 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
331 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
332 ira_reg_equiv[i].memory = copy_rtx (res);
333 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
334 ira_reg_equiv[i].invariant = copy_rtx (res);
338 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
340 /* Update equivalence for REGNO. We need to this as the equivalence
341 might contain other pseudos which are changed by their
344 update_equiv (int regno)
348 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
349 ira_reg_equiv[regno].memory
350 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
352 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
353 ira_reg_equiv[regno].invariant
354 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
358 /* If we have decided to substitute X with another value, return that
359 value, otherwise return X. */
366 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
367 || ! ira_reg_equiv[regno].defined_p
368 || ! ira_reg_equiv[regno].profitable_p
369 || lra_get_regno_hard_regno (regno) >= 0)
371 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
373 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
375 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
380 /* If we have decided to substitute X with the equivalent value,
381 return that value after elimination for INSN, otherwise return
384 get_equiv_with_elimination (rtx x, rtx insn)
386 rtx res = get_equiv (x);
388 if (x == res || CONSTANT_P (res))
390 return lra_eliminate_regs_1 (insn, res, GET_MODE (res), false, false, true);
393 /* Set up curr_operand_mode. */
395 init_curr_operand_mode (void)
397 int nop = curr_static_id->n_operands;
398 for (int i = 0; i < nop; i++)
400 enum machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
401 if (mode == VOIDmode)
403 /* The .md mode for address operands is the mode of the
404 addressed value rather than the mode of the address itself. */
405 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
408 mode = curr_static_id->operand[i].mode;
410 curr_operand_mode[i] = mode;
416 /* The page contains code to reuse input reloads. */
418 /* Structure describes input reload of the current insns. */
421 /* Reloaded value. */
423 /* Reload pseudo used. */
427 /* The number of elements in the following array. */
428 static int curr_insn_input_reloads_num;
429 /* Array containing info about input reloads. It is used to find the
430 same input reload and reuse the reload pseudo in this case. */
431 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
433 /* Initiate data concerning reuse of input reloads for the current
436 init_curr_insn_input_reloads (void)
438 curr_insn_input_reloads_num = 0;
441 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
442 created input reload pseudo (only if TYPE is not OP_OUT). The
443 result pseudo is returned through RESULT_REG. Return TRUE if we
444 created a new pseudo, FALSE if we reused the already created input
445 reload pseudo. Use TITLE to describe new registers for debug
448 get_reload_reg (enum op_type type, enum machine_mode mode, rtx original,
449 enum reg_class rclass, const char *title, rtx *result_reg)
452 enum reg_class new_class;
457 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
460 /* Prevent reuse value of expression with side effects,
461 e.g. volatile memory. */
462 if (! side_effects_p (original))
463 for (i = 0; i < curr_insn_input_reloads_num; i++)
464 if (rtx_equal_p (curr_insn_input_reloads[i].input, original)
465 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
467 rtx reg = curr_insn_input_reloads[i].reg;
469 /* If input is equal to original and both are VOIDmode,
470 GET_MODE (reg) might be still different from mode.
471 Ensure we don't return *result_reg with wrong mode. */
472 if (GET_MODE (reg) != mode)
474 if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode))
476 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
477 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
481 if (lra_dump_file != NULL)
483 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
484 dump_value_slim (lra_dump_file, original, 1);
486 if (new_class != lra_get_allocno_class (regno))
487 lra_change_class (regno, new_class, ", change to", false);
488 if (lra_dump_file != NULL)
489 fprintf (lra_dump_file, "\n");
492 *result_reg = lra_create_new_reg (mode, original, rclass, title);
493 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
494 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
495 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
501 /* The page contains code to extract memory address parts. */
503 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
505 ok_for_index_p_nonstrict (rtx reg)
507 unsigned regno = REGNO (reg);
509 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
512 /* A version of regno_ok_for_base_p for use here, when all pseudos
513 should count as OK. Arguments as for regno_ok_for_base_p. */
515 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, addr_space_t as,
516 enum rtx_code outer_code, enum rtx_code index_code)
518 unsigned regno = REGNO (reg);
520 if (regno >= FIRST_PSEUDO_REGISTER)
522 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
527 /* The page contains major code to choose the current insn alternative
528 and generate reloads for it. */
530 /* Return the offset from REGNO of the least significant register
533 This function is used to tell whether two registers satisfy
534 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
536 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
537 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
539 lra_constraint_offset (int regno, enum machine_mode mode)
541 lra_assert (regno < FIRST_PSEUDO_REGISTER);
542 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD
543 && SCALAR_INT_MODE_P (mode))
544 return hard_regno_nregs[regno][mode] - 1;
548 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
549 if they are the same hard reg, and has special hacks for
550 auto-increment and auto-decrement. This is specifically intended for
551 process_alt_operands to use in determining whether two operands
552 match. X is the operand whose number is the lower of the two.
554 It is supposed that X is the output operand and Y is the input
555 operand. Y_HARD_REGNO is the final hard regno of register Y or
556 register in subreg Y as we know it now. Otherwise, it is a
559 operands_match_p (rtx x, rtx y, int y_hard_regno)
562 RTX_CODE code = GET_CODE (x);
567 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
568 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
572 i = get_hard_regno (x);
576 if ((j = y_hard_regno) < 0)
579 i += lra_constraint_offset (i, GET_MODE (x));
580 j += lra_constraint_offset (j, GET_MODE (y));
585 /* If two operands must match, because they are really a single
586 operand of an assembler insn, then two post-increments are invalid
587 because the assembler insn would increment only once. On the
588 other hand, a post-increment matches ordinary indexing if the
589 post-increment is the output operand. */
590 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
591 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
593 /* Two pre-increments are invalid because the assembler insn would
594 increment only once. On the other hand, a pre-increment matches
595 ordinary indexing if the pre-increment is the input operand. */
596 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
597 || GET_CODE (y) == PRE_MODIFY)
598 return operands_match_p (x, XEXP (y, 0), -1);
602 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
603 && x == SUBREG_REG (y))
605 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
606 && SUBREG_REG (x) == y)
609 /* Now we have disposed of all the cases in which different rtx
611 if (code != GET_CODE (y))
614 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
615 if (GET_MODE (x) != GET_MODE (y))
624 return XEXP (x, 0) == XEXP (y, 0);
626 return XSTR (x, 0) == XSTR (y, 0);
632 /* Compare the elements. If any pair of corresponding elements fail
633 to match, return false for the whole things. */
635 fmt = GET_RTX_FORMAT (code);
636 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
642 if (XWINT (x, i) != XWINT (y, i))
647 if (XINT (x, i) != XINT (y, i))
652 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
661 if (XVECLEN (x, i) != XVECLEN (y, i))
663 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
665 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
671 /* It is believed that rtx's at this level will never
672 contain anything but integers and other rtx's, except for
673 within LABEL_REFs and SYMBOL_REFs. */
681 /* True if X is a constant that can be forced into the constant pool.
682 MODE is the mode of the operand, or VOIDmode if not known. */
683 #define CONST_POOL_OK_P(MODE, X) \
684 ((MODE) != VOIDmode \
686 && GET_CODE (X) != HIGH \
687 && !targetm.cannot_force_const_mem (MODE, X))
689 /* True if C is a non-empty register class that has too few registers
690 to be safely used as a reload target class. */
691 #define SMALL_REGISTER_CLASS_P(C) \
692 (ira_class_hard_regs_num [(C)] == 1 \
693 || (ira_class_hard_regs_num [(C)] >= 1 \
694 && targetm.class_likely_spilled_p (C)))
696 /* If REG is a reload pseudo, try to make its class satisfying CL. */
698 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
700 enum reg_class rclass;
702 /* Do not make more accurate class from reloads generated. They are
703 mostly moves with a lot of constraints. Making more accurate
704 class may results in very narrow class and impossibility of find
705 registers for several reloads of one insn. */
706 if (INSN_UID (curr_insn) >= new_insn_uid_start)
708 if (GET_CODE (reg) == SUBREG)
709 reg = SUBREG_REG (reg);
710 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
712 if (in_class_p (reg, cl, &rclass) && rclass != cl)
713 lra_change_class (REGNO (reg), rclass, " Change to", true);
716 /* Generate reloads for matching OUT and INS (array of input operand
717 numbers with end marker -1) with reg class GOAL_CLASS. Add input
718 and output reloads correspondingly to the lists *BEFORE and *AFTER.
719 OUT might be negative. In this case we generate input reloads for
720 matched input operands INS. */
722 match_reload (signed char out, signed char *ins, enum reg_class goal_class,
723 rtx *before, rtx *after)
726 rtx new_in_reg, new_out_reg, reg, clobber;
727 enum machine_mode inmode, outmode;
728 rtx in_rtx = *curr_id->operand_loc[ins[0]];
729 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
731 inmode = curr_operand_mode[ins[0]];
732 outmode = out < 0 ? inmode : curr_operand_mode[out];
733 push_to_sequence (*before);
734 if (inmode != outmode)
736 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
739 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
741 if (SCALAR_INT_MODE_P (inmode))
742 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
744 new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
745 LRA_SUBREG_P (new_out_reg) = 1;
746 /* If the input reg is dying here, we can use the same hard
747 register for REG and IN_RTX. We do it only for original
748 pseudos as reload pseudos can die although original
749 pseudos still live where reload pseudos dies. */
750 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
751 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)))
752 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
757 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
759 if (SCALAR_INT_MODE_P (outmode))
760 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
762 new_in_reg = gen_rtx_SUBREG (inmode, reg, 0);
763 /* NEW_IN_REG is non-paradoxical subreg. We don't want
764 NEW_OUT_REG living above. We add clobber clause for
765 this. This is just a temporary clobber. We can remove
766 it at the end of LRA work. */
767 clobber = emit_clobber (new_out_reg);
768 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
769 LRA_SUBREG_P (new_in_reg) = 1;
770 if (GET_CODE (in_rtx) == SUBREG)
772 rtx subreg_reg = SUBREG_REG (in_rtx);
774 /* If SUBREG_REG is dying here and sub-registers IN_RTX
775 and NEW_IN_REG are similar, we can use the same hard
776 register for REG and SUBREG_REG. */
777 if (REG_P (subreg_reg)
778 && (int) REGNO (subreg_reg) < lra_new_regno_start
779 && GET_MODE (subreg_reg) == outmode
780 && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg)
781 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)))
782 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
788 /* Pseudos have values -- see comments for lra_reg_info.
789 Different pseudos with the same value do not conflict even if
790 they live in the same place. When we create a pseudo we
791 assign value of original pseudo (if any) from which we
792 created the new pseudo. If we create the pseudo from the
793 input pseudo, the new pseudo will no conflict with the input
794 pseudo which is wrong when the input pseudo lives after the
795 insn and as the new pseudo value is changed by the insn
796 output. Therefore we create the new pseudo from the output.
798 We cannot reuse the current output register because we might
799 have a situation like "a <- a op b", where the constraints
800 force the second input operand ("b") to match the output
801 operand ("a"). "b" must then be copied into a new register
802 so that it doesn't clobber the current value of "a". */
804 new_in_reg = new_out_reg
805 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
808 /* In operand can be got from transformations before processing insn
809 constraints. One example of such transformations is subreg
810 reloading (see function simplify_operand_subreg). The new
811 pseudos created by the transformations might have inaccurate
812 class (ALL_REGS) and we should make their classes more
814 narrow_reload_pseudo_class (in_rtx, goal_class);
815 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
816 *before = get_insns ();
818 for (i = 0; (in = ins[i]) >= 0; i++)
821 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
822 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
823 *curr_id->operand_loc[in] = new_in_reg;
825 lra_update_dups (curr_id, ins);
828 /* See a comment for the input operand above. */
829 narrow_reload_pseudo_class (out_rtx, goal_class);
830 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
833 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
835 *after = get_insns ();
838 *curr_id->operand_loc[out] = new_out_reg;
839 lra_update_dup (curr_id, out);
842 /* Return register class which is union of all reg classes in insn
843 constraint alternative string starting with P. */
844 static enum reg_class
845 reg_class_from_constraints (const char *p)
848 enum reg_class op_class = NO_REGS;
851 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
858 op_class = (reg_class_subunion
859 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
865 op_class = reg_class_subunion[op_class][GENERAL_REGS];
869 if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS)
871 #ifdef EXTRA_CONSTRAINT_STR
872 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
874 = (reg_class_subunion
875 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
882 = reg_class_subunion[op_class][REG_CLASS_FROM_CONSTRAINT (c, p)];
885 while ((p += len), c);
889 /* If OP is a register, return the class of the register as per
890 get_reg_class, otherwise return NO_REGS. */
891 static inline enum reg_class
892 get_op_class (rtx op)
894 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
897 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
898 otherwise. If modes of MEM_PSEUDO and VAL are different, use
899 SUBREG for VAL to make them equal. */
901 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
903 if (GET_MODE (mem_pseudo) != GET_MODE (val))
905 /* Usually size of mem_pseudo is greater than val size but in
906 rare cases it can be less as it can be defined by target
907 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
910 val = gen_rtx_SUBREG (GET_MODE (mem_pseudo),
911 GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val,
913 LRA_SUBREG_P (val) = 1;
917 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
918 LRA_SUBREG_P (mem_pseudo) = 1;
922 ? gen_move_insn (mem_pseudo, val)
923 : gen_move_insn (val, mem_pseudo));
926 /* Process a special case insn (register move), return true if we
927 don't need to process it anymore. INSN should be a single set
928 insn. Set up that RTL was changed through CHANGE_P and macro
929 SECONDARY_MEMORY_NEEDED says to use secondary memory through
932 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
935 rtx dest, src, dreg, sreg, old_sreg, new_reg, before, scratch_reg;
936 enum reg_class dclass, sclass, secondary_class;
937 enum machine_mode sreg_mode;
938 secondary_reload_info sri;
940 lra_assert (curr_insn_set != NULL_RTX);
941 dreg = dest = SET_DEST (curr_insn_set);
942 sreg = src = SET_SRC (curr_insn_set);
943 if (GET_CODE (dest) == SUBREG)
944 dreg = SUBREG_REG (dest);
945 if (GET_CODE (src) == SUBREG)
946 sreg = SUBREG_REG (src);
947 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
949 sclass = dclass = NO_REGS;
951 dclass = get_reg_class (REGNO (dreg));
952 if (dclass == ALL_REGS)
953 /* ALL_REGS is used for new pseudos created by transformations
954 like reload of SUBREG_REG (see function
955 simplify_operand_subreg). We don't know their class yet. We
956 should figure out the class from processing the insn
957 constraints not in this fast path function. Even if ALL_REGS
958 were a right class for the pseudo, secondary_... hooks usually
959 are not define for ALL_REGS. */
961 sreg_mode = GET_MODE (sreg);
964 sclass = get_reg_class (REGNO (sreg));
965 if (sclass == ALL_REGS)
966 /* See comments above. */
968 if (sclass == NO_REGS && dclass == NO_REGS)
970 #ifdef SECONDARY_MEMORY_NEEDED
971 if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src))
972 #ifdef SECONDARY_MEMORY_NEEDED_MODE
973 && ((sclass != NO_REGS && dclass != NO_REGS)
974 || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src)))
982 if (! REG_P (dreg) || ! REG_P (sreg))
985 sri.icode = CODE_FOR_nothing;
987 secondary_class = NO_REGS;
988 /* Set up hard register for a reload pseudo for hook
989 secondary_reload because some targets just ignore unassigned
990 pseudos in the hook. */
991 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
993 dregno = REGNO (dreg);
994 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
998 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1000 sregno = REGNO (sreg);
1001 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1005 if (sclass != NO_REGS)
1007 = (enum reg_class) targetm.secondary_reload (false, dest,
1008 (reg_class_t) sclass,
1009 GET_MODE (src), &sri);
1010 if (sclass == NO_REGS
1011 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1012 && dclass != NO_REGS))
1014 enum reg_class old_sclass = secondary_class;
1015 secondary_reload_info old_sri = sri;
1017 sri.prev_sri = NULL;
1018 sri.icode = CODE_FOR_nothing;
1021 = (enum reg_class) targetm.secondary_reload (true, sreg,
1022 (reg_class_t) dclass,
1024 /* Check the target hook consistency. */
1026 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1027 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1028 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1031 reg_renumber [sregno] = -1;
1033 reg_renumber [dregno] = -1;
1034 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1038 if (secondary_class != NO_REGS)
1039 new_reg = lra_create_new_reg_with_unique_value (sreg_mode, NULL_RTX,
1043 if (old_sreg != sreg)
1044 sreg = copy_rtx (sreg);
1045 if (sri.icode == CODE_FOR_nothing)
1046 lra_emit_move (new_reg, sreg);
1049 enum reg_class scratch_class;
1051 scratch_class = (reg_class_from_constraints
1052 (insn_data[sri.icode].operand[2].constraint));
1053 scratch_reg = (lra_create_new_reg_with_unique_value
1054 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1055 scratch_class, "scratch"));
1056 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1057 sreg, scratch_reg));
1059 before = get_insns ();
1061 lra_process_new_insns (curr_insn, before, NULL_RTX, "Inserting the move");
1062 if (new_reg != NULL_RTX)
1064 if (GET_CODE (src) == SUBREG)
1065 SUBREG_REG (src) = new_reg;
1067 SET_SRC (curr_insn_set) = new_reg;
1071 if (lra_dump_file != NULL)
1073 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1074 dump_insn_slim (lra_dump_file, curr_insn);
1076 lra_set_insn_deleted (curr_insn);
1082 /* The following data describe the result of process_alt_operands.
1083 The data are used in curr_insn_transform to generate reloads. */
1085 /* The chosen reg classes which should be used for the corresponding
1087 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1088 /* True if the operand should be the same as another operand and that
1089 other operand does not need a reload. */
1090 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1091 /* True if the operand does not need a reload. */
1092 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1093 /* True if the operand can be offsetable memory. */
1094 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1095 /* The number of an operand to which given operand can be matched to. */
1096 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1097 /* The number of elements in the following array. */
1098 static int goal_alt_dont_inherit_ops_num;
1099 /* Numbers of operands whose reload pseudos should not be inherited. */
1100 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1101 /* True if the insn commutative operands should be swapped. */
1102 static bool goal_alt_swapped;
1103 /* The chosen insn alternative. */
1104 static int goal_alt_number;
1106 /* The following five variables are used to choose the best insn
1107 alternative. They reflect final characteristics of the best
1110 /* Number of necessary reloads and overall cost reflecting the
1111 previous value and other unpleasantness of the best alternative. */
1112 static int best_losers, best_overall;
1113 /* Overall number hard registers used for reloads. For example, on
1114 some targets we need 2 general registers to reload DFmode and only
1115 one floating point register. */
1116 static int best_reload_nregs;
1117 /* Overall number reflecting distances of previous reloading the same
1118 value. The distances are counted from the current BB start. It is
1119 used to improve inheritance chances. */
1120 static int best_reload_sum;
1122 /* True if the current insn should have no correspondingly input or
1124 static bool no_input_reloads_p, no_output_reloads_p;
1126 /* True if we swapped the commutative operands in the current
1128 static int curr_swapped;
1130 /* Arrange for address element *LOC to be a register of class CL.
1131 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1132 automodified value; handle that case by adding the required output
1133 reloads to list AFTER. Return true if the RTL was changed. */
1135 process_addr_reg (rtx *loc, rtx *before, rtx *after, enum reg_class cl)
1138 enum reg_class rclass, new_class;
1141 enum machine_mode mode;
1142 bool before_p = false;
1144 loc = strip_subreg (loc);
1146 mode = GET_MODE (reg);
1149 /* Always reload memory in an address even if the target supports
1151 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1156 regno = REGNO (reg);
1157 rclass = get_reg_class (regno);
1158 if ((*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1160 if (lra_dump_file != NULL)
1162 fprintf (lra_dump_file,
1163 "Changing pseudo %d in address of insn %u on equiv ",
1164 REGNO (reg), INSN_UID (curr_insn));
1165 dump_value_slim (lra_dump_file, *loc, 1);
1166 fprintf (lra_dump_file, "\n");
1168 *loc = copy_rtx (*loc);
1170 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1173 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1174 mode, reg, cl, "address", &new_reg))
1177 else if (new_class != NO_REGS && rclass != new_class)
1179 lra_change_class (regno, new_class, " Change to", true);
1187 push_to_sequence (*before);
1188 lra_emit_move (new_reg, reg);
1189 *before = get_insns ();
1196 lra_emit_move (reg, new_reg);
1198 *after = get_insns ();
1204 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1205 the insn to be inserted before curr insn. AFTER returns the
1206 the insn to be inserted after curr insn. ORIGREG and NEWREG
1207 are the original reg and new reg for reload. */
1209 insert_move_for_subreg (rtx *before, rtx *after, rtx origreg, rtx newreg)
1213 push_to_sequence (*before);
1214 lra_emit_move (newreg, origreg);
1215 *before = get_insns ();
1221 lra_emit_move (origreg, newreg);
1223 *after = get_insns ();
1228 /* Make reloads for subreg in operand NOP with internal subreg mode
1229 REG_MODE, add new reloads for further processing. Return true if
1230 any reload was generated. */
1232 simplify_operand_subreg (int nop, enum machine_mode reg_mode)
1236 enum machine_mode mode;
1238 rtx operand = *curr_id->operand_loc[nop];
1239 enum reg_class regclass;
1242 before = after = NULL_RTX;
1244 if (GET_CODE (operand) != SUBREG)
1247 mode = GET_MODE (operand);
1248 reg = SUBREG_REG (operand);
1249 type = curr_static_id->operand[nop].type;
1250 /* If we change address for paradoxical subreg of memory, the
1251 address might violate the necessary alignment or the access might
1252 be slow. So take this into consideration. We should not worry
1253 about access beyond allocated memory for paradoxical memory
1254 subregs as we don't substitute such equiv memory (see processing
1255 equivalences in function lra_constraints) and because for spilled
1256 pseudos we allocate stack memory enough for the biggest
1257 corresponding paradoxical subreg. */
1259 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg))
1260 || MEM_ALIGN (reg) >= GET_MODE_ALIGNMENT (mode)))
1261 || (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER))
1263 alter_subreg (curr_id->operand_loc[nop], false);
1266 /* Put constant into memory when we have mixed modes. It generates
1267 a better code in most cases as it does not need a secondary
1268 reload memory. It also prevents LRA looping when LRA is using
1269 secondary reload memory again and again. */
1270 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1271 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1273 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1274 alter_subreg (curr_id->operand_loc[nop], false);
1277 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1278 if there may be a problem accessing OPERAND in the outer
1281 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1282 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1283 /* Don't reload paradoxical subregs because we could be looping
1284 having repeatedly final regno out of hard regs range. */
1285 && (hard_regno_nregs[hard_regno][GET_MODE (reg)]
1286 >= hard_regno_nregs[hard_regno][mode])
1287 && simplify_subreg_regno (hard_regno, GET_MODE (reg),
1288 SUBREG_BYTE (operand), mode) < 0
1289 /* Don't reload subreg for matching reload. It is actually
1290 valid subreg in LRA. */
1291 && ! LRA_SUBREG_P (operand))
1292 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1294 enum reg_class rclass;
1297 /* There is a big probability that we will get the same class
1298 for the new pseudo and we will get the same insn which
1299 means infinite looping. So spill the new pseudo. */
1302 /* The class will be defined later in curr_insn_transform. */
1304 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1306 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1307 rclass, "subreg reg", &new_reg))
1309 bool insert_before, insert_after;
1310 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1312 insert_before = (type != OP_OUT
1313 || GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (mode));
1314 insert_after = (type != OP_IN);
1315 insert_move_for_subreg (insert_before ? &before : NULL,
1316 insert_after ? &after : NULL,
1319 SUBREG_REG (operand) = new_reg;
1320 lra_process_new_insns (curr_insn, before, after,
1321 "Inserting subreg reload");
1324 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1325 IRA allocates hardreg to the inner pseudo reg according to its mode
1326 instead of the outermode, so the size of the hardreg may not be enough
1327 to contain the outermode operand, in that case we may need to insert
1328 reload for the reg. For the following two types of paradoxical subreg,
1329 we need to insert reload:
1330 1. If the op_type is OP_IN, and the hardreg could not be paired with
1331 other hardreg to contain the outermode operand
1332 (checked by in_hard_reg_set_p), we need to insert the reload.
1333 2. If the op_type is OP_OUT or OP_INOUT.
1335 Here is a paradoxical subreg example showing how the reload is generated:
1337 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1338 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1340 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1341 here, if reg107 is assigned to hardreg R15, because R15 is the last
1342 hardreg, compiler cannot find another hardreg to pair with R15 to
1343 contain TImode data. So we insert a TImode reload reg180 for it.
1344 After reload is inserted:
1346 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1347 (reg:DI 107 [ __comp ])) -1
1348 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1349 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1351 Two reload hard registers will be allocated to reg180 to save TImode data
1353 else if (REG_P (reg)
1354 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1355 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1356 && (hard_regno_nregs[hard_regno][GET_MODE (reg)]
1357 < hard_regno_nregs[hard_regno][mode])
1358 && (regclass = lra_get_allocno_class (REGNO (reg)))
1360 || !in_hard_reg_set_p (reg_class_contents[regclass],
1363 /* The class will be defined later in curr_insn_transform. */
1364 enum reg_class rclass
1365 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1367 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1368 rclass, "paradoxical subreg", &new_reg))
1371 bool insert_before, insert_after;
1373 PUT_MODE (new_reg, mode);
1374 subreg = simplify_gen_subreg (GET_MODE (reg), new_reg, mode, 0);
1375 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1377 insert_before = (type != OP_OUT);
1378 insert_after = (type != OP_IN);
1379 insert_move_for_subreg (insert_before ? &before : NULL,
1380 insert_after ? &after : NULL,
1383 SUBREG_REG (operand) = new_reg;
1384 lra_process_new_insns (curr_insn, before, after,
1385 "Inserting paradoxical subreg reload");
1391 /* Return TRUE if X refers for a hard register from SET. */
1393 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1395 int i, j, x_hard_regno;
1396 enum machine_mode mode;
1402 code = GET_CODE (x);
1403 mode = GET_MODE (x);
1407 code = GET_CODE (x);
1408 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode))
1409 mode = GET_MODE (x);
1414 x_hard_regno = get_hard_regno (x);
1415 return (x_hard_regno >= 0
1416 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1420 struct address_info ad;
1422 decompose_mem_address (&ad, x);
1423 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1425 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1428 fmt = GET_RTX_FORMAT (code);
1429 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1433 if (uses_hard_regs_p (XEXP (x, i), set))
1436 else if (fmt[i] == 'E')
1438 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1439 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1446 /* Return true if OP is a spilled pseudo. */
1448 spilled_pseudo_p (rtx op)
1451 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1454 /* Return true if X is a general constant. */
1456 general_constant_p (rtx x)
1458 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1462 reg_in_class_p (rtx reg, enum reg_class cl)
1465 return get_reg_class (REGNO (reg)) == NO_REGS;
1466 return in_class_p (reg, cl, NULL);
1469 /* Major function to choose the current insn alternative and what
1470 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1471 negative we should consider only this alternative. Return false if
1472 we can not choose the alternative or find how to reload the
1475 process_alt_operands (int only_alternative)
1478 int nop, overall, nalt;
1479 int n_alternatives = curr_static_id->n_alternatives;
1480 int n_operands = curr_static_id->n_operands;
1481 /* LOSERS counts the operands that don't fit this alternative and
1482 would require loading. */
1484 /* REJECT is a count of how undesirable this alternative says it is
1485 if any reloading is required. If the alternative matches exactly
1486 then REJECT is ignored, but otherwise it gets this much counted
1487 against it in addition to the reloading needed. */
1489 /* The number of elements in the following array. */
1490 int early_clobbered_regs_num;
1491 /* Numbers of operands which are early clobber registers. */
1492 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1493 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1494 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1495 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1496 bool curr_alt_win[MAX_RECOG_OPERANDS];
1497 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1498 int curr_alt_matches[MAX_RECOG_OPERANDS];
1499 /* The number of elements in the following array. */
1500 int curr_alt_dont_inherit_ops_num;
1501 /* Numbers of operands whose reload pseudos should not be inherited. */
1502 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1504 /* The register when the operand is a subreg of register, otherwise the
1506 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1507 /* The register if the operand is a register or subreg of register,
1509 rtx operand_reg[MAX_RECOG_OPERANDS];
1510 int hard_regno[MAX_RECOG_OPERANDS];
1511 enum machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1512 int reload_nregs, reload_sum;
1516 /* Calculate some data common for all alternatives to speed up the
1518 for (nop = 0; nop < n_operands; nop++)
1522 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1523 /* The real hard regno of the operand after the allocation. */
1524 hard_regno[nop] = get_hard_regno (op);
1526 operand_reg[nop] = reg = op;
1527 biggest_mode[nop] = GET_MODE (op);
1528 if (GET_CODE (op) == SUBREG)
1530 operand_reg[nop] = reg = SUBREG_REG (op);
1531 if (GET_MODE_SIZE (biggest_mode[nop])
1532 < GET_MODE_SIZE (GET_MODE (reg)))
1533 biggest_mode[nop] = GET_MODE (reg);
1536 operand_reg[nop] = NULL_RTX;
1537 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1538 || ((int) REGNO (reg)
1539 == lra_get_elimination_hard_regno (REGNO (reg))))
1540 no_subreg_reg_operand[nop] = reg;
1542 operand_reg[nop] = no_subreg_reg_operand[nop]
1543 /* Just use natural mode for elimination result. It should
1544 be enough for extra constraints hooks. */
1545 = regno_reg_rtx[hard_regno[nop]];
1548 /* The constraints are made of several alternatives. Each operand's
1549 constraint looks like foo,bar,... with commas separating the
1550 alternatives. The first alternatives for all operands go
1551 together, the second alternatives go together, etc.
1553 First loop over alternatives. */
1554 for (nalt = 0; nalt < n_alternatives; nalt++)
1556 /* Loop over operands for one constraint alternative. */
1557 #if HAVE_ATTR_enabled
1558 if (curr_id->alternative_enabled_p != NULL
1559 && ! curr_id->alternative_enabled_p[nalt])
1563 if (only_alternative >= 0 && nalt != only_alternative)
1567 overall = losers = reject = reload_nregs = reload_sum = 0;
1568 for (nop = 0; nop < n_operands; nop++)
1570 int inc = (curr_static_id
1571 ->operand_alternative[nalt * n_operands + nop].reject);
1572 if (lra_dump_file != NULL && inc != 0)
1573 fprintf (lra_dump_file,
1574 " Staticly defined alt reject+=%d\n", inc);
1577 early_clobbered_regs_num = 0;
1579 for (nop = 0; nop < n_operands; nop++)
1583 int len, c, m, i, opalt_num, this_alternative_matches;
1584 bool win, did_match, offmemok, early_clobber_p;
1585 /* false => this operand can be reloaded somehow for this
1588 /* true => this operand can be reloaded if the alternative
1591 /* True if a constant forced into memory would be OK for
1594 enum reg_class this_alternative, this_costly_alternative;
1595 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
1596 bool this_alternative_match_win, this_alternative_win;
1597 bool this_alternative_offmemok;
1599 enum machine_mode mode;
1601 opalt_num = nalt * n_operands + nop;
1602 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
1604 /* Fast track for no constraints at all. */
1605 curr_alt[nop] = NO_REGS;
1606 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
1607 curr_alt_win[nop] = true;
1608 curr_alt_match_win[nop] = false;
1609 curr_alt_offmemok[nop] = false;
1610 curr_alt_matches[nop] = -1;
1614 op = no_subreg_reg_operand[nop];
1615 mode = curr_operand_mode[nop];
1617 win = did_match = winreg = offmemok = constmemok = false;
1620 early_clobber_p = false;
1621 p = curr_static_id->operand_alternative[opalt_num].constraint;
1623 this_costly_alternative = this_alternative = NO_REGS;
1624 /* We update set of possible hard regs besides its class
1625 because reg class might be inaccurate. For example,
1626 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1627 is translated in HI_REGS because classes are merged by
1628 pairs and there is no accurate intermediate class. */
1629 CLEAR_HARD_REG_SET (this_alternative_set);
1630 CLEAR_HARD_REG_SET (this_costly_alternative_set);
1631 this_alternative_win = false;
1632 this_alternative_match_win = false;
1633 this_alternative_offmemok = false;
1634 this_alternative_matches = -1;
1636 /* An empty constraint should be excluded by the fast
1638 lra_assert (*p != 0 && *p != ',');
1640 /* Scan this alternative's specs for this operand; set WIN
1641 if the operand fits any letter in this alternative.
1642 Otherwise, clear BADOP if this operand could fit some
1643 letter after reloads, or set WINREG if this operand could
1644 fit after reloads provided the constraint allows some
1649 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1658 case '=': case '+': case '?': case '*': case '!':
1659 case ' ': case '\t':
1663 /* We only support one commutative marker, the first
1664 one. We already set commutative above. */
1668 early_clobber_p = true;
1672 /* Ignore rest of this alternative. */
1676 case '0': case '1': case '2': case '3': case '4':
1677 case '5': case '6': case '7': case '8': case '9':
1682 m = strtoul (p, &end, 10);
1685 lra_assert (nop > m);
1687 this_alternative_matches = m;
1688 m_hregno = get_hard_regno (*curr_id->operand_loc[m]);
1689 /* We are supposed to match a previous operand.
1690 If we do, we win if that one did. If we do
1691 not, count both of the operands as losers.
1692 (This is too conservative, since most of the
1693 time only a single reload insn will be needed
1694 to make the two operands win. As a result,
1695 this alternative may be rejected when it is
1696 actually desirable.) */
1698 if (operands_match_p (*curr_id->operand_loc[nop],
1699 *curr_id->operand_loc[m], m_hregno))
1701 /* We should reject matching of an early
1702 clobber operand if the matching operand is
1703 not dying in the insn. */
1704 if (! curr_static_id->operand[m].early_clobber
1705 || operand_reg[nop] == NULL_RTX
1706 || (find_regno_note (curr_insn, REG_DEAD,
1708 || REGNO (op) == REGNO (operand_reg[m])))
1713 /* If we are matching a non-offsettable
1714 address where an offsettable address was
1715 expected, then we must reject this
1716 combination, because we can't reload
1718 if (curr_alt_offmemok[m]
1719 && MEM_P (*curr_id->operand_loc[m])
1720 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
1725 /* Operands don't match. Both operands must
1726 allow a reload register, otherwise we
1727 cannot make them match. */
1728 if (curr_alt[m] == NO_REGS)
1730 /* Retroactively mark the operand we had to
1731 match as a loser, if it wasn't already and
1732 it wasn't matched to a register constraint
1733 (e.g it might be matched by memory). */
1735 && (operand_reg[m] == NULL_RTX
1736 || hard_regno[m] < 0))
1740 += (ira_reg_class_max_nregs[curr_alt[m]]
1741 [GET_MODE (*curr_id->operand_loc[m])]);
1744 /* We prefer no matching alternatives because
1745 it gives more freedom in RA. */
1746 if (operand_reg[nop] == NULL_RTX
1747 || (find_regno_note (curr_insn, REG_DEAD,
1748 REGNO (operand_reg[nop]))
1751 if (lra_dump_file != NULL)
1754 " %d Matching alt: reject+=2\n",
1759 /* If we have to reload this operand and some
1760 previous operand also had to match the same
1761 thing as this operand, we don't know how to do
1763 if (!match_p || !curr_alt_win[m])
1765 for (i = 0; i < nop; i++)
1766 if (curr_alt_matches[i] == m)
1774 /* This can be fixed with reloads if the operand
1775 we are supposed to match can be fixed with
1778 this_alternative = curr_alt[m];
1779 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
1780 winreg = this_alternative != NO_REGS;
1785 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1787 this_alternative = reg_class_subunion[this_alternative][cl];
1788 IOR_HARD_REG_SET (this_alternative_set,
1789 reg_class_contents[cl]);
1792 this_costly_alternative
1793 = reg_class_subunion[this_costly_alternative][cl];
1794 IOR_HARD_REG_SET (this_costly_alternative_set,
1795 reg_class_contents[cl]);
1801 case TARGET_MEM_CONSTRAINT:
1802 if (MEM_P (op) || spilled_pseudo_p (op))
1804 /* We can put constant or pseudo value into memory
1805 to satisfy the constraint. */
1806 if (CONST_POOL_OK_P (mode, op) || REG_P (op))
1813 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1814 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1820 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1821 || GET_CODE (XEXP (op, 0)) == POST_INC))
1825 /* Memory op whose address is not offsettable. */
1828 && ! offsettable_nonstrict_memref_p (op))
1832 /* Memory operand whose address is offsettable. */
1835 && offsettable_nonstrict_memref_p (op))
1836 || spilled_pseudo_p (op))
1838 /* We can put constant or pseudo value into memory
1839 or make memory address offsetable to satisfy the
1841 if (CONST_POOL_OK_P (mode, op) || MEM_P (op) || REG_P (op))
1849 if (GET_CODE (op) == CONST_DOUBLE
1850 || (GET_CODE (op) == CONST_VECTOR
1851 && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)))
1857 if (CONST_DOUBLE_AS_FLOAT_P (op)
1858 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
1863 if (CONST_SCALAR_INT_P (op))
1867 if (general_constant_p (op))
1872 if (CONST_SCALAR_INT_P (op))
1884 if (CONST_INT_P (op)
1885 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
1890 /* This constraint should be excluded by the fast
1897 || general_constant_p (op)
1898 || spilled_pseudo_p (op))
1900 /* Drop through into 'r' case. */
1904 = reg_class_subunion[this_alternative][GENERAL_REGS];
1905 IOR_HARD_REG_SET (this_alternative_set,
1906 reg_class_contents[GENERAL_REGS]);
1909 this_costly_alternative
1910 = (reg_class_subunion
1911 [this_costly_alternative][GENERAL_REGS]);
1912 IOR_HARD_REG_SET (this_costly_alternative_set,
1913 reg_class_contents[GENERAL_REGS]);
1918 if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS)
1920 #ifdef EXTRA_CONSTRAINT_STR
1921 if (EXTRA_MEMORY_CONSTRAINT (c, p))
1923 if (EXTRA_CONSTRAINT_STR (op, c, p))
1925 else if (spilled_pseudo_p (op))
1928 /* If we didn't already win, we can reload
1929 constants via force_const_mem or put the
1930 pseudo value into memory, or make other
1931 memory by reloading the address like for
1933 if (CONST_POOL_OK_P (mode, op)
1934 || MEM_P (op) || REG_P (op))
1940 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1942 if (EXTRA_CONSTRAINT_STR (op, c, p))
1945 /* If we didn't already win, we can reload
1946 the address into a base register. */
1947 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1950 = reg_class_subunion[this_alternative][cl];
1951 IOR_HARD_REG_SET (this_alternative_set,
1952 reg_class_contents[cl]);
1955 this_costly_alternative
1956 = (reg_class_subunion
1957 [this_costly_alternative][cl]);
1958 IOR_HARD_REG_SET (this_costly_alternative_set,
1959 reg_class_contents[cl]);
1965 if (EXTRA_CONSTRAINT_STR (op, c, p))
1971 cl = REG_CLASS_FROM_CONSTRAINT (c, p);
1972 this_alternative = reg_class_subunion[this_alternative][cl];
1973 IOR_HARD_REG_SET (this_alternative_set,
1974 reg_class_contents[cl]);
1977 this_costly_alternative
1978 = reg_class_subunion[this_costly_alternative][cl];
1979 IOR_HARD_REG_SET (this_costly_alternative_set,
1980 reg_class_contents[cl]);
1983 if (mode == BLKmode)
1988 if (hard_regno[nop] >= 0
1989 && in_hard_reg_set_p (this_alternative_set,
1990 mode, hard_regno[nop]))
1992 else if (hard_regno[nop] < 0
1993 && in_class_p (op, this_alternative, NULL))
1998 if (c != ' ' && c != '\t')
1999 costly_p = c == '*';
2001 while ((p += len), c);
2003 scratch_p = (operand_reg[nop] != NULL_RTX
2004 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2005 /* Record which operands fit this alternative. */
2008 this_alternative_win = true;
2009 if (operand_reg[nop] != NULL_RTX)
2011 if (hard_regno[nop] >= 0)
2013 if (in_hard_reg_set_p (this_costly_alternative_set,
2014 mode, hard_regno[nop]))
2016 if (lra_dump_file != NULL)
2017 fprintf (lra_dump_file,
2018 " %d Costly set: reject++\n",
2025 /* Prefer won reg to spilled pseudo under other
2026 equal conditions for possibe inheritance. */
2029 if (lra_dump_file != NULL)
2032 " %d Non pseudo reload: reject++\n",
2036 if (in_class_p (operand_reg[nop],
2037 this_costly_alternative, NULL))
2039 if (lra_dump_file != NULL)
2042 " %d Non pseudo costly reload:"
2048 /* We simulate the behaviour of old reload here.
2049 Although scratches need hard registers and it
2050 might result in spilling other pseudos, no reload
2051 insns are generated for the scratches. So it
2052 might cost something but probably less than old
2053 reload pass believes. */
2056 if (lra_dump_file != NULL)
2057 fprintf (lra_dump_file,
2058 " %d Scratch win: reject+=2\n",
2065 this_alternative_match_win = true;
2068 int const_to_mem = 0;
2071 /* Never do output reload of stack pointer. It makes
2072 impossible to do elimination when SP is changed in
2074 if (op == stack_pointer_rtx && ! frame_pointer_needed
2075 && curr_static_id->operand[nop].type != OP_IN)
2078 /* If this alternative asks for a specific reg class, see if there
2079 is at least one allocatable register in that class. */
2081 = (this_alternative == NO_REGS
2082 || (hard_reg_set_subset_p
2083 (reg_class_contents[this_alternative],
2084 lra_no_alloc_regs)));
2086 /* For asms, verify that the class for this alternative is possible
2087 for the mode that is specified. */
2088 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2091 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2092 if (HARD_REGNO_MODE_OK (i, mode)
2093 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2096 if (i == FIRST_PSEUDO_REGISTER)
2100 /* If this operand accepts a register, and if the
2101 register class has at least one allocatable register,
2102 then this operand can be reloaded. */
2103 if (winreg && !no_regs_p)
2108 if (lra_dump_file != NULL)
2109 fprintf (lra_dump_file,
2110 " alt=%d: Bad operand -- refuse\n",
2115 this_alternative_offmemok = offmemok;
2116 if (this_costly_alternative != NO_REGS)
2118 if (lra_dump_file != NULL)
2119 fprintf (lra_dump_file,
2120 " %d Costly loser: reject++\n", nop);
2123 /* If the operand is dying, has a matching constraint,
2124 and satisfies constraints of the matched operand
2125 which failed to satisfy the own constraints, probably
2126 the reload for this operand will be gone. */
2127 if (this_alternative_matches >= 0
2128 && !curr_alt_win[this_alternative_matches]
2130 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2131 && (hard_regno[nop] >= 0
2132 ? in_hard_reg_set_p (this_alternative_set,
2133 mode, hard_regno[nop])
2134 : in_class_p (op, this_alternative, NULL)))
2136 if (lra_dump_file != NULL)
2139 " %d Dying matched operand reload: reject++\n",
2145 /* Strict_low_part requires to reload the register
2146 not the sub-register. In this case we should
2147 check that a final reload hard reg can hold the
2149 if (curr_static_id->operand[nop].strict_low
2151 && hard_regno[nop] < 0
2152 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2153 && ira_class_hard_regs_num[this_alternative] > 0
2154 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2155 [this_alternative][0],
2157 (*curr_id->operand_loc[nop])))
2159 if (lra_dump_file != NULL)
2162 " alt=%d: Strict low subreg reload -- refuse\n",
2168 if (operand_reg[nop] != NULL_RTX
2169 /* Output operands and matched input operands are
2170 not inherited. The following conditions do not
2171 exactly describe the previous statement but they
2172 are pretty close. */
2173 && curr_static_id->operand[nop].type != OP_OUT
2174 && (this_alternative_matches < 0
2175 || curr_static_id->operand[nop].type != OP_IN))
2177 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2181 /* The value of reload_sum has sense only if we
2182 process insns in their order. It happens only on
2183 the first constraints sub-pass when we do most of
2185 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2186 reload_sum += last_reload - bb_reload_num;
2188 /* If this is a constant that is reloaded into the
2189 desired class by copying it to memory first, count
2190 that as another reload. This is consistent with
2191 other code and is required to avoid choosing another
2192 alternative when the constant is moved into memory.
2193 Note that the test here is precisely the same as in
2194 the code below that calls force_const_mem. */
2195 if (CONST_POOL_OK_P (mode, op)
2196 && ((targetm.preferred_reload_class
2197 (op, this_alternative) == NO_REGS)
2198 || no_input_reloads_p))
2205 /* Alternative loses if it requires a type of reload not
2206 permitted for this insn. We can always reload
2207 objects with a REG_UNUSED note. */
2208 if ((curr_static_id->operand[nop].type != OP_IN
2209 && no_output_reloads_p
2210 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2211 || (curr_static_id->operand[nop].type != OP_OUT
2212 && no_input_reloads_p && ! const_to_mem)
2213 || (this_alternative_matches >= 0
2214 && (no_input_reloads_p
2215 || (no_output_reloads_p
2216 && (curr_static_id->operand
2217 [this_alternative_matches].type != OP_IN)
2218 && ! find_reg_note (curr_insn, REG_UNUSED,
2219 no_subreg_reg_operand
2220 [this_alternative_matches])))))
2222 if (lra_dump_file != NULL)
2225 " alt=%d: No input/otput reload -- refuse\n",
2230 /* Check strong discouragement of reload of non-constant
2231 into class THIS_ALTERNATIVE. */
2232 if (! CONSTANT_P (op) && ! no_regs_p
2233 && (targetm.preferred_reload_class
2234 (op, this_alternative) == NO_REGS
2235 || (curr_static_id->operand[nop].type == OP_OUT
2236 && (targetm.preferred_output_reload_class
2237 (op, this_alternative) == NO_REGS))))
2239 if (lra_dump_file != NULL)
2240 fprintf (lra_dump_file,
2241 " %d Non-prefered reload: reject+=%d\n",
2242 nop, LRA_MAX_REJECT);
2243 reject += LRA_MAX_REJECT;
2246 if (! (MEM_P (op) && offmemok)
2247 && ! (const_to_mem && constmemok))
2249 /* We prefer to reload pseudos over reloading other
2250 things, since such reloads may be able to be
2251 eliminated later. So bump REJECT in other cases.
2252 Don't do this in the case where we are forcing a
2253 constant into memory and it will then win since
2254 we don't want to have a different alternative
2256 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2258 if (lra_dump_file != NULL)
2261 " %d Non-pseudo reload: reject+=2\n",
2268 += ira_reg_class_max_nregs[this_alternative][mode];
2270 if (SMALL_REGISTER_CLASS_P (this_alternative))
2272 if (lra_dump_file != NULL)
2275 " %d Small class reload: reject+=%d\n",
2276 nop, LRA_LOSER_COST_FACTOR / 2);
2277 reject += LRA_LOSER_COST_FACTOR / 2;
2281 /* We are trying to spill pseudo into memory. It is
2282 usually more costly than moving to a hard register
2283 although it might takes the same number of
2285 if (no_regs_p && REG_P (op) && hard_regno[nop] >= 0)
2287 if (lra_dump_file != NULL)
2290 " %d Spill pseudo in memory: reject+=3\n",
2295 #ifdef SECONDARY_MEMORY_NEEDED
2296 /* If reload requires moving value through secondary
2297 memory, it will need one more insn at least. */
2298 if (this_alternative != NO_REGS
2299 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2300 && ((curr_static_id->operand[nop].type != OP_OUT
2301 && SECONDARY_MEMORY_NEEDED (cl, this_alternative,
2303 || (curr_static_id->operand[nop].type != OP_IN
2304 && SECONDARY_MEMORY_NEEDED (this_alternative, cl,
2308 /* Input reloads can be inherited more often than output
2309 reloads can be removed, so penalize output
2311 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2313 if (lra_dump_file != NULL)
2316 " %d Non input pseudo reload: reject++\n",
2322 if (early_clobber_p && ! scratch_p)
2324 if (lra_dump_file != NULL)
2325 fprintf (lra_dump_file,
2326 " %d Early clobber: reject++\n", nop);
2329 /* ??? We check early clobbers after processing all operands
2330 (see loop below) and there we update the costs more.
2331 Should we update the cost (may be approximately) here
2332 because of early clobber register reloads or it is a rare
2333 or non-important thing to be worth to do it. */
2334 overall = losers * LRA_LOSER_COST_FACTOR + reject;
2335 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2337 if (lra_dump_file != NULL)
2338 fprintf (lra_dump_file,
2339 " alt=%d,overall=%d,losers=%d -- refuse\n",
2340 nalt, overall, losers);
2344 curr_alt[nop] = this_alternative;
2345 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2346 curr_alt_win[nop] = this_alternative_win;
2347 curr_alt_match_win[nop] = this_alternative_match_win;
2348 curr_alt_offmemok[nop] = this_alternative_offmemok;
2349 curr_alt_matches[nop] = this_alternative_matches;
2351 if (this_alternative_matches >= 0
2352 && !did_match && !this_alternative_win)
2353 curr_alt_win[this_alternative_matches] = false;
2355 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2356 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2358 if (curr_insn_set != NULL_RTX && n_operands == 2
2359 /* Prevent processing non-move insns. */
2360 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2361 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2362 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2363 && REG_P (no_subreg_reg_operand[0])
2364 && REG_P (no_subreg_reg_operand[1])
2365 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2366 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2367 || (! curr_alt_win[0] && curr_alt_win[1]
2368 && REG_P (no_subreg_reg_operand[1])
2369 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2370 || (curr_alt_win[0] && ! curr_alt_win[1]
2371 && REG_P (no_subreg_reg_operand[0])
2372 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2373 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2374 no_subreg_reg_operand[1])
2375 || (targetm.preferred_reload_class
2376 (no_subreg_reg_operand[1],
2377 (enum reg_class) curr_alt[1]) != NO_REGS))
2378 /* If it is a result of recent elimination in move
2379 insn we can transform it into an add still by
2380 using this alternative. */
2381 && GET_CODE (no_subreg_reg_operand[1]) != PLUS)))
2383 /* We have a move insn and a new reload insn will be similar
2384 to the current insn. We should avoid such situation as it
2385 results in LRA cycling. */
2386 overall += LRA_MAX_REJECT;
2389 curr_alt_dont_inherit_ops_num = 0;
2390 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2392 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2393 HARD_REG_SET temp_set;
2395 i = early_clobbered_nops[nop];
2396 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2397 || hard_regno[i] < 0)
2399 lra_assert (operand_reg[i] != NULL_RTX);
2400 clobbered_hard_regno = hard_regno[i];
2401 CLEAR_HARD_REG_SET (temp_set);
2402 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2403 first_conflict_j = last_conflict_j = -1;
2404 for (j = 0; j < n_operands; j++)
2406 /* We don't want process insides of match_operator and
2407 match_parallel because otherwise we would process
2408 their operands once again generating a wrong
2410 || curr_static_id->operand[j].is_operator)
2412 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2413 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2415 /* If we don't reload j-th operand, check conflicts. */
2416 else if ((curr_alt_win[j] || curr_alt_match_win[j])
2417 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2419 if (first_conflict_j < 0)
2420 first_conflict_j = j;
2421 last_conflict_j = j;
2423 if (last_conflict_j < 0)
2425 /* If earlyclobber operand conflicts with another
2426 non-matching operand which is actually the same register
2427 as the earlyclobber operand, it is better to reload the
2428 another operand as an operand matching the earlyclobber
2429 operand can be also the same. */
2430 if (first_conflict_j == last_conflict_j
2431 && operand_reg[last_conflict_j]
2432 != NULL_RTX && ! curr_alt_match_win[last_conflict_j]
2433 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2435 curr_alt_win[last_conflict_j] = false;
2436 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2439 /* Early clobber was already reflected in REJECT. */
2440 lra_assert (reject > 0);
2441 if (lra_dump_file != NULL)
2444 " %d Conflict early clobber reload: reject--\n",
2447 overall += LRA_LOSER_COST_FACTOR - 1;
2451 /* We need to reload early clobbered register and the
2452 matched registers. */
2453 for (j = 0; j < n_operands; j++)
2454 if (curr_alt_matches[j] == i)
2456 curr_alt_match_win[j] = false;
2458 overall += LRA_LOSER_COST_FACTOR;
2460 if (! curr_alt_match_win[i])
2461 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2464 /* Remember pseudos used for match reloads are never
2466 lra_assert (curr_alt_matches[i] >= 0);
2467 curr_alt_win[curr_alt_matches[i]] = false;
2469 curr_alt_win[i] = curr_alt_match_win[i] = false;
2471 /* Early clobber was already reflected in REJECT. */
2472 lra_assert (reject > 0);
2473 if (lra_dump_file != NULL)
2476 " %d Matched conflict early clobber reloads:"
2480 overall += LRA_LOSER_COST_FACTOR - 1;
2483 if (lra_dump_file != NULL)
2484 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2485 nalt, overall, losers, reload_nregs);
2487 /* If this alternative can be made to work by reloading, and it
2488 needs less reloading than the others checked so far, record
2489 it as the chosen goal for reloading. */
2490 if ((best_losers != 0 && losers == 0)
2491 || (((best_losers == 0 && losers == 0)
2492 || (best_losers != 0 && losers != 0))
2493 && (best_overall > overall
2494 || (best_overall == overall
2495 /* If the cost of the reloads is the same,
2496 prefer alternative which requires minimal
2497 number of reload regs. */
2498 && (reload_nregs < best_reload_nregs
2499 || (reload_nregs == best_reload_nregs
2500 && (best_reload_sum < reload_sum
2501 || (best_reload_sum == reload_sum
2502 && nalt < goal_alt_number))))))))
2504 for (nop = 0; nop < n_operands; nop++)
2506 goal_alt_win[nop] = curr_alt_win[nop];
2507 goal_alt_match_win[nop] = curr_alt_match_win[nop];
2508 goal_alt_matches[nop] = curr_alt_matches[nop];
2509 goal_alt[nop] = curr_alt[nop];
2510 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
2512 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
2513 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
2514 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
2515 goal_alt_swapped = curr_swapped;
2516 best_overall = overall;
2517 best_losers = losers;
2518 best_reload_nregs = reload_nregs;
2519 best_reload_sum = reload_sum;
2520 goal_alt_number = nalt;
2523 /* Everything is satisfied. Do not process alternatives
2532 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2533 space AS, and check that each pseudo has the proper kind of hard
2536 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2537 rtx addr, addr_space_t as)
2539 #ifdef GO_IF_LEGITIMATE_ADDRESS
2540 lra_assert (ADDR_SPACE_GENERIC_P (as));
2541 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
2547 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
2551 /* Return whether address AD is valid. */
2554 valid_address_p (struct address_info *ad)
2556 /* Some ports do not check displacements for eliminable registers,
2557 so we replace them temporarily with the elimination target. */
2558 rtx saved_base_reg = NULL_RTX;
2559 rtx saved_index_reg = NULL_RTX;
2560 rtx *base_term = strip_subreg (ad->base_term);
2561 rtx *index_term = strip_subreg (ad->index_term);
2562 if (base_term != NULL)
2564 saved_base_reg = *base_term;
2565 lra_eliminate_reg_if_possible (base_term);
2566 if (ad->base_term2 != NULL)
2567 *ad->base_term2 = *ad->base_term;
2569 if (index_term != NULL)
2571 saved_index_reg = *index_term;
2572 lra_eliminate_reg_if_possible (index_term);
2574 bool ok_p = valid_address_p (ad->mode, *ad->outer, ad->as);
2575 if (saved_base_reg != NULL_RTX)
2577 *base_term = saved_base_reg;
2578 if (ad->base_term2 != NULL)
2579 *ad->base_term2 = *ad->base_term;
2581 if (saved_index_reg != NULL_RTX)
2582 *index_term = saved_index_reg;
2586 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2588 base_plus_disp_to_reg (struct address_info *ad)
2593 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
2594 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
2595 get_index_code (ad));
2596 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
2598 lra_emit_add (new_reg, *ad->base_term, *ad->disp_term);
2602 /* Return true if we can add a displacement to address AD, even if that
2603 makes the address invalid. The fix-up code requires any new address
2604 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2606 can_add_disp_p (struct address_info *ad)
2608 return (!ad->autoinc_p
2609 && ad->segment == NULL
2610 && ad->base == ad->base_term
2611 && ad->disp == ad->disp_term);
2614 /* Make equiv substitution in address AD. Return true if a substitution
2617 equiv_address_substitution (struct address_info *ad)
2619 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
2620 HOST_WIDE_INT disp, scale;
2623 base_term = strip_subreg (ad->base_term);
2624 if (base_term == NULL)
2625 base_reg = new_base_reg = NULL_RTX;
2628 base_reg = *base_term;
2629 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
2631 index_term = strip_subreg (ad->index_term);
2632 if (index_term == NULL)
2633 index_reg = new_index_reg = NULL_RTX;
2636 index_reg = *index_term;
2637 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
2639 if (base_reg == new_base_reg && index_reg == new_index_reg)
2643 if (lra_dump_file != NULL)
2645 fprintf (lra_dump_file, "Changing address in insn %d ",
2646 INSN_UID (curr_insn));
2647 dump_value_slim (lra_dump_file, *ad->outer, 1);
2649 if (base_reg != new_base_reg)
2651 if (REG_P (new_base_reg))
2653 *base_term = new_base_reg;
2656 else if (GET_CODE (new_base_reg) == PLUS
2657 && REG_P (XEXP (new_base_reg, 0))
2658 && CONST_INT_P (XEXP (new_base_reg, 1))
2659 && can_add_disp_p (ad))
2661 disp += INTVAL (XEXP (new_base_reg, 1));
2662 *base_term = XEXP (new_base_reg, 0);
2665 if (ad->base_term2 != NULL)
2666 *ad->base_term2 = *ad->base_term;
2668 if (index_reg != new_index_reg)
2670 if (REG_P (new_index_reg))
2672 *index_term = new_index_reg;
2675 else if (GET_CODE (new_index_reg) == PLUS
2676 && REG_P (XEXP (new_index_reg, 0))
2677 && CONST_INT_P (XEXP (new_index_reg, 1))
2678 && can_add_disp_p (ad)
2679 && (scale = get_index_scale (ad)))
2681 disp += INTVAL (XEXP (new_index_reg, 1)) * scale;
2682 *index_term = XEXP (new_index_reg, 0);
2688 if (ad->disp != NULL)
2689 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
2692 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
2693 update_address (ad);
2697 if (lra_dump_file != NULL)
2700 fprintf (lra_dump_file, " -- no change\n");
2703 fprintf (lra_dump_file, " on equiv ");
2704 dump_value_slim (lra_dump_file, *ad->outer, 1);
2705 fprintf (lra_dump_file, "\n");
2711 /* Major function to make reloads for an address in operand NOP.
2712 The supported cases are:
2714 1) an address that existed before LRA started, at which point it
2715 must have been valid. These addresses are subject to elimination
2716 and may have become invalid due to the elimination offset being out
2719 2) an address created by forcing a constant to memory
2720 (force_const_to_mem). The initial form of these addresses might
2721 not be valid, and it is this function's job to make them valid.
2723 3) a frame address formed from a register and a (possibly zero)
2724 constant offset. As above, these addresses might not be valid and
2725 this function must make them so.
2727 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2728 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2729 address. Return true for any RTL change. */
2731 process_address (int nop, rtx *before, rtx *after)
2733 struct address_info ad;
2735 rtx op = *curr_id->operand_loc[nop];
2736 const char *constraint = curr_static_id->operand[nop].constraint;
2739 if (constraint[0] == 'p'
2740 || EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint))
2741 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
2742 else if (MEM_P (op))
2743 decompose_mem_address (&ad, op);
2744 else if (GET_CODE (op) == SUBREG
2745 && MEM_P (SUBREG_REG (op)))
2746 decompose_mem_address (&ad, SUBREG_REG (op));
2749 change_p = equiv_address_substitution (&ad);
2750 if (ad.base_term != NULL
2751 && (process_addr_reg
2752 (ad.base_term, before,
2754 && !(REG_P (*ad.base_term)
2755 && find_regno_note (curr_insn, REG_DEAD,
2756 REGNO (*ad.base_term)) != NULL_RTX)
2758 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
2759 get_index_code (&ad)))))
2762 if (ad.base_term2 != NULL)
2763 *ad.base_term2 = *ad.base_term;
2765 if (ad.index_term != NULL
2766 && process_addr_reg (ad.index_term, before, NULL, INDEX_REG_CLASS))
2769 #ifdef EXTRA_CONSTRAINT_STR
2770 /* Target hooks sometimes reject extra constraint addresses -- use
2771 EXTRA_CONSTRAINT_STR for the validation. */
2772 if (constraint[0] != 'p'
2773 && EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint)
2774 && EXTRA_CONSTRAINT_STR (op, constraint[0], constraint))
2778 /* There are three cases where the shape of *AD.INNER may now be invalid:
2780 1) the original address was valid, but either elimination or
2781 equiv_address_substitution was applied and that made
2782 the address invalid.
2784 2) the address is an invalid symbolic address created by
2787 3) the address is a frame address with an invalid offset.
2789 All these cases involve a non-autoinc address, so there is no
2790 point revalidating other types. */
2791 if (ad.autoinc_p || valid_address_p (&ad))
2794 /* Any index existed before LRA started, so we can assume that the
2795 presence and shape of the index is valid. */
2796 push_to_sequence (*before);
2797 lra_assert (ad.disp == ad.disp_term);
2798 if (ad.base == NULL)
2800 if (ad.index == NULL)
2803 enum reg_class cl = base_reg_class (ad.mode, ad.as,
2805 rtx addr = *ad.inner;
2807 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
2811 rtx last = get_last_insn ();
2813 /* addr => lo_sum (new_base, addr), case (2) above. */
2814 insn = emit_insn (gen_rtx_SET
2816 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
2817 code = recog_memoized (insn);
2820 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
2821 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
2823 /* Try to put lo_sum into register. */
2824 insn = emit_insn (gen_rtx_SET
2826 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
2827 code = recog_memoized (insn);
2830 *ad.inner = new_reg;
2831 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
2841 delete_insns_since (last);
2846 /* addr => new_base, case (2) above. */
2847 lra_emit_move (new_reg, addr);
2848 *ad.inner = new_reg;
2853 /* index * scale + disp => new base + index * scale,
2855 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
2856 GET_CODE (*ad.index));
2858 lra_assert (INDEX_REG_CLASS != NO_REGS);
2859 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
2860 lra_emit_move (new_reg, *ad.disp);
2861 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
2862 new_reg, *ad.index);
2865 else if (ad.index == NULL)
2869 rtx set, insns, last_insn;
2870 /* base + disp => new base, cases (1) and (3) above. */
2871 /* Another option would be to reload the displacement into an
2872 index register. However, postreload has code to optimize
2873 address reloads that have the same base and different
2874 displacements, so reloading into an index register would
2875 not necessarily be a win. */
2877 new_reg = base_plus_disp_to_reg (&ad);
2878 insns = get_insns ();
2879 last_insn = get_last_insn ();
2880 /* If we generated at least two insns, try last insn source as
2881 an address. If we succeed, we generate one less insn. */
2882 if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX
2883 && GET_CODE (SET_SRC (set)) == PLUS
2884 && REG_P (XEXP (SET_SRC (set), 0))
2885 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
2887 *ad.inner = SET_SRC (set);
2888 if (valid_address_p (ad.mode, *ad.outer, ad.as))
2890 *ad.base_term = XEXP (SET_SRC (set), 0);
2891 *ad.disp_term = XEXP (SET_SRC (set), 1);
2892 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
2893 get_index_code (&ad));
2894 regno = REGNO (*ad.base_term);
2895 if (regno >= FIRST_PSEUDO_REGISTER
2896 && cl != lra_get_allocno_class (regno))
2897 lra_change_class (regno, cl, " Change to", true);
2898 new_reg = SET_SRC (set);
2899 delete_insns_since (PREV_INSN (last_insn));
2904 *ad.inner = new_reg;
2908 /* base + scale * index + disp => new base + scale * index,
2910 new_reg = base_plus_disp_to_reg (&ad);
2911 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
2912 new_reg, *ad.index);
2914 *before = get_insns ();
2919 /* Emit insns to reload VALUE into a new register. VALUE is an
2920 auto-increment or auto-decrement RTX whose operand is a register or
2921 memory location; so reloading involves incrementing that location.
2922 IN is either identical to VALUE, or some cheaper place to reload
2923 value being incremented/decremented from.
2925 INC_AMOUNT is the number to increment or decrement by (always
2926 positive and ignored for POST_MODIFY/PRE_MODIFY).
2928 Return pseudo containing the result. */
2930 emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount)
2932 /* REG or MEM to be copied and incremented. */
2933 rtx incloc = XEXP (value, 0);
2934 /* Nonzero if increment after copying. */
2935 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
2936 || GET_CODE (value) == POST_MODIFY);
2941 rtx real_in = in == value ? incloc : in;
2945 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
2947 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
2948 || GET_CODE (XEXP (value, 1)) == MINUS);
2949 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
2950 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
2951 inc = XEXP (XEXP (value, 1), 1);
2955 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
2956 inc_amount = -inc_amount;
2958 inc = GEN_INT (inc_amount);
2961 if (! post && REG_P (incloc))
2964 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
2967 if (real_in != result)
2969 /* First copy the location to the result register. */
2970 lra_assert (REG_P (result));
2971 emit_insn (gen_move_insn (result, real_in));
2974 /* We suppose that there are insns to add/sub with the constant
2975 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2976 old reload worked with this assumption. If the assumption
2977 becomes wrong, we should use approach in function
2978 base_plus_disp_to_reg. */
2981 /* See if we can directly increment INCLOC. */
2982 last = get_last_insn ();
2983 add_insn = emit_insn (plus_p
2984 ? gen_add2_insn (incloc, inc)
2985 : gen_sub2_insn (incloc, inc));
2987 code = recog_memoized (add_insn);
2990 if (! post && result != incloc)
2991 emit_insn (gen_move_insn (result, incloc));
2994 delete_insns_since (last);
2997 /* If couldn't do the increment directly, must increment in RESULT.
2998 The way we do this depends on whether this is pre- or
2999 post-increment. For pre-increment, copy INCLOC to the reload
3000 register, increment it there, then save back. */
3003 if (real_in != result)
3004 emit_insn (gen_move_insn (result, real_in));
3006 emit_insn (gen_add2_insn (result, inc));
3008 emit_insn (gen_sub2_insn (result, inc));
3009 if (result != incloc)
3010 emit_insn (gen_move_insn (incloc, result));
3016 Because this might be a jump insn or a compare, and because
3017 RESULT may not be available after the insn in an input
3018 reload, we must do the incrementing before the insn being
3021 We have already copied IN to RESULT. Increment the copy in
3022 RESULT, save that back, then decrement RESULT so it has
3023 the original value. */
3025 emit_insn (gen_add2_insn (result, inc));
3027 emit_insn (gen_sub2_insn (result, inc));
3028 emit_insn (gen_move_insn (incloc, result));
3029 /* Restore non-modified value for the result. We prefer this
3030 way because it does not require an additional hard
3034 if (CONST_INT_P (inc))
3035 emit_insn (gen_add2_insn (result,
3036 gen_int_mode (-INTVAL (inc),
3037 GET_MODE (result))));
3039 emit_insn (gen_sub2_insn (result, inc));
3042 emit_insn (gen_add2_insn (result, inc));
3047 /* Return true if the current move insn does not need processing as we
3048 already know that it satisfies its constraints. */
3050 simple_move_p (void)
3053 enum reg_class dclass, sclass;
3055 lra_assert (curr_insn_set != NULL_RTX);
3056 dest = SET_DEST (curr_insn_set);
3057 src = SET_SRC (curr_insn_set);
3058 return ((dclass = get_op_class (dest)) != NO_REGS
3059 && (sclass = get_op_class (src)) != NO_REGS
3060 /* The backend guarantees that register moves of cost 2
3061 never need reloads. */
3062 && targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2);
3065 /* Swap operands NOP and NOP + 1. */
3067 swap_operands (int nop)
3069 enum machine_mode mode = curr_operand_mode[nop];
3070 curr_operand_mode[nop] = curr_operand_mode[nop + 1];
3071 curr_operand_mode[nop + 1] = mode;
3072 rtx x = *curr_id->operand_loc[nop];
3073 *curr_id->operand_loc[nop] = *curr_id->operand_loc[nop + 1];
3074 *curr_id->operand_loc[nop + 1] = x;
3075 /* Swap the duplicates too. */
3076 lra_update_dup (curr_id, nop);
3077 lra_update_dup (curr_id, nop + 1);
3080 /* Main entry point of the constraint code: search the body of the
3081 current insn to choose the best alternative. It is mimicking insn
3082 alternative cost calculation model of former reload pass. That is
3083 because machine descriptions were written to use this model. This
3084 model can be changed in future. Make commutative operand exchange
3087 Return true if some RTL changes happened during function call. */
3089 curr_insn_transform (void)
3095 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3096 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3099 /* Flag that the insn has been changed through a transformation. */
3102 #ifdef SECONDARY_MEMORY_NEEDED
3105 int max_regno_before;
3106 int reused_alternative_num;
3108 curr_insn_set = single_set (curr_insn);
3109 if (curr_insn_set != NULL_RTX && simple_move_p ())
3112 no_input_reloads_p = no_output_reloads_p = false;
3113 goal_alt_number = -1;
3114 change_p = sec_mem_p = false;
3115 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3116 reloads; neither are insns that SET cc0. Insns that use CC0 are
3117 not allowed to have any input reloads. */
3118 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3119 no_output_reloads_p = true;
3122 if (reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3123 no_input_reloads_p = true;
3124 if (reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3125 no_output_reloads_p = true;
3128 n_operands = curr_static_id->n_operands;
3129 n_alternatives = curr_static_id->n_alternatives;
3131 /* Just return "no reloads" if insn has no operands with
3133 if (n_operands == 0 || n_alternatives == 0)
3136 max_regno_before = max_reg_num ();
3138 for (i = 0; i < n_operands; i++)
3140 goal_alt_matched[i][0] = -1;
3141 goal_alt_matches[i] = -1;
3144 commutative = curr_static_id->commutative;
3146 /* Now see what we need for pseudos that didn't get hard regs or got
3147 the wrong kind of hard reg. For this, we must consider all the
3148 operands together against the register constraints. */
3150 best_losers = best_overall = INT_MAX;
3151 best_reload_sum = 0;
3153 curr_swapped = false;
3154 goal_alt_swapped = false;
3156 /* Make equivalence substitution and memory subreg elimination
3157 before address processing because an address legitimacy can
3158 depend on memory mode. */
3159 for (i = 0; i < n_operands; i++)
3161 rtx op = *curr_id->operand_loc[i];
3162 rtx subst, old = op;
3163 bool op_change_p = false;
3165 if (GET_CODE (old) == SUBREG)
3166 old = SUBREG_REG (old);
3167 subst = get_equiv_with_elimination (old, curr_insn);
3170 subst = copy_rtx (subst);
3171 lra_assert (REG_P (old));
3172 if (GET_CODE (op) == SUBREG)
3173 SUBREG_REG (op) = subst;
3175 *curr_id->operand_loc[i] = subst;
3176 if (lra_dump_file != NULL)
3178 fprintf (lra_dump_file,
3179 "Changing pseudo %d in operand %i of insn %u on equiv ",
3180 REGNO (old), i, INSN_UID (curr_insn));
3181 dump_value_slim (lra_dump_file, subst, 1);
3182 fprintf (lra_dump_file, "\n");
3184 op_change_p = change_p = true;
3186 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3189 lra_update_dup (curr_id, i);
3193 /* Reload address registers and displacements. We do it before
3194 finding an alternative because of memory constraints. */
3195 before = after = NULL_RTX;
3196 for (i = 0; i < n_operands; i++)
3197 if (! curr_static_id->operand[i].is_operator
3198 && process_address (i, &before, &after))
3201 lra_update_dup (curr_id, i);
3205 /* If we've changed the instruction then any alternative that
3206 we chose previously may no longer be valid. */
3207 lra_set_used_insn_alternative (curr_insn, -1);
3209 if (curr_insn_set != NULL_RTX
3210 && check_and_process_move (&change_p, &sec_mem_p))
3215 reused_alternative_num = curr_id->used_insn_alternative;
3216 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3217 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3218 reused_alternative_num, INSN_UID (curr_insn));
3220 if (process_alt_operands (reused_alternative_num))
3223 /* If insn is commutative (it's safe to exchange a certain pair of
3224 operands) then we need to try each alternative twice, the second
3225 time matching those two operands as if we had exchanged them. To
3226 do this, really exchange them in operands.
3228 If we have just tried the alternatives the second time, return
3229 operands to normal and drop through. */
3231 if (reused_alternative_num < 0 && commutative >= 0)
3233 curr_swapped = !curr_swapped;
3236 swap_operands (commutative);
3240 swap_operands (commutative);
3243 if (! alt_p && ! sec_mem_p)
3245 /* No alternative works with reloads?? */
3246 if (INSN_CODE (curr_insn) >= 0)
3247 fatal_insn ("unable to generate reloads for:", curr_insn);
3248 error_for_asm (curr_insn,
3249 "inconsistent operand constraints in an %<asm%>");
3250 /* Avoid further trouble with this insn. */
3251 PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3252 lra_invalidate_insn_data (curr_insn);
3256 /* If the best alternative is with operands 1 and 2 swapped, swap
3257 them. Update the operand numbers of any reloads already
3260 if (goal_alt_swapped)
3262 if (lra_dump_file != NULL)
3263 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
3264 INSN_UID (curr_insn));
3266 /* Swap the duplicates too. */
3267 swap_operands (commutative);
3271 #ifdef SECONDARY_MEMORY_NEEDED
3272 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3273 too conservatively. So we use the secondary memory only if there
3274 is no any alternative without reloads. */
3275 use_sec_mem_p = false;
3277 use_sec_mem_p = true;
3280 for (i = 0; i < n_operands; i++)
3281 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3283 use_sec_mem_p = i < n_operands;
3288 rtx new_reg, src, dest, rld;
3289 enum machine_mode sec_mode, rld_mode;
3291 lra_assert (sec_mem_p);
3292 lra_assert (curr_static_id->operand[0].type == OP_OUT
3293 && curr_static_id->operand[1].type == OP_IN);
3294 dest = *curr_id->operand_loc[0];
3295 src = *curr_id->operand_loc[1];
3296 rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src))
3298 rld_mode = GET_MODE (rld);
3299 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3300 sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode);
3302 sec_mode = rld_mode;
3304 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3305 NO_REGS, "secondary");
3306 /* If the mode is changed, it should be wider. */
3307 lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode));
3308 if (sec_mode != rld_mode)
3310 /* If the target says specifically to use another mode for
3311 secondary memory moves we can not reuse the original
3313 after = emit_spill_move (false, new_reg, dest);
3314 lra_process_new_insns (curr_insn, NULL_RTX, after,
3315 "Inserting the sec. move");
3316 /* We may have non null BEFORE here (e.g. after address
3318 push_to_sequence (before);
3319 before = emit_spill_move (true, new_reg, src);
3321 before = get_insns ();
3323 lra_process_new_insns (curr_insn, before, NULL_RTX, "Changing on");
3324 lra_set_insn_deleted (curr_insn);
3326 else if (dest == rld)
3328 *curr_id->operand_loc[0] = new_reg;
3329 after = emit_spill_move (false, new_reg, dest);
3330 lra_process_new_insns (curr_insn, NULL_RTX, after,
3331 "Inserting the sec. move");
3335 *curr_id->operand_loc[1] = new_reg;
3336 /* See comments above. */
3337 push_to_sequence (before);
3338 before = emit_spill_move (true, new_reg, src);
3340 before = get_insns ();
3342 lra_process_new_insns (curr_insn, before, NULL_RTX,
3343 "Inserting the sec. move");
3345 lra_update_insn_regno_info (curr_insn);
3350 lra_assert (goal_alt_number >= 0);
3351 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
3353 if (lra_dump_file != NULL)
3357 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
3358 goal_alt_number, INSN_UID (curr_insn));
3359 for (i = 0; i < n_operands; i++)
3361 p = (curr_static_id->operand_alternative
3362 [goal_alt_number * n_operands + i].constraint);
3365 fprintf (lra_dump_file, " (%d) ", i);
3366 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
3367 fputc (*p, lra_dump_file);
3369 if (INSN_CODE (curr_insn) >= 0
3370 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
3371 fprintf (lra_dump_file, " {%s}", p);
3372 if (curr_id->sp_offset != 0)
3373 fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)",
3374 curr_id->sp_offset);
3375 fprintf (lra_dump_file, "\n");
3378 /* Right now, for any pair of operands I and J that are required to
3379 match, with J < I, goal_alt_matches[I] is J. Add I to
3380 goal_alt_matched[J]. */
3382 for (i = 0; i < n_operands; i++)
3383 if ((j = goal_alt_matches[i]) >= 0)
3385 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
3387 /* We allow matching one output operand and several input
3390 || (curr_static_id->operand[j].type == OP_OUT
3391 && curr_static_id->operand[i].type == OP_IN
3392 && (curr_static_id->operand
3393 [goal_alt_matched[j][0]].type == OP_IN)));
3394 goal_alt_matched[j][k] = i;
3395 goal_alt_matched[j][k + 1] = -1;
3398 for (i = 0; i < n_operands; i++)
3399 goal_alt_win[i] |= goal_alt_match_win[i];
3401 /* Any constants that aren't allowed and can't be reloaded into
3402 registers are here changed into memory references. */
3403 for (i = 0; i < n_operands; i++)
3404 if (goal_alt_win[i])
3407 enum reg_class new_class;
3408 rtx reg = *curr_id->operand_loc[i];
3410 if (GET_CODE (reg) == SUBREG)
3411 reg = SUBREG_REG (reg);
3413 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
3415 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
3417 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
3420 lra_change_class (regno, new_class, " Change to", true);
3426 const char *constraint;
3428 rtx op = *curr_id->operand_loc[i];
3429 rtx subreg = NULL_RTX;
3430 enum machine_mode mode = curr_operand_mode[i];
3432 if (GET_CODE (op) == SUBREG)
3435 op = SUBREG_REG (op);
3436 mode = GET_MODE (op);
3439 if (CONST_POOL_OK_P (mode, op)
3440 && ((targetm.preferred_reload_class
3441 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
3442 || no_input_reloads_p))
3444 rtx tem = force_const_mem (mode, op);
3447 if (subreg != NULL_RTX)
3448 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
3450 *curr_id->operand_loc[i] = tem;
3451 lra_update_dup (curr_id, i);
3452 process_address (i, &before, &after);
3454 /* If the alternative accepts constant pool refs directly
3455 there will be no reload needed at all. */
3456 if (subreg != NULL_RTX)
3458 /* Skip alternatives before the one requested. */
3459 constraint = (curr_static_id->operand_alternative
3460 [goal_alt_number * n_operands + i].constraint);
3462 (c = *constraint) && c != ',' && c != '#';
3463 constraint += CONSTRAINT_LEN (c, constraint))
3465 if (c == TARGET_MEM_CONSTRAINT || c == 'o')
3467 #ifdef EXTRA_CONSTRAINT_STR
3468 if (EXTRA_MEMORY_CONSTRAINT (c, constraint)
3469 && EXTRA_CONSTRAINT_STR (tem, c, constraint))
3473 if (c == '\0' || c == ',' || c == '#')
3476 goal_alt_win[i] = true;
3480 for (i = 0; i < n_operands; i++)
3483 bool optional_p = false;
3485 rtx op = *curr_id->operand_loc[i];
3487 if (goal_alt_win[i])
3489 if (goal_alt[i] == NO_REGS
3491 /* When we assign NO_REGS it means that we will not
3492 assign a hard register to the scratch pseudo by
3493 assigment pass and the scratch pseudo will be
3494 spilled. Spilled scratch pseudos are transformed
3495 back to scratches at the LRA end. */
3496 && lra_former_scratch_operand_p (curr_insn, i))
3498 int regno = REGNO (op);
3499 lra_change_class (regno, NO_REGS, " Change to", true);
3500 if (lra_get_regno_hard_regno (regno) >= 0)
3501 /* We don't have to mark all insn affected by the
3502 spilled pseudo as there is only one such insn, the
3504 reg_renumber[regno] = -1;
3506 /* We can do an optional reload. If the pseudo got a hard
3507 reg, we might improve the code through inheritance. If
3508 it does not get a hard register we coalesce memory/memory
3509 moves later. Ignore move insns to avoid cycling. */
3511 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
3512 && goal_alt[i] != NO_REGS && REG_P (op)
3513 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
3514 && regno < new_regno_start
3515 && ! lra_former_scratch_p (regno)
3516 && reg_renumber[regno] < 0
3517 && (curr_insn_set == NULL_RTX
3518 || !((REG_P (SET_SRC (curr_insn_set))
3519 || MEM_P (SET_SRC (curr_insn_set))
3520 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
3521 && (REG_P (SET_DEST (curr_insn_set))
3522 || MEM_P (SET_DEST (curr_insn_set))
3523 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
3529 /* Operands that match previous ones have already been handled. */
3530 if (goal_alt_matches[i] >= 0)
3533 /* We should not have an operand with a non-offsettable address
3534 appearing where an offsettable address will do. It also may
3535 be a case when the address should be special in other words
3536 not a general one (e.g. it needs no index reg). */
3537 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
3539 enum reg_class rclass;
3540 rtx *loc = &XEXP (op, 0);
3541 enum rtx_code code = GET_CODE (*loc);
3543 push_to_sequence (before);
3544 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
3546 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
3547 new_reg = emit_inc (rclass, *loc, *loc,
3548 /* This value does not matter for MODIFY. */
3549 GET_MODE_SIZE (GET_MODE (op)));
3550 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass,
3551 "offsetable address", &new_reg))
3552 lra_emit_move (new_reg, *loc);
3553 before = get_insns ();
3556 lra_update_dup (curr_id, i);
3558 else if (goal_alt_matched[i][0] == -1)
3560 enum machine_mode mode;
3562 int hard_regno, byte;
3563 enum op_type type = curr_static_id->operand[i].type;
3565 loc = curr_id->operand_loc[i];
3566 mode = curr_operand_mode[i];
3567 if (GET_CODE (*loc) == SUBREG)
3569 reg = SUBREG_REG (*loc);
3570 byte = SUBREG_BYTE (*loc);
3572 /* Strict_low_part requires reload the register not
3573 the sub-register. */
3574 && (curr_static_id->operand[i].strict_low
3575 || (GET_MODE_SIZE (mode)
3576 <= GET_MODE_SIZE (GET_MODE (reg))
3578 = get_try_hard_regno (REGNO (reg))) >= 0
3579 && (simplify_subreg_regno
3581 GET_MODE (reg), byte, mode) < 0)
3582 && (goal_alt[i] == NO_REGS
3583 || (simplify_subreg_regno
3584 (ira_class_hard_regs[goal_alt[i]][0],
3585 GET_MODE (reg), byte, mode) >= 0)))))
3587 loc = &SUBREG_REG (*loc);
3588 mode = GET_MODE (*loc);
3592 if (get_reload_reg (type, mode, old, goal_alt[i], "", &new_reg)
3595 push_to_sequence (before);
3596 lra_emit_move (new_reg, old);
3597 before = get_insns ();
3602 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
3605 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
3607 after = get_insns ();
3611 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
3612 if (goal_alt_dont_inherit_ops[j] == i)
3614 lra_set_regno_unique_value (REGNO (new_reg));
3617 lra_update_dup (curr_id, i);
3619 else if (curr_static_id->operand[i].type == OP_IN
3620 && (curr_static_id->operand[goal_alt_matched[i][0]].type
3623 /* generate reloads for input and matched outputs. */
3624 match_inputs[0] = i;
3625 match_inputs[1] = -1;
3626 match_reload (goal_alt_matched[i][0], match_inputs,
3627 goal_alt[i], &before, &after);
3629 else if (curr_static_id->operand[i].type == OP_OUT
3630 && (curr_static_id->operand[goal_alt_matched[i][0]].type
3632 /* Generate reloads for output and matched inputs. */
3633 match_reload (i, goal_alt_matched[i], goal_alt[i], &before, &after);
3634 else if (curr_static_id->operand[i].type == OP_IN
3635 && (curr_static_id->operand[goal_alt_matched[i][0]].type
3638 /* Generate reloads for matched inputs. */
3639 match_inputs[0] = i;
3640 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
3641 match_inputs[j + 1] = k;
3642 match_inputs[j + 1] = -1;
3643 match_reload (-1, match_inputs, goal_alt[i], &before, &after);
3646 /* We must generate code in any case when function
3647 process_alt_operands decides that it is possible. */
3651 lra_assert (REG_P (op));
3653 op = *curr_id->operand_loc[i]; /* Substitution. */
3654 if (GET_CODE (op) == SUBREG)
3655 op = SUBREG_REG (op);
3656 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
3657 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
3658 lra_reg_info[REGNO (op)].restore_regno = regno;
3659 if (lra_dump_file != NULL)
3660 fprintf (lra_dump_file,
3661 " Making reload reg %d for reg %d optional\n",
3665 if (before != NULL_RTX || after != NULL_RTX
3666 || max_regno_before != max_reg_num ())
3670 lra_update_operator_dups (curr_id);
3671 /* Something changes -- process the insn. */
3672 lra_update_insn_regno_info (curr_insn);
3674 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
3678 /* Return true if X is in LIST. */
3680 in_list_p (rtx x, rtx list)
3682 for (; list != NULL_RTX; list = XEXP (list, 1))
3683 if (XEXP (list, 0) == x)
3688 /* Return true if X contains an allocatable hard register (if
3689 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3691 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
3697 code = GET_CODE (x);
3700 int regno = REGNO (x);
3701 HARD_REG_SET alloc_regs;
3705 if (regno >= FIRST_PSEUDO_REGISTER)
3706 regno = lra_get_regno_hard_regno (regno);
3709 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
3710 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
3714 if (regno < FIRST_PSEUDO_REGISTER)
3718 return lra_get_regno_hard_regno (regno) < 0;
3721 fmt = GET_RTX_FORMAT (code);
3722 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3726 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
3729 else if (fmt[i] == 'E')
3731 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3732 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
3739 /* Process all regs in location *LOC and change them on equivalent
3740 substitution. Return true if any change was done. */
3742 loc_equivalence_change_p (rtx *loc)
3744 rtx subst, reg, x = *loc;
3745 bool result = false;
3746 enum rtx_code code = GET_CODE (x);
3752 reg = SUBREG_REG (x);
3753 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
3754 && GET_MODE (subst) == VOIDmode)
3756 /* We cannot reload debug location. Simplify subreg here
3757 while we know the inner mode. */
3758 *loc = simplify_gen_subreg (GET_MODE (x), subst,
3759 GET_MODE (reg), SUBREG_BYTE (x));
3763 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
3769 /* Scan all the operand sub-expressions. */
3770 fmt = GET_RTX_FORMAT (code);
3771 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3774 result = loc_equivalence_change_p (&XEXP (x, i)) || result;
3775 else if (fmt[i] == 'E')
3776 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3778 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
3783 /* Similar to loc_equivalence_change_p, but for use as
3784 simplify_replace_fn_rtx callback. DATA is insn for which the
3785 elimination is done. If it null we don't do the elimination. */
3787 loc_equivalence_callback (rtx loc, const_rtx, void *data)
3792 rtx subst = (data == NULL
3793 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx) data));
3800 /* Maximum number of generated reload insns per an insn. It is for
3801 preventing this pass cycling in a bug case. */
3802 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3804 /* The current iteration number of this LRA pass. */
3805 int lra_constraint_iter;
3807 /* The current iteration number of this LRA pass after the last spill
3809 int lra_constraint_iter_after_spill;
3811 /* True if we substituted equiv which needs checking register
3812 allocation correctness because the equivalent value contains
3813 allocatable hard registers or when we restore multi-register
3815 bool lra_risky_transformations_p;
3817 /* Return true if REGNO is referenced in more than one block. */
3819 multi_block_pseudo_p (int regno)
3821 basic_block bb = NULL;
3825 if (regno < FIRST_PSEUDO_REGISTER)
3828 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
3830 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
3831 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
3836 /* Return true if LIST contains a deleted insn. */
3838 contains_deleted_insn_p (rtx list)
3840 for (; list != NULL_RTX; list = XEXP (list, 1))
3841 if (NOTE_P (XEXP (list, 0))
3842 && NOTE_KIND (XEXP (list, 0)) == NOTE_INSN_DELETED)
3847 /* Return true if X contains a pseudo dying in INSN. */
3849 dead_pseudo_p (rtx x, rtx insn)
3856 return (insn != NULL_RTX
3857 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
3858 code = GET_CODE (x);
3859 fmt = GET_RTX_FORMAT (code);
3860 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3864 if (dead_pseudo_p (XEXP (x, i), insn))
3867 else if (fmt[i] == 'E')
3869 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3870 if (dead_pseudo_p (XVECEXP (x, i, j), insn))
3877 /* Return true if INSN contains a dying pseudo in INSN right hand
3880 insn_rhs_dead_pseudo_p (rtx insn)
3882 rtx set = single_set (insn);
3884 gcc_assert (set != NULL);
3885 return dead_pseudo_p (SET_SRC (set), insn);
3888 /* Return true if any init insn of REGNO contains a dying pseudo in
3889 insn right hand side. */
3891 init_insn_rhs_dead_pseudo_p (int regno)
3893 rtx insns = ira_reg_equiv[regno].init_insns;
3898 return insn_rhs_dead_pseudo_p (insns);
3899 for (; insns != NULL_RTX; insns = XEXP (insns, 1))
3900 if (insn_rhs_dead_pseudo_p (XEXP (insns, 0)))
3905 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3906 reverse only if we have one init insn with given REGNO as a
3909 reverse_equiv_p (int regno)
3913 if ((insns = ira_reg_equiv[regno].init_insns) == NULL_RTX)
3915 if (! INSN_P (XEXP (insns, 0))
3916 || XEXP (insns, 1) != NULL_RTX)
3918 if ((set = single_set (XEXP (insns, 0))) == NULL_RTX)
3920 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
3923 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3924 call this function only for non-reverse equivalence. */
3926 contains_reloaded_insn_p (int regno)
3929 rtx list = ira_reg_equiv[regno].init_insns;
3931 for (; list != NULL_RTX; list = XEXP (list, 1))
3932 if ((set = single_set (XEXP (list, 0))) == NULL_RTX
3933 || ! REG_P (SET_DEST (set))
3934 || (int) REGNO (SET_DEST (set)) != regno)
3939 /* Entry function of LRA constraint pass. Return true if the
3940 constraint pass did change the code. */
3942 lra_constraints (bool first_p)
3945 int i, hard_regno, new_insns_num;
3946 unsigned int min_len, new_min_len, uid;
3947 rtx set, x, reg, dest_reg;
3948 basic_block last_bb;
3949 bitmap_head equiv_insn_bitmap;
3952 lra_constraint_iter++;
3953 if (lra_dump_file != NULL)
3954 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
3955 lra_constraint_iter);
3956 lra_constraint_iter_after_spill++;
3957 if (lra_constraint_iter_after_spill > LRA_MAX_CONSTRAINT_ITERATION_NUMBER)
3959 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3960 LRA_MAX_CONSTRAINT_ITERATION_NUMBER);
3962 lra_risky_transformations_p = false;
3963 new_insn_uid_start = get_max_uid ();
3964 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
3965 /* Mark used hard regs for target stack size calulations. */
3966 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
3967 if (lra_reg_info[i].nrefs != 0
3968 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
3972 nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode];
3973 for (j = 0; j < nregs; j++)
3974 df_set_regs_ever_live (hard_regno + j, true);
3976 /* Do elimination before the equivalence processing as we can spill
3977 some pseudos during elimination. */
3978 lra_eliminate (false, first_p);
3979 bitmap_initialize (&equiv_insn_bitmap, ®_obstack);
3980 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
3981 if (lra_reg_info[i].nrefs != 0)
3983 ira_reg_equiv[i].profitable_p = true;
3984 reg = regno_reg_rtx[i];
3985 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
3987 bool pseudo_p = contains_reg_p (x, false, false);
3989 /* After RTL transformation, we can not guarantee that
3990 pseudo in the substitution was not reloaded which might
3991 make equivalence invalid. For example, in reverse
3998 the memory address register was reloaded before the 2nd
4000 if ((! first_p && pseudo_p)
4001 /* We don't use DF for compilation speed sake. So it
4002 is problematic to update live info when we use an
4003 equivalence containing pseudos in more than one
4005 || (pseudo_p && multi_block_pseudo_p (i))
4006 /* If an init insn was deleted for some reason, cancel
4007 the equiv. We could update the equiv insns after
4008 transformations including an equiv insn deletion
4009 but it is not worthy as such cases are extremely
4011 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4012 /* If it is not a reverse equivalence, we check that a
4013 pseudo in rhs of the init insn is not dying in the
4014 insn. Otherwise, the live info at the beginning of
4015 the corresponding BB might be wrong after we
4016 removed the insn. When the equiv can be a
4017 constant, the right hand side of the init insn can
4019 || (! reverse_equiv_p (i)
4020 && (init_insn_rhs_dead_pseudo_p (i)
4021 /* If we reloaded the pseudo in an equivalence
4022 init insn, we can not remove the equiv init
4023 insns and the init insns might write into
4024 const memory in this case. */
4025 || contains_reloaded_insn_p (i)))
4026 /* Prevent access beyond equivalent memory for
4027 paradoxical subregs. */
4029 && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode)
4030 > GET_MODE_SIZE (GET_MODE (x)))))
4031 ira_reg_equiv[i].defined_p = false;
4032 if (contains_reg_p (x, false, true))
4033 ira_reg_equiv[i].profitable_p = false;
4034 if (get_equiv (reg) != reg)
4035 bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4038 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4040 /* We should add all insns containing pseudos which should be
4041 substituted by their equivalences. */
4042 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi)
4043 lra_push_insn_by_uid (uid);
4044 min_len = lra_insn_stack_length ();
4048 while ((new_min_len = lra_insn_stack_length ()) != 0)
4050 curr_insn = lra_pop_insn ();
4052 curr_bb = BLOCK_FOR_INSN (curr_insn);
4053 if (curr_bb != last_bb)
4056 bb_reload_num = lra_curr_reload_num;
4058 if (min_len > new_min_len)
4060 min_len = new_min_len;
4063 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4065 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4066 MAX_RELOAD_INSNS_NUMBER);
4068 if (DEBUG_INSN_P (curr_insn))
4070 /* We need to check equivalence in debug insn and change
4071 pseudo to the equivalent value if necessary. */
4072 curr_id = lra_get_insn_recog_data (curr_insn);
4073 if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)))
4075 rtx old = *curr_id->operand_loc[0];
4076 *curr_id->operand_loc[0]
4077 = simplify_replace_fn_rtx (old, NULL_RTX,
4078 loc_equivalence_callback, curr_insn);
4079 if (old != *curr_id->operand_loc[0])
4081 lra_update_insn_regno_info (curr_insn);
4086 else if (INSN_P (curr_insn))
4088 if ((set = single_set (curr_insn)) != NULL_RTX)
4090 dest_reg = SET_DEST (set);
4091 /* The equivalence pseudo could be set up as SUBREG in a
4092 case when it is a call restore insn in a mode
4093 different from the pseudo mode. */
4094 if (GET_CODE (dest_reg) == SUBREG)
4095 dest_reg = SUBREG_REG (dest_reg);
4096 if ((REG_P (dest_reg)
4097 && (x = get_equiv (dest_reg)) != dest_reg
4098 /* Remove insns which set up a pseudo whose value
4099 can not be changed. Such insns might be not in
4100 init_insns because we don't update equiv data
4101 during insn transformations.
4103 As an example, let suppose that a pseudo got
4104 hard register and on the 1st pass was not
4105 changed to equivalent constant. We generate an
4106 additional insn setting up the pseudo because of
4107 secondary memory movement. Then the pseudo is
4108 spilled and we use the equiv constant. In this
4109 case we should remove the additional insn and
4110 this insn is not init_insns list. */
4111 && (! MEM_P (x) || MEM_READONLY_P (x)
4112 /* Check that this is actually an insn setting
4113 up the equivalence. */
4114 || in_list_p (curr_insn,
4116 [REGNO (dest_reg)].init_insns)))
4117 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
4118 && in_list_p (curr_insn,
4120 [REGNO (SET_SRC (set))].init_insns)))
4122 /* This is equiv init insn of pseudo which did not get a
4123 hard register -- remove the insn. */
4124 if (lra_dump_file != NULL)
4126 fprintf (lra_dump_file,
4127 " Removing equiv init insn %i (freq=%d)\n",
4128 INSN_UID (curr_insn),
4129 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
4130 dump_insn_slim (lra_dump_file, curr_insn);
4132 if (contains_reg_p (x, true, false))
4133 lra_risky_transformations_p = true;
4134 lra_set_insn_deleted (curr_insn);
4138 curr_id = lra_get_insn_recog_data (curr_insn);
4139 curr_static_id = curr_id->insn_static_data;
4140 init_curr_insn_input_reloads ();
4141 init_curr_operand_mode ();
4142 if (curr_insn_transform ())
4144 /* Check non-transformed insns too for equiv change as USE
4145 or CLOBBER don't need reloads but can contain pseudos
4146 being changed on their equivalences. */
4147 else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))
4148 && loc_equivalence_change_p (&PATTERN (curr_insn)))
4150 lra_update_insn_regno_info (curr_insn);
4155 bitmap_clear (&equiv_insn_bitmap);
4156 /* If we used a new hard regno, changed_p should be true because the
4157 hard reg is assigned to a new pseudo. */
4158 #ifdef ENABLE_CHECKING
4161 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4162 if (lra_reg_info[i].nrefs != 0
4163 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4165 int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)];
4167 for (j = 0; j < nregs; j++)
4168 lra_assert (df_regs_ever_live_p (hard_regno + j));
4175 /* Initiate the LRA constraint pass. It is done once per
4178 lra_constraints_init (void)
4182 /* Finalize the LRA constraint pass. It is done once per
4185 lra_constraints_finish (void)
4191 /* This page contains code to do inheritance/split
4194 /* Number of reloads passed so far in current EBB. */
4195 static int reloads_num;
4197 /* Number of calls passed so far in current EBB. */
4198 static int calls_num;
4200 /* Current reload pseudo check for validity of elements in
4202 static int curr_usage_insns_check;
4204 /* Info about last usage of registers in EBB to do inheritance/split
4205 transformation. Inheritance transformation is done from a spilled
4206 pseudo and split transformations from a hard register or a pseudo
4207 assigned to a hard register. */
4210 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4211 value INSNS is valid. The insns is chain of optional debug insns
4212 and a finishing non-debug insn using the corresponding reg. The
4213 value is also used to mark the registers which are set up in the
4214 current insn. The negated insn uid is used for this. */
4216 /* Value of global reloads_num at the last insn in INSNS. */
4218 /* Value of global reloads_nums at the last insn in INSNS. */
4220 /* It can be true only for splitting. And it means that the restore
4221 insn should be put after insn given by the following member. */
4223 /* Next insns in the current EBB which use the original reg and the
4224 original reg value is not changed between the current insn and
4225 the next insns. In order words, e.g. for inheritance, if we need
4226 to use the original reg value again in the next insns we can try
4227 to use the value in a hard register from a reload insn of the
4232 /* Map: regno -> corresponding pseudo usage insns. */
4233 static struct usage_insns *usage_insns;
4236 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
4238 usage_insns[regno].check = curr_usage_insns_check;
4239 usage_insns[regno].insns = insn;
4240 usage_insns[regno].reloads_num = reloads_num;
4241 usage_insns[regno].calls_num = calls_num;
4242 usage_insns[regno].after_p = after_p;
4245 /* The function is used to form list REGNO usages which consists of
4246 optional debug insns finished by a non-debug insn using REGNO.
4247 RELOADS_NUM is current number of reload insns processed so far. */
4249 add_next_usage_insn (int regno, rtx insn, int reloads_num)
4251 rtx next_usage_insns;
4253 if (usage_insns[regno].check == curr_usage_insns_check
4254 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
4255 && DEBUG_INSN_P (insn))
4257 /* Check that we did not add the debug insn yet. */
4258 if (next_usage_insns != insn
4259 && (GET_CODE (next_usage_insns) != INSN_LIST
4260 || XEXP (next_usage_insns, 0) != insn))
4261 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
4264 else if (NONDEBUG_INSN_P (insn))
4265 setup_next_usage_insn (regno, insn, reloads_num, false);
4267 usage_insns[regno].check = 0;
4270 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4271 register NEW_REG. Return true if any change was made. */
4273 substitute_pseudo (rtx *loc, int old_regno, rtx new_reg)
4276 bool result = false;
4284 code = GET_CODE (x);
4285 if (code == REG && (int) REGNO (x) == old_regno)
4287 enum machine_mode mode = GET_MODE (*loc);
4288 enum machine_mode inner_mode = GET_MODE (new_reg);
4290 if (mode != inner_mode)
4292 if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode)
4293 || ! SCALAR_INT_MODE_P (inner_mode))
4294 new_reg = gen_rtx_SUBREG (mode, new_reg, 0);
4296 new_reg = gen_lowpart_SUBREG (mode, new_reg);
4302 /* Scan all the operand sub-expressions. */
4303 fmt = GET_RTX_FORMAT (code);
4304 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4308 if (substitute_pseudo (&XEXP (x, i), old_regno, new_reg))
4311 else if (fmt[i] == 'E')
4313 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4314 if (substitute_pseudo (&XVECEXP (x, i, j), old_regno, new_reg))
4321 /* Return first non-debug insn in list USAGE_INSNS. */
4323 skip_usage_debug_insns (rtx usage_insns)
4327 /* Skip debug insns. */
4328 for (insn = usage_insns;
4329 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
4330 insn = XEXP (insn, 1))
4335 /* Return true if we need secondary memory moves for insn in
4336 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4339 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
4340 rtx usage_insns ATTRIBUTE_UNUSED)
4342 #ifndef SECONDARY_MEMORY_NEEDED
4345 rtx insn, set, dest;
4348 if (inher_cl == ALL_REGS
4349 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
4351 lra_assert (INSN_P (insn));
4352 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
4354 dest = SET_DEST (set);
4357 lra_assert (inher_cl != NO_REGS);
4358 cl = get_reg_class (REGNO (dest));
4359 return (cl != NO_REGS && cl != ALL_REGS
4360 && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest)));
4364 /* Registers involved in inheritance/split in the current EBB
4365 (inheritance/split pseudos and original registers). */
4366 static bitmap_head check_only_regs;
4368 /* Do inheritance transformations for insn INSN, which defines (if
4369 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4370 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4371 form as the "insns" field of usage_insns. Return true if we
4372 succeed in such transformation.
4374 The transformations look like:
4377 ... p <- i (new insn)
4379 <- ... p ... <- ... i ...
4381 ... i <- p (new insn)
4382 <- ... p ... <- ... i ...
4384 <- ... p ... <- ... i ...
4385 where p is a spilled original pseudo and i is a new inheritance pseudo.
4388 The inheritance pseudo has the smallest class of two classes CL and
4389 class of ORIGINAL REGNO. */
4391 inherit_reload_reg (bool def_p, int original_regno,
4392 enum reg_class cl, rtx insn, rtx next_usage_insns)
4394 enum reg_class rclass = lra_get_allocno_class (original_regno);
4395 rtx original_reg = regno_reg_rtx[original_regno];
4396 rtx new_reg, new_insns, usage_insn;
4398 lra_assert (! usage_insns[original_regno].after_p);
4399 if (lra_dump_file != NULL)
4400 fprintf (lra_dump_file,
4401 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4402 if (! ira_reg_classes_intersect_p[cl][rclass])
4404 if (lra_dump_file != NULL)
4406 fprintf (lra_dump_file,
4407 " Rejecting inheritance for %d "
4408 "because of disjoint classes %s and %s\n",
4409 original_regno, reg_class_names[cl],
4410 reg_class_names[rclass]);
4411 fprintf (lra_dump_file,
4412 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4416 if ((ira_class_subset_p[cl][rclass] && cl != rclass)
4417 /* We don't use a subset of two classes because it can be
4418 NO_REGS. This transformation is still profitable in most
4419 cases even if the classes are not intersected as register
4420 move is probably cheaper than a memory load. */
4421 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
4423 if (lra_dump_file != NULL)
4424 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
4425 reg_class_names[cl], reg_class_names[rclass]);
4429 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
4431 /* Reject inheritance resulting in secondary memory moves.
4432 Otherwise, there is a danger in LRA cycling. Also such
4433 transformation will be unprofitable. */
4434 if (lra_dump_file != NULL)
4436 rtx insn = skip_usage_debug_insns (next_usage_insns);
4437 rtx set = single_set (insn);
4439 lra_assert (set != NULL_RTX);
4441 rtx dest = SET_DEST (set);
4443 lra_assert (REG_P (dest));
4444 fprintf (lra_dump_file,
4445 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4446 "as secondary mem is needed\n",
4447 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
4448 original_regno, reg_class_names[rclass]);
4449 fprintf (lra_dump_file,
4450 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4454 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
4455 rclass, "inheritance");
4458 emit_move_insn (original_reg, new_reg);
4460 emit_move_insn (new_reg, original_reg);
4461 new_insns = get_insns ();
4463 if (NEXT_INSN (new_insns) != NULL_RTX)
4465 if (lra_dump_file != NULL)
4467 fprintf (lra_dump_file,
4468 " Rejecting inheritance %d->%d "
4469 "as it results in 2 or more insns:\n",
4470 original_regno, REGNO (new_reg));
4471 dump_rtl_slim (lra_dump_file, new_insns, NULL_RTX, -1, 0);
4472 fprintf (lra_dump_file,
4473 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4477 substitute_pseudo (&insn, original_regno, new_reg);
4478 lra_update_insn_regno_info (insn);
4480 /* We now have a new usage insn for original regno. */
4481 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
4482 if (lra_dump_file != NULL)
4483 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
4484 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
4485 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno;
4486 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
4487 bitmap_set_bit (&check_only_regs, original_regno);
4488 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
4490 lra_process_new_insns (insn, NULL_RTX, new_insns,
4491 "Add original<-inheritance");
4493 lra_process_new_insns (insn, new_insns, NULL_RTX,
4494 "Add inheritance<-original");
4495 while (next_usage_insns != NULL_RTX)
4497 if (GET_CODE (next_usage_insns) != INSN_LIST)
4499 usage_insn = next_usage_insns;
4500 lra_assert (NONDEBUG_INSN_P (usage_insn));
4501 next_usage_insns = NULL;
4505 usage_insn = XEXP (next_usage_insns, 0);
4506 lra_assert (DEBUG_INSN_P (usage_insn));
4507 next_usage_insns = XEXP (next_usage_insns, 1);
4509 substitute_pseudo (&usage_insn, original_regno, new_reg);
4510 lra_update_insn_regno_info (usage_insn);
4511 if (lra_dump_file != NULL)
4513 fprintf (lra_dump_file,
4514 " Inheritance reuse change %d->%d (bb%d):\n",
4515 original_regno, REGNO (new_reg),
4516 BLOCK_FOR_INSN (usage_insn)->index);
4517 dump_insn_slim (lra_dump_file, usage_insn);
4520 if (lra_dump_file != NULL)
4521 fprintf (lra_dump_file,
4522 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4526 /* Return true if we need a caller save/restore for pseudo REGNO which
4527 was assigned to a hard register. */
4529 need_for_call_save_p (int regno)
4531 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
4532 return (usage_insns[regno].calls_num < calls_num
4533 && (overlaps_hard_reg_set_p
4535 PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
4536 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber[regno],
4537 PSEUDO_REGNO_MODE (regno))));
4540 /* Global registers occurring in the current EBB. */
4541 static bitmap_head ebb_global_regs;
4543 /* Return true if we need a split for hard register REGNO or pseudo
4544 REGNO which was assigned to a hard register.
4545 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4546 used for reloads since the EBB end. It is an approximation of the
4547 used hard registers in the split range. The exact value would
4548 require expensive calculations. If we were aggressive with
4549 splitting because of the approximation, the split pseudo will save
4550 the same hard register assignment and will be removed in the undo
4551 pass. We still need the approximation because too aggressive
4552 splitting would result in too inaccurate cost calculation in the
4553 assignment pass because of too many generated moves which will be
4554 probably removed in the undo pass. */
4556 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
4558 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
4560 lra_assert (hard_regno >= 0);
4561 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
4562 /* Don't split eliminable hard registers, otherwise we can
4563 split hard registers like hard frame pointer, which
4564 lives on BB start/end according to DF-infrastructure,
4565 when there is a pseudo assigned to the register and
4566 living in the same BB. */
4567 && (regno >= FIRST_PSEUDO_REGISTER
4568 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
4569 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
4570 /* Don't split call clobbered hard regs living through
4571 calls, otherwise we might have a check problem in the
4572 assign sub-pass as in the most cases (exception is a
4573 situation when lra_risky_transformations_p value is
4574 true) the assign pass assumes that all pseudos living
4575 through calls are assigned to call saved hard regs. */
4576 && (regno >= FIRST_PSEUDO_REGISTER
4577 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
4578 || usage_insns[regno].calls_num == calls_num)
4579 /* We need at least 2 reloads to make pseudo splitting
4580 profitable. We should provide hard regno splitting in
4581 any case to solve 1st insn scheduling problem when
4582 moving hard register definition up might result in
4583 impossibility to find hard register for reload pseudo of
4584 small register class. */
4585 && (usage_insns[regno].reloads_num
4586 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 2) < reloads_num)
4587 && (regno < FIRST_PSEUDO_REGISTER
4588 /* For short living pseudos, spilling + inheritance can
4589 be considered a substitution for splitting.
4590 Therefore we do not splitting for local pseudos. It
4591 decreases also aggressiveness of splitting. The
4592 minimal number of references is chosen taking into
4593 account that for 2 references splitting has no sense
4594 as we can just spill the pseudo. */
4595 || (regno >= FIRST_PSEUDO_REGISTER
4596 && lra_reg_info[regno].nrefs > 3
4597 && bitmap_bit_p (&ebb_global_regs, regno))))
4598 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
4601 /* Return class for the split pseudo created from original pseudo with
4602 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4603 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4604 results in no secondary memory movements. */
4605 static enum reg_class
4606 choose_split_class (enum reg_class allocno_class,
4607 int hard_regno ATTRIBUTE_UNUSED,
4608 enum machine_mode mode ATTRIBUTE_UNUSED)
4610 #ifndef SECONDARY_MEMORY_NEEDED
4611 return allocno_class;
4614 enum reg_class cl, best_cl = NO_REGS;
4615 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4616 = REGNO_REG_CLASS (hard_regno);
4618 if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode)
4619 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
4620 return allocno_class;
4622 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
4624 if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode)
4625 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode)
4626 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
4627 && (best_cl == NO_REGS
4628 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
4634 /* Do split transformations for insn INSN, which defines or uses
4635 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4636 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4637 "insns" field of usage_insns.
4639 The transformations look like:
4642 ... s <- p (new insn -- save)
4644 ... p <- s (new insn -- restore)
4645 <- ... p ... <- ... p ...
4647 <- ... p ... <- ... p ...
4648 ... s <- p (new insn -- save)
4650 ... p <- s (new insn -- restore)
4651 <- ... p ... <- ... p ...
4653 where p is an original pseudo got a hard register or a hard
4654 register and s is a new split pseudo. The save is put before INSN
4655 if BEFORE_P is true. Return true if we succeed in such
4658 split_reg (bool before_p, int original_regno, rtx insn, rtx next_usage_insns)
4660 enum reg_class rclass;
4662 int hard_regno, nregs;
4663 rtx new_reg, save, restore, usage_insn;
4667 if (original_regno < FIRST_PSEUDO_REGISTER)
4669 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
4670 hard_regno = original_regno;
4671 call_save_p = false;
4676 hard_regno = reg_renumber[original_regno];
4677 nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (original_regno)];
4678 rclass = lra_get_allocno_class (original_regno);
4679 original_reg = regno_reg_rtx[original_regno];
4680 call_save_p = need_for_call_save_p (original_regno);
4682 original_reg = regno_reg_rtx[original_regno];
4683 lra_assert (hard_regno >= 0);
4684 if (lra_dump_file != NULL)
4685 fprintf (lra_dump_file,
4686 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4689 enum machine_mode mode = GET_MODE (original_reg);
4691 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
4692 hard_regno_nregs[hard_regno][mode],
4694 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
4698 rclass = choose_split_class (rclass, hard_regno,
4699 GET_MODE (original_reg));
4700 if (rclass == NO_REGS)
4702 if (lra_dump_file != NULL)
4704 fprintf (lra_dump_file,
4705 " Rejecting split of %d(%s): "
4706 "no good reg class for %d(%s)\n",
4708 reg_class_names[lra_get_allocno_class (original_regno)],
4710 reg_class_names[REGNO_REG_CLASS (hard_regno)]);
4713 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4717 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
4719 reg_renumber[REGNO (new_reg)] = hard_regno;
4721 save = emit_spill_move (true, new_reg, original_reg);
4722 if (NEXT_INSN (save) != NULL_RTX)
4724 lra_assert (! call_save_p);
4725 if (lra_dump_file != NULL)
4729 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4730 original_regno, REGNO (new_reg), call_save_p ? "call" : "");
4731 dump_rtl_slim (lra_dump_file, save, NULL_RTX, -1, 0);
4732 fprintf (lra_dump_file,
4733 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4737 restore = emit_spill_move (false, new_reg, original_reg);
4738 if (NEXT_INSN (restore) != NULL_RTX)
4740 lra_assert (! call_save_p);
4741 if (lra_dump_file != NULL)
4743 fprintf (lra_dump_file,
4744 " Rejecting split %d->%d "
4745 "resulting in > 2 %s restore insns:\n",
4746 original_regno, REGNO (new_reg), call_save_p ? "call" : "");
4747 dump_rtl_slim (lra_dump_file, restore, NULL_RTX, -1, 0);
4748 fprintf (lra_dump_file,
4749 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4753 after_p = usage_insns[original_regno].after_p;
4754 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno;
4755 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
4756 bitmap_set_bit (&check_only_regs, original_regno);
4757 bitmap_set_bit (&lra_split_regs, REGNO (new_reg));
4760 if (GET_CODE (next_usage_insns) != INSN_LIST)
4762 usage_insn = next_usage_insns;
4765 usage_insn = XEXP (next_usage_insns, 0);
4766 lra_assert (DEBUG_INSN_P (usage_insn));
4767 next_usage_insns = XEXP (next_usage_insns, 1);
4768 substitute_pseudo (&usage_insn, original_regno, new_reg);
4769 lra_update_insn_regno_info (usage_insn);
4770 if (lra_dump_file != NULL)
4772 fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
4773 original_regno, REGNO (new_reg));
4774 dump_insn_slim (lra_dump_file, usage_insn);
4777 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
4778 lra_assert (usage_insn != insn || (after_p && before_p));
4779 lra_process_new_insns (usage_insn, after_p ? NULL_RTX : restore,
4780 after_p ? restore : NULL_RTX,
4782 ? "Add reg<-save" : "Add reg<-split");
4783 lra_process_new_insns (insn, before_p ? save : NULL_RTX,
4784 before_p ? NULL_RTX : save,
4786 ? "Add save<-reg" : "Add split<-reg");
4788 /* If we are trying to split multi-register. We should check
4789 conflicts on the next assignment sub-pass. IRA can allocate on
4790 sub-register levels, LRA do this on pseudos level right now and
4791 this discrepancy may create allocation conflicts after
4793 lra_risky_transformations_p = true;
4794 if (lra_dump_file != NULL)
4795 fprintf (lra_dump_file,
4796 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4800 /* Recognize that we need a split transformation for insn INSN, which
4801 defines or uses REGNO in its insn biggest MODE (we use it only if
4802 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4803 hard registers which might be used for reloads since the EBB end.
4804 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4805 uid before starting INSN processing. Return true if we succeed in
4806 such transformation. */
4808 split_if_necessary (int regno, enum machine_mode mode,
4809 HARD_REG_SET potential_reload_hard_regs,
4810 bool before_p, rtx insn, int max_uid)
4814 rtx next_usage_insns;
4816 if (regno < FIRST_PSEUDO_REGISTER)
4817 nregs = hard_regno_nregs[regno][mode];
4818 for (i = 0; i < nregs; i++)
4819 if (usage_insns[regno + i].check == curr_usage_insns_check
4820 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
4821 /* To avoid processing the register twice or more. */
4822 && ((GET_CODE (next_usage_insns) != INSN_LIST
4823 && INSN_UID (next_usage_insns) < max_uid)
4824 || (GET_CODE (next_usage_insns) == INSN_LIST
4825 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
4826 && need_for_split_p (potential_reload_hard_regs, regno + i)
4827 && split_reg (before_p, regno + i, insn, next_usage_insns))
4832 /* Check only registers living at the current program point in the
4834 static bitmap_head live_regs;
4836 /* Update live info in EBB given by its HEAD and TAIL insns after
4837 inheritance/split transformation. The function removes dead moves
4840 update_ebb_live_info (rtx head, rtx tail)
4847 basic_block last_bb, prev_bb, curr_bb;
4849 struct lra_insn_reg *reg;
4853 last_bb = BLOCK_FOR_INSN (tail);
4855 for (curr_insn = tail;
4856 curr_insn != PREV_INSN (head);
4857 curr_insn = prev_insn)
4859 prev_insn = PREV_INSN (curr_insn);
4860 /* We need to process empty blocks too. They contain
4861 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4862 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
4864 curr_bb = BLOCK_FOR_INSN (curr_insn);
4865 if (curr_bb != prev_bb)
4867 if (prev_bb != NULL)
4869 /* Update df_get_live_in (prev_bb): */
4870 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
4871 if (bitmap_bit_p (&live_regs, j))
4872 bitmap_set_bit (df_get_live_in (prev_bb), j);
4874 bitmap_clear_bit (df_get_live_in (prev_bb), j);
4876 if (curr_bb != last_bb)
4878 /* Update df_get_live_out (curr_bb): */
4879 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
4881 live_p = bitmap_bit_p (&live_regs, j);
4883 FOR_EACH_EDGE (e, ei, curr_bb->succs)
4884 if (bitmap_bit_p (df_get_live_in (e->dest), j))
4890 bitmap_set_bit (df_get_live_out (curr_bb), j);
4892 bitmap_clear_bit (df_get_live_out (curr_bb), j);
4896 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
4898 if (! NONDEBUG_INSN_P (curr_insn))
4900 curr_id = lra_get_insn_recog_data (curr_insn);
4902 if ((set = single_set (curr_insn)) != NULL_RTX && REG_P (SET_DEST (set))
4903 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
4904 && bitmap_bit_p (&check_only_regs, regno)
4905 && ! bitmap_bit_p (&live_regs, regno))
4907 /* See which defined values die here. */
4908 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
4909 if (reg->type == OP_OUT && ! reg->subreg_p)
4910 bitmap_clear_bit (&live_regs, reg->regno);
4911 /* Mark each used value as live. */
4912 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
4913 if (reg->type != OP_OUT
4914 && bitmap_bit_p (&check_only_regs, reg->regno))
4915 bitmap_set_bit (&live_regs, reg->regno);
4916 /* It is quite important to remove dead move insns because it
4917 means removing dead store. We don't need to process them for
4921 if (lra_dump_file != NULL)
4923 fprintf (lra_dump_file, " Removing dead insn:\n ");
4924 dump_insn_slim (lra_dump_file, curr_insn);
4926 lra_set_insn_deleted (curr_insn);
4931 /* The structure describes info to do an inheritance for the current
4932 insn. We need to collect such info first before doing the
4933 transformations because the transformations change the insn
4934 internal representation. */
4937 /* Original regno. */
4939 /* Subsequent insns which can inherit original reg value. */
4943 /* Array containing all info for doing inheritance from the current
4945 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
4947 /* Number elements in the previous array. */
4948 static int to_inherit_num;
4950 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4951 structure to_inherit. */
4953 add_to_inherit (int regno, rtx insns)
4957 for (i = 0; i < to_inherit_num; i++)
4958 if (to_inherit[i].regno == regno)
4960 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
4961 to_inherit[to_inherit_num].regno = regno;
4962 to_inherit[to_inherit_num++].insns = insns;
4965 /* Return the last non-debug insn in basic block BB, or the block begin
4968 get_last_insertion_point (basic_block bb)
4972 FOR_BB_INSNS_REVERSE (bb, insn)
4973 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
4978 /* Set up RES by registers living on edges FROM except the edge (FROM,
4979 TO) or by registers set up in a jump insn in BB FROM. */
4981 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
4984 struct lra_insn_reg *reg;
4988 lra_assert (to != NULL);
4990 FOR_EACH_EDGE (e, ei, from->succs)
4992 bitmap_ior_into (res, df_get_live_in (e->dest));
4993 last = get_last_insertion_point (from);
4994 if (! JUMP_P (last))
4996 curr_id = lra_get_insn_recog_data (last);
4997 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
4998 if (reg->type != OP_IN)
4999 bitmap_set_bit (res, reg->regno);
5002 /* Used as a temporary results of some bitmap calculations. */
5003 static bitmap_head temp_bitmap;
5005 /* Do inheritance/split transformations in EBB starting with HEAD and
5006 finishing on TAIL. We process EBB insns in the reverse order.
5007 Return true if we did any inheritance/split transformation in the
5010 We should avoid excessive splitting which results in worse code
5011 because of inaccurate cost calculations for spilling new split
5012 pseudos in such case. To achieve this we do splitting only if
5013 register pressure is high in given basic block and there are reload
5014 pseudos requiring hard registers. We could do more register
5015 pressure calculations at any given program point to avoid necessary
5016 splitting even more but it is to expensive and the current approach
5017 works well enough. */
5019 inherit_in_ebb (rtx head, rtx tail)
5021 int i, src_regno, dst_regno, nregs;
5022 bool change_p, succ_p, update_reloads_num_p;
5023 rtx prev_insn, next_usage_insns, set, last_insn;
5025 struct lra_insn_reg *reg;
5026 basic_block last_processed_bb, curr_bb = NULL;
5027 HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
5031 bool head_p, after_p;
5034 curr_usage_insns_check++;
5035 reloads_num = calls_num = 0;
5036 bitmap_clear (&check_only_regs);
5037 last_processed_bb = NULL;
5038 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
5039 CLEAR_HARD_REG_SET (live_hard_regs);
5040 /* We don't process new insns generated in the loop. */
5041 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
5043 prev_insn = PREV_INSN (curr_insn);
5044 if (BLOCK_FOR_INSN (curr_insn) != NULL)
5045 curr_bb = BLOCK_FOR_INSN (curr_insn);
5046 if (last_processed_bb != curr_bb)
5048 /* We are at the end of BB. Add qualified living
5049 pseudos for potential splitting. */
5050 to_process = df_get_live_out (curr_bb);
5051 if (last_processed_bb != NULL)
5053 /* We are somewhere in the middle of EBB. */
5054 get_live_on_other_edges (curr_bb, last_processed_bb,
5056 to_process = &temp_bitmap;
5058 last_processed_bb = curr_bb;
5059 last_insn = get_last_insertion_point (curr_bb);
5060 after_p = (! JUMP_P (last_insn)
5061 && (! CALL_P (last_insn)
5062 || (find_reg_note (last_insn,
5063 REG_NORETURN, NULL_RTX) == NULL_RTX
5064 && ! SIBLING_CALL_P (last_insn))));
5065 REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_out (curr_bb));
5066 IOR_HARD_REG_SET (live_hard_regs, eliminable_regset);
5067 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
5068 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
5069 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
5071 if ((int) j >= lra_constraint_new_regno_start)
5073 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
5075 if (j < FIRST_PSEUDO_REGISTER)
5076 SET_HARD_REG_BIT (live_hard_regs, j);
5078 add_to_hard_reg_set (&live_hard_regs,
5079 PSEUDO_REGNO_MODE (j),
5081 setup_next_usage_insn (j, last_insn, reloads_num, after_p);
5085 src_regno = dst_regno = -1;
5086 if (NONDEBUG_INSN_P (curr_insn)
5087 && (set = single_set (curr_insn)) != NULL_RTX
5088 && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set)))
5090 src_regno = REGNO (SET_SRC (set));
5091 dst_regno = REGNO (SET_DEST (set));
5093 update_reloads_num_p = true;
5094 if (src_regno < lra_constraint_new_regno_start
5095 && src_regno >= FIRST_PSEUDO_REGISTER
5096 && reg_renumber[src_regno] < 0
5097 && dst_regno >= lra_constraint_new_regno_start
5098 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
5100 /* 'reload_pseudo <- original_pseudo'. */
5102 update_reloads_num_p = false;
5104 if (usage_insns[src_regno].check == curr_usage_insns_check
5105 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
5106 succ_p = inherit_reload_reg (false, src_regno, cl,
5107 curr_insn, next_usage_insns);
5111 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
5112 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5113 IOR_HARD_REG_SET (potential_reload_hard_regs,
5114 reg_class_contents[cl]);
5116 else if (src_regno >= lra_constraint_new_regno_start
5117 && dst_regno < lra_constraint_new_regno_start
5118 && dst_regno >= FIRST_PSEUDO_REGISTER
5119 && reg_renumber[dst_regno] < 0
5120 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
5121 && usage_insns[dst_regno].check == curr_usage_insns_check
5122 && (next_usage_insns
5123 = usage_insns[dst_regno].insns) != NULL_RTX)
5126 update_reloads_num_p = false;
5127 /* 'original_pseudo <- reload_pseudo'. */
5128 if (! JUMP_P (curr_insn)
5129 && inherit_reload_reg (true, dst_regno, cl,
5130 curr_insn, next_usage_insns))
5133 usage_insns[dst_regno].check = 0;
5134 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5135 IOR_HARD_REG_SET (potential_reload_hard_regs,
5136 reg_class_contents[cl]);
5138 else if (INSN_P (curr_insn))
5141 int max_uid = get_max_uid ();
5143 curr_id = lra_get_insn_recog_data (curr_insn);
5144 curr_static_id = curr_id->insn_static_data;
5146 /* Process insn definitions. */
5147 for (iter = 0; iter < 2; iter++)
5148 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
5151 if (reg->type != OP_IN
5152 && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
5154 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
5155 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
5156 && usage_insns[dst_regno].check == curr_usage_insns_check
5157 && (next_usage_insns
5158 = usage_insns[dst_regno].insns) != NULL_RTX)
5160 struct lra_insn_reg *r;
5162 for (r = curr_id->regs; r != NULL; r = r->next)
5163 if (r->type != OP_OUT && r->regno == dst_regno)
5165 /* Don't do inheritance if the pseudo is also
5166 used in the insn. */
5168 /* We can not do inheritance right now
5169 because the current insn reg info (chain
5170 regs) can change after that. */
5171 add_to_inherit (dst_regno, next_usage_insns);
5173 /* We can not process one reg twice here because of
5174 usage_insns invalidation. */
5175 if ((dst_regno < FIRST_PSEUDO_REGISTER
5176 || reg_renumber[dst_regno] >= 0)
5177 && ! reg->subreg_p && reg->type != OP_IN)
5181 if (split_if_necessary (dst_regno, reg->biggest_mode,
5182 potential_reload_hard_regs,
5183 false, curr_insn, max_uid))
5185 CLEAR_HARD_REG_SET (s);
5186 if (dst_regno < FIRST_PSEUDO_REGISTER)
5187 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
5189 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
5190 reg_renumber[dst_regno]);
5191 AND_COMPL_HARD_REG_SET (live_hard_regs, s);
5193 /* We should invalidate potential inheritance or
5194 splitting for the current insn usages to the next
5195 usage insns (see code below) as the output pseudo
5197 if ((dst_regno >= FIRST_PSEUDO_REGISTER
5198 && reg_renumber[dst_regno] < 0)
5199 || (reg->type == OP_OUT && ! reg->subreg_p
5200 && (dst_regno < FIRST_PSEUDO_REGISTER
5201 || reg_renumber[dst_regno] >= 0)))
5203 /* Invalidate and mark definitions. */
5204 if (dst_regno >= FIRST_PSEUDO_REGISTER)
5205 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
5208 nregs = hard_regno_nregs[dst_regno][reg->biggest_mode];
5209 for (i = 0; i < nregs; i++)
5210 usage_insns[dst_regno + i].check
5211 = -(int) INSN_UID (curr_insn);
5215 if (! JUMP_P (curr_insn))
5216 for (i = 0; i < to_inherit_num; i++)
5217 if (inherit_reload_reg (true, to_inherit[i].regno,
5218 ALL_REGS, curr_insn,
5219 to_inherit[i].insns))
5221 if (CALL_P (curr_insn))
5223 rtx cheap, pat, dest, restore;
5224 int regno, hard_regno;
5227 if ((cheap = find_reg_note (curr_insn,
5228 REG_RETURNED, NULL_RTX)) != NULL_RTX
5229 && ((cheap = XEXP (cheap, 0)), true)
5230 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
5231 && (hard_regno = reg_renumber[regno]) >= 0
5232 /* If there are pending saves/restores, the
5233 optimization is not worth. */
5234 && usage_insns[regno].calls_num == calls_num - 1
5235 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
5237 /* Restore the pseudo from the call result as
5238 REG_RETURNED note says that the pseudo value is
5239 in the call result and the pseudo is an argument
5241 pat = PATTERN (curr_insn);
5242 if (GET_CODE (pat) == PARALLEL)
5243 pat = XVECEXP (pat, 0, 0);
5244 dest = SET_DEST (pat);
5246 emit_move_insn (cheap, copy_rtx (dest));
5247 restore = get_insns ();
5249 lra_process_new_insns (curr_insn, NULL, restore,
5250 "Inserting call parameter restore");
5251 /* We don't need to save/restore of the pseudo from
5253 usage_insns[regno].calls_num = calls_num;
5254 bitmap_set_bit (&check_only_regs, regno);
5258 /* Process insn usages. */
5259 for (iter = 0; iter < 2; iter++)
5260 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
5263 if ((reg->type != OP_OUT
5264 || (reg->type == OP_OUT && reg->subreg_p))
5265 && (src_regno = reg->regno) < lra_constraint_new_regno_start)
5267 if (src_regno >= FIRST_PSEUDO_REGISTER
5268 && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
5270 if (usage_insns[src_regno].check == curr_usage_insns_check
5271 && (next_usage_insns
5272 = usage_insns[src_regno].insns) != NULL_RTX
5273 && NONDEBUG_INSN_P (curr_insn))
5274 add_to_inherit (src_regno, next_usage_insns);
5275 else if (usage_insns[src_regno].check
5276 != -(int) INSN_UID (curr_insn))
5277 /* Add usages but only if the reg is not set up
5278 in the same insn. */
5279 add_next_usage_insn (src_regno, curr_insn, reloads_num);
5281 else if (src_regno < FIRST_PSEUDO_REGISTER
5282 || reg_renumber[src_regno] >= 0)
5285 rtx use_insn = curr_insn;
5287 before_p = (JUMP_P (curr_insn)
5288 || (CALL_P (curr_insn) && reg->type == OP_IN));
5289 if (NONDEBUG_INSN_P (curr_insn)
5290 && split_if_necessary (src_regno, reg->biggest_mode,
5291 potential_reload_hard_regs,
5292 before_p, curr_insn, max_uid))
5295 lra_risky_transformations_p = true;
5298 usage_insns[src_regno].check = 0;
5300 use_insn = PREV_INSN (curr_insn);
5302 if (NONDEBUG_INSN_P (curr_insn))
5304 if (src_regno < FIRST_PSEUDO_REGISTER)
5305 add_to_hard_reg_set (&live_hard_regs,
5306 reg->biggest_mode, src_regno);
5308 add_to_hard_reg_set (&live_hard_regs,
5309 PSEUDO_REGNO_MODE (src_regno),
5310 reg_renumber[src_regno]);
5312 add_next_usage_insn (src_regno, use_insn, reloads_num);
5315 /* Process call args. */
5316 if (curr_id->arg_hard_regs != NULL)
5317 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5318 if (src_regno < FIRST_PSEUDO_REGISTER)
5320 SET_HARD_REG_BIT (live_hard_regs, src_regno);
5321 add_next_usage_insn (src_regno, curr_insn, reloads_num);
5323 for (i = 0; i < to_inherit_num; i++)
5325 src_regno = to_inherit[i].regno;
5326 if (inherit_reload_reg (false, src_regno, ALL_REGS,
5327 curr_insn, to_inherit[i].insns))
5330 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
5333 if (update_reloads_num_p
5334 && NONDEBUG_INSN_P (curr_insn)
5335 && (set = single_set (curr_insn)) != NULL_RTX)
5338 if ((REG_P (SET_DEST (set))
5339 && (regno = REGNO (SET_DEST (set))) >= lra_constraint_new_regno_start
5340 && reg_renumber[regno] < 0
5341 && (cl = lra_get_allocno_class (regno)) != NO_REGS)
5342 || (REG_P (SET_SRC (set))
5343 && (regno = REGNO (SET_SRC (set))) >= lra_constraint_new_regno_start
5344 && reg_renumber[regno] < 0
5345 && (cl = lra_get_allocno_class (regno)) != NO_REGS))
5348 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
5349 IOR_HARD_REG_SET (potential_reload_hard_regs,
5350 reg_class_contents[cl]);
5353 /* We reached the start of the current basic block. */
5354 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
5355 || BLOCK_FOR_INSN (prev_insn) != curr_bb)
5357 /* We reached the beginning of the current block -- do
5358 rest of spliting in the current BB. */
5359 to_process = df_get_live_in (curr_bb);
5360 if (BLOCK_FOR_INSN (head) != curr_bb)
5362 /* We are somewhere in the middle of EBB. */
5363 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
5364 curr_bb, &temp_bitmap);
5365 to_process = &temp_bitmap;
5368 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
5370 if ((int) j >= lra_constraint_new_regno_start)
5372 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
5373 && usage_insns[j].check == curr_usage_insns_check
5374 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
5376 if (need_for_split_p (potential_reload_hard_regs, j))
5378 if (lra_dump_file != NULL && head_p)
5380 fprintf (lra_dump_file,
5381 " ----------------------------------\n");
5384 if (split_reg (false, j, bb_note (curr_bb),
5388 usage_insns[j].check = 0;
5396 /* This value affects EBB forming. If probability of edge from EBB to
5397 a BB is not greater than the following value, we don't add the BB
5399 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5401 /* Current number of inheritance/split iteration. */
5402 int lra_inheritance_iter;
5404 /* Entry function for inheritance/split pass. */
5406 lra_inheritance (void)
5409 basic_block bb, start_bb;
5412 lra_inheritance_iter++;
5413 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
5415 timevar_push (TV_LRA_INHERITANCE);
5416 if (lra_dump_file != NULL)
5417 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
5418 lra_inheritance_iter);
5419 curr_usage_insns_check = 0;
5420 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
5421 for (i = 0; i < lra_constraint_new_regno_start; i++)
5422 usage_insns[i].check = 0;
5423 bitmap_initialize (&check_only_regs, ®_obstack);
5424 bitmap_initialize (&live_regs, ®_obstack);
5425 bitmap_initialize (&temp_bitmap, ®_obstack);
5426 bitmap_initialize (&ebb_global_regs, ®_obstack);
5427 FOR_EACH_BB_FN (bb, cfun)
5430 if (lra_dump_file != NULL)
5431 fprintf (lra_dump_file, "EBB");
5432 /* Form a EBB starting with BB. */
5433 bitmap_clear (&ebb_global_regs);
5434 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
5437 if (lra_dump_file != NULL)
5438 fprintf (lra_dump_file, " %d", bb->index);
5439 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
5440 || LABEL_P (BB_HEAD (bb->next_bb)))
5442 e = find_fallthru_edge (bb->succs);
5445 if (e->probability <= EBB_PROBABILITY_CUTOFF)
5449 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
5450 if (lra_dump_file != NULL)
5451 fprintf (lra_dump_file, "\n");
5452 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
5453 /* Remember that the EBB head and tail can change in
5455 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
5457 bitmap_clear (&ebb_global_regs);
5458 bitmap_clear (&temp_bitmap);
5459 bitmap_clear (&live_regs);
5460 bitmap_clear (&check_only_regs);
5463 timevar_pop (TV_LRA_INHERITANCE);
5468 /* This page contains code to undo failed inheritance/split
5471 /* Current number of iteration undoing inheritance/split. */
5472 int lra_undo_inheritance_iter;
5474 /* Fix BB live info LIVE after removing pseudos created on pass doing
5475 inheritance/split which are REMOVED_PSEUDOS. */
5477 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
5482 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
5483 if (bitmap_clear_bit (live, regno))
5484 bitmap_set_bit (live, lra_reg_info[regno].restore_regno);
5487 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5492 if (GET_CODE (reg) == SUBREG)
5493 reg = SUBREG_REG (reg);
5499 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5500 return true if we did any change. The undo transformations for
5501 inheritance looks like
5505 p <- i, i <- p, and i <- i3
5506 where p is original pseudo from which inheritance pseudo i was
5507 created, i and i3 are removed inheritance pseudos, i2 is another
5508 not removed inheritance pseudo. All split pseudos or other
5509 occurrences of removed inheritance pseudos are changed on the
5510 corresponding original pseudos.
5512 The function also schedules insns changed and created during
5513 inheritance/split pass for processing by the subsequent constraint
5516 remove_inheritance_pseudos (bitmap remove_pseudos)
5519 int regno, sregno, prev_sregno, dregno, restore_regno;
5520 rtx set, prev_set, prev_insn;
5521 bool change_p, done_p;
5523 change_p = ! bitmap_empty_p (remove_pseudos);
5524 /* We can not finish the function right away if CHANGE_P is true
5525 because we need to marks insns affected by previous
5526 inheritance/split pass for processing by the subsequent
5528 FOR_EACH_BB_FN (bb, cfun)
5530 fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
5531 fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
5532 FOR_BB_INSNS_REVERSE (bb, curr_insn)
5534 if (! INSN_P (curr_insn))
5537 sregno = dregno = -1;
5538 if (change_p && NONDEBUG_INSN_P (curr_insn)
5539 && (set = single_set (curr_insn)) != NULL_RTX)
5541 dregno = get_regno (SET_DEST (set));
5542 sregno = get_regno (SET_SRC (set));
5545 if (sregno >= 0 && dregno >= 0)
5547 if ((bitmap_bit_p (remove_pseudos, sregno)
5548 && (lra_reg_info[sregno].restore_regno == dregno
5549 || (bitmap_bit_p (remove_pseudos, dregno)
5550 && (lra_reg_info[sregno].restore_regno
5551 == lra_reg_info[dregno].restore_regno))))
5552 || (bitmap_bit_p (remove_pseudos, dregno)
5553 && lra_reg_info[dregno].restore_regno == sregno))
5554 /* One of the following cases:
5555 original <- removed inheritance pseudo
5556 removed inherit pseudo <- another removed inherit pseudo
5557 removed inherit pseudo <- original pseudo
5559 removed_split_pseudo <- original_reg
5560 original_reg <- removed_split_pseudo */
5562 if (lra_dump_file != NULL)
5564 fprintf (lra_dump_file, " Removing %s:\n",
5565 bitmap_bit_p (&lra_split_regs, sregno)
5566 || bitmap_bit_p (&lra_split_regs, dregno)
5567 ? "split" : "inheritance");
5568 dump_insn_slim (lra_dump_file, curr_insn);
5570 lra_set_insn_deleted (curr_insn);
5573 else if (bitmap_bit_p (remove_pseudos, sregno)
5574 && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
5576 /* Search the following pattern:
5577 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5578 original_pseudo <- inherit_or_split_pseudo1
5579 where the 2nd insn is the current insn and
5580 inherit_or_split_pseudo2 is not removed. If it is found,
5581 change the current insn onto:
5582 original_pseudo <- inherit_or_split_pseudo2. */
5583 for (prev_insn = PREV_INSN (curr_insn);
5584 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
5585 prev_insn = PREV_INSN (prev_insn))
5587 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
5588 && (prev_set = single_set (prev_insn)) != NULL_RTX
5589 /* There should be no subregs in insn we are
5590 searching because only the original reg might
5591 be in subreg when we changed the mode of
5592 load/store for splitting. */
5593 && REG_P (SET_DEST (prev_set))
5594 && REG_P (SET_SRC (prev_set))
5595 && (int) REGNO (SET_DEST (prev_set)) == sregno
5596 && ((prev_sregno = REGNO (SET_SRC (prev_set)))
5597 >= FIRST_PSEUDO_REGISTER)
5598 /* As we consider chain of inheritance or
5599 splitting described in above comment we should
5600 check that sregno and prev_sregno were
5601 inheritance/split pseudos created from the
5602 same original regno. */
5603 && (lra_reg_info[sregno].restore_regno
5604 == lra_reg_info[prev_sregno].restore_regno)
5605 && ! bitmap_bit_p (remove_pseudos, prev_sregno))
5607 lra_assert (GET_MODE (SET_SRC (prev_set))
5608 == GET_MODE (regno_reg_rtx[sregno]));
5609 if (GET_CODE (SET_SRC (set)) == SUBREG)
5610 SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set);
5612 SET_SRC (set) = SET_SRC (prev_set);
5613 lra_push_insn_and_update_insn_regno_info (curr_insn);
5614 lra_set_used_insn_alternative_by_uid
5615 (INSN_UID (curr_insn), -1);
5617 if (lra_dump_file != NULL)
5619 fprintf (lra_dump_file, " Change reload insn:\n");
5620 dump_insn_slim (lra_dump_file, curr_insn);
5627 struct lra_insn_reg *reg;
5628 bool restored_regs_p = false;
5629 bool kept_regs_p = false;
5631 curr_id = lra_get_insn_recog_data (curr_insn);
5632 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5635 restore_regno = lra_reg_info[regno].restore_regno;
5636 if (restore_regno >= 0)
5638 if (change_p && bitmap_bit_p (remove_pseudos, regno))
5640 substitute_pseudo (&curr_insn, regno,
5641 regno_reg_rtx[restore_regno]);
5642 restored_regs_p = true;
5648 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
5650 /* The instruction has changed since the previous
5651 constraints pass. */
5652 lra_push_insn_and_update_insn_regno_info (curr_insn);
5653 lra_set_used_insn_alternative_by_uid
5654 (INSN_UID (curr_insn), -1);
5656 else if (restored_regs_p)
5657 /* The instruction has been restored to the form that
5658 it had during the previous constraints pass. */
5659 lra_update_insn_regno_info (curr_insn);
5660 if (restored_regs_p && lra_dump_file != NULL)
5662 fprintf (lra_dump_file, " Insn after restoring regs:\n");
5663 dump_insn_slim (lra_dump_file, curr_insn);
5671 /* If optional reload pseudos failed to get a hard register or was not
5672 inherited, it is better to remove optional reloads. We do this
5673 transformation after undoing inheritance to figure out necessity to
5674 remove optional reloads easier. Return true if we do any
5677 undo_optional_reloads (void)
5679 bool change_p, keep_p;
5680 unsigned int regno, uid;
5681 bitmap_iterator bi, bi2;
5682 rtx insn, set, src, dest;
5683 bitmap_head removed_optional_reload_pseudos, insn_bitmap;
5685 bitmap_initialize (&removed_optional_reload_pseudos, ®_obstack);
5686 bitmap_copy (&removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
5687 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
5690 /* Keep optional reloads from previous subpasses. */
5691 if (lra_reg_info[regno].restore_regno < 0
5692 /* If the original pseudo changed its allocation, just
5693 removing the optional pseudo is dangerous as the original
5694 pseudo will have longer live range. */
5695 || reg_renumber[lra_reg_info[regno].restore_regno] >= 0)
5697 else if (reg_renumber[regno] >= 0)
5698 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
5700 insn = lra_insn_recog_data[uid]->insn;
5701 if ((set = single_set (insn)) == NULL_RTX)
5703 src = SET_SRC (set);
5704 dest = SET_DEST (set);
5705 if (! REG_P (src) || ! REG_P (dest))
5707 if (REGNO (dest) == regno
5708 /* Ignore insn for optional reloads itself. */
5709 && lra_reg_info[regno].restore_regno != (int) REGNO (src)
5710 /* Check only inheritance on last inheritance pass. */
5711 && (int) REGNO (src) >= new_regno_start
5712 /* Check that the optional reload was inherited. */
5713 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
5721 bitmap_clear_bit (&removed_optional_reload_pseudos, regno);
5722 if (lra_dump_file != NULL)
5723 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
5726 change_p = ! bitmap_empty_p (&removed_optional_reload_pseudos);
5727 bitmap_initialize (&insn_bitmap, ®_obstack);
5728 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos, 0, regno, bi)
5730 if (lra_dump_file != NULL)
5731 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
5732 bitmap_copy (&insn_bitmap, &lra_reg_info[regno].insn_bitmap);
5733 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap, 0, uid, bi2)
5735 insn = lra_insn_recog_data[uid]->insn;
5736 if ((set = single_set (insn)) != NULL_RTX)
5738 src = SET_SRC (set);
5739 dest = SET_DEST (set);
5740 if (REG_P (src) && REG_P (dest)
5741 && ((REGNO (src) == regno
5742 && (lra_reg_info[regno].restore_regno
5743 == (int) REGNO (dest)))
5744 || (REGNO (dest) == regno
5745 && (lra_reg_info[regno].restore_regno
5746 == (int) REGNO (src)))))
5748 if (lra_dump_file != NULL)
5750 fprintf (lra_dump_file, " Deleting move %u\n",
5752 dump_insn_slim (lra_dump_file, insn);
5754 lra_set_insn_deleted (insn);
5757 /* We should not worry about generation memory-memory
5758 moves here as if the corresponding inheritance did
5759 not work (inheritance pseudo did not get a hard reg),
5760 we remove the inheritance pseudo and the optional
5763 substitute_pseudo (&insn, regno,
5764 regno_reg_rtx[lra_reg_info[regno].restore_regno]);
5765 lra_update_insn_regno_info (insn);
5766 if (lra_dump_file != NULL)
5768 fprintf (lra_dump_file,
5769 " Restoring original insn:\n");
5770 dump_insn_slim (lra_dump_file, insn);
5774 /* Clear restore_regnos. */
5775 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
5776 lra_reg_info[regno].restore_regno = -1;
5777 bitmap_clear (&insn_bitmap);
5778 bitmap_clear (&removed_optional_reload_pseudos);
5782 /* Entry function for undoing inheritance/split transformation. Return true
5783 if we did any RTL change in this pass. */
5785 lra_undo_inheritance (void)
5788 int restore_regno, hard_regno;
5789 int n_all_inherit, n_inherit, n_all_split, n_split;
5790 bitmap_head remove_pseudos;
5794 lra_undo_inheritance_iter++;
5795 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
5797 if (lra_dump_file != NULL)
5798 fprintf (lra_dump_file,
5799 "\n********** Undoing inheritance #%d: **********\n\n",
5800 lra_undo_inheritance_iter);
5801 bitmap_initialize (&remove_pseudos, ®_obstack);
5802 n_inherit = n_all_inherit = 0;
5803 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
5804 if (lra_reg_info[regno].restore_regno >= 0)
5807 if (reg_renumber[regno] < 0
5808 /* If the original pseudo changed its allocation, just
5809 removing inheritance is dangerous as for changing
5810 allocation we used shorter live-ranges. */
5811 && reg_renumber[lra_reg_info[regno].restore_regno] < 0)
5812 bitmap_set_bit (&remove_pseudos, regno);
5816 if (lra_dump_file != NULL && n_all_inherit != 0)
5817 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
5818 n_inherit, n_all_inherit,
5819 (double) n_inherit / n_all_inherit * 100);
5820 n_split = n_all_split = 0;
5821 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
5822 if ((restore_regno = lra_reg_info[regno].restore_regno) >= 0)
5825 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
5826 ? reg_renumber[restore_regno] : restore_regno);
5827 if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
5828 bitmap_set_bit (&remove_pseudos, regno);
5832 if (lra_dump_file != NULL)
5833 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
5834 regno, restore_regno);
5837 if (lra_dump_file != NULL && n_all_split != 0)
5838 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
5839 n_split, n_all_split,
5840 (double) n_split / n_all_split * 100);
5841 change_p = remove_inheritance_pseudos (&remove_pseudos);
5842 bitmap_clear (&remove_pseudos);
5843 /* Clear restore_regnos. */
5844 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
5845 lra_reg_info[regno].restore_regno = -1;
5846 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
5847 lra_reg_info[regno].restore_regno = -1;
5848 change_p = undo_optional_reloads () || change_p;