1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
4 This definition file is free software; you can redistribute it
5 and/or modify it under the terms of the GNU General Public
6 License as published by the Free Software Foundation; either
7 version 2, or (at your option) any later version.
9 This definition file is distributed in the hope that it will be
10 useful, but WITHOUT ANY WARRANTY; without even the implied
11 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 See the GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 #define SI_TYPE_SIZE 32
22 #define __BITS4 (SI_TYPE_SIZE / 4)
23 #define __ll_B (1L << (SI_TYPE_SIZE / 2))
24 #define __ll_lowpart(t) ((USItype) (t) % __ll_B)
25 #define __ll_highpart(t) ((USItype) (t) / __ll_B)
27 /* Define auxiliary asm macros.
29 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
30 multiplies two USItype integers MULTIPLER and MULTIPLICAND,
31 and generates a two-part USItype product in HIGH_PROD and
34 2) __umulsidi3(a,b) multiplies two USItype integers A and B,
35 and returns a UDItype product. This is just a variant of umul_ppmm.
37 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
38 denominator) divides a two-word unsigned integer, composed by the
39 integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
40 places the quotient in QUOTIENT and the remainder in REMAINDER.
41 HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
42 If, in addition, the most significant bit of DENOMINATOR must be 1,
43 then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
45 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
46 denominator). Like udiv_qrnnd but the numbers are signed. The
47 quotient is rounded towards 0.
49 5) count_leading_zeros(count, x) counts the number of zero-bits from
50 the msb to the first non-zero bit. This is the number of steps X
51 needs to be shifted left to set the msb. Undefined for X == 0.
53 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
54 high_addend_2, low_addend_2) adds two two-word unsigned integers,
55 composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
56 LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and
57 LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is
60 7) sub_ddmmss(high_difference, low_difference, high_minuend,
61 low_minuend, high_subtrahend, low_subtrahend) subtracts two
62 two-word unsigned integers, composed by HIGH_MINUEND_1 and
63 LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
64 respectively. The result is placed in HIGH_DIFFERENCE and
65 LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
68 If any of these macros are left undefined for a particular CPU,
71 /* The CPUs come in alphabetical order below.
73 Please add support for more CPUs here, or improve the current support
75 (E.g. WE32100, IBM360.) */
77 #if defined (__GNUC__) && !defined (NO_ASM)
79 /* We sometimes need to clobber "cc" with gcc2, but that would not be
80 understood by gcc1. Use cpp to avoid major code duplication. */
83 #define __AND_CLOBBER_CC
84 #else /* __GNUC__ >= 2 */
85 #define __CLOBBER_CC : "cc"
86 #define __AND_CLOBBER_CC , "cc"
87 #endif /* __GNUC__ < 2 */
89 #if defined (__a29k__) || defined (_AM29K)
90 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
91 __asm__ ("add %1,%4,%5
93 : "=r" ((USItype)(sh)), \
94 "=&r" ((USItype)(sl)) \
95 : "%r" ((USItype)(ah)), \
96 "rI" ((USItype)(bh)), \
97 "%r" ((USItype)(al)), \
99 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
100 __asm__ ("sub %1,%4,%5
102 : "=r" ((USItype)(sh)), \
103 "=&r" ((USItype)(sl)) \
104 : "r" ((USItype)(ah)), \
105 "rI" ((USItype)(bh)), \
106 "r" ((USItype)(al)), \
107 "rI" ((USItype)(bl)))
108 #define umul_ppmm(xh, xl, m0, m1) \
110 USItype __m0 = (m0), __m1 = (m1); \
111 __asm__ ("multiplu %0,%1,%2" \
112 : "=r" ((USItype)(xl)) \
115 __asm__ ("multmu %0,%1,%2" \
116 : "=r" ((USItype)(xh)) \
120 #define udiv_qrnnd(q, r, n1, n0, d) \
121 __asm__ ("dividu %0,%3,%4" \
122 : "=r" ((USItype)(q)), \
123 "=q" ((USItype)(r)) \
124 : "1" ((USItype)(n1)), \
125 "r" ((USItype)(n0)), \
127 #define count_leading_zeros(count, x) \
128 __asm__ ("clz %0,%1" \
129 : "=r" ((USItype)(count)) \
130 : "r" ((USItype)(x)))
131 #endif /* __a29k__ */
133 #if defined (__arm__)
134 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
135 __asm__ ("adds %1, %4, %5
137 : "=r" ((USItype)(sh)), \
138 "=&r" ((USItype)(sl)) \
139 : "%r" ((USItype)(ah)), \
140 "rI" ((USItype)(bh)), \
141 "%r" ((USItype)(al)), \
142 "rI" ((USItype)(bl)))
143 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
144 __asm__ ("subs %1, %4, %5
146 : "=r" ((USItype)(sh)), \
147 "=&r" ((USItype)(sl)) \
148 : "r" ((USItype)(ah)), \
149 "rI" ((USItype)(bh)), \
150 "r" ((USItype)(al)), \
151 "rI" ((USItype)(bl)))
152 #define umul_ppmm(xh, xl, a, b) \
153 __asm__ ("%@ Inlined umul_ppmm
154 mov %|r0, %2, lsr #16
155 mov %|r2, %3, lsr #16
156 bic %|r1, %2, %|r0, lsl #16
157 bic %|r2, %3, %|r2, lsl #16
162 adds %|r1, %|r2, %|r1
164 adds %1, %1, %|r1, lsl #16
165 adc %0, %0, %|r1, lsr #16" \
166 : "=&r" ((USItype)(xh)), \
167 "=r" ((USItype)(xl)) \
168 : "r" ((USItype)(a)), \
172 #define UDIV_TIME 100
175 #if defined (__clipper__)
176 #define umul_ppmm(w1, w0, u, v) \
177 ({union {UDItype __ll; \
178 struct {USItype __l, __h;} __i; \
180 __asm__ ("mulwux %2,%0" \
182 : "%0" ((USItype)(u)), \
183 "r" ((USItype)(v))); \
184 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
185 #define smul_ppmm(w1, w0, u, v) \
186 ({union {DItype __ll; \
187 struct {SItype __l, __h;} __i; \
189 __asm__ ("mulwx %2,%0" \
191 : "%0" ((SItype)(u)), \
192 "r" ((SItype)(v))); \
193 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
194 #define __umulsidi3(u, v) \
196 __asm__ ("mulwux %2,%0" \
198 : "%0" ((USItype)(u)), \
199 "r" ((USItype)(v))); \
201 #endif /* __clipper__ */
203 #if defined (__gmicro__)
204 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
205 __asm__ ("add.w %5,%1
207 : "=g" ((USItype)(sh)), \
208 "=&g" ((USItype)(sl)) \
209 : "%0" ((USItype)(ah)), \
210 "g" ((USItype)(bh)), \
211 "%1" ((USItype)(al)), \
213 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
214 __asm__ ("sub.w %5,%1
216 : "=g" ((USItype)(sh)), \
217 "=&g" ((USItype)(sl)) \
218 : "0" ((USItype)(ah)), \
219 "g" ((USItype)(bh)), \
220 "1" ((USItype)(al)), \
222 #define umul_ppmm(ph, pl, m0, m1) \
223 __asm__ ("mulx %3,%0,%1" \
224 : "=g" ((USItype)(ph)), \
225 "=r" ((USItype)(pl)) \
226 : "%0" ((USItype)(m0)), \
228 #define udiv_qrnnd(q, r, nh, nl, d) \
229 __asm__ ("divx %4,%0,%1" \
230 : "=g" ((USItype)(q)), \
231 "=r" ((USItype)(r)) \
232 : "1" ((USItype)(nh)), \
233 "0" ((USItype)(nl)), \
235 #define count_leading_zeros(count, x) \
236 __asm__ ("bsch/1 %1,%0" \
238 : "g" ((USItype)(x)), \
243 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
244 __asm__ ("add %4,%5,%1
246 : "=r" ((USItype)(sh)), \
247 "=&r" ((USItype)(sl)) \
248 : "%rM" ((USItype)(ah)), \
249 "rM" ((USItype)(bh)), \
250 "%rM" ((USItype)(al)), \
251 "rM" ((USItype)(bl)))
252 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
253 __asm__ ("sub %4,%5,%1
255 : "=r" ((USItype)(sh)), \
256 "=&r" ((USItype)(sl)) \
257 : "rM" ((USItype)(ah)), \
258 "rM" ((USItype)(bh)), \
259 "rM" ((USItype)(al)), \
260 "rM" ((USItype)(bl)))
261 #if defined (_PA_RISC1_1)
262 #define umul_ppmm(w1, w0, u, v) \
267 struct {USItype __w1, __w0;} __w1w0; \
269 __asm__ ("xmpyu %1,%2,%0" \
271 : "x" ((USItype)(u)), \
272 "x" ((USItype)(v))); \
273 (w1) = __t.__w1w0.__w1; \
274 (w0) = __t.__w1w0.__w0; \
281 #define count_leading_zeros(count, x) \
286 extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
287 extru,tr %1,15,16,%1 ; No. Shift down, skip add.
288 ldo 16(%0),%0 ; Yes. Perform add.
289 extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
290 extru,tr %1,23,8,%1 ; No. Shift down, skip add.
291 ldo 8(%0),%0 ; Yes. Perform add.
292 extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
293 extru,tr %1,27,4,%1 ; No. Shift down, skip add.
294 ldo 4(%0),%0 ; Yes. Perform add.
295 extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
296 extru,tr %1,29,2,%1 ; No. Shift down, skip add.
297 ldo 2(%0),%0 ; Yes. Perform add.
298 extru %1,30,1,%1 ; Extract bit 1.
299 sub %0,%1,%0 ; Subtract it.
300 " : "=r" (count), "=r" (__tmp) : "1" (x)); \
304 #if defined (__i386__) || defined (__i486__)
305 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
308 : "=r" ((USItype)(sh)), \
309 "=&r" ((USItype)(sl)) \
310 : "%0" ((USItype)(ah)), \
311 "g" ((USItype)(bh)), \
312 "%1" ((USItype)(al)), \
314 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
317 : "=r" ((USItype)(sh)), \
318 "=&r" ((USItype)(sl)) \
319 : "0" ((USItype)(ah)), \
320 "g" ((USItype)(bh)), \
321 "1" ((USItype)(al)), \
323 #define umul_ppmm(w1, w0, u, v) \
325 : "=a" ((USItype)(w0)), \
326 "=d" ((USItype)(w1)) \
327 : "%0" ((USItype)(u)), \
329 #define udiv_qrnnd(q, r, n1, n0, d) \
331 : "=a" ((USItype)(q)), \
332 "=d" ((USItype)(r)) \
333 : "0" ((USItype)(n0)), \
334 "1" ((USItype)(n1)), \
336 #define count_leading_zeros(count, x) \
339 __asm__ ("bsrl %1,%0" \
340 : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
341 (count) = __cbtmp ^ 31; \
347 #if defined (__i860__)
349 /* Make sure these patterns really improve the code before
350 switching them on. */
351 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
356 struct {USItype __l, __h;} __i; \
358 __a.__i.__l = (al); \
359 __a.__i.__h = (ah); \
360 __b.__i.__l = (bl); \
361 __b.__i.__h = (bh); \
362 __asm__ ("fiadd.dd %1,%2,%0" \
364 : "%f" (__a.__ll), "f" (__b.__ll)); \
365 (sh) = __s.__i.__h; \
366 (sl) = __s.__i.__l; \
368 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
373 struct {USItype __l, __h;} __i; \
375 __a.__i.__l = (al); \
376 __a.__i.__h = (ah); \
377 __b.__i.__l = (bl); \
378 __b.__i.__h = (bh); \
379 __asm__ ("fisub.dd %1,%2,%0" \
381 : "%f" (__a.__ll), "f" (__b.__ll)); \
382 (sh) = __s.__i.__h; \
383 (sl) = __s.__i.__l; \
386 #endif /* __i860__ */
388 #if defined (__i960__)
389 #define umul_ppmm(w1, w0, u, v) \
390 ({union {UDItype __ll; \
391 struct {USItype __l, __h;} __i; \
393 __asm__ ("emul %2,%1,%0" \
395 : "%dI" ((USItype)(u)), \
396 "dI" ((USItype)(v))); \
397 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
398 #define __umulsidi3(u, v) \
400 __asm__ ("emul %2,%1,%0" \
402 : "%dI" ((USItype)(u)), \
403 "dI" ((USItype)(v))); \
405 #endif /* __i960__ */
407 #if defined (__mc68000__)
408 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
409 __asm__ ("add%.l %5,%1
411 : "=d" ((USItype)(sh)), \
412 "=&d" ((USItype)(sl)) \
413 : "%0" ((USItype)(ah)), \
414 "d" ((USItype)(bh)), \
415 "%1" ((USItype)(al)), \
417 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
418 __asm__ ("sub%.l %5,%1
420 : "=d" ((USItype)(sh)), \
421 "=&d" ((USItype)(sl)) \
422 : "0" ((USItype)(ah)), \
423 "d" ((USItype)(bh)), \
424 "1" ((USItype)(al)), \
426 #if defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)
427 #define umul_ppmm(w1, w0, u, v) \
428 __asm__ ("mulu%.l %3,%1:%0" \
429 : "=d" ((USItype)(w0)), \
430 "=d" ((USItype)(w1)) \
431 : "%0" ((USItype)(u)), \
432 "dmi" ((USItype)(v)))
434 #define udiv_qrnnd(q, r, n1, n0, d) \
435 __asm__ ("divu%.l %4,%1:%0" \
436 : "=d" ((USItype)(q)), \
437 "=d" ((USItype)(r)) \
438 : "0" ((USItype)(n0)), \
439 "1" ((USItype)(n1)), \
440 "dmi" ((USItype)(d)))
442 #define sdiv_qrnnd(q, r, n1, n0, d) \
443 __asm__ ("divs%.l %4,%1:%0" \
444 : "=d" ((USItype)(q)), \
445 "=d" ((USItype)(r)) \
446 : "0" ((USItype)(n0)), \
447 "1" ((USItype)(n1)), \
448 "dmi" ((USItype)(d)))
449 #define count_leading_zeros(count, x) \
450 __asm__ ("bfffo %1{%b2:%b2},%0" \
451 : "=d" ((USItype)(count)) \
452 : "od" ((USItype)(x)), "n" (0))
453 #else /* not mc68020 */
454 /* %/ inserts REGISTER_PREFIX. */
455 #define umul_ppmm(xh, xl, a, b) \
456 __asm__ ("| Inlined umul_ppmm
482 : "=g" ((USItype)(xh)), \
483 "=g" ((USItype)(xl)) \
484 : "g" ((USItype)(a)), \
486 : "d0", "d1", "d2", "d3", "d4")
487 #define UMUL_TIME 100
488 #define UDIV_TIME 400
489 #endif /* not mc68020 */
492 #if defined (__m88000__)
493 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
494 __asm__ ("addu.co %1,%r4,%r5
495 addu.ci %0,%r2,%r3" \
496 : "=r" ((USItype)(sh)), \
497 "=&r" ((USItype)(sl)) \
498 : "%rJ" ((USItype)(ah)), \
499 "rJ" ((USItype)(bh)), \
500 "%rJ" ((USItype)(al)), \
501 "rJ" ((USItype)(bl)))
502 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
503 __asm__ ("subu.co %1,%r4,%r5
504 subu.ci %0,%r2,%r3" \
505 : "=r" ((USItype)(sh)), \
506 "=&r" ((USItype)(sl)) \
507 : "rJ" ((USItype)(ah)), \
508 "rJ" ((USItype)(bh)), \
509 "rJ" ((USItype)(al)), \
510 "rJ" ((USItype)(bl)))
511 #define count_leading_zeros(count, x) \
514 __asm__ ("ff1 %0,%1" \
516 : "r" ((USItype)(x))); \
517 (count) = __cbtmp ^ 31; \
519 #if defined (__mc88110__)
520 #define umul_ppmm(wh, wl, u, v) \
522 union {UDItype __ll; \
523 struct {USItype __h, __l;} __i; \
525 __asm__ ("mulu.d %0,%1,%2" \
527 : "r" ((USItype)(u)), \
528 "r" ((USItype)(v))); \
529 (wh) = __xx.__i.__h; \
530 (wl) = __xx.__i.__l; \
532 #define udiv_qrnnd(q, r, n1, n0, d) \
533 ({union {UDItype __ll; \
534 struct {USItype __h, __l;} __i; \
537 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
538 __asm__ ("divu.d %0,%1,%2" \
541 "r" ((USItype)(d))); \
542 (r) = (n0) - __q * (d); (q) = __q; })
547 #define UDIV_TIME 150
548 #endif /* __mc88110__ */
549 #endif /* __m88000__ */
551 #if defined (__mips__)
552 #define umul_ppmm(w1, w0, u, v) \
553 __asm__ ("multu %2,%3
556 : "=d" ((USItype)(w0)), \
557 "=d" ((USItype)(w1)) \
558 : "d" ((USItype)(u)), \
561 #define UDIV_TIME 100
562 #endif /* __mips__ */
564 #if defined (__ns32000__)
565 #define umul_ppmm(w1, w0, u, v) \
566 ({union {UDItype __ll; \
567 struct {USItype __l, __h;} __i; \
569 __asm__ ("meid %2,%0" \
571 : "%0" ((USItype)(u)), \
572 "g" ((USItype)(v))); \
573 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
574 #define __umulsidi3(u, v) \
576 __asm__ ("meid %2,%0" \
578 : "%0" ((USItype)(u)), \
579 "g" ((USItype)(v))); \
581 #define udiv_qrnnd(q, r, n1, n0, d) \
582 ({union {UDItype __ll; \
583 struct {USItype __l, __h;} __i; \
585 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
586 __asm__ ("deid %2,%0" \
589 "g" ((USItype)(d))); \
590 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
591 #endif /* __ns32000__ */
593 #if (defined (__powerpc__) || defined (___IBMR2__)) && W_TYPE_SIZE == 32
594 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
596 if (__builtin_constant_p (bh) && (bh) == 0) \
597 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
598 : "=r" ((USItype)(sh)), \
599 "=&r" ((USItype)(sl)) \
600 : "%r" ((USItype)(ah)), \
601 "%r" ((USItype)(al)), \
602 "rI" ((USItype)(bl))); \
603 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
604 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
605 : "=r" ((USItype)(sh)), \
606 "=&r" ((USItype)(sl)) \
607 : "%r" ((USItype)(ah)), \
608 "%r" ((USItype)(al)), \
609 "rI" ((USItype)(bl))); \
611 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
612 : "=r" ((USItype)(sh)), \
613 "=&r" ((USItype)(sl)) \
614 : "%r" ((USItype)(ah)), \
615 "r" ((USItype)(bh)), \
616 "%r" ((USItype)(al)), \
617 "rI" ((USItype)(bl))); \
619 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
621 if (__builtin_constant_p (ah) && (ah) == 0) \
622 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
623 : "=r" ((USItype)(sh)), \
624 "=&r" ((USItype)(sl)) \
625 : "r" ((USItype)(bh)), \
626 "rI" ((USItype)(al)), \
627 "r" ((USItype)(bl))); \
628 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
629 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
630 : "=r" ((USItype)(sh)), \
631 "=&r" ((USItype)(sl)) \
632 : "r" ((USItype)(bh)), \
633 "rI" ((USItype)(al)), \
634 "r" ((USItype)(bl))); \
635 else if (__builtin_constant_p (bh) && (bh) == 0) \
636 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
637 : "=r" ((USItype)(sh)), \
638 "=&r" ((USItype)(sl)) \
639 : "r" ((USItype)(ah)), \
640 "rI" ((USItype)(al)), \
641 "r" ((USItype)(bl))); \
642 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
643 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
644 : "=r" ((USItype)(sh)), \
645 "=&r" ((USItype)(sl)) \
646 : "r" ((USItype)(ah)), \
647 "rI" ((USItype)(al)), \
648 "r" ((USItype)(bl))); \
650 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
651 : "=r" ((USItype)(sh)), \
652 "=&r" ((USItype)(sl)) \
653 : "r" ((USItype)(ah)), \
654 "r" ((USItype)(bh)), \
655 "rI" ((USItype)(al)), \
656 "r" ((USItype)(bl))); \
658 #define count_leading_zeros(count, x) \
659 __asm__ ("{cntlz|cntlzw} %0,%1" \
660 : "=r" ((USItype)(count)) \
661 : "r" ((USItype)(x)))
662 #if defined (__powerpc__)
663 #define umul_ppmm(ph, pl, m0, m1) \
665 USItype __m0 = (m0), __m1 = (m1); \
666 __asm__ ("mulhwu %0,%1,%2" \
667 : "=r" ((USItype) ph) \
670 (pl) = __m0 * __m1; \
673 #define smul_ppmm(ph, pl, m0, m1) \
675 SItype __m0 = (m0), __m1 = (m1); \
676 __asm__ ("mulhw %0,%1,%2" \
677 : "=r" ((SItype) ph) \
680 (pl) = __m0 * __m1; \
683 #define UDIV_TIME 120
685 #define umul_ppmm(xh, xl, m0, m1) \
687 USItype __m0 = (m0), __m1 = (m1); \
688 __asm__ ("mul %0,%2,%3" \
689 : "=r" ((USItype)(xh)), \
690 "=q" ((USItype)(xl)) \
693 (xh) += ((((SItype) __m0 >> 31) & __m1) \
694 + (((SItype) __m1 >> 31) & __m0)); \
697 #define smul_ppmm(xh, xl, m0, m1) \
698 __asm__ ("mul %0,%2,%3" \
699 : "=r" ((SItype)(xh)), \
700 "=q" ((SItype)(xl)) \
704 #define sdiv_qrnnd(q, r, nh, nl, d) \
705 __asm__ ("div %0,%2,%4" \
706 : "=r" ((SItype)(q)), "=q" ((SItype)(r)) \
707 : "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d)))
708 #define UDIV_TIME 100
710 #endif /* Power architecture variants. */
712 #if defined (__pyr__)
713 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
716 : "=r" ((USItype)(sh)), \
717 "=&r" ((USItype)(sl)) \
718 : "%0" ((USItype)(ah)), \
719 "g" ((USItype)(bh)), \
720 "%1" ((USItype)(al)), \
722 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
725 : "=r" ((USItype)(sh)), \
726 "=&r" ((USItype)(sl)) \
727 : "0" ((USItype)(ah)), \
728 "g" ((USItype)(bh)), \
729 "1" ((USItype)(al)), \
731 /* This insn doesn't work on ancient pyramids. */
732 #define umul_ppmm(w1, w0, u, v) \
735 struct {USItype __h, __l;} __i; \
738 __asm__ ("uemul %3,%0" \
739 : "=r" (__xx.__i.__h), \
740 "=r" (__xx.__i.__l) \
741 : "1" (__xx.__i.__l), \
742 "g" ((USItype)(v))); \
743 (w1) = __xx.__i.__h; \
744 (w0) = __xx.__i.__l;})
747 #if defined (__ibm032__) /* RT/ROMP */
748 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
751 : "=r" ((USItype)(sh)), \
752 "=&r" ((USItype)(sl)) \
753 : "%0" ((USItype)(ah)), \
754 "r" ((USItype)(bh)), \
755 "%1" ((USItype)(al)), \
757 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
760 : "=r" ((USItype)(sh)), \
761 "=&r" ((USItype)(sl)) \
762 : "0" ((USItype)(ah)), \
763 "r" ((USItype)(bh)), \
764 "1" ((USItype)(al)), \
766 #define umul_ppmm(ph, pl, m0, m1) \
768 USItype __m0 = (m0), __m1 = (m1); \
790 : "=r" ((USItype)(ph)), \
791 "=r" ((USItype)(pl)) \
795 (ph) += ((((SItype) __m0 >> 31) & __m1) \
796 + (((SItype) __m1 >> 31) & __m0)); \
799 #define UDIV_TIME 200
800 #define count_leading_zeros(count, x) \
802 if ((x) >= 0x10000) \
803 __asm__ ("clz %0,%1" \
804 : "=r" ((USItype)(count)) \
805 : "r" ((USItype)(x) >> 16)); \
808 __asm__ ("clz %0,%1" \
809 : "=r" ((USItype)(count)) \
810 : "r" ((USItype)(x))); \
816 #if defined (__sparc__)
817 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
818 __asm__ ("addcc %r4,%5,%1
820 : "=r" ((USItype)(sh)), \
821 "=&r" ((USItype)(sl)) \
822 : "%rJ" ((USItype)(ah)), \
823 "rI" ((USItype)(bh)), \
824 "%rJ" ((USItype)(al)), \
825 "rI" ((USItype)(bl)) \
827 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
828 __asm__ ("subcc %r4,%5,%1
830 : "=r" ((USItype)(sh)), \
831 "=&r" ((USItype)(sl)) \
832 : "rJ" ((USItype)(ah)), \
833 "rI" ((USItype)(bh)), \
834 "rJ" ((USItype)(al)), \
835 "rI" ((USItype)(bl)) \
837 #if defined (__sparc_v8__)
838 #define umul_ppmm(w1, w0, u, v) \
839 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
840 : "=r" ((USItype)(w1)), \
841 "=r" ((USItype)(w0)) \
842 : "r" ((USItype)(u)), \
844 #define udiv_qrnnd(q, r, n1, n0, d) \
845 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
846 : "=&r" ((USItype)(q)), \
847 "=&r" ((USItype)(r)) \
848 : "r" ((USItype)(n1)), \
849 "r" ((USItype)(n0)), \
852 #if defined (__sparclite__)
853 /* This has hardware multiply but not divide. It also has two additional
854 instructions scan (ffs from high bit) and divscc. */
855 #define umul_ppmm(w1, w0, u, v) \
856 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
857 : "=r" ((USItype)(w1)), \
858 "=r" ((USItype)(w0)) \
859 : "r" ((USItype)(u)), \
861 #define udiv_qrnnd(q, r, n1, n0, d) \
862 __asm__ ("! Inlined udiv_qrnnd
863 wr %%g0,%2,%%y ! Not a delayed write for sparclite
900 1: ! End of inline udiv_qrnnd" \
901 : "=r" ((USItype)(q)), \
902 "=r" ((USItype)(r)) \
903 : "r" ((USItype)(n1)), \
904 "r" ((USItype)(n0)), \
905 "rI" ((USItype)(d)) \
906 : "%g1" __AND_CLOBBER_CC)
908 #define count_leading_zeros(count, x) \
909 __asm__ ("scan %1,0,%0" \
910 : "=r" ((USItype)(x)) \
911 : "r" ((USItype)(count)))
913 /* SPARC without integer multiplication and divide instructions.
914 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
915 #define umul_ppmm(w1, w0, u, v) \
916 __asm__ ("! Inlined umul_ppmm
917 wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
918 sra %3,31,%%g2 ! Don't move this insn
919 and %2,%%g2,%%g2 ! Don't move this insn
920 andcc %%g0,0,%%g1 ! Don't move this insn
956 : "=r" ((USItype)(w1)), \
957 "=r" ((USItype)(w0)) \
958 : "%rI" ((USItype)(u)), \
960 : "%g1", "%g2" __AND_CLOBBER_CC)
961 #define UMUL_TIME 39 /* 39 instructions */
962 /* It's quite necessary to add this much assembler for the sparc.
963 The default udiv_qrnnd (in C) is more than 10 times slower! */
964 #define udiv_qrnnd(q, r, n1, n0, d) \
965 __asm__ ("! Inlined udiv_qrnnd
969 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
970 sub %1,%2,%1 ! this kills msb of n
971 addx %1,%1,%1 ! so this can't give carry
976 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
978 sub %1,%2,%1 ! this kills msb of n
983 ! Got carry from n. Subtract next step to cancel this carry.
985 addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
988 ! End of inline udiv_qrnnd" \
989 : "=&r" ((USItype)(q)), \
990 "=&r" ((USItype)(r)) \
991 : "r" ((USItype)(d)), \
992 "1" ((USItype)(n1)), \
993 "0" ((USItype)(n0)) : "%g1" __AND_CLOBBER_CC)
994 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
995 #endif /* __sparclite__ */
996 #endif /* __sparc_v8__ */
997 #endif /* __sparc__ */
999 #if defined (__vax__)
1000 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1001 __asm__ ("addl2 %5,%1
1003 : "=g" ((USItype)(sh)), \
1004 "=&g" ((USItype)(sl)) \
1005 : "%0" ((USItype)(ah)), \
1006 "g" ((USItype)(bh)), \
1007 "%1" ((USItype)(al)), \
1008 "g" ((USItype)(bl)))
1009 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1010 __asm__ ("subl2 %5,%1
1012 : "=g" ((USItype)(sh)), \
1013 "=&g" ((USItype)(sl)) \
1014 : "0" ((USItype)(ah)), \
1015 "g" ((USItype)(bh)), \
1016 "1" ((USItype)(al)), \
1017 "g" ((USItype)(bl)))
1018 #define umul_ppmm(xh, xl, m0, m1) \
1022 struct {USItype __l, __h;} __i; \
1024 USItype __m0 = (m0), __m1 = (m1); \
1025 __asm__ ("emul %1,%2,$0,%0" \
1026 : "=r" (__xx.__ll) \
1029 (xh) = __xx.__i.__h; \
1030 (xl) = __xx.__i.__l; \
1031 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1032 + (((SItype) __m1 >> 31) & __m0)); \
1034 #define sdiv_qrnnd(q, r, n1, n0, d) \
1036 union {DItype __ll; \
1037 struct {SItype __l, __h;} __i; \
1039 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1040 __asm__ ("ediv %3,%2,%0,%1" \
1041 : "=g" (q), "=g" (r) \
1042 : "g" (__n1n0.ll), "g" (d)); \
1044 #endif /* __vax__ */
1046 #endif /* __GNUC__ */
1048 /* If this machine has no inline assembler, use C macros. */
1050 #if !defined (add_ssaaaa)
1051 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1054 __x = (al) + (bl); \
1055 (sh) = (ah) + (bh) + (__x < (al)); \
1060 #if !defined (sub_ddmmss)
1061 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1064 __x = (al) - (bl); \
1065 (sh) = (ah) - (bh) - (__x > (al)); \
1070 #if !defined (umul_ppmm)
1071 #define umul_ppmm(w1, w0, u, v) \
1073 USItype __x0, __x1, __x2, __x3; \
1074 USItype __ul, __vl, __uh, __vh; \
1076 __ul = __ll_lowpart (u); \
1077 __uh = __ll_highpart (u); \
1078 __vl = __ll_lowpart (v); \
1079 __vh = __ll_highpart (v); \
1081 __x0 = (USItype) __ul * __vl; \
1082 __x1 = (USItype) __ul * __vh; \
1083 __x2 = (USItype) __uh * __vl; \
1084 __x3 = (USItype) __uh * __vh; \
1086 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1087 __x1 += __x2; /* but this indeed can */ \
1088 if (__x1 < __x2) /* did we get it? */ \
1089 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1091 (w1) = __x3 + __ll_highpart (__x1); \
1092 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1096 #if !defined (__umulsidi3)
1097 #define __umulsidi3(u, v) \
1099 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1103 /* Define this unconditionally, so it can be used for debugging. */
1104 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1106 USItype __d1, __d0, __q1, __q0; \
1107 USItype __r1, __r0, __m; \
1108 __d1 = __ll_highpart (d); \
1109 __d0 = __ll_lowpart (d); \
1111 __r1 = (n1) % __d1; \
1112 __q1 = (n1) / __d1; \
1113 __m = (USItype) __q1 * __d0; \
1114 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1117 __q1--, __r1 += (d); \
1118 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1120 __q1--, __r1 += (d); \
1124 __r0 = __r1 % __d1; \
1125 __q0 = __r1 / __d1; \
1126 __m = (USItype) __q0 * __d0; \
1127 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1130 __q0--, __r0 += (d); \
1133 __q0--, __r0 += (d); \
1137 (q) = (USItype) __q1 * __ll_B | __q0; \
1141 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1142 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1143 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1144 #define udiv_qrnnd(q, r, nh, nl, d) \
1147 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1152 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1153 #if !defined (udiv_qrnnd)
1154 #define UDIV_NEEDS_NORMALIZATION 1
1155 #define udiv_qrnnd __udiv_qrnnd_c
1158 #if !defined (count_leading_zeros)
1159 extern const UQItype __clz_tab[];
1160 #define count_leading_zeros(count, x) \
1162 USItype __xr = (x); \
1165 if (SI_TYPE_SIZE <= 32) \
1167 __a = __xr < (1<<2*__BITS4) \
1168 ? (__xr < (1<<__BITS4) ? 0 : __BITS4) \
1169 : (__xr < (1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1173 for (__a = SI_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1174 if (((__xr >> __a) & 0xff) != 0) \
1178 (count) = SI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1182 #ifndef UDIV_NEEDS_NORMALIZATION
1183 #define UDIV_NEEDS_NORMALIZATION 0