1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 93-97, 1998 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
4 and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to the Free
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Instruction scheduling pass.
26 This pass implements list scheduling within basic blocks. It is
27 run twice: (1) after flow analysis, but before register allocation,
28 and (2) after register allocation.
30 The first run performs interblock scheduling, moving insns between
31 different blocks in the same "region", and the second runs only
32 basic block scheduling.
34 Interblock motions performed are useful motions and speculative
35 motions, including speculative loads. Motions requiring code
36 duplication are not supported. The identification of motion type
37 and the check for validity of speculative motions requires
38 construction and analysis of the function's control flow graph.
39 The scheduler works as follows:
41 We compute insn priorities based on data dependencies. Flow
42 analysis only creates a fraction of the data-dependencies we must
43 observe: namely, only those dependencies which the combiner can be
44 expected to use. For this pass, we must therefore create the
45 remaining dependencies we need to observe: register dependencies,
46 memory dependencies, dependencies to keep function calls in order,
47 and the dependence between a conditional branch and the setting of
48 condition codes are all dealt with here.
50 The scheduler first traverses the data flow graph, starting with
51 the last instruction, and proceeding to the first, assigning values
52 to insn_priority as it goes. This sorts the instructions
53 topologically by data dependence.
55 Once priorities have been established, we order the insns using
56 list scheduling. This works as follows: starting with a list of
57 all the ready insns, and sorted according to priority number, we
58 schedule the insn from the end of the list by placing its
59 predecessors in the list according to their priority order. We
60 consider this insn scheduled by setting the pointer to the "end" of
61 the list to point to the previous insn. When an insn has no
62 predecessors, we either queue it until sufficient time has elapsed
63 or add it to the ready list. As the instructions are scheduled or
64 when stalls are introduced, the queue advances and dumps insns into
65 the ready list. When all insns down to the lowest priority have
66 been scheduled, the critical path of the basic block has been made
67 as short as possible. The remaining insns are then scheduled in
70 Function unit conflicts are resolved during forward list scheduling
71 by tracking the time when each insn is committed to the schedule
72 and from that, the time the function units it uses must be free.
73 As insns on the ready list are considered for scheduling, those
74 that would result in a blockage of the already committed insns are
75 queued until no blockage will result.
77 The following list shows the order in which we want to break ties
78 among insns in the ready list:
80 1. choose insn with the longest path to end of bb, ties
82 2. choose insn with least contribution to register pressure,
84 3. prefer in-block upon interblock motion, ties broken by
85 4. prefer useful upon speculative motion, ties broken by
86 5. choose insn with largest control flow probability, ties
88 6. choose insn with the least dependences upon the previously
89 scheduled insn, or finally
90 7 choose the insn which has the most insns dependent on it.
91 8. choose insn with lowest UID.
93 Memory references complicate matters. Only if we can be certain
94 that memory references are not part of the data dependency graph
95 (via true, anti, or output dependence), can we move operations past
96 memory references. To first approximation, reads can be done
97 independently, while writes introduce dependencies. Better
98 approximations will yield fewer dependencies.
100 Before reload, an extended analysis of interblock data dependences
101 is required for interblock scheduling. This is performed in
102 compute_block_backward_dependences ().
104 Dependencies set up by memory references are treated in exactly the
105 same way as other dependencies, by using LOG_LINKS backward
106 dependences. LOG_LINKS are translated into INSN_DEPEND forward
107 dependences for the purpose of forward list scheduling.
109 Having optimized the critical path, we may have also unduly
110 extended the lifetimes of some registers. If an operation requires
111 that constants be loaded into registers, it is certainly desirable
112 to load those constants as early as necessary, but no earlier.
113 I.e., it will not do to load up a bunch of registers at the
114 beginning of a basic block only to use them at the end, if they
115 could be loaded later, since this may result in excessive register
118 Note that since branches are never in basic blocks, but only end
119 basic blocks, this pass will not move branches. But that is ok,
120 since we can use GNU's delayed branch scheduling pass to take care
123 Also note that no further optimizations based on algebraic
124 identities are performed, so this pass would be a good one to
125 perform instruction splitting, such as breaking up a multiply
126 instruction into shifts and adds where that is profitable.
128 Given the memory aliasing analysis that this pass should perform,
129 it should be possible to remove redundant stores to memory, and to
130 load values from registers instead of hitting memory.
132 Before reload, speculative insns are moved only if a 'proof' exists
133 that no exception will be caused by this, and if no live registers
134 exist that inhibit the motion (live registers constraints are not
135 represented by data dependence edges).
137 This pass must update information that subsequent passes expect to
138 be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
139 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
142 The information in the line number notes is carefully retained by
143 this pass. Notes that refer to the starting and ending of
144 exception regions are also carefully retained by this pass. All
145 other NOTE insns are grouped in their same relative order at the
146 beginning of basic blocks and regions that have been scheduled.
148 The main entry point for this pass is schedule_insns(), called for
149 each function. The work of the scheduler is organized in three
150 levels: (1) function level: insns are subject to splitting,
151 control-flow-graph is constructed, regions are computed (after
152 reload, each region is of one block), (2) region level: control
153 flow graph attributes required for interblock scheduling are
154 computed (dominators, reachability, etc.), data dependences and
155 priorities are computed, and (3) block level: insns in the block
156 are actually scheduled. */
161 #include "basic-block.h"
163 #include "hard-reg-set.h"
165 #include "insn-config.h"
166 #include "insn-attr.h"
170 extern char *reg_known_equiv_p;
171 extern rtx *reg_known_value;
173 #ifdef INSN_SCHEDULING
175 /* target_units bitmask has 1 for each unit in the cpu. It should be
176 possible to compute this variable from the machine description.
177 But currently it is computed by examinning the insn list. Since
178 this is only needed for visualization, it seems an acceptable
179 solution. (For understanding the mapping of bits to units, see
180 definition of function_units[] in "insn-attrtab.c") */
182 static int target_units = 0;
184 /* issue_rate is the number of insns that can be scheduled in the same
185 machine cycle. It can be defined in the config/mach/mach.h file,
186 otherwise we set it to 1. */
188 static int issue_rate;
194 /* sched-verbose controls the amount of debugging output the
195 scheduler prints. It is controlled by -fsched-verbose-N:
196 N>0 and no -DSR : the output is directed to stderr.
197 N>=10 will direct the printouts to stderr (regardless of -dSR).
199 N=2: bb's probabilities, detailed ready list info, unit/insn info.
200 N=3: rtl at abort point, control-flow, regions info.
201 N=5: dependences info. */
203 #define MAX_RGN_BLOCKS 10
204 #define MAX_RGN_INSNS 100
206 static int sched_verbose_param = 0;
207 static int sched_verbose = 0;
209 /* nr_inter/spec counts interblock/speculative motion for the function */
210 static int nr_inter, nr_spec;
213 /* debugging file. all printouts are sent to dump, which is always set,
214 either to stderr, or to the dump listing file (-dRS). */
215 static FILE *dump = 0;
217 /* fix_sched_param() is called from toplev.c upon detection
218 of the -fsched-***-N options. */
221 fix_sched_param (param, val)
224 if (!strcmp (param, "verbose"))
225 sched_verbose_param = atoi (val);
227 warning ("fix_sched_param: unknown param: %s", param);
231 /* Arrays set up by scheduling for the same respective purposes as
232 similar-named arrays set up by flow analysis. We work with these
233 arrays during the scheduling pass so we can compare values against
236 Values of these arrays are copied at the end of this pass into the
237 arrays set up by flow analysis. */
238 static int *sched_reg_n_calls_crossed;
239 static int *sched_reg_live_length;
240 static int *sched_reg_basic_block;
242 /* We need to know the current block number during the post scheduling
243 update of live register information so that we can also update
244 REG_BASIC_BLOCK if a register changes blocks. */
245 static int current_block_num;
247 /* Element N is the next insn that sets (hard or pseudo) register
248 N within the current basic block; or zero, if there is no
249 such insn. Needed for new registers which may be introduced
250 by splitting insns. */
251 static rtx *reg_last_uses;
252 static rtx *reg_last_sets;
253 static regset reg_pending_sets;
254 static int reg_pending_sets_all;
256 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
257 static int *insn_luid;
258 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
260 /* Vector indexed by INSN_UID giving each instruction a priority. */
261 static int *insn_priority;
262 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
264 static short *insn_costs;
265 #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
267 /* Vector indexed by INSN_UID giving an encoding of the function units
269 static short *insn_units;
270 #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)]
272 /* Vector indexed by INSN_UID giving each instruction a register-weight.
273 This weight is an estimation of the insn contribution to registers pressure. */
274 static int *insn_reg_weight;
275 #define INSN_REG_WEIGHT(INSN) (insn_reg_weight[INSN_UID (INSN)])
277 /* Vector indexed by INSN_UID giving list of insns which
278 depend upon INSN. Unlike LOG_LINKS, it represents forward dependences. */
279 static rtx *insn_depend;
280 #define INSN_DEPEND(INSN) insn_depend[INSN_UID (INSN)]
282 /* Vector indexed by INSN_UID. Initialized to the number of incoming
283 edges in forward dependence graph (= number of LOG_LINKS). As
284 scheduling procedes, dependence counts are decreased. An
285 instruction moves to the ready list when its counter is zero. */
286 static int *insn_dep_count;
287 #define INSN_DEP_COUNT(INSN) (insn_dep_count[INSN_UID (INSN)])
289 /* Vector indexed by INSN_UID giving an encoding of the blockage range
290 function. The unit and the range are encoded. */
291 static unsigned int *insn_blockage;
292 #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)]
294 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
295 #define ENCODE_BLOCKAGE(U, R) \
296 ((((U) << UNIT_BITS) << BLOCKAGE_BITS \
297 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
298 | MAX_BLOCKAGE_COST (R))
299 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
300 #define BLOCKAGE_RANGE(B) \
301 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
302 | ((B) & BLOCKAGE_MASK))
304 /* Encodings of the `<name>_unit_blockage_range' function. */
305 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
306 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
308 #define DONE_PRIORITY -1
309 #define MAX_PRIORITY 0x7fffffff
310 #define TAIL_PRIORITY 0x7ffffffe
311 #define LAUNCH_PRIORITY 0x7f000001
312 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
313 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
315 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
316 static int *insn_ref_count;
317 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
319 /* Vector indexed by INSN_UID giving line-number note in effect for each
320 insn. For line-number notes, this indicates whether the note may be
322 static rtx *line_note;
323 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
325 /* Vector indexed by basic block number giving the starting line-number
326 for each basic block. */
327 static rtx *line_note_head;
329 /* List of important notes we must keep around. This is a pointer to the
330 last element in the list. */
331 static rtx note_list;
333 /* Regsets telling whether a given register is live or dead before the last
334 scheduled insn. Must scan the instructions once before scheduling to
335 determine what registers are live or dead at the end of the block. */
336 static regset bb_live_regs;
338 /* Regset telling whether a given register is live after the insn currently
339 being scheduled. Before processing an insn, this is equal to bb_live_regs
340 above. This is used so that we can find registers that are newly born/dead
341 after processing an insn. */
342 static regset old_live_regs;
344 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
345 during the initial scan and reused later. If there are not exactly as
346 many REG_DEAD notes in the post scheduled code as there were in the
347 prescheduled code then we trigger an abort because this indicates a bug. */
348 static rtx dead_notes;
352 /* An instruction is ready to be scheduled when all insns preceding it
353 have already been scheduled. It is important to ensure that all
354 insns which use its result will not be executed until its result
355 has been computed. An insn is maintained in one of four structures:
357 (P) the "Pending" set of insns which cannot be scheduled until
358 their dependencies have been satisfied.
359 (Q) the "Queued" set of insns that can be scheduled when sufficient
361 (R) the "Ready" list of unscheduled, uncommitted insns.
362 (S) the "Scheduled" list of insns.
364 Initially, all insns are either "Pending" or "Ready" depending on
365 whether their dependencies are satisfied.
367 Insns move from the "Ready" list to the "Scheduled" list as they
368 are committed to the schedule. As this occurs, the insns in the
369 "Pending" list have their dependencies satisfied and move to either
370 the "Ready" list or the "Queued" set depending on whether
371 sufficient time has passed to make them ready. As time passes,
372 insns move from the "Queued" set to the "Ready" list. Insns may
373 move from the "Ready" list to the "Queued" set if they are blocked
374 due to a function unit conflict.
376 The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled
377 insns, i.e., those that are ready, queued, and pending.
378 The "Queued" set (Q) is implemented by the variable `insn_queue'.
379 The "Ready" list (R) is implemented by the variables `ready' and
381 The "Scheduled" list (S) is the new insn chain built by this pass.
383 The transition (R->S) is implemented in the scheduling loop in
384 `schedule_block' when the best insn to schedule is chosen.
385 The transition (R->Q) is implemented in `queue_insn' when an
386 insn is found to have a function unit conflict with the already
388 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
389 insns move from the ready list to the scheduled list.
390 The transition (Q->R) is implemented in 'queue_to_insn' as time
391 passes or stalls are introduced. */
393 /* Implement a circular buffer to delay instructions until sufficient
394 time has passed. INSN_QUEUE_SIZE is a power of two larger than
395 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
396 longest time an isnsn may be queued. */
397 static rtx insn_queue[INSN_QUEUE_SIZE];
398 static int q_ptr = 0;
399 static int q_size = 0;
400 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
401 #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1))
403 /* Vector indexed by INSN_UID giving the minimum clock tick at which
404 the insn becomes ready. This is used to note timing constraints for
405 insns in the pending list. */
406 static int *insn_tick;
407 #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)])
409 /* Data structure for keeping track of register information
410 during that register's life. */
419 /* Forward declarations. */
420 static void add_dependence PROTO ((rtx, rtx, enum reg_note));
421 static void remove_dependence PROTO ((rtx, rtx));
422 static rtx find_insn_list PROTO ((rtx, rtx));
423 static int insn_unit PROTO ((rtx));
424 static unsigned int blockage_range PROTO ((int, rtx));
425 static void clear_units PROTO ((void));
426 static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int));
427 static void schedule_unit PROTO ((int, rtx, int));
428 static int actual_hazard PROTO ((int, rtx, int, int));
429 static int potential_hazard PROTO ((int, rtx, int));
430 static int insn_cost PROTO ((rtx, rtx, rtx));
431 static int priority PROTO ((rtx));
432 static void free_pending_lists PROTO ((void));
433 static void add_insn_mem_dependence PROTO ((rtx *, rtx *, rtx, rtx));
434 static void flush_pending_lists PROTO ((rtx, int));
435 static void sched_analyze_1 PROTO ((rtx, rtx));
436 static void sched_analyze_2 PROTO ((rtx, rtx));
437 static void sched_analyze_insn PROTO ((rtx, rtx, rtx));
438 static void sched_analyze PROTO ((rtx, rtx));
439 static void sched_note_set PROTO ((rtx, int));
440 static int rank_for_schedule PROTO ((const GENERIC_PTR, const GENERIC_PTR));
441 static void swap_sort PROTO ((rtx *, int));
442 static void queue_insn PROTO ((rtx, int));
443 static int schedule_insn PROTO ((rtx, rtx *, int, int));
444 static void create_reg_dead_note PROTO ((rtx, rtx));
445 static void attach_deaths PROTO ((rtx, rtx, int));
446 static void attach_deaths_insn PROTO ((rtx));
447 static int new_sometimes_live PROTO ((struct sometimes *, int, int));
448 static void finish_sometimes_live PROTO ((struct sometimes *, int));
449 static int schedule_block PROTO ((int, int));
450 static rtx regno_use_in PROTO ((int, rtx));
451 static void split_hard_reg_notes PROTO ((rtx, rtx, rtx));
452 static void new_insn_dead_notes PROTO ((rtx, rtx, rtx, rtx));
453 static void update_n_sets PROTO ((rtx, int));
454 static void update_flow_info PROTO ((rtx, rtx, rtx, rtx));
455 static char *safe_concat PROTO ((char *, char *, char *));
456 static int insn_issue_delay PROTO ((rtx));
457 static int birthing_insn_p PROTO ((rtx));
458 static void adjust_priority PROTO ((rtx));
460 /* Mapping of insns to their original block prior to scheduling. */
461 static int *insn_orig_block;
462 #define INSN_BLOCK(insn) (insn_orig_block[INSN_UID (insn)])
464 /* Some insns (e.g. call) are not allowed to move across blocks. */
465 static char *cant_move;
466 #define CANT_MOVE(insn) (cant_move[INSN_UID (insn)])
468 /* Control flow graph edges are kept in circular lists. */
477 static edge *edge_table;
479 #define NEXT_IN(edge) (edge_table[edge].next_in)
480 #define NEXT_OUT(edge) (edge_table[edge].next_out)
481 #define FROM_BLOCK(edge) (edge_table[edge].from_block)
482 #define TO_BLOCK(edge) (edge_table[edge].to_block)
484 /* Number of edges in the control flow graph. (in fact larger than
485 that by 1, since edge 0 is unused.) */
488 /* Circular list of incoming/outgoing edges of a block */
489 static int *in_edges;
490 static int *out_edges;
492 #define IN_EDGES(block) (in_edges[block])
493 #define OUT_EDGES(block) (out_edges[block])
495 /* List of labels which cannot be deleted, needed for control
496 flow graph construction. */
497 extern rtx forced_labels;
500 static int is_cfg_nonregular PROTO ((void));
501 static int build_control_flow PROTO ((int_list_ptr *, int_list_ptr *,
503 static void new_edge PROTO ((int, int));
506 /* A region is the main entity for interblock scheduling: insns
507 are allowed to move between blocks in the same region, along
508 control flow graph edges, in the 'up' direction. */
511 int rgn_nr_blocks; /* number of blocks in region */
512 int rgn_blocks; /* blocks in the region (actually index in rgn_bb_table) */
516 /* Number of regions in the procedure */
517 static int nr_regions;
519 /* Table of region descriptions */
520 static region *rgn_table;
522 /* Array of lists of regions' blocks */
523 static int *rgn_bb_table;
525 /* Topological order of blocks in the region (if b2 is reachable from
526 b1, block_to_bb[b2] > block_to_bb[b1]).
527 Note: A basic block is always referred to by either block or b,
528 while its topological order name (in the region) is refered to by
531 static int *block_to_bb;
533 /* The number of the region containing a block. */
534 static int *containing_rgn;
536 #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks)
537 #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks)
538 #define BLOCK_TO_BB(block) (block_to_bb[block])
539 #define CONTAINING_RGN(block) (containing_rgn[block])
541 void debug_regions PROTO ((void));
542 static void find_single_block_region PROTO ((void));
543 static void find_rgns PROTO ((int_list_ptr *, int_list_ptr *,
544 int *, int *, sbitmap *));
545 static int too_large PROTO ((int, int *, int *));
547 extern void debug_live PROTO ((int, int));
549 /* Blocks of the current region being scheduled. */
550 static int current_nr_blocks;
551 static int current_blocks;
553 /* The mapping from bb to block */
554 #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)])
557 /* Bit vectors and bitset operations are needed for computations on
558 the control flow graph. */
560 typedef unsigned HOST_WIDE_INT *bitset;
563 int *first_member; /* pointer to the list start in bitlst_table. */
564 int nr_members; /* the number of members of the bit list. */
568 static int bitlst_table_last;
569 static int bitlst_table_size;
570 static int *bitlst_table;
572 static char bitset_member PROTO ((bitset, int, int));
573 static void extract_bitlst PROTO ((bitset, int, bitlst *));
575 /* target info declarations.
577 The block currently being scheduled is referred to as the "target" block,
578 while other blocks in the region from which insns can be moved to the
579 target are called "source" blocks. The candidate structure holds info
580 about such sources: are they valid? Speculative? Etc. */
581 typedef bitlst bblst;
592 static candidate *candidate_table;
594 /* A speculative motion requires checking live information on the path
595 from 'source' to 'target'. The split blocks are those to be checked.
596 After a speculative motion, live information should be modified in
599 Lists of split and update blocks for each candidate of the current
600 target are in array bblst_table */
601 static int *bblst_table, bblst_size, bblst_last;
603 #define IS_VALID(src) ( candidate_table[src].is_valid )
604 #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative )
605 #define SRC_PROB(src) ( candidate_table[src].src_prob )
607 /* The bb being currently scheduled. */
608 static int target_bb;
611 typedef bitlst edgelst;
613 /* target info functions */
614 static void split_edges PROTO ((int, int, edgelst *));
615 static void compute_trg_info PROTO ((int));
616 void debug_candidate PROTO ((int));
617 void debug_candidates PROTO ((int));
620 /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */
621 typedef bitset bbset;
623 /* Number of words of the bbset. */
624 static int bbset_size;
626 /* Dominators array: dom[i] contains the bbset of dominators of
627 bb i in the region. */
630 /* bb 0 is the only region entry */
631 #define IS_RGN_ENTRY(bb) (!bb)
633 /* Is bb_src dominated by bb_trg. */
634 #define IS_DOMINATED(bb_src, bb_trg) \
635 ( bitset_member (dom[bb_src], bb_trg, bbset_size) )
637 /* Probability: Prob[i] is a float in [0, 1] which is the probability
638 of bb i relative to the region entry. */
641 /* The probability of bb_src, relative to bb_trg. Note, that while the
642 'prob[bb]' is a float in [0, 1], this macro returns an integer
644 #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \
647 /* Bit-set of edges, where bit i stands for edge i. */
648 typedef bitset edgeset;
650 /* Number of edges in the region. */
651 static int rgn_nr_edges;
653 /* Array of size rgn_nr_edges. */
654 static int *rgn_edges;
656 /* Number of words in an edgeset. */
657 static int edgeset_size;
659 /* Mapping from each edge in the graph to its number in the rgn. */
660 static int *edge_to_bit;
661 #define EDGE_TO_BIT(edge) (edge_to_bit[edge])
663 /* The split edges of a source bb is different for each target
664 bb. In order to compute this efficiently, the 'potential-split edges'
665 are computed for each bb prior to scheduling a region. This is actually
666 the split edges of each bb relative to the region entry.
668 pot_split[bb] is the set of potential split edges of bb. */
669 static edgeset *pot_split;
671 /* For every bb, a set of its ancestor edges. */
672 static edgeset *ancestor_edges;
674 static void compute_dom_prob_ps PROTO ((int));
676 #define ABS_VALUE(x) (((x)<0)?(-(x)):(x))
677 #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (INSN_BLOCK (INSN))))
678 #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (INSN_BLOCK (INSN))))
679 #define INSN_BB(INSN) (BLOCK_TO_BB (INSN_BLOCK (INSN)))
681 /* parameters affecting the decision of rank_for_schedule() */
682 #define MIN_DIFF_PRIORITY 2
683 #define MIN_PROBABILITY 40
684 #define MIN_PROB_DIFF 10
686 /* speculative scheduling functions */
687 static int check_live_1 PROTO ((int, rtx));
688 static void update_live_1 PROTO ((int, rtx));
689 static int check_live PROTO ((rtx, int));
690 static void update_live PROTO ((rtx, int));
691 static void set_spec_fed PROTO ((rtx));
692 static int is_pfree PROTO ((rtx, int, int));
693 static int find_conditional_protection PROTO ((rtx, int));
694 static int is_conditionally_protected PROTO ((rtx, int, int));
695 static int may_trap_exp PROTO ((rtx, int));
696 static int haifa_classify_insn PROTO ((rtx));
697 static int is_prisky PROTO ((rtx, int, int));
698 static int is_exception_free PROTO ((rtx, int, int));
700 static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx));
701 static void compute_block_forward_dependences PROTO ((int));
702 static void init_rgn_data_dependences PROTO ((int));
703 static void add_branch_dependences PROTO ((rtx, rtx));
704 static void compute_block_backward_dependences PROTO ((int));
705 void debug_dependencies PROTO ((void));
707 /* Notes handling mechanism:
708 =========================
709 Generally, NOTES are saved before scheduling and restored after scheduling.
710 The scheduler distinguishes between three types of notes:
712 (1) LINE_NUMBER notes, generated and used for debugging. Here,
713 before scheduling a region, a pointer to the LINE_NUMBER note is
714 added to the insn following it (in save_line_notes()), and the note
715 is removed (in rm_line_notes() and unlink_line_notes()). After
716 scheduling the region, this pointer is used for regeneration of
717 the LINE_NUMBER note (in restore_line_notes()).
719 (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
720 Before scheduling a region, a pointer to the note is added to the insn
721 that follows or precedes it. (This happens as part of the data dependence
722 computation). After scheduling an insn, the pointer contained in it is
723 used for regenerating the corresponding note (in reemit_notes).
725 (3) All other notes (e.g. INSN_DELETED): Before scheduling a block,
726 these notes are put in a list (in rm_other_notes() and
727 unlink_other_notes ()). After scheduling the block, these notes are
728 inserted at the beginning of the block (in schedule_block()). */
730 static rtx unlink_other_notes PROTO ((rtx, rtx));
731 static rtx unlink_line_notes PROTO ((rtx, rtx));
732 static void rm_line_notes PROTO ((int));
733 static void save_line_notes PROTO ((int));
734 static void restore_line_notes PROTO ((int));
735 static void rm_redundant_line_notes PROTO ((void));
736 static void rm_other_notes PROTO ((rtx, rtx));
737 static rtx reemit_notes PROTO ((rtx, rtx));
739 static void get_block_head_tail PROTO ((int, rtx *, rtx *));
741 static void find_pre_sched_live PROTO ((int));
742 static void find_post_sched_live PROTO ((int));
743 static void update_reg_usage PROTO ((void));
744 static int queue_to_ready PROTO ((rtx [], int));
746 static void debug_ready_list PROTO ((rtx[], int));
747 static void init_target_units PROTO ((void));
748 static void insn_print_units PROTO ((rtx));
749 static int get_visual_tbl_length PROTO ((void));
750 static void init_block_visualization PROTO ((void));
751 static void print_block_visualization PROTO ((int, char *));
752 static void visualize_scheduled_insns PROTO ((int, int));
753 static void visualize_no_unit PROTO ((rtx));
754 static void visualize_stall_cycles PROTO ((int, int));
755 static void print_exp PROTO ((char *, rtx, int));
756 static void print_value PROTO ((char *, rtx, int));
757 static void print_pattern PROTO ((char *, rtx, int));
758 static void print_insn PROTO ((char *, rtx, int));
759 void debug_reg_vector PROTO ((regset));
761 static rtx move_insn1 PROTO ((rtx, rtx));
762 static rtx move_insn PROTO ((rtx, rtx));
763 static rtx group_leader PROTO ((rtx));
764 static int set_priorities PROTO ((int));
765 static void init_rtx_vector PROTO ((rtx **, rtx *, int, int));
766 static void schedule_region PROTO ((int));
767 static void split_block_insns PROTO ((int));
769 #endif /* INSN_SCHEDULING */
771 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
773 /* Helper functions for instruction scheduling. */
775 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
776 static rtx unused_insn_list;
778 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
779 static rtx unused_expr_list;
781 static void free_list PROTO ((rtx *, rtx *));
782 static rtx alloc_INSN_LIST PROTO ((rtx, rtx));
783 static rtx alloc_EXPR_LIST PROTO ((int, rtx, rtx));
786 free_list (listp, unused_listp)
787 rtx *listp, *unused_listp;
789 register rtx link, prev_link;
795 link = XEXP (prev_link, 1);
800 link = XEXP (link, 1);
803 XEXP (prev_link, 1) = *unused_listp;
804 *unused_listp = *listp;
809 alloc_INSN_LIST (val, next)
814 if (unused_insn_list)
816 r = unused_insn_list;
817 unused_insn_list = XEXP (r, 1);
820 PUT_REG_NOTE_KIND (r, VOIDmode);
823 r = gen_rtx_INSN_LIST (VOIDmode, val, next);
829 alloc_EXPR_LIST (kind, val, next)
835 if (unused_expr_list)
837 r = unused_expr_list;
838 unused_expr_list = XEXP (r, 1);
841 PUT_REG_NOTE_KIND (r, kind);
844 r = gen_rtx_EXPR_LIST (kind, val, next);
849 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
850 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
851 of dependence that this link represents. */
854 add_dependence (insn, elem, dep_type)
857 enum reg_note dep_type;
861 /* Don't depend an insn on itself. */
865 /* If elem is part of a sequence that must be scheduled together, then
866 make the dependence point to the last insn of the sequence.
867 When HAVE_cc0, it is possible for NOTEs to exist between users and
868 setters of the condition codes, so we must skip past notes here.
869 Otherwise, NOTEs are impossible here. */
871 next = NEXT_INSN (elem);
874 while (next && GET_CODE (next) == NOTE)
875 next = NEXT_INSN (next);
878 if (next && SCHED_GROUP_P (next)
879 && GET_CODE (next) != CODE_LABEL)
881 /* Notes will never intervene here though, so don't bother checking
883 /* We must reject CODE_LABELs, so that we don't get confused by one
884 that has LABEL_PRESERVE_P set, which is represented by the same
885 bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be
887 while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next))
888 && GET_CODE (NEXT_INSN (next)) != CODE_LABEL)
889 next = NEXT_INSN (next);
891 /* Again, don't depend an insn on itself. */
895 /* Make the dependence to NEXT, the last insn of the group, instead
896 of the original ELEM. */
900 #ifdef INSN_SCHEDULING
901 /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.)
902 No need for interblock dependences with calls, since
903 calls are not moved between blocks. Note: the edge where
904 elem is a CALL is still required. */
905 if (GET_CODE (insn) == CALL_INSN
906 && (INSN_BB (elem) != INSN_BB (insn)))
911 /* Check that we don't already have this dependence. */
912 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
913 if (XEXP (link, 0) == elem)
915 /* If this is a more restrictive type of dependence than the existing
916 one, then change the existing dependence to this type. */
917 if ((int) dep_type < (int) REG_NOTE_KIND (link))
918 PUT_REG_NOTE_KIND (link, dep_type);
921 /* Might want to check one level of transitivity to save conses. */
923 link = alloc_INSN_LIST (elem, LOG_LINKS (insn));
924 LOG_LINKS (insn) = link;
926 /* Insn dependency, not data dependency. */
927 PUT_REG_NOTE_KIND (link, dep_type);
930 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
931 of INSN. Abort if not found. */
934 remove_dependence (insn, elem)
938 rtx prev, link, next;
941 for (prev = 0, link = LOG_LINKS (insn); link; link = next)
943 next = XEXP (link, 1);
944 if (XEXP (link, 0) == elem)
947 XEXP (prev, 1) = next;
949 LOG_LINKS (insn) = next;
951 XEXP (link, 1) = unused_insn_list;
952 unused_insn_list = link;
965 #ifndef INSN_SCHEDULING
967 schedule_insns (dump_file)
977 #define HAIFA_INLINE __inline
980 /* Computation of memory dependencies. */
982 /* The *_insns and *_mems are paired lists. Each pending memory operation
983 will have a pointer to the MEM rtx on one list and a pointer to the
984 containing insn on the other list in the same place in the list. */
986 /* We can't use add_dependence like the old code did, because a single insn
987 may have multiple memory accesses, and hence needs to be on the list
988 once for each memory access. Add_dependence won't let you add an insn
989 to a list more than once. */
991 /* An INSN_LIST containing all insns with pending read operations. */
992 static rtx pending_read_insns;
994 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
995 static rtx pending_read_mems;
997 /* An INSN_LIST containing all insns with pending write operations. */
998 static rtx pending_write_insns;
1000 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
1001 static rtx pending_write_mems;
1003 /* Indicates the combined length of the two pending lists. We must prevent
1004 these lists from ever growing too large since the number of dependencies
1005 produced is at least O(N*N), and execution time is at least O(4*N*N), as
1006 a function of the length of these pending lists. */
1008 static int pending_lists_length;
1010 /* The last insn upon which all memory references must depend.
1011 This is an insn which flushed the pending lists, creating a dependency
1012 between it and all previously pending memory references. This creates
1013 a barrier (or a checkpoint) which no memory reference is allowed to cross.
1015 This includes all non constant CALL_INSNs. When we do interprocedural
1016 alias analysis, this restriction can be relaxed.
1017 This may also be an INSN that writes memory if the pending lists grow
1020 static rtx last_pending_memory_flush;
1022 /* The last function call we have seen. All hard regs, and, of course,
1023 the last function call, must depend on this. */
1025 static rtx last_function_call;
1027 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
1028 that does not already cross a call. We create dependencies between each
1029 of those insn and the next call insn, to ensure that they won't cross a call
1030 after scheduling is done. */
1032 static rtx sched_before_next_call;
1034 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
1035 so that insns independent of the last scheduled insn will be preferred
1036 over dependent instructions. */
1038 static rtx last_scheduled_insn;
1040 /* Data structures for the computation of data dependences in a regions. We
1041 keep one copy of each of the declared above variables for each bb in the
1042 region. Before analyzing the data dependences for a bb, its variables
1043 are initialized as a function of the variables of its predecessors. When
1044 the analysis for a bb completes, we save the contents of each variable X
1045 to a corresponding bb_X[bb] variable. For example, pending_read_insns is
1046 copied to bb_pending_read_insns[bb]. Another change is that few
1047 variables are now a list of insns rather than a single insn:
1048 last_pending_memory_flash, last_function_call, reg_last_sets. The
1049 manipulation of these variables was changed appropriately. */
1051 static rtx **bb_reg_last_uses;
1052 static rtx **bb_reg_last_sets;
1054 static rtx *bb_pending_read_insns;
1055 static rtx *bb_pending_read_mems;
1056 static rtx *bb_pending_write_insns;
1057 static rtx *bb_pending_write_mems;
1058 static int *bb_pending_lists_length;
1060 static rtx *bb_last_pending_memory_flush;
1061 static rtx *bb_last_function_call;
1062 static rtx *bb_sched_before_next_call;
1064 /* functions for construction of the control flow graph. */
1066 /* Return 1 if control flow graph should not be constructed, 0 otherwise.
1068 We decide not to build the control flow graph if there is possibly more
1069 than one entry to the function, if computed branches exist, of if we
1070 have nonlocal gotos. */
1073 is_cfg_nonregular ()
1079 /* If we have a label that could be the target of a nonlocal goto, then
1080 the cfg is not well structured. */
1081 if (nonlocal_label_rtx_list () != NULL)
1084 /* If we have any forced labels, then the cfg is not well structured. */
1088 /* If this function has a computed jump, then we consider the cfg
1089 not well structured. */
1090 if (current_function_has_computed_jump)
1093 /* If we have exception handlers, then we consider the cfg not well
1094 structured. ?!? We should be able to handle this now that flow.c
1095 computes an accurate cfg for EH. */
1096 if (exception_handler_labels)
1099 /* If we have non-jumping insns which refer to labels, then we consider
1100 the cfg not well structured. */
1101 /* check for labels referred to other thn by jumps */
1102 for (b = 0; b < n_basic_blocks; b++)
1103 for (insn = basic_block_head[b];; insn = NEXT_INSN (insn))
1105 code = GET_CODE (insn);
1106 if (GET_RTX_CLASS (code) == 'i')
1110 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1111 if (REG_NOTE_KIND (note) == REG_LABEL)
1115 if (insn == basic_block_end[b])
1119 /* All the tests passed. Consider the cfg well structured. */
1123 /* Build the control flow graph and set nr_edges.
1125 Instead of trying to build a cfg ourselves, we rely on flow to
1126 do it for us. Stamp out useless code (and bug) duplication.
1128 Return nonzero if an irregularity in the cfg is found which would
1129 prevent cross block scheduling. */
1132 build_control_flow (s_preds, s_succs, num_preds, num_succs)
1133 int_list_ptr *s_preds;
1134 int_list_ptr *s_succs;
1142 /* Count the number of edges in the cfg. */
1145 for (i = 0; i < n_basic_blocks; i++)
1147 nr_edges += num_succs[i];
1149 /* Unreachable loops with more than one basic block are detected
1150 during the DFS traversal in find_rgns.
1152 Unreachable loops with a single block are detected here. This
1153 test is redundant with the one in find_rgns, but it's much
1154 cheaper to go ahead and catch the trivial case here. */
1155 if (num_preds[i] == 0
1156 || (num_preds[i] == 1 && INT_LIST_VAL (s_preds[i]) == i))
1160 /* Account for entry/exit edges. */
1163 in_edges = (int *) xmalloc (n_basic_blocks * sizeof (int));
1164 out_edges = (int *) xmalloc (n_basic_blocks * sizeof (int));
1165 bzero ((char *) in_edges, n_basic_blocks * sizeof (int));
1166 bzero ((char *) out_edges, n_basic_blocks * sizeof (int));
1168 edge_table = (edge *) xmalloc ((nr_edges) * sizeof (edge));
1169 bzero ((char *) edge_table, ((nr_edges) * sizeof (edge)));
1172 for (i = 0; i < n_basic_blocks; i++)
1173 for (succ = s_succs[i]; succ; succ = succ->next)
1175 if (INT_LIST_VAL (succ) != EXIT_BLOCK)
1176 new_edge (i, INT_LIST_VAL (succ));
1179 /* increment by 1, since edge 0 is unused. */
1186 /* Record an edge in the control flow graph from SOURCE to TARGET.
1188 In theory, this is redundant with the s_succs computed above, but
1189 we have not converted all of haifa to use information from the
1193 new_edge (source, target)
1197 int curr_edge, fst_edge;
1199 /* check for duplicates */
1200 fst_edge = curr_edge = OUT_EDGES (source);
1203 if (FROM_BLOCK (curr_edge) == source
1204 && TO_BLOCK (curr_edge) == target)
1209 curr_edge = NEXT_OUT (curr_edge);
1211 if (fst_edge == curr_edge)
1217 FROM_BLOCK (e) = source;
1218 TO_BLOCK (e) = target;
1220 if (OUT_EDGES (source))
1222 next_edge = NEXT_OUT (OUT_EDGES (source));
1223 NEXT_OUT (OUT_EDGES (source)) = e;
1224 NEXT_OUT (e) = next_edge;
1228 OUT_EDGES (source) = e;
1232 if (IN_EDGES (target))
1234 next_edge = NEXT_IN (IN_EDGES (target));
1235 NEXT_IN (IN_EDGES (target)) = e;
1236 NEXT_IN (e) = next_edge;
1240 IN_EDGES (target) = e;
1246 /* BITSET macros for operations on the control flow graph. */
1248 /* Compute bitwise union of two bitsets. */
1249 #define BITSET_UNION(set1, set2, len) \
1250 do { register bitset tp = set1, sp = set2; \
1252 for (i = 0; i < len; i++) \
1253 *(tp++) |= *(sp++); } while (0)
1255 /* Compute bitwise intersection of two bitsets. */
1256 #define BITSET_INTER(set1, set2, len) \
1257 do { register bitset tp = set1, sp = set2; \
1259 for (i = 0; i < len; i++) \
1260 *(tp++) &= *(sp++); } while (0)
1262 /* Compute bitwise difference of two bitsets. */
1263 #define BITSET_DIFFER(set1, set2, len) \
1264 do { register bitset tp = set1, sp = set2; \
1266 for (i = 0; i < len; i++) \
1267 *(tp++) &= ~*(sp++); } while (0)
1269 /* Inverts every bit of bitset 'set' */
1270 #define BITSET_INVERT(set, len) \
1271 do { register bitset tmpset = set; \
1273 for (i = 0; i < len; i++, tmpset++) \
1274 *tmpset = ~*tmpset; } while (0)
1276 /* Turn on the index'th bit in bitset set. */
1277 #define BITSET_ADD(set, index, len) \
1279 if (index >= HOST_BITS_PER_WIDE_INT * len) \
1282 set[index/HOST_BITS_PER_WIDE_INT] |= \
1283 1 << (index % HOST_BITS_PER_WIDE_INT); \
1286 /* Turn off the index'th bit in set. */
1287 #define BITSET_REMOVE(set, index, len) \
1289 if (index >= HOST_BITS_PER_WIDE_INT * len) \
1292 set[index/HOST_BITS_PER_WIDE_INT] &= \
1293 ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \
1297 /* Check if the index'th bit in bitset set is on. */
1300 bitset_member (set, index, len)
1304 if (index >= HOST_BITS_PER_WIDE_INT * len)
1306 return (set[index / HOST_BITS_PER_WIDE_INT] &
1307 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0;
1311 /* Translate a bit-set SET to a list BL of the bit-set members. */
1314 extract_bitlst (set, len, bl)
1320 unsigned HOST_WIDE_INT word;
1322 /* bblst table space is reused in each call to extract_bitlst */
1323 bitlst_table_last = 0;
1325 bl->first_member = &bitlst_table[bitlst_table_last];
1328 for (i = 0; i < len; i++)
1331 offset = i * HOST_BITS_PER_WIDE_INT;
1332 for (j = 0; word; j++)
1336 bitlst_table[bitlst_table_last++] = offset;
1347 /* functions for the construction of regions */
1349 /* Print the regions, for debugging purposes. Callable from debugger. */
1356 fprintf (dump, "\n;; ------------ REGIONS ----------\n\n");
1357 for (rgn = 0; rgn < nr_regions; rgn++)
1359 fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn,
1360 rgn_table[rgn].rgn_nr_blocks);
1361 fprintf (dump, ";;\tbb/block: ");
1363 for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++)
1365 current_blocks = RGN_BLOCKS (rgn);
1367 if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb)))
1370 fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb));
1373 fprintf (dump, "\n\n");
1378 /* Build a single block region for each basic block in the function.
1379 This allows for using the same code for interblock and basic block
1383 find_single_block_region ()
1387 for (i = 0; i < n_basic_blocks; i++)
1389 rgn_bb_table[i] = i;
1390 RGN_NR_BLOCKS (i) = 1;
1392 CONTAINING_RGN (i) = i;
1393 BLOCK_TO_BB (i) = 0;
1395 nr_regions = n_basic_blocks;
1399 /* Update number of blocks and the estimate for number of insns
1400 in the region. Return 1 if the region is "too large" for interblock
1401 scheduling (compile time considerations), otherwise return 0. */
1404 too_large (block, num_bbs, num_insns)
1405 int block, *num_bbs, *num_insns;
1408 (*num_insns) += (INSN_LUID (basic_block_end[block]) -
1409 INSN_LUID (basic_block_head[block]));
1410 if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS))
1417 /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk]
1418 is still an inner loop. Put in max_hdr[blk] the header of the most inner
1419 loop containing blk. */
1420 #define UPDATE_LOOP_RELATIONS(blk, hdr) \
1422 if (max_hdr[blk] == -1) \
1423 max_hdr[blk] = hdr; \
1424 else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \
1425 RESET_BIT (inner, hdr); \
1426 else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \
1428 RESET_BIT (inner,max_hdr[blk]); \
1429 max_hdr[blk] = hdr; \
1434 /* Find regions for interblock scheduling.
1436 A region for scheduling can be:
1438 * A loop-free procedure, or
1440 * A reducible inner loop, or
1442 * A basic block not contained in any other region.
1445 ?!? In theory we could build other regions based on extended basic
1446 blocks or reverse extended basic blocks. Is it worth the trouble?
1448 Loop blocks that form a region are put into the region's block list
1449 in topological order.
1451 This procedure stores its results into the following global (ick) variables
1460 We use dominator relationships to avoid making regions out of non-reducible
1463 This procedure needs to be converted to work on pred/succ lists instead
1464 of edge tables. That would simplify it somewhat. */
1467 find_rgns (s_preds, s_succs, num_preds, num_succs, dom)
1468 int_list_ptr *s_preds;
1469 int_list_ptr *s_succs;
1474 int *max_hdr, *dfs_nr, *stack, *queue, *degree;
1476 int node, child, loop_head, i, head, tail;
1477 int count = 0, sp, idx = 0, current_edge = out_edges[0];
1478 int num_bbs, num_insns, unreachable;
1479 int too_large_failure;
1481 /* Note if an edge has been passed. */
1484 /* Note if a block is a natural loop header. */
1487 /* Note if a block is an natural inner loop header. */
1490 /* Note if a block is in the block queue. */
1493 /* Note if a block is in the block queue. */
1496 /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops
1497 and a mapping from block to its loop header (if the block is contained
1498 in a loop, else -1).
1500 Store results in HEADER, INNER, and MAX_HDR respectively, these will
1501 be used as inputs to the second traversal.
1503 STACK, SP and DFS_NR are only used during the first traversal. */
1505 /* Allocate and initialize variables for the first traversal. */
1506 max_hdr = (int *) alloca (n_basic_blocks * sizeof (int));
1507 dfs_nr = (int *) alloca (n_basic_blocks * sizeof (int));
1508 bzero ((char *) dfs_nr, n_basic_blocks * sizeof (int));
1509 stack = (int *) alloca (nr_edges * sizeof (int));
1511 inner = sbitmap_alloc (n_basic_blocks);
1512 sbitmap_ones (inner);
1514 header = sbitmap_alloc (n_basic_blocks);
1515 sbitmap_zero (header);
1517 passed = sbitmap_alloc (nr_edges);
1518 sbitmap_zero (passed);
1520 in_queue = sbitmap_alloc (n_basic_blocks);
1521 sbitmap_zero (in_queue);
1523 in_stack = sbitmap_alloc (n_basic_blocks);
1524 sbitmap_zero (in_stack);
1526 for (i = 0; i < n_basic_blocks; i++)
1529 /* DFS traversal to find inner loops in the cfg. */
1534 if (current_edge == 0 || TEST_BIT (passed, current_edge))
1536 /* We have reached a leaf node or a node that was already
1537 processed. Pop edges off the stack until we find
1538 an edge that has not yet been processed. */
1540 && (current_edge == 0 || TEST_BIT (passed, current_edge)))
1542 /* Pop entry off the stack. */
1543 current_edge = stack[sp--];
1544 node = FROM_BLOCK (current_edge);
1545 child = TO_BLOCK (current_edge);
1546 RESET_BIT (in_stack, child);
1547 if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
1548 UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
1549 current_edge = NEXT_OUT (current_edge);
1552 /* See if have finished the DFS tree traversal. */
1553 if (sp < 0 && TEST_BIT (passed, current_edge))
1556 /* Nope, continue the traversal with the popped node. */
1560 /* Process a node. */
1561 node = FROM_BLOCK (current_edge);
1562 child = TO_BLOCK (current_edge);
1563 SET_BIT (in_stack, node);
1564 dfs_nr[node] = ++count;
1566 /* If the successor is in the stack, then we've found a loop.
1567 Mark the loop, if it is not a natural loop, then it will
1568 be rejected during the second traversal. */
1569 if (TEST_BIT (in_stack, child))
1572 SET_BIT (header, child);
1573 UPDATE_LOOP_RELATIONS (node, child);
1574 SET_BIT (passed, current_edge);
1575 current_edge = NEXT_OUT (current_edge);
1579 /* If the child was already visited, then there is no need to visit
1580 it again. Just update the loop relationships and restart
1584 if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
1585 UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
1586 SET_BIT (passed, current_edge);
1587 current_edge = NEXT_OUT (current_edge);
1591 /* Push an entry on the stack and continue DFS traversal. */
1592 stack[++sp] = current_edge;
1593 SET_BIT (passed, current_edge);
1594 current_edge = OUT_EDGES (child);
1597 /* Another check for unreachable blocks. The earlier test in
1598 is_cfg_nonregular only finds unreachable blocks that do not
1601 The DFS traversal will mark every block that is reachable from
1602 the entry node by placing a nonzero value in dfs_nr. Thus if
1603 dfs_nr is zero for any block, then it must be unreachable. */
1605 for (i = 0; i < n_basic_blocks; i++)
1612 /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array
1613 to hold degree counts. */
1616 /* Compute the in-degree of every block in the graph */
1617 for (i = 0; i < n_basic_blocks; i++)
1618 degree[i] = num_preds[i];
1620 /* Do not perform region scheduling if there are any unreachable
1625 SET_BIT (header, 0);
1627 /* Second travsersal:find reducible inner loops and topologically sort
1628 block of each region. */
1630 queue = (int *) alloca (n_basic_blocks * sizeof (int));
1632 /* Find blocks which are inner loop headers. We still have non-reducible
1633 loops to consider at this point. */
1634 for (i = 0; i < n_basic_blocks; i++)
1636 if (TEST_BIT (header, i) && TEST_BIT (inner, i))
1641 /* Now check that the loop is reducible. We do this separate
1642 from finding inner loops so that we do not find a reducible
1643 loop which contains an inner non-reducible loop.
1645 A simple way to find reducible/natrual loops is to verify
1646 that each block in the loop is dominated by the loop
1649 If there exists a block that is not dominated by the loop
1650 header, then the block is reachable from outside the loop
1651 and thus the loop is not a natural loop. */
1652 for (j = 0; j < n_basic_blocks; j++)
1654 /* First identify blocks in the loop, except for the loop
1656 if (i == max_hdr[j] && i != j)
1658 /* Now verify that the block is dominated by the loop
1660 if (!TEST_BIT (dom[j], i))
1665 /* If we exited the loop early, then I is the header of a non
1666 reducible loop and we should quit processing it now. */
1667 if (j != n_basic_blocks)
1670 /* I is a header of an inner loop, or block 0 in a subroutine
1671 with no loops at all. */
1673 too_large_failure = 0;
1674 loop_head = max_hdr[i];
1676 /* Decrease degree of all I's successors for topological
1678 for (ps = s_succs[i]; ps; ps = ps->next)
1679 if (INT_LIST_VAL (ps) != EXIT_BLOCK
1680 && INT_LIST_VAL (ps) != ENTRY_BLOCK)
1681 --degree[INT_LIST_VAL(ps)];
1683 /* Estimate # insns, and count # blocks in the region. */
1685 num_insns = (INSN_LUID (basic_block_end[i])
1686 - INSN_LUID (basic_block_head[i]));
1689 /* Find all loop latches (blocks which back edges to the loop
1690 header) or all the leaf blocks in the cfg has no loops.
1692 Place those blocks into the queue. */
1695 for (j = 0; j < n_basic_blocks; j++)
1696 /* Leaf nodes have only a single successor which must
1698 if (num_succs[j] == 1
1699 && INT_LIST_VAL (s_succs[j]) == EXIT_BLOCK)
1702 SET_BIT (in_queue, j);
1704 if (too_large (j, &num_bbs, &num_insns))
1706 too_large_failure = 1;
1715 for (ps = s_preds[i]; ps; ps = ps->next)
1717 node = INT_LIST_VAL (ps);
1719 if (node == ENTRY_BLOCK || node == EXIT_BLOCK)
1722 if (max_hdr[node] == loop_head && node != i)
1724 /* This is a loop latch. */
1725 queue[++tail] = node;
1726 SET_BIT (in_queue, node);
1728 if (too_large (node, &num_bbs, &num_insns))
1730 too_large_failure = 1;
1738 /* Now add all the blocks in the loop to the queue.
1740 We know the loop is a natural loop; however the algorithm
1741 above will not always mark certain blocks as being in the
1750 The algorithm in the DFS traversal may not mark B & D as part
1751 of the loop (ie they will not have max_hdr set to A).
1753 We know they can not be loop latches (else they would have
1754 had max_hdr set since they'd have a backedge to a dominator
1755 block). So we don't need them on the initial queue.
1757 We know they are part of the loop because they are dominated
1758 by the loop header and can be reached by a backwards walk of
1759 the edges starting with nodes on the initial queue.
1761 It is safe and desirable to include those nodes in the
1762 loop/scheduling region. To do so we would need to decrease
1763 the degree of a node if it is the target of a backedge
1764 within the loop itself as the node is placed in the queue.
1766 We do not do this because I'm not sure that the actual
1767 scheduling code will properly handle this case. ?!? */
1769 while (head < tail && !too_large_failure)
1772 child = queue[++head];
1774 for (ps = s_preds[child]; ps; ps = ps->next)
1776 node = INT_LIST_VAL (ps);
1778 /* See discussion above about nodes not marked as in
1779 this loop during the initial DFS traversal. */
1780 if (node == ENTRY_BLOCK || node == EXIT_BLOCK
1781 || max_hdr[node] != loop_head)
1786 else if (!TEST_BIT (in_queue, node) && node != i)
1788 queue[++tail] = node;
1789 SET_BIT (in_queue, node);
1791 if (too_large (node, &num_bbs, &num_insns))
1793 too_large_failure = 1;
1800 if (tail >= 0 && !too_large_failure)
1802 /* Place the loop header into list of region blocks. */
1804 rgn_bb_table[idx] = i;
1805 RGN_NR_BLOCKS (nr_regions) = num_bbs;
1806 RGN_BLOCKS (nr_regions) = idx++;
1807 CONTAINING_RGN (i) = nr_regions;
1808 BLOCK_TO_BB (i) = count = 0;
1810 /* Remove blocks from queue[] when their in degree becomes
1811 zero. Repeat until no blocks are left on the list. This
1812 produces a topological list of blocks in the region. */
1819 child = queue[head];
1820 if (degree[child] == 0)
1823 rgn_bb_table[idx++] = child;
1824 BLOCK_TO_BB (child) = ++count;
1825 CONTAINING_RGN (child) = nr_regions;
1826 queue[head] = queue[tail--];
1828 for (ps = s_succs[child]; ps; ps = ps->next)
1829 if (INT_LIST_VAL (ps) != ENTRY_BLOCK
1830 && INT_LIST_VAL (ps) != EXIT_BLOCK)
1831 --degree[INT_LIST_VAL (ps)];
1842 /* Any block that did not end up in a region is placed into a region
1844 for (i = 0; i < n_basic_blocks; i++)
1847 rgn_bb_table[idx] = i;
1848 RGN_NR_BLOCKS (nr_regions) = 1;
1849 RGN_BLOCKS (nr_regions) = idx++;
1850 CONTAINING_RGN (i) = nr_regions++;
1851 BLOCK_TO_BB (i) = 0;
1862 /* functions for regions scheduling information */
1864 /* Compute dominators, probability, and potential-split-edges of bb.
1865 Assume that these values were already computed for bb's predecessors. */
1868 compute_dom_prob_ps (bb)
1871 int nxt_in_edge, fst_in_edge, pred;
1872 int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges;
1875 if (IS_RGN_ENTRY (bb))
1877 BITSET_ADD (dom[bb], 0, bbset_size);
1882 fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb));
1884 /* intialize dom[bb] to '111..1' */
1885 BITSET_INVERT (dom[bb], bbset_size);
1889 pred = FROM_BLOCK (nxt_in_edge);
1890 BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size);
1892 BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)],
1895 BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size);
1898 nr_rgn_out_edges = 0;
1899 fst_out_edge = OUT_EDGES (pred);
1900 nxt_out_edge = NEXT_OUT (fst_out_edge);
1901 BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)],
1904 BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size);
1906 /* the successor doesn't belong the region? */
1907 if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) !=
1908 CONTAINING_RGN (BB_TO_BLOCK (bb)))
1911 while (fst_out_edge != nxt_out_edge)
1914 /* the successor doesn't belong the region? */
1915 if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) !=
1916 CONTAINING_RGN (BB_TO_BLOCK (bb)))
1918 BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size);
1919 nxt_out_edge = NEXT_OUT (nxt_out_edge);
1923 /* now nr_rgn_out_edges is the number of region-exit edges from pred,
1924 and nr_out_edges will be the number of pred out edges not leaving
1926 nr_out_edges -= nr_rgn_out_edges;
1927 if (nr_rgn_out_edges > 0)
1928 prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges;
1930 prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges;
1931 nxt_in_edge = NEXT_IN (nxt_in_edge);
1933 while (fst_in_edge != nxt_in_edge);
1935 BITSET_ADD (dom[bb], bb, bbset_size);
1936 BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size);
1938 if (sched_verbose >= 2)
1939 fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb]));
1940 } /* compute_dom_prob_ps */
1942 /* functions for target info */
1944 /* Compute in BL the list of split-edges of bb_src relatively to bb_trg.
1945 Note that bb_trg dominates bb_src. */
1948 split_edges (bb_src, bb_trg, bl)
1953 int es = edgeset_size;
1954 edgeset src = (edgeset) alloca (es * sizeof (HOST_WIDE_INT));
1957 src[es] = (pot_split[bb_src])[es];
1958 BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size);
1959 extract_bitlst (src, edgeset_size, bl);
1963 /* Find the valid candidate-source-blocks for the target block TRG, compute
1964 their probability, and check if they are speculative or not.
1965 For speculative sources, compute their update-blocks and split-blocks. */
1968 compute_trg_info (trg)
1971 register candidate *sp;
1973 int check_block, update_idx;
1974 int i, j, k, fst_edge, nxt_edge;
1976 /* define some of the fields for the target bb as well */
1977 sp = candidate_table + trg;
1979 sp->is_speculative = 0;
1982 for (i = trg + 1; i < current_nr_blocks; i++)
1984 sp = candidate_table + i;
1986 sp->is_valid = IS_DOMINATED (i, trg);
1989 sp->src_prob = GET_SRC_PROB (i, trg);
1990 sp->is_valid = (sp->src_prob >= MIN_PROBABILITY);
1995 split_edges (i, trg, &el);
1996 sp->is_speculative = (el.nr_members) ? 1 : 0;
1997 if (sp->is_speculative && !flag_schedule_speculative)
2003 sp->split_bbs.first_member = &bblst_table[bblst_last];
2004 sp->split_bbs.nr_members = el.nr_members;
2005 for (j = 0; j < el.nr_members; bblst_last++, j++)
2006 bblst_table[bblst_last] =
2007 TO_BLOCK (rgn_edges[el.first_member[j]]);
2008 sp->update_bbs.first_member = &bblst_table[bblst_last];
2010 for (j = 0; j < el.nr_members; j++)
2012 check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]);
2013 fst_edge = nxt_edge = OUT_EDGES (check_block);
2016 for (k = 0; k < el.nr_members; k++)
2017 if (EDGE_TO_BIT (nxt_edge) == el.first_member[k])
2020 if (k >= el.nr_members)
2022 bblst_table[bblst_last++] = TO_BLOCK (nxt_edge);
2026 nxt_edge = NEXT_OUT (nxt_edge);
2028 while (fst_edge != nxt_edge);
2030 sp->update_bbs.nr_members = update_idx;
2035 sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0;
2037 sp->is_speculative = 0;
2041 } /* compute_trg_info */
2044 /* Print candidates info, for debugging purposes. Callable from debugger. */
2050 if (!candidate_table[i].is_valid)
2053 if (candidate_table[i].is_speculative)
2056 fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i);
2058 fprintf (dump, "split path: ");
2059 for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++)
2061 int b = candidate_table[i].split_bbs.first_member[j];
2063 fprintf (dump, " %d ", b);
2065 fprintf (dump, "\n");
2067 fprintf (dump, "update path: ");
2068 for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++)
2070 int b = candidate_table[i].update_bbs.first_member[j];
2072 fprintf (dump, " %d ", b);
2074 fprintf (dump, "\n");
2078 fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i));
2083 /* Print candidates info, for debugging purposes. Callable from debugger. */
2086 debug_candidates (trg)
2091 fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n",
2092 BB_TO_BLOCK (trg), trg);
2093 for (i = trg + 1; i < current_nr_blocks; i++)
2094 debug_candidate (i);
2098 /* functions for speculative scheduing */
2100 /* Return 0 if x is a set of a register alive in the beginning of one
2101 of the split-blocks of src, otherwise return 1. */
2104 check_live_1 (src, x)
2110 register rtx reg = SET_DEST (x);
2115 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
2116 || GET_CODE (reg) == SIGN_EXTRACT
2117 || GET_CODE (reg) == STRICT_LOW_PART)
2118 reg = XEXP (reg, 0);
2120 if (GET_CODE (reg) == PARALLEL
2121 && GET_MODE (reg) == BLKmode)
2124 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2125 if (check_live_1 (src, XVECEXP (reg, 0, i)))
2130 if (GET_CODE (reg) != REG)
2133 regno = REGNO (reg);
2135 if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2137 /* Global registers are assumed live */
2142 if (regno < FIRST_PSEUDO_REGISTER)
2144 /* check for hard registers */
2145 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2148 for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
2150 int b = candidate_table[src].split_bbs.first_member[i];
2152 if (REGNO_REG_SET_P (basic_block_live_at_start[b], regno + j))
2161 /* check for psuedo registers */
2162 for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
2164 int b = candidate_table[src].split_bbs.first_member[i];
2166 if (REGNO_REG_SET_P (basic_block_live_at_start[b], regno))
2178 /* If x is a set of a register R, mark that R is alive in the beginning
2179 of every update-block of src. */
2182 update_live_1 (src, x)
2188 register rtx reg = SET_DEST (x);
2193 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
2194 || GET_CODE (reg) == SIGN_EXTRACT
2195 || GET_CODE (reg) == STRICT_LOW_PART)
2196 reg = XEXP (reg, 0);
2198 if (GET_CODE (reg) == PARALLEL
2199 && GET_MODE (reg) == BLKmode)
2202 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2203 update_live_1 (src, XVECEXP (reg, 0, i));
2207 if (GET_CODE (reg) != REG)
2210 /* Global registers are always live, so the code below does not apply
2213 regno = REGNO (reg);
2215 if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno])
2217 if (regno < FIRST_PSEUDO_REGISTER)
2219 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2222 for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
2224 int b = candidate_table[src].update_bbs.first_member[i];
2226 SET_REGNO_REG_SET (basic_block_live_at_start[b], regno + j);
2232 for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
2234 int b = candidate_table[src].update_bbs.first_member[i];
2236 SET_REGNO_REG_SET (basic_block_live_at_start[b], regno);
2243 /* Return 1 if insn can be speculatively moved from block src to trg,
2244 otherwise return 0. Called before first insertion of insn to
2245 ready-list or before the scheduling. */
2248 check_live (insn, src)
2252 /* find the registers set by instruction */
2253 if (GET_CODE (PATTERN (insn)) == SET
2254 || GET_CODE (PATTERN (insn)) == CLOBBER)
2255 return check_live_1 (src, PATTERN (insn));
2256 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
2259 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
2260 if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
2261 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
2262 && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j)))
2272 /* Update the live registers info after insn was moved speculatively from
2273 block src to trg. */
2276 update_live (insn, src)
2280 /* find the registers set by instruction */
2281 if (GET_CODE (PATTERN (insn)) == SET
2282 || GET_CODE (PATTERN (insn)) == CLOBBER)
2283 update_live_1 (src, PATTERN (insn));
2284 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
2287 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
2288 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
2289 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
2290 update_live_1 (src, XVECEXP (PATTERN (insn), 0, j));
2294 /* Exception Free Loads:
2296 We define five classes of speculative loads: IFREE, IRISKY,
2297 PFREE, PRISKY, and MFREE.
2299 IFREE loads are loads that are proved to be exception-free, just
2300 by examining the load insn. Examples for such loads are loads
2301 from TOC and loads of global data.
2303 IRISKY loads are loads that are proved to be exception-risky,
2304 just by examining the load insn. Examples for such loads are
2305 volatile loads and loads from shared memory.
2307 PFREE loads are loads for which we can prove, by examining other
2308 insns, that they are exception-free. Currently, this class consists
2309 of loads for which we are able to find a "similar load", either in
2310 the target block, or, if only one split-block exists, in that split
2311 block. Load2 is similar to load1 if both have same single base
2312 register. We identify only part of the similar loads, by finding
2313 an insn upon which both load1 and load2 have a DEF-USE dependence.
2315 PRISKY loads are loads for which we can prove, by examining other
2316 insns, that they are exception-risky. Currently we have two proofs for
2317 such loads. The first proof detects loads that are probably guarded by a
2318 test on the memory address. This proof is based on the
2319 backward and forward data dependence information for the region.
2320 Let load-insn be the examined load.
2321 Load-insn is PRISKY iff ALL the following hold:
2323 - insn1 is not in the same block as load-insn
2324 - there is a DEF-USE dependence chain (insn1, ..., load-insn)
2325 - test-insn is either a compare or a branch, not in the same block as load-insn
2326 - load-insn is reachable from test-insn
2327 - there is a DEF-USE dependence chain (insn1, ..., test-insn)
2329 This proof might fail when the compare and the load are fed
2330 by an insn not in the region. To solve this, we will add to this
2331 group all loads that have no input DEF-USE dependence.
2333 The second proof detects loads that are directly or indirectly
2334 fed by a speculative load. This proof is affected by the
2335 scheduling process. We will use the flag fed_by_spec_load.
2336 Initially, all insns have this flag reset. After a speculative
2337 motion of an insn, if insn is either a load, or marked as
2338 fed_by_spec_load, we will also mark as fed_by_spec_load every
2339 insn1 for which a DEF-USE dependence (insn, insn1) exists. A
2340 load which is fed_by_spec_load is also PRISKY.
2342 MFREE (maybe-free) loads are all the remaining loads. They may be
2343 exception-free, but we cannot prove it.
2345 Now, all loads in IFREE and PFREE classes are considered
2346 exception-free, while all loads in IRISKY and PRISKY classes are
2347 considered exception-risky. As for loads in the MFREE class,
2348 these are considered either exception-free or exception-risky,
2349 depending on whether we are pessimistic or optimistic. We have
2350 to take the pessimistic approach to assure the safety of
2351 speculative scheduling, but we can take the optimistic approach
2352 by invoking the -fsched_spec_load_dangerous option. */
2354 enum INSN_TRAP_CLASS
2356 TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2,
2357 PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5
2360 #define WORST_CLASS(class1, class2) \
2361 ((class1 > class2) ? class1 : class2)
2363 /* Indexed by INSN_UID, and set if there's DEF-USE dependence between */
2364 /* some speculatively moved load insn and this one. */
2365 char *fed_by_spec_load;
2368 /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */
2369 #define IS_REACHABLE(bb_from, bb_to) \
2371 || IS_RGN_ENTRY (bb_from) \
2372 || (bitset_member (ancestor_edges[bb_to], \
2373 EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \
2375 #define FED_BY_SPEC_LOAD(insn) (fed_by_spec_load[INSN_UID (insn)])
2376 #define IS_LOAD_INSN(insn) (is_load_insn[INSN_UID (insn)])
2378 /* Non-zero iff the address is comprised from at most 1 register */
2379 #define CONST_BASED_ADDRESS_P(x) \
2380 (GET_CODE (x) == REG \
2381 || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \
2382 || (GET_CODE (x) == LO_SUM)) \
2383 && (GET_CODE (XEXP (x, 0)) == CONST_INT \
2384 || GET_CODE (XEXP (x, 1)) == CONST_INT)))
2386 /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */
2389 set_spec_fed (load_insn)
2394 for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1))
2395 if (GET_MODE (link) == VOIDmode)
2396 FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1;
2397 } /* set_spec_fed */
2399 /* On the path from the insn to load_insn_bb, find a conditional branch */
2400 /* depending on insn, that guards the speculative load. */
2403 find_conditional_protection (insn, load_insn_bb)
2409 /* iterate through DEF-USE forward dependences */
2410 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
2412 rtx next = XEXP (link, 0);
2413 if ((CONTAINING_RGN (INSN_BLOCK (next)) ==
2414 CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb)))
2415 && IS_REACHABLE (INSN_BB (next), load_insn_bb)
2416 && load_insn_bb != INSN_BB (next)
2417 && GET_MODE (link) == VOIDmode
2418 && (GET_CODE (next) == JUMP_INSN
2419 || find_conditional_protection (next, load_insn_bb)))
2423 } /* find_conditional_protection */
2425 /* Returns 1 if the same insn1 that participates in the computation
2426 of load_insn's address is feeding a conditional branch that is
2427 guarding on load_insn. This is true if we find a the two DEF-USE
2429 insn1 -> ... -> conditional-branch
2430 insn1 -> ... -> load_insn,
2431 and if a flow path exist:
2432 insn1 -> ... -> conditional-branch -> ... -> load_insn,
2433 and if insn1 is on the path
2434 region-entry -> ... -> bb_trg -> ... load_insn.
2436 Locate insn1 by climbing on LOG_LINKS from load_insn.
2437 Locate the branch by following INSN_DEPEND from insn1. */
2440 is_conditionally_protected (load_insn, bb_src, bb_trg)
2446 for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1))
2448 rtx insn1 = XEXP (link, 0);
2450 /* must be a DEF-USE dependence upon non-branch */
2451 if (GET_MODE (link) != VOIDmode
2452 || GET_CODE (insn1) == JUMP_INSN)
2455 /* must exist a path: region-entry -> ... -> bb_trg -> ... load_insn */
2456 if (INSN_BB (insn1) == bb_src
2457 || (CONTAINING_RGN (INSN_BLOCK (insn1))
2458 != CONTAINING_RGN (BB_TO_BLOCK (bb_src)))
2459 || (!IS_REACHABLE (bb_trg, INSN_BB (insn1))
2460 && !IS_REACHABLE (INSN_BB (insn1), bb_trg)))
2463 /* now search for the conditional-branch */
2464 if (find_conditional_protection (insn1, bb_src))
2467 /* recursive step: search another insn1, "above" current insn1. */
2468 return is_conditionally_protected (insn1, bb_src, bb_trg);
2471 /* the chain does not exsist */
2473 } /* is_conditionally_protected */
2475 /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence
2476 load_insn can move speculatively from bb_src to bb_trg. All the
2477 following must hold:
2479 (1) both loads have 1 base register (PFREE_CANDIDATEs).
2480 (2) load_insn and load1 have a def-use dependence upon
2481 the same insn 'insn1'.
2482 (3) either load2 is in bb_trg, or:
2483 - there's only one split-block, and
2484 - load1 is on the escape path, and
2486 From all these we can conclude that the two loads access memory
2487 addresses that differ at most by a constant, and hence if moving
2488 load_insn would cause an exception, it would have been caused by
2492 is_pfree (load_insn, bb_src, bb_trg)
2497 register candidate *candp = candidate_table + bb_src;
2499 if (candp->split_bbs.nr_members != 1)
2500 /* must have exactly one escape block */
2503 for (back_link = LOG_LINKS (load_insn);
2504 back_link; back_link = XEXP (back_link, 1))
2506 rtx insn1 = XEXP (back_link, 0);
2508 if (GET_MODE (back_link) == VOIDmode)
2510 /* found a DEF-USE dependence (insn1, load_insn) */
2513 for (fore_link = INSN_DEPEND (insn1);
2514 fore_link; fore_link = XEXP (fore_link, 1))
2516 rtx insn2 = XEXP (fore_link, 0);
2517 if (GET_MODE (fore_link) == VOIDmode)
2519 /* found a DEF-USE dependence (insn1, insn2) */
2520 if (haifa_classify_insn (insn2) != PFREE_CANDIDATE)
2521 /* insn2 not guaranteed to be a 1 base reg load */
2524 if (INSN_BB (insn2) == bb_trg)
2525 /* insn2 is the similar load, in the target block */
2528 if (*(candp->split_bbs.first_member) == INSN_BLOCK (insn2))
2529 /* insn2 is a similar load, in a split-block */
2536 /* couldn't find a similar load */
2540 /* Returns a class that insn with GET_DEST(insn)=x may belong to,
2541 as found by analyzing insn's expression. */
2544 may_trap_exp (x, is_store)
2552 code = GET_CODE (x);
2562 /* The insn uses memory */
2563 /* a volatile load */
2564 if (MEM_VOLATILE_P (x))
2566 /* an exception-free load */
2567 if (!may_trap_p (x))
2569 /* a load with 1 base register, to be further checked */
2570 if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))
2571 return PFREE_CANDIDATE;
2572 /* no info on the load, to be further checked */
2573 return PRISKY_CANDIDATE;
2578 int i, insn_class = TRAP_FREE;
2580 /* neither store nor load, check if it may cause a trap */
2583 /* recursive step: walk the insn... */
2584 fmt = GET_RTX_FORMAT (code);
2585 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2589 int tmp_class = may_trap_exp (XEXP (x, i), is_store);
2590 insn_class = WORST_CLASS (insn_class, tmp_class);
2592 else if (fmt[i] == 'E')
2595 for (j = 0; j < XVECLEN (x, i); j++)
2597 int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);
2598 insn_class = WORST_CLASS (insn_class, tmp_class);
2599 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2603 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2608 } /* may_trap_exp */
2611 /* Classifies insn for the purpose of verifying that it can be
2612 moved speculatively, by examining it's patterns, returning:
2613 TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).
2614 TRAP_FREE: non-load insn.
2615 IFREE: load from a globaly safe location.
2616 IRISKY: volatile load.
2617 PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for
2618 being either PFREE or PRISKY. */
2621 haifa_classify_insn (insn)
2624 rtx pat = PATTERN (insn);
2625 int tmp_class = TRAP_FREE;
2626 int insn_class = TRAP_FREE;
2629 if (GET_CODE (pat) == PARALLEL)
2631 int i, len = XVECLEN (pat, 0);
2633 for (i = len - 1; i >= 0; i--)
2635 code = GET_CODE (XVECEXP (pat, 0, i));
2639 /* test if it is a 'store' */
2640 tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1);
2643 /* test if it is a store */
2644 tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1);
2645 if (tmp_class == TRAP_RISKY)
2647 /* test if it is a load */
2649 WORST_CLASS (tmp_class,
2650 may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0));
2653 tmp_class = TRAP_RISKY;
2657 insn_class = WORST_CLASS (insn_class, tmp_class);
2658 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2664 code = GET_CODE (pat);
2668 /* test if it is a 'store' */
2669 tmp_class = may_trap_exp (XEXP (pat, 0), 1);
2672 /* test if it is a store */
2673 tmp_class = may_trap_exp (SET_DEST (pat), 1);
2674 if (tmp_class == TRAP_RISKY)
2676 /* test if it is a load */
2678 WORST_CLASS (tmp_class,
2679 may_trap_exp (SET_SRC (pat), 0));
2682 tmp_class = TRAP_RISKY;
2686 insn_class = tmp_class;
2691 } /* haifa_classify_insn */
2693 /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by
2694 a load moved speculatively, or if load_insn is protected by
2695 a compare on load_insn's address). */
2698 is_prisky (load_insn, bb_src, bb_trg)
2702 if (FED_BY_SPEC_LOAD (load_insn))
2705 if (LOG_LINKS (load_insn) == NULL)
2706 /* dependence may 'hide' out of the region. */
2709 if (is_conditionally_protected (load_insn, bb_src, bb_trg))
2715 /* Insn is a candidate to be moved speculatively from bb_src to bb_trg.
2716 Return 1 if insn is exception-free (and the motion is valid)
2720 is_exception_free (insn, bb_src, bb_trg)
2724 int insn_class = haifa_classify_insn (insn);
2726 /* handle non-load insns */
2737 if (!flag_schedule_speculative_load)
2739 IS_LOAD_INSN (insn) = 1;
2746 case PFREE_CANDIDATE:
2747 if (is_pfree (insn, bb_src, bb_trg))
2749 /* don't 'break' here: PFREE-candidate is also PRISKY-candidate */
2750 case PRISKY_CANDIDATE:
2751 if (!flag_schedule_speculative_load_dangerous
2752 || is_prisky (insn, bb_src, bb_trg))
2758 return flag_schedule_speculative_load_dangerous;
2759 } /* is_exception_free */
2762 /* Process an insn's memory dependencies. There are four kinds of
2765 (0) read dependence: read follows read
2766 (1) true dependence: read follows write
2767 (2) anti dependence: write follows read
2768 (3) output dependence: write follows write
2770 We are careful to build only dependencies which actually exist, and
2771 use transitivity to avoid building too many links. */
2773 /* Return the INSN_LIST containing INSN in LIST, or NULL
2774 if LIST does not contain INSN. */
2776 HAIFA_INLINE static rtx
2777 find_insn_list (insn, list)
2783 if (XEXP (list, 0) == insn)
2785 list = XEXP (list, 1);
2791 /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 otherwise. */
2793 HAIFA_INLINE static char
2794 find_insn_mem_list (insn, x, list, list1)
2800 if (XEXP (list, 0) == insn
2801 && XEXP (list1, 0) == x)
2803 list = XEXP (list, 1);
2804 list1 = XEXP (list1, 1);
2810 /* Compute the function units used by INSN. This caches the value
2811 returned by function_units_used. A function unit is encoded as the
2812 unit number if the value is non-negative and the compliment of a
2813 mask if the value is negative. A function unit index is the
2814 non-negative encoding. */
2816 HAIFA_INLINE static int
2820 register int unit = INSN_UNIT (insn);
2824 recog_memoized (insn);
2826 /* A USE insn, or something else we don't need to understand.
2827 We can't pass these directly to function_units_used because it will
2828 trigger a fatal error for unrecognizable insns. */
2829 if (INSN_CODE (insn) < 0)
2833 unit = function_units_used (insn);
2834 /* Increment non-negative values so we can cache zero. */
2838 /* We only cache 16 bits of the result, so if the value is out of
2839 range, don't cache it. */
2840 if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
2842 || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
2843 INSN_UNIT (insn) = unit;
2845 return (unit > 0 ? unit - 1 : unit);
2848 /* Compute the blockage range for executing INSN on UNIT. This caches
2849 the value returned by the blockage_range_function for the unit.
2850 These values are encoded in an int where the upper half gives the
2851 minimum value and the lower half gives the maximum value. */
2853 HAIFA_INLINE static unsigned int
2854 blockage_range (unit, insn)
2858 unsigned int blockage = INSN_BLOCKAGE (insn);
2861 if (UNIT_BLOCKED (blockage) != unit + 1)
2863 range = function_units[unit].blockage_range_function (insn);
2864 /* We only cache the blockage range for one unit and then only if
2866 if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
2867 INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
2870 range = BLOCKAGE_RANGE (blockage);
2875 /* A vector indexed by function unit instance giving the last insn to use
2876 the unit. The value of the function unit instance index for unit U
2877 instance I is (U + I * FUNCTION_UNITS_SIZE). */
2878 static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
2880 /* A vector indexed by function unit instance giving the minimum time when
2881 the unit will unblock based on the maximum blockage cost. */
2882 static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
2884 /* A vector indexed by function unit number giving the number of insns
2885 that remain to use the unit. */
2886 static int unit_n_insns[FUNCTION_UNITS_SIZE];
2888 /* Reset the function unit state to the null state. */
2893 bzero ((char *) unit_last_insn, sizeof (unit_last_insn));
2894 bzero ((char *) unit_tick, sizeof (unit_tick));
2895 bzero ((char *) unit_n_insns, sizeof (unit_n_insns));
2898 /* Return the issue-delay of an insn */
2900 HAIFA_INLINE static int
2901 insn_issue_delay (insn)
2905 int unit = insn_unit (insn);
2907 /* efficiency note: in fact, we are working 'hard' to compute a
2908 value that was available in md file, and is not available in
2909 function_units[] structure. It would be nice to have this
2910 value there, too. */
2913 if (function_units[unit].blockage_range_function &&
2914 function_units[unit].blockage_function)
2915 delay = function_units[unit].blockage_function (insn, insn);
2918 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
2919 if ((unit & 1) != 0 && function_units[i].blockage_range_function
2920 && function_units[i].blockage_function)
2921 delay = MAX (delay, function_units[i].blockage_function (insn, insn));
2926 /* Return the actual hazard cost of executing INSN on the unit UNIT,
2927 instance INSTANCE at time CLOCK if the previous actual hazard cost
2930 HAIFA_INLINE static int
2931 actual_hazard_this_instance (unit, instance, insn, clock, cost)
2932 int unit, instance, clock, cost;
2935 int tick = unit_tick[instance]; /* issue time of the last issued insn */
2937 if (tick - clock > cost)
2939 /* The scheduler is operating forward, so unit's last insn is the
2940 executing insn and INSN is the candidate insn. We want a
2941 more exact measure of the blockage if we execute INSN at CLOCK
2942 given when we committed the execution of the unit's last insn.
2944 The blockage value is given by either the unit's max blockage
2945 constant, blockage range function, or blockage function. Use
2946 the most exact form for the given unit. */
2948 if (function_units[unit].blockage_range_function)
2950 if (function_units[unit].blockage_function)
2951 tick += (function_units[unit].blockage_function
2952 (unit_last_insn[instance], insn)
2953 - function_units[unit].max_blockage);
2955 tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
2956 - function_units[unit].max_blockage);
2958 if (tick - clock > cost)
2959 cost = tick - clock;
2964 /* Record INSN as having begun execution on the units encoded by UNIT at
2967 HAIFA_INLINE static void
2968 schedule_unit (unit, insn, clock)
2976 int instance = unit;
2977 #if MAX_MULTIPLICITY > 1
2978 /* Find the first free instance of the function unit and use that
2979 one. We assume that one is free. */
2980 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
2982 if (!actual_hazard_this_instance (unit, instance, insn, clock, 0))
2984 instance += FUNCTION_UNITS_SIZE;
2987 unit_last_insn[instance] = insn;
2988 unit_tick[instance] = (clock + function_units[unit].max_blockage);
2991 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
2992 if ((unit & 1) != 0)
2993 schedule_unit (i, insn, clock);
2996 /* Return the actual hazard cost of executing INSN on the units encoded by
2997 UNIT at time CLOCK if the previous actual hazard cost was COST. */
2999 HAIFA_INLINE static int
3000 actual_hazard (unit, insn, clock, cost)
3001 int unit, clock, cost;
3008 /* Find the instance of the function unit with the minimum hazard. */
3009 int instance = unit;
3010 int best_cost = actual_hazard_this_instance (unit, instance, insn,
3014 #if MAX_MULTIPLICITY > 1
3015 if (best_cost > cost)
3017 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
3019 instance += FUNCTION_UNITS_SIZE;
3020 this_cost = actual_hazard_this_instance (unit, instance, insn,
3022 if (this_cost < best_cost)
3024 best_cost = this_cost;
3025 if (this_cost <= cost)
3031 cost = MAX (cost, best_cost);
3034 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
3035 if ((unit & 1) != 0)
3036 cost = actual_hazard (i, insn, clock, cost);
3041 /* Return the potential hazard cost of executing an instruction on the
3042 units encoded by UNIT if the previous potential hazard cost was COST.
3043 An insn with a large blockage time is chosen in preference to one
3044 with a smaller time; an insn that uses a unit that is more likely
3045 to be used is chosen in preference to one with a unit that is less
3046 used. We are trying to minimize a subsequent actual hazard. */
3048 HAIFA_INLINE static int
3049 potential_hazard (unit, insn, cost)
3054 unsigned int minb, maxb;
3058 minb = maxb = function_units[unit].max_blockage;
3061 if (function_units[unit].blockage_range_function)
3063 maxb = minb = blockage_range (unit, insn);
3064 maxb = MAX_BLOCKAGE_COST (maxb);
3065 minb = MIN_BLOCKAGE_COST (minb);
3070 /* Make the number of instructions left dominate. Make the
3071 minimum delay dominate the maximum delay. If all these
3072 are the same, use the unit number to add an arbitrary
3073 ordering. Other terms can be added. */
3074 ncost = minb * 0x40 + maxb;
3075 ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
3082 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
3083 if ((unit & 1) != 0)
3084 cost = potential_hazard (i, insn, cost);
3089 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
3090 This is the number of cycles between instruction issue and
3091 instruction results. */
3093 HAIFA_INLINE static int
3094 insn_cost (insn, link, used)
3095 rtx insn, link, used;
3097 register int cost = INSN_COST (insn);
3101 recog_memoized (insn);
3103 /* A USE insn, or something else we don't need to understand.
3104 We can't pass these directly to result_ready_cost because it will
3105 trigger a fatal error for unrecognizable insns. */
3106 if (INSN_CODE (insn) < 0)
3108 INSN_COST (insn) = 1;
3113 cost = result_ready_cost (insn);
3118 INSN_COST (insn) = cost;
3122 /* in this case estimate cost without caring how insn is used. */
3123 if (link == 0 && used == 0)
3126 /* A USE insn should never require the value used to be computed. This
3127 allows the computation of a function's result and parameter values to
3128 overlap the return and call. */
3129 recog_memoized (used);
3130 if (INSN_CODE (used) < 0)
3131 LINK_COST_FREE (link) = 1;
3133 /* If some dependencies vary the cost, compute the adjustment. Most
3134 commonly, the adjustment is complete: either the cost is ignored
3135 (in the case of an output- or anti-dependence), or the cost is
3136 unchanged. These values are cached in the link as LINK_COST_FREE
3137 and LINK_COST_ZERO. */
3139 if (LINK_COST_FREE (link))
3142 else if (!LINK_COST_ZERO (link))
3146 ADJUST_COST (used, link, insn, ncost);
3148 LINK_COST_FREE (link) = ncost = 1;
3150 LINK_COST_ZERO (link) = 1;
3157 /* Compute the priority number for INSN. */
3166 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
3169 if ((this_priority = INSN_PRIORITY (insn)) == 0)
3171 if (INSN_DEPEND (insn) == 0)
3172 this_priority = insn_cost (insn, 0, 0);
3174 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
3179 if (RTX_INTEGRATED_P (link))
3182 next = XEXP (link, 0);
3184 /* critical path is meaningful in block boundaries only */
3185 if (INSN_BLOCK (next) != INSN_BLOCK (insn))
3188 next_priority = insn_cost (insn, link, next) + priority (next);
3189 if (next_priority > this_priority)
3190 this_priority = next_priority;
3192 INSN_PRIORITY (insn) = this_priority;
3194 return this_priority;
3198 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
3199 them to the unused_*_list variables, so that they can be reused. */
3202 free_pending_lists ()
3204 if (current_nr_blocks <= 1)
3206 free_list (&pending_read_insns, &unused_insn_list);
3207 free_list (&pending_write_insns, &unused_insn_list);
3208 free_list (&pending_read_mems, &unused_expr_list);
3209 free_list (&pending_write_mems, &unused_expr_list);
3213 /* interblock scheduling */
3216 for (bb = 0; bb < current_nr_blocks; bb++)
3218 free_list (&bb_pending_read_insns[bb], &unused_insn_list);
3219 free_list (&bb_pending_write_insns[bb], &unused_insn_list);
3220 free_list (&bb_pending_read_mems[bb], &unused_expr_list);
3221 free_list (&bb_pending_write_mems[bb], &unused_expr_list);
3226 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
3227 The MEM is a memory reference contained within INSN, which we are saving
3228 so that we can do memory aliasing on it. */
3231 add_insn_mem_dependence (insn_list, mem_list, insn, mem)
3232 rtx *insn_list, *mem_list, insn, mem;
3236 link = alloc_INSN_LIST (insn, *insn_list);
3239 link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list);
3242 pending_lists_length++;
3246 /* Make a dependency between every memory reference on the pending lists
3247 and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush
3251 flush_pending_lists (insn, only_write)
3258 while (pending_read_insns && ! only_write)
3260 add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI);
3262 link = pending_read_insns;
3263 pending_read_insns = XEXP (pending_read_insns, 1);
3264 XEXP (link, 1) = unused_insn_list;
3265 unused_insn_list = link;
3267 link = pending_read_mems;
3268 pending_read_mems = XEXP (pending_read_mems, 1);
3269 XEXP (link, 1) = unused_expr_list;
3270 unused_expr_list = link;
3272 while (pending_write_insns)
3274 add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI);
3276 link = pending_write_insns;
3277 pending_write_insns = XEXP (pending_write_insns, 1);
3278 XEXP (link, 1) = unused_insn_list;
3279 unused_insn_list = link;
3281 link = pending_write_mems;
3282 pending_write_mems = XEXP (pending_write_mems, 1);
3283 XEXP (link, 1) = unused_expr_list;
3284 unused_expr_list = link;
3286 pending_lists_length = 0;
3288 /* last_pending_memory_flush is now a list of insns */
3289 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
3290 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3292 free_list (&last_pending_memory_flush, &unused_insn_list);
3293 last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX);
3296 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
3297 by the write to the destination of X, and reads of everything mentioned. */
3300 sched_analyze_1 (x, insn)
3305 register rtx dest = SET_DEST (x);
3310 if (GET_CODE (dest) == PARALLEL
3311 && GET_MODE (dest) == BLKmode)
3314 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
3315 sched_analyze_1 (XVECEXP (dest, 0, i), insn);
3316 if (GET_CODE (x) == SET)
3317 sched_analyze_2 (SET_SRC (x), insn);
3321 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
3322 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
3324 if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
3326 /* The second and third arguments are values read by this insn. */
3327 sched_analyze_2 (XEXP (dest, 1), insn);
3328 sched_analyze_2 (XEXP (dest, 2), insn);
3330 dest = SUBREG_REG (dest);
3333 if (GET_CODE (dest) == REG)
3337 regno = REGNO (dest);
3339 /* A hard reg in a wide mode may really be multiple registers.
3340 If so, mark all of them just like the first. */
3341 if (regno < FIRST_PSEUDO_REGISTER)
3343 i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
3348 for (u = reg_last_uses[regno + i]; u; u = XEXP (u, 1))
3349 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3350 reg_last_uses[regno + i] = 0;
3352 for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1))
3353 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3355 SET_REGNO_REG_SET (reg_pending_sets, regno + i);
3357 if ((call_used_regs[regno + i] || global_regs[regno + i]))
3358 /* Function calls clobber all call_used regs. */
3359 for (u = last_function_call; u; u = XEXP (u, 1))
3360 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3367 for (u = reg_last_uses[regno]; u; u = XEXP (u, 1))
3368 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3369 reg_last_uses[regno] = 0;
3371 for (u = reg_last_sets[regno]; u; u = XEXP (u, 1))
3372 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3374 SET_REGNO_REG_SET (reg_pending_sets, regno);
3376 /* Pseudos that are REG_EQUIV to something may be replaced
3377 by that during reloading. We need only add dependencies for
3378 the address in the REG_EQUIV note. */
3379 if (!reload_completed
3380 && reg_known_equiv_p[regno]
3381 && GET_CODE (reg_known_value[regno]) == MEM)
3382 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
3384 /* Don't let it cross a call after scheduling if it doesn't
3385 already cross one. */
3387 if (REG_N_CALLS_CROSSED (regno) == 0)
3388 for (u = last_function_call; u; u = XEXP (u, 1))
3389 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3392 else if (GET_CODE (dest) == MEM)
3394 /* Writing memory. */
3396 if (pending_lists_length > 32)
3398 /* Flush all pending reads and writes to prevent the pending lists
3399 from getting any larger. Insn scheduling runs too slowly when
3400 these lists get long. The number 32 was chosen because it
3401 seems like a reasonable number. When compiling GCC with itself,
3402 this flush occurs 8 times for sparc, and 10 times for m88k using
3404 flush_pending_lists (insn, 0);
3409 rtx pending, pending_mem;
3411 pending = pending_read_insns;
3412 pending_mem = pending_read_mems;
3415 /* If a dependency already exists, don't create a new one. */
3416 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3417 if (anti_dependence (XEXP (pending_mem, 0), dest))
3418 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
3420 pending = XEXP (pending, 1);
3421 pending_mem = XEXP (pending_mem, 1);
3424 pending = pending_write_insns;
3425 pending_mem = pending_write_mems;
3428 /* If a dependency already exists, don't create a new one. */
3429 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3430 if (output_dependence (XEXP (pending_mem, 0), dest))
3431 add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT);
3433 pending = XEXP (pending, 1);
3434 pending_mem = XEXP (pending_mem, 1);
3437 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
3438 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3440 add_insn_mem_dependence (&pending_write_insns, &pending_write_mems,
3443 sched_analyze_2 (XEXP (dest, 0), insn);
3446 /* Analyze reads. */
3447 if (GET_CODE (x) == SET)
3448 sched_analyze_2 (SET_SRC (x), insn);
3451 /* Analyze the uses of memory and registers in rtx X in INSN. */
3454 sched_analyze_2 (x, insn)
3460 register enum rtx_code code;
3466 code = GET_CODE (x);
3475 /* Ignore constants. Note that we must handle CONST_DOUBLE here
3476 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
3477 this does not mean that this insn is using cc0. */
3485 /* User of CC0 depends on immediately preceding insn. */
3486 SCHED_GROUP_P (insn) = 1;
3488 /* There may be a note before this insn now, but all notes will
3489 be removed before we actually try to schedule the insns, so
3490 it won't cause a problem later. We must avoid it here though. */
3491 prev = prev_nonnote_insn (insn);
3493 /* Make a copy of all dependencies on the immediately previous insn,
3494 and add to this insn. This is so that all the dependencies will
3495 apply to the group. Remove an explicit dependence on this insn
3496 as SCHED_GROUP_P now represents it. */
3498 if (find_insn_list (prev, LOG_LINKS (insn)))
3499 remove_dependence (insn, prev);
3501 for (link = LOG_LINKS (prev); link; link = XEXP (link, 1))
3502 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
3511 int regno = REGNO (x);
3512 if (regno < FIRST_PSEUDO_REGISTER)
3516 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
3519 reg_last_uses[regno + i]
3520 = alloc_INSN_LIST (insn, reg_last_uses[regno + i]);
3522 for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1))
3523 add_dependence (insn, XEXP (u, 0), 0);
3525 if ((call_used_regs[regno + i] || global_regs[regno + i]))
3526 /* Function calls clobber all call_used regs. */
3527 for (u = last_function_call; u; u = XEXP (u, 1))
3528 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3533 reg_last_uses[regno] = alloc_INSN_LIST (insn, reg_last_uses[regno]);
3535 for (u = reg_last_sets[regno]; u; u = XEXP (u, 1))
3536 add_dependence (insn, XEXP (u, 0), 0);
3538 /* Pseudos that are REG_EQUIV to something may be replaced
3539 by that during reloading. We need only add dependencies for
3540 the address in the REG_EQUIV note. */
3541 if (!reload_completed
3542 && reg_known_equiv_p[regno]
3543 && GET_CODE (reg_known_value[regno]) == MEM)
3544 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
3546 /* If the register does not already cross any calls, then add this
3547 insn to the sched_before_next_call list so that it will still
3548 not cross calls after scheduling. */
3549 if (REG_N_CALLS_CROSSED (regno) == 0)
3550 add_dependence (sched_before_next_call, insn, REG_DEP_ANTI);
3557 /* Reading memory. */
3559 rtx pending, pending_mem;
3561 pending = pending_read_insns;
3562 pending_mem = pending_read_mems;
3565 /* If a dependency already exists, don't create a new one. */
3566 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3567 if (read_dependence (XEXP (pending_mem, 0), x))
3568 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
3570 pending = XEXP (pending, 1);
3571 pending_mem = XEXP (pending_mem, 1);
3574 pending = pending_write_insns;
3575 pending_mem = pending_write_mems;
3578 /* If a dependency already exists, don't create a new one. */
3579 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3580 if (true_dependence (XEXP (pending_mem, 0), VOIDmode,
3582 add_dependence (insn, XEXP (pending, 0), 0);
3584 pending = XEXP (pending, 1);
3585 pending_mem = XEXP (pending_mem, 1);
3588 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
3589 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3591 /* Always add these dependencies to pending_reads, since
3592 this insn may be followed by a write. */
3593 add_insn_mem_dependence (&pending_read_insns, &pending_read_mems,
3596 /* Take advantage of tail recursion here. */
3597 sched_analyze_2 (XEXP (x, 0), insn);
3601 /* Force pending stores to memory in case a trap handler needs them. */
3603 flush_pending_lists (insn, 1);
3608 case UNSPEC_VOLATILE:
3612 /* Traditional and volatile asm instructions must be considered to use
3613 and clobber all hard registers, all pseudo-registers and all of
3614 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
3616 Consider for instance a volatile asm that changes the fpu rounding
3617 mode. An insn should not be moved across this even if it only uses
3618 pseudo-regs because it might give an incorrectly rounded result. */
3619 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
3621 int max_reg = max_reg_num ();
3622 for (i = 0; i < max_reg; i++)
3624 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3625 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3626 reg_last_uses[i] = 0;
3628 /* reg_last_sets[r] is now a list of insns */
3629 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3630 add_dependence (insn, XEXP (u, 0), 0);
3632 reg_pending_sets_all = 1;
3634 flush_pending_lists (insn, 0);
3637 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
3638 We can not just fall through here since then we would be confused
3639 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
3640 traditional asms unlike their normal usage. */
3642 if (code == ASM_OPERANDS)
3644 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
3645 sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn);
3655 /* These both read and modify the result. We must handle them as writes
3656 to get proper dependencies for following instructions. We must handle
3657 them as reads to get proper dependencies from this to previous
3658 instructions. Thus we need to pass them to both sched_analyze_1
3659 and sched_analyze_2. We must call sched_analyze_2 first in order
3660 to get the proper antecedent for the read. */
3661 sched_analyze_2 (XEXP (x, 0), insn);
3662 sched_analyze_1 (x, insn);
3669 /* Other cases: walk the insn. */
3670 fmt = GET_RTX_FORMAT (code);
3671 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3674 sched_analyze_2 (XEXP (x, i), insn);
3675 else if (fmt[i] == 'E')
3676 for (j = 0; j < XVECLEN (x, i); j++)
3677 sched_analyze_2 (XVECEXP (x, i, j), insn);
3681 /* Analyze an INSN with pattern X to find all dependencies. */
3684 sched_analyze_insn (x, insn, loop_notes)
3688 register RTX_CODE code = GET_CODE (x);
3690 int maxreg = max_reg_num ();
3693 if (code == SET || code == CLOBBER)
3694 sched_analyze_1 (x, insn);
3695 else if (code == PARALLEL)
3698 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
3700 code = GET_CODE (XVECEXP (x, 0, i));
3701 if (code == SET || code == CLOBBER)
3702 sched_analyze_1 (XVECEXP (x, 0, i), insn);
3704 sched_analyze_2 (XVECEXP (x, 0, i), insn);
3708 sched_analyze_2 (x, insn);
3710 /* Mark registers CLOBBERED or used by called function. */
3711 if (GET_CODE (insn) == CALL_INSN)
3712 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
3714 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
3715 sched_analyze_1 (XEXP (link, 0), insn);
3717 sched_analyze_2 (XEXP (link, 0), insn);
3720 /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic
3721 block, then we must be sure that no instructions are scheduled across it.
3722 Otherwise, the reg_n_refs info (which depends on loop_depth) would
3723 become incorrect. */
3727 int max_reg = max_reg_num ();
3728 int schedule_barrier_found = 0;
3731 /* Update loop_notes with any notes from this insn. Also determine
3732 if any of the notes on the list correspond to instruction scheduling
3733 barriers (loop, eh & setjmp notes, but not range notes. */
3735 while (XEXP (link, 1))
3737 if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG
3738 || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END
3739 || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG
3740 || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END
3741 || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP)
3742 schedule_barrier_found = 1;
3744 link = XEXP (link, 1);
3746 XEXP (link, 1) = REG_NOTES (insn);
3747 REG_NOTES (insn) = loop_notes;
3749 /* Add dependencies if a scheduling barrier was found. */
3750 if (schedule_barrier_found)
3752 for (i = 0; i < max_reg; i++)
3755 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3756 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3757 reg_last_uses[i] = 0;
3759 /* reg_last_sets[r] is now a list of insns */
3760 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3761 add_dependence (insn, XEXP (u, 0), 0);
3763 reg_pending_sets_all = 1;
3765 flush_pending_lists (insn, 0);
3770 /* After reload, it is possible for an instruction to have a REG_DEAD note
3771 for a register that actually dies a few instructions earlier. For
3772 example, this can happen with SECONDARY_MEMORY_NEEDED reloads.
3773 In this case, we must consider the insn to use the register mentioned
3774 in the REG_DEAD note. Otherwise, we may accidentally move this insn
3775 after another insn that sets the register, thus getting obviously invalid
3776 rtl. This confuses reorg which believes that REG_DEAD notes are still
3779 ??? We would get better code if we fixed reload to put the REG_DEAD
3780 notes in the right places, but that may not be worth the effort. */
3782 if (reload_completed)
3786 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
3787 if (REG_NOTE_KIND (note) == REG_DEAD)
3788 sched_analyze_2 (XEXP (note, 0), insn);
3791 EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i,
3793 /* reg_last_sets[r] is now a list of insns */
3794 free_list (®_last_sets[i], &unused_insn_list);
3796 = alloc_INSN_LIST (insn, NULL_RTX);
3798 CLEAR_REG_SET (reg_pending_sets);
3800 if (reg_pending_sets_all)
3802 for (i = 0; i < maxreg; i++)
3804 /* reg_last_sets[r] is now a list of insns */
3805 free_list (®_last_sets[i], &unused_insn_list);
3806 reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX);
3809 reg_pending_sets_all = 0;
3812 /* Handle function calls and function returns created by the epilogue
3814 if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
3819 /* When scheduling instructions, we make sure calls don't lose their
3820 accompanying USE insns by depending them one on another in order.
3822 Also, we must do the same thing for returns created by the epilogue
3823 threading code. Note this code works only in this special case,
3824 because other passes make no guarantee that they will never emit
3825 an instruction between a USE and a RETURN. There is such a guarantee
3826 for USE instructions immediately before a call. */
3828 prev_dep_insn = insn;
3829 dep_insn = PREV_INSN (insn);
3830 while (GET_CODE (dep_insn) == INSN
3831 && GET_CODE (PATTERN (dep_insn)) == USE
3832 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG)
3834 SCHED_GROUP_P (prev_dep_insn) = 1;
3836 /* Make a copy of all dependencies on dep_insn, and add to insn.
3837 This is so that all of the dependencies will apply to the
3840 for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1))
3841 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
3843 prev_dep_insn = dep_insn;
3844 dep_insn = PREV_INSN (dep_insn);
3849 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
3850 for every dependency. */
3853 sched_analyze (head, tail)
3860 for (insn = head;; insn = NEXT_INSN (insn))
3862 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
3864 /* Make each JUMP_INSN a scheduling barrier for memory references. */
3865 if (GET_CODE (insn) == JUMP_INSN)
3866 last_pending_memory_flush
3867 = alloc_INSN_LIST (insn, last_pending_memory_flush);
3868 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
3871 else if (GET_CODE (insn) == CALL_INSN)
3876 CANT_MOVE (insn) = 1;
3878 /* Any instruction using a hard register which may get clobbered
3879 by a call needs to be marked as dependent on this call.
3880 This prevents a use of a hard return reg from being moved
3881 past a void call (i.e. it does not explicitly set the hard
3884 /* If this call is followed by a NOTE_INSN_SETJMP, then assume that
3885 all registers, not just hard registers, may be clobbered by this
3888 /* Insn, being a CALL_INSN, magically depends on
3889 `last_function_call' already. */
3891 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE
3892 && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP)
3894 int max_reg = max_reg_num ();
3895 for (i = 0; i < max_reg; i++)
3897 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3898 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3900 reg_last_uses[i] = 0;
3902 /* reg_last_sets[r] is now a list of insns */
3903 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3904 add_dependence (insn, XEXP (u, 0), 0);
3906 reg_pending_sets_all = 1;
3908 /* Add a pair of fake REG_NOTE which we will later
3909 convert back into a NOTE_INSN_SETJMP note. See
3910 reemit_notes for why we use a pair of NOTEs. */
3911 REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD,
3914 REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD,
3915 GEN_INT (NOTE_INSN_SETJMP),
3920 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3921 if (call_used_regs[i] || global_regs[i])
3923 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3924 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3925 reg_last_uses[i] = 0;
3927 /* reg_last_sets[r] is now a list of insns */
3928 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3929 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3931 SET_REGNO_REG_SET (reg_pending_sets, i);
3935 /* For each insn which shouldn't cross a call, add a dependence
3936 between that insn and this call insn. */
3937 x = LOG_LINKS (sched_before_next_call);
3940 add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI);
3943 LOG_LINKS (sched_before_next_call) = 0;
3945 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
3948 /* In the absence of interprocedural alias analysis, we must flush
3949 all pending reads and writes, and start new dependencies starting
3950 from here. But only flush writes for constant calls (which may
3951 be passed a pointer to something we haven't written yet). */
3952 flush_pending_lists (insn, CONST_CALL_P (insn));
3954 /* Depend this function call (actually, the user of this
3955 function call) on all hard register clobberage. */
3957 /* last_function_call is now a list of insns */
3958 free_list(&last_function_call, &unused_insn_list);
3959 last_function_call = alloc_INSN_LIST (insn, NULL_RTX);
3962 /* See comments on reemit_notes as to why we do this. */
3963 /* ??? Actually, the reemit_notes just say what is done, not why. */
3965 else if (GET_CODE (insn) == NOTE
3966 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START
3967 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END))
3969 loop_notes = alloc_EXPR_LIST (REG_DEAD, NOTE_RANGE_INFO (insn),
3971 loop_notes = alloc_EXPR_LIST (REG_DEAD,
3972 GEN_INT (NOTE_LINE_NUMBER (insn)),
3975 else if (GET_CODE (insn) == NOTE
3976 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG
3977 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END
3978 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG
3979 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END
3980 || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP
3981 && GET_CODE (PREV_INSN (insn)) != CALL_INSN)))
3983 loop_notes = alloc_EXPR_LIST (REG_DEAD,
3984 GEN_INT (NOTE_BLOCK_NUMBER (insn)),
3986 loop_notes = alloc_EXPR_LIST (REG_DEAD,
3987 GEN_INT (NOTE_LINE_NUMBER (insn)),
3989 CONST_CALL_P (loop_notes) = CONST_CALL_P (insn);
3998 /* Called when we see a set of a register. If death is true, then we are
3999 scanning backwards. Mark that register as unborn. If nobody says
4000 otherwise, that is how things will remain. If death is false, then we
4001 are scanning forwards. Mark that register as being born. */
4004 sched_note_set (x, death)
4009 register rtx reg = SET_DEST (x);
4015 if (GET_CODE (reg) == PARALLEL
4016 && GET_MODE (reg) == BLKmode)
4019 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
4020 sched_note_set (XVECEXP (reg, 0, i), death);
4024 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART
4025 || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT)
4027 /* Must treat modification of just one hardware register of a multi-reg
4028 value or just a byte field of a register exactly the same way that
4029 mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg
4030 does not kill the entire register. */
4031 if (GET_CODE (reg) != SUBREG
4032 || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg))
4035 reg = SUBREG_REG (reg);
4038 if (GET_CODE (reg) != REG)
4041 /* Global registers are always live, so the code below does not apply
4044 regno = REGNO (reg);
4045 if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno])
4049 /* If we only set part of the register, then this set does not
4054 /* Try killing this register. */
4055 if (regno < FIRST_PSEUDO_REGISTER)
4057 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
4060 CLEAR_REGNO_REG_SET (bb_live_regs, regno + j);
4065 /* Recompute REG_BASIC_BLOCK as we update all the other
4066 dataflow information. */
4067 if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN)
4068 sched_reg_basic_block[regno] = current_block_num;
4069 else if (sched_reg_basic_block[regno] != current_block_num)
4070 sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL;
4072 CLEAR_REGNO_REG_SET (bb_live_regs, regno);
4077 /* Make the register live again. */
4078 if (regno < FIRST_PSEUDO_REGISTER)
4080 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
4083 SET_REGNO_REG_SET (bb_live_regs, regno + j);
4088 SET_REGNO_REG_SET (bb_live_regs, regno);
4094 /* Macros and functions for keeping the priority queue sorted, and
4095 dealing with queueing and dequeueing of instructions. */
4097 #define SCHED_SORT(READY, N_READY) \
4098 do { if ((N_READY) == 2) \
4099 swap_sort (READY, N_READY); \
4100 else if ((N_READY) > 2) \
4101 qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
4104 /* Returns a positive value if x is preferred; returns a negative value if
4105 y is preferred. Should never return 0, since that will make the sort
4109 rank_for_schedule (x, y)
4110 const GENERIC_PTR x;
4111 const GENERIC_PTR y;
4113 rtx tmp = *(rtx *)y;
4114 rtx tmp2 = *(rtx *)x;
4116 int tmp_class, tmp2_class, depend_count1, depend_count2;
4117 int val, priority_val, spec_val, prob_val, weight_val;
4120 /* prefer insn with higher priority */
4121 priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
4123 return priority_val;
4125 /* prefer an insn with smaller contribution to registers-pressure */
4126 if (!reload_completed &&
4127 (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2)))
4128 return (weight_val);
4130 /* some comparison make sense in interblock scheduling only */
4131 if (INSN_BB (tmp) != INSN_BB (tmp2))
4133 /* prefer an inblock motion on an interblock motion */
4134 if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb))
4136 if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb))
4139 /* prefer a useful motion on a speculative one */
4140 if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2)))
4143 /* prefer a more probable (speculative) insn */
4144 prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp);
4149 /* compare insns based on their relation to the last-scheduled-insn */
4150 if (last_scheduled_insn)
4152 /* Classify the instructions into three classes:
4153 1) Data dependent on last schedule insn.
4154 2) Anti/Output dependent on last scheduled insn.
4155 3) Independent of last scheduled insn, or has latency of one.
4156 Choose the insn from the highest numbered class if different. */
4157 link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn));
4158 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1)
4160 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
4165 link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn));
4166 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1)
4168 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
4173 if ((val = tmp2_class - tmp_class))
4177 /* Prefer the insn which has more later insns that depend on it.
4178 This gives the scheduler more freedom when scheduling later
4179 instructions at the expense of added register pressure. */
4181 for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1))
4185 for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1))
4188 val = depend_count2 - depend_count1;
4192 /* If insns are equally good, sort by INSN_LUID (original insn order),
4193 so that we make the sort stable. This minimizes instruction movement,
4194 thus minimizing sched's effect on debugging and cross-jumping. */
4195 return INSN_LUID (tmp) - INSN_LUID (tmp2);
4198 /* Resort the array A in which only element at index N may be out of order. */
4200 HAIFA_INLINE static void
4205 rtx insn = a[n - 1];
4208 while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
4216 static int max_priority;
4218 /* Add INSN to the insn queue so that it can be executed at least
4219 N_CYCLES after the currently executing insn. Preserve insns
4220 chain for debugging purposes. */
4222 HAIFA_INLINE static void
4223 queue_insn (insn, n_cycles)
4227 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
4228 rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
4229 insn_queue[next_q] = link;
4232 if (sched_verbose >= 2)
4234 fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn));
4236 if (INSN_BB (insn) != target_bb)
4237 fprintf (dump, "(b%d) ", INSN_BLOCK (insn));
4239 fprintf (dump, "queued for %d cycles.\n", n_cycles);
4244 /* Return nonzero if PAT is the pattern of an insn which makes a
4247 HAIFA_INLINE static int
4248 birthing_insn_p (pat)
4253 if (reload_completed == 1)
4256 if (GET_CODE (pat) == SET
4257 && (GET_CODE (SET_DEST (pat)) == REG
4258 || (GET_CODE (SET_DEST (pat)) == PARALLEL
4259 && GET_MODE (SET_DEST (pat)) == BLKmode)))
4261 rtx dest = SET_DEST (pat);
4264 /* It would be more accurate to use refers_to_regno_p or
4265 reg_mentioned_p to determine when the dest is not live before this
4267 if (GET_CODE (dest) == REG)
4270 if (REGNO_REG_SET_P (bb_live_regs, i))
4271 return (REG_N_SETS (i) == 1);
4275 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
4277 int regno = REGNO (SET_DEST (XVECEXP (dest, 0, i)));
4278 if (REGNO_REG_SET_P (bb_live_regs, regno))
4279 return (REG_N_SETS (regno) == 1);
4284 if (GET_CODE (pat) == PARALLEL)
4286 for (j = 0; j < XVECLEN (pat, 0); j++)
4287 if (birthing_insn_p (XVECEXP (pat, 0, j)))
4293 /* PREV is an insn that is ready to execute. Adjust its priority if that
4294 will help shorten register lifetimes. */
4296 HAIFA_INLINE static void
4297 adjust_priority (prev)
4300 /* Trying to shorten register lives after reload has completed
4301 is useless and wrong. It gives inaccurate schedules. */
4302 if (reload_completed == 0)
4307 /* ??? This code has no effect, because REG_DEAD notes are removed
4308 before we ever get here. */
4309 for (note = REG_NOTES (prev); note; note = XEXP (note, 1))
4310 if (REG_NOTE_KIND (note) == REG_DEAD)
4313 /* Defer scheduling insns which kill registers, since that
4314 shortens register lives. Prefer scheduling insns which
4315 make registers live for the same reason. */
4319 INSN_PRIORITY (prev) >>= 3;
4322 INSN_PRIORITY (prev) >>= 2;
4326 INSN_PRIORITY (prev) >>= 1;
4329 if (birthing_insn_p (PATTERN (prev)))
4331 int max = max_priority;
4333 if (max > INSN_PRIORITY (prev))
4334 INSN_PRIORITY (prev) = max;
4338 #ifdef ADJUST_PRIORITY
4339 ADJUST_PRIORITY (prev);
4344 /* Clock at which the previous instruction was issued. */
4345 static int last_clock_var;
4347 /* INSN is the "currently executing insn". Launch each insn which was
4348 waiting on INSN. READY is a vector of insns which are ready to fire.
4349 N_READY is the number of elements in READY. CLOCK is the current
4353 schedule_insn (insn, ready, n_ready, clock)
4362 unit = insn_unit (insn);
4364 if (sched_verbose >= 2)
4366 fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", INSN_UID (insn));
4367 insn_print_units (insn);
4368 fprintf (dump, "\n");
4371 if (sched_verbose && unit == -1)
4372 visualize_no_unit (insn);
4374 if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose)
4375 schedule_unit (unit, insn, clock);
4377 if (INSN_DEPEND (insn) == 0)
4380 /* This is used by the function adjust_priority above. */
4382 max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn));
4384 max_priority = INSN_PRIORITY (insn);
4386 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
4388 rtx next = XEXP (link, 0);
4389 int cost = insn_cost (insn, link, next);
4391 INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost);
4393 if ((INSN_DEP_COUNT (next) -= 1) == 0)
4395 int effective_cost = INSN_TICK (next) - clock;
4397 /* For speculative insns, before inserting to ready/queue,
4398 check live, exception-free, and issue-delay */
4399 if (INSN_BB (next) != target_bb
4400 && (!IS_VALID (INSN_BB (next))
4402 || (IS_SPECULATIVE_INSN (next)
4403 && (insn_issue_delay (next) > 3
4404 || !check_live (next, INSN_BB (next))
4405 || !is_exception_free (next, INSN_BB (next), target_bb)))))
4408 if (sched_verbose >= 2)
4410 fprintf (dump, ";;\t\tdependences resolved: insn %d ", INSN_UID (next));
4412 if (current_nr_blocks > 1 && INSN_BB (next) != target_bb)
4413 fprintf (dump, "/b%d ", INSN_BLOCK (next));
4415 if (effective_cost <= 1)
4416 fprintf (dump, "into ready\n");
4418 fprintf (dump, "into queue with cost=%d\n", effective_cost);
4421 /* Adjust the priority of NEXT and either put it on the ready
4422 list or queue it. */
4423 adjust_priority (next);
4424 if (effective_cost <= 1)
4425 ready[n_ready++] = next;
4427 queue_insn (next, effective_cost);
4431 /* Annotate the instruction with issue information -- TImode
4432 indicates that the instruction is expected not to be able
4433 to issue on the same cycle as the previous insn. A machine
4434 may use this information to decide how the instruction should
4436 if (reload_completed && issue_rate > 1)
4438 PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode);
4439 last_clock_var = clock;
4446 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
4450 create_reg_dead_note (reg, insn)
4455 /* The number of registers killed after scheduling must be the same as the
4456 number of registers killed before scheduling. The number of REG_DEAD
4457 notes may not be conserved, i.e. two SImode hard register REG_DEAD notes
4458 might become one DImode hard register REG_DEAD note, but the number of
4459 registers killed will be conserved.
4461 We carefully remove REG_DEAD notes from the dead_notes list, so that
4462 there will be none left at the end. If we run out early, then there
4463 is a bug somewhere in flow, combine and/or sched. */
4465 if (dead_notes == 0)
4467 if (current_nr_blocks <= 1)
4470 link = alloc_EXPR_LIST (REG_DEAD, NULL_RTX, NULL_RTX);
4474 /* Number of regs killed by REG. */
4475 int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1
4476 : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)));
4477 /* Number of regs killed by REG_DEAD notes taken off the list. */
4481 reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
4482 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
4483 GET_MODE (XEXP (link, 0))));
4484 while (reg_note_regs < regs_killed)
4486 link = XEXP (link, 1);
4488 /* LINK might be zero if we killed more registers after scheduling
4489 than before, and the last hard register we kill is actually
4492 This is normal for interblock scheduling, so deal with it in
4493 that case, else abort. */
4494 if (link == NULL_RTX && current_nr_blocks <= 1)
4496 else if (link == NULL_RTX)
4497 link = alloc_EXPR_LIST (REG_DEAD, gen_rtx_REG (word_mode, 0),
4500 reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
4501 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
4502 GET_MODE (XEXP (link, 0))));
4504 dead_notes = XEXP (link, 1);
4506 /* If we took too many regs kills off, put the extra ones back. */
4507 while (reg_note_regs > regs_killed)
4509 rtx temp_reg, temp_link;
4511 temp_reg = gen_rtx_REG (word_mode, 0);
4512 temp_link = alloc_EXPR_LIST (REG_DEAD, temp_reg, dead_notes);
4513 dead_notes = temp_link;
4518 XEXP (link, 0) = reg;
4519 XEXP (link, 1) = REG_NOTES (insn);
4520 REG_NOTES (insn) = link;
4523 /* Subroutine on attach_deaths_insn--handles the recursive search
4524 through INSN. If SET_P is true, then x is being modified by the insn. */
4527 attach_deaths (x, insn, set_p)
4534 register enum rtx_code code;
4540 code = GET_CODE (x);
4552 /* Get rid of the easy cases first. */
4557 /* If the register dies in this insn, queue that note, and mark
4558 this register as needing to die. */
4559 /* This code is very similar to mark_used_1 (if set_p is false)
4560 and mark_set_1 (if set_p is true) in flow.c. */
4570 all_needed = some_needed = REGNO_REG_SET_P (old_live_regs, regno);
4571 if (regno < FIRST_PSEUDO_REGISTER)
4575 n = HARD_REGNO_NREGS (regno, GET_MODE (x));
4578 int needed = (REGNO_REG_SET_P (old_live_regs, regno + n));
4579 some_needed |= needed;
4580 all_needed &= needed;
4584 /* If it wasn't live before we started, then add a REG_DEAD note.
4585 We must check the previous lifetime info not the current info,
4586 because we may have to execute this code several times, e.g.
4587 once for a clobber (which doesn't add a note) and later
4588 for a use (which does add a note).
4590 Always make the register live. We must do this even if it was
4591 live before, because this may be an insn which sets and uses
4592 the same register, in which case the register has already been
4593 killed, so we must make it live again.
4595 Global registers are always live, and should never have a REG_DEAD
4596 note added for them, so none of the code below applies to them. */
4598 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
4600 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
4601 STACK_POINTER_REGNUM, since these are always considered to be
4602 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
4603 if (regno != FRAME_POINTER_REGNUM
4604 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
4605 && ! (regno == HARD_FRAME_POINTER_REGNUM)
4607 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
4608 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
4610 && regno != STACK_POINTER_REGNUM)
4612 if (! all_needed && ! dead_or_set_p (insn, x))
4614 /* Check for the case where the register dying partially
4615 overlaps the register set by this insn. */
4616 if (regno < FIRST_PSEUDO_REGISTER
4617 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
4619 int n = HARD_REGNO_NREGS (regno, GET_MODE (x));
4621 some_needed |= dead_or_set_regno_p (insn, regno + n);
4624 /* If none of the words in X is needed, make a REG_DEAD
4625 note. Otherwise, we must make partial REG_DEAD
4628 create_reg_dead_note (x, insn);
4633 /* Don't make a REG_DEAD note for a part of a
4634 register that is set in the insn. */
4635 for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1;
4637 if (! REGNO_REG_SET_P (old_live_regs, regno+i)
4638 && ! dead_or_set_regno_p (insn, regno + i))
4639 create_reg_dead_note (gen_rtx_REG (reg_raw_mode[regno + i],
4646 if (regno < FIRST_PSEUDO_REGISTER)
4648 int j = HARD_REGNO_NREGS (regno, GET_MODE (x));
4651 SET_REGNO_REG_SET (bb_live_regs, regno + j);
4656 /* Recompute REG_BASIC_BLOCK as we update all the other
4657 dataflow information. */
4658 if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN)
4659 sched_reg_basic_block[regno] = current_block_num;
4660 else if (sched_reg_basic_block[regno] != current_block_num)
4661 sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL;
4663 SET_REGNO_REG_SET (bb_live_regs, regno);
4670 /* Handle tail-recursive case. */
4671 attach_deaths (XEXP (x, 0), insn, 0);
4675 attach_deaths (SUBREG_REG (x), insn,
4676 set_p && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
4678 || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
4679 == GET_MODE_SIZE (GET_MODE ((x))))));
4682 case STRICT_LOW_PART:
4683 attach_deaths (XEXP (x, 0), insn, 0);
4688 attach_deaths (XEXP (x, 0), insn, 0);
4689 attach_deaths (XEXP (x, 1), insn, 0);
4690 attach_deaths (XEXP (x, 2), insn, 0);
4695 && GET_MODE (x) == BLKmode)
4697 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4698 attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1);
4704 /* Other cases: walk the insn. */
4705 fmt = GET_RTX_FORMAT (code);
4706 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4709 attach_deaths (XEXP (x, i), insn, 0);
4710 else if (fmt[i] == 'E')
4711 for (j = 0; j < XVECLEN (x, i); j++)
4712 attach_deaths (XVECEXP (x, i, j), insn, 0);
4717 /* After INSN has executed, add register death notes for each register
4718 that is dead after INSN. */
4721 attach_deaths_insn (insn)
4724 rtx x = PATTERN (insn);
4725 register RTX_CODE code = GET_CODE (x);
4730 attach_deaths (SET_SRC (x), insn, 0);
4732 /* A register might die here even if it is the destination, e.g.
4733 it is the target of a volatile read and is otherwise unused.
4734 Hence we must always call attach_deaths for the SET_DEST. */
4735 attach_deaths (SET_DEST (x), insn, 1);
4737 else if (code == PARALLEL)
4740 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4742 code = GET_CODE (XVECEXP (x, 0, i));
4745 attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0);
4747 attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1);
4749 /* Flow does not add REG_DEAD notes to registers that die in
4750 clobbers, so we can't either. */
4751 else if (code != CLOBBER)
4752 attach_deaths (XVECEXP (x, 0, i), insn, 0);
4755 /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a
4756 MEM being clobbered, just like flow. */
4757 else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == MEM)
4758 attach_deaths (XEXP (XEXP (x, 0), 0), insn, 0);
4759 /* Otherwise don't add a death note to things being clobbered. */
4760 else if (code != CLOBBER)
4761 attach_deaths (x, insn, 0);
4763 /* Make death notes for things used in the called function. */
4764 if (GET_CODE (insn) == CALL_INSN)
4765 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
4766 attach_deaths (XEXP (XEXP (link, 0), 0), insn,
4767 GET_CODE (XEXP (link, 0)) == CLOBBER);
4770 /* functions for handlnig of notes */
4772 /* Delete notes beginning with INSN and put them in the chain
4773 of notes ended by NOTE_LIST.
4774 Returns the insn following the notes. */
4777 unlink_other_notes (insn, tail)
4780 rtx prev = PREV_INSN (insn);
4782 while (insn != tail && GET_CODE (insn) == NOTE)
4784 rtx next = NEXT_INSN (insn);
4785 /* Delete the note from its current position. */
4787 NEXT_INSN (prev) = next;
4789 PREV_INSN (next) = prev;
4791 /* Don't save away NOTE_INSN_SETJMPs, because they must remain
4792 immediately after the call they follow. We use a fake
4793 (REG_DEAD (const_int -1)) note to remember them.
4794 Likewise with NOTE_INSN_{LOOP,EHREGION}_{BEG, END}. */
4795 if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP
4796 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG
4797 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END
4798 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START
4799 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END
4800 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG
4801 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END)
4803 /* Insert the note at the end of the notes list. */
4804 PREV_INSN (insn) = note_list;
4806 NEXT_INSN (note_list) = insn;
4815 /* Delete line notes beginning with INSN. Record line-number notes so
4816 they can be reused. Returns the insn following the notes. */
4819 unlink_line_notes (insn, tail)
4822 rtx prev = PREV_INSN (insn);
4824 while (insn != tail && GET_CODE (insn) == NOTE)
4826 rtx next = NEXT_INSN (insn);
4828 if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
4830 /* Delete the note from its current position. */
4832 NEXT_INSN (prev) = next;
4834 PREV_INSN (next) = prev;
4836 /* Record line-number notes so they can be reused. */
4837 LINE_NOTE (insn) = insn;
4847 /* Return the head and tail pointers of BB. */
4849 HAIFA_INLINE static void
4850 get_block_head_tail (bb, headp, tailp)
4860 b = BB_TO_BLOCK (bb);
4862 /* HEAD and TAIL delimit the basic block being scheduled. */
4863 head = basic_block_head[b];
4864 tail = basic_block_end[b];
4866 /* Don't include any notes or labels at the beginning of the
4867 basic block, or notes at the ends of basic blocks. */
4868 while (head != tail)
4870 if (GET_CODE (head) == NOTE)
4871 head = NEXT_INSN (head);
4872 else if (GET_CODE (tail) == NOTE)
4873 tail = PREV_INSN (tail);
4874 else if (GET_CODE (head) == CODE_LABEL)
4875 head = NEXT_INSN (head);
4884 /* Delete line notes from bb. Save them so they can be later restored
4885 (in restore_line_notes ()). */
4896 get_block_head_tail (bb, &head, &tail);
4899 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
4902 next_tail = NEXT_INSN (tail);
4903 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4907 /* Farm out notes, and maybe save them in NOTE_LIST.
4908 This is needed to keep the debugger from
4909 getting completely deranged. */
4910 if (GET_CODE (insn) == NOTE)
4913 insn = unlink_line_notes (insn, next_tail);
4919 if (insn == next_tail)
4925 /* Save line number notes for each insn in bb. */
4928 save_line_notes (bb)
4934 /* We must use the true line number for the first insn in the block
4935 that was computed and saved at the start of this pass. We can't
4936 use the current line number, because scheduling of the previous
4937 block may have changed the current line number. */
4939 rtx line = line_note_head[BB_TO_BLOCK (bb)];
4942 get_block_head_tail (bb, &head, &tail);
4943 next_tail = NEXT_INSN (tail);
4945 for (insn = basic_block_head[BB_TO_BLOCK (bb)];
4947 insn = NEXT_INSN (insn))
4948 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4951 LINE_NOTE (insn) = line;
4955 /* After bb was scheduled, insert line notes into the insns list. */
4958 restore_line_notes (bb)
4961 rtx line, note, prev, new;
4962 int added_notes = 0;
4964 rtx head, next_tail, insn;
4966 b = BB_TO_BLOCK (bb);
4968 head = basic_block_head[b];
4969 next_tail = NEXT_INSN (basic_block_end[b]);
4971 /* Determine the current line-number. We want to know the current
4972 line number of the first insn of the block here, in case it is
4973 different from the true line number that was saved earlier. If
4974 different, then we need a line number note before the first insn
4975 of this block. If it happens to be the same, then we don't want to
4976 emit another line number note here. */
4977 for (line = head; line; line = PREV_INSN (line))
4978 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4981 /* Walk the insns keeping track of the current line-number and inserting
4982 the line-number notes as needed. */
4983 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4984 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4986 /* This used to emit line number notes before every non-deleted note.
4987 However, this confuses a debugger, because line notes not separated
4988 by real instructions all end up at the same address. I can find no
4989 use for line number notes before other notes, so none are emitted. */
4990 else if (GET_CODE (insn) != NOTE
4991 && (note = LINE_NOTE (insn)) != 0
4994 || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
4995 || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
4998 prev = PREV_INSN (insn);
4999 if (LINE_NOTE (note))
5001 /* Re-use the original line-number note. */
5002 LINE_NOTE (note) = 0;
5003 PREV_INSN (note) = prev;
5004 NEXT_INSN (prev) = note;
5005 PREV_INSN (insn) = note;
5006 NEXT_INSN (note) = insn;
5011 new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
5012 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
5013 RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note);
5016 if (sched_verbose && added_notes)
5017 fprintf (dump, ";; added %d line-number notes\n", added_notes);
5020 /* After scheduling the function, delete redundant line notes from the
5024 rm_redundant_line_notes ()
5027 rtx insn = get_insns ();
5028 int active_insn = 0;
5031 /* Walk the insns deleting redundant line-number notes. Many of these
5032 are already present. The remainder tend to occur at basic
5033 block boundaries. */
5034 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
5035 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
5037 /* If there are no active insns following, INSN is redundant. */
5038 if (active_insn == 0)
5041 NOTE_SOURCE_FILE (insn) = 0;
5042 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
5044 /* If the line number is unchanged, LINE is redundant. */
5046 && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
5047 && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
5050 NOTE_SOURCE_FILE (line) = 0;
5051 NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
5058 else if (!((GET_CODE (insn) == NOTE
5059 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
5060 || (GET_CODE (insn) == INSN
5061 && (GET_CODE (PATTERN (insn)) == USE
5062 || GET_CODE (PATTERN (insn)) == CLOBBER))))
5065 if (sched_verbose && notes)
5066 fprintf (dump, ";; deleted %d line-number notes\n", notes);
5069 /* Delete notes between head and tail and put them in the chain
5070 of notes ended by NOTE_LIST. */
5073 rm_other_notes (head, tail)
5081 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
5084 next_tail = NEXT_INSN (tail);
5085 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5089 /* Farm out notes, and maybe save them in NOTE_LIST.
5090 This is needed to keep the debugger from
5091 getting completely deranged. */
5092 if (GET_CODE (insn) == NOTE)
5096 insn = unlink_other_notes (insn, next_tail);
5102 if (insn == next_tail)
5108 /* Constructor for `sometimes' data structure. */
5111 new_sometimes_live (regs_sometimes_live, regno, sometimes_max)
5112 struct sometimes *regs_sometimes_live;
5116 register struct sometimes *p;
5118 /* There should never be a register greater than max_regno here. If there
5119 is, it means that a define_split has created a new pseudo reg. This
5120 is not allowed, since there will not be flow info available for any
5121 new register, so catch the error here. */
5122 if (regno >= max_regno)
5125 p = ®s_sometimes_live[sometimes_max];
5128 p->calls_crossed = 0;
5130 return sometimes_max;
5133 /* Count lengths of all regs we are currently tracking,
5134 and find new registers no longer live. */
5137 finish_sometimes_live (regs_sometimes_live, sometimes_max)
5138 struct sometimes *regs_sometimes_live;
5143 for (i = 0; i < sometimes_max; i++)
5145 register struct sometimes *p = ®s_sometimes_live[i];
5146 int regno = p->regno;
5148 sched_reg_live_length[regno] += p->live_length;
5149 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
5153 /* functions for computation of registers live/usage info */
5155 /* It is assumed that prior to scheduling basic_block_live_at_start (b)
5156 contains the registers that are alive at the entry to b.
5158 Two passes follow: The first pass is performed before the scheduling
5159 of a region. It scans each block of the region forward, computing
5160 the set of registers alive at the end of the basic block and
5161 discard REG_DEAD notes (done by find_pre_sched_live ()).
5163 The second path is invoked after scheduling all region blocks.
5164 It scans each block of the region backward, a block being traversed
5165 only after its succesors in the region. When the set of registers
5166 live at the end of a basic block may be changed by the scheduling
5167 (this may happen for multiple blocks region), it is computed as
5168 the union of the registers live at the start of its succesors.
5169 The last-use information is updated by inserting REG_DEAD notes.
5170 (done by find_post_sched_live ()) */
5172 /* Scan all the insns to be scheduled, removing register death notes.
5173 Register death notes end up in DEAD_NOTES.
5174 Recreate the register life information for the end of this basic
5178 find_pre_sched_live (bb)
5181 rtx insn, next_tail, head, tail;
5182 int b = BB_TO_BLOCK (bb);
5184 get_block_head_tail (bb, &head, &tail);
5185 COPY_REG_SET (bb_live_regs, basic_block_live_at_start[b]);
5186 next_tail = NEXT_INSN (tail);
5188 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5190 rtx prev, next, link;
5193 /* Handle register life information. */
5194 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
5196 /* See if the register gets born here. */
5197 /* We must check for registers being born before we check for
5198 registers dying. It is possible for a register to be born and
5199 die in the same insn, e.g. reading from a volatile memory
5200 location into an otherwise unused register. Such a register
5201 must be marked as dead after this insn. */
5202 if (GET_CODE (PATTERN (insn)) == SET
5203 || GET_CODE (PATTERN (insn)) == CLOBBER)
5205 sched_note_set (PATTERN (insn), 0);
5209 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
5212 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
5213 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
5214 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
5216 sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0);
5220 /* ??? This code is obsolete and should be deleted. It
5221 is harmless though, so we will leave it in for now. */
5222 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
5223 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
5224 sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0);
5227 /* Each call cobbers (makes live) all call-clobbered regs
5228 that are not global or fixed. Note that the function-value
5229 reg is a call_clobbered reg. */
5230 if (GET_CODE (insn) == CALL_INSN)
5233 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
5234 if (call_used_regs[j] && !global_regs[j]
5237 SET_REGNO_REG_SET (bb_live_regs, j);
5241 /* Need to know what registers this insn kills. */
5242 for (prev = 0, link = REG_NOTES (insn); link; link = next)
5244 next = XEXP (link, 1);
5245 if ((REG_NOTE_KIND (link) == REG_DEAD
5246 || REG_NOTE_KIND (link) == REG_UNUSED)
5247 /* Verify that the REG_NOTE has a valid value. */
5248 && GET_CODE (XEXP (link, 0)) == REG)
5250 register int regno = REGNO (XEXP (link, 0));
5254 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
5256 if (REG_NOTE_KIND (link) == REG_DEAD)
5259 XEXP (prev, 1) = next;
5261 REG_NOTES (insn) = next;
5262 XEXP (link, 1) = dead_notes;
5268 if (regno < FIRST_PSEUDO_REGISTER)
5270 int j = HARD_REGNO_NREGS (regno,
5271 GET_MODE (XEXP (link, 0)));
5274 CLEAR_REGNO_REG_SET (bb_live_regs, regno+j);
5279 CLEAR_REGNO_REG_SET (bb_live_regs, regno);
5287 INSN_REG_WEIGHT (insn) = reg_weight;
5291 /* Update register life and usage information for block bb
5292 after scheduling. Put register dead notes back in the code. */
5295 find_post_sched_live (bb)
5302 rtx head, tail, prev_head, next_tail;
5304 register struct sometimes *regs_sometimes_live;
5306 b = BB_TO_BLOCK (bb);
5308 /* compute live regs at the end of bb as a function of its successors. */
5309 if (current_nr_blocks > 1)
5314 first_edge = e = OUT_EDGES (b);
5315 CLEAR_REG_SET (bb_live_regs);
5322 b_succ = TO_BLOCK (e);
5323 IOR_REG_SET (bb_live_regs, basic_block_live_at_start[b_succ]);
5326 while (e != first_edge);
5329 get_block_head_tail (bb, &head, &tail);
5330 next_tail = NEXT_INSN (tail);
5331 prev_head = PREV_INSN (head);
5333 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, i,
5335 sched_reg_basic_block[i] = REG_BLOCK_GLOBAL;
5338 /* if the block is empty, same regs are alive at its end and its start.
5339 since this is not guaranteed after interblock scheduling, make sure they
5340 are truly identical. */
5341 if (NEXT_INSN (prev_head) == tail
5342 && (GET_RTX_CLASS (GET_CODE (tail)) != 'i'))
5344 if (current_nr_blocks > 1)
5345 COPY_REG_SET (basic_block_live_at_start[b], bb_live_regs);
5350 b = BB_TO_BLOCK (bb);
5351 current_block_num = b;
5353 /* Keep track of register lives. */
5354 old_live_regs = ALLOCA_REG_SET ();
5356 = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes));
5359 /* initiate "sometimes" data, starting with registers live at end */
5361 COPY_REG_SET (old_live_regs, bb_live_regs);
5362 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, 0, j,
5365 = new_sometimes_live (regs_sometimes_live,
5369 /* scan insns back, computing regs live info */
5370 for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
5372 /* First we kill registers set by this insn, and then we
5373 make registers used by this insn live. This is the opposite
5374 order used above because we are traversing the instructions
5377 /* Strictly speaking, we should scan REG_UNUSED notes and make
5378 every register mentioned there live, however, we will just
5379 kill them again immediately below, so there doesn't seem to
5380 be any reason why we bother to do this. */
5382 /* See if this is the last notice we must take of a register. */
5383 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
5386 if (GET_CODE (PATTERN (insn)) == SET
5387 || GET_CODE (PATTERN (insn)) == CLOBBER)
5388 sched_note_set (PATTERN (insn), 1);
5389 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
5391 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
5392 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
5393 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
5394 sched_note_set (XVECEXP (PATTERN (insn), 0, j), 1);
5397 /* This code keeps life analysis information up to date. */
5398 if (GET_CODE (insn) == CALL_INSN)
5400 register struct sometimes *p;
5402 /* A call kills all call used registers that are not
5403 global or fixed, except for those mentioned in the call
5404 pattern which will be made live again later. */
5405 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5406 if (call_used_regs[i] && ! global_regs[i]
5409 CLEAR_REGNO_REG_SET (bb_live_regs, i);
5412 /* Regs live at the time of a call instruction must not
5413 go in a register clobbered by calls. Record this for
5414 all regs now live. Note that insns which are born or
5415 die in a call do not cross a call, so this must be done
5416 after the killings (above) and before the births
5418 p = regs_sometimes_live;
5419 for (i = 0; i < sometimes_max; i++, p++)
5420 if (REGNO_REG_SET_P (bb_live_regs, p->regno))
5421 p->calls_crossed += 1;
5424 /* Make every register used live, and add REG_DEAD notes for
5425 registers which were not live before we started. */
5426 attach_deaths_insn (insn);
5428 /* Find registers now made live by that instruction. */
5429 EXECUTE_IF_AND_COMPL_IN_REG_SET (bb_live_regs, old_live_regs, 0, j,
5432 = new_sometimes_live (regs_sometimes_live,
5435 IOR_REG_SET (old_live_regs, bb_live_regs);
5437 /* Count lengths of all regs we are worrying about now,
5438 and handle registers no longer live. */
5440 for (i = 0; i < sometimes_max; i++)
5442 register struct sometimes *p = ®s_sometimes_live[i];
5443 int regno = p->regno;
5445 p->live_length += 1;
5447 if (!REGNO_REG_SET_P (bb_live_regs, regno))
5449 /* This is the end of one of this register's lifetime
5450 segments. Save the lifetime info collected so far,
5451 and clear its bit in the old_live_regs entry. */
5452 sched_reg_live_length[regno] += p->live_length;
5453 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
5454 CLEAR_REGNO_REG_SET (old_live_regs, p->regno);
5456 /* Delete the reg_sometimes_live entry for this reg by
5457 copying the last entry over top of it. */
5458 *p = regs_sometimes_live[--sometimes_max];
5459 /* ...and decrement i so that this newly copied entry
5460 will be processed. */
5466 finish_sometimes_live (regs_sometimes_live, sometimes_max);
5468 /* In interblock scheduling, basic_block_live_at_start may have changed. */
5469 if (current_nr_blocks > 1)
5470 COPY_REG_SET (basic_block_live_at_start[b], bb_live_regs);
5473 FREE_REG_SET (old_live_regs);
5474 } /* find_post_sched_live */
5476 /* After scheduling the subroutine, restore information about uses of
5484 if (n_basic_blocks > 0)
5485 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, regno,
5487 sched_reg_basic_block[regno]
5491 for (regno = 0; regno < max_regno; regno++)
5492 if (sched_reg_live_length[regno])
5496 if (REG_LIVE_LENGTH (regno) > sched_reg_live_length[regno])
5498 ";; register %d life shortened from %d to %d\n",
5499 regno, REG_LIVE_LENGTH (regno),
5500 sched_reg_live_length[regno]);
5501 /* Negative values are special; don't overwrite the current
5502 reg_live_length value if it is negative. */
5503 else if (REG_LIVE_LENGTH (regno) < sched_reg_live_length[regno]
5504 && REG_LIVE_LENGTH (regno) >= 0)
5506 ";; register %d life extended from %d to %d\n",
5507 regno, REG_LIVE_LENGTH (regno),
5508 sched_reg_live_length[regno]);
5510 if (!REG_N_CALLS_CROSSED (regno)
5511 && sched_reg_n_calls_crossed[regno])
5513 ";; register %d now crosses calls\n", regno);
5514 else if (REG_N_CALLS_CROSSED (regno)
5515 && !sched_reg_n_calls_crossed[regno]
5516 && REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL)
5518 ";; register %d no longer crosses calls\n", regno);
5520 if (REG_BASIC_BLOCK (regno) != sched_reg_basic_block[regno]
5521 && sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN
5522 && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN)
5524 ";; register %d changed basic block from %d to %d\n",
5525 regno, REG_BASIC_BLOCK(regno),
5526 sched_reg_basic_block[regno]);
5529 /* Negative values are special; don't overwrite the current
5530 reg_live_length value if it is negative. */
5531 if (REG_LIVE_LENGTH (regno) >= 0)
5532 REG_LIVE_LENGTH (regno) = sched_reg_live_length[regno];
5534 if (sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN
5535 && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN)
5536 REG_BASIC_BLOCK(regno) = sched_reg_basic_block[regno];
5538 /* We can't change the value of reg_n_calls_crossed to zero for
5539 pseudos which are live in more than one block.
5541 This is because combine might have made an optimization which
5542 invalidated basic_block_live_at_start and reg_n_calls_crossed,
5543 but it does not update them. If we update reg_n_calls_crossed
5544 here, the two variables are now inconsistent, and this might
5545 confuse the caller-save code into saving a register that doesn't
5546 need to be saved. This is only a problem when we zero calls
5547 crossed for a pseudo live in multiple basic blocks.
5549 Alternatively, we could try to correctly update basic block live
5550 at start here in sched, but that seems complicated.
5552 Note: it is possible that a global register became local, as result
5553 of interblock motion, but will remain marked as a global register. */
5554 if (sched_reg_n_calls_crossed[regno]
5555 || REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL)
5556 REG_N_CALLS_CROSSED (regno) = sched_reg_n_calls_crossed[regno];
5561 /* Scheduling clock, modified in schedule_block() and queue_to_ready () */
5562 static int clock_var;
5564 /* Move insns that became ready to fire from queue to ready list. */
5567 queue_to_ready (ready, n_ready)
5574 q_ptr = NEXT_Q (q_ptr);
5576 /* Add all pending insns that can be scheduled without stalls to the
5578 for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1))
5581 insn = XEXP (link, 0);
5584 if (sched_verbose >= 2)
5585 fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
5587 if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
5588 fprintf (dump, "(b%d) ", INSN_BLOCK (insn));
5590 ready[n_ready++] = insn;
5591 if (sched_verbose >= 2)
5592 fprintf (dump, "moving to ready without stalls\n");
5594 insn_queue[q_ptr] = 0;
5596 /* If there are no ready insns, stall until one is ready and add all
5597 of the pending insns at that point to the ready list. */
5600 register int stalls;
5602 for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++)
5604 if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
5606 for (; link; link = XEXP (link, 1))
5608 insn = XEXP (link, 0);
5611 if (sched_verbose >= 2)
5612 fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
5614 if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
5615 fprintf (dump, "(b%d) ", INSN_BLOCK (insn));
5617 ready[n_ready++] = insn;
5618 if (sched_verbose >= 2)
5619 fprintf (dump, "moving to ready with %d stalls\n", stalls);
5621 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
5628 if (sched_verbose && stalls)
5629 visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls);
5630 q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
5631 clock_var += stalls;
5636 /* Print the ready list for debugging purposes. Callable from debugger. */
5639 debug_ready_list (ready, n_ready)
5645 for (i = 0; i < n_ready; i++)
5647 fprintf (dump, " %d", INSN_UID (ready[i]));
5648 if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb)
5649 fprintf (dump, "/b%d", INSN_BLOCK (ready[i]));
5651 fprintf (dump, "\n");
5654 /* Print names of units on which insn can/should execute, for debugging. */
5657 insn_print_units (insn)
5661 int unit = insn_unit (insn);
5664 fprintf (dump, "none");
5666 fprintf (dump, "%s", function_units[unit].name);
5669 fprintf (dump, "[");
5670 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
5673 fprintf (dump, "%s", function_units[i].name);
5675 fprintf (dump, " ");
5677 fprintf (dump, "]");
5681 /* MAX_VISUAL_LINES is the maximum number of lines in visualization table
5682 of a basic block. If more lines are needed, table is splitted to two.
5683 n_visual_lines is the number of lines printed so far for a block.
5684 visual_tbl contains the block visualization info.
5685 vis_no_unit holds insns in a cycle that are not mapped to any unit. */
5686 #define MAX_VISUAL_LINES 100
5691 rtx vis_no_unit[10];
5693 /* Finds units that are in use in this fuction. Required only
5694 for visualization. */
5697 init_target_units ()
5702 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
5704 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
5707 unit = insn_unit (insn);
5710 target_units |= ~unit;
5712 target_units |= (1 << unit);
5716 /* Return the length of the visualization table */
5719 get_visual_tbl_length ()
5725 /* compute length of one field in line */
5726 s = (char *) alloca (INSN_LEN + 5);
5727 sprintf (s, " %33s", "uname");
5730 /* compute length of one line */
5733 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
5734 if (function_units[unit].bitmask & target_units)
5735 for (i = 0; i < function_units[unit].multiplicity; i++)
5738 n += strlen ("\n") + 2;
5740 /* compute length of visualization string */
5741 return (MAX_VISUAL_LINES * n);
5744 /* Init block visualization debugging info */
5747 init_block_visualization ()
5749 strcpy (visual_tbl, "");
5757 safe_concat (buf, cur, str)
5762 char *end = buf + BUF_LEN - 2; /* leave room for null */
5771 while (cur < end && (c = *str++) != '\0')
5778 /* This recognizes rtx, I classified as expressions. These are always */
5779 /* represent some action on values or results of other expression, */
5780 /* that may be stored in objects representing values. */
5783 print_exp (buf, x, verbose)
5791 char *fun = (char *)0;
5796 for (i = 0; i < 4; i++)
5802 switch (GET_CODE (x))
5805 op[0] = XEXP (x, 0);
5807 op[1] = XEXP (x, 1);
5810 op[0] = XEXP (x, 0);
5812 op[1] = XEXP (x, 1);
5816 op[0] = XEXP (x, 0);
5818 op[1] = XEXP (x, 1);
5822 op[0] = XEXP (x, 0);
5823 op[1] = XEXP (x, 1);
5827 op[0] = XEXP (x, 0);
5830 op[0] = XEXP (x, 0);
5832 op[1] = XEXP (x, 1);
5835 op[0] = XEXP (x, 0);
5837 op[1] = XEXP (x, 1);
5841 op[0] = XEXP (x, 0);
5842 op[1] = XEXP (x, 1);
5845 op[0] = XEXP (x, 0);
5847 op[1] = XEXP (x, 1);
5851 op[0] = XEXP (x, 0);
5852 op[1] = XEXP (x, 1);
5856 op[0] = XEXP (x, 0);
5857 op[1] = XEXP (x, 1);
5861 op[0] = XEXP (x, 0);
5862 op[1] = XEXP (x, 1);
5866 op[0] = XEXP (x, 0);
5867 op[1] = XEXP (x, 1);
5871 op[0] = XEXP (x, 0);
5872 op[1] = XEXP (x, 1);
5876 op[0] = XEXP (x, 0);
5879 op[0] = XEXP (x, 0);
5881 op[1] = XEXP (x, 1);
5884 op[0] = XEXP (x, 0);
5886 op[1] = XEXP (x, 1);
5889 op[0] = XEXP (x, 0);
5891 op[1] = XEXP (x, 1);
5894 op[0] = XEXP (x, 0);
5896 op[1] = XEXP (x, 1);
5899 op[0] = XEXP (x, 0);
5901 op[1] = XEXP (x, 1);
5904 op[0] = XEXP (x, 0);
5906 op[1] = XEXP (x, 1);
5909 op[0] = XEXP (x, 0);
5911 op[1] = XEXP (x, 1);
5914 op[0] = XEXP (x, 0);
5916 op[1] = XEXP (x, 1);
5920 op[0] = XEXP (x, 0);
5924 op[0] = XEXP (x, 0);
5928 op[0] = XEXP (x, 0);
5931 op[0] = XEXP (x, 0);
5933 op[1] = XEXP (x, 1);
5936 op[0] = XEXP (x, 0);
5938 op[1] = XEXP (x, 1);
5941 op[0] = XEXP (x, 0);
5943 op[1] = XEXP (x, 1);
5947 op[0] = XEXP (x, 0);
5948 op[1] = XEXP (x, 1);
5951 op[0] = XEXP (x, 0);
5953 op[1] = XEXP (x, 1);
5957 op[0] = XEXP (x, 0);
5958 op[1] = XEXP (x, 1);
5961 op[0] = XEXP (x, 0);
5963 op[1] = XEXP (x, 1);
5967 op[0] = XEXP (x, 0);
5968 op[1] = XEXP (x, 1);
5971 op[0] = XEXP (x, 0);
5973 op[1] = XEXP (x, 1);
5977 op[0] = XEXP (x, 0);
5978 op[1] = XEXP (x, 1);
5981 fun = (verbose) ? "sign_extract" : "sxt";
5982 op[0] = XEXP (x, 0);
5983 op[1] = XEXP (x, 1);
5984 op[2] = XEXP (x, 2);
5987 fun = (verbose) ? "zero_extract" : "zxt";
5988 op[0] = XEXP (x, 0);
5989 op[1] = XEXP (x, 1);
5990 op[2] = XEXP (x, 2);
5993 fun = (verbose) ? "sign_extend" : "sxn";
5994 op[0] = XEXP (x, 0);
5997 fun = (verbose) ? "zero_extend" : "zxn";
5998 op[0] = XEXP (x, 0);
6001 fun = (verbose) ? "float_extend" : "fxn";
6002 op[0] = XEXP (x, 0);
6005 fun = (verbose) ? "trunc" : "trn";
6006 op[0] = XEXP (x, 0);
6008 case FLOAT_TRUNCATE:
6009 fun = (verbose) ? "float_trunc" : "ftr";
6010 op[0] = XEXP (x, 0);
6013 fun = (verbose) ? "float" : "flt";
6014 op[0] = XEXP (x, 0);
6016 case UNSIGNED_FLOAT:
6017 fun = (verbose) ? "uns_float" : "ufl";
6018 op[0] = XEXP (x, 0);
6022 op[0] = XEXP (x, 0);
6025 fun = (verbose) ? "uns_fix" : "ufx";
6026 op[0] = XEXP (x, 0);
6030 op[0] = XEXP (x, 0);
6034 op[0] = XEXP (x, 0);
6037 op[0] = XEXP (x, 0);
6041 op[0] = XEXP (x, 0);
6046 op[0] = XEXP (x, 0);
6050 op[1] = XEXP (x, 1);
6055 op[0] = XEXP (x, 0);
6057 op[1] = XEXP (x, 1);
6059 op[2] = XEXP (x, 2);
6064 op[0] = TRAP_CONDITION (x);
6067 case UNSPEC_VOLATILE:
6069 cur = safe_concat (buf, cur, "unspec");
6070 if (GET_CODE (x) == UNSPEC_VOLATILE)
6071 cur = safe_concat (buf, cur, "/v");
6072 cur = safe_concat (buf, cur, "[");
6074 for (i = 0; i < XVECLEN (x, 0); i++)
6076 print_pattern (tmp, XVECEXP (x, 0, i), verbose);
6077 cur = safe_concat (buf, cur, sep);
6078 cur = safe_concat (buf, cur, tmp);
6081 cur = safe_concat (buf, cur, "] ");
6082 sprintf (tmp, "%d", XINT (x, 1));
6083 cur = safe_concat (buf, cur, tmp);
6087 /* if (verbose) debug_rtx (x); */
6088 st[0] = GET_RTX_NAME (GET_CODE (x));
6092 /* Print this as a function? */
6095 cur = safe_concat (buf, cur, fun);
6096 cur = safe_concat (buf, cur, "(");
6099 for (i = 0; i < 4; i++)
6102 cur = safe_concat (buf, cur, st[i]);
6107 cur = safe_concat (buf, cur, ",");
6109 print_value (tmp, op[i], verbose);
6110 cur = safe_concat (buf, cur, tmp);
6115 cur = safe_concat (buf, cur, ")");
6118 /* Prints rtxes, i customly classified as values. They're constants, */
6119 /* registers, labels, symbols and memory accesses. */
6122 print_value (buf, x, verbose)
6130 switch (GET_CODE (x))
6133 sprintf (t, "0x%lx", (long)INTVAL (x));
6134 cur = safe_concat (buf, cur, t);
6137 sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6138 cur = safe_concat (buf, cur, t);
6141 cur = safe_concat (buf, cur, "\"");
6142 cur = safe_concat (buf, cur, XSTR (x, 0));
6143 cur = safe_concat (buf, cur, "\"");
6146 cur = safe_concat (buf, cur, "`");
6147 cur = safe_concat (buf, cur, XSTR (x, 0));
6148 cur = safe_concat (buf, cur, "'");
6151 sprintf (t, "L%d", INSN_UID (XEXP (x, 0)));
6152 cur = safe_concat (buf, cur, t);
6155 print_value (t, XEXP (x, 0), verbose);
6156 cur = safe_concat (buf, cur, "const(");
6157 cur = safe_concat (buf, cur, t);
6158 cur = safe_concat (buf, cur, ")");
6161 print_value (t, XEXP (x, 0), verbose);
6162 cur = safe_concat (buf, cur, "high(");
6163 cur = safe_concat (buf, cur, t);
6164 cur = safe_concat (buf, cur, ")");
6167 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
6169 int c = reg_names[ REGNO (x) ][0];
6170 if (c >= '0' && c <= '9')
6171 cur = safe_concat (buf, cur, "%");
6173 cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]);
6177 sprintf (t, "r%d", REGNO (x));
6178 cur = safe_concat (buf, cur, t);
6182 print_value (t, SUBREG_REG (x), verbose);
6183 cur = safe_concat (buf, cur, t);
6184 sprintf (t, "#%d", SUBREG_WORD (x));
6185 cur = safe_concat (buf, cur, t);
6188 cur = safe_concat (buf, cur, "scratch");
6191 cur = safe_concat (buf, cur, "cc0");
6194 cur = safe_concat (buf, cur, "pc");
6197 print_value (t, XEXP (x, 0), verbose);
6198 cur = safe_concat (buf, cur, "[");
6199 cur = safe_concat (buf, cur, t);
6200 cur = safe_concat (buf, cur, "]");
6203 print_exp (t, x, verbose);
6204 cur = safe_concat (buf, cur, t);
6209 /* The next step in insn detalization, its pattern recognition */
6212 print_pattern (buf, x, verbose)
6217 char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN];
6219 switch (GET_CODE (x))
6222 print_value (t1, SET_DEST (x), verbose);
6223 print_value (t2, SET_SRC (x), verbose);
6224 sprintf (buf, "%s=%s", t1, t2);
6227 sprintf (buf, "return");
6230 print_exp (buf, x, verbose);
6233 print_value (t1, XEXP (x, 0), verbose);
6234 sprintf (buf, "clobber %s", t1);
6237 print_value (t1, XEXP (x, 0), verbose);
6238 sprintf (buf, "use %s", t1);
6245 for (i = 0; i < XVECLEN (x, 0); i++)
6247 print_pattern (t2, XVECEXP (x, 0, i), verbose);
6248 sprintf (t3, "%s%s;", t1, t2);
6251 sprintf (buf, "%s}", t1);
6258 sprintf (t1, "%%{");
6259 for (i = 0; i < XVECLEN (x, 0); i++)
6261 print_insn (t2, XVECEXP (x, 0, i), verbose);
6262 sprintf (t3, "%s%s;", t1, t2);
6265 sprintf (buf, "%s%%}", t1);
6269 sprintf (buf, "asm {%s}", XSTR (x, 0));
6274 print_value (buf, XEXP (x, 0), verbose);
6277 print_value (t1, TRAP_CONDITION (x), verbose);
6278 sprintf (buf, "trap_if %s", t1);
6284 sprintf (t1, "unspec{");
6285 for (i = 0; i < XVECLEN (x, 0); i++)
6287 print_pattern (t2, XVECEXP (x, 0, i), verbose);
6288 sprintf (t3, "%s%s;", t1, t2);
6291 sprintf (buf, "%s}", t1);
6294 case UNSPEC_VOLATILE:
6298 sprintf (t1, "unspec/v{");
6299 for (i = 0; i < XVECLEN (x, 0); i++)
6301 print_pattern (t2, XVECEXP (x, 0, i), verbose);
6302 sprintf (t3, "%s%s;", t1, t2);
6305 sprintf (buf, "%s}", t1);
6309 print_value (buf, x, verbose);
6311 } /* print_pattern */
6313 /* This is the main function in rtl visualization mechanism. It
6314 accepts an rtx and tries to recognize it as an insn, then prints it
6315 properly in human readable form, resembling assembler mnemonics. */
6316 /* For every insn it prints its UID and BB the insn belongs */
6317 /* too. (probably the last "option" should be extended somehow, since */
6318 /* it depends now on sched.c inner variables ...) */
6321 print_insn (buf, x, verbose)
6329 switch (GET_CODE (x))
6332 print_pattern (t, PATTERN (x), verbose);
6334 sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x),
6337 sprintf (buf, "%-4d %s", INSN_UID (x), t);
6340 print_pattern (t, PATTERN (x), verbose);
6342 sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x),
6345 sprintf (buf, "%-4d %s", INSN_UID (x), t);
6349 if (GET_CODE (x) == PARALLEL)
6351 x = XVECEXP (x, 0, 0);
6352 print_pattern (t, x, verbose);
6355 strcpy (t, "call <...>");
6357 sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn),
6358 INSN_UID (insn), t);
6360 sprintf (buf, "%-4d %s", INSN_UID (insn), t);
6363 sprintf (buf, "L%d:", INSN_UID (x));
6366 sprintf (buf, "i% 4d: barrier", INSN_UID (x));
6369 if (NOTE_LINE_NUMBER (x) > 0)
6370 sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x),
6371 NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x));
6373 sprintf (buf, "%4d %s", INSN_UID (x),
6374 GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x)));
6379 sprintf (buf, "Not an INSN at all\n");
6383 sprintf (buf, "i%-4d <What?>", INSN_UID (x));
6387 /* Print visualization debugging info */
6390 print_block_visualization (b, s)
6397 fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s);
6399 /* Print names of units */
6400 fprintf (dump, ";; %-8s", "clock");
6401 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
6402 if (function_units[unit].bitmask & target_units)
6403 for (i = 0; i < function_units[unit].multiplicity; i++)
6404 fprintf (dump, " %-33s", function_units[unit].name);
6405 fprintf (dump, " %-8s\n", "no-unit");
6407 fprintf (dump, ";; %-8s", "=====");
6408 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
6409 if (function_units[unit].bitmask & target_units)
6410 for (i = 0; i < function_units[unit].multiplicity; i++)
6411 fprintf (dump, " %-33s", "==============================");
6412 fprintf (dump, " %-8s\n", "=======");
6414 /* Print insns in each cycle */
6415 fprintf (dump, "%s\n", visual_tbl);
6418 /* Print insns in the 'no_unit' column of visualization */
6421 visualize_no_unit (insn)
6424 vis_no_unit[n_vis_no_unit] = insn;
6428 /* Print insns scheduled in clock, for visualization. */
6431 visualize_scheduled_insns (b, clock)
6436 /* if no more room, split table into two */
6437 if (n_visual_lines >= MAX_VISUAL_LINES)
6439 print_block_visualization (b, "(incomplete)");
6440 init_block_visualization ();
6445 sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock);
6446 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
6447 if (function_units[unit].bitmask & target_units)
6448 for (i = 0; i < function_units[unit].multiplicity; i++)
6450 int instance = unit + i * FUNCTION_UNITS_SIZE;
6451 rtx insn = unit_last_insn[instance];
6453 /* print insns that still keep the unit busy */
6455 actual_hazard_this_instance (unit, instance, insn, clock, 0))
6458 print_insn (str, insn, 0);
6459 str[INSN_LEN] = '\0';
6460 sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str);
6463 sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------");
6466 /* print insns that are not assigned to any unit */
6467 for (i = 0; i < n_vis_no_unit; i++)
6468 sprintf (visual_tbl + strlen (visual_tbl), " %-8d",
6469 INSN_UID (vis_no_unit[i]));
6472 sprintf (visual_tbl + strlen (visual_tbl), "\n");
6475 /* Print stalled cycles */
6478 visualize_stall_cycles (b, stalls)
6483 /* if no more room, split table into two */
6484 if (n_visual_lines >= MAX_VISUAL_LINES)
6486 print_block_visualization (b, "(incomplete)");
6487 init_block_visualization ();
6492 sprintf (visual_tbl + strlen (visual_tbl), ";; ");
6493 for (i = 0; i < stalls; i++)
6494 sprintf (visual_tbl + strlen (visual_tbl), ".");
6495 sprintf (visual_tbl + strlen (visual_tbl), "\n");
6498 /* move_insn1: Remove INSN from insn chain, and link it after LAST insn */
6501 move_insn1 (insn, last)
6504 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
6505 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
6507 NEXT_INSN (insn) = NEXT_INSN (last);
6508 PREV_INSN (NEXT_INSN (last)) = insn;
6510 NEXT_INSN (last) = insn;
6511 PREV_INSN (insn) = last;
6516 /* Search INSN for fake REG_DEAD note pairs for NOTE_INSN_SETJMP,
6517 NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into
6518 NOTEs. The REG_DEAD note following first one is contains the saved
6519 value for NOTE_BLOCK_NUMBER which is useful for
6520 NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction
6521 output by the instruction scheduler. Return the new value of LAST. */
6524 reemit_notes (insn, last)
6531 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
6533 if (REG_NOTE_KIND (note) == REG_DEAD
6534 && GET_CODE (XEXP (note, 0)) == CONST_INT)
6536 int note_type = INTVAL (XEXP (note, 0));
6537 if (note_type == NOTE_INSN_SETJMP)
6539 retval = emit_note_after (NOTE_INSN_SETJMP, insn);
6540 CONST_CALL_P (retval) = CONST_CALL_P (note);
6541 remove_note (insn, note);
6542 note = XEXP (note, 1);
6544 else if (note_type == NOTE_INSN_RANGE_START
6545 || note_type == NOTE_INSN_RANGE_END)
6547 last = emit_note_before (note_type, last);
6548 remove_note (insn, note);
6549 note = XEXP (note, 1);
6550 NOTE_RANGE_INFO (last) = XEXP (note, 0);
6554 last = emit_note_before (INTVAL (XEXP (note, 0)), last);
6555 remove_note (insn, note);
6556 note = XEXP (note, 1);
6557 NOTE_BLOCK_NUMBER (last) = INTVAL (XEXP (note, 0));
6559 remove_note (insn, note);
6565 /* Move INSN, and all insns which should be issued before it,
6566 due to SCHED_GROUP_P flag. Reemit notes if needed.
6568 Return the last insn emitted by the scheduler, which is the
6569 return value from the first call to reemit_notes. */
6572 move_insn (insn, last)
6577 /* If INSN has SCHED_GROUP_P set, then issue it and any other
6578 insns with SCHED_GROUP_P set first. */
6579 while (SCHED_GROUP_P (insn))
6581 rtx prev = PREV_INSN (insn);
6583 /* Move a SCHED_GROUP_P insn. */
6584 move_insn1 (insn, last);
6585 /* If this is the first call to reemit_notes, then record
6586 its return value. */
6587 if (retval == NULL_RTX)
6588 retval = reemit_notes (insn, insn);
6590 reemit_notes (insn, insn);
6594 /* Now move the first non SCHED_GROUP_P insn. */
6595 move_insn1 (insn, last);
6597 /* If this is the first call to reemit_notes, then record
6598 its return value. */
6599 if (retval == NULL_RTX)
6600 retval = reemit_notes (insn, insn);
6602 reemit_notes (insn, insn);
6607 /* Return an insn which represents a SCHED_GROUP, which is
6608 the last insn in the group. */
6619 insn = next_nonnote_insn (insn);
6621 while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL));
6626 /* Use forward list scheduling to rearrange insns of block BB in region RGN,
6627 possibly bringing insns from subsequent blocks in the same region.
6628 Return number of insns scheduled. */
6631 schedule_block (bb, rgn_n_insns)
6635 /* Local variables. */
6642 /* flow block of this bb */
6643 int b = BB_TO_BLOCK (bb);
6645 /* target_n_insns == number of insns in b before scheduling starts.
6646 sched_target_n_insns == how many of b's insns were scheduled.
6647 sched_n_insns == how many insns were scheduled in b */
6648 int target_n_insns = 0;
6649 int sched_target_n_insns = 0;
6650 int sched_n_insns = 0;
6652 #define NEED_NOTHING 0
6657 /* head/tail info for this block */
6664 /* We used to have code to avoid getting parameters moved from hard
6665 argument registers into pseudos.
6667 However, it was removed when it proved to be of marginal benefit
6668 and caused problems because schedule_block and compute_forward_dependences
6669 had different notions of what the "head" insn was. */
6670 get_block_head_tail (bb, &head, &tail);
6672 /* Interblock scheduling could have moved the original head insn from this
6673 block into a proceeding block. This may also cause schedule_block and
6674 compute_forward_dependences to have different notions of what the
6677 If the interblock movement happened to make this block start with
6678 some notes (LOOP, EH or SETJMP) before the first real insn, then
6679 HEAD will have various special notes attached to it which must be
6680 removed so that we don't end up with extra copies of the notes. */
6681 if (GET_RTX_CLASS (GET_CODE (head)) == 'i')
6685 for (note = REG_NOTES (head); note; note = XEXP (note, 1))
6686 if (REG_NOTE_KIND (note) == REG_DEAD
6687 && GET_CODE (XEXP (note, 0)) == CONST_INT)
6688 remove_note (head, note);
6691 next_tail = NEXT_INSN (tail);
6692 prev_head = PREV_INSN (head);
6694 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
6695 to schedule this block. */
6697 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
6698 return (sched_n_insns);
6703 fprintf (dump, ";; ======================================================\n");
6705 ";; -- basic block %d from %d to %d -- %s reload\n",
6706 b, INSN_UID (basic_block_head[b]),
6707 INSN_UID (basic_block_end[b]),
6708 (reload_completed ? "after" : "before"));
6709 fprintf (dump, ";; ======================================================\n");
6710 fprintf (dump, "\n");
6712 visual_tbl = (char *) alloca (get_visual_tbl_length ());
6713 init_block_visualization ();
6716 /* remove remaining note insns from the block, save them in
6717 note_list. These notes are restored at the end of
6718 schedule_block (). */
6720 rm_other_notes (head, tail);
6724 /* prepare current target block info */
6725 if (current_nr_blocks > 1)
6727 candidate_table = (candidate *) alloca (current_nr_blocks * sizeof (candidate));
6730 /* ??? It is not clear why bblst_size is computed this way. The original
6731 number was clearly too small as it resulted in compiler failures.
6732 Multiplying by the original number by 2 (to account for update_bbs
6733 members) seems to be a reasonable solution. */
6734 /* ??? Or perhaps there is a bug somewhere else in this file? */
6735 bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2;
6736 bblst_table = (int *) alloca (bblst_size * sizeof (int));
6738 bitlst_table_last = 0;
6739 bitlst_table_size = rgn_nr_edges;
6740 bitlst_table = (int *) alloca (rgn_nr_edges * sizeof (int));
6742 compute_trg_info (bb);
6747 /* Allocate the ready list */
6748 ready = (rtx *) alloca ((rgn_n_insns + 1) * sizeof (rtx));
6750 /* Print debugging information. */
6751 if (sched_verbose >= 5)
6752 debug_dependencies ();
6755 /* Initialize ready list with all 'ready' insns in target block.
6756 Count number of insns in the target block being scheduled. */
6758 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6762 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6764 next = NEXT_INSN (insn);
6766 if (INSN_DEP_COUNT (insn) == 0
6767 && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
6768 ready[n_ready++] = insn;
6769 if (!(SCHED_GROUP_P (insn)))
6773 /* Add to ready list all 'ready' insns in valid source blocks.
6774 For speculative insns, check-live, exception-free, and
6776 for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++)
6777 if (IS_VALID (bb_src))
6783 get_block_head_tail (bb_src, &head, &tail);
6784 src_next_tail = NEXT_INSN (tail);
6788 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
6791 for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn))
6793 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6796 if (!CANT_MOVE (insn)
6797 && (!IS_SPECULATIVE_INSN (insn)
6798 || (insn_issue_delay (insn) <= 3
6799 && check_live (insn, bb_src)
6800 && is_exception_free (insn, bb_src, target_bb))))
6805 next = NEXT_INSN (insn);
6806 if (INSN_DEP_COUNT (insn) == 0
6807 && (SCHED_GROUP_P (next) == 0
6808 || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
6809 ready[n_ready++] = insn;
6814 #ifdef MD_SCHED_INIT
6815 MD_SCHED_INIT (dump, sched_verbose);
6818 /* no insns scheduled in this block yet */
6819 last_scheduled_insn = 0;
6821 /* Sort the ready list */
6822 SCHED_SORT (ready, n_ready);
6823 #ifdef MD_SCHED_REORDER
6824 MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready);
6827 if (sched_verbose >= 2)
6829 fprintf (dump, ";;\t\tReady list initially: ");
6830 debug_ready_list (ready, n_ready);
6833 /* Q_SIZE is the total number of insns in the queue. */
6838 bzero ((char *) insn_queue, sizeof (insn_queue));
6840 /* We start inserting insns after PREV_HEAD. */
6843 /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */
6844 new_needs = (NEXT_INSN (prev_head) == basic_block_head[b]
6845 ? NEED_HEAD : NEED_NOTHING);
6846 if (PREV_INSN (next_tail) == basic_block_end[b])
6847 new_needs |= NEED_TAIL;
6849 /* loop until all the insns in BB are scheduled. */
6850 while (sched_target_n_insns < target_n_insns)
6856 /* Add to the ready list all pending insns that can be issued now.
6857 If there are no ready insns, increment clock until one
6858 is ready and add all pending insns at that point to the ready
6860 n_ready = queue_to_ready (ready, n_ready);
6865 if (sched_verbose >= 2)
6867 fprintf (dump, ";;\t\tReady list after queue_to_ready: ");
6868 debug_ready_list (ready, n_ready);
6871 /* Sort the ready list. */
6872 SCHED_SORT (ready, n_ready);
6873 #ifdef MD_SCHED_REORDER
6874 MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready);
6879 fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var);
6880 debug_ready_list (ready, n_ready);
6883 /* Issue insns from ready list.
6884 It is important to count down from n_ready, because n_ready may change
6885 as insns are issued. */
6886 can_issue_more = issue_rate;
6887 for (i = n_ready - 1; i >= 0 && can_issue_more; i--)
6889 rtx insn = ready[i];
6890 int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0);
6894 queue_insn (insn, cost);
6895 ready[i] = ready[--n_ready]; /* remove insn from ready list */
6899 /* an interblock motion? */
6900 if (INSN_BB (insn) != target_bb)
6904 if (IS_SPECULATIVE_INSN (insn))
6907 if (!check_live (insn, INSN_BB (insn)))
6909 /* speculative motion, live check failed, remove
6910 insn from ready list */
6911 ready[i] = ready[--n_ready];
6914 update_live (insn, INSN_BB (insn));
6916 /* for speculative load, mark insns fed by it. */
6917 if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn))
6918 set_spec_fed (insn);
6925 while (SCHED_GROUP_P (temp))
6926 temp = PREV_INSN (temp);
6928 /* Update source block boundaries. */
6929 b1 = INSN_BLOCK (temp);
6930 if (temp == basic_block_head[b1]
6931 && insn == basic_block_end[b1])
6933 /* We moved all the insns in the basic block.
6934 Emit a note after the last insn and update the
6935 begin/end boundaries to point to the note. */
6936 emit_note_after (NOTE_INSN_DELETED, insn);
6937 basic_block_end[b1] = NEXT_INSN (insn);
6938 basic_block_head[b1] = NEXT_INSN (insn);
6940 else if (insn == basic_block_end[b1])
6942 /* We took insns from the end of the basic block,
6943 so update the end of block boundary so that it
6944 points to the first insn we did not move. */
6945 basic_block_end[b1] = PREV_INSN (temp);
6947 else if (temp == basic_block_head[b1])
6949 /* We took insns from the start of the basic block,
6950 so update the start of block boundary so that
6951 it points to the first insn we did not move. */
6952 basic_block_head[b1] = NEXT_INSN (insn);
6957 /* in block motion */
6958 sched_target_n_insns++;
6961 last_scheduled_insn = insn;
6962 last = move_insn (insn, last);
6965 #ifdef MD_SCHED_VARIABLE_ISSUE
6966 MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, can_issue_more);
6971 n_ready = schedule_insn (insn, ready, n_ready, clock_var);
6973 /* remove insn from ready list */
6974 ready[i] = ready[--n_ready];
6976 /* close this block after scheduling its jump */
6977 if (GET_CODE (last_scheduled_insn) == JUMP_INSN)
6985 visualize_scheduled_insns (b, clock_var);
6992 fprintf (dump, ";;\tReady list (final): ");
6993 debug_ready_list (ready, n_ready);
6994 print_block_visualization (b, "");
6997 /* Sanity check -- queue must be empty now. Meaningless if region has
6999 if (current_nr_blocks > 1)
7000 if (!flag_schedule_interblock && q_size != 0)
7003 /* update head/tail boundaries. */
7004 head = NEXT_INSN (prev_head);
7007 /* Restore-other-notes: NOTE_LIST is the end of a chain of notes
7008 previously found among the insns. Insert them at the beginning
7012 rtx note_head = note_list;
7014 while (PREV_INSN (note_head))
7016 note_head = PREV_INSN (note_head);
7019 PREV_INSN (note_head) = PREV_INSN (head);
7020 NEXT_INSN (PREV_INSN (head)) = note_head;
7021 PREV_INSN (head) = note_list;
7022 NEXT_INSN (note_list) = head;
7026 /* update target block boundaries. */
7027 if (new_needs & NEED_HEAD)
7028 basic_block_head[b] = head;
7030 if (new_needs & NEED_TAIL)
7031 basic_block_end[b] = tail;
7036 fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n",
7037 clock_var, INSN_UID (basic_block_head[b]));
7038 fprintf (dump, ";; new basic block end = %d\n\n",
7039 INSN_UID (basic_block_end[b]));
7042 return (sched_n_insns);
7043 } /* schedule_block () */
7046 /* print the bit-set of registers, S. callable from debugger */
7049 debug_reg_vector (s)
7054 EXECUTE_IF_SET_IN_REG_SET (s, 0, regno,
7056 fprintf (dump, " %d", regno);
7059 fprintf (dump, "\n");
7062 /* Use the backward dependences from LOG_LINKS to build
7063 forward dependences in INSN_DEPEND. */
7066 compute_block_forward_dependences (bb)
7072 enum reg_note dep_type;
7074 get_block_head_tail (bb, &head, &tail);
7075 next_tail = NEXT_INSN (tail);
7076 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7078 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7081 insn = group_leader (insn);
7083 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
7085 rtx x = group_leader (XEXP (link, 0));
7088 if (x != XEXP (link, 0))
7091 /* Ignore dependences upon deleted insn */
7092 if (GET_CODE (x) == NOTE || INSN_DELETED_P (x))
7094 if (find_insn_list (insn, INSN_DEPEND (x)))
7097 new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x));
7099 dep_type = REG_NOTE_KIND (link);
7100 PUT_REG_NOTE_KIND (new_link, dep_type);
7102 INSN_DEPEND (x) = new_link;
7103 INSN_DEP_COUNT (insn) += 1;
7108 /* Initialize variables for region data dependence analysis.
7109 n_bbs is the number of region blocks */
7111 __inline static void
7112 init_rgn_data_dependences (n_bbs)
7117 /* variables for which one copy exists for each block */
7118 bzero ((char *) bb_pending_read_insns, n_bbs * sizeof (rtx));
7119 bzero ((char *) bb_pending_read_mems, n_bbs * sizeof (rtx));
7120 bzero ((char *) bb_pending_write_insns, n_bbs * sizeof (rtx));
7121 bzero ((char *) bb_pending_write_mems, n_bbs * sizeof (rtx));
7122 bzero ((char *) bb_pending_lists_length, n_bbs * sizeof (rtx));
7123 bzero ((char *) bb_last_pending_memory_flush, n_bbs * sizeof (rtx));
7124 bzero ((char *) bb_last_function_call, n_bbs * sizeof (rtx));
7125 bzero ((char *) bb_sched_before_next_call, n_bbs * sizeof (rtx));
7127 /* Create an insn here so that we can hang dependencies off of it later. */
7128 for (bb = 0; bb < n_bbs; bb++)
7130 bb_sched_before_next_call[bb] =
7131 gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX,
7132 NULL_RTX, 0, NULL_RTX, NULL_RTX);
7133 LOG_LINKS (bb_sched_before_next_call[bb]) = 0;
7137 /* Add dependences so that branches are scheduled to run last in their block */
7140 add_branch_dependences (head, tail)
7146 /* For all branches, calls, uses, and cc0 setters, force them to remain
7147 in order at the end of the block by adding dependencies and giving
7148 the last a high priority. There may be notes present, and prev_head
7151 Branches must obviously remain at the end. Calls should remain at the
7152 end since moving them results in worse register allocation. Uses remain
7153 at the end to ensure proper register allocation. cc0 setters remaim
7154 at the end because they can't be moved away from their cc0 user. */
7157 while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN
7158 || (GET_CODE (insn) == INSN
7159 && (GET_CODE (PATTERN (insn)) == USE
7161 || sets_cc0_p (PATTERN (insn))
7164 || GET_CODE (insn) == NOTE)
7166 if (GET_CODE (insn) != NOTE)
7169 && !find_insn_list (insn, LOG_LINKS (last)))
7171 add_dependence (last, insn, REG_DEP_ANTI);
7172 INSN_REF_COUNT (insn)++;
7175 CANT_MOVE (insn) = 1;
7178 /* Skip over insns that are part of a group.
7179 Make each insn explicitly depend on the previous insn.
7180 This ensures that only the group header will ever enter
7181 the ready queue (and, when scheduled, will automatically
7182 schedule the SCHED_GROUP_P block). */
7183 while (SCHED_GROUP_P (insn))
7185 rtx temp = prev_nonnote_insn (insn);
7186 add_dependence (insn, temp, REG_DEP_ANTI);
7191 /* Don't overrun the bounds of the basic block. */
7195 insn = PREV_INSN (insn);
7198 /* make sure these insns are scheduled last in their block */
7201 while (insn != head)
7203 insn = prev_nonnote_insn (insn);
7205 if (INSN_REF_COUNT (insn) != 0)
7208 if (!find_insn_list (last, LOG_LINKS (insn)))
7209 add_dependence (last, insn, REG_DEP_ANTI);
7210 INSN_REF_COUNT (insn) = 1;
7212 /* Skip over insns that are part of a group. */
7213 while (SCHED_GROUP_P (insn))
7214 insn = prev_nonnote_insn (insn);
7218 /* Compute bacward dependences inside BB. In a multiple blocks region:
7219 (1) a bb is analyzed after its predecessors, and (2) the lists in
7220 effect at the end of bb (after analyzing for bb) are inherited by
7223 Specifically for reg-reg data dependences, the block insns are
7224 scanned by sched_analyze () top-to-bottom. Two lists are
7225 naintained by sched_analyze (): reg_last_defs[] for register DEFs,
7226 and reg_last_uses[] for register USEs.
7228 When analysis is completed for bb, we update for its successors:
7229 ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb])
7230 ; - USES[succ] = Union (USES [succ], DEFS [bb])
7232 The mechanism for computing mem-mem data dependence is very
7233 similar, and the result is interblock dependences in the region. */
7236 compute_block_backward_dependences (bb)
7242 int max_reg = max_reg_num ();
7244 b = BB_TO_BLOCK (bb);
7246 if (current_nr_blocks == 1)
7248 reg_last_uses = (rtx *) alloca (max_reg * sizeof (rtx));
7249 reg_last_sets = (rtx *) alloca (max_reg * sizeof (rtx));
7251 bzero ((char *) reg_last_uses, max_reg * sizeof (rtx));
7252 bzero ((char *) reg_last_sets, max_reg * sizeof (rtx));
7254 pending_read_insns = 0;
7255 pending_read_mems = 0;
7256 pending_write_insns = 0;
7257 pending_write_mems = 0;
7258 pending_lists_length = 0;
7259 last_function_call = 0;
7260 last_pending_memory_flush = 0;
7261 sched_before_next_call
7262 = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX,
7263 NULL_RTX, 0, NULL_RTX, NULL_RTX);
7264 LOG_LINKS (sched_before_next_call) = 0;
7268 reg_last_uses = bb_reg_last_uses[bb];
7269 reg_last_sets = bb_reg_last_sets[bb];
7271 pending_read_insns = bb_pending_read_insns[bb];
7272 pending_read_mems = bb_pending_read_mems[bb];
7273 pending_write_insns = bb_pending_write_insns[bb];
7274 pending_write_mems = bb_pending_write_mems[bb];
7275 pending_lists_length = bb_pending_lists_length[bb];
7276 last_function_call = bb_last_function_call[bb];
7277 last_pending_memory_flush = bb_last_pending_memory_flush[bb];
7279 sched_before_next_call = bb_sched_before_next_call[bb];
7282 /* do the analysis for this block */
7283 get_block_head_tail (bb, &head, &tail);
7284 sched_analyze (head, tail);
7285 add_branch_dependences (head, tail);
7287 if (current_nr_blocks > 1)
7290 int b_succ, bb_succ;
7292 rtx link_insn, link_mem;
7295 /* these lists should point to the right place, for correct freeing later. */
7296 bb_pending_read_insns[bb] = pending_read_insns;
7297 bb_pending_read_mems[bb] = pending_read_mems;
7298 bb_pending_write_insns[bb] = pending_write_insns;
7299 bb_pending_write_mems[bb] = pending_write_mems;
7301 /* bb's structures are inherited by it's successors */
7302 first_edge = e = OUT_EDGES (b);
7306 b_succ = TO_BLOCK (e);
7307 bb_succ = BLOCK_TO_BB (b_succ);
7309 /* only bbs "below" bb, in the same region, are interesting */
7310 if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ)
7317 for (reg = 0; reg < max_reg; reg++)
7320 /* reg-last-uses lists are inherited by bb_succ */
7321 for (u = reg_last_uses[reg]; u; u = XEXP (u, 1))
7323 if (find_insn_list (XEXP (u, 0), (bb_reg_last_uses[bb_succ])[reg]))
7326 (bb_reg_last_uses[bb_succ])[reg]
7327 = alloc_INSN_LIST (XEXP (u, 0),
7328 (bb_reg_last_uses[bb_succ])[reg]);
7331 /* reg-last-defs lists are inherited by bb_succ */
7332 for (u = reg_last_sets[reg]; u; u = XEXP (u, 1))
7334 if (find_insn_list (XEXP (u, 0), (bb_reg_last_sets[bb_succ])[reg]))
7337 (bb_reg_last_sets[bb_succ])[reg]
7338 = alloc_INSN_LIST (XEXP (u, 0),
7339 (bb_reg_last_sets[bb_succ])[reg]);
7343 /* mem read/write lists are inherited by bb_succ */
7344 link_insn = pending_read_insns;
7345 link_mem = pending_read_mems;
7348 if (!(find_insn_mem_list (XEXP (link_insn, 0), XEXP (link_mem, 0),
7349 bb_pending_read_insns[bb_succ],
7350 bb_pending_read_mems[bb_succ])))
7351 add_insn_mem_dependence (&bb_pending_read_insns[bb_succ],
7352 &bb_pending_read_mems[bb_succ],
7353 XEXP (link_insn, 0), XEXP (link_mem, 0));
7354 link_insn = XEXP (link_insn, 1);
7355 link_mem = XEXP (link_mem, 1);
7358 link_insn = pending_write_insns;
7359 link_mem = pending_write_mems;
7362 if (!(find_insn_mem_list (XEXP (link_insn, 0), XEXP (link_mem, 0),
7363 bb_pending_write_insns[bb_succ],
7364 bb_pending_write_mems[bb_succ])))
7365 add_insn_mem_dependence (&bb_pending_write_insns[bb_succ],
7366 &bb_pending_write_mems[bb_succ],
7367 XEXP (link_insn, 0), XEXP (link_mem, 0));
7369 link_insn = XEXP (link_insn, 1);
7370 link_mem = XEXP (link_mem, 1);
7373 /* last_function_call is inherited by bb_succ */
7374 for (u = last_function_call; u; u = XEXP (u, 1))
7376 if (find_insn_list (XEXP (u, 0), bb_last_function_call[bb_succ]))
7379 bb_last_function_call[bb_succ]
7380 = alloc_INSN_LIST (XEXP (u, 0),
7381 bb_last_function_call[bb_succ]);
7384 /* last_pending_memory_flush is inherited by bb_succ */
7385 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
7387 if (find_insn_list (XEXP (u, 0), bb_last_pending_memory_flush[bb_succ]))
7390 bb_last_pending_memory_flush[bb_succ]
7391 = alloc_INSN_LIST (XEXP (u, 0),
7392 bb_last_pending_memory_flush[bb_succ]);
7395 /* sched_before_next_call is inherited by bb_succ */
7396 x = LOG_LINKS (sched_before_next_call);
7397 for (; x; x = XEXP (x, 1))
7398 add_dependence (bb_sched_before_next_call[bb_succ],
7399 XEXP (x, 0), REG_DEP_ANTI);
7403 while (e != first_edge);
7406 /* Free up the INSN_LISTs
7408 Note this loop is executed max_reg * nr_regions times. It's first
7409 implementation accounted for over 90% of the calls to free_list.
7410 The list was empty for the vast majority of those calls. On the PA,
7411 not calling free_list in those cases improves -O2 compile times by
7413 for (b = 0; b < max_reg; ++b)
7415 if (reg_last_sets[b])
7416 free_list (®_last_sets[b], &unused_insn_list);
7417 if (reg_last_uses[b])
7418 free_list (®_last_uses[b], &unused_insn_list);
7421 /* Assert that we won't need bb_reg_last_* for this block anymore. */
7422 if (current_nr_blocks > 1)
7424 bb_reg_last_uses[bb] = (rtx *) NULL_RTX;
7425 bb_reg_last_sets[bb] = (rtx *) NULL_RTX;
7429 /* Print dependences for debugging, callable from debugger */
7432 debug_dependencies ()
7436 fprintf (dump, ";; --------------- forward dependences: ------------ \n");
7437 for (bb = 0; bb < current_nr_blocks; bb++)
7445 get_block_head_tail (bb, &head, &tail);
7446 next_tail = NEXT_INSN (tail);
7447 fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n",
7448 BB_TO_BLOCK (bb), bb);
7450 fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
7451 "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units");
7452 fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
7453 "----", "----", "--", "---", "----", "----", "--------", "-----");
7454 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7459 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7462 fprintf (dump, ";; %6d ", INSN_UID (insn));
7463 if (GET_CODE (insn) == NOTE)
7465 n = NOTE_LINE_NUMBER (insn);
7467 fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n));
7469 fprintf (dump, "line %d, file %s\n", n,
7470 NOTE_SOURCE_FILE (insn));
7473 fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn)));
7477 unit = insn_unit (insn);
7479 || function_units[unit].blockage_range_function == 0) ? 0 :
7480 function_units[unit].blockage_range_function (insn);
7482 ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ",
7483 (SCHED_GROUP_P (insn) ? "+" : " "),
7487 INSN_DEP_COUNT (insn),
7488 INSN_PRIORITY (insn),
7489 insn_cost (insn, 0, 0),
7490 (int) MIN_BLOCKAGE_COST (range),
7491 (int) MAX_BLOCKAGE_COST (range));
7492 insn_print_units (insn);
7493 fprintf (dump, "\t: ");
7494 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
7495 fprintf (dump, "%d ", INSN_UID (XEXP (link, 0)));
7496 fprintf (dump, "\n");
7500 fprintf (dump, "\n");
7503 /* Set_priorities: compute priority of each insn in the block */
7516 get_block_head_tail (bb, &head, &tail);
7517 prev_head = PREV_INSN (head);
7520 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
7524 for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
7527 if (GET_CODE (insn) == NOTE)
7530 if (!(SCHED_GROUP_P (insn)))
7532 (void) priority (insn);
7538 /* Make each element of VECTOR point at an rtx-vector,
7539 taking the space for all those rtx-vectors from SPACE.
7540 SPACE is of type (rtx *), but it is really as long as NELTS rtx-vectors.
7541 BYTES_PER_ELT is the number of bytes in one rtx-vector.
7542 (this is the same as init_regset_vector () in flow.c) */
7545 init_rtx_vector (vector, space, nelts, bytes_per_elt)
7552 register rtx *p = space;
7554 for (i = 0; i < nelts; i++)
7557 p += bytes_per_elt / sizeof (*p);
7561 /* Schedule a region. A region is either an inner loop, a loop-free
7562 subroutine, or a single basic block. Each bb in the region is
7563 scheduled after its flow predecessors. */
7566 schedule_region (rgn)
7570 int rgn_n_insns = 0;
7571 int sched_rgn_n_insns = 0;
7573 /* set variables for the current region */
7574 current_nr_blocks = RGN_NR_BLOCKS (rgn);
7575 current_blocks = RGN_BLOCKS (rgn);
7577 reg_pending_sets = ALLOCA_REG_SET ();
7578 reg_pending_sets_all = 0;
7580 /* initializations for region data dependence analyisis */
7581 if (current_nr_blocks > 1)
7584 int maxreg = max_reg_num ();
7586 bb_reg_last_uses = (rtx **) alloca (current_nr_blocks * sizeof (rtx *));
7587 space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx));
7588 bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx));
7589 init_rtx_vector (bb_reg_last_uses, space, current_nr_blocks, maxreg * sizeof (rtx *));
7591 bb_reg_last_sets = (rtx **) alloca (current_nr_blocks * sizeof (rtx *));
7592 space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx));
7593 bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx));
7594 init_rtx_vector (bb_reg_last_sets, space, current_nr_blocks, maxreg * sizeof (rtx *));
7596 bb_pending_read_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7597 bb_pending_read_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7598 bb_pending_write_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7599 bb_pending_write_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7600 bb_pending_lists_length = (int *) alloca (current_nr_blocks * sizeof (int));
7601 bb_last_pending_memory_flush = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7602 bb_last_function_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7603 bb_sched_before_next_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7605 init_rgn_data_dependences (current_nr_blocks);
7608 /* compute LOG_LINKS */
7609 for (bb = 0; bb < current_nr_blocks; bb++)
7610 compute_block_backward_dependences (bb);
7612 /* compute INSN_DEPEND */
7613 for (bb = current_nr_blocks - 1; bb >= 0; bb--)
7614 compute_block_forward_dependences (bb);
7616 /* Delete line notes, compute live-regs at block end, and set priorities. */
7618 for (bb = 0; bb < current_nr_blocks; bb++)
7620 if (reload_completed == 0)
7621 find_pre_sched_live (bb);
7623 if (write_symbols != NO_DEBUG)
7625 save_line_notes (bb);
7629 rgn_n_insns += set_priorities (bb);
7632 /* compute interblock info: probabilities, split-edges, dominators, etc. */
7633 if (current_nr_blocks > 1)
7637 prob = (float *) alloca ((current_nr_blocks) * sizeof (float));
7639 bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1;
7640 dom = (bbset *) alloca (current_nr_blocks * sizeof (bbset));
7641 for (i = 0; i < current_nr_blocks; i++)
7643 dom[i] = (bbset) alloca (bbset_size * sizeof (HOST_WIDE_INT));
7644 bzero ((char *) dom[i], bbset_size * sizeof (HOST_WIDE_INT));
7649 edge_to_bit = (int *) alloca (nr_edges * sizeof (int));
7650 for (i = 1; i < nr_edges; i++)
7651 if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn)
7652 EDGE_TO_BIT (i) = rgn_nr_edges++;
7653 rgn_edges = (int *) alloca (rgn_nr_edges * sizeof (int));
7656 for (i = 1; i < nr_edges; i++)
7657 if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn))
7658 rgn_edges[rgn_nr_edges++] = i;
7661 edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1;
7662 pot_split = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset));
7663 ancestor_edges = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset));
7664 for (i = 0; i < current_nr_blocks; i++)
7667 (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT));
7668 bzero ((char *) pot_split[i],
7669 edgeset_size * sizeof (HOST_WIDE_INT));
7671 (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT));
7672 bzero ((char *) ancestor_edges[i],
7673 edgeset_size * sizeof (HOST_WIDE_INT));
7676 /* compute probabilities, dominators, split_edges */
7677 for (bb = 0; bb < current_nr_blocks; bb++)
7678 compute_dom_prob_ps (bb);
7681 /* now we can schedule all blocks */
7682 for (bb = 0; bb < current_nr_blocks; bb++)
7684 sched_rgn_n_insns += schedule_block (bb, rgn_n_insns);
7691 /* sanity check: verify that all region insns were scheduled */
7692 if (sched_rgn_n_insns != rgn_n_insns)
7695 /* update register life and usage information */
7696 if (reload_completed == 0)
7698 for (bb = current_nr_blocks - 1; bb >= 0; bb--)
7699 find_post_sched_live (bb);
7701 if (current_nr_blocks <= 1)
7702 /* Sanity check. There should be no REG_DEAD notes leftover at the end.
7703 In practice, this can occur as the result of bugs in flow, combine.c,
7704 and/or sched.c. The values of the REG_DEAD notes remaining are
7705 meaningless, because dead_notes is just used as a free list. */
7706 if (dead_notes != 0)
7710 /* restore line notes. */
7711 if (write_symbols != NO_DEBUG)
7713 for (bb = 0; bb < current_nr_blocks; bb++)
7714 restore_line_notes (bb);
7717 /* Done with this region */
7718 free_pending_lists ();
7720 FREE_REG_SET (reg_pending_sets);
7723 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
7724 REGNO, returning the rtx of the reference found if any. Otherwise,
7728 regno_use_in (regno, x)
7736 if (GET_CODE (x) == REG && REGNO (x) == regno)
7739 fmt = GET_RTX_FORMAT (GET_CODE (x));
7740 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7744 if ((tem = regno_use_in (regno, XEXP (x, i))))
7747 else if (fmt[i] == 'E')
7748 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7749 if ((tem = regno_use_in (regno, XVECEXP (x, i, j))))
7756 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
7757 needed for the hard register mentioned in the note. This can happen
7758 if the reference to the hard register in the original insn was split into
7759 several smaller hard register references in the split insns. */
7762 split_hard_reg_notes (note, first, last)
7763 rtx note, first, last;
7765 rtx reg, temp, link;
7766 int n_regs, i, new_reg;
7769 /* Assume that this is a REG_DEAD note. */
7770 if (REG_NOTE_KIND (note) != REG_DEAD)
7773 reg = XEXP (note, 0);
7775 n_regs = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
7777 for (i = 0; i < n_regs; i++)
7779 new_reg = REGNO (reg) + i;
7781 /* Check for references to new_reg in the split insns. */
7782 for (insn = last;; insn = PREV_INSN (insn))
7784 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
7785 && (temp = regno_use_in (new_reg, PATTERN (insn))))
7787 /* Create a new reg dead note ere. */
7788 link = alloc_EXPR_LIST (REG_DEAD, temp, REG_NOTES (insn));
7789 REG_NOTES (insn) = link;
7791 /* If killed multiple registers here, then add in the excess. */
7792 i += HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) - 1;
7796 /* It isn't mentioned anywhere, so no new reg note is needed for
7804 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
7805 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
7808 new_insn_dead_notes (pat, insn, last, orig_insn)
7809 rtx pat, insn, last, orig_insn;
7813 /* PAT is either a CLOBBER or a SET here. */
7814 dest = XEXP (pat, 0);
7816 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
7817 || GET_CODE (dest) == STRICT_LOW_PART
7818 || GET_CODE (dest) == SIGN_EXTRACT)
7819 dest = XEXP (dest, 0);
7821 if (GET_CODE (dest) == REG)
7823 /* If the original insn already used this register, we may not add new
7824 notes for it. One example for a split that needs this test is
7825 when a multi-word memory access with register-indirect addressing
7826 is split into multiple memory accesses with auto-increment and
7827 one adjusting add instruction for the address register. */
7828 if (reg_referenced_p (dest, PATTERN (orig_insn)))
7830 for (tem = last; tem != insn; tem = PREV_INSN (tem))
7832 if (GET_RTX_CLASS (GET_CODE (tem)) == 'i'
7833 && reg_overlap_mentioned_p (dest, PATTERN (tem))
7834 && (set = single_set (tem)))
7836 rtx tem_dest = SET_DEST (set);
7838 while (GET_CODE (tem_dest) == ZERO_EXTRACT
7839 || GET_CODE (tem_dest) == SUBREG
7840 || GET_CODE (tem_dest) == STRICT_LOW_PART
7841 || GET_CODE (tem_dest) == SIGN_EXTRACT)
7842 tem_dest = XEXP (tem_dest, 0);
7844 if (!rtx_equal_p (tem_dest, dest))
7846 /* Use the same scheme as combine.c, don't put both REG_DEAD
7847 and REG_UNUSED notes on the same insn. */
7848 if (!find_regno_note (tem, REG_UNUSED, REGNO (dest))
7849 && !find_regno_note (tem, REG_DEAD, REGNO (dest)))
7851 rtx note = alloc_EXPR_LIST (REG_DEAD, dest,
7853 REG_NOTES (tem) = note;
7855 /* The reg only dies in one insn, the last one that uses
7859 else if (reg_overlap_mentioned_p (dest, SET_SRC (set)))
7860 /* We found an instruction that both uses the register,
7861 and sets it, so no new REG_NOTE is needed for this set. */
7865 /* If this is a set, it must die somewhere, unless it is the dest of
7866 the original insn, and hence is live after the original insn. Abort
7867 if it isn't supposed to be live after the original insn.
7869 If this is a clobber, then just add a REG_UNUSED note. */
7872 int live_after_orig_insn = 0;
7873 rtx pattern = PATTERN (orig_insn);
7876 if (GET_CODE (pat) == CLOBBER)
7878 rtx note = alloc_EXPR_LIST (REG_UNUSED, dest, REG_NOTES (insn));
7879 REG_NOTES (insn) = note;
7883 /* The original insn could have multiple sets, so search the
7884 insn for all sets. */
7885 if (GET_CODE (pattern) == SET)
7887 if (reg_overlap_mentioned_p (dest, SET_DEST (pattern)))
7888 live_after_orig_insn = 1;
7890 else if (GET_CODE (pattern) == PARALLEL)
7892 for (i = 0; i < XVECLEN (pattern, 0); i++)
7893 if (GET_CODE (XVECEXP (pattern, 0, i)) == SET
7894 && reg_overlap_mentioned_p (dest,
7895 SET_DEST (XVECEXP (pattern,
7897 live_after_orig_insn = 1;
7900 if (!live_after_orig_insn)
7906 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
7907 registers modified by X. INC is -1 if the containing insn is being deleted,
7908 and is 1 if the containing insn is a newly generated insn. */
7911 update_n_sets (x, inc)
7915 rtx dest = SET_DEST (x);
7917 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
7918 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
7919 dest = SUBREG_REG (dest);
7921 if (GET_CODE (dest) == REG)
7923 int regno = REGNO (dest);
7925 if (regno < FIRST_PSEUDO_REGISTER)
7928 int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest));
7930 for (i = regno; i < endregno; i++)
7931 REG_N_SETS (i) += inc;
7934 REG_N_SETS (regno) += inc;
7938 /* Updates all flow-analysis related quantities (including REG_NOTES) for
7939 the insns from FIRST to LAST inclusive that were created by splitting
7940 ORIG_INSN. NOTES are the original REG_NOTES. */
7943 update_flow_info (notes, first, last, orig_insn)
7950 rtx orig_dest, temp;
7953 /* Get and save the destination set by the original insn. */
7955 orig_dest = single_set (orig_insn);
7957 orig_dest = SET_DEST (orig_dest);
7959 /* Move REG_NOTES from the original insn to where they now belong. */
7961 for (note = notes; note; note = next)
7963 next = XEXP (note, 1);
7964 switch (REG_NOTE_KIND (note))
7968 /* Move these notes from the original insn to the last new insn where
7969 the register is now set. */
7971 for (insn = last;; insn = PREV_INSN (insn))
7973 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
7974 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
7976 /* If this note refers to a multiple word hard register, it
7977 may have been split into several smaller hard register
7978 references, so handle it specially. */
7979 temp = XEXP (note, 0);
7980 if (REG_NOTE_KIND (note) == REG_DEAD
7981 && GET_CODE (temp) == REG
7982 && REGNO (temp) < FIRST_PSEUDO_REGISTER
7983 && HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) > 1)
7984 split_hard_reg_notes (note, first, last);
7987 XEXP (note, 1) = REG_NOTES (insn);
7988 REG_NOTES (insn) = note;
7991 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
7993 /* ??? This won't handle multiple word registers correctly,
7994 but should be good enough for now. */
7995 if (REG_NOTE_KIND (note) == REG_UNUSED
7996 && GET_CODE (XEXP (note, 0)) != SCRATCH
7997 && !dead_or_set_p (insn, XEXP (note, 0)))
7998 PUT_REG_NOTE_KIND (note, REG_DEAD);
8000 /* The reg only dies in one insn, the last one that uses
8004 /* It must die somewhere, fail it we couldn't find where it died.
8006 If this is a REG_UNUSED note, then it must be a temporary
8007 register that was not needed by this instantiation of the
8008 pattern, so we can safely ignore it. */
8011 /* After reload, REG_DEAD notes come sometimes an
8012 instruction after the register actually dies. */
8013 if (reload_completed && REG_NOTE_KIND (note) == REG_DEAD)
8015 XEXP (note, 1) = REG_NOTES (insn);
8016 REG_NOTES (insn) = note;
8020 if (REG_NOTE_KIND (note) != REG_UNUSED)
8029 /* If the insn that set the register to 0 was deleted, this
8030 note cannot be relied on any longer. The destination might
8031 even have been moved to memory.
8032 This was observed for SH4 with execute/920501-6.c compilation,
8033 -O2 -fomit-frame-pointer -finline-functions . */
8034 if (GET_CODE (XEXP (note, 0)) == NOTE
8035 || INSN_DELETED_P (XEXP (note, 0)))
8037 /* This note applies to the dest of the original insn. Find the
8038 first new insn that now has the same dest, and move the note
8044 for (insn = first;; insn = NEXT_INSN (insn))
8046 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8047 && (temp = single_set (insn))
8048 && rtx_equal_p (SET_DEST (temp), orig_dest))
8050 XEXP (note, 1) = REG_NOTES (insn);
8051 REG_NOTES (insn) = note;
8052 /* The reg is only zero before one insn, the first that
8056 /* If this note refers to a multiple word hard
8057 register, it may have been split into several smaller
8058 hard register references. We could split the notes,
8059 but simply dropping them is good enough. */
8060 if (GET_CODE (orig_dest) == REG
8061 && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER
8062 && HARD_REGNO_NREGS (REGNO (orig_dest),
8063 GET_MODE (orig_dest)) > 1)
8065 /* It must be set somewhere, fail if we couldn't find where it
8074 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
8075 set is meaningless. Just drop the note. */
8079 case REG_NO_CONFLICT:
8080 /* These notes apply to the dest of the original insn. Find the last
8081 new insn that now has the same dest, and move the note there. */
8086 for (insn = last;; insn = PREV_INSN (insn))
8088 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8089 && (temp = single_set (insn))
8090 && rtx_equal_p (SET_DEST (temp), orig_dest))
8092 XEXP (note, 1) = REG_NOTES (insn);
8093 REG_NOTES (insn) = note;
8094 /* Only put this note on one of the new insns. */
8098 /* The original dest must still be set someplace. Abort if we
8099 couldn't find it. */
8102 /* However, if this note refers to a multiple word hard
8103 register, it may have been split into several smaller
8104 hard register references. We could split the notes,
8105 but simply dropping them is good enough. */
8106 if (GET_CODE (orig_dest) == REG
8107 && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER
8108 && HARD_REGNO_NREGS (REGNO (orig_dest),
8109 GET_MODE (orig_dest)) > 1)
8111 /* Likewise for multi-word memory references. */
8112 if (GET_CODE (orig_dest) == MEM
8113 && SIZE_FOR_MODE (orig_dest) > UNITS_PER_WORD)
8121 /* Move a REG_LIBCALL note to the first insn created, and update
8122 the corresponding REG_RETVAL note. */
8123 XEXP (note, 1) = REG_NOTES (first);
8124 REG_NOTES (first) = note;
8126 insn = XEXP (note, 0);
8127 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
8129 XEXP (note, 0) = first;
8132 case REG_EXEC_COUNT:
8133 /* Move a REG_EXEC_COUNT note to the first insn created. */
8134 XEXP (note, 1) = REG_NOTES (first);
8135 REG_NOTES (first) = note;
8139 /* Move a REG_RETVAL note to the last insn created, and update
8140 the corresponding REG_LIBCALL note. */
8141 XEXP (note, 1) = REG_NOTES (last);
8142 REG_NOTES (last) = note;
8144 insn = XEXP (note, 0);
8145 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
8147 XEXP (note, 0) = last;
8152 /* This should be moved to whichever instruction is a JUMP_INSN. */
8154 for (insn = last;; insn = PREV_INSN (insn))
8156 if (GET_CODE (insn) == JUMP_INSN)
8158 XEXP (note, 1) = REG_NOTES (insn);
8159 REG_NOTES (insn) = note;
8160 /* Only put this note on one of the new insns. */
8163 /* Fail if we couldn't find a JUMP_INSN. */
8170 /* reload sometimes leaves obsolete REG_INC notes around. */
8171 if (reload_completed)
8173 /* This should be moved to whichever instruction now has the
8174 increment operation. */
8178 /* Should be moved to the new insn(s) which use the label. */
8179 for (insn = first; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
8180 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8181 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
8183 REG_NOTES (insn) = alloc_EXPR_LIST (REG_LABEL,
8191 /* These two notes will never appear until after reorg, so we don't
8192 have to handle them here. */
8198 /* Each new insn created, except the last, has a new set. If the destination
8199 is a register, then this reg is now live across several insns, whereas
8200 previously the dest reg was born and died within the same insn. To
8201 reflect this, we now need a REG_DEAD note on the insn where this
8204 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
8206 for (insn = first; insn != last; insn = NEXT_INSN (insn))
8211 pat = PATTERN (insn);
8212 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
8213 new_insn_dead_notes (pat, insn, last, orig_insn);
8214 else if (GET_CODE (pat) == PARALLEL)
8216 for (i = 0; i < XVECLEN (pat, 0); i++)
8217 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8218 || GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER)
8219 new_insn_dead_notes (XVECEXP (pat, 0, i), insn, last, orig_insn);
8223 /* If any insn, except the last, uses the register set by the last insn,
8224 then we need a new REG_DEAD note on that insn. In this case, there
8225 would not have been a REG_DEAD note for this register in the original
8226 insn because it was used and set within one insn. */
8228 set = single_set (last);
8231 rtx dest = SET_DEST (set);
8233 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
8234 || GET_CODE (dest) == STRICT_LOW_PART
8235 || GET_CODE (dest) == SIGN_EXTRACT)
8236 dest = XEXP (dest, 0);
8238 if (GET_CODE (dest) == REG
8239 /* Global registers are always live, so the code below does not
8241 && (REGNO (dest) >= FIRST_PSEUDO_REGISTER
8242 || ! global_regs[REGNO (dest)]))
8244 rtx stop_insn = PREV_INSN (first);
8246 /* If the last insn uses the register that it is setting, then
8247 we don't want to put a REG_DEAD note there. Search backwards
8248 to find the first insn that sets but does not use DEST. */
8251 if (reg_overlap_mentioned_p (dest, SET_SRC (set)))
8253 for (insn = PREV_INSN (insn); insn != first;
8254 insn = PREV_INSN (insn))
8256 if ((set = single_set (insn))
8257 && reg_mentioned_p (dest, SET_DEST (set))
8258 && ! reg_overlap_mentioned_p (dest, SET_SRC (set)))
8263 /* Now find the first insn that uses but does not set DEST. */
8265 for (insn = PREV_INSN (insn); insn != stop_insn;
8266 insn = PREV_INSN (insn))
8268 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8269 && reg_mentioned_p (dest, PATTERN (insn))
8270 && (set = single_set (insn)))
8272 rtx insn_dest = SET_DEST (set);
8274 while (GET_CODE (insn_dest) == ZERO_EXTRACT
8275 || GET_CODE (insn_dest) == SUBREG
8276 || GET_CODE (insn_dest) == STRICT_LOW_PART
8277 || GET_CODE (insn_dest) == SIGN_EXTRACT)
8278 insn_dest = XEXP (insn_dest, 0);
8280 if (insn_dest != dest)
8282 note = alloc_EXPR_LIST (REG_DEAD, dest, REG_NOTES (insn));
8283 REG_NOTES (insn) = note;
8284 /* The reg only dies in one insn, the last one
8293 /* If the original dest is modifying a multiple register target, and the
8294 original instruction was split such that the original dest is now set
8295 by two or more SUBREG sets, then the split insns no longer kill the
8296 destination of the original insn.
8298 In this case, if there exists an instruction in the same basic block,
8299 before the split insn, which uses the original dest, and this use is
8300 killed by the original insn, then we must remove the REG_DEAD note on
8301 this insn, because it is now superfluous.
8303 This does not apply when a hard register gets split, because the code
8304 knows how to handle overlapping hard registers properly. */
8305 if (orig_dest && GET_CODE (orig_dest) == REG)
8307 int found_orig_dest = 0;
8308 int found_split_dest = 0;
8310 for (insn = first;; insn = NEXT_INSN (insn))
8315 /* I'm not sure if this can happen, but let's be safe. */
8316 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8319 pat = PATTERN (insn);
8320 i = GET_CODE (pat) == PARALLEL ? XVECLEN (pat, 0) : 0;
8325 if (GET_CODE (set) == SET)
8327 if (GET_CODE (SET_DEST (set)) == REG
8328 && REGNO (SET_DEST (set)) == REGNO (orig_dest))
8330 found_orig_dest = 1;
8333 else if (GET_CODE (SET_DEST (set)) == SUBREG
8334 && SUBREG_REG (SET_DEST (set)) == orig_dest)
8336 found_split_dest = 1;
8342 set = XVECEXP (pat, 0, i);
8349 if (found_split_dest)
8351 /* Search backwards from FIRST, looking for the first insn that uses
8352 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
8353 If we find an insn, and it has a REG_DEAD note, then delete the
8356 for (insn = first; insn; insn = PREV_INSN (insn))
8358 if (GET_CODE (insn) == CODE_LABEL
8359 || GET_CODE (insn) == JUMP_INSN)
8361 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8362 && reg_mentioned_p (orig_dest, insn))
8364 note = find_regno_note (insn, REG_DEAD, REGNO (orig_dest));
8366 remove_note (insn, note);
8370 else if (!found_orig_dest)
8372 /* This should never happen. */
8377 /* Update reg_n_sets. This is necessary to prevent local alloc from
8378 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
8379 a reg from set once to set multiple times. */
8382 rtx x = PATTERN (orig_insn);
8383 RTX_CODE code = GET_CODE (x);
8385 if (code == SET || code == CLOBBER)
8386 update_n_sets (x, -1);
8387 else if (code == PARALLEL)
8390 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8392 code = GET_CODE (XVECEXP (x, 0, i));
8393 if (code == SET || code == CLOBBER)
8394 update_n_sets (XVECEXP (x, 0, i), -1);
8398 for (insn = first;; insn = NEXT_INSN (insn))
8401 code = GET_CODE (x);
8403 if (code == SET || code == CLOBBER)
8404 update_n_sets (x, 1);
8405 else if (code == PARALLEL)
8408 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8410 code = GET_CODE (XVECEXP (x, 0, i));
8411 if (code == SET || code == CLOBBER)
8412 update_n_sets (XVECEXP (x, 0, i), 1);
8422 /* Do the splitting of insns in the block b. */
8425 split_block_insns (b)
8430 for (insn = basic_block_head[b];; insn = next)
8432 rtx set, last, first, notes;
8434 /* Can't use `next_real_insn' because that
8435 might go across CODE_LABELS and short-out basic blocks. */
8436 next = NEXT_INSN (insn);
8437 if (GET_CODE (insn) != INSN)
8439 if (insn == basic_block_end[b])
8445 /* Don't split no-op move insns. These should silently disappear
8446 later in final. Splitting such insns would break the code
8447 that handles REG_NO_CONFLICT blocks. */
8448 set = single_set (insn);
8449 if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
8451 if (insn == basic_block_end[b])
8454 /* Nops get in the way while scheduling, so delete them now if
8455 register allocation has already been done. It is too risky
8456 to try to do this before register allocation, and there are
8457 unlikely to be very many nops then anyways. */
8458 if (reload_completed)
8460 PUT_CODE (insn, NOTE);
8461 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8462 NOTE_SOURCE_FILE (insn) = 0;
8468 /* Split insns here to get max fine-grain parallelism. */
8469 first = PREV_INSN (insn);
8470 notes = REG_NOTES (insn);
8471 last = try_split (PATTERN (insn), insn, 1);
8474 /* try_split returns the NOTE that INSN became. */
8475 first = NEXT_INSN (first);
8476 update_flow_info (notes, first, last, insn);
8478 PUT_CODE (insn, NOTE);
8479 NOTE_SOURCE_FILE (insn) = 0;
8480 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8481 if (insn == basic_block_head[b])
8482 basic_block_head[b] = first;
8483 if (insn == basic_block_end[b])
8485 basic_block_end[b] = last;
8490 if (insn == basic_block_end[b])
8495 /* The one entry point in this file. DUMP_FILE is the dump file for
8499 schedule_insns (dump_file)
8510 /* disable speculative loads in their presence if cc0 defined */
8512 flag_schedule_speculative_load = 0;
8515 /* Taking care of this degenerate case makes the rest of
8516 this code simpler. */
8517 if (n_basic_blocks == 0)
8520 /* set dump and sched_verbose for the desired debugging output. If no
8521 dump-file was specified, but -fsched-verbose-N (any N), print to stderr.
8522 For -fsched-verbose-N, N>=10, print everything to stderr. */
8523 sched_verbose = sched_verbose_param;
8524 if (sched_verbose_param == 0 && dump_file)
8526 dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file);
8531 /* Initialize the unused_*_lists. We can't use the ones left over from
8532 the previous function, because gcc has freed that memory. We can use
8533 the ones left over from the first sched pass in the second pass however,
8534 so only clear them on the first sched pass. The first pass is before
8535 reload if flag_schedule_insns is set, otherwise it is afterwards. */
8537 if (reload_completed == 0 || !flag_schedule_insns)
8539 unused_insn_list = 0;
8540 unused_expr_list = 0;
8543 /* initialize issue_rate */
8544 issue_rate = ISSUE_RATE;
8546 /* do the splitting first for all blocks */
8547 for (b = 0; b < n_basic_blocks; b++)
8548 split_block_insns (b);
8550 max_uid = (get_max_uid () + 1);
8552 cant_move = (char *) xmalloc (max_uid * sizeof (char));
8553 bzero ((char *) cant_move, max_uid * sizeof (char));
8555 fed_by_spec_load = (char *) xmalloc (max_uid * sizeof (char));
8556 bzero ((char *) fed_by_spec_load, max_uid * sizeof (char));
8558 is_load_insn = (char *) xmalloc (max_uid * sizeof (char));
8559 bzero ((char *) is_load_insn, max_uid * sizeof (char));
8561 insn_orig_block = (int *) xmalloc (max_uid * sizeof (int));
8562 insn_luid = (int *) xmalloc (max_uid * sizeof (int));
8565 for (b = 0; b < n_basic_blocks; b++)
8566 for (insn = basic_block_head[b];; insn = NEXT_INSN (insn))
8568 INSN_BLOCK (insn) = b;
8569 INSN_LUID (insn) = luid++;
8571 if (insn == basic_block_end[b])
8575 /* after reload, remove inter-blocks dependences computed before reload. */
8576 if (reload_completed)
8581 for (b = 0; b < n_basic_blocks; b++)
8582 for (insn = basic_block_head[b];; insn = NEXT_INSN (insn))
8586 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
8589 link = LOG_LINKS (insn);
8592 rtx x = XEXP (link, 0);
8594 if (INSN_BLOCK (x) != b)
8596 remove_dependence (insn, x);
8597 link = prev ? XEXP (prev, 1) : LOG_LINKS (insn);
8600 prev = link, link = XEXP (prev, 1);
8604 if (insn == basic_block_end[b])
8610 rgn_table = (region *) alloca ((n_basic_blocks) * sizeof (region));
8611 rgn_bb_table = (int *) alloca ((n_basic_blocks) * sizeof (int));
8612 block_to_bb = (int *) alloca ((n_basic_blocks) * sizeof (int));
8613 containing_rgn = (int *) alloca ((n_basic_blocks) * sizeof (int));
8615 /* compute regions for scheduling */
8616 if (reload_completed
8617 || n_basic_blocks == 1
8618 || !flag_schedule_interblock)
8620 find_single_block_region ();
8624 /* verify that a 'good' control flow graph can be built */
8625 if (is_cfg_nonregular ())
8627 find_single_block_region ();
8631 int_list_ptr *s_preds, *s_succs;
8632 int *num_preds, *num_succs;
8633 sbitmap *dom, *pdom;
8635 s_preds = (int_list_ptr *) alloca (n_basic_blocks
8636 * sizeof (int_list_ptr));
8637 s_succs = (int_list_ptr *) alloca (n_basic_blocks
8638 * sizeof (int_list_ptr));
8639 num_preds = (int *) alloca (n_basic_blocks * sizeof (int));
8640 num_succs = (int *) alloca (n_basic_blocks * sizeof (int));
8641 dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks);
8642 pdom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks);
8644 /* The scheduler runs after flow; therefore, we can't blindly call
8645 back into find_basic_blocks since doing so could invalidate the
8646 info in basic_block_live_at_start.
8648 Consider a block consisting entirely of dead stores; after life
8649 analysis it would be a block of NOTE_INSN_DELETED notes. If
8650 we call find_basic_blocks again, then the block would be removed
8651 entirely and invalidate our the register live information.
8653 We could (should?) recompute register live information. Doing
8654 so may even be beneficial. */
8656 compute_preds_succs (s_preds, s_succs, num_preds, num_succs);
8658 /* Compute the dominators and post dominators. We don't currently use
8659 post dominators, but we should for speculative motion analysis. */
8660 compute_dominators (dom, pdom, s_preds, s_succs);
8662 /* build_control_flow will return nonzero if it detects unreachable
8663 blocks or any other irregularity with the cfg which prevents
8664 cross block scheduling. */
8665 if (build_control_flow (s_preds, s_succs, num_preds, num_succs) != 0)
8666 find_single_block_region ();
8668 find_rgns (s_preds, s_succs, num_preds, num_succs, dom);
8670 if (sched_verbose >= 3)
8673 /* For now. This will move as more and more of haifa is converted
8674 to using the cfg code in flow.c */
8681 /* Allocate data for this pass. See comments, above,
8682 for what these vectors do.
8684 We use xmalloc instead of alloca, because max_uid can be very large
8685 when there is a lot of function inlining. If we used alloca, we could
8686 exceed stack limits on some hosts for some inputs. */
8687 insn_priority = (int *) xmalloc (max_uid * sizeof (int));
8688 insn_reg_weight = (int *) xmalloc (max_uid * sizeof (int));
8689 insn_tick = (int *) xmalloc (max_uid * sizeof (int));
8690 insn_costs = (short *) xmalloc (max_uid * sizeof (short));
8691 insn_units = (short *) xmalloc (max_uid * sizeof (short));
8692 insn_blockage = (unsigned int *) xmalloc (max_uid * sizeof (unsigned int));
8693 insn_ref_count = (int *) xmalloc (max_uid * sizeof (int));
8695 /* Allocate for forward dependencies */
8696 insn_dep_count = (int *) xmalloc (max_uid * sizeof (int));
8697 insn_depend = (rtx *) xmalloc (max_uid * sizeof (rtx));
8699 if (reload_completed == 0)
8703 sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int));
8704 sched_reg_live_length = (int *) alloca (max_regno * sizeof (int));
8705 sched_reg_basic_block = (int *) alloca (max_regno * sizeof (int));
8706 bb_live_regs = ALLOCA_REG_SET ();
8707 bzero ((char *) sched_reg_n_calls_crossed, max_regno * sizeof (int));
8708 bzero ((char *) sched_reg_live_length, max_regno * sizeof (int));
8710 for (i = 0; i < max_regno; i++)
8711 sched_reg_basic_block[i] = REG_BLOCK_UNKNOWN;
8715 sched_reg_n_calls_crossed = 0;
8716 sched_reg_live_length = 0;
8719 init_alias_analysis ();
8721 if (write_symbols != NO_DEBUG)
8725 line_note = (rtx *) xmalloc (max_uid * sizeof (rtx));
8726 bzero ((char *) line_note, max_uid * sizeof (rtx));
8727 line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx));
8728 bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx));
8730 /* Save-line-note-head:
8731 Determine the line-number at the start of each basic block.
8732 This must be computed and saved now, because after a basic block's
8733 predecessor has been scheduled, it is impossible to accurately
8734 determine the correct line number for the first insn of the block. */
8736 for (b = 0; b < n_basic_blocks; b++)
8737 for (line = basic_block_head[b]; line; line = PREV_INSN (line))
8738 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
8740 line_note_head[b] = line;
8745 bzero ((char *) insn_priority, max_uid * sizeof (int));
8746 bzero ((char *) insn_reg_weight, max_uid * sizeof (int));
8747 bzero ((char *) insn_tick, max_uid * sizeof (int));
8748 bzero ((char *) insn_costs, max_uid * sizeof (short));
8749 bzero ((char *) insn_units, max_uid * sizeof (short));
8750 bzero ((char *) insn_blockage, max_uid * sizeof (unsigned int));
8751 bzero ((char *) insn_ref_count, max_uid * sizeof (int));
8753 /* Initialize for forward dependencies */
8754 bzero ((char *) insn_depend, max_uid * sizeof (rtx));
8755 bzero ((char *) insn_dep_count, max_uid * sizeof (int));
8757 /* Find units used in this fuction, for visualization */
8759 init_target_units ();
8761 /* ??? Add a NOTE after the last insn of the last basic block. It is not
8762 known why this is done. */
8764 insn = basic_block_end[n_basic_blocks - 1];
8765 if (NEXT_INSN (insn) == 0
8766 || (GET_CODE (insn) != NOTE
8767 && GET_CODE (insn) != CODE_LABEL
8768 /* Don't emit a NOTE if it would end up between an unconditional
8769 jump and a BARRIER. */
8770 && !(GET_CODE (insn) == JUMP_INSN
8771 && GET_CODE (NEXT_INSN (insn)) == BARRIER)))
8772 emit_note_after (NOTE_INSN_DELETED, basic_block_end[n_basic_blocks - 1]);
8774 /* Schedule every region in the subroutine */
8775 for (rgn = 0; rgn < nr_regions; rgn++)
8777 schedule_region (rgn);
8784 /* Reposition the prologue and epilogue notes in case we moved the
8785 prologue/epilogue insns. */
8786 if (reload_completed)
8787 reposition_prologue_and_epilogue_notes (get_insns ());
8789 /* delete redundant line notes. */
8790 if (write_symbols != NO_DEBUG)
8791 rm_redundant_line_notes ();
8793 /* Update information about uses of registers in the subroutine. */
8794 if (reload_completed == 0)
8795 update_reg_usage ();
8799 if (reload_completed == 0 && flag_schedule_interblock)
8801 fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n",
8809 fprintf (dump, "\n\n");
8813 free (fed_by_spec_load);
8814 free (is_load_insn);
8815 free (insn_orig_block);
8818 free (insn_priority);
8819 free (insn_reg_weight);
8823 free (insn_blockage);
8824 free (insn_ref_count);
8826 free (insn_dep_count);
8829 if (write_symbols != NO_DEBUG)
8833 FREE_REG_SET (bb_live_regs);
8852 #endif /* INSN_SCHEDULING */