1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "diagnostic-core.h"
34 #include "insn-config.h"
38 #include "langhooks.h"
43 struct target_expmed default_target_expmed;
45 struct target_expmed *this_target_expmed = &default_target_expmed;
48 static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
49 unsigned HOST_WIDE_INT,
50 unsigned HOST_WIDE_INT, rtx);
51 static void store_split_bit_field (rtx, unsigned HOST_WIDE_INT,
52 unsigned HOST_WIDE_INT, rtx);
53 static rtx extract_fixed_bit_field (enum machine_mode, rtx,
54 unsigned HOST_WIDE_INT,
55 unsigned HOST_WIDE_INT,
56 unsigned HOST_WIDE_INT, rtx, int);
57 static rtx mask_rtx (enum machine_mode, int, int, int);
58 static rtx lshift_value (enum machine_mode, rtx, int, int);
59 static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT,
60 unsigned HOST_WIDE_INT, int);
61 static void do_cmp_and_jump (rtx, rtx, enum rtx_code, enum machine_mode, rtx);
62 static rtx expand_smod_pow2 (enum machine_mode, rtx, HOST_WIDE_INT);
63 static rtx expand_sdiv_pow2 (enum machine_mode, rtx, HOST_WIDE_INT);
65 /* Test whether a value is zero of a power of two. */
66 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
68 #ifndef SLOW_UNALIGNED_ACCESS
69 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
72 /* For compilers that support multiple targets with different word sizes,
73 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
74 is the H8/300(H) compiler. */
76 #ifndef MAX_BITS_PER_WORD
77 #define MAX_BITS_PER_WORD BITS_PER_WORD
80 /* Reduce conditional compilation elsewhere. */
83 #define CODE_FOR_insv CODE_FOR_nothing
84 #define gen_insv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extv CODE_FOR_nothing
89 #define gen_extv(a,b,c,d) NULL_RTX
93 #define CODE_FOR_extzv CODE_FOR_nothing
94 #define gen_extzv(a,b,c,d) NULL_RTX
102 struct rtx_def reg; rtunion reg_fld[2];
103 struct rtx_def plus; rtunion plus_fld1;
105 struct rtx_def mult; rtunion mult_fld1;
106 struct rtx_def sdiv; rtunion sdiv_fld1;
107 struct rtx_def udiv; rtunion udiv_fld1;
109 struct rtx_def sdiv_32; rtunion sdiv_32_fld1;
110 struct rtx_def smod_32; rtunion smod_32_fld1;
111 struct rtx_def wide_mult; rtunion wide_mult_fld1;
112 struct rtx_def wide_lshr; rtunion wide_lshr_fld1;
113 struct rtx_def wide_trunc;
114 struct rtx_def shift; rtunion shift_fld1;
115 struct rtx_def shift_mult; rtunion shift_mult_fld1;
116 struct rtx_def shift_add; rtunion shift_add_fld1;
117 struct rtx_def shift_sub0; rtunion shift_sub0_fld1;
118 struct rtx_def shift_sub1; rtunion shift_sub1_fld1;
121 rtx pow2[MAX_BITS_PER_WORD];
122 rtx cint[MAX_BITS_PER_WORD];
124 enum machine_mode mode, wider_mode;
128 for (m = 1; m < MAX_BITS_PER_WORD; m++)
130 pow2[m] = GEN_INT ((HOST_WIDE_INT) 1 << m);
131 cint[m] = GEN_INT (m);
133 memset (&all, 0, sizeof all);
135 PUT_CODE (&all.reg, REG);
136 /* Avoid using hard regs in ways which may be unsupported. */
137 SET_REGNO (&all.reg, LAST_VIRTUAL_REGISTER + 1);
139 PUT_CODE (&all.plus, PLUS);
140 XEXP (&all.plus, 0) = &all.reg;
141 XEXP (&all.plus, 1) = &all.reg;
143 PUT_CODE (&all.neg, NEG);
144 XEXP (&all.neg, 0) = &all.reg;
146 PUT_CODE (&all.mult, MULT);
147 XEXP (&all.mult, 0) = &all.reg;
148 XEXP (&all.mult, 1) = &all.reg;
150 PUT_CODE (&all.sdiv, DIV);
151 XEXP (&all.sdiv, 0) = &all.reg;
152 XEXP (&all.sdiv, 1) = &all.reg;
154 PUT_CODE (&all.udiv, UDIV);
155 XEXP (&all.udiv, 0) = &all.reg;
156 XEXP (&all.udiv, 1) = &all.reg;
158 PUT_CODE (&all.sdiv_32, DIV);
159 XEXP (&all.sdiv_32, 0) = &all.reg;
160 XEXP (&all.sdiv_32, 1) = 32 < MAX_BITS_PER_WORD ? cint[32] : GEN_INT (32);
162 PUT_CODE (&all.smod_32, MOD);
163 XEXP (&all.smod_32, 0) = &all.reg;
164 XEXP (&all.smod_32, 1) = XEXP (&all.sdiv_32, 1);
166 PUT_CODE (&all.zext, ZERO_EXTEND);
167 XEXP (&all.zext, 0) = &all.reg;
169 PUT_CODE (&all.wide_mult, MULT);
170 XEXP (&all.wide_mult, 0) = &all.zext;
171 XEXP (&all.wide_mult, 1) = &all.zext;
173 PUT_CODE (&all.wide_lshr, LSHIFTRT);
174 XEXP (&all.wide_lshr, 0) = &all.wide_mult;
176 PUT_CODE (&all.wide_trunc, TRUNCATE);
177 XEXP (&all.wide_trunc, 0) = &all.wide_lshr;
179 PUT_CODE (&all.shift, ASHIFT);
180 XEXP (&all.shift, 0) = &all.reg;
182 PUT_CODE (&all.shift_mult, MULT);
183 XEXP (&all.shift_mult, 0) = &all.reg;
185 PUT_CODE (&all.shift_add, PLUS);
186 XEXP (&all.shift_add, 0) = &all.shift_mult;
187 XEXP (&all.shift_add, 1) = &all.reg;
189 PUT_CODE (&all.shift_sub0, MINUS);
190 XEXP (&all.shift_sub0, 0) = &all.shift_mult;
191 XEXP (&all.shift_sub0, 1) = &all.reg;
193 PUT_CODE (&all.shift_sub1, MINUS);
194 XEXP (&all.shift_sub1, 0) = &all.reg;
195 XEXP (&all.shift_sub1, 1) = &all.shift_mult;
197 for (speed = 0; speed < 2; speed++)
199 crtl->maybe_hot_insn_p = speed;
200 zero_cost[speed] = rtx_cost (const0_rtx, SET, speed);
202 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
204 mode = GET_MODE_WIDER_MODE (mode))
206 PUT_MODE (&all.reg, mode);
207 PUT_MODE (&all.plus, mode);
208 PUT_MODE (&all.neg, mode);
209 PUT_MODE (&all.mult, mode);
210 PUT_MODE (&all.sdiv, mode);
211 PUT_MODE (&all.udiv, mode);
212 PUT_MODE (&all.sdiv_32, mode);
213 PUT_MODE (&all.smod_32, mode);
214 PUT_MODE (&all.wide_trunc, mode);
215 PUT_MODE (&all.shift, mode);
216 PUT_MODE (&all.shift_mult, mode);
217 PUT_MODE (&all.shift_add, mode);
218 PUT_MODE (&all.shift_sub0, mode);
219 PUT_MODE (&all.shift_sub1, mode);
221 add_cost[speed][mode] = rtx_cost (&all.plus, SET, speed);
222 neg_cost[speed][mode] = rtx_cost (&all.neg, SET, speed);
223 mul_cost[speed][mode] = rtx_cost (&all.mult, SET, speed);
224 sdiv_cost[speed][mode] = rtx_cost (&all.sdiv, SET, speed);
225 udiv_cost[speed][mode] = rtx_cost (&all.udiv, SET, speed);
227 sdiv_pow2_cheap[speed][mode] = (rtx_cost (&all.sdiv_32, SET, speed)
228 <= 2 * add_cost[speed][mode]);
229 smod_pow2_cheap[speed][mode] = (rtx_cost (&all.smod_32, SET, speed)
230 <= 4 * add_cost[speed][mode]);
232 wider_mode = GET_MODE_WIDER_MODE (mode);
233 if (wider_mode != VOIDmode)
235 PUT_MODE (&all.zext, wider_mode);
236 PUT_MODE (&all.wide_mult, wider_mode);
237 PUT_MODE (&all.wide_lshr, wider_mode);
238 XEXP (&all.wide_lshr, 1) = GEN_INT (GET_MODE_BITSIZE (mode));
240 mul_widen_cost[speed][wider_mode]
241 = rtx_cost (&all.wide_mult, SET, speed);
242 mul_highpart_cost[speed][mode]
243 = rtx_cost (&all.wide_trunc, SET, speed);
246 shift_cost[speed][mode][0] = 0;
247 shiftadd_cost[speed][mode][0] = shiftsub0_cost[speed][mode][0]
248 = shiftsub1_cost[speed][mode][0] = add_cost[speed][mode];
250 n = MIN (MAX_BITS_PER_WORD, GET_MODE_BITSIZE (mode));
251 for (m = 1; m < n; m++)
253 XEXP (&all.shift, 1) = cint[m];
254 XEXP (&all.shift_mult, 1) = pow2[m];
256 shift_cost[speed][mode][m] = rtx_cost (&all.shift, SET, speed);
257 shiftadd_cost[speed][mode][m] = rtx_cost (&all.shift_add, SET, speed);
258 shiftsub0_cost[speed][mode][m] = rtx_cost (&all.shift_sub0, SET, speed);
259 shiftsub1_cost[speed][mode][m] = rtx_cost (&all.shift_sub1, SET, speed);
264 memset (alg_hash, 0, sizeof (alg_hash));
266 alg_hash_used_p = true;
267 default_rtl_profile ();
270 /* Return an rtx representing minus the value of X.
271 MODE is the intended mode of the result,
272 useful if X is a CONST_INT. */
275 negate_rtx (enum machine_mode mode, rtx x)
277 rtx result = simplify_unary_operation (NEG, mode, x, mode);
280 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
285 /* Report on the availability of insv/extv/extzv and the desired mode
286 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
287 is false; else the mode of the specified operand. If OPNO is -1,
288 all the caller cares about is whether the insn is available. */
290 mode_for_extraction (enum extraction_pattern pattern, int opno)
292 const struct insn_data_d *data;
299 data = &insn_data[CODE_FOR_insv];
302 return MAX_MACHINE_MODE;
307 data = &insn_data[CODE_FOR_extv];
310 return MAX_MACHINE_MODE;
315 data = &insn_data[CODE_FOR_extzv];
318 return MAX_MACHINE_MODE;
327 /* Everyone who uses this function used to follow it with
328 if (result == VOIDmode) result = word_mode; */
329 if (data->operand[opno].mode == VOIDmode)
331 return data->operand[opno].mode;
334 /* Return true if X, of mode MODE, matches the predicate for operand
335 OPNO of instruction ICODE. Allow volatile memories, regardless of
336 the ambient volatile_ok setting. */
339 check_predicate_volatile_ok (enum insn_code icode, int opno,
340 rtx x, enum machine_mode mode)
342 bool save_volatile_ok, result;
344 save_volatile_ok = volatile_ok;
345 result = insn_data[(int) icode].operand[opno].predicate (x, mode);
346 volatile_ok = save_volatile_ok;
350 /* A subroutine of store_bit_field, with the same arguments. Return true
351 if the operation could be implemented.
353 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
354 no other way of implementing the operation. If FALLBACK_P is false,
355 return false instead. */
358 store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
359 unsigned HOST_WIDE_INT bitnum, enum machine_mode fieldmode,
360 rtx value, bool fallback_p)
363 = (MEM_P (str_rtx)) ? BITS_PER_UNIT : BITS_PER_WORD;
364 unsigned HOST_WIDE_INT offset, bitpos;
369 enum machine_mode op_mode = mode_for_extraction (EP_insv, 3);
371 while (GET_CODE (op0) == SUBREG)
373 /* The following line once was done only if WORDS_BIG_ENDIAN,
374 but I think that is a mistake. WORDS_BIG_ENDIAN is
375 meaningful at a much higher level; when structures are copied
376 between memory and regs, the higher-numbered regs
377 always get higher addresses. */
378 int inner_mode_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)));
379 int outer_mode_size = GET_MODE_SIZE (GET_MODE (op0));
383 /* Paradoxical subregs need special handling on big endian machines. */
384 if (SUBREG_BYTE (op0) == 0 && inner_mode_size < outer_mode_size)
386 int difference = inner_mode_size - outer_mode_size;
388 if (WORDS_BIG_ENDIAN)
389 byte_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
390 if (BYTES_BIG_ENDIAN)
391 byte_offset += difference % UNITS_PER_WORD;
394 byte_offset = SUBREG_BYTE (op0);
396 bitnum += byte_offset * BITS_PER_UNIT;
397 op0 = SUBREG_REG (op0);
400 /* No action is needed if the target is a register and if the field
401 lies completely outside that register. This can occur if the source
402 code contains an out-of-bounds access to a small array. */
403 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
406 /* Use vec_set patterns for inserting parts of vectors whenever
408 if (VECTOR_MODE_P (GET_MODE (op0))
410 && optab_handler (vec_set_optab, GET_MODE (op0)) != CODE_FOR_nothing
411 && fieldmode == GET_MODE_INNER (GET_MODE (op0))
412 && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
413 && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
415 enum machine_mode outermode = GET_MODE (op0);
416 enum machine_mode innermode = GET_MODE_INNER (outermode);
417 int icode = (int) optab_handler (vec_set_optab, outermode);
418 int pos = bitnum / GET_MODE_BITSIZE (innermode);
419 rtx rtxpos = GEN_INT (pos);
423 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
424 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
425 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
429 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
430 src = copy_to_mode_reg (mode1, src);
432 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
433 rtxpos = copy_to_mode_reg (mode1, rtxpos);
435 /* We could handle this, but we should always be called with a pseudo
436 for our targets and all insns should take them as outputs. */
437 gcc_assert ((*insn_data[icode].operand[0].predicate) (dest, mode0)
438 && (*insn_data[icode].operand[1].predicate) (src, mode1)
439 && (*insn_data[icode].operand[2].predicate) (rtxpos, mode2));
440 pat = GEN_FCN (icode) (dest, src, rtxpos);
451 /* If the target is a register, overwriting the entire object, or storing
452 a full-word or multi-word field can be done with just a SUBREG.
454 If the target is memory, storing any naturally aligned field can be
455 done with a simple store. For targets that support fast unaligned
456 memory, any naturally sized, unit aligned field can be done directly. */
458 offset = bitnum / unit;
459 bitpos = bitnum % unit;
460 byte_offset = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
461 + (offset * UNITS_PER_WORD);
464 && bitsize == GET_MODE_BITSIZE (fieldmode)
466 ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
467 || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
468 && byte_offset % GET_MODE_SIZE (fieldmode) == 0)
469 : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
470 || (offset * BITS_PER_UNIT % bitsize == 0
471 && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))
474 op0 = adjust_address (op0, fieldmode, offset);
475 else if (GET_MODE (op0) != fieldmode)
476 op0 = simplify_gen_subreg (fieldmode, op0, GET_MODE (op0),
478 emit_move_insn (op0, value);
482 /* Make sure we are playing with integral modes. Pun with subregs
483 if we aren't. This must come after the entire register case above,
484 since that case is valid for any mode. The following cases are only
485 valid for integral modes. */
487 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
488 if (imode != GET_MODE (op0))
491 op0 = adjust_address (op0, imode, 0);
494 gcc_assert (imode != BLKmode);
495 op0 = gen_lowpart (imode, op0);
500 /* We may be accessing data outside the field, which means
501 we can alias adjacent data. */
504 op0 = shallow_copy_rtx (op0);
505 set_mem_alias_set (op0, 0);
506 set_mem_expr (op0, 0);
509 /* If OP0 is a register, BITPOS must count within a word.
510 But as we have it, it counts within whatever size OP0 now has.
511 On a bigendian machine, these are not the same, so convert. */
514 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
515 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
517 /* Storing an lsb-aligned field in a register
518 can be done with a movestrict instruction. */
521 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
522 && bitsize == GET_MODE_BITSIZE (fieldmode)
523 && optab_handler (movstrict_optab, fieldmode) != CODE_FOR_nothing)
525 int icode = optab_handler (movstrict_optab, fieldmode);
527 rtx start = get_last_insn ();
530 /* Get appropriate low part of the value being stored. */
531 if (CONST_INT_P (value) || REG_P (value))
532 value = gen_lowpart (fieldmode, value);
533 else if (!(GET_CODE (value) == SYMBOL_REF
534 || GET_CODE (value) == LABEL_REF
535 || GET_CODE (value) == CONST))
536 value = convert_to_mode (fieldmode, value, 0);
538 if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode))
539 value = copy_to_mode_reg (fieldmode, value);
541 if (GET_CODE (op0) == SUBREG)
543 /* Else we've got some float mode source being extracted into
544 a different float mode destination -- this combination of
545 subregs results in Severe Tire Damage. */
546 gcc_assert (GET_MODE (SUBREG_REG (op0)) == fieldmode
547 || GET_MODE_CLASS (fieldmode) == MODE_INT
548 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT);
549 arg0 = SUBREG_REG (op0);
552 insn = (GEN_FCN (icode)
553 (gen_rtx_SUBREG (fieldmode, arg0,
554 (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
555 + (offset * UNITS_PER_WORD)),
562 delete_insns_since (start);
565 /* Handle fields bigger than a word. */
567 if (bitsize > BITS_PER_WORD)
569 /* Here we transfer the words of the field
570 in the order least significant first.
571 This is because the most significant word is the one which may
573 However, only do that if the value is not BLKmode. */
575 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
576 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
580 /* This is the mode we must force value to, so that there will be enough
581 subwords to extract. Note that fieldmode will often (always?) be
582 VOIDmode, because that is what store_field uses to indicate that this
583 is a bit field, but passing VOIDmode to operand_subword_force
585 fieldmode = GET_MODE (value);
586 if (fieldmode == VOIDmode)
587 fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
589 last = get_last_insn ();
590 for (i = 0; i < nwords; i++)
592 /* If I is 0, use the low-order word in both field and target;
593 if I is 1, use the next to lowest word; and so on. */
594 unsigned int wordnum = (backwards ? nwords - i - 1 : i);
595 unsigned int bit_offset = (backwards
596 ? MAX ((int) bitsize - ((int) i + 1)
599 : (int) i * BITS_PER_WORD);
600 rtx value_word = operand_subword_force (value, wordnum, fieldmode);
602 if (!store_bit_field_1 (op0, MIN (BITS_PER_WORD,
603 bitsize - i * BITS_PER_WORD),
604 bitnum + bit_offset, word_mode,
605 value_word, fallback_p))
607 delete_insns_since (last);
614 /* From here on we can assume that the field to be stored in is
615 a full-word (whatever type that is), since it is shorter than a word. */
617 /* OFFSET is the number of words or bytes (UNIT says which)
618 from STR_RTX to the first word or byte containing part of the field. */
623 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
627 /* Since this is a destination (lvalue), we can't copy
628 it to a pseudo. We can remove a SUBREG that does not
629 change the size of the operand. Such a SUBREG may
630 have been added above. */
631 gcc_assert (GET_CODE (op0) == SUBREG
632 && (GET_MODE_SIZE (GET_MODE (op0))
633 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))));
634 op0 = SUBREG_REG (op0);
636 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
637 op0, (offset * UNITS_PER_WORD));
642 /* If VALUE has a floating-point or complex mode, access it as an
643 integer of the corresponding size. This can occur on a machine
644 with 64 bit registers that uses SFmode for float. It can also
645 occur for unaligned float or complex fields. */
647 if (GET_MODE (value) != VOIDmode
648 && GET_MODE_CLASS (GET_MODE (value)) != MODE_INT
649 && GET_MODE_CLASS (GET_MODE (value)) != MODE_PARTIAL_INT)
651 value = gen_reg_rtx (int_mode_for_mode (GET_MODE (value)));
652 emit_move_insn (gen_lowpart (GET_MODE (orig_value), value), orig_value);
655 /* Now OFFSET is nonzero only if OP0 is memory
656 and is therefore always measured in bytes. */
659 && GET_MODE (value) != BLKmode
661 && GET_MODE_BITSIZE (op_mode) >= bitsize
662 && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
663 && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode)))
664 && insn_data[CODE_FOR_insv].operand[1].predicate (GEN_INT (bitsize),
666 && check_predicate_volatile_ok (CODE_FOR_insv, 0, op0, VOIDmode))
668 int xbitpos = bitpos;
671 rtx last = get_last_insn ();
673 bool copy_back = false;
675 /* Add OFFSET into OP0's address. */
677 xop0 = adjust_address (xop0, byte_mode, offset);
679 /* If xop0 is a register, we need it in OP_MODE
680 to make it acceptable to the format of insv. */
681 if (GET_CODE (xop0) == SUBREG)
682 /* We can't just change the mode, because this might clobber op0,
683 and we will need the original value of op0 if insv fails. */
684 xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
685 if (REG_P (xop0) && GET_MODE (xop0) != op_mode)
686 xop0 = gen_lowpart_SUBREG (op_mode, xop0);
688 /* If the destination is a paradoxical subreg such that we need a
689 truncate to the inner mode, perform the insertion on a temporary and
690 truncate the result to the original destination. Note that we can't
691 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
692 X) 0)) is (reg:N X). */
693 if (GET_CODE (xop0) == SUBREG
694 && REG_P (SUBREG_REG (xop0))
695 && (!TRULY_NOOP_TRUNCATION
696 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (xop0))),
697 GET_MODE_BITSIZE (op_mode))))
699 rtx tem = gen_reg_rtx (op_mode);
700 emit_move_insn (tem, xop0);
705 /* On big-endian machines, we count bits from the most significant.
706 If the bit field insn does not, we must invert. */
708 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
709 xbitpos = unit - bitsize - xbitpos;
711 /* We have been counting XBITPOS within UNIT.
712 Count instead within the size of the register. */
713 if (BITS_BIG_ENDIAN && !MEM_P (xop0))
714 xbitpos += GET_MODE_BITSIZE (op_mode) - unit;
716 unit = GET_MODE_BITSIZE (op_mode);
718 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
720 if (GET_MODE (value) != op_mode)
722 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
724 /* Optimization: Don't bother really extending VALUE
725 if it has all the bits we will actually use. However,
726 if we must narrow it, be sure we do it correctly. */
728 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (op_mode))
732 tmp = simplify_subreg (op_mode, value1, GET_MODE (value), 0);
734 tmp = simplify_gen_subreg (op_mode,
735 force_reg (GET_MODE (value),
737 GET_MODE (value), 0);
741 value1 = gen_lowpart (op_mode, value1);
743 else if (CONST_INT_P (value))
744 value1 = gen_int_mode (INTVAL (value), op_mode);
746 /* Parse phase is supposed to make VALUE's data type
747 match that of the component reference, which is a type
748 at least as wide as the field; so VALUE should have
749 a mode that corresponds to that type. */
750 gcc_assert (CONSTANT_P (value));
753 /* If this machine's insv insists on a register,
754 get VALUE1 into a register. */
755 if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate)
757 value1 = force_reg (op_mode, value1);
759 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
765 convert_move (op0, xop0, true);
768 delete_insns_since (last);
771 /* If OP0 is a memory, try copying it to a register and seeing if a
772 cheap register alternative is available. */
773 if (HAVE_insv && MEM_P (op0))
775 enum machine_mode bestmode;
777 /* Get the mode to use for inserting into this field. If OP0 is
778 BLKmode, get the smallest mode consistent with the alignment. If
779 OP0 is a non-BLKmode object that is no wider than OP_MODE, use its
780 mode. Otherwise, use the smallest mode containing the field. */
782 if (GET_MODE (op0) == BLKmode
783 || (op_mode != MAX_MACHINE_MODE
784 && GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (op_mode)))
785 bestmode = get_best_mode (bitsize, bitnum, MEM_ALIGN (op0),
786 (op_mode == MAX_MACHINE_MODE
787 ? VOIDmode : op_mode),
788 MEM_VOLATILE_P (op0));
790 bestmode = GET_MODE (op0);
792 if (bestmode != VOIDmode
793 && GET_MODE_SIZE (bestmode) >= GET_MODE_SIZE (fieldmode)
794 && !(SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
795 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0)))
797 rtx last, tempreg, xop0;
798 unsigned HOST_WIDE_INT xoffset, xbitpos;
800 last = get_last_insn ();
802 /* Adjust address to point to the containing unit of
803 that mode. Compute the offset as a multiple of this unit,
804 counting in bytes. */
805 unit = GET_MODE_BITSIZE (bestmode);
806 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
807 xbitpos = bitnum % unit;
808 xop0 = adjust_address (op0, bestmode, xoffset);
810 /* Fetch that unit, store the bitfield in it, then store
812 tempreg = copy_to_reg (xop0);
813 if (store_bit_field_1 (tempreg, bitsize, xbitpos,
814 fieldmode, orig_value, false))
816 emit_move_insn (xop0, tempreg);
819 delete_insns_since (last);
826 store_fixed_bit_field (op0, offset, bitsize, bitpos, value);
830 /* Generate code to store value from rtx VALUE
831 into a bit-field within structure STR_RTX
832 containing BITSIZE bits starting at bit BITNUM.
833 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
836 store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
837 unsigned HOST_WIDE_INT bitnum, enum machine_mode fieldmode,
840 if (!store_bit_field_1 (str_rtx, bitsize, bitnum, fieldmode, value, true))
844 /* Use shifts and boolean operations to store VALUE
845 into a bit field of width BITSIZE
846 in a memory location specified by OP0 except offset by OFFSET bytes.
847 (OFFSET must be 0 if OP0 is a register.)
848 The field starts at position BITPOS within the byte.
849 (If OP0 is a register, it may be a full word or a narrower mode,
850 but BITPOS still counts within a full word,
851 which is significant on bigendian machines.) */
854 store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset,
855 unsigned HOST_WIDE_INT bitsize,
856 unsigned HOST_WIDE_INT bitpos, rtx value)
858 enum machine_mode mode;
859 unsigned int total_bits = BITS_PER_WORD;
864 /* There is a case not handled here:
865 a structure with a known alignment of just a halfword
866 and a field split across two aligned halfwords within the structure.
867 Or likewise a structure with a known alignment of just a byte
868 and a field split across two bytes.
869 Such cases are not supposed to be able to occur. */
871 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
873 gcc_assert (!offset);
874 /* Special treatment for a bit field split across two registers. */
875 if (bitsize + bitpos > BITS_PER_WORD)
877 store_split_bit_field (op0, bitsize, bitpos, value);
883 /* Get the proper mode to use for this field. We want a mode that
884 includes the entire field. If such a mode would be larger than
885 a word, we won't be doing the extraction the normal way.
886 We don't want a mode bigger than the destination. */
888 mode = GET_MODE (op0);
889 if (GET_MODE_BITSIZE (mode) == 0
890 || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
893 if (MEM_VOLATILE_P (op0)
894 && GET_MODE_BITSIZE (GET_MODE (op0)) > 0
895 && flag_strict_volatile_bitfields > 0)
896 mode = GET_MODE (op0);
898 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
899 MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
901 if (mode == VOIDmode)
903 /* The only way this should occur is if the field spans word
905 store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
910 total_bits = GET_MODE_BITSIZE (mode);
912 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
913 be in the range 0 to total_bits-1, and put any excess bytes in
915 if (bitpos >= total_bits)
917 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
918 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
922 /* Get ref to an aligned byte, halfword, or word containing the field.
923 Adjust BITPOS to be position within a word,
924 and OFFSET to be the offset of that word.
925 Then alter OP0 to refer to that word. */
926 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
927 offset -= (offset % (total_bits / BITS_PER_UNIT));
928 op0 = adjust_address (op0, mode, offset);
931 mode = GET_MODE (op0);
933 /* Now MODE is either some integral mode for a MEM as OP0,
934 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
935 The bit field is contained entirely within OP0.
936 BITPOS is the starting bit number within OP0.
937 (OP0's mode may actually be narrower than MODE.) */
939 if (BYTES_BIG_ENDIAN)
940 /* BITPOS is the distance between our msb
941 and that of the containing datum.
942 Convert it to the distance from the lsb. */
943 bitpos = total_bits - bitsize - bitpos;
945 /* Now BITPOS is always the distance between our lsb
948 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
949 we must first convert its mode to MODE. */
951 if (CONST_INT_P (value))
953 HOST_WIDE_INT v = INTVAL (value);
955 if (bitsize < HOST_BITS_PER_WIDE_INT)
956 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
960 else if ((bitsize < HOST_BITS_PER_WIDE_INT
961 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
962 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
965 value = lshift_value (mode, value, bitpos, bitsize);
969 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
970 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
972 if (GET_MODE (value) != mode)
973 value = convert_to_mode (mode, value, 1);
976 value = expand_binop (mode, and_optab, value,
977 mask_rtx (mode, 0, bitsize, 0),
978 NULL_RTX, 1, OPTAB_LIB_WIDEN);
980 value = expand_shift (LSHIFT_EXPR, mode, value,
981 build_int_cst (NULL_TREE, bitpos), NULL_RTX, 1);
984 /* Now clear the chosen bits in OP0,
985 except that if VALUE is -1 we need not bother. */
986 /* We keep the intermediates in registers to allow CSE to combine
987 consecutive bitfield assignments. */
989 temp = force_reg (mode, op0);
993 temp = expand_binop (mode, and_optab, temp,
994 mask_rtx (mode, bitpos, bitsize, 1),
995 NULL_RTX, 1, OPTAB_LIB_WIDEN);
996 temp = force_reg (mode, temp);
999 /* Now logical-or VALUE into OP0, unless it is zero. */
1003 temp = expand_binop (mode, ior_optab, temp, value,
1004 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1005 temp = force_reg (mode, temp);
1010 op0 = copy_rtx (op0);
1011 emit_move_insn (op0, temp);
1015 /* Store a bit field that is split across multiple accessible memory objects.
1017 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1018 BITSIZE is the field width; BITPOS the position of its first bit
1020 VALUE is the value to store.
1022 This does not yet handle fields wider than BITS_PER_WORD. */
1025 store_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1026 unsigned HOST_WIDE_INT bitpos, rtx value)
1029 unsigned int bitsdone = 0;
1031 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1033 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1034 unit = BITS_PER_WORD;
1036 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1038 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1039 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1040 that VALUE might be a floating-point constant. */
1041 if (CONSTANT_P (value) && !CONST_INT_P (value))
1043 rtx word = gen_lowpart_common (word_mode, value);
1045 if (word && (value != word))
1048 value = gen_lowpart_common (word_mode,
1049 force_reg (GET_MODE (value) != VOIDmode
1051 : word_mode, value));
1054 while (bitsdone < bitsize)
1056 unsigned HOST_WIDE_INT thissize;
1058 unsigned HOST_WIDE_INT thispos;
1059 unsigned HOST_WIDE_INT offset;
1061 offset = (bitpos + bitsdone) / unit;
1062 thispos = (bitpos + bitsdone) % unit;
1064 /* THISSIZE must not overrun a word boundary. Otherwise,
1065 store_fixed_bit_field will call us again, and we will mutually
1067 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1068 thissize = MIN (thissize, unit - thispos);
1070 if (BYTES_BIG_ENDIAN)
1074 /* We must do an endian conversion exactly the same way as it is
1075 done in extract_bit_field, so that the two calls to
1076 extract_fixed_bit_field will have comparable arguments. */
1077 if (!MEM_P (value) || GET_MODE (value) == BLKmode)
1078 total_bits = BITS_PER_WORD;
1080 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
1082 /* Fetch successively less significant portions. */
1083 if (CONST_INT_P (value))
1084 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1085 >> (bitsize - bitsdone - thissize))
1086 & (((HOST_WIDE_INT) 1 << thissize) - 1));
1088 /* The args are chosen so that the last part includes the
1089 lsb. Give extract_bit_field the value it needs (with
1090 endianness compensation) to fetch the piece we want. */
1091 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
1092 total_bits - bitsize + bitsdone,
1097 /* Fetch successively more significant portions. */
1098 if (CONST_INT_P (value))
1099 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1101 & (((HOST_WIDE_INT) 1 << thissize) - 1));
1103 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
1104 bitsdone, NULL_RTX, 1);
1107 /* If OP0 is a register, then handle OFFSET here.
1109 When handling multiword bitfields, extract_bit_field may pass
1110 down a word_mode SUBREG of a larger REG for a bitfield that actually
1111 crosses a word boundary. Thus, for a SUBREG, we must find
1112 the current word starting from the base register. */
1113 if (GET_CODE (op0) == SUBREG)
1115 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1116 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1117 GET_MODE (SUBREG_REG (op0)));
1120 else if (REG_P (op0))
1122 word = operand_subword_force (op0, offset, GET_MODE (op0));
1128 /* OFFSET is in UNITs, and UNIT is in bits.
1129 store_fixed_bit_field wants offset in bytes. */
1130 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, thissize,
1132 bitsdone += thissize;
1136 /* A subroutine of extract_bit_field_1 that converts return value X
1137 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1138 to extract_bit_field. */
1141 convert_extracted_bit_field (rtx x, enum machine_mode mode,
1142 enum machine_mode tmode, bool unsignedp)
1144 if (GET_MODE (x) == tmode || GET_MODE (x) == mode)
1147 /* If the x mode is not a scalar integral, first convert to the
1148 integer mode of that size and then access it as a floating-point
1149 value via a SUBREG. */
1150 if (!SCALAR_INT_MODE_P (tmode))
1152 enum machine_mode smode;
1154 smode = mode_for_size (GET_MODE_BITSIZE (tmode), MODE_INT, 0);
1155 x = convert_to_mode (smode, x, unsignedp);
1156 x = force_reg (smode, x);
1157 return gen_lowpart (tmode, x);
1160 return convert_to_mode (tmode, x, unsignedp);
1163 /* A subroutine of extract_bit_field, with the same arguments.
1164 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1165 if we can find no other means of implementing the operation.
1166 if FALLBACK_P is false, return NULL instead. */
1169 extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1170 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1171 enum machine_mode mode, enum machine_mode tmode,
1175 = (MEM_P (str_rtx)) ? BITS_PER_UNIT : BITS_PER_WORD;
1176 unsigned HOST_WIDE_INT offset, bitpos;
1178 enum machine_mode int_mode;
1179 enum machine_mode ext_mode;
1180 enum machine_mode mode1;
1181 enum insn_code icode;
1184 if (tmode == VOIDmode)
1187 while (GET_CODE (op0) == SUBREG)
1189 bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
1190 op0 = SUBREG_REG (op0);
1193 /* If we have an out-of-bounds access to a register, just return an
1194 uninitialized register of the required mode. This can occur if the
1195 source code contains an out-of-bounds access to a small array. */
1196 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
1197 return gen_reg_rtx (tmode);
1200 && mode == GET_MODE (op0)
1202 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1204 /* We're trying to extract a full register from itself. */
1208 /* See if we can get a better vector mode before extracting. */
1209 if (VECTOR_MODE_P (GET_MODE (op0))
1211 && GET_MODE_INNER (GET_MODE (op0)) != tmode)
1213 enum machine_mode new_mode;
1214 int nunits = GET_MODE_NUNITS (GET_MODE (op0));
1216 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1217 new_mode = MIN_MODE_VECTOR_FLOAT;
1218 else if (GET_MODE_CLASS (tmode) == MODE_FRACT)
1219 new_mode = MIN_MODE_VECTOR_FRACT;
1220 else if (GET_MODE_CLASS (tmode) == MODE_UFRACT)
1221 new_mode = MIN_MODE_VECTOR_UFRACT;
1222 else if (GET_MODE_CLASS (tmode) == MODE_ACCUM)
1223 new_mode = MIN_MODE_VECTOR_ACCUM;
1224 else if (GET_MODE_CLASS (tmode) == MODE_UACCUM)
1225 new_mode = MIN_MODE_VECTOR_UACCUM;
1227 new_mode = MIN_MODE_VECTOR_INT;
1229 for (; new_mode != VOIDmode ; new_mode = GET_MODE_WIDER_MODE (new_mode))
1230 if (GET_MODE_NUNITS (new_mode) == nunits
1231 && GET_MODE_SIZE (new_mode) == GET_MODE_SIZE (GET_MODE (op0))
1232 && targetm.vector_mode_supported_p (new_mode))
1234 if (new_mode != VOIDmode)
1235 op0 = gen_lowpart (new_mode, op0);
1238 /* Use vec_extract patterns for extracting parts of vectors whenever
1240 if (VECTOR_MODE_P (GET_MODE (op0))
1242 && optab_handler (vec_extract_optab, GET_MODE (op0)) != CODE_FOR_nothing
1243 && ((bitnum + bitsize - 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
1244 == bitnum / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
1246 enum machine_mode outermode = GET_MODE (op0);
1247 enum machine_mode innermode = GET_MODE_INNER (outermode);
1248 int icode = (int) optab_handler (vec_extract_optab, outermode);
1249 unsigned HOST_WIDE_INT pos = bitnum / GET_MODE_BITSIZE (innermode);
1250 rtx rtxpos = GEN_INT (pos);
1252 rtx dest = NULL, pat, seq;
1253 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
1254 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
1255 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
1257 if (innermode == tmode || innermode == mode)
1261 dest = gen_reg_rtx (innermode);
1265 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0))
1266 dest = copy_to_mode_reg (mode0, dest);
1268 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
1269 src = copy_to_mode_reg (mode1, src);
1271 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
1272 rtxpos = copy_to_mode_reg (mode1, rtxpos);
1274 /* We could handle this, but we should always be called with a pseudo
1275 for our targets and all insns should take them as outputs. */
1276 gcc_assert ((*insn_data[icode].operand[0].predicate) (dest, mode0)
1277 && (*insn_data[icode].operand[1].predicate) (src, mode1)
1278 && (*insn_data[icode].operand[2].predicate) (rtxpos, mode2));
1280 pat = GEN_FCN (icode) (dest, src, rtxpos);
1288 return gen_lowpart (tmode, dest);
1293 /* Make sure we are playing with integral modes. Pun with subregs
1296 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1297 if (imode != GET_MODE (op0))
1300 op0 = adjust_address (op0, imode, 0);
1301 else if (imode != BLKmode)
1303 op0 = gen_lowpart (imode, op0);
1305 /* If we got a SUBREG, force it into a register since we
1306 aren't going to be able to do another SUBREG on it. */
1307 if (GET_CODE (op0) == SUBREG)
1308 op0 = force_reg (imode, op0);
1310 else if (REG_P (op0))
1313 imode = smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0)),
1315 reg = gen_reg_rtx (imode);
1316 subreg = gen_lowpart_SUBREG (GET_MODE (op0), reg);
1317 emit_move_insn (subreg, op0);
1319 bitnum += SUBREG_BYTE (subreg) * BITS_PER_UNIT;
1323 rtx mem = assign_stack_temp (GET_MODE (op0),
1324 GET_MODE_SIZE (GET_MODE (op0)), 0);
1325 emit_move_insn (mem, op0);
1326 op0 = adjust_address (mem, BLKmode, 0);
1331 /* We may be accessing data outside the field, which means
1332 we can alias adjacent data. */
1335 op0 = shallow_copy_rtx (op0);
1336 set_mem_alias_set (op0, 0);
1337 set_mem_expr (op0, 0);
1340 /* Extraction of a full-word or multi-word value from a structure
1341 in a register or aligned memory can be done with just a SUBREG.
1342 A subword value in the least significant part of a register
1343 can also be extracted with a SUBREG. For this, we need the
1344 byte offset of the value in op0. */
1346 bitpos = bitnum % unit;
1347 offset = bitnum / unit;
1348 byte_offset = bitpos / BITS_PER_UNIT + offset * UNITS_PER_WORD;
1350 /* If OP0 is a register, BITPOS must count within a word.
1351 But as we have it, it counts within whatever size OP0 now has.
1352 On a bigendian machine, these are not the same, so convert. */
1353 if (BYTES_BIG_ENDIAN
1355 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1356 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1358 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1359 If that's wrong, the solution is to test for it and set TARGET to 0
1362 /* Only scalar integer modes can be converted via subregs. There is an
1363 additional problem for FP modes here in that they can have a precision
1364 which is different from the size. mode_for_size uses precision, but
1365 we want a mode based on the size, so we must avoid calling it for FP
1367 mode1 = (SCALAR_INT_MODE_P (tmode)
1368 ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)
1371 /* If the bitfield is volatile, we need to make sure the access
1372 remains on a type-aligned boundary. */
1373 if (GET_CODE (op0) == MEM
1374 && MEM_VOLATILE_P (op0)
1375 && GET_MODE_BITSIZE (GET_MODE (op0)) > 0
1376 && flag_strict_volatile_bitfields > 0)
1377 goto no_subreg_mode_swap;
1379 if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1380 && bitpos % BITS_PER_WORD == 0)
1381 || (mode1 != BLKmode
1382 /* ??? The big endian test here is wrong. This is correct
1383 if the value is in a register, and if mode_for_size is not
1384 the same mode as op0. This causes us to get unnecessarily
1385 inefficient code from the Thumb port when -mbig-endian. */
1386 && (BYTES_BIG_ENDIAN
1387 ? bitpos + bitsize == BITS_PER_WORD
1390 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode1),
1391 GET_MODE_BITSIZE (GET_MODE (op0)))
1392 && GET_MODE_SIZE (mode1) != 0
1393 && byte_offset % GET_MODE_SIZE (mode1) == 0)
1395 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0))
1396 || (offset * BITS_PER_UNIT % bitsize == 0
1397 && MEM_ALIGN (op0) % bitsize == 0)))))
1400 op0 = adjust_address (op0, mode1, offset);
1401 else if (mode1 != GET_MODE (op0))
1403 rtx sub = simplify_gen_subreg (mode1, op0, GET_MODE (op0),
1406 goto no_subreg_mode_swap;
1410 return convert_to_mode (tmode, op0, unsignedp);
1413 no_subreg_mode_swap:
1415 /* Handle fields bigger than a word. */
1417 if (bitsize > BITS_PER_WORD)
1419 /* Here we transfer the words of the field
1420 in the order least significant first.
1421 This is because the most significant word is the one which may
1422 be less than full. */
1424 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1427 if (target == 0 || !REG_P (target))
1428 target = gen_reg_rtx (mode);
1430 /* Indicate for flow that the entire target reg is being set. */
1431 emit_clobber (target);
1433 for (i = 0; i < nwords; i++)
1435 /* If I is 0, use the low-order word in both field and target;
1436 if I is 1, use the next to lowest word; and so on. */
1437 /* Word number in TARGET to use. */
1438 unsigned int wordnum
1440 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1442 /* Offset from start of field in OP0. */
1443 unsigned int bit_offset = (WORDS_BIG_ENDIAN
1444 ? MAX (0, ((int) bitsize - ((int) i + 1)
1445 * (int) BITS_PER_WORD))
1446 : (int) i * BITS_PER_WORD);
1447 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1449 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1450 bitsize - i * BITS_PER_WORD),
1451 bitnum + bit_offset, 1, target_part, mode,
1454 gcc_assert (target_part);
1456 if (result_part != target_part)
1457 emit_move_insn (target_part, result_part);
1462 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1463 need to be zero'd out. */
1464 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1466 unsigned int i, total_words;
1468 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1469 for (i = nwords; i < total_words; i++)
1471 (operand_subword (target,
1472 WORDS_BIG_ENDIAN ? total_words - i - 1 : i,
1479 /* Signed bit field: sign-extend with two arithmetic shifts. */
1480 target = expand_shift (LSHIFT_EXPR, mode, target,
1481 build_int_cst (NULL_TREE,
1482 GET_MODE_BITSIZE (mode) - bitsize),
1484 return expand_shift (RSHIFT_EXPR, mode, target,
1485 build_int_cst (NULL_TREE,
1486 GET_MODE_BITSIZE (mode) - bitsize),
1490 /* From here on we know the desired field is smaller than a word. */
1492 /* Check if there is a correspondingly-sized integer field, so we can
1493 safely extract it as one size of integer, if necessary; then
1494 truncate or extend to the size that is wanted; then use SUBREGs or
1495 convert_to_mode to get one of the modes we really wanted. */
1497 int_mode = int_mode_for_mode (tmode);
1498 if (int_mode == BLKmode)
1499 int_mode = int_mode_for_mode (mode);
1500 /* Should probably push op0 out to memory and then do a load. */
1501 gcc_assert (int_mode != BLKmode);
1503 /* OFFSET is the number of words or bytes (UNIT says which)
1504 from STR_RTX to the first word or byte containing part of the field. */
1508 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1511 op0 = copy_to_reg (op0);
1512 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1513 op0, (offset * UNITS_PER_WORD));
1518 /* Now OFFSET is nonzero only for memory operands. */
1519 ext_mode = mode_for_extraction (unsignedp ? EP_extzv : EP_extv, 0);
1520 icode = unsignedp ? CODE_FOR_extzv : CODE_FOR_extv;
1521 if (ext_mode != MAX_MACHINE_MODE
1523 && GET_MODE_BITSIZE (ext_mode) >= bitsize
1524 /* If op0 is a register, we need it in EXT_MODE to make it
1525 acceptable to the format of ext(z)v. */
1526 && !(GET_CODE (op0) == SUBREG && GET_MODE (op0) != ext_mode)
1527 && !((REG_P (op0) || GET_CODE (op0) == SUBREG)
1528 && (bitsize + bitpos > GET_MODE_BITSIZE (ext_mode)))
1529 && check_predicate_volatile_ok (icode, 1, op0, GET_MODE (op0)))
1531 unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
1532 rtx bitsize_rtx, bitpos_rtx;
1533 rtx last = get_last_insn ();
1535 rtx xtarget = target;
1536 rtx xspec_target = target;
1537 rtx xspec_target_subreg = 0;
1540 /* If op0 is a register, we need it in EXT_MODE to make it
1541 acceptable to the format of ext(z)v. */
1542 if (REG_P (xop0) && GET_MODE (xop0) != ext_mode)
1543 xop0 = gen_lowpart_SUBREG (ext_mode, xop0);
1545 /* Get ref to first byte containing part of the field. */
1546 xop0 = adjust_address (xop0, byte_mode, xoffset);
1548 /* On big-endian machines, we count bits from the most significant.
1549 If the bit field insn does not, we must invert. */
1550 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1551 xbitpos = unit - bitsize - xbitpos;
1553 /* Now convert from counting within UNIT to counting in EXT_MODE. */
1554 if (BITS_BIG_ENDIAN && !MEM_P (xop0))
1555 xbitpos += GET_MODE_BITSIZE (ext_mode) - unit;
1557 unit = GET_MODE_BITSIZE (ext_mode);
1560 xtarget = xspec_target = gen_reg_rtx (tmode);
1562 if (GET_MODE (xtarget) != ext_mode)
1564 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1565 between the mode of the extraction (word_mode) and the target
1566 mode. Instead, create a temporary and use convert_move to set
1569 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (xtarget)),
1570 GET_MODE_BITSIZE (ext_mode)))
1572 xtarget = gen_lowpart (ext_mode, xtarget);
1573 if (GET_MODE_SIZE (ext_mode)
1574 > GET_MODE_SIZE (GET_MODE (xspec_target)))
1575 xspec_target_subreg = xtarget;
1578 xtarget = gen_reg_rtx (ext_mode);
1581 /* If this machine's ext(z)v insists on a register target,
1582 make sure we have one. */
1583 if (!insn_data[(int) icode].operand[0].predicate (xtarget, ext_mode))
1584 xtarget = gen_reg_rtx (ext_mode);
1586 bitsize_rtx = GEN_INT (bitsize);
1587 bitpos_rtx = GEN_INT (xbitpos);
1590 ? gen_extzv (xtarget, xop0, bitsize_rtx, bitpos_rtx)
1591 : gen_extv (xtarget, xop0, bitsize_rtx, bitpos_rtx));
1595 if (xtarget == xspec_target)
1597 if (xtarget == xspec_target_subreg)
1598 return xspec_target;
1599 return convert_extracted_bit_field (xtarget, mode, tmode, unsignedp);
1601 delete_insns_since (last);
1604 /* If OP0 is a memory, try copying it to a register and seeing if a
1605 cheap register alternative is available. */
1606 if (ext_mode != MAX_MACHINE_MODE && MEM_P (op0))
1608 enum machine_mode bestmode;
1610 /* Get the mode to use for inserting into this field. If
1611 OP0 is BLKmode, get the smallest mode consistent with the
1612 alignment. If OP0 is a non-BLKmode object that is no
1613 wider than EXT_MODE, use its mode. Otherwise, use the
1614 smallest mode containing the field. */
1616 if (GET_MODE (op0) == BLKmode
1617 || (ext_mode != MAX_MACHINE_MODE
1618 && GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (ext_mode)))
1619 bestmode = get_best_mode (bitsize, bitnum, MEM_ALIGN (op0),
1620 (ext_mode == MAX_MACHINE_MODE
1621 ? VOIDmode : ext_mode),
1622 MEM_VOLATILE_P (op0));
1624 bestmode = GET_MODE (op0);
1626 if (bestmode != VOIDmode
1627 && !(SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
1628 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0)))
1630 unsigned HOST_WIDE_INT xoffset, xbitpos;
1632 /* Compute the offset as a multiple of this unit,
1633 counting in bytes. */
1634 unit = GET_MODE_BITSIZE (bestmode);
1635 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1636 xbitpos = bitnum % unit;
1638 /* Make sure the register is big enough for the whole field. */
1639 if (xoffset * BITS_PER_UNIT + unit
1640 >= offset * BITS_PER_UNIT + bitsize)
1642 rtx last, result, xop0;
1644 last = get_last_insn ();
1646 /* Fetch it to a register in that size. */
1647 xop0 = adjust_address (op0, bestmode, xoffset);
1648 xop0 = force_reg (bestmode, xop0);
1649 result = extract_bit_field_1 (xop0, bitsize, xbitpos,
1651 mode, tmode, false);
1655 delete_insns_since (last);
1663 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1664 bitpos, target, unsignedp);
1665 return convert_extracted_bit_field (target, mode, tmode, unsignedp);
1668 /* Generate code to extract a byte-field from STR_RTX
1669 containing BITSIZE bits, starting at BITNUM,
1670 and put it in TARGET if possible (if TARGET is nonzero).
1671 Regardless of TARGET, we return the rtx for where the value is placed.
1673 STR_RTX is the structure containing the byte (a REG or MEM).
1674 UNSIGNEDP is nonzero if this is an unsigned bit field.
1675 MODE is the natural mode of the field value once extracted.
1676 TMODE is the mode the caller would like the value to have;
1677 but the value may be returned with type MODE instead.
1679 If a TARGET is specified and we can store in it at no extra cost,
1680 we do so, and return TARGET.
1681 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1682 if they are equally easy. */
1685 extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1686 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1687 enum machine_mode mode, enum machine_mode tmode)
1689 return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp,
1690 target, mode, tmode, true);
1693 /* Extract a bit field using shifts and boolean operations
1694 Returns an rtx to represent the value.
1695 OP0 addresses a register (word) or memory (byte).
1696 BITPOS says which bit within the word or byte the bit field starts in.
1697 OFFSET says how many bytes farther the bit field starts;
1698 it is 0 if OP0 is a register.
1699 BITSIZE says how many bits long the bit field is.
1700 (If OP0 is a register, it may be narrower than a full word,
1701 but BITPOS still counts within a full word,
1702 which is significant on bigendian machines.)
1704 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1705 If TARGET is nonzero, attempts to store the value there
1706 and return TARGET, but this is not guaranteed.
1707 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1710 extract_fixed_bit_field (enum machine_mode tmode, rtx op0,
1711 unsigned HOST_WIDE_INT offset,
1712 unsigned HOST_WIDE_INT bitsize,
1713 unsigned HOST_WIDE_INT bitpos, rtx target,
1716 unsigned int total_bits = BITS_PER_WORD;
1717 enum machine_mode mode;
1719 if (GET_CODE (op0) == SUBREG || REG_P (op0))
1721 /* Special treatment for a bit field split across two registers. */
1722 if (bitsize + bitpos > BITS_PER_WORD)
1723 return extract_split_bit_field (op0, bitsize, bitpos, unsignedp);
1727 /* Get the proper mode to use for this field. We want a mode that
1728 includes the entire field. If such a mode would be larger than
1729 a word, we won't be doing the extraction the normal way. */
1731 if (MEM_VOLATILE_P (op0)
1732 && flag_strict_volatile_bitfields > 0)
1734 if (GET_MODE_BITSIZE (GET_MODE (op0)) > 0)
1735 mode = GET_MODE (op0);
1736 else if (target && GET_MODE_BITSIZE (GET_MODE (target)) > 0)
1737 mode = GET_MODE (target);
1742 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1743 MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0));
1745 if (mode == VOIDmode)
1746 /* The only way this should occur is if the field spans word
1748 return extract_split_bit_field (op0, bitsize,
1749 bitpos + offset * BITS_PER_UNIT,
1752 total_bits = GET_MODE_BITSIZE (mode);
1754 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1755 be in the range 0 to total_bits-1, and put any excess bytes in
1757 if (bitpos >= total_bits)
1759 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1760 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1764 /* If we're accessing a volatile MEM, we can't do the next
1765 alignment step if it results in a multi-word access where we
1766 otherwise wouldn't have one. So, check for that case
1769 && MEM_VOLATILE_P (op0)
1770 && flag_strict_volatile_bitfields > 0
1771 && bitpos + bitsize <= total_bits
1772 && bitpos + bitsize + (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT > total_bits)
1774 if (STRICT_ALIGNMENT)
1776 static bool informed_about_misalignment = false;
1779 if (bitsize == total_bits)
1780 warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
1781 "mis-aligned access used for structure member");
1783 warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
1784 "mis-aligned access used for structure bitfield");
1786 if (! informed_about_misalignment && warned)
1788 informed_about_misalignment = true;
1789 inform (input_location,
1790 "When a volatile object spans multiple type-sized locations,"
1791 " the compiler must choose between using a single mis-aligned access to"
1792 " preserve the volatility, or using multiple aligned accesses to avoid"
1793 " runtime faults. This code may fail at runtime if the hardware does"
1794 " not allow this access.");
1801 /* Get ref to an aligned byte, halfword, or word containing the field.
1802 Adjust BITPOS to be position within a word,
1803 and OFFSET to be the offset of that word.
1804 Then alter OP0 to refer to that word. */
1805 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1806 offset -= (offset % (total_bits / BITS_PER_UNIT));
1809 op0 = adjust_address (op0, mode, offset);
1812 mode = GET_MODE (op0);
1814 if (BYTES_BIG_ENDIAN)
1815 /* BITPOS is the distance between our msb and that of OP0.
1816 Convert it to the distance from the lsb. */
1817 bitpos = total_bits - bitsize - bitpos;
1819 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1820 We have reduced the big-endian case to the little-endian case. */
1826 /* If the field does not already start at the lsb,
1827 shift it so it does. */
1828 tree amount = build_int_cst (NULL_TREE, bitpos);
1829 /* Maybe propagate the target for the shift. */
1830 /* But not if we will return it--could confuse integrate.c. */
1831 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1832 if (tmode != mode) subtarget = 0;
1833 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1835 /* Convert the value to the desired mode. */
1837 op0 = convert_to_mode (tmode, op0, 1);
1839 /* Unless the msb of the field used to be the msb when we shifted,
1840 mask out the upper bits. */
1842 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
1843 return expand_binop (GET_MODE (op0), and_optab, op0,
1844 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1845 target, 1, OPTAB_LIB_WIDEN);
1849 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1850 then arithmetic-shift its lsb to the lsb of the word. */
1851 op0 = force_reg (mode, op0);
1855 /* Find the narrowest integer mode that contains the field. */
1857 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1858 mode = GET_MODE_WIDER_MODE (mode))
1859 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1861 op0 = convert_to_mode (mode, op0, 0);
1865 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1868 = build_int_cst (NULL_TREE,
1869 GET_MODE_BITSIZE (mode) - (bitsize + bitpos));
1870 /* Maybe propagate the target for the shift. */
1871 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1872 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1875 return expand_shift (RSHIFT_EXPR, mode, op0,
1876 build_int_cst (NULL_TREE,
1877 GET_MODE_BITSIZE (mode) - bitsize),
1881 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1882 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1883 complement of that if COMPLEMENT. The mask is truncated if
1884 necessary to the width of mode MODE. The mask is zero-extended if
1885 BITSIZE+BITPOS is too small for MODE. */
1888 mask_rtx (enum machine_mode mode, int bitpos, int bitsize, int complement)
1892 mask = double_int_mask (bitsize);
1893 mask = double_int_lshift (mask, bitpos, HOST_BITS_PER_DOUBLE_INT, false);
1896 mask = double_int_not (mask);
1898 return immed_double_int_const (mask, mode);
1901 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1902 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1905 lshift_value (enum machine_mode mode, rtx value, int bitpos, int bitsize)
1909 val = double_int_zext (uhwi_to_double_int (INTVAL (value)), bitsize);
1910 val = double_int_lshift (val, bitpos, HOST_BITS_PER_DOUBLE_INT, false);
1912 return immed_double_int_const (val, mode);
1915 /* Extract a bit field that is split across two words
1916 and return an RTX for the result.
1918 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1919 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1920 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1923 extract_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1924 unsigned HOST_WIDE_INT bitpos, int unsignedp)
1927 unsigned int bitsdone = 0;
1928 rtx result = NULL_RTX;
1931 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1933 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1934 unit = BITS_PER_WORD;
1936 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1938 while (bitsdone < bitsize)
1940 unsigned HOST_WIDE_INT thissize;
1942 unsigned HOST_WIDE_INT thispos;
1943 unsigned HOST_WIDE_INT offset;
1945 offset = (bitpos + bitsdone) / unit;
1946 thispos = (bitpos + bitsdone) % unit;
1948 /* THISSIZE must not overrun a word boundary. Otherwise,
1949 extract_fixed_bit_field will call us again, and we will mutually
1951 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1952 thissize = MIN (thissize, unit - thispos);
1954 /* If OP0 is a register, then handle OFFSET here.
1956 When handling multiword bitfields, extract_bit_field may pass
1957 down a word_mode SUBREG of a larger REG for a bitfield that actually
1958 crosses a word boundary. Thus, for a SUBREG, we must find
1959 the current word starting from the base register. */
1960 if (GET_CODE (op0) == SUBREG)
1962 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1963 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1964 GET_MODE (SUBREG_REG (op0)));
1967 else if (REG_P (op0))
1969 word = operand_subword_force (op0, offset, GET_MODE (op0));
1975 /* Extract the parts in bit-counting order,
1976 whose meaning is determined by BYTES_PER_UNIT.
1977 OFFSET is in UNITs, and UNIT is in bits.
1978 extract_fixed_bit_field wants offset in bytes. */
1979 part = extract_fixed_bit_field (word_mode, word,
1980 offset * unit / BITS_PER_UNIT,
1981 thissize, thispos, 0, 1);
1982 bitsdone += thissize;
1984 /* Shift this part into place for the result. */
1985 if (BYTES_BIG_ENDIAN)
1987 if (bitsize != bitsdone)
1988 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1989 build_int_cst (NULL_TREE, bitsize - bitsdone),
1994 if (bitsdone != thissize)
1995 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1996 build_int_cst (NULL_TREE,
1997 bitsdone - thissize), 0, 1);
2003 /* Combine the parts with bitwise or. This works
2004 because we extracted each part as an unsigned bit field. */
2005 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
2011 /* Unsigned bit field: we are done. */
2014 /* Signed bit field: sign-extend with two arithmetic shifts. */
2015 result = expand_shift (LSHIFT_EXPR, word_mode, result,
2016 build_int_cst (NULL_TREE, BITS_PER_WORD - bitsize),
2018 return expand_shift (RSHIFT_EXPR, word_mode, result,
2019 build_int_cst (NULL_TREE, BITS_PER_WORD - bitsize),
2023 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
2024 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
2025 MODE, fill the upper bits with zeros. Fail if the layout of either
2026 mode is unknown (as for CC modes) or if the extraction would involve
2027 unprofitable mode punning. Return the value on success, otherwise
2030 This is different from gen_lowpart* in these respects:
2032 - the returned value must always be considered an rvalue
2034 - when MODE is wider than SRC_MODE, the extraction involves
2037 - when MODE is smaller than SRC_MODE, the extraction involves
2038 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2040 In other words, this routine performs a computation, whereas the
2041 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2045 extract_low_bits (enum machine_mode mode, enum machine_mode src_mode, rtx src)
2047 enum machine_mode int_mode, src_int_mode;
2049 if (mode == src_mode)
2052 if (CONSTANT_P (src))
2054 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2055 fails, it will happily create (subreg (symbol_ref)) or similar
2057 unsigned int byte = subreg_lowpart_offset (mode, src_mode);
2058 rtx ret = simplify_subreg (mode, src, src_mode, byte);
2062 if (GET_MODE (src) == VOIDmode
2063 || !validate_subreg (mode, src_mode, src, byte))
2066 src = force_reg (GET_MODE (src), src);
2067 return gen_rtx_SUBREG (mode, src, byte);
2070 if (GET_MODE_CLASS (mode) == MODE_CC || GET_MODE_CLASS (src_mode) == MODE_CC)
2073 if (GET_MODE_BITSIZE (mode) == GET_MODE_BITSIZE (src_mode)
2074 && MODES_TIEABLE_P (mode, src_mode))
2076 rtx x = gen_lowpart_common (mode, src);
2081 src_int_mode = int_mode_for_mode (src_mode);
2082 int_mode = int_mode_for_mode (mode);
2083 if (src_int_mode == BLKmode || int_mode == BLKmode)
2086 if (!MODES_TIEABLE_P (src_int_mode, src_mode))
2088 if (!MODES_TIEABLE_P (int_mode, mode))
2091 src = gen_lowpart (src_int_mode, src);
2092 src = convert_modes (int_mode, src_int_mode, src, true);
2093 src = gen_lowpart (mode, src);
2097 /* Add INC into TARGET. */
2100 expand_inc (rtx target, rtx inc)
2102 rtx value = expand_binop (GET_MODE (target), add_optab,
2104 target, 0, OPTAB_LIB_WIDEN);
2105 if (value != target)
2106 emit_move_insn (target, value);
2109 /* Subtract DEC from TARGET. */
2112 expand_dec (rtx target, rtx dec)
2114 rtx value = expand_binop (GET_MODE (target), sub_optab,
2116 target, 0, OPTAB_LIB_WIDEN);
2117 if (value != target)
2118 emit_move_insn (target, value);
2121 /* Output a shift instruction for expression code CODE,
2122 with SHIFTED being the rtx for the value to shift,
2123 and AMOUNT the tree for the amount to shift by.
2124 Store the result in the rtx TARGET, if that is convenient.
2125 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2126 Return the rtx for where the value is. */
2129 expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
2130 tree amount, rtx target, int unsignedp)
2133 int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
2134 int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
2135 optab lshift_optab = ashl_optab;
2136 optab rshift_arith_optab = ashr_optab;
2137 optab rshift_uns_optab = lshr_optab;
2138 optab lrotate_optab = rotl_optab;
2139 optab rrotate_optab = rotr_optab;
2140 enum machine_mode op1_mode;
2142 bool speed = optimize_insn_for_speed_p ();
2144 op1 = expand_normal (amount);
2145 op1_mode = GET_MODE (op1);
2147 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2148 shift amount is a vector, use the vector/vector shift patterns. */
2149 if (VECTOR_MODE_P (mode) && VECTOR_MODE_P (op1_mode))
2151 lshift_optab = vashl_optab;
2152 rshift_arith_optab = vashr_optab;
2153 rshift_uns_optab = vlshr_optab;
2154 lrotate_optab = vrotl_optab;
2155 rrotate_optab = vrotr_optab;
2158 /* Previously detected shift-counts computed by NEGATE_EXPR
2159 and shifted in the other direction; but that does not work
2162 if (SHIFT_COUNT_TRUNCATED)
2164 if (CONST_INT_P (op1)
2165 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
2166 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
2167 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
2168 % GET_MODE_BITSIZE (mode));
2169 else if (GET_CODE (op1) == SUBREG
2170 && subreg_lowpart_p (op1)
2171 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (op1))))
2172 op1 = SUBREG_REG (op1);
2175 if (op1 == const0_rtx)
2178 /* Check whether its cheaper to implement a left shift by a constant
2179 bit count by a sequence of additions. */
2180 if (code == LSHIFT_EXPR
2181 && CONST_INT_P (op1)
2183 && INTVAL (op1) < GET_MODE_BITSIZE (mode)
2184 && INTVAL (op1) < MAX_BITS_PER_WORD
2185 && shift_cost[speed][mode][INTVAL (op1)] > INTVAL (op1) * add_cost[speed][mode]
2186 && shift_cost[speed][mode][INTVAL (op1)] != MAX_COST)
2189 for (i = 0; i < INTVAL (op1); i++)
2191 temp = force_reg (mode, shifted);
2192 shifted = expand_binop (mode, add_optab, temp, temp, NULL_RTX,
2193 unsignedp, OPTAB_LIB_WIDEN);
2198 for (attempt = 0; temp == 0 && attempt < 3; attempt++)
2200 enum optab_methods methods;
2203 methods = OPTAB_DIRECT;
2204 else if (attempt == 1)
2205 methods = OPTAB_WIDEN;
2207 methods = OPTAB_LIB_WIDEN;
2211 /* Widening does not work for rotation. */
2212 if (methods == OPTAB_WIDEN)
2214 else if (methods == OPTAB_LIB_WIDEN)
2216 /* If we have been unable to open-code this by a rotation,
2217 do it as the IOR of two shifts. I.e., to rotate A
2218 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2219 where C is the bitsize of A.
2221 It is theoretically possible that the target machine might
2222 not be able to perform either shift and hence we would
2223 be making two libcalls rather than just the one for the
2224 shift (similarly if IOR could not be done). We will allow
2225 this extremely unlikely lossage to avoid complicating the
2228 rtx subtarget = target == shifted ? 0 : target;
2229 tree new_amount, other_amount;
2231 tree type = TREE_TYPE (amount);
2232 if (GET_MODE (op1) != TYPE_MODE (type)
2233 && GET_MODE (op1) != VOIDmode)
2234 op1 = convert_to_mode (TYPE_MODE (type), op1, 1);
2235 new_amount = make_tree (type, op1);
2237 = fold_build2 (MINUS_EXPR, type,
2238 build_int_cst (type, GET_MODE_BITSIZE (mode)),
2241 shifted = force_reg (mode, shifted);
2243 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2244 mode, shifted, new_amount, 0, 1);
2245 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2246 mode, shifted, other_amount, subtarget, 1);
2247 return expand_binop (mode, ior_optab, temp, temp1, target,
2248 unsignedp, methods);
2251 temp = expand_binop (mode,
2252 left ? lrotate_optab : rrotate_optab,
2253 shifted, op1, target, unsignedp, methods);
2256 temp = expand_binop (mode,
2257 left ? lshift_optab : rshift_uns_optab,
2258 shifted, op1, target, unsignedp, methods);
2260 /* Do arithmetic shifts.
2261 Also, if we are going to widen the operand, we can just as well
2262 use an arithmetic right-shift instead of a logical one. */
2263 if (temp == 0 && ! rotate
2264 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2266 enum optab_methods methods1 = methods;
2268 /* If trying to widen a log shift to an arithmetic shift,
2269 don't accept an arithmetic shift of the same size. */
2271 methods1 = OPTAB_MUST_WIDEN;
2273 /* Arithmetic shift */
2275 temp = expand_binop (mode,
2276 left ? lshift_optab : rshift_arith_optab,
2277 shifted, op1, target, unsignedp, methods1);
2280 /* We used to try extzv here for logical right shifts, but that was
2281 only useful for one machine, the VAX, and caused poor code
2282 generation there for lshrdi3, so the code was deleted and a
2283 define_expand for lshrsi3 was added to vax.md. */
2290 /* Indicates the type of fixup needed after a constant multiplication.
2291 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2292 the result should be negated, and ADD_VARIANT means that the
2293 multiplicand should be added to the result. */
2294 enum mult_variant {basic_variant, negate_variant, add_variant};
2296 static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
2297 const struct mult_cost *, enum machine_mode mode);
2298 static bool choose_mult_variant (enum machine_mode, HOST_WIDE_INT,
2299 struct algorithm *, enum mult_variant *, int);
2300 static rtx expand_mult_const (enum machine_mode, rtx, HOST_WIDE_INT, rtx,
2301 const struct algorithm *, enum mult_variant);
2302 static unsigned HOST_WIDE_INT choose_multiplier (unsigned HOST_WIDE_INT, int,
2303 int, rtx *, int *, int *);
2304 static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
2305 static rtx extract_high_half (enum machine_mode, rtx);
2306 static rtx expand_mult_highpart (enum machine_mode, rtx, rtx, rtx, int, int);
2307 static rtx expand_mult_highpart_optab (enum machine_mode, rtx, rtx, rtx,
2309 /* Compute and return the best algorithm for multiplying by T.
2310 The algorithm must cost less than cost_limit
2311 If retval.cost >= COST_LIMIT, no algorithm was found and all
2312 other field of the returned struct are undefined.
2313 MODE is the machine mode of the multiplication. */
2316 synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
2317 const struct mult_cost *cost_limit, enum machine_mode mode)
2320 struct algorithm *alg_in, *best_alg;
2321 struct mult_cost best_cost;
2322 struct mult_cost new_limit;
2323 int op_cost, op_latency;
2324 unsigned HOST_WIDE_INT orig_t = t;
2325 unsigned HOST_WIDE_INT q;
2326 int maxm = MIN (BITS_PER_WORD, GET_MODE_BITSIZE (mode));
2328 bool cache_hit = false;
2329 enum alg_code cache_alg = alg_zero;
2330 bool speed = optimize_insn_for_speed_p ();
2332 /* Indicate that no algorithm is yet found. If no algorithm
2333 is found, this value will be returned and indicate failure. */
2334 alg_out->cost.cost = cost_limit->cost + 1;
2335 alg_out->cost.latency = cost_limit->latency + 1;
2337 if (cost_limit->cost < 0
2338 || (cost_limit->cost == 0 && cost_limit->latency <= 0))
2341 /* Restrict the bits of "t" to the multiplication's mode. */
2342 t &= GET_MODE_MASK (mode);
2344 /* t == 1 can be done in zero cost. */
2348 alg_out->cost.cost = 0;
2349 alg_out->cost.latency = 0;
2350 alg_out->op[0] = alg_m;
2354 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2358 if (MULT_COST_LESS (cost_limit, zero_cost[speed]))
2363 alg_out->cost.cost = zero_cost[speed];
2364 alg_out->cost.latency = zero_cost[speed];
2365 alg_out->op[0] = alg_zero;
2370 /* We'll be needing a couple extra algorithm structures now. */
2372 alg_in = XALLOCA (struct algorithm);
2373 best_alg = XALLOCA (struct algorithm);
2374 best_cost = *cost_limit;
2376 /* Compute the hash index. */
2377 hash_index = (t ^ (unsigned int) mode ^ (speed * 256)) % NUM_ALG_HASH_ENTRIES;
2379 /* See if we already know what to do for T. */
2380 if (alg_hash[hash_index].t == t
2381 && alg_hash[hash_index].mode == mode
2382 && alg_hash[hash_index].mode == mode
2383 && alg_hash[hash_index].speed == speed
2384 && alg_hash[hash_index].alg != alg_unknown)
2386 cache_alg = alg_hash[hash_index].alg;
2388 if (cache_alg == alg_impossible)
2390 /* The cache tells us that it's impossible to synthesize
2391 multiplication by T within alg_hash[hash_index].cost. */
2392 if (!CHEAPER_MULT_COST (&alg_hash[hash_index].cost, cost_limit))
2393 /* COST_LIMIT is at least as restrictive as the one
2394 recorded in the hash table, in which case we have no
2395 hope of synthesizing a multiplication. Just
2399 /* If we get here, COST_LIMIT is less restrictive than the
2400 one recorded in the hash table, so we may be able to
2401 synthesize a multiplication. Proceed as if we didn't
2402 have the cache entry. */
2406 if (CHEAPER_MULT_COST (cost_limit, &alg_hash[hash_index].cost))
2407 /* The cached algorithm shows that this multiplication
2408 requires more cost than COST_LIMIT. Just return. This
2409 way, we don't clobber this cache entry with
2410 alg_impossible but retain useful information. */
2422 goto do_alg_addsub_t_m2;
2424 case alg_add_factor:
2425 case alg_sub_factor:
2426 goto do_alg_addsub_factor;
2429 goto do_alg_add_t2_m;
2432 goto do_alg_sub_t2_m;
2440 /* If we have a group of zero bits at the low-order part of T, try
2441 multiplying by the remaining bits and then doing a shift. */
2446 m = floor_log2 (t & -t); /* m = number of low zero bits */
2450 /* The function expand_shift will choose between a shift and
2451 a sequence of additions, so the observed cost is given as
2452 MIN (m * add_cost[speed][mode], shift_cost[speed][mode][m]). */
2453 op_cost = m * add_cost[speed][mode];
2454 if (shift_cost[speed][mode][m] < op_cost)
2455 op_cost = shift_cost[speed][mode][m];
2456 new_limit.cost = best_cost.cost - op_cost;
2457 new_limit.latency = best_cost.latency - op_cost;
2458 synth_mult (alg_in, q, &new_limit, mode);
2460 alg_in->cost.cost += op_cost;
2461 alg_in->cost.latency += op_cost;
2462 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2464 struct algorithm *x;
2465 best_cost = alg_in->cost;
2466 x = alg_in, alg_in = best_alg, best_alg = x;
2467 best_alg->log[best_alg->ops] = m;
2468 best_alg->op[best_alg->ops] = alg_shift;
2471 /* See if treating ORIG_T as a signed number yields a better
2472 sequence. Try this sequence only for a negative ORIG_T
2473 as it would be useless for a non-negative ORIG_T. */
2474 if ((HOST_WIDE_INT) orig_t < 0)
2476 /* Shift ORIG_T as follows because a right shift of a
2477 negative-valued signed type is implementation
2479 q = ~(~orig_t >> m);
2480 /* The function expand_shift will choose between a shift
2481 and a sequence of additions, so the observed cost is
2482 given as MIN (m * add_cost[speed][mode],
2483 shift_cost[speed][mode][m]). */
2484 op_cost = m * add_cost[speed][mode];
2485 if (shift_cost[speed][mode][m] < op_cost)
2486 op_cost = shift_cost[speed][mode][m];
2487 new_limit.cost = best_cost.cost - op_cost;
2488 new_limit.latency = best_cost.latency - op_cost;
2489 synth_mult (alg_in, q, &new_limit, mode);
2491 alg_in->cost.cost += op_cost;
2492 alg_in->cost.latency += op_cost;
2493 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2495 struct algorithm *x;
2496 best_cost = alg_in->cost;
2497 x = alg_in, alg_in = best_alg, best_alg = x;
2498 best_alg->log[best_alg->ops] = m;
2499 best_alg->op[best_alg->ops] = alg_shift;
2507 /* If we have an odd number, add or subtract one. */
2510 unsigned HOST_WIDE_INT w;
2513 for (w = 1; (w & t) != 0; w <<= 1)
2515 /* If T was -1, then W will be zero after the loop. This is another
2516 case where T ends with ...111. Handling this with (T + 1) and
2517 subtract 1 produces slightly better code and results in algorithm
2518 selection much faster than treating it like the ...0111 case
2522 /* Reject the case where t is 3.
2523 Thus we prefer addition in that case. */
2526 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2528 op_cost = add_cost[speed][mode];
2529 new_limit.cost = best_cost.cost - op_cost;
2530 new_limit.latency = best_cost.latency - op_cost;
2531 synth_mult (alg_in, t + 1, &new_limit, mode);
2533 alg_in->cost.cost += op_cost;
2534 alg_in->cost.latency += op_cost;
2535 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2537 struct algorithm *x;
2538 best_cost = alg_in->cost;
2539 x = alg_in, alg_in = best_alg, best_alg = x;
2540 best_alg->log[best_alg->ops] = 0;
2541 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2546 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2548 op_cost = add_cost[speed][mode];
2549 new_limit.cost = best_cost.cost - op_cost;
2550 new_limit.latency = best_cost.latency - op_cost;
2551 synth_mult (alg_in, t - 1, &new_limit, mode);
2553 alg_in->cost.cost += op_cost;
2554 alg_in->cost.latency += op_cost;
2555 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2557 struct algorithm *x;
2558 best_cost = alg_in->cost;
2559 x = alg_in, alg_in = best_alg, best_alg = x;
2560 best_alg->log[best_alg->ops] = 0;
2561 best_alg->op[best_alg->ops] = alg_add_t_m2;
2565 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2566 quickly with a - a * n for some appropriate constant n. */
2567 m = exact_log2 (-orig_t + 1);
2568 if (m >= 0 && m < maxm)
2570 op_cost = shiftsub1_cost[speed][mode][m];
2571 new_limit.cost = best_cost.cost - op_cost;
2572 new_limit.latency = best_cost.latency - op_cost;
2573 synth_mult (alg_in, (unsigned HOST_WIDE_INT) (-orig_t + 1) >> m, &new_limit, mode);
2575 alg_in->cost.cost += op_cost;
2576 alg_in->cost.latency += op_cost;
2577 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2579 struct algorithm *x;
2580 best_cost = alg_in->cost;
2581 x = alg_in, alg_in = best_alg, best_alg = x;
2582 best_alg->log[best_alg->ops] = m;
2583 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2591 /* Look for factors of t of the form
2592 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2593 If we find such a factor, we can multiply by t using an algorithm that
2594 multiplies by q, shift the result by m and add/subtract it to itself.
2596 We search for large factors first and loop down, even if large factors
2597 are less probable than small; if we find a large factor we will find a
2598 good sequence quickly, and therefore be able to prune (by decreasing
2599 COST_LIMIT) the search. */
2601 do_alg_addsub_factor:
2602 for (m = floor_log2 (t - 1); m >= 2; m--)
2604 unsigned HOST_WIDE_INT d;
2606 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2607 if (t % d == 0 && t > d && m < maxm
2608 && (!cache_hit || cache_alg == alg_add_factor))
2610 /* If the target has a cheap shift-and-add instruction use
2611 that in preference to a shift insn followed by an add insn.
2612 Assume that the shift-and-add is "atomic" with a latency
2613 equal to its cost, otherwise assume that on superscalar
2614 hardware the shift may be executed concurrently with the
2615 earlier steps in the algorithm. */
2616 op_cost = add_cost[speed][mode] + shift_cost[speed][mode][m];
2617 if (shiftadd_cost[speed][mode][m] < op_cost)
2619 op_cost = shiftadd_cost[speed][mode][m];
2620 op_latency = op_cost;
2623 op_latency = add_cost[speed][mode];
2625 new_limit.cost = best_cost.cost - op_cost;
2626 new_limit.latency = best_cost.latency - op_latency;
2627 synth_mult (alg_in, t / d, &new_limit, mode);
2629 alg_in->cost.cost += op_cost;
2630 alg_in->cost.latency += op_latency;
2631 if (alg_in->cost.latency < op_cost)
2632 alg_in->cost.latency = op_cost;
2633 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2635 struct algorithm *x;
2636 best_cost = alg_in->cost;
2637 x = alg_in, alg_in = best_alg, best_alg = x;
2638 best_alg->log[best_alg->ops] = m;
2639 best_alg->op[best_alg->ops] = alg_add_factor;
2641 /* Other factors will have been taken care of in the recursion. */
2645 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2646 if (t % d == 0 && t > d && m < maxm
2647 && (!cache_hit || cache_alg == alg_sub_factor))
2649 /* If the target has a cheap shift-and-subtract insn use
2650 that in preference to a shift insn followed by a sub insn.
2651 Assume that the shift-and-sub is "atomic" with a latency
2652 equal to it's cost, otherwise assume that on superscalar
2653 hardware the shift may be executed concurrently with the
2654 earlier steps in the algorithm. */
2655 op_cost = add_cost[speed][mode] + shift_cost[speed][mode][m];
2656 if (shiftsub0_cost[speed][mode][m] < op_cost)
2658 op_cost = shiftsub0_cost[speed][mode][m];
2659 op_latency = op_cost;
2662 op_latency = add_cost[speed][mode];
2664 new_limit.cost = best_cost.cost - op_cost;
2665 new_limit.latency = best_cost.latency - op_latency;
2666 synth_mult (alg_in, t / d, &new_limit, mode);
2668 alg_in->cost.cost += op_cost;
2669 alg_in->cost.latency += op_latency;
2670 if (alg_in->cost.latency < op_cost)
2671 alg_in->cost.latency = op_cost;
2672 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2674 struct algorithm *x;
2675 best_cost = alg_in->cost;
2676 x = alg_in, alg_in = best_alg, best_alg = x;
2677 best_alg->log[best_alg->ops] = m;
2678 best_alg->op[best_alg->ops] = alg_sub_factor;
2686 /* Try shift-and-add (load effective address) instructions,
2687 i.e. do a*3, a*5, a*9. */
2694 if (m >= 0 && m < maxm)
2696 op_cost = shiftadd_cost[speed][mode][m];
2697 new_limit.cost = best_cost.cost - op_cost;
2698 new_limit.latency = best_cost.latency - op_cost;
2699 synth_mult (alg_in, (t - 1) >> m, &new_limit, mode);
2701 alg_in->cost.cost += op_cost;
2702 alg_in->cost.latency += op_cost;
2703 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2705 struct algorithm *x;
2706 best_cost = alg_in->cost;
2707 x = alg_in, alg_in = best_alg, best_alg = x;
2708 best_alg->log[best_alg->ops] = m;
2709 best_alg->op[best_alg->ops] = alg_add_t2_m;
2719 if (m >= 0 && m < maxm)
2721 op_cost = shiftsub0_cost[speed][mode][m];
2722 new_limit.cost = best_cost.cost - op_cost;
2723 new_limit.latency = best_cost.latency - op_cost;
2724 synth_mult (alg_in, (t + 1) >> m, &new_limit, mode);
2726 alg_in->cost.cost += op_cost;
2727 alg_in->cost.latency += op_cost;
2728 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2730 struct algorithm *x;
2731 best_cost = alg_in->cost;
2732 x = alg_in, alg_in = best_alg, best_alg = x;
2733 best_alg->log[best_alg->ops] = m;
2734 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2742 /* If best_cost has not decreased, we have not found any algorithm. */
2743 if (!CHEAPER_MULT_COST (&best_cost, cost_limit))
2745 /* We failed to find an algorithm. Record alg_impossible for
2746 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2747 we are asked to find an algorithm for T within the same or
2748 lower COST_LIMIT, we can immediately return to the
2750 alg_hash[hash_index].t = t;
2751 alg_hash[hash_index].mode = mode;
2752 alg_hash[hash_index].speed = speed;
2753 alg_hash[hash_index].alg = alg_impossible;
2754 alg_hash[hash_index].cost = *cost_limit;
2758 /* Cache the result. */
2761 alg_hash[hash_index].t = t;
2762 alg_hash[hash_index].mode = mode;
2763 alg_hash[hash_index].speed = speed;
2764 alg_hash[hash_index].alg = best_alg->op[best_alg->ops];
2765 alg_hash[hash_index].cost.cost = best_cost.cost;
2766 alg_hash[hash_index].cost.latency = best_cost.latency;
2769 /* If we are getting a too long sequence for `struct algorithm'
2770 to record, make this search fail. */
2771 if (best_alg->ops == MAX_BITS_PER_WORD)
2774 /* Copy the algorithm from temporary space to the space at alg_out.
2775 We avoid using structure assignment because the majority of
2776 best_alg is normally undefined, and this is a critical function. */
2777 alg_out->ops = best_alg->ops + 1;
2778 alg_out->cost = best_cost;
2779 memcpy (alg_out->op, best_alg->op,
2780 alg_out->ops * sizeof *alg_out->op);
2781 memcpy (alg_out->log, best_alg->log,
2782 alg_out->ops * sizeof *alg_out->log);
2785 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2786 Try three variations:
2788 - a shift/add sequence based on VAL itself
2789 - a shift/add sequence based on -VAL, followed by a negation
2790 - a shift/add sequence based on VAL - 1, followed by an addition.
2792 Return true if the cheapest of these cost less than MULT_COST,
2793 describing the algorithm in *ALG and final fixup in *VARIANT. */
2796 choose_mult_variant (enum machine_mode mode, HOST_WIDE_INT val,
2797 struct algorithm *alg, enum mult_variant *variant,
2800 struct algorithm alg2;
2801 struct mult_cost limit;
2803 bool speed = optimize_insn_for_speed_p ();
2805 /* Fail quickly for impossible bounds. */
2809 /* Ensure that mult_cost provides a reasonable upper bound.
2810 Any constant multiplication can be performed with less
2811 than 2 * bits additions. */
2812 op_cost = 2 * GET_MODE_BITSIZE (mode) * add_cost[speed][mode];
2813 if (mult_cost > op_cost)
2814 mult_cost = op_cost;
2816 *variant = basic_variant;
2817 limit.cost = mult_cost;
2818 limit.latency = mult_cost;
2819 synth_mult (alg, val, &limit, mode);
2821 /* This works only if the inverted value actually fits in an
2823 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2825 op_cost = neg_cost[speed][mode];
2826 if (MULT_COST_LESS (&alg->cost, mult_cost))
2828 limit.cost = alg->cost.cost - op_cost;
2829 limit.latency = alg->cost.latency - op_cost;
2833 limit.cost = mult_cost - op_cost;
2834 limit.latency = mult_cost - op_cost;
2837 synth_mult (&alg2, -val, &limit, mode);
2838 alg2.cost.cost += op_cost;
2839 alg2.cost.latency += op_cost;
2840 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
2841 *alg = alg2, *variant = negate_variant;
2844 /* This proves very useful for division-by-constant. */
2845 op_cost = add_cost[speed][mode];
2846 if (MULT_COST_LESS (&alg->cost, mult_cost))
2848 limit.cost = alg->cost.cost - op_cost;
2849 limit.latency = alg->cost.latency - op_cost;
2853 limit.cost = mult_cost - op_cost;
2854 limit.latency = mult_cost - op_cost;
2857 synth_mult (&alg2, val - 1, &limit, mode);
2858 alg2.cost.cost += op_cost;
2859 alg2.cost.latency += op_cost;
2860 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
2861 *alg = alg2, *variant = add_variant;
2863 return MULT_COST_LESS (&alg->cost, mult_cost);
2866 /* A subroutine of expand_mult, used for constant multiplications.
2867 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2868 convenient. Use the shift/add sequence described by ALG and apply
2869 the final fixup specified by VARIANT. */
2872 expand_mult_const (enum machine_mode mode, rtx op0, HOST_WIDE_INT val,
2873 rtx target, const struct algorithm *alg,
2874 enum mult_variant variant)
2876 HOST_WIDE_INT val_so_far;
2877 rtx insn, accum, tem;
2879 enum machine_mode nmode;
2881 /* Avoid referencing memory over and over and invalid sharing
2883 op0 = force_reg (mode, op0);
2885 /* ACCUM starts out either as OP0 or as a zero, depending on
2886 the first operation. */
2888 if (alg->op[0] == alg_zero)
2890 accum = copy_to_mode_reg (mode, const0_rtx);
2893 else if (alg->op[0] == alg_m)
2895 accum = copy_to_mode_reg (mode, op0);
2901 for (opno = 1; opno < alg->ops; opno++)
2903 int log = alg->log[opno];
2904 rtx shift_subtarget = optimize ? 0 : accum;
2906 = (opno == alg->ops - 1 && target != 0 && variant != add_variant
2909 rtx accum_target = optimize ? 0 : accum;
2911 switch (alg->op[opno])
2914 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2915 build_int_cst (NULL_TREE, log),
2921 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2922 build_int_cst (NULL_TREE, log),
2924 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2925 add_target ? add_target : accum_target);
2926 val_so_far += (HOST_WIDE_INT) 1 << log;
2930 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2931 build_int_cst (NULL_TREE, log),
2933 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2934 add_target ? add_target : accum_target);
2935 val_so_far -= (HOST_WIDE_INT) 1 << log;
2939 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2940 build_int_cst (NULL_TREE, log),
2943 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2944 add_target ? add_target : accum_target);
2945 val_so_far = (val_so_far << log) + 1;
2949 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2950 build_int_cst (NULL_TREE, log),
2951 shift_subtarget, 0);
2952 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2953 add_target ? add_target : accum_target);
2954 val_so_far = (val_so_far << log) - 1;
2957 case alg_add_factor:
2958 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2959 build_int_cst (NULL_TREE, log),
2961 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2962 add_target ? add_target : accum_target);
2963 val_so_far += val_so_far << log;
2966 case alg_sub_factor:
2967 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2968 build_int_cst (NULL_TREE, log),
2970 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2972 ? add_target : (optimize ? 0 : tem)));
2973 val_so_far = (val_so_far << log) - val_so_far;
2980 /* Write a REG_EQUAL note on the last insn so that we can cse
2981 multiplication sequences. Note that if ACCUM is a SUBREG,
2982 we've set the inner register and must properly indicate
2985 tem = op0, nmode = mode;
2986 if (GET_CODE (accum) == SUBREG)
2988 nmode = GET_MODE (SUBREG_REG (accum));
2989 tem = gen_lowpart (nmode, op0);
2992 insn = get_last_insn ();
2993 set_unique_reg_note (insn, REG_EQUAL,
2994 gen_rtx_MULT (nmode, tem,
2995 GEN_INT (val_so_far)));
2998 if (variant == negate_variant)
3000 val_so_far = -val_so_far;
3001 accum = expand_unop (mode, neg_optab, accum, target, 0);
3003 else if (variant == add_variant)
3005 val_so_far = val_so_far + 1;
3006 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
3009 /* Compare only the bits of val and val_so_far that are significant
3010 in the result mode, to avoid sign-/zero-extension confusion. */
3011 val &= GET_MODE_MASK (mode);
3012 val_so_far &= GET_MODE_MASK (mode);
3013 gcc_assert (val == val_so_far);
3018 /* Perform a multiplication and return an rtx for the result.
3019 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3020 TARGET is a suggestion for where to store the result (an rtx).
3022 We check specially for a constant integer as OP1.
3023 If you want this check for OP0 as well, then before calling
3024 you should swap the two operands if OP0 would be constant. */
3027 expand_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
3030 enum mult_variant variant;
3031 struct algorithm algorithm;
3033 bool speed = optimize_insn_for_speed_p ();
3035 /* Handling const0_rtx here allows us to use zero as a rogue value for
3037 if (op1 == const0_rtx)
3039 if (op1 == const1_rtx)
3041 if (op1 == constm1_rtx)
3042 return expand_unop (mode,
3043 GET_MODE_CLASS (mode) == MODE_INT
3044 && !unsignedp && flag_trapv
3045 ? negv_optab : neg_optab,
3048 /* These are the operations that are potentially turned into a sequence
3049 of shifts and additions. */
3050 if (SCALAR_INT_MODE_P (mode)
3051 && (unsignedp || !flag_trapv))
3053 HOST_WIDE_INT coeff = 0;
3054 rtx fake_reg = gen_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
3056 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3057 less than or equal in size to `unsigned int' this doesn't matter.
3058 If the mode is larger than `unsigned int', then synth_mult works
3059 only if the constant value exactly fits in an `unsigned int' without
3060 any truncation. This means that multiplying by negative values does
3061 not work; results are off by 2^32 on a 32 bit machine. */
3063 if (CONST_INT_P (op1))
3065 /* Attempt to handle multiplication of DImode values by negative
3066 coefficients, by performing the multiplication by a positive
3067 multiplier and then inverting the result. */
3068 if (INTVAL (op1) < 0
3069 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
3071 /* Its safe to use -INTVAL (op1) even for INT_MIN, as the
3072 result is interpreted as an unsigned coefficient.
3073 Exclude cost of op0 from max_cost to match the cost
3074 calculation of the synth_mult. */
3075 max_cost = rtx_cost (gen_rtx_MULT (mode, fake_reg, op1), SET, speed)
3076 - neg_cost[speed][mode];
3078 && choose_mult_variant (mode, -INTVAL (op1), &algorithm,
3079 &variant, max_cost))
3081 rtx temp = expand_mult_const (mode, op0, -INTVAL (op1),
3082 NULL_RTX, &algorithm,
3084 return expand_unop (mode, neg_optab, temp, target, 0);
3087 else coeff = INTVAL (op1);
3089 else if (GET_CODE (op1) == CONST_DOUBLE)
3091 /* If we are multiplying in DImode, it may still be a win
3092 to try to work with shifts and adds. */
3093 if (CONST_DOUBLE_HIGH (op1) == 0
3094 && CONST_DOUBLE_LOW (op1) > 0)
3095 coeff = CONST_DOUBLE_LOW (op1);
3096 else if (CONST_DOUBLE_LOW (op1) == 0
3097 && EXACT_POWER_OF_2_OR_ZERO_P (CONST_DOUBLE_HIGH (op1)))
3099 int shift = floor_log2 (CONST_DOUBLE_HIGH (op1))
3100 + HOST_BITS_PER_WIDE_INT;
3101 return expand_shift (LSHIFT_EXPR, mode, op0,
3102 build_int_cst (NULL_TREE, shift),
3107 /* We used to test optimize here, on the grounds that it's better to
3108 produce a smaller program when -O is not used. But this causes
3109 such a terrible slowdown sometimes that it seems better to always
3113 /* Special case powers of two. */
3114 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3115 return expand_shift (LSHIFT_EXPR, mode, op0,
3116 build_int_cst (NULL_TREE, floor_log2 (coeff)),
3119 /* Exclude cost of op0 from max_cost to match the cost
3120 calculation of the synth_mult. */
3121 max_cost = rtx_cost (gen_rtx_MULT (mode, fake_reg, op1), SET, speed);
3122 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3124 return expand_mult_const (mode, op0, coeff, target,
3125 &algorithm, variant);
3129 if (GET_CODE (op0) == CONST_DOUBLE)
3136 /* Expand x*2.0 as x+x. */
3137 if (GET_CODE (op1) == CONST_DOUBLE
3138 && SCALAR_FLOAT_MODE_P (mode))
3141 REAL_VALUE_FROM_CONST_DOUBLE (d, op1);
3143 if (REAL_VALUES_EQUAL (d, dconst2))
3145 op0 = force_reg (GET_MODE (op0), op0);
3146 return expand_binop (mode, add_optab, op0, op0,
3147 target, unsignedp, OPTAB_LIB_WIDEN);
3151 /* This used to use umul_optab if unsigned, but for non-widening multiply
3152 there is no difference between signed and unsigned. */
3153 op0 = expand_binop (mode,
3155 && flag_trapv && (GET_MODE_CLASS(mode) == MODE_INT)
3156 ? smulv_optab : smul_optab,
3157 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
3162 /* Perform a widening multiplication and return an rtx for the result.
3163 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3164 TARGET is a suggestion for where to store the result (an rtx).
3165 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3166 or smul_widen_optab.
3168 We check specially for a constant integer as OP1, comparing the
3169 cost of a widening multiply against the cost of a sequence of shifts
3173 expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
3174 int unsignedp, optab this_optab)
3176 bool speed = optimize_insn_for_speed_p ();
3178 if (CONST_INT_P (op1)
3179 && (INTVAL (op1) >= 0
3180 || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT))
3182 HOST_WIDE_INT coeff = INTVAL (op1);
3184 enum mult_variant variant;
3185 struct algorithm algorithm;
3187 /* Special case powers of two. */
3188 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3190 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3191 return expand_shift (LSHIFT_EXPR, mode, op0,
3192 build_int_cst (NULL_TREE, floor_log2 (coeff)),
3196 /* Exclude cost of op0 from max_cost to match the cost
3197 calculation of the synth_mult. */
3198 max_cost = mul_widen_cost[speed][mode];
3199 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3202 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3203 return expand_mult_const (mode, op0, coeff, target,
3204 &algorithm, variant);
3207 return expand_binop (mode, this_optab, op0, op1, target,
3208 unsignedp, OPTAB_LIB_WIDEN);
3211 /* Return the smallest n such that 2**n >= X. */
3214 ceil_log2 (unsigned HOST_WIDE_INT x)
3216 return floor_log2 (x - 1) + 1;
3219 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3220 replace division by D, and put the least significant N bits of the result
3221 in *MULTIPLIER_PTR and return the most significant bit.
3223 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3224 needed precision is in PRECISION (should be <= N).
3226 PRECISION should be as small as possible so this function can choose
3227 multiplier more freely.
3229 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3230 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3232 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3233 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3236 unsigned HOST_WIDE_INT
3237 choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision,
3238 rtx *multiplier_ptr, int *post_shift_ptr, int *lgup_ptr)
3240 HOST_WIDE_INT mhigh_hi, mlow_hi;
3241 unsigned HOST_WIDE_INT mhigh_lo, mlow_lo;
3242 int lgup, post_shift;
3244 unsigned HOST_WIDE_INT nl, dummy1;
3245 HOST_WIDE_INT nh, dummy2;
3247 /* lgup = ceil(log2(divisor)); */
3248 lgup = ceil_log2 (d);
3250 gcc_assert (lgup <= n);
3253 pow2 = n + lgup - precision;
3255 /* We could handle this with some effort, but this case is much
3256 better handled directly with a scc insn, so rely on caller using
3258 gcc_assert (pow != 2 * HOST_BITS_PER_WIDE_INT);
3260 /* mlow = 2^(N + lgup)/d */
3261 if (pow >= HOST_BITS_PER_WIDE_INT)
3263 nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
3269 nl = (unsigned HOST_WIDE_INT) 1 << pow;
3271 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
3272 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
3274 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
3275 if (pow2 >= HOST_BITS_PER_WIDE_INT)
3276 nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
3278 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
3279 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
3280 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
3282 gcc_assert (!mhigh_hi || nh - d < d);
3283 gcc_assert (mhigh_hi <= 1 && mlow_hi <= 1);
3284 /* Assert that mlow < mhigh. */
3285 gcc_assert (mlow_hi < mhigh_hi
3286 || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo));
3288 /* If precision == N, then mlow, mhigh exceed 2^N
3289 (but they do not exceed 2^(N+1)). */
3291 /* Reduce to lowest terms. */
3292 for (post_shift = lgup; post_shift > 0; post_shift--)
3294 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
3295 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
3305 *post_shift_ptr = post_shift;
3307 if (n < HOST_BITS_PER_WIDE_INT)
3309 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
3310 *multiplier_ptr = GEN_INT (mhigh_lo & mask);
3311 return mhigh_lo >= mask;
3315 *multiplier_ptr = GEN_INT (mhigh_lo);
3320 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3321 congruent to 1 (mod 2**N). */
3323 static unsigned HOST_WIDE_INT
3324 invert_mod2n (unsigned HOST_WIDE_INT x, int n)
3326 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3328 /* The algorithm notes that the choice y = x satisfies
3329 x*y == 1 mod 2^3, since x is assumed odd.
3330 Each iteration doubles the number of bits of significance in y. */
3332 unsigned HOST_WIDE_INT mask;
3333 unsigned HOST_WIDE_INT y = x;
3336 mask = (n == HOST_BITS_PER_WIDE_INT
3337 ? ~(unsigned HOST_WIDE_INT) 0
3338 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
3342 y = y * (2 - x*y) & mask; /* Modulo 2^N */
3348 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3349 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3350 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3351 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3354 The result is put in TARGET if that is convenient.
3356 MODE is the mode of operation. */
3359 expand_mult_highpart_adjust (enum machine_mode mode, rtx adj_operand, rtx op0,
3360 rtx op1, rtx target, int unsignedp)
3363 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
3365 tem = expand_shift (RSHIFT_EXPR, mode, op0,
3366 build_int_cst (NULL_TREE, GET_MODE_BITSIZE (mode) - 1),
3368 tem = expand_and (mode, tem, op1, NULL_RTX);
3370 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3373 tem = expand_shift (RSHIFT_EXPR, mode, op1,
3374 build_int_cst (NULL_TREE, GET_MODE_BITSIZE (mode) - 1),
3376 tem = expand_and (mode, tem, op0, NULL_RTX);
3377 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3383 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
3386 extract_high_half (enum machine_mode mode, rtx op)
3388 enum machine_mode wider_mode;
3390 if (mode == word_mode)
3391 return gen_highpart (mode, op);
3393 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3395 wider_mode = GET_MODE_WIDER_MODE (mode);
3396 op = expand_shift (RSHIFT_EXPR, wider_mode, op,
3397 build_int_cst (NULL_TREE, GET_MODE_BITSIZE (mode)), 0, 1);
3398 return convert_modes (mode, wider_mode, op, 0);
3401 /* Like expand_mult_highpart, but only consider using a multiplication
3402 optab. OP1 is an rtx for the constant operand. */
3405 expand_mult_highpart_optab (enum machine_mode mode, rtx op0, rtx op1,
3406 rtx target, int unsignedp, int max_cost)
3408 rtx narrow_op1 = gen_int_mode (INTVAL (op1), mode);
3409 enum machine_mode wider_mode;
3413 bool speed = optimize_insn_for_speed_p ();
3415 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3417 wider_mode = GET_MODE_WIDER_MODE (mode);
3418 size = GET_MODE_BITSIZE (mode);
3420 /* Firstly, try using a multiplication insn that only generates the needed
3421 high part of the product, and in the sign flavor of unsignedp. */
3422 if (mul_highpart_cost[speed][mode] < max_cost)
3424 moptab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
3425 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3426 unsignedp, OPTAB_DIRECT);
3431 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3432 Need to adjust the result after the multiplication. */
3433 if (size - 1 < BITS_PER_WORD
3434 && (mul_highpart_cost[speed][mode] + 2 * shift_cost[speed][mode][size-1]
3435 + 4 * add_cost[speed][mode] < max_cost))
3437 moptab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
3438 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3439 unsignedp, OPTAB_DIRECT);
3441 /* We used the wrong signedness. Adjust the result. */
3442 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3446 /* Try widening multiplication. */
3447 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
3448 if (optab_handler (moptab, wider_mode) != CODE_FOR_nothing
3449 && mul_widen_cost[speed][wider_mode] < max_cost)
3451 tem = expand_binop (wider_mode, moptab, op0, narrow_op1, 0,
3452 unsignedp, OPTAB_WIDEN);
3454 return extract_high_half (mode, tem);
3457 /* Try widening the mode and perform a non-widening multiplication. */
3458 if (optab_handler (smul_optab, wider_mode) != CODE_FOR_nothing
3459 && size - 1 < BITS_PER_WORD
3460 && mul_cost[speed][wider_mode] + shift_cost[speed][mode][size-1] < max_cost)
3462 rtx insns, wop0, wop1;
3464 /* We need to widen the operands, for example to ensure the
3465 constant multiplier is correctly sign or zero extended.
3466 Use a sequence to clean-up any instructions emitted by
3467 the conversions if things don't work out. */
3469 wop0 = convert_modes (wider_mode, mode, op0, unsignedp);
3470 wop1 = convert_modes (wider_mode, mode, op1, unsignedp);
3471 tem = expand_binop (wider_mode, smul_optab, wop0, wop1, 0,
3472 unsignedp, OPTAB_WIDEN);
3473 insns = get_insns ();
3479 return extract_high_half (mode, tem);
3483 /* Try widening multiplication of opposite signedness, and adjust. */
3484 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
3485 if (optab_handler (moptab, wider_mode) != CODE_FOR_nothing
3486 && size - 1 < BITS_PER_WORD
3487 && (mul_widen_cost[speed][wider_mode] + 2 * shift_cost[speed][mode][size-1]
3488 + 4 * add_cost[speed][mode] < max_cost))
3490 tem = expand_binop (wider_mode, moptab, op0, narrow_op1,
3491 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
3494 tem = extract_high_half (mode, tem);
3495 /* We used the wrong signedness. Adjust the result. */
3496 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3504 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3505 putting the high half of the result in TARGET if that is convenient,
3506 and return where the result is. If the operation can not be performed,
3509 MODE is the mode of operation and result.
3511 UNSIGNEDP nonzero means unsigned multiply.
3513 MAX_COST is the total allowed cost for the expanded RTL. */
3516 expand_mult_highpart (enum machine_mode mode, rtx op0, rtx op1,
3517 rtx target, int unsignedp, int max_cost)
3519 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
3520 unsigned HOST_WIDE_INT cnst1;
3522 bool sign_adjust = false;
3523 enum mult_variant variant;
3524 struct algorithm alg;
3526 bool speed = optimize_insn_for_speed_p ();
3528 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3529 /* We can't support modes wider than HOST_BITS_PER_INT. */
3530 gcc_assert (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT);
3532 cnst1 = INTVAL (op1) & GET_MODE_MASK (mode);
3534 /* We can't optimize modes wider than BITS_PER_WORD.
3535 ??? We might be able to perform double-word arithmetic if
3536 mode == word_mode, however all the cost calculations in
3537 synth_mult etc. assume single-word operations. */
3538 if (GET_MODE_BITSIZE (wider_mode) > BITS_PER_WORD)
3539 return expand_mult_highpart_optab (mode, op0, op1, target,
3540 unsignedp, max_cost);
3542 extra_cost = shift_cost[speed][mode][GET_MODE_BITSIZE (mode) - 1];
3544 /* Check whether we try to multiply by a negative constant. */
3545 if (!unsignedp && ((cnst1 >> (GET_MODE_BITSIZE (mode) - 1)) & 1))
3548 extra_cost += add_cost[speed][mode];
3551 /* See whether shift/add multiplication is cheap enough. */
3552 if (choose_mult_variant (wider_mode, cnst1, &alg, &variant,
3553 max_cost - extra_cost))
3555 /* See whether the specialized multiplication optabs are
3556 cheaper than the shift/add version. */
3557 tem = expand_mult_highpart_optab (mode, op0, op1, target, unsignedp,
3558 alg.cost.cost + extra_cost);
3562 tem = convert_to_mode (wider_mode, op0, unsignedp);
3563 tem = expand_mult_const (wider_mode, tem, cnst1, 0, &alg, variant);
3564 tem = extract_high_half (mode, tem);
3566 /* Adjust result for signedness. */
3568 tem = force_operand (gen_rtx_MINUS (mode, tem, op0), tem);
3572 return expand_mult_highpart_optab (mode, op0, op1, target,
3573 unsignedp, max_cost);
3577 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3580 expand_smod_pow2 (enum machine_mode mode, rtx op0, HOST_WIDE_INT d)
3582 unsigned HOST_WIDE_INT masklow, maskhigh;
3583 rtx result, temp, shift, label;
3586 logd = floor_log2 (d);
3587 result = gen_reg_rtx (mode);
3589 /* Avoid conditional branches when they're expensive. */
3590 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3591 && optimize_insn_for_speed_p ())
3593 rtx signmask = emit_store_flag (result, LT, op0, const0_rtx,
3597 signmask = force_reg (mode, signmask);
3598 masklow = ((HOST_WIDE_INT) 1 << logd) - 1;
3599 shift = GEN_INT (GET_MODE_BITSIZE (mode) - logd);
3601 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3602 which instruction sequence to use. If logical right shifts
3603 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3604 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3606 temp = gen_rtx_LSHIFTRT (mode, result, shift);
3607 if (optab_handler (lshr_optab, mode) == CODE_FOR_nothing
3608 || rtx_cost (temp, SET, optimize_insn_for_speed_p ()) > COSTS_N_INSNS (2))
3610 temp = expand_binop (mode, xor_optab, op0, signmask,
3611 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3612 temp = expand_binop (mode, sub_optab, temp, signmask,
3613 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3614 temp = expand_binop (mode, and_optab, temp, GEN_INT (masklow),
3615 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3616 temp = expand_binop (mode, xor_optab, temp, signmask,
3617 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3618 temp = expand_binop (mode, sub_optab, temp, signmask,
3619 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3623 signmask = expand_binop (mode, lshr_optab, signmask, shift,
3624 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3625 signmask = force_reg (mode, signmask);
3627 temp = expand_binop (mode, add_optab, op0, signmask,
3628 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3629 temp = expand_binop (mode, and_optab, temp, GEN_INT (masklow),
3630 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3631 temp = expand_binop (mode, sub_optab, temp, signmask,
3632 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3638 /* Mask contains the mode's signbit and the significant bits of the
3639 modulus. By including the signbit in the operation, many targets
3640 can avoid an explicit compare operation in the following comparison
3643 masklow = ((HOST_WIDE_INT) 1 << logd) - 1;
3644 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3646 masklow |= (HOST_WIDE_INT) -1 << (GET_MODE_BITSIZE (mode) - 1);
3650 maskhigh = (HOST_WIDE_INT) -1
3651 << (GET_MODE_BITSIZE (mode) - HOST_BITS_PER_WIDE_INT - 1);
3653 temp = expand_binop (mode, and_optab, op0,
3654 immed_double_const (masklow, maskhigh, mode),
3655 result, 1, OPTAB_LIB_WIDEN);
3657 emit_move_insn (result, temp);
3659 label = gen_label_rtx ();
3660 do_cmp_and_jump (result, const0_rtx, GE, mode, label);
3662 temp = expand_binop (mode, sub_optab, result, const1_rtx, result,
3663 0, OPTAB_LIB_WIDEN);
3664 masklow = (HOST_WIDE_INT) -1 << logd;
3666 temp = expand_binop (mode, ior_optab, temp,
3667 immed_double_const (masklow, maskhigh, mode),
3668 result, 1, OPTAB_LIB_WIDEN);
3669 temp = expand_binop (mode, add_optab, temp, const1_rtx, result,
3670 0, OPTAB_LIB_WIDEN);
3672 emit_move_insn (result, temp);
3677 /* Expand signed division of OP0 by a power of two D in mode MODE.
3678 This routine is only called for positive values of D. */
3681 expand_sdiv_pow2 (enum machine_mode mode, rtx op0, HOST_WIDE_INT d)
3687 logd = floor_log2 (d);
3688 shift = build_int_cst (NULL_TREE, logd);
3691 && BRANCH_COST (optimize_insn_for_speed_p (),
3694 temp = gen_reg_rtx (mode);
3695 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, 1);
3696 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3697 0, OPTAB_LIB_WIDEN);
3698 return expand_shift (RSHIFT_EXPR, mode, temp, shift, NULL_RTX, 0);
3701 #ifdef HAVE_conditional_move
3702 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3707 /* ??? emit_conditional_move forces a stack adjustment via
3708 compare_from_rtx so, if the sequence is discarded, it will
3709 be lost. Do it now instead. */
3710 do_pending_stack_adjust ();
3713 temp2 = copy_to_mode_reg (mode, op0);
3714 temp = expand_binop (mode, add_optab, temp2, GEN_INT (d-1),
3715 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3716 temp = force_reg (mode, temp);
3718 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3719 temp2 = emit_conditional_move (temp2, LT, temp2, const0_rtx,
3720 mode, temp, temp2, mode, 0);
3723 rtx seq = get_insns ();
3726 return expand_shift (RSHIFT_EXPR, mode, temp2, shift, NULL_RTX, 0);
3732 if (BRANCH_COST (optimize_insn_for_speed_p (),
3735 int ushift = GET_MODE_BITSIZE (mode) - logd;
3737 temp = gen_reg_rtx (mode);
3738 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, -1);
3739 if (shift_cost[optimize_insn_for_speed_p ()][mode][ushift] > COSTS_N_INSNS (1))
3740 temp = expand_binop (mode, and_optab, temp, GEN_INT (d - 1),
3741 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3743 temp = expand_shift (RSHIFT_EXPR, mode, temp,
3744 build_int_cst (NULL_TREE, ushift),
3746 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3747 0, OPTAB_LIB_WIDEN);
3748 return expand_shift (RSHIFT_EXPR, mode, temp, shift, NULL_RTX, 0);
3751 label = gen_label_rtx ();
3752 temp = copy_to_mode_reg (mode, op0);
3753 do_cmp_and_jump (temp, const0_rtx, GE, mode, label);
3754 expand_inc (temp, GEN_INT (d - 1));
3756 return expand_shift (RSHIFT_EXPR, mode, temp, shift, NULL_RTX, 0);
3759 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3760 if that is convenient, and returning where the result is.
3761 You may request either the quotient or the remainder as the result;
3762 specify REM_FLAG nonzero to get the remainder.
3764 CODE is the expression code for which kind of division this is;
3765 it controls how rounding is done. MODE is the machine mode to use.
3766 UNSIGNEDP nonzero means do unsigned division. */
3768 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3769 and then correct it by or'ing in missing high bits
3770 if result of ANDI is nonzero.
3771 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3772 This could optimize to a bfexts instruction.
3773 But C doesn't use these operations, so their optimizations are
3775 /* ??? For modulo, we don't actually need the highpart of the first product,
3776 the low part will do nicely. And for small divisors, the second multiply
3777 can also be a low-part only multiply or even be completely left out.
3778 E.g. to calculate the remainder of a division by 3 with a 32 bit
3779 multiply, multiply with 0x55555556 and extract the upper two bits;
3780 the result is exact for inputs up to 0x1fffffff.
3781 The input range can be reduced by using cross-sum rules.
3782 For odd divisors >= 3, the following table gives right shift counts
3783 so that if a number is shifted by an integer multiple of the given
3784 amount, the remainder stays the same:
3785 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3786 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3787 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3788 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3789 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3791 Cross-sum rules for even numbers can be derived by leaving as many bits
3792 to the right alone as the divisor has zeros to the right.
3793 E.g. if x is an unsigned 32 bit number:
3794 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3798 expand_divmod (int rem_flag, enum tree_code code, enum machine_mode mode,
3799 rtx op0, rtx op1, rtx target, int unsignedp)
3801 enum machine_mode compute_mode;
3803 rtx quotient = 0, remainder = 0;
3807 optab optab1, optab2;
3808 int op1_is_constant, op1_is_pow2 = 0;
3809 int max_cost, extra_cost;
3810 static HOST_WIDE_INT last_div_const = 0;
3811 static HOST_WIDE_INT ext_op1;
3812 bool speed = optimize_insn_for_speed_p ();
3814 op1_is_constant = CONST_INT_P (op1);
3815 if (op1_is_constant)
3817 ext_op1 = INTVAL (op1);
3819 ext_op1 &= GET_MODE_MASK (mode);
3820 op1_is_pow2 = ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1)
3821 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1))));
3825 This is the structure of expand_divmod:
3827 First comes code to fix up the operands so we can perform the operations
3828 correctly and efficiently.
3830 Second comes a switch statement with code specific for each rounding mode.
3831 For some special operands this code emits all RTL for the desired
3832 operation, for other cases, it generates only a quotient and stores it in
3833 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3834 to indicate that it has not done anything.
3836 Last comes code that finishes the operation. If QUOTIENT is set and
3837 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3838 QUOTIENT is not set, it is computed using trunc rounding.
3840 We try to generate special code for division and remainder when OP1 is a
3841 constant. If |OP1| = 2**n we can use shifts and some other fast
3842 operations. For other values of OP1, we compute a carefully selected
3843 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3846 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3847 half of the product. Different strategies for generating the product are
3848 implemented in expand_mult_highpart.
3850 If what we actually want is the remainder, we generate that by another
3851 by-constant multiplication and a subtraction. */
3853 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3854 code below will malfunction if we are, so check here and handle
3855 the special case if so. */
3856 if (op1 == const1_rtx)
3857 return rem_flag ? const0_rtx : op0;
3859 /* When dividing by -1, we could get an overflow.
3860 negv_optab can handle overflows. */
3861 if (! unsignedp && op1 == constm1_rtx)
3865 return expand_unop (mode, flag_trapv && GET_MODE_CLASS(mode) == MODE_INT
3866 ? negv_optab : neg_optab, op0, target, 0);
3870 /* Don't use the function value register as a target
3871 since we have to read it as well as write it,
3872 and function-inlining gets confused by this. */
3873 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
3874 /* Don't clobber an operand while doing a multi-step calculation. */
3875 || ((rem_flag || op1_is_constant)
3876 && (reg_mentioned_p (target, op0)
3877 || (MEM_P (op0) && MEM_P (target))))
3878 || reg_mentioned_p (target, op1)
3879 || (MEM_P (op1) && MEM_P (target))))
3882 /* Get the mode in which to perform this computation. Normally it will
3883 be MODE, but sometimes we can't do the desired operation in MODE.
3884 If so, pick a wider mode in which we can do the operation. Convert
3885 to that mode at the start to avoid repeated conversions.
3887 First see what operations we need. These depend on the expression
3888 we are evaluating. (We assume that divxx3 insns exist under the
3889 same conditions that modxx3 insns and that these insns don't normally
3890 fail. If these assumptions are not correct, we may generate less
3891 efficient code in some cases.)
3893 Then see if we find a mode in which we can open-code that operation
3894 (either a division, modulus, or shift). Finally, check for the smallest
3895 mode for which we can do the operation with a library call. */
3897 /* We might want to refine this now that we have division-by-constant
3898 optimization. Since expand_mult_highpart tries so many variants, it is
3899 not straightforward to generalize this. Maybe we should make an array
3900 of possible modes in init_expmed? Save this for GCC 2.7. */
3902 optab1 = ((op1_is_pow2 && op1 != const0_rtx)
3903 ? (unsignedp ? lshr_optab : ashr_optab)
3904 : (unsignedp ? udiv_optab : sdiv_optab));
3905 optab2 = ((op1_is_pow2 && op1 != const0_rtx)
3907 : (unsignedp ? udivmod_optab : sdivmod_optab));
3909 for (compute_mode = mode; compute_mode != VOIDmode;
3910 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3911 if (optab_handler (optab1, compute_mode) != CODE_FOR_nothing
3912 || optab_handler (optab2, compute_mode) != CODE_FOR_nothing)
3915 if (compute_mode == VOIDmode)
3916 for (compute_mode = mode; compute_mode != VOIDmode;
3917 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3918 if (optab_libfunc (optab1, compute_mode)
3919 || optab_libfunc (optab2, compute_mode))
3922 /* If we still couldn't find a mode, use MODE, but expand_binop will
3924 if (compute_mode == VOIDmode)
3925 compute_mode = mode;
3927 if (target && GET_MODE (target) == compute_mode)
3930 tquotient = gen_reg_rtx (compute_mode);
3932 size = GET_MODE_BITSIZE (compute_mode);
3934 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3935 (mode), and thereby get better code when OP1 is a constant. Do that
3936 later. It will require going over all usages of SIZE below. */
3937 size = GET_MODE_BITSIZE (mode);
3940 /* Only deduct something for a REM if the last divide done was
3941 for a different constant. Then set the constant of the last
3943 max_cost = unsignedp ? udiv_cost[speed][compute_mode] : sdiv_cost[speed][compute_mode];
3944 if (rem_flag && ! (last_div_const != 0 && op1_is_constant
3945 && INTVAL (op1) == last_div_const))
3946 max_cost -= mul_cost[speed][compute_mode] + add_cost[speed][compute_mode];
3948 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3950 /* Now convert to the best mode to use. */
3951 if (compute_mode != mode)
3953 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3954 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3956 /* convert_modes may have placed op1 into a register, so we
3957 must recompute the following. */
3958 op1_is_constant = CONST_INT_P (op1);
3959 op1_is_pow2 = (op1_is_constant
3960 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3962 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3965 /* If one of the operands is a volatile MEM, copy it into a register. */
3967 if (MEM_P (op0) && MEM_VOLATILE_P (op0))
3968 op0 = force_reg (compute_mode, op0);
3969 if (MEM_P (op1) && MEM_VOLATILE_P (op1))
3970 op1 = force_reg (compute_mode, op1);
3972 /* If we need the remainder or if OP1 is constant, we need to
3973 put OP0 in a register in case it has any queued subexpressions. */
3974 if (rem_flag || op1_is_constant)
3975 op0 = force_reg (compute_mode, op0);
3977 last = get_last_insn ();
3979 /* Promote floor rounding to trunc rounding for unsigned operations. */
3982 if (code == FLOOR_DIV_EXPR)
3983 code = TRUNC_DIV_EXPR;
3984 if (code == FLOOR_MOD_EXPR)
3985 code = TRUNC_MOD_EXPR;
3986 if (code == EXACT_DIV_EXPR && op1_is_pow2)
3987 code = TRUNC_DIV_EXPR;
3990 if (op1 != const0_rtx)
3993 case TRUNC_MOD_EXPR:
3994 case TRUNC_DIV_EXPR:
3995 if (op1_is_constant)
3999 unsigned HOST_WIDE_INT mh;
4000 int pre_shift, post_shift;
4003 unsigned HOST_WIDE_INT d = (INTVAL (op1)
4004 & GET_MODE_MASK (compute_mode));
4006 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
4008 pre_shift = floor_log2 (d);
4012 = expand_binop (compute_mode, and_optab, op0,
4013 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
4017 return gen_lowpart (mode, remainder);
4019 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4020 build_int_cst (NULL_TREE,
4024 else if (size <= HOST_BITS_PER_WIDE_INT)
4026 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
4028 /* Most significant bit of divisor is set; emit an scc
4030 quotient = emit_store_flag_force (tquotient, GEU, op0, op1,
4031 compute_mode, 1, 1);
4035 /* Find a suitable multiplier and right shift count
4036 instead of multiplying with D. */
4038 mh = choose_multiplier (d, size, size,
4039 &ml, &post_shift, &dummy);
4041 /* If the suggested multiplier is more than SIZE bits,
4042 we can do better for even divisors, using an
4043 initial right shift. */
4044 if (mh != 0 && (d & 1) == 0)
4046 pre_shift = floor_log2 (d & -d);
4047 mh = choose_multiplier (d >> pre_shift, size,
4049 &ml, &post_shift, &dummy);
4059 if (post_shift - 1 >= BITS_PER_WORD)
4063 = (shift_cost[speed][compute_mode][post_shift - 1]
4064 + shift_cost[speed][compute_mode][1]
4065 + 2 * add_cost[speed][compute_mode]);
4066 t1 = expand_mult_highpart (compute_mode, op0, ml,
4068 max_cost - extra_cost);
4071 t2 = force_operand (gen_rtx_MINUS (compute_mode,
4075 (RSHIFT_EXPR, compute_mode, t2,
4076 build_int_cst (NULL_TREE, 1),
4078 t4 = force_operand (gen_rtx_PLUS (compute_mode,
4081 quotient = expand_shift
4082 (RSHIFT_EXPR, compute_mode, t4,
4083 build_int_cst (NULL_TREE, post_shift - 1),
4090 if (pre_shift >= BITS_PER_WORD
4091 || post_shift >= BITS_PER_WORD)
4095 (RSHIFT_EXPR, compute_mode, op0,
4096 build_int_cst (NULL_TREE, pre_shift),
4099 = (shift_cost[speed][compute_mode][pre_shift]
4100 + shift_cost[speed][compute_mode][post_shift]);
4101 t2 = expand_mult_highpart (compute_mode, t1, ml,
4103 max_cost - extra_cost);
4106 quotient = expand_shift
4107 (RSHIFT_EXPR, compute_mode, t2,
4108 build_int_cst (NULL_TREE, post_shift),
4113 else /* Too wide mode to use tricky code */
4116 insn = get_last_insn ();
4118 && (set = single_set (insn)) != 0
4119 && SET_DEST (set) == quotient)
4120 set_unique_reg_note (insn,
4122 gen_rtx_UDIV (compute_mode, op0, op1));
4124 else /* TRUNC_DIV, signed */
4126 unsigned HOST_WIDE_INT ml;
4127 int lgup, post_shift;
4129 HOST_WIDE_INT d = INTVAL (op1);
4130 unsigned HOST_WIDE_INT abs_d;
4132 /* Since d might be INT_MIN, we have to cast to
4133 unsigned HOST_WIDE_INT before negating to avoid
4134 undefined signed overflow. */
4136 ? (unsigned HOST_WIDE_INT) d
4137 : - (unsigned HOST_WIDE_INT) d);
4139 /* n rem d = n rem -d */
4140 if (rem_flag && d < 0)
4143 op1 = gen_int_mode (abs_d, compute_mode);
4149 quotient = expand_unop (compute_mode, neg_optab, op0,
4151 else if (HOST_BITS_PER_WIDE_INT >= size
4152 && abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
4154 /* This case is not handled correctly below. */
4155 quotient = emit_store_flag (tquotient, EQ, op0, op1,
4156 compute_mode, 1, 1);
4160 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
4161 && (rem_flag ? smod_pow2_cheap[speed][compute_mode]
4162 : sdiv_pow2_cheap[speed][compute_mode])
4163 /* We assume that cheap metric is true if the
4164 optab has an expander for this mode. */
4165 && ((optab_handler ((rem_flag ? smod_optab
4168 != CODE_FOR_nothing)
4169 || (optab_handler (sdivmod_optab,
4171 != CODE_FOR_nothing)))
4173 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
4177 remainder = expand_smod_pow2 (compute_mode, op0, d);
4179 return gen_lowpart (mode, remainder);
4182 if (sdiv_pow2_cheap[speed][compute_mode]
4183 && ((optab_handler (sdiv_optab, compute_mode)
4184 != CODE_FOR_nothing)
4185 || (optab_handler (sdivmod_optab, compute_mode)
4186 != CODE_FOR_nothing)))
4187 quotient = expand_divmod (0, TRUNC_DIV_EXPR,
4189 gen_int_mode (abs_d,
4193 quotient = expand_sdiv_pow2 (compute_mode, op0, abs_d);
4195 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4196 negate the quotient. */
4199 insn = get_last_insn ();
4201 && (set = single_set (insn)) != 0
4202 && SET_DEST (set) == quotient
4203 && abs_d < ((unsigned HOST_WIDE_INT) 1
4204 << (HOST_BITS_PER_WIDE_INT - 1)))
4205 set_unique_reg_note (insn,
4207 gen_rtx_DIV (compute_mode,
4214 quotient = expand_unop (compute_mode, neg_optab,
4215 quotient, quotient, 0);
4218 else if (size <= HOST_BITS_PER_WIDE_INT)
4220 choose_multiplier (abs_d, size, size - 1,
4221 &mlr, &post_shift, &lgup);
4222 ml = (unsigned HOST_WIDE_INT) INTVAL (mlr);
4223 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
4227 if (post_shift >= BITS_PER_WORD
4228 || size - 1 >= BITS_PER_WORD)
4231 extra_cost = (shift_cost[speed][compute_mode][post_shift]
4232 + shift_cost[speed][compute_mode][size - 1]
4233 + add_cost[speed][compute_mode]);
4234 t1 = expand_mult_highpart (compute_mode, op0, mlr,
4236 max_cost - extra_cost);
4240 (RSHIFT_EXPR, compute_mode, t1,
4241 build_int_cst (NULL_TREE, post_shift),
4244 (RSHIFT_EXPR, compute_mode, op0,
4245 build_int_cst (NULL_TREE, size - 1),
4249 = force_operand (gen_rtx_MINUS (compute_mode,
4254 = force_operand (gen_rtx_MINUS (compute_mode,
4262 if (post_shift >= BITS_PER_WORD
4263 || size - 1 >= BITS_PER_WORD)
4266 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
4267 mlr = gen_int_mode (ml, compute_mode);
4268 extra_cost = (shift_cost[speed][compute_mode][post_shift]
4269 + shift_cost[speed][compute_mode][size - 1]
4270 + 2 * add_cost[speed][compute_mode]);
4271 t1 = expand_mult_highpart (compute_mode, op0, mlr,
4273 max_cost - extra_cost);
4276 t2 = force_operand (gen_rtx_PLUS (compute_mode,
4280 (RSHIFT_EXPR, compute_mode, t2,
4281 build_int_cst (NULL_TREE, post_shift),
4284 (RSHIFT_EXPR, compute_mode, op0,
4285 build_int_cst (NULL_TREE, size - 1),
4289 = force_operand (gen_rtx_MINUS (compute_mode,
4294 = force_operand (gen_rtx_MINUS (compute_mode,
4299 else /* Too wide mode to use tricky code */
4302 insn = get_last_insn ();
4304 && (set = single_set (insn)) != 0
4305 && SET_DEST (set) == quotient)
4306 set_unique_reg_note (insn,
4308 gen_rtx_DIV (compute_mode, op0, op1));
4313 delete_insns_since (last);
4316 case FLOOR_DIV_EXPR:
4317 case FLOOR_MOD_EXPR:
4318 /* We will come here only for signed operations. */
4319 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4321 unsigned HOST_WIDE_INT mh;
4322 int pre_shift, lgup, post_shift;
4323 HOST_WIDE_INT d = INTVAL (op1);
4328 /* We could just as easily deal with negative constants here,
4329 but it does not seem worth the trouble for GCC 2.6. */
4330 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
4332 pre_shift = floor_log2 (d);
4335 remainder = expand_binop (compute_mode, and_optab, op0,
4336 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
4337 remainder, 0, OPTAB_LIB_WIDEN);
4339 return gen_lowpart (mode, remainder);
4341 quotient = expand_shift
4342 (RSHIFT_EXPR, compute_mode, op0,
4343 build_int_cst (NULL_TREE, pre_shift),
4350 mh = choose_multiplier (d, size, size - 1,
4351 &ml, &post_shift, &lgup);
4354 if (post_shift < BITS_PER_WORD
4355 && size - 1 < BITS_PER_WORD)
4358 (RSHIFT_EXPR, compute_mode, op0,
4359 build_int_cst (NULL_TREE, size - 1),
4361 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
4362 NULL_RTX, 0, OPTAB_WIDEN);
4363 extra_cost = (shift_cost[speed][compute_mode][post_shift]
4364 + shift_cost[speed][compute_mode][size - 1]
4365 + 2 * add_cost[speed][compute_mode]);
4366 t3 = expand_mult_highpart (compute_mode, t2, ml,
4368 max_cost - extra_cost);
4372 (RSHIFT_EXPR, compute_mode, t3,
4373 build_int_cst (NULL_TREE, post_shift),
4375 quotient = expand_binop (compute_mode, xor_optab,
4376 t4, t1, tquotient, 0,
4384 rtx nsign, t1, t2, t3, t4;
4385 t1 = force_operand (gen_rtx_PLUS (compute_mode,
4386 op0, constm1_rtx), NULL_RTX);
4387 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
4389 nsign = expand_shift
4390 (RSHIFT_EXPR, compute_mode, t2,
4391 build_int_cst (NULL_TREE, size - 1),
4393 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
4395 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
4400 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
4402 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4411 delete_insns_since (last);
4413 /* Try using an instruction that produces both the quotient and
4414 remainder, using truncation. We can easily compensate the quotient
4415 or remainder to get floor rounding, once we have the remainder.
4416 Notice that we compute also the final remainder value here,
4417 and return the result right away. */
4418 if (target == 0 || GET_MODE (target) != compute_mode)
4419 target = gen_reg_rtx (compute_mode);
4424 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4425 quotient = gen_reg_rtx (compute_mode);
4430 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4431 remainder = gen_reg_rtx (compute_mode);
4434 if (expand_twoval_binop (sdivmod_optab, op0, op1,
4435 quotient, remainder, 0))
4437 /* This could be computed with a branch-less sequence.
4438 Save that for later. */
4440 rtx label = gen_label_rtx ();
4441 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
4442 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4443 NULL_RTX, 0, OPTAB_WIDEN);
4444 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
4445 expand_dec (quotient, const1_rtx);
4446 expand_inc (remainder, op1);
4448 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4451 /* No luck with division elimination or divmod. Have to do it
4452 by conditionally adjusting op0 *and* the result. */
4454 rtx label1, label2, label3, label4, label5;
4458 quotient = gen_reg_rtx (compute_mode);
4459 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4460 label1 = gen_label_rtx ();
4461 label2 = gen_label_rtx ();
4462 label3 = gen_label_rtx ();
4463 label4 = gen_label_rtx ();
4464 label5 = gen_label_rtx ();
4465 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4466 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
4467 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4468 quotient, 0, OPTAB_LIB_WIDEN);
4469 if (tem != quotient)
4470 emit_move_insn (quotient, tem);
4471 emit_jump_insn (gen_jump (label5));
4473 emit_label (label1);
4474 expand_inc (adjusted_op0, const1_rtx);
4475 emit_jump_insn (gen_jump (label4));
4477 emit_label (label2);
4478 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
4479 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4480 quotient, 0, OPTAB_LIB_WIDEN);
4481 if (tem != quotient)
4482 emit_move_insn (quotient, tem);
4483 emit_jump_insn (gen_jump (label5));
4485 emit_label (label3);
4486 expand_dec (adjusted_op0, const1_rtx);
4487 emit_label (label4);
4488 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4489 quotient, 0, OPTAB_LIB_WIDEN);
4490 if (tem != quotient)
4491 emit_move_insn (quotient, tem);
4492 expand_dec (quotient, const1_rtx);
4493 emit_label (label5);
4501 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
4504 unsigned HOST_WIDE_INT d = INTVAL (op1);
4505 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4506 build_int_cst (NULL_TREE, floor_log2 (d)),
4508 t2 = expand_binop (compute_mode, and_optab, op0,
4510 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4511 t3 = gen_reg_rtx (compute_mode);
4512 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4513 compute_mode, 1, 1);
4517 lab = gen_label_rtx ();
4518 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4519 expand_inc (t1, const1_rtx);
4524 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4530 /* Try using an instruction that produces both the quotient and
4531 remainder, using truncation. We can easily compensate the
4532 quotient or remainder to get ceiling rounding, once we have the
4533 remainder. Notice that we compute also the final remainder
4534 value here, and return the result right away. */
4535 if (target == 0 || GET_MODE (target) != compute_mode)
4536 target = gen_reg_rtx (compute_mode);
4540 remainder = (REG_P (target)
4541 ? target : gen_reg_rtx (compute_mode));
4542 quotient = gen_reg_rtx (compute_mode);
4546 quotient = (REG_P (target)
4547 ? target : gen_reg_rtx (compute_mode));
4548 remainder = gen_reg_rtx (compute_mode);
4551 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
4554 /* This could be computed with a branch-less sequence.
4555 Save that for later. */
4556 rtx label = gen_label_rtx ();
4557 do_cmp_and_jump (remainder, const0_rtx, EQ,
4558 compute_mode, label);
4559 expand_inc (quotient, const1_rtx);
4560 expand_dec (remainder, op1);
4562 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4565 /* No luck with division elimination or divmod. Have to do it
4566 by conditionally adjusting op0 *and* the result. */
4569 rtx adjusted_op0, tem;
4571 quotient = gen_reg_rtx (compute_mode);
4572 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4573 label1 = gen_label_rtx ();
4574 label2 = gen_label_rtx ();
4575 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
4576 compute_mode, label1);
4577 emit_move_insn (quotient, const0_rtx);
4578 emit_jump_insn (gen_jump (label2));
4580 emit_label (label1);
4581 expand_dec (adjusted_op0, const1_rtx);
4582 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
4583 quotient, 1, OPTAB_LIB_WIDEN);
4584 if (tem != quotient)
4585 emit_move_insn (quotient, tem);
4586 expand_inc (quotient, const1_rtx);
4587 emit_label (label2);
4592 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
4593 && INTVAL (op1) >= 0)
4595 /* This is extremely similar to the code for the unsigned case
4596 above. For 2.7 we should merge these variants, but for
4597 2.6.1 I don't want to touch the code for unsigned since that
4598 get used in C. The signed case will only be used by other
4602 unsigned HOST_WIDE_INT d = INTVAL (op1);
4603 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4604 build_int_cst (NULL_TREE, floor_log2 (d)),
4606 t2 = expand_binop (compute_mode, and_optab, op0,
4608 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4609 t3 = gen_reg_rtx (compute_mode);
4610 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4611 compute_mode, 1, 1);
4615 lab = gen_label_rtx ();
4616 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4617 expand_inc (t1, const1_rtx);
4622 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4628 /* Try using an instruction that produces both the quotient and
4629 remainder, using truncation. We can easily compensate the
4630 quotient or remainder to get ceiling rounding, once we have the
4631 remainder. Notice that we compute also the final remainder
4632 value here, and return the result right away. */
4633 if (target == 0 || GET_MODE (target) != compute_mode)
4634 target = gen_reg_rtx (compute_mode);
4637 remainder= (REG_P (target)
4638 ? target : gen_reg_rtx (compute_mode));
4639 quotient = gen_reg_rtx (compute_mode);
4643 quotient = (REG_P (target)
4644 ? target : gen_reg_rtx (compute_mode));
4645 remainder = gen_reg_rtx (compute_mode);
4648 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
4651 /* This could be computed with a branch-less sequence.
4652 Save that for later. */
4654 rtx label = gen_label_rtx ();
4655 do_cmp_and_jump (remainder, const0_rtx, EQ,
4656 compute_mode, label);
4657 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4658 NULL_RTX, 0, OPTAB_WIDEN);
4659 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
4660 expand_inc (quotient, const1_rtx);
4661 expand_dec (remainder, op1);
4663 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4666 /* No luck with division elimination or divmod. Have to do it
4667 by conditionally adjusting op0 *and* the result. */
4669 rtx label1, label2, label3, label4, label5;
4673 quotient = gen_reg_rtx (compute_mode);
4674 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4675 label1 = gen_label_rtx ();
4676 label2 = gen_label_rtx ();
4677 label3 = gen_label_rtx ();
4678 label4 = gen_label_rtx ();
4679 label5 = gen_label_rtx ();
4680 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4681 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
4682 compute_mode, label1);
4683 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4684 quotient, 0, OPTAB_LIB_WIDEN);
4685 if (tem != quotient)
4686 emit_move_insn (quotient, tem);
4687 emit_jump_insn (gen_jump (label5));
4689 emit_label (label1);
4690 expand_dec (adjusted_op0, const1_rtx);
4691 emit_jump_insn (gen_jump (label4));
4693 emit_label (label2);
4694 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
4695 compute_mode, label3);
4696 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4697 quotient, 0, OPTAB_LIB_WIDEN);
4698 if (tem != quotient)
4699 emit_move_insn (quotient, tem);
4700 emit_jump_insn (gen_jump (label5));
4702 emit_label (label3);
4703 expand_inc (adjusted_op0, const1_rtx);
4704 emit_label (label4);
4705 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4706 quotient, 0, OPTAB_LIB_WIDEN);
4707 if (tem != quotient)
4708 emit_move_insn (quotient, tem);
4709 expand_inc (quotient, const1_rtx);
4710 emit_label (label5);
4715 case EXACT_DIV_EXPR:
4716 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4718 HOST_WIDE_INT d = INTVAL (op1);
4719 unsigned HOST_WIDE_INT ml;
4723 pre_shift = floor_log2 (d & -d);
4724 ml = invert_mod2n (d >> pre_shift, size);
4725 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4726 build_int_cst (NULL_TREE, pre_shift),
4727 NULL_RTX, unsignedp);
4728 quotient = expand_mult (compute_mode, t1,
4729 gen_int_mode (ml, compute_mode),
4732 insn = get_last_insn ();
4733 set_unique_reg_note (insn,
4735 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4741 case ROUND_DIV_EXPR:
4742 case ROUND_MOD_EXPR:
4747 label = gen_label_rtx ();
4748 quotient = gen_reg_rtx (compute_mode);
4749 remainder = gen_reg_rtx (compute_mode);
4750 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
4753 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
4754 quotient, 1, OPTAB_LIB_WIDEN);
4755 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
4756 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4757 remainder, 1, OPTAB_LIB_WIDEN);
4759 tem = plus_constant (op1, -1);
4760 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4761 build_int_cst (NULL_TREE, 1),
4763 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
4764 expand_inc (quotient, const1_rtx);
4765 expand_dec (remainder, op1);
4770 rtx abs_rem, abs_op1, tem, mask;
4772 label = gen_label_rtx ();
4773 quotient = gen_reg_rtx (compute_mode);
4774 remainder = gen_reg_rtx (compute_mode);
4775 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
4778 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
4779 quotient, 0, OPTAB_LIB_WIDEN);
4780 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
4781 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4782 remainder, 0, OPTAB_LIB_WIDEN);
4784 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0);
4785 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0);
4786 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
4787 build_int_cst (NULL_TREE, 1),
4789 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
4790 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4791 NULL_RTX, 0, OPTAB_WIDEN);
4792 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4793 build_int_cst (NULL_TREE, size - 1),
4795 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
4796 NULL_RTX, 0, OPTAB_WIDEN);
4797 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4798 NULL_RTX, 0, OPTAB_WIDEN);
4799 expand_inc (quotient, tem);
4800 tem = expand_binop (compute_mode, xor_optab, mask, op1,
4801 NULL_RTX, 0, OPTAB_WIDEN);
4802 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4803 NULL_RTX, 0, OPTAB_WIDEN);
4804 expand_dec (remainder, tem);
4807 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4815 if (target && GET_MODE (target) != compute_mode)
4820 /* Try to produce the remainder without producing the quotient.
4821 If we seem to have a divmod pattern that does not require widening,
4822 don't try widening here. We should really have a WIDEN argument
4823 to expand_twoval_binop, since what we'd really like to do here is
4824 1) try a mod insn in compute_mode
4825 2) try a divmod insn in compute_mode
4826 3) try a div insn in compute_mode and multiply-subtract to get
4828 4) try the same things with widening allowed. */
4830 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4833 ((optab_handler (optab2, compute_mode)
4834 != CODE_FOR_nothing)
4835 ? OPTAB_DIRECT : OPTAB_WIDEN));
4838 /* No luck there. Can we do remainder and divide at once
4839 without a library call? */
4840 remainder = gen_reg_rtx (compute_mode);
4841 if (! expand_twoval_binop ((unsignedp
4845 NULL_RTX, remainder, unsignedp))
4850 return gen_lowpart (mode, remainder);
4853 /* Produce the quotient. Try a quotient insn, but not a library call.
4854 If we have a divmod in this mode, use it in preference to widening
4855 the div (for this test we assume it will not fail). Note that optab2
4856 is set to the one of the two optabs that the call below will use. */
4858 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
4859 op0, op1, rem_flag ? NULL_RTX : target,
4861 ((optab_handler (optab2, compute_mode)
4862 != CODE_FOR_nothing)
4863 ? OPTAB_DIRECT : OPTAB_WIDEN));
4867 /* No luck there. Try a quotient-and-remainder insn,
4868 keeping the quotient alone. */
4869 quotient = gen_reg_rtx (compute_mode);
4870 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
4872 quotient, NULL_RTX, unsignedp))
4876 /* Still no luck. If we are not computing the remainder,
4877 use a library call for the quotient. */
4878 quotient = sign_expand_binop (compute_mode,
4879 udiv_optab, sdiv_optab,
4881 unsignedp, OPTAB_LIB_WIDEN);
4888 if (target && GET_MODE (target) != compute_mode)
4893 /* No divide instruction either. Use library for remainder. */
4894 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4896 unsignedp, OPTAB_LIB_WIDEN);
4897 /* No remainder function. Try a quotient-and-remainder
4898 function, keeping the remainder. */
4901 remainder = gen_reg_rtx (compute_mode);
4902 if (!expand_twoval_binop_libfunc
4903 (unsignedp ? udivmod_optab : sdivmod_optab,
4905 NULL_RTX, remainder,
4906 unsignedp ? UMOD : MOD))
4907 remainder = NULL_RTX;
4912 /* We divided. Now finish doing X - Y * (X / Y). */
4913 remainder = expand_mult (compute_mode, quotient, op1,
4914 NULL_RTX, unsignedp);
4915 remainder = expand_binop (compute_mode, sub_optab, op0,
4916 remainder, target, unsignedp,
4921 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4924 /* Return a tree node with data type TYPE, describing the value of X.
4925 Usually this is an VAR_DECL, if there is no obvious better choice.
4926 X may be an expression, however we only support those expressions
4927 generated by loop.c. */
4930 make_tree (tree type, rtx x)
4934 switch (GET_CODE (x))
4938 HOST_WIDE_INT hi = 0;
4941 && !(TYPE_UNSIGNED (type)
4942 && (GET_MODE_BITSIZE (TYPE_MODE (type))
4943 < HOST_BITS_PER_WIDE_INT)))
4946 t = build_int_cst_wide (type, INTVAL (x), hi);
4952 if (GET_MODE (x) == VOIDmode)
4953 t = build_int_cst_wide (type,
4954 CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
4959 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
4960 t = build_real (type, d);
4967 int units = CONST_VECTOR_NUNITS (x);
4968 tree itype = TREE_TYPE (type);
4973 /* Build a tree with vector elements. */
4974 for (i = units - 1; i >= 0; --i)
4976 rtx elt = CONST_VECTOR_ELT (x, i);
4977 t = tree_cons (NULL_TREE, make_tree (itype, elt), t);
4980 return build_vector (type, t);
4984 return fold_build2 (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4985 make_tree (type, XEXP (x, 1)));
4988 return fold_build2 (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4989 make_tree (type, XEXP (x, 1)));
4992 return fold_build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)));
4995 return fold_build2 (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
4996 make_tree (type, XEXP (x, 1)));
4999 return fold_build2 (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
5000 make_tree (type, XEXP (x, 1)));
5003 t = unsigned_type_for (type);
5004 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5005 make_tree (t, XEXP (x, 0)),
5006 make_tree (type, XEXP (x, 1))));
5009 t = signed_type_for (type);
5010 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5011 make_tree (t, XEXP (x, 0)),
5012 make_tree (type, XEXP (x, 1))));
5015 if (TREE_CODE (type) != REAL_TYPE)
5016 t = signed_type_for (type);
5020 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5021 make_tree (t, XEXP (x, 0)),
5022 make_tree (t, XEXP (x, 1))));
5024 t = unsigned_type_for (type);
5025 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5026 make_tree (t, XEXP (x, 0)),
5027 make_tree (t, XEXP (x, 1))));
5031 t = lang_hooks.types.type_for_mode (GET_MODE (XEXP (x, 0)),
5032 GET_CODE (x) == ZERO_EXTEND);
5033 return fold_convert (type, make_tree (t, XEXP (x, 0)));
5036 return make_tree (type, XEXP (x, 0));
5039 t = SYMBOL_REF_DECL (x);
5041 return fold_convert (type, build_fold_addr_expr (t));
5042 /* else fall through. */
5045 t = build_decl (RTL_LOCATION (x), VAR_DECL, NULL_TREE, type);
5047 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5048 address mode to pointer mode. */
5049 if (POINTER_TYPE_P (type))
5050 x = convert_memory_address_addr_space
5051 (TYPE_MODE (type), x, TYPE_ADDR_SPACE (TREE_TYPE (type)));
5053 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5054 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5055 t->decl_with_rtl.rtl = x;
5061 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5062 and returning TARGET.
5064 If TARGET is 0, a pseudo-register or constant is returned. */
5067 expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target)
5071 if (GET_MODE (op0) == VOIDmode && GET_MODE (op1) == VOIDmode)
5072 tem = simplify_binary_operation (AND, mode, op0, op1);
5074 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
5078 else if (tem != target)
5079 emit_move_insn (target, tem);
5083 /* Helper function for emit_store_flag. */
5085 emit_cstore (rtx target, enum insn_code icode, enum rtx_code code,
5086 enum machine_mode mode, enum machine_mode compare_mode,
5087 int unsignedp, rtx x, rtx y, int normalizep,
5088 enum machine_mode target_mode)
5090 rtx op0, last, comparison, subtarget, pattern;
5091 enum machine_mode result_mode = insn_data[(int) icode].operand[0].mode;
5093 last = get_last_insn ();
5094 x = prepare_operand (icode, x, 2, mode, compare_mode, unsignedp);
5095 y = prepare_operand (icode, y, 3, mode, compare_mode, unsignedp);
5096 comparison = gen_rtx_fmt_ee (code, result_mode, x, y);
5098 || !insn_data[icode].operand[2].predicate
5099 (x, insn_data[icode].operand[2].mode)
5100 || !insn_data[icode].operand[3].predicate
5101 (y, insn_data[icode].operand[3].mode)
5102 || !insn_data[icode].operand[1].predicate (comparison, VOIDmode))
5104 delete_insns_since (last);
5108 if (target_mode == VOIDmode)
5109 target_mode = result_mode;
5111 target = gen_reg_rtx (target_mode);
5114 || !(insn_data[(int) icode].operand[0].predicate (target, result_mode)))
5115 subtarget = gen_reg_rtx (result_mode);
5119 pattern = GEN_FCN (icode) (subtarget, comparison, x, y);
5122 emit_insn (pattern);
5124 /* If we are converting to a wider mode, first convert to
5125 TARGET_MODE, then normalize. This produces better combining
5126 opportunities on machines that have a SIGN_EXTRACT when we are
5127 testing a single bit. This mostly benefits the 68k.
5129 If STORE_FLAG_VALUE does not have the sign bit set when
5130 interpreted in MODE, we can do this conversion as unsigned, which
5131 is usually more efficient. */
5132 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (result_mode))
5134 convert_move (target, subtarget,
5135 (GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT)
5136 && 0 == (STORE_FLAG_VALUE
5137 & ((HOST_WIDE_INT) 1
5138 << (GET_MODE_BITSIZE (result_mode) -1))));
5140 result_mode = target_mode;
5145 /* If we want to keep subexpressions around, don't reuse our last
5150 /* Now normalize to the proper value in MODE. Sometimes we don't
5151 have to do anything. */
5152 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
5154 /* STORE_FLAG_VALUE might be the most negative number, so write
5155 the comparison this way to avoid a compiler-time warning. */
5156 else if (- normalizep == STORE_FLAG_VALUE)
5157 op0 = expand_unop (result_mode, neg_optab, op0, subtarget, 0);
5159 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5160 it hard to use a value of just the sign bit due to ANSI integer
5161 constant typing rules. */
5162 else if (GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
5163 && (STORE_FLAG_VALUE
5164 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
5165 op0 = expand_shift (RSHIFT_EXPR, result_mode, op0,
5166 size_int (GET_MODE_BITSIZE (result_mode) - 1), subtarget,
5170 gcc_assert (STORE_FLAG_VALUE & 1);
5172 op0 = expand_and (result_mode, op0, const1_rtx, subtarget);
5173 if (normalizep == -1)
5174 op0 = expand_unop (result_mode, neg_optab, op0, op0, 0);
5177 /* If we were converting to a smaller mode, do the conversion now. */
5178 if (target_mode != result_mode)
5180 convert_move (target, op0, 0);
5188 /* A subroutine of emit_store_flag only including "tricks" that do not
5189 need a recursive call. These are kept separate to avoid infinite
5193 emit_store_flag_1 (rtx target, enum rtx_code code, rtx op0, rtx op1,
5194 enum machine_mode mode, int unsignedp, int normalizep,
5195 enum machine_mode target_mode)
5198 enum insn_code icode;
5199 enum machine_mode compare_mode;
5200 enum mode_class mclass;
5201 enum rtx_code scode;
5205 code = unsigned_condition (code);
5206 scode = swap_condition (code);
5208 /* If one operand is constant, make it the second one. Only do this
5209 if the other operand is not constant as well. */
5211 if (swap_commutative_operands_p (op0, op1))
5216 code = swap_condition (code);
5219 if (mode == VOIDmode)
5220 mode = GET_MODE (op0);
5222 /* For some comparisons with 1 and -1, we can convert this to
5223 comparisons with zero. This will often produce more opportunities for
5224 store-flag insns. */
5229 if (op1 == const1_rtx)
5230 op1 = const0_rtx, code = LE;
5233 if (op1 == constm1_rtx)
5234 op1 = const0_rtx, code = LT;
5237 if (op1 == const1_rtx)
5238 op1 = const0_rtx, code = GT;
5241 if (op1 == constm1_rtx)
5242 op1 = const0_rtx, code = GE;
5245 if (op1 == const1_rtx)
5246 op1 = const0_rtx, code = NE;
5249 if (op1 == const1_rtx)
5250 op1 = const0_rtx, code = EQ;
5256 /* If we are comparing a double-word integer with zero or -1, we can
5257 convert the comparison into one involving a single word. */
5258 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
5259 && GET_MODE_CLASS (mode) == MODE_INT
5260 && (!MEM_P (op0) || ! MEM_VOLATILE_P (op0)))
5262 if ((code == EQ || code == NE)
5263 && (op1 == const0_rtx || op1 == constm1_rtx))
5267 /* Do a logical OR or AND of the two words and compare the
5269 op00 = simplify_gen_subreg (word_mode, op0, mode, 0);
5270 op01 = simplify_gen_subreg (word_mode, op0, mode, UNITS_PER_WORD);
5271 tem = expand_binop (word_mode,
5272 op1 == const0_rtx ? ior_optab : and_optab,
5273 op00, op01, NULL_RTX, unsignedp,
5277 tem = emit_store_flag (NULL_RTX, code, tem, op1, word_mode,
5278 unsignedp, normalizep);
5280 else if ((code == LT || code == GE) && op1 == const0_rtx)
5284 /* If testing the sign bit, can just test on high word. */
5285 op0h = simplify_gen_subreg (word_mode, op0, mode,
5286 subreg_highpart_offset (word_mode,
5288 tem = emit_store_flag (NULL_RTX, code, op0h, op1, word_mode,
5289 unsignedp, normalizep);
5296 if (target_mode == VOIDmode || GET_MODE (tem) == target_mode)
5299 target = gen_reg_rtx (target_mode);
5301 convert_move (target, tem,
5302 0 == ((normalizep ? normalizep : STORE_FLAG_VALUE)
5303 & ((HOST_WIDE_INT) 1
5304 << (GET_MODE_BITSIZE (word_mode) -1))));
5309 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5310 complement of A (for GE) and shifting the sign bit to the low bit. */
5311 if (op1 == const0_rtx && (code == LT || code == GE)
5312 && GET_MODE_CLASS (mode) == MODE_INT
5313 && (normalizep || STORE_FLAG_VALUE == 1
5314 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5315 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5316 == ((unsigned HOST_WIDE_INT) 1
5317 << (GET_MODE_BITSIZE (mode) - 1))))))
5324 /* If the result is to be wider than OP0, it is best to convert it
5325 first. If it is to be narrower, it is *incorrect* to convert it
5327 else if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
5329 op0 = convert_modes (target_mode, mode, op0, 0);
5333 if (target_mode != mode)
5337 op0 = expand_unop (mode, one_cmpl_optab, op0,
5338 ((STORE_FLAG_VALUE == 1 || normalizep)
5339 ? 0 : subtarget), 0);
5341 if (STORE_FLAG_VALUE == 1 || normalizep)
5342 /* If we are supposed to produce a 0/1 value, we want to do
5343 a logical shift from the sign bit to the low-order bit; for
5344 a -1/0 value, we do an arithmetic shift. */
5345 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
5346 size_int (GET_MODE_BITSIZE (mode) - 1),
5347 subtarget, normalizep != -1);
5349 if (mode != target_mode)
5350 op0 = convert_modes (target_mode, mode, op0, 0);
5355 mclass = GET_MODE_CLASS (mode);
5356 for (compare_mode = mode; compare_mode != VOIDmode;
5357 compare_mode = GET_MODE_WIDER_MODE (compare_mode))
5359 enum machine_mode optab_mode = mclass == MODE_CC ? CCmode : compare_mode;
5360 icode = optab_handler (cstore_optab, optab_mode);
5361 if (icode != CODE_FOR_nothing)
5363 do_pending_stack_adjust ();
5364 tem = emit_cstore (target, icode, code, mode, compare_mode,
5365 unsignedp, op0, op1, normalizep, target_mode);
5369 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5371 tem = emit_cstore (target, icode, scode, mode, compare_mode,
5372 unsignedp, op1, op0, normalizep, target_mode);
5383 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5384 and storing in TARGET. Normally return TARGET.
5385 Return 0 if that cannot be done.
5387 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5388 it is VOIDmode, they cannot both be CONST_INT.
5390 UNSIGNEDP is for the case where we have to widen the operands
5391 to perform the operation. It says to use zero-extension.
5393 NORMALIZEP is 1 if we should convert the result to be either zero
5394 or one. Normalize is -1 if we should convert the result to be
5395 either zero or -1. If NORMALIZEP is zero, the result will be left
5396 "raw" out of the scc insn. */
5399 emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
5400 enum machine_mode mode, int unsignedp, int normalizep)
5402 enum machine_mode target_mode = target ? GET_MODE (target) : VOIDmode;
5403 enum rtx_code rcode;
5405 rtx tem, last, trueval;
5407 tem = emit_store_flag_1 (target, code, op0, op1, mode, unsignedp, normalizep,
5412 /* If we reached here, we can't do this with a scc insn, however there
5413 are some comparisons that can be done in other ways. Don't do any
5414 of these cases if branches are very cheap. */
5415 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5418 /* See what we need to return. We can only return a 1, -1, or the
5421 if (normalizep == 0)
5423 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5424 normalizep = STORE_FLAG_VALUE;
5426 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5427 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5428 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
5434 last = get_last_insn ();
5436 /* If optimizing, use different pseudo registers for each insn, instead
5437 of reusing the same pseudo. This leads to better CSE, but slows
5438 down the compiler, since there are more pseudos */
5439 subtarget = (!optimize
5440 && (target_mode == mode)) ? target : NULL_RTX;
5441 trueval = GEN_INT (normalizep ? normalizep : STORE_FLAG_VALUE);
5443 /* For floating-point comparisons, try the reverse comparison or try
5444 changing the "orderedness" of the comparison. */
5445 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5447 enum rtx_code first_code;
5450 rcode = reverse_condition_maybe_unordered (code);
5451 if (can_compare_p (rcode, mode, ccp_store_flag)
5452 && (code == ORDERED || code == UNORDERED
5453 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
5454 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
5456 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5457 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5459 /* For the reverse comparison, use either an addition or a XOR. */
5461 && rtx_cost (GEN_INT (normalizep), PLUS,
5462 optimize_insn_for_speed_p ()) == 0)
5464 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5465 STORE_FLAG_VALUE, target_mode);
5467 return expand_binop (target_mode, add_optab, tem,
5468 GEN_INT (normalizep),
5469 target, 0, OPTAB_WIDEN);
5472 && rtx_cost (trueval, XOR,
5473 optimize_insn_for_speed_p ()) == 0)
5475 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5476 normalizep, target_mode);
5478 return expand_binop (target_mode, xor_optab, tem, trueval,
5479 target, INTVAL (trueval) >= 0, OPTAB_WIDEN);
5483 delete_insns_since (last);
5485 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5486 if (code == ORDERED || code == UNORDERED)
5489 and_them = split_comparison (code, mode, &first_code, &code);
5491 /* If there are no NaNs, the first comparison should always fall through.
5492 Effectively change the comparison to the other one. */
5493 if (!HONOR_NANS (mode))
5495 gcc_assert (first_code == (and_them ? ORDERED : UNORDERED));
5496 return emit_store_flag_1 (target, code, op0, op1, mode, 0, normalizep,
5500 #ifdef HAVE_conditional_move
5501 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5502 conditional move. */
5503 tem = emit_store_flag_1 (subtarget, first_code, op0, op1, mode, 0,
5504 normalizep, target_mode);
5509 tem = emit_conditional_move (target, code, op0, op1, mode,
5510 tem, const0_rtx, GET_MODE (tem), 0);
5512 tem = emit_conditional_move (target, code, op0, op1, mode,
5513 trueval, tem, GET_MODE (tem), 0);
5516 delete_insns_since (last);
5523 /* The remaining tricks only apply to integer comparisons. */
5525 if (GET_MODE_CLASS (mode) != MODE_INT)
5528 /* If this is an equality comparison of integers, we can try to exclusive-or
5529 (or subtract) the two operands and use a recursive call to try the
5530 comparison with zero. Don't do any of these cases if branches are
5533 if ((code == EQ || code == NE) && op1 != const0_rtx)
5535 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
5539 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
5542 tem = emit_store_flag (target, code, tem, const0_rtx,
5543 mode, unsignedp, normalizep);
5547 delete_insns_since (last);
5550 /* For integer comparisons, try the reverse comparison. However, for
5551 small X and if we'd have anyway to extend, implementing "X != 0"
5552 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5553 rcode = reverse_condition (code);
5554 if (can_compare_p (rcode, mode, ccp_store_flag)
5555 && ! (optab_handler (cstore_optab, mode) == CODE_FOR_nothing
5557 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5558 && op1 == const0_rtx))
5560 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5561 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5563 /* Again, for the reverse comparison, use either an addition or a XOR. */
5565 && rtx_cost (GEN_INT (normalizep), PLUS,
5566 optimize_insn_for_speed_p ()) == 0)
5568 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5569 STORE_FLAG_VALUE, target_mode);
5571 tem = expand_binop (target_mode, add_optab, tem,
5572 GEN_INT (normalizep), target, 0, OPTAB_WIDEN);
5575 && rtx_cost (trueval, XOR,
5576 optimize_insn_for_speed_p ()) == 0)
5578 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5579 normalizep, target_mode);
5581 tem = expand_binop (target_mode, xor_optab, tem, trueval, target,
5582 INTVAL (trueval) >= 0, OPTAB_WIDEN);
5587 delete_insns_since (last);
5590 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5591 the constant zero. Reject all other comparisons at this point. Only
5592 do LE and GT if branches are expensive since they are expensive on
5593 2-operand machines. */
5595 if (op1 != const0_rtx
5596 || (code != EQ && code != NE
5597 && (BRANCH_COST (optimize_insn_for_speed_p (),
5598 false) <= 1 || (code != LE && code != GT))))
5601 /* Try to put the result of the comparison in the sign bit. Assume we can't
5602 do the necessary operation below. */
5606 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5607 the sign bit set. */
5611 /* This is destructive, so SUBTARGET can't be OP0. */
5612 if (rtx_equal_p (subtarget, op0))
5615 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
5618 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
5622 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5623 number of bits in the mode of OP0, minus one. */
5627 if (rtx_equal_p (subtarget, op0))
5630 tem = expand_shift (RSHIFT_EXPR, mode, op0,
5631 size_int (GET_MODE_BITSIZE (mode) - 1),
5633 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
5637 if (code == EQ || code == NE)
5639 /* For EQ or NE, one way to do the comparison is to apply an operation
5640 that converts the operand into a positive number if it is nonzero
5641 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5642 for NE we negate. This puts the result in the sign bit. Then we
5643 normalize with a shift, if needed.
5645 Two operations that can do the above actions are ABS and FFS, so try
5646 them. If that doesn't work, and MODE is smaller than a full word,
5647 we can use zero-extension to the wider mode (an unsigned conversion)
5648 as the operation. */
5650 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5651 that is compensated by the subsequent overflow when subtracting
5654 if (optab_handler (abs_optab, mode) != CODE_FOR_nothing)
5655 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
5656 else if (optab_handler (ffs_optab, mode) != CODE_FOR_nothing)
5657 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
5658 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5660 tem = convert_modes (word_mode, mode, op0, 1);
5667 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
5670 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
5673 /* If we couldn't do it that way, for NE we can "or" the two's complement
5674 of the value with itself. For EQ, we take the one's complement of
5675 that "or", which is an extra insn, so we only handle EQ if branches
5680 || BRANCH_COST (optimize_insn_for_speed_p (),
5683 if (rtx_equal_p (subtarget, op0))
5686 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
5687 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
5690 if (tem && code == EQ)
5691 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
5695 if (tem && normalizep)
5696 tem = expand_shift (RSHIFT_EXPR, mode, tem,
5697 size_int (GET_MODE_BITSIZE (mode) - 1),
5698 subtarget, normalizep == 1);
5704 else if (GET_MODE (tem) != target_mode)
5706 convert_move (target, tem, 0);
5709 else if (!subtarget)
5711 emit_move_insn (target, tem);
5716 delete_insns_since (last);
5721 /* Like emit_store_flag, but always succeeds. */
5724 emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1,
5725 enum machine_mode mode, int unsignedp, int normalizep)
5728 rtx trueval, falseval;
5730 /* First see if emit_store_flag can do the job. */
5731 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
5736 target = gen_reg_rtx (word_mode);
5738 /* If this failed, we have to do this with set/compare/jump/set code.
5739 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5740 trueval = normalizep ? GEN_INT (normalizep) : const1_rtx;
5742 && GET_MODE_CLASS (mode) == MODE_INT
5745 && op1 == const0_rtx)
5747 label = gen_label_rtx ();
5748 do_compare_rtx_and_jump (target, const0_rtx, EQ, unsignedp,
5749 mode, NULL_RTX, NULL_RTX, label, -1);
5750 emit_move_insn (target, trueval);
5756 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
5757 target = gen_reg_rtx (GET_MODE (target));
5759 /* Jump in the right direction if the target cannot implement CODE
5760 but can jump on its reverse condition. */
5761 falseval = const0_rtx;
5762 if (! can_compare_p (code, mode, ccp_jump)
5763 && (! FLOAT_MODE_P (mode)
5764 || code == ORDERED || code == UNORDERED
5765 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
5766 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
5768 enum rtx_code rcode;
5769 if (FLOAT_MODE_P (mode))
5770 rcode = reverse_condition_maybe_unordered (code);
5772 rcode = reverse_condition (code);
5774 /* Canonicalize to UNORDERED for the libcall. */
5775 if (can_compare_p (rcode, mode, ccp_jump)
5776 || (code == ORDERED && ! can_compare_p (ORDERED, mode, ccp_jump)))
5779 trueval = const0_rtx;
5784 emit_move_insn (target, trueval);
5785 label = gen_label_rtx ();
5786 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX,
5787 NULL_RTX, label, -1);
5789 emit_move_insn (target, falseval);
5795 /* Perform possibly multi-word comparison and conditional jump to LABEL
5796 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5797 now a thin wrapper around do_compare_rtx_and_jump. */
5800 do_cmp_and_jump (rtx arg1, rtx arg2, enum rtx_code op, enum machine_mode mode,
5803 int unsignedp = (op == LTU || op == LEU || op == GTU || op == GEU);
5804 do_compare_rtx_and_jump (arg1, arg2, op, unsignedp, mode,
5805 NULL_RTX, NULL_RTX, label, -1);