1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 /* Middle-to-low level generation of rtx code and insns.
26 This file contains support functions for creating rtl expressions
27 and manipulating them in the doubly-linked chain of insns.
29 The patterns of the insns are created by machine-dependent
30 routines in insn-emit.c, which is generated automatically from
31 the machine description. These routines make the individual rtx's
32 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
33 which are automatically generated from rtl.def; what is machine
34 dependent is the kind of rtx's they make and what arguments they
39 #include "coretypes.h"
49 #include "hard-reg-set.h"
51 #include "insn-config.h"
55 #include "basic-block.h"
58 #include "langhooks.h"
59 #include "tree-pass.h"
62 /* Commonly used modes. */
64 enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */
65 enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */
66 enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */
67 enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */
70 /* This is *not* reset after each function. It gives each CODE_LABEL
71 in the entire compilation a unique label number. */
73 static GTY(()) int label_num = 1;
75 /* Nonzero means do not generate NOTEs for source line numbers. */
77 static int no_line_numbers;
79 /* Commonly used rtx's, so that we only need space for one copy.
80 These are initialized once for the entire compilation.
81 All of these are unique; no other rtx-object will be equal to any
84 rtx global_rtl[GR_MAX];
86 /* Commonly used RTL for hard registers. These objects are not necessarily
87 unique, so we allocate them separately from global_rtl. They are
88 initialized once per compilation unit, then copied into regno_reg_rtx
89 at the beginning of each function. */
90 static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER];
92 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
93 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
94 record a copy of const[012]_rtx. */
96 rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE];
100 REAL_VALUE_TYPE dconst0;
101 REAL_VALUE_TYPE dconst1;
102 REAL_VALUE_TYPE dconst2;
103 REAL_VALUE_TYPE dconst3;
104 REAL_VALUE_TYPE dconst10;
105 REAL_VALUE_TYPE dconstm1;
106 REAL_VALUE_TYPE dconstm2;
107 REAL_VALUE_TYPE dconsthalf;
108 REAL_VALUE_TYPE dconstthird;
109 REAL_VALUE_TYPE dconstsqrt2;
110 REAL_VALUE_TYPE dconste;
112 /* All references to the following fixed hard registers go through
113 these unique rtl objects. On machines where the frame-pointer and
114 arg-pointer are the same register, they use the same unique object.
116 After register allocation, other rtl objects which used to be pseudo-regs
117 may be clobbered to refer to the frame-pointer register.
118 But references that were originally to the frame-pointer can be
119 distinguished from the others because they contain frame_pointer_rtx.
121 When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little
122 tricky: until register elimination has taken place hard_frame_pointer_rtx
123 should be used if it is being set, and frame_pointer_rtx otherwise. After
124 register elimination hard_frame_pointer_rtx should always be used.
125 On machines where the two registers are same (most) then these are the
128 In an inline procedure, the stack and frame pointer rtxs may not be
129 used for anything else. */
130 rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */
131 rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */
132 rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */
134 /* This is used to implement __builtin_return_address for some machines.
135 See for instance the MIPS port. */
136 rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */
138 /* We make one copy of (const_int C) where C is in
139 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
140 to save space during the compilation and simplify comparisons of
143 rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];
145 /* A hash table storing CONST_INTs whose absolute value is greater
146 than MAX_SAVED_CONST_INT. */
148 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def)))
149 htab_t const_int_htab;
151 /* A hash table storing memory attribute structures. */
152 static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs)))
153 htab_t mem_attrs_htab;
155 /* A hash table storing register attribute structures. */
156 static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs)))
157 htab_t reg_attrs_htab;
159 /* A hash table storing all CONST_DOUBLEs. */
160 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def)))
161 htab_t const_double_htab;
163 #define first_insn (cfun->emit->x_first_insn)
164 #define last_insn (cfun->emit->x_last_insn)
165 #define cur_insn_uid (cfun->emit->x_cur_insn_uid)
166 #define last_location (cfun->emit->x_last_location)
167 #define first_label_num (cfun->emit->x_first_label_num)
169 static rtx make_call_insn_raw (rtx);
170 static rtx change_address_1 (rtx, enum machine_mode, rtx, int);
171 static void reset_used_decls (tree);
172 static void mark_label_nuses (rtx);
173 static hashval_t const_int_htab_hash (const void *);
174 static int const_int_htab_eq (const void *, const void *);
175 static hashval_t const_double_htab_hash (const void *);
176 static int const_double_htab_eq (const void *, const void *);
177 static rtx lookup_const_double (rtx);
178 static hashval_t mem_attrs_htab_hash (const void *);
179 static int mem_attrs_htab_eq (const void *, const void *);
180 static mem_attrs *get_mem_attrs (HOST_WIDE_INT, tree, rtx, rtx, unsigned int,
182 static hashval_t reg_attrs_htab_hash (const void *);
183 static int reg_attrs_htab_eq (const void *, const void *);
184 static reg_attrs *get_reg_attrs (tree, int);
185 static tree component_ref_for_mem_expr (tree);
186 static rtx gen_const_vector (enum machine_mode, int);
187 static void copy_rtx_if_shared_1 (rtx *orig);
189 /* Probability of the conditional branch currently proceeded by try_split.
190 Set to -1 otherwise. */
191 int split_branch_probability = -1;
193 /* Returns a hash code for X (which is a really a CONST_INT). */
196 const_int_htab_hash (const void *x)
198 return (hashval_t) INTVAL ((rtx) x);
201 /* Returns nonzero if the value represented by X (which is really a
202 CONST_INT) is the same as that given by Y (which is really a
206 const_int_htab_eq (const void *x, const void *y)
208 return (INTVAL ((rtx) x) == *((const HOST_WIDE_INT *) y));
211 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
213 const_double_htab_hash (const void *x)
218 if (GET_MODE (value) == VOIDmode)
219 h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value);
222 h = real_hash (CONST_DOUBLE_REAL_VALUE (value));
223 /* MODE is used in the comparison, so it should be in the hash. */
224 h ^= GET_MODE (value);
229 /* Returns nonzero if the value represented by X (really a ...)
230 is the same as that represented by Y (really a ...) */
232 const_double_htab_eq (const void *x, const void *y)
234 rtx a = (rtx)x, b = (rtx)y;
236 if (GET_MODE (a) != GET_MODE (b))
238 if (GET_MODE (a) == VOIDmode)
239 return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b)
240 && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b));
242 return real_identical (CONST_DOUBLE_REAL_VALUE (a),
243 CONST_DOUBLE_REAL_VALUE (b));
246 /* Returns a hash code for X (which is a really a mem_attrs *). */
249 mem_attrs_htab_hash (const void *x)
251 mem_attrs *p = (mem_attrs *) x;
253 return (p->alias ^ (p->align * 1000)
254 ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000)
255 ^ ((p->size ? INTVAL (p->size) : 0) * 2500000)
256 ^ (size_t) iterative_hash_expr (p->expr, 0));
259 /* Returns nonzero if the value represented by X (which is really a
260 mem_attrs *) is the same as that given by Y (which is also really a
264 mem_attrs_htab_eq (const void *x, const void *y)
266 mem_attrs *p = (mem_attrs *) x;
267 mem_attrs *q = (mem_attrs *) y;
269 return (p->alias == q->alias && p->offset == q->offset
270 && p->size == q->size && p->align == q->align
271 && (p->expr == q->expr
272 || (p->expr != NULL_TREE && q->expr != NULL_TREE
273 && operand_equal_p (p->expr, q->expr, 0))));
276 /* Allocate a new mem_attrs structure and insert it into the hash table if
277 one identical to it is not already in the table. We are doing this for
281 get_mem_attrs (HOST_WIDE_INT alias, tree expr, rtx offset, rtx size,
282 unsigned int align, enum machine_mode mode)
287 /* If everything is the default, we can just return zero.
288 This must match what the corresponding MEM_* macros return when the
289 field is not present. */
290 if (alias == 0 && expr == 0 && offset == 0
292 || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size)))
293 && (STRICT_ALIGNMENT && mode != BLKmode
294 ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT))
299 attrs.offset = offset;
303 slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT);
306 *slot = ggc_alloc (sizeof (mem_attrs));
307 memcpy (*slot, &attrs, sizeof (mem_attrs));
313 /* Returns a hash code for X (which is a really a reg_attrs *). */
316 reg_attrs_htab_hash (const void *x)
318 reg_attrs *p = (reg_attrs *) x;
320 return ((p->offset * 1000) ^ (long) p->decl);
323 /* Returns nonzero if the value represented by X (which is really a
324 reg_attrs *) is the same as that given by Y (which is also really a
328 reg_attrs_htab_eq (const void *x, const void *y)
330 reg_attrs *p = (reg_attrs *) x;
331 reg_attrs *q = (reg_attrs *) y;
333 return (p->decl == q->decl && p->offset == q->offset);
335 /* Allocate a new reg_attrs structure and insert it into the hash table if
336 one identical to it is not already in the table. We are doing this for
340 get_reg_attrs (tree decl, int offset)
345 /* If everything is the default, we can just return zero. */
346 if (decl == 0 && offset == 0)
350 attrs.offset = offset;
352 slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT);
355 *slot = ggc_alloc (sizeof (reg_attrs));
356 memcpy (*slot, &attrs, sizeof (reg_attrs));
364 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule
370 rtx x = gen_rtx_ASM_INPUT (VOIDmode, "");
371 MEM_VOLATILE_P (x) = true;
377 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
378 don't attempt to share with the various global pieces of rtl (such as
379 frame_pointer_rtx). */
382 gen_raw_REG (enum machine_mode mode, int regno)
384 rtx x = gen_rtx_raw_REG (mode, regno);
385 ORIGINAL_REGNO (x) = regno;
389 /* There are some RTL codes that require special attention; the generation
390 functions do the raw handling. If you add to this list, modify
391 special_rtx in gengenrtl.c as well. */
394 gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg)
398 if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT)
399 return const_int_rtx[arg + MAX_SAVED_CONST_INT];
401 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
402 if (const_true_rtx && arg == STORE_FLAG_VALUE)
403 return const_true_rtx;
406 /* Look up the CONST_INT in the hash table. */
407 slot = htab_find_slot_with_hash (const_int_htab, &arg,
408 (hashval_t) arg, INSERT);
410 *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg);
416 gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode)
418 return GEN_INT (trunc_int_for_mode (c, mode));
421 /* CONST_DOUBLEs might be created from pairs of integers, or from
422 REAL_VALUE_TYPEs. Also, their length is known only at run time,
423 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
425 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
426 hash table. If so, return its counterpart; otherwise add it
427 to the hash table and return it. */
429 lookup_const_double (rtx real)
431 void **slot = htab_find_slot (const_double_htab, real, INSERT);
438 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
439 VALUE in mode MODE. */
441 const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode)
443 rtx real = rtx_alloc (CONST_DOUBLE);
444 PUT_MODE (real, mode);
448 return lookup_const_double (real);
451 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
452 of ints: I0 is the low-order word and I1 is the high-order word.
453 Do not use this routine for non-integer modes; convert to
454 REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */
457 immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode)
462 /* There are the following cases (note that there are no modes with
463 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT):
465 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
467 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of
468 the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only
469 from copies of the sign bit, and sign of i0 and i1 are the same), then
470 we return a CONST_INT for i0.
471 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
472 if (mode != VOIDmode)
474 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
475 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
476 /* We can get a 0 for an error mark. */
477 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
478 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT);
480 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
481 return gen_int_mode (i0, mode);
483 gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT);
486 /* If this integer fits in one word, return a CONST_INT. */
487 if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0))
490 /* We use VOIDmode for integers. */
491 value = rtx_alloc (CONST_DOUBLE);
492 PUT_MODE (value, VOIDmode);
494 CONST_DOUBLE_LOW (value) = i0;
495 CONST_DOUBLE_HIGH (value) = i1;
497 for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++)
498 XWINT (value, i) = 0;
500 return lookup_const_double (value);
504 gen_rtx_REG (enum machine_mode mode, unsigned int regno)
506 /* In case the MD file explicitly references the frame pointer, have
507 all such references point to the same frame pointer. This is
508 used during frame pointer elimination to distinguish the explicit
509 references to these registers from pseudos that happened to be
512 If we have eliminated the frame pointer or arg pointer, we will
513 be using it as a normal register, for example as a spill
514 register. In such cases, we might be accessing it in a mode that
515 is not Pmode and therefore cannot use the pre-allocated rtx.
517 Also don't do this when we are making new REGs in reload, since
518 we don't want to get confused with the real pointers. */
520 if (mode == Pmode && !reload_in_progress)
522 if (regno == FRAME_POINTER_REGNUM
523 && (!reload_completed || frame_pointer_needed))
524 return frame_pointer_rtx;
525 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
526 if (regno == HARD_FRAME_POINTER_REGNUM
527 && (!reload_completed || frame_pointer_needed))
528 return hard_frame_pointer_rtx;
530 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
531 if (regno == ARG_POINTER_REGNUM)
532 return arg_pointer_rtx;
534 #ifdef RETURN_ADDRESS_POINTER_REGNUM
535 if (regno == RETURN_ADDRESS_POINTER_REGNUM)
536 return return_address_pointer_rtx;
538 if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM
539 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
540 return pic_offset_table_rtx;
541 if (regno == STACK_POINTER_REGNUM)
542 return stack_pointer_rtx;
546 /* If the per-function register table has been set up, try to re-use
547 an existing entry in that table to avoid useless generation of RTL.
549 This code is disabled for now until we can fix the various backends
550 which depend on having non-shared hard registers in some cases. Long
551 term we want to re-enable this code as it can significantly cut down
552 on the amount of useless RTL that gets generated.
554 We'll also need to fix some code that runs after reload that wants to
555 set ORIGINAL_REGNO. */
560 && regno < FIRST_PSEUDO_REGISTER
561 && reg_raw_mode[regno] == mode)
562 return regno_reg_rtx[regno];
565 return gen_raw_REG (mode, regno);
569 gen_rtx_MEM (enum machine_mode mode, rtx addr)
571 rtx rt = gen_rtx_raw_MEM (mode, addr);
573 /* This field is not cleared by the mere allocation of the rtx, so
580 /* Generate a memory referring to non-trapping constant memory. */
583 gen_const_mem (enum machine_mode mode, rtx addr)
585 rtx mem = gen_rtx_MEM (mode, addr);
586 MEM_READONLY_P (mem) = 1;
587 MEM_NOTRAP_P (mem) = 1;
591 /* Generate a MEM referring to fixed portions of the frame, e.g., register
595 gen_frame_mem (enum machine_mode mode, rtx addr)
597 rtx mem = gen_rtx_MEM (mode, addr);
598 MEM_NOTRAP_P (mem) = 1;
599 set_mem_alias_set (mem, get_frame_alias_set ());
603 /* Generate a MEM referring to a temporary use of the stack, not part
604 of the fixed stack frame. For example, something which is pushed
605 by a target splitter. */
607 gen_tmp_stack_mem (enum machine_mode mode, rtx addr)
609 rtx mem = gen_rtx_MEM (mode, addr);
610 MEM_NOTRAP_P (mem) = 1;
611 if (!current_function_calls_alloca)
612 set_mem_alias_set (mem, get_frame_alias_set ());
616 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
617 this construct would be valid, and false otherwise. */
620 validate_subreg (enum machine_mode omode, enum machine_mode imode,
621 rtx reg, unsigned int offset)
623 unsigned int isize = GET_MODE_SIZE (imode);
624 unsigned int osize = GET_MODE_SIZE (omode);
626 /* All subregs must be aligned. */
627 if (offset % osize != 0)
630 /* The subreg offset cannot be outside the inner object. */
634 /* ??? This should not be here. Temporarily continue to allow word_mode
635 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
636 Generally, backends are doing something sketchy but it'll take time to
638 if (omode == word_mode)
640 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
641 is the culprit here, and not the backends. */
642 else if (osize >= UNITS_PER_WORD && isize >= osize)
644 /* Allow component subregs of complex and vector. Though given the below
645 extraction rules, it's not always clear what that means. */
646 else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
647 && GET_MODE_INNER (imode) == omode)
649 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
650 i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to
651 represent this. It's questionable if this ought to be represented at
652 all -- why can't this all be hidden in post-reload splitters that make
653 arbitrarily mode changes to the registers themselves. */
654 else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode)
656 /* Subregs involving floating point modes are not allowed to
657 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
658 (subreg:SI (reg:DF) 0) isn't. */
659 else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode))
665 /* Paradoxical subregs must have offset zero. */
669 /* This is a normal subreg. Verify that the offset is representable. */
671 /* For hard registers, we already have most of these rules collected in
672 subreg_offset_representable_p. */
673 if (reg && REG_P (reg) && HARD_REGISTER_P (reg))
675 unsigned int regno = REGNO (reg);
677 #ifdef CANNOT_CHANGE_MODE_CLASS
678 if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
679 && GET_MODE_INNER (imode) == omode)
681 else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode))
685 return subreg_offset_representable_p (regno, imode, offset, omode);
688 /* For pseudo registers, we want most of the same checks. Namely:
689 If the register no larger than a word, the subreg must be lowpart.
690 If the register is larger than a word, the subreg must be the lowpart
691 of a subword. A subreg does *not* perform arbitrary bit extraction.
692 Given that we've already checked mode/offset alignment, we only have
693 to check subword subregs here. */
694 if (osize < UNITS_PER_WORD)
696 enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode;
697 unsigned int low_off = subreg_lowpart_offset (omode, wmode);
698 if (offset % UNITS_PER_WORD != low_off)
705 gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset)
707 gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset));
708 return gen_rtx_raw_SUBREG (mode, reg, offset);
711 /* Generate a SUBREG representing the least-significant part of REG if MODE
712 is smaller than mode of REG, otherwise paradoxical SUBREG. */
715 gen_lowpart_SUBREG (enum machine_mode mode, rtx reg)
717 enum machine_mode inmode;
719 inmode = GET_MODE (reg);
720 if (inmode == VOIDmode)
722 return gen_rtx_SUBREG (mode, reg,
723 subreg_lowpart_offset (mode, inmode));
726 /* gen_rtvec (n, [rt1, ..., rtn])
728 ** This routine creates an rtvec and stores within it the
729 ** pointers to rtx's which are its arguments.
734 gen_rtvec (int n, ...)
743 return NULL_RTVEC; /* Don't allocate an empty rtvec... */
745 vector = alloca (n * sizeof (rtx));
747 for (i = 0; i < n; i++)
748 vector[i] = va_arg (p, rtx);
750 /* The definition of VA_* in K&R C causes `n' to go out of scope. */
754 return gen_rtvec_v (save_n, vector);
758 gen_rtvec_v (int n, rtx *argp)
764 return NULL_RTVEC; /* Don't allocate an empty rtvec... */
766 rt_val = rtvec_alloc (n); /* Allocate an rtvec... */
768 for (i = 0; i < n; i++)
769 rt_val->elem[i] = *argp++;
774 /* Generate a REG rtx for a new pseudo register of mode MODE.
775 This pseudo is assigned the next sequential register number. */
778 gen_reg_rtx (enum machine_mode mode)
780 struct function *f = cfun;
783 gcc_assert (can_create_pseudo_p ());
785 if (generating_concat_p
786 && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
787 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT))
789 /* For complex modes, don't make a single pseudo.
790 Instead, make a CONCAT of two pseudos.
791 This allows noncontiguous allocation of the real and imaginary parts,
792 which makes much better code. Besides, allocating DCmode
793 pseudos overstrains reload on some machines like the 386. */
794 rtx realpart, imagpart;
795 enum machine_mode partmode = GET_MODE_INNER (mode);
797 realpart = gen_reg_rtx (partmode);
798 imagpart = gen_reg_rtx (partmode);
799 return gen_rtx_CONCAT (mode, realpart, imagpart);
802 /* Make sure regno_pointer_align, and regno_reg_rtx are large
803 enough to have an element for this pseudo reg number. */
805 if (reg_rtx_no == f->emit->regno_pointer_align_length)
807 int old_size = f->emit->regno_pointer_align_length;
811 new = ggc_realloc (f->emit->regno_pointer_align, old_size * 2);
812 memset (new + old_size, 0, old_size);
813 f->emit->regno_pointer_align = (unsigned char *) new;
815 new1 = ggc_realloc (f->emit->x_regno_reg_rtx,
816 old_size * 2 * sizeof (rtx));
817 memset (new1 + old_size, 0, old_size * sizeof (rtx));
818 regno_reg_rtx = new1;
820 f->emit->regno_pointer_align_length = old_size * 2;
823 val = gen_raw_REG (mode, reg_rtx_no);
824 regno_reg_rtx[reg_rtx_no++] = val;
828 /* Update NEW with the same attributes as REG, but offsetted by OFFSET.
829 Do the big endian correction if needed. */
832 update_reg_offset (rtx new, rtx reg, int offset)
835 HOST_WIDE_INT var_size;
837 /* PR middle-end/14084
838 The problem appears when a variable is stored in a larger register
839 and later it is used in the original mode or some mode in between
840 or some part of variable is accessed.
842 On little endian machines there is no problem because
843 the REG_OFFSET of the start of the variable is the same when
844 accessed in any mode (it is 0).
846 However, this is not true on big endian machines.
847 The offset of the start of the variable is different when accessed
849 When we are taking a part of the REG we have to change the OFFSET
850 from offset WRT size of mode of REG to offset WRT size of variable.
852 If we would not do the big endian correction the resulting REG_OFFSET
853 would be larger than the size of the DECL.
855 Examples of correction, for BYTES_BIG_ENDIAN WORDS_BIG_ENDIAN machine:
857 REG.mode MODE DECL size old offset new offset description
858 DI SI 4 4 0 int32 in SImode
859 DI SI 1 4 0 char in SImode
860 DI QI 1 7 0 char in QImode
861 DI QI 4 5 1 1st element in QImode
863 DI HI 4 6 2 1st element in HImode
866 If the size of DECL is equal or greater than the size of REG
867 we can't do this correction because the register holds the
868 whole variable or a part of the variable and thus the REG_OFFSET
869 is already correct. */
871 decl = REG_EXPR (reg);
872 if ((BYTES_BIG_ENDIAN || WORDS_BIG_ENDIAN)
875 && GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (GET_MODE (new))
876 && ((var_size = int_size_in_bytes (TREE_TYPE (decl))) > 0
877 && var_size < GET_MODE_SIZE (GET_MODE (reg))))
881 /* Convert machine endian to little endian WRT size of mode of REG. */
882 if (WORDS_BIG_ENDIAN)
883 offset_le = ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset)
884 / UNITS_PER_WORD) * UNITS_PER_WORD;
886 offset_le = (offset / UNITS_PER_WORD) * UNITS_PER_WORD;
888 if (BYTES_BIG_ENDIAN)
889 offset_le += ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset)
892 offset_le += offset % UNITS_PER_WORD;
894 if (offset_le >= var_size)
896 /* MODE is wider than the variable so the new reg will cover
897 the whole variable so the resulting OFFSET should be 0. */
902 /* Convert little endian to machine endian WRT size of variable. */
903 if (WORDS_BIG_ENDIAN)
904 offset = ((var_size - 1 - offset_le)
905 / UNITS_PER_WORD) * UNITS_PER_WORD;
907 offset = (offset_le / UNITS_PER_WORD) * UNITS_PER_WORD;
909 if (BYTES_BIG_ENDIAN)
910 offset += ((var_size - 1 - offset_le)
913 offset += offset_le % UNITS_PER_WORD;
917 REG_ATTRS (new) = get_reg_attrs (REG_EXPR (reg),
918 REG_OFFSET (reg) + offset);
921 /* Generate a register with same attributes as REG, but offsetted by
925 gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno,
928 rtx new = gen_rtx_REG (mode, regno);
930 update_reg_offset (new, reg, offset);
934 /* Generate a new pseudo-register with the same attributes as REG, but
935 offsetted by OFFSET. */
938 gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset)
940 rtx new = gen_reg_rtx (mode);
942 update_reg_offset (new, reg, offset);
946 /* Set the decl for MEM to DECL. */
949 set_reg_attrs_from_mem (rtx reg, rtx mem)
951 if (MEM_OFFSET (mem) && GET_CODE (MEM_OFFSET (mem)) == CONST_INT)
953 = get_reg_attrs (MEM_EXPR (mem), INTVAL (MEM_OFFSET (mem)));
956 /* Set the register attributes for registers contained in PARM_RTX.
957 Use needed values from memory attributes of MEM. */
960 set_reg_attrs_for_parm (rtx parm_rtx, rtx mem)
962 if (REG_P (parm_rtx))
963 set_reg_attrs_from_mem (parm_rtx, mem);
964 else if (GET_CODE (parm_rtx) == PARALLEL)
966 /* Check for a NULL entry in the first slot, used to indicate that the
967 parameter goes both on the stack and in registers. */
968 int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1;
969 for (; i < XVECLEN (parm_rtx, 0); i++)
971 rtx x = XVECEXP (parm_rtx, 0, i);
972 if (REG_P (XEXP (x, 0)))
973 REG_ATTRS (XEXP (x, 0))
974 = get_reg_attrs (MEM_EXPR (mem),
975 INTVAL (XEXP (x, 1)));
980 /* Assign the RTX X to declaration T. */
982 set_decl_rtl (tree t, rtx x)
984 DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x;
988 /* For register, we maintain the reverse information too. */
990 REG_ATTRS (x) = get_reg_attrs (t, 0);
991 else if (GET_CODE (x) == SUBREG)
992 REG_ATTRS (SUBREG_REG (x))
993 = get_reg_attrs (t, -SUBREG_BYTE (x));
994 if (GET_CODE (x) == CONCAT)
996 if (REG_P (XEXP (x, 0)))
997 REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0);
998 if (REG_P (XEXP (x, 1)))
999 REG_ATTRS (XEXP (x, 1))
1000 = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0))));
1002 if (GET_CODE (x) == PARALLEL)
1005 for (i = 0; i < XVECLEN (x, 0); i++)
1007 rtx y = XVECEXP (x, 0, i);
1008 if (REG_P (XEXP (y, 0)))
1009 REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1)));
1014 /* Assign the RTX X to parameter declaration T. */
1016 set_decl_incoming_rtl (tree t, rtx x)
1018 DECL_INCOMING_RTL (t) = x;
1022 /* For register, we maintain the reverse information too. */
1024 REG_ATTRS (x) = get_reg_attrs (t, 0);
1025 else if (GET_CODE (x) == SUBREG)
1026 REG_ATTRS (SUBREG_REG (x))
1027 = get_reg_attrs (t, -SUBREG_BYTE (x));
1028 if (GET_CODE (x) == CONCAT)
1030 if (REG_P (XEXP (x, 0)))
1031 REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0);
1032 if (REG_P (XEXP (x, 1)))
1033 REG_ATTRS (XEXP (x, 1))
1034 = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0))));
1036 if (GET_CODE (x) == PARALLEL)
1040 /* Check for a NULL entry, used to indicate that the parameter goes
1041 both on the stack and in registers. */
1042 if (XEXP (XVECEXP (x, 0, 0), 0))
1047 for (i = start; i < XVECLEN (x, 0); i++)
1049 rtx y = XVECEXP (x, 0, i);
1050 if (REG_P (XEXP (y, 0)))
1051 REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1)));
1056 /* Identify REG (which may be a CONCAT) as a user register. */
1059 mark_user_reg (rtx reg)
1061 if (GET_CODE (reg) == CONCAT)
1063 REG_USERVAR_P (XEXP (reg, 0)) = 1;
1064 REG_USERVAR_P (XEXP (reg, 1)) = 1;
1068 gcc_assert (REG_P (reg));
1069 REG_USERVAR_P (reg) = 1;
1073 /* Identify REG as a probable pointer register and show its alignment
1074 as ALIGN, if nonzero. */
1077 mark_reg_pointer (rtx reg, int align)
1079 if (! REG_POINTER (reg))
1081 REG_POINTER (reg) = 1;
1084 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1086 else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg)))
1087 /* We can no-longer be sure just how aligned this pointer is. */
1088 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1091 /* Return 1 plus largest pseudo reg number used in the current function. */
1099 /* Return 1 + the largest label number used so far in the current function. */
1102 max_label_num (void)
1107 /* Return first label number used in this function (if any were used). */
1110 get_first_label_num (void)
1112 return first_label_num;
1115 /* If the rtx for label was created during the expansion of a nested
1116 function, then first_label_num won't include this label number.
1117 Fix this now so that array indicies work later. */
1120 maybe_set_first_label_num (rtx x)
1122 if (CODE_LABEL_NUMBER (x) < first_label_num)
1123 first_label_num = CODE_LABEL_NUMBER (x);
1126 /* Return a value representing some low-order bits of X, where the number
1127 of low-order bits is given by MODE. Note that no conversion is done
1128 between floating-point and fixed-point values, rather, the bit
1129 representation is returned.
1131 This function handles the cases in common between gen_lowpart, below,
1132 and two variants in cse.c and combine.c. These are the cases that can
1133 be safely handled at all points in the compilation.
1135 If this is not a case we can handle, return 0. */
1138 gen_lowpart_common (enum machine_mode mode, rtx x)
1140 int msize = GET_MODE_SIZE (mode);
1143 enum machine_mode innermode;
1145 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1146 so we have to make one up. Yuk. */
1147 innermode = GET_MODE (x);
1148 if (GET_CODE (x) == CONST_INT
1149 && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT)
1150 innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1151 else if (innermode == VOIDmode)
1152 innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0);
1154 xsize = GET_MODE_SIZE (innermode);
1156 gcc_assert (innermode != VOIDmode && innermode != BLKmode);
1158 if (innermode == mode)
1161 /* MODE must occupy no more words than the mode of X. */
1162 if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD
1163 > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
1166 /* Don't allow generating paradoxical FLOAT_MODE subregs. */
1167 if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize)
1170 offset = subreg_lowpart_offset (mode, innermode);
1172 if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
1173 && (GET_MODE_CLASS (mode) == MODE_INT
1174 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT))
1176 /* If we are getting the low-order part of something that has been
1177 sign- or zero-extended, we can either just use the object being
1178 extended or make a narrower extension. If we want an even smaller
1179 piece than the size of the object being extended, call ourselves
1182 This case is used mostly by combine and cse. */
1184 if (GET_MODE (XEXP (x, 0)) == mode)
1186 else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
1187 return gen_lowpart_common (mode, XEXP (x, 0));
1188 else if (msize < xsize)
1189 return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0));
1191 else if (GET_CODE (x) == SUBREG || REG_P (x)
1192 || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
1193 || GET_CODE (x) == CONST_DOUBLE || GET_CODE (x) == CONST_INT)
1194 return simplify_gen_subreg (mode, x, innermode, offset);
1196 /* Otherwise, we can't do this. */
1201 gen_highpart (enum machine_mode mode, rtx x)
1203 unsigned int msize = GET_MODE_SIZE (mode);
1206 /* This case loses if X is a subreg. To catch bugs early,
1207 complain if an invalid MODE is used even in other cases. */
1208 gcc_assert (msize <= UNITS_PER_WORD
1209 || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x)));
1211 result = simplify_gen_subreg (mode, x, GET_MODE (x),
1212 subreg_highpart_offset (mode, GET_MODE (x)));
1213 gcc_assert (result);
1215 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1216 the target if we have a MEM. gen_highpart must return a valid operand,
1217 emitting code if necessary to do so. */
1220 result = validize_mem (result);
1221 gcc_assert (result);
1227 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1228 be VOIDmode constant. */
1230 gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp)
1232 if (GET_MODE (exp) != VOIDmode)
1234 gcc_assert (GET_MODE (exp) == innermode);
1235 return gen_highpart (outermode, exp);
1237 return simplify_gen_subreg (outermode, exp, innermode,
1238 subreg_highpart_offset (outermode, innermode));
1241 /* Return offset in bytes to get OUTERMODE low part
1242 of the value in mode INNERMODE stored in memory in target format. */
1245 subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode)
1247 unsigned int offset = 0;
1248 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
1252 if (WORDS_BIG_ENDIAN)
1253 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
1254 if (BYTES_BIG_ENDIAN)
1255 offset += difference % UNITS_PER_WORD;
1261 /* Return offset in bytes to get OUTERMODE high part
1262 of the value in mode INNERMODE stored in memory in target format. */
1264 subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode)
1266 unsigned int offset = 0;
1267 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
1269 gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode));
1273 if (! WORDS_BIG_ENDIAN)
1274 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
1275 if (! BYTES_BIG_ENDIAN)
1276 offset += difference % UNITS_PER_WORD;
1282 /* Return 1 iff X, assumed to be a SUBREG,
1283 refers to the least significant part of its containing reg.
1284 If X is not a SUBREG, always return 1 (it is its own low part!). */
1287 subreg_lowpart_p (rtx x)
1289 if (GET_CODE (x) != SUBREG)
1291 else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
1294 return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x)))
1295 == SUBREG_BYTE (x));
1298 /* Return subword OFFSET of operand OP.
1299 The word number, OFFSET, is interpreted as the word number starting
1300 at the low-order address. OFFSET 0 is the low-order word if not
1301 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1303 If we cannot extract the required word, we return zero. Otherwise,
1304 an rtx corresponding to the requested word will be returned.
1306 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1307 reload has completed, a valid address will always be returned. After
1308 reload, if a valid address cannot be returned, we return zero.
1310 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1311 it is the responsibility of the caller.
1313 MODE is the mode of OP in case it is a CONST_INT.
1315 ??? This is still rather broken for some cases. The problem for the
1316 moment is that all callers of this thing provide no 'goal mode' to
1317 tell us to work with. This exists because all callers were written
1318 in a word based SUBREG world.
1319 Now use of this function can be deprecated by simplify_subreg in most
1324 operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode)
1326 if (mode == VOIDmode)
1327 mode = GET_MODE (op);
1329 gcc_assert (mode != VOIDmode);
1331 /* If OP is narrower than a word, fail. */
1333 && (GET_MODE_SIZE (mode) < UNITS_PER_WORD))
1336 /* If we want a word outside OP, return zero. */
1338 && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode))
1341 /* Form a new MEM at the requested address. */
1344 rtx new = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD);
1346 if (! validate_address)
1349 else if (reload_completed)
1351 if (! strict_memory_address_p (word_mode, XEXP (new, 0)))
1355 return replace_equiv_address (new, XEXP (new, 0));
1358 /* Rest can be handled by simplify_subreg. */
1359 return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD));
1362 /* Similar to `operand_subword', but never return 0. If we can't
1363 extract the required subword, put OP into a register and try again.
1364 The second attempt must succeed. We always validate the address in
1367 MODE is the mode of OP, in case it is CONST_INT. */
1370 operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode)
1372 rtx result = operand_subword (op, offset, 1, mode);
1377 if (mode != BLKmode && mode != VOIDmode)
1379 /* If this is a register which can not be accessed by words, copy it
1380 to a pseudo register. */
1382 op = copy_to_reg (op);
1384 op = force_reg (mode, op);
1387 result = operand_subword (op, offset, 1, mode);
1388 gcc_assert (result);
1393 /* Within a MEM_EXPR, we care about either (1) a component ref of a decl,
1394 or (2) a component ref of something variable. Represent the later with
1395 a NULL expression. */
1398 component_ref_for_mem_expr (tree ref)
1400 tree inner = TREE_OPERAND (ref, 0);
1402 if (TREE_CODE (inner) == COMPONENT_REF)
1403 inner = component_ref_for_mem_expr (inner);
1406 /* Now remove any conversions: they don't change what the underlying
1407 object is. Likewise for SAVE_EXPR. */
1408 while (TREE_CODE (inner) == NOP_EXPR || TREE_CODE (inner) == CONVERT_EXPR
1409 || TREE_CODE (inner) == NON_LVALUE_EXPR
1410 || TREE_CODE (inner) == VIEW_CONVERT_EXPR
1411 || TREE_CODE (inner) == SAVE_EXPR)
1412 inner = TREE_OPERAND (inner, 0);
1414 if (! DECL_P (inner))
1418 if (inner == TREE_OPERAND (ref, 0))
1421 return build3 (COMPONENT_REF, TREE_TYPE (ref), inner,
1422 TREE_OPERAND (ref, 1), NULL_TREE);
1425 /* Returns 1 if both MEM_EXPR can be considered equal
1429 mem_expr_equal_p (tree expr1, tree expr2)
1434 if (! expr1 || ! expr2)
1437 if (TREE_CODE (expr1) != TREE_CODE (expr2))
1440 if (TREE_CODE (expr1) == COMPONENT_REF)
1442 mem_expr_equal_p (TREE_OPERAND (expr1, 0),
1443 TREE_OPERAND (expr2, 0))
1444 && mem_expr_equal_p (TREE_OPERAND (expr1, 1), /* field decl */
1445 TREE_OPERAND (expr2, 1));
1447 if (INDIRECT_REF_P (expr1))
1448 return mem_expr_equal_p (TREE_OPERAND (expr1, 0),
1449 TREE_OPERAND (expr2, 0));
1451 /* ARRAY_REFs, ARRAY_RANGE_REFs and BIT_FIELD_REFs should already
1452 have been resolved here. */
1453 gcc_assert (DECL_P (expr1));
1455 /* Decls with different pointers can't be equal. */
1459 /* Given REF, a MEM, and T, either the type of X or the expression
1460 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1461 if we are making a new object of this type. BITPOS is nonzero if
1462 there is an offset outstanding on T that will be applied later. */
1465 set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp,
1466 HOST_WIDE_INT bitpos)
1468 HOST_WIDE_INT alias = MEM_ALIAS_SET (ref);
1469 tree expr = MEM_EXPR (ref);
1470 rtx offset = MEM_OFFSET (ref);
1471 rtx size = MEM_SIZE (ref);
1472 unsigned int align = MEM_ALIGN (ref);
1473 HOST_WIDE_INT apply_bitpos = 0;
1476 /* It can happen that type_for_mode was given a mode for which there
1477 is no language-level type. In which case it returns NULL, which
1482 type = TYPE_P (t) ? t : TREE_TYPE (t);
1483 if (type == error_mark_node)
1486 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1487 wrong answer, as it assumes that DECL_RTL already has the right alias
1488 info. Callers should not set DECL_RTL until after the call to
1489 set_mem_attributes. */
1490 gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t));
1492 /* Get the alias set from the expression or type (perhaps using a
1493 front-end routine) and use it. */
1494 alias = get_alias_set (t);
1496 MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type);
1497 MEM_IN_STRUCT_P (ref)
1498 = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE;
1499 MEM_POINTER (ref) = POINTER_TYPE_P (type);
1501 /* If we are making an object of this type, or if this is a DECL, we know
1502 that it is a scalar if the type is not an aggregate. */
1503 if ((objectp || DECL_P (t))
1504 && ! AGGREGATE_TYPE_P (type)
1505 && TREE_CODE (type) != COMPLEX_TYPE)
1506 MEM_SCALAR_P (ref) = 1;
1508 /* We can set the alignment from the type if we are making an object,
1509 this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */
1510 if (objectp || TREE_CODE (t) == INDIRECT_REF
1511 || TREE_CODE (t) == ALIGN_INDIRECT_REF
1512 || TYPE_ALIGN_OK (type))
1513 align = MAX (align, TYPE_ALIGN (type));
1515 if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF)
1517 if (integer_zerop (TREE_OPERAND (t, 1)))
1518 /* We don't know anything about the alignment. */
1519 align = BITS_PER_UNIT;
1521 align = tree_low_cst (TREE_OPERAND (t, 1), 1);
1524 /* If the size is known, we can set that. */
1525 if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1))
1526 size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1));
1528 /* If T is not a type, we may be able to deduce some more information about
1534 if (TREE_THIS_VOLATILE (t))
1535 MEM_VOLATILE_P (ref) = 1;
1537 /* Now remove any conversions: they don't change what the underlying
1538 object is. Likewise for SAVE_EXPR. */
1539 while (TREE_CODE (t) == NOP_EXPR || TREE_CODE (t) == CONVERT_EXPR
1540 || TREE_CODE (t) == NON_LVALUE_EXPR
1541 || TREE_CODE (t) == VIEW_CONVERT_EXPR
1542 || TREE_CODE (t) == SAVE_EXPR)
1543 t = TREE_OPERAND (t, 0);
1545 /* We may look through structure-like accesses for the purposes of
1546 examining TREE_THIS_NOTRAP, but not array-like accesses. */
1548 while (TREE_CODE (base) == COMPONENT_REF
1549 || TREE_CODE (base) == REALPART_EXPR
1550 || TREE_CODE (base) == IMAGPART_EXPR
1551 || TREE_CODE (base) == BIT_FIELD_REF)
1552 base = TREE_OPERAND (base, 0);
1556 if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS))
1557 MEM_NOTRAP_P (ref) = !DECL_WEAK (base);
1559 MEM_NOTRAP_P (ref) = 1;
1562 MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base);
1564 base = get_base_address (base);
1565 if (base && DECL_P (base)
1566 && TREE_READONLY (base)
1567 && (TREE_STATIC (base) || DECL_EXTERNAL (base)))
1569 tree base_type = TREE_TYPE (base);
1570 gcc_assert (!(base_type && TYPE_NEEDS_CONSTRUCTING (base_type))
1571 || DECL_ARTIFICIAL (base));
1572 MEM_READONLY_P (ref) = 1;
1575 /* If this expression uses it's parent's alias set, mark it such
1576 that we won't change it. */
1577 if (component_uses_parent_alias_set (t))
1578 MEM_KEEP_ALIAS_SET_P (ref) = 1;
1580 /* If this is a decl, set the attributes of the MEM from it. */
1584 offset = const0_rtx;
1585 apply_bitpos = bitpos;
1586 size = (DECL_SIZE_UNIT (t)
1587 && host_integerp (DECL_SIZE_UNIT (t), 1)
1588 ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0);
1589 align = DECL_ALIGN (t);
1592 /* If this is a constant, we know the alignment. */
1593 else if (CONSTANT_CLASS_P (t))
1595 align = TYPE_ALIGN (type);
1596 #ifdef CONSTANT_ALIGNMENT
1597 align = CONSTANT_ALIGNMENT (t, align);
1601 /* If this is a field reference and not a bit-field, record it. */
1602 /* ??? There is some information that can be gleened from bit-fields,
1603 such as the word offset in the structure that might be modified.
1604 But skip it for now. */
1605 else if (TREE_CODE (t) == COMPONENT_REF
1606 && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
1608 expr = component_ref_for_mem_expr (t);
1609 offset = const0_rtx;
1610 apply_bitpos = bitpos;
1611 /* ??? Any reason the field size would be different than
1612 the size we got from the type? */
1615 /* If this is an array reference, look for an outer field reference. */
1616 else if (TREE_CODE (t) == ARRAY_REF)
1618 tree off_tree = size_zero_node;
1619 /* We can't modify t, because we use it at the end of the
1625 tree index = TREE_OPERAND (t2, 1);
1626 tree low_bound = array_ref_low_bound (t2);
1627 tree unit_size = array_ref_element_size (t2);
1629 /* We assume all arrays have sizes that are a multiple of a byte.
1630 First subtract the lower bound, if any, in the type of the
1631 index, then convert to sizetype and multiply by the size of
1632 the array element. */
1633 if (! integer_zerop (low_bound))
1634 index = fold_build2 (MINUS_EXPR, TREE_TYPE (index),
1637 off_tree = size_binop (PLUS_EXPR,
1638 size_binop (MULT_EXPR,
1639 fold_convert (sizetype,
1643 t2 = TREE_OPERAND (t2, 0);
1645 while (TREE_CODE (t2) == ARRAY_REF);
1651 if (host_integerp (off_tree, 1))
1653 HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1);
1654 HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT;
1655 align = DECL_ALIGN (t2);
1656 if (aoff && (unsigned HOST_WIDE_INT) aoff < align)
1658 offset = GEN_INT (ioff);
1659 apply_bitpos = bitpos;
1662 else if (TREE_CODE (t2) == COMPONENT_REF)
1664 expr = component_ref_for_mem_expr (t2);
1665 if (host_integerp (off_tree, 1))
1667 offset = GEN_INT (tree_low_cst (off_tree, 1));
1668 apply_bitpos = bitpos;
1670 /* ??? Any reason the field size would be different than
1671 the size we got from the type? */
1673 else if (flag_argument_noalias > 1
1674 && (INDIRECT_REF_P (t2))
1675 && TREE_CODE (TREE_OPERAND (t2, 0)) == PARM_DECL)
1682 /* If this is a Fortran indirect argument reference, record the
1684 else if (flag_argument_noalias > 1
1685 && (INDIRECT_REF_P (t))
1686 && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL)
1693 /* If we modified OFFSET based on T, then subtract the outstanding
1694 bit position offset. Similarly, increase the size of the accessed
1695 object to contain the negative offset. */
1698 offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT));
1700 size = plus_constant (size, apply_bitpos / BITS_PER_UNIT);
1703 if (TREE_CODE (t) == ALIGN_INDIRECT_REF)
1705 /* Force EXPR and OFFSE to NULL, since we don't know exactly what
1706 we're overlapping. */
1711 /* Now set the attributes we computed above. */
1713 = get_mem_attrs (alias, expr, offset, size, align, GET_MODE (ref));
1715 /* If this is already known to be a scalar or aggregate, we are done. */
1716 if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref))
1719 /* If it is a reference into an aggregate, this is part of an aggregate.
1720 Otherwise we don't know. */
1721 else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF
1722 || TREE_CODE (t) == ARRAY_RANGE_REF
1723 || TREE_CODE (t) == BIT_FIELD_REF)
1724 MEM_IN_STRUCT_P (ref) = 1;
1728 set_mem_attributes (rtx ref, tree t, int objectp)
1730 set_mem_attributes_minus_bitpos (ref, t, objectp, 0);
1733 /* Set the decl for MEM to DECL. */
1736 set_mem_attrs_from_reg (rtx mem, rtx reg)
1739 = get_mem_attrs (MEM_ALIAS_SET (mem), REG_EXPR (reg),
1740 GEN_INT (REG_OFFSET (reg)),
1741 MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem));
1744 /* Set the alias set of MEM to SET. */
1747 set_mem_alias_set (rtx mem, HOST_WIDE_INT set)
1749 #ifdef ENABLE_CHECKING
1750 /* If the new and old alias sets don't conflict, something is wrong. */
1751 gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem)));
1754 MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem),
1755 MEM_SIZE (mem), MEM_ALIGN (mem),
1759 /* Set the alignment of MEM to ALIGN bits. */
1762 set_mem_align (rtx mem, unsigned int align)
1764 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1765 MEM_OFFSET (mem), MEM_SIZE (mem), align,
1769 /* Set the expr for MEM to EXPR. */
1772 set_mem_expr (rtx mem, tree expr)
1775 = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem),
1776 MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem));
1779 /* Set the offset of MEM to OFFSET. */
1782 set_mem_offset (rtx mem, rtx offset)
1784 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1785 offset, MEM_SIZE (mem), MEM_ALIGN (mem),
1789 /* Set the size of MEM to SIZE. */
1792 set_mem_size (rtx mem, rtx size)
1794 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1795 MEM_OFFSET (mem), size, MEM_ALIGN (mem),
1799 /* Return a memory reference like MEMREF, but with its mode changed to MODE
1800 and its address changed to ADDR. (VOIDmode means don't change the mode.
1801 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
1802 returned memory location is required to be valid. The memory
1803 attributes are not changed. */
1806 change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate)
1810 gcc_assert (MEM_P (memref));
1811 if (mode == VOIDmode)
1812 mode = GET_MODE (memref);
1814 addr = XEXP (memref, 0);
1815 if (mode == GET_MODE (memref) && addr == XEXP (memref, 0)
1816 && (!validate || memory_address_p (mode, addr)))
1821 if (reload_in_progress || reload_completed)
1822 gcc_assert (memory_address_p (mode, addr));
1824 addr = memory_address (mode, addr);
1827 if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref))
1830 new = gen_rtx_MEM (mode, addr);
1831 MEM_COPY_ATTRIBUTES (new, memref);
1835 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
1836 way we are changing MEMREF, so we only preserve the alias set. */
1839 change_address (rtx memref, enum machine_mode mode, rtx addr)
1841 rtx new = change_address_1 (memref, mode, addr, 1), size;
1842 enum machine_mode mmode = GET_MODE (new);
1845 size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode));
1846 align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode);
1848 /* If there are no changes, just return the original memory reference. */
1851 if (MEM_ATTRS (memref) == 0
1852 || (MEM_EXPR (memref) == NULL
1853 && MEM_OFFSET (memref) == NULL
1854 && MEM_SIZE (memref) == size
1855 && MEM_ALIGN (memref) == align))
1858 new = gen_rtx_MEM (mmode, XEXP (memref, 0));
1859 MEM_COPY_ATTRIBUTES (new, memref);
1863 = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, mmode);
1868 /* Return a memory reference like MEMREF, but with its mode changed
1869 to MODE and its address offset by OFFSET bytes. If VALIDATE is
1870 nonzero, the memory address is forced to be valid.
1871 If ADJUST is zero, OFFSET is only used to update MEM_ATTRS
1872 and caller is responsible for adjusting MEMREF base register. */
1875 adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset,
1876 int validate, int adjust)
1878 rtx addr = XEXP (memref, 0);
1880 rtx memoffset = MEM_OFFSET (memref);
1882 unsigned int memalign = MEM_ALIGN (memref);
1884 /* If there are no changes, just return the original memory reference. */
1885 if (mode == GET_MODE (memref) && !offset
1886 && (!validate || memory_address_p (mode, addr)))
1889 /* ??? Prefer to create garbage instead of creating shared rtl.
1890 This may happen even if offset is nonzero -- consider
1891 (plus (plus reg reg) const_int) -- so do this always. */
1892 addr = copy_rtx (addr);
1896 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
1897 object, we can merge it into the LO_SUM. */
1898 if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM
1900 && (unsigned HOST_WIDE_INT) offset
1901 < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT)
1902 addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0),
1903 plus_constant (XEXP (addr, 1), offset));
1905 addr = plus_constant (addr, offset);
1908 new = change_address_1 (memref, mode, addr, validate);
1910 /* Compute the new values of the memory attributes due to this adjustment.
1911 We add the offsets and update the alignment. */
1913 memoffset = GEN_INT (offset + INTVAL (memoffset));
1915 /* Compute the new alignment by taking the MIN of the alignment and the
1916 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
1921 (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT);
1923 /* We can compute the size in a number of ways. */
1924 if (GET_MODE (new) != BLKmode)
1925 size = GEN_INT (GET_MODE_SIZE (GET_MODE (new)));
1926 else if (MEM_SIZE (memref))
1927 size = plus_constant (MEM_SIZE (memref), -offset);
1929 MEM_ATTRS (new) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref),
1930 memoffset, size, memalign, GET_MODE (new));
1932 /* At some point, we should validate that this offset is within the object,
1933 if all the appropriate values are known. */
1937 /* Return a memory reference like MEMREF, but with its mode changed
1938 to MODE and its address changed to ADDR, which is assumed to be
1939 MEMREF offseted by OFFSET bytes. If VALIDATE is
1940 nonzero, the memory address is forced to be valid. */
1943 adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr,
1944 HOST_WIDE_INT offset, int validate)
1946 memref = change_address_1 (memref, VOIDmode, addr, validate);
1947 return adjust_address_1 (memref, mode, offset, validate, 0);
1950 /* Return a memory reference like MEMREF, but whose address is changed by
1951 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
1952 known to be in OFFSET (possibly 1). */
1955 offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2)
1957 rtx new, addr = XEXP (memref, 0);
1959 new = simplify_gen_binary (PLUS, Pmode, addr, offset);
1961 /* At this point we don't know _why_ the address is invalid. It
1962 could have secondary memory references, multiplies or anything.
1964 However, if we did go and rearrange things, we can wind up not
1965 being able to recognize the magic around pic_offset_table_rtx.
1966 This stuff is fragile, and is yet another example of why it is
1967 bad to expose PIC machinery too early. */
1968 if (! memory_address_p (GET_MODE (memref), new)
1969 && GET_CODE (addr) == PLUS
1970 && XEXP (addr, 0) == pic_offset_table_rtx)
1972 addr = force_reg (GET_MODE (addr), addr);
1973 new = simplify_gen_binary (PLUS, Pmode, addr, offset);
1976 update_temp_slot_address (XEXP (memref, 0), new);
1977 new = change_address_1 (memref, VOIDmode, new, 1);
1979 /* If there are no changes, just return the original memory reference. */
1983 /* Update the alignment to reflect the offset. Reset the offset, which
1986 = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0,
1987 MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT),
1992 /* Return a memory reference like MEMREF, but with its address changed to
1993 ADDR. The caller is asserting that the actual piece of memory pointed
1994 to is the same, just the form of the address is being changed, such as
1995 by putting something into a register. */
1998 replace_equiv_address (rtx memref, rtx addr)
2000 /* change_address_1 copies the memory attribute structure without change
2001 and that's exactly what we want here. */
2002 update_temp_slot_address (XEXP (memref, 0), addr);
2003 return change_address_1 (memref, VOIDmode, addr, 1);
2006 /* Likewise, but the reference is not required to be valid. */
2009 replace_equiv_address_nv (rtx memref, rtx addr)
2011 return change_address_1 (memref, VOIDmode, addr, 0);
2014 /* Return a memory reference like MEMREF, but with its mode widened to
2015 MODE and offset by OFFSET. This would be used by targets that e.g.
2016 cannot issue QImode memory operations and have to use SImode memory
2017 operations plus masking logic. */
2020 widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset)
2022 rtx new = adjust_address_1 (memref, mode, offset, 1, 1);
2023 tree expr = MEM_EXPR (new);
2024 rtx memoffset = MEM_OFFSET (new);
2025 unsigned int size = GET_MODE_SIZE (mode);
2027 /* If there are no changes, just return the original memory reference. */
2031 /* If we don't know what offset we were at within the expression, then
2032 we can't know if we've overstepped the bounds. */
2038 if (TREE_CODE (expr) == COMPONENT_REF)
2040 tree field = TREE_OPERAND (expr, 1);
2041 tree offset = component_ref_field_offset (expr);
2043 if (! DECL_SIZE_UNIT (field))
2049 /* Is the field at least as large as the access? If so, ok,
2050 otherwise strip back to the containing structure. */
2051 if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST
2052 && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0
2053 && INTVAL (memoffset) >= 0)
2056 if (! host_integerp (offset, 1))
2062 expr = TREE_OPERAND (expr, 0);
2064 = (GEN_INT (INTVAL (memoffset)
2065 + tree_low_cst (offset, 1)
2066 + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1)
2069 /* Similarly for the decl. */
2070 else if (DECL_P (expr)
2071 && DECL_SIZE_UNIT (expr)
2072 && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST
2073 && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0
2074 && (! memoffset || INTVAL (memoffset) >= 0))
2078 /* The widened memory access overflows the expression, which means
2079 that it could alias another expression. Zap it. */
2086 memoffset = NULL_RTX;
2088 /* The widened memory may alias other stuff, so zap the alias set. */
2089 /* ??? Maybe use get_alias_set on any remaining expression. */
2091 MEM_ATTRS (new) = get_mem_attrs (0, expr, memoffset, GEN_INT (size),
2092 MEM_ALIGN (new), mode);
2097 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2100 gen_label_rtx (void)
2102 return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX,
2103 NULL, label_num++, NULL);
2106 /* For procedure integration. */
2108 /* Install new pointers to the first and last insns in the chain.
2109 Also, set cur_insn_uid to one higher than the last in use.
2110 Used for an inline-procedure after copying the insn chain. */
2113 set_new_first_and_last_insn (rtx first, rtx last)
2121 for (insn = first; insn; insn = NEXT_INSN (insn))
2122 cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
2127 /* Go through all the RTL insn bodies and copy any invalid shared
2128 structure. This routine should only be called once. */
2131 unshare_all_rtl_1 (rtx insn)
2133 /* Unshare just about everything else. */
2134 unshare_all_rtl_in_chain (insn);
2136 /* Make sure the addresses of stack slots found outside the insn chain
2137 (such as, in DECL_RTL of a variable) are not shared
2138 with the insn chain.
2140 This special care is necessary when the stack slot MEM does not
2141 actually appear in the insn chain. If it does appear, its address
2142 is unshared from all else at that point. */
2143 stack_slot_list = copy_rtx_if_shared (stack_slot_list);
2146 /* Go through all the RTL insn bodies and copy any invalid shared
2147 structure, again. This is a fairly expensive thing to do so it
2148 should be done sparingly. */
2151 unshare_all_rtl_again (rtx insn)
2156 for (p = insn; p; p = NEXT_INSN (p))
2159 reset_used_flags (PATTERN (p));
2160 reset_used_flags (REG_NOTES (p));
2163 /* Make sure that virtual stack slots are not shared. */
2164 reset_used_decls (DECL_INITIAL (cfun->decl));
2166 /* Make sure that virtual parameters are not shared. */
2167 for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl))
2168 reset_used_flags (DECL_RTL (decl));
2170 reset_used_flags (stack_slot_list);
2172 unshare_all_rtl_1 (insn);
2176 unshare_all_rtl (void)
2178 unshare_all_rtl_1 (get_insns ());
2182 struct tree_opt_pass pass_unshare_all_rtl =
2184 "unshare", /* name */
2186 unshare_all_rtl, /* execute */
2189 0, /* static_pass_number */
2191 0, /* properties_required */
2192 0, /* properties_provided */
2193 0, /* properties_destroyed */
2194 0, /* todo_flags_start */
2195 TODO_dump_func, /* todo_flags_finish */
2200 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2201 Recursively does the same for subexpressions. */
2204 verify_rtx_sharing (rtx orig, rtx insn)
2209 const char *format_ptr;
2214 code = GET_CODE (x);
2216 /* These types may be freely shared. */
2231 /* SCRATCH must be shared because they represent distinct values. */
2233 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2238 if (shared_const_p (orig))
2243 /* A MEM is allowed to be shared if its address is constant. */
2244 if (CONSTANT_ADDRESS_P (XEXP (x, 0))
2245 || reload_completed || reload_in_progress)
2254 /* This rtx may not be shared. If it has already been seen,
2255 replace it with a copy of itself. */
2256 #ifdef ENABLE_CHECKING
2257 if (RTX_FLAG (x, used))
2259 error ("invalid rtl sharing found in the insn");
2261 error ("shared rtx");
2263 internal_error ("internal consistency failure");
2266 gcc_assert (!RTX_FLAG (x, used));
2268 RTX_FLAG (x, used) = 1;
2270 /* Now scan the subexpressions recursively. */
2272 format_ptr = GET_RTX_FORMAT (code);
2274 for (i = 0; i < GET_RTX_LENGTH (code); i++)
2276 switch (*format_ptr++)
2279 verify_rtx_sharing (XEXP (x, i), insn);
2283 if (XVEC (x, i) != NULL)
2286 int len = XVECLEN (x, i);
2288 for (j = 0; j < len; j++)
2290 /* We allow sharing of ASM_OPERANDS inside single
2292 if (j && GET_CODE (XVECEXP (x, i, j)) == SET
2293 && (GET_CODE (SET_SRC (XVECEXP (x, i, j)))
2295 verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn);
2297 verify_rtx_sharing (XVECEXP (x, i, j), insn);
2306 /* Go through all the RTL insn bodies and check that there is no unexpected
2307 sharing in between the subexpressions. */
2310 verify_rtl_sharing (void)
2314 for (p = get_insns (); p; p = NEXT_INSN (p))
2317 reset_used_flags (PATTERN (p));
2318 reset_used_flags (REG_NOTES (p));
2319 if (GET_CODE (PATTERN (p)) == SEQUENCE)
2322 rtx q, sequence = PATTERN (p);
2324 for (i = 0; i < XVECLEN (sequence, 0); i++)
2326 q = XVECEXP (sequence, 0, i);
2327 gcc_assert (INSN_P (q));
2328 reset_used_flags (PATTERN (q));
2329 reset_used_flags (REG_NOTES (q));
2334 for (p = get_insns (); p; p = NEXT_INSN (p))
2337 verify_rtx_sharing (PATTERN (p), p);
2338 verify_rtx_sharing (REG_NOTES (p), p);
2342 /* Go through all the RTL insn bodies and copy any invalid shared structure.
2343 Assumes the mark bits are cleared at entry. */
2346 unshare_all_rtl_in_chain (rtx insn)
2348 for (; insn; insn = NEXT_INSN (insn))
2351 PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn));
2352 REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn));
2356 /* Go through all virtual stack slots of a function and mark them as
2359 reset_used_decls (tree blk)
2364 for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t))
2365 if (DECL_RTL_SET_P (t))
2366 reset_used_flags (DECL_RTL (t));
2368 /* Now process sub-blocks. */
2369 for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t))
2370 reset_used_decls (t);
2373 /* Mark ORIG as in use, and return a copy of it if it was already in use.
2374 Recursively does the same for subexpressions. Uses
2375 copy_rtx_if_shared_1 to reduce stack space. */
2378 copy_rtx_if_shared (rtx orig)
2380 copy_rtx_if_shared_1 (&orig);
2384 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
2385 use. Recursively does the same for subexpressions. */
2388 copy_rtx_if_shared_1 (rtx *orig1)
2394 const char *format_ptr;
2398 /* Repeat is used to turn tail-recursion into iteration. */
2405 code = GET_CODE (x);
2407 /* These types may be freely shared. */
2421 /* SCRATCH must be shared because they represent distinct values. */
2424 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2429 if (shared_const_p (x))
2438 /* The chain of insns is not being copied. */
2445 /* This rtx may not be shared. If it has already been seen,
2446 replace it with a copy of itself. */
2448 if (RTX_FLAG (x, used))
2450 x = shallow_copy_rtx (x);
2453 RTX_FLAG (x, used) = 1;
2455 /* Now scan the subexpressions recursively.
2456 We can store any replaced subexpressions directly into X
2457 since we know X is not shared! Any vectors in X
2458 must be copied if X was copied. */
2460 format_ptr = GET_RTX_FORMAT (code);
2461 length = GET_RTX_LENGTH (code);
2464 for (i = 0; i < length; i++)
2466 switch (*format_ptr++)
2470 copy_rtx_if_shared_1 (last_ptr);
2471 last_ptr = &XEXP (x, i);
2475 if (XVEC (x, i) != NULL)
2478 int len = XVECLEN (x, i);
2480 /* Copy the vector iff I copied the rtx and the length
2482 if (copied && len > 0)
2483 XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem);
2485 /* Call recursively on all inside the vector. */
2486 for (j = 0; j < len; j++)
2489 copy_rtx_if_shared_1 (last_ptr);
2490 last_ptr = &XVECEXP (x, i, j);
2505 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
2506 to look for shared sub-parts. */
2509 reset_used_flags (rtx x)
2513 const char *format_ptr;
2516 /* Repeat is used to turn tail-recursion into iteration. */
2521 code = GET_CODE (x);
2523 /* These types may be freely shared so we needn't do any resetting
2544 /* The chain of insns is not being copied. */
2551 RTX_FLAG (x, used) = 0;
2553 format_ptr = GET_RTX_FORMAT (code);
2554 length = GET_RTX_LENGTH (code);
2556 for (i = 0; i < length; i++)
2558 switch (*format_ptr++)
2566 reset_used_flags (XEXP (x, i));
2570 for (j = 0; j < XVECLEN (x, i); j++)
2571 reset_used_flags (XVECEXP (x, i, j));
2577 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
2578 to look for shared sub-parts. */
2581 set_used_flags (rtx x)
2585 const char *format_ptr;
2590 code = GET_CODE (x);
2592 /* These types may be freely shared so we needn't do any resetting
2613 /* The chain of insns is not being copied. */
2620 RTX_FLAG (x, used) = 1;
2622 format_ptr = GET_RTX_FORMAT (code);
2623 for (i = 0; i < GET_RTX_LENGTH (code); i++)
2625 switch (*format_ptr++)
2628 set_used_flags (XEXP (x, i));
2632 for (j = 0; j < XVECLEN (x, i); j++)
2633 set_used_flags (XVECEXP (x, i, j));
2639 /* Copy X if necessary so that it won't be altered by changes in OTHER.
2640 Return X or the rtx for the pseudo reg the value of X was copied into.
2641 OTHER must be valid as a SET_DEST. */
2644 make_safe_from (rtx x, rtx other)
2647 switch (GET_CODE (other))
2650 other = SUBREG_REG (other);
2652 case STRICT_LOW_PART:
2655 other = XEXP (other, 0);
2664 && GET_CODE (x) != SUBREG)
2666 && (REGNO (other) < FIRST_PSEUDO_REGISTER
2667 || reg_mentioned_p (other, x))))
2669 rtx temp = gen_reg_rtx (GET_MODE (x));
2670 emit_move_insn (temp, x);
2676 /* Emission of insns (adding them to the doubly-linked list). */
2678 /* Return the first insn of the current sequence or current function. */
2686 /* Specify a new insn as the first in the chain. */
2689 set_first_insn (rtx insn)
2691 gcc_assert (!PREV_INSN (insn));
2695 /* Return the last insn emitted in current sequence or current function. */
2698 get_last_insn (void)
2703 /* Specify a new insn as the last in the chain. */
2706 set_last_insn (rtx insn)
2708 gcc_assert (!NEXT_INSN (insn));
2712 /* Return the last insn emitted, even if it is in a sequence now pushed. */
2715 get_last_insn_anywhere (void)
2717 struct sequence_stack *stack;
2720 for (stack = seq_stack; stack; stack = stack->next)
2721 if (stack->last != 0)
2726 /* Return the first nonnote insn emitted in current sequence or current
2727 function. This routine looks inside SEQUENCEs. */
2730 get_first_nonnote_insn (void)
2732 rtx insn = first_insn;
2737 for (insn = next_insn (insn);
2738 insn && NOTE_P (insn);
2739 insn = next_insn (insn))
2743 if (NONJUMP_INSN_P (insn)
2744 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2745 insn = XVECEXP (PATTERN (insn), 0, 0);
2752 /* Return the last nonnote insn emitted in current sequence or current
2753 function. This routine looks inside SEQUENCEs. */
2756 get_last_nonnote_insn (void)
2758 rtx insn = last_insn;
2763 for (insn = previous_insn (insn);
2764 insn && NOTE_P (insn);
2765 insn = previous_insn (insn))
2769 if (NONJUMP_INSN_P (insn)
2770 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2771 insn = XVECEXP (PATTERN (insn), 0,
2772 XVECLEN (PATTERN (insn), 0) - 1);
2779 /* Return a number larger than any instruction's uid in this function. */
2784 return cur_insn_uid;
2787 /* Return the next insn. If it is a SEQUENCE, return the first insn
2791 next_insn (rtx insn)
2795 insn = NEXT_INSN (insn);
2796 if (insn && NONJUMP_INSN_P (insn)
2797 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2798 insn = XVECEXP (PATTERN (insn), 0, 0);
2804 /* Return the previous insn. If it is a SEQUENCE, return the last insn
2808 previous_insn (rtx insn)
2812 insn = PREV_INSN (insn);
2813 if (insn && NONJUMP_INSN_P (insn)
2814 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2815 insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1);
2821 /* Return the next insn after INSN that is not a NOTE. This routine does not
2822 look inside SEQUENCEs. */
2825 next_nonnote_insn (rtx insn)
2829 insn = NEXT_INSN (insn);
2830 if (insn == 0 || !NOTE_P (insn))
2837 /* Return the previous insn before INSN that is not a NOTE. This routine does
2838 not look inside SEQUENCEs. */
2841 prev_nonnote_insn (rtx insn)
2845 insn = PREV_INSN (insn);
2846 if (insn == 0 || !NOTE_P (insn))
2853 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
2854 or 0, if there is none. This routine does not look inside
2858 next_real_insn (rtx insn)
2862 insn = NEXT_INSN (insn);
2863 if (insn == 0 || INSN_P (insn))
2870 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
2871 or 0, if there is none. This routine does not look inside
2875 prev_real_insn (rtx insn)
2879 insn = PREV_INSN (insn);
2880 if (insn == 0 || INSN_P (insn))
2887 /* Return the last CALL_INSN in the current list, or 0 if there is none.
2888 This routine does not look inside SEQUENCEs. */
2891 last_call_insn (void)
2895 for (insn = get_last_insn ();
2896 insn && !CALL_P (insn);
2897 insn = PREV_INSN (insn))
2903 /* Find the next insn after INSN that really does something. This routine
2904 does not look inside SEQUENCEs. Until reload has completed, this is the
2905 same as next_real_insn. */
2908 active_insn_p (rtx insn)
2910 return (CALL_P (insn) || JUMP_P (insn)
2911 || (NONJUMP_INSN_P (insn)
2912 && (! reload_completed
2913 || (GET_CODE (PATTERN (insn)) != USE
2914 && GET_CODE (PATTERN (insn)) != CLOBBER))));
2918 next_active_insn (rtx insn)
2922 insn = NEXT_INSN (insn);
2923 if (insn == 0 || active_insn_p (insn))
2930 /* Find the last insn before INSN that really does something. This routine
2931 does not look inside SEQUENCEs. Until reload has completed, this is the
2932 same as prev_real_insn. */
2935 prev_active_insn (rtx insn)
2939 insn = PREV_INSN (insn);
2940 if (insn == 0 || active_insn_p (insn))
2947 /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */
2950 next_label (rtx insn)
2954 insn = NEXT_INSN (insn);
2955 if (insn == 0 || LABEL_P (insn))
2962 /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */
2965 prev_label (rtx insn)
2969 insn = PREV_INSN (insn);
2970 if (insn == 0 || LABEL_P (insn))
2977 /* Return the last label to mark the same position as LABEL. Return null
2978 if LABEL itself is null. */
2981 skip_consecutive_labels (rtx label)
2985 for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn))
2993 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
2994 and REG_CC_USER notes so we can find it. */
2997 link_cc0_insns (rtx insn)
2999 rtx user = next_nonnote_insn (insn);
3001 if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE)
3002 user = XVECEXP (PATTERN (user), 0, 0);
3004 REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn,
3006 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn));
3009 /* Return the next insn that uses CC0 after INSN, which is assumed to
3010 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
3011 applied to the result of this function should yield INSN).
3013 Normally, this is simply the next insn. However, if a REG_CC_USER note
3014 is present, it contains the insn that uses CC0.
3016 Return 0 if we can't find the insn. */
3019 next_cc0_user (rtx insn)
3021 rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX);
3024 return XEXP (note, 0);
3026 insn = next_nonnote_insn (insn);
3027 if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
3028 insn = XVECEXP (PATTERN (insn), 0, 0);
3030 if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn)))
3036 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
3037 note, it is the previous insn. */
3040 prev_cc0_setter (rtx insn)
3042 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
3045 return XEXP (note, 0);
3047 insn = prev_nonnote_insn (insn);
3048 gcc_assert (sets_cc0_p (PATTERN (insn)));
3055 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3058 find_auto_inc (rtx *xp, void *data)
3063 if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC)
3066 switch (GET_CODE (x))
3074 if (rtx_equal_p (reg, XEXP (x, 0)))
3085 /* Increment the label uses for all labels present in rtx. */
3088 mark_label_nuses (rtx x)
3094 code = GET_CODE (x);
3095 if (code == LABEL_REF && LABEL_P (XEXP (x, 0)))
3096 LABEL_NUSES (XEXP (x, 0))++;
3098 fmt = GET_RTX_FORMAT (code);
3099 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3102 mark_label_nuses (XEXP (x, i));
3103 else if (fmt[i] == 'E')
3104 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3105 mark_label_nuses (XVECEXP (x, i, j));
3110 /* Try splitting insns that can be split for better scheduling.
3111 PAT is the pattern which might split.
3112 TRIAL is the insn providing PAT.
3113 LAST is nonzero if we should return the last insn of the sequence produced.
3115 If this routine succeeds in splitting, it returns the first or last
3116 replacement insn depending on the value of LAST. Otherwise, it
3117 returns TRIAL. If the insn to be returned can be split, it will be. */
3120 try_split (rtx pat, rtx trial, int last)
3122 rtx before = PREV_INSN (trial);
3123 rtx after = NEXT_INSN (trial);
3124 int has_barrier = 0;
3128 rtx insn_last, insn;
3131 if (any_condjump_p (trial)
3132 && (note = find_reg_note (trial, REG_BR_PROB, 0)))
3133 split_branch_probability = INTVAL (XEXP (note, 0));
3134 probability = split_branch_probability;
3136 seq = split_insns (pat, trial);
3138 split_branch_probability = -1;
3140 /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER.
3141 We may need to handle this specially. */
3142 if (after && BARRIER_P (after))
3145 after = NEXT_INSN (after);
3151 /* Avoid infinite loop if any insn of the result matches
3152 the original pattern. */
3156 if (INSN_P (insn_last)
3157 && rtx_equal_p (PATTERN (insn_last), pat))
3159 if (!NEXT_INSN (insn_last))
3161 insn_last = NEXT_INSN (insn_last);
3164 /* We will be adding the new sequence to the function. The splitters
3165 may have introduced invalid RTL sharing, so unshare the sequence now. */
3166 unshare_all_rtl_in_chain (seq);
3169 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3173 mark_jump_label (PATTERN (insn), insn, 0);
3175 if (probability != -1
3176 && any_condjump_p (insn)
3177 && !find_reg_note (insn, REG_BR_PROB, 0))
3179 /* We can preserve the REG_BR_PROB notes only if exactly
3180 one jump is created, otherwise the machine description
3181 is responsible for this step using
3182 split_branch_probability variable. */
3183 gcc_assert (njumps == 1);
3185 = gen_rtx_EXPR_LIST (REG_BR_PROB,
3186 GEN_INT (probability),
3192 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3193 in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */
3196 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3199 rtx *p = &CALL_INSN_FUNCTION_USAGE (insn);
3202 *p = CALL_INSN_FUNCTION_USAGE (trial);
3203 SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial);
3207 /* Copy notes, particularly those related to the CFG. */
3208 for (note = REG_NOTES (trial); note; note = XEXP (note, 1))
3210 switch (REG_NOTE_KIND (note))
3213 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3216 || (flag_non_call_exceptions && INSN_P (insn)
3217 && may_trap_p (PATTERN (insn))))
3219 = gen_rtx_EXPR_LIST (REG_EH_REGION,
3227 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3231 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note),
3237 case REG_NON_LOCAL_GOTO:
3238 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3242 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note),
3250 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3252 rtx reg = XEXP (note, 0);
3253 if (!FIND_REG_INC_NOTE (insn, reg)
3254 && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0)
3255 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, reg,
3266 /* If there are LABELS inside the split insns increment the
3267 usage count so we don't delete the label. */
3268 if (NONJUMP_INSN_P (trial))
3271 while (insn != NULL_RTX)
3273 if (NONJUMP_INSN_P (insn))
3274 mark_label_nuses (PATTERN (insn));
3276 insn = PREV_INSN (insn);
3280 tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial));
3282 delete_insn (trial);
3284 emit_barrier_after (tem);
3286 /* Recursively call try_split for each new insn created; by the
3287 time control returns here that insn will be fully split, so
3288 set LAST and continue from the insn after the one returned.
3289 We can't use next_active_insn here since AFTER may be a note.
3290 Ignore deleted insns, which can be occur if not optimizing. */
3291 for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem))
3292 if (! INSN_DELETED_P (tem) && INSN_P (tem))
3293 tem = try_split (PATTERN (tem), tem, 1);
3295 /* Return either the first or the last insn, depending on which was
3298 ? (after ? PREV_INSN (after) : last_insn)
3299 : NEXT_INSN (before);
3302 /* Make and return an INSN rtx, initializing all its slots.
3303 Store PATTERN in the pattern slots. */
3306 make_insn_raw (rtx pattern)
3310 insn = rtx_alloc (INSN);
3312 INSN_UID (insn) = cur_insn_uid++;
3313 PATTERN (insn) = pattern;
3314 INSN_CODE (insn) = -1;
3315 REG_NOTES (insn) = NULL;
3316 INSN_LOCATOR (insn) = curr_insn_locator ();
3317 BLOCK_FOR_INSN (insn) = NULL;
3319 #ifdef ENABLE_RTL_CHECKING
3322 && (returnjump_p (insn)
3323 || (GET_CODE (insn) == SET
3324 && SET_DEST (insn) == pc_rtx)))
3326 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
3334 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
3337 make_jump_insn_raw (rtx pattern)
3341 insn = rtx_alloc (JUMP_INSN);
3342 INSN_UID (insn) = cur_insn_uid++;
3344 PATTERN (insn) = pattern;
3345 INSN_CODE (insn) = -1;
3346 REG_NOTES (insn) = NULL;
3347 JUMP_LABEL (insn) = NULL;
3348 INSN_LOCATOR (insn) = curr_insn_locator ();
3349 BLOCK_FOR_INSN (insn) = NULL;
3354 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
3357 make_call_insn_raw (rtx pattern)
3361 insn = rtx_alloc (CALL_INSN);
3362 INSN_UID (insn) = cur_insn_uid++;
3364 PATTERN (insn) = pattern;
3365 INSN_CODE (insn) = -1;
3366 REG_NOTES (insn) = NULL;
3367 CALL_INSN_FUNCTION_USAGE (insn) = NULL;
3368 INSN_LOCATOR (insn) = curr_insn_locator ();
3369 BLOCK_FOR_INSN (insn) = NULL;
3374 /* Add INSN to the end of the doubly-linked list.
3375 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
3380 PREV_INSN (insn) = last_insn;
3381 NEXT_INSN (insn) = 0;
3383 if (NULL != last_insn)
3384 NEXT_INSN (last_insn) = insn;
3386 if (NULL == first_insn)
3392 /* Add INSN into the doubly-linked list after insn AFTER. This and
3393 the next should be the only functions called to insert an insn once
3394 delay slots have been filled since only they know how to update a
3398 add_insn_after (rtx insn, rtx after, basic_block bb)
3400 rtx next = NEXT_INSN (after);
3402 gcc_assert (!optimize || !INSN_DELETED_P (after));
3404 NEXT_INSN (insn) = next;
3405 PREV_INSN (insn) = after;
3409 PREV_INSN (next) = insn;
3410 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
3411 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn;
3413 else if (last_insn == after)
3417 struct sequence_stack *stack = seq_stack;
3418 /* Scan all pending sequences too. */
3419 for (; stack; stack = stack->next)
3420 if (after == stack->last)
3429 if (!BARRIER_P (after)
3430 && !BARRIER_P (insn)
3431 && (bb = BLOCK_FOR_INSN (after)))
3433 set_block_for_insn (insn, bb);
3435 df_insn_rescan (insn);
3436 /* Should not happen as first in the BB is always
3437 either NOTE or LABEL. */
3438 if (BB_END (bb) == after
3439 /* Avoid clobbering of structure when creating new BB. */
3440 && !BARRIER_P (insn)
3441 && !NOTE_INSN_BASIC_BLOCK_P (insn))
3445 NEXT_INSN (after) = insn;
3446 if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE)
3448 rtx sequence = PATTERN (after);
3449 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
3453 /* Add INSN into the doubly-linked list before insn BEFORE. This and
3454 the previous should be the only functions called to insert an insn
3455 once delay slots have been filled since only they know how to
3456 update a SEQUENCE. If BB is NULL, an attempt is made to infer the
3460 add_insn_before (rtx insn, rtx before, basic_block bb)
3462 rtx prev = PREV_INSN (before);
3464 gcc_assert (!optimize || !INSN_DELETED_P (before));
3466 PREV_INSN (insn) = prev;
3467 NEXT_INSN (insn) = before;
3471 NEXT_INSN (prev) = insn;
3472 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
3474 rtx sequence = PATTERN (prev);
3475 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
3478 else if (first_insn == before)
3482 struct sequence_stack *stack = seq_stack;
3483 /* Scan all pending sequences too. */
3484 for (; stack; stack = stack->next)
3485 if (before == stack->first)
3487 stack->first = insn;
3495 && !BARRIER_P (before)
3496 && !BARRIER_P (insn))
3497 bb = BLOCK_FOR_INSN (before);
3501 set_block_for_insn (insn, bb);
3503 df_insn_rescan (insn);
3504 /* Should not happen as first in the BB is always either NOTE or
3506 gcc_assert (BB_HEAD (bb) != insn
3507 /* Avoid clobbering of structure when creating new BB. */
3509 || NOTE_INSN_BASIC_BLOCK_P (insn));
3512 PREV_INSN (before) = insn;
3513 if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE)
3514 PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn;
3518 /* Replace insn with an deleted instruction note. */
3520 void set_insn_deleted (rtx insn)
3522 df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn));
3523 PUT_CODE (insn, NOTE);
3524 NOTE_KIND (insn) = NOTE_INSN_DELETED;
3528 /* Remove an insn from its doubly-linked list. This function knows how
3529 to handle sequences. */
3531 remove_insn (rtx insn)
3533 rtx next = NEXT_INSN (insn);
3534 rtx prev = PREV_INSN (insn);
3537 /* Later in the code, the block will be marked dirty. */
3538 df_insn_delete (NULL, INSN_UID (insn));
3542 NEXT_INSN (prev) = next;
3543 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
3545 rtx sequence = PATTERN (prev);
3546 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next;
3549 else if (first_insn == insn)
3553 struct sequence_stack *stack = seq_stack;
3554 /* Scan all pending sequences too. */
3555 for (; stack; stack = stack->next)
3556 if (insn == stack->first)
3558 stack->first = next;
3567 PREV_INSN (next) = prev;
3568 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
3569 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev;
3571 else if (last_insn == insn)
3575 struct sequence_stack *stack = seq_stack;
3576 /* Scan all pending sequences too. */
3577 for (; stack; stack = stack->next)
3578 if (insn == stack->last)
3586 if (!BARRIER_P (insn)
3587 && (bb = BLOCK_FOR_INSN (insn)))
3590 df_set_bb_dirty (bb);
3591 if (BB_HEAD (bb) == insn)
3593 /* Never ever delete the basic block note without deleting whole
3595 gcc_assert (!NOTE_P (insn));
3596 BB_HEAD (bb) = next;
3598 if (BB_END (bb) == insn)
3603 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
3606 add_function_usage_to (rtx call_insn, rtx call_fusage)
3608 gcc_assert (call_insn && CALL_P (call_insn));
3610 /* Put the register usage information on the CALL. If there is already
3611 some usage information, put ours at the end. */
3612 if (CALL_INSN_FUNCTION_USAGE (call_insn))
3616 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0;
3617 link = XEXP (link, 1))
3620 XEXP (link, 1) = call_fusage;
3623 CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage;
3626 /* Delete all insns made since FROM.
3627 FROM becomes the new last instruction. */
3630 delete_insns_since (rtx from)
3635 NEXT_INSN (from) = 0;
3639 /* This function is deprecated, please use sequences instead.
3641 Move a consecutive bunch of insns to a different place in the chain.
3642 The insns to be moved are those between FROM and TO.
3643 They are moved to a new position after the insn AFTER.
3644 AFTER must not be FROM or TO or any insn in between.
3646 This function does not know about SEQUENCEs and hence should not be
3647 called after delay-slot filling has been done. */
3650 reorder_insns_nobb (rtx from, rtx to, rtx after)
3652 /* Splice this bunch out of where it is now. */
3653 if (PREV_INSN (from))
3654 NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to);
3656 PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from);
3657 if (last_insn == to)
3658 last_insn = PREV_INSN (from);
3659 if (first_insn == from)
3660 first_insn = NEXT_INSN (to);
3662 /* Make the new neighbors point to it and it to them. */
3663 if (NEXT_INSN (after))
3664 PREV_INSN (NEXT_INSN (after)) = to;
3666 NEXT_INSN (to) = NEXT_INSN (after);
3667 PREV_INSN (from) = after;
3668 NEXT_INSN (after) = from;
3669 if (after == last_insn)
3673 /* Same as function above, but take care to update BB boundaries. */
3675 reorder_insns (rtx from, rtx to, rtx after)
3677 rtx prev = PREV_INSN (from);
3678 basic_block bb, bb2;
3680 reorder_insns_nobb (from, to, after);
3682 if (!BARRIER_P (after)
3683 && (bb = BLOCK_FOR_INSN (after)))
3686 df_set_bb_dirty (bb);
3688 if (!BARRIER_P (from)
3689 && (bb2 = BLOCK_FOR_INSN (from)))
3691 if (BB_END (bb2) == to)
3692 BB_END (bb2) = prev;
3693 df_set_bb_dirty (bb2);
3696 if (BB_END (bb) == after)
3699 for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x))
3702 set_block_for_insn (x, bb);
3703 df_insn_change_bb (x);
3709 /* Emit insn(s) of given code and pattern
3710 at a specified place within the doubly-linked list.
3712 All of the emit_foo global entry points accept an object
3713 X which is either an insn list or a PATTERN of a single
3716 There are thus a few canonical ways to generate code and
3717 emit it at a specific place in the instruction stream. For
3718 example, consider the instruction named SPOT and the fact that
3719 we would like to emit some instructions before SPOT. We might
3723 ... emit the new instructions ...
3724 insns_head = get_insns ();
3727 emit_insn_before (insns_head, SPOT);
3729 It used to be common to generate SEQUENCE rtl instead, but that
3730 is a relic of the past which no longer occurs. The reason is that
3731 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
3732 generated would almost certainly die right after it was created. */
3734 /* Make X be output before the instruction BEFORE. */
3737 emit_insn_before_noloc (rtx x, rtx before, basic_block bb)
3742 gcc_assert (before);
3747 switch (GET_CODE (x))
3758 rtx next = NEXT_INSN (insn);
3759 add_insn_before (insn, before, bb);
3765 #ifdef ENABLE_RTL_CHECKING
3772 last = make_insn_raw (x);
3773 add_insn_before (last, before, bb);
3780 /* Make an instruction with body X and code JUMP_INSN
3781 and output it before the instruction BEFORE. */
3784 emit_jump_insn_before_noloc (rtx x, rtx before)
3786 rtx insn, last = NULL_RTX;
3788 gcc_assert (before);
3790 switch (GET_CODE (x))
3801 rtx next = NEXT_INSN (insn);
3802 add_insn_before (insn, before, NULL);
3808 #ifdef ENABLE_RTL_CHECKING
3815 last = make_jump_insn_raw (x);
3816 add_insn_before (last, before, NULL);
3823 /* Make an instruction with body X and code CALL_INSN
3824 and output it before the instruction BEFORE. */
3827 emit_call_insn_before_noloc (rtx x, rtx before)
3829 rtx last = NULL_RTX, insn;
3831 gcc_assert (before);
3833 switch (GET_CODE (x))
3844 rtx next = NEXT_INSN (insn);
3845 add_insn_before (insn, before, NULL);
3851 #ifdef ENABLE_RTL_CHECKING
3858 last = make_call_insn_raw (x);
3859 add_insn_before (last, before, NULL);
3866 /* Make an insn of code BARRIER
3867 and output it before the insn BEFORE. */
3870 emit_barrier_before (rtx before)
3872 rtx insn = rtx_alloc (BARRIER);
3874 INSN_UID (insn) = cur_insn_uid++;
3876 add_insn_before (insn, before, NULL);
3880 /* Emit the label LABEL before the insn BEFORE. */
3883 emit_label_before (rtx label, rtx before)
3885 /* This can be called twice for the same label as a result of the
3886 confusion that follows a syntax error! So make it harmless. */
3887 if (INSN_UID (label) == 0)
3889 INSN_UID (label) = cur_insn_uid++;
3890 add_insn_before (label, before, NULL);
3896 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
3899 emit_note_before (enum insn_note subtype, rtx before)
3901 rtx note = rtx_alloc (NOTE);
3902 INSN_UID (note) = cur_insn_uid++;
3903 NOTE_KIND (note) = subtype;
3904 BLOCK_FOR_INSN (note) = NULL;
3905 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
3907 add_insn_before (note, before, NULL);
3911 /* Helper for emit_insn_after, handles lists of instructions
3915 emit_insn_after_1 (rtx first, rtx after, basic_block bb)
3919 if (!bb && !BARRIER_P (after))
3920 bb = BLOCK_FOR_INSN (after);
3924 df_set_bb_dirty (bb);
3925 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
3926 if (!BARRIER_P (last))
3928 set_block_for_insn (last, bb);
3929 df_insn_rescan (last);
3931 if (!BARRIER_P (last))
3933 set_block_for_insn (last, bb);
3934 df_insn_rescan (last);
3936 if (BB_END (bb) == after)
3940 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
3943 after_after = NEXT_INSN (after);
3945 NEXT_INSN (after) = first;
3946 PREV_INSN (first) = after;
3947 NEXT_INSN (last) = after_after;
3949 PREV_INSN (after_after) = last;
3951 if (after == last_insn)
3956 /* Make X be output after the insn AFTER and set the BB of insn. If
3957 BB is NULL, an attempt is made to infer the BB from AFTER. */
3960 emit_insn_after_noloc (rtx x, rtx after, basic_block bb)
3969 switch (GET_CODE (x))
3977 last = emit_insn_after_1 (x, after, bb);
3980 #ifdef ENABLE_RTL_CHECKING
3987 last = make_insn_raw (x);
3988 add_insn_after (last, after, bb);
3996 /* Make an insn of code JUMP_INSN with body X
3997 and output it after the insn AFTER. */
4000 emit_jump_insn_after_noloc (rtx x, rtx after)
4006 switch (GET_CODE (x))
4014 last = emit_insn_after_1 (x, after, NULL);
4017 #ifdef ENABLE_RTL_CHECKING
4024 last = make_jump_insn_raw (x);
4025 add_insn_after (last, after, NULL);
4032 /* Make an instruction with body X and code CALL_INSN
4033 and output it after the instruction AFTER. */
4036 emit_call_insn_after_noloc (rtx x, rtx after)
4042 switch (GET_CODE (x))
4050 last = emit_insn_after_1 (x, after, NULL);
4053 #ifdef ENABLE_RTL_CHECKING
4060 last = make_call_insn_raw (x);
4061 add_insn_after (last, after, NULL);
4068 /* Make an insn of code BARRIER
4069 and output it after the insn AFTER. */
4072 emit_barrier_after (rtx after)
4074 rtx insn = rtx_alloc (BARRIER);
4076 INSN_UID (insn) = cur_insn_uid++;
4078 add_insn_after (insn, after, NULL);
4082 /* Emit the label LABEL after the insn AFTER. */
4085 emit_label_after (rtx label, rtx after)
4087 /* This can be called twice for the same label
4088 as a result of the confusion that follows a syntax error!
4089 So make it harmless. */
4090 if (INSN_UID (label) == 0)
4092 INSN_UID (label) = cur_insn_uid++;
4093 add_insn_after (label, after, NULL);
4099 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4102 emit_note_after (enum insn_note subtype, rtx after)
4104 rtx note = rtx_alloc (NOTE);
4105 INSN_UID (note) = cur_insn_uid++;
4106 NOTE_KIND (note) = subtype;
4107 BLOCK_FOR_INSN (note) = NULL;
4108 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
4109 add_insn_after (note, after, NULL);
4113 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4115 emit_insn_after_setloc (rtx pattern, rtx after, int loc)
4117 rtx last = emit_insn_after_noloc (pattern, after, NULL);
4119 if (pattern == NULL_RTX || !loc)
4122 after = NEXT_INSN (after);
4125 if (active_insn_p (after) && !INSN_LOCATOR (after))
4126 INSN_LOCATOR (after) = loc;
4129 after = NEXT_INSN (after);
4134 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4136 emit_insn_after (rtx pattern, rtx after)
4139 return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (after));
4141 return emit_insn_after_noloc (pattern, after, NULL);
4144 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4146 emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc)
4148 rtx last = emit_jump_insn_after_noloc (pattern, after);
4150 if (pattern == NULL_RTX || !loc)
4153 after = NEXT_INSN (after);
4156 if (active_insn_p (after) && !INSN_LOCATOR (after))
4157 INSN_LOCATOR (after) = loc;
4160 after = NEXT_INSN (after);
4165 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4167 emit_jump_insn_after (rtx pattern, rtx after)
4170 return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (after));
4172 return emit_jump_insn_after_noloc (pattern, after);
4175 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4177 emit_call_insn_after_setloc (rtx pattern, rtx after, int loc)
4179 rtx last = emit_call_insn_after_noloc (pattern, after);
4181 if (pattern == NULL_RTX || !loc)
4184 after = NEXT_INSN (after);
4187 if (active_insn_p (after) && !INSN_LOCATOR (after))
4188 INSN_LOCATOR (after) = loc;
4191 after = NEXT_INSN (after);
4196 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4198 emit_call_insn_after (rtx pattern, rtx after)
4201 return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (after));
4203 return emit_call_insn_after_noloc (pattern, after);
4206 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */
4208 emit_insn_before_setloc (rtx pattern, rtx before, int loc)
4210 rtx first = PREV_INSN (before);
4211 rtx last = emit_insn_before_noloc (pattern, before, NULL);
4213 if (pattern == NULL_RTX || !loc)
4217 first = get_insns ();
4219 first = NEXT_INSN (first);
4222 if (active_insn_p (first) && !INSN_LOCATOR (first))
4223 INSN_LOCATOR (first) = loc;
4226 first = NEXT_INSN (first);
4231 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4233 emit_insn_before (rtx pattern, rtx before)
4235 if (INSN_P (before))
4236 return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (before));
4238 return emit_insn_before_noloc (pattern, before, NULL);
4241 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4243 emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc)
4245 rtx first = PREV_INSN (before);
4246 rtx last = emit_jump_insn_before_noloc (pattern, before);
4248 if (pattern == NULL_RTX)
4251 first = NEXT_INSN (first);
4254 if (active_insn_p (first) && !INSN_LOCATOR (first))
4255 INSN_LOCATOR (first) = loc;
4258 first = NEXT_INSN (first);
4263 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4265 emit_jump_insn_before (rtx pattern, rtx before)
4267 if (INSN_P (before))
4268 return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (before));
4270 return emit_jump_insn_before_noloc (pattern, before);
4273 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4275 emit_call_insn_before_setloc (rtx pattern, rtx before, int loc)
4277 rtx first = PREV_INSN (before);
4278 rtx last = emit_call_insn_before_noloc (pattern, before);
4280 if (pattern == NULL_RTX)
4283 first = NEXT_INSN (first);
4286 if (active_insn_p (first) && !INSN_LOCATOR (first))
4287 INSN_LOCATOR (first) = loc;
4290 first = NEXT_INSN (first);
4295 /* like emit_call_insn_before_noloc,
4296 but set insn_locator according to before. */
4298 emit_call_insn_before (rtx pattern, rtx before)
4300 if (INSN_P (before))
4301 return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (before));
4303 return emit_call_insn_before_noloc (pattern, before);
4306 /* Take X and emit it at the end of the doubly-linked
4309 Returns the last insn emitted. */
4314 rtx last = last_insn;
4320 switch (GET_CODE (x))
4331 rtx next = NEXT_INSN (insn);
4338 #ifdef ENABLE_RTL_CHECKING
4345 last = make_insn_raw (x);
4353 /* Make an insn of code JUMP_INSN with pattern X
4354 and add it to the end of the doubly-linked list. */
4357 emit_jump_insn (rtx x)
4359 rtx last = NULL_RTX, insn;
4361 switch (GET_CODE (x))
4372 rtx next = NEXT_INSN (insn);
4379 #ifdef ENABLE_RTL_CHECKING
4386 last = make_jump_insn_raw (x);
4394 /* Make an insn of code CALL_INSN with pattern X
4395 and add it to the end of the doubly-linked list. */
4398 emit_call_insn (rtx x)
4402 switch (GET_CODE (x))
4410 insn = emit_insn (x);
4413 #ifdef ENABLE_RTL_CHECKING
4420 insn = make_call_insn_raw (x);
4428 /* Add the label LABEL to the end of the doubly-linked list. */
4431 emit_label (rtx label)
4433 /* This can be called twice for the same label
4434 as a result of the confusion that follows a syntax error!
4435 So make it harmless. */
4436 if (INSN_UID (label) == 0)
4438 INSN_UID (label) = cur_insn_uid++;
4444 /* Make an insn of code BARRIER
4445 and add it to the end of the doubly-linked list. */
4450 rtx barrier = rtx_alloc (BARRIER);
4451 INSN_UID (barrier) = cur_insn_uid++;
4456 /* Emit a copy of note ORIG. */
4459 emit_note_copy (rtx orig)
4463 note = rtx_alloc (NOTE);
4465 INSN_UID (note) = cur_insn_uid++;
4466 NOTE_DATA (note) = NOTE_DATA (orig);
4467 NOTE_KIND (note) = NOTE_KIND (orig);
4468 BLOCK_FOR_INSN (note) = NULL;
4474 /* Make an insn of code NOTE or type NOTE_NO
4475 and add it to the end of the doubly-linked list. */
4478 emit_note (enum insn_note kind)
4482 note = rtx_alloc (NOTE);
4483 INSN_UID (note) = cur_insn_uid++;
4484 NOTE_KIND (note) = kind;
4485 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
4486 BLOCK_FOR_INSN (note) = NULL;
4491 /* Cause next statement to emit a line note even if the line number
4495 force_next_line_note (void)
4497 #ifdef USE_MAPPED_LOCATION
4500 last_location.line = -1;
4504 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
4505 note of this type already exists, remove it first. */
4508 set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum)
4510 rtx note = find_reg_note (insn, kind, NULL_RTX);
4511 rtx new_note = NULL;
4517 /* Don't add REG_EQUAL/REG_EQUIV notes if the insn
4518 has multiple sets (some callers assume single_set
4519 means the insn only has one set, when in fact it
4520 means the insn only has one * useful * set). */
4521 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
4527 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
4528 It serves no useful purpose and breaks eliminate_regs. */
4529 if (GET_CODE (datum) == ASM_OPERANDS)
4534 XEXP (note, 0) = datum;
4535 df_notes_rescan (insn);
4543 XEXP (note, 0) = datum;
4549 new_note = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn));
4550 REG_NOTES (insn) = new_note;
4556 df_notes_rescan (insn);
4562 return REG_NOTES (insn);
4565 /* Return an indication of which type of insn should have X as a body.
4566 The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */
4568 static enum rtx_code
4569 classify_insn (rtx x)
4573 if (GET_CODE (x) == CALL)
4575 if (GET_CODE (x) == RETURN)
4577 if (GET_CODE (x) == SET)
4579 if (SET_DEST (x) == pc_rtx)
4581 else if (GET_CODE (SET_SRC (x)) == CALL)
4586 if (GET_CODE (x) == PARALLEL)
4589 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
4590 if (GET_CODE (XVECEXP (x, 0, j)) == CALL)
4592 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
4593 && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx)
4595 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
4596 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL)
4602 /* Emit the rtl pattern X as an appropriate kind of insn.
4603 If X is a label, it is simply added into the insn chain. */
4608 enum rtx_code code = classify_insn (x);
4613 return emit_label (x);
4615 return emit_insn (x);
4618 rtx insn = emit_jump_insn (x);
4619 if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN)
4620 return emit_barrier ();
4624 return emit_call_insn (x);
4630 /* Space for free sequence stack entries. */
4631 static GTY ((deletable)) struct sequence_stack *free_sequence_stack;
4633 /* Begin emitting insns to a sequence. If this sequence will contain
4634 something that might cause the compiler to pop arguments to function
4635 calls (because those pops have previously been deferred; see
4636 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
4637 before calling this function. That will ensure that the deferred
4638 pops are not accidentally emitted in the middle of this sequence. */
4641 start_sequence (void)
4643 struct sequence_stack *tem;
4645 if (free_sequence_stack != NULL)
4647 tem = free_sequence_stack;
4648 free_sequence_stack = tem->next;
4651 tem = ggc_alloc (sizeof (struct sequence_stack));
4653 tem->next = seq_stack;
4654 tem->first = first_insn;
4655 tem->last = last_insn;
4663 /* Set up the insn chain starting with FIRST as the current sequence,
4664 saving the previously current one. See the documentation for
4665 start_sequence for more information about how to use this function. */
4668 push_to_sequence (rtx first)
4674 for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last));
4680 /* Like push_to_sequence, but take the last insn as an argument to avoid
4681 looping through the list. */
4684 push_to_sequence2 (rtx first, rtx last)
4692 /* Set up the outer-level insn chain
4693 as the current sequence, saving the previously current one. */
4696 push_topmost_sequence (void)
4698 struct sequence_stack *stack, *top = NULL;
4702 for (stack = seq_stack; stack; stack = stack->next)
4705 first_insn = top->first;
4706 last_insn = top->last;
4709 /* After emitting to the outer-level insn chain, update the outer-level
4710 insn chain, and restore the previous saved state. */
4713 pop_topmost_sequence (void)
4715 struct sequence_stack *stack, *top = NULL;
4717 for (stack = seq_stack; stack; stack = stack->next)
4720 top->first = first_insn;
4721 top->last = last_insn;
4726 /* After emitting to a sequence, restore previous saved state.
4728 To get the contents of the sequence just made, you must call
4729 `get_insns' *before* calling here.
4731 If the compiler might have deferred popping arguments while
4732 generating this sequence, and this sequence will not be immediately
4733 inserted into the instruction stream, use do_pending_stack_adjust
4734 before calling get_insns. That will ensure that the deferred
4735 pops are inserted into this sequence, and not into some random
4736 location in the instruction stream. See INHIBIT_DEFER_POP for more
4737 information about deferred popping of arguments. */
4742 struct sequence_stack *tem = seq_stack;
4744 first_insn = tem->first;
4745 last_insn = tem->last;
4746 seq_stack = tem->next;
4748 memset (tem, 0, sizeof (*tem));
4749 tem->next = free_sequence_stack;
4750 free_sequence_stack = tem;
4753 /* Return 1 if currently emitting into a sequence. */
4756 in_sequence_p (void)
4758 return seq_stack != 0;
4761 /* Put the various virtual registers into REGNO_REG_RTX. */
4764 init_virtual_regs (struct emit_status *es)
4766 rtx *ptr = es->x_regno_reg_rtx;
4767 ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx;
4768 ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx;
4769 ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx;
4770 ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx;
4771 ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx;
4775 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
4776 static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS];
4777 static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS];
4778 static int copy_insn_n_scratches;
4780 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
4781 copied an ASM_OPERANDS.
4782 In that case, it is the original input-operand vector. */
4783 static rtvec orig_asm_operands_vector;
4785 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
4786 copied an ASM_OPERANDS.
4787 In that case, it is the copied input-operand vector. */
4788 static rtvec copy_asm_operands_vector;
4790 /* Likewise for the constraints vector. */
4791 static rtvec orig_asm_constraints_vector;
4792 static rtvec copy_asm_constraints_vector;
4794 /* Recursively create a new copy of an rtx for copy_insn.
4795 This function differs from copy_rtx in that it handles SCRATCHes and
4796 ASM_OPERANDs properly.
4797 Normally, this function is not used directly; use copy_insn as front end.
4798 However, you could first copy an insn pattern with copy_insn and then use
4799 this function afterwards to properly copy any REG_NOTEs containing
4803 copy_insn_1 (rtx orig)
4808 const char *format_ptr;
4810 code = GET_CODE (orig);
4824 if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER)
4829 for (i = 0; i < copy_insn_n_scratches; i++)
4830 if (copy_insn_scratch_in[i] == orig)
4831 return copy_insn_scratch_out[i];
4835 if (shared_const_p (orig))
4839 /* A MEM with a constant address is not sharable. The problem is that
4840 the constant address may need to be reloaded. If the mem is shared,
4841 then reloading one copy of this mem will cause all copies to appear
4842 to have been reloaded. */
4848 /* Copy the various flags, fields, and other information. We assume
4849 that all fields need copying, and then clear the fields that should
4850 not be copied. That is the sensible default behavior, and forces
4851 us to explicitly document why we are *not* copying a flag. */
4852 copy = shallow_copy_rtx (orig);
4854 /* We do not copy the USED flag, which is used as a mark bit during
4855 walks over the RTL. */
4856 RTX_FLAG (copy, used) = 0;
4858 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
4861 RTX_FLAG (copy, jump) = 0;
4862 RTX_FLAG (copy, call) = 0;
4863 RTX_FLAG (copy, frame_related) = 0;
4866 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
4868 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
4869 switch (*format_ptr++)
4872 if (XEXP (orig, i) != NULL)
4873 XEXP (copy, i) = copy_insn_1 (XEXP (orig, i));
4878 if (XVEC (orig, i) == orig_asm_constraints_vector)
4879 XVEC (copy, i) = copy_asm_constraints_vector;
4880 else if (XVEC (orig, i) == orig_asm_operands_vector)
4881 XVEC (copy, i) = copy_asm_operands_vector;
4882 else if (XVEC (orig, i) != NULL)
4884 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
4885 for (j = 0; j < XVECLEN (copy, i); j++)
4886 XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j));
4897 /* These are left unchanged. */
4904 if (code == SCRATCH)
4906 i = copy_insn_n_scratches++;
4907 gcc_assert (i < MAX_RECOG_OPERANDS);
4908 copy_insn_scratch_in[i] = orig;
4909 copy_insn_scratch_out[i] = copy;
4911 else if (code == ASM_OPERANDS)
4913 orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig);
4914 copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy);
4915 orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig);
4916 copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy);
4922 /* Create a new copy of an rtx.
4923 This function differs from copy_rtx in that it handles SCRATCHes and
4924 ASM_OPERANDs properly.
4925 INSN doesn't really have to be a full INSN; it could be just the
4928 copy_insn (rtx insn)
4930 copy_insn_n_scratches = 0;
4931 orig_asm_operands_vector = 0;
4932 orig_asm_constraints_vector = 0;
4933 copy_asm_operands_vector = 0;
4934 copy_asm_constraints_vector = 0;
4935 return copy_insn_1 (insn);
4938 /* Initialize data structures and variables in this file
4939 before generating rtl for each function. */
4944 struct function *f = cfun;
4946 f->emit = ggc_alloc (sizeof (struct emit_status));
4950 reg_rtx_no = LAST_VIRTUAL_REGISTER + 1;
4951 last_location = UNKNOWN_LOCATION;
4952 first_label_num = label_num;
4955 /* Init the tables that describe all the pseudo regs. */
4957 f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101;
4959 f->emit->regno_pointer_align
4960 = ggc_alloc_cleared (f->emit->regno_pointer_align_length
4961 * sizeof (unsigned char));
4964 = ggc_alloc (f->emit->regno_pointer_align_length * sizeof (rtx));
4966 /* Put copies of all the hard registers into regno_reg_rtx. */
4967 memcpy (regno_reg_rtx,
4968 static_regno_reg_rtx,
4969 FIRST_PSEUDO_REGISTER * sizeof (rtx));
4971 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
4972 init_virtual_regs (f->emit);
4974 /* Indicate that the virtual registers and stack locations are
4976 REG_POINTER (stack_pointer_rtx) = 1;
4977 REG_POINTER (frame_pointer_rtx) = 1;
4978 REG_POINTER (hard_frame_pointer_rtx) = 1;
4979 REG_POINTER (arg_pointer_rtx) = 1;
4981 REG_POINTER (virtual_incoming_args_rtx) = 1;
4982 REG_POINTER (virtual_stack_vars_rtx) = 1;
4983 REG_POINTER (virtual_stack_dynamic_rtx) = 1;
4984 REG_POINTER (virtual_outgoing_args_rtx) = 1;
4985 REG_POINTER (virtual_cfa_rtx) = 1;
4987 #ifdef STACK_BOUNDARY
4988 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY;
4989 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
4990 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
4991 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY;
4993 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY;
4994 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY;
4995 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY;
4996 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY;
4997 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD;
5000 #ifdef INIT_EXPANDERS
5005 /* Generate a vector constant for mode MODE and constant value CONSTANT. */
5008 gen_const_vector (enum machine_mode mode, int constant)
5013 enum machine_mode inner;
5015 units = GET_MODE_NUNITS (mode);
5016 inner = GET_MODE_INNER (mode);
5018 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner));
5020 v = rtvec_alloc (units);
5022 /* We need to call this function after we set the scalar const_tiny_rtx
5024 gcc_assert (const_tiny_rtx[constant][(int) inner]);
5026 for (i = 0; i < units; ++i)
5027 RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner];
5029 tem = gen_rtx_raw_CONST_VECTOR (mode, v);
5033 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
5034 all elements are zero, and the one vector when all elements are one. */
5036 gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v)
5038 enum machine_mode inner = GET_MODE_INNER (mode);
5039 int nunits = GET_MODE_NUNITS (mode);
5043 /* Check to see if all of the elements have the same value. */
5044 x = RTVEC_ELT (v, nunits - 1);
5045 for (i = nunits - 2; i >= 0; i--)
5046 if (RTVEC_ELT (v, i) != x)
5049 /* If the values are all the same, check to see if we can use one of the
5050 standard constant vectors. */
5053 if (x == CONST0_RTX (inner))
5054 return CONST0_RTX (mode);
5055 else if (x == CONST1_RTX (inner))
5056 return CONST1_RTX (mode);
5059 return gen_rtx_raw_CONST_VECTOR (mode, v);
5062 /* Create some permanent unique rtl objects shared between all functions.
5063 LINE_NUMBERS is nonzero if line numbers are to be generated. */
5066 init_emit_once (int line_numbers)
5069 enum machine_mode mode;
5070 enum machine_mode double_mode;
5072 /* We need reg_raw_mode, so initialize the modes now. */
5073 init_reg_modes_once ();
5075 /* Initialize the CONST_INT, CONST_DOUBLE, and memory attribute hash
5077 const_int_htab = htab_create_ggc (37, const_int_htab_hash,
5078 const_int_htab_eq, NULL);
5080 const_double_htab = htab_create_ggc (37, const_double_htab_hash,
5081 const_double_htab_eq, NULL);
5083 mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash,
5084 mem_attrs_htab_eq, NULL);
5085 reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash,
5086 reg_attrs_htab_eq, NULL);
5088 no_line_numbers = ! line_numbers;
5090 /* Compute the word and byte modes. */
5092 byte_mode = VOIDmode;
5093 word_mode = VOIDmode;
5094 double_mode = VOIDmode;
5096 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
5098 mode = GET_MODE_WIDER_MODE (mode))
5100 if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT
5101 && byte_mode == VOIDmode)
5104 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD
5105 && word_mode == VOIDmode)
5109 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
5111 mode = GET_MODE_WIDER_MODE (mode))
5113 if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE
5114 && double_mode == VOIDmode)
5118 ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0);
5120 /* Assign register numbers to the globally defined register rtx.
5121 This must be done at runtime because the register number field
5122 is in a union and some compilers can't initialize unions. */
5124 pc_rtx = gen_rtx_PC (VOIDmode);
5125 cc0_rtx = gen_rtx_CC0 (VOIDmode);
5126 stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM);
5127 frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM);
5128 if (hard_frame_pointer_rtx == 0)
5129 hard_frame_pointer_rtx = gen_raw_REG (Pmode,
5130 HARD_FRAME_POINTER_REGNUM);
5131 if (arg_pointer_rtx == 0)
5132 arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM);
5133 virtual_incoming_args_rtx =
5134 gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM);
5135 virtual_stack_vars_rtx =
5136 gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM);
5137 virtual_stack_dynamic_rtx =
5138 gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM);
5139 virtual_outgoing_args_rtx =
5140 gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM);
5141 virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM);
5143 /* Initialize RTL for commonly used hard registers. These are
5144 copied into regno_reg_rtx as we begin to compile each function. */
5145 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5146 static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i);
5148 #ifdef INIT_EXPANDERS
5149 /* This is to initialize {init|mark|free}_machine_status before the first
5150 call to push_function_context_to. This is needed by the Chill front
5151 end which calls push_function_context_to before the first call to
5152 init_function_start. */
5156 /* Create the unique rtx's for certain rtx codes and operand values. */
5158 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
5159 tries to use these variables. */
5160 for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++)
5161 const_int_rtx[i + MAX_SAVED_CONST_INT] =
5162 gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i);
5164 if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT
5165 && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT)
5166 const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT];
5168 const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE);
5170 REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode);
5171 REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode);
5172 REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode);
5173 REAL_VALUE_FROM_INT (dconst3, 3, 0, double_mode);
5174 REAL_VALUE_FROM_INT (dconst10, 10, 0, double_mode);
5175 REAL_VALUE_FROM_INT (dconstm1, -1, -1, double_mode);
5176 REAL_VALUE_FROM_INT (dconstm2, -2, -1, double_mode);
5178 dconsthalf = dconst1;
5179 SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1);
5181 real_arithmetic (&dconstthird, RDIV_EXPR, &dconst1, &dconst3);
5183 /* Initialize mathematical constants for constant folding builtins.
5184 These constants need to be given to at least 160 bits precision. */
5185 real_from_string (&dconstsqrt2,
5186 "1.4142135623730950488016887242096980785696718753769480731766797379907");
5187 real_from_string (&dconste,
5188 "2.7182818284590452353602874713526624977572470936999595749669676277241");
5190 for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++)
5192 REAL_VALUE_TYPE *r =
5193 (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2);
5195 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
5197 mode = GET_MODE_WIDER_MODE (mode))
5198 const_tiny_rtx[i][(int) mode] =
5199 CONST_DOUBLE_FROM_REAL_VALUE (*r, mode);
5201 for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT);
5203 mode = GET_MODE_WIDER_MODE (mode))
5204 const_tiny_rtx[i][(int) mode] =
5205 CONST_DOUBLE_FROM_REAL_VALUE (*r, mode);
5207 const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i);
5209 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
5211 mode = GET_MODE_WIDER_MODE (mode))
5212 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
5214 for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT);
5216 mode = GET_MODE_WIDER_MODE (mode))
5217 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
5220 for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT);
5222 mode = GET_MODE_WIDER_MODE (mode))
5224 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
5225 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
5228 for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT);
5230 mode = GET_MODE_WIDER_MODE (mode))
5232 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
5233 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
5236 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
5238 mode = GET_MODE_WIDER_MODE (mode))
5240 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5241 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5244 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
5246 mode = GET_MODE_WIDER_MODE (mode))
5248 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5249 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5252 for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i)
5253 if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC)
5254 const_tiny_rtx[0][i] = const0_rtx;
5256 const_tiny_rtx[0][(int) BImode] = const0_rtx;
5257 if (STORE_FLAG_VALUE == 1)
5258 const_tiny_rtx[1][(int) BImode] = const1_rtx;
5260 #ifdef RETURN_ADDRESS_POINTER_REGNUM
5261 return_address_pointer_rtx
5262 = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM);
5265 #ifdef STATIC_CHAIN_REGNUM
5266 static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
5268 #ifdef STATIC_CHAIN_INCOMING_REGNUM
5269 if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM)
5270 static_chain_incoming_rtx
5271 = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM);
5274 static_chain_incoming_rtx = static_chain_rtx;
5278 static_chain_rtx = STATIC_CHAIN;
5280 #ifdef STATIC_CHAIN_INCOMING
5281 static_chain_incoming_rtx = STATIC_CHAIN_INCOMING;
5283 static_chain_incoming_rtx = static_chain_rtx;
5287 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
5288 pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
5291 /* Produce exact duplicate of insn INSN after AFTER.
5292 Care updating of libcall regions if present. */
5295 emit_copy_of_insn_after (rtx insn, rtx after)
5298 rtx note1, note2, link;
5300 switch (GET_CODE (insn))
5303 new = emit_insn_after (copy_insn (PATTERN (insn)), after);
5307 new = emit_jump_insn_after (copy_insn (PATTERN (insn)), after);
5311 new = emit_call_insn_after (copy_insn (PATTERN (insn)), after);
5312 if (CALL_INSN_FUNCTION_USAGE (insn))
5313 CALL_INSN_FUNCTION_USAGE (new)
5314 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn));
5315 SIBLING_CALL_P (new) = SIBLING_CALL_P (insn);
5316 CONST_OR_PURE_CALL_P (new) = CONST_OR_PURE_CALL_P (insn);
5323 /* Update LABEL_NUSES. */
5324 mark_jump_label (PATTERN (new), new, 0);
5326 INSN_LOCATOR (new) = INSN_LOCATOR (insn);
5328 /* If the old insn is frame related, then so is the new one. This is
5329 primarily needed for IA-64 unwind info which marks epilogue insns,
5330 which may be duplicated by the basic block reordering code. */
5331 RTX_FRAME_RELATED_P (new) = RTX_FRAME_RELATED_P (insn);
5333 /* Copy all REG_NOTES except REG_LABEL since mark_jump_label will
5335 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
5336 if (REG_NOTE_KIND (link) != REG_LABEL)
5338 if (GET_CODE (link) == EXPR_LIST)
5340 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link),
5341 copy_insn_1 (XEXP (link, 0)), REG_NOTES (new));
5344 = gen_rtx_INSN_LIST (REG_NOTE_KIND (link),
5345 XEXP (link, 0), REG_NOTES (new));
5348 /* Fix the libcall sequences. */
5349 if ((note1 = find_reg_note (new, REG_RETVAL, NULL_RTX)) != NULL)
5352 while ((note2 = find_reg_note (p, REG_LIBCALL, NULL_RTX)) == NULL)
5354 XEXP (note1, 0) = p;
5355 XEXP (note2, 0) = new;
5357 INSN_CODE (new) = INSN_CODE (insn);
5361 static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
5363 gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno)
5365 if (hard_reg_clobbers[mode][regno])
5366 return hard_reg_clobbers[mode][regno];
5368 return (hard_reg_clobbers[mode][regno] =
5369 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno)));
5372 #include "gt-emit-rtl.h"