1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
49 #include "target-def.h"
50 #include "langhooks.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Cached operands, and operator to compare for use in set/branch on
78 /* what type of branch to use */
79 enum cmp_type branch_type;
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
85 /* Current frame size calculated by compute_frame_size. */
86 unsigned xtensa_current_frame_size;
88 /* Largest block move to handle in-line. */
89 #define LARGEST_MOVE_RATIO 15
91 /* Define the structure for the machine field in struct function. */
92 struct machine_function GTY(())
94 int accesses_prev_frame;
98 rtx set_frame_ptr_insn;
101 /* Vector, indexed by hard register number, which contains 1 for a
102 register that is allowable in a candidate for leaf function
105 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
107 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
113 /* Map hard register number to register class */
114 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
116 RL_REGS, SP_REG, RL_REGS, RL_REGS,
117 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
118 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
119 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
120 AR_REGS, AR_REGS, BR_REGS,
121 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
122 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
123 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
124 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 static enum internal_test map_test_to_internal_test (enum rtx_code);
129 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
130 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
131 static rtx gen_conditional_move (rtx);
132 static rtx fixup_subreg_mem (rtx);
133 static struct machine_function * xtensa_init_machine_status (void);
134 static bool xtensa_return_in_msb (const_tree);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
137 static rtx xtensa_builtin_saveregs (void);
138 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
139 int) ATTRIBUTE_UNUSED;
140 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
141 unsigned HOST_WIDE_INT);
142 static bool xtensa_rtx_costs (rtx, int, int, int *, bool);
143 static tree xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree, const_tree);
145 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
147 static rtx xtensa_function_value (const_tree, const_tree, bool);
148 static void xtensa_init_builtins (void);
149 static tree xtensa_fold_builtin (tree, tree, bool);
150 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
151 static void xtensa_va_start (tree, rtx);
153 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
157 /* This macro generates the assembly code for function exit,
158 on machines that need it. If FUNCTION_EPILOGUE is not defined
159 then individual return instructions are generated for each
160 return statement. Args are same as for FUNCTION_PROLOGUE. */
162 #undef TARGET_ASM_FUNCTION_EPILOGUE
163 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
165 /* These hooks specify assembly directives for creating certain kinds
166 of integer object. */
168 #undef TARGET_ASM_ALIGNED_SI_OP
169 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
171 #undef TARGET_ASM_SELECT_RTX_SECTION
172 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
174 #undef TARGET_DEFAULT_TARGET_FLAGS
175 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS xtensa_rtx_costs
179 #undef TARGET_ADDRESS_COST
180 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
182 #undef TARGET_BUILD_BUILTIN_VA_LIST
183 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
185 #undef TARGET_EXPAND_BUILTIN_VA_START
186 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
188 #undef TARGET_PROMOTE_FUNCTION_ARGS
189 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
190 #undef TARGET_PROMOTE_FUNCTION_RETURN
191 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
192 #undef TARGET_PROMOTE_PROTOTYPES
193 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
195 #undef TARGET_RETURN_IN_MEMORY
196 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
197 #undef TARGET_FUNCTION_VALUE
198 #define TARGET_FUNCTION_VALUE xtensa_function_value
199 #undef TARGET_SPLIT_COMPLEX_ARG
200 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
201 #undef TARGET_MUST_PASS_IN_STACK
202 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
204 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
205 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
206 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
207 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
209 #undef TARGET_RETURN_IN_MSB
210 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
212 #undef TARGET_INIT_BUILTINS
213 #define TARGET_INIT_BUILTINS xtensa_init_builtins
214 #undef TARGET_FOLD_BUILTIN
215 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
216 #undef TARGET_EXPAND_BUILTIN
217 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
219 struct gcc_target targetm = TARGET_INITIALIZER;
222 /* Functions to test Xtensa immediate operand validity. */
225 xtensa_simm8 (HOST_WIDE_INT v)
227 return v >= -128 && v <= 127;
232 xtensa_simm8x256 (HOST_WIDE_INT v)
234 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
239 xtensa_simm12b (HOST_WIDE_INT v)
241 return v >= -2048 && v <= 2047;
246 xtensa_uimm8 (HOST_WIDE_INT v)
248 return v >= 0 && v <= 255;
253 xtensa_uimm8x2 (HOST_WIDE_INT v)
255 return (v & 1) == 0 && (v >= 0 && v <= 510);
260 xtensa_uimm8x4 (HOST_WIDE_INT v)
262 return (v & 3) == 0 && (v >= 0 && v <= 1020);
267 xtensa_b4const (HOST_WIDE_INT v)
294 xtensa_b4const_or_zero (HOST_WIDE_INT v)
298 return xtensa_b4const (v);
303 xtensa_b4constu (HOST_WIDE_INT v)
330 xtensa_mask_immediate (HOST_WIDE_INT v)
332 #define MAX_MASK_SIZE 16
335 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
348 /* This is just like the standard true_regnum() function except that it
349 works even when reg_renumber is not initialized. */
352 xt_true_regnum (rtx x)
354 if (GET_CODE (x) == REG)
357 && REGNO (x) >= FIRST_PSEUDO_REGISTER
358 && reg_renumber[REGNO (x)] >= 0)
359 return reg_renumber[REGNO (x)];
362 if (GET_CODE (x) == SUBREG)
364 int base = xt_true_regnum (SUBREG_REG (x));
365 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
366 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
367 GET_MODE (SUBREG_REG (x)),
368 SUBREG_BYTE (x), GET_MODE (x));
375 xtensa_valid_move (enum machine_mode mode, rtx *operands)
377 /* Either the destination or source must be a register, and the
378 MAC16 accumulator doesn't count. */
380 if (register_operand (operands[0], mode))
382 int dst_regnum = xt_true_regnum (operands[0]);
384 /* The stack pointer can only be assigned with a MOVSP opcode. */
385 if (dst_regnum == STACK_POINTER_REGNUM)
386 return (mode == SImode
387 && register_operand (operands[1], mode)
388 && !ACC_REG_P (xt_true_regnum (operands[1])));
390 if (!ACC_REG_P (dst_regnum))
393 if (register_operand (operands[1], mode))
395 int src_regnum = xt_true_regnum (operands[1]);
396 if (!ACC_REG_P (src_regnum))
404 smalloffset_mem_p (rtx op)
406 if (GET_CODE (op) == MEM)
408 rtx addr = XEXP (op, 0);
409 if (GET_CODE (addr) == REG)
410 return BASE_REG_P (addr, 0);
411 if (GET_CODE (addr) == PLUS)
413 rtx offset = XEXP (addr, 0);
415 if (GET_CODE (offset) != CONST_INT)
416 offset = XEXP (addr, 1);
417 if (GET_CODE (offset) != CONST_INT)
420 val = INTVAL (offset);
421 return (val & 3) == 0 && (val >= 0 && val <= 60);
429 constantpool_address_p (rtx addr)
433 if (GET_CODE (addr) == CONST)
437 /* Only handle (PLUS (SYM, OFFSET)) form. */
438 addr = XEXP (addr, 0);
439 if (GET_CODE (addr) != PLUS)
442 /* Make sure the address is word aligned. */
443 offset = XEXP (addr, 1);
444 if ((GET_CODE (offset) != CONST_INT)
445 || ((INTVAL (offset) & 3) != 0))
448 sym = XEXP (addr, 0);
451 if ((GET_CODE (sym) == SYMBOL_REF)
452 && CONSTANT_POOL_ADDRESS_P (sym))
459 constantpool_mem_p (rtx op)
461 if (GET_CODE (op) == SUBREG)
462 op = SUBREG_REG (op);
463 if (GET_CODE (op) == MEM)
464 return constantpool_address_p (XEXP (op, 0));
470 xtensa_extend_reg (rtx dst, rtx src)
472 rtx temp = gen_reg_rtx (SImode);
473 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
475 /* Generate paradoxical subregs as needed so that the modes match. */
476 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
477 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
479 emit_insn (gen_ashlsi3 (temp, src, shift));
480 emit_insn (gen_ashrsi3 (dst, temp, shift));
485 xtensa_mem_offset (unsigned v, enum machine_mode mode)
490 /* Handle the worst case for block moves. See xtensa_expand_block_move
491 where we emit an optimized block move operation if the block can be
492 moved in < "move_ratio" pieces. The worst case is when the block is
493 aligned but has a size of (3 mod 4) (does this happen?) so that the
494 last piece requires a byte load/store. */
495 return (xtensa_uimm8 (v)
496 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
499 return xtensa_uimm8 (v);
502 return xtensa_uimm8x2 (v);
505 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
511 return xtensa_uimm8x4 (v);
515 /* Make normal rtx_code into something we can index from an array. */
517 static enum internal_test
518 map_test_to_internal_test (enum rtx_code test_code)
520 enum internal_test test = ITEST_MAX;
525 case EQ: test = ITEST_EQ; break;
526 case NE: test = ITEST_NE; break;
527 case GT: test = ITEST_GT; break;
528 case GE: test = ITEST_GE; break;
529 case LT: test = ITEST_LT; break;
530 case LE: test = ITEST_LE; break;
531 case GTU: test = ITEST_GTU; break;
532 case GEU: test = ITEST_GEU; break;
533 case LTU: test = ITEST_LTU; break;
534 case LEU: test = ITEST_LEU; break;
541 /* Generate the code to compare two integer values. The return value is
542 the comparison expression. */
545 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
546 rtx cmp0, /* first operand to compare */
547 rtx cmp1, /* second operand to compare */
548 int *p_invert /* whether branch needs to reverse test */)
552 enum rtx_code test_code; /* test code to use in insn */
553 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
554 int const_add; /* constant to add (convert LE -> LT) */
555 int reverse_regs; /* reverse registers in test */
556 int invert_const; /* != 0 if invert value if cmp1 is constant */
557 int invert_reg; /* != 0 if invert value if cmp1 is register */
558 int unsignedp; /* != 0 for unsigned comparisons. */
561 static struct cmp_info info[ (int)ITEST_MAX ] = {
563 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
564 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
566 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
567 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
568 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
569 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
571 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
572 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
573 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
574 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
577 enum internal_test test;
578 enum machine_mode mode;
579 struct cmp_info *p_info;
581 test = map_test_to_internal_test (test_code);
582 gcc_assert (test != ITEST_MAX);
584 p_info = &info[ (int)test ];
586 mode = GET_MODE (cmp0);
587 if (mode == VOIDmode)
588 mode = GET_MODE (cmp1);
590 /* Make sure we can handle any constants given to us. */
591 if (GET_CODE (cmp1) == CONST_INT)
593 HOST_WIDE_INT value = INTVAL (cmp1);
594 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
596 /* if the immediate overflows or does not fit in the immediate field,
597 spill it to a register */
599 if ((p_info->unsignedp ?
600 (uvalue + p_info->const_add > uvalue) :
601 (value + p_info->const_add > value)) != (p_info->const_add > 0))
603 cmp1 = force_reg (mode, cmp1);
605 else if (!(p_info->const_range_p) (value + p_info->const_add))
607 cmp1 = force_reg (mode, cmp1);
610 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
612 cmp1 = force_reg (mode, cmp1);
615 /* See if we need to invert the result. */
616 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
617 ? p_info->invert_const
618 : p_info->invert_reg);
620 /* Comparison to constants, may involve adding 1 to change a LT into LE.
621 Comparison between two registers, may involve switching operands. */
622 if (GET_CODE (cmp1) == CONST_INT)
624 if (p_info->const_add != 0)
625 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
628 else if (p_info->reverse_regs)
635 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
639 /* Generate the code to compare two float values. The return value is
640 the comparison expression. */
643 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
644 rtx cmp0, /* first operand to compare */
645 rtx cmp1 /* second operand to compare */)
647 rtx (*gen_fn) (rtx, rtx, rtx);
649 int reverse_regs, invert;
653 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
654 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
655 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
656 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
657 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
658 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
659 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
660 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
661 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
662 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
663 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
664 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
666 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
668 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
670 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
671 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
681 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
682 emit_insn (gen_fn (brtmp, cmp0, cmp1));
684 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
689 xtensa_expand_conditional_branch (rtx *operands, enum rtx_code test_code)
691 enum cmp_type type = branch_type;
692 rtx cmp0 = branch_cmp[0];
693 rtx cmp1 = branch_cmp[1];
702 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
706 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
710 if (!TARGET_HARD_FLOAT)
711 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
714 cmp = gen_float_relational (test_code, cmp0, cmp1);
718 /* Generate the branch. */
720 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
729 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
730 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
737 gen_conditional_move (rtx cmp)
739 enum rtx_code code = GET_CODE (cmp);
740 rtx op0 = branch_cmp[0];
741 rtx op1 = branch_cmp[1];
743 if (branch_type == CMP_SI)
745 /* Jump optimization calls get_condition() which canonicalizes
746 comparisons like (GE x <const>) to (GT x <const-1>).
747 Transform those comparisons back to GE, since that is the
748 comparison supported in Xtensa. We shouldn't have to
749 transform <LE x const> comparisons, because neither
750 xtensa_expand_conditional_branch() nor get_condition() will
753 if ((code == GT) && (op1 == constm1_rtx))
758 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
760 if (boolean_operator (cmp, VOIDmode))
762 /* Swap the operands to make const0 second. */
763 if (op0 == const0_rtx)
769 /* If not comparing against zero, emit a comparison (subtract). */
770 if (op1 != const0_rtx)
772 op0 = expand_binop (SImode, sub_optab, op0, op1,
773 0, 0, OPTAB_LIB_WIDEN);
777 else if (branch_operator (cmp, VOIDmode))
779 /* Swap the operands to make const0 second. */
780 if (op0 == const0_rtx)
787 case LT: code = GE; break;
788 case GE: code = LT; break;
789 default: gcc_unreachable ();
793 if (op1 != const0_rtx)
799 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
802 if (TARGET_HARD_FLOAT && (branch_type == CMP_SF))
803 return gen_float_relational (code, op0, op1);
810 xtensa_expand_conditional_move (rtx *operands, int isflt)
813 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
815 if (!(cmp = gen_conditional_move (operands[1])))
819 gen_fn = (branch_type == CMP_SI
820 ? gen_movsfcc_internal0
821 : gen_movsfcc_internal1);
823 gen_fn = (branch_type == CMP_SI
824 ? gen_movsicc_internal0
825 : gen_movsicc_internal1);
827 emit_insn (gen_fn (operands[0], XEXP (cmp, 0),
828 operands[2], operands[3], cmp));
834 xtensa_expand_scc (rtx *operands)
836 rtx dest = operands[0];
837 rtx cmp = operands[1];
838 rtx one_tmp, zero_tmp;
839 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
841 if (!(cmp = gen_conditional_move (cmp)))
844 one_tmp = gen_reg_rtx (SImode);
845 zero_tmp = gen_reg_rtx (SImode);
846 emit_insn (gen_movsi (one_tmp, const_true_rtx));
847 emit_insn (gen_movsi (zero_tmp, const0_rtx));
849 gen_fn = (branch_type == CMP_SI
850 ? gen_movsicc_internal0
851 : gen_movsicc_internal1);
852 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
857 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
858 for the output, i.e., the input operands are twice as big as MODE. */
861 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
863 switch (GET_CODE (operands[1]))
866 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
867 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
871 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
872 operands[2] = adjust_address (operands[1], mode, 0);
877 split_double (operands[1], &operands[2], &operands[3]);
884 switch (GET_CODE (operands[0]))
887 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
888 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
892 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
893 operands[0] = adjust_address (operands[0], mode, 0);
902 /* Emit insns to move operands[1] into operands[0].
903 Return 1 if we have written out everything that needs to be done to
904 do the move. Otherwise, return 0 and the caller will emit the move
908 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
910 if (CONSTANT_P (operands[1])
911 && (GET_CODE (operands[1]) != CONST_INT
912 || !xtensa_simm12b (INTVAL (operands[1]))))
915 operands[1] = force_const_mem (SImode, operands[1]);
917 /* PC-relative loads are always SImode, and CONST16 is only
918 supported in the movsi pattern, so add a SUBREG for any other
923 if (register_operand (operands[0], mode))
925 operands[0] = simplify_gen_subreg (SImode, operands[0], mode, 0);
926 emit_move_insn (operands[0], operands[1]);
931 operands[1] = force_reg (SImode, operands[1]);
932 operands[1] = gen_lowpart_SUBREG (mode, operands[1]);
937 if (!(reload_in_progress | reload_completed)
938 && !xtensa_valid_move (mode, operands))
939 operands[1] = force_reg (mode, operands[1]);
941 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
943 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
944 instruction won't be recognized after reload, so we remove the
945 subreg and adjust mem accordingly. */
946 if (reload_in_progress)
948 operands[0] = fixup_subreg_mem (operands[0]);
949 operands[1] = fixup_subreg_mem (operands[1]);
956 fixup_subreg_mem (rtx x)
958 if (GET_CODE (x) == SUBREG
959 && GET_CODE (SUBREG_REG (x)) == REG
960 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
963 gen_rtx_SUBREG (GET_MODE (x),
964 reg_equiv_mem [REGNO (SUBREG_REG (x))],
966 x = alter_subreg (&temp);
972 /* Check if an incoming argument in a7 is expected to be used soon and
973 if OPND is a register or register pair that includes a7. If so,
974 create a new pseudo and copy a7 into that pseudo at the very
975 beginning of the function, followed by the special "set_frame_ptr"
976 unspec_volatile insn. The return value is either the original
977 operand, if it is not a7, or the new pseudo containing a copy of
978 the incoming argument. This is necessary because the register
979 allocator will ignore conflicts with a7 and may either assign some
980 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
981 the incoming argument in a7. By copying the argument out of a7 as
982 the very first thing, and then immediately following that with an
983 unspec_volatile to keep the scheduler away, we should avoid any
984 problems. Putting the set_frame_ptr insn at the beginning, with
985 only the a7 copy before it, also makes it easier for the prologue
986 expander to initialize the frame pointer after the a7 copy and to
987 fix up the a7 copy to use the stack pointer instead of the frame
991 xtensa_copy_incoming_a7 (rtx opnd)
995 enum machine_mode mode;
997 if (!cfun->machine->need_a7_copy)
1000 /* This function should never be called again once a7 has been copied. */
1001 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1003 mode = GET_MODE (opnd);
1005 /* The operand using a7 may come in a later instruction, so just return
1006 the original operand if it doesn't use a7. */
1008 if (GET_CODE (reg) == SUBREG)
1010 gcc_assert (SUBREG_BYTE (reg) == 0);
1011 reg = SUBREG_REG (reg);
1013 if (GET_CODE (reg) != REG
1014 || REGNO (reg) > A7_REG
1015 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1018 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1019 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1021 cfun->machine->need_a7_copy = false;
1023 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1024 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1027 tmp = gen_reg_rtx (mode);
1033 /* Copy the value out of A7 here but keep the first word in A6 until
1034 after the set_frame_ptr insn. Otherwise, the register allocator
1035 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1037 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1038 gen_raw_REG (SImode, A7_REG)));
1041 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1044 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1047 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1050 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1056 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1058 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1059 if (mode == DFmode || mode == DImode)
1060 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1061 gen_rtx_REG (SImode, A7_REG - 1)));
1062 entry_insns = get_insns ();
1065 if (cfun->machine->vararg_a7)
1067 /* This is called from within builtin_saveregs, which will insert the
1068 saveregs code at the function entry, ahead of anything placed at
1069 the function entry now. Instead, save the sequence to be inserted
1070 at the beginning of the saveregs code. */
1071 cfun->machine->vararg_a7_copy = entry_insns;
1075 /* Put entry_insns after the NOTE that starts the function. If
1076 this is inside a start_sequence, make the outer-level insn
1077 chain current, so the code is placed at the start of the
1079 push_topmost_sequence ();
1080 /* Do not use entry_of_function() here. This is called from within
1081 expand_function_start, when the CFG still holds GIMPLE. */
1082 emit_insn_after (entry_insns, get_insns ());
1083 pop_topmost_sequence ();
1090 /* Try to expand a block move operation to a sequence of RTL move
1091 instructions. If not optimizing, or if the block size is not a
1092 constant, or if the block is too large, the expansion fails and GCC
1093 falls back to calling memcpy().
1095 operands[0] is the destination
1096 operands[1] is the source
1097 operands[2] is the length
1098 operands[3] is the alignment */
1101 xtensa_expand_block_move (rtx *operands)
1103 static const enum machine_mode mode_from_align[] =
1105 VOIDmode, QImode, HImode, VOIDmode, SImode,
1108 rtx dst_mem = operands[0];
1109 rtx src_mem = operands[1];
1110 HOST_WIDE_INT bytes, align;
1111 int num_pieces, move_ratio;
1113 enum machine_mode mode[2];
1122 /* If this is not a fixed size move, just call memcpy. */
1123 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1126 bytes = INTVAL (operands[2]);
1127 align = INTVAL (operands[3]);
1129 /* Anything to move? */
1133 if (align > MOVE_MAX)
1136 /* Decide whether to expand inline based on the optimization level. */
1139 move_ratio = LARGEST_MOVE_RATIO;
1140 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1141 if (num_pieces > move_ratio)
1144 x = XEXP (dst_mem, 0);
1147 x = force_reg (Pmode, x);
1148 dst_mem = replace_equiv_address (dst_mem, x);
1151 x = XEXP (src_mem, 0);
1154 x = force_reg (Pmode, x);
1155 src_mem = replace_equiv_address (src_mem, x);
1158 active[0] = active[1] = false;
1169 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1170 next_amount = MIN (next_amount, align);
1172 amount[next] = next_amount;
1173 mode[next] = mode_from_align[next_amount];
1174 temp[next] = gen_reg_rtx (mode[next]);
1176 x = adjust_address (src_mem, mode[next], offset_ld);
1177 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1179 offset_ld += next_amount;
1180 bytes -= next_amount;
1181 active[next] = true;
1186 active[phase] = false;
1188 x = adjust_address (dst_mem, mode[phase], offset_st);
1189 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1191 offset_st += amount[phase];
1194 while (active[next]);
1201 xtensa_expand_nonlocal_goto (rtx *operands)
1203 rtx goto_handler = operands[1];
1204 rtx containing_fp = operands[3];
1206 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1207 is too big to generate in-line. */
1209 if (GET_CODE (containing_fp) != REG)
1210 containing_fp = force_reg (Pmode, containing_fp);
1212 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1214 containing_fp, Pmode,
1215 goto_handler, Pmode);
1219 static struct machine_function *
1220 xtensa_init_machine_status (void)
1222 return GGC_CNEW (struct machine_function);
1226 /* Shift VAL of mode MODE left by COUNT bits. */
1229 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1231 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1232 NULL_RTX, 1, OPTAB_DIRECT);
1233 return expand_simple_binop (SImode, ASHIFT, val, count,
1234 NULL_RTX, 1, OPTAB_DIRECT);
1238 /* Structure to hold the initial parameters for a compare_and_swap operation
1239 in HImode and QImode. */
1241 struct alignment_context
1243 rtx memsi; /* SI aligned memory location. */
1244 rtx shift; /* Bit offset with regard to lsb. */
1245 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1246 rtx modemaski; /* ~modemask */
1250 /* Initialize structure AC for word access to HI and QI mode memory. */
1253 init_alignment_context (struct alignment_context *ac, rtx mem)
1255 enum machine_mode mode = GET_MODE (mem);
1256 rtx byteoffset = NULL_RTX;
1257 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1260 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1263 /* Alignment is unknown. */
1266 /* Force the address into a register. */
1267 addr = force_reg (Pmode, XEXP (mem, 0));
1269 /* Align it to SImode. */
1270 align = expand_simple_binop (Pmode, AND, addr,
1271 GEN_INT (-GET_MODE_SIZE (SImode)),
1272 NULL_RTX, 1, OPTAB_DIRECT);
1274 ac->memsi = gen_rtx_MEM (SImode, align);
1275 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1276 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1277 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1279 byteoffset = expand_simple_binop (Pmode, AND, addr,
1280 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1281 NULL_RTX, 1, OPTAB_DIRECT);
1284 /* Calculate shiftcount. */
1285 if (TARGET_BIG_ENDIAN)
1287 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1289 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1290 NULL_RTX, 1, OPTAB_DIRECT);
1295 ac->shift = NULL_RTX;
1297 ac->shift = byteoffset;
1300 if (ac->shift != NULL_RTX)
1302 /* Shift is the byte count, but we need the bitcount. */
1303 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1304 GEN_INT (BITS_PER_UNIT),
1305 NULL_RTX, 1, OPTAB_DIRECT);
1306 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1307 GEN_INT (GET_MODE_MASK (mode)),
1309 NULL_RTX, 1, OPTAB_DIRECT);
1312 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1314 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1318 /* Expand an atomic compare and swap operation for HImode and QImode.
1319 MEM is the memory location, CMP the old value to compare MEM with
1320 and NEW_RTX the value to set if CMP == MEM. */
1323 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx)
1325 enum machine_mode mode = GET_MODE (mem);
1326 struct alignment_context ac;
1327 rtx tmp, cmpv, newv, val;
1328 rtx oldval = gen_reg_rtx (SImode);
1329 rtx res = gen_reg_rtx (SImode);
1330 rtx csloop = gen_label_rtx ();
1331 rtx csend = gen_label_rtx ();
1333 init_alignment_context (&ac, mem);
1335 if (ac.shift != NULL_RTX)
1337 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1338 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift);
1341 /* Load the surrounding word into VAL with the MEM value masked out. */
1342 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1343 ac.modemaski, NULL_RTX, 1,
1345 emit_label (csloop);
1347 /* Patch CMP and NEW_RTX into VAL at correct position. */
1348 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1349 NULL_RTX, 1, OPTAB_DIRECT));
1350 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
1351 NULL_RTX, 1, OPTAB_DIRECT));
1353 /* Jump to end if we're done. */
1354 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1355 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1357 /* Check for changes outside mode. */
1358 emit_move_insn (oldval, val);
1359 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1360 val, 1, OPTAB_DIRECT);
1362 emit_move_insn (val, tmp);
1364 /* Loop internal if so. */
1365 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1369 /* Return the correct part of the bitfield. */
1370 convert_move (target,
1371 (ac.shift == NULL_RTX ? res
1372 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1373 NULL_RTX, 1, OPTAB_DIRECT)),
1378 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1379 the default expansion works fine for SImode). MEM is the memory location
1380 and VAL the value to play with. If AFTER is true then store the value
1381 MEM holds after the operation, if AFTER is false then store the value MEM
1382 holds before the operation. If TARGET is zero then discard that value, else
1383 store it to TARGET. */
1386 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1389 enum machine_mode mode = GET_MODE (mem);
1390 struct alignment_context ac;
1391 rtx csloop = gen_label_rtx ();
1393 rtx old = gen_reg_rtx (SImode);
1394 rtx new_rtx = gen_reg_rtx (SImode);
1395 rtx orig = NULL_RTX;
1397 init_alignment_context (&ac, mem);
1399 /* Prepare values before the compare-and-swap loop. */
1400 if (ac.shift != NULL_RTX)
1401 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1406 orig = gen_reg_rtx (SImode);
1407 convert_move (orig, val, 1);
1415 case MULT: /* NAND */
1417 /* val = "11..1<val>11..1" */
1418 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1419 NULL_RTX, 1, OPTAB_DIRECT);
1426 /* Load full word. Subsequent loads are performed by S32C1I. */
1427 cmp = force_reg (SImode, ac.memsi);
1429 emit_label (csloop);
1430 emit_move_insn (old, cmp);
1436 val = expand_simple_binop (SImode, code, old, orig,
1437 NULL_RTX, 1, OPTAB_DIRECT);
1438 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1439 NULL_RTX, 1, OPTAB_DIRECT);
1442 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1443 NULL_RTX, 1, OPTAB_DIRECT);
1444 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1445 new_rtx, 1, OPTAB_DIRECT);
1451 tmp = expand_simple_binop (SImode, code, old, val,
1452 new_rtx, 1, OPTAB_DIRECT);
1455 case MULT: /* NAND */
1456 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1457 NULL_RTX, 1, OPTAB_DIRECT);
1458 tmp = expand_simple_binop (SImode, AND, tmp, val,
1459 new_rtx, 1, OPTAB_DIRECT);
1467 emit_move_insn (new_rtx, tmp);
1468 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx));
1469 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1473 tmp = (after ? new_rtx : cmp);
1474 convert_move (target,
1475 (ac.shift == NULL_RTX ? tmp
1476 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1477 NULL_RTX, 1, OPTAB_DIRECT)),
1484 xtensa_setup_frame_addresses (void)
1486 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1487 cfun->machine->accesses_prev_frame = 1;
1490 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1495 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1496 a comment showing where the end of the loop is. However, if there is a
1497 label or a branch at the end of the loop then we need to place a nop
1498 there. If the loop ends with a label we need the nop so that branches
1499 targeting that label will target the nop (and thus remain in the loop),
1500 instead of targeting the instruction after the loop (and thus exiting
1501 the loop). If the loop ends with a branch, we need the nop in case the
1502 branch is targeting a location inside the loop. When the branch
1503 executes it will cause the loop count to be decremented even if it is
1504 taken (because it is the last instruction in the loop), so we need to
1505 nop after the branch to prevent the loop count from being decremented
1506 when the branch is taken. */
1509 xtensa_emit_loop_end (rtx insn, rtx *operands)
1513 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1515 switch (GET_CODE (insn))
1522 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1528 rtx body = PATTERN (insn);
1530 if (GET_CODE (body) == JUMP_INSN)
1532 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1535 else if ((GET_CODE (body) != USE)
1536 && (GET_CODE (body) != CLOBBER))
1543 output_asm_insn ("# loop end for %0", operands);
1548 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1550 static char result[64];
1554 code = GET_CODE (operands[3]);
1557 case EQ: op = inverted ? "ne" : "eq"; break;
1558 case NE: op = inverted ? "eq" : "ne"; break;
1559 case LT: op = inverted ? "ge" : "lt"; break;
1560 case GE: op = inverted ? "lt" : "ge"; break;
1561 case LTU: op = inverted ? "geu" : "ltu"; break;
1562 case GEU: op = inverted ? "ltu" : "geu"; break;
1563 default: gcc_unreachable ();
1568 if (INTVAL (operands[1]) == 0)
1569 sprintf (result, "b%sz%s\t%%0, %%2", op,
1570 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1572 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1575 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1582 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1584 static char result[64];
1587 switch (GET_CODE (operands[3]))
1589 case EQ: op = inverted ? "bs" : "bc"; break;
1590 case NE: op = inverted ? "bc" : "bs"; break;
1591 default: gcc_unreachable ();
1596 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1597 operands[1] = GEN_INT (bitnum);
1598 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1601 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1608 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1610 static char result[64];
1614 code = GET_CODE (operands[4]);
1619 case EQ: op = inverted ? "t" : "f"; break;
1620 case NE: op = inverted ? "f" : "t"; break;
1621 default: gcc_unreachable ();
1628 case EQ: op = inverted ? "nez" : "eqz"; break;
1629 case NE: op = inverted ? "eqz" : "nez"; break;
1630 case LT: op = inverted ? "gez" : "ltz"; break;
1631 case GE: op = inverted ? "ltz" : "gez"; break;
1632 default: gcc_unreachable ();
1636 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1637 op, isfp ? ".s" : "", inverted ? 3 : 2);
1643 xtensa_emit_call (int callop, rtx *operands)
1645 static char result[64];
1646 rtx tgt = operands[callop];
1648 if (GET_CODE (tgt) == CONST_INT)
1649 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1650 else if (register_operand (tgt, VOIDmode))
1651 sprintf (result, "callx8\t%%%d", callop);
1653 sprintf (result, "call8\t%%%d", callop);
1660 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1662 /* Allow constant pool addresses. */
1663 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1664 && ! TARGET_CONST16 && constantpool_address_p (addr))
1667 while (GET_CODE (addr) == SUBREG)
1668 addr = SUBREG_REG (addr);
1670 /* Allow base registers. */
1671 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1674 /* Check for "register + offset" addressing. */
1675 if (GET_CODE (addr) == PLUS)
1677 rtx xplus0 = XEXP (addr, 0);
1678 rtx xplus1 = XEXP (addr, 1);
1679 enum rtx_code code0;
1680 enum rtx_code code1;
1682 while (GET_CODE (xplus0) == SUBREG)
1683 xplus0 = SUBREG_REG (xplus0);
1684 code0 = GET_CODE (xplus0);
1686 while (GET_CODE (xplus1) == SUBREG)
1687 xplus1 = SUBREG_REG (xplus1);
1688 code1 = GET_CODE (xplus1);
1690 /* Swap operands if necessary so the register is first. */
1691 if (code0 != REG && code1 == REG)
1693 xplus0 = XEXP (addr, 1);
1694 xplus1 = XEXP (addr, 0);
1695 code0 = GET_CODE (xplus0);
1696 code1 = GET_CODE (xplus1);
1699 if (code0 == REG && BASE_REG_P (xplus0, strict)
1700 && code1 == CONST_INT
1701 && xtensa_mem_offset (INTVAL (xplus1), mode))
1710 xtensa_legitimize_address (rtx x,
1711 rtx oldx ATTRIBUTE_UNUSED,
1712 enum machine_mode mode)
1714 if (GET_CODE (x) == PLUS)
1716 rtx plus0 = XEXP (x, 0);
1717 rtx plus1 = XEXP (x, 1);
1719 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1721 plus0 = XEXP (x, 1);
1722 plus1 = XEXP (x, 0);
1725 /* Try to split up the offset to use an ADDMI instruction. */
1726 if (GET_CODE (plus0) == REG
1727 && GET_CODE (plus1) == CONST_INT
1728 && !xtensa_mem_offset (INTVAL (plus1), mode)
1729 && !xtensa_simm8 (INTVAL (plus1))
1730 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1731 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1733 rtx temp = gen_reg_rtx (Pmode);
1734 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1735 emit_insn (gen_rtx_SET (Pmode, temp,
1736 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1737 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1745 /* Return the debugger register number to use for 'regno'. */
1748 xtensa_dbx_register_number (int regno)
1752 if (GP_REG_P (regno))
1754 regno -= GP_REG_FIRST;
1757 else if (BR_REG_P (regno))
1759 regno -= BR_REG_FIRST;
1762 else if (FP_REG_P (regno))
1764 regno -= FP_REG_FIRST;
1767 else if (ACC_REG_P (regno))
1769 first = 0x200; /* Start of Xtensa special registers. */
1770 regno = 16; /* ACCLO is special register 16. */
1773 /* When optimizing, we sometimes get asked about pseudo-registers
1774 that don't represent hard registers. Return 0 for these. */
1778 return first + regno;
1782 /* Argument support functions. */
1784 /* Initialize CUMULATIVE_ARGS for a function. */
1787 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
1790 cum->incoming = incoming;
1794 /* Advance the argument to the next argument position. */
1797 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type)
1802 arg_words = &cum->arg_words;
1803 max = MAX_ARGS_IN_REGISTERS;
1805 words = (((mode != BLKmode)
1806 ? (int) GET_MODE_SIZE (mode)
1807 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1809 if (*arg_words < max
1810 && (targetm.calls.must_pass_in_stack (mode, type)
1811 || *arg_words + words > max))
1814 *arg_words += words;
1818 /* Return an RTL expression containing the register for the given mode,
1819 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1820 if this is an incoming argument to the current function. */
1823 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1826 int regbase, words, max;
1830 arg_words = &cum->arg_words;
1831 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
1832 max = MAX_ARGS_IN_REGISTERS;
1834 words = (((mode != BLKmode)
1835 ? (int) GET_MODE_SIZE (mode)
1836 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1838 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
1840 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
1841 *arg_words = (*arg_words + align - 1) & -align;
1844 if (*arg_words + words > max)
1847 regno = regbase + *arg_words;
1849 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
1850 cfun->machine->need_a7_copy = true;
1852 return gen_rtx_REG (mode, regno);
1857 function_arg_boundary (enum machine_mode mode, tree type)
1859 unsigned int alignment;
1861 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
1862 if (alignment < PARM_BOUNDARY)
1863 alignment = PARM_BOUNDARY;
1864 if (alignment > STACK_BOUNDARY)
1865 alignment = STACK_BOUNDARY;
1871 xtensa_return_in_msb (const_tree valtype)
1873 return (TARGET_BIG_ENDIAN
1874 && AGGREGATE_TYPE_P (valtype)
1875 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
1880 override_options (void)
1883 enum machine_mode mode;
1885 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
1886 error ("boolean registers required for the floating-point option");
1888 /* Set up array giving whether a given register can hold a given mode. */
1889 for (mode = VOIDmode;
1890 mode != MAX_MACHINE_MODE;
1891 mode = (enum machine_mode) ((int) mode + 1))
1893 int size = GET_MODE_SIZE (mode);
1894 enum mode_class mclass = GET_MODE_CLASS (mode);
1896 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1900 if (ACC_REG_P (regno))
1901 temp = (TARGET_MAC16
1902 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD));
1903 else if (GP_REG_P (regno))
1904 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
1905 else if (FP_REG_P (regno))
1906 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
1907 else if (BR_REG_P (regno))
1908 temp = (TARGET_BOOLEANS && (mode == CCmode));
1912 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
1916 init_machine_status = xtensa_init_machine_status;
1918 /* Check PIC settings. PIC is only supported when using L32R
1919 instructions, and some targets need to always use PIC. */
1920 if (flag_pic && TARGET_CONST16)
1921 error ("-f%s is not supported with CONST16 instructions",
1922 (flag_pic > 1 ? "PIC" : "pic"));
1923 else if (XTENSA_ALWAYS_PIC)
1926 error ("PIC is required but not supported with CONST16 instructions");
1929 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1932 if (flag_pic && !flag_pie)
1935 /* Hot/cold partitioning does not work on this architecture, because of
1936 constant pools (the load instruction cannot necessarily reach that far).
1937 Therefore disable it on this architecture. */
1938 if (flag_reorder_blocks_and_partition)
1940 flag_reorder_blocks_and_partition = 0;
1941 flag_reorder_blocks = 1;
1946 /* A C compound statement to output to stdio stream STREAM the
1947 assembler syntax for an instruction operand X. X is an RTL
1950 CODE is a value that can be used to specify one of several ways
1951 of printing the operand. It is used when identical operands
1952 must be printed differently depending on the context. CODE
1953 comes from the '%' specification that was used to request
1954 printing of the operand. If the specification was just '%DIGIT'
1955 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1956 is the ASCII code for LTR.
1958 If X is a register, this macro should print the register's name.
1959 The names can be found in an array 'reg_names' whose type is
1960 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1962 When the machine description has a specification '%PUNCT' (a '%'
1963 followed by a punctuation character), this macro is called with
1964 a null pointer for X and the punctuation character for CODE.
1966 'a', 'c', 'l', and 'n' are reserved.
1968 The Xtensa specific codes are:
1970 'd' CONST_INT, print as signed decimal
1971 'x' CONST_INT, print as signed hexadecimal
1972 'K' CONST_INT, print number of bits in mask for EXTUI
1973 'R' CONST_INT, print (X & 0x1f)
1974 'L' CONST_INT, print ((32 - X) & 0x1f)
1975 'D' REG, print second register of double-word register operand
1976 'N' MEM, print address of next word following a memory operand
1977 'v' MEM, if memory reference is volatile, output a MEMW before it
1978 't' any constant, add "@h" suffix for top 16 bits
1979 'b' any constant, add "@l" suffix for bottom 16 bits
1983 printx (FILE *file, signed int val)
1985 /* Print a hexadecimal value in a nice way. */
1986 if ((val > -0xa) && (val < 0xa))
1987 fprintf (file, "%d", val);
1989 fprintf (file, "-0x%x", -val);
1991 fprintf (file, "0x%x", val);
1996 print_operand (FILE *file, rtx x, int letter)
1999 error ("PRINT_OPERAND null pointer");
2004 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2005 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
2007 output_operand_lossage ("invalid %%D value");
2011 if (GET_CODE (x) == MEM)
2013 /* For a volatile memory reference, emit a MEMW before the
2015 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2016 fprintf (file, "memw\n\t");
2019 output_operand_lossage ("invalid %%v value");
2023 if (GET_CODE (x) == MEM
2024 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2026 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2027 output_address (XEXP (x, 0));
2030 output_operand_lossage ("invalid %%N value");
2034 if (GET_CODE (x) == CONST_INT)
2037 unsigned val = INTVAL (x);
2043 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2044 fatal_insn ("invalid mask", x);
2046 fprintf (file, "%d", num_bits);
2049 output_operand_lossage ("invalid %%K value");
2053 if (GET_CODE (x) == CONST_INT)
2054 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2056 output_operand_lossage ("invalid %%L value");
2060 if (GET_CODE (x) == CONST_INT)
2061 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2063 output_operand_lossage ("invalid %%R value");
2067 if (GET_CODE (x) == CONST_INT)
2068 printx (file, INTVAL (x));
2070 output_operand_lossage ("invalid %%x value");
2074 if (GET_CODE (x) == CONST_INT)
2075 fprintf (file, "%ld", INTVAL (x));
2077 output_operand_lossage ("invalid %%d value");
2082 if (GET_CODE (x) == CONST_INT)
2084 printx (file, INTVAL (x));
2085 fputs (letter == 't' ? "@h" : "@l", file);
2087 else if (GET_CODE (x) == CONST_DOUBLE)
2090 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2091 if (GET_MODE (x) == SFmode)
2094 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2095 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2098 output_operand_lossage ("invalid %%t/%%b value");
2100 else if (GET_CODE (x) == CONST)
2102 /* X must be a symbolic constant on ELF. Write an expression
2103 suitable for 'const16' that sets the high or low 16 bits. */
2104 if (GET_CODE (XEXP (x, 0)) != PLUS
2105 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2106 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2107 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2108 output_operand_lossage ("invalid %%t/%%b value");
2109 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2110 fputs (letter == 't' ? "@h" : "@l", file);
2111 /* There must be a non-alphanumeric character between 'h' or 'l'
2112 and the number. The '-' is added by print_operand() already. */
2113 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2115 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2119 output_addr_const (file, x);
2120 fputs (letter == 't' ? "@h" : "@l", file);
2125 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2126 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2127 else if (GET_CODE (x) == MEM)
2128 output_address (XEXP (x, 0));
2129 else if (GET_CODE (x) == CONST_INT)
2130 fprintf (file, "%ld", INTVAL (x));
2132 output_addr_const (file, x);
2137 /* A C compound statement to output to stdio stream STREAM the
2138 assembler syntax for an instruction operand that is a memory
2139 reference whose address is ADDR. ADDR is an RTL expression. */
2142 print_operand_address (FILE *file, rtx addr)
2145 error ("PRINT_OPERAND_ADDRESS, null pointer");
2147 switch (GET_CODE (addr))
2150 fatal_insn ("invalid address", addr);
2154 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2160 rtx offset = (rtx)0;
2161 rtx arg0 = XEXP (addr, 0);
2162 rtx arg1 = XEXP (addr, 1);
2164 if (GET_CODE (arg0) == REG)
2169 else if (GET_CODE (arg1) == REG)
2175 fatal_insn ("no register in address", addr);
2177 if (CONSTANT_P (offset))
2179 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2180 output_addr_const (file, offset);
2183 fatal_insn ("address offset not a constant", addr);
2191 output_addr_const (file, addr);
2198 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2200 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2202 switch (XINT (x, 1))
2207 output_addr_const (fp, XVECEXP (x, 0, 0));
2221 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2228 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2230 switch (GET_MODE_CLASS (mode))
2233 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2235 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2239 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2240 if (HOST_BITS_PER_LONG > 32)
2241 value_long[0] &= 0xffffffff;
2242 fprintf (file, "0x%08lx\n", value_long[0]);
2246 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2247 if (HOST_BITS_PER_LONG > 32)
2249 value_long[0] &= 0xffffffff;
2250 value_long[1] &= 0xffffffff;
2252 fprintf (file, "0x%08lx, 0x%08lx\n",
2253 value_long[0], value_long[1]);
2263 case MODE_PARTIAL_INT:
2264 size = GET_MODE_SIZE (mode);
2268 output_addr_const (file, x);
2273 split_double (x, &first, &second);
2274 output_addr_const (file, first);
2276 output_addr_const (file, second);
2291 /* Return the bytes needed to compute the frame pointer from the current
2294 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2295 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2298 compute_frame_size (int size)
2300 /* Add space for the incoming static chain value. */
2301 if (cfun->static_chain_decl != NULL)
2302 size += (1 * UNITS_PER_WORD);
2304 xtensa_current_frame_size =
2305 XTENSA_STACK_ALIGN (size
2306 + crtl->outgoing_args_size
2307 + (WINDOW_SIZE * UNITS_PER_WORD));
2308 return xtensa_current_frame_size;
2313 xtensa_frame_pointer_required (void)
2315 /* The code to expand builtin_frame_addr and builtin_return_addr
2316 currently uses the hard_frame_pointer instead of frame_pointer.
2317 This seems wrong but maybe it's necessary for other architectures.
2318 This function is derived from the i386 code. */
2320 if (cfun->machine->accesses_prev_frame)
2327 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2328 and the total number of words must be a multiple of 128 bits. */
2329 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2332 xtensa_expand_prologue (void)
2334 HOST_WIDE_INT total_size;
2338 total_size = compute_frame_size (get_frame_size ());
2339 size_rtx = GEN_INT (total_size);
2341 if (total_size < (1 << (12+3)))
2342 insn = emit_insn (gen_entry (size_rtx));
2345 /* Use a8 as a temporary since a0-a7 may be live. */
2346 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2347 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2348 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2349 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2350 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2353 if (frame_pointer_needed)
2355 if (cfun->machine->set_frame_ptr_insn)
2359 push_topmost_sequence ();
2360 first = get_insns ();
2361 pop_topmost_sequence ();
2363 /* For all instructions prior to set_frame_ptr_insn, replace
2364 hard_frame_pointer references with stack_pointer. */
2366 insn != cfun->machine->set_frame_ptr_insn;
2367 insn = NEXT_INSN (insn))
2371 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2372 hard_frame_pointer_rtx,
2374 df_insn_rescan (insn);
2379 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2380 stack_pointer_rtx));
2383 /* Create a note to describe the CFA. Because this is only used to set
2384 DW_AT_frame_base for debug info, don't bother tracking changes through
2385 each instruction in the prologue. It just takes up space. */
2386 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2387 ? hard_frame_pointer_rtx
2388 : stack_pointer_rtx),
2389 plus_constant (stack_pointer_rtx, -total_size));
2390 RTX_FRAME_RELATED_P (insn) = 1;
2391 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2392 note_rtx, REG_NOTES (insn));
2396 /* Clear variables at function end. */
2399 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2400 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2402 xtensa_current_frame_size = 0;
2407 xtensa_return_addr (int count, rtx frame)
2409 rtx result, retaddr, curaddr, label;
2412 retaddr = gen_rtx_REG (Pmode, A0_REG);
2415 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2416 addr = memory_address (Pmode, addr);
2417 retaddr = gen_reg_rtx (Pmode);
2418 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2421 /* The 2 most-significant bits of the return address on Xtensa hold
2422 the register window size. To get the real return address, these
2423 bits must be replaced with the high bits from some address in the
2426 /* Get the 2 high bits of a local label in the code. */
2427 curaddr = gen_reg_rtx (Pmode);
2428 label = gen_label_rtx ();
2430 LABEL_PRESERVE_P (label) = 1;
2431 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2432 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2433 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2435 /* Clear the 2 high bits of the return address. */
2436 result = gen_reg_rtx (Pmode);
2437 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2438 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2440 /* Combine them to get the result. */
2441 emit_insn (gen_iorsi3 (result, result, curaddr));
2446 /* Create the va_list data type.
2448 This structure is set up by __builtin_saveregs. The __va_reg field
2449 points to a stack-allocated region holding the contents of the
2450 incoming argument registers. The __va_ndx field is an index
2451 initialized to the position of the first unnamed (variable)
2452 argument. This same index is also used to address the arguments
2453 passed in memory. Thus, the __va_stk field is initialized to point
2454 to the position of the first argument in memory offset to account
2455 for the arguments passed in registers and to account for the size
2456 of the argument registers not being 16-byte aligned. E.G., there
2457 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2458 for the first stack argument to have the maximal alignment of 16
2459 bytes, so we offset the __va_stk address by 32 bytes so that
2460 __va_stk[32] references the first argument on the stack. */
2463 xtensa_build_builtin_va_list (void)
2465 tree f_stk, f_reg, f_ndx, record, type_decl;
2467 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2468 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2470 f_stk = build_decl (FIELD_DECL, get_identifier ("__va_stk"),
2472 f_reg = build_decl (FIELD_DECL, get_identifier ("__va_reg"),
2474 f_ndx = build_decl (FIELD_DECL, get_identifier ("__va_ndx"),
2477 DECL_FIELD_CONTEXT (f_stk) = record;
2478 DECL_FIELD_CONTEXT (f_reg) = record;
2479 DECL_FIELD_CONTEXT (f_ndx) = record;
2481 TREE_CHAIN (record) = type_decl;
2482 TYPE_NAME (record) = type_decl;
2483 TYPE_FIELDS (record) = f_stk;
2484 TREE_CHAIN (f_stk) = f_reg;
2485 TREE_CHAIN (f_reg) = f_ndx;
2487 layout_type (record);
2492 /* Save the incoming argument registers on the stack. Returns the
2493 address of the saved registers. */
2496 xtensa_builtin_saveregs (void)
2499 int arg_words = crtl->args.info.arg_words;
2500 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2505 /* Allocate the general-purpose register space. */
2506 gp_regs = assign_stack_local
2507 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2508 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2510 /* Now store the incoming registers. */
2511 cfun->machine->need_a7_copy = true;
2512 cfun->machine->vararg_a7 = true;
2513 move_block_from_reg (GP_ARG_FIRST + arg_words,
2514 adjust_address (gp_regs, BLKmode,
2515 arg_words * UNITS_PER_WORD),
2517 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2518 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2520 return XEXP (gp_regs, 0);
2524 /* Implement `va_start' for varargs and stdarg. We look at the
2525 current function to fill in an initial va_list. */
2528 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2536 arg_words = crtl->args.info.arg_words;
2538 f_stk = TYPE_FIELDS (va_list_type_node);
2539 f_reg = TREE_CHAIN (f_stk);
2540 f_ndx = TREE_CHAIN (f_reg);
2542 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2543 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2545 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2548 /* Call __builtin_saveregs; save the result in __va_reg */
2549 u = make_tree (sizetype, expand_builtin_saveregs ());
2550 u = fold_convert (ptr_type_node, u);
2551 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2552 TREE_SIDE_EFFECTS (t) = 1;
2553 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2555 /* Set the __va_stk member to ($arg_ptr - 32). */
2556 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2557 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2558 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2559 TREE_SIDE_EFFECTS (t) = 1;
2560 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2562 /* Set the __va_ndx member. If the first variable argument is on
2563 the stack, adjust __va_ndx by 2 words to account for the extra
2564 alignment offset for __va_stk. */
2565 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2567 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2568 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2569 TREE_SIDE_EFFECTS (t) = 1;
2570 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2574 /* Implement `va_arg'. */
2577 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2578 gimple_seq *post_p ATTRIBUTE_UNUSED)
2583 tree type_size, array, orig_ndx, addr, size, va_size, t;
2584 tree lab_false, lab_over, lab_false2;
2587 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2589 type = build_pointer_type (type);
2591 /* Handle complex values as separate real and imaginary parts. */
2592 if (TREE_CODE (type) == COMPLEX_TYPE)
2594 tree real_part, imag_part;
2596 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2598 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2600 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2603 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2605 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2608 f_stk = TYPE_FIELDS (va_list_type_node);
2609 f_reg = TREE_CHAIN (f_stk);
2610 f_ndx = TREE_CHAIN (f_reg);
2612 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2614 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2616 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2619 type_size = size_in_bytes (type);
2620 va_size = round_up (type_size, UNITS_PER_WORD);
2621 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2624 /* First align __va_ndx if necessary for this arg:
2626 orig_ndx = (AP).__va_ndx;
2627 if (__alignof__ (TYPE) > 4 )
2628 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2629 & -__alignof__ (TYPE)); */
2631 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2633 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2635 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2637 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2638 build_int_cst (integer_type_node, align - 1));
2639 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2640 build_int_cst (integer_type_node, -align));
2641 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2645 /* Increment __va_ndx to point past the argument:
2647 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2649 t = fold_convert (integer_type_node, va_size);
2650 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2651 gimplify_assign (unshare_expr (ndx), t, pre_p);
2654 /* Check if the argument is in registers:
2656 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2657 && !must_pass_in_stack (type))
2658 __array = (AP).__va_reg; */
2660 array = create_tmp_var (ptr_type_node, NULL);
2663 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2665 lab_false = create_artificial_label ();
2666 lab_over = create_artificial_label ();
2668 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2669 build_int_cst (integer_type_node,
2670 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2671 t = build3 (COND_EXPR, void_type_node, t,
2672 build1 (GOTO_EXPR, void_type_node, lab_false),
2674 gimplify_and_add (t, pre_p);
2676 gimplify_assign (unshare_expr (array), reg, pre_p);
2678 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2679 gimplify_and_add (t, pre_p);
2681 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2682 gimplify_and_add (t, pre_p);
2686 /* ...otherwise, the argument is on the stack (never split between
2687 registers and the stack -- change __va_ndx if necessary):
2691 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2692 (AP).__va_ndx = 32 + __va_size (TYPE);
2693 __array = (AP).__va_stk;
2696 lab_false2 = create_artificial_label ();
2698 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
2699 build_int_cst (integer_type_node,
2700 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2701 t = build3 (COND_EXPR, void_type_node, t,
2702 build1 (GOTO_EXPR, void_type_node, lab_false2),
2704 gimplify_and_add (t, pre_p);
2706 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
2707 t = fold_convert (integer_type_node, t);
2708 gimplify_assign (unshare_expr (ndx), t, pre_p);
2710 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2711 gimplify_and_add (t, pre_p);
2713 gimplify_assign (array, stk, pre_p);
2717 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2718 gimplify_and_add (t, pre_p);
2722 /* Given the base array pointer (__array) and index to the subsequent
2723 argument (__va_ndx), find the address:
2725 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2729 The results are endian-dependent because values smaller than one word
2730 are aligned differently. */
2733 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
2735 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
2736 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
2737 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
2738 unshare_expr (type_size));
2742 size = unshare_expr (va_size);
2744 t = fold_convert (sizetype, unshare_expr (ndx));
2745 t = build2 (MINUS_EXPR, sizetype, t, size);
2746 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t);
2748 addr = fold_convert (build_pointer_type (type), addr);
2750 addr = build_va_arg_indirect_ref (addr);
2751 return build_va_arg_indirect_ref (addr);
2759 XTENSA_BUILTIN_UMULSIDI3,
2765 xtensa_init_builtins (void)
2769 ftype = build_function_type_list (unsigned_intDI_type_node,
2770 unsigned_intSI_type_node,
2771 unsigned_intSI_type_node, NULL_TREE);
2773 add_builtin_function ("__builtin_umulsidi3", ftype,
2774 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
2775 "__umulsidi3", NULL_TREE);
2780 xtensa_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED)
2782 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2785 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2787 arg0 = TREE_VALUE (arglist);
2788 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
2789 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
2790 || TARGET_MUL32_HIGH)
2791 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
2792 fold_convert (unsigned_intDI_type_node, arg0),
2793 fold_convert (unsigned_intDI_type_node, arg1));
2798 internal_error ("bad builtin code");
2804 xtensa_expand_builtin (tree exp, rtx target,
2805 rtx subtarget ATTRIBUTE_UNUSED,
2806 enum machine_mode mode ATTRIBUTE_UNUSED,
2809 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2810 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2812 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2813 __umulsidi3 function when the Xtensa configuration can directly
2814 implement it. If not, just call the function. */
2815 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2816 return expand_call (exp, target, ignore);
2818 internal_error ("bad builtin code");
2824 xtensa_preferred_reload_class (rtx x, enum reg_class rclass, int isoutput)
2826 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
2829 /* Don't use the stack pointer or hard frame pointer for reloads!
2830 The hard frame pointer would normally be OK except that it may
2831 briefly hold an incoming argument in the prologue, and reload
2832 won't know that it is live because the hard frame pointer is
2833 treated specially. */
2835 if (rclass == AR_REGS || rclass == GR_REGS)
2843 xtensa_secondary_reload_class (enum reg_class rclass,
2844 enum machine_mode mode ATTRIBUTE_UNUSED,
2845 rtx x, int isoutput)
2849 if (GET_CODE (x) == SIGN_EXTEND)
2851 regno = xt_true_regnum (x);
2855 if (rclass == FP_REGS && constantpool_mem_p (x))
2859 if (ACC_REG_P (regno))
2860 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS);
2861 if (rclass == ACC_REG)
2862 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
2869 order_regs_for_local_alloc (void)
2871 if (!leaf_function_p ())
2873 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
2874 FIRST_PSEUDO_REGISTER * sizeof (int));
2878 int i, num_arg_regs;
2881 /* Use the AR registers in increasing order (skipping a0 and a1)
2882 but save the incoming argument registers for a last resort. */
2883 num_arg_regs = crtl->args.info.arg_words;
2884 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
2885 num_arg_regs = MAX_ARGS_IN_REGISTERS;
2886 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
2887 reg_alloc_order[nxt++] = i + num_arg_regs;
2888 for (i = 0; i < num_arg_regs; i++)
2889 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
2891 /* List the coprocessor registers in order. */
2892 for (i = 0; i < BR_REG_NUM; i++)
2893 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
2895 /* List the FP registers in order for now. */
2896 for (i = 0; i < 16; i++)
2897 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
2899 /* GCC requires that we list *all* the registers.... */
2900 reg_alloc_order[nxt++] = 0; /* a0 = return address */
2901 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
2902 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
2903 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
2905 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
2910 /* Some Xtensa targets support multiple bss sections. If the section
2911 name ends with ".bss", add SECTION_BSS to the flags. */
2914 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
2916 unsigned int flags = default_section_type_flags (decl, name, reloc);
2919 suffix = strrchr (name, '.');
2920 if (suffix && strcmp (suffix, ".bss") == 0)
2922 if (!decl || (TREE_CODE (decl) == VAR_DECL
2923 && DECL_INITIAL (decl) == NULL_TREE))
2924 flags |= SECTION_BSS; /* @nobits */
2926 warning (0, "only uninitialized variables can be placed in a "
2934 /* The literal pool stays with the function. */
2937 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
2938 rtx x ATTRIBUTE_UNUSED,
2939 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
2941 return function_section (current_function_decl);
2945 /* Compute a (partial) cost for rtx X. Return true if the complete
2946 cost has been computed, and false if subexpressions should be
2947 scanned. In either case, *TOTAL contains the cost result. */
2950 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total,
2951 bool speed ATTRIBUTE_UNUSED)
2959 if (xtensa_simm12b (INTVAL (x)))
2966 if (xtensa_simm8 (INTVAL (x))
2967 || xtensa_simm8x256 (INTVAL (x)))
2974 if (xtensa_mask_immediate (INTVAL (x)))
2981 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
2992 /* No way to tell if X is the 2nd operand so be conservative. */
2995 if (xtensa_simm12b (INTVAL (x)))
2997 else if (TARGET_CONST16)
2998 *total = COSTS_N_INSNS (2);
3007 *total = COSTS_N_INSNS (2);
3014 *total = COSTS_N_INSNS (4);
3022 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3024 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3025 *total = COSTS_N_INSNS (num_words);
3027 *total = COSTS_N_INSNS (2*num_words);
3033 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3037 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3041 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3047 if (GET_MODE (x) == DImode)
3048 *total = COSTS_N_INSNS (2);
3050 *total = COSTS_N_INSNS (1);
3056 if (GET_MODE (x) == DImode)
3057 *total = COSTS_N_INSNS (50);
3059 *total = COSTS_N_INSNS (1);
3064 enum machine_mode xmode = GET_MODE (x);
3065 if (xmode == SFmode)
3066 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3067 else if (xmode == DFmode)
3068 *total = COSTS_N_INSNS (50);
3070 *total = COSTS_N_INSNS (4);
3077 enum machine_mode xmode = GET_MODE (x);
3078 if (xmode == SFmode)
3079 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3080 else if (xmode == DFmode || xmode == DImode)
3081 *total = COSTS_N_INSNS (50);
3083 *total = COSTS_N_INSNS (1);
3088 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3093 enum machine_mode xmode = GET_MODE (x);
3094 if (xmode == SFmode)
3095 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3096 else if (xmode == DFmode)
3097 *total = COSTS_N_INSNS (50);
3098 else if (xmode == DImode)
3099 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3100 else if (TARGET_MUL32)
3101 *total = COSTS_N_INSNS (4);
3102 else if (TARGET_MAC16)
3103 *total = COSTS_N_INSNS (16);
3104 else if (TARGET_MUL16)
3105 *total = COSTS_N_INSNS (12);
3107 *total = COSTS_N_INSNS (50);
3114 enum machine_mode xmode = GET_MODE (x);
3115 if (xmode == SFmode)
3117 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3120 else if (xmode == DFmode)
3122 *total = COSTS_N_INSNS (50);
3131 enum machine_mode xmode = GET_MODE (x);
3132 if (xmode == DImode)
3133 *total = COSTS_N_INSNS (50);
3134 else if (TARGET_DIV32)
3135 *total = COSTS_N_INSNS (32);
3137 *total = COSTS_N_INSNS (50);
3142 if (GET_MODE (x) == SFmode)
3143 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3145 *total = COSTS_N_INSNS (50);
3152 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3157 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3162 *total = COSTS_N_INSNS (1);
3170 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3173 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3175 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3176 > 4 * UNITS_PER_WORD);
3179 /* Worker function for TARGET_FUNCTION_VALUE. */
3182 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3185 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3186 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3187 ? SImode : TYPE_MODE (valtype),
3188 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3191 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3192 instruction with a minimal stack frame in order to get some free
3193 registers. Once the actual call target is known, the proper stack frame
3194 size is extracted from the ENTRY instruction at the target and the
3195 current frame is adjusted to match. The trampoline then transfers
3196 control to the instruction following the ENTRY at the target. Note:
3197 this assumes that the target begins with an ENTRY instruction. */
3200 xtensa_trampoline_template (FILE *stream)
3202 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3204 fprintf (stream, "\t.begin no-transform\n");
3205 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3209 /* Save the return address. */
3210 fprintf (stream, "\tmov\ta10, a0\n");
3212 /* Use a CALL0 instruction to skip past the constants and in the
3213 process get the PC into A0. This allows PC-relative access to
3214 the constants without relying on L32R. */
3215 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3218 fprintf (stream, "\tj\t.Lskipconsts\n");
3220 fprintf (stream, "\t.align\t4\n");
3221 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3222 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3223 fprintf (stream, ".Lskipconsts:\n");
3225 /* Load the static chain and function address from the trampoline. */
3228 fprintf (stream, "\taddi\ta0, a0, 3\n");
3229 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3230 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3234 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3235 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3238 /* Store the static chain. */
3239 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3241 /* Set the proper stack pointer value. */
3242 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3243 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3244 TARGET_BIG_ENDIAN ? 8 : 12);
3245 fprintf (stream, "\tslli\ta9, a9, 3\n");
3246 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3247 fprintf (stream, "\tsub\ta9, sp, a9\n");
3248 fprintf (stream, "\tmovsp\tsp, a9\n");
3251 /* Restore the return address. */
3252 fprintf (stream, "\tmov\ta0, a10\n");
3254 /* Jump to the instruction following the ENTRY. */
3255 fprintf (stream, "\taddi\ta8, a8, 3\n");
3256 fprintf (stream, "\tjx\ta8\n");
3258 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3260 fprintf (stream, "\t.byte\t0\n");
3262 fprintf (stream, "\tnop\n");
3264 fprintf (stream, "\t.end no-transform\n");
3269 xtensa_initialize_trampoline (rtx addr, rtx func, rtx chain)
3271 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3272 int chain_off = use_call0 ? 12 : 8;
3273 int func_off = use_call0 ? 16 : 12;
3274 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, chain_off)), chain);
3275 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, func_off)), func);
3276 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3277 0, VOIDmode, 1, addr, Pmode);
3281 #include "gt-xtensa.h"