1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
33 #include "insn-attr.h"
34 #include "insn-codes.h"
43 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 /* Enumeration for all of the relational tests, so that we can build
55 arrays indexed by the test type, and not worry about the order
73 /* Array giving truth value on whether or not a given hard register
74 can support a given mode. */
75 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
77 /* Current frame size calculated by compute_frame_size. */
78 unsigned xtensa_current_frame_size;
80 /* Largest block move to handle in-line. */
81 #define LARGEST_MOVE_RATIO 15
83 /* Define the structure for the machine field in struct function. */
84 struct GTY(()) machine_function
86 int accesses_prev_frame;
90 rtx set_frame_ptr_insn;
93 /* Vector, indexed by hard register number, which contains 1 for a
94 register that is allowable in a candidate for leaf function
97 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
99 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
101 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
105 /* Map hard register number to register class */
106 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
108 RL_REGS, SP_REG, RL_REGS, RL_REGS,
109 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
110 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
111 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
112 AR_REGS, AR_REGS, BR_REGS,
113 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
114 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
115 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
116 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
120 static void xtensa_option_override (void);
121 static enum internal_test map_test_to_internal_test (enum rtx_code);
122 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
123 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
124 static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx);
125 static rtx fixup_subreg_mem (rtx);
126 static struct machine_function * xtensa_init_machine_status (void);
127 static rtx xtensa_legitimize_tls_address (rtx);
128 static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode);
129 static bool xtensa_mode_dependent_address_p (const_rtx);
130 static bool xtensa_return_in_msb (const_tree);
131 static void printx (FILE *, signed int);
132 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
133 static rtx xtensa_builtin_saveregs (void);
134 static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool);
135 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
136 int) ATTRIBUTE_UNUSED;
137 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
138 unsigned HOST_WIDE_INT);
139 static bool xtensa_rtx_costs (rtx, int, int, int *, bool);
140 static int xtensa_register_move_cost (enum machine_mode, reg_class_t,
142 static int xtensa_memory_move_cost (enum machine_mode, reg_class_t, bool);
143 static tree xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree, const_tree);
145 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
147 static void xtensa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
149 static rtx xtensa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
151 static rtx xtensa_function_incoming_arg (CUMULATIVE_ARGS *,
152 enum machine_mode, const_tree, bool);
153 static rtx xtensa_function_value (const_tree, const_tree, bool);
154 static rtx xtensa_libcall_value (enum machine_mode, const_rtx);
155 static bool xtensa_function_value_regno_p (const unsigned int);
156 static unsigned int xtensa_function_arg_boundary (enum machine_mode,
158 static void xtensa_init_builtins (void);
159 static tree xtensa_fold_builtin (tree, int, tree *, bool);
160 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
161 static void xtensa_va_start (tree, rtx);
162 static bool xtensa_frame_pointer_required (void);
163 static rtx xtensa_static_chain (const_tree, bool);
164 static void xtensa_asm_trampoline_template (FILE *);
165 static void xtensa_trampoline_init (rtx, tree, rtx);
166 static bool xtensa_output_addr_const_extra (FILE *, rtx);
168 static reg_class_t xtensa_preferred_reload_class (rtx, reg_class_t);
169 static reg_class_t xtensa_preferred_output_reload_class (rtx, reg_class_t);
170 static reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t,
172 struct secondary_reload_info *);
174 static bool constantpool_address_p (const_rtx addr);
176 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
179 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
181 static const struct default_options xtensa_option_optimization_table[] =
183 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
184 /* Reordering blocks for Xtensa is not a good idea unless the
185 compiler understands the range of conditional branches.
186 Currently all branch relaxation for Xtensa is handled in the
187 assembler, so GCC cannot do a good job of reordering blocks.
188 Do not enable reordering unless it is explicitly requested. */
189 { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 },
190 { OPT_LEVELS_NONE, 0, NULL, 0 }
194 /* This macro generates the assembly code for function exit,
195 on machines that need it. If FUNCTION_EPILOGUE is not defined
196 then individual return instructions are generated for each
197 return statement. Args are same as for FUNCTION_PROLOGUE. */
199 #undef TARGET_ASM_FUNCTION_EPILOGUE
200 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
202 /* These hooks specify assembly directives for creating certain kinds
203 of integer object. */
205 #undef TARGET_ASM_ALIGNED_SI_OP
206 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
208 #undef TARGET_ASM_SELECT_RTX_SECTION
209 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
211 #undef TARGET_DEFAULT_TARGET_FLAGS
212 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
214 #undef TARGET_LEGITIMIZE_ADDRESS
215 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
216 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
217 #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p
219 #undef TARGET_REGISTER_MOVE_COST
220 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost
221 #undef TARGET_MEMORY_MOVE_COST
222 #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS xtensa_rtx_costs
225 #undef TARGET_ADDRESS_COST
226 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
228 #undef TARGET_BUILD_BUILTIN_VA_LIST
229 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
231 #undef TARGET_EXPAND_BUILTIN_VA_START
232 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
234 #undef TARGET_PROMOTE_FUNCTION_MODE
235 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
236 #undef TARGET_PROMOTE_PROTOTYPES
237 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
239 #undef TARGET_RETURN_IN_MEMORY
240 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
241 #undef TARGET_FUNCTION_VALUE
242 #define TARGET_FUNCTION_VALUE xtensa_function_value
243 #undef TARGET_LIBCALL_VALUE
244 #define TARGET_LIBCALL_VALUE xtensa_libcall_value
245 #undef TARGET_FUNCTION_VALUE_REGNO_P
246 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p
248 #undef TARGET_SPLIT_COMPLEX_ARG
249 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
250 #undef TARGET_MUST_PASS_IN_STACK
251 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
252 #undef TARGET_FUNCTION_ARG_ADVANCE
253 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
254 #undef TARGET_FUNCTION_ARG
255 #define TARGET_FUNCTION_ARG xtensa_function_arg
256 #undef TARGET_FUNCTION_INCOMING_ARG
257 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
258 #undef TARGET_FUNCTION_ARG_BOUNDARY
259 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
261 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
262 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
263 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
264 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
266 #undef TARGET_RETURN_IN_MSB
267 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
269 #undef TARGET_INIT_BUILTINS
270 #define TARGET_INIT_BUILTINS xtensa_init_builtins
271 #undef TARGET_FOLD_BUILTIN
272 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
273 #undef TARGET_EXPAND_BUILTIN
274 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
276 #undef TARGET_PREFERRED_RELOAD_CLASS
277 #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class
278 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
279 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class
281 #undef TARGET_SECONDARY_RELOAD
282 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
284 #undef TARGET_HAVE_TLS
285 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
287 #undef TARGET_CANNOT_FORCE_CONST_MEM
288 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_tls_referenced_p
290 #undef TARGET_LEGITIMATE_ADDRESS_P
291 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
293 #undef TARGET_FRAME_POINTER_REQUIRED
294 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
296 #undef TARGET_STATIC_CHAIN
297 #define TARGET_STATIC_CHAIN xtensa_static_chain
298 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
299 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
300 #undef TARGET_TRAMPOLINE_INIT
301 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
303 #undef TARGET_OPTION_OVERRIDE
304 #define TARGET_OPTION_OVERRIDE xtensa_option_override
305 #undef TARGET_OPTION_OPTIMIZATION_TABLE
306 #define TARGET_OPTION_OPTIMIZATION_TABLE xtensa_option_optimization_table
308 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
309 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
311 struct gcc_target targetm = TARGET_INITIALIZER;
314 /* Functions to test Xtensa immediate operand validity. */
317 xtensa_simm8 (HOST_WIDE_INT v)
319 return v >= -128 && v <= 127;
324 xtensa_simm8x256 (HOST_WIDE_INT v)
326 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
331 xtensa_simm12b (HOST_WIDE_INT v)
333 return v >= -2048 && v <= 2047;
338 xtensa_uimm8 (HOST_WIDE_INT v)
340 return v >= 0 && v <= 255;
345 xtensa_uimm8x2 (HOST_WIDE_INT v)
347 return (v & 1) == 0 && (v >= 0 && v <= 510);
352 xtensa_uimm8x4 (HOST_WIDE_INT v)
354 return (v & 3) == 0 && (v >= 0 && v <= 1020);
359 xtensa_b4const (HOST_WIDE_INT v)
386 xtensa_b4const_or_zero (HOST_WIDE_INT v)
390 return xtensa_b4const (v);
395 xtensa_b4constu (HOST_WIDE_INT v)
422 xtensa_mask_immediate (HOST_WIDE_INT v)
424 #define MAX_MASK_SIZE 16
427 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
440 /* This is just like the standard true_regnum() function except that it
441 works even when reg_renumber is not initialized. */
444 xt_true_regnum (rtx x)
446 if (GET_CODE (x) == REG)
449 && REGNO (x) >= FIRST_PSEUDO_REGISTER
450 && reg_renumber[REGNO (x)] >= 0)
451 return reg_renumber[REGNO (x)];
454 if (GET_CODE (x) == SUBREG)
456 int base = xt_true_regnum (SUBREG_REG (x));
457 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
458 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
459 GET_MODE (SUBREG_REG (x)),
460 SUBREG_BYTE (x), GET_MODE (x));
467 xtensa_valid_move (enum machine_mode mode, rtx *operands)
469 /* Either the destination or source must be a register, and the
470 MAC16 accumulator doesn't count. */
472 if (register_operand (operands[0], mode))
474 int dst_regnum = xt_true_regnum (operands[0]);
476 /* The stack pointer can only be assigned with a MOVSP opcode. */
477 if (dst_regnum == STACK_POINTER_REGNUM)
478 return (mode == SImode
479 && register_operand (operands[1], mode)
480 && !ACC_REG_P (xt_true_regnum (operands[1])));
482 if (!ACC_REG_P (dst_regnum))
485 if (register_operand (operands[1], mode))
487 int src_regnum = xt_true_regnum (operands[1]);
488 if (!ACC_REG_P (src_regnum))
496 smalloffset_mem_p (rtx op)
498 if (GET_CODE (op) == MEM)
500 rtx addr = XEXP (op, 0);
501 if (GET_CODE (addr) == REG)
502 return BASE_REG_P (addr, 0);
503 if (GET_CODE (addr) == PLUS)
505 rtx offset = XEXP (addr, 0);
507 if (GET_CODE (offset) != CONST_INT)
508 offset = XEXP (addr, 1);
509 if (GET_CODE (offset) != CONST_INT)
512 val = INTVAL (offset);
513 return (val & 3) == 0 && (val >= 0 && val <= 60);
521 constantpool_address_p (const_rtx addr)
523 const_rtx sym = addr;
525 if (GET_CODE (addr) == CONST)
529 /* Only handle (PLUS (SYM, OFFSET)) form. */
530 addr = XEXP (addr, 0);
531 if (GET_CODE (addr) != PLUS)
534 /* Make sure the address is word aligned. */
535 offset = XEXP (addr, 1);
536 if ((!CONST_INT_P (offset))
537 || ((INTVAL (offset) & 3) != 0))
540 sym = XEXP (addr, 0);
543 if ((GET_CODE (sym) == SYMBOL_REF)
544 && CONSTANT_POOL_ADDRESS_P (sym))
551 constantpool_mem_p (rtx op)
553 if (GET_CODE (op) == SUBREG)
554 op = SUBREG_REG (op);
555 if (GET_CODE (op) == MEM)
556 return constantpool_address_p (XEXP (op, 0));
561 /* Return TRUE if X is a thread-local symbol. */
564 xtensa_tls_symbol_p (rtx x)
566 if (! TARGET_HAVE_TLS)
569 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
574 xtensa_extend_reg (rtx dst, rtx src)
576 rtx temp = gen_reg_rtx (SImode);
577 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
579 /* Generate paradoxical subregs as needed so that the modes match. */
580 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
581 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
583 emit_insn (gen_ashlsi3 (temp, src, shift));
584 emit_insn (gen_ashrsi3 (dst, temp, shift));
589 xtensa_mem_offset (unsigned v, enum machine_mode mode)
594 /* Handle the worst case for block moves. See xtensa_expand_block_move
595 where we emit an optimized block move operation if the block can be
596 moved in < "move_ratio" pieces. The worst case is when the block is
597 aligned but has a size of (3 mod 4) (does this happen?) so that the
598 last piece requires a byte load/store. */
599 return (xtensa_uimm8 (v)
600 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
603 return xtensa_uimm8 (v);
606 return xtensa_uimm8x2 (v);
609 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
615 return xtensa_uimm8x4 (v);
619 /* Make normal rtx_code into something we can index from an array. */
621 static enum internal_test
622 map_test_to_internal_test (enum rtx_code test_code)
624 enum internal_test test = ITEST_MAX;
629 case EQ: test = ITEST_EQ; break;
630 case NE: test = ITEST_NE; break;
631 case GT: test = ITEST_GT; break;
632 case GE: test = ITEST_GE; break;
633 case LT: test = ITEST_LT; break;
634 case LE: test = ITEST_LE; break;
635 case GTU: test = ITEST_GTU; break;
636 case GEU: test = ITEST_GEU; break;
637 case LTU: test = ITEST_LTU; break;
638 case LEU: test = ITEST_LEU; break;
645 /* Generate the code to compare two integer values. The return value is
646 the comparison expression. */
649 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
650 rtx cmp0, /* first operand to compare */
651 rtx cmp1, /* second operand to compare */
652 int *p_invert /* whether branch needs to reverse test */)
656 enum rtx_code test_code; /* test code to use in insn */
657 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
658 int const_add; /* constant to add (convert LE -> LT) */
659 int reverse_regs; /* reverse registers in test */
660 int invert_const; /* != 0 if invert value if cmp1 is constant */
661 int invert_reg; /* != 0 if invert value if cmp1 is register */
662 int unsignedp; /* != 0 for unsigned comparisons. */
665 static struct cmp_info info[ (int)ITEST_MAX ] = {
667 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
668 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
670 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
671 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
672 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
673 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
675 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
676 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
677 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
678 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
681 enum internal_test test;
682 enum machine_mode mode;
683 struct cmp_info *p_info;
685 test = map_test_to_internal_test (test_code);
686 gcc_assert (test != ITEST_MAX);
688 p_info = &info[ (int)test ];
690 mode = GET_MODE (cmp0);
691 if (mode == VOIDmode)
692 mode = GET_MODE (cmp1);
694 /* Make sure we can handle any constants given to us. */
695 if (GET_CODE (cmp1) == CONST_INT)
697 HOST_WIDE_INT value = INTVAL (cmp1);
698 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
700 /* if the immediate overflows or does not fit in the immediate field,
701 spill it to a register */
703 if ((p_info->unsignedp ?
704 (uvalue + p_info->const_add > uvalue) :
705 (value + p_info->const_add > value)) != (p_info->const_add > 0))
707 cmp1 = force_reg (mode, cmp1);
709 else if (!(p_info->const_range_p) (value + p_info->const_add))
711 cmp1 = force_reg (mode, cmp1);
714 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
716 cmp1 = force_reg (mode, cmp1);
719 /* See if we need to invert the result. */
720 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
721 ? p_info->invert_const
722 : p_info->invert_reg);
724 /* Comparison to constants, may involve adding 1 to change a LT into LE.
725 Comparison between two registers, may involve switching operands. */
726 if (GET_CODE (cmp1) == CONST_INT)
728 if (p_info->const_add != 0)
729 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
732 else if (p_info->reverse_regs)
739 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
743 /* Generate the code to compare two float values. The return value is
744 the comparison expression. */
747 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
748 rtx cmp0, /* first operand to compare */
749 rtx cmp1 /* second operand to compare */)
751 rtx (*gen_fn) (rtx, rtx, rtx);
753 int reverse_regs, invert;
757 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
758 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
759 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
760 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
761 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
762 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
763 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
764 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
765 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
766 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
767 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
768 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
770 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
772 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
774 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
775 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
785 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
786 emit_insn (gen_fn (brtmp, cmp0, cmp1));
788 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
793 xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode)
795 enum rtx_code test_code = GET_CODE (operands[0]);
796 rtx cmp0 = operands[1];
797 rtx cmp1 = operands[2];
806 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
810 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
814 if (!TARGET_HARD_FLOAT)
815 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
818 cmp = gen_float_relational (test_code, cmp0, cmp1);
822 /* Generate the branch. */
824 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
833 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
834 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
841 gen_conditional_move (enum rtx_code code, enum machine_mode mode,
848 /* Jump optimization calls get_condition() which canonicalizes
849 comparisons like (GE x <const>) to (GT x <const-1>).
850 Transform those comparisons back to GE, since that is the
851 comparison supported in Xtensa. We shouldn't have to
852 transform <LE x const> comparisons, because neither
853 xtensa_expand_conditional_branch() nor get_condition() will
856 if ((code == GT) && (op1 == constm1_rtx))
861 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
863 if (boolean_operator (cmp, VOIDmode))
865 /* Swap the operands to make const0 second. */
866 if (op0 == const0_rtx)
872 /* If not comparing against zero, emit a comparison (subtract). */
873 if (op1 != const0_rtx)
875 op0 = expand_binop (SImode, sub_optab, op0, op1,
876 0, 0, OPTAB_LIB_WIDEN);
880 else if (branch_operator (cmp, VOIDmode))
882 /* Swap the operands to make const0 second. */
883 if (op0 == const0_rtx)
890 case LT: code = GE; break;
891 case GE: code = LT; break;
892 default: gcc_unreachable ();
896 if (op1 != const0_rtx)
902 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
905 if (TARGET_HARD_FLOAT && mode == SFmode)
906 return gen_float_relational (code, op0, op1);
913 xtensa_expand_conditional_move (rtx *operands, int isflt)
915 rtx dest = operands[0];
916 rtx cmp = operands[1];
917 enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0));
918 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
920 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode,
921 XEXP (cmp, 0), XEXP (cmp, 1))))
925 gen_fn = (cmp_mode == SImode
926 ? gen_movsfcc_internal0
927 : gen_movsfcc_internal1);
929 gen_fn = (cmp_mode == SImode
930 ? gen_movsicc_internal0
931 : gen_movsicc_internal1);
933 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp));
939 xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode)
941 rtx dest = operands[0];
943 rtx one_tmp, zero_tmp;
944 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
946 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode,
947 operands[2], operands[3])))
950 one_tmp = gen_reg_rtx (SImode);
951 zero_tmp = gen_reg_rtx (SImode);
952 emit_insn (gen_movsi (one_tmp, const_true_rtx));
953 emit_insn (gen_movsi (zero_tmp, const0_rtx));
955 gen_fn = (cmp_mode == SImode
956 ? gen_movsicc_internal0
957 : gen_movsicc_internal1);
958 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
963 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
964 for the output, i.e., the input operands are twice as big as MODE. */
967 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
969 switch (GET_CODE (operands[1]))
972 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
973 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
977 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
978 operands[2] = adjust_address (operands[1], mode, 0);
983 split_double (operands[1], &operands[2], &operands[3]);
990 switch (GET_CODE (operands[0]))
993 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
994 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
998 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
999 operands[0] = adjust_address (operands[0], mode, 0);
1008 /* Emit insns to move operands[1] into operands[0].
1009 Return 1 if we have written out everything that needs to be done to
1010 do the move. Otherwise, return 0 and the caller will emit the move
1014 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
1016 rtx src = operands[1];
1018 if (CONSTANT_P (src)
1019 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
1021 rtx dst = operands[0];
1023 if (xtensa_tls_referenced_p (src))
1027 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
1029 addend = XEXP (XEXP (src, 0), 1);
1030 src = XEXP (XEXP (src, 0), 0);
1033 src = xtensa_legitimize_tls_address (src);
1036 src = gen_rtx_PLUS (mode, src, addend);
1037 src = force_operand (src, dst);
1039 emit_move_insn (dst, src);
1043 if (! TARGET_CONST16)
1045 src = force_const_mem (SImode, src);
1049 /* PC-relative loads are always SImode, and CONST16 is only
1050 supported in the movsi pattern, so add a SUBREG for any other
1055 if (register_operand (dst, mode))
1057 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src);
1062 src = force_reg (SImode, src);
1063 src = gen_lowpart_SUBREG (mode, src);
1069 if (!(reload_in_progress | reload_completed)
1070 && !xtensa_valid_move (mode, operands))
1071 operands[1] = force_reg (mode, operands[1]);
1073 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1075 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1076 instruction won't be recognized after reload, so we remove the
1077 subreg and adjust mem accordingly. */
1078 if (reload_in_progress)
1080 operands[0] = fixup_subreg_mem (operands[0]);
1081 operands[1] = fixup_subreg_mem (operands[1]);
1088 fixup_subreg_mem (rtx x)
1090 if (GET_CODE (x) == SUBREG
1091 && GET_CODE (SUBREG_REG (x)) == REG
1092 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
1095 gen_rtx_SUBREG (GET_MODE (x),
1096 reg_equiv_mem (REGNO (SUBREG_REG (x))),
1098 x = alter_subreg (&temp);
1104 /* Check if an incoming argument in a7 is expected to be used soon and
1105 if OPND is a register or register pair that includes a7. If so,
1106 create a new pseudo and copy a7 into that pseudo at the very
1107 beginning of the function, followed by the special "set_frame_ptr"
1108 unspec_volatile insn. The return value is either the original
1109 operand, if it is not a7, or the new pseudo containing a copy of
1110 the incoming argument. This is necessary because the register
1111 allocator will ignore conflicts with a7 and may either assign some
1112 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1113 the incoming argument in a7. By copying the argument out of a7 as
1114 the very first thing, and then immediately following that with an
1115 unspec_volatile to keep the scheduler away, we should avoid any
1116 problems. Putting the set_frame_ptr insn at the beginning, with
1117 only the a7 copy before it, also makes it easier for the prologue
1118 expander to initialize the frame pointer after the a7 copy and to
1119 fix up the a7 copy to use the stack pointer instead of the frame
1123 xtensa_copy_incoming_a7 (rtx opnd)
1125 rtx entry_insns = 0;
1127 enum machine_mode mode;
1129 if (!cfun->machine->need_a7_copy)
1132 /* This function should never be called again once a7 has been copied. */
1133 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1135 mode = GET_MODE (opnd);
1137 /* The operand using a7 may come in a later instruction, so just return
1138 the original operand if it doesn't use a7. */
1140 if (GET_CODE (reg) == SUBREG)
1142 gcc_assert (SUBREG_BYTE (reg) == 0);
1143 reg = SUBREG_REG (reg);
1145 if (GET_CODE (reg) != REG
1146 || REGNO (reg) > A7_REG
1147 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1150 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1151 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1153 cfun->machine->need_a7_copy = false;
1155 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1156 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1159 tmp = gen_reg_rtx (mode);
1165 /* Copy the value out of A7 here but keep the first word in A6 until
1166 after the set_frame_ptr insn. Otherwise, the register allocator
1167 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1169 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1170 gen_raw_REG (SImode, A7_REG)));
1173 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1176 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1179 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1182 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1188 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1190 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1191 if (mode == DFmode || mode == DImode)
1192 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1193 gen_rtx_REG (SImode, A7_REG - 1)));
1194 entry_insns = get_insns ();
1197 if (cfun->machine->vararg_a7)
1199 /* This is called from within builtin_saveregs, which will insert the
1200 saveregs code at the function entry, ahead of anything placed at
1201 the function entry now. Instead, save the sequence to be inserted
1202 at the beginning of the saveregs code. */
1203 cfun->machine->vararg_a7_copy = entry_insns;
1207 /* Put entry_insns after the NOTE that starts the function. If
1208 this is inside a start_sequence, make the outer-level insn
1209 chain current, so the code is placed at the start of the
1211 push_topmost_sequence ();
1212 /* Do not use entry_of_function() here. This is called from within
1213 expand_function_start, when the CFG still holds GIMPLE. */
1214 emit_insn_after (entry_insns, get_insns ());
1215 pop_topmost_sequence ();
1222 /* Try to expand a block move operation to a sequence of RTL move
1223 instructions. If not optimizing, or if the block size is not a
1224 constant, or if the block is too large, the expansion fails and GCC
1225 falls back to calling memcpy().
1227 operands[0] is the destination
1228 operands[1] is the source
1229 operands[2] is the length
1230 operands[3] is the alignment */
1233 xtensa_expand_block_move (rtx *operands)
1235 static const enum machine_mode mode_from_align[] =
1237 VOIDmode, QImode, HImode, VOIDmode, SImode,
1240 rtx dst_mem = operands[0];
1241 rtx src_mem = operands[1];
1242 HOST_WIDE_INT bytes, align;
1243 int num_pieces, move_ratio;
1245 enum machine_mode mode[2];
1254 /* If this is not a fixed size move, just call memcpy. */
1255 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1258 bytes = INTVAL (operands[2]);
1259 align = INTVAL (operands[3]);
1261 /* Anything to move? */
1265 if (align > MOVE_MAX)
1268 /* Decide whether to expand inline based on the optimization level. */
1271 move_ratio = LARGEST_MOVE_RATIO;
1272 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1273 if (num_pieces > move_ratio)
1276 x = XEXP (dst_mem, 0);
1279 x = force_reg (Pmode, x);
1280 dst_mem = replace_equiv_address (dst_mem, x);
1283 x = XEXP (src_mem, 0);
1286 x = force_reg (Pmode, x);
1287 src_mem = replace_equiv_address (src_mem, x);
1290 active[0] = active[1] = false;
1301 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1302 next_amount = MIN (next_amount, align);
1304 amount[next] = next_amount;
1305 mode[next] = mode_from_align[next_amount];
1306 temp[next] = gen_reg_rtx (mode[next]);
1308 x = adjust_address (src_mem, mode[next], offset_ld);
1309 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1311 offset_ld += next_amount;
1312 bytes -= next_amount;
1313 active[next] = true;
1318 active[phase] = false;
1320 x = adjust_address (dst_mem, mode[phase], offset_st);
1321 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1323 offset_st += amount[phase];
1326 while (active[next]);
1333 xtensa_expand_nonlocal_goto (rtx *operands)
1335 rtx goto_handler = operands[1];
1336 rtx containing_fp = operands[3];
1338 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1339 is too big to generate in-line. */
1341 if (GET_CODE (containing_fp) != REG)
1342 containing_fp = force_reg (Pmode, containing_fp);
1344 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1345 LCT_NORMAL, VOIDmode, 2,
1346 containing_fp, Pmode,
1347 goto_handler, Pmode);
1351 static struct machine_function *
1352 xtensa_init_machine_status (void)
1354 return ggc_alloc_cleared_machine_function ();
1358 /* Shift VAL of mode MODE left by COUNT bits. */
1361 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1363 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1364 NULL_RTX, 1, OPTAB_DIRECT);
1365 return expand_simple_binop (SImode, ASHIFT, val, count,
1366 NULL_RTX, 1, OPTAB_DIRECT);
1370 /* Structure to hold the initial parameters for a compare_and_swap operation
1371 in HImode and QImode. */
1373 struct alignment_context
1375 rtx memsi; /* SI aligned memory location. */
1376 rtx shift; /* Bit offset with regard to lsb. */
1377 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1378 rtx modemaski; /* ~modemask */
1382 /* Initialize structure AC for word access to HI and QI mode memory. */
1385 init_alignment_context (struct alignment_context *ac, rtx mem)
1387 enum machine_mode mode = GET_MODE (mem);
1388 rtx byteoffset = NULL_RTX;
1389 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1392 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1395 /* Alignment is unknown. */
1398 /* Force the address into a register. */
1399 addr = force_reg (Pmode, XEXP (mem, 0));
1401 /* Align it to SImode. */
1402 align = expand_simple_binop (Pmode, AND, addr,
1403 GEN_INT (-GET_MODE_SIZE (SImode)),
1404 NULL_RTX, 1, OPTAB_DIRECT);
1406 ac->memsi = gen_rtx_MEM (SImode, align);
1407 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1408 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1409 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1411 byteoffset = expand_simple_binop (Pmode, AND, addr,
1412 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1413 NULL_RTX, 1, OPTAB_DIRECT);
1416 /* Calculate shiftcount. */
1417 if (TARGET_BIG_ENDIAN)
1419 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1421 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1422 NULL_RTX, 1, OPTAB_DIRECT);
1427 ac->shift = NULL_RTX;
1429 ac->shift = byteoffset;
1432 if (ac->shift != NULL_RTX)
1434 /* Shift is the byte count, but we need the bitcount. */
1435 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1436 GEN_INT (BITS_PER_UNIT),
1437 NULL_RTX, 1, OPTAB_DIRECT);
1438 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1439 GEN_INT (GET_MODE_MASK (mode)),
1441 NULL_RTX, 1, OPTAB_DIRECT);
1444 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1446 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1450 /* Expand an atomic compare and swap operation for HImode and QImode.
1451 MEM is the memory location, CMP the old value to compare MEM with
1452 and NEW_RTX the value to set if CMP == MEM. */
1455 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx)
1457 enum machine_mode mode = GET_MODE (mem);
1458 struct alignment_context ac;
1459 rtx tmp, cmpv, newv, val;
1460 rtx oldval = gen_reg_rtx (SImode);
1461 rtx res = gen_reg_rtx (SImode);
1462 rtx csloop = gen_label_rtx ();
1463 rtx csend = gen_label_rtx ();
1465 init_alignment_context (&ac, mem);
1467 if (ac.shift != NULL_RTX)
1469 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1470 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift);
1473 /* Load the surrounding word into VAL with the MEM value masked out. */
1474 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1475 ac.modemaski, NULL_RTX, 1,
1477 emit_label (csloop);
1479 /* Patch CMP and NEW_RTX into VAL at correct position. */
1480 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1481 NULL_RTX, 1, OPTAB_DIRECT));
1482 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
1483 NULL_RTX, 1, OPTAB_DIRECT));
1485 /* Jump to end if we're done. */
1486 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1487 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1489 /* Check for changes outside mode. */
1490 emit_move_insn (oldval, val);
1491 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1492 val, 1, OPTAB_DIRECT);
1494 emit_move_insn (val, tmp);
1496 /* Loop internal if so. */
1497 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1501 /* Return the correct part of the bitfield. */
1502 convert_move (target,
1503 (ac.shift == NULL_RTX ? res
1504 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1505 NULL_RTX, 1, OPTAB_DIRECT)),
1510 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1511 the default expansion works fine for SImode). MEM is the memory location
1512 and VAL the value to play with. If AFTER is true then store the value
1513 MEM holds after the operation, if AFTER is false then store the value MEM
1514 holds before the operation. If TARGET is zero then discard that value, else
1515 store it to TARGET. */
1518 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1521 enum machine_mode mode = GET_MODE (mem);
1522 struct alignment_context ac;
1523 rtx csloop = gen_label_rtx ();
1525 rtx old = gen_reg_rtx (SImode);
1526 rtx new_rtx = gen_reg_rtx (SImode);
1527 rtx orig = NULL_RTX;
1529 init_alignment_context (&ac, mem);
1531 /* Prepare values before the compare-and-swap loop. */
1532 if (ac.shift != NULL_RTX)
1533 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1538 orig = gen_reg_rtx (SImode);
1539 convert_move (orig, val, 1);
1547 case MULT: /* NAND */
1549 /* val = "11..1<val>11..1" */
1550 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1551 NULL_RTX, 1, OPTAB_DIRECT);
1558 /* Load full word. Subsequent loads are performed by S32C1I. */
1559 cmp = force_reg (SImode, ac.memsi);
1561 emit_label (csloop);
1562 emit_move_insn (old, cmp);
1568 val = expand_simple_binop (SImode, code, old, orig,
1569 NULL_RTX, 1, OPTAB_DIRECT);
1570 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1571 NULL_RTX, 1, OPTAB_DIRECT);
1574 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1575 NULL_RTX, 1, OPTAB_DIRECT);
1576 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1577 new_rtx, 1, OPTAB_DIRECT);
1583 tmp = expand_simple_binop (SImode, code, old, val,
1584 new_rtx, 1, OPTAB_DIRECT);
1587 case MULT: /* NAND */
1588 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1589 NULL_RTX, 1, OPTAB_DIRECT);
1590 tmp = expand_simple_binop (SImode, AND, tmp, val,
1591 new_rtx, 1, OPTAB_DIRECT);
1599 emit_move_insn (new_rtx, tmp);
1600 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx));
1601 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1605 tmp = (after ? new_rtx : cmp);
1606 convert_move (target,
1607 (ac.shift == NULL_RTX ? tmp
1608 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1609 NULL_RTX, 1, OPTAB_DIRECT)),
1616 xtensa_setup_frame_addresses (void)
1618 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1619 cfun->machine->accesses_prev_frame = 1;
1622 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1623 LCT_NORMAL, VOIDmode, 0);
1627 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1628 a comment showing where the end of the loop is. However, if there is a
1629 label or a branch at the end of the loop then we need to place a nop
1630 there. If the loop ends with a label we need the nop so that branches
1631 targeting that label will target the nop (and thus remain in the loop),
1632 instead of targeting the instruction after the loop (and thus exiting
1633 the loop). If the loop ends with a branch, we need the nop in case the
1634 branch is targeting a location inside the loop. When the branch
1635 executes it will cause the loop count to be decremented even if it is
1636 taken (because it is the last instruction in the loop), so we need to
1637 nop after the branch to prevent the loop count from being decremented
1638 when the branch is taken. */
1641 xtensa_emit_loop_end (rtx insn, rtx *operands)
1645 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1647 switch (GET_CODE (insn))
1654 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1660 rtx body = PATTERN (insn);
1662 if (GET_CODE (body) == JUMP_INSN)
1664 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1667 else if ((GET_CODE (body) != USE)
1668 && (GET_CODE (body) != CLOBBER))
1675 output_asm_insn ("# loop end for %0", operands);
1680 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1682 static char result[64];
1686 code = GET_CODE (operands[3]);
1689 case EQ: op = inverted ? "ne" : "eq"; break;
1690 case NE: op = inverted ? "eq" : "ne"; break;
1691 case LT: op = inverted ? "ge" : "lt"; break;
1692 case GE: op = inverted ? "lt" : "ge"; break;
1693 case LTU: op = inverted ? "geu" : "ltu"; break;
1694 case GEU: op = inverted ? "ltu" : "geu"; break;
1695 default: gcc_unreachable ();
1700 if (INTVAL (operands[1]) == 0)
1701 sprintf (result, "b%sz%s\t%%0, %%2", op,
1702 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1704 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1707 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1714 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1716 static char result[64];
1719 switch (GET_CODE (operands[3]))
1721 case EQ: op = inverted ? "bs" : "bc"; break;
1722 case NE: op = inverted ? "bc" : "bs"; break;
1723 default: gcc_unreachable ();
1728 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1729 operands[1] = GEN_INT (bitnum);
1730 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1733 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1740 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1742 static char result[64];
1746 code = GET_CODE (operands[4]);
1751 case EQ: op = inverted ? "t" : "f"; break;
1752 case NE: op = inverted ? "f" : "t"; break;
1753 default: gcc_unreachable ();
1760 case EQ: op = inverted ? "nez" : "eqz"; break;
1761 case NE: op = inverted ? "eqz" : "nez"; break;
1762 case LT: op = inverted ? "gez" : "ltz"; break;
1763 case GE: op = inverted ? "ltz" : "gez"; break;
1764 default: gcc_unreachable ();
1768 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1769 op, isfp ? ".s" : "", inverted ? 3 : 2);
1775 xtensa_emit_call (int callop, rtx *operands)
1777 static char result[64];
1778 rtx tgt = operands[callop];
1780 if (GET_CODE (tgt) == CONST_INT)
1781 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1782 else if (register_operand (tgt, VOIDmode))
1783 sprintf (result, "callx8\t%%%d", callop);
1785 sprintf (result, "call8\t%%%d", callop);
1792 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1794 /* Allow constant pool addresses. */
1795 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1796 && ! TARGET_CONST16 && constantpool_address_p (addr)
1797 && ! xtensa_tls_referenced_p (addr))
1800 while (GET_CODE (addr) == SUBREG)
1801 addr = SUBREG_REG (addr);
1803 /* Allow base registers. */
1804 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1807 /* Check for "register + offset" addressing. */
1808 if (GET_CODE (addr) == PLUS)
1810 rtx xplus0 = XEXP (addr, 0);
1811 rtx xplus1 = XEXP (addr, 1);
1812 enum rtx_code code0;
1813 enum rtx_code code1;
1815 while (GET_CODE (xplus0) == SUBREG)
1816 xplus0 = SUBREG_REG (xplus0);
1817 code0 = GET_CODE (xplus0);
1819 while (GET_CODE (xplus1) == SUBREG)
1820 xplus1 = SUBREG_REG (xplus1);
1821 code1 = GET_CODE (xplus1);
1823 /* Swap operands if necessary so the register is first. */
1824 if (code0 != REG && code1 == REG)
1826 xplus0 = XEXP (addr, 1);
1827 xplus1 = XEXP (addr, 0);
1828 code0 = GET_CODE (xplus0);
1829 code1 = GET_CODE (xplus1);
1832 if (code0 == REG && BASE_REG_P (xplus0, strict)
1833 && code1 == CONST_INT
1834 && xtensa_mem_offset (INTVAL (xplus1), mode))
1842 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1844 static GTY(()) rtx xtensa_tls_module_base_symbol;
1847 xtensa_tls_module_base (void)
1849 if (! xtensa_tls_module_base_symbol)
1851 xtensa_tls_module_base_symbol =
1852 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_");
1853 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol)
1854 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
1857 return xtensa_tls_module_base_symbol;
1862 xtensa_call_tls_desc (rtx sym, rtx *retp)
1864 rtx fn, arg, a10, call_insn, insns;
1867 fn = gen_reg_rtx (Pmode);
1868 arg = gen_reg_rtx (Pmode);
1869 a10 = gen_rtx_REG (Pmode, 10);
1871 emit_insn (gen_tls_func (fn, sym));
1872 emit_insn (gen_tls_arg (arg, sym));
1873 emit_move_insn (a10, arg);
1874 call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx));
1875 CALL_INSN_FUNCTION_USAGE (call_insn)
1876 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, a10),
1877 CALL_INSN_FUNCTION_USAGE (call_insn));
1878 insns = get_insns ();
1887 xtensa_legitimize_tls_address (rtx x)
1889 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
1890 rtx dest, tp, ret, modbase, base, addend, insns;
1892 dest = gen_reg_rtx (Pmode);
1895 case TLS_MODEL_GLOBAL_DYNAMIC:
1896 insns = xtensa_call_tls_desc (x, &ret);
1897 emit_libcall_block (insns, dest, ret, x);
1900 case TLS_MODEL_LOCAL_DYNAMIC:
1901 base = gen_reg_rtx (Pmode);
1902 modbase = xtensa_tls_module_base ();
1903 insns = xtensa_call_tls_desc (modbase, &ret);
1904 emit_libcall_block (insns, base, ret, modbase);
1905 addend = force_reg (SImode, gen_sym_DTPOFF (x));
1906 emit_insn (gen_addsi3 (dest, base, addend));
1909 case TLS_MODEL_INITIAL_EXEC:
1910 case TLS_MODEL_LOCAL_EXEC:
1911 tp = gen_reg_rtx (SImode);
1912 emit_insn (gen_load_tp (tp));
1913 addend = force_reg (SImode, gen_sym_TPOFF (x));
1914 emit_insn (gen_addsi3 (dest, tp, addend));
1926 xtensa_legitimize_address (rtx x,
1927 rtx oldx ATTRIBUTE_UNUSED,
1928 enum machine_mode mode)
1930 if (xtensa_tls_symbol_p (x))
1931 return xtensa_legitimize_tls_address (x);
1933 if (GET_CODE (x) == PLUS)
1935 rtx plus0 = XEXP (x, 0);
1936 rtx plus1 = XEXP (x, 1);
1938 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1940 plus0 = XEXP (x, 1);
1941 plus1 = XEXP (x, 0);
1944 /* Try to split up the offset to use an ADDMI instruction. */
1945 if (GET_CODE (plus0) == REG
1946 && GET_CODE (plus1) == CONST_INT
1947 && !xtensa_mem_offset (INTVAL (plus1), mode)
1948 && !xtensa_simm8 (INTVAL (plus1))
1949 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1950 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1952 rtx temp = gen_reg_rtx (Pmode);
1953 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1954 emit_insn (gen_rtx_SET (Pmode, temp,
1955 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1956 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1963 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
1965 Treat constant-pool references as "mode dependent" since they can
1966 only be accessed with SImode loads. This works around a bug in the
1967 combiner where a constant pool reference is temporarily converted
1968 to an HImode load, which is then assumed to zero-extend based on
1969 our definition of LOAD_EXTEND_OP. This is wrong because the high
1970 bits of a 16-bit value in the constant pool are now sign-extended
1974 xtensa_mode_dependent_address_p (const_rtx addr)
1976 return constantpool_address_p (addr);
1979 /* Helper for xtensa_tls_referenced_p. */
1982 xtensa_tls_referenced_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1984 if (GET_CODE (*x) == SYMBOL_REF)
1985 return SYMBOL_REF_TLS_MODEL (*x) != 0;
1987 /* Ignore TLS references that have already been legitimized. */
1988 if (GET_CODE (*x) == UNSPEC)
1990 switch (XINT (*x, 1))
1994 case UNSPEC_TLS_FUNC:
1995 case UNSPEC_TLS_ARG:
1996 case UNSPEC_TLS_CALL:
2007 /* Return TRUE if X contains any TLS symbol references. */
2010 xtensa_tls_referenced_p (rtx x)
2012 if (! TARGET_HAVE_TLS)
2015 return for_each_rtx (&x, xtensa_tls_referenced_p_1, NULL);
2019 /* Return the debugger register number to use for 'regno'. */
2022 xtensa_dbx_register_number (int regno)
2026 if (GP_REG_P (regno))
2028 regno -= GP_REG_FIRST;
2031 else if (BR_REG_P (regno))
2033 regno -= BR_REG_FIRST;
2036 else if (FP_REG_P (regno))
2038 regno -= FP_REG_FIRST;
2041 else if (ACC_REG_P (regno))
2043 first = 0x200; /* Start of Xtensa special registers. */
2044 regno = 16; /* ACCLO is special register 16. */
2047 /* When optimizing, we sometimes get asked about pseudo-registers
2048 that don't represent hard registers. Return 0 for these. */
2052 return first + regno;
2056 /* Argument support functions. */
2058 /* Initialize CUMULATIVE_ARGS for a function. */
2061 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
2064 cum->incoming = incoming;
2068 /* Advance the argument to the next argument position. */
2071 xtensa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2072 const_tree type, bool named ATTRIBUTE_UNUSED)
2077 arg_words = &cum->arg_words;
2078 max = MAX_ARGS_IN_REGISTERS;
2080 words = (((mode != BLKmode)
2081 ? (int) GET_MODE_SIZE (mode)
2082 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2084 if (*arg_words < max
2085 && (targetm.calls.must_pass_in_stack (mode, type)
2086 || *arg_words + words > max))
2089 *arg_words += words;
2093 /* Return an RTL expression containing the register for the given mode,
2094 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2095 if this is an incoming argument to the current function. */
2098 xtensa_function_arg_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2099 const_tree type, bool incoming_p)
2101 int regbase, words, max;
2105 arg_words = &cum->arg_words;
2106 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
2107 max = MAX_ARGS_IN_REGISTERS;
2109 words = (((mode != BLKmode)
2110 ? (int) GET_MODE_SIZE (mode)
2111 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2113 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
2115 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
2116 *arg_words = (*arg_words + align - 1) & -align;
2119 if (*arg_words + words > max)
2122 regno = regbase + *arg_words;
2124 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
2125 cfun->machine->need_a7_copy = true;
2127 return gen_rtx_REG (mode, regno);
2130 /* Implement TARGET_FUNCTION_ARG. */
2133 xtensa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2134 const_tree type, bool named ATTRIBUTE_UNUSED)
2136 return xtensa_function_arg_1 (cum, mode, type, false);
2139 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2142 xtensa_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2143 const_tree type, bool named ATTRIBUTE_UNUSED)
2145 return xtensa_function_arg_1 (cum, mode, type, true);
2149 xtensa_function_arg_boundary (enum machine_mode mode, const_tree type)
2151 unsigned int alignment;
2153 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
2154 if (alignment < PARM_BOUNDARY)
2155 alignment = PARM_BOUNDARY;
2156 if (alignment > STACK_BOUNDARY)
2157 alignment = STACK_BOUNDARY;
2163 xtensa_return_in_msb (const_tree valtype)
2165 return (TARGET_BIG_ENDIAN
2166 && AGGREGATE_TYPE_P (valtype)
2167 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
2172 xtensa_option_override (void)
2175 enum machine_mode mode;
2177 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
2178 error ("boolean registers required for the floating-point option");
2180 /* Set up array giving whether a given register can hold a given mode. */
2181 for (mode = VOIDmode;
2182 mode != MAX_MACHINE_MODE;
2183 mode = (enum machine_mode) ((int) mode + 1))
2185 int size = GET_MODE_SIZE (mode);
2186 enum mode_class mclass = GET_MODE_CLASS (mode);
2188 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2192 if (ACC_REG_P (regno))
2193 temp = (TARGET_MAC16
2194 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD));
2195 else if (GP_REG_P (regno))
2196 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
2197 else if (FP_REG_P (regno))
2198 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
2199 else if (BR_REG_P (regno))
2200 temp = (TARGET_BOOLEANS && (mode == CCmode));
2204 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
2208 init_machine_status = xtensa_init_machine_status;
2210 /* Check PIC settings. PIC is only supported when using L32R
2211 instructions, and some targets need to always use PIC. */
2212 if (flag_pic && TARGET_CONST16)
2213 error ("-f%s is not supported with CONST16 instructions",
2214 (flag_pic > 1 ? "PIC" : "pic"));
2215 else if (TARGET_FORCE_NO_PIC)
2217 else if (XTENSA_ALWAYS_PIC)
2220 error ("PIC is required but not supported with CONST16 instructions");
2223 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2226 if (flag_pic && !flag_pie)
2229 /* Hot/cold partitioning does not work on this architecture, because of
2230 constant pools (the load instruction cannot necessarily reach that far).
2231 Therefore disable it on this architecture. */
2232 if (flag_reorder_blocks_and_partition)
2234 flag_reorder_blocks_and_partition = 0;
2235 flag_reorder_blocks = 1;
2239 /* A C compound statement to output to stdio stream STREAM the
2240 assembler syntax for an instruction operand X. X is an RTL
2243 CODE is a value that can be used to specify one of several ways
2244 of printing the operand. It is used when identical operands
2245 must be printed differently depending on the context. CODE
2246 comes from the '%' specification that was used to request
2247 printing of the operand. If the specification was just '%DIGIT'
2248 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2249 is the ASCII code for LTR.
2251 If X is a register, this macro should print the register's name.
2252 The names can be found in an array 'reg_names' whose type is
2253 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2255 When the machine description has a specification '%PUNCT' (a '%'
2256 followed by a punctuation character), this macro is called with
2257 a null pointer for X and the punctuation character for CODE.
2259 'a', 'c', 'l', and 'n' are reserved.
2261 The Xtensa specific codes are:
2263 'd' CONST_INT, print as signed decimal
2264 'x' CONST_INT, print as signed hexadecimal
2265 'K' CONST_INT, print number of bits in mask for EXTUI
2266 'R' CONST_INT, print (X & 0x1f)
2267 'L' CONST_INT, print ((32 - X) & 0x1f)
2268 'D' REG, print second register of double-word register operand
2269 'N' MEM, print address of next word following a memory operand
2270 'v' MEM, if memory reference is volatile, output a MEMW before it
2271 't' any constant, add "@h" suffix for top 16 bits
2272 'b' any constant, add "@l" suffix for bottom 16 bits
2276 printx (FILE *file, signed int val)
2278 /* Print a hexadecimal value in a nice way. */
2279 if ((val > -0xa) && (val < 0xa))
2280 fprintf (file, "%d", val);
2282 fprintf (file, "-0x%x", -val);
2284 fprintf (file, "0x%x", val);
2289 print_operand (FILE *file, rtx x, int letter)
2292 error ("PRINT_OPERAND null pointer");
2297 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2298 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
2300 output_operand_lossage ("invalid %%D value");
2304 if (GET_CODE (x) == MEM)
2306 /* For a volatile memory reference, emit a MEMW before the
2308 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2309 fprintf (file, "memw\n\t");
2312 output_operand_lossage ("invalid %%v value");
2316 if (GET_CODE (x) == MEM
2317 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2319 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2320 output_address (XEXP (x, 0));
2323 output_operand_lossage ("invalid %%N value");
2327 if (GET_CODE (x) == CONST_INT)
2330 unsigned val = INTVAL (x);
2336 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2337 fatal_insn ("invalid mask", x);
2339 fprintf (file, "%d", num_bits);
2342 output_operand_lossage ("invalid %%K value");
2346 if (GET_CODE (x) == CONST_INT)
2347 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2349 output_operand_lossage ("invalid %%L value");
2353 if (GET_CODE (x) == CONST_INT)
2354 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2356 output_operand_lossage ("invalid %%R value");
2360 if (GET_CODE (x) == CONST_INT)
2361 printx (file, INTVAL (x));
2363 output_operand_lossage ("invalid %%x value");
2367 if (GET_CODE (x) == CONST_INT)
2368 fprintf (file, "%ld", INTVAL (x));
2370 output_operand_lossage ("invalid %%d value");
2375 if (GET_CODE (x) == CONST_INT)
2377 printx (file, INTVAL (x));
2378 fputs (letter == 't' ? "@h" : "@l", file);
2380 else if (GET_CODE (x) == CONST_DOUBLE)
2383 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2384 if (GET_MODE (x) == SFmode)
2387 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2388 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2391 output_operand_lossage ("invalid %%t/%%b value");
2393 else if (GET_CODE (x) == CONST)
2395 /* X must be a symbolic constant on ELF. Write an expression
2396 suitable for 'const16' that sets the high or low 16 bits. */
2397 if (GET_CODE (XEXP (x, 0)) != PLUS
2398 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2399 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2400 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2401 output_operand_lossage ("invalid %%t/%%b value");
2402 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2403 fputs (letter == 't' ? "@h" : "@l", file);
2404 /* There must be a non-alphanumeric character between 'h' or 'l'
2405 and the number. The '-' is added by print_operand() already. */
2406 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2408 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2412 output_addr_const (file, x);
2413 fputs (letter == 't' ? "@h" : "@l", file);
2418 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2419 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2420 else if (GET_CODE (x) == MEM)
2421 output_address (XEXP (x, 0));
2422 else if (GET_CODE (x) == CONST_INT)
2423 fprintf (file, "%ld", INTVAL (x));
2425 output_addr_const (file, x);
2430 /* A C compound statement to output to stdio stream STREAM the
2431 assembler syntax for an instruction operand that is a memory
2432 reference whose address is ADDR. ADDR is an RTL expression. */
2435 print_operand_address (FILE *file, rtx addr)
2438 error ("PRINT_OPERAND_ADDRESS, null pointer");
2440 switch (GET_CODE (addr))
2443 fatal_insn ("invalid address", addr);
2447 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2453 rtx offset = (rtx)0;
2454 rtx arg0 = XEXP (addr, 0);
2455 rtx arg1 = XEXP (addr, 1);
2457 if (GET_CODE (arg0) == REG)
2462 else if (GET_CODE (arg1) == REG)
2468 fatal_insn ("no register in address", addr);
2470 if (CONSTANT_P (offset))
2472 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2473 output_addr_const (file, offset);
2476 fatal_insn ("address offset not a constant", addr);
2484 output_addr_const (file, addr);
2489 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2492 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2494 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2496 switch (XINT (x, 1))
2499 output_addr_const (fp, XVECEXP (x, 0, 0));
2500 fputs ("@TPOFF", fp);
2503 output_addr_const (fp, XVECEXP (x, 0, 0));
2504 fputs ("@DTPOFF", fp);
2509 output_addr_const (fp, XVECEXP (x, 0, 0));
2523 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2530 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2532 switch (GET_MODE_CLASS (mode))
2535 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2537 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2541 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2542 if (HOST_BITS_PER_LONG > 32)
2543 value_long[0] &= 0xffffffff;
2544 fprintf (file, "0x%08lx\n", value_long[0]);
2548 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2549 if (HOST_BITS_PER_LONG > 32)
2551 value_long[0] &= 0xffffffff;
2552 value_long[1] &= 0xffffffff;
2554 fprintf (file, "0x%08lx, 0x%08lx\n",
2555 value_long[0], value_long[1]);
2565 case MODE_PARTIAL_INT:
2566 size = GET_MODE_SIZE (mode);
2570 output_addr_const (file, x);
2575 split_double (x, &first, &second);
2576 output_addr_const (file, first);
2578 output_addr_const (file, second);
2593 /* Return the bytes needed to compute the frame pointer from the current
2596 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2597 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2600 compute_frame_size (int size)
2602 /* Add space for the incoming static chain value. */
2603 if (cfun->static_chain_decl != NULL)
2604 size += (1 * UNITS_PER_WORD);
2606 xtensa_current_frame_size =
2607 XTENSA_STACK_ALIGN (size
2608 + crtl->outgoing_args_size
2609 + (WINDOW_SIZE * UNITS_PER_WORD));
2610 return xtensa_current_frame_size;
2615 xtensa_frame_pointer_required (void)
2617 /* The code to expand builtin_frame_addr and builtin_return_addr
2618 currently uses the hard_frame_pointer instead of frame_pointer.
2619 This seems wrong but maybe it's necessary for other architectures.
2620 This function is derived from the i386 code. */
2622 if (cfun->machine->accesses_prev_frame)
2629 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2630 and the total number of words must be a multiple of 128 bits. */
2631 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2634 xtensa_expand_prologue (void)
2636 HOST_WIDE_INT total_size;
2640 total_size = compute_frame_size (get_frame_size ());
2641 size_rtx = GEN_INT (total_size);
2643 if (total_size < (1 << (12+3)))
2644 insn = emit_insn (gen_entry (size_rtx));
2647 /* Use a8 as a temporary since a0-a7 may be live. */
2648 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2649 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2650 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2651 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2652 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2655 if (frame_pointer_needed)
2657 if (cfun->machine->set_frame_ptr_insn)
2661 push_topmost_sequence ();
2662 first = get_insns ();
2663 pop_topmost_sequence ();
2665 /* For all instructions prior to set_frame_ptr_insn, replace
2666 hard_frame_pointer references with stack_pointer. */
2668 insn != cfun->machine->set_frame_ptr_insn;
2669 insn = NEXT_INSN (insn))
2673 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2674 hard_frame_pointer_rtx,
2676 df_insn_rescan (insn);
2681 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2682 stack_pointer_rtx));
2685 /* Create a note to describe the CFA. Because this is only used to set
2686 DW_AT_frame_base for debug info, don't bother tracking changes through
2687 each instruction in the prologue. It just takes up space. */
2688 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2689 ? hard_frame_pointer_rtx
2690 : stack_pointer_rtx),
2691 plus_constant (stack_pointer_rtx, -total_size));
2692 RTX_FRAME_RELATED_P (insn) = 1;
2693 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx);
2697 /* Clear variables at function end. */
2700 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2701 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2703 xtensa_current_frame_size = 0;
2708 xtensa_return_addr (int count, rtx frame)
2710 rtx result, retaddr, curaddr, label;
2713 retaddr = gen_rtx_REG (Pmode, A0_REG);
2716 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2717 addr = memory_address (Pmode, addr);
2718 retaddr = gen_reg_rtx (Pmode);
2719 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2722 /* The 2 most-significant bits of the return address on Xtensa hold
2723 the register window size. To get the real return address, these
2724 bits must be replaced with the high bits from some address in the
2727 /* Get the 2 high bits of a local label in the code. */
2728 curaddr = gen_reg_rtx (Pmode);
2729 label = gen_label_rtx ();
2731 LABEL_PRESERVE_P (label) = 1;
2732 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2733 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2734 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2736 /* Clear the 2 high bits of the return address. */
2737 result = gen_reg_rtx (Pmode);
2738 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2739 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2741 /* Combine them to get the result. */
2742 emit_insn (gen_iorsi3 (result, result, curaddr));
2747 /* Create the va_list data type.
2749 This structure is set up by __builtin_saveregs. The __va_reg field
2750 points to a stack-allocated region holding the contents of the
2751 incoming argument registers. The __va_ndx field is an index
2752 initialized to the position of the first unnamed (variable)
2753 argument. This same index is also used to address the arguments
2754 passed in memory. Thus, the __va_stk field is initialized to point
2755 to the position of the first argument in memory offset to account
2756 for the arguments passed in registers and to account for the size
2757 of the argument registers not being 16-byte aligned. E.G., there
2758 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2759 for the first stack argument to have the maximal alignment of 16
2760 bytes, so we offset the __va_stk address by 32 bytes so that
2761 __va_stk[32] references the first argument on the stack. */
2764 xtensa_build_builtin_va_list (void)
2766 tree f_stk, f_reg, f_ndx, record, type_decl;
2768 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2769 type_decl = build_decl (BUILTINS_LOCATION,
2770 TYPE_DECL, get_identifier ("__va_list_tag"), record);
2772 f_stk = build_decl (BUILTINS_LOCATION,
2773 FIELD_DECL, get_identifier ("__va_stk"),
2775 f_reg = build_decl (BUILTINS_LOCATION,
2776 FIELD_DECL, get_identifier ("__va_reg"),
2778 f_ndx = build_decl (BUILTINS_LOCATION,
2779 FIELD_DECL, get_identifier ("__va_ndx"),
2782 DECL_FIELD_CONTEXT (f_stk) = record;
2783 DECL_FIELD_CONTEXT (f_reg) = record;
2784 DECL_FIELD_CONTEXT (f_ndx) = record;
2786 TYPE_STUB_DECL (record) = type_decl;
2787 TYPE_NAME (record) = type_decl;
2788 TYPE_FIELDS (record) = f_stk;
2789 DECL_CHAIN (f_stk) = f_reg;
2790 DECL_CHAIN (f_reg) = f_ndx;
2792 layout_type (record);
2797 /* Save the incoming argument registers on the stack. Returns the
2798 address of the saved registers. */
2801 xtensa_builtin_saveregs (void)
2804 int arg_words = crtl->args.info.arg_words;
2805 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2810 /* Allocate the general-purpose register space. */
2811 gp_regs = assign_stack_local
2812 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2813 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2815 /* Now store the incoming registers. */
2816 cfun->machine->need_a7_copy = true;
2817 cfun->machine->vararg_a7 = true;
2818 move_block_from_reg (GP_ARG_FIRST + arg_words,
2819 adjust_address (gp_regs, BLKmode,
2820 arg_words * UNITS_PER_WORD),
2822 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2823 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2825 return XEXP (gp_regs, 0);
2829 /* Implement `va_start' for varargs and stdarg. We look at the
2830 current function to fill in an initial va_list. */
2833 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2841 arg_words = crtl->args.info.arg_words;
2843 f_stk = TYPE_FIELDS (va_list_type_node);
2844 f_reg = DECL_CHAIN (f_stk);
2845 f_ndx = DECL_CHAIN (f_reg);
2847 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2848 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2850 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2853 /* Call __builtin_saveregs; save the result in __va_reg */
2854 u = make_tree (sizetype, expand_builtin_saveregs ());
2855 u = fold_convert (ptr_type_node, u);
2856 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2857 TREE_SIDE_EFFECTS (t) = 1;
2858 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2860 /* Set the __va_stk member to ($arg_ptr - 32). */
2861 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2862 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2863 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2864 TREE_SIDE_EFFECTS (t) = 1;
2865 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2867 /* Set the __va_ndx member. If the first variable argument is on
2868 the stack, adjust __va_ndx by 2 words to account for the extra
2869 alignment offset for __va_stk. */
2870 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2872 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2873 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2874 TREE_SIDE_EFFECTS (t) = 1;
2875 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2879 /* Implement `va_arg'. */
2882 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2883 gimple_seq *post_p ATTRIBUTE_UNUSED)
2888 tree type_size, array, orig_ndx, addr, size, va_size, t;
2889 tree lab_false, lab_over, lab_false2;
2892 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2894 type = build_pointer_type (type);
2896 /* Handle complex values as separate real and imaginary parts. */
2897 if (TREE_CODE (type) == COMPLEX_TYPE)
2899 tree real_part, imag_part;
2901 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2903 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2905 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2908 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2910 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2913 f_stk = TYPE_FIELDS (va_list_type_node);
2914 f_reg = DECL_CHAIN (f_stk);
2915 f_ndx = DECL_CHAIN (f_reg);
2917 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2919 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2921 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2924 type_size = size_in_bytes (type);
2925 va_size = round_up (type_size, UNITS_PER_WORD);
2926 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2929 /* First align __va_ndx if necessary for this arg:
2931 orig_ndx = (AP).__va_ndx;
2932 if (__alignof__ (TYPE) > 4 )
2933 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2934 & -__alignof__ (TYPE)); */
2936 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2938 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2940 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2942 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2943 build_int_cst (integer_type_node, align - 1));
2944 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2945 build_int_cst (integer_type_node, -align));
2946 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2950 /* Increment __va_ndx to point past the argument:
2952 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2954 t = fold_convert (integer_type_node, va_size);
2955 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2956 gimplify_assign (unshare_expr (ndx), t, pre_p);
2959 /* Check if the argument is in registers:
2961 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2962 && !must_pass_in_stack (type))
2963 __array = (AP).__va_reg; */
2965 array = create_tmp_var (ptr_type_node, NULL);
2968 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2970 lab_false = create_artificial_label (UNKNOWN_LOCATION);
2971 lab_over = create_artificial_label (UNKNOWN_LOCATION);
2973 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2974 build_int_cst (integer_type_node,
2975 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2976 t = build3 (COND_EXPR, void_type_node, t,
2977 build1 (GOTO_EXPR, void_type_node, lab_false),
2979 gimplify_and_add (t, pre_p);
2981 gimplify_assign (unshare_expr (array), reg, pre_p);
2983 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2984 gimplify_and_add (t, pre_p);
2986 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2987 gimplify_and_add (t, pre_p);
2991 /* ...otherwise, the argument is on the stack (never split between
2992 registers and the stack -- change __va_ndx if necessary):
2996 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2997 (AP).__va_ndx = 32 + __va_size (TYPE);
2998 __array = (AP).__va_stk;
3001 lab_false2 = create_artificial_label (UNKNOWN_LOCATION);
3003 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
3004 build_int_cst (integer_type_node,
3005 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
3006 t = build3 (COND_EXPR, void_type_node, t,
3007 build1 (GOTO_EXPR, void_type_node, lab_false2),
3009 gimplify_and_add (t, pre_p);
3011 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
3012 t = fold_convert (integer_type_node, t);
3013 gimplify_assign (unshare_expr (ndx), t, pre_p);
3015 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
3016 gimplify_and_add (t, pre_p);
3018 gimplify_assign (array, stk, pre_p);
3022 t = build1 (LABEL_EXPR, void_type_node, lab_over);
3023 gimplify_and_add (t, pre_p);
3027 /* Given the base array pointer (__array) and index to the subsequent
3028 argument (__va_ndx), find the address:
3030 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
3034 The results are endian-dependent because values smaller than one word
3035 are aligned differently. */
3038 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
3040 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
3041 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
3042 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
3043 unshare_expr (type_size));
3047 size = unshare_expr (va_size);
3049 t = fold_convert (sizetype, unshare_expr (ndx));
3050 t = build2 (MINUS_EXPR, sizetype, t, size);
3051 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t);
3053 addr = fold_convert (build_pointer_type (type), addr);
3055 addr = build_va_arg_indirect_ref (addr);
3056 return build_va_arg_indirect_ref (addr);
3064 XTENSA_BUILTIN_UMULSIDI3,
3065 XTENSA_BUILTIN_THREAD_POINTER,
3066 XTENSA_BUILTIN_SET_THREAD_POINTER,
3072 xtensa_init_builtins (void)
3076 ftype = build_function_type_list (unsigned_intDI_type_node,
3077 unsigned_intSI_type_node,
3078 unsigned_intSI_type_node, NULL_TREE);
3080 decl = add_builtin_function ("__builtin_umulsidi3", ftype,
3081 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
3082 "__umulsidi3", NULL_TREE);
3083 TREE_NOTHROW (decl) = 1;
3084 TREE_READONLY (decl) = 1;
3086 if (TARGET_THREADPTR)
3088 ftype = build_function_type (ptr_type_node, void_list_node);
3089 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
3090 XTENSA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
3092 TREE_READONLY (decl) = 1;
3093 TREE_NOTHROW (decl) = 1;
3095 ftype = build_function_type_list (void_type_node, ptr_type_node,
3097 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
3098 XTENSA_BUILTIN_SET_THREAD_POINTER,
3099 BUILT_IN_MD, NULL, NULL_TREE);
3100 TREE_NOTHROW (decl) = 1;
3106 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
3107 bool ignore ATTRIBUTE_UNUSED)
3109 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3114 case XTENSA_BUILTIN_UMULSIDI3:
3117 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
3118 || TARGET_MUL32_HIGH)
3119 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
3120 fold_convert (unsigned_intDI_type_node, arg0),
3121 fold_convert (unsigned_intDI_type_node, arg1));
3124 case XTENSA_BUILTIN_THREAD_POINTER:
3125 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3129 internal_error ("bad builtin code");
3138 xtensa_expand_builtin (tree exp, rtx target,
3139 rtx subtarget ATTRIBUTE_UNUSED,
3140 enum machine_mode mode ATTRIBUTE_UNUSED,
3143 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
3144 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3149 case XTENSA_BUILTIN_UMULSIDI3:
3150 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3151 __umulsidi3 function when the Xtensa configuration can directly
3152 implement it. If not, just call the function. */
3153 return expand_call (exp, target, ignore);
3155 case XTENSA_BUILTIN_THREAD_POINTER:
3156 if (!target || !register_operand (target, Pmode))
3157 target = gen_reg_rtx (Pmode);
3158 emit_insn (gen_load_tp (target));
3161 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3162 arg = expand_normal (CALL_EXPR_ARG (exp, 0));
3163 if (!register_operand (arg, Pmode))
3164 arg = copy_to_mode_reg (Pmode, arg);
3165 emit_insn (gen_set_tp (arg));
3169 internal_error ("bad builtin code");
3174 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */
3177 xtensa_preferred_reload_class (rtx x, reg_class_t rclass)
3179 if (CONSTANT_P (x) && CONST_DOUBLE_P (x))
3182 /* Don't use the stack pointer or hard frame pointer for reloads!
3183 The hard frame pointer would normally be OK except that it may
3184 briefly hold an incoming argument in the prologue, and reload
3185 won't know that it is live because the hard frame pointer is
3186 treated specially. */
3188 if (rclass == AR_REGS || rclass == GR_REGS)
3194 /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
3197 xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED,
3200 /* Don't use the stack pointer or hard frame pointer for reloads!
3201 The hard frame pointer would normally be OK except that it may
3202 briefly hold an incoming argument in the prologue, and reload
3203 won't know that it is live because the hard frame pointer is
3204 treated specially. */
3206 if (rclass == AR_REGS || rclass == GR_REGS)
3212 /* Worker function for TARGET_SECONDARY_RELOAD. */
3215 xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
3216 enum machine_mode mode, secondary_reload_info *sri)
3220 if (in_p && constantpool_mem_p (x))
3222 if (rclass == FP_REGS)
3226 sri->icode = CODE_FOR_reloadqi_literal;
3227 else if (mode == HImode)
3228 sri->icode = CODE_FOR_reloadhi_literal;
3231 regno = xt_true_regnum (x);
3232 if (ACC_REG_P (regno))
3233 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS);
3234 if (rclass == ACC_REG)
3235 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
3242 order_regs_for_local_alloc (void)
3244 if (!leaf_function_p ())
3246 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
3247 FIRST_PSEUDO_REGISTER * sizeof (int));
3251 int i, num_arg_regs;
3254 /* Use the AR registers in increasing order (skipping a0 and a1)
3255 but save the incoming argument registers for a last resort. */
3256 num_arg_regs = crtl->args.info.arg_words;
3257 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
3258 num_arg_regs = MAX_ARGS_IN_REGISTERS;
3259 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
3260 reg_alloc_order[nxt++] = i + num_arg_regs;
3261 for (i = 0; i < num_arg_regs; i++)
3262 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
3264 /* List the coprocessor registers in order. */
3265 for (i = 0; i < BR_REG_NUM; i++)
3266 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
3268 /* List the FP registers in order for now. */
3269 for (i = 0; i < 16; i++)
3270 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
3272 /* GCC requires that we list *all* the registers.... */
3273 reg_alloc_order[nxt++] = 0; /* a0 = return address */
3274 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
3275 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
3276 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
3278 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
3283 /* Some Xtensa targets support multiple bss sections. If the section
3284 name ends with ".bss", add SECTION_BSS to the flags. */
3287 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
3289 unsigned int flags = default_section_type_flags (decl, name, reloc);
3292 suffix = strrchr (name, '.');
3293 if (suffix && strcmp (suffix, ".bss") == 0)
3295 if (!decl || (TREE_CODE (decl) == VAR_DECL
3296 && DECL_INITIAL (decl) == NULL_TREE))
3297 flags |= SECTION_BSS; /* @nobits */
3299 warning (0, "only uninitialized variables can be placed in a "
3307 /* The literal pool stays with the function. */
3310 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
3311 rtx x ATTRIBUTE_UNUSED,
3312 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
3314 return function_section (current_function_decl);
3317 /* Worker function for TARGET_REGISTER_MOVE_COST. */
3320 xtensa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
3321 reg_class_t from, reg_class_t to)
3323 if (from == to && from != BR_REGS && to != BR_REGS)
3325 else if (reg_class_subset_p (from, AR_REGS)
3326 && reg_class_subset_p (to, AR_REGS))
3328 else if (reg_class_subset_p (from, AR_REGS) && to == ACC_REG)
3330 else if (from == ACC_REG && reg_class_subset_p (to, AR_REGS))
3336 /* Worker function for TARGET_MEMORY_MOVE_COST. */
3339 xtensa_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
3340 reg_class_t rclass ATTRIBUTE_UNUSED,
3341 bool in ATTRIBUTE_UNUSED)
3346 /* Compute a (partial) cost for rtx X. Return true if the complete
3347 cost has been computed, and false if subexpressions should be
3348 scanned. In either case, *TOTAL contains the cost result. */
3351 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total,
3352 bool speed ATTRIBUTE_UNUSED)
3360 if (xtensa_simm12b (INTVAL (x)))
3367 if (xtensa_simm8 (INTVAL (x))
3368 || xtensa_simm8x256 (INTVAL (x)))
3375 if (xtensa_mask_immediate (INTVAL (x)))
3382 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
3393 /* No way to tell if X is the 2nd operand so be conservative. */
3396 if (xtensa_simm12b (INTVAL (x)))
3398 else if (TARGET_CONST16)
3399 *total = COSTS_N_INSNS (2);
3408 *total = COSTS_N_INSNS (2);
3415 *total = COSTS_N_INSNS (4);
3423 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3425 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3426 *total = COSTS_N_INSNS (num_words);
3428 *total = COSTS_N_INSNS (2*num_words);
3434 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3438 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3442 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3448 if (GET_MODE (x) == DImode)
3449 *total = COSTS_N_INSNS (2);
3451 *total = COSTS_N_INSNS (1);
3457 if (GET_MODE (x) == DImode)
3458 *total = COSTS_N_INSNS (50);
3460 *total = COSTS_N_INSNS (1);
3465 enum machine_mode xmode = GET_MODE (x);
3466 if (xmode == SFmode)
3467 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3468 else if (xmode == DFmode)
3469 *total = COSTS_N_INSNS (50);
3471 *total = COSTS_N_INSNS (4);
3478 enum machine_mode xmode = GET_MODE (x);
3479 if (xmode == SFmode)
3480 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3481 else if (xmode == DFmode || xmode == DImode)
3482 *total = COSTS_N_INSNS (50);
3484 *total = COSTS_N_INSNS (1);
3489 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3494 enum machine_mode xmode = GET_MODE (x);
3495 if (xmode == SFmode)
3496 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3497 else if (xmode == DFmode)
3498 *total = COSTS_N_INSNS (50);
3499 else if (xmode == DImode)
3500 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3501 else if (TARGET_MUL32)
3502 *total = COSTS_N_INSNS (4);
3503 else if (TARGET_MAC16)
3504 *total = COSTS_N_INSNS (16);
3505 else if (TARGET_MUL16)
3506 *total = COSTS_N_INSNS (12);
3508 *total = COSTS_N_INSNS (50);
3515 enum machine_mode xmode = GET_MODE (x);
3516 if (xmode == SFmode)
3518 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3521 else if (xmode == DFmode)
3523 *total = COSTS_N_INSNS (50);
3532 enum machine_mode xmode = GET_MODE (x);
3533 if (xmode == DImode)
3534 *total = COSTS_N_INSNS (50);
3535 else if (TARGET_DIV32)
3536 *total = COSTS_N_INSNS (32);
3538 *total = COSTS_N_INSNS (50);
3543 if (GET_MODE (x) == SFmode)
3544 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3546 *total = COSTS_N_INSNS (50);
3553 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3558 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3563 *total = COSTS_N_INSNS (1);
3571 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3574 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3576 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3577 > 4 * UNITS_PER_WORD);
3580 /* Worker function for TARGET_FUNCTION_VALUE. */
3583 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3586 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3587 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3588 ? SImode : TYPE_MODE (valtype),
3589 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3592 /* Worker function for TARGET_LIBCALL_VALUE. */
3595 xtensa_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
3597 return gen_rtx_REG ((GET_MODE_CLASS (mode) == MODE_INT
3598 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3599 ? SImode : mode, GP_RETURN);
3602 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */
3605 xtensa_function_value_regno_p (const unsigned int regno)
3607 return (regno == GP_RETURN);
3610 /* The static chain is passed in memory. Provide rtx giving 'mem'
3611 expressions that denote where they are stored. */
3614 xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
3616 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx;
3617 return gen_frame_mem (Pmode, plus_constant (base, -5 * UNITS_PER_WORD));
3621 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3622 instruction with a minimal stack frame in order to get some free
3623 registers. Once the actual call target is known, the proper stack frame
3624 size is extracted from the ENTRY instruction at the target and the
3625 current frame is adjusted to match. The trampoline then transfers
3626 control to the instruction following the ENTRY at the target. Note:
3627 this assumes that the target begins with an ENTRY instruction. */
3630 xtensa_asm_trampoline_template (FILE *stream)
3632 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3634 fprintf (stream, "\t.begin no-transform\n");
3635 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3639 /* Save the return address. */
3640 fprintf (stream, "\tmov\ta10, a0\n");
3642 /* Use a CALL0 instruction to skip past the constants and in the
3643 process get the PC into A0. This allows PC-relative access to
3644 the constants without relying on L32R. */
3645 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3648 fprintf (stream, "\tj\t.Lskipconsts\n");
3650 fprintf (stream, "\t.align\t4\n");
3651 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3652 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3653 fprintf (stream, ".Lskipconsts:\n");
3655 /* Load the static chain and function address from the trampoline. */
3658 fprintf (stream, "\taddi\ta0, a0, 3\n");
3659 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3660 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3664 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3665 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3668 /* Store the static chain. */
3669 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3671 /* Set the proper stack pointer value. */
3672 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3673 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3674 TARGET_BIG_ENDIAN ? 8 : 12);
3675 fprintf (stream, "\tslli\ta9, a9, 3\n");
3676 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3677 fprintf (stream, "\tsub\ta9, sp, a9\n");
3678 fprintf (stream, "\tmovsp\tsp, a9\n");
3681 /* Restore the return address. */
3682 fprintf (stream, "\tmov\ta0, a10\n");
3684 /* Jump to the instruction following the ENTRY. */
3685 fprintf (stream, "\taddi\ta8, a8, 3\n");
3686 fprintf (stream, "\tjx\ta8\n");
3688 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3690 fprintf (stream, "\t.byte\t0\n");
3692 fprintf (stream, "\tnop\n");
3694 fprintf (stream, "\t.end no-transform\n");
3698 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
3700 rtx func = XEXP (DECL_RTL (fndecl), 0);
3701 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3702 int chain_off = use_call0 ? 12 : 8;
3703 int func_off = use_call0 ? 16 : 12;
3705 emit_block_move (m_tramp, assemble_trampoline_template (),
3706 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3708 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain);
3709 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func);
3710 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3711 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
3715 #include "gt-xtensa.h"