1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
33 #include "insn-attr.h"
34 #include "insn-codes.h"
43 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 /* Enumeration for all of the relational tests, so that we can build
55 arrays indexed by the test type, and not worry about the order
73 /* Array giving truth value on whether or not a given hard register
74 can support a given mode. */
75 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
77 /* Current frame size calculated by compute_frame_size. */
78 unsigned xtensa_current_frame_size;
80 /* Largest block move to handle in-line. */
81 #define LARGEST_MOVE_RATIO 15
83 /* Define the structure for the machine field in struct function. */
84 struct GTY(()) machine_function
86 int accesses_prev_frame;
90 rtx set_frame_ptr_insn;
93 /* Vector, indexed by hard register number, which contains 1 for a
94 register that is allowable in a candidate for leaf function
97 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
99 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
101 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
105 /* Map hard register number to register class */
106 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
108 RL_REGS, SP_REG, RL_REGS, RL_REGS,
109 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
110 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
111 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
112 AR_REGS, AR_REGS, BR_REGS,
113 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
114 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
115 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
116 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
120 static void xtensa_option_override (void);
121 static enum internal_test map_test_to_internal_test (enum rtx_code);
122 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
123 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
124 static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx);
125 static rtx fixup_subreg_mem (rtx);
126 static struct machine_function * xtensa_init_machine_status (void);
127 static rtx xtensa_legitimize_tls_address (rtx);
128 static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode);
129 static bool xtensa_return_in_msb (const_tree);
130 static void printx (FILE *, signed int);
131 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
132 static rtx xtensa_builtin_saveregs (void);
133 static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool);
134 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
135 int) ATTRIBUTE_UNUSED;
136 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
137 unsigned HOST_WIDE_INT);
138 static bool xtensa_rtx_costs (rtx, int, int, int *, bool);
139 static tree xtensa_build_builtin_va_list (void);
140 static bool xtensa_return_in_memory (const_tree, const_tree);
141 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
143 static void xtensa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
145 static rtx xtensa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
147 static rtx xtensa_function_incoming_arg (CUMULATIVE_ARGS *,
148 enum machine_mode, const_tree, bool);
149 static rtx xtensa_function_value (const_tree, const_tree, bool);
150 static unsigned int xtensa_function_arg_boundary (enum machine_mode,
152 static void xtensa_init_builtins (void);
153 static tree xtensa_fold_builtin (tree, int, tree *, bool);
154 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
155 static void xtensa_va_start (tree, rtx);
156 static bool xtensa_frame_pointer_required (void);
157 static rtx xtensa_static_chain (const_tree, bool);
158 static void xtensa_asm_trampoline_template (FILE *);
159 static void xtensa_trampoline_init (rtx, tree, rtx);
160 static bool xtensa_output_addr_const_extra (FILE *, rtx);
162 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
165 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
167 static const struct default_options xtensa_option_optimization_table[] =
169 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
170 /* Reordering blocks for Xtensa is not a good idea unless the
171 compiler understands the range of conditional branches.
172 Currently all branch relaxation for Xtensa is handled in the
173 assembler, so GCC cannot do a good job of reordering blocks.
174 Do not enable reordering unless it is explicitly requested. */
175 { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 },
176 { OPT_LEVELS_NONE, 0, NULL, 0 }
180 /* This macro generates the assembly code for function exit,
181 on machines that need it. If FUNCTION_EPILOGUE is not defined
182 then individual return instructions are generated for each
183 return statement. Args are same as for FUNCTION_PROLOGUE. */
185 #undef TARGET_ASM_FUNCTION_EPILOGUE
186 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
188 /* These hooks specify assembly directives for creating certain kinds
189 of integer object. */
191 #undef TARGET_ASM_ALIGNED_SI_OP
192 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
194 #undef TARGET_ASM_SELECT_RTX_SECTION
195 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
197 #undef TARGET_DEFAULT_TARGET_FLAGS
198 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
200 #undef TARGET_LEGITIMIZE_ADDRESS
201 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
203 #undef TARGET_RTX_COSTS
204 #define TARGET_RTX_COSTS xtensa_rtx_costs
205 #undef TARGET_ADDRESS_COST
206 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
208 #undef TARGET_BUILD_BUILTIN_VA_LIST
209 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
211 #undef TARGET_EXPAND_BUILTIN_VA_START
212 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
214 #undef TARGET_PROMOTE_FUNCTION_MODE
215 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
216 #undef TARGET_PROMOTE_PROTOTYPES
217 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
219 #undef TARGET_RETURN_IN_MEMORY
220 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
221 #undef TARGET_FUNCTION_VALUE
222 #define TARGET_FUNCTION_VALUE xtensa_function_value
223 #undef TARGET_SPLIT_COMPLEX_ARG
224 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
225 #undef TARGET_MUST_PASS_IN_STACK
226 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
227 #undef TARGET_FUNCTION_ARG_ADVANCE
228 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
229 #undef TARGET_FUNCTION_ARG
230 #define TARGET_FUNCTION_ARG xtensa_function_arg
231 #undef TARGET_FUNCTION_INCOMING_ARG
232 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
233 #undef TARGET_FUNCTION_ARG_BOUNDARY
234 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
236 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
237 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
238 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
239 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
241 #undef TARGET_RETURN_IN_MSB
242 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
244 #undef TARGET_INIT_BUILTINS
245 #define TARGET_INIT_BUILTINS xtensa_init_builtins
246 #undef TARGET_FOLD_BUILTIN
247 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
248 #undef TARGET_EXPAND_BUILTIN
249 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
251 #undef TARGET_SECONDARY_RELOAD
252 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
254 #undef TARGET_HAVE_TLS
255 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
257 #undef TARGET_CANNOT_FORCE_CONST_MEM
258 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_tls_referenced_p
260 #undef TARGET_LEGITIMATE_ADDRESS_P
261 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
263 #undef TARGET_FRAME_POINTER_REQUIRED
264 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
266 #undef TARGET_STATIC_CHAIN
267 #define TARGET_STATIC_CHAIN xtensa_static_chain
268 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
269 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
270 #undef TARGET_TRAMPOLINE_INIT
271 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
273 #undef TARGET_OPTION_OVERRIDE
274 #define TARGET_OPTION_OVERRIDE xtensa_option_override
275 #undef TARGET_OPTION_OPTIMIZATION_TABLE
276 #define TARGET_OPTION_OPTIMIZATION_TABLE xtensa_option_optimization_table
278 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
279 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
281 struct gcc_target targetm = TARGET_INITIALIZER;
284 /* Functions to test Xtensa immediate operand validity. */
287 xtensa_simm8 (HOST_WIDE_INT v)
289 return v >= -128 && v <= 127;
294 xtensa_simm8x256 (HOST_WIDE_INT v)
296 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
301 xtensa_simm12b (HOST_WIDE_INT v)
303 return v >= -2048 && v <= 2047;
308 xtensa_uimm8 (HOST_WIDE_INT v)
310 return v >= 0 && v <= 255;
315 xtensa_uimm8x2 (HOST_WIDE_INT v)
317 return (v & 1) == 0 && (v >= 0 && v <= 510);
322 xtensa_uimm8x4 (HOST_WIDE_INT v)
324 return (v & 3) == 0 && (v >= 0 && v <= 1020);
329 xtensa_b4const (HOST_WIDE_INT v)
356 xtensa_b4const_or_zero (HOST_WIDE_INT v)
360 return xtensa_b4const (v);
365 xtensa_b4constu (HOST_WIDE_INT v)
392 xtensa_mask_immediate (HOST_WIDE_INT v)
394 #define MAX_MASK_SIZE 16
397 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
410 /* This is just like the standard true_regnum() function except that it
411 works even when reg_renumber is not initialized. */
414 xt_true_regnum (rtx x)
416 if (GET_CODE (x) == REG)
419 && REGNO (x) >= FIRST_PSEUDO_REGISTER
420 && reg_renumber[REGNO (x)] >= 0)
421 return reg_renumber[REGNO (x)];
424 if (GET_CODE (x) == SUBREG)
426 int base = xt_true_regnum (SUBREG_REG (x));
427 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
428 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
429 GET_MODE (SUBREG_REG (x)),
430 SUBREG_BYTE (x), GET_MODE (x));
437 xtensa_valid_move (enum machine_mode mode, rtx *operands)
439 /* Either the destination or source must be a register, and the
440 MAC16 accumulator doesn't count. */
442 if (register_operand (operands[0], mode))
444 int dst_regnum = xt_true_regnum (operands[0]);
446 /* The stack pointer can only be assigned with a MOVSP opcode. */
447 if (dst_regnum == STACK_POINTER_REGNUM)
448 return (mode == SImode
449 && register_operand (operands[1], mode)
450 && !ACC_REG_P (xt_true_regnum (operands[1])));
452 if (!ACC_REG_P (dst_regnum))
455 if (register_operand (operands[1], mode))
457 int src_regnum = xt_true_regnum (operands[1]);
458 if (!ACC_REG_P (src_regnum))
466 smalloffset_mem_p (rtx op)
468 if (GET_CODE (op) == MEM)
470 rtx addr = XEXP (op, 0);
471 if (GET_CODE (addr) == REG)
472 return BASE_REG_P (addr, 0);
473 if (GET_CODE (addr) == PLUS)
475 rtx offset = XEXP (addr, 0);
477 if (GET_CODE (offset) != CONST_INT)
478 offset = XEXP (addr, 1);
479 if (GET_CODE (offset) != CONST_INT)
482 val = INTVAL (offset);
483 return (val & 3) == 0 && (val >= 0 && val <= 60);
491 constantpool_address_p (rtx addr)
495 if (GET_CODE (addr) == CONST)
499 /* Only handle (PLUS (SYM, OFFSET)) form. */
500 addr = XEXP (addr, 0);
501 if (GET_CODE (addr) != PLUS)
504 /* Make sure the address is word aligned. */
505 offset = XEXP (addr, 1);
506 if ((GET_CODE (offset) != CONST_INT)
507 || ((INTVAL (offset) & 3) != 0))
510 sym = XEXP (addr, 0);
513 if ((GET_CODE (sym) == SYMBOL_REF)
514 && CONSTANT_POOL_ADDRESS_P (sym))
521 constantpool_mem_p (rtx op)
523 if (GET_CODE (op) == SUBREG)
524 op = SUBREG_REG (op);
525 if (GET_CODE (op) == MEM)
526 return constantpool_address_p (XEXP (op, 0));
531 /* Return TRUE if X is a thread-local symbol. */
534 xtensa_tls_symbol_p (rtx x)
536 if (! TARGET_HAVE_TLS)
539 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
544 xtensa_extend_reg (rtx dst, rtx src)
546 rtx temp = gen_reg_rtx (SImode);
547 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
549 /* Generate paradoxical subregs as needed so that the modes match. */
550 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
551 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
553 emit_insn (gen_ashlsi3 (temp, src, shift));
554 emit_insn (gen_ashrsi3 (dst, temp, shift));
559 xtensa_mem_offset (unsigned v, enum machine_mode mode)
564 /* Handle the worst case for block moves. See xtensa_expand_block_move
565 where we emit an optimized block move operation if the block can be
566 moved in < "move_ratio" pieces. The worst case is when the block is
567 aligned but has a size of (3 mod 4) (does this happen?) so that the
568 last piece requires a byte load/store. */
569 return (xtensa_uimm8 (v)
570 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
573 return xtensa_uimm8 (v);
576 return xtensa_uimm8x2 (v);
579 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
585 return xtensa_uimm8x4 (v);
589 /* Make normal rtx_code into something we can index from an array. */
591 static enum internal_test
592 map_test_to_internal_test (enum rtx_code test_code)
594 enum internal_test test = ITEST_MAX;
599 case EQ: test = ITEST_EQ; break;
600 case NE: test = ITEST_NE; break;
601 case GT: test = ITEST_GT; break;
602 case GE: test = ITEST_GE; break;
603 case LT: test = ITEST_LT; break;
604 case LE: test = ITEST_LE; break;
605 case GTU: test = ITEST_GTU; break;
606 case GEU: test = ITEST_GEU; break;
607 case LTU: test = ITEST_LTU; break;
608 case LEU: test = ITEST_LEU; break;
615 /* Generate the code to compare two integer values. The return value is
616 the comparison expression. */
619 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
620 rtx cmp0, /* first operand to compare */
621 rtx cmp1, /* second operand to compare */
622 int *p_invert /* whether branch needs to reverse test */)
626 enum rtx_code test_code; /* test code to use in insn */
627 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
628 int const_add; /* constant to add (convert LE -> LT) */
629 int reverse_regs; /* reverse registers in test */
630 int invert_const; /* != 0 if invert value if cmp1 is constant */
631 int invert_reg; /* != 0 if invert value if cmp1 is register */
632 int unsignedp; /* != 0 for unsigned comparisons. */
635 static struct cmp_info info[ (int)ITEST_MAX ] = {
637 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
638 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
640 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
641 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
642 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
643 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
645 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
646 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
647 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
648 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
651 enum internal_test test;
652 enum machine_mode mode;
653 struct cmp_info *p_info;
655 test = map_test_to_internal_test (test_code);
656 gcc_assert (test != ITEST_MAX);
658 p_info = &info[ (int)test ];
660 mode = GET_MODE (cmp0);
661 if (mode == VOIDmode)
662 mode = GET_MODE (cmp1);
664 /* Make sure we can handle any constants given to us. */
665 if (GET_CODE (cmp1) == CONST_INT)
667 HOST_WIDE_INT value = INTVAL (cmp1);
668 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
670 /* if the immediate overflows or does not fit in the immediate field,
671 spill it to a register */
673 if ((p_info->unsignedp ?
674 (uvalue + p_info->const_add > uvalue) :
675 (value + p_info->const_add > value)) != (p_info->const_add > 0))
677 cmp1 = force_reg (mode, cmp1);
679 else if (!(p_info->const_range_p) (value + p_info->const_add))
681 cmp1 = force_reg (mode, cmp1);
684 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
686 cmp1 = force_reg (mode, cmp1);
689 /* See if we need to invert the result. */
690 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
691 ? p_info->invert_const
692 : p_info->invert_reg);
694 /* Comparison to constants, may involve adding 1 to change a LT into LE.
695 Comparison between two registers, may involve switching operands. */
696 if (GET_CODE (cmp1) == CONST_INT)
698 if (p_info->const_add != 0)
699 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
702 else if (p_info->reverse_regs)
709 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
713 /* Generate the code to compare two float values. The return value is
714 the comparison expression. */
717 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
718 rtx cmp0, /* first operand to compare */
719 rtx cmp1 /* second operand to compare */)
721 rtx (*gen_fn) (rtx, rtx, rtx);
723 int reverse_regs, invert;
727 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
728 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
729 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
730 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
731 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
732 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
733 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
734 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
735 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
736 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
737 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
738 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
740 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
742 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
744 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
745 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
755 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
756 emit_insn (gen_fn (brtmp, cmp0, cmp1));
758 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
763 xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode)
765 enum rtx_code test_code = GET_CODE (operands[0]);
766 rtx cmp0 = operands[1];
767 rtx cmp1 = operands[2];
776 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
780 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
784 if (!TARGET_HARD_FLOAT)
785 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
788 cmp = gen_float_relational (test_code, cmp0, cmp1);
792 /* Generate the branch. */
794 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
803 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
804 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
811 gen_conditional_move (enum rtx_code code, enum machine_mode mode,
818 /* Jump optimization calls get_condition() which canonicalizes
819 comparisons like (GE x <const>) to (GT x <const-1>).
820 Transform those comparisons back to GE, since that is the
821 comparison supported in Xtensa. We shouldn't have to
822 transform <LE x const> comparisons, because neither
823 xtensa_expand_conditional_branch() nor get_condition() will
826 if ((code == GT) && (op1 == constm1_rtx))
831 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
833 if (boolean_operator (cmp, VOIDmode))
835 /* Swap the operands to make const0 second. */
836 if (op0 == const0_rtx)
842 /* If not comparing against zero, emit a comparison (subtract). */
843 if (op1 != const0_rtx)
845 op0 = expand_binop (SImode, sub_optab, op0, op1,
846 0, 0, OPTAB_LIB_WIDEN);
850 else if (branch_operator (cmp, VOIDmode))
852 /* Swap the operands to make const0 second. */
853 if (op0 == const0_rtx)
860 case LT: code = GE; break;
861 case GE: code = LT; break;
862 default: gcc_unreachable ();
866 if (op1 != const0_rtx)
872 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
875 if (TARGET_HARD_FLOAT && mode == SFmode)
876 return gen_float_relational (code, op0, op1);
883 xtensa_expand_conditional_move (rtx *operands, int isflt)
885 rtx dest = operands[0];
886 rtx cmp = operands[1];
887 enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0));
888 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
890 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode,
891 XEXP (cmp, 0), XEXP (cmp, 1))))
895 gen_fn = (cmp_mode == SImode
896 ? gen_movsfcc_internal0
897 : gen_movsfcc_internal1);
899 gen_fn = (cmp_mode == SImode
900 ? gen_movsicc_internal0
901 : gen_movsicc_internal1);
903 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp));
909 xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode)
911 rtx dest = operands[0];
913 rtx one_tmp, zero_tmp;
914 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
916 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode,
917 operands[2], operands[3])))
920 one_tmp = gen_reg_rtx (SImode);
921 zero_tmp = gen_reg_rtx (SImode);
922 emit_insn (gen_movsi (one_tmp, const_true_rtx));
923 emit_insn (gen_movsi (zero_tmp, const0_rtx));
925 gen_fn = (cmp_mode == SImode
926 ? gen_movsicc_internal0
927 : gen_movsicc_internal1);
928 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
933 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
934 for the output, i.e., the input operands are twice as big as MODE. */
937 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
939 switch (GET_CODE (operands[1]))
942 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
943 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
947 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
948 operands[2] = adjust_address (operands[1], mode, 0);
953 split_double (operands[1], &operands[2], &operands[3]);
960 switch (GET_CODE (operands[0]))
963 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
964 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
968 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
969 operands[0] = adjust_address (operands[0], mode, 0);
978 /* Emit insns to move operands[1] into operands[0].
979 Return 1 if we have written out everything that needs to be done to
980 do the move. Otherwise, return 0 and the caller will emit the move
984 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
986 rtx src = operands[1];
989 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
991 rtx dst = operands[0];
993 if (xtensa_tls_referenced_p (src))
997 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
999 addend = XEXP (XEXP (src, 0), 1);
1000 src = XEXP (XEXP (src, 0), 0);
1003 src = xtensa_legitimize_tls_address (src);
1006 src = gen_rtx_PLUS (mode, src, addend);
1007 src = force_operand (src, dst);
1009 emit_move_insn (dst, src);
1013 if (! TARGET_CONST16)
1015 src = force_const_mem (SImode, src);
1019 /* PC-relative loads are always SImode, and CONST16 is only
1020 supported in the movsi pattern, so add a SUBREG for any other
1025 if (register_operand (dst, mode))
1027 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src);
1032 src = force_reg (SImode, src);
1033 src = gen_lowpart_SUBREG (mode, src);
1039 if (!(reload_in_progress | reload_completed)
1040 && !xtensa_valid_move (mode, operands))
1041 operands[1] = force_reg (mode, operands[1]);
1043 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1045 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1046 instruction won't be recognized after reload, so we remove the
1047 subreg and adjust mem accordingly. */
1048 if (reload_in_progress)
1050 operands[0] = fixup_subreg_mem (operands[0]);
1051 operands[1] = fixup_subreg_mem (operands[1]);
1058 fixup_subreg_mem (rtx x)
1060 if (GET_CODE (x) == SUBREG
1061 && GET_CODE (SUBREG_REG (x)) == REG
1062 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
1065 gen_rtx_SUBREG (GET_MODE (x),
1066 reg_equiv_mem [REGNO (SUBREG_REG (x))],
1068 x = alter_subreg (&temp);
1074 /* Check if an incoming argument in a7 is expected to be used soon and
1075 if OPND is a register or register pair that includes a7. If so,
1076 create a new pseudo and copy a7 into that pseudo at the very
1077 beginning of the function, followed by the special "set_frame_ptr"
1078 unspec_volatile insn. The return value is either the original
1079 operand, if it is not a7, or the new pseudo containing a copy of
1080 the incoming argument. This is necessary because the register
1081 allocator will ignore conflicts with a7 and may either assign some
1082 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1083 the incoming argument in a7. By copying the argument out of a7 as
1084 the very first thing, and then immediately following that with an
1085 unspec_volatile to keep the scheduler away, we should avoid any
1086 problems. Putting the set_frame_ptr insn at the beginning, with
1087 only the a7 copy before it, also makes it easier for the prologue
1088 expander to initialize the frame pointer after the a7 copy and to
1089 fix up the a7 copy to use the stack pointer instead of the frame
1093 xtensa_copy_incoming_a7 (rtx opnd)
1095 rtx entry_insns = 0;
1097 enum machine_mode mode;
1099 if (!cfun->machine->need_a7_copy)
1102 /* This function should never be called again once a7 has been copied. */
1103 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1105 mode = GET_MODE (opnd);
1107 /* The operand using a7 may come in a later instruction, so just return
1108 the original operand if it doesn't use a7. */
1110 if (GET_CODE (reg) == SUBREG)
1112 gcc_assert (SUBREG_BYTE (reg) == 0);
1113 reg = SUBREG_REG (reg);
1115 if (GET_CODE (reg) != REG
1116 || REGNO (reg) > A7_REG
1117 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1120 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1121 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1123 cfun->machine->need_a7_copy = false;
1125 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1126 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1129 tmp = gen_reg_rtx (mode);
1135 /* Copy the value out of A7 here but keep the first word in A6 until
1136 after the set_frame_ptr insn. Otherwise, the register allocator
1137 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1139 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1140 gen_raw_REG (SImode, A7_REG)));
1143 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1146 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1149 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1152 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1158 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1160 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1161 if (mode == DFmode || mode == DImode)
1162 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1163 gen_rtx_REG (SImode, A7_REG - 1)));
1164 entry_insns = get_insns ();
1167 if (cfun->machine->vararg_a7)
1169 /* This is called from within builtin_saveregs, which will insert the
1170 saveregs code at the function entry, ahead of anything placed at
1171 the function entry now. Instead, save the sequence to be inserted
1172 at the beginning of the saveregs code. */
1173 cfun->machine->vararg_a7_copy = entry_insns;
1177 /* Put entry_insns after the NOTE that starts the function. If
1178 this is inside a start_sequence, make the outer-level insn
1179 chain current, so the code is placed at the start of the
1181 push_topmost_sequence ();
1182 /* Do not use entry_of_function() here. This is called from within
1183 expand_function_start, when the CFG still holds GIMPLE. */
1184 emit_insn_after (entry_insns, get_insns ());
1185 pop_topmost_sequence ();
1192 /* Try to expand a block move operation to a sequence of RTL move
1193 instructions. If not optimizing, or if the block size is not a
1194 constant, or if the block is too large, the expansion fails and GCC
1195 falls back to calling memcpy().
1197 operands[0] is the destination
1198 operands[1] is the source
1199 operands[2] is the length
1200 operands[3] is the alignment */
1203 xtensa_expand_block_move (rtx *operands)
1205 static const enum machine_mode mode_from_align[] =
1207 VOIDmode, QImode, HImode, VOIDmode, SImode,
1210 rtx dst_mem = operands[0];
1211 rtx src_mem = operands[1];
1212 HOST_WIDE_INT bytes, align;
1213 int num_pieces, move_ratio;
1215 enum machine_mode mode[2];
1224 /* If this is not a fixed size move, just call memcpy. */
1225 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1228 bytes = INTVAL (operands[2]);
1229 align = INTVAL (operands[3]);
1231 /* Anything to move? */
1235 if (align > MOVE_MAX)
1238 /* Decide whether to expand inline based on the optimization level. */
1241 move_ratio = LARGEST_MOVE_RATIO;
1242 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1243 if (num_pieces > move_ratio)
1246 x = XEXP (dst_mem, 0);
1249 x = force_reg (Pmode, x);
1250 dst_mem = replace_equiv_address (dst_mem, x);
1253 x = XEXP (src_mem, 0);
1256 x = force_reg (Pmode, x);
1257 src_mem = replace_equiv_address (src_mem, x);
1260 active[0] = active[1] = false;
1271 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1272 next_amount = MIN (next_amount, align);
1274 amount[next] = next_amount;
1275 mode[next] = mode_from_align[next_amount];
1276 temp[next] = gen_reg_rtx (mode[next]);
1278 x = adjust_address (src_mem, mode[next], offset_ld);
1279 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1281 offset_ld += next_amount;
1282 bytes -= next_amount;
1283 active[next] = true;
1288 active[phase] = false;
1290 x = adjust_address (dst_mem, mode[phase], offset_st);
1291 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1293 offset_st += amount[phase];
1296 while (active[next]);
1303 xtensa_expand_nonlocal_goto (rtx *operands)
1305 rtx goto_handler = operands[1];
1306 rtx containing_fp = operands[3];
1308 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1309 is too big to generate in-line. */
1311 if (GET_CODE (containing_fp) != REG)
1312 containing_fp = force_reg (Pmode, containing_fp);
1314 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1315 LCT_NORMAL, VOIDmode, 2,
1316 containing_fp, Pmode,
1317 goto_handler, Pmode);
1321 static struct machine_function *
1322 xtensa_init_machine_status (void)
1324 return ggc_alloc_cleared_machine_function ();
1328 /* Shift VAL of mode MODE left by COUNT bits. */
1331 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1333 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1334 NULL_RTX, 1, OPTAB_DIRECT);
1335 return expand_simple_binop (SImode, ASHIFT, val, count,
1336 NULL_RTX, 1, OPTAB_DIRECT);
1340 /* Structure to hold the initial parameters for a compare_and_swap operation
1341 in HImode and QImode. */
1343 struct alignment_context
1345 rtx memsi; /* SI aligned memory location. */
1346 rtx shift; /* Bit offset with regard to lsb. */
1347 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1348 rtx modemaski; /* ~modemask */
1352 /* Initialize structure AC for word access to HI and QI mode memory. */
1355 init_alignment_context (struct alignment_context *ac, rtx mem)
1357 enum machine_mode mode = GET_MODE (mem);
1358 rtx byteoffset = NULL_RTX;
1359 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1362 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1365 /* Alignment is unknown. */
1368 /* Force the address into a register. */
1369 addr = force_reg (Pmode, XEXP (mem, 0));
1371 /* Align it to SImode. */
1372 align = expand_simple_binop (Pmode, AND, addr,
1373 GEN_INT (-GET_MODE_SIZE (SImode)),
1374 NULL_RTX, 1, OPTAB_DIRECT);
1376 ac->memsi = gen_rtx_MEM (SImode, align);
1377 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1378 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1379 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1381 byteoffset = expand_simple_binop (Pmode, AND, addr,
1382 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1383 NULL_RTX, 1, OPTAB_DIRECT);
1386 /* Calculate shiftcount. */
1387 if (TARGET_BIG_ENDIAN)
1389 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1391 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1392 NULL_RTX, 1, OPTAB_DIRECT);
1397 ac->shift = NULL_RTX;
1399 ac->shift = byteoffset;
1402 if (ac->shift != NULL_RTX)
1404 /* Shift is the byte count, but we need the bitcount. */
1405 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1406 GEN_INT (BITS_PER_UNIT),
1407 NULL_RTX, 1, OPTAB_DIRECT);
1408 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1409 GEN_INT (GET_MODE_MASK (mode)),
1411 NULL_RTX, 1, OPTAB_DIRECT);
1414 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1416 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1420 /* Expand an atomic compare and swap operation for HImode and QImode.
1421 MEM is the memory location, CMP the old value to compare MEM with
1422 and NEW_RTX the value to set if CMP == MEM. */
1425 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx)
1427 enum machine_mode mode = GET_MODE (mem);
1428 struct alignment_context ac;
1429 rtx tmp, cmpv, newv, val;
1430 rtx oldval = gen_reg_rtx (SImode);
1431 rtx res = gen_reg_rtx (SImode);
1432 rtx csloop = gen_label_rtx ();
1433 rtx csend = gen_label_rtx ();
1435 init_alignment_context (&ac, mem);
1437 if (ac.shift != NULL_RTX)
1439 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1440 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift);
1443 /* Load the surrounding word into VAL with the MEM value masked out. */
1444 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1445 ac.modemaski, NULL_RTX, 1,
1447 emit_label (csloop);
1449 /* Patch CMP and NEW_RTX into VAL at correct position. */
1450 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1451 NULL_RTX, 1, OPTAB_DIRECT));
1452 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
1453 NULL_RTX, 1, OPTAB_DIRECT));
1455 /* Jump to end if we're done. */
1456 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1457 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1459 /* Check for changes outside mode. */
1460 emit_move_insn (oldval, val);
1461 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1462 val, 1, OPTAB_DIRECT);
1464 emit_move_insn (val, tmp);
1466 /* Loop internal if so. */
1467 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1471 /* Return the correct part of the bitfield. */
1472 convert_move (target,
1473 (ac.shift == NULL_RTX ? res
1474 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1475 NULL_RTX, 1, OPTAB_DIRECT)),
1480 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1481 the default expansion works fine for SImode). MEM is the memory location
1482 and VAL the value to play with. If AFTER is true then store the value
1483 MEM holds after the operation, if AFTER is false then store the value MEM
1484 holds before the operation. If TARGET is zero then discard that value, else
1485 store it to TARGET. */
1488 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1491 enum machine_mode mode = GET_MODE (mem);
1492 struct alignment_context ac;
1493 rtx csloop = gen_label_rtx ();
1495 rtx old = gen_reg_rtx (SImode);
1496 rtx new_rtx = gen_reg_rtx (SImode);
1497 rtx orig = NULL_RTX;
1499 init_alignment_context (&ac, mem);
1501 /* Prepare values before the compare-and-swap loop. */
1502 if (ac.shift != NULL_RTX)
1503 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1508 orig = gen_reg_rtx (SImode);
1509 convert_move (orig, val, 1);
1517 case MULT: /* NAND */
1519 /* val = "11..1<val>11..1" */
1520 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1521 NULL_RTX, 1, OPTAB_DIRECT);
1528 /* Load full word. Subsequent loads are performed by S32C1I. */
1529 cmp = force_reg (SImode, ac.memsi);
1531 emit_label (csloop);
1532 emit_move_insn (old, cmp);
1538 val = expand_simple_binop (SImode, code, old, orig,
1539 NULL_RTX, 1, OPTAB_DIRECT);
1540 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1541 NULL_RTX, 1, OPTAB_DIRECT);
1544 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1545 NULL_RTX, 1, OPTAB_DIRECT);
1546 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1547 new_rtx, 1, OPTAB_DIRECT);
1553 tmp = expand_simple_binop (SImode, code, old, val,
1554 new_rtx, 1, OPTAB_DIRECT);
1557 case MULT: /* NAND */
1558 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1559 NULL_RTX, 1, OPTAB_DIRECT);
1560 tmp = expand_simple_binop (SImode, AND, tmp, val,
1561 new_rtx, 1, OPTAB_DIRECT);
1569 emit_move_insn (new_rtx, tmp);
1570 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx));
1571 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1575 tmp = (after ? new_rtx : cmp);
1576 convert_move (target,
1577 (ac.shift == NULL_RTX ? tmp
1578 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1579 NULL_RTX, 1, OPTAB_DIRECT)),
1586 xtensa_setup_frame_addresses (void)
1588 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1589 cfun->machine->accesses_prev_frame = 1;
1592 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1593 LCT_NORMAL, VOIDmode, 0);
1597 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1598 a comment showing where the end of the loop is. However, if there is a
1599 label or a branch at the end of the loop then we need to place a nop
1600 there. If the loop ends with a label we need the nop so that branches
1601 targeting that label will target the nop (and thus remain in the loop),
1602 instead of targeting the instruction after the loop (and thus exiting
1603 the loop). If the loop ends with a branch, we need the nop in case the
1604 branch is targeting a location inside the loop. When the branch
1605 executes it will cause the loop count to be decremented even if it is
1606 taken (because it is the last instruction in the loop), so we need to
1607 nop after the branch to prevent the loop count from being decremented
1608 when the branch is taken. */
1611 xtensa_emit_loop_end (rtx insn, rtx *operands)
1615 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1617 switch (GET_CODE (insn))
1624 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1630 rtx body = PATTERN (insn);
1632 if (GET_CODE (body) == JUMP_INSN)
1634 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1637 else if ((GET_CODE (body) != USE)
1638 && (GET_CODE (body) != CLOBBER))
1645 output_asm_insn ("# loop end for %0", operands);
1650 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1652 static char result[64];
1656 code = GET_CODE (operands[3]);
1659 case EQ: op = inverted ? "ne" : "eq"; break;
1660 case NE: op = inverted ? "eq" : "ne"; break;
1661 case LT: op = inverted ? "ge" : "lt"; break;
1662 case GE: op = inverted ? "lt" : "ge"; break;
1663 case LTU: op = inverted ? "geu" : "ltu"; break;
1664 case GEU: op = inverted ? "ltu" : "geu"; break;
1665 default: gcc_unreachable ();
1670 if (INTVAL (operands[1]) == 0)
1671 sprintf (result, "b%sz%s\t%%0, %%2", op,
1672 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1674 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1677 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1684 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1686 static char result[64];
1689 switch (GET_CODE (operands[3]))
1691 case EQ: op = inverted ? "bs" : "bc"; break;
1692 case NE: op = inverted ? "bc" : "bs"; break;
1693 default: gcc_unreachable ();
1698 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1699 operands[1] = GEN_INT (bitnum);
1700 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1703 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1710 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1712 static char result[64];
1716 code = GET_CODE (operands[4]);
1721 case EQ: op = inverted ? "t" : "f"; break;
1722 case NE: op = inverted ? "f" : "t"; break;
1723 default: gcc_unreachable ();
1730 case EQ: op = inverted ? "nez" : "eqz"; break;
1731 case NE: op = inverted ? "eqz" : "nez"; break;
1732 case LT: op = inverted ? "gez" : "ltz"; break;
1733 case GE: op = inverted ? "ltz" : "gez"; break;
1734 default: gcc_unreachable ();
1738 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1739 op, isfp ? ".s" : "", inverted ? 3 : 2);
1745 xtensa_emit_call (int callop, rtx *operands)
1747 static char result[64];
1748 rtx tgt = operands[callop];
1750 if (GET_CODE (tgt) == CONST_INT)
1751 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1752 else if (register_operand (tgt, VOIDmode))
1753 sprintf (result, "callx8\t%%%d", callop);
1755 sprintf (result, "call8\t%%%d", callop);
1762 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1764 /* Allow constant pool addresses. */
1765 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1766 && ! TARGET_CONST16 && constantpool_address_p (addr)
1767 && ! xtensa_tls_referenced_p (addr))
1770 while (GET_CODE (addr) == SUBREG)
1771 addr = SUBREG_REG (addr);
1773 /* Allow base registers. */
1774 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1777 /* Check for "register + offset" addressing. */
1778 if (GET_CODE (addr) == PLUS)
1780 rtx xplus0 = XEXP (addr, 0);
1781 rtx xplus1 = XEXP (addr, 1);
1782 enum rtx_code code0;
1783 enum rtx_code code1;
1785 while (GET_CODE (xplus0) == SUBREG)
1786 xplus0 = SUBREG_REG (xplus0);
1787 code0 = GET_CODE (xplus0);
1789 while (GET_CODE (xplus1) == SUBREG)
1790 xplus1 = SUBREG_REG (xplus1);
1791 code1 = GET_CODE (xplus1);
1793 /* Swap operands if necessary so the register is first. */
1794 if (code0 != REG && code1 == REG)
1796 xplus0 = XEXP (addr, 1);
1797 xplus1 = XEXP (addr, 0);
1798 code0 = GET_CODE (xplus0);
1799 code1 = GET_CODE (xplus1);
1802 if (code0 == REG && BASE_REG_P (xplus0, strict)
1803 && code1 == CONST_INT
1804 && xtensa_mem_offset (INTVAL (xplus1), mode))
1812 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1814 static GTY(()) rtx xtensa_tls_module_base_symbol;
1817 xtensa_tls_module_base (void)
1819 if (! xtensa_tls_module_base_symbol)
1821 xtensa_tls_module_base_symbol =
1822 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_");
1823 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol)
1824 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
1827 return xtensa_tls_module_base_symbol;
1832 xtensa_call_tls_desc (rtx sym, rtx *retp)
1834 rtx fn, arg, a10, call_insn, insns;
1837 fn = gen_reg_rtx (Pmode);
1838 arg = gen_reg_rtx (Pmode);
1839 a10 = gen_rtx_REG (Pmode, 10);
1841 emit_insn (gen_tls_func (fn, sym));
1842 emit_insn (gen_tls_arg (arg, sym));
1843 emit_move_insn (a10, arg);
1844 call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx));
1845 CALL_INSN_FUNCTION_USAGE (call_insn)
1846 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, a10),
1847 CALL_INSN_FUNCTION_USAGE (call_insn));
1848 insns = get_insns ();
1857 xtensa_legitimize_tls_address (rtx x)
1859 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
1860 rtx dest, tp, ret, modbase, base, addend, insns;
1862 dest = gen_reg_rtx (Pmode);
1865 case TLS_MODEL_GLOBAL_DYNAMIC:
1866 insns = xtensa_call_tls_desc (x, &ret);
1867 emit_libcall_block (insns, dest, ret, x);
1870 case TLS_MODEL_LOCAL_DYNAMIC:
1871 base = gen_reg_rtx (Pmode);
1872 modbase = xtensa_tls_module_base ();
1873 insns = xtensa_call_tls_desc (modbase, &ret);
1874 emit_libcall_block (insns, base, ret, modbase);
1875 addend = force_reg (SImode, gen_sym_DTPOFF (x));
1876 emit_insn (gen_addsi3 (dest, base, addend));
1879 case TLS_MODEL_INITIAL_EXEC:
1880 case TLS_MODEL_LOCAL_EXEC:
1881 tp = gen_reg_rtx (SImode);
1882 emit_insn (gen_load_tp (tp));
1883 addend = force_reg (SImode, gen_sym_TPOFF (x));
1884 emit_insn (gen_addsi3 (dest, tp, addend));
1896 xtensa_legitimize_address (rtx x,
1897 rtx oldx ATTRIBUTE_UNUSED,
1898 enum machine_mode mode)
1900 if (xtensa_tls_symbol_p (x))
1901 return xtensa_legitimize_tls_address (x);
1903 if (GET_CODE (x) == PLUS)
1905 rtx plus0 = XEXP (x, 0);
1906 rtx plus1 = XEXP (x, 1);
1908 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1910 plus0 = XEXP (x, 1);
1911 plus1 = XEXP (x, 0);
1914 /* Try to split up the offset to use an ADDMI instruction. */
1915 if (GET_CODE (plus0) == REG
1916 && GET_CODE (plus1) == CONST_INT
1917 && !xtensa_mem_offset (INTVAL (plus1), mode)
1918 && !xtensa_simm8 (INTVAL (plus1))
1919 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1920 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1922 rtx temp = gen_reg_rtx (Pmode);
1923 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1924 emit_insn (gen_rtx_SET (Pmode, temp,
1925 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1926 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1934 /* Helper for xtensa_tls_referenced_p. */
1937 xtensa_tls_referenced_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1939 if (GET_CODE (*x) == SYMBOL_REF)
1940 return SYMBOL_REF_TLS_MODEL (*x) != 0;
1942 /* Ignore TLS references that have already been legitimized. */
1943 if (GET_CODE (*x) == UNSPEC)
1945 switch (XINT (*x, 1))
1949 case UNSPEC_TLS_FUNC:
1950 case UNSPEC_TLS_ARG:
1951 case UNSPEC_TLS_CALL:
1962 /* Return TRUE if X contains any TLS symbol references. */
1965 xtensa_tls_referenced_p (rtx x)
1967 if (! TARGET_HAVE_TLS)
1970 return for_each_rtx (&x, xtensa_tls_referenced_p_1, NULL);
1974 /* Return the debugger register number to use for 'regno'. */
1977 xtensa_dbx_register_number (int regno)
1981 if (GP_REG_P (regno))
1983 regno -= GP_REG_FIRST;
1986 else if (BR_REG_P (regno))
1988 regno -= BR_REG_FIRST;
1991 else if (FP_REG_P (regno))
1993 regno -= FP_REG_FIRST;
1996 else if (ACC_REG_P (regno))
1998 first = 0x200; /* Start of Xtensa special registers. */
1999 regno = 16; /* ACCLO is special register 16. */
2002 /* When optimizing, we sometimes get asked about pseudo-registers
2003 that don't represent hard registers. Return 0 for these. */
2007 return first + regno;
2011 /* Argument support functions. */
2013 /* Initialize CUMULATIVE_ARGS for a function. */
2016 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
2019 cum->incoming = incoming;
2023 /* Advance the argument to the next argument position. */
2026 xtensa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2027 const_tree type, bool named ATTRIBUTE_UNUSED)
2032 arg_words = &cum->arg_words;
2033 max = MAX_ARGS_IN_REGISTERS;
2035 words = (((mode != BLKmode)
2036 ? (int) GET_MODE_SIZE (mode)
2037 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2039 if (*arg_words < max
2040 && (targetm.calls.must_pass_in_stack (mode, type)
2041 || *arg_words + words > max))
2044 *arg_words += words;
2048 /* Return an RTL expression containing the register for the given mode,
2049 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2050 if this is an incoming argument to the current function. */
2053 xtensa_function_arg_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2054 const_tree type, bool incoming_p)
2056 int regbase, words, max;
2060 arg_words = &cum->arg_words;
2061 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
2062 max = MAX_ARGS_IN_REGISTERS;
2064 words = (((mode != BLKmode)
2065 ? (int) GET_MODE_SIZE (mode)
2066 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2068 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
2070 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
2071 *arg_words = (*arg_words + align - 1) & -align;
2074 if (*arg_words + words > max)
2077 regno = regbase + *arg_words;
2079 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
2080 cfun->machine->need_a7_copy = true;
2082 return gen_rtx_REG (mode, regno);
2085 /* Implement TARGET_FUNCTION_ARG. */
2088 xtensa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2089 const_tree type, bool named ATTRIBUTE_UNUSED)
2091 return xtensa_function_arg_1 (cum, mode, type, false);
2094 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2097 xtensa_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2098 const_tree type, bool named ATTRIBUTE_UNUSED)
2100 return xtensa_function_arg_1 (cum, mode, type, true);
2104 xtensa_function_arg_boundary (enum machine_mode mode, const_tree type)
2106 unsigned int alignment;
2108 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
2109 if (alignment < PARM_BOUNDARY)
2110 alignment = PARM_BOUNDARY;
2111 if (alignment > STACK_BOUNDARY)
2112 alignment = STACK_BOUNDARY;
2118 xtensa_return_in_msb (const_tree valtype)
2120 return (TARGET_BIG_ENDIAN
2121 && AGGREGATE_TYPE_P (valtype)
2122 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
2127 xtensa_option_override (void)
2130 enum machine_mode mode;
2132 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
2133 error ("boolean registers required for the floating-point option");
2135 /* Set up array giving whether a given register can hold a given mode. */
2136 for (mode = VOIDmode;
2137 mode != MAX_MACHINE_MODE;
2138 mode = (enum machine_mode) ((int) mode + 1))
2140 int size = GET_MODE_SIZE (mode);
2141 enum mode_class mclass = GET_MODE_CLASS (mode);
2143 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2147 if (ACC_REG_P (regno))
2148 temp = (TARGET_MAC16
2149 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD));
2150 else if (GP_REG_P (regno))
2151 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
2152 else if (FP_REG_P (regno))
2153 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
2154 else if (BR_REG_P (regno))
2155 temp = (TARGET_BOOLEANS && (mode == CCmode));
2159 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
2163 init_machine_status = xtensa_init_machine_status;
2165 /* Check PIC settings. PIC is only supported when using L32R
2166 instructions, and some targets need to always use PIC. */
2167 if (flag_pic && TARGET_CONST16)
2168 error ("-f%s is not supported with CONST16 instructions",
2169 (flag_pic > 1 ? "PIC" : "pic"));
2170 else if (TARGET_FORCE_NO_PIC)
2172 else if (XTENSA_ALWAYS_PIC)
2175 error ("PIC is required but not supported with CONST16 instructions");
2178 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2181 if (flag_pic && !flag_pie)
2184 /* Hot/cold partitioning does not work on this architecture, because of
2185 constant pools (the load instruction cannot necessarily reach that far).
2186 Therefore disable it on this architecture. */
2187 if (flag_reorder_blocks_and_partition)
2189 flag_reorder_blocks_and_partition = 0;
2190 flag_reorder_blocks = 1;
2194 /* A C compound statement to output to stdio stream STREAM the
2195 assembler syntax for an instruction operand X. X is an RTL
2198 CODE is a value that can be used to specify one of several ways
2199 of printing the operand. It is used when identical operands
2200 must be printed differently depending on the context. CODE
2201 comes from the '%' specification that was used to request
2202 printing of the operand. If the specification was just '%DIGIT'
2203 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2204 is the ASCII code for LTR.
2206 If X is a register, this macro should print the register's name.
2207 The names can be found in an array 'reg_names' whose type is
2208 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2210 When the machine description has a specification '%PUNCT' (a '%'
2211 followed by a punctuation character), this macro is called with
2212 a null pointer for X and the punctuation character for CODE.
2214 'a', 'c', 'l', and 'n' are reserved.
2216 The Xtensa specific codes are:
2218 'd' CONST_INT, print as signed decimal
2219 'x' CONST_INT, print as signed hexadecimal
2220 'K' CONST_INT, print number of bits in mask for EXTUI
2221 'R' CONST_INT, print (X & 0x1f)
2222 'L' CONST_INT, print ((32 - X) & 0x1f)
2223 'D' REG, print second register of double-word register operand
2224 'N' MEM, print address of next word following a memory operand
2225 'v' MEM, if memory reference is volatile, output a MEMW before it
2226 't' any constant, add "@h" suffix for top 16 bits
2227 'b' any constant, add "@l" suffix for bottom 16 bits
2231 printx (FILE *file, signed int val)
2233 /* Print a hexadecimal value in a nice way. */
2234 if ((val > -0xa) && (val < 0xa))
2235 fprintf (file, "%d", val);
2237 fprintf (file, "-0x%x", -val);
2239 fprintf (file, "0x%x", val);
2244 print_operand (FILE *file, rtx x, int letter)
2247 error ("PRINT_OPERAND null pointer");
2252 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2253 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
2255 output_operand_lossage ("invalid %%D value");
2259 if (GET_CODE (x) == MEM)
2261 /* For a volatile memory reference, emit a MEMW before the
2263 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2264 fprintf (file, "memw\n\t");
2267 output_operand_lossage ("invalid %%v value");
2271 if (GET_CODE (x) == MEM
2272 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2274 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2275 output_address (XEXP (x, 0));
2278 output_operand_lossage ("invalid %%N value");
2282 if (GET_CODE (x) == CONST_INT)
2285 unsigned val = INTVAL (x);
2291 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2292 fatal_insn ("invalid mask", x);
2294 fprintf (file, "%d", num_bits);
2297 output_operand_lossage ("invalid %%K value");
2301 if (GET_CODE (x) == CONST_INT)
2302 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2304 output_operand_lossage ("invalid %%L value");
2308 if (GET_CODE (x) == CONST_INT)
2309 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2311 output_operand_lossage ("invalid %%R value");
2315 if (GET_CODE (x) == CONST_INT)
2316 printx (file, INTVAL (x));
2318 output_operand_lossage ("invalid %%x value");
2322 if (GET_CODE (x) == CONST_INT)
2323 fprintf (file, "%ld", INTVAL (x));
2325 output_operand_lossage ("invalid %%d value");
2330 if (GET_CODE (x) == CONST_INT)
2332 printx (file, INTVAL (x));
2333 fputs (letter == 't' ? "@h" : "@l", file);
2335 else if (GET_CODE (x) == CONST_DOUBLE)
2338 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2339 if (GET_MODE (x) == SFmode)
2342 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2343 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2346 output_operand_lossage ("invalid %%t/%%b value");
2348 else if (GET_CODE (x) == CONST)
2350 /* X must be a symbolic constant on ELF. Write an expression
2351 suitable for 'const16' that sets the high or low 16 bits. */
2352 if (GET_CODE (XEXP (x, 0)) != PLUS
2353 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2354 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2355 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2356 output_operand_lossage ("invalid %%t/%%b value");
2357 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2358 fputs (letter == 't' ? "@h" : "@l", file);
2359 /* There must be a non-alphanumeric character between 'h' or 'l'
2360 and the number. The '-' is added by print_operand() already. */
2361 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2363 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2367 output_addr_const (file, x);
2368 fputs (letter == 't' ? "@h" : "@l", file);
2373 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2374 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2375 else if (GET_CODE (x) == MEM)
2376 output_address (XEXP (x, 0));
2377 else if (GET_CODE (x) == CONST_INT)
2378 fprintf (file, "%ld", INTVAL (x));
2380 output_addr_const (file, x);
2385 /* A C compound statement to output to stdio stream STREAM the
2386 assembler syntax for an instruction operand that is a memory
2387 reference whose address is ADDR. ADDR is an RTL expression. */
2390 print_operand_address (FILE *file, rtx addr)
2393 error ("PRINT_OPERAND_ADDRESS, null pointer");
2395 switch (GET_CODE (addr))
2398 fatal_insn ("invalid address", addr);
2402 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2408 rtx offset = (rtx)0;
2409 rtx arg0 = XEXP (addr, 0);
2410 rtx arg1 = XEXP (addr, 1);
2412 if (GET_CODE (arg0) == REG)
2417 else if (GET_CODE (arg1) == REG)
2423 fatal_insn ("no register in address", addr);
2425 if (CONSTANT_P (offset))
2427 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2428 output_addr_const (file, offset);
2431 fatal_insn ("address offset not a constant", addr);
2439 output_addr_const (file, addr);
2444 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2447 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2449 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2451 switch (XINT (x, 1))
2454 output_addr_const (fp, XVECEXP (x, 0, 0));
2455 fputs ("@TPOFF", fp);
2458 output_addr_const (fp, XVECEXP (x, 0, 0));
2459 fputs ("@DTPOFF", fp);
2464 output_addr_const (fp, XVECEXP (x, 0, 0));
2478 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2485 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2487 switch (GET_MODE_CLASS (mode))
2490 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2492 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2496 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2497 if (HOST_BITS_PER_LONG > 32)
2498 value_long[0] &= 0xffffffff;
2499 fprintf (file, "0x%08lx\n", value_long[0]);
2503 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2504 if (HOST_BITS_PER_LONG > 32)
2506 value_long[0] &= 0xffffffff;
2507 value_long[1] &= 0xffffffff;
2509 fprintf (file, "0x%08lx, 0x%08lx\n",
2510 value_long[0], value_long[1]);
2520 case MODE_PARTIAL_INT:
2521 size = GET_MODE_SIZE (mode);
2525 output_addr_const (file, x);
2530 split_double (x, &first, &second);
2531 output_addr_const (file, first);
2533 output_addr_const (file, second);
2548 /* Return the bytes needed to compute the frame pointer from the current
2551 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2552 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2555 compute_frame_size (int size)
2557 /* Add space for the incoming static chain value. */
2558 if (cfun->static_chain_decl != NULL)
2559 size += (1 * UNITS_PER_WORD);
2561 xtensa_current_frame_size =
2562 XTENSA_STACK_ALIGN (size
2563 + crtl->outgoing_args_size
2564 + (WINDOW_SIZE * UNITS_PER_WORD));
2565 return xtensa_current_frame_size;
2570 xtensa_frame_pointer_required (void)
2572 /* The code to expand builtin_frame_addr and builtin_return_addr
2573 currently uses the hard_frame_pointer instead of frame_pointer.
2574 This seems wrong but maybe it's necessary for other architectures.
2575 This function is derived from the i386 code. */
2577 if (cfun->machine->accesses_prev_frame)
2584 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2585 and the total number of words must be a multiple of 128 bits. */
2586 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2589 xtensa_expand_prologue (void)
2591 HOST_WIDE_INT total_size;
2595 total_size = compute_frame_size (get_frame_size ());
2596 size_rtx = GEN_INT (total_size);
2598 if (total_size < (1 << (12+3)))
2599 insn = emit_insn (gen_entry (size_rtx));
2602 /* Use a8 as a temporary since a0-a7 may be live. */
2603 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2604 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2605 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2606 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2607 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2610 if (frame_pointer_needed)
2612 if (cfun->machine->set_frame_ptr_insn)
2616 push_topmost_sequence ();
2617 first = get_insns ();
2618 pop_topmost_sequence ();
2620 /* For all instructions prior to set_frame_ptr_insn, replace
2621 hard_frame_pointer references with stack_pointer. */
2623 insn != cfun->machine->set_frame_ptr_insn;
2624 insn = NEXT_INSN (insn))
2628 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2629 hard_frame_pointer_rtx,
2631 df_insn_rescan (insn);
2636 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2637 stack_pointer_rtx));
2640 /* Create a note to describe the CFA. Because this is only used to set
2641 DW_AT_frame_base for debug info, don't bother tracking changes through
2642 each instruction in the prologue. It just takes up space. */
2643 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2644 ? hard_frame_pointer_rtx
2645 : stack_pointer_rtx),
2646 plus_constant (stack_pointer_rtx, -total_size));
2647 RTX_FRAME_RELATED_P (insn) = 1;
2648 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx);
2652 /* Clear variables at function end. */
2655 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2656 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2658 xtensa_current_frame_size = 0;
2663 xtensa_return_addr (int count, rtx frame)
2665 rtx result, retaddr, curaddr, label;
2668 retaddr = gen_rtx_REG (Pmode, A0_REG);
2671 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2672 addr = memory_address (Pmode, addr);
2673 retaddr = gen_reg_rtx (Pmode);
2674 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2677 /* The 2 most-significant bits of the return address on Xtensa hold
2678 the register window size. To get the real return address, these
2679 bits must be replaced with the high bits from some address in the
2682 /* Get the 2 high bits of a local label in the code. */
2683 curaddr = gen_reg_rtx (Pmode);
2684 label = gen_label_rtx ();
2686 LABEL_PRESERVE_P (label) = 1;
2687 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2688 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2689 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2691 /* Clear the 2 high bits of the return address. */
2692 result = gen_reg_rtx (Pmode);
2693 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2694 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2696 /* Combine them to get the result. */
2697 emit_insn (gen_iorsi3 (result, result, curaddr));
2702 /* Create the va_list data type.
2704 This structure is set up by __builtin_saveregs. The __va_reg field
2705 points to a stack-allocated region holding the contents of the
2706 incoming argument registers. The __va_ndx field is an index
2707 initialized to the position of the first unnamed (variable)
2708 argument. This same index is also used to address the arguments
2709 passed in memory. Thus, the __va_stk field is initialized to point
2710 to the position of the first argument in memory offset to account
2711 for the arguments passed in registers and to account for the size
2712 of the argument registers not being 16-byte aligned. E.G., there
2713 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2714 for the first stack argument to have the maximal alignment of 16
2715 bytes, so we offset the __va_stk address by 32 bytes so that
2716 __va_stk[32] references the first argument on the stack. */
2719 xtensa_build_builtin_va_list (void)
2721 tree f_stk, f_reg, f_ndx, record, type_decl;
2723 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2724 type_decl = build_decl (BUILTINS_LOCATION,
2725 TYPE_DECL, get_identifier ("__va_list_tag"), record);
2727 f_stk = build_decl (BUILTINS_LOCATION,
2728 FIELD_DECL, get_identifier ("__va_stk"),
2730 f_reg = build_decl (BUILTINS_LOCATION,
2731 FIELD_DECL, get_identifier ("__va_reg"),
2733 f_ndx = build_decl (BUILTINS_LOCATION,
2734 FIELD_DECL, get_identifier ("__va_ndx"),
2737 DECL_FIELD_CONTEXT (f_stk) = record;
2738 DECL_FIELD_CONTEXT (f_reg) = record;
2739 DECL_FIELD_CONTEXT (f_ndx) = record;
2741 TYPE_STUB_DECL (record) = type_decl;
2742 TYPE_NAME (record) = type_decl;
2743 TYPE_FIELDS (record) = f_stk;
2744 DECL_CHAIN (f_stk) = f_reg;
2745 DECL_CHAIN (f_reg) = f_ndx;
2747 layout_type (record);
2752 /* Save the incoming argument registers on the stack. Returns the
2753 address of the saved registers. */
2756 xtensa_builtin_saveregs (void)
2759 int arg_words = crtl->args.info.arg_words;
2760 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2765 /* Allocate the general-purpose register space. */
2766 gp_regs = assign_stack_local
2767 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2768 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2770 /* Now store the incoming registers. */
2771 cfun->machine->need_a7_copy = true;
2772 cfun->machine->vararg_a7 = true;
2773 move_block_from_reg (GP_ARG_FIRST + arg_words,
2774 adjust_address (gp_regs, BLKmode,
2775 arg_words * UNITS_PER_WORD),
2777 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2778 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2780 return XEXP (gp_regs, 0);
2784 /* Implement `va_start' for varargs and stdarg. We look at the
2785 current function to fill in an initial va_list. */
2788 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2796 arg_words = crtl->args.info.arg_words;
2798 f_stk = TYPE_FIELDS (va_list_type_node);
2799 f_reg = DECL_CHAIN (f_stk);
2800 f_ndx = DECL_CHAIN (f_reg);
2802 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2803 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2805 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2808 /* Call __builtin_saveregs; save the result in __va_reg */
2809 u = make_tree (sizetype, expand_builtin_saveregs ());
2810 u = fold_convert (ptr_type_node, u);
2811 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2812 TREE_SIDE_EFFECTS (t) = 1;
2813 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2815 /* Set the __va_stk member to ($arg_ptr - 32). */
2816 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2817 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2818 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2819 TREE_SIDE_EFFECTS (t) = 1;
2820 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2822 /* Set the __va_ndx member. If the first variable argument is on
2823 the stack, adjust __va_ndx by 2 words to account for the extra
2824 alignment offset for __va_stk. */
2825 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2827 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2828 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2829 TREE_SIDE_EFFECTS (t) = 1;
2830 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2834 /* Implement `va_arg'. */
2837 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2838 gimple_seq *post_p ATTRIBUTE_UNUSED)
2843 tree type_size, array, orig_ndx, addr, size, va_size, t;
2844 tree lab_false, lab_over, lab_false2;
2847 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2849 type = build_pointer_type (type);
2851 /* Handle complex values as separate real and imaginary parts. */
2852 if (TREE_CODE (type) == COMPLEX_TYPE)
2854 tree real_part, imag_part;
2856 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2858 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2860 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2863 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2865 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2868 f_stk = TYPE_FIELDS (va_list_type_node);
2869 f_reg = DECL_CHAIN (f_stk);
2870 f_ndx = DECL_CHAIN (f_reg);
2872 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2874 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2876 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2879 type_size = size_in_bytes (type);
2880 va_size = round_up (type_size, UNITS_PER_WORD);
2881 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2884 /* First align __va_ndx if necessary for this arg:
2886 orig_ndx = (AP).__va_ndx;
2887 if (__alignof__ (TYPE) > 4 )
2888 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2889 & -__alignof__ (TYPE)); */
2891 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2893 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2895 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2897 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2898 build_int_cst (integer_type_node, align - 1));
2899 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2900 build_int_cst (integer_type_node, -align));
2901 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2905 /* Increment __va_ndx to point past the argument:
2907 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2909 t = fold_convert (integer_type_node, va_size);
2910 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2911 gimplify_assign (unshare_expr (ndx), t, pre_p);
2914 /* Check if the argument is in registers:
2916 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2917 && !must_pass_in_stack (type))
2918 __array = (AP).__va_reg; */
2920 array = create_tmp_var (ptr_type_node, NULL);
2923 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2925 lab_false = create_artificial_label (UNKNOWN_LOCATION);
2926 lab_over = create_artificial_label (UNKNOWN_LOCATION);
2928 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2929 build_int_cst (integer_type_node,
2930 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2931 t = build3 (COND_EXPR, void_type_node, t,
2932 build1 (GOTO_EXPR, void_type_node, lab_false),
2934 gimplify_and_add (t, pre_p);
2936 gimplify_assign (unshare_expr (array), reg, pre_p);
2938 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2939 gimplify_and_add (t, pre_p);
2941 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2942 gimplify_and_add (t, pre_p);
2946 /* ...otherwise, the argument is on the stack (never split between
2947 registers and the stack -- change __va_ndx if necessary):
2951 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2952 (AP).__va_ndx = 32 + __va_size (TYPE);
2953 __array = (AP).__va_stk;
2956 lab_false2 = create_artificial_label (UNKNOWN_LOCATION);
2958 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
2959 build_int_cst (integer_type_node,
2960 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2961 t = build3 (COND_EXPR, void_type_node, t,
2962 build1 (GOTO_EXPR, void_type_node, lab_false2),
2964 gimplify_and_add (t, pre_p);
2966 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
2967 t = fold_convert (integer_type_node, t);
2968 gimplify_assign (unshare_expr (ndx), t, pre_p);
2970 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2971 gimplify_and_add (t, pre_p);
2973 gimplify_assign (array, stk, pre_p);
2977 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2978 gimplify_and_add (t, pre_p);
2982 /* Given the base array pointer (__array) and index to the subsequent
2983 argument (__va_ndx), find the address:
2985 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2989 The results are endian-dependent because values smaller than one word
2990 are aligned differently. */
2993 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
2995 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
2996 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
2997 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
2998 unshare_expr (type_size));
3002 size = unshare_expr (va_size);
3004 t = fold_convert (sizetype, unshare_expr (ndx));
3005 t = build2 (MINUS_EXPR, sizetype, t, size);
3006 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t);
3008 addr = fold_convert (build_pointer_type (type), addr);
3010 addr = build_va_arg_indirect_ref (addr);
3011 return build_va_arg_indirect_ref (addr);
3019 XTENSA_BUILTIN_UMULSIDI3,
3020 XTENSA_BUILTIN_THREAD_POINTER,
3021 XTENSA_BUILTIN_SET_THREAD_POINTER,
3027 xtensa_init_builtins (void)
3031 ftype = build_function_type_list (unsigned_intDI_type_node,
3032 unsigned_intSI_type_node,
3033 unsigned_intSI_type_node, NULL_TREE);
3035 decl = add_builtin_function ("__builtin_umulsidi3", ftype,
3036 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
3037 "__umulsidi3", NULL_TREE);
3038 TREE_NOTHROW (decl) = 1;
3039 TREE_READONLY (decl) = 1;
3041 if (TARGET_THREADPTR)
3043 ftype = build_function_type (ptr_type_node, void_list_node);
3044 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
3045 XTENSA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
3047 TREE_READONLY (decl) = 1;
3048 TREE_NOTHROW (decl) = 1;
3050 ftype = build_function_type_list (void_type_node, ptr_type_node,
3052 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
3053 XTENSA_BUILTIN_SET_THREAD_POINTER,
3054 BUILT_IN_MD, NULL, NULL_TREE);
3055 TREE_NOTHROW (decl) = 1;
3061 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
3062 bool ignore ATTRIBUTE_UNUSED)
3064 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3069 case XTENSA_BUILTIN_UMULSIDI3:
3072 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
3073 || TARGET_MUL32_HIGH)
3074 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
3075 fold_convert (unsigned_intDI_type_node, arg0),
3076 fold_convert (unsigned_intDI_type_node, arg1));
3079 case XTENSA_BUILTIN_THREAD_POINTER:
3080 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3084 internal_error ("bad builtin code");
3093 xtensa_expand_builtin (tree exp, rtx target,
3094 rtx subtarget ATTRIBUTE_UNUSED,
3095 enum machine_mode mode ATTRIBUTE_UNUSED,
3098 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
3099 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3104 case XTENSA_BUILTIN_UMULSIDI3:
3105 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3106 __umulsidi3 function when the Xtensa configuration can directly
3107 implement it. If not, just call the function. */
3108 return expand_call (exp, target, ignore);
3110 case XTENSA_BUILTIN_THREAD_POINTER:
3111 if (!target || !register_operand (target, Pmode))
3112 target = gen_reg_rtx (Pmode);
3113 emit_insn (gen_load_tp (target));
3116 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3117 arg = expand_normal (CALL_EXPR_ARG (exp, 0));
3118 if (!register_operand (arg, Pmode))
3119 arg = copy_to_mode_reg (Pmode, arg);
3120 emit_insn (gen_set_tp (arg));
3124 internal_error ("bad builtin code");
3131 xtensa_preferred_reload_class (rtx x, enum reg_class rclass, int isoutput)
3133 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
3136 /* Don't use the stack pointer or hard frame pointer for reloads!
3137 The hard frame pointer would normally be OK except that it may
3138 briefly hold an incoming argument in the prologue, and reload
3139 won't know that it is live because the hard frame pointer is
3140 treated specially. */
3142 if (rclass == AR_REGS || rclass == GR_REGS)
3150 xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
3151 enum machine_mode mode, secondary_reload_info *sri)
3155 if (in_p && constantpool_mem_p (x))
3157 if (rclass == FP_REGS)
3161 sri->icode = CODE_FOR_reloadqi_literal;
3162 else if (mode == HImode)
3163 sri->icode = CODE_FOR_reloadhi_literal;
3166 regno = xt_true_regnum (x);
3167 if (ACC_REG_P (regno))
3168 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS);
3169 if (rclass == ACC_REG)
3170 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
3177 order_regs_for_local_alloc (void)
3179 if (!leaf_function_p ())
3181 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
3182 FIRST_PSEUDO_REGISTER * sizeof (int));
3186 int i, num_arg_regs;
3189 /* Use the AR registers in increasing order (skipping a0 and a1)
3190 but save the incoming argument registers for a last resort. */
3191 num_arg_regs = crtl->args.info.arg_words;
3192 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
3193 num_arg_regs = MAX_ARGS_IN_REGISTERS;
3194 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
3195 reg_alloc_order[nxt++] = i + num_arg_regs;
3196 for (i = 0; i < num_arg_regs; i++)
3197 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
3199 /* List the coprocessor registers in order. */
3200 for (i = 0; i < BR_REG_NUM; i++)
3201 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
3203 /* List the FP registers in order for now. */
3204 for (i = 0; i < 16; i++)
3205 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
3207 /* GCC requires that we list *all* the registers.... */
3208 reg_alloc_order[nxt++] = 0; /* a0 = return address */
3209 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
3210 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
3211 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
3213 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
3218 /* Some Xtensa targets support multiple bss sections. If the section
3219 name ends with ".bss", add SECTION_BSS to the flags. */
3222 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
3224 unsigned int flags = default_section_type_flags (decl, name, reloc);
3227 suffix = strrchr (name, '.');
3228 if (suffix && strcmp (suffix, ".bss") == 0)
3230 if (!decl || (TREE_CODE (decl) == VAR_DECL
3231 && DECL_INITIAL (decl) == NULL_TREE))
3232 flags |= SECTION_BSS; /* @nobits */
3234 warning (0, "only uninitialized variables can be placed in a "
3242 /* The literal pool stays with the function. */
3245 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
3246 rtx x ATTRIBUTE_UNUSED,
3247 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
3249 return function_section (current_function_decl);
3253 /* Compute a (partial) cost for rtx X. Return true if the complete
3254 cost has been computed, and false if subexpressions should be
3255 scanned. In either case, *TOTAL contains the cost result. */
3258 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total,
3259 bool speed ATTRIBUTE_UNUSED)
3267 if (xtensa_simm12b (INTVAL (x)))
3274 if (xtensa_simm8 (INTVAL (x))
3275 || xtensa_simm8x256 (INTVAL (x)))
3282 if (xtensa_mask_immediate (INTVAL (x)))
3289 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
3300 /* No way to tell if X is the 2nd operand so be conservative. */
3303 if (xtensa_simm12b (INTVAL (x)))
3305 else if (TARGET_CONST16)
3306 *total = COSTS_N_INSNS (2);
3315 *total = COSTS_N_INSNS (2);
3322 *total = COSTS_N_INSNS (4);
3330 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3332 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3333 *total = COSTS_N_INSNS (num_words);
3335 *total = COSTS_N_INSNS (2*num_words);
3341 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3345 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3349 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3355 if (GET_MODE (x) == DImode)
3356 *total = COSTS_N_INSNS (2);
3358 *total = COSTS_N_INSNS (1);
3364 if (GET_MODE (x) == DImode)
3365 *total = COSTS_N_INSNS (50);
3367 *total = COSTS_N_INSNS (1);
3372 enum machine_mode xmode = GET_MODE (x);
3373 if (xmode == SFmode)
3374 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3375 else if (xmode == DFmode)
3376 *total = COSTS_N_INSNS (50);
3378 *total = COSTS_N_INSNS (4);
3385 enum machine_mode xmode = GET_MODE (x);
3386 if (xmode == SFmode)
3387 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3388 else if (xmode == DFmode || xmode == DImode)
3389 *total = COSTS_N_INSNS (50);
3391 *total = COSTS_N_INSNS (1);
3396 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3401 enum machine_mode xmode = GET_MODE (x);
3402 if (xmode == SFmode)
3403 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3404 else if (xmode == DFmode)
3405 *total = COSTS_N_INSNS (50);
3406 else if (xmode == DImode)
3407 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3408 else if (TARGET_MUL32)
3409 *total = COSTS_N_INSNS (4);
3410 else if (TARGET_MAC16)
3411 *total = COSTS_N_INSNS (16);
3412 else if (TARGET_MUL16)
3413 *total = COSTS_N_INSNS (12);
3415 *total = COSTS_N_INSNS (50);
3422 enum machine_mode xmode = GET_MODE (x);
3423 if (xmode == SFmode)
3425 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3428 else if (xmode == DFmode)
3430 *total = COSTS_N_INSNS (50);
3439 enum machine_mode xmode = GET_MODE (x);
3440 if (xmode == DImode)
3441 *total = COSTS_N_INSNS (50);
3442 else if (TARGET_DIV32)
3443 *total = COSTS_N_INSNS (32);
3445 *total = COSTS_N_INSNS (50);
3450 if (GET_MODE (x) == SFmode)
3451 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3453 *total = COSTS_N_INSNS (50);
3460 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3465 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3470 *total = COSTS_N_INSNS (1);
3478 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3481 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3483 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3484 > 4 * UNITS_PER_WORD);
3487 /* Worker function for TARGET_FUNCTION_VALUE. */
3490 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3493 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3494 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3495 ? SImode : TYPE_MODE (valtype),
3496 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3499 /* The static chain is passed in memory. Provide rtx giving 'mem'
3500 expressions that denote where they are stored. */
3503 xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
3505 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx;
3506 return gen_frame_mem (Pmode, plus_constant (base, -5 * UNITS_PER_WORD));
3510 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3511 instruction with a minimal stack frame in order to get some free
3512 registers. Once the actual call target is known, the proper stack frame
3513 size is extracted from the ENTRY instruction at the target and the
3514 current frame is adjusted to match. The trampoline then transfers
3515 control to the instruction following the ENTRY at the target. Note:
3516 this assumes that the target begins with an ENTRY instruction. */
3519 xtensa_asm_trampoline_template (FILE *stream)
3521 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3523 fprintf (stream, "\t.begin no-transform\n");
3524 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3528 /* Save the return address. */
3529 fprintf (stream, "\tmov\ta10, a0\n");
3531 /* Use a CALL0 instruction to skip past the constants and in the
3532 process get the PC into A0. This allows PC-relative access to
3533 the constants without relying on L32R. */
3534 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3537 fprintf (stream, "\tj\t.Lskipconsts\n");
3539 fprintf (stream, "\t.align\t4\n");
3540 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3541 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3542 fprintf (stream, ".Lskipconsts:\n");
3544 /* Load the static chain and function address from the trampoline. */
3547 fprintf (stream, "\taddi\ta0, a0, 3\n");
3548 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3549 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3553 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3554 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3557 /* Store the static chain. */
3558 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3560 /* Set the proper stack pointer value. */
3561 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3562 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3563 TARGET_BIG_ENDIAN ? 8 : 12);
3564 fprintf (stream, "\tslli\ta9, a9, 3\n");
3565 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3566 fprintf (stream, "\tsub\ta9, sp, a9\n");
3567 fprintf (stream, "\tmovsp\tsp, a9\n");
3570 /* Restore the return address. */
3571 fprintf (stream, "\tmov\ta0, a10\n");
3573 /* Jump to the instruction following the ENTRY. */
3574 fprintf (stream, "\taddi\ta8, a8, 3\n");
3575 fprintf (stream, "\tjx\ta8\n");
3577 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3579 fprintf (stream, "\t.byte\t0\n");
3581 fprintf (stream, "\tnop\n");
3583 fprintf (stream, "\t.end no-transform\n");
3587 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
3589 rtx func = XEXP (DECL_RTL (fndecl), 0);
3590 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3591 int chain_off = use_call0 ? 12 : 8;
3592 int func_off = use_call0 ? 16 : 12;
3594 emit_block_move (m_tramp, assemble_trampoline_template (),
3595 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3597 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain);
3598 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func);
3599 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3600 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
3604 #include "gt-xtensa.h"