1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
33 #include "insn-attr.h"
34 #include "insn-codes.h"
43 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 /* Enumeration for all of the relational tests, so that we can build
55 arrays indexed by the test type, and not worry about the order
73 /* Array giving truth value on whether or not a given hard register
74 can support a given mode. */
75 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
77 /* Current frame size calculated by compute_frame_size. */
78 unsigned xtensa_current_frame_size;
80 /* Largest block move to handle in-line. */
81 #define LARGEST_MOVE_RATIO 15
83 /* Define the structure for the machine field in struct function. */
84 struct GTY(()) machine_function
86 int accesses_prev_frame;
90 rtx set_frame_ptr_insn;
93 /* Vector, indexed by hard register number, which contains 1 for a
94 register that is allowable in a candidate for leaf function
97 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
99 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
101 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
105 /* Map hard register number to register class */
106 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
108 RL_REGS, SP_REG, RL_REGS, RL_REGS,
109 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
110 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
111 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
112 AR_REGS, AR_REGS, BR_REGS,
113 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
114 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
115 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
116 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
120 static void xtensa_option_override (void);
121 static enum internal_test map_test_to_internal_test (enum rtx_code);
122 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
123 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
124 static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx);
125 static rtx fixup_subreg_mem (rtx);
126 static struct machine_function * xtensa_init_machine_status (void);
127 static rtx xtensa_legitimize_tls_address (rtx);
128 static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode);
129 static bool xtensa_mode_dependent_address_p (const_rtx);
130 static bool xtensa_return_in_msb (const_tree);
131 static void printx (FILE *, signed int);
132 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
133 static rtx xtensa_builtin_saveregs (void);
134 static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool);
135 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
136 int) ATTRIBUTE_UNUSED;
137 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
138 unsigned HOST_WIDE_INT);
139 static bool xtensa_rtx_costs (rtx, int, int, int *, bool);
140 static int xtensa_register_move_cost (enum machine_mode, reg_class_t,
142 static int xtensa_memory_move_cost (enum machine_mode, reg_class_t, bool);
143 static tree xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree, const_tree);
145 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
147 static void xtensa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
149 static rtx xtensa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
151 static rtx xtensa_function_incoming_arg (CUMULATIVE_ARGS *,
152 enum machine_mode, const_tree, bool);
153 static rtx xtensa_function_value (const_tree, const_tree, bool);
154 static rtx xtensa_libcall_value (enum machine_mode, const_rtx);
155 static bool xtensa_function_value_regno_p (const unsigned int);
156 static unsigned int xtensa_function_arg_boundary (enum machine_mode,
158 static void xtensa_init_builtins (void);
159 static tree xtensa_fold_builtin (tree, int, tree *, bool);
160 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
161 static void xtensa_va_start (tree, rtx);
162 static bool xtensa_frame_pointer_required (void);
163 static rtx xtensa_static_chain (const_tree, bool);
164 static void xtensa_asm_trampoline_template (FILE *);
165 static void xtensa_trampoline_init (rtx, tree, rtx);
166 static bool xtensa_output_addr_const_extra (FILE *, rtx);
167 static bool xtensa_cannot_force_const_mem (enum machine_mode, rtx);
169 static reg_class_t xtensa_preferred_reload_class (rtx, reg_class_t);
170 static reg_class_t xtensa_preferred_output_reload_class (rtx, reg_class_t);
171 static reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t,
173 struct secondary_reload_info *);
175 static bool constantpool_address_p (const_rtx addr);
176 static bool xtensa_legitimate_constant_p (enum machine_mode, rtx);
178 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
181 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
183 static const struct default_options xtensa_option_optimization_table[] =
185 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
186 /* Reordering blocks for Xtensa is not a good idea unless the
187 compiler understands the range of conditional branches.
188 Currently all branch relaxation for Xtensa is handled in the
189 assembler, so GCC cannot do a good job of reordering blocks.
190 Do not enable reordering unless it is explicitly requested. */
191 { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 },
192 { OPT_LEVELS_NONE, 0, NULL, 0 }
196 /* This macro generates the assembly code for function exit,
197 on machines that need it. If FUNCTION_EPILOGUE is not defined
198 then individual return instructions are generated for each
199 return statement. Args are same as for FUNCTION_PROLOGUE. */
201 #undef TARGET_ASM_FUNCTION_EPILOGUE
202 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
204 /* These hooks specify assembly directives for creating certain kinds
205 of integer object. */
207 #undef TARGET_ASM_ALIGNED_SI_OP
208 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
210 #undef TARGET_ASM_SELECT_RTX_SECTION
211 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
213 #undef TARGET_DEFAULT_TARGET_FLAGS
214 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
216 #undef TARGET_LEGITIMIZE_ADDRESS
217 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
218 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
219 #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p
221 #undef TARGET_REGISTER_MOVE_COST
222 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost
223 #undef TARGET_MEMORY_MOVE_COST
224 #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost
225 #undef TARGET_RTX_COSTS
226 #define TARGET_RTX_COSTS xtensa_rtx_costs
227 #undef TARGET_ADDRESS_COST
228 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
230 #undef TARGET_BUILD_BUILTIN_VA_LIST
231 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
233 #undef TARGET_EXPAND_BUILTIN_VA_START
234 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
236 #undef TARGET_PROMOTE_FUNCTION_MODE
237 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
238 #undef TARGET_PROMOTE_PROTOTYPES
239 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
241 #undef TARGET_RETURN_IN_MEMORY
242 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
243 #undef TARGET_FUNCTION_VALUE
244 #define TARGET_FUNCTION_VALUE xtensa_function_value
245 #undef TARGET_LIBCALL_VALUE
246 #define TARGET_LIBCALL_VALUE xtensa_libcall_value
247 #undef TARGET_FUNCTION_VALUE_REGNO_P
248 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p
250 #undef TARGET_SPLIT_COMPLEX_ARG
251 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
252 #undef TARGET_MUST_PASS_IN_STACK
253 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
254 #undef TARGET_FUNCTION_ARG_ADVANCE
255 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
256 #undef TARGET_FUNCTION_ARG
257 #define TARGET_FUNCTION_ARG xtensa_function_arg
258 #undef TARGET_FUNCTION_INCOMING_ARG
259 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
260 #undef TARGET_FUNCTION_ARG_BOUNDARY
261 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
263 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
264 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
265 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
266 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
268 #undef TARGET_RETURN_IN_MSB
269 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
271 #undef TARGET_INIT_BUILTINS
272 #define TARGET_INIT_BUILTINS xtensa_init_builtins
273 #undef TARGET_FOLD_BUILTIN
274 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
275 #undef TARGET_EXPAND_BUILTIN
276 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
278 #undef TARGET_PREFERRED_RELOAD_CLASS
279 #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class
280 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
281 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class
283 #undef TARGET_SECONDARY_RELOAD
284 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
286 #undef TARGET_HAVE_TLS
287 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
289 #undef TARGET_CANNOT_FORCE_CONST_MEM
290 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem
292 #undef TARGET_LEGITIMATE_ADDRESS_P
293 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
295 #undef TARGET_FRAME_POINTER_REQUIRED
296 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
298 #undef TARGET_STATIC_CHAIN
299 #define TARGET_STATIC_CHAIN xtensa_static_chain
300 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
301 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
302 #undef TARGET_TRAMPOLINE_INIT
303 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
305 #undef TARGET_OPTION_OVERRIDE
306 #define TARGET_OPTION_OVERRIDE xtensa_option_override
307 #undef TARGET_OPTION_OPTIMIZATION_TABLE
308 #define TARGET_OPTION_OPTIMIZATION_TABLE xtensa_option_optimization_table
310 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
311 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
313 #undef TARGET_LEGITIMATE_CONSTANT_P
314 #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p
316 struct gcc_target targetm = TARGET_INITIALIZER;
319 /* Functions to test Xtensa immediate operand validity. */
322 xtensa_simm8 (HOST_WIDE_INT v)
324 return v >= -128 && v <= 127;
329 xtensa_simm8x256 (HOST_WIDE_INT v)
331 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
336 xtensa_simm12b (HOST_WIDE_INT v)
338 return v >= -2048 && v <= 2047;
343 xtensa_uimm8 (HOST_WIDE_INT v)
345 return v >= 0 && v <= 255;
350 xtensa_uimm8x2 (HOST_WIDE_INT v)
352 return (v & 1) == 0 && (v >= 0 && v <= 510);
357 xtensa_uimm8x4 (HOST_WIDE_INT v)
359 return (v & 3) == 0 && (v >= 0 && v <= 1020);
364 xtensa_b4const (HOST_WIDE_INT v)
391 xtensa_b4const_or_zero (HOST_WIDE_INT v)
395 return xtensa_b4const (v);
400 xtensa_b4constu (HOST_WIDE_INT v)
427 xtensa_mask_immediate (HOST_WIDE_INT v)
429 #define MAX_MASK_SIZE 16
432 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
445 /* This is just like the standard true_regnum() function except that it
446 works even when reg_renumber is not initialized. */
449 xt_true_regnum (rtx x)
451 if (GET_CODE (x) == REG)
454 && REGNO (x) >= FIRST_PSEUDO_REGISTER
455 && reg_renumber[REGNO (x)] >= 0)
456 return reg_renumber[REGNO (x)];
459 if (GET_CODE (x) == SUBREG)
461 int base = xt_true_regnum (SUBREG_REG (x));
462 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
463 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
464 GET_MODE (SUBREG_REG (x)),
465 SUBREG_BYTE (x), GET_MODE (x));
472 xtensa_valid_move (enum machine_mode mode, rtx *operands)
474 /* Either the destination or source must be a register, and the
475 MAC16 accumulator doesn't count. */
477 if (register_operand (operands[0], mode))
479 int dst_regnum = xt_true_regnum (operands[0]);
481 /* The stack pointer can only be assigned with a MOVSP opcode. */
482 if (dst_regnum == STACK_POINTER_REGNUM)
483 return (mode == SImode
484 && register_operand (operands[1], mode)
485 && !ACC_REG_P (xt_true_regnum (operands[1])));
487 if (!ACC_REG_P (dst_regnum))
490 if (register_operand (operands[1], mode))
492 int src_regnum = xt_true_regnum (operands[1]);
493 if (!ACC_REG_P (src_regnum))
501 smalloffset_mem_p (rtx op)
503 if (GET_CODE (op) == MEM)
505 rtx addr = XEXP (op, 0);
506 if (GET_CODE (addr) == REG)
507 return BASE_REG_P (addr, 0);
508 if (GET_CODE (addr) == PLUS)
510 rtx offset = XEXP (addr, 0);
512 if (GET_CODE (offset) != CONST_INT)
513 offset = XEXP (addr, 1);
514 if (GET_CODE (offset) != CONST_INT)
517 val = INTVAL (offset);
518 return (val & 3) == 0 && (val >= 0 && val <= 60);
526 constantpool_address_p (const_rtx addr)
528 const_rtx sym = addr;
530 if (GET_CODE (addr) == CONST)
534 /* Only handle (PLUS (SYM, OFFSET)) form. */
535 addr = XEXP (addr, 0);
536 if (GET_CODE (addr) != PLUS)
539 /* Make sure the address is word aligned. */
540 offset = XEXP (addr, 1);
541 if ((!CONST_INT_P (offset))
542 || ((INTVAL (offset) & 3) != 0))
545 sym = XEXP (addr, 0);
548 if ((GET_CODE (sym) == SYMBOL_REF)
549 && CONSTANT_POOL_ADDRESS_P (sym))
556 constantpool_mem_p (rtx op)
558 if (GET_CODE (op) == SUBREG)
559 op = SUBREG_REG (op);
560 if (GET_CODE (op) == MEM)
561 return constantpool_address_p (XEXP (op, 0));
566 /* Return TRUE if X is a thread-local symbol. */
569 xtensa_tls_symbol_p (rtx x)
571 if (! TARGET_HAVE_TLS)
574 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
579 xtensa_extend_reg (rtx dst, rtx src)
581 rtx temp = gen_reg_rtx (SImode);
582 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
584 /* Generate paradoxical subregs as needed so that the modes match. */
585 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
586 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
588 emit_insn (gen_ashlsi3 (temp, src, shift));
589 emit_insn (gen_ashrsi3 (dst, temp, shift));
594 xtensa_mem_offset (unsigned v, enum machine_mode mode)
599 /* Handle the worst case for block moves. See xtensa_expand_block_move
600 where we emit an optimized block move operation if the block can be
601 moved in < "move_ratio" pieces. The worst case is when the block is
602 aligned but has a size of (3 mod 4) (does this happen?) so that the
603 last piece requires a byte load/store. */
604 return (xtensa_uimm8 (v)
605 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
608 return xtensa_uimm8 (v);
611 return xtensa_uimm8x2 (v);
614 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
620 return xtensa_uimm8x4 (v);
624 /* Make normal rtx_code into something we can index from an array. */
626 static enum internal_test
627 map_test_to_internal_test (enum rtx_code test_code)
629 enum internal_test test = ITEST_MAX;
634 case EQ: test = ITEST_EQ; break;
635 case NE: test = ITEST_NE; break;
636 case GT: test = ITEST_GT; break;
637 case GE: test = ITEST_GE; break;
638 case LT: test = ITEST_LT; break;
639 case LE: test = ITEST_LE; break;
640 case GTU: test = ITEST_GTU; break;
641 case GEU: test = ITEST_GEU; break;
642 case LTU: test = ITEST_LTU; break;
643 case LEU: test = ITEST_LEU; break;
650 /* Generate the code to compare two integer values. The return value is
651 the comparison expression. */
654 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
655 rtx cmp0, /* first operand to compare */
656 rtx cmp1, /* second operand to compare */
657 int *p_invert /* whether branch needs to reverse test */)
661 enum rtx_code test_code; /* test code to use in insn */
662 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
663 int const_add; /* constant to add (convert LE -> LT) */
664 int reverse_regs; /* reverse registers in test */
665 int invert_const; /* != 0 if invert value if cmp1 is constant */
666 int invert_reg; /* != 0 if invert value if cmp1 is register */
667 int unsignedp; /* != 0 for unsigned comparisons. */
670 static struct cmp_info info[ (int)ITEST_MAX ] = {
672 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
673 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
675 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
676 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
677 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
678 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
680 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
681 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
682 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
683 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
686 enum internal_test test;
687 enum machine_mode mode;
688 struct cmp_info *p_info;
690 test = map_test_to_internal_test (test_code);
691 gcc_assert (test != ITEST_MAX);
693 p_info = &info[ (int)test ];
695 mode = GET_MODE (cmp0);
696 if (mode == VOIDmode)
697 mode = GET_MODE (cmp1);
699 /* Make sure we can handle any constants given to us. */
700 if (GET_CODE (cmp1) == CONST_INT)
702 HOST_WIDE_INT value = INTVAL (cmp1);
703 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
705 /* if the immediate overflows or does not fit in the immediate field,
706 spill it to a register */
708 if ((p_info->unsignedp ?
709 (uvalue + p_info->const_add > uvalue) :
710 (value + p_info->const_add > value)) != (p_info->const_add > 0))
712 cmp1 = force_reg (mode, cmp1);
714 else if (!(p_info->const_range_p) (value + p_info->const_add))
716 cmp1 = force_reg (mode, cmp1);
719 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
721 cmp1 = force_reg (mode, cmp1);
724 /* See if we need to invert the result. */
725 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
726 ? p_info->invert_const
727 : p_info->invert_reg);
729 /* Comparison to constants, may involve adding 1 to change a LT into LE.
730 Comparison between two registers, may involve switching operands. */
731 if (GET_CODE (cmp1) == CONST_INT)
733 if (p_info->const_add != 0)
734 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
737 else if (p_info->reverse_regs)
744 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
748 /* Generate the code to compare two float values. The return value is
749 the comparison expression. */
752 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
753 rtx cmp0, /* first operand to compare */
754 rtx cmp1 /* second operand to compare */)
756 rtx (*gen_fn) (rtx, rtx, rtx);
758 int reverse_regs, invert;
762 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
763 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
764 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
765 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
766 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
767 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
768 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
769 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
770 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
771 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
772 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
773 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
775 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
777 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
779 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
780 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
790 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
791 emit_insn (gen_fn (brtmp, cmp0, cmp1));
793 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
798 xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode)
800 enum rtx_code test_code = GET_CODE (operands[0]);
801 rtx cmp0 = operands[1];
802 rtx cmp1 = operands[2];
811 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
815 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
819 if (!TARGET_HARD_FLOAT)
820 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
823 cmp = gen_float_relational (test_code, cmp0, cmp1);
827 /* Generate the branch. */
829 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
838 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
839 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
846 gen_conditional_move (enum rtx_code code, enum machine_mode mode,
853 /* Jump optimization calls get_condition() which canonicalizes
854 comparisons like (GE x <const>) to (GT x <const-1>).
855 Transform those comparisons back to GE, since that is the
856 comparison supported in Xtensa. We shouldn't have to
857 transform <LE x const> comparisons, because neither
858 xtensa_expand_conditional_branch() nor get_condition() will
861 if ((code == GT) && (op1 == constm1_rtx))
866 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
868 if (boolean_operator (cmp, VOIDmode))
870 /* Swap the operands to make const0 second. */
871 if (op0 == const0_rtx)
877 /* If not comparing against zero, emit a comparison (subtract). */
878 if (op1 != const0_rtx)
880 op0 = expand_binop (SImode, sub_optab, op0, op1,
881 0, 0, OPTAB_LIB_WIDEN);
885 else if (branch_operator (cmp, VOIDmode))
887 /* Swap the operands to make const0 second. */
888 if (op0 == const0_rtx)
895 case LT: code = GE; break;
896 case GE: code = LT; break;
897 default: gcc_unreachable ();
901 if (op1 != const0_rtx)
907 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
910 if (TARGET_HARD_FLOAT && mode == SFmode)
911 return gen_float_relational (code, op0, op1);
918 xtensa_expand_conditional_move (rtx *operands, int isflt)
920 rtx dest = operands[0];
921 rtx cmp = operands[1];
922 enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0));
923 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
925 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode,
926 XEXP (cmp, 0), XEXP (cmp, 1))))
930 gen_fn = (cmp_mode == SImode
931 ? gen_movsfcc_internal0
932 : gen_movsfcc_internal1);
934 gen_fn = (cmp_mode == SImode
935 ? gen_movsicc_internal0
936 : gen_movsicc_internal1);
938 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp));
944 xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode)
946 rtx dest = operands[0];
948 rtx one_tmp, zero_tmp;
949 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
951 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode,
952 operands[2], operands[3])))
955 one_tmp = gen_reg_rtx (SImode);
956 zero_tmp = gen_reg_rtx (SImode);
957 emit_insn (gen_movsi (one_tmp, const_true_rtx));
958 emit_insn (gen_movsi (zero_tmp, const0_rtx));
960 gen_fn = (cmp_mode == SImode
961 ? gen_movsicc_internal0
962 : gen_movsicc_internal1);
963 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
968 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
969 for the output, i.e., the input operands are twice as big as MODE. */
972 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
974 switch (GET_CODE (operands[1]))
977 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
978 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
982 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
983 operands[2] = adjust_address (operands[1], mode, 0);
988 split_double (operands[1], &operands[2], &operands[3]);
995 switch (GET_CODE (operands[0]))
998 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
999 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
1003 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
1004 operands[0] = adjust_address (operands[0], mode, 0);
1013 /* Emit insns to move operands[1] into operands[0].
1014 Return 1 if we have written out everything that needs to be done to
1015 do the move. Otherwise, return 0 and the caller will emit the move
1019 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
1021 rtx src = operands[1];
1023 if (CONSTANT_P (src)
1024 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
1026 rtx dst = operands[0];
1028 if (xtensa_tls_referenced_p (src))
1032 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
1034 addend = XEXP (XEXP (src, 0), 1);
1035 src = XEXP (XEXP (src, 0), 0);
1038 src = xtensa_legitimize_tls_address (src);
1041 src = gen_rtx_PLUS (mode, src, addend);
1042 src = force_operand (src, dst);
1044 emit_move_insn (dst, src);
1048 if (! TARGET_CONST16)
1050 src = force_const_mem (SImode, src);
1054 /* PC-relative loads are always SImode, and CONST16 is only
1055 supported in the movsi pattern, so add a SUBREG for any other
1060 if (register_operand (dst, mode))
1062 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src);
1067 src = force_reg (SImode, src);
1068 src = gen_lowpart_SUBREG (mode, src);
1074 if (!(reload_in_progress | reload_completed)
1075 && !xtensa_valid_move (mode, operands))
1076 operands[1] = force_reg (mode, operands[1]);
1078 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1080 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1081 instruction won't be recognized after reload, so we remove the
1082 subreg and adjust mem accordingly. */
1083 if (reload_in_progress)
1085 operands[0] = fixup_subreg_mem (operands[0]);
1086 operands[1] = fixup_subreg_mem (operands[1]);
1093 fixup_subreg_mem (rtx x)
1095 if (GET_CODE (x) == SUBREG
1096 && GET_CODE (SUBREG_REG (x)) == REG
1097 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
1100 gen_rtx_SUBREG (GET_MODE (x),
1101 reg_equiv_mem (REGNO (SUBREG_REG (x))),
1103 x = alter_subreg (&temp);
1109 /* Check if an incoming argument in a7 is expected to be used soon and
1110 if OPND is a register or register pair that includes a7. If so,
1111 create a new pseudo and copy a7 into that pseudo at the very
1112 beginning of the function, followed by the special "set_frame_ptr"
1113 unspec_volatile insn. The return value is either the original
1114 operand, if it is not a7, or the new pseudo containing a copy of
1115 the incoming argument. This is necessary because the register
1116 allocator will ignore conflicts with a7 and may either assign some
1117 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1118 the incoming argument in a7. By copying the argument out of a7 as
1119 the very first thing, and then immediately following that with an
1120 unspec_volatile to keep the scheduler away, we should avoid any
1121 problems. Putting the set_frame_ptr insn at the beginning, with
1122 only the a7 copy before it, also makes it easier for the prologue
1123 expander to initialize the frame pointer after the a7 copy and to
1124 fix up the a7 copy to use the stack pointer instead of the frame
1128 xtensa_copy_incoming_a7 (rtx opnd)
1130 rtx entry_insns = 0;
1132 enum machine_mode mode;
1134 if (!cfun->machine->need_a7_copy)
1137 /* This function should never be called again once a7 has been copied. */
1138 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1140 mode = GET_MODE (opnd);
1142 /* The operand using a7 may come in a later instruction, so just return
1143 the original operand if it doesn't use a7. */
1145 if (GET_CODE (reg) == SUBREG)
1147 gcc_assert (SUBREG_BYTE (reg) == 0);
1148 reg = SUBREG_REG (reg);
1150 if (GET_CODE (reg) != REG
1151 || REGNO (reg) > A7_REG
1152 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1155 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1156 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1158 cfun->machine->need_a7_copy = false;
1160 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1161 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1164 tmp = gen_reg_rtx (mode);
1170 /* Copy the value out of A7 here but keep the first word in A6 until
1171 after the set_frame_ptr insn. Otherwise, the register allocator
1172 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1174 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1175 gen_raw_REG (SImode, A7_REG)));
1178 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1181 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1184 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1187 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1193 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1195 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1196 if (mode == DFmode || mode == DImode)
1197 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1198 gen_rtx_REG (SImode, A7_REG - 1)));
1199 entry_insns = get_insns ();
1202 if (cfun->machine->vararg_a7)
1204 /* This is called from within builtin_saveregs, which will insert the
1205 saveregs code at the function entry, ahead of anything placed at
1206 the function entry now. Instead, save the sequence to be inserted
1207 at the beginning of the saveregs code. */
1208 cfun->machine->vararg_a7_copy = entry_insns;
1212 /* Put entry_insns after the NOTE that starts the function. If
1213 this is inside a start_sequence, make the outer-level insn
1214 chain current, so the code is placed at the start of the
1216 push_topmost_sequence ();
1217 /* Do not use entry_of_function() here. This is called from within
1218 expand_function_start, when the CFG still holds GIMPLE. */
1219 emit_insn_after (entry_insns, get_insns ());
1220 pop_topmost_sequence ();
1227 /* Try to expand a block move operation to a sequence of RTL move
1228 instructions. If not optimizing, or if the block size is not a
1229 constant, or if the block is too large, the expansion fails and GCC
1230 falls back to calling memcpy().
1232 operands[0] is the destination
1233 operands[1] is the source
1234 operands[2] is the length
1235 operands[3] is the alignment */
1238 xtensa_expand_block_move (rtx *operands)
1240 static const enum machine_mode mode_from_align[] =
1242 VOIDmode, QImode, HImode, VOIDmode, SImode,
1245 rtx dst_mem = operands[0];
1246 rtx src_mem = operands[1];
1247 HOST_WIDE_INT bytes, align;
1248 int num_pieces, move_ratio;
1250 enum machine_mode mode[2];
1259 /* If this is not a fixed size move, just call memcpy. */
1260 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1263 bytes = INTVAL (operands[2]);
1264 align = INTVAL (operands[3]);
1266 /* Anything to move? */
1270 if (align > MOVE_MAX)
1273 /* Decide whether to expand inline based on the optimization level. */
1276 move_ratio = LARGEST_MOVE_RATIO;
1277 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1278 if (num_pieces > move_ratio)
1281 x = XEXP (dst_mem, 0);
1284 x = force_reg (Pmode, x);
1285 dst_mem = replace_equiv_address (dst_mem, x);
1288 x = XEXP (src_mem, 0);
1291 x = force_reg (Pmode, x);
1292 src_mem = replace_equiv_address (src_mem, x);
1295 active[0] = active[1] = false;
1306 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1307 next_amount = MIN (next_amount, align);
1309 amount[next] = next_amount;
1310 mode[next] = mode_from_align[next_amount];
1311 temp[next] = gen_reg_rtx (mode[next]);
1313 x = adjust_address (src_mem, mode[next], offset_ld);
1314 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1316 offset_ld += next_amount;
1317 bytes -= next_amount;
1318 active[next] = true;
1323 active[phase] = false;
1325 x = adjust_address (dst_mem, mode[phase], offset_st);
1326 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1328 offset_st += amount[phase];
1331 while (active[next]);
1338 xtensa_expand_nonlocal_goto (rtx *operands)
1340 rtx goto_handler = operands[1];
1341 rtx containing_fp = operands[3];
1343 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1344 is too big to generate in-line. */
1346 if (GET_CODE (containing_fp) != REG)
1347 containing_fp = force_reg (Pmode, containing_fp);
1349 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1350 LCT_NORMAL, VOIDmode, 2,
1351 containing_fp, Pmode,
1352 goto_handler, Pmode);
1356 static struct machine_function *
1357 xtensa_init_machine_status (void)
1359 return ggc_alloc_cleared_machine_function ();
1363 /* Shift VAL of mode MODE left by COUNT bits. */
1366 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1368 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1369 NULL_RTX, 1, OPTAB_DIRECT);
1370 return expand_simple_binop (SImode, ASHIFT, val, count,
1371 NULL_RTX, 1, OPTAB_DIRECT);
1375 /* Structure to hold the initial parameters for a compare_and_swap operation
1376 in HImode and QImode. */
1378 struct alignment_context
1380 rtx memsi; /* SI aligned memory location. */
1381 rtx shift; /* Bit offset with regard to lsb. */
1382 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1383 rtx modemaski; /* ~modemask */
1387 /* Initialize structure AC for word access to HI and QI mode memory. */
1390 init_alignment_context (struct alignment_context *ac, rtx mem)
1392 enum machine_mode mode = GET_MODE (mem);
1393 rtx byteoffset = NULL_RTX;
1394 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1397 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1400 /* Alignment is unknown. */
1403 /* Force the address into a register. */
1404 addr = force_reg (Pmode, XEXP (mem, 0));
1406 /* Align it to SImode. */
1407 align = expand_simple_binop (Pmode, AND, addr,
1408 GEN_INT (-GET_MODE_SIZE (SImode)),
1409 NULL_RTX, 1, OPTAB_DIRECT);
1411 ac->memsi = gen_rtx_MEM (SImode, align);
1412 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1413 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1414 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1416 byteoffset = expand_simple_binop (Pmode, AND, addr,
1417 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1418 NULL_RTX, 1, OPTAB_DIRECT);
1421 /* Calculate shiftcount. */
1422 if (TARGET_BIG_ENDIAN)
1424 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1426 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1427 NULL_RTX, 1, OPTAB_DIRECT);
1432 ac->shift = NULL_RTX;
1434 ac->shift = byteoffset;
1437 if (ac->shift != NULL_RTX)
1439 /* Shift is the byte count, but we need the bitcount. */
1440 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1441 GEN_INT (BITS_PER_UNIT),
1442 NULL_RTX, 1, OPTAB_DIRECT);
1443 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1444 GEN_INT (GET_MODE_MASK (mode)),
1446 NULL_RTX, 1, OPTAB_DIRECT);
1449 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1451 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1455 /* Expand an atomic compare and swap operation for HImode and QImode.
1456 MEM is the memory location, CMP the old value to compare MEM with
1457 and NEW_RTX the value to set if CMP == MEM. */
1460 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx)
1462 enum machine_mode mode = GET_MODE (mem);
1463 struct alignment_context ac;
1464 rtx tmp, cmpv, newv, val;
1465 rtx oldval = gen_reg_rtx (SImode);
1466 rtx res = gen_reg_rtx (SImode);
1467 rtx csloop = gen_label_rtx ();
1468 rtx csend = gen_label_rtx ();
1470 init_alignment_context (&ac, mem);
1472 if (ac.shift != NULL_RTX)
1474 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1475 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift);
1478 /* Load the surrounding word into VAL with the MEM value masked out. */
1479 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1480 ac.modemaski, NULL_RTX, 1,
1482 emit_label (csloop);
1484 /* Patch CMP and NEW_RTX into VAL at correct position. */
1485 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1486 NULL_RTX, 1, OPTAB_DIRECT));
1487 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
1488 NULL_RTX, 1, OPTAB_DIRECT));
1490 /* Jump to end if we're done. */
1491 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1492 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1494 /* Check for changes outside mode. */
1495 emit_move_insn (oldval, val);
1496 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1497 val, 1, OPTAB_DIRECT);
1499 emit_move_insn (val, tmp);
1501 /* Loop internal if so. */
1502 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1506 /* Return the correct part of the bitfield. */
1507 convert_move (target,
1508 (ac.shift == NULL_RTX ? res
1509 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1510 NULL_RTX, 1, OPTAB_DIRECT)),
1515 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1516 the default expansion works fine for SImode). MEM is the memory location
1517 and VAL the value to play with. If AFTER is true then store the value
1518 MEM holds after the operation, if AFTER is false then store the value MEM
1519 holds before the operation. If TARGET is zero then discard that value, else
1520 store it to TARGET. */
1523 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1526 enum machine_mode mode = GET_MODE (mem);
1527 struct alignment_context ac;
1528 rtx csloop = gen_label_rtx ();
1530 rtx old = gen_reg_rtx (SImode);
1531 rtx new_rtx = gen_reg_rtx (SImode);
1532 rtx orig = NULL_RTX;
1534 init_alignment_context (&ac, mem);
1536 /* Prepare values before the compare-and-swap loop. */
1537 if (ac.shift != NULL_RTX)
1538 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1543 orig = gen_reg_rtx (SImode);
1544 convert_move (orig, val, 1);
1552 case MULT: /* NAND */
1554 /* val = "11..1<val>11..1" */
1555 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1556 NULL_RTX, 1, OPTAB_DIRECT);
1563 /* Load full word. Subsequent loads are performed by S32C1I. */
1564 cmp = force_reg (SImode, ac.memsi);
1566 emit_label (csloop);
1567 emit_move_insn (old, cmp);
1573 val = expand_simple_binop (SImode, code, old, orig,
1574 NULL_RTX, 1, OPTAB_DIRECT);
1575 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1576 NULL_RTX, 1, OPTAB_DIRECT);
1579 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1580 NULL_RTX, 1, OPTAB_DIRECT);
1581 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1582 new_rtx, 1, OPTAB_DIRECT);
1588 tmp = expand_simple_binop (SImode, code, old, val,
1589 new_rtx, 1, OPTAB_DIRECT);
1592 case MULT: /* NAND */
1593 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1594 NULL_RTX, 1, OPTAB_DIRECT);
1595 tmp = expand_simple_binop (SImode, AND, tmp, val,
1596 new_rtx, 1, OPTAB_DIRECT);
1604 emit_move_insn (new_rtx, tmp);
1605 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx));
1606 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1610 tmp = (after ? new_rtx : cmp);
1611 convert_move (target,
1612 (ac.shift == NULL_RTX ? tmp
1613 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1614 NULL_RTX, 1, OPTAB_DIRECT)),
1621 xtensa_setup_frame_addresses (void)
1623 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1624 cfun->machine->accesses_prev_frame = 1;
1627 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1628 LCT_NORMAL, VOIDmode, 0);
1632 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1633 a comment showing where the end of the loop is. However, if there is a
1634 label or a branch at the end of the loop then we need to place a nop
1635 there. If the loop ends with a label we need the nop so that branches
1636 targeting that label will target the nop (and thus remain in the loop),
1637 instead of targeting the instruction after the loop (and thus exiting
1638 the loop). If the loop ends with a branch, we need the nop in case the
1639 branch is targeting a location inside the loop. When the branch
1640 executes it will cause the loop count to be decremented even if it is
1641 taken (because it is the last instruction in the loop), so we need to
1642 nop after the branch to prevent the loop count from being decremented
1643 when the branch is taken. */
1646 xtensa_emit_loop_end (rtx insn, rtx *operands)
1650 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1652 switch (GET_CODE (insn))
1659 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1665 rtx body = PATTERN (insn);
1667 if (GET_CODE (body) == JUMP_INSN)
1669 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1672 else if ((GET_CODE (body) != USE)
1673 && (GET_CODE (body) != CLOBBER))
1680 output_asm_insn ("# loop end for %0", operands);
1685 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1687 static char result[64];
1691 code = GET_CODE (operands[3]);
1694 case EQ: op = inverted ? "ne" : "eq"; break;
1695 case NE: op = inverted ? "eq" : "ne"; break;
1696 case LT: op = inverted ? "ge" : "lt"; break;
1697 case GE: op = inverted ? "lt" : "ge"; break;
1698 case LTU: op = inverted ? "geu" : "ltu"; break;
1699 case GEU: op = inverted ? "ltu" : "geu"; break;
1700 default: gcc_unreachable ();
1705 if (INTVAL (operands[1]) == 0)
1706 sprintf (result, "b%sz%s\t%%0, %%2", op,
1707 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1709 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1712 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1719 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1721 static char result[64];
1724 switch (GET_CODE (operands[3]))
1726 case EQ: op = inverted ? "bs" : "bc"; break;
1727 case NE: op = inverted ? "bc" : "bs"; break;
1728 default: gcc_unreachable ();
1733 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1734 operands[1] = GEN_INT (bitnum);
1735 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1738 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1745 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1747 static char result[64];
1751 code = GET_CODE (operands[4]);
1756 case EQ: op = inverted ? "t" : "f"; break;
1757 case NE: op = inverted ? "f" : "t"; break;
1758 default: gcc_unreachable ();
1765 case EQ: op = inverted ? "nez" : "eqz"; break;
1766 case NE: op = inverted ? "eqz" : "nez"; break;
1767 case LT: op = inverted ? "gez" : "ltz"; break;
1768 case GE: op = inverted ? "ltz" : "gez"; break;
1769 default: gcc_unreachable ();
1773 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1774 op, isfp ? ".s" : "", inverted ? 3 : 2);
1780 xtensa_emit_call (int callop, rtx *operands)
1782 static char result[64];
1783 rtx tgt = operands[callop];
1785 if (GET_CODE (tgt) == CONST_INT)
1786 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1787 else if (register_operand (tgt, VOIDmode))
1788 sprintf (result, "callx8\t%%%d", callop);
1790 sprintf (result, "call8\t%%%d", callop);
1797 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1799 /* Allow constant pool addresses. */
1800 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1801 && ! TARGET_CONST16 && constantpool_address_p (addr)
1802 && ! xtensa_tls_referenced_p (addr))
1805 while (GET_CODE (addr) == SUBREG)
1806 addr = SUBREG_REG (addr);
1808 /* Allow base registers. */
1809 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1812 /* Check for "register + offset" addressing. */
1813 if (GET_CODE (addr) == PLUS)
1815 rtx xplus0 = XEXP (addr, 0);
1816 rtx xplus1 = XEXP (addr, 1);
1817 enum rtx_code code0;
1818 enum rtx_code code1;
1820 while (GET_CODE (xplus0) == SUBREG)
1821 xplus0 = SUBREG_REG (xplus0);
1822 code0 = GET_CODE (xplus0);
1824 while (GET_CODE (xplus1) == SUBREG)
1825 xplus1 = SUBREG_REG (xplus1);
1826 code1 = GET_CODE (xplus1);
1828 /* Swap operands if necessary so the register is first. */
1829 if (code0 != REG && code1 == REG)
1831 xplus0 = XEXP (addr, 1);
1832 xplus1 = XEXP (addr, 0);
1833 code0 = GET_CODE (xplus0);
1834 code1 = GET_CODE (xplus1);
1837 if (code0 == REG && BASE_REG_P (xplus0, strict)
1838 && code1 == CONST_INT
1839 && xtensa_mem_offset (INTVAL (xplus1), mode))
1847 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1849 static GTY(()) rtx xtensa_tls_module_base_symbol;
1852 xtensa_tls_module_base (void)
1854 if (! xtensa_tls_module_base_symbol)
1856 xtensa_tls_module_base_symbol =
1857 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_");
1858 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol)
1859 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
1862 return xtensa_tls_module_base_symbol;
1867 xtensa_call_tls_desc (rtx sym, rtx *retp)
1869 rtx fn, arg, a10, call_insn, insns;
1872 fn = gen_reg_rtx (Pmode);
1873 arg = gen_reg_rtx (Pmode);
1874 a10 = gen_rtx_REG (Pmode, 10);
1876 emit_insn (gen_tls_func (fn, sym));
1877 emit_insn (gen_tls_arg (arg, sym));
1878 emit_move_insn (a10, arg);
1879 call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx));
1880 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), a10);
1881 insns = get_insns ();
1890 xtensa_legitimize_tls_address (rtx x)
1892 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
1893 rtx dest, tp, ret, modbase, base, addend, insns;
1895 dest = gen_reg_rtx (Pmode);
1898 case TLS_MODEL_GLOBAL_DYNAMIC:
1899 insns = xtensa_call_tls_desc (x, &ret);
1900 emit_libcall_block (insns, dest, ret, x);
1903 case TLS_MODEL_LOCAL_DYNAMIC:
1904 base = gen_reg_rtx (Pmode);
1905 modbase = xtensa_tls_module_base ();
1906 insns = xtensa_call_tls_desc (modbase, &ret);
1907 emit_libcall_block (insns, base, ret, modbase);
1908 addend = force_reg (SImode, gen_sym_DTPOFF (x));
1909 emit_insn (gen_addsi3 (dest, base, addend));
1912 case TLS_MODEL_INITIAL_EXEC:
1913 case TLS_MODEL_LOCAL_EXEC:
1914 tp = gen_reg_rtx (SImode);
1915 emit_insn (gen_load_tp (tp));
1916 addend = force_reg (SImode, gen_sym_TPOFF (x));
1917 emit_insn (gen_addsi3 (dest, tp, addend));
1929 xtensa_legitimize_address (rtx x,
1930 rtx oldx ATTRIBUTE_UNUSED,
1931 enum machine_mode mode)
1933 if (xtensa_tls_symbol_p (x))
1934 return xtensa_legitimize_tls_address (x);
1936 if (GET_CODE (x) == PLUS)
1938 rtx plus0 = XEXP (x, 0);
1939 rtx plus1 = XEXP (x, 1);
1941 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1943 plus0 = XEXP (x, 1);
1944 plus1 = XEXP (x, 0);
1947 /* Try to split up the offset to use an ADDMI instruction. */
1948 if (GET_CODE (plus0) == REG
1949 && GET_CODE (plus1) == CONST_INT
1950 && !xtensa_mem_offset (INTVAL (plus1), mode)
1951 && !xtensa_simm8 (INTVAL (plus1))
1952 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1953 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1955 rtx temp = gen_reg_rtx (Pmode);
1956 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1957 emit_insn (gen_rtx_SET (Pmode, temp,
1958 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1959 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1966 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
1968 Treat constant-pool references as "mode dependent" since they can
1969 only be accessed with SImode loads. This works around a bug in the
1970 combiner where a constant pool reference is temporarily converted
1971 to an HImode load, which is then assumed to zero-extend based on
1972 our definition of LOAD_EXTEND_OP. This is wrong because the high
1973 bits of a 16-bit value in the constant pool are now sign-extended
1977 xtensa_mode_dependent_address_p (const_rtx addr)
1979 return constantpool_address_p (addr);
1982 /* Helper for xtensa_tls_referenced_p. */
1985 xtensa_tls_referenced_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1987 if (GET_CODE (*x) == SYMBOL_REF)
1988 return SYMBOL_REF_TLS_MODEL (*x) != 0;
1990 /* Ignore TLS references that have already been legitimized. */
1991 if (GET_CODE (*x) == UNSPEC)
1993 switch (XINT (*x, 1))
1997 case UNSPEC_TLS_FUNC:
1998 case UNSPEC_TLS_ARG:
1999 case UNSPEC_TLS_CALL:
2010 /* Return TRUE if X contains any TLS symbol references. */
2013 xtensa_tls_referenced_p (rtx x)
2015 if (! TARGET_HAVE_TLS)
2018 return for_each_rtx (&x, xtensa_tls_referenced_p_1, NULL);
2022 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2025 xtensa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2027 return xtensa_tls_referenced_p (x);
2031 /* Return the debugger register number to use for 'regno'. */
2034 xtensa_dbx_register_number (int regno)
2038 if (GP_REG_P (regno))
2040 regno -= GP_REG_FIRST;
2043 else if (BR_REG_P (regno))
2045 regno -= BR_REG_FIRST;
2048 else if (FP_REG_P (regno))
2050 regno -= FP_REG_FIRST;
2053 else if (ACC_REG_P (regno))
2055 first = 0x200; /* Start of Xtensa special registers. */
2056 regno = 16; /* ACCLO is special register 16. */
2059 /* When optimizing, we sometimes get asked about pseudo-registers
2060 that don't represent hard registers. Return 0 for these. */
2064 return first + regno;
2068 /* Argument support functions. */
2070 /* Initialize CUMULATIVE_ARGS for a function. */
2073 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
2076 cum->incoming = incoming;
2080 /* Advance the argument to the next argument position. */
2083 xtensa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2084 const_tree type, bool named ATTRIBUTE_UNUSED)
2089 arg_words = &cum->arg_words;
2090 max = MAX_ARGS_IN_REGISTERS;
2092 words = (((mode != BLKmode)
2093 ? (int) GET_MODE_SIZE (mode)
2094 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2096 if (*arg_words < max
2097 && (targetm.calls.must_pass_in_stack (mode, type)
2098 || *arg_words + words > max))
2101 *arg_words += words;
2105 /* Return an RTL expression containing the register for the given mode,
2106 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2107 if this is an incoming argument to the current function. */
2110 xtensa_function_arg_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2111 const_tree type, bool incoming_p)
2113 int regbase, words, max;
2117 arg_words = &cum->arg_words;
2118 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
2119 max = MAX_ARGS_IN_REGISTERS;
2121 words = (((mode != BLKmode)
2122 ? (int) GET_MODE_SIZE (mode)
2123 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2125 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
2127 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
2128 *arg_words = (*arg_words + align - 1) & -align;
2131 if (*arg_words + words > max)
2134 regno = regbase + *arg_words;
2136 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
2137 cfun->machine->need_a7_copy = true;
2139 return gen_rtx_REG (mode, regno);
2142 /* Implement TARGET_FUNCTION_ARG. */
2145 xtensa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2146 const_tree type, bool named ATTRIBUTE_UNUSED)
2148 return xtensa_function_arg_1 (cum, mode, type, false);
2151 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2154 xtensa_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2155 const_tree type, bool named ATTRIBUTE_UNUSED)
2157 return xtensa_function_arg_1 (cum, mode, type, true);
2161 xtensa_function_arg_boundary (enum machine_mode mode, const_tree type)
2163 unsigned int alignment;
2165 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
2166 if (alignment < PARM_BOUNDARY)
2167 alignment = PARM_BOUNDARY;
2168 if (alignment > STACK_BOUNDARY)
2169 alignment = STACK_BOUNDARY;
2175 xtensa_return_in_msb (const_tree valtype)
2177 return (TARGET_BIG_ENDIAN
2178 && AGGREGATE_TYPE_P (valtype)
2179 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
2184 xtensa_option_override (void)
2187 enum machine_mode mode;
2189 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
2190 error ("boolean registers required for the floating-point option");
2192 /* Set up array giving whether a given register can hold a given mode. */
2193 for (mode = VOIDmode;
2194 mode != MAX_MACHINE_MODE;
2195 mode = (enum machine_mode) ((int) mode + 1))
2197 int size = GET_MODE_SIZE (mode);
2198 enum mode_class mclass = GET_MODE_CLASS (mode);
2200 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2204 if (ACC_REG_P (regno))
2205 temp = (TARGET_MAC16
2206 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD));
2207 else if (GP_REG_P (regno))
2208 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
2209 else if (FP_REG_P (regno))
2210 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
2211 else if (BR_REG_P (regno))
2212 temp = (TARGET_BOOLEANS && (mode == CCmode));
2216 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
2220 init_machine_status = xtensa_init_machine_status;
2222 /* Check PIC settings. PIC is only supported when using L32R
2223 instructions, and some targets need to always use PIC. */
2224 if (flag_pic && TARGET_CONST16)
2225 error ("-f%s is not supported with CONST16 instructions",
2226 (flag_pic > 1 ? "PIC" : "pic"));
2227 else if (TARGET_FORCE_NO_PIC)
2229 else if (XTENSA_ALWAYS_PIC)
2232 error ("PIC is required but not supported with CONST16 instructions");
2235 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2238 if (flag_pic && !flag_pie)
2241 /* Hot/cold partitioning does not work on this architecture, because of
2242 constant pools (the load instruction cannot necessarily reach that far).
2243 Therefore disable it on this architecture. */
2244 if (flag_reorder_blocks_and_partition)
2246 flag_reorder_blocks_and_partition = 0;
2247 flag_reorder_blocks = 1;
2251 /* A C compound statement to output to stdio stream STREAM the
2252 assembler syntax for an instruction operand X. X is an RTL
2255 CODE is a value that can be used to specify one of several ways
2256 of printing the operand. It is used when identical operands
2257 must be printed differently depending on the context. CODE
2258 comes from the '%' specification that was used to request
2259 printing of the operand. If the specification was just '%DIGIT'
2260 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2261 is the ASCII code for LTR.
2263 If X is a register, this macro should print the register's name.
2264 The names can be found in an array 'reg_names' whose type is
2265 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2267 When the machine description has a specification '%PUNCT' (a '%'
2268 followed by a punctuation character), this macro is called with
2269 a null pointer for X and the punctuation character for CODE.
2271 'a', 'c', 'l', and 'n' are reserved.
2273 The Xtensa specific codes are:
2275 'd' CONST_INT, print as signed decimal
2276 'x' CONST_INT, print as signed hexadecimal
2277 'K' CONST_INT, print number of bits in mask for EXTUI
2278 'R' CONST_INT, print (X & 0x1f)
2279 'L' CONST_INT, print ((32 - X) & 0x1f)
2280 'D' REG, print second register of double-word register operand
2281 'N' MEM, print address of next word following a memory operand
2282 'v' MEM, if memory reference is volatile, output a MEMW before it
2283 't' any constant, add "@h" suffix for top 16 bits
2284 'b' any constant, add "@l" suffix for bottom 16 bits
2288 printx (FILE *file, signed int val)
2290 /* Print a hexadecimal value in a nice way. */
2291 if ((val > -0xa) && (val < 0xa))
2292 fprintf (file, "%d", val);
2294 fprintf (file, "-0x%x", -val);
2296 fprintf (file, "0x%x", val);
2301 print_operand (FILE *file, rtx x, int letter)
2304 error ("PRINT_OPERAND null pointer");
2309 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2310 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
2312 output_operand_lossage ("invalid %%D value");
2316 if (GET_CODE (x) == MEM)
2318 /* For a volatile memory reference, emit a MEMW before the
2320 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2321 fprintf (file, "memw\n\t");
2324 output_operand_lossage ("invalid %%v value");
2328 if (GET_CODE (x) == MEM
2329 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2331 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2332 output_address (XEXP (x, 0));
2335 output_operand_lossage ("invalid %%N value");
2339 if (GET_CODE (x) == CONST_INT)
2342 unsigned val = INTVAL (x);
2348 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2349 fatal_insn ("invalid mask", x);
2351 fprintf (file, "%d", num_bits);
2354 output_operand_lossage ("invalid %%K value");
2358 if (GET_CODE (x) == CONST_INT)
2359 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2361 output_operand_lossage ("invalid %%L value");
2365 if (GET_CODE (x) == CONST_INT)
2366 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2368 output_operand_lossage ("invalid %%R value");
2372 if (GET_CODE (x) == CONST_INT)
2373 printx (file, INTVAL (x));
2375 output_operand_lossage ("invalid %%x value");
2379 if (GET_CODE (x) == CONST_INT)
2380 fprintf (file, "%ld", INTVAL (x));
2382 output_operand_lossage ("invalid %%d value");
2387 if (GET_CODE (x) == CONST_INT)
2389 printx (file, INTVAL (x));
2390 fputs (letter == 't' ? "@h" : "@l", file);
2392 else if (GET_CODE (x) == CONST_DOUBLE)
2395 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2396 if (GET_MODE (x) == SFmode)
2399 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2400 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2403 output_operand_lossage ("invalid %%t/%%b value");
2405 else if (GET_CODE (x) == CONST)
2407 /* X must be a symbolic constant on ELF. Write an expression
2408 suitable for 'const16' that sets the high or low 16 bits. */
2409 if (GET_CODE (XEXP (x, 0)) != PLUS
2410 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2411 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2412 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2413 output_operand_lossage ("invalid %%t/%%b value");
2414 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2415 fputs (letter == 't' ? "@h" : "@l", file);
2416 /* There must be a non-alphanumeric character between 'h' or 'l'
2417 and the number. The '-' is added by print_operand() already. */
2418 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2420 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2424 output_addr_const (file, x);
2425 fputs (letter == 't' ? "@h" : "@l", file);
2430 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2431 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2432 else if (GET_CODE (x) == MEM)
2433 output_address (XEXP (x, 0));
2434 else if (GET_CODE (x) == CONST_INT)
2435 fprintf (file, "%ld", INTVAL (x));
2437 output_addr_const (file, x);
2442 /* A C compound statement to output to stdio stream STREAM the
2443 assembler syntax for an instruction operand that is a memory
2444 reference whose address is ADDR. ADDR is an RTL expression. */
2447 print_operand_address (FILE *file, rtx addr)
2450 error ("PRINT_OPERAND_ADDRESS, null pointer");
2452 switch (GET_CODE (addr))
2455 fatal_insn ("invalid address", addr);
2459 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2465 rtx offset = (rtx)0;
2466 rtx arg0 = XEXP (addr, 0);
2467 rtx arg1 = XEXP (addr, 1);
2469 if (GET_CODE (arg0) == REG)
2474 else if (GET_CODE (arg1) == REG)
2480 fatal_insn ("no register in address", addr);
2482 if (CONSTANT_P (offset))
2484 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2485 output_addr_const (file, offset);
2488 fatal_insn ("address offset not a constant", addr);
2496 output_addr_const (file, addr);
2501 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2504 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2506 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2508 switch (XINT (x, 1))
2511 output_addr_const (fp, XVECEXP (x, 0, 0));
2512 fputs ("@TPOFF", fp);
2515 output_addr_const (fp, XVECEXP (x, 0, 0));
2516 fputs ("@DTPOFF", fp);
2521 output_addr_const (fp, XVECEXP (x, 0, 0));
2535 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2542 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2544 switch (GET_MODE_CLASS (mode))
2547 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2549 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2553 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2554 if (HOST_BITS_PER_LONG > 32)
2555 value_long[0] &= 0xffffffff;
2556 fprintf (file, "0x%08lx\n", value_long[0]);
2560 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2561 if (HOST_BITS_PER_LONG > 32)
2563 value_long[0] &= 0xffffffff;
2564 value_long[1] &= 0xffffffff;
2566 fprintf (file, "0x%08lx, 0x%08lx\n",
2567 value_long[0], value_long[1]);
2577 case MODE_PARTIAL_INT:
2578 size = GET_MODE_SIZE (mode);
2582 output_addr_const (file, x);
2587 split_double (x, &first, &second);
2588 output_addr_const (file, first);
2590 output_addr_const (file, second);
2605 /* Return the bytes needed to compute the frame pointer from the current
2608 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2609 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2612 compute_frame_size (int size)
2614 /* Add space for the incoming static chain value. */
2615 if (cfun->static_chain_decl != NULL)
2616 size += (1 * UNITS_PER_WORD);
2618 xtensa_current_frame_size =
2619 XTENSA_STACK_ALIGN (size
2620 + crtl->outgoing_args_size
2621 + (WINDOW_SIZE * UNITS_PER_WORD));
2622 return xtensa_current_frame_size;
2627 xtensa_frame_pointer_required (void)
2629 /* The code to expand builtin_frame_addr and builtin_return_addr
2630 currently uses the hard_frame_pointer instead of frame_pointer.
2631 This seems wrong but maybe it's necessary for other architectures.
2632 This function is derived from the i386 code. */
2634 if (cfun->machine->accesses_prev_frame)
2641 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2642 and the total number of words must be a multiple of 128 bits. */
2643 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2646 xtensa_expand_prologue (void)
2648 HOST_WIDE_INT total_size;
2652 total_size = compute_frame_size (get_frame_size ());
2653 size_rtx = GEN_INT (total_size);
2655 if (total_size < (1 << (12+3)))
2656 insn = emit_insn (gen_entry (size_rtx));
2659 /* Use a8 as a temporary since a0-a7 may be live. */
2660 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2661 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2662 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2663 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2664 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2667 if (frame_pointer_needed)
2669 if (cfun->machine->set_frame_ptr_insn)
2673 push_topmost_sequence ();
2674 first = get_insns ();
2675 pop_topmost_sequence ();
2677 /* For all instructions prior to set_frame_ptr_insn, replace
2678 hard_frame_pointer references with stack_pointer. */
2680 insn != cfun->machine->set_frame_ptr_insn;
2681 insn = NEXT_INSN (insn))
2685 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2686 hard_frame_pointer_rtx,
2688 df_insn_rescan (insn);
2693 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2694 stack_pointer_rtx));
2697 /* Create a note to describe the CFA. Because this is only used to set
2698 DW_AT_frame_base for debug info, don't bother tracking changes through
2699 each instruction in the prologue. It just takes up space. */
2700 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2701 ? hard_frame_pointer_rtx
2702 : stack_pointer_rtx),
2703 plus_constant (stack_pointer_rtx, -total_size));
2704 RTX_FRAME_RELATED_P (insn) = 1;
2705 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx);
2709 /* Clear variables at function end. */
2712 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2713 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2715 xtensa_current_frame_size = 0;
2720 xtensa_return_addr (int count, rtx frame)
2722 rtx result, retaddr, curaddr, label;
2725 retaddr = gen_rtx_REG (Pmode, A0_REG);
2728 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2729 addr = memory_address (Pmode, addr);
2730 retaddr = gen_reg_rtx (Pmode);
2731 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2734 /* The 2 most-significant bits of the return address on Xtensa hold
2735 the register window size. To get the real return address, these
2736 bits must be replaced with the high bits from some address in the
2739 /* Get the 2 high bits of a local label in the code. */
2740 curaddr = gen_reg_rtx (Pmode);
2741 label = gen_label_rtx ();
2743 LABEL_PRESERVE_P (label) = 1;
2744 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2745 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2746 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2748 /* Clear the 2 high bits of the return address. */
2749 result = gen_reg_rtx (Pmode);
2750 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2751 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2753 /* Combine them to get the result. */
2754 emit_insn (gen_iorsi3 (result, result, curaddr));
2759 /* Create the va_list data type.
2761 This structure is set up by __builtin_saveregs. The __va_reg field
2762 points to a stack-allocated region holding the contents of the
2763 incoming argument registers. The __va_ndx field is an index
2764 initialized to the position of the first unnamed (variable)
2765 argument. This same index is also used to address the arguments
2766 passed in memory. Thus, the __va_stk field is initialized to point
2767 to the position of the first argument in memory offset to account
2768 for the arguments passed in registers and to account for the size
2769 of the argument registers not being 16-byte aligned. E.G., there
2770 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2771 for the first stack argument to have the maximal alignment of 16
2772 bytes, so we offset the __va_stk address by 32 bytes so that
2773 __va_stk[32] references the first argument on the stack. */
2776 xtensa_build_builtin_va_list (void)
2778 tree f_stk, f_reg, f_ndx, record, type_decl;
2780 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2781 type_decl = build_decl (BUILTINS_LOCATION,
2782 TYPE_DECL, get_identifier ("__va_list_tag"), record);
2784 f_stk = build_decl (BUILTINS_LOCATION,
2785 FIELD_DECL, get_identifier ("__va_stk"),
2787 f_reg = build_decl (BUILTINS_LOCATION,
2788 FIELD_DECL, get_identifier ("__va_reg"),
2790 f_ndx = build_decl (BUILTINS_LOCATION,
2791 FIELD_DECL, get_identifier ("__va_ndx"),
2794 DECL_FIELD_CONTEXT (f_stk) = record;
2795 DECL_FIELD_CONTEXT (f_reg) = record;
2796 DECL_FIELD_CONTEXT (f_ndx) = record;
2798 TYPE_STUB_DECL (record) = type_decl;
2799 TYPE_NAME (record) = type_decl;
2800 TYPE_FIELDS (record) = f_stk;
2801 DECL_CHAIN (f_stk) = f_reg;
2802 DECL_CHAIN (f_reg) = f_ndx;
2804 layout_type (record);
2809 /* Save the incoming argument registers on the stack. Returns the
2810 address of the saved registers. */
2813 xtensa_builtin_saveregs (void)
2816 int arg_words = crtl->args.info.arg_words;
2817 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2822 /* Allocate the general-purpose register space. */
2823 gp_regs = assign_stack_local
2824 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2825 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2827 /* Now store the incoming registers. */
2828 cfun->machine->need_a7_copy = true;
2829 cfun->machine->vararg_a7 = true;
2830 move_block_from_reg (GP_ARG_FIRST + arg_words,
2831 adjust_address (gp_regs, BLKmode,
2832 arg_words * UNITS_PER_WORD),
2834 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2835 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2837 return XEXP (gp_regs, 0);
2841 /* Implement `va_start' for varargs and stdarg. We look at the
2842 current function to fill in an initial va_list. */
2845 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2853 arg_words = crtl->args.info.arg_words;
2855 f_stk = TYPE_FIELDS (va_list_type_node);
2856 f_reg = DECL_CHAIN (f_stk);
2857 f_ndx = DECL_CHAIN (f_reg);
2859 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2860 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2862 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2865 /* Call __builtin_saveregs; save the result in __va_reg */
2866 u = make_tree (sizetype, expand_builtin_saveregs ());
2867 u = fold_convert (ptr_type_node, u);
2868 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2869 TREE_SIDE_EFFECTS (t) = 1;
2870 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2872 /* Set the __va_stk member to ($arg_ptr - 32). */
2873 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2874 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2875 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2876 TREE_SIDE_EFFECTS (t) = 1;
2877 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2879 /* Set the __va_ndx member. If the first variable argument is on
2880 the stack, adjust __va_ndx by 2 words to account for the extra
2881 alignment offset for __va_stk. */
2882 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2884 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2885 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2886 TREE_SIDE_EFFECTS (t) = 1;
2887 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2891 /* Implement `va_arg'. */
2894 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2895 gimple_seq *post_p ATTRIBUTE_UNUSED)
2900 tree type_size, array, orig_ndx, addr, size, va_size, t;
2901 tree lab_false, lab_over, lab_false2;
2904 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2906 type = build_pointer_type (type);
2908 /* Handle complex values as separate real and imaginary parts. */
2909 if (TREE_CODE (type) == COMPLEX_TYPE)
2911 tree real_part, imag_part;
2913 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2915 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2917 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2920 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2922 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2925 f_stk = TYPE_FIELDS (va_list_type_node);
2926 f_reg = DECL_CHAIN (f_stk);
2927 f_ndx = DECL_CHAIN (f_reg);
2929 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2931 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2933 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2936 type_size = size_in_bytes (type);
2937 va_size = round_up (type_size, UNITS_PER_WORD);
2938 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2941 /* First align __va_ndx if necessary for this arg:
2943 orig_ndx = (AP).__va_ndx;
2944 if (__alignof__ (TYPE) > 4 )
2945 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2946 & -__alignof__ (TYPE)); */
2948 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2950 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2952 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2954 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2955 build_int_cst (integer_type_node, align - 1));
2956 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2957 build_int_cst (integer_type_node, -align));
2958 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2962 /* Increment __va_ndx to point past the argument:
2964 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2966 t = fold_convert (integer_type_node, va_size);
2967 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2968 gimplify_assign (unshare_expr (ndx), t, pre_p);
2971 /* Check if the argument is in registers:
2973 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2974 && !must_pass_in_stack (type))
2975 __array = (AP).__va_reg; */
2977 array = create_tmp_var (ptr_type_node, NULL);
2980 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2982 lab_false = create_artificial_label (UNKNOWN_LOCATION);
2983 lab_over = create_artificial_label (UNKNOWN_LOCATION);
2985 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2986 build_int_cst (integer_type_node,
2987 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2988 t = build3 (COND_EXPR, void_type_node, t,
2989 build1 (GOTO_EXPR, void_type_node, lab_false),
2991 gimplify_and_add (t, pre_p);
2993 gimplify_assign (unshare_expr (array), reg, pre_p);
2995 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2996 gimplify_and_add (t, pre_p);
2998 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2999 gimplify_and_add (t, pre_p);
3003 /* ...otherwise, the argument is on the stack (never split between
3004 registers and the stack -- change __va_ndx if necessary):
3008 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
3009 (AP).__va_ndx = 32 + __va_size (TYPE);
3010 __array = (AP).__va_stk;
3013 lab_false2 = create_artificial_label (UNKNOWN_LOCATION);
3015 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
3016 build_int_cst (integer_type_node,
3017 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
3018 t = build3 (COND_EXPR, void_type_node, t,
3019 build1 (GOTO_EXPR, void_type_node, lab_false2),
3021 gimplify_and_add (t, pre_p);
3023 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
3024 t = fold_convert (integer_type_node, t);
3025 gimplify_assign (unshare_expr (ndx), t, pre_p);
3027 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
3028 gimplify_and_add (t, pre_p);
3030 gimplify_assign (array, stk, pre_p);
3034 t = build1 (LABEL_EXPR, void_type_node, lab_over);
3035 gimplify_and_add (t, pre_p);
3039 /* Given the base array pointer (__array) and index to the subsequent
3040 argument (__va_ndx), find the address:
3042 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
3046 The results are endian-dependent because values smaller than one word
3047 are aligned differently. */
3050 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
3052 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
3053 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
3054 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
3055 unshare_expr (type_size));
3059 size = unshare_expr (va_size);
3061 t = fold_convert (sizetype, unshare_expr (ndx));
3062 t = build2 (MINUS_EXPR, sizetype, t, size);
3063 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t);
3065 addr = fold_convert (build_pointer_type (type), addr);
3067 addr = build_va_arg_indirect_ref (addr);
3068 return build_va_arg_indirect_ref (addr);
3076 XTENSA_BUILTIN_UMULSIDI3,
3077 XTENSA_BUILTIN_THREAD_POINTER,
3078 XTENSA_BUILTIN_SET_THREAD_POINTER,
3084 xtensa_init_builtins (void)
3088 ftype = build_function_type_list (unsigned_intDI_type_node,
3089 unsigned_intSI_type_node,
3090 unsigned_intSI_type_node, NULL_TREE);
3092 decl = add_builtin_function ("__builtin_umulsidi3", ftype,
3093 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
3094 "__umulsidi3", NULL_TREE);
3095 TREE_NOTHROW (decl) = 1;
3096 TREE_READONLY (decl) = 1;
3098 if (TARGET_THREADPTR)
3100 ftype = build_function_type (ptr_type_node, void_list_node);
3101 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
3102 XTENSA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
3104 TREE_READONLY (decl) = 1;
3105 TREE_NOTHROW (decl) = 1;
3107 ftype = build_function_type_list (void_type_node, ptr_type_node,
3109 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
3110 XTENSA_BUILTIN_SET_THREAD_POINTER,
3111 BUILT_IN_MD, NULL, NULL_TREE);
3112 TREE_NOTHROW (decl) = 1;
3118 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
3119 bool ignore ATTRIBUTE_UNUSED)
3121 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3126 case XTENSA_BUILTIN_UMULSIDI3:
3129 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
3130 || TARGET_MUL32_HIGH)
3131 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
3132 fold_convert (unsigned_intDI_type_node, arg0),
3133 fold_convert (unsigned_intDI_type_node, arg1));
3136 case XTENSA_BUILTIN_THREAD_POINTER:
3137 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3141 internal_error ("bad builtin code");
3150 xtensa_expand_builtin (tree exp, rtx target,
3151 rtx subtarget ATTRIBUTE_UNUSED,
3152 enum machine_mode mode ATTRIBUTE_UNUSED,
3155 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
3156 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3161 case XTENSA_BUILTIN_UMULSIDI3:
3162 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3163 __umulsidi3 function when the Xtensa configuration can directly
3164 implement it. If not, just call the function. */
3165 return expand_call (exp, target, ignore);
3167 case XTENSA_BUILTIN_THREAD_POINTER:
3168 if (!target || !register_operand (target, Pmode))
3169 target = gen_reg_rtx (Pmode);
3170 emit_insn (gen_load_tp (target));
3173 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3174 arg = expand_normal (CALL_EXPR_ARG (exp, 0));
3175 if (!register_operand (arg, Pmode))
3176 arg = copy_to_mode_reg (Pmode, arg);
3177 emit_insn (gen_set_tp (arg));
3181 internal_error ("bad builtin code");
3186 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */
3189 xtensa_preferred_reload_class (rtx x, reg_class_t rclass)
3191 if (CONSTANT_P (x) && CONST_DOUBLE_P (x))
3194 /* Don't use the stack pointer or hard frame pointer for reloads!
3195 The hard frame pointer would normally be OK except that it may
3196 briefly hold an incoming argument in the prologue, and reload
3197 won't know that it is live because the hard frame pointer is
3198 treated specially. */
3200 if (rclass == AR_REGS || rclass == GR_REGS)
3206 /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
3209 xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED,
3212 /* Don't use the stack pointer or hard frame pointer for reloads!
3213 The hard frame pointer would normally be OK except that it may
3214 briefly hold an incoming argument in the prologue, and reload
3215 won't know that it is live because the hard frame pointer is
3216 treated specially. */
3218 if (rclass == AR_REGS || rclass == GR_REGS)
3224 /* Worker function for TARGET_SECONDARY_RELOAD. */
3227 xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
3228 enum machine_mode mode, secondary_reload_info *sri)
3232 if (in_p && constantpool_mem_p (x))
3234 if (rclass == FP_REGS)
3238 sri->icode = CODE_FOR_reloadqi_literal;
3239 else if (mode == HImode)
3240 sri->icode = CODE_FOR_reloadhi_literal;
3243 regno = xt_true_regnum (x);
3244 if (ACC_REG_P (regno))
3245 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS);
3246 if (rclass == ACC_REG)
3247 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
3254 order_regs_for_local_alloc (void)
3256 if (!leaf_function_p ())
3258 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
3259 FIRST_PSEUDO_REGISTER * sizeof (int));
3263 int i, num_arg_regs;
3266 /* Use the AR registers in increasing order (skipping a0 and a1)
3267 but save the incoming argument registers for a last resort. */
3268 num_arg_regs = crtl->args.info.arg_words;
3269 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
3270 num_arg_regs = MAX_ARGS_IN_REGISTERS;
3271 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
3272 reg_alloc_order[nxt++] = i + num_arg_regs;
3273 for (i = 0; i < num_arg_regs; i++)
3274 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
3276 /* List the coprocessor registers in order. */
3277 for (i = 0; i < BR_REG_NUM; i++)
3278 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
3280 /* List the FP registers in order for now. */
3281 for (i = 0; i < 16; i++)
3282 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
3284 /* GCC requires that we list *all* the registers.... */
3285 reg_alloc_order[nxt++] = 0; /* a0 = return address */
3286 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
3287 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
3288 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
3290 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
3295 /* Some Xtensa targets support multiple bss sections. If the section
3296 name ends with ".bss", add SECTION_BSS to the flags. */
3299 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
3301 unsigned int flags = default_section_type_flags (decl, name, reloc);
3304 suffix = strrchr (name, '.');
3305 if (suffix && strcmp (suffix, ".bss") == 0)
3307 if (!decl || (TREE_CODE (decl) == VAR_DECL
3308 && DECL_INITIAL (decl) == NULL_TREE))
3309 flags |= SECTION_BSS; /* @nobits */
3311 warning (0, "only uninitialized variables can be placed in a "
3319 /* The literal pool stays with the function. */
3322 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
3323 rtx x ATTRIBUTE_UNUSED,
3324 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
3326 return function_section (current_function_decl);
3329 /* Worker function for TARGET_REGISTER_MOVE_COST. */
3332 xtensa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
3333 reg_class_t from, reg_class_t to)
3335 if (from == to && from != BR_REGS && to != BR_REGS)
3337 else if (reg_class_subset_p (from, AR_REGS)
3338 && reg_class_subset_p (to, AR_REGS))
3340 else if (reg_class_subset_p (from, AR_REGS) && to == ACC_REG)
3342 else if (from == ACC_REG && reg_class_subset_p (to, AR_REGS))
3348 /* Worker function for TARGET_MEMORY_MOVE_COST. */
3351 xtensa_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
3352 reg_class_t rclass ATTRIBUTE_UNUSED,
3353 bool in ATTRIBUTE_UNUSED)
3358 /* Compute a (partial) cost for rtx X. Return true if the complete
3359 cost has been computed, and false if subexpressions should be
3360 scanned. In either case, *TOTAL contains the cost result. */
3363 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total,
3364 bool speed ATTRIBUTE_UNUSED)
3372 if (xtensa_simm12b (INTVAL (x)))
3379 if (xtensa_simm8 (INTVAL (x))
3380 || xtensa_simm8x256 (INTVAL (x)))
3387 if (xtensa_mask_immediate (INTVAL (x)))
3394 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
3405 /* No way to tell if X is the 2nd operand so be conservative. */
3408 if (xtensa_simm12b (INTVAL (x)))
3410 else if (TARGET_CONST16)
3411 *total = COSTS_N_INSNS (2);
3420 *total = COSTS_N_INSNS (2);
3427 *total = COSTS_N_INSNS (4);
3435 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3437 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3438 *total = COSTS_N_INSNS (num_words);
3440 *total = COSTS_N_INSNS (2*num_words);
3446 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3450 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3454 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3460 if (GET_MODE (x) == DImode)
3461 *total = COSTS_N_INSNS (2);
3463 *total = COSTS_N_INSNS (1);
3469 if (GET_MODE (x) == DImode)
3470 *total = COSTS_N_INSNS (50);
3472 *total = COSTS_N_INSNS (1);
3477 enum machine_mode xmode = GET_MODE (x);
3478 if (xmode == SFmode)
3479 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3480 else if (xmode == DFmode)
3481 *total = COSTS_N_INSNS (50);
3483 *total = COSTS_N_INSNS (4);
3490 enum machine_mode xmode = GET_MODE (x);
3491 if (xmode == SFmode)
3492 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3493 else if (xmode == DFmode || xmode == DImode)
3494 *total = COSTS_N_INSNS (50);
3496 *total = COSTS_N_INSNS (1);
3501 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3506 enum machine_mode xmode = GET_MODE (x);
3507 if (xmode == SFmode)
3508 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3509 else if (xmode == DFmode)
3510 *total = COSTS_N_INSNS (50);
3511 else if (xmode == DImode)
3512 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3513 else if (TARGET_MUL32)
3514 *total = COSTS_N_INSNS (4);
3515 else if (TARGET_MAC16)
3516 *total = COSTS_N_INSNS (16);
3517 else if (TARGET_MUL16)
3518 *total = COSTS_N_INSNS (12);
3520 *total = COSTS_N_INSNS (50);
3527 enum machine_mode xmode = GET_MODE (x);
3528 if (xmode == SFmode)
3530 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3533 else if (xmode == DFmode)
3535 *total = COSTS_N_INSNS (50);
3544 enum machine_mode xmode = GET_MODE (x);
3545 if (xmode == DImode)
3546 *total = COSTS_N_INSNS (50);
3547 else if (TARGET_DIV32)
3548 *total = COSTS_N_INSNS (32);
3550 *total = COSTS_N_INSNS (50);
3555 if (GET_MODE (x) == SFmode)
3556 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3558 *total = COSTS_N_INSNS (50);
3565 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3570 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3575 *total = COSTS_N_INSNS (1);
3583 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3586 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3588 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3589 > 4 * UNITS_PER_WORD);
3592 /* Worker function for TARGET_FUNCTION_VALUE. */
3595 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3598 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3599 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3600 ? SImode : TYPE_MODE (valtype),
3601 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3604 /* Worker function for TARGET_LIBCALL_VALUE. */
3607 xtensa_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
3609 return gen_rtx_REG ((GET_MODE_CLASS (mode) == MODE_INT
3610 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3611 ? SImode : mode, GP_RETURN);
3614 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */
3617 xtensa_function_value_regno_p (const unsigned int regno)
3619 return (regno == GP_RETURN);
3622 /* The static chain is passed in memory. Provide rtx giving 'mem'
3623 expressions that denote where they are stored. */
3626 xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
3628 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx;
3629 return gen_frame_mem (Pmode, plus_constant (base, -5 * UNITS_PER_WORD));
3633 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3634 instruction with a minimal stack frame in order to get some free
3635 registers. Once the actual call target is known, the proper stack frame
3636 size is extracted from the ENTRY instruction at the target and the
3637 current frame is adjusted to match. The trampoline then transfers
3638 control to the instruction following the ENTRY at the target. Note:
3639 this assumes that the target begins with an ENTRY instruction. */
3642 xtensa_asm_trampoline_template (FILE *stream)
3644 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3646 fprintf (stream, "\t.begin no-transform\n");
3647 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3651 /* Save the return address. */
3652 fprintf (stream, "\tmov\ta10, a0\n");
3654 /* Use a CALL0 instruction to skip past the constants and in the
3655 process get the PC into A0. This allows PC-relative access to
3656 the constants without relying on L32R. */
3657 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3660 fprintf (stream, "\tj\t.Lskipconsts\n");
3662 fprintf (stream, "\t.align\t4\n");
3663 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3664 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3665 fprintf (stream, ".Lskipconsts:\n");
3667 /* Load the static chain and function address from the trampoline. */
3670 fprintf (stream, "\taddi\ta0, a0, 3\n");
3671 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3672 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3676 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3677 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3680 /* Store the static chain. */
3681 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3683 /* Set the proper stack pointer value. */
3684 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3685 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3686 TARGET_BIG_ENDIAN ? 8 : 12);
3687 fprintf (stream, "\tslli\ta9, a9, 3\n");
3688 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3689 fprintf (stream, "\tsub\ta9, sp, a9\n");
3690 fprintf (stream, "\tmovsp\tsp, a9\n");
3693 /* Restore the return address. */
3694 fprintf (stream, "\tmov\ta0, a10\n");
3696 /* Jump to the instruction following the ENTRY. */
3697 fprintf (stream, "\taddi\ta8, a8, 3\n");
3698 fprintf (stream, "\tjx\ta8\n");
3700 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3702 fprintf (stream, "\t.byte\t0\n");
3704 fprintf (stream, "\tnop\n");
3706 fprintf (stream, "\t.end no-transform\n");
3710 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
3712 rtx func = XEXP (DECL_RTL (fndecl), 0);
3713 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3714 int chain_off = use_call0 ? 12 : 8;
3715 int func_off = use_call0 ? 16 : 12;
3717 emit_block_move (m_tramp, assemble_trampoline_template (),
3718 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3720 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain);
3721 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func);
3722 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3723 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
3726 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
3729 xtensa_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
3731 return !xtensa_tls_referenced_p (x);
3734 #include "gt-xtensa.h"