1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
33 #include "insn-attr.h"
34 #include "insn-codes.h"
43 #include "diagnostic-core.h"
49 #include "target-def.h"
50 #include "langhooks.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Array giving truth value on whether or not a given hard register
75 can support a given mode. */
76 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
78 /* Current frame size calculated by compute_frame_size. */
79 unsigned xtensa_current_frame_size;
81 /* Largest block move to handle in-line. */
82 #define LARGEST_MOVE_RATIO 15
84 /* Define the structure for the machine field in struct function. */
85 struct GTY(()) machine_function
87 int accesses_prev_frame;
91 rtx set_frame_ptr_insn;
94 /* Vector, indexed by hard register number, which contains 1 for a
95 register that is allowable in a candidate for leaf function
98 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
100 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
102 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
106 /* Map hard register number to register class */
107 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
109 RL_REGS, SP_REG, RL_REGS, RL_REGS,
110 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
111 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
112 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
113 AR_REGS, AR_REGS, BR_REGS,
114 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
115 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
116 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
117 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
121 static void xtensa_option_override (void);
122 static enum internal_test map_test_to_internal_test (enum rtx_code);
123 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
124 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
125 static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx);
126 static rtx fixup_subreg_mem (rtx);
127 static struct machine_function * xtensa_init_machine_status (void);
128 static rtx xtensa_legitimize_tls_address (rtx);
129 static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode);
130 static bool xtensa_return_in_msb (const_tree);
131 static void printx (FILE *, signed int);
132 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
133 static rtx xtensa_builtin_saveregs (void);
134 static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool);
135 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
136 int) ATTRIBUTE_UNUSED;
137 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
138 unsigned HOST_WIDE_INT);
139 static bool xtensa_rtx_costs (rtx, int, int, int *, bool);
140 static tree xtensa_build_builtin_va_list (void);
141 static bool xtensa_return_in_memory (const_tree, const_tree);
142 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
144 static void xtensa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
146 static rtx xtensa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
148 static rtx xtensa_function_incoming_arg (CUMULATIVE_ARGS *,
149 enum machine_mode, const_tree, bool);
150 static rtx xtensa_function_value (const_tree, const_tree, bool);
151 static void xtensa_init_builtins (void);
152 static tree xtensa_fold_builtin (tree, int, tree *, bool);
153 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
154 static void xtensa_va_start (tree, rtx);
155 static bool xtensa_frame_pointer_required (void);
156 static rtx xtensa_static_chain (const_tree, bool);
157 static void xtensa_asm_trampoline_template (FILE *);
158 static void xtensa_trampoline_init (rtx, tree, rtx);
160 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
163 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
165 static const struct default_options xtensa_option_optimization_table[] =
167 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
168 /* Reordering blocks for Xtensa is not a good idea unless the
169 compiler understands the range of conditional branches.
170 Currently all branch relaxation for Xtensa is handled in the
171 assembler, so GCC cannot do a good job of reordering blocks.
172 Do not enable reordering unless it is explicitly requested. */
173 { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 },
174 { OPT_LEVELS_NONE, 0, NULL, 0 }
178 /* This macro generates the assembly code for function exit,
179 on machines that need it. If FUNCTION_EPILOGUE is not defined
180 then individual return instructions are generated for each
181 return statement. Args are same as for FUNCTION_PROLOGUE. */
183 #undef TARGET_ASM_FUNCTION_EPILOGUE
184 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
186 /* These hooks specify assembly directives for creating certain kinds
187 of integer object. */
189 #undef TARGET_ASM_ALIGNED_SI_OP
190 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
192 #undef TARGET_ASM_SELECT_RTX_SECTION
193 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
195 #undef TARGET_DEFAULT_TARGET_FLAGS
196 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
198 #undef TARGET_LEGITIMIZE_ADDRESS
199 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
201 #undef TARGET_RTX_COSTS
202 #define TARGET_RTX_COSTS xtensa_rtx_costs
203 #undef TARGET_ADDRESS_COST
204 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
206 #undef TARGET_BUILD_BUILTIN_VA_LIST
207 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
209 #undef TARGET_EXPAND_BUILTIN_VA_START
210 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
212 #undef TARGET_PROMOTE_FUNCTION_MODE
213 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
214 #undef TARGET_PROMOTE_PROTOTYPES
215 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
217 #undef TARGET_RETURN_IN_MEMORY
218 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
219 #undef TARGET_FUNCTION_VALUE
220 #define TARGET_FUNCTION_VALUE xtensa_function_value
221 #undef TARGET_SPLIT_COMPLEX_ARG
222 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
223 #undef TARGET_MUST_PASS_IN_STACK
224 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
225 #undef TARGET_FUNCTION_ARG_ADVANCE
226 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
227 #undef TARGET_FUNCTION_ARG
228 #define TARGET_FUNCTION_ARG xtensa_function_arg
229 #undef TARGET_FUNCTION_INCOMING_ARG
230 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
232 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
233 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
234 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
235 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
237 #undef TARGET_RETURN_IN_MSB
238 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
240 #undef TARGET_INIT_BUILTINS
241 #define TARGET_INIT_BUILTINS xtensa_init_builtins
242 #undef TARGET_FOLD_BUILTIN
243 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
244 #undef TARGET_EXPAND_BUILTIN
245 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
247 #undef TARGET_SECONDARY_RELOAD
248 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
250 #undef TARGET_HAVE_TLS
251 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
253 #undef TARGET_CANNOT_FORCE_CONST_MEM
254 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_tls_referenced_p
256 #undef TARGET_LEGITIMATE_ADDRESS_P
257 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
259 #undef TARGET_FRAME_POINTER_REQUIRED
260 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
262 #undef TARGET_STATIC_CHAIN
263 #define TARGET_STATIC_CHAIN xtensa_static_chain
264 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
265 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
266 #undef TARGET_TRAMPOLINE_INIT
267 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
269 #undef TARGET_OPTION_OVERRIDE
270 #define TARGET_OPTION_OVERRIDE xtensa_option_override
271 #undef TARGET_OPTION_OPTIMIZATION_TABLE
272 #define TARGET_OPTION_OPTIMIZATION_TABLE xtensa_option_optimization_table
274 struct gcc_target targetm = TARGET_INITIALIZER;
277 /* Functions to test Xtensa immediate operand validity. */
280 xtensa_simm8 (HOST_WIDE_INT v)
282 return v >= -128 && v <= 127;
287 xtensa_simm8x256 (HOST_WIDE_INT v)
289 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
294 xtensa_simm12b (HOST_WIDE_INT v)
296 return v >= -2048 && v <= 2047;
301 xtensa_uimm8 (HOST_WIDE_INT v)
303 return v >= 0 && v <= 255;
308 xtensa_uimm8x2 (HOST_WIDE_INT v)
310 return (v & 1) == 0 && (v >= 0 && v <= 510);
315 xtensa_uimm8x4 (HOST_WIDE_INT v)
317 return (v & 3) == 0 && (v >= 0 && v <= 1020);
322 xtensa_b4const (HOST_WIDE_INT v)
349 xtensa_b4const_or_zero (HOST_WIDE_INT v)
353 return xtensa_b4const (v);
358 xtensa_b4constu (HOST_WIDE_INT v)
385 xtensa_mask_immediate (HOST_WIDE_INT v)
387 #define MAX_MASK_SIZE 16
390 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
403 /* This is just like the standard true_regnum() function except that it
404 works even when reg_renumber is not initialized. */
407 xt_true_regnum (rtx x)
409 if (GET_CODE (x) == REG)
412 && REGNO (x) >= FIRST_PSEUDO_REGISTER
413 && reg_renumber[REGNO (x)] >= 0)
414 return reg_renumber[REGNO (x)];
417 if (GET_CODE (x) == SUBREG)
419 int base = xt_true_regnum (SUBREG_REG (x));
420 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
421 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
422 GET_MODE (SUBREG_REG (x)),
423 SUBREG_BYTE (x), GET_MODE (x));
430 xtensa_valid_move (enum machine_mode mode, rtx *operands)
432 /* Either the destination or source must be a register, and the
433 MAC16 accumulator doesn't count. */
435 if (register_operand (operands[0], mode))
437 int dst_regnum = xt_true_regnum (operands[0]);
439 /* The stack pointer can only be assigned with a MOVSP opcode. */
440 if (dst_regnum == STACK_POINTER_REGNUM)
441 return (mode == SImode
442 && register_operand (operands[1], mode)
443 && !ACC_REG_P (xt_true_regnum (operands[1])));
445 if (!ACC_REG_P (dst_regnum))
448 if (register_operand (operands[1], mode))
450 int src_regnum = xt_true_regnum (operands[1]);
451 if (!ACC_REG_P (src_regnum))
459 smalloffset_mem_p (rtx op)
461 if (GET_CODE (op) == MEM)
463 rtx addr = XEXP (op, 0);
464 if (GET_CODE (addr) == REG)
465 return BASE_REG_P (addr, 0);
466 if (GET_CODE (addr) == PLUS)
468 rtx offset = XEXP (addr, 0);
470 if (GET_CODE (offset) != CONST_INT)
471 offset = XEXP (addr, 1);
472 if (GET_CODE (offset) != CONST_INT)
475 val = INTVAL (offset);
476 return (val & 3) == 0 && (val >= 0 && val <= 60);
484 constantpool_address_p (rtx addr)
488 if (GET_CODE (addr) == CONST)
492 /* Only handle (PLUS (SYM, OFFSET)) form. */
493 addr = XEXP (addr, 0);
494 if (GET_CODE (addr) != PLUS)
497 /* Make sure the address is word aligned. */
498 offset = XEXP (addr, 1);
499 if ((GET_CODE (offset) != CONST_INT)
500 || ((INTVAL (offset) & 3) != 0))
503 sym = XEXP (addr, 0);
506 if ((GET_CODE (sym) == SYMBOL_REF)
507 && CONSTANT_POOL_ADDRESS_P (sym))
514 constantpool_mem_p (rtx op)
516 if (GET_CODE (op) == SUBREG)
517 op = SUBREG_REG (op);
518 if (GET_CODE (op) == MEM)
519 return constantpool_address_p (XEXP (op, 0));
524 /* Return TRUE if X is a thread-local symbol. */
527 xtensa_tls_symbol_p (rtx x)
529 if (! TARGET_HAVE_TLS)
532 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
537 xtensa_extend_reg (rtx dst, rtx src)
539 rtx temp = gen_reg_rtx (SImode);
540 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
542 /* Generate paradoxical subregs as needed so that the modes match. */
543 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
544 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
546 emit_insn (gen_ashlsi3 (temp, src, shift));
547 emit_insn (gen_ashrsi3 (dst, temp, shift));
552 xtensa_mem_offset (unsigned v, enum machine_mode mode)
557 /* Handle the worst case for block moves. See xtensa_expand_block_move
558 where we emit an optimized block move operation if the block can be
559 moved in < "move_ratio" pieces. The worst case is when the block is
560 aligned but has a size of (3 mod 4) (does this happen?) so that the
561 last piece requires a byte load/store. */
562 return (xtensa_uimm8 (v)
563 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
566 return xtensa_uimm8 (v);
569 return xtensa_uimm8x2 (v);
572 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
578 return xtensa_uimm8x4 (v);
582 /* Make normal rtx_code into something we can index from an array. */
584 static enum internal_test
585 map_test_to_internal_test (enum rtx_code test_code)
587 enum internal_test test = ITEST_MAX;
592 case EQ: test = ITEST_EQ; break;
593 case NE: test = ITEST_NE; break;
594 case GT: test = ITEST_GT; break;
595 case GE: test = ITEST_GE; break;
596 case LT: test = ITEST_LT; break;
597 case LE: test = ITEST_LE; break;
598 case GTU: test = ITEST_GTU; break;
599 case GEU: test = ITEST_GEU; break;
600 case LTU: test = ITEST_LTU; break;
601 case LEU: test = ITEST_LEU; break;
608 /* Generate the code to compare two integer values. The return value is
609 the comparison expression. */
612 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
613 rtx cmp0, /* first operand to compare */
614 rtx cmp1, /* second operand to compare */
615 int *p_invert /* whether branch needs to reverse test */)
619 enum rtx_code test_code; /* test code to use in insn */
620 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
621 int const_add; /* constant to add (convert LE -> LT) */
622 int reverse_regs; /* reverse registers in test */
623 int invert_const; /* != 0 if invert value if cmp1 is constant */
624 int invert_reg; /* != 0 if invert value if cmp1 is register */
625 int unsignedp; /* != 0 for unsigned comparisons. */
628 static struct cmp_info info[ (int)ITEST_MAX ] = {
630 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
631 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
633 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
634 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
635 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
636 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
638 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
639 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
640 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
641 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
644 enum internal_test test;
645 enum machine_mode mode;
646 struct cmp_info *p_info;
648 test = map_test_to_internal_test (test_code);
649 gcc_assert (test != ITEST_MAX);
651 p_info = &info[ (int)test ];
653 mode = GET_MODE (cmp0);
654 if (mode == VOIDmode)
655 mode = GET_MODE (cmp1);
657 /* Make sure we can handle any constants given to us. */
658 if (GET_CODE (cmp1) == CONST_INT)
660 HOST_WIDE_INT value = INTVAL (cmp1);
661 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
663 /* if the immediate overflows or does not fit in the immediate field,
664 spill it to a register */
666 if ((p_info->unsignedp ?
667 (uvalue + p_info->const_add > uvalue) :
668 (value + p_info->const_add > value)) != (p_info->const_add > 0))
670 cmp1 = force_reg (mode, cmp1);
672 else if (!(p_info->const_range_p) (value + p_info->const_add))
674 cmp1 = force_reg (mode, cmp1);
677 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
679 cmp1 = force_reg (mode, cmp1);
682 /* See if we need to invert the result. */
683 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
684 ? p_info->invert_const
685 : p_info->invert_reg);
687 /* Comparison to constants, may involve adding 1 to change a LT into LE.
688 Comparison between two registers, may involve switching operands. */
689 if (GET_CODE (cmp1) == CONST_INT)
691 if (p_info->const_add != 0)
692 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
695 else if (p_info->reverse_regs)
702 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
706 /* Generate the code to compare two float values. The return value is
707 the comparison expression. */
710 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
711 rtx cmp0, /* first operand to compare */
712 rtx cmp1 /* second operand to compare */)
714 rtx (*gen_fn) (rtx, rtx, rtx);
716 int reverse_regs, invert;
720 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
721 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
722 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
723 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
724 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
725 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
726 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
727 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
728 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
729 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
730 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
731 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
733 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
735 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
737 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
738 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
748 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
749 emit_insn (gen_fn (brtmp, cmp0, cmp1));
751 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
756 xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode)
758 enum rtx_code test_code = GET_CODE (operands[0]);
759 rtx cmp0 = operands[1];
760 rtx cmp1 = operands[2];
769 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
773 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
777 if (!TARGET_HARD_FLOAT)
778 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
781 cmp = gen_float_relational (test_code, cmp0, cmp1);
785 /* Generate the branch. */
787 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
796 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
797 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
804 gen_conditional_move (enum rtx_code code, enum machine_mode mode,
811 /* Jump optimization calls get_condition() which canonicalizes
812 comparisons like (GE x <const>) to (GT x <const-1>).
813 Transform those comparisons back to GE, since that is the
814 comparison supported in Xtensa. We shouldn't have to
815 transform <LE x const> comparisons, because neither
816 xtensa_expand_conditional_branch() nor get_condition() will
819 if ((code == GT) && (op1 == constm1_rtx))
824 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
826 if (boolean_operator (cmp, VOIDmode))
828 /* Swap the operands to make const0 second. */
829 if (op0 == const0_rtx)
835 /* If not comparing against zero, emit a comparison (subtract). */
836 if (op1 != const0_rtx)
838 op0 = expand_binop (SImode, sub_optab, op0, op1,
839 0, 0, OPTAB_LIB_WIDEN);
843 else if (branch_operator (cmp, VOIDmode))
845 /* Swap the operands to make const0 second. */
846 if (op0 == const0_rtx)
853 case LT: code = GE; break;
854 case GE: code = LT; break;
855 default: gcc_unreachable ();
859 if (op1 != const0_rtx)
865 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
868 if (TARGET_HARD_FLOAT && mode == SFmode)
869 return gen_float_relational (code, op0, op1);
876 xtensa_expand_conditional_move (rtx *operands, int isflt)
878 rtx dest = operands[0];
879 rtx cmp = operands[1];
880 enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0));
881 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
883 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode,
884 XEXP (cmp, 0), XEXP (cmp, 1))))
888 gen_fn = (cmp_mode == SImode
889 ? gen_movsfcc_internal0
890 : gen_movsfcc_internal1);
892 gen_fn = (cmp_mode == SImode
893 ? gen_movsicc_internal0
894 : gen_movsicc_internal1);
896 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp));
902 xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode)
904 rtx dest = operands[0];
906 rtx one_tmp, zero_tmp;
907 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
909 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode,
910 operands[2], operands[3])))
913 one_tmp = gen_reg_rtx (SImode);
914 zero_tmp = gen_reg_rtx (SImode);
915 emit_insn (gen_movsi (one_tmp, const_true_rtx));
916 emit_insn (gen_movsi (zero_tmp, const0_rtx));
918 gen_fn = (cmp_mode == SImode
919 ? gen_movsicc_internal0
920 : gen_movsicc_internal1);
921 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
926 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
927 for the output, i.e., the input operands are twice as big as MODE. */
930 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
932 switch (GET_CODE (operands[1]))
935 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
936 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
940 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
941 operands[2] = adjust_address (operands[1], mode, 0);
946 split_double (operands[1], &operands[2], &operands[3]);
953 switch (GET_CODE (operands[0]))
956 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
957 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
961 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
962 operands[0] = adjust_address (operands[0], mode, 0);
971 /* Emit insns to move operands[1] into operands[0].
972 Return 1 if we have written out everything that needs to be done to
973 do the move. Otherwise, return 0 and the caller will emit the move
977 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
979 rtx src = operands[1];
982 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
984 rtx dst = operands[0];
986 if (xtensa_tls_referenced_p (src))
990 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
992 addend = XEXP (XEXP (src, 0), 1);
993 src = XEXP (XEXP (src, 0), 0);
996 src = xtensa_legitimize_tls_address (src);
999 src = gen_rtx_PLUS (mode, src, addend);
1000 src = force_operand (src, dst);
1002 emit_move_insn (dst, src);
1006 if (! TARGET_CONST16)
1008 src = force_const_mem (SImode, src);
1012 /* PC-relative loads are always SImode, and CONST16 is only
1013 supported in the movsi pattern, so add a SUBREG for any other
1018 if (register_operand (dst, mode))
1020 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src);
1025 src = force_reg (SImode, src);
1026 src = gen_lowpart_SUBREG (mode, src);
1032 if (!(reload_in_progress | reload_completed)
1033 && !xtensa_valid_move (mode, operands))
1034 operands[1] = force_reg (mode, operands[1]);
1036 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1038 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1039 instruction won't be recognized after reload, so we remove the
1040 subreg and adjust mem accordingly. */
1041 if (reload_in_progress)
1043 operands[0] = fixup_subreg_mem (operands[0]);
1044 operands[1] = fixup_subreg_mem (operands[1]);
1051 fixup_subreg_mem (rtx x)
1053 if (GET_CODE (x) == SUBREG
1054 && GET_CODE (SUBREG_REG (x)) == REG
1055 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
1058 gen_rtx_SUBREG (GET_MODE (x),
1059 reg_equiv_mem [REGNO (SUBREG_REG (x))],
1061 x = alter_subreg (&temp);
1067 /* Check if an incoming argument in a7 is expected to be used soon and
1068 if OPND is a register or register pair that includes a7. If so,
1069 create a new pseudo and copy a7 into that pseudo at the very
1070 beginning of the function, followed by the special "set_frame_ptr"
1071 unspec_volatile insn. The return value is either the original
1072 operand, if it is not a7, or the new pseudo containing a copy of
1073 the incoming argument. This is necessary because the register
1074 allocator will ignore conflicts with a7 and may either assign some
1075 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1076 the incoming argument in a7. By copying the argument out of a7 as
1077 the very first thing, and then immediately following that with an
1078 unspec_volatile to keep the scheduler away, we should avoid any
1079 problems. Putting the set_frame_ptr insn at the beginning, with
1080 only the a7 copy before it, also makes it easier for the prologue
1081 expander to initialize the frame pointer after the a7 copy and to
1082 fix up the a7 copy to use the stack pointer instead of the frame
1086 xtensa_copy_incoming_a7 (rtx opnd)
1088 rtx entry_insns = 0;
1090 enum machine_mode mode;
1092 if (!cfun->machine->need_a7_copy)
1095 /* This function should never be called again once a7 has been copied. */
1096 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1098 mode = GET_MODE (opnd);
1100 /* The operand using a7 may come in a later instruction, so just return
1101 the original operand if it doesn't use a7. */
1103 if (GET_CODE (reg) == SUBREG)
1105 gcc_assert (SUBREG_BYTE (reg) == 0);
1106 reg = SUBREG_REG (reg);
1108 if (GET_CODE (reg) != REG
1109 || REGNO (reg) > A7_REG
1110 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1113 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1114 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1116 cfun->machine->need_a7_copy = false;
1118 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1119 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1122 tmp = gen_reg_rtx (mode);
1128 /* Copy the value out of A7 here but keep the first word in A6 until
1129 after the set_frame_ptr insn. Otherwise, the register allocator
1130 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1132 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1133 gen_raw_REG (SImode, A7_REG)));
1136 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1139 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1142 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1145 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1151 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1153 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1154 if (mode == DFmode || mode == DImode)
1155 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1156 gen_rtx_REG (SImode, A7_REG - 1)));
1157 entry_insns = get_insns ();
1160 if (cfun->machine->vararg_a7)
1162 /* This is called from within builtin_saveregs, which will insert the
1163 saveregs code at the function entry, ahead of anything placed at
1164 the function entry now. Instead, save the sequence to be inserted
1165 at the beginning of the saveregs code. */
1166 cfun->machine->vararg_a7_copy = entry_insns;
1170 /* Put entry_insns after the NOTE that starts the function. If
1171 this is inside a start_sequence, make the outer-level insn
1172 chain current, so the code is placed at the start of the
1174 push_topmost_sequence ();
1175 /* Do not use entry_of_function() here. This is called from within
1176 expand_function_start, when the CFG still holds GIMPLE. */
1177 emit_insn_after (entry_insns, get_insns ());
1178 pop_topmost_sequence ();
1185 /* Try to expand a block move operation to a sequence of RTL move
1186 instructions. If not optimizing, or if the block size is not a
1187 constant, or if the block is too large, the expansion fails and GCC
1188 falls back to calling memcpy().
1190 operands[0] is the destination
1191 operands[1] is the source
1192 operands[2] is the length
1193 operands[3] is the alignment */
1196 xtensa_expand_block_move (rtx *operands)
1198 static const enum machine_mode mode_from_align[] =
1200 VOIDmode, QImode, HImode, VOIDmode, SImode,
1203 rtx dst_mem = operands[0];
1204 rtx src_mem = operands[1];
1205 HOST_WIDE_INT bytes, align;
1206 int num_pieces, move_ratio;
1208 enum machine_mode mode[2];
1217 /* If this is not a fixed size move, just call memcpy. */
1218 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1221 bytes = INTVAL (operands[2]);
1222 align = INTVAL (operands[3]);
1224 /* Anything to move? */
1228 if (align > MOVE_MAX)
1231 /* Decide whether to expand inline based on the optimization level. */
1234 move_ratio = LARGEST_MOVE_RATIO;
1235 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1236 if (num_pieces > move_ratio)
1239 x = XEXP (dst_mem, 0);
1242 x = force_reg (Pmode, x);
1243 dst_mem = replace_equiv_address (dst_mem, x);
1246 x = XEXP (src_mem, 0);
1249 x = force_reg (Pmode, x);
1250 src_mem = replace_equiv_address (src_mem, x);
1253 active[0] = active[1] = false;
1264 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1265 next_amount = MIN (next_amount, align);
1267 amount[next] = next_amount;
1268 mode[next] = mode_from_align[next_amount];
1269 temp[next] = gen_reg_rtx (mode[next]);
1271 x = adjust_address (src_mem, mode[next], offset_ld);
1272 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1274 offset_ld += next_amount;
1275 bytes -= next_amount;
1276 active[next] = true;
1281 active[phase] = false;
1283 x = adjust_address (dst_mem, mode[phase], offset_st);
1284 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1286 offset_st += amount[phase];
1289 while (active[next]);
1296 xtensa_expand_nonlocal_goto (rtx *operands)
1298 rtx goto_handler = operands[1];
1299 rtx containing_fp = operands[3];
1301 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1302 is too big to generate in-line. */
1304 if (GET_CODE (containing_fp) != REG)
1305 containing_fp = force_reg (Pmode, containing_fp);
1307 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1308 LCT_NORMAL, VOIDmode, 2,
1309 containing_fp, Pmode,
1310 goto_handler, Pmode);
1314 static struct machine_function *
1315 xtensa_init_machine_status (void)
1317 return ggc_alloc_cleared_machine_function ();
1321 /* Shift VAL of mode MODE left by COUNT bits. */
1324 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1326 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1327 NULL_RTX, 1, OPTAB_DIRECT);
1328 return expand_simple_binop (SImode, ASHIFT, val, count,
1329 NULL_RTX, 1, OPTAB_DIRECT);
1333 /* Structure to hold the initial parameters for a compare_and_swap operation
1334 in HImode and QImode. */
1336 struct alignment_context
1338 rtx memsi; /* SI aligned memory location. */
1339 rtx shift; /* Bit offset with regard to lsb. */
1340 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1341 rtx modemaski; /* ~modemask */
1345 /* Initialize structure AC for word access to HI and QI mode memory. */
1348 init_alignment_context (struct alignment_context *ac, rtx mem)
1350 enum machine_mode mode = GET_MODE (mem);
1351 rtx byteoffset = NULL_RTX;
1352 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1355 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1358 /* Alignment is unknown. */
1361 /* Force the address into a register. */
1362 addr = force_reg (Pmode, XEXP (mem, 0));
1364 /* Align it to SImode. */
1365 align = expand_simple_binop (Pmode, AND, addr,
1366 GEN_INT (-GET_MODE_SIZE (SImode)),
1367 NULL_RTX, 1, OPTAB_DIRECT);
1369 ac->memsi = gen_rtx_MEM (SImode, align);
1370 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1371 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1372 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1374 byteoffset = expand_simple_binop (Pmode, AND, addr,
1375 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1376 NULL_RTX, 1, OPTAB_DIRECT);
1379 /* Calculate shiftcount. */
1380 if (TARGET_BIG_ENDIAN)
1382 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1384 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1385 NULL_RTX, 1, OPTAB_DIRECT);
1390 ac->shift = NULL_RTX;
1392 ac->shift = byteoffset;
1395 if (ac->shift != NULL_RTX)
1397 /* Shift is the byte count, but we need the bitcount. */
1398 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1399 GEN_INT (BITS_PER_UNIT),
1400 NULL_RTX, 1, OPTAB_DIRECT);
1401 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1402 GEN_INT (GET_MODE_MASK (mode)),
1404 NULL_RTX, 1, OPTAB_DIRECT);
1407 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1409 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1413 /* Expand an atomic compare and swap operation for HImode and QImode.
1414 MEM is the memory location, CMP the old value to compare MEM with
1415 and NEW_RTX the value to set if CMP == MEM. */
1418 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx)
1420 enum machine_mode mode = GET_MODE (mem);
1421 struct alignment_context ac;
1422 rtx tmp, cmpv, newv, val;
1423 rtx oldval = gen_reg_rtx (SImode);
1424 rtx res = gen_reg_rtx (SImode);
1425 rtx csloop = gen_label_rtx ();
1426 rtx csend = gen_label_rtx ();
1428 init_alignment_context (&ac, mem);
1430 if (ac.shift != NULL_RTX)
1432 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1433 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift);
1436 /* Load the surrounding word into VAL with the MEM value masked out. */
1437 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1438 ac.modemaski, NULL_RTX, 1,
1440 emit_label (csloop);
1442 /* Patch CMP and NEW_RTX into VAL at correct position. */
1443 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1444 NULL_RTX, 1, OPTAB_DIRECT));
1445 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
1446 NULL_RTX, 1, OPTAB_DIRECT));
1448 /* Jump to end if we're done. */
1449 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1450 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1452 /* Check for changes outside mode. */
1453 emit_move_insn (oldval, val);
1454 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1455 val, 1, OPTAB_DIRECT);
1457 emit_move_insn (val, tmp);
1459 /* Loop internal if so. */
1460 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1464 /* Return the correct part of the bitfield. */
1465 convert_move (target,
1466 (ac.shift == NULL_RTX ? res
1467 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1468 NULL_RTX, 1, OPTAB_DIRECT)),
1473 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1474 the default expansion works fine for SImode). MEM is the memory location
1475 and VAL the value to play with. If AFTER is true then store the value
1476 MEM holds after the operation, if AFTER is false then store the value MEM
1477 holds before the operation. If TARGET is zero then discard that value, else
1478 store it to TARGET. */
1481 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1484 enum machine_mode mode = GET_MODE (mem);
1485 struct alignment_context ac;
1486 rtx csloop = gen_label_rtx ();
1488 rtx old = gen_reg_rtx (SImode);
1489 rtx new_rtx = gen_reg_rtx (SImode);
1490 rtx orig = NULL_RTX;
1492 init_alignment_context (&ac, mem);
1494 /* Prepare values before the compare-and-swap loop. */
1495 if (ac.shift != NULL_RTX)
1496 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1501 orig = gen_reg_rtx (SImode);
1502 convert_move (orig, val, 1);
1510 case MULT: /* NAND */
1512 /* val = "11..1<val>11..1" */
1513 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1514 NULL_RTX, 1, OPTAB_DIRECT);
1521 /* Load full word. Subsequent loads are performed by S32C1I. */
1522 cmp = force_reg (SImode, ac.memsi);
1524 emit_label (csloop);
1525 emit_move_insn (old, cmp);
1531 val = expand_simple_binop (SImode, code, old, orig,
1532 NULL_RTX, 1, OPTAB_DIRECT);
1533 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1534 NULL_RTX, 1, OPTAB_DIRECT);
1537 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1538 NULL_RTX, 1, OPTAB_DIRECT);
1539 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1540 new_rtx, 1, OPTAB_DIRECT);
1546 tmp = expand_simple_binop (SImode, code, old, val,
1547 new_rtx, 1, OPTAB_DIRECT);
1550 case MULT: /* NAND */
1551 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1552 NULL_RTX, 1, OPTAB_DIRECT);
1553 tmp = expand_simple_binop (SImode, AND, tmp, val,
1554 new_rtx, 1, OPTAB_DIRECT);
1562 emit_move_insn (new_rtx, tmp);
1563 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx));
1564 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1568 tmp = (after ? new_rtx : cmp);
1569 convert_move (target,
1570 (ac.shift == NULL_RTX ? tmp
1571 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1572 NULL_RTX, 1, OPTAB_DIRECT)),
1579 xtensa_setup_frame_addresses (void)
1581 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1582 cfun->machine->accesses_prev_frame = 1;
1585 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1586 LCT_NORMAL, VOIDmode, 0);
1590 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1591 a comment showing where the end of the loop is. However, if there is a
1592 label or a branch at the end of the loop then we need to place a nop
1593 there. If the loop ends with a label we need the nop so that branches
1594 targeting that label will target the nop (and thus remain in the loop),
1595 instead of targeting the instruction after the loop (and thus exiting
1596 the loop). If the loop ends with a branch, we need the nop in case the
1597 branch is targeting a location inside the loop. When the branch
1598 executes it will cause the loop count to be decremented even if it is
1599 taken (because it is the last instruction in the loop), so we need to
1600 nop after the branch to prevent the loop count from being decremented
1601 when the branch is taken. */
1604 xtensa_emit_loop_end (rtx insn, rtx *operands)
1608 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1610 switch (GET_CODE (insn))
1617 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1623 rtx body = PATTERN (insn);
1625 if (GET_CODE (body) == JUMP_INSN)
1627 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1630 else if ((GET_CODE (body) != USE)
1631 && (GET_CODE (body) != CLOBBER))
1638 output_asm_insn ("# loop end for %0", operands);
1643 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1645 static char result[64];
1649 code = GET_CODE (operands[3]);
1652 case EQ: op = inverted ? "ne" : "eq"; break;
1653 case NE: op = inverted ? "eq" : "ne"; break;
1654 case LT: op = inverted ? "ge" : "lt"; break;
1655 case GE: op = inverted ? "lt" : "ge"; break;
1656 case LTU: op = inverted ? "geu" : "ltu"; break;
1657 case GEU: op = inverted ? "ltu" : "geu"; break;
1658 default: gcc_unreachable ();
1663 if (INTVAL (operands[1]) == 0)
1664 sprintf (result, "b%sz%s\t%%0, %%2", op,
1665 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1667 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1670 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1677 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1679 static char result[64];
1682 switch (GET_CODE (operands[3]))
1684 case EQ: op = inverted ? "bs" : "bc"; break;
1685 case NE: op = inverted ? "bc" : "bs"; break;
1686 default: gcc_unreachable ();
1691 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1692 operands[1] = GEN_INT (bitnum);
1693 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1696 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1703 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1705 static char result[64];
1709 code = GET_CODE (operands[4]);
1714 case EQ: op = inverted ? "t" : "f"; break;
1715 case NE: op = inverted ? "f" : "t"; break;
1716 default: gcc_unreachable ();
1723 case EQ: op = inverted ? "nez" : "eqz"; break;
1724 case NE: op = inverted ? "eqz" : "nez"; break;
1725 case LT: op = inverted ? "gez" : "ltz"; break;
1726 case GE: op = inverted ? "ltz" : "gez"; break;
1727 default: gcc_unreachable ();
1731 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1732 op, isfp ? ".s" : "", inverted ? 3 : 2);
1738 xtensa_emit_call (int callop, rtx *operands)
1740 static char result[64];
1741 rtx tgt = operands[callop];
1743 if (GET_CODE (tgt) == CONST_INT)
1744 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1745 else if (register_operand (tgt, VOIDmode))
1746 sprintf (result, "callx8\t%%%d", callop);
1748 sprintf (result, "call8\t%%%d", callop);
1755 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1757 /* Allow constant pool addresses. */
1758 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1759 && ! TARGET_CONST16 && constantpool_address_p (addr)
1760 && ! xtensa_tls_referenced_p (addr))
1763 while (GET_CODE (addr) == SUBREG)
1764 addr = SUBREG_REG (addr);
1766 /* Allow base registers. */
1767 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1770 /* Check for "register + offset" addressing. */
1771 if (GET_CODE (addr) == PLUS)
1773 rtx xplus0 = XEXP (addr, 0);
1774 rtx xplus1 = XEXP (addr, 1);
1775 enum rtx_code code0;
1776 enum rtx_code code1;
1778 while (GET_CODE (xplus0) == SUBREG)
1779 xplus0 = SUBREG_REG (xplus0);
1780 code0 = GET_CODE (xplus0);
1782 while (GET_CODE (xplus1) == SUBREG)
1783 xplus1 = SUBREG_REG (xplus1);
1784 code1 = GET_CODE (xplus1);
1786 /* Swap operands if necessary so the register is first. */
1787 if (code0 != REG && code1 == REG)
1789 xplus0 = XEXP (addr, 1);
1790 xplus1 = XEXP (addr, 0);
1791 code0 = GET_CODE (xplus0);
1792 code1 = GET_CODE (xplus1);
1795 if (code0 == REG && BASE_REG_P (xplus0, strict)
1796 && code1 == CONST_INT
1797 && xtensa_mem_offset (INTVAL (xplus1), mode))
1805 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1807 static GTY(()) rtx xtensa_tls_module_base_symbol;
1810 xtensa_tls_module_base (void)
1812 if (! xtensa_tls_module_base_symbol)
1814 xtensa_tls_module_base_symbol =
1815 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_");
1816 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol)
1817 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
1820 return xtensa_tls_module_base_symbol;
1825 xtensa_call_tls_desc (rtx sym, rtx *retp)
1827 rtx fn, arg, a10, call_insn, insns;
1830 fn = gen_reg_rtx (Pmode);
1831 arg = gen_reg_rtx (Pmode);
1832 a10 = gen_rtx_REG (Pmode, 10);
1834 emit_insn (gen_tls_func (fn, sym));
1835 emit_insn (gen_tls_arg (arg, sym));
1836 emit_move_insn (a10, arg);
1837 call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx));
1838 CALL_INSN_FUNCTION_USAGE (call_insn)
1839 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, a10),
1840 CALL_INSN_FUNCTION_USAGE (call_insn));
1841 insns = get_insns ();
1850 xtensa_legitimize_tls_address (rtx x)
1852 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
1853 rtx dest, tp, ret, modbase, base, addend, insns;
1855 dest = gen_reg_rtx (Pmode);
1858 case TLS_MODEL_GLOBAL_DYNAMIC:
1859 insns = xtensa_call_tls_desc (x, &ret);
1860 emit_libcall_block (insns, dest, ret, x);
1863 case TLS_MODEL_LOCAL_DYNAMIC:
1864 base = gen_reg_rtx (Pmode);
1865 modbase = xtensa_tls_module_base ();
1866 insns = xtensa_call_tls_desc (modbase, &ret);
1867 emit_libcall_block (insns, base, ret, modbase);
1868 addend = force_reg (SImode, gen_sym_DTPOFF (x));
1869 emit_insn (gen_addsi3 (dest, base, addend));
1872 case TLS_MODEL_INITIAL_EXEC:
1873 case TLS_MODEL_LOCAL_EXEC:
1874 tp = gen_reg_rtx (SImode);
1875 emit_insn (gen_load_tp (tp));
1876 addend = force_reg (SImode, gen_sym_TPOFF (x));
1877 emit_insn (gen_addsi3 (dest, tp, addend));
1889 xtensa_legitimize_address (rtx x,
1890 rtx oldx ATTRIBUTE_UNUSED,
1891 enum machine_mode mode)
1893 if (xtensa_tls_symbol_p (x))
1894 return xtensa_legitimize_tls_address (x);
1896 if (GET_CODE (x) == PLUS)
1898 rtx plus0 = XEXP (x, 0);
1899 rtx plus1 = XEXP (x, 1);
1901 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1903 plus0 = XEXP (x, 1);
1904 plus1 = XEXP (x, 0);
1907 /* Try to split up the offset to use an ADDMI instruction. */
1908 if (GET_CODE (plus0) == REG
1909 && GET_CODE (plus1) == CONST_INT
1910 && !xtensa_mem_offset (INTVAL (plus1), mode)
1911 && !xtensa_simm8 (INTVAL (plus1))
1912 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1913 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1915 rtx temp = gen_reg_rtx (Pmode);
1916 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1917 emit_insn (gen_rtx_SET (Pmode, temp,
1918 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1919 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1927 /* Helper for xtensa_tls_referenced_p. */
1930 xtensa_tls_referenced_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1932 if (GET_CODE (*x) == SYMBOL_REF)
1933 return SYMBOL_REF_TLS_MODEL (*x) != 0;
1935 /* Ignore TLS references that have already been legitimized. */
1936 if (GET_CODE (*x) == UNSPEC)
1938 switch (XINT (*x, 1))
1942 case UNSPEC_TLS_FUNC:
1943 case UNSPEC_TLS_ARG:
1944 case UNSPEC_TLS_CALL:
1955 /* Return TRUE if X contains any TLS symbol references. */
1958 xtensa_tls_referenced_p (rtx x)
1960 if (! TARGET_HAVE_TLS)
1963 return for_each_rtx (&x, xtensa_tls_referenced_p_1, NULL);
1967 /* Return the debugger register number to use for 'regno'. */
1970 xtensa_dbx_register_number (int regno)
1974 if (GP_REG_P (regno))
1976 regno -= GP_REG_FIRST;
1979 else if (BR_REG_P (regno))
1981 regno -= BR_REG_FIRST;
1984 else if (FP_REG_P (regno))
1986 regno -= FP_REG_FIRST;
1989 else if (ACC_REG_P (regno))
1991 first = 0x200; /* Start of Xtensa special registers. */
1992 regno = 16; /* ACCLO is special register 16. */
1995 /* When optimizing, we sometimes get asked about pseudo-registers
1996 that don't represent hard registers. Return 0 for these. */
2000 return first + regno;
2004 /* Argument support functions. */
2006 /* Initialize CUMULATIVE_ARGS for a function. */
2009 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
2012 cum->incoming = incoming;
2016 /* Advance the argument to the next argument position. */
2019 xtensa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2020 const_tree type, bool named ATTRIBUTE_UNUSED)
2025 arg_words = &cum->arg_words;
2026 max = MAX_ARGS_IN_REGISTERS;
2028 words = (((mode != BLKmode)
2029 ? (int) GET_MODE_SIZE (mode)
2030 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2032 if (*arg_words < max
2033 && (targetm.calls.must_pass_in_stack (mode, type)
2034 || *arg_words + words > max))
2037 *arg_words += words;
2041 /* Return an RTL expression containing the register for the given mode,
2042 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2043 if this is an incoming argument to the current function. */
2046 xtensa_function_arg_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2047 const_tree type, bool incoming_p)
2049 int regbase, words, max;
2053 arg_words = &cum->arg_words;
2054 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
2055 max = MAX_ARGS_IN_REGISTERS;
2057 words = (((mode != BLKmode)
2058 ? (int) GET_MODE_SIZE (mode)
2059 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2061 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
2063 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
2064 *arg_words = (*arg_words + align - 1) & -align;
2067 if (*arg_words + words > max)
2070 regno = regbase + *arg_words;
2072 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
2073 cfun->machine->need_a7_copy = true;
2075 return gen_rtx_REG (mode, regno);
2078 /* Implement TARGET_FUNCTION_ARG. */
2081 xtensa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2082 const_tree type, bool named ATTRIBUTE_UNUSED)
2084 return xtensa_function_arg_1 (cum, mode, type, false);
2087 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2090 xtensa_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2091 const_tree type, bool named ATTRIBUTE_UNUSED)
2093 return xtensa_function_arg_1 (cum, mode, type, true);
2097 function_arg_boundary (enum machine_mode mode, tree type)
2099 unsigned int alignment;
2101 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
2102 if (alignment < PARM_BOUNDARY)
2103 alignment = PARM_BOUNDARY;
2104 if (alignment > STACK_BOUNDARY)
2105 alignment = STACK_BOUNDARY;
2111 xtensa_return_in_msb (const_tree valtype)
2113 return (TARGET_BIG_ENDIAN
2114 && AGGREGATE_TYPE_P (valtype)
2115 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
2120 xtensa_option_override (void)
2123 enum machine_mode mode;
2125 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
2126 error ("boolean registers required for the floating-point option");
2128 /* Set up array giving whether a given register can hold a given mode. */
2129 for (mode = VOIDmode;
2130 mode != MAX_MACHINE_MODE;
2131 mode = (enum machine_mode) ((int) mode + 1))
2133 int size = GET_MODE_SIZE (mode);
2134 enum mode_class mclass = GET_MODE_CLASS (mode);
2136 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2140 if (ACC_REG_P (regno))
2141 temp = (TARGET_MAC16
2142 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD));
2143 else if (GP_REG_P (regno))
2144 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
2145 else if (FP_REG_P (regno))
2146 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
2147 else if (BR_REG_P (regno))
2148 temp = (TARGET_BOOLEANS && (mode == CCmode));
2152 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
2156 init_machine_status = xtensa_init_machine_status;
2158 /* Check PIC settings. PIC is only supported when using L32R
2159 instructions, and some targets need to always use PIC. */
2160 if (flag_pic && TARGET_CONST16)
2161 error ("-f%s is not supported with CONST16 instructions",
2162 (flag_pic > 1 ? "PIC" : "pic"));
2163 else if (TARGET_FORCE_NO_PIC)
2165 else if (XTENSA_ALWAYS_PIC)
2168 error ("PIC is required but not supported with CONST16 instructions");
2171 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2174 if (flag_pic && !flag_pie)
2177 /* Hot/cold partitioning does not work on this architecture, because of
2178 constant pools (the load instruction cannot necessarily reach that far).
2179 Therefore disable it on this architecture. */
2180 if (flag_reorder_blocks_and_partition)
2182 flag_reorder_blocks_and_partition = 0;
2183 flag_reorder_blocks = 1;
2187 /* A C compound statement to output to stdio stream STREAM the
2188 assembler syntax for an instruction operand X. X is an RTL
2191 CODE is a value that can be used to specify one of several ways
2192 of printing the operand. It is used when identical operands
2193 must be printed differently depending on the context. CODE
2194 comes from the '%' specification that was used to request
2195 printing of the operand. If the specification was just '%DIGIT'
2196 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2197 is the ASCII code for LTR.
2199 If X is a register, this macro should print the register's name.
2200 The names can be found in an array 'reg_names' whose type is
2201 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2203 When the machine description has a specification '%PUNCT' (a '%'
2204 followed by a punctuation character), this macro is called with
2205 a null pointer for X and the punctuation character for CODE.
2207 'a', 'c', 'l', and 'n' are reserved.
2209 The Xtensa specific codes are:
2211 'd' CONST_INT, print as signed decimal
2212 'x' CONST_INT, print as signed hexadecimal
2213 'K' CONST_INT, print number of bits in mask for EXTUI
2214 'R' CONST_INT, print (X & 0x1f)
2215 'L' CONST_INT, print ((32 - X) & 0x1f)
2216 'D' REG, print second register of double-word register operand
2217 'N' MEM, print address of next word following a memory operand
2218 'v' MEM, if memory reference is volatile, output a MEMW before it
2219 't' any constant, add "@h" suffix for top 16 bits
2220 'b' any constant, add "@l" suffix for bottom 16 bits
2224 printx (FILE *file, signed int val)
2226 /* Print a hexadecimal value in a nice way. */
2227 if ((val > -0xa) && (val < 0xa))
2228 fprintf (file, "%d", val);
2230 fprintf (file, "-0x%x", -val);
2232 fprintf (file, "0x%x", val);
2237 print_operand (FILE *file, rtx x, int letter)
2240 error ("PRINT_OPERAND null pointer");
2245 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2246 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
2248 output_operand_lossage ("invalid %%D value");
2252 if (GET_CODE (x) == MEM)
2254 /* For a volatile memory reference, emit a MEMW before the
2256 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2257 fprintf (file, "memw\n\t");
2260 output_operand_lossage ("invalid %%v value");
2264 if (GET_CODE (x) == MEM
2265 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2267 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2268 output_address (XEXP (x, 0));
2271 output_operand_lossage ("invalid %%N value");
2275 if (GET_CODE (x) == CONST_INT)
2278 unsigned val = INTVAL (x);
2284 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2285 fatal_insn ("invalid mask", x);
2287 fprintf (file, "%d", num_bits);
2290 output_operand_lossage ("invalid %%K value");
2294 if (GET_CODE (x) == CONST_INT)
2295 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2297 output_operand_lossage ("invalid %%L value");
2301 if (GET_CODE (x) == CONST_INT)
2302 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2304 output_operand_lossage ("invalid %%R value");
2308 if (GET_CODE (x) == CONST_INT)
2309 printx (file, INTVAL (x));
2311 output_operand_lossage ("invalid %%x value");
2315 if (GET_CODE (x) == CONST_INT)
2316 fprintf (file, "%ld", INTVAL (x));
2318 output_operand_lossage ("invalid %%d value");
2323 if (GET_CODE (x) == CONST_INT)
2325 printx (file, INTVAL (x));
2326 fputs (letter == 't' ? "@h" : "@l", file);
2328 else if (GET_CODE (x) == CONST_DOUBLE)
2331 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2332 if (GET_MODE (x) == SFmode)
2335 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2336 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2339 output_operand_lossage ("invalid %%t/%%b value");
2341 else if (GET_CODE (x) == CONST)
2343 /* X must be a symbolic constant on ELF. Write an expression
2344 suitable for 'const16' that sets the high or low 16 bits. */
2345 if (GET_CODE (XEXP (x, 0)) != PLUS
2346 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2347 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2348 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2349 output_operand_lossage ("invalid %%t/%%b value");
2350 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2351 fputs (letter == 't' ? "@h" : "@l", file);
2352 /* There must be a non-alphanumeric character between 'h' or 'l'
2353 and the number. The '-' is added by print_operand() already. */
2354 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2356 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2360 output_addr_const (file, x);
2361 fputs (letter == 't' ? "@h" : "@l", file);
2366 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2367 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2368 else if (GET_CODE (x) == MEM)
2369 output_address (XEXP (x, 0));
2370 else if (GET_CODE (x) == CONST_INT)
2371 fprintf (file, "%ld", INTVAL (x));
2373 output_addr_const (file, x);
2378 /* A C compound statement to output to stdio stream STREAM the
2379 assembler syntax for an instruction operand that is a memory
2380 reference whose address is ADDR. ADDR is an RTL expression. */
2383 print_operand_address (FILE *file, rtx addr)
2386 error ("PRINT_OPERAND_ADDRESS, null pointer");
2388 switch (GET_CODE (addr))
2391 fatal_insn ("invalid address", addr);
2395 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2401 rtx offset = (rtx)0;
2402 rtx arg0 = XEXP (addr, 0);
2403 rtx arg1 = XEXP (addr, 1);
2405 if (GET_CODE (arg0) == REG)
2410 else if (GET_CODE (arg1) == REG)
2416 fatal_insn ("no register in address", addr);
2418 if (CONSTANT_P (offset))
2420 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2421 output_addr_const (file, offset);
2424 fatal_insn ("address offset not a constant", addr);
2432 output_addr_const (file, addr);
2439 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2441 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2443 switch (XINT (x, 1))
2446 output_addr_const (fp, XVECEXP (x, 0, 0));
2447 fputs ("@TPOFF", fp);
2450 output_addr_const (fp, XVECEXP (x, 0, 0));
2451 fputs ("@DTPOFF", fp);
2456 output_addr_const (fp, XVECEXP (x, 0, 0));
2470 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2477 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2479 switch (GET_MODE_CLASS (mode))
2482 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2484 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2488 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2489 if (HOST_BITS_PER_LONG > 32)
2490 value_long[0] &= 0xffffffff;
2491 fprintf (file, "0x%08lx\n", value_long[0]);
2495 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2496 if (HOST_BITS_PER_LONG > 32)
2498 value_long[0] &= 0xffffffff;
2499 value_long[1] &= 0xffffffff;
2501 fprintf (file, "0x%08lx, 0x%08lx\n",
2502 value_long[0], value_long[1]);
2512 case MODE_PARTIAL_INT:
2513 size = GET_MODE_SIZE (mode);
2517 output_addr_const (file, x);
2522 split_double (x, &first, &second);
2523 output_addr_const (file, first);
2525 output_addr_const (file, second);
2540 /* Return the bytes needed to compute the frame pointer from the current
2543 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2544 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2547 compute_frame_size (int size)
2549 /* Add space for the incoming static chain value. */
2550 if (cfun->static_chain_decl != NULL)
2551 size += (1 * UNITS_PER_WORD);
2553 xtensa_current_frame_size =
2554 XTENSA_STACK_ALIGN (size
2555 + crtl->outgoing_args_size
2556 + (WINDOW_SIZE * UNITS_PER_WORD));
2557 return xtensa_current_frame_size;
2562 xtensa_frame_pointer_required (void)
2564 /* The code to expand builtin_frame_addr and builtin_return_addr
2565 currently uses the hard_frame_pointer instead of frame_pointer.
2566 This seems wrong but maybe it's necessary for other architectures.
2567 This function is derived from the i386 code. */
2569 if (cfun->machine->accesses_prev_frame)
2576 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2577 and the total number of words must be a multiple of 128 bits. */
2578 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2581 xtensa_expand_prologue (void)
2583 HOST_WIDE_INT total_size;
2587 total_size = compute_frame_size (get_frame_size ());
2588 size_rtx = GEN_INT (total_size);
2590 if (total_size < (1 << (12+3)))
2591 insn = emit_insn (gen_entry (size_rtx));
2594 /* Use a8 as a temporary since a0-a7 may be live. */
2595 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2596 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2597 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2598 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2599 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2602 if (frame_pointer_needed)
2604 if (cfun->machine->set_frame_ptr_insn)
2608 push_topmost_sequence ();
2609 first = get_insns ();
2610 pop_topmost_sequence ();
2612 /* For all instructions prior to set_frame_ptr_insn, replace
2613 hard_frame_pointer references with stack_pointer. */
2615 insn != cfun->machine->set_frame_ptr_insn;
2616 insn = NEXT_INSN (insn))
2620 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2621 hard_frame_pointer_rtx,
2623 df_insn_rescan (insn);
2628 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2629 stack_pointer_rtx));
2632 /* Create a note to describe the CFA. Because this is only used to set
2633 DW_AT_frame_base for debug info, don't bother tracking changes through
2634 each instruction in the prologue. It just takes up space. */
2635 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2636 ? hard_frame_pointer_rtx
2637 : stack_pointer_rtx),
2638 plus_constant (stack_pointer_rtx, -total_size));
2639 RTX_FRAME_RELATED_P (insn) = 1;
2640 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx);
2644 /* Clear variables at function end. */
2647 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2648 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2650 xtensa_current_frame_size = 0;
2655 xtensa_return_addr (int count, rtx frame)
2657 rtx result, retaddr, curaddr, label;
2660 retaddr = gen_rtx_REG (Pmode, A0_REG);
2663 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2664 addr = memory_address (Pmode, addr);
2665 retaddr = gen_reg_rtx (Pmode);
2666 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2669 /* The 2 most-significant bits of the return address on Xtensa hold
2670 the register window size. To get the real return address, these
2671 bits must be replaced with the high bits from some address in the
2674 /* Get the 2 high bits of a local label in the code. */
2675 curaddr = gen_reg_rtx (Pmode);
2676 label = gen_label_rtx ();
2678 LABEL_PRESERVE_P (label) = 1;
2679 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2680 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2681 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2683 /* Clear the 2 high bits of the return address. */
2684 result = gen_reg_rtx (Pmode);
2685 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2686 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2688 /* Combine them to get the result. */
2689 emit_insn (gen_iorsi3 (result, result, curaddr));
2694 /* Create the va_list data type.
2696 This structure is set up by __builtin_saveregs. The __va_reg field
2697 points to a stack-allocated region holding the contents of the
2698 incoming argument registers. The __va_ndx field is an index
2699 initialized to the position of the first unnamed (variable)
2700 argument. This same index is also used to address the arguments
2701 passed in memory. Thus, the __va_stk field is initialized to point
2702 to the position of the first argument in memory offset to account
2703 for the arguments passed in registers and to account for the size
2704 of the argument registers not being 16-byte aligned. E.G., there
2705 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2706 for the first stack argument to have the maximal alignment of 16
2707 bytes, so we offset the __va_stk address by 32 bytes so that
2708 __va_stk[32] references the first argument on the stack. */
2711 xtensa_build_builtin_va_list (void)
2713 tree f_stk, f_reg, f_ndx, record, type_decl;
2715 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2716 type_decl = build_decl (BUILTINS_LOCATION,
2717 TYPE_DECL, get_identifier ("__va_list_tag"), record);
2719 f_stk = build_decl (BUILTINS_LOCATION,
2720 FIELD_DECL, get_identifier ("__va_stk"),
2722 f_reg = build_decl (BUILTINS_LOCATION,
2723 FIELD_DECL, get_identifier ("__va_reg"),
2725 f_ndx = build_decl (BUILTINS_LOCATION,
2726 FIELD_DECL, get_identifier ("__va_ndx"),
2729 DECL_FIELD_CONTEXT (f_stk) = record;
2730 DECL_FIELD_CONTEXT (f_reg) = record;
2731 DECL_FIELD_CONTEXT (f_ndx) = record;
2733 TYPE_STUB_DECL (record) = type_decl;
2734 TYPE_NAME (record) = type_decl;
2735 TYPE_FIELDS (record) = f_stk;
2736 DECL_CHAIN (f_stk) = f_reg;
2737 DECL_CHAIN (f_reg) = f_ndx;
2739 layout_type (record);
2744 /* Save the incoming argument registers on the stack. Returns the
2745 address of the saved registers. */
2748 xtensa_builtin_saveregs (void)
2751 int arg_words = crtl->args.info.arg_words;
2752 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2757 /* Allocate the general-purpose register space. */
2758 gp_regs = assign_stack_local
2759 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2760 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2762 /* Now store the incoming registers. */
2763 cfun->machine->need_a7_copy = true;
2764 cfun->machine->vararg_a7 = true;
2765 move_block_from_reg (GP_ARG_FIRST + arg_words,
2766 adjust_address (gp_regs, BLKmode,
2767 arg_words * UNITS_PER_WORD),
2769 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2770 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2772 return XEXP (gp_regs, 0);
2776 /* Implement `va_start' for varargs and stdarg. We look at the
2777 current function to fill in an initial va_list. */
2780 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2788 arg_words = crtl->args.info.arg_words;
2790 f_stk = TYPE_FIELDS (va_list_type_node);
2791 f_reg = DECL_CHAIN (f_stk);
2792 f_ndx = DECL_CHAIN (f_reg);
2794 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2795 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2797 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2800 /* Call __builtin_saveregs; save the result in __va_reg */
2801 u = make_tree (sizetype, expand_builtin_saveregs ());
2802 u = fold_convert (ptr_type_node, u);
2803 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2804 TREE_SIDE_EFFECTS (t) = 1;
2805 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2807 /* Set the __va_stk member to ($arg_ptr - 32). */
2808 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2809 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2810 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2811 TREE_SIDE_EFFECTS (t) = 1;
2812 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2814 /* Set the __va_ndx member. If the first variable argument is on
2815 the stack, adjust __va_ndx by 2 words to account for the extra
2816 alignment offset for __va_stk. */
2817 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2819 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2820 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2821 TREE_SIDE_EFFECTS (t) = 1;
2822 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2826 /* Implement `va_arg'. */
2829 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2830 gimple_seq *post_p ATTRIBUTE_UNUSED)
2835 tree type_size, array, orig_ndx, addr, size, va_size, t;
2836 tree lab_false, lab_over, lab_false2;
2839 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2841 type = build_pointer_type (type);
2843 /* Handle complex values as separate real and imaginary parts. */
2844 if (TREE_CODE (type) == COMPLEX_TYPE)
2846 tree real_part, imag_part;
2848 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2850 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2852 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2855 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2857 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2860 f_stk = TYPE_FIELDS (va_list_type_node);
2861 f_reg = DECL_CHAIN (f_stk);
2862 f_ndx = DECL_CHAIN (f_reg);
2864 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2866 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2868 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2871 type_size = size_in_bytes (type);
2872 va_size = round_up (type_size, UNITS_PER_WORD);
2873 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2876 /* First align __va_ndx if necessary for this arg:
2878 orig_ndx = (AP).__va_ndx;
2879 if (__alignof__ (TYPE) > 4 )
2880 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2881 & -__alignof__ (TYPE)); */
2883 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2885 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2887 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2889 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2890 build_int_cst (integer_type_node, align - 1));
2891 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2892 build_int_cst (integer_type_node, -align));
2893 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2897 /* Increment __va_ndx to point past the argument:
2899 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2901 t = fold_convert (integer_type_node, va_size);
2902 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2903 gimplify_assign (unshare_expr (ndx), t, pre_p);
2906 /* Check if the argument is in registers:
2908 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2909 && !must_pass_in_stack (type))
2910 __array = (AP).__va_reg; */
2912 array = create_tmp_var (ptr_type_node, NULL);
2915 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2917 lab_false = create_artificial_label (UNKNOWN_LOCATION);
2918 lab_over = create_artificial_label (UNKNOWN_LOCATION);
2920 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2921 build_int_cst (integer_type_node,
2922 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2923 t = build3 (COND_EXPR, void_type_node, t,
2924 build1 (GOTO_EXPR, void_type_node, lab_false),
2926 gimplify_and_add (t, pre_p);
2928 gimplify_assign (unshare_expr (array), reg, pre_p);
2930 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2931 gimplify_and_add (t, pre_p);
2933 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2934 gimplify_and_add (t, pre_p);
2938 /* ...otherwise, the argument is on the stack (never split between
2939 registers and the stack -- change __va_ndx if necessary):
2943 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2944 (AP).__va_ndx = 32 + __va_size (TYPE);
2945 __array = (AP).__va_stk;
2948 lab_false2 = create_artificial_label (UNKNOWN_LOCATION);
2950 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
2951 build_int_cst (integer_type_node,
2952 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2953 t = build3 (COND_EXPR, void_type_node, t,
2954 build1 (GOTO_EXPR, void_type_node, lab_false2),
2956 gimplify_and_add (t, pre_p);
2958 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
2959 t = fold_convert (integer_type_node, t);
2960 gimplify_assign (unshare_expr (ndx), t, pre_p);
2962 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2963 gimplify_and_add (t, pre_p);
2965 gimplify_assign (array, stk, pre_p);
2969 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2970 gimplify_and_add (t, pre_p);
2974 /* Given the base array pointer (__array) and index to the subsequent
2975 argument (__va_ndx), find the address:
2977 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2981 The results are endian-dependent because values smaller than one word
2982 are aligned differently. */
2985 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
2987 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
2988 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
2989 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
2990 unshare_expr (type_size));
2994 size = unshare_expr (va_size);
2996 t = fold_convert (sizetype, unshare_expr (ndx));
2997 t = build2 (MINUS_EXPR, sizetype, t, size);
2998 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t);
3000 addr = fold_convert (build_pointer_type (type), addr);
3002 addr = build_va_arg_indirect_ref (addr);
3003 return build_va_arg_indirect_ref (addr);
3011 XTENSA_BUILTIN_UMULSIDI3,
3012 XTENSA_BUILTIN_THREAD_POINTER,
3013 XTENSA_BUILTIN_SET_THREAD_POINTER,
3019 xtensa_init_builtins (void)
3023 ftype = build_function_type_list (unsigned_intDI_type_node,
3024 unsigned_intSI_type_node,
3025 unsigned_intSI_type_node, NULL_TREE);
3027 decl = add_builtin_function ("__builtin_umulsidi3", ftype,
3028 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
3029 "__umulsidi3", NULL_TREE);
3030 TREE_NOTHROW (decl) = 1;
3031 TREE_READONLY (decl) = 1;
3033 if (TARGET_THREADPTR)
3035 ftype = build_function_type (ptr_type_node, void_list_node);
3036 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
3037 XTENSA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
3039 TREE_READONLY (decl) = 1;
3040 TREE_NOTHROW (decl) = 1;
3042 ftype = build_function_type_list (void_type_node, ptr_type_node,
3044 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
3045 XTENSA_BUILTIN_SET_THREAD_POINTER,
3046 BUILT_IN_MD, NULL, NULL_TREE);
3047 TREE_NOTHROW (decl) = 1;
3053 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
3054 bool ignore ATTRIBUTE_UNUSED)
3056 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3061 case XTENSA_BUILTIN_UMULSIDI3:
3064 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
3065 || TARGET_MUL32_HIGH)
3066 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
3067 fold_convert (unsigned_intDI_type_node, arg0),
3068 fold_convert (unsigned_intDI_type_node, arg1));
3071 case XTENSA_BUILTIN_THREAD_POINTER:
3072 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3076 internal_error ("bad builtin code");
3085 xtensa_expand_builtin (tree exp, rtx target,
3086 rtx subtarget ATTRIBUTE_UNUSED,
3087 enum machine_mode mode ATTRIBUTE_UNUSED,
3090 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
3091 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3096 case XTENSA_BUILTIN_UMULSIDI3:
3097 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3098 __umulsidi3 function when the Xtensa configuration can directly
3099 implement it. If not, just call the function. */
3100 return expand_call (exp, target, ignore);
3102 case XTENSA_BUILTIN_THREAD_POINTER:
3103 if (!target || !register_operand (target, Pmode))
3104 target = gen_reg_rtx (Pmode);
3105 emit_insn (gen_load_tp (target));
3108 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3109 arg = expand_normal (CALL_EXPR_ARG (exp, 0));
3110 if (!register_operand (arg, Pmode))
3111 arg = copy_to_mode_reg (Pmode, arg);
3112 emit_insn (gen_set_tp (arg));
3116 internal_error ("bad builtin code");
3123 xtensa_preferred_reload_class (rtx x, enum reg_class rclass, int isoutput)
3125 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
3128 /* Don't use the stack pointer or hard frame pointer for reloads!
3129 The hard frame pointer would normally be OK except that it may
3130 briefly hold an incoming argument in the prologue, and reload
3131 won't know that it is live because the hard frame pointer is
3132 treated specially. */
3134 if (rclass == AR_REGS || rclass == GR_REGS)
3142 xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
3143 enum machine_mode mode, secondary_reload_info *sri)
3147 if (in_p && constantpool_mem_p (x))
3149 if (rclass == FP_REGS)
3153 sri->icode = CODE_FOR_reloadqi_literal;
3154 else if (mode == HImode)
3155 sri->icode = CODE_FOR_reloadhi_literal;
3158 regno = xt_true_regnum (x);
3159 if (ACC_REG_P (regno))
3160 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS);
3161 if (rclass == ACC_REG)
3162 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
3169 order_regs_for_local_alloc (void)
3171 if (!leaf_function_p ())
3173 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
3174 FIRST_PSEUDO_REGISTER * sizeof (int));
3178 int i, num_arg_regs;
3181 /* Use the AR registers in increasing order (skipping a0 and a1)
3182 but save the incoming argument registers for a last resort. */
3183 num_arg_regs = crtl->args.info.arg_words;
3184 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
3185 num_arg_regs = MAX_ARGS_IN_REGISTERS;
3186 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
3187 reg_alloc_order[nxt++] = i + num_arg_regs;
3188 for (i = 0; i < num_arg_regs; i++)
3189 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
3191 /* List the coprocessor registers in order. */
3192 for (i = 0; i < BR_REG_NUM; i++)
3193 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
3195 /* List the FP registers in order for now. */
3196 for (i = 0; i < 16; i++)
3197 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
3199 /* GCC requires that we list *all* the registers.... */
3200 reg_alloc_order[nxt++] = 0; /* a0 = return address */
3201 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
3202 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
3203 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
3205 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
3210 /* Some Xtensa targets support multiple bss sections. If the section
3211 name ends with ".bss", add SECTION_BSS to the flags. */
3214 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
3216 unsigned int flags = default_section_type_flags (decl, name, reloc);
3219 suffix = strrchr (name, '.');
3220 if (suffix && strcmp (suffix, ".bss") == 0)
3222 if (!decl || (TREE_CODE (decl) == VAR_DECL
3223 && DECL_INITIAL (decl) == NULL_TREE))
3224 flags |= SECTION_BSS; /* @nobits */
3226 warning (0, "only uninitialized variables can be placed in a "
3234 /* The literal pool stays with the function. */
3237 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
3238 rtx x ATTRIBUTE_UNUSED,
3239 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
3241 return function_section (current_function_decl);
3245 /* Compute a (partial) cost for rtx X. Return true if the complete
3246 cost has been computed, and false if subexpressions should be
3247 scanned. In either case, *TOTAL contains the cost result. */
3250 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total,
3251 bool speed ATTRIBUTE_UNUSED)
3259 if (xtensa_simm12b (INTVAL (x)))
3266 if (xtensa_simm8 (INTVAL (x))
3267 || xtensa_simm8x256 (INTVAL (x)))
3274 if (xtensa_mask_immediate (INTVAL (x)))
3281 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
3292 /* No way to tell if X is the 2nd operand so be conservative. */
3295 if (xtensa_simm12b (INTVAL (x)))
3297 else if (TARGET_CONST16)
3298 *total = COSTS_N_INSNS (2);
3307 *total = COSTS_N_INSNS (2);
3314 *total = COSTS_N_INSNS (4);
3322 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3324 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3325 *total = COSTS_N_INSNS (num_words);
3327 *total = COSTS_N_INSNS (2*num_words);
3333 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3337 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3341 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3347 if (GET_MODE (x) == DImode)
3348 *total = COSTS_N_INSNS (2);
3350 *total = COSTS_N_INSNS (1);
3356 if (GET_MODE (x) == DImode)
3357 *total = COSTS_N_INSNS (50);
3359 *total = COSTS_N_INSNS (1);
3364 enum machine_mode xmode = GET_MODE (x);
3365 if (xmode == SFmode)
3366 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3367 else if (xmode == DFmode)
3368 *total = COSTS_N_INSNS (50);
3370 *total = COSTS_N_INSNS (4);
3377 enum machine_mode xmode = GET_MODE (x);
3378 if (xmode == SFmode)
3379 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3380 else if (xmode == DFmode || xmode == DImode)
3381 *total = COSTS_N_INSNS (50);
3383 *total = COSTS_N_INSNS (1);
3388 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3393 enum machine_mode xmode = GET_MODE (x);
3394 if (xmode == SFmode)
3395 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3396 else if (xmode == DFmode)
3397 *total = COSTS_N_INSNS (50);
3398 else if (xmode == DImode)
3399 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3400 else if (TARGET_MUL32)
3401 *total = COSTS_N_INSNS (4);
3402 else if (TARGET_MAC16)
3403 *total = COSTS_N_INSNS (16);
3404 else if (TARGET_MUL16)
3405 *total = COSTS_N_INSNS (12);
3407 *total = COSTS_N_INSNS (50);
3414 enum machine_mode xmode = GET_MODE (x);
3415 if (xmode == SFmode)
3417 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3420 else if (xmode == DFmode)
3422 *total = COSTS_N_INSNS (50);
3431 enum machine_mode xmode = GET_MODE (x);
3432 if (xmode == DImode)
3433 *total = COSTS_N_INSNS (50);
3434 else if (TARGET_DIV32)
3435 *total = COSTS_N_INSNS (32);
3437 *total = COSTS_N_INSNS (50);
3442 if (GET_MODE (x) == SFmode)
3443 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3445 *total = COSTS_N_INSNS (50);
3452 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3457 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3462 *total = COSTS_N_INSNS (1);
3470 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3473 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3475 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3476 > 4 * UNITS_PER_WORD);
3479 /* Worker function for TARGET_FUNCTION_VALUE. */
3482 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3485 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3486 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3487 ? SImode : TYPE_MODE (valtype),
3488 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3491 /* The static chain is passed in memory. Provide rtx giving 'mem'
3492 expressions that denote where they are stored. */
3495 xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
3497 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx;
3498 return gen_frame_mem (Pmode, plus_constant (base, -5 * UNITS_PER_WORD));
3502 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3503 instruction with a minimal stack frame in order to get some free
3504 registers. Once the actual call target is known, the proper stack frame
3505 size is extracted from the ENTRY instruction at the target and the
3506 current frame is adjusted to match. The trampoline then transfers
3507 control to the instruction following the ENTRY at the target. Note:
3508 this assumes that the target begins with an ENTRY instruction. */
3511 xtensa_asm_trampoline_template (FILE *stream)
3513 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3515 fprintf (stream, "\t.begin no-transform\n");
3516 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3520 /* Save the return address. */
3521 fprintf (stream, "\tmov\ta10, a0\n");
3523 /* Use a CALL0 instruction to skip past the constants and in the
3524 process get the PC into A0. This allows PC-relative access to
3525 the constants without relying on L32R. */
3526 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3529 fprintf (stream, "\tj\t.Lskipconsts\n");
3531 fprintf (stream, "\t.align\t4\n");
3532 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3533 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3534 fprintf (stream, ".Lskipconsts:\n");
3536 /* Load the static chain and function address from the trampoline. */
3539 fprintf (stream, "\taddi\ta0, a0, 3\n");
3540 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3541 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3545 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3546 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3549 /* Store the static chain. */
3550 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3552 /* Set the proper stack pointer value. */
3553 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3554 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3555 TARGET_BIG_ENDIAN ? 8 : 12);
3556 fprintf (stream, "\tslli\ta9, a9, 3\n");
3557 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3558 fprintf (stream, "\tsub\ta9, sp, a9\n");
3559 fprintf (stream, "\tmovsp\tsp, a9\n");
3562 /* Restore the return address. */
3563 fprintf (stream, "\tmov\ta0, a10\n");
3565 /* Jump to the instruction following the ENTRY. */
3566 fprintf (stream, "\taddi\ta8, a8, 3\n");
3567 fprintf (stream, "\tjx\ta8\n");
3569 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3571 fprintf (stream, "\t.byte\t0\n");
3573 fprintf (stream, "\tnop\n");
3575 fprintf (stream, "\t.end no-transform\n");
3579 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
3581 rtx func = XEXP (DECL_RTL (fndecl), 0);
3582 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3583 int chain_off = use_call0 ? 12 : 8;
3584 int func_off = use_call0 ? 16 : 12;
3586 emit_block_move (m_tramp, assemble_trampoline_template (),
3587 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3589 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain);
3590 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func);
3591 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3592 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
3596 #include "gt-xtensa.h"