1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs {
67 /* Integer signed load */
70 /* Integer zeroed load */
76 /* fmov, fneg, fabs */
80 const int float_plusminus;
86 const int float_cmove;
92 const int float_div_sf;
95 const int float_div_df;
98 const int float_sqrt_sf;
101 const int float_sqrt_df;
109 /* integer multiply cost for each bit set past the most
110 significant 3, so the formula for multiply cost becomes:
113 highest_bit = highest_clear_bit(rs1);
115 highest_bit = highest_set_bit(rs1);
118 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
120 A value of zero indicates that the multiply costs is fixed,
122 const int int_mul_bit_factor;
133 /* penalty for shifts, due to scheduling rules etc. */
134 const int shift_penalty;
138 struct processor_costs cypress_costs = {
139 COSTS_N_INSNS (2), /* int load */
140 COSTS_N_INSNS (2), /* int signed load */
141 COSTS_N_INSNS (2), /* int zeroed load */
142 COSTS_N_INSNS (2), /* float load */
143 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
144 COSTS_N_INSNS (5), /* fadd, fsub */
145 COSTS_N_INSNS (1), /* fcmp */
146 COSTS_N_INSNS (1), /* fmov, fmovr */
147 COSTS_N_INSNS (7), /* fmul */
148 COSTS_N_INSNS (37), /* fdivs */
149 COSTS_N_INSNS (37), /* fdivd */
150 COSTS_N_INSNS (63), /* fsqrts */
151 COSTS_N_INSNS (63), /* fsqrtd */
152 COSTS_N_INSNS (1), /* imul */
153 COSTS_N_INSNS (1), /* imulX */
154 0, /* imul bit factor */
155 COSTS_N_INSNS (1), /* idiv */
156 COSTS_N_INSNS (1), /* idivX */
157 COSTS_N_INSNS (1), /* movcc/movr */
158 0, /* shift penalty */
162 struct processor_costs supersparc_costs = {
163 COSTS_N_INSNS (1), /* int load */
164 COSTS_N_INSNS (1), /* int signed load */
165 COSTS_N_INSNS (1), /* int zeroed load */
166 COSTS_N_INSNS (0), /* float load */
167 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
168 COSTS_N_INSNS (3), /* fadd, fsub */
169 COSTS_N_INSNS (3), /* fcmp */
170 COSTS_N_INSNS (1), /* fmov, fmovr */
171 COSTS_N_INSNS (3), /* fmul */
172 COSTS_N_INSNS (6), /* fdivs */
173 COSTS_N_INSNS (9), /* fdivd */
174 COSTS_N_INSNS (12), /* fsqrts */
175 COSTS_N_INSNS (12), /* fsqrtd */
176 COSTS_N_INSNS (4), /* imul */
177 COSTS_N_INSNS (4), /* imulX */
178 0, /* imul bit factor */
179 COSTS_N_INSNS (4), /* idiv */
180 COSTS_N_INSNS (4), /* idivX */
181 COSTS_N_INSNS (1), /* movcc/movr */
182 1, /* shift penalty */
186 struct processor_costs hypersparc_costs = {
187 COSTS_N_INSNS (1), /* int load */
188 COSTS_N_INSNS (1), /* int signed load */
189 COSTS_N_INSNS (1), /* int zeroed load */
190 COSTS_N_INSNS (1), /* float load */
191 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
192 COSTS_N_INSNS (1), /* fadd, fsub */
193 COSTS_N_INSNS (1), /* fcmp */
194 COSTS_N_INSNS (1), /* fmov, fmovr */
195 COSTS_N_INSNS (1), /* fmul */
196 COSTS_N_INSNS (8), /* fdivs */
197 COSTS_N_INSNS (12), /* fdivd */
198 COSTS_N_INSNS (17), /* fsqrts */
199 COSTS_N_INSNS (17), /* fsqrtd */
200 COSTS_N_INSNS (17), /* imul */
201 COSTS_N_INSNS (17), /* imulX */
202 0, /* imul bit factor */
203 COSTS_N_INSNS (17), /* idiv */
204 COSTS_N_INSNS (17), /* idivX */
205 COSTS_N_INSNS (1), /* movcc/movr */
206 0, /* shift penalty */
210 struct processor_costs leon_costs = {
211 COSTS_N_INSNS (1), /* int load */
212 COSTS_N_INSNS (1), /* int signed load */
213 COSTS_N_INSNS (1), /* int zeroed load */
214 COSTS_N_INSNS (1), /* float load */
215 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
216 COSTS_N_INSNS (1), /* fadd, fsub */
217 COSTS_N_INSNS (1), /* fcmp */
218 COSTS_N_INSNS (1), /* fmov, fmovr */
219 COSTS_N_INSNS (1), /* fmul */
220 COSTS_N_INSNS (15), /* fdivs */
221 COSTS_N_INSNS (15), /* fdivd */
222 COSTS_N_INSNS (23), /* fsqrts */
223 COSTS_N_INSNS (23), /* fsqrtd */
224 COSTS_N_INSNS (5), /* imul */
225 COSTS_N_INSNS (5), /* imulX */
226 0, /* imul bit factor */
227 COSTS_N_INSNS (5), /* idiv */
228 COSTS_N_INSNS (5), /* idivX */
229 COSTS_N_INSNS (1), /* movcc/movr */
230 0, /* shift penalty */
234 struct processor_costs sparclet_costs = {
235 COSTS_N_INSNS (3), /* int load */
236 COSTS_N_INSNS (3), /* int signed load */
237 COSTS_N_INSNS (1), /* int zeroed load */
238 COSTS_N_INSNS (1), /* float load */
239 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
240 COSTS_N_INSNS (1), /* fadd, fsub */
241 COSTS_N_INSNS (1), /* fcmp */
242 COSTS_N_INSNS (1), /* fmov, fmovr */
243 COSTS_N_INSNS (1), /* fmul */
244 COSTS_N_INSNS (1), /* fdivs */
245 COSTS_N_INSNS (1), /* fdivd */
246 COSTS_N_INSNS (1), /* fsqrts */
247 COSTS_N_INSNS (1), /* fsqrtd */
248 COSTS_N_INSNS (5), /* imul */
249 COSTS_N_INSNS (5), /* imulX */
250 0, /* imul bit factor */
251 COSTS_N_INSNS (5), /* idiv */
252 COSTS_N_INSNS (5), /* idivX */
253 COSTS_N_INSNS (1), /* movcc/movr */
254 0, /* shift penalty */
258 struct processor_costs ultrasparc_costs = {
259 COSTS_N_INSNS (2), /* int load */
260 COSTS_N_INSNS (3), /* int signed load */
261 COSTS_N_INSNS (2), /* int zeroed load */
262 COSTS_N_INSNS (2), /* float load */
263 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
264 COSTS_N_INSNS (4), /* fadd, fsub */
265 COSTS_N_INSNS (1), /* fcmp */
266 COSTS_N_INSNS (2), /* fmov, fmovr */
267 COSTS_N_INSNS (4), /* fmul */
268 COSTS_N_INSNS (13), /* fdivs */
269 COSTS_N_INSNS (23), /* fdivd */
270 COSTS_N_INSNS (13), /* fsqrts */
271 COSTS_N_INSNS (23), /* fsqrtd */
272 COSTS_N_INSNS (4), /* imul */
273 COSTS_N_INSNS (4), /* imulX */
274 2, /* imul bit factor */
275 COSTS_N_INSNS (37), /* idiv */
276 COSTS_N_INSNS (68), /* idivX */
277 COSTS_N_INSNS (2), /* movcc/movr */
278 2, /* shift penalty */
282 struct processor_costs ultrasparc3_costs = {
283 COSTS_N_INSNS (2), /* int load */
284 COSTS_N_INSNS (3), /* int signed load */
285 COSTS_N_INSNS (3), /* int zeroed load */
286 COSTS_N_INSNS (2), /* float load */
287 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
288 COSTS_N_INSNS (4), /* fadd, fsub */
289 COSTS_N_INSNS (5), /* fcmp */
290 COSTS_N_INSNS (3), /* fmov, fmovr */
291 COSTS_N_INSNS (4), /* fmul */
292 COSTS_N_INSNS (17), /* fdivs */
293 COSTS_N_INSNS (20), /* fdivd */
294 COSTS_N_INSNS (20), /* fsqrts */
295 COSTS_N_INSNS (29), /* fsqrtd */
296 COSTS_N_INSNS (6), /* imul */
297 COSTS_N_INSNS (6), /* imulX */
298 0, /* imul bit factor */
299 COSTS_N_INSNS (40), /* idiv */
300 COSTS_N_INSNS (71), /* idivX */
301 COSTS_N_INSNS (2), /* movcc/movr */
302 0, /* shift penalty */
306 struct processor_costs niagara_costs = {
307 COSTS_N_INSNS (3), /* int load */
308 COSTS_N_INSNS (3), /* int signed load */
309 COSTS_N_INSNS (3), /* int zeroed load */
310 COSTS_N_INSNS (9), /* float load */
311 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
312 COSTS_N_INSNS (8), /* fadd, fsub */
313 COSTS_N_INSNS (26), /* fcmp */
314 COSTS_N_INSNS (8), /* fmov, fmovr */
315 COSTS_N_INSNS (29), /* fmul */
316 COSTS_N_INSNS (54), /* fdivs */
317 COSTS_N_INSNS (83), /* fdivd */
318 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
319 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
320 COSTS_N_INSNS (11), /* imul */
321 COSTS_N_INSNS (11), /* imulX */
322 0, /* imul bit factor */
323 COSTS_N_INSNS (72), /* idiv */
324 COSTS_N_INSNS (72), /* idivX */
325 COSTS_N_INSNS (1), /* movcc/movr */
326 0, /* shift penalty */
330 struct processor_costs niagara2_costs = {
331 COSTS_N_INSNS (3), /* int load */
332 COSTS_N_INSNS (3), /* int signed load */
333 COSTS_N_INSNS (3), /* int zeroed load */
334 COSTS_N_INSNS (3), /* float load */
335 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
336 COSTS_N_INSNS (6), /* fadd, fsub */
337 COSTS_N_INSNS (6), /* fcmp */
338 COSTS_N_INSNS (6), /* fmov, fmovr */
339 COSTS_N_INSNS (6), /* fmul */
340 COSTS_N_INSNS (19), /* fdivs */
341 COSTS_N_INSNS (33), /* fdivd */
342 COSTS_N_INSNS (19), /* fsqrts */
343 COSTS_N_INSNS (33), /* fsqrtd */
344 COSTS_N_INSNS (5), /* imul */
345 COSTS_N_INSNS (5), /* imulX */
346 0, /* imul bit factor */
347 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
348 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
349 COSTS_N_INSNS (1), /* movcc/movr */
350 0, /* shift penalty */
354 struct processor_costs niagara3_costs = {
355 COSTS_N_INSNS (3), /* int load */
356 COSTS_N_INSNS (3), /* int signed load */
357 COSTS_N_INSNS (3), /* int zeroed load */
358 COSTS_N_INSNS (3), /* float load */
359 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
360 COSTS_N_INSNS (9), /* fadd, fsub */
361 COSTS_N_INSNS (9), /* fcmp */
362 COSTS_N_INSNS (9), /* fmov, fmovr */
363 COSTS_N_INSNS (9), /* fmul */
364 COSTS_N_INSNS (23), /* fdivs */
365 COSTS_N_INSNS (37), /* fdivd */
366 COSTS_N_INSNS (23), /* fsqrts */
367 COSTS_N_INSNS (37), /* fsqrtd */
368 COSTS_N_INSNS (9), /* imul */
369 COSTS_N_INSNS (9), /* imulX */
370 0, /* imul bit factor */
371 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
372 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
373 COSTS_N_INSNS (1), /* movcc/movr */
374 0, /* shift penalty */
377 static const struct processor_costs *sparc_costs = &cypress_costs;
379 #ifdef HAVE_AS_RELAX_OPTION
380 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
381 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
382 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
383 somebody does not branch between the sethi and jmp. */
384 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
386 #define LEAF_SIBCALL_SLOT_RESERVED_P \
387 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
390 /* Vector to say how input registers are mapped to output registers.
391 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
392 eliminate it. You must use -fomit-frame-pointer to get that. */
393 char leaf_reg_remap[] =
394 { 0, 1, 2, 3, 4, 5, 6, 7,
395 -1, -1, -1, -1, -1, -1, 14, -1,
396 -1, -1, -1, -1, -1, -1, -1, -1,
397 8, 9, 10, 11, 12, 13, -1, 15,
399 32, 33, 34, 35, 36, 37, 38, 39,
400 40, 41, 42, 43, 44, 45, 46, 47,
401 48, 49, 50, 51, 52, 53, 54, 55,
402 56, 57, 58, 59, 60, 61, 62, 63,
403 64, 65, 66, 67, 68, 69, 70, 71,
404 72, 73, 74, 75, 76, 77, 78, 79,
405 80, 81, 82, 83, 84, 85, 86, 87,
406 88, 89, 90, 91, 92, 93, 94, 95,
407 96, 97, 98, 99, 100, 101, 102};
409 /* Vector, indexed by hard register number, which contains 1
410 for a register that is allowable in a candidate for leaf
411 function treatment. */
412 char sparc_leaf_regs[] =
413 { 1, 1, 1, 1, 1, 1, 1, 1,
414 0, 0, 0, 0, 0, 0, 1, 0,
415 0, 0, 0, 0, 0, 0, 0, 0,
416 1, 1, 1, 1, 1, 1, 0, 1,
417 1, 1, 1, 1, 1, 1, 1, 1,
418 1, 1, 1, 1, 1, 1, 1, 1,
419 1, 1, 1, 1, 1, 1, 1, 1,
420 1, 1, 1, 1, 1, 1, 1, 1,
421 1, 1, 1, 1, 1, 1, 1, 1,
422 1, 1, 1, 1, 1, 1, 1, 1,
423 1, 1, 1, 1, 1, 1, 1, 1,
424 1, 1, 1, 1, 1, 1, 1, 1,
425 1, 1, 1, 1, 1, 1, 1};
427 struct GTY(()) machine_function
429 /* Size of the frame of the function. */
430 HOST_WIDE_INT frame_size;
432 /* Size of the frame of the function minus the register window save area
433 and the outgoing argument area. */
434 HOST_WIDE_INT apparent_frame_size;
436 /* Register we pretend the frame pointer is allocated to. Normally, this
437 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
438 record "offset" separately as it may be too big for (reg + disp). */
440 HOST_WIDE_INT frame_base_offset;
442 /* Some local-dynamic TLS symbol name. */
443 const char *some_ld_name;
445 /* Number of global or FP registers to be saved (as 4-byte quantities). */
446 int n_global_fp_regs;
448 /* True if the current function is leaf and uses only leaf regs,
449 so that the SPARC leaf function optimization can be applied.
450 Private version of current_function_uses_only_leaf_regs, see
451 sparc_expand_prologue for the rationale. */
454 /* True if the prologue saves local or in registers. */
455 bool save_local_in_regs_p;
457 /* True if the data calculated by sparc_expand_prologue are valid. */
458 bool prologue_data_valid_p;
461 #define sparc_frame_size cfun->machine->frame_size
462 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
463 #define sparc_frame_base_reg cfun->machine->frame_base_reg
464 #define sparc_frame_base_offset cfun->machine->frame_base_offset
465 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
466 #define sparc_leaf_function_p cfun->machine->leaf_function_p
467 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
468 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
470 /* 1 if the next opcode is to be specially indented. */
471 int sparc_indent_opcode = 0;
473 static void sparc_option_override (void);
474 static void sparc_init_modes (void);
475 static void scan_record_type (const_tree, int *, int *, int *);
476 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
477 const_tree, bool, bool, int *, int *);
479 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
480 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
482 static void sparc_emit_set_const32 (rtx, rtx);
483 static void sparc_emit_set_const64 (rtx, rtx);
484 static void sparc_output_addr_vec (rtx);
485 static void sparc_output_addr_diff_vec (rtx);
486 static void sparc_output_deferred_case_vectors (void);
487 static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
488 static bool sparc_legitimate_constant_p (enum machine_mode, rtx);
489 static rtx sparc_builtin_saveregs (void);
490 static int epilogue_renumber (rtx *, int);
491 static bool sparc_assemble_integer (rtx, unsigned int, int);
492 static int set_extends (rtx);
493 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
494 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
495 #ifdef TARGET_SOLARIS
496 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
497 tree) ATTRIBUTE_UNUSED;
499 static int sparc_adjust_cost (rtx, rtx, rtx, int);
500 static int sparc_issue_rate (void);
501 static void sparc_sched_init (FILE *, int, int);
502 static int sparc_use_sched_lookahead (void);
504 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
505 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
506 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
507 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
508 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
510 static bool sparc_function_ok_for_sibcall (tree, tree);
511 static void sparc_init_libfuncs (void);
512 static void sparc_init_builtins (void);
513 static void sparc_vis_init_builtins (void);
514 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
515 static tree sparc_fold_builtin (tree, int, tree *, bool);
516 static int sparc_vis_mul8x16 (int, int);
517 static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
518 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
519 HOST_WIDE_INT, tree);
520 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
521 HOST_WIDE_INT, const_tree);
522 static void sparc_reorg (void);
523 static struct machine_function * sparc_init_machine_status (void);
524 static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
525 static rtx sparc_tls_get_addr (void);
526 static rtx sparc_tls_got (void);
527 static const char *get_some_local_dynamic_name (void);
528 static int get_some_local_dynamic_name_1 (rtx *, void *);
529 static int sparc_register_move_cost (enum machine_mode,
530 reg_class_t, reg_class_t);
531 static bool sparc_rtx_costs (rtx, int, int, int, int *, bool);
532 static rtx sparc_function_value (const_tree, const_tree, bool);
533 static rtx sparc_libcall_value (enum machine_mode, const_rtx);
534 static bool sparc_function_value_regno_p (const unsigned int);
535 static rtx sparc_struct_value_rtx (tree, int);
536 static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
537 int *, const_tree, int);
538 static bool sparc_return_in_memory (const_tree, const_tree);
539 static bool sparc_strict_argument_naming (cumulative_args_t);
540 static void sparc_va_start (tree, rtx);
541 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
542 static bool sparc_vector_mode_supported_p (enum machine_mode);
543 static bool sparc_tls_referenced_p (rtx);
544 static rtx sparc_legitimize_tls_address (rtx);
545 static rtx sparc_legitimize_pic_address (rtx, rtx);
546 static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
547 static rtx sparc_delegitimize_address (rtx);
548 static bool sparc_mode_dependent_address_p (const_rtx);
549 static bool sparc_pass_by_reference (cumulative_args_t,
550 enum machine_mode, const_tree, bool);
551 static void sparc_function_arg_advance (cumulative_args_t,
552 enum machine_mode, const_tree, bool);
553 static rtx sparc_function_arg_1 (cumulative_args_t,
554 enum machine_mode, const_tree, bool, bool);
555 static rtx sparc_function_arg (cumulative_args_t,
556 enum machine_mode, const_tree, bool);
557 static rtx sparc_function_incoming_arg (cumulative_args_t,
558 enum machine_mode, const_tree, bool);
559 static unsigned int sparc_function_arg_boundary (enum machine_mode,
561 static int sparc_arg_partial_bytes (cumulative_args_t,
562 enum machine_mode, tree, bool);
563 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
564 static void sparc_file_end (void);
565 static bool sparc_frame_pointer_required (void);
566 static bool sparc_can_eliminate (const int, const int);
567 static rtx sparc_builtin_setjmp_frame_value (void);
568 static void sparc_conditional_register_usage (void);
569 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
570 static const char *sparc_mangle_type (const_tree);
572 static void sparc_trampoline_init (rtx, tree, rtx);
573 static enum machine_mode sparc_preferred_simd_mode (enum machine_mode);
574 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
575 static bool sparc_print_operand_punct_valid_p (unsigned char);
576 static void sparc_print_operand (FILE *, rtx, int);
577 static void sparc_print_operand_address (FILE *, rtx);
578 static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t,
579 enum machine_mode, secondary_reload_info *);
581 #ifdef SUBTARGET_ATTRIBUTE_TABLE
582 /* Table of valid machine attributes. */
583 static const struct attribute_spec sparc_attribute_table[] =
585 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
587 SUBTARGET_ATTRIBUTE_TABLE,
588 { NULL, 0, 0, false, false, false, NULL, false }
592 /* Option handling. */
595 enum cmodel sparc_cmodel;
597 char sparc_hard_reg_printed[8];
599 /* Initialize the GCC target structure. */
601 /* The default is to use .half rather than .short for aligned HI objects. */
602 #undef TARGET_ASM_ALIGNED_HI_OP
603 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
605 #undef TARGET_ASM_UNALIGNED_HI_OP
606 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
607 #undef TARGET_ASM_UNALIGNED_SI_OP
608 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
609 #undef TARGET_ASM_UNALIGNED_DI_OP
610 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
612 /* The target hook has to handle DI-mode values. */
613 #undef TARGET_ASM_INTEGER
614 #define TARGET_ASM_INTEGER sparc_assemble_integer
616 #undef TARGET_ASM_FUNCTION_PROLOGUE
617 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
618 #undef TARGET_ASM_FUNCTION_EPILOGUE
619 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
621 #undef TARGET_SCHED_ADJUST_COST
622 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
623 #undef TARGET_SCHED_ISSUE_RATE
624 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
625 #undef TARGET_SCHED_INIT
626 #define TARGET_SCHED_INIT sparc_sched_init
627 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
628 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
630 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
631 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
633 #undef TARGET_INIT_LIBFUNCS
634 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
635 #undef TARGET_INIT_BUILTINS
636 #define TARGET_INIT_BUILTINS sparc_init_builtins
638 #undef TARGET_LEGITIMIZE_ADDRESS
639 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
640 #undef TARGET_DELEGITIMIZE_ADDRESS
641 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
642 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
643 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
645 #undef TARGET_EXPAND_BUILTIN
646 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
647 #undef TARGET_FOLD_BUILTIN
648 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
651 #undef TARGET_HAVE_TLS
652 #define TARGET_HAVE_TLS true
655 #undef TARGET_CANNOT_FORCE_CONST_MEM
656 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
658 #undef TARGET_ASM_OUTPUT_MI_THUNK
659 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
660 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
661 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
663 #undef TARGET_MACHINE_DEPENDENT_REORG
664 #define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
666 #undef TARGET_RTX_COSTS
667 #define TARGET_RTX_COSTS sparc_rtx_costs
668 #undef TARGET_ADDRESS_COST
669 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
670 #undef TARGET_REGISTER_MOVE_COST
671 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
673 #undef TARGET_PROMOTE_FUNCTION_MODE
674 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
676 #undef TARGET_FUNCTION_VALUE
677 #define TARGET_FUNCTION_VALUE sparc_function_value
678 #undef TARGET_LIBCALL_VALUE
679 #define TARGET_LIBCALL_VALUE sparc_libcall_value
680 #undef TARGET_FUNCTION_VALUE_REGNO_P
681 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
683 #undef TARGET_STRUCT_VALUE_RTX
684 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
685 #undef TARGET_RETURN_IN_MEMORY
686 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
687 #undef TARGET_MUST_PASS_IN_STACK
688 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
689 #undef TARGET_PASS_BY_REFERENCE
690 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
691 #undef TARGET_ARG_PARTIAL_BYTES
692 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
693 #undef TARGET_FUNCTION_ARG_ADVANCE
694 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
695 #undef TARGET_FUNCTION_ARG
696 #define TARGET_FUNCTION_ARG sparc_function_arg
697 #undef TARGET_FUNCTION_INCOMING_ARG
698 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
699 #undef TARGET_FUNCTION_ARG_BOUNDARY
700 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
702 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
703 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
704 #undef TARGET_STRICT_ARGUMENT_NAMING
705 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
707 #undef TARGET_EXPAND_BUILTIN_VA_START
708 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
709 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
710 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
712 #undef TARGET_VECTOR_MODE_SUPPORTED_P
713 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
715 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
716 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
718 #ifdef SUBTARGET_INSERT_ATTRIBUTES
719 #undef TARGET_INSERT_ATTRIBUTES
720 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
723 #ifdef SUBTARGET_ATTRIBUTE_TABLE
724 #undef TARGET_ATTRIBUTE_TABLE
725 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
728 #undef TARGET_RELAXED_ORDERING
729 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
731 #undef TARGET_OPTION_OVERRIDE
732 #define TARGET_OPTION_OVERRIDE sparc_option_override
734 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
735 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
736 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
739 #undef TARGET_ASM_FILE_END
740 #define TARGET_ASM_FILE_END sparc_file_end
742 #undef TARGET_FRAME_POINTER_REQUIRED
743 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
745 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
746 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
748 #undef TARGET_CAN_ELIMINATE
749 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
751 #undef TARGET_PREFERRED_RELOAD_CLASS
752 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
754 #undef TARGET_SECONDARY_RELOAD
755 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
757 #undef TARGET_CONDITIONAL_REGISTER_USAGE
758 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
760 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
761 #undef TARGET_MANGLE_TYPE
762 #define TARGET_MANGLE_TYPE sparc_mangle_type
765 #undef TARGET_LEGITIMATE_ADDRESS_P
766 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
768 #undef TARGET_LEGITIMATE_CONSTANT_P
769 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
771 #undef TARGET_TRAMPOLINE_INIT
772 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
774 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
775 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
776 #undef TARGET_PRINT_OPERAND
777 #define TARGET_PRINT_OPERAND sparc_print_operand
778 #undef TARGET_PRINT_OPERAND_ADDRESS
779 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
781 struct gcc_target targetm = TARGET_INITIALIZER;
784 dump_target_flag_bits (const int flags)
786 if (flags & MASK_64BIT)
787 fprintf (stderr, "64BIT ");
788 if (flags & MASK_APP_REGS)
789 fprintf (stderr, "APP_REGS ");
790 if (flags & MASK_FASTER_STRUCTS)
791 fprintf (stderr, "FASTER_STRUCTS ");
792 if (flags & MASK_FLAT)
793 fprintf (stderr, "FLAT ");
794 if (flags & MASK_FMAF)
795 fprintf (stderr, "FMAF ");
796 if (flags & MASK_FPU)
797 fprintf (stderr, "FPU ");
798 if (flags & MASK_HARD_QUAD)
799 fprintf (stderr, "HARD_QUAD ");
800 if (flags & MASK_POPC)
801 fprintf (stderr, "POPC ");
802 if (flags & MASK_PTR64)
803 fprintf (stderr, "PTR64 ");
804 if (flags & MASK_STACK_BIAS)
805 fprintf (stderr, "STACK_BIAS ");
806 if (flags & MASK_UNALIGNED_DOUBLES)
807 fprintf (stderr, "UNALIGNED_DOUBLES ");
808 if (flags & MASK_V8PLUS)
809 fprintf (stderr, "V8PLUS ");
810 if (flags & MASK_VIS)
811 fprintf (stderr, "VIS ");
812 if (flags & MASK_VIS2)
813 fprintf (stderr, "VIS2 ");
814 if (flags & MASK_VIS3)
815 fprintf (stderr, "VIS3 ");
816 if (flags & MASK_DEPRECATED_V8_INSNS)
817 fprintf (stderr, "DEPRECATED_V8_INSNS ");
818 if (flags & MASK_LITTLE_ENDIAN)
819 fprintf (stderr, "LITTLE_ENDIAN ");
820 if (flags & MASK_SPARCLET)
821 fprintf (stderr, "SPARCLET ");
822 if (flags & MASK_SPARCLITE)
823 fprintf (stderr, "SPARCLITE ");
825 fprintf (stderr, "V8 ");
827 fprintf (stderr, "V9 ");
831 dump_target_flags (const char *prefix, const int flags)
833 fprintf (stderr, "%s: (%08x) [ ", prefix, flags);
834 dump_target_flag_bits (flags);
835 fprintf(stderr, "]\n");
838 /* Validate and override various options, and do some machine dependent
842 sparc_option_override (void)
844 static struct code_model {
845 const char *const name;
846 const enum cmodel value;
847 } const cmodels[] = {
849 { "medlow", CM_MEDLOW },
850 { "medmid", CM_MEDMID },
851 { "medany", CM_MEDANY },
852 { "embmedany", CM_EMBMEDANY },
853 { NULL, (enum cmodel) 0 }
855 const struct code_model *cmodel;
856 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
857 static struct cpu_default {
859 const enum processor_type processor;
860 } const cpu_default[] = {
861 /* There must be one entry here for each TARGET_CPU value. */
862 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
863 { TARGET_CPU_v8, PROCESSOR_V8 },
864 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
865 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
866 { TARGET_CPU_leon, PROCESSOR_LEON },
867 { TARGET_CPU_sparclite, PROCESSOR_F930 },
868 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
869 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
870 { TARGET_CPU_v9, PROCESSOR_V9 },
871 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
872 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
873 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
874 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
875 { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 },
876 { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 },
879 const struct cpu_default *def;
880 /* Table of values for -m{cpu,tune}=. This must match the order of
881 the PROCESSOR_* enumeration. */
882 static struct cpu_table {
883 const char *const name;
886 } const cpu_table[] = {
887 { "v7", MASK_ISA, 0 },
888 { "cypress", MASK_ISA, 0 },
889 { "v8", MASK_ISA, MASK_V8 },
890 /* TI TMS390Z55 supersparc */
891 { "supersparc", MASK_ISA, MASK_V8 },
892 { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
894 { "leon", MASK_ISA, MASK_V8|MASK_FPU },
895 { "sparclite", MASK_ISA, MASK_SPARCLITE },
896 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
897 { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
898 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
899 { "f934", MASK_ISA, MASK_SPARCLITE|MASK_FPU },
900 { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
901 { "sparclet", MASK_ISA, MASK_SPARCLET },
903 { "tsc701", MASK_ISA, MASK_SPARCLET },
904 { "v9", MASK_ISA, MASK_V9 },
905 /* UltraSPARC I, II, IIi */
906 { "ultrasparc", MASK_ISA,
907 /* Although insns using %y are deprecated, it is a clear win. */
908 MASK_V9|MASK_DEPRECATED_V8_INSNS },
910 /* ??? Check if %y issue still holds true. */
911 { "ultrasparc3", MASK_ISA,
912 MASK_V9|MASK_DEPRECATED_V8_INSNS|MASK_VIS2 },
914 { "niagara", MASK_ISA,
915 MASK_V9|MASK_DEPRECATED_V8_INSNS },
917 { "niagara2", MASK_ISA,
918 MASK_V9|MASK_POPC|MASK_VIS2 },
920 { "niagara3", MASK_ISA,
921 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
923 { "niagara4", MASK_ISA,
924 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
926 const struct cpu_table *cpu;
930 if (sparc_debug_string != NULL)
935 p = ASTRDUP (sparc_debug_string);
936 while ((q = strtok (p, ",")) != NULL)
950 if (! strcmp (q, "all"))
951 mask = MASK_DEBUG_ALL;
952 else if (! strcmp (q, "options"))
953 mask = MASK_DEBUG_OPTIONS;
955 error ("unknown -mdebug-%s switch", q);
958 sparc_debug &= ~mask;
964 if (TARGET_DEBUG_OPTIONS)
966 dump_target_flags("Initial target_flags", target_flags);
967 dump_target_flags("target_flags_explicit", target_flags_explicit);
970 #ifdef SUBTARGET_OVERRIDE_OPTIONS
971 SUBTARGET_OVERRIDE_OPTIONS;
974 #ifndef SPARC_BI_ARCH
975 /* Check for unsupported architecture size. */
976 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
977 error ("%s is not supported by this configuration",
978 DEFAULT_ARCH32_P ? "-m64" : "-m32");
981 /* We force all 64bit archs to use 128 bit long double */
982 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
984 error ("-mlong-double-64 not allowed with -m64");
985 target_flags |= MASK_LONG_DOUBLE_128;
988 /* Code model selection. */
989 sparc_cmodel = SPARC_DEFAULT_CMODEL;
993 sparc_cmodel = CM_32;
996 if (sparc_cmodel_string != NULL)
1000 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
1001 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
1003 if (cmodel->name == NULL)
1004 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
1006 sparc_cmodel = cmodel->value;
1009 error ("-mcmodel= is not supported on 32 bit systems");
1012 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1013 for (i = 8; i < 16; i++)
1014 if (!call_used_regs [i])
1016 error ("-fcall-saved-REG is not supported for out registers");
1017 call_used_regs [i] = 1;
1020 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
1022 /* Set the default CPU. */
1023 if (!global_options_set.x_sparc_cpu_and_features)
1025 for (def = &cpu_default[0]; def->cpu != -1; ++def)
1026 if (def->cpu == TARGET_CPU_DEFAULT)
1028 gcc_assert (def->cpu != -1);
1029 sparc_cpu_and_features = def->processor;
1032 if ((target_flags & MASK_V8PLUS)
1033 && sparc_cpu_and_features < PROCESSOR_V9)
1034 sparc_cpu_and_features = PROCESSOR_V9;
1036 if (!global_options_set.x_sparc_cpu)
1037 sparc_cpu = sparc_cpu_and_features;
1039 cpu = &cpu_table[(int) sparc_cpu_and_features];
1041 if (TARGET_DEBUG_OPTIONS)
1043 fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name);
1044 fprintf (stderr, "sparc_cpu: %s\n",
1045 cpu_table[(int) sparc_cpu].name);
1046 dump_target_flags ("cpu->disable", cpu->disable);
1047 dump_target_flags ("cpu->enable", cpu->enable);
1050 target_flags &= ~cpu->disable;
1051 target_flags |= (cpu->enable
1052 #ifndef HAVE_AS_FMAF_HPC_VIS3
1053 & ~(MASK_FMAF | MASK_VIS3)
1057 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1058 the processor default. */
1059 if (target_flags_explicit & MASK_FPU)
1060 target_flags = (target_flags & ~MASK_FPU) | fpu;
1062 /* -mvis2 implies -mvis */
1064 target_flags |= MASK_VIS;
1066 /* -mvis3 implies -mvis2 and -mvis */
1068 target_flags |= MASK_VIS2 | MASK_VIS;
1070 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
1072 target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_FMAF);
1074 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1076 -m64 also implies v9. */
1077 if (TARGET_VIS || TARGET_ARCH64)
1079 target_flags |= MASK_V9;
1080 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
1083 /* -mvis also implies -mv8plus on 32-bit */
1084 if (TARGET_VIS && ! TARGET_ARCH64)
1085 target_flags |= MASK_V8PLUS;
1087 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1088 if (TARGET_V9 && TARGET_ARCH32)
1089 target_flags |= MASK_DEPRECATED_V8_INSNS;
1091 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1092 if (! TARGET_V9 || TARGET_ARCH64)
1093 target_flags &= ~MASK_V8PLUS;
1095 /* Don't use stack biasing in 32 bit mode. */
1097 target_flags &= ~MASK_STACK_BIAS;
1099 /* Supply a default value for align_functions. */
1100 if (align_functions == 0
1101 && (sparc_cpu == PROCESSOR_ULTRASPARC
1102 || sparc_cpu == PROCESSOR_ULTRASPARC3
1103 || sparc_cpu == PROCESSOR_NIAGARA
1104 || sparc_cpu == PROCESSOR_NIAGARA2
1105 || sparc_cpu == PROCESSOR_NIAGARA3
1106 || sparc_cpu == PROCESSOR_NIAGARA4))
1107 align_functions = 32;
1109 /* Validate PCC_STRUCT_RETURN. */
1110 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
1111 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
1113 /* Only use .uaxword when compiling for a 64-bit target. */
1115 targetm.asm_out.unaligned_op.di = NULL;
1117 /* Do various machine dependent initializations. */
1118 sparc_init_modes ();
1120 /* Set up function hooks. */
1121 init_machine_status = sparc_init_machine_status;
1126 case PROCESSOR_CYPRESS:
1127 sparc_costs = &cypress_costs;
1130 case PROCESSOR_SPARCLITE:
1131 case PROCESSOR_SUPERSPARC:
1132 sparc_costs = &supersparc_costs;
1134 case PROCESSOR_F930:
1135 case PROCESSOR_F934:
1136 case PROCESSOR_HYPERSPARC:
1137 case PROCESSOR_SPARCLITE86X:
1138 sparc_costs = &hypersparc_costs;
1140 case PROCESSOR_LEON:
1141 sparc_costs = &leon_costs;
1143 case PROCESSOR_SPARCLET:
1144 case PROCESSOR_TSC701:
1145 sparc_costs = &sparclet_costs;
1148 case PROCESSOR_ULTRASPARC:
1149 sparc_costs = &ultrasparc_costs;
1151 case PROCESSOR_ULTRASPARC3:
1152 sparc_costs = &ultrasparc3_costs;
1154 case PROCESSOR_NIAGARA:
1155 sparc_costs = &niagara_costs;
1157 case PROCESSOR_NIAGARA2:
1158 sparc_costs = &niagara2_costs;
1160 case PROCESSOR_NIAGARA3:
1161 case PROCESSOR_NIAGARA4:
1162 sparc_costs = &niagara3_costs;
1164 case PROCESSOR_NATIVE:
1168 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1169 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1170 target_flags |= MASK_LONG_DOUBLE_128;
1173 if (TARGET_DEBUG_OPTIONS)
1174 dump_target_flags ("Final target_flags", target_flags);
1176 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
1177 ((sparc_cpu == PROCESSOR_ULTRASPARC
1178 || sparc_cpu == PROCESSOR_NIAGARA
1179 || sparc_cpu == PROCESSOR_NIAGARA2
1180 || sparc_cpu == PROCESSOR_NIAGARA3
1181 || sparc_cpu == PROCESSOR_NIAGARA4)
1183 : (sparc_cpu == PROCESSOR_ULTRASPARC3
1185 global_options.x_param_values,
1186 global_options_set.x_param_values);
1187 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
1188 ((sparc_cpu == PROCESSOR_ULTRASPARC
1189 || sparc_cpu == PROCESSOR_ULTRASPARC3
1190 || sparc_cpu == PROCESSOR_NIAGARA
1191 || sparc_cpu == PROCESSOR_NIAGARA2
1192 || sparc_cpu == PROCESSOR_NIAGARA3
1193 || sparc_cpu == PROCESSOR_NIAGARA4)
1195 global_options.x_param_values,
1196 global_options_set.x_param_values);
1198 /* Disable save slot sharing for call-clobbered registers by default.
1199 The IRA sharing algorithm works on single registers only and this
1200 pessimizes for double floating-point registers. */
1201 if (!global_options_set.x_flag_ira_share_save_slots)
1202 flag_ira_share_save_slots = 0;
1205 /* Miscellaneous utilities. */
1207 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1208 or branch on register contents instructions. */
1211 v9_regcmp_p (enum rtx_code code)
1213 return (code == EQ || code == NE || code == GE || code == LT
1214 || code == LE || code == GT);
1217 /* Nonzero if OP is a floating point constant which can
1218 be loaded into an integer register using a single
1219 sethi instruction. */
1224 if (GET_CODE (op) == CONST_DOUBLE)
1229 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1230 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1231 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
1237 /* Nonzero if OP is a floating point constant which can
1238 be loaded into an integer register using a single
1244 if (GET_CODE (op) == CONST_DOUBLE)
1249 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1250 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1251 return SPARC_SIMM13_P (i);
1257 /* Nonzero if OP is a floating point constant which can
1258 be loaded into an integer register using a high/losum
1259 instruction sequence. */
1262 fp_high_losum_p (rtx op)
1264 /* The constraints calling this should only be in
1265 SFmode move insns, so any constant which cannot
1266 be moved using a single insn will do. */
1267 if (GET_CODE (op) == CONST_DOUBLE)
1272 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1273 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1274 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
1280 /* Return true if the address of LABEL can be loaded by means of the
1281 mov{si,di}_pic_label_ref patterns in PIC mode. */
1284 can_use_mov_pic_label_ref (rtx label)
1286 /* VxWorks does not impose a fixed gap between segments; the run-time
1287 gap can be different from the object-file gap. We therefore can't
1288 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1289 are absolutely sure that X is in the same segment as the GOT.
1290 Unfortunately, the flexibility of linker scripts means that we
1291 can't be sure of that in general, so assume that GOT-relative
1292 accesses are never valid on VxWorks. */
1293 if (TARGET_VXWORKS_RTP)
1296 /* Similarly, if the label is non-local, it might end up being placed
1297 in a different section than the current one; now mov_pic_label_ref
1298 requires the label and the code to be in the same section. */
1299 if (LABEL_REF_NONLOCAL_P (label))
1302 /* Finally, if we are reordering basic blocks and partition into hot
1303 and cold sections, this might happen for any label. */
1304 if (flag_reorder_blocks_and_partition)
1310 /* Expand a move instruction. Return true if all work is done. */
1313 sparc_expand_move (enum machine_mode mode, rtx *operands)
1315 /* Handle sets of MEM first. */
1316 if (GET_CODE (operands[0]) == MEM)
1318 /* 0 is a register (or a pair of registers) on SPARC. */
1319 if (register_or_zero_operand (operands[1], mode))
1322 if (!reload_in_progress)
1324 operands[0] = validize_mem (operands[0]);
1325 operands[1] = force_reg (mode, operands[1]);
1329 /* Fixup TLS cases. */
1331 && CONSTANT_P (operands[1])
1332 && sparc_tls_referenced_p (operands [1]))
1334 operands[1] = sparc_legitimize_tls_address (operands[1]);
1338 /* Fixup PIC cases. */
1339 if (flag_pic && CONSTANT_P (operands[1]))
1341 if (pic_address_needs_scratch (operands[1]))
1342 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
1344 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1345 if (GET_CODE (operands[1]) == LABEL_REF
1346 && can_use_mov_pic_label_ref (operands[1]))
1350 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1356 gcc_assert (TARGET_ARCH64);
1357 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1362 if (symbolic_operand (operands[1], mode))
1365 = sparc_legitimize_pic_address (operands[1],
1367 ? operands[0] : NULL_RTX);
1372 /* If we are trying to toss an integer constant into FP registers,
1373 or loading a FP or vector constant, force it into memory. */
1374 if (CONSTANT_P (operands[1])
1375 && REG_P (operands[0])
1376 && (SPARC_FP_REG_P (REGNO (operands[0]))
1377 || SCALAR_FLOAT_MODE_P (mode)
1378 || VECTOR_MODE_P (mode)))
1380 /* emit_group_store will send such bogosity to us when it is
1381 not storing directly into memory. So fix this up to avoid
1382 crashes in output_constant_pool. */
1383 if (operands [1] == const0_rtx)
1384 operands[1] = CONST0_RTX (mode);
1386 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1387 always other regs. */
1388 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1389 && (const_zero_operand (operands[1], mode)
1390 || const_all_ones_operand (operands[1], mode)))
1393 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1394 /* We are able to build any SF constant in integer registers
1395 with at most 2 instructions. */
1397 /* And any DF constant in integer registers. */
1399 && ! can_create_pseudo_p ())))
1402 operands[1] = force_const_mem (mode, operands[1]);
1403 if (!reload_in_progress)
1404 operands[1] = validize_mem (operands[1]);
1408 /* Accept non-constants and valid constants unmodified. */
1409 if (!CONSTANT_P (operands[1])
1410 || GET_CODE (operands[1]) == HIGH
1411 || input_operand (operands[1], mode))
1417 /* All QImode constants require only one insn, so proceed. */
1422 sparc_emit_set_const32 (operands[0], operands[1]);
1426 /* input_operand should have filtered out 32-bit mode. */
1427 sparc_emit_set_const64 (operands[0], operands[1]);
1437 /* Load OP1, a 32-bit constant, into OP0, a register.
1438 We know it can't be done in one insn when we get
1439 here, the move expander guarantees this. */
1442 sparc_emit_set_const32 (rtx op0, rtx op1)
1444 enum machine_mode mode = GET_MODE (op0);
1447 if (can_create_pseudo_p ())
1448 temp = gen_reg_rtx (mode);
1450 if (GET_CODE (op1) == CONST_INT)
1452 gcc_assert (!small_int_operand (op1, mode)
1453 && !const_high_operand (op1, mode));
1455 /* Emit them as real moves instead of a HIGH/LO_SUM,
1456 this way CSE can see everything and reuse intermediate
1457 values if it wants. */
1458 emit_insn (gen_rtx_SET (VOIDmode, temp,
1459 GEN_INT (INTVAL (op1)
1460 & ~(HOST_WIDE_INT)0x3ff)));
1462 emit_insn (gen_rtx_SET (VOIDmode,
1464 gen_rtx_IOR (mode, temp,
1465 GEN_INT (INTVAL (op1) & 0x3ff))));
1469 /* A symbol, emit in the traditional way. */
1470 emit_insn (gen_rtx_SET (VOIDmode, temp,
1471 gen_rtx_HIGH (mode, op1)));
1472 emit_insn (gen_rtx_SET (VOIDmode,
1473 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1477 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1478 If TEMP is nonzero, we are forbidden to use any other scratch
1479 registers. Otherwise, we are allowed to generate them as needed.
1481 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1482 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1485 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1487 rtx temp1, temp2, temp3, temp4, temp5;
1490 if (temp && GET_MODE (temp) == TImode)
1493 temp = gen_rtx_REG (DImode, REGNO (temp));
1496 /* SPARC-V9 code-model support. */
1497 switch (sparc_cmodel)
1500 /* The range spanned by all instructions in the object is less
1501 than 2^31 bytes (2GB) and the distance from any instruction
1502 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1503 than 2^31 bytes (2GB).
1505 The executable must be in the low 4TB of the virtual address
1508 sethi %hi(symbol), %temp1
1509 or %temp1, %lo(symbol), %reg */
1511 temp1 = temp; /* op0 is allowed. */
1513 temp1 = gen_reg_rtx (DImode);
1515 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1516 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1520 /* The range spanned by all instructions in the object is less
1521 than 2^31 bytes (2GB) and the distance from any instruction
1522 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1523 than 2^31 bytes (2GB).
1525 The executable must be in the low 16TB of the virtual address
1528 sethi %h44(symbol), %temp1
1529 or %temp1, %m44(symbol), %temp2
1530 sllx %temp2, 12, %temp3
1531 or %temp3, %l44(symbol), %reg */
1536 temp3 = temp; /* op0 is allowed. */
1540 temp1 = gen_reg_rtx (DImode);
1541 temp2 = gen_reg_rtx (DImode);
1542 temp3 = gen_reg_rtx (DImode);
1545 emit_insn (gen_seth44 (temp1, op1));
1546 emit_insn (gen_setm44 (temp2, temp1, op1));
1547 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1548 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1549 emit_insn (gen_setl44 (op0, temp3, op1));
1553 /* The range spanned by all instructions in the object is less
1554 than 2^31 bytes (2GB) and the distance from any instruction
1555 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1556 than 2^31 bytes (2GB).
1558 The executable can be placed anywhere in the virtual address
1561 sethi %hh(symbol), %temp1
1562 sethi %lm(symbol), %temp2
1563 or %temp1, %hm(symbol), %temp3
1564 sllx %temp3, 32, %temp4
1565 or %temp4, %temp2, %temp5
1566 or %temp5, %lo(symbol), %reg */
1569 /* It is possible that one of the registers we got for operands[2]
1570 might coincide with that of operands[0] (which is why we made
1571 it TImode). Pick the other one to use as our scratch. */
1572 if (rtx_equal_p (temp, op0))
1574 gcc_assert (ti_temp);
1575 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1578 temp2 = temp; /* op0 is _not_ allowed, see above. */
1585 temp1 = gen_reg_rtx (DImode);
1586 temp2 = gen_reg_rtx (DImode);
1587 temp3 = gen_reg_rtx (DImode);
1588 temp4 = gen_reg_rtx (DImode);
1589 temp5 = gen_reg_rtx (DImode);
1592 emit_insn (gen_sethh (temp1, op1));
1593 emit_insn (gen_setlm (temp2, op1));
1594 emit_insn (gen_sethm (temp3, temp1, op1));
1595 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1596 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1597 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1598 gen_rtx_PLUS (DImode, temp4, temp2)));
1599 emit_insn (gen_setlo (op0, temp5, op1));
1603 /* Old old old backwards compatibility kruft here.
1604 Essentially it is MEDLOW with a fixed 64-bit
1605 virtual base added to all data segment addresses.
1606 Text-segment stuff is computed like MEDANY, we can't
1607 reuse the code above because the relocation knobs
1610 Data segment: sethi %hi(symbol), %temp1
1611 add %temp1, EMBMEDANY_BASE_REG, %temp2
1612 or %temp2, %lo(symbol), %reg */
1613 if (data_segment_operand (op1, GET_MODE (op1)))
1617 temp1 = temp; /* op0 is allowed. */
1622 temp1 = gen_reg_rtx (DImode);
1623 temp2 = gen_reg_rtx (DImode);
1626 emit_insn (gen_embmedany_sethi (temp1, op1));
1627 emit_insn (gen_embmedany_brsum (temp2, temp1));
1628 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1631 /* Text segment: sethi %uhi(symbol), %temp1
1632 sethi %hi(symbol), %temp2
1633 or %temp1, %ulo(symbol), %temp3
1634 sllx %temp3, 32, %temp4
1635 or %temp4, %temp2, %temp5
1636 or %temp5, %lo(symbol), %reg */
1641 /* It is possible that one of the registers we got for operands[2]
1642 might coincide with that of operands[0] (which is why we made
1643 it TImode). Pick the other one to use as our scratch. */
1644 if (rtx_equal_p (temp, op0))
1646 gcc_assert (ti_temp);
1647 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1650 temp2 = temp; /* op0 is _not_ allowed, see above. */
1657 temp1 = gen_reg_rtx (DImode);
1658 temp2 = gen_reg_rtx (DImode);
1659 temp3 = gen_reg_rtx (DImode);
1660 temp4 = gen_reg_rtx (DImode);
1661 temp5 = gen_reg_rtx (DImode);
1664 emit_insn (gen_embmedany_textuhi (temp1, op1));
1665 emit_insn (gen_embmedany_texthi (temp2, op1));
1666 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1667 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1668 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1669 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1670 gen_rtx_PLUS (DImode, temp4, temp2)));
1671 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1680 #if HOST_BITS_PER_WIDE_INT == 32
1682 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1687 /* These avoid problems when cross compiling. If we do not
1688 go through all this hair then the optimizer will see
1689 invalid REG_EQUAL notes or in some cases none at all. */
1690 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
1691 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1692 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1693 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1695 /* The optimizer is not to assume anything about exactly
1696 which bits are set for a HIGH, they are unspecified.
1697 Unfortunately this leads to many missed optimizations
1698 during CSE. We mask out the non-HIGH bits, and matches
1699 a plain movdi, to alleviate this problem. */
1701 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1703 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
1707 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1709 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
1713 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1715 return gen_rtx_IOR (DImode, src, GEN_INT (val));
1719 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1721 return gen_rtx_XOR (DImode, src, GEN_INT (val));
1724 /* Worker routines for 64-bit constant formation on arch64.
1725 One of the key things to be doing in these emissions is
1726 to create as many temp REGs as possible. This makes it
1727 possible for half-built constants to be used later when
1728 such values are similar to something required later on.
1729 Without doing this, the optimizer cannot see such
1732 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1733 unsigned HOST_WIDE_INT, int);
1736 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1737 unsigned HOST_WIDE_INT low_bits, int is_neg)
1739 unsigned HOST_WIDE_INT high_bits;
1742 high_bits = (~low_bits) & 0xffffffff;
1744 high_bits = low_bits;
1746 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1749 emit_insn (gen_rtx_SET (VOIDmode, op0,
1750 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1754 /* If we are XOR'ing with -1, then we should emit a one's complement
1755 instead. This way the combiner will notice logical operations
1756 such as ANDN later on and substitute. */
1757 if ((low_bits & 0x3ff) == 0x3ff)
1759 emit_insn (gen_rtx_SET (VOIDmode, op0,
1760 gen_rtx_NOT (DImode, temp)));
1764 emit_insn (gen_rtx_SET (VOIDmode, op0,
1765 gen_safe_XOR64 (temp,
1766 (-(HOST_WIDE_INT)0x400
1767 | (low_bits & 0x3ff)))));
1772 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1773 unsigned HOST_WIDE_INT, int);
1776 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1777 unsigned HOST_WIDE_INT high_bits,
1778 unsigned HOST_WIDE_INT low_immediate,
1783 if ((high_bits & 0xfffffc00) != 0)
1785 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1786 if ((high_bits & ~0xfffffc00) != 0)
1787 emit_insn (gen_rtx_SET (VOIDmode, op0,
1788 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1794 emit_insn (gen_safe_SET64 (temp, high_bits));
1798 /* Now shift it up into place. */
1799 emit_insn (gen_rtx_SET (VOIDmode, op0,
1800 gen_rtx_ASHIFT (DImode, temp2,
1801 GEN_INT (shift_count))));
1803 /* If there is a low immediate part piece, finish up by
1804 putting that in as well. */
1805 if (low_immediate != 0)
1806 emit_insn (gen_rtx_SET (VOIDmode, op0,
1807 gen_safe_OR64 (op0, low_immediate)));
1810 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1811 unsigned HOST_WIDE_INT);
1813 /* Full 64-bit constant decomposition. Even though this is the
1814 'worst' case, we still optimize a few things away. */
1816 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1817 unsigned HOST_WIDE_INT high_bits,
1818 unsigned HOST_WIDE_INT low_bits)
1822 if (can_create_pseudo_p ())
1823 sub_temp = gen_reg_rtx (DImode);
1825 if ((high_bits & 0xfffffc00) != 0)
1827 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1828 if ((high_bits & ~0xfffffc00) != 0)
1829 emit_insn (gen_rtx_SET (VOIDmode,
1831 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1837 emit_insn (gen_safe_SET64 (temp, high_bits));
1841 if (can_create_pseudo_p ())
1843 rtx temp2 = gen_reg_rtx (DImode);
1844 rtx temp3 = gen_reg_rtx (DImode);
1845 rtx temp4 = gen_reg_rtx (DImode);
1847 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1848 gen_rtx_ASHIFT (DImode, sub_temp,
1851 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
1852 if ((low_bits & ~0xfffffc00) != 0)
1854 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1855 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1856 emit_insn (gen_rtx_SET (VOIDmode, op0,
1857 gen_rtx_PLUS (DImode, temp4, temp3)));
1861 emit_insn (gen_rtx_SET (VOIDmode, op0,
1862 gen_rtx_PLUS (DImode, temp4, temp2)));
1867 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1868 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1869 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1872 /* We are in the middle of reload, so this is really
1873 painful. However we do still make an attempt to
1874 avoid emitting truly stupid code. */
1875 if (low1 != const0_rtx)
1877 emit_insn (gen_rtx_SET (VOIDmode, op0,
1878 gen_rtx_ASHIFT (DImode, sub_temp,
1879 GEN_INT (to_shift))));
1880 emit_insn (gen_rtx_SET (VOIDmode, op0,
1881 gen_rtx_IOR (DImode, op0, low1)));
1889 if (low2 != const0_rtx)
1891 emit_insn (gen_rtx_SET (VOIDmode, op0,
1892 gen_rtx_ASHIFT (DImode, sub_temp,
1893 GEN_INT (to_shift))));
1894 emit_insn (gen_rtx_SET (VOIDmode, op0,
1895 gen_rtx_IOR (DImode, op0, low2)));
1903 emit_insn (gen_rtx_SET (VOIDmode, op0,
1904 gen_rtx_ASHIFT (DImode, sub_temp,
1905 GEN_INT (to_shift))));
1906 if (low3 != const0_rtx)
1907 emit_insn (gen_rtx_SET (VOIDmode, op0,
1908 gen_rtx_IOR (DImode, op0, low3)));
1913 /* Analyze a 64-bit constant for certain properties. */
1914 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1915 unsigned HOST_WIDE_INT,
1916 int *, int *, int *);
1919 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1920 unsigned HOST_WIDE_INT low_bits,
1921 int *hbsp, int *lbsp, int *abbasp)
1923 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1926 lowest_bit_set = highest_bit_set = -1;
1930 if ((lowest_bit_set == -1)
1931 && ((low_bits >> i) & 1))
1933 if ((highest_bit_set == -1)
1934 && ((high_bits >> (32 - i - 1)) & 1))
1935 highest_bit_set = (64 - i - 1);
1938 && ((highest_bit_set == -1)
1939 || (lowest_bit_set == -1)));
1945 if ((lowest_bit_set == -1)
1946 && ((high_bits >> i) & 1))
1947 lowest_bit_set = i + 32;
1948 if ((highest_bit_set == -1)
1949 && ((low_bits >> (32 - i - 1)) & 1))
1950 highest_bit_set = 32 - i - 1;
1953 && ((highest_bit_set == -1)
1954 || (lowest_bit_set == -1)));
1956 /* If there are no bits set this should have gone out
1957 as one instruction! */
1958 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
1959 all_bits_between_are_set = 1;
1960 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1964 if ((low_bits & (1 << i)) != 0)
1969 if ((high_bits & (1 << (i - 32))) != 0)
1972 all_bits_between_are_set = 0;
1975 *hbsp = highest_bit_set;
1976 *lbsp = lowest_bit_set;
1977 *abbasp = all_bits_between_are_set;
1980 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1983 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1984 unsigned HOST_WIDE_INT low_bits)
1986 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1989 || high_bits == 0xffffffff)
1992 analyze_64bit_constant (high_bits, low_bits,
1993 &highest_bit_set, &lowest_bit_set,
1994 &all_bits_between_are_set);
1996 if ((highest_bit_set == 63
1997 || lowest_bit_set == 0)
1998 && all_bits_between_are_set != 0)
2001 if ((highest_bit_set - lowest_bit_set) < 21)
2007 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2008 unsigned HOST_WIDE_INT,
2011 static unsigned HOST_WIDE_INT
2012 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2013 unsigned HOST_WIDE_INT low_bits,
2014 int lowest_bit_set, int shift)
2016 HOST_WIDE_INT hi, lo;
2018 if (lowest_bit_set < 32)
2020 lo = (low_bits >> lowest_bit_set) << shift;
2021 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2026 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2028 gcc_assert (! (hi & lo));
2032 /* Here we are sure to be arch64 and this is an integer constant
2033 being loaded into a register. Emit the most efficient
2034 insn sequence possible. Detection of all the 1-insn cases
2035 has been done already. */
2037 sparc_emit_set_const64 (rtx op0, rtx op1)
2039 unsigned HOST_WIDE_INT high_bits, low_bits;
2040 int lowest_bit_set, highest_bit_set;
2041 int all_bits_between_are_set;
2044 /* Sanity check that we know what we are working with. */
2045 gcc_assert (TARGET_ARCH64
2046 && (GET_CODE (op0) == SUBREG
2047 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
2049 if (! can_create_pseudo_p ())
2052 if (GET_CODE (op1) != CONST_INT)
2054 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2059 temp = gen_reg_rtx (DImode);
2061 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2062 low_bits = (INTVAL (op1) & 0xffffffff);
2064 /* low_bits bits 0 --> 31
2065 high_bits bits 32 --> 63 */
2067 analyze_64bit_constant (high_bits, low_bits,
2068 &highest_bit_set, &lowest_bit_set,
2069 &all_bits_between_are_set);
2071 /* First try for a 2-insn sequence. */
2073 /* These situations are preferred because the optimizer can
2074 * do more things with them:
2076 * sllx %reg, shift, %reg
2078 * srlx %reg, shift, %reg
2079 * 3) mov some_small_const, %reg
2080 * sllx %reg, shift, %reg
2082 if (((highest_bit_set == 63
2083 || lowest_bit_set == 0)
2084 && all_bits_between_are_set != 0)
2085 || ((highest_bit_set - lowest_bit_set) < 12))
2087 HOST_WIDE_INT the_const = -1;
2088 int shift = lowest_bit_set;
2090 if ((highest_bit_set != 63
2091 && lowest_bit_set != 0)
2092 || all_bits_between_are_set == 0)
2095 create_simple_focus_bits (high_bits, low_bits,
2098 else if (lowest_bit_set == 0)
2099 shift = -(63 - highest_bit_set);
2101 gcc_assert (SPARC_SIMM13_P (the_const));
2102 gcc_assert (shift != 0);
2104 emit_insn (gen_safe_SET64 (temp, the_const));
2106 emit_insn (gen_rtx_SET (VOIDmode,
2108 gen_rtx_ASHIFT (DImode,
2112 emit_insn (gen_rtx_SET (VOIDmode,
2114 gen_rtx_LSHIFTRT (DImode,
2116 GEN_INT (-shift))));
2120 /* Now a range of 22 or less bits set somewhere.
2121 * 1) sethi %hi(focus_bits), %reg
2122 * sllx %reg, shift, %reg
2123 * 2) sethi %hi(focus_bits), %reg
2124 * srlx %reg, shift, %reg
2126 if ((highest_bit_set - lowest_bit_set) < 21)
2128 unsigned HOST_WIDE_INT focus_bits =
2129 create_simple_focus_bits (high_bits, low_bits,
2130 lowest_bit_set, 10);
2132 gcc_assert (SPARC_SETHI_P (focus_bits));
2133 gcc_assert (lowest_bit_set != 10);
2135 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
2137 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2138 if (lowest_bit_set < 10)
2139 emit_insn (gen_rtx_SET (VOIDmode,
2141 gen_rtx_LSHIFTRT (DImode, temp,
2142 GEN_INT (10 - lowest_bit_set))));
2143 else if (lowest_bit_set > 10)
2144 emit_insn (gen_rtx_SET (VOIDmode,
2146 gen_rtx_ASHIFT (DImode, temp,
2147 GEN_INT (lowest_bit_set - 10))));
2151 /* 1) sethi %hi(low_bits), %reg
2152 * or %reg, %lo(low_bits), %reg
2153 * 2) sethi %hi(~low_bits), %reg
2154 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2157 || high_bits == 0xffffffff)
2159 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2160 (high_bits == 0xffffffff));
2164 /* Now, try 3-insn sequences. */
2166 /* 1) sethi %hi(high_bits), %reg
2167 * or %reg, %lo(high_bits), %reg
2168 * sllx %reg, 32, %reg
2172 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2176 /* We may be able to do something quick
2177 when the constant is negated, so try that. */
2178 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2179 (~low_bits) & 0xfffffc00))
2181 /* NOTE: The trailing bits get XOR'd so we need the
2182 non-negated bits, not the negated ones. */
2183 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2185 if ((((~high_bits) & 0xffffffff) == 0
2186 && ((~low_bits) & 0x80000000) == 0)
2187 || (((~high_bits) & 0xffffffff) == 0xffffffff
2188 && ((~low_bits) & 0x80000000) != 0))
2190 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
2192 if ((SPARC_SETHI_P (fast_int)
2193 && (~high_bits & 0xffffffff) == 0)
2194 || SPARC_SIMM13_P (fast_int))
2195 emit_insn (gen_safe_SET64 (temp, fast_int));
2197 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
2202 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2203 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2204 sparc_emit_set_const64 (temp, negated_const);
2207 /* If we are XOR'ing with -1, then we should emit a one's complement
2208 instead. This way the combiner will notice logical operations
2209 such as ANDN later on and substitute. */
2210 if (trailing_bits == 0x3ff)
2212 emit_insn (gen_rtx_SET (VOIDmode, op0,
2213 gen_rtx_NOT (DImode, temp)));
2217 emit_insn (gen_rtx_SET (VOIDmode,
2219 gen_safe_XOR64 (temp,
2220 (-0x400 | trailing_bits))));
2225 /* 1) sethi %hi(xxx), %reg
2226 * or %reg, %lo(xxx), %reg
2227 * sllx %reg, yyy, %reg
2229 * ??? This is just a generalized version of the low_bits==0
2230 * thing above, FIXME...
2232 if ((highest_bit_set - lowest_bit_set) < 32)
2234 unsigned HOST_WIDE_INT focus_bits =
2235 create_simple_focus_bits (high_bits, low_bits,
2238 /* We can't get here in this state. */
2239 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
2241 /* So what we know is that the set bits straddle the
2242 middle of the 64-bit word. */
2243 sparc_emit_set_const64_quick2 (op0, temp,
2249 /* 1) sethi %hi(high_bits), %reg
2250 * or %reg, %lo(high_bits), %reg
2251 * sllx %reg, 32, %reg
2252 * or %reg, low_bits, %reg
2254 if (SPARC_SIMM13_P(low_bits)
2255 && ((int)low_bits > 0))
2257 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2261 /* The easiest way when all else fails, is full decomposition. */
2262 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2264 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2266 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2267 return the mode to be used for the comparison. For floating-point,
2268 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2269 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2270 processing is needed. */
2273 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2275 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2301 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2302 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2304 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2305 return CCX_NOOVmode;
2311 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2318 /* Emit the compare insn and return the CC reg for a CODE comparison
2319 with operands X and Y. */
2322 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
2324 enum machine_mode mode;
2327 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2330 mode = SELECT_CC_MODE (code, x, y);
2332 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2333 fcc regs (cse can't tell they're really call clobbered regs and will
2334 remove a duplicate comparison even if there is an intervening function
2335 call - it will then try to reload the cc reg via an int reg which is why
2336 we need the movcc patterns). It is possible to provide the movcc
2337 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2338 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2339 to tell cse that CCFPE mode registers (even pseudos) are call
2342 /* ??? This is an experiment. Rather than making changes to cse which may
2343 or may not be easy/clean, we do our own cse. This is possible because
2344 we will generate hard registers. Cse knows they're call clobbered (it
2345 doesn't know the same thing about pseudos). If we guess wrong, no big
2346 deal, but if we win, great! */
2348 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2349 #if 1 /* experiment */
2352 /* We cycle through the registers to ensure they're all exercised. */
2353 static int next_fcc_reg = 0;
2354 /* Previous x,y for each fcc reg. */
2355 static rtx prev_args[4][2];
2357 /* Scan prev_args for x,y. */
2358 for (reg = 0; reg < 4; reg++)
2359 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2364 prev_args[reg][0] = x;
2365 prev_args[reg][1] = y;
2366 next_fcc_reg = (next_fcc_reg + 1) & 3;
2368 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2371 cc_reg = gen_reg_rtx (mode);
2372 #endif /* ! experiment */
2373 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2374 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2376 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2378 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2379 will only result in an unrecognizable insn so no point in asserting. */
2380 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
2386 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2389 gen_compare_reg (rtx cmp)
2391 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
2394 /* This function is used for v9 only.
2395 DEST is the target of the Scc insn.
2396 CODE is the code for an Scc's comparison.
2397 X and Y are the values we compare.
2399 This function is needed to turn
2402 (gt (reg:CCX 100 %icc)
2406 (gt:DI (reg:CCX 100 %icc)
2409 IE: The instruction recognizer needs to see the mode of the comparison to
2410 find the right instruction. We could use "gt:DI" right in the
2411 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2414 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
2417 && (GET_MODE (x) == DImode
2418 || GET_MODE (dest) == DImode))
2421 /* Try to use the movrCC insns. */
2423 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2425 && v9_regcmp_p (compare_code))
2430 /* Special case for op0 != 0. This can be done with one instruction if
2433 if (compare_code == NE
2434 && GET_MODE (dest) == DImode
2435 && rtx_equal_p (op0, dest))
2437 emit_insn (gen_rtx_SET (VOIDmode, dest,
2438 gen_rtx_IF_THEN_ELSE (DImode,
2439 gen_rtx_fmt_ee (compare_code, DImode,
2446 if (reg_overlap_mentioned_p (dest, op0))
2448 /* Handle the case where dest == x.
2449 We "early clobber" the result. */
2450 op0 = gen_reg_rtx (GET_MODE (x));
2451 emit_move_insn (op0, x);
2454 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2455 if (GET_MODE (op0) != DImode)
2457 temp = gen_reg_rtx (DImode);
2458 convert_move (temp, op0, 0);
2462 emit_insn (gen_rtx_SET (VOIDmode, dest,
2463 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2464 gen_rtx_fmt_ee (compare_code, DImode,
2472 x = gen_compare_reg_1 (compare_code, x, y);
2475 gcc_assert (GET_MODE (x) != CC_NOOVmode
2476 && GET_MODE (x) != CCX_NOOVmode);
2478 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2479 emit_insn (gen_rtx_SET (VOIDmode, dest,
2480 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2481 gen_rtx_fmt_ee (compare_code,
2482 GET_MODE (x), x, y),
2483 const1_rtx, dest)));
2489 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2490 without jumps using the addx/subx instructions. */
2493 emit_scc_insn (rtx operands[])
2500 /* The quad-word fp compare library routines all return nonzero to indicate
2501 true, which is different from the equivalent libgcc routines, so we must
2502 handle them specially here. */
2503 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2505 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2506 GET_CODE (operands[1]));
2507 operands[2] = XEXP (operands[1], 0);
2508 operands[3] = XEXP (operands[1], 1);
2511 code = GET_CODE (operands[1]);
2515 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2516 more applications). The exception to this is "reg != 0" which can
2517 be done in one instruction on v9 (so we do it). */
2520 if (GET_MODE (x) == SImode)
2522 rtx pat = gen_seqsi_special (operands[0], x, y);
2526 else if (GET_MODE (x) == DImode)
2528 rtx pat = gen_seqdi_special (operands[0], x, y);
2536 if (GET_MODE (x) == SImode)
2538 rtx pat = gen_snesi_special (operands[0], x, y);
2542 else if (GET_MODE (x) == DImode)
2544 rtx pat = gen_snedi_special (operands[0], x, y);
2550 /* For the rest, on v9 we can use conditional moves. */
2554 if (gen_v9_scc (operands[0], code, x, y))
2558 /* We can do LTU and GEU using the addx/subx instructions too. And
2559 for GTU/LEU, if both operands are registers swap them and fall
2560 back to the easy case. */
2561 if (code == GTU || code == LEU)
2563 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2564 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2569 code = swap_condition (code);
2573 if (code == LTU || code == GEU)
2575 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2576 gen_rtx_fmt_ee (code, SImode,
2577 gen_compare_reg_1 (code, x, y),
2582 /* Nope, do branches. */
2586 /* Emit a conditional jump insn for the v9 architecture using comparison code
2587 CODE and jump target LABEL.
2588 This function exists to take advantage of the v9 brxx insns. */
2591 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2593 emit_jump_insn (gen_rtx_SET (VOIDmode,
2595 gen_rtx_IF_THEN_ELSE (VOIDmode,
2596 gen_rtx_fmt_ee (code, GET_MODE (op0),
2598 gen_rtx_LABEL_REF (VOIDmode, label),
2603 emit_conditional_branch_insn (rtx operands[])
2605 /* The quad-word fp compare library routines all return nonzero to indicate
2606 true, which is different from the equivalent libgcc routines, so we must
2607 handle them specially here. */
2608 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
2610 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
2611 GET_CODE (operands[0]));
2612 operands[1] = XEXP (operands[0], 0);
2613 operands[2] = XEXP (operands[0], 1);
2616 if (TARGET_ARCH64 && operands[2] == const0_rtx
2617 && GET_CODE (operands[1]) == REG
2618 && GET_MODE (operands[1]) == DImode)
2620 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
2624 operands[1] = gen_compare_reg (operands[0]);
2625 operands[2] = const0_rtx;
2626 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
2627 operands[1], operands[2]);
2628 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
2633 /* Generate a DFmode part of a hard TFmode register.
2634 REG is the TFmode hard register, LOW is 1 for the
2635 low 64bit of the register and 0 otherwise.
2638 gen_df_reg (rtx reg, int low)
2640 int regno = REGNO (reg);
2642 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2643 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2644 return gen_rtx_REG (DFmode, regno);
2647 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2648 Unlike normal calls, TFmode operands are passed by reference. It is
2649 assumed that no more than 3 operands are required. */
2652 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2654 rtx ret_slot = NULL, arg[3], func_sym;
2657 /* We only expect to be called for conversions, unary, and binary ops. */
2658 gcc_assert (nargs == 2 || nargs == 3);
2660 for (i = 0; i < nargs; ++i)
2662 rtx this_arg = operands[i];
2665 /* TFmode arguments and return values are passed by reference. */
2666 if (GET_MODE (this_arg) == TFmode)
2668 int force_stack_temp;
2670 force_stack_temp = 0;
2671 if (TARGET_BUGGY_QP_LIB && i == 0)
2672 force_stack_temp = 1;
2674 if (GET_CODE (this_arg) == MEM
2675 && ! force_stack_temp)
2676 this_arg = XEXP (this_arg, 0);
2677 else if (CONSTANT_P (this_arg)
2678 && ! force_stack_temp)
2680 this_slot = force_const_mem (TFmode, this_arg);
2681 this_arg = XEXP (this_slot, 0);
2685 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2687 /* Operand 0 is the return value. We'll copy it out later. */
2689 emit_move_insn (this_slot, this_arg);
2691 ret_slot = this_slot;
2693 this_arg = XEXP (this_slot, 0);
2700 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2702 if (GET_MODE (operands[0]) == TFmode)
2705 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2706 arg[0], GET_MODE (arg[0]),
2707 arg[1], GET_MODE (arg[1]));
2709 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2710 arg[0], GET_MODE (arg[0]),
2711 arg[1], GET_MODE (arg[1]),
2712 arg[2], GET_MODE (arg[2]));
2715 emit_move_insn (operands[0], ret_slot);
2721 gcc_assert (nargs == 2);
2723 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2724 GET_MODE (operands[0]), 1,
2725 arg[1], GET_MODE (arg[1]));
2727 if (ret != operands[0])
2728 emit_move_insn (operands[0], ret);
2732 /* Expand soft-float TFmode calls to sparc abi routines. */
2735 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2757 emit_soft_tfmode_libcall (func, 3, operands);
2761 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2765 gcc_assert (code == SQRT);
2768 emit_soft_tfmode_libcall (func, 2, operands);
2772 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2779 switch (GET_MODE (operands[1]))
2792 case FLOAT_TRUNCATE:
2793 switch (GET_MODE (operands[0]))
2807 switch (GET_MODE (operands[1]))
2812 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
2822 case UNSIGNED_FLOAT:
2823 switch (GET_MODE (operands[1]))
2828 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2839 switch (GET_MODE (operands[0]))
2853 switch (GET_MODE (operands[0]))
2870 emit_soft_tfmode_libcall (func, 2, operands);
2873 /* Expand a hard-float tfmode operation. All arguments must be in
2877 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2881 if (GET_RTX_CLASS (code) == RTX_UNARY)
2883 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2884 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2888 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2889 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2890 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2891 operands[1], operands[2]);
2894 if (register_operand (operands[0], VOIDmode))
2897 dest = gen_reg_rtx (GET_MODE (operands[0]));
2899 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2901 if (dest != operands[0])
2902 emit_move_insn (operands[0], dest);
2906 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2908 if (TARGET_HARD_QUAD)
2909 emit_hard_tfmode_operation (code, operands);
2911 emit_soft_tfmode_binop (code, operands);
2915 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2917 if (TARGET_HARD_QUAD)
2918 emit_hard_tfmode_operation (code, operands);
2920 emit_soft_tfmode_unop (code, operands);
2924 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2926 if (TARGET_HARD_QUAD)
2927 emit_hard_tfmode_operation (code, operands);
2929 emit_soft_tfmode_cvt (code, operands);
2932 /* Return nonzero if a branch/jump/call instruction will be emitting
2933 nop into its delay slot. */
2936 empty_delay_slot (rtx insn)
2940 /* If no previous instruction (should not happen), return true. */
2941 if (PREV_INSN (insn) == NULL)
2944 seq = NEXT_INSN (PREV_INSN (insn));
2945 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2951 /* Return nonzero if TRIAL can go into the call delay slot. */
2954 tls_call_delay (rtx trial)
2959 call __tls_get_addr, %tgd_call (foo)
2960 add %l7, %o0, %o0, %tgd_add (foo)
2961 while Sun as/ld does not. */
2962 if (TARGET_GNU_TLS || !TARGET_TLS)
2965 pat = PATTERN (trial);
2967 /* We must reject tgd_add{32|64}, i.e.
2968 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2969 and tldm_add{32|64}, i.e.
2970 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2972 if (GET_CODE (pat) == SET
2973 && GET_CODE (SET_SRC (pat)) == PLUS)
2975 rtx unspec = XEXP (SET_SRC (pat), 1);
2977 if (GET_CODE (unspec) == UNSPEC
2978 && (XINT (unspec, 1) == UNSPEC_TLSGD
2979 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2986 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2987 instruction. RETURN_P is true if the v9 variant 'return' is to be
2988 considered in the test too.
2990 TRIAL must be a SET whose destination is a REG appropriate for the
2991 'restore' instruction or, if RETURN_P is true, for the 'return'
2995 eligible_for_restore_insn (rtx trial, bool return_p)
2997 rtx pat = PATTERN (trial);
2998 rtx src = SET_SRC (pat);
3000 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3001 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3002 && arith_operand (src, GET_MODE (src)))
3005 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3007 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3010 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3011 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3012 && arith_double_operand (src, GET_MODE (src)))
3013 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3015 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3016 else if (! TARGET_FPU && register_operand (src, SFmode))
3019 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3020 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3023 /* If we have the 'return' instruction, anything that does not use
3024 local or output registers and can go into a delay slot wins. */
3027 && !epilogue_renumber (&pat, 1)
3028 && get_attr_in_uncond_branch_delay (trial)
3029 == IN_UNCOND_BRANCH_DELAY_TRUE)
3032 /* The 'restore src1,src2,dest' pattern for SImode. */
3033 else if (GET_CODE (src) == PLUS
3034 && register_operand (XEXP (src, 0), SImode)
3035 && arith_operand (XEXP (src, 1), SImode))
3038 /* The 'restore src1,src2,dest' pattern for DImode. */
3039 else if (GET_CODE (src) == PLUS
3040 && register_operand (XEXP (src, 0), DImode)
3041 && arith_double_operand (XEXP (src, 1), DImode))
3044 /* The 'restore src1,%lo(src2),dest' pattern. */
3045 else if (GET_CODE (src) == LO_SUM
3046 && ! TARGET_CM_MEDMID
3047 && ((register_operand (XEXP (src, 0), SImode)
3048 && immediate_operand (XEXP (src, 1), SImode))
3050 && register_operand (XEXP (src, 0), DImode)
3051 && immediate_operand (XEXP (src, 1), DImode))))
3054 /* The 'restore src,src,dest' pattern. */
3055 else if (GET_CODE (src) == ASHIFT
3056 && (register_operand (XEXP (src, 0), SImode)
3057 || register_operand (XEXP (src, 0), DImode))
3058 && XEXP (src, 1) == const1_rtx)
3064 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3067 eligible_for_return_delay (rtx trial)
3072 if (GET_CODE (trial) != INSN)
3075 if (get_attr_length (trial) != 1)
3078 /* If the function uses __builtin_eh_return, the eh_return machinery
3079 occupies the delay slot. */
3080 if (crtl->calls_eh_return)
3083 /* In the case of a leaf or flat function, anything can go into the slot. */
3084 if (sparc_leaf_function_p || TARGET_FLAT)
3086 get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;
3088 pat = PATTERN (trial);
3089 if (GET_CODE (pat) == PARALLEL)
3095 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
3097 rtx expr = XVECEXP (pat, 0, i);
3098 if (GET_CODE (expr) != SET)
3100 if (GET_CODE (SET_DEST (expr)) != REG)
3102 regno = REGNO (SET_DEST (expr));
3103 if (regno >= 8 && regno < 24)
3106 return !epilogue_renumber (&pat, 1)
3107 && (get_attr_in_uncond_branch_delay (trial)
3108 == IN_UNCOND_BRANCH_DELAY_TRUE);
3111 if (GET_CODE (pat) != SET)
3114 if (GET_CODE (SET_DEST (pat)) != REG)
3117 regno = REGNO (SET_DEST (pat));
3119 /* Otherwise, only operations which can be done in tandem with
3120 a `restore' or `return' insn can go into the delay slot. */
3121 if (regno >= 8 && regno < 24)
3124 /* If this instruction sets up floating point register and we have a return
3125 instruction, it can probably go in. But restore will not work
3129 && !epilogue_renumber (&pat, 1)
3130 && get_attr_in_uncond_branch_delay (trial)
3131 == IN_UNCOND_BRANCH_DELAY_TRUE);
3133 return eligible_for_restore_insn (trial, true);
3136 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3139 eligible_for_sibcall_delay (rtx trial)
3143 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3146 if (get_attr_length (trial) != 1)
3149 pat = PATTERN (trial);
3151 if (sparc_leaf_function_p || TARGET_FLAT)
3153 /* If the tail call is done using the call instruction,
3154 we have to restore %o7 in the delay slot. */
3155 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3158 /* %g1 is used to build the function address */
3159 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3165 /* Otherwise, only operations which can be done in tandem with
3166 a `restore' insn can go into the delay slot. */
3167 if (GET_CODE (SET_DEST (pat)) != REG
3168 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3169 || REGNO (SET_DEST (pat)) >= 32)
3172 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3174 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3177 return eligible_for_restore_insn (trial, false);
3180 /* Determine if it's legal to put X into the constant pool. This
3181 is not possible if X contains the address of a symbol that is
3182 not constant (TLS) or not known at final link time (PIC). */
3185 sparc_cannot_force_const_mem (enum machine_mode mode, rtx x)
3187 switch (GET_CODE (x))
3192 /* Accept all non-symbolic constants. */
3196 /* Labels are OK iff we are non-PIC. */
3197 return flag_pic != 0;
3200 /* 'Naked' TLS symbol references are never OK,
3201 non-TLS symbols are OK iff we are non-PIC. */
3202 if (SYMBOL_REF_TLS_MODEL (x))
3205 return flag_pic != 0;
3208 return sparc_cannot_force_const_mem (mode, XEXP (x, 0));
3211 return sparc_cannot_force_const_mem (mode, XEXP (x, 0))
3212 || sparc_cannot_force_const_mem (mode, XEXP (x, 1));
3220 /* Global Offset Table support. */
3221 static GTY(()) rtx got_helper_rtx = NULL_RTX;
3222 static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
3224 /* Return the SYMBOL_REF for the Global Offset Table. */
3226 static GTY(()) rtx sparc_got_symbol = NULL_RTX;
3231 if (!sparc_got_symbol)
3232 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3234 return sparc_got_symbol;
3237 /* Ensure that we are not using patterns that are not OK with PIC. */
3247 op = recog_data.operand[i];
3248 gcc_assert (GET_CODE (op) != SYMBOL_REF
3249 && (GET_CODE (op) != CONST
3250 || (GET_CODE (XEXP (op, 0)) == MINUS
3251 && XEXP (XEXP (op, 0), 0) == sparc_got ()
3252 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
3259 /* Return true if X is an address which needs a temporary register when
3260 reloaded while generating PIC code. */
3263 pic_address_needs_scratch (rtx x)
3265 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3266 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3267 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3268 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3269 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3275 /* Determine if a given RTX is a valid constant. We already know this
3276 satisfies CONSTANT_P. */
3279 sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
3281 switch (GET_CODE (x))
3285 if (sparc_tls_referenced_p (x))
3290 if (GET_MODE (x) == VOIDmode)
3293 /* Floating point constants are generally not ok.
3294 The only exception is 0.0 and all-ones in VIS. */
3296 && SCALAR_FLOAT_MODE_P (mode)
3297 && (const_zero_operand (x, mode)
3298 || const_all_ones_operand (x, mode)))
3304 /* Vector constants are generally not ok.
3305 The only exception is 0 or -1 in VIS. */
3307 && (const_zero_operand (x, mode)
3308 || const_all_ones_operand (x, mode)))
3320 /* Determine if a given RTX is a valid constant address. */
3323 constant_address_p (rtx x)
3325 switch (GET_CODE (x))
3333 if (flag_pic && pic_address_needs_scratch (x))
3335 return sparc_legitimate_constant_p (Pmode, x);
3338 return !flag_pic && sparc_legitimate_constant_p (Pmode, x);
3345 /* Nonzero if the constant value X is a legitimate general operand
3346 when generating PIC code. It is given that flag_pic is on and
3347 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3350 legitimate_pic_operand_p (rtx x)
3352 if (pic_address_needs_scratch (x))
3354 if (sparc_tls_referenced_p (x))
3359 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3361 && INTVAL (X) >= -0x1000 \
3362 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3364 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3366 && INTVAL (X) >= -0x1000 \
3367 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3369 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3371 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3372 ordinarily. This changes a bit when generating PIC. */
3375 sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3377 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3379 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3381 else if (GET_CODE (addr) == PLUS)
3383 rs1 = XEXP (addr, 0);
3384 rs2 = XEXP (addr, 1);
3386 /* Canonicalize. REG comes first, if there are no regs,
3387 LO_SUM comes first. */
3389 && GET_CODE (rs1) != SUBREG
3391 || GET_CODE (rs2) == SUBREG
3392 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3394 rs1 = XEXP (addr, 1);
3395 rs2 = XEXP (addr, 0);
3399 && rs1 == pic_offset_table_rtx
3401 && GET_CODE (rs2) != SUBREG
3402 && GET_CODE (rs2) != LO_SUM
3403 && GET_CODE (rs2) != MEM
3404 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
3405 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3406 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3408 || GET_CODE (rs1) == SUBREG)
3409 && RTX_OK_FOR_OFFSET_P (rs2, mode)))
3414 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3415 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3417 /* We prohibit REG + REG for TFmode when there are no quad move insns
3418 and we consequently need to split. We do this because REG+REG
3419 is not an offsettable address. If we get the situation in reload
3420 where source and destination of a movtf pattern are both MEMs with
3421 REG+REG address, then only one of them gets converted to an
3422 offsettable address. */
3424 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3427 /* We prohibit REG + REG on ARCH32 if not optimizing for
3428 DFmode/DImode because then mem_min_alignment is likely to be zero
3429 after reload and the forced split would lack a matching splitter
3431 if (TARGET_ARCH32 && !optimize
3432 && (mode == DFmode || mode == DImode))
3435 else if (USE_AS_OFFSETABLE_LO10
3436 && GET_CODE (rs1) == LO_SUM
3438 && ! TARGET_CM_MEDMID
3439 && RTX_OK_FOR_OLO10_P (rs2, mode))
3442 imm1 = XEXP (rs1, 1);
3443 rs1 = XEXP (rs1, 0);
3444 if (!CONSTANT_P (imm1)
3445 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3449 else if (GET_CODE (addr) == LO_SUM)
3451 rs1 = XEXP (addr, 0);
3452 imm1 = XEXP (addr, 1);
3454 if (!CONSTANT_P (imm1)
3455 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3458 /* We can't allow TFmode in 32-bit mode, because an offset greater
3459 than the alignment (8) may cause the LO_SUM to overflow. */
3460 if (mode == TFmode && TARGET_ARCH32)
3463 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3468 if (GET_CODE (rs1) == SUBREG)
3469 rs1 = SUBREG_REG (rs1);
3475 if (GET_CODE (rs2) == SUBREG)
3476 rs2 = SUBREG_REG (rs2);
3483 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3484 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3489 if ((REGNO (rs1) >= 32
3490 && REGNO (rs1) != FRAME_POINTER_REGNUM
3491 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3493 && (REGNO (rs2) >= 32
3494 && REGNO (rs2) != FRAME_POINTER_REGNUM
3495 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3501 /* Return the SYMBOL_REF for the tls_get_addr function. */
3503 static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
3506 sparc_tls_get_addr (void)
3508 if (!sparc_tls_symbol)
3509 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3511 return sparc_tls_symbol;
3514 /* Return the Global Offset Table to be used in TLS mode. */
3517 sparc_tls_got (void)
3519 /* In PIC mode, this is just the PIC offset table. */
3522 crtl->uses_pic_offset_table = 1;
3523 return pic_offset_table_rtx;
3526 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3527 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3528 if (TARGET_SUN_TLS && TARGET_ARCH32)
3530 load_got_register ();
3531 return global_offset_table_rtx;
3534 /* In all other cases, we load a new pseudo with the GOT symbol. */
3535 return copy_to_reg (sparc_got ());
3538 /* Return true if X contains a thread-local symbol. */
3541 sparc_tls_referenced_p (rtx x)
3543 if (!TARGET_HAVE_TLS)
3546 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
3547 x = XEXP (XEXP (x, 0), 0);
3549 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
3552 /* That's all we handle in sparc_legitimize_tls_address for now. */
3556 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3557 this (thread-local) address. */
3560 sparc_legitimize_tls_address (rtx addr)
3562 rtx temp1, temp2, temp3, ret, o0, got, insn;
3564 gcc_assert (can_create_pseudo_p ());
3566 if (GET_CODE (addr) == SYMBOL_REF)
3567 switch (SYMBOL_REF_TLS_MODEL (addr))
3569 case TLS_MODEL_GLOBAL_DYNAMIC:
3571 temp1 = gen_reg_rtx (SImode);
3572 temp2 = gen_reg_rtx (SImode);
3573 ret = gen_reg_rtx (Pmode);
3574 o0 = gen_rtx_REG (Pmode, 8);
3575 got = sparc_tls_got ();
3576 emit_insn (gen_tgd_hi22 (temp1, addr));
3577 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3580 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3581 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3586 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3587 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3590 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3591 insn = get_insns ();
3593 emit_libcall_block (insn, ret, o0, addr);
3596 case TLS_MODEL_LOCAL_DYNAMIC:
3598 temp1 = gen_reg_rtx (SImode);
3599 temp2 = gen_reg_rtx (SImode);
3600 temp3 = gen_reg_rtx (Pmode);
3601 ret = gen_reg_rtx (Pmode);
3602 o0 = gen_rtx_REG (Pmode, 8);
3603 got = sparc_tls_got ();
3604 emit_insn (gen_tldm_hi22 (temp1));
3605 emit_insn (gen_tldm_lo10 (temp2, temp1));
3608 emit_insn (gen_tldm_add32 (o0, got, temp2));
3609 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3614 emit_insn (gen_tldm_add64 (o0, got, temp2));
3615 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3618 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3619 insn = get_insns ();
3621 emit_libcall_block (insn, temp3, o0,
3622 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3623 UNSPEC_TLSLD_BASE));
3624 temp1 = gen_reg_rtx (SImode);
3625 temp2 = gen_reg_rtx (SImode);
3626 emit_insn (gen_tldo_hix22 (temp1, addr));
3627 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3629 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3631 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3634 case TLS_MODEL_INITIAL_EXEC:
3635 temp1 = gen_reg_rtx (SImode);
3636 temp2 = gen_reg_rtx (SImode);
3637 temp3 = gen_reg_rtx (Pmode);
3638 got = sparc_tls_got ();
3639 emit_insn (gen_tie_hi22 (temp1, addr));
3640 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3642 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3644 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3647 ret = gen_reg_rtx (Pmode);
3649 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3652 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3656 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3659 case TLS_MODEL_LOCAL_EXEC:
3660 temp1 = gen_reg_rtx (Pmode);
3661 temp2 = gen_reg_rtx (Pmode);
3664 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3665 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3669 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3670 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3672 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3679 else if (GET_CODE (addr) == CONST)
3683 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
3685 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
3686 offset = XEXP (XEXP (addr, 0), 1);
3688 base = force_operand (base, NULL_RTX);
3689 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
3690 offset = force_reg (Pmode, offset);
3691 ret = gen_rtx_PLUS (Pmode, base, offset);
3695 gcc_unreachable (); /* for now ... */
3700 /* Legitimize PIC addresses. If the address is already position-independent,
3701 we return ORIG. Newly generated position-independent addresses go into a
3702 reg. This is REG if nonzero, otherwise we allocate register(s) as
3706 sparc_legitimize_pic_address (rtx orig, rtx reg)
3708 bool gotdata_op = false;
3710 if (GET_CODE (orig) == SYMBOL_REF
3711 /* See the comment in sparc_expand_move. */
3712 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
3714 rtx pic_ref, address;
3719 gcc_assert (can_create_pseudo_p ());
3720 reg = gen_reg_rtx (Pmode);
3725 /* If not during reload, allocate another temp reg here for loading
3726 in the address, so that these instructions can be optimized
3728 rtx temp_reg = (! can_create_pseudo_p ()
3729 ? reg : gen_reg_rtx (Pmode));
3731 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3732 won't get confused into thinking that these two instructions
3733 are loading in the true address of the symbol. If in the
3734 future a PIC rtx exists, that should be used instead. */
3737 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3738 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3742 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3743 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3751 crtl->uses_pic_offset_table = 1;
3755 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
3756 pic_offset_table_rtx,
3759 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
3760 pic_offset_table_rtx,
3766 = gen_const_mem (Pmode,
3767 gen_rtx_PLUS (Pmode,
3768 pic_offset_table_rtx, address));
3769 insn = emit_move_insn (reg, pic_ref);
3772 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3774 set_unique_reg_note (insn, REG_EQUAL, orig);
3777 else if (GET_CODE (orig) == CONST)
3781 if (GET_CODE (XEXP (orig, 0)) == PLUS
3782 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3787 gcc_assert (can_create_pseudo_p ());
3788 reg = gen_reg_rtx (Pmode);
3791 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3792 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
3793 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
3794 base == reg ? NULL_RTX : reg);
3796 if (GET_CODE (offset) == CONST_INT)
3798 if (SMALL_INT (offset))
3799 return plus_constant (base, INTVAL (offset));
3800 else if (can_create_pseudo_p ())
3801 offset = force_reg (Pmode, offset);
3803 /* If we reach here, then something is seriously wrong. */
3806 return gen_rtx_PLUS (Pmode, base, offset);
3808 else if (GET_CODE (orig) == LABEL_REF)
3809 /* ??? We ought to be checking that the register is live instead, in case
3810 it is eliminated. */
3811 crtl->uses_pic_offset_table = 1;
3816 /* Try machine-dependent ways of modifying an illegitimate address X
3817 to be legitimate. If we find one, return the new, valid address.
3819 OLDX is the address as it was before break_out_memory_refs was called.
3820 In some cases it is useful to look at this to decide what needs to be done.
3822 MODE is the mode of the operand pointed to by X.
3824 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3827 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3828 enum machine_mode mode)
3832 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3833 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3834 force_operand (XEXP (x, 0), NULL_RTX));
3835 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3836 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3837 force_operand (XEXP (x, 1), NULL_RTX));
3838 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3839 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3841 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3842 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3843 force_operand (XEXP (x, 1), NULL_RTX));
3845 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
3848 if (sparc_tls_referenced_p (x))
3849 x = sparc_legitimize_tls_address (x);
3851 x = sparc_legitimize_pic_address (x, NULL_RTX);
3852 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3853 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3854 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3855 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3856 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3857 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3858 else if (GET_CODE (x) == SYMBOL_REF
3859 || GET_CODE (x) == CONST
3860 || GET_CODE (x) == LABEL_REF)
3861 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3866 /* Delegitimize an address that was legitimized by the above function. */
3869 sparc_delegitimize_address (rtx x)
3871 x = delegitimize_mem_from_attrs (x);
3873 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
3874 switch (XINT (XEXP (x, 1), 1))
3876 case UNSPEC_MOVE_PIC:
3878 x = XVECEXP (XEXP (x, 1), 0, 0);
3879 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3885 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3886 if (GET_CODE (x) == MINUS
3887 && REG_P (XEXP (x, 0))
3888 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
3889 && GET_CODE (XEXP (x, 1)) == LO_SUM
3890 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
3891 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
3893 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
3894 gcc_assert (GET_CODE (x) == LABEL_REF);
3900 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3901 replace the input X, or the original X if no replacement is called for.
3902 The output parameter *WIN is 1 if the calling macro should goto WIN,
3905 For SPARC, we wish to handle addresses by splitting them into
3906 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3907 This cuts the number of extra insns by one.
3909 Do nothing when generating PIC code and the address is a symbolic
3910 operand or requires a scratch register. */
3913 sparc_legitimize_reload_address (rtx x, enum machine_mode mode,
3914 int opnum, int type,
3915 int ind_levels ATTRIBUTE_UNUSED, int *win)
3917 /* Decompose SImode constants into HIGH+LO_SUM. */
3919 && (mode != TFmode || TARGET_ARCH64)
3920 && GET_MODE (x) == SImode
3921 && GET_CODE (x) != LO_SUM
3922 && GET_CODE (x) != HIGH
3923 && sparc_cmodel <= CM_MEDLOW
3925 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
3927 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
3928 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3929 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3930 opnum, (enum reload_type)type);
3935 /* We have to recognize what we have already generated above. */
3936 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
3938 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3939 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3940 opnum, (enum reload_type)type);
3949 /* Return true if ADDR (a legitimate address expression)
3950 has an effect that depends on the machine mode it is used for.
3956 is not equivalent to
3958 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3960 because [%l7+a+1] is interpreted as the address of (a+1). */
3964 sparc_mode_dependent_address_p (const_rtx addr)
3966 if (flag_pic && GET_CODE (addr) == PLUS)
3968 rtx op0 = XEXP (addr, 0);
3969 rtx op1 = XEXP (addr, 1);
3970 if (op0 == pic_offset_table_rtx
3971 && symbolic_operand (op1, VOIDmode))
3978 #ifdef HAVE_GAS_HIDDEN
3979 # define USE_HIDDEN_LINKONCE 1
3981 # define USE_HIDDEN_LINKONCE 0
3985 get_pc_thunk_name (char name[32], unsigned int regno)
3987 const char *reg_name = reg_names[regno];
3989 /* Skip the leading '%' as that cannot be used in a
3993 if (USE_HIDDEN_LINKONCE)
3994 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
3996 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
3999 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4002 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
4004 int orig_flag_pic = flag_pic;
4007 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4010 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
4012 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
4013 flag_pic = orig_flag_pic;
4018 /* Emit code to load the GOT register. */
4021 load_got_register (void)
4023 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4024 if (!global_offset_table_rtx)
4025 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
4027 if (TARGET_VXWORKS_RTP)
4028 emit_insn (gen_vxworks_load_got ());
4031 /* The GOT symbol is subject to a PC-relative relocation so we need a
4032 helper function to add the PC value and thus get the final value. */
4033 if (!got_helper_rtx)
4036 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
4037 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4040 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
4042 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
4045 /* Need to emit this whether or not we obey regdecls,
4046 since setjmp/longjmp can cause life info to screw up.
4047 ??? In the case where we don't obey regdecls, this is not sufficient
4048 since we may not fall out the bottom. */
4049 emit_use (global_offset_table_rtx);
4052 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4053 address of the call target. */
4056 sparc_emit_call_insn (rtx pat, rtx addr)
4060 insn = emit_call_insn (pat);
4062 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4063 if (TARGET_VXWORKS_RTP
4065 && GET_CODE (addr) == SYMBOL_REF
4066 && (SYMBOL_REF_DECL (addr)
4067 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
4068 : !SYMBOL_REF_LOCAL_P (addr)))
4070 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
4071 crtl->uses_pic_offset_table = 1;
4075 /* Return 1 if RTX is a MEM which is known to be aligned to at
4076 least a DESIRED byte boundary. */
4079 mem_min_alignment (rtx mem, int desired)
4081 rtx addr, base, offset;
4083 /* If it's not a MEM we can't accept it. */
4084 if (GET_CODE (mem) != MEM)
4088 if (!TARGET_UNALIGNED_DOUBLES
4089 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
4092 /* ??? The rest of the function predates MEM_ALIGN so
4093 there is probably a bit of redundancy. */
4094 addr = XEXP (mem, 0);
4095 base = offset = NULL_RTX;
4096 if (GET_CODE (addr) == PLUS)
4098 if (GET_CODE (XEXP (addr, 0)) == REG)
4100 base = XEXP (addr, 0);
4102 /* What we are saying here is that if the base
4103 REG is aligned properly, the compiler will make
4104 sure any REG based index upon it will be so
4106 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4107 offset = XEXP (addr, 1);
4109 offset = const0_rtx;
4112 else if (GET_CODE (addr) == REG)
4115 offset = const0_rtx;
4118 if (base != NULL_RTX)
4120 int regno = REGNO (base);
4122 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
4124 /* Check if the compiler has recorded some information
4125 about the alignment of the base REG. If reload has
4126 completed, we already matched with proper alignments.
4127 If not running global_alloc, reload might give us
4128 unaligned pointer to local stack though. */
4130 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4131 || (optimize && reload_completed))
4132 && (INTVAL (offset) & (desired - 1)) == 0)
4137 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4141 else if (! TARGET_UNALIGNED_DOUBLES
4142 || CONSTANT_P (addr)
4143 || GET_CODE (addr) == LO_SUM)
4145 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4146 is true, in which case we can only assume that an access is aligned if
4147 it is to a constant address, or the address involves a LO_SUM. */
4151 /* An obviously unaligned address. */
4156 /* Vectors to keep interesting information about registers where it can easily
4157 be got. We used to use the actual mode value as the bit number, but there
4158 are more than 32 modes now. Instead we use two tables: one indexed by
4159 hard register number, and one indexed by mode. */
4161 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4162 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4163 mapped into one sparc_mode_class mode. */
4165 enum sparc_mode_class {
4166 S_MODE, D_MODE, T_MODE, O_MODE,
4167 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4171 /* Modes for single-word and smaller quantities. */
4172 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4174 /* Modes for double-word and smaller quantities. */
4175 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4177 /* Modes for quad-word and smaller quantities. */
4178 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4180 /* Modes for 8-word and smaller quantities. */
4181 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4183 /* Modes for single-float quantities. We must allow any single word or
4184 smaller quantity. This is because the fix/float conversion instructions
4185 take integer inputs/outputs from the float registers. */
4186 #define SF_MODES (S_MODES)
4188 /* Modes for double-float and smaller quantities. */
4189 #define DF_MODES (D_MODES)
4191 /* Modes for quad-float and smaller quantities. */
4192 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4194 /* Modes for quad-float pairs and smaller quantities. */
4195 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4197 /* Modes for double-float only quantities. */
4198 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4200 /* Modes for quad-float and double-float only quantities. */
4201 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4203 /* Modes for quad-float pairs and double-float only quantities. */
4204 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4206 /* Modes for condition codes. */
4207 #define CC_MODES (1 << (int) CC_MODE)
4208 #define CCFP_MODES (1 << (int) CCFP_MODE)
4210 /* Value is 1 if register/mode pair is acceptable on sparc.
4211 The funny mixture of D and T modes is because integer operations
4212 do not specially operate on tetra quantities, so non-quad-aligned
4213 registers can hold quadword quantities (except %o4 and %i4 because
4214 they cross fixed registers). */
4216 /* This points to either the 32 bit or the 64 bit version. */
4217 const int *hard_regno_mode_classes;
4219 static const int hard_32bit_mode_classes[] = {
4220 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4221 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4222 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4223 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4225 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4226 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4227 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4228 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4230 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4231 and none can hold SFmode/SImode values. */
4232 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4233 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4234 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4235 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4238 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4240 /* %icc, %sfp, %gsr */
4241 CC_MODES, 0, D_MODES
4244 static const int hard_64bit_mode_classes[] = {
4245 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4246 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4247 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4248 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4250 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4251 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4252 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4253 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4255 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4256 and none can hold SFmode/SImode values. */
4257 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4258 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4259 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4260 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4263 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4265 /* %icc, %sfp, %gsr */
4266 CC_MODES, 0, D_MODES
4269 int sparc_mode_class [NUM_MACHINE_MODES];
4271 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4274 sparc_init_modes (void)
4278 for (i = 0; i < NUM_MACHINE_MODES; i++)
4280 switch (GET_MODE_CLASS (i))
4283 case MODE_PARTIAL_INT:
4284 case MODE_COMPLEX_INT:
4285 if (GET_MODE_SIZE (i) <= 4)
4286 sparc_mode_class[i] = 1 << (int) S_MODE;
4287 else if (GET_MODE_SIZE (i) == 8)
4288 sparc_mode_class[i] = 1 << (int) D_MODE;
4289 else if (GET_MODE_SIZE (i) == 16)
4290 sparc_mode_class[i] = 1 << (int) T_MODE;
4291 else if (GET_MODE_SIZE (i) == 32)
4292 sparc_mode_class[i] = 1 << (int) O_MODE;
4294 sparc_mode_class[i] = 0;
4296 case MODE_VECTOR_INT:
4297 if (GET_MODE_SIZE (i) <= 4)
4298 sparc_mode_class[i] = 1 << (int)SF_MODE;
4299 else if (GET_MODE_SIZE (i) == 8)
4300 sparc_mode_class[i] = 1 << (int)DF_MODE;
4303 case MODE_COMPLEX_FLOAT:
4304 if (GET_MODE_SIZE (i) <= 4)
4305 sparc_mode_class[i] = 1 << (int) SF_MODE;
4306 else if (GET_MODE_SIZE (i) == 8)
4307 sparc_mode_class[i] = 1 << (int) DF_MODE;
4308 else if (GET_MODE_SIZE (i) == 16)
4309 sparc_mode_class[i] = 1 << (int) TF_MODE;
4310 else if (GET_MODE_SIZE (i) == 32)
4311 sparc_mode_class[i] = 1 << (int) OF_MODE;
4313 sparc_mode_class[i] = 0;
4316 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4317 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4319 sparc_mode_class[i] = 1 << (int) CC_MODE;
4322 sparc_mode_class[i] = 0;
4328 hard_regno_mode_classes = hard_64bit_mode_classes;
4330 hard_regno_mode_classes = hard_32bit_mode_classes;
4332 /* Initialize the array used by REGNO_REG_CLASS. */
4333 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4335 if (i < 16 && TARGET_V8PLUS)
4336 sparc_regno_reg_class[i] = I64_REGS;
4337 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4338 sparc_regno_reg_class[i] = GENERAL_REGS;
4340 sparc_regno_reg_class[i] = FP_REGS;
4342 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4344 sparc_regno_reg_class[i] = FPCC_REGS;
4346 sparc_regno_reg_class[i] = NO_REGS;
4350 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4353 save_global_or_fp_reg_p (unsigned int regno,
4354 int leaf_function ATTRIBUTE_UNUSED)
4356 return !call_used_regs[regno] && df_regs_ever_live_p (regno);
4359 /* Return whether the return address register (%i7) is needed. */
4362 return_addr_reg_needed_p (int leaf_function)
4364 /* If it is live, for example because of __builtin_return_address (0). */
4365 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM))
4368 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4370 /* Loading the GOT register clobbers %o7. */
4371 || crtl->uses_pic_offset_table
4372 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM))
4378 /* Return whether REGNO, a local or in register, must be saved/restored. */
4381 save_local_or_in_reg_p (unsigned int regno, int leaf_function)
4383 /* General case: call-saved registers live at some point. */
4384 if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
4387 /* Frame pointer register (%fp) if needed. */
4388 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
4391 /* Return address register (%i7) if needed. */
4392 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function))
4395 /* GOT register (%l7) if needed. */
4396 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
4399 /* If the function accesses prior frames, the frame pointer and the return
4400 address of the previous frame must be saved on the stack. */
4401 if (crtl->accesses_prior_frames
4402 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM))
4408 /* Compute the frame size required by the function. This function is called
4409 during the reload pass and also by sparc_expand_prologue. */
4412 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4414 HOST_WIDE_INT frame_size, apparent_frame_size;
4415 int args_size, n_global_fp_regs = 0;
4416 bool save_local_in_regs_p = false;
4419 /* If the function allocates dynamic stack space, the dynamic offset is
4420 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4421 if (leaf_function && !cfun->calls_alloca)
4424 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl);
4426 /* Calculate space needed for global registers. */
4428 for (i = 0; i < 8; i++)
4429 if (save_global_or_fp_reg_p (i, 0))
4430 n_global_fp_regs += 2;
4432 for (i = 0; i < 8; i += 2)
4433 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4434 n_global_fp_regs += 2;
4436 /* In the flat window model, find out which local and in registers need to
4437 be saved. We don't reserve space in the current frame for them as they
4438 will be spilled into the register window save area of the caller's frame.
4439 However, as soon as we use this register window save area, we must create
4440 that of the current frame to make it the live one. */
4442 for (i = 16; i < 32; i++)
4443 if (save_local_or_in_reg_p (i, leaf_function))
4445 save_local_in_regs_p = true;
4449 /* Calculate space needed for FP registers. */
4450 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4451 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4452 n_global_fp_regs += 2;
4455 && n_global_fp_regs == 0
4457 && !save_local_in_regs_p)
4458 frame_size = apparent_frame_size = 0;
4461 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4462 apparent_frame_size = (size - STARTING_FRAME_OFFSET + 7) & -8;
4463 apparent_frame_size += n_global_fp_regs * 4;
4465 /* We need to add the size of the outgoing argument area. */
4466 frame_size = apparent_frame_size + ((args_size + 7) & -8);
4468 /* And that of the register window save area. */
4469 frame_size += FIRST_PARM_OFFSET (cfun->decl);
4471 /* Finally, bump to the appropriate alignment. */
4472 frame_size = SPARC_STACK_ALIGN (frame_size);
4475 /* Set up values for use in prologue and epilogue. */
4476 sparc_frame_size = frame_size;
4477 sparc_apparent_frame_size = apparent_frame_size;
4478 sparc_n_global_fp_regs = n_global_fp_regs;
4479 sparc_save_local_in_regs_p = save_local_in_regs_p;
4484 /* Output any necessary .register pseudo-ops. */
4487 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4489 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4495 /* Check if %g[2367] were used without
4496 .register being printed for them already. */
4497 for (i = 2; i < 8; i++)
4499 if (df_regs_ever_live_p (i)
4500 && ! sparc_hard_reg_printed [i])
4502 sparc_hard_reg_printed [i] = 1;
4503 /* %g7 is used as TLS base register, use #ignore
4504 for it instead of #scratch. */
4505 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
4506 i == 7 ? "ignore" : "scratch");
4513 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4515 #if PROBE_INTERVAL > 4096
4516 #error Cannot use indexed addressing mode for stack probing
4519 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4520 inclusive. These are offsets from the current stack pointer.
4522 Note that we don't use the REG+REG addressing mode for the probes because
4523 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4524 so the advantages of having a single code win here. */
4527 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
4529 rtx g1 = gen_rtx_REG (Pmode, 1);
4531 /* See if we have a constant small number of probes to generate. If so,
4532 that's the easy case. */
4533 if (size <= PROBE_INTERVAL)
4535 emit_move_insn (g1, GEN_INT (first));
4536 emit_insn (gen_rtx_SET (VOIDmode, g1,
4537 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4538 emit_stack_probe (plus_constant (g1, -size));
4541 /* The run-time loop is made up of 10 insns in the generic case while the
4542 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4543 else if (size <= 5 * PROBE_INTERVAL)
4547 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
4548 emit_insn (gen_rtx_SET (VOIDmode, g1,
4549 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4550 emit_stack_probe (g1);
4552 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4553 it exceeds SIZE. If only two probes are needed, this will not
4554 generate any code. Then probe at FIRST + SIZE. */
4555 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
4557 emit_insn (gen_rtx_SET (VOIDmode, g1,
4558 plus_constant (g1, -PROBE_INTERVAL)));
4559 emit_stack_probe (g1);
4562 emit_stack_probe (plus_constant (g1, (i - PROBE_INTERVAL) - size));
4565 /* Otherwise, do the same as above, but in a loop. Note that we must be
4566 extra careful with variables wrapping around because we might be at
4567 the very top (or the very bottom) of the address space and we have
4568 to be able to handle this case properly; in particular, we use an
4569 equality test for the loop condition. */
4572 HOST_WIDE_INT rounded_size;
4573 rtx g4 = gen_rtx_REG (Pmode, 4);
4575 emit_move_insn (g1, GEN_INT (first));
4578 /* Step 1: round SIZE to the previous multiple of the interval. */
4580 rounded_size = size & -PROBE_INTERVAL;
4581 emit_move_insn (g4, GEN_INT (rounded_size));
4584 /* Step 2: compute initial and final value of the loop counter. */
4586 /* TEST_ADDR = SP + FIRST. */
4587 emit_insn (gen_rtx_SET (VOIDmode, g1,
4588 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4590 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4591 emit_insn (gen_rtx_SET (VOIDmode, g4, gen_rtx_MINUS (Pmode, g1, g4)));
4596 while (TEST_ADDR != LAST_ADDR)
4598 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4602 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4603 until it is equal to ROUNDED_SIZE. */
4606 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
4608 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
4611 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4612 that SIZE is equal to ROUNDED_SIZE. */
4614 if (size != rounded_size)
4615 emit_stack_probe (plus_constant (g4, rounded_size - size));
4618 /* Make sure nothing is scheduled before we are done. */
4619 emit_insn (gen_blockage ());
4622 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4623 absolute addresses. */
4626 output_probe_stack_range (rtx reg1, rtx reg2)
4628 static int labelno = 0;
4629 char loop_lab[32], end_lab[32];
4632 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
4633 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
4635 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
4637 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4640 output_asm_insn ("cmp\t%0, %1", xops);
4642 fputs ("\tbe,pn\t%xcc,", asm_out_file);
4644 fputs ("\tbe\t", asm_out_file);
4645 assemble_name_raw (asm_out_file, end_lab);
4646 fputc ('\n', asm_out_file);
4648 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4649 xops[1] = GEN_INT (-PROBE_INTERVAL);
4650 output_asm_insn (" add\t%0, %1, %0", xops);
4652 /* Probe at TEST_ADDR and branch. */
4654 fputs ("\tba,pt\t%xcc,", asm_out_file);
4656 fputs ("\tba\t", asm_out_file);
4657 assemble_name_raw (asm_out_file, loop_lab);
4658 fputc ('\n', asm_out_file);
4659 xops[1] = GEN_INT (SPARC_STACK_BIAS);
4660 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
4662 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
4667 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4668 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4669 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4670 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4671 the action to be performed if it returns false. Return the new offset. */
4673 typedef bool (*sorr_pred_t) (unsigned int, int);
4674 typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t;
4677 emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base,
4678 int offset, int leaf_function, sorr_pred_t save_p,
4679 sorr_act_t action_true, sorr_act_t action_false)
4684 if (TARGET_ARCH64 && high <= 32)
4688 for (i = low; i < high; i++)
4690 if (save_p (i, leaf_function))
4692 mem = gen_frame_mem (DImode, plus_constant (base, offset));
4693 if (action_true == SORR_SAVE)
4695 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4696 RTX_FRAME_RELATED_P (insn) = 1;
4698 else /* action_true == SORR_RESTORE */
4700 /* The frame pointer must be restored last since its old
4701 value may be used as base address for the frame. This
4702 is problematic in 64-bit mode only because of the lack
4703 of double-word load instruction. */
4704 if (i == HARD_FRAME_POINTER_REGNUM)
4707 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4711 else if (action_false == SORR_ADVANCE)
4717 mem = gen_frame_mem (DImode, plus_constant (base, fp_offset));
4718 emit_move_insn (hard_frame_pointer_rtx, mem);
4723 for (i = low; i < high; i += 2)
4725 bool reg0 = save_p (i, leaf_function);
4726 bool reg1 = save_p (i + 1, leaf_function);
4727 enum machine_mode mode;
4732 mode = i < 32 ? DImode : DFmode;
4737 mode = i < 32 ? SImode : SFmode;
4742 mode = i < 32 ? SImode : SFmode;
4748 if (action_false == SORR_ADVANCE)
4753 mem = gen_frame_mem (mode, plus_constant (base, offset));
4754 if (action_true == SORR_SAVE)
4756 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4757 RTX_FRAME_RELATED_P (insn) = 1;
4761 mem = gen_frame_mem (SImode, plus_constant (base, offset));
4762 set1 = gen_rtx_SET (VOIDmode, mem,
4763 gen_rtx_REG (SImode, regno));
4764 RTX_FRAME_RELATED_P (set1) = 1;
4766 = gen_frame_mem (SImode, plus_constant (base, offset + 4));
4767 set2 = gen_rtx_SET (VOIDmode, mem,
4768 gen_rtx_REG (SImode, regno + 1));
4769 RTX_FRAME_RELATED_P (set2) = 1;
4770 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4771 gen_rtx_PARALLEL (VOIDmode,
4772 gen_rtvec (2, set1, set2)));
4775 else /* action_true == SORR_RESTORE */
4776 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4778 /* Always preserve double-word alignment. */
4779 offset = (offset + 8) & -8;
4786 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4789 emit_adjust_base_to_offset (rtx base, int offset)
4791 /* ??? This might be optimized a little as %g1 might already have a
4792 value close enough that a single add insn will do. */
4793 /* ??? Although, all of this is probably only a temporary fix because
4794 if %g1 can hold a function result, then sparc_expand_epilogue will
4795 lose (the result will be clobbered). */
4796 rtx new_base = gen_rtx_REG (Pmode, 1);
4797 emit_move_insn (new_base, GEN_INT (offset));
4798 emit_insn (gen_rtx_SET (VOIDmode,
4799 new_base, gen_rtx_PLUS (Pmode, base, new_base)));
4803 /* Emit code to save/restore call-saved global and FP registers. */
4806 emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action)
4808 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095)
4810 base = emit_adjust_base_to_offset (base, offset);
4815 = emit_save_or_restore_regs (0, 8, base, offset, 0,
4816 save_global_or_fp_reg_p, action, SORR_NONE);
4817 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0,
4818 save_global_or_fp_reg_p, action, SORR_NONE);
4821 /* Emit code to save/restore call-saved local and in registers. */
4824 emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action)
4826 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095)
4828 base = emit_adjust_base_to_offset (base, offset);
4832 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p,
4833 save_local_or_in_reg_p, action, SORR_ADVANCE);
4836 /* Emit a window_save insn. */
4839 emit_window_save (rtx increment)
4841 rtx insn = emit_insn (gen_window_save (increment));
4842 RTX_FRAME_RELATED_P (insn) = 1;
4844 /* The incoming return address (%o7) is saved in %i7. */
4845 add_reg_note (insn, REG_CFA_REGISTER,
4846 gen_rtx_SET (VOIDmode,
4847 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM),
4849 INCOMING_RETURN_ADDR_REGNUM)));
4851 /* The window save event. */
4852 add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx);
4854 /* The CFA is %fp, the hard frame pointer. */
4855 add_reg_note (insn, REG_CFA_DEF_CFA,
4856 plus_constant (hard_frame_pointer_rtx,
4857 INCOMING_FRAME_SP_OFFSET));
4862 /* Generate an increment for the stack pointer. */
4865 gen_stack_pointer_inc (rtx increment)
4867 return gen_rtx_SET (VOIDmode,
4869 gen_rtx_PLUS (Pmode,
4874 /* Generate a decrement for the stack pointer. */
4877 gen_stack_pointer_dec (rtx decrement)
4879 return gen_rtx_SET (VOIDmode,
4881 gen_rtx_MINUS (Pmode,
4886 /* Expand the function prologue. The prologue is responsible for reserving
4887 storage for the frame, saving the call-saved registers and loading the
4888 GOT register if needed. */
4891 sparc_expand_prologue (void)
4896 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4897 on the final value of the flag means deferring the prologue/epilogue
4898 expansion until just before the second scheduling pass, which is too
4899 late to emit multiple epilogues or return insns.
4901 Of course we are making the assumption that the value of the flag
4902 will not change between now and its final value. Of the three parts
4903 of the formula, only the last one can reasonably vary. Let's take a
4904 closer look, after assuming that the first two ones are set to true
4905 (otherwise the last value is effectively silenced).
4907 If only_leaf_regs_used returns false, the global predicate will also
4908 be false so the actual frame size calculated below will be positive.
4909 As a consequence, the save_register_window insn will be emitted in
4910 the instruction stream; now this insn explicitly references %fp
4911 which is not a leaf register so only_leaf_regs_used will always
4912 return false subsequently.
4914 If only_leaf_regs_used returns true, we hope that the subsequent
4915 optimization passes won't cause non-leaf registers to pop up. For
4916 example, the regrename pass has special provisions to not rename to
4917 non-leaf registers in a leaf function. */
4918 sparc_leaf_function_p
4919 = optimize > 0 && current_function_is_leaf && only_leaf_regs_used ();
4921 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4923 if (flag_stack_usage_info)
4924 current_function_static_stack_size = size;
4926 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4927 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
4931 else if (sparc_leaf_function_p)
4933 rtx size_int_rtx = GEN_INT (-size);
4936 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
4937 else if (size <= 8192)
4939 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4940 /* %sp is still the CFA register. */
4941 RTX_FRAME_RELATED_P (insn) = 1;
4942 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4946 rtx size_rtx = gen_rtx_REG (Pmode, 1);
4947 emit_move_insn (size_rtx, size_int_rtx);
4948 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
4949 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4950 gen_stack_pointer_inc (size_int_rtx));
4953 RTX_FRAME_RELATED_P (insn) = 1;
4957 rtx size_int_rtx = GEN_INT (-size);
4960 emit_window_save (size_int_rtx);
4961 else if (size <= 8192)
4963 emit_window_save (GEN_INT (-4096));
4964 /* %sp is not the CFA register anymore. */
4965 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4969 rtx size_rtx = gen_rtx_REG (Pmode, 1);
4970 emit_move_insn (size_rtx, size_int_rtx);
4971 emit_window_save (size_rtx);
4975 if (sparc_leaf_function_p)
4977 sparc_frame_base_reg = stack_pointer_rtx;
4978 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
4982 sparc_frame_base_reg = hard_frame_pointer_rtx;
4983 sparc_frame_base_offset = SPARC_STACK_BIAS;
4986 if (sparc_n_global_fp_regs > 0)
4987 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4988 sparc_frame_base_offset
4989 - sparc_apparent_frame_size,
4992 /* Load the GOT register if needed. */
4993 if (crtl->uses_pic_offset_table)
4994 load_got_register ();
4996 /* Advertise that the data calculated just above are now valid. */
4997 sparc_prologue_data_valid_p = true;
5000 /* Expand the function prologue. The prologue is responsible for reserving
5001 storage for the frame, saving the call-saved registers and loading the
5002 GOT register if needed. */
5005 sparc_flat_expand_prologue (void)
5010 sparc_leaf_function_p = optimize > 0 && current_function_is_leaf;
5012 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
5014 if (flag_stack_usage_info)
5015 current_function_static_stack_size = size;
5017 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
5018 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
5020 if (sparc_save_local_in_regs_p)
5021 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS,
5028 rtx size_int_rtx, size_rtx;
5030 size_rtx = size_int_rtx = GEN_INT (-size);
5032 /* We establish the frame (i.e. decrement the stack pointer) first, even
5033 if we use a frame pointer, because we cannot clobber any call-saved
5034 registers, including the frame pointer, if we haven't created a new
5035 register save area, for the sake of compatibility with the ABI. */
5037 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
5038 else if (size <= 8192 && !frame_pointer_needed)
5040 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5041 RTX_FRAME_RELATED_P (insn) = 1;
5042 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5046 size_rtx = gen_rtx_REG (Pmode, 1);
5047 emit_move_insn (size_rtx, size_int_rtx);
5048 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
5049 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5050 gen_stack_pointer_inc (size_int_rtx));
5052 RTX_FRAME_RELATED_P (insn) = 1;
5054 /* Ensure nothing is scheduled until after the frame is established. */
5055 emit_insn (gen_blockage ());
5057 if (frame_pointer_needed)
5059 insn = emit_insn (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5060 gen_rtx_MINUS (Pmode,
5063 RTX_FRAME_RELATED_P (insn) = 1;
5065 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5066 gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5067 plus_constant (stack_pointer_rtx,
5071 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5073 rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM);
5074 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
5076 insn = emit_move_insn (i7, o7);
5077 RTX_FRAME_RELATED_P (insn) = 1;
5079 add_reg_note (insn, REG_CFA_REGISTER,
5080 gen_rtx_SET (VOIDmode, i7, o7));
5082 /* Prevent this instruction from ever being considered dead,
5083 even if this function has no epilogue. */
5084 emit_insn (gen_rtx_USE (VOIDmode, i7));
5088 if (frame_pointer_needed)
5090 sparc_frame_base_reg = hard_frame_pointer_rtx;
5091 sparc_frame_base_offset = SPARC_STACK_BIAS;
5095 sparc_frame_base_reg = stack_pointer_rtx;
5096 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5099 if (sparc_n_global_fp_regs > 0)
5100 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5101 sparc_frame_base_offset
5102 - sparc_apparent_frame_size,
5105 /* Load the GOT register if needed. */
5106 if (crtl->uses_pic_offset_table)
5107 load_got_register ();
5109 /* Advertise that the data calculated just above are now valid. */
5110 sparc_prologue_data_valid_p = true;
5113 /* This function generates the assembly code for function entry, which boils
5114 down to emitting the necessary .register directives. */
5117 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5119 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5121 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
5123 sparc_output_scratch_registers (file);
5126 /* Expand the function epilogue, either normal or part of a sibcall.
5127 We emit all the instructions except the return or the call. */
5130 sparc_expand_epilogue (bool for_eh)
5132 HOST_WIDE_INT size = sparc_frame_size;
5134 if (sparc_n_global_fp_regs > 0)
5135 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5136 sparc_frame_base_offset
5137 - sparc_apparent_frame_size,
5140 if (size == 0 || for_eh)
5142 else if (sparc_leaf_function_p)
5145 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
5146 else if (size <= 8192)
5148 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5149 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
5153 rtx reg = gen_rtx_REG (Pmode, 1);
5154 emit_move_insn (reg, GEN_INT (-size));
5155 emit_insn (gen_stack_pointer_dec (reg));
5160 /* Expand the function epilogue, either normal or part of a sibcall.
5161 We emit all the instructions except the return or the call. */
5164 sparc_flat_expand_epilogue (bool for_eh)
5166 HOST_WIDE_INT size = sparc_frame_size;
5168 if (sparc_n_global_fp_regs > 0)
5169 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5170 sparc_frame_base_offset
5171 - sparc_apparent_frame_size,
5174 /* If we have a frame pointer, we'll need both to restore it before the
5175 frame is destroyed and use its current value in destroying the frame.
5176 Since we don't have an atomic way to do that in the flat window model,
5177 we save the current value into a temporary register (%g1). */
5178 if (frame_pointer_needed && !for_eh)
5179 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx);
5181 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5182 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM),
5183 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM));
5185 if (sparc_save_local_in_regs_p)
5186 emit_save_or_restore_local_in_regs (sparc_frame_base_reg,
5187 sparc_frame_base_offset,
5190 if (size == 0 || for_eh)
5192 else if (frame_pointer_needed)
5194 /* Make sure the frame is destroyed after everything else is done. */
5195 emit_insn (gen_blockage ());
5197 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1));
5202 emit_insn (gen_blockage ());
5205 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
5206 else if (size <= 8192)
5208 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5209 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
5213 rtx reg = gen_rtx_REG (Pmode, 1);
5214 emit_move_insn (reg, GEN_INT (-size));
5215 emit_insn (gen_stack_pointer_dec (reg));
5220 /* Return true if it is appropriate to emit `return' instructions in the
5221 body of a function. */
5224 sparc_can_use_return_insn_p (void)
5226 return sparc_prologue_data_valid_p
5227 && sparc_n_global_fp_regs == 0
5229 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p)
5230 : (sparc_frame_size == 0 || !sparc_leaf_function_p);
5233 /* This function generates the assembly code for function exit. */
5236 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5238 /* If the last two instructions of a function are "call foo; dslot;"
5239 the return address might point to the first instruction in the next
5240 function and we have to output a dummy nop for the sake of sane
5241 backtraces in such cases. This is pointless for sibling calls since
5242 the return address is explicitly adjusted. */
5244 rtx insn, last_real_insn;
5246 insn = get_last_insn ();
5248 last_real_insn = prev_real_insn (insn);
5250 && GET_CODE (last_real_insn) == INSN
5251 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
5252 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
5255 && CALL_P (last_real_insn)
5256 && !SIBLING_CALL_P (last_real_insn))
5257 fputs("\tnop\n", file);
5259 sparc_output_deferred_case_vectors ();
5262 /* Output a 'restore' instruction. */
5265 output_restore (rtx pat)
5271 fputs ("\t restore\n", asm_out_file);
5275 gcc_assert (GET_CODE (pat) == SET);
5277 operands[0] = SET_DEST (pat);
5278 pat = SET_SRC (pat);
5280 switch (GET_CODE (pat))
5283 operands[1] = XEXP (pat, 0);
5284 operands[2] = XEXP (pat, 1);
5285 output_asm_insn (" restore %r1, %2, %Y0", operands);
5288 operands[1] = XEXP (pat, 0);
5289 operands[2] = XEXP (pat, 1);
5290 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
5293 operands[1] = XEXP (pat, 0);
5294 gcc_assert (XEXP (pat, 1) == const1_rtx);
5295 output_asm_insn (" restore %r1, %r1, %Y0", operands);
5299 output_asm_insn (" restore %%g0, %1, %Y0", operands);
5304 /* Output a return. */
5307 output_return (rtx insn)
5309 if (crtl->calls_eh_return)
5311 /* If the function uses __builtin_eh_return, the eh_return
5312 machinery occupies the delay slot. */
5313 gcc_assert (!final_sequence);
5315 if (flag_delayed_branch)
5317 if (!TARGET_FLAT && TARGET_V9)
5318 fputs ("\treturn\t%i7+8\n", asm_out_file);
5322 fputs ("\trestore\n", asm_out_file);
5324 fputs ("\tjmp\t%o7+8\n", asm_out_file);
5327 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
5332 fputs ("\trestore\n", asm_out_file);
5334 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file);
5335 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
5338 else if (sparc_leaf_function_p || TARGET_FLAT)
5340 /* This is a leaf or flat function so we don't have to bother restoring
5341 the register window, which frees us from dealing with the convoluted
5342 semantics of restore/return. We simply output the jump to the
5343 return address and the insn in the delay slot (if any). */
5345 return "jmp\t%%o7+%)%#";
5349 /* This is a regular function so we have to restore the register window.
5350 We may have a pending insn for the delay slot, which will be either
5351 combined with the 'restore' instruction or put in the delay slot of
5352 the 'return' instruction. */
5358 delay = NEXT_INSN (insn);
5361 pat = PATTERN (delay);
5363 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
5365 epilogue_renumber (&pat, 0);
5366 return "return\t%%i7+%)%#";
5370 output_asm_insn ("jmp\t%%i7+%)", NULL);
5371 output_restore (pat);
5372 PATTERN (delay) = gen_blockage ();
5373 INSN_CODE (delay) = -1;
5378 /* The delay slot is empty. */
5380 return "return\t%%i7+%)\n\t nop";
5381 else if (flag_delayed_branch)
5382 return "jmp\t%%i7+%)\n\t restore";
5384 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5391 /* Output a sibling call. */
5394 output_sibcall (rtx insn, rtx call_operand)
5398 gcc_assert (flag_delayed_branch);
5400 operands[0] = call_operand;
5402 if (sparc_leaf_function_p || TARGET_FLAT)
5404 /* This is a leaf or flat function so we don't have to bother restoring
5405 the register window. We simply output the jump to the function and
5406 the insn in the delay slot (if any). */
5408 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
5411 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5414 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5415 it into branch if possible. */
5416 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5421 /* This is a regular function so we have to restore the register window.
5422 We may have a pending insn for the delay slot, which will be combined
5423 with the 'restore' instruction. */
5425 output_asm_insn ("call\t%a0, 0", operands);
5429 rtx delay = NEXT_INSN (insn);
5432 output_restore (PATTERN (delay));
5434 PATTERN (delay) = gen_blockage ();
5435 INSN_CODE (delay) = -1;
5438 output_restore (NULL_RTX);
5444 /* Functions for handling argument passing.
5446 For 32-bit, the first 6 args are normally in registers and the rest are
5447 pushed. Any arg that starts within the first 6 words is at least
5448 partially passed in a register unless its data type forbids.
5450 For 64-bit, the argument registers are laid out as an array of 16 elements
5451 and arguments are added sequentially. The first 6 int args and up to the
5452 first 16 fp args (depending on size) are passed in regs.
5454 Slot Stack Integral Float Float in structure Double Long Double
5455 ---- ----- -------- ----- ------------------ ------ -----------
5456 15 [SP+248] %f31 %f30,%f31 %d30
5457 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5458 13 [SP+232] %f27 %f26,%f27 %d26
5459 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5460 11 [SP+216] %f23 %f22,%f23 %d22
5461 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5462 9 [SP+200] %f19 %f18,%f19 %d18
5463 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5464 7 [SP+184] %f15 %f14,%f15 %d14
5465 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5466 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5467 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5468 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5469 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5470 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5471 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5473 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5475 Integral arguments are always passed as 64-bit quantities appropriately
5478 Passing of floating point values is handled as follows.
5479 If a prototype is in scope:
5480 If the value is in a named argument (i.e. not a stdarg function or a
5481 value not part of the `...') then the value is passed in the appropriate
5483 If the value is part of the `...' and is passed in one of the first 6
5484 slots then the value is passed in the appropriate int reg.
5485 If the value is part of the `...' and is not passed in one of the first 6
5486 slots then the value is passed in memory.
5487 If a prototype is not in scope:
5488 If the value is one of the first 6 arguments the value is passed in the
5489 appropriate integer reg and the appropriate fp reg.
5490 If the value is not one of the first 6 arguments the value is passed in
5491 the appropriate fp reg and in memory.
5494 Summary of the calling conventions implemented by GCC on the SPARC:
5497 size argument return value
5499 small integer <4 int. reg. int. reg.
5500 word 4 int. reg. int. reg.
5501 double word 8 int. reg. int. reg.
5503 _Complex small integer <8 int. reg. int. reg.
5504 _Complex word 8 int. reg. int. reg.
5505 _Complex double word 16 memory int. reg.
5507 vector integer <=8 int. reg. FP reg.
5508 vector integer >8 memory memory
5510 float 4 int. reg. FP reg.
5511 double 8 int. reg. FP reg.
5512 long double 16 memory memory
5514 _Complex float 8 memory FP reg.
5515 _Complex double 16 memory FP reg.
5516 _Complex long double 32 memory FP reg.
5518 vector float any memory memory
5520 aggregate any memory memory
5525 size argument return value
5527 small integer <8 int. reg. int. reg.
5528 word 8 int. reg. int. reg.
5529 double word 16 int. reg. int. reg.
5531 _Complex small integer <16 int. reg. int. reg.
5532 _Complex word 16 int. reg. int. reg.
5533 _Complex double word 32 memory int. reg.
5535 vector integer <=16 FP reg. FP reg.
5536 vector integer 16<s<=32 memory FP reg.
5537 vector integer >32 memory memory
5539 float 4 FP reg. FP reg.
5540 double 8 FP reg. FP reg.
5541 long double 16 FP reg. FP reg.
5543 _Complex float 8 FP reg. FP reg.
5544 _Complex double 16 FP reg. FP reg.
5545 _Complex long double 32 memory FP reg.
5547 vector float <=16 FP reg. FP reg.
5548 vector float 16<s<=32 memory FP reg.
5549 vector float >32 memory memory
5551 aggregate <=16 reg. reg.
5552 aggregate 16<s<=32 memory reg.
5553 aggregate >32 memory memory
5557 Note #1: complex floating-point types follow the extended SPARC ABIs as
5558 implemented by the Sun compiler.
5560 Note #2: integral vector types follow the scalar floating-point types
5561 conventions to match what is implemented by the Sun VIS SDK.
5563 Note #3: floating-point vector types follow the aggregate types
5567 /* Maximum number of int regs for args. */
5568 #define SPARC_INT_ARG_MAX 6
5569 /* Maximum number of fp regs for args. */
5570 #define SPARC_FP_ARG_MAX 16
5572 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5574 /* Handle the INIT_CUMULATIVE_ARGS macro.
5575 Initialize a variable CUM of type CUMULATIVE_ARGS
5576 for a call to a function whose data type is FNTYPE.
5577 For a library call, FNTYPE is 0. */
5580 init_cumulative_args (struct sparc_args *cum, tree fntype,
5581 rtx libname ATTRIBUTE_UNUSED,
5582 tree fndecl ATTRIBUTE_UNUSED)
5585 cum->prototype_p = fntype && prototype_p (fntype);
5586 cum->libcall_p = fntype == 0;
5589 /* Handle promotion of pointer and integer arguments. */
5591 static enum machine_mode
5592 sparc_promote_function_mode (const_tree type,
5593 enum machine_mode mode,
5595 const_tree fntype ATTRIBUTE_UNUSED,
5596 int for_return ATTRIBUTE_UNUSED)
5598 if (type != NULL_TREE && POINTER_TYPE_P (type))
5600 *punsignedp = POINTERS_EXTEND_UNSIGNED;
5604 /* Integral arguments are passed as full words, as per the ABI. */
5605 if (GET_MODE_CLASS (mode) == MODE_INT
5606 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5612 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5615 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5617 return TARGET_ARCH64 ? true : false;
5620 /* Scan the record type TYPE and return the following predicates:
5621 - INTREGS_P: the record contains at least one field or sub-field
5622 that is eligible for promotion in integer registers.
5623 - FP_REGS_P: the record contains at least one field or sub-field
5624 that is eligible for promotion in floating-point registers.
5625 - PACKED_P: the record contains at least one field that is packed.
5627 Sub-fields are not taken into account for the PACKED_P predicate. */
5630 scan_record_type (const_tree type, int *intregs_p, int *fpregs_p,
5635 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5637 if (TREE_CODE (field) == FIELD_DECL)
5639 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5640 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5641 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5642 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5648 if (packed_p && DECL_PACKED (field))
5654 /* Compute the slot number to pass an argument in.
5655 Return the slot number or -1 if passing on the stack.
5657 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5658 the preceding args and about the function being called.
5659 MODE is the argument's machine mode.
5660 TYPE is the data type of the argument (as a tree).
5661 This is null for libcalls where that information may
5663 NAMED is nonzero if this argument is a named parameter
5664 (otherwise it is an extra parameter matching an ellipsis).
5665 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5666 *PREGNO records the register number to use if scalar type.
5667 *PPADDING records the amount of padding needed in words. */
5670 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5671 const_tree type, bool named, bool incoming_p,
5672 int *pregno, int *ppadding)
5674 int regbase = (incoming_p
5675 ? SPARC_INCOMING_INT_ARG_FIRST
5676 : SPARC_OUTGOING_INT_ARG_FIRST);
5677 int slotno = cum->words;
5678 enum mode_class mclass;
5683 if (type && TREE_ADDRESSABLE (type))
5689 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5692 /* For SPARC64, objects requiring 16-byte alignment get it. */
5694 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
5695 && (slotno & 1) != 0)
5696 slotno++, *ppadding = 1;
5698 mclass = GET_MODE_CLASS (mode);
5699 if (type && TREE_CODE (type) == VECTOR_TYPE)
5701 /* Vector types deserve special treatment because they are
5702 polymorphic wrt their mode, depending upon whether VIS
5703 instructions are enabled. */
5704 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5706 /* The SPARC port defines no floating-point vector modes. */
5707 gcc_assert (mode == BLKmode);
5711 /* Integral vector types should either have a vector
5712 mode or an integral mode, because we are guaranteed
5713 by pass_by_reference that their size is not greater
5714 than 16 bytes and TImode is 16-byte wide. */
5715 gcc_assert (mode != BLKmode);
5717 /* Vector integers are handled like floats according to
5719 mclass = MODE_FLOAT;
5726 case MODE_COMPLEX_FLOAT:
5727 case MODE_VECTOR_INT:
5728 if (TARGET_ARCH64 && TARGET_FPU && named)
5730 if (slotno >= SPARC_FP_ARG_MAX)
5732 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5733 /* Arguments filling only one single FP register are
5734 right-justified in the outer double FP register. */
5735 if (GET_MODE_SIZE (mode) <= 4)
5742 case MODE_COMPLEX_INT:
5743 if (slotno >= SPARC_INT_ARG_MAX)
5745 regno = regbase + slotno;
5749 if (mode == VOIDmode)
5750 /* MODE is VOIDmode when generating the actual call. */
5753 gcc_assert (mode == BLKmode);
5757 || (TREE_CODE (type) != VECTOR_TYPE
5758 && TREE_CODE (type) != RECORD_TYPE))
5760 if (slotno >= SPARC_INT_ARG_MAX)
5762 regno = regbase + slotno;
5764 else /* TARGET_ARCH64 && type */
5766 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5768 /* First see what kinds of registers we would need. */
5769 if (TREE_CODE (type) == VECTOR_TYPE)
5772 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5774 /* The ABI obviously doesn't specify how packed structures
5775 are passed. These are defined to be passed in int regs
5776 if possible, otherwise memory. */
5777 if (packed_p || !named)
5778 fpregs_p = 0, intregs_p = 1;
5780 /* If all arg slots are filled, then must pass on stack. */
5781 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5784 /* If there are only int args and all int arg slots are filled,
5785 then must pass on stack. */
5786 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5789 /* Note that even if all int arg slots are filled, fp members may
5790 still be passed in regs if such regs are available.
5791 *PREGNO isn't set because there may be more than one, it's up
5792 to the caller to compute them. */
5805 /* Handle recursive register counting for structure field layout. */
5807 struct function_arg_record_value_parms
5809 rtx ret; /* return expression being built. */
5810 int slotno; /* slot number of the argument. */
5811 int named; /* whether the argument is named. */
5812 int regbase; /* regno of the base register. */
5813 int stack; /* 1 if part of the argument is on the stack. */
5814 int intoffset; /* offset of the first pending integer field. */
5815 unsigned int nregs; /* number of words passed in registers. */
5818 static void function_arg_record_value_3
5819 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5820 static void function_arg_record_value_2
5821 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5822 static void function_arg_record_value_1
5823 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5824 static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
5825 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5827 /* A subroutine of function_arg_record_value. Traverse the structure
5828 recursively and determine how many registers will be required. */
5831 function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
5832 struct function_arg_record_value_parms *parms,
5837 /* We need to compute how many registers are needed so we can
5838 allocate the PARALLEL but before we can do that we need to know
5839 whether there are any packed fields. The ABI obviously doesn't
5840 specify how structures are passed in this case, so they are
5841 defined to be passed in int regs if possible, otherwise memory,
5842 regardless of whether there are fp values present. */
5845 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5847 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5854 /* Compute how many registers we need. */
5855 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5857 if (TREE_CODE (field) == FIELD_DECL)
5859 HOST_WIDE_INT bitpos = startbitpos;
5861 if (DECL_SIZE (field) != 0)
5863 if (integer_zerop (DECL_SIZE (field)))
5866 if (host_integerp (bit_position (field), 1))
5867 bitpos += int_bit_position (field);
5870 /* ??? FIXME: else assume zero offset. */
5872 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5873 function_arg_record_value_1 (TREE_TYPE (field),
5877 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5878 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5883 if (parms->intoffset != -1)
5885 unsigned int startbit, endbit;
5886 int intslots, this_slotno;
5888 startbit = parms->intoffset & -BITS_PER_WORD;
5889 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5891 intslots = (endbit - startbit) / BITS_PER_WORD;
5892 this_slotno = parms->slotno + parms->intoffset
5895 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5897 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5898 /* We need to pass this field on the stack. */
5902 parms->nregs += intslots;
5903 parms->intoffset = -1;
5906 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5907 If it wasn't true we wouldn't be here. */
5908 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5909 && DECL_MODE (field) == BLKmode)
5910 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5911 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5918 if (parms->intoffset == -1)
5919 parms->intoffset = bitpos;
5925 /* A subroutine of function_arg_record_value. Assign the bits of the
5926 structure between parms->intoffset and bitpos to integer registers. */
5929 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5930 struct function_arg_record_value_parms *parms)
5932 enum machine_mode mode;
5934 unsigned int startbit, endbit;
5935 int this_slotno, intslots, intoffset;
5938 if (parms->intoffset == -1)
5941 intoffset = parms->intoffset;
5942 parms->intoffset = -1;
5944 startbit = intoffset & -BITS_PER_WORD;
5945 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5946 intslots = (endbit - startbit) / BITS_PER_WORD;
5947 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5949 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5953 /* If this is the trailing part of a word, only load that much into
5954 the register. Otherwise load the whole register. Note that in
5955 the latter case we may pick up unwanted bits. It's not a problem
5956 at the moment but may wish to revisit. */
5958 if (intoffset % BITS_PER_WORD != 0)
5959 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5964 intoffset /= BITS_PER_UNIT;
5967 regno = parms->regbase + this_slotno;
5968 reg = gen_rtx_REG (mode, regno);
5969 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5970 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5973 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5978 while (intslots > 0);
5981 /* A subroutine of function_arg_record_value. Traverse the structure
5982 recursively and assign bits to floating point registers. Track which
5983 bits in between need integer registers; invoke function_arg_record_value_3
5984 to make that happen. */
5987 function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
5988 struct function_arg_record_value_parms *parms,
5994 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5996 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
6003 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6005 if (TREE_CODE (field) == FIELD_DECL)
6007 HOST_WIDE_INT bitpos = startbitpos;
6009 if (DECL_SIZE (field) != 0)
6011 if (integer_zerop (DECL_SIZE (field)))
6014 if (host_integerp (bit_position (field), 1))
6015 bitpos += int_bit_position (field);
6018 /* ??? FIXME: else assume zero offset. */
6020 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
6021 function_arg_record_value_2 (TREE_TYPE (field),
6025 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
6026 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
6031 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
6032 int regno, nregs, pos;
6033 enum machine_mode mode = DECL_MODE (field);
6036 function_arg_record_value_3 (bitpos, parms);
6038 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
6041 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6042 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
6044 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
6046 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6052 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
6053 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
6055 reg = gen_rtx_REG (mode, regno);
6056 pos = bitpos / BITS_PER_UNIT;
6057 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6058 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6062 regno += GET_MODE_SIZE (mode) / 4;
6063 reg = gen_rtx_REG (mode, regno);
6064 pos += GET_MODE_SIZE (mode);
6065 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6066 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6072 if (parms->intoffset == -1)
6073 parms->intoffset = bitpos;
6079 /* Used by function_arg and sparc_function_value_1 to implement the complex
6080 conventions of the 64-bit ABI for passing and returning structures.
6081 Return an expression valid as a return value for the FUNCTION_ARG
6082 and TARGET_FUNCTION_VALUE.
6084 TYPE is the data type of the argument (as a tree).
6085 This is null for libcalls where that information may
6087 MODE is the argument's machine mode.
6088 SLOTNO is the index number of the argument's slot in the parameter array.
6089 NAMED is nonzero if this argument is a named parameter
6090 (otherwise it is an extra parameter matching an ellipsis).
6091 REGBASE is the regno of the base register for the parameter array. */
6094 function_arg_record_value (const_tree type, enum machine_mode mode,
6095 int slotno, int named, int regbase)
6097 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6098 struct function_arg_record_value_parms parms;
6101 parms.ret = NULL_RTX;
6102 parms.slotno = slotno;
6103 parms.named = named;
6104 parms.regbase = regbase;
6107 /* Compute how many registers we need. */
6109 parms.intoffset = 0;
6110 function_arg_record_value_1 (type, 0, &parms, false);
6112 /* Take into account pending integer fields. */
6113 if (parms.intoffset != -1)
6115 unsigned int startbit, endbit;
6116 int intslots, this_slotno;
6118 startbit = parms.intoffset & -BITS_PER_WORD;
6119 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
6120 intslots = (endbit - startbit) / BITS_PER_WORD;
6121 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
6123 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
6125 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
6126 /* We need to pass this field on the stack. */
6130 parms.nregs += intslots;
6132 nregs = parms.nregs;
6134 /* Allocate the vector and handle some annoying special cases. */
6137 /* ??? Empty structure has no value? Duh? */
6140 /* Though there's nothing really to store, return a word register
6141 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6142 leads to breakage due to the fact that there are zero bytes to
6144 return gen_rtx_REG (mode, regbase);
6148 /* ??? C++ has structures with no fields, and yet a size. Give up
6149 for now and pass everything back in integer registers. */
6150 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6152 if (nregs + slotno > SPARC_INT_ARG_MAX)
6153 nregs = SPARC_INT_ARG_MAX - slotno;
6155 gcc_assert (nregs != 0);
6157 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
6159 /* If at least one field must be passed on the stack, generate
6160 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6161 also be passed on the stack. We can't do much better because the
6162 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6163 of structures for which the fields passed exclusively in registers
6164 are not at the beginning of the structure. */
6166 XVECEXP (parms.ret, 0, 0)
6167 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6169 /* Fill in the entries. */
6171 parms.intoffset = 0;
6172 function_arg_record_value_2 (type, 0, &parms, false);
6173 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
6175 gcc_assert (parms.nregs == nregs);
6180 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6181 of the 64-bit ABI for passing and returning unions.
6182 Return an expression valid as a return value for the FUNCTION_ARG
6183 and TARGET_FUNCTION_VALUE.
6185 SIZE is the size in bytes of the union.
6186 MODE is the argument's machine mode.
6187 REGNO is the hard register the union will be passed in. */
6190 function_arg_union_value (int size, enum machine_mode mode, int slotno,
6193 int nwords = ROUND_ADVANCE (size), i;
6196 /* See comment in previous function for empty structures. */
6198 return gen_rtx_REG (mode, regno);
6200 if (slotno == SPARC_INT_ARG_MAX - 1)
6203 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
6205 for (i = 0; i < nwords; i++)
6207 /* Unions are passed left-justified. */
6208 XVECEXP (regs, 0, i)
6209 = gen_rtx_EXPR_LIST (VOIDmode,
6210 gen_rtx_REG (word_mode, regno),
6211 GEN_INT (UNITS_PER_WORD * i));
6218 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6219 for passing and returning large (BLKmode) vectors.
6220 Return an expression valid as a return value for the FUNCTION_ARG
6221 and TARGET_FUNCTION_VALUE.
6223 SIZE is the size in bytes of the vector (at least 8 bytes).
6224 REGNO is the FP hard register the vector will be passed in. */
6227 function_arg_vector_value (int size, int regno)
6229 int i, nregs = size / 8;
6232 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
6234 for (i = 0; i < nregs; i++)
6236 XVECEXP (regs, 0, i)
6237 = gen_rtx_EXPR_LIST (VOIDmode,
6238 gen_rtx_REG (DImode, regno + 2*i),
6245 /* Determine where to put an argument to a function.
6246 Value is zero to push the argument on the stack,
6247 or a hard register in which to store the argument.
6249 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6250 the preceding args and about the function being called.
6251 MODE is the argument's machine mode.
6252 TYPE is the data type of the argument (as a tree).
6253 This is null for libcalls where that information may
6255 NAMED is true if this argument is a named parameter
6256 (otherwise it is an extra parameter matching an ellipsis).
6257 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6258 TARGET_FUNCTION_INCOMING_ARG. */
6261 sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
6262 const_tree type, bool named, bool incoming_p)
6264 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6266 int regbase = (incoming_p
6267 ? SPARC_INCOMING_INT_ARG_FIRST
6268 : SPARC_OUTGOING_INT_ARG_FIRST);
6269 int slotno, regno, padding;
6270 enum mode_class mclass = GET_MODE_CLASS (mode);
6272 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
6277 /* Vector types deserve special treatment because they are polymorphic wrt
6278 their mode, depending upon whether VIS instructions are enabled. */
6279 if (type && TREE_CODE (type) == VECTOR_TYPE)
6281 HOST_WIDE_INT size = int_size_in_bytes (type);
6282 gcc_assert ((TARGET_ARCH32 && size <= 8)
6283 || (TARGET_ARCH64 && size <= 16));
6285 if (mode == BLKmode)
6286 return function_arg_vector_value (size,
6287 SPARC_FP_ARG_FIRST + 2*slotno);
6289 mclass = MODE_FLOAT;
6293 return gen_rtx_REG (mode, regno);
6295 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6296 and are promoted to registers if possible. */
6297 if (type && TREE_CODE (type) == RECORD_TYPE)
6299 HOST_WIDE_INT size = int_size_in_bytes (type);
6300 gcc_assert (size <= 16);
6302 return function_arg_record_value (type, mode, slotno, named, regbase);
6305 /* Unions up to 16 bytes in size are passed in integer registers. */
6306 else if (type && TREE_CODE (type) == UNION_TYPE)
6308 HOST_WIDE_INT size = int_size_in_bytes (type);
6309 gcc_assert (size <= 16);
6311 return function_arg_union_value (size, mode, slotno, regno);
6314 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6315 but also have the slot allocated for them.
6316 If no prototype is in scope fp values in register slots get passed
6317 in two places, either fp regs and int regs or fp regs and memory. */
6318 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6319 && SPARC_FP_REG_P (regno))
6321 rtx reg = gen_rtx_REG (mode, regno);
6322 if (cum->prototype_p || cum->libcall_p)
6324 /* "* 2" because fp reg numbers are recorded in 4 byte
6327 /* ??? This will cause the value to be passed in the fp reg and
6328 in the stack. When a prototype exists we want to pass the
6329 value in the reg but reserve space on the stack. That's an
6330 optimization, and is deferred [for a bit]. */
6331 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
6332 return gen_rtx_PARALLEL (mode,
6334 gen_rtx_EXPR_LIST (VOIDmode,
6335 NULL_RTX, const0_rtx),
6336 gen_rtx_EXPR_LIST (VOIDmode,
6340 /* ??? It seems that passing back a register even when past
6341 the area declared by REG_PARM_STACK_SPACE will allocate
6342 space appropriately, and will not copy the data onto the
6343 stack, exactly as we desire.
6345 This is due to locate_and_pad_parm being called in
6346 expand_call whenever reg_parm_stack_space > 0, which
6347 while beneficial to our example here, would seem to be
6348 in error from what had been intended. Ho hum... -- r~ */
6356 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
6360 /* On incoming, we don't need to know that the value
6361 is passed in %f0 and %i0, and it confuses other parts
6362 causing needless spillage even on the simplest cases. */
6366 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
6367 + (regno - SPARC_FP_ARG_FIRST) / 2);
6369 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6370 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
6372 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6376 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6377 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6378 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6383 /* All other aggregate types are passed in an integer register in a mode
6384 corresponding to the size of the type. */
6385 else if (type && AGGREGATE_TYPE_P (type))
6387 HOST_WIDE_INT size = int_size_in_bytes (type);
6388 gcc_assert (size <= 16);
6390 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6393 return gen_rtx_REG (mode, regno);
6396 /* Handle the TARGET_FUNCTION_ARG target hook. */
6399 sparc_function_arg (cumulative_args_t cum, enum machine_mode mode,
6400 const_tree type, bool named)
6402 return sparc_function_arg_1 (cum, mode, type, named, false);
6405 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6408 sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
6409 const_tree type, bool named)
6411 return sparc_function_arg_1 (cum, mode, type, named, true);
6414 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6417 sparc_function_arg_boundary (enum machine_mode mode, const_tree type)
6419 return ((TARGET_ARCH64
6420 && (GET_MODE_ALIGNMENT (mode) == 128
6421 || (type && TYPE_ALIGN (type) == 128)))
6426 /* For an arg passed partly in registers and partly in memory,
6427 this is the number of bytes of registers used.
6428 For args passed entirely in registers or entirely in memory, zero.
6430 Any arg that starts in the first 6 regs but won't entirely fit in them
6431 needs partial registers on v8. On v9, structures with integer
6432 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6433 values that begin in the last fp reg [where "last fp reg" varies with the
6434 mode] will be split between that reg and memory. */
6437 sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode,
6438 tree type, bool named)
6440 int slotno, regno, padding;
6442 /* We pass false for incoming_p here, it doesn't matter. */
6443 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
6444 false, ®no, &padding);
6451 if ((slotno + (mode == BLKmode
6452 ? ROUND_ADVANCE (int_size_in_bytes (type))
6453 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
6454 > SPARC_INT_ARG_MAX)
6455 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
6459 /* We are guaranteed by pass_by_reference that the size of the
6460 argument is not greater than 16 bytes, so we only need to return
6461 one word if the argument is partially passed in registers. */
6463 if (type && AGGREGATE_TYPE_P (type))
6465 int size = int_size_in_bytes (type);
6467 if (size > UNITS_PER_WORD
6468 && slotno == SPARC_INT_ARG_MAX - 1)
6469 return UNITS_PER_WORD;
6471 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
6472 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6473 && ! (TARGET_FPU && named)))
6475 /* The complex types are passed as packed types. */
6476 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
6477 && slotno == SPARC_INT_ARG_MAX - 1)
6478 return UNITS_PER_WORD;
6480 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6482 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
6484 return UNITS_PER_WORD;
6491 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6492 Specify whether to pass the argument by reference. */
6495 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
6496 enum machine_mode mode, const_tree type,
6497 bool named ATTRIBUTE_UNUSED)
6500 /* Original SPARC 32-bit ABI says that structures and unions,
6501 and quad-precision floats are passed by reference. For Pascal,
6502 also pass arrays by reference. All other base types are passed
6505 Extended ABI (as implemented by the Sun compiler) says that all
6506 complex floats are passed by reference. Pass complex integers
6507 in registers up to 8 bytes. More generally, enforce the 2-word
6508 cap for passing arguments in registers.
6510 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6511 integers are passed like floats of the same size, that is in
6512 registers up to 8 bytes. Pass all vector floats by reference
6513 like structure and unions. */
6514 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
6516 /* Catch CDImode, TFmode, DCmode and TCmode. */
6517 || GET_MODE_SIZE (mode) > 8
6519 && TREE_CODE (type) == VECTOR_TYPE
6520 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6522 /* Original SPARC 64-bit ABI says that structures and unions
6523 smaller than 16 bytes are passed in registers, as well as
6524 all other base types.
6526 Extended ABI (as implemented by the Sun compiler) says that
6527 complex floats are passed in registers up to 16 bytes. Pass
6528 all complex integers in registers up to 16 bytes. More generally,
6529 enforce the 2-word cap for passing arguments in registers.
6531 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6532 integers are passed like floats of the same size, that is in
6533 registers (up to 16 bytes). Pass all vector floats like structure
6536 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
6537 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
6538 /* Catch CTImode and TCmode. */
6539 || GET_MODE_SIZE (mode) > 16);
6542 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6543 Update the data in CUM to advance over an argument
6544 of mode MODE and data type TYPE.
6545 TYPE is null for libcalls where that information may not be available. */
6548 sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
6549 const_tree type, bool named)
6551 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6554 /* We pass false for incoming_p here, it doesn't matter. */
6555 function_arg_slotno (cum, mode, type, named, false, ®no, &padding);
6557 /* If argument requires leading padding, add it. */
6558 cum->words += padding;
6562 cum->words += (mode != BLKmode
6563 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6564 : ROUND_ADVANCE (int_size_in_bytes (type)));
6568 if (type && AGGREGATE_TYPE_P (type))
6570 int size = int_size_in_bytes (type);
6574 else if (size <= 16)
6576 else /* passed by reference */
6581 cum->words += (mode != BLKmode
6582 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6583 : ROUND_ADVANCE (int_size_in_bytes (type)));
6588 /* Handle the FUNCTION_ARG_PADDING macro.
6589 For the 64 bit ABI structs are always stored left shifted in their
6593 function_arg_padding (enum machine_mode mode, const_tree type)
6595 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
6598 /* Fall back to the default. */
6599 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
6602 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6603 Specify whether to return the return value in memory. */
6606 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6609 /* Original SPARC 32-bit ABI says that structures and unions,
6610 and quad-precision floats are returned in memory. All other
6611 base types are returned in registers.
6613 Extended ABI (as implemented by the Sun compiler) says that
6614 all complex floats are returned in registers (8 FP registers
6615 at most for '_Complex long double'). Return all complex integers
6616 in registers (4 at most for '_Complex long long').
6618 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6619 integers are returned like floats of the same size, that is in
6620 registers up to 8 bytes and in memory otherwise. Return all
6621 vector floats in memory like structure and unions; note that
6622 they always have BLKmode like the latter. */
6623 return (TYPE_MODE (type) == BLKmode
6624 || TYPE_MODE (type) == TFmode
6625 || (TREE_CODE (type) == VECTOR_TYPE
6626 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6628 /* Original SPARC 64-bit ABI says that structures and unions
6629 smaller than 32 bytes are returned in registers, as well as
6630 all other base types.
6632 Extended ABI (as implemented by the Sun compiler) says that all
6633 complex floats are returned in registers (8 FP registers at most
6634 for '_Complex long double'). Return all complex integers in
6635 registers (4 at most for '_Complex TItype').
6637 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6638 integers are returned like floats of the same size, that is in
6639 registers. Return all vector floats like structure and unions;
6640 note that they always have BLKmode like the latter. */
6641 return (TYPE_MODE (type) == BLKmode
6642 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
6645 /* Handle the TARGET_STRUCT_VALUE target hook.
6646 Return where to find the structure return value address. */
6649 sparc_struct_value_rtx (tree fndecl, int incoming)
6658 mem = gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx,
6659 STRUCT_VALUE_OFFSET));
6661 mem = gen_frame_mem (Pmode, plus_constant (stack_pointer_rtx,
6662 STRUCT_VALUE_OFFSET));
6664 /* Only follow the SPARC ABI for fixed-size structure returns.
6665 Variable size structure returns are handled per the normal
6666 procedures in GCC. This is enabled by -mstd-struct-return */
6668 && sparc_std_struct_return
6669 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
6670 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
6672 /* We must check and adjust the return address, as it is
6673 optional as to whether the return object is really
6675 rtx ret_reg = gen_rtx_REG (Pmode, 31);
6676 rtx scratch = gen_reg_rtx (SImode);
6677 rtx endlab = gen_label_rtx ();
6679 /* Calculate the return object size */
6680 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
6681 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
6682 /* Construct a temporary return value */
6684 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
6686 /* Implement SPARC 32-bit psABI callee return struct checking:
6688 Fetch the instruction where we will return to and see if
6689 it's an unimp instruction (the most significant 10 bits
6691 emit_move_insn (scratch, gen_rtx_MEM (SImode,
6692 plus_constant (ret_reg, 8)));
6693 /* Assume the size is valid and pre-adjust */
6694 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4)));
6695 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
6697 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4)));
6698 /* Write the address of the memory pointed to by temp_val into
6699 the memory pointed to by mem */
6700 emit_move_insn (mem, XEXP (temp_val, 0));
6701 emit_label (endlab);
6708 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6709 For v9, function return values are subject to the same rules as arguments,
6710 except that up to 32 bytes may be returned in registers. */
6713 sparc_function_value_1 (const_tree type, enum machine_mode mode,
6716 /* Beware that the two values are swapped here wrt function_arg. */
6717 int regbase = (outgoing
6718 ? SPARC_INCOMING_INT_ARG_FIRST
6719 : SPARC_OUTGOING_INT_ARG_FIRST);
6720 enum mode_class mclass = GET_MODE_CLASS (mode);
6723 /* Vector types deserve special treatment because they are polymorphic wrt
6724 their mode, depending upon whether VIS instructions are enabled. */
6725 if (type && TREE_CODE (type) == VECTOR_TYPE)
6727 HOST_WIDE_INT size = int_size_in_bytes (type);
6728 gcc_assert ((TARGET_ARCH32 && size <= 8)
6729 || (TARGET_ARCH64 && size <= 32));
6731 if (mode == BLKmode)
6732 return function_arg_vector_value (size,
6733 SPARC_FP_ARG_FIRST);
6735 mclass = MODE_FLOAT;
6738 if (TARGET_ARCH64 && type)
6740 /* Structures up to 32 bytes in size are returned in registers. */
6741 if (TREE_CODE (type) == RECORD_TYPE)
6743 HOST_WIDE_INT size = int_size_in_bytes (type);
6744 gcc_assert (size <= 32);
6746 return function_arg_record_value (type, mode, 0, 1, regbase);
6749 /* Unions up to 32 bytes in size are returned in integer registers. */
6750 else if (TREE_CODE (type) == UNION_TYPE)
6752 HOST_WIDE_INT size = int_size_in_bytes (type);
6753 gcc_assert (size <= 32);
6755 return function_arg_union_value (size, mode, 0, regbase);
6758 /* Objects that require it are returned in FP registers. */
6759 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6762 /* All other aggregate types are returned in an integer register in a
6763 mode corresponding to the size of the type. */
6764 else if (AGGREGATE_TYPE_P (type))
6766 /* All other aggregate types are passed in an integer register
6767 in a mode corresponding to the size of the type. */
6768 HOST_WIDE_INT size = int_size_in_bytes (type);
6769 gcc_assert (size <= 32);
6771 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6773 /* ??? We probably should have made the same ABI change in
6774 3.4.0 as the one we made for unions. The latter was
6775 required by the SCD though, while the former is not
6776 specified, so we favored compatibility and efficiency.
6778 Now we're stuck for aggregates larger than 16 bytes,
6779 because OImode vanished in the meantime. Let's not
6780 try to be unduly clever, and simply follow the ABI
6781 for unions in that case. */
6782 if (mode == BLKmode)
6783 return function_arg_union_value (size, mode, 0, regbase);
6788 /* We should only have pointer and integer types at this point. This
6789 must match sparc_promote_function_mode. */
6790 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6794 /* We should only have pointer and integer types at this point. This must
6795 match sparc_promote_function_mode. */
6796 else if (TARGET_ARCH32
6797 && mclass == MODE_INT
6798 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6801 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
6802 regno = SPARC_FP_ARG_FIRST;
6806 return gen_rtx_REG (mode, regno);
6809 /* Handle TARGET_FUNCTION_VALUE.
6810 On the SPARC, the value is found in the first "output" register, but the
6811 called function leaves it in the first "input" register. */
6814 sparc_function_value (const_tree valtype,
6815 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
6818 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
6821 /* Handle TARGET_LIBCALL_VALUE. */
6824 sparc_libcall_value (enum machine_mode mode,
6825 const_rtx fun ATTRIBUTE_UNUSED)
6827 return sparc_function_value_1 (NULL_TREE, mode, false);
6830 /* Handle FUNCTION_VALUE_REGNO_P.
6831 On the SPARC, the first "output" reg is used for integer values, and the
6832 first floating point register is used for floating point values. */
6835 sparc_function_value_regno_p (const unsigned int regno)
6837 return (regno == 8 || regno == 32);
6840 /* Do what is necessary for `va_start'. We look at the current function
6841 to determine if stdarg or varargs is used and return the address of
6842 the first unnamed parameter. */
6845 sparc_builtin_saveregs (void)
6847 int first_reg = crtl->args.info.words;
6851 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
6852 emit_move_insn (gen_rtx_MEM (word_mode,
6853 gen_rtx_PLUS (Pmode,
6855 GEN_INT (FIRST_PARM_OFFSET (0)
6858 gen_rtx_REG (word_mode,
6859 SPARC_INCOMING_INT_ARG_FIRST + regno));
6861 address = gen_rtx_PLUS (Pmode,
6863 GEN_INT (FIRST_PARM_OFFSET (0)
6864 + UNITS_PER_WORD * first_reg));
6869 /* Implement `va_start' for stdarg. */
6872 sparc_va_start (tree valist, rtx nextarg)
6874 nextarg = expand_builtin_saveregs ();
6875 std_expand_builtin_va_start (valist, nextarg);
6878 /* Implement `va_arg' for stdarg. */
6881 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6884 HOST_WIDE_INT size, rsize, align;
6887 tree ptrtype = build_pointer_type (type);
6889 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6892 size = rsize = UNITS_PER_WORD;
6898 size = int_size_in_bytes (type);
6899 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6904 /* For SPARC64, objects requiring 16-byte alignment get it. */
6905 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6906 align = 2 * UNITS_PER_WORD;
6908 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6909 are left-justified in their slots. */
6910 if (AGGREGATE_TYPE_P (type))
6913 size = rsize = UNITS_PER_WORD;
6923 incr = fold_build_pointer_plus_hwi (incr, align - 1);
6924 incr = fold_convert (sizetype, incr);
6925 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
6927 incr = fold_convert (ptr_type_node, incr);
6930 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6933 if (BYTES_BIG_ENDIAN && size < rsize)
6934 addr = fold_build_pointer_plus_hwi (incr, rsize - size);
6938 addr = fold_convert (build_pointer_type (ptrtype), addr);
6939 addr = build_va_arg_indirect_ref (addr);
6942 /* If the address isn't aligned properly for the type, we need a temporary.
6943 FIXME: This is inefficient, usually we can do this in registers. */
6944 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
6946 tree tmp = create_tmp_var (type, "va_arg_tmp");
6947 tree dest_addr = build_fold_addr_expr (tmp);
6948 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
6949 3, dest_addr, addr, size_int (rsize));
6950 TREE_ADDRESSABLE (tmp) = 1;
6951 gimplify_and_add (copy, pre_p);
6956 addr = fold_convert (ptrtype, addr);
6958 incr = fold_build_pointer_plus_hwi (incr, rsize);
6959 gimplify_assign (valist, incr, post_p);
6961 return build_va_arg_indirect_ref (addr);
6964 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6965 Specify whether the vector mode is supported by the hardware. */
6968 sparc_vector_mode_supported_p (enum machine_mode mode)
6970 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
6973 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6975 static enum machine_mode
6976 sparc_preferred_simd_mode (enum machine_mode mode)
6994 /* Return the string to output an unconditional branch to LABEL, which is
6995 the operand number of the label.
6997 DEST is the destination insn (i.e. the label), INSN is the source. */
7000 output_ubranch (rtx dest, int label, rtx insn)
7002 static char string[64];
7003 bool v9_form = false;
7006 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
7008 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7009 - INSN_ADDRESSES (INSN_UID (insn)));
7010 /* Leave some instructions for "slop". */
7011 if (delta >= -260000 && delta < 260000)
7016 strcpy (string, "ba%*,pt\t%%xcc, ");
7018 strcpy (string, "b%*\t");
7020 p = strchr (string, '\0');
7031 /* Return the string to output a conditional branch to LABEL, which is
7032 the operand number of the label. OP is the conditional expression.
7033 XEXP (OP, 0) is assumed to be a condition code register (integer or
7034 floating point) and its mode specifies what kind of comparison we made.
7036 DEST is the destination insn (i.e. the label), INSN is the source.
7038 REVERSED is nonzero if we should reverse the sense of the comparison.
7040 ANNUL is nonzero if we should generate an annulling branch. */
7043 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
7046 static char string[64];
7047 enum rtx_code code = GET_CODE (op);
7048 rtx cc_reg = XEXP (op, 0);
7049 enum machine_mode mode = GET_MODE (cc_reg);
7050 const char *labelno, *branch;
7051 int spaces = 8, far;
7054 /* v9 branches are limited to +-1MB. If it is too far away,
7067 fbne,a,pn %fcc2, .LC29
7075 far = TARGET_V9 && (get_attr_length (insn) >= 3);
7078 /* Reversal of FP compares takes care -- an ordered compare
7079 becomes an unordered compare and vice versa. */
7080 if (mode == CCFPmode || mode == CCFPEmode)
7081 code = reverse_condition_maybe_unordered (code);
7083 code = reverse_condition (code);
7086 /* Start by writing the branch condition. */
7087 if (mode == CCFPmode || mode == CCFPEmode)
7138 /* ??? !v9: FP branches cannot be preceded by another floating point
7139 insn. Because there is currently no concept of pre-delay slots,
7140 we can fix this only by always emitting a nop before a floating
7145 strcpy (string, "nop\n\t");
7146 strcat (string, branch);
7159 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7171 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7192 strcpy (string, branch);
7194 spaces -= strlen (branch);
7195 p = strchr (string, '\0');
7197 /* Now add the annulling, the label, and a possible noop. */
7210 if (! far && insn && INSN_ADDRESSES_SET_P ())
7212 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7213 - INSN_ADDRESSES (INSN_UID (insn)));
7214 /* Leave some instructions for "slop". */
7215 if (delta < -260000 || delta >= 260000)
7219 if (mode == CCFPmode || mode == CCFPEmode)
7221 static char v9_fcc_labelno[] = "%%fccX, ";
7222 /* Set the char indicating the number of the fcc reg to use. */
7223 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
7224 labelno = v9_fcc_labelno;
7227 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
7231 else if (mode == CCXmode || mode == CCX_NOOVmode)
7233 labelno = "%%xcc, ";
7238 labelno = "%%icc, ";
7243 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7246 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7259 strcpy (p, labelno);
7260 p = strchr (p, '\0');
7263 strcpy (p, ".+12\n\t nop\n\tb\t");
7264 /* Skip the next insn if requested or
7265 if we know that it will be a nop. */
7266 if (annul || ! final_sequence)
7280 /* Emit a library call comparison between floating point X and Y.
7281 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7282 Return the new operator to be used in the comparison sequence.
7284 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7285 values as arguments instead of the TFmode registers themselves,
7286 that's why we cannot call emit_float_lib_cmp. */
7289 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
7292 rtx slot0, slot1, result, tem, tem2, libfunc;
7293 enum machine_mode mode;
7294 enum rtx_code new_comparison;
7299 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
7303 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
7307 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
7311 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
7315 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
7319 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
7330 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
7343 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7344 emit_move_insn (slot0, x);
7351 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7352 emit_move_insn (slot1, y);
7355 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7356 emit_library_call (libfunc, LCT_NORMAL,
7358 XEXP (slot0, 0), Pmode,
7359 XEXP (slot1, 0), Pmode);
7364 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7365 emit_library_call (libfunc, LCT_NORMAL,
7367 x, TFmode, y, TFmode);
7372 /* Immediately move the result of the libcall into a pseudo
7373 register so reload doesn't clobber the value if it needs
7374 the return register for a spill reg. */
7375 result = gen_reg_rtx (mode);
7376 emit_move_insn (result, hard_libcall_value (mode, libfunc));
7381 return gen_rtx_NE (VOIDmode, result, const0_rtx);
7384 new_comparison = (comparison == UNORDERED ? EQ : NE);
7385 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
7388 new_comparison = (comparison == UNGT ? GT : NE);
7389 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
7391 return gen_rtx_NE (VOIDmode, result, const2_rtx);
7393 tem = gen_reg_rtx (mode);
7395 emit_insn (gen_andsi3 (tem, result, const1_rtx));
7397 emit_insn (gen_anddi3 (tem, result, const1_rtx));
7398 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
7401 tem = gen_reg_rtx (mode);
7403 emit_insn (gen_addsi3 (tem, result, const1_rtx));
7405 emit_insn (gen_adddi3 (tem, result, const1_rtx));
7406 tem2 = gen_reg_rtx (mode);
7408 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
7410 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
7411 new_comparison = (comparison == UNEQ ? EQ : NE);
7412 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
7418 /* Generate an unsigned DImode to FP conversion. This is the same code
7419 optabs would emit if we didn't have TFmode patterns. */
7422 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
7424 rtx neglab, donelab, i0, i1, f0, in, out;
7427 in = force_reg (DImode, operands[1]);
7428 neglab = gen_label_rtx ();
7429 donelab = gen_label_rtx ();
7430 i0 = gen_reg_rtx (DImode);
7431 i1 = gen_reg_rtx (DImode);
7432 f0 = gen_reg_rtx (mode);
7434 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
7436 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
7437 emit_jump_insn (gen_jump (donelab));
7440 emit_label (neglab);
7442 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
7443 emit_insn (gen_anddi3 (i1, in, const1_rtx));
7444 emit_insn (gen_iordi3 (i0, i0, i1));
7445 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
7446 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
7448 emit_label (donelab);
7451 /* Generate an FP to unsigned DImode conversion. This is the same code
7452 optabs would emit if we didn't have TFmode patterns. */
7455 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
7457 rtx neglab, donelab, i0, i1, f0, in, out, limit;
7460 in = force_reg (mode, operands[1]);
7461 neglab = gen_label_rtx ();
7462 donelab = gen_label_rtx ();
7463 i0 = gen_reg_rtx (DImode);
7464 i1 = gen_reg_rtx (DImode);
7465 limit = gen_reg_rtx (mode);
7466 f0 = gen_reg_rtx (mode);
7468 emit_move_insn (limit,
7469 CONST_DOUBLE_FROM_REAL_VALUE (
7470 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
7471 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
7473 emit_insn (gen_rtx_SET (VOIDmode,
7475 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
7476 emit_jump_insn (gen_jump (donelab));
7479 emit_label (neglab);
7481 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
7482 emit_insn (gen_rtx_SET (VOIDmode,
7484 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
7485 emit_insn (gen_movdi (i1, const1_rtx));
7486 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
7487 emit_insn (gen_xordi3 (out, i0, i1));
7489 emit_label (donelab);
7492 /* Return the string to output a conditional branch to LABEL, testing
7493 register REG. LABEL is the operand number of the label; REG is the
7494 operand number of the reg. OP is the conditional expression. The mode
7495 of REG says what kind of comparison we made.
7497 DEST is the destination insn (i.e. the label), INSN is the source.
7499 REVERSED is nonzero if we should reverse the sense of the comparison.
7501 ANNUL is nonzero if we should generate an annulling branch. */
7504 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
7505 int annul, rtx insn)
7507 static char string[64];
7508 enum rtx_code code = GET_CODE (op);
7509 enum machine_mode mode = GET_MODE (XEXP (op, 0));
7514 /* branch on register are limited to +-128KB. If it is too far away,
7527 brgez,a,pn %o1, .LC29
7533 ba,pt %xcc, .LC29 */
7535 far = get_attr_length (insn) >= 3;
7537 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7539 code = reverse_condition (code);
7541 /* Only 64 bit versions of these instructions exist. */
7542 gcc_assert (mode == DImode);
7544 /* Start by writing the branch condition. */
7549 strcpy (string, "brnz");
7553 strcpy (string, "brz");
7557 strcpy (string, "brgez");
7561 strcpy (string, "brlz");
7565 strcpy (string, "brlez");
7569 strcpy (string, "brgz");
7576 p = strchr (string, '\0');
7578 /* Now add the annulling, reg, label, and nop. */
7585 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7588 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7593 *p = p < string + 8 ? '\t' : ' ';
7601 int veryfar = 1, delta;
7603 if (INSN_ADDRESSES_SET_P ())
7605 delta = (INSN_ADDRESSES (INSN_UID (dest))
7606 - INSN_ADDRESSES (INSN_UID (insn)));
7607 /* Leave some instructions for "slop". */
7608 if (delta >= -260000 && delta < 260000)
7612 strcpy (p, ".+12\n\t nop\n\t");
7613 /* Skip the next insn if requested or
7614 if we know that it will be a nop. */
7615 if (annul || ! final_sequence)
7625 strcpy (p, "ba,pt\t%%xcc, ");
7639 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7640 Such instructions cannot be used in the delay slot of return insn on v9.
7641 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7645 epilogue_renumber (register rtx *where, int test)
7647 register const char *fmt;
7649 register enum rtx_code code;
7654 code = GET_CODE (*where);
7659 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
7661 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
7662 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
7670 /* Do not replace the frame pointer with the stack pointer because
7671 it can cause the delayed instruction to load below the stack.
7672 This occurs when instructions like:
7674 (set (reg/i:SI 24 %i0)
7675 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7676 (const_int -20 [0xffffffec])) 0))
7678 are in the return delayed slot. */
7680 if (GET_CODE (XEXP (*where, 0)) == REG
7681 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
7682 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
7683 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
7688 if (SPARC_STACK_BIAS
7689 && GET_CODE (XEXP (*where, 0)) == REG
7690 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
7698 fmt = GET_RTX_FORMAT (code);
7700 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7705 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7706 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7709 else if (fmt[i] == 'e'
7710 && epilogue_renumber (&(XEXP (*where, i)), test))
7716 /* Leaf functions and non-leaf functions have different needs. */
7719 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7722 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7724 static const int *const reg_alloc_orders[] = {
7725 reg_leaf_alloc_order,
7726 reg_nonleaf_alloc_order};
7729 order_regs_for_local_alloc (void)
7731 static int last_order_nonleaf = 1;
7733 if (df_regs_ever_live_p (15) != last_order_nonleaf)
7735 last_order_nonleaf = !last_order_nonleaf;
7736 memcpy ((char *) reg_alloc_order,
7737 (const char *) reg_alloc_orders[last_order_nonleaf],
7738 FIRST_PSEUDO_REGISTER * sizeof (int));
7742 /* Return 1 if REG and MEM are legitimate enough to allow the various
7743 mem<-->reg splits to be run. */
7746 sparc_splitdi_legitimate (rtx reg, rtx mem)
7748 /* Punt if we are here by mistake. */
7749 gcc_assert (reload_completed);
7751 /* We must have an offsettable memory reference. */
7752 if (! offsettable_memref_p (mem))
7755 /* If we have legitimate args for ldd/std, we do not want
7756 the split to happen. */
7757 if ((REGNO (reg) % 2) == 0
7758 && mem_min_alignment (mem, 8))
7765 /* Return 1 if x and y are some kind of REG and they refer to
7766 different hard registers. This test is guaranteed to be
7767 run after reload. */
7770 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
7772 if (GET_CODE (x) != REG)
7774 if (GET_CODE (y) != REG)
7776 if (REGNO (x) == REGNO (y))
7781 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7782 This makes them candidates for using ldd and std insns.
7784 Note reg1 and reg2 *must* be hard registers. */
7787 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
7789 /* We might have been passed a SUBREG. */
7790 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7793 if (REGNO (reg1) % 2 != 0)
7796 /* Integer ldd is deprecated in SPARC V9 */
7797 if (TARGET_V9 && REGNO (reg1) < 32)
7800 return (REGNO (reg1) == REGNO (reg2) - 1);
7803 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7806 This can only happen when addr1 and addr2, the addresses in mem1
7807 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7808 addr1 must also be aligned on a 64-bit boundary.
7810 Also iff dependent_reg_rtx is not null it should not be used to
7811 compute the address for mem1, i.e. we cannot optimize a sequence
7823 But, note that the transformation from:
7828 is perfectly fine. Thus, the peephole2 patterns always pass us
7829 the destination register of the first load, never the second one.
7831 For stores we don't have a similar problem, so dependent_reg_rtx is
7835 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
7839 HOST_WIDE_INT offset1;
7841 /* The mems cannot be volatile. */
7842 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7845 /* MEM1 should be aligned on a 64-bit boundary. */
7846 if (MEM_ALIGN (mem1) < 64)
7849 addr1 = XEXP (mem1, 0);
7850 addr2 = XEXP (mem2, 0);
7852 /* Extract a register number and offset (if used) from the first addr. */
7853 if (GET_CODE (addr1) == PLUS)
7855 /* If not a REG, return zero. */
7856 if (GET_CODE (XEXP (addr1, 0)) != REG)
7860 reg1 = REGNO (XEXP (addr1, 0));
7861 /* The offset must be constant! */
7862 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7864 offset1 = INTVAL (XEXP (addr1, 1));
7867 else if (GET_CODE (addr1) != REG)
7871 reg1 = REGNO (addr1);
7872 /* This was a simple (mem (reg)) expression. Offset is 0. */
7876 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7877 if (GET_CODE (addr2) != PLUS)
7880 if (GET_CODE (XEXP (addr2, 0)) != REG
7881 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7884 if (reg1 != REGNO (XEXP (addr2, 0)))
7887 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7890 /* The first offset must be evenly divisible by 8 to ensure the
7891 address is 64 bit aligned. */
7892 if (offset1 % 8 != 0)
7895 /* The offset for the second addr must be 4 more than the first addr. */
7896 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7899 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7904 /* Return 1 if reg is a pseudo, or is the first register in
7905 a hard register pair. This makes it suitable for use in
7906 ldd and std insns. */
7909 register_ok_for_ldd (rtx reg)
7911 /* We might have been passed a SUBREG. */
7915 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7916 return (REGNO (reg) % 2 == 0);
7921 /* Return 1 if OP is a memory whose address is known to be
7922 aligned to 8-byte boundary, or a pseudo during reload.
7923 This makes it suitable for use in ldd and std insns. */
7926 memory_ok_for_ldd (rtx op)
7930 /* In 64-bit mode, we assume that the address is word-aligned. */
7931 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
7934 if (! can_create_pseudo_p ()
7935 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
7938 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
7940 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
7949 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7952 sparc_print_operand_punct_valid_p (unsigned char code)
7965 /* Implement TARGET_PRINT_OPERAND.
7966 Print operand X (an rtx) in assembler syntax to file FILE.
7967 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7968 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7971 sparc_print_operand (FILE *file, rtx x, int code)
7976 /* Output an insn in a delay slot. */
7978 sparc_indent_opcode = 1;
7980 fputs ("\n\t nop", file);
7983 /* Output an annul flag if there's nothing for the delay slot and we
7984 are optimizing. This is always used with '(' below.
7985 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7986 this is a dbx bug. So, we only do this when optimizing.
7987 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7988 Always emit a nop in case the next instruction is a branch. */
7989 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7993 /* Output a 'nop' if there's nothing for the delay slot and we are
7994 not optimizing. This is always used with '*' above. */
7995 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7996 fputs ("\n\t nop", file);
7997 else if (final_sequence)
7998 sparc_indent_opcode = 1;
8001 /* Output the right displacement from the saved PC on function return.
8002 The caller may have placed an "unimp" insn immediately after the call
8003 so we have to account for it. This insn is used in the 32-bit ABI
8004 when calling a function that returns a non zero-sized structure. The
8005 64-bit ABI doesn't have it. Be careful to have this test be the same
8006 as that for the call. The exception is when sparc_std_struct_return
8007 is enabled, the psABI is followed exactly and the adjustment is made
8008 by the code in sparc_struct_value_rtx. The call emitted is the same
8009 when sparc_std_struct_return is enabled. */
8011 && cfun->returns_struct
8012 && !sparc_std_struct_return
8013 && DECL_SIZE (DECL_RESULT (current_function_decl))
8014 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
8016 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
8022 /* Output the Embedded Medium/Anywhere code model base register. */
8023 fputs (EMBMEDANY_BASE_REG, file);
8026 /* Print some local dynamic TLS name. */
8027 assemble_name (file, get_some_local_dynamic_name ());
8031 /* Adjust the operand to take into account a RESTORE operation. */
8032 if (GET_CODE (x) == CONST_INT)
8034 else if (GET_CODE (x) != REG)
8035 output_operand_lossage ("invalid %%Y operand");
8036 else if (REGNO (x) < 8)
8037 fputs (reg_names[REGNO (x)], file);
8038 else if (REGNO (x) >= 24 && REGNO (x) < 32)
8039 fputs (reg_names[REGNO (x)-16], file);
8041 output_operand_lossage ("invalid %%Y operand");
8044 /* Print out the low order register name of a register pair. */
8045 if (WORDS_BIG_ENDIAN)
8046 fputs (reg_names[REGNO (x)+1], file);
8048 fputs (reg_names[REGNO (x)], file);
8051 /* Print out the high order register name of a register pair. */
8052 if (WORDS_BIG_ENDIAN)
8053 fputs (reg_names[REGNO (x)], file);
8055 fputs (reg_names[REGNO (x)+1], file);
8058 /* Print out the second register name of a register pair or quad.
8059 I.e., R (%o0) => %o1. */
8060 fputs (reg_names[REGNO (x)+1], file);
8063 /* Print out the third register name of a register quad.
8064 I.e., S (%o0) => %o2. */
8065 fputs (reg_names[REGNO (x)+2], file);
8068 /* Print out the fourth register name of a register quad.
8069 I.e., T (%o0) => %o3. */
8070 fputs (reg_names[REGNO (x)+3], file);
8073 /* Print a condition code register. */
8074 if (REGNO (x) == SPARC_ICC_REG)
8076 /* We don't handle CC[X]_NOOVmode because they're not supposed
8078 if (GET_MODE (x) == CCmode)
8079 fputs ("%icc", file);
8080 else if (GET_MODE (x) == CCXmode)
8081 fputs ("%xcc", file);
8086 /* %fccN register */
8087 fputs (reg_names[REGNO (x)], file);
8090 /* Print the operand's address only. */
8091 output_address (XEXP (x, 0));
8094 /* In this case we need a register. Use %g0 if the
8095 operand is const0_rtx. */
8097 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
8099 fputs ("%g0", file);
8106 switch (GET_CODE (x))
8108 case IOR: fputs ("or", file); break;
8109 case AND: fputs ("and", file); break;
8110 case XOR: fputs ("xor", file); break;
8111 default: output_operand_lossage ("invalid %%A operand");
8116 switch (GET_CODE (x))
8118 case IOR: fputs ("orn", file); break;
8119 case AND: fputs ("andn", file); break;
8120 case XOR: fputs ("xnor", file); break;
8121 default: output_operand_lossage ("invalid %%B operand");
8125 /* These are used by the conditional move instructions. */
8129 enum rtx_code rc = GET_CODE (x);
8133 enum machine_mode mode = GET_MODE (XEXP (x, 0));
8134 if (mode == CCFPmode || mode == CCFPEmode)
8135 rc = reverse_condition_maybe_unordered (GET_CODE (x));
8137 rc = reverse_condition (GET_CODE (x));
8141 case NE: fputs ("ne", file); break;
8142 case EQ: fputs ("e", file); break;
8143 case GE: fputs ("ge", file); break;
8144 case GT: fputs ("g", file); break;
8145 case LE: fputs ("le", file); break;
8146 case LT: fputs ("l", file); break;
8147 case GEU: fputs ("geu", file); break;
8148 case GTU: fputs ("gu", file); break;
8149 case LEU: fputs ("leu", file); break;
8150 case LTU: fputs ("lu", file); break;
8151 case LTGT: fputs ("lg", file); break;
8152 case UNORDERED: fputs ("u", file); break;
8153 case ORDERED: fputs ("o", file); break;
8154 case UNLT: fputs ("ul", file); break;
8155 case UNLE: fputs ("ule", file); break;
8156 case UNGT: fputs ("ug", file); break;
8157 case UNGE: fputs ("uge", file); break;
8158 case UNEQ: fputs ("ue", file); break;
8159 default: output_operand_lossage (code == 'c'
8160 ? "invalid %%c operand"
8161 : "invalid %%C operand");
8166 /* These are used by the movr instruction pattern. */
8170 enum rtx_code rc = (code == 'd'
8171 ? reverse_condition (GET_CODE (x))
8175 case NE: fputs ("ne", file); break;
8176 case EQ: fputs ("e", file); break;
8177 case GE: fputs ("gez", file); break;
8178 case LT: fputs ("lz", file); break;
8179 case LE: fputs ("lez", file); break;
8180 case GT: fputs ("gz", file); break;
8181 default: output_operand_lossage (code == 'd'
8182 ? "invalid %%d operand"
8183 : "invalid %%D operand");
8190 /* Print a sign-extended character. */
8191 int i = trunc_int_for_mode (INTVAL (x), QImode);
8192 fprintf (file, "%d", i);
8197 /* Operand must be a MEM; write its address. */
8198 if (GET_CODE (x) != MEM)
8199 output_operand_lossage ("invalid %%f operand");
8200 output_address (XEXP (x, 0));
8205 /* Print a sign-extended 32-bit value. */
8207 if (GET_CODE(x) == CONST_INT)
8209 else if (GET_CODE(x) == CONST_DOUBLE)
8210 i = CONST_DOUBLE_LOW (x);
8213 output_operand_lossage ("invalid %%s operand");
8216 i = trunc_int_for_mode (i, SImode);
8217 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
8222 /* Do nothing special. */
8226 /* Undocumented flag. */
8227 output_operand_lossage ("invalid operand output code");
8230 if (GET_CODE (x) == REG)
8231 fputs (reg_names[REGNO (x)], file);
8232 else if (GET_CODE (x) == MEM)
8235 /* Poor Sun assembler doesn't understand absolute addressing. */
8236 if (CONSTANT_P (XEXP (x, 0)))
8237 fputs ("%g0+", file);
8238 output_address (XEXP (x, 0));
8241 else if (GET_CODE (x) == HIGH)
8243 fputs ("%hi(", file);
8244 output_addr_const (file, XEXP (x, 0));
8247 else if (GET_CODE (x) == LO_SUM)
8249 sparc_print_operand (file, XEXP (x, 0), 0);
8250 if (TARGET_CM_MEDMID)
8251 fputs ("+%l44(", file);
8253 fputs ("+%lo(", file);
8254 output_addr_const (file, XEXP (x, 1));
8257 else if (GET_CODE (x) == CONST_DOUBLE
8258 && (GET_MODE (x) == VOIDmode
8259 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
8261 if (CONST_DOUBLE_HIGH (x) == 0)
8262 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
8263 else if (CONST_DOUBLE_HIGH (x) == -1
8264 && CONST_DOUBLE_LOW (x) < 0)
8265 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
8267 output_operand_lossage ("long long constant not a valid immediate operand");
8269 else if (GET_CODE (x) == CONST_DOUBLE)
8270 output_operand_lossage ("floating point constant not a valid immediate operand");
8271 else { output_addr_const (file, x); }
8274 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8277 sparc_print_operand_address (FILE *file, rtx x)
8279 register rtx base, index = 0;
8281 register rtx addr = x;
8284 fputs (reg_names[REGNO (addr)], file);
8285 else if (GET_CODE (addr) == PLUS)
8287 if (CONST_INT_P (XEXP (addr, 0)))
8288 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
8289 else if (CONST_INT_P (XEXP (addr, 1)))
8290 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
8292 base = XEXP (addr, 0), index = XEXP (addr, 1);
8293 if (GET_CODE (base) == LO_SUM)
8295 gcc_assert (USE_AS_OFFSETABLE_LO10
8297 && ! TARGET_CM_MEDMID);
8298 output_operand (XEXP (base, 0), 0);
8299 fputs ("+%lo(", file);
8300 output_address (XEXP (base, 1));
8301 fprintf (file, ")+%d", offset);
8305 fputs (reg_names[REGNO (base)], file);
8307 fprintf (file, "%+d", offset);
8308 else if (REG_P (index))
8309 fprintf (file, "+%s", reg_names[REGNO (index)]);
8310 else if (GET_CODE (index) == SYMBOL_REF
8311 || GET_CODE (index) == LABEL_REF
8312 || GET_CODE (index) == CONST)
8313 fputc ('+', file), output_addr_const (file, index);
8314 else gcc_unreachable ();
8317 else if (GET_CODE (addr) == MINUS
8318 && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
8320 output_addr_const (file, XEXP (addr, 0));
8322 output_addr_const (file, XEXP (addr, 1));
8323 fputs ("-.)", file);
8325 else if (GET_CODE (addr) == LO_SUM)
8327 output_operand (XEXP (addr, 0), 0);
8328 if (TARGET_CM_MEDMID)
8329 fputs ("+%l44(", file);
8331 fputs ("+%lo(", file);
8332 output_address (XEXP (addr, 1));
8336 && GET_CODE (addr) == CONST
8337 && GET_CODE (XEXP (addr, 0)) == MINUS
8338 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST
8339 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS
8340 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)
8342 addr = XEXP (addr, 0);
8343 output_addr_const (file, XEXP (addr, 0));
8344 /* Group the args of the second CONST in parenthesis. */
8346 /* Skip past the second CONST--it does nothing for us. */
8347 output_addr_const (file, XEXP (XEXP (addr, 1), 0));
8348 /* Close the parenthesis. */
8353 output_addr_const (file, addr);
8357 /* Target hook for assembling integer objects. The sparc version has
8358 special handling for aligned DI-mode objects. */
8361 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
8363 /* ??? We only output .xword's for symbols and only then in environments
8364 where the assembler can handle them. */
8365 if (aligned_p && size == 8
8366 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
8370 assemble_integer_with_op ("\t.xword\t", x);
8375 assemble_aligned_integer (4, const0_rtx);
8376 assemble_aligned_integer (4, x);
8380 return default_assemble_integer (x, size, aligned_p);
8383 /* Return the value of a code used in the .proc pseudo-op that says
8384 what kind of result this function returns. For non-C types, we pick
8385 the closest C type. */
8387 #ifndef SHORT_TYPE_SIZE
8388 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8391 #ifndef INT_TYPE_SIZE
8392 #define INT_TYPE_SIZE BITS_PER_WORD
8395 #ifndef LONG_TYPE_SIZE
8396 #define LONG_TYPE_SIZE BITS_PER_WORD
8399 #ifndef LONG_LONG_TYPE_SIZE
8400 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8403 #ifndef FLOAT_TYPE_SIZE
8404 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8407 #ifndef DOUBLE_TYPE_SIZE
8408 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8411 #ifndef LONG_DOUBLE_TYPE_SIZE
8412 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8416 sparc_type_code (register tree type)
8418 register unsigned long qualifiers = 0;
8419 register unsigned shift;
8421 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8422 setting more, since some assemblers will give an error for this. Also,
8423 we must be careful to avoid shifts of 32 bits or more to avoid getting
8424 unpredictable results. */
8426 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
8428 switch (TREE_CODE (type))
8434 qualifiers |= (3 << shift);
8439 qualifiers |= (2 << shift);
8443 case REFERENCE_TYPE:
8445 qualifiers |= (1 << shift);
8449 return (qualifiers | 8);
8452 case QUAL_UNION_TYPE:
8453 return (qualifiers | 9);
8456 return (qualifiers | 10);
8459 return (qualifiers | 16);
8462 /* If this is a range type, consider it to be the underlying
8464 if (TREE_TYPE (type) != 0)
8467 /* Carefully distinguish all the standard types of C,
8468 without messing up if the language is not C. We do this by
8469 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8470 look at both the names and the above fields, but that's redundant.
8471 Any type whose size is between two C types will be considered
8472 to be the wider of the two types. Also, we do not have a
8473 special code to use for "long long", so anything wider than
8474 long is treated the same. Note that we can't distinguish
8475 between "int" and "long" in this code if they are the same
8476 size, but that's fine, since neither can the assembler. */
8478 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
8479 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
8481 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
8482 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
8484 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
8485 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
8488 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
8491 /* If this is a range type, consider it to be the underlying
8493 if (TREE_TYPE (type) != 0)
8496 /* Carefully distinguish all the standard types of C,
8497 without messing up if the language is not C. */
8499 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
8500 return (qualifiers | 6);
8503 return (qualifiers | 7);
8505 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
8506 /* ??? We need to distinguish between double and float complex types,
8507 but I don't know how yet because I can't reach this code from
8508 existing front-ends. */
8509 return (qualifiers | 7); /* Who knows? */
8512 case BOOLEAN_TYPE: /* Boolean truth value type. */
8518 gcc_unreachable (); /* Not a type! */
8525 /* Nested function support. */
8527 /* Emit RTL insns to initialize the variable parts of a trampoline.
8528 FNADDR is an RTX for the address of the function's pure code.
8529 CXT is an RTX for the static chain value for the function.
8531 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8532 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8533 (to store insns). This is a bit excessive. Perhaps a different
8534 mechanism would be better here.
8536 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8539 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8541 /* SPARC 32-bit trampoline:
8544 sethi %hi(static), %g2
8546 or %g2, %lo(static), %g2
8548 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8549 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8553 (adjust_address (m_tramp, SImode, 0),
8554 expand_binop (SImode, ior_optab,
8555 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1),
8556 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
8557 NULL_RTX, 1, OPTAB_DIRECT));
8560 (adjust_address (m_tramp, SImode, 4),
8561 expand_binop (SImode, ior_optab,
8562 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1),
8563 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
8564 NULL_RTX, 1, OPTAB_DIRECT));
8567 (adjust_address (m_tramp, SImode, 8),
8568 expand_binop (SImode, ior_optab,
8569 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
8570 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
8571 NULL_RTX, 1, OPTAB_DIRECT));
8574 (adjust_address (m_tramp, SImode, 12),
8575 expand_binop (SImode, ior_optab,
8576 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
8577 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
8578 NULL_RTX, 1, OPTAB_DIRECT));
8580 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8581 aligned on a 16 byte boundary so one flush clears it all. */
8582 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
8583 if (sparc_cpu != PROCESSOR_ULTRASPARC
8584 && sparc_cpu != PROCESSOR_ULTRASPARC3
8585 && sparc_cpu != PROCESSOR_NIAGARA
8586 && sparc_cpu != PROCESSOR_NIAGARA2
8587 && sparc_cpu != PROCESSOR_NIAGARA3
8588 && sparc_cpu != PROCESSOR_NIAGARA4)
8589 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
8591 /* Call __enable_execute_stack after writing onto the stack to make sure
8592 the stack address is accessible. */
8593 #ifdef HAVE_ENABLE_EXECUTE_STACK
8594 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8595 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8600 /* The 64-bit version is simpler because it makes more sense to load the
8601 values as "immediate" data out of the trampoline. It's also easier since
8602 we can read the PC without clobbering a register. */
8605 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8607 /* SPARC 64-bit trampoline:
8616 emit_move_insn (adjust_address (m_tramp, SImode, 0),
8617 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
8618 emit_move_insn (adjust_address (m_tramp, SImode, 4),
8619 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
8620 emit_move_insn (adjust_address (m_tramp, SImode, 8),
8621 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
8622 emit_move_insn (adjust_address (m_tramp, SImode, 12),
8623 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
8624 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
8625 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
8626 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
8628 if (sparc_cpu != PROCESSOR_ULTRASPARC
8629 && sparc_cpu != PROCESSOR_ULTRASPARC3
8630 && sparc_cpu != PROCESSOR_NIAGARA
8631 && sparc_cpu != PROCESSOR_NIAGARA2
8632 && sparc_cpu != PROCESSOR_NIAGARA3
8633 && sparc_cpu != PROCESSOR_NIAGARA4)
8634 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
8636 /* Call __enable_execute_stack after writing onto the stack to make sure
8637 the stack address is accessible. */
8638 #ifdef HAVE_ENABLE_EXECUTE_STACK
8639 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8640 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8644 /* Worker for TARGET_TRAMPOLINE_INIT. */
8647 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
8649 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
8650 cxt = force_reg (Pmode, cxt);
8652 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
8654 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
8657 /* Adjust the cost of a scheduling dependency. Return the new cost of
8658 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8661 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8663 enum attr_type insn_type;
8665 if (! recog_memoized (insn))
8668 insn_type = get_attr_type (insn);
8670 if (REG_NOTE_KIND (link) == 0)
8672 /* Data dependency; DEP_INSN writes a register that INSN reads some
8675 /* if a load, then the dependence must be on the memory address;
8676 add an extra "cycle". Note that the cost could be two cycles
8677 if the reg was written late in an instruction group; we ca not tell
8679 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8682 /* Get the delay only if the address of the store is the dependence. */
8683 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8685 rtx pat = PATTERN(insn);
8686 rtx dep_pat = PATTERN (dep_insn);
8688 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8689 return cost; /* This should not happen! */
8691 /* The dependency between the two instructions was on the data that
8692 is being stored. Assume that this implies that the address of the
8693 store is not dependent. */
8694 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8697 return cost + 3; /* An approximation. */
8700 /* A shift instruction cannot receive its data from an instruction
8701 in the same cycle; add a one cycle penalty. */
8702 if (insn_type == TYPE_SHIFT)
8703 return cost + 3; /* Split before cascade into shift. */
8707 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8708 INSN writes some cycles later. */
8710 /* These are only significant for the fpu unit; writing a fp reg before
8711 the fpu has finished with it stalls the processor. */
8713 /* Reusing an integer register causes no problems. */
8714 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8722 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8724 enum attr_type insn_type, dep_type;
8725 rtx pat = PATTERN(insn);
8726 rtx dep_pat = PATTERN (dep_insn);
8728 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8731 insn_type = get_attr_type (insn);
8732 dep_type = get_attr_type (dep_insn);
8734 switch (REG_NOTE_KIND (link))
8737 /* Data dependency; DEP_INSN writes a register that INSN reads some
8744 /* Get the delay iff the address of the store is the dependence. */
8745 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8748 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8755 /* If a load, then the dependence must be on the memory address. If
8756 the addresses aren't equal, then it might be a false dependency */
8757 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8759 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8760 || GET_CODE (SET_DEST (dep_pat)) != MEM
8761 || GET_CODE (SET_SRC (pat)) != MEM
8762 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8763 XEXP (SET_SRC (pat), 0)))
8771 /* Compare to branch latency is 0. There is no benefit from
8772 separating compare and branch. */
8773 if (dep_type == TYPE_COMPARE)
8775 /* Floating point compare to branch latency is less than
8776 compare to conditional move. */
8777 if (dep_type == TYPE_FPCMP)
8786 /* Anti-dependencies only penalize the fpu unit. */
8787 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8799 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8803 case PROCESSOR_SUPERSPARC:
8804 cost = supersparc_adjust_cost (insn, link, dep, cost);
8806 case PROCESSOR_HYPERSPARC:
8807 case PROCESSOR_SPARCLITE86X:
8808 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8817 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8818 int sched_verbose ATTRIBUTE_UNUSED,
8819 int max_ready ATTRIBUTE_UNUSED)
8823 sparc_use_sched_lookahead (void)
8825 if (sparc_cpu == PROCESSOR_NIAGARA
8826 || sparc_cpu == PROCESSOR_NIAGARA2
8827 || sparc_cpu == PROCESSOR_NIAGARA3
8828 || sparc_cpu == PROCESSOR_NIAGARA4)
8830 if (sparc_cpu == PROCESSOR_ULTRASPARC
8831 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8833 if ((1 << sparc_cpu) &
8834 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8835 (1 << PROCESSOR_SPARCLITE86X)))
8841 sparc_issue_rate (void)
8845 case PROCESSOR_NIAGARA:
8846 case PROCESSOR_NIAGARA2:
8847 case PROCESSOR_NIAGARA3:
8848 case PROCESSOR_NIAGARA4:
8852 /* Assume V9 processors are capable of at least dual-issue. */
8854 case PROCESSOR_SUPERSPARC:
8856 case PROCESSOR_HYPERSPARC:
8857 case PROCESSOR_SPARCLITE86X:
8859 case PROCESSOR_ULTRASPARC:
8860 case PROCESSOR_ULTRASPARC3:
8866 set_extends (rtx insn)
8868 register rtx pat = PATTERN (insn);
8870 switch (GET_CODE (SET_SRC (pat)))
8872 /* Load and some shift instructions zero extend. */
8875 /* sethi clears the high bits */
8877 /* LO_SUM is used with sethi. sethi cleared the high
8878 bits and the values used with lo_sum are positive */
8880 /* Store flag stores 0 or 1 */
8890 rtx op0 = XEXP (SET_SRC (pat), 0);
8891 rtx op1 = XEXP (SET_SRC (pat), 1);
8892 if (GET_CODE (op1) == CONST_INT)
8893 return INTVAL (op1) >= 0;
8894 if (GET_CODE (op0) != REG)
8896 if (sparc_check_64 (op0, insn) == 1)
8898 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8903 rtx op0 = XEXP (SET_SRC (pat), 0);
8904 rtx op1 = XEXP (SET_SRC (pat), 1);
8905 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8907 if (GET_CODE (op1) == CONST_INT)
8908 return INTVAL (op1) >= 0;
8909 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8912 return GET_MODE (SET_SRC (pat)) == SImode;
8913 /* Positive integers leave the high bits zero. */
8915 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8917 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8920 return - (GET_MODE (SET_SRC (pat)) == SImode);
8922 return sparc_check_64 (SET_SRC (pat), insn);
8928 /* We _ought_ to have only one kind per function, but... */
8929 static GTY(()) rtx sparc_addr_diff_list;
8930 static GTY(()) rtx sparc_addr_list;
8933 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8935 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8937 sparc_addr_diff_list
8938 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8940 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8944 sparc_output_addr_vec (rtx vec)
8946 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8947 int idx, vlen = XVECLEN (body, 0);
8949 #ifdef ASM_OUTPUT_ADDR_VEC_START
8950 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8953 #ifdef ASM_OUTPUT_CASE_LABEL
8954 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8957 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8960 for (idx = 0; idx < vlen; idx++)
8962 ASM_OUTPUT_ADDR_VEC_ELT
8963 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8966 #ifdef ASM_OUTPUT_ADDR_VEC_END
8967 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8972 sparc_output_addr_diff_vec (rtx vec)
8974 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8975 rtx base = XEXP (XEXP (body, 0), 0);
8976 int idx, vlen = XVECLEN (body, 1);
8978 #ifdef ASM_OUTPUT_ADDR_VEC_START
8979 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8982 #ifdef ASM_OUTPUT_CASE_LABEL
8983 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8986 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8989 for (idx = 0; idx < vlen; idx++)
8991 ASM_OUTPUT_ADDR_DIFF_ELT
8994 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8995 CODE_LABEL_NUMBER (base));
8998 #ifdef ASM_OUTPUT_ADDR_VEC_END
8999 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
9004 sparc_output_deferred_case_vectors (void)
9009 if (sparc_addr_list == NULL_RTX
9010 && sparc_addr_diff_list == NULL_RTX)
9013 /* Align to cache line in the function's code section. */
9014 switch_to_section (current_function_section ());
9016 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9018 ASM_OUTPUT_ALIGN (asm_out_file, align);
9020 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
9021 sparc_output_addr_vec (XEXP (t, 0));
9022 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
9023 sparc_output_addr_diff_vec (XEXP (t, 0));
9025 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
9028 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9029 unknown. Return 1 if the high bits are zero, -1 if the register is
9032 sparc_check_64 (rtx x, rtx insn)
9034 /* If a register is set only once it is safe to ignore insns this
9035 code does not know how to handle. The loop will either recognize
9036 the single set and return the correct value or fail to recognize
9041 gcc_assert (GET_CODE (x) == REG);
9043 if (GET_MODE (x) == DImode)
9044 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
9046 if (flag_expensive_optimizations
9047 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
9053 insn = get_last_insn_anywhere ();
9058 while ((insn = PREV_INSN (insn)))
9060 switch (GET_CODE (insn))
9073 rtx pat = PATTERN (insn);
9074 if (GET_CODE (pat) != SET)
9076 if (rtx_equal_p (x, SET_DEST (pat)))
9077 return set_extends (insn);
9078 if (y && rtx_equal_p (y, SET_DEST (pat)))
9079 return set_extends (insn);
9080 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
9088 /* Returns assembly code to perform a DImode shift using
9089 a 64-bit global or out register on SPARC-V8+. */
9091 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
9093 static char asm_code[60];
9095 /* The scratch register is only required when the destination
9096 register is not a 64-bit global or out register. */
9097 if (which_alternative != 2)
9098 operands[3] = operands[0];
9100 /* We can only shift by constants <= 63. */
9101 if (GET_CODE (operands[2]) == CONST_INT)
9102 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
9104 if (GET_CODE (operands[1]) == CONST_INT)
9106 output_asm_insn ("mov\t%1, %3", operands);
9110 output_asm_insn ("sllx\t%H1, 32, %3", operands);
9111 if (sparc_check_64 (operands[1], insn) <= 0)
9112 output_asm_insn ("srl\t%L1, 0, %L1", operands);
9113 output_asm_insn ("or\t%L1, %3, %3", operands);
9116 strcpy(asm_code, opcode);
9118 if (which_alternative != 2)
9119 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9121 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9124 /* Output rtl to increment the profiler label LABELNO
9125 for profiling a function entry. */
9128 sparc_profile_hook (int labelno)
9133 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
9134 if (NO_PROFILE_COUNTERS)
9136 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
9140 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9141 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9142 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
9146 #ifdef TARGET_SOLARIS
9147 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9150 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
9151 tree decl ATTRIBUTE_UNUSED)
9153 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
9155 solaris_elf_asm_comdat_section (name, flags, decl);
9159 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
9161 if (!(flags & SECTION_DEBUG))
9162 fputs (",#alloc", asm_out_file);
9163 if (flags & SECTION_WRITE)
9164 fputs (",#write", asm_out_file);
9165 if (flags & SECTION_TLS)
9166 fputs (",#tls", asm_out_file);
9167 if (flags & SECTION_CODE)
9168 fputs (",#execinstr", asm_out_file);
9170 /* ??? Handle SECTION_BSS. */
9172 fputc ('\n', asm_out_file);
9174 #endif /* TARGET_SOLARIS */
9176 /* We do not allow indirect calls to be optimized into sibling calls.
9178 We cannot use sibling calls when delayed branches are disabled
9179 because they will likely require the call delay slot to be filled.
9181 Also, on SPARC 32-bit we cannot emit a sibling call when the
9182 current function returns a structure. This is because the "unimp
9183 after call" convention would cause the callee to return to the
9184 wrong place. The generic code already disallows cases where the
9185 function being called returns a structure.
9187 It may seem strange how this last case could occur. Usually there
9188 is code after the call which jumps to epilogue code which dumps the
9189 return value into the struct return area. That ought to invalidate
9190 the sibling call right? Well, in the C++ case we can end up passing
9191 the pointer to the struct return area to a constructor (which returns
9192 void) and then nothing else happens. Such a sibling call would look
9193 valid without the added check here.
9195 VxWorks PIC PLT entries require the global pointer to be initialized
9196 on entry. We therefore can't emit sibling calls to them. */
9198 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9201 && flag_delayed_branch
9202 && (TARGET_ARCH64 || ! cfun->returns_struct)
9203 && !(TARGET_VXWORKS_RTP
9205 && !targetm.binds_local_p (decl)));
9208 /* libfunc renaming. */
9211 sparc_init_libfuncs (void)
9215 /* Use the subroutines that Sun's library provides for integer
9216 multiply and divide. The `*' prevents an underscore from
9217 being prepended by the compiler. .umul is a little faster
9219 set_optab_libfunc (smul_optab, SImode, "*.umul");
9220 set_optab_libfunc (sdiv_optab, SImode, "*.div");
9221 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
9222 set_optab_libfunc (smod_optab, SImode, "*.rem");
9223 set_optab_libfunc (umod_optab, SImode, "*.urem");
9225 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9226 set_optab_libfunc (add_optab, TFmode, "_Q_add");
9227 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
9228 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
9229 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
9230 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
9232 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9233 is because with soft-float, the SFmode and DFmode sqrt
9234 instructions will be absent, and the compiler will notice and
9235 try to use the TFmode sqrt instruction for calls to the
9236 builtin function sqrt, but this fails. */
9238 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
9240 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
9241 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
9242 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
9243 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
9244 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
9245 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
9247 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
9248 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
9249 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
9250 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
9252 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
9253 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
9254 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9255 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
9257 if (DITF_CONVERSION_LIBFUNCS)
9259 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
9260 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
9261 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9262 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
9265 if (SUN_CONVERSION_LIBFUNCS)
9267 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9268 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9269 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9270 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9275 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9276 do not exist in the library. Make sure the compiler does not
9277 emit calls to them by accident. (It should always use the
9278 hardware instructions.) */
9279 set_optab_libfunc (smul_optab, SImode, 0);
9280 set_optab_libfunc (sdiv_optab, SImode, 0);
9281 set_optab_libfunc (udiv_optab, SImode, 0);
9282 set_optab_libfunc (smod_optab, SImode, 0);
9283 set_optab_libfunc (umod_optab, SImode, 0);
9285 if (SUN_INTEGER_MULTIPLY_64)
9287 set_optab_libfunc (smul_optab, DImode, "__mul64");
9288 set_optab_libfunc (sdiv_optab, DImode, "__div64");
9289 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
9290 set_optab_libfunc (smod_optab, DImode, "__rem64");
9291 set_optab_libfunc (umod_optab, DImode, "__urem64");
9294 if (SUN_CONVERSION_LIBFUNCS)
9296 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
9297 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
9298 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
9299 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
9304 static tree def_builtin(const char *name, int code, tree type)
9306 return add_builtin_function(name, type, code, BUILT_IN_MD, NULL,
9310 static tree def_builtin_const(const char *name, int code, tree type)
9312 tree t = def_builtin(name, code, type);
9315 TREE_READONLY (t) = 1;
9320 /* Implement the TARGET_INIT_BUILTINS target hook.
9321 Create builtin functions for special SPARC instructions. */
9324 sparc_init_builtins (void)
9327 sparc_vis_init_builtins ();
9330 /* Create builtin functions for VIS 1.0 instructions. */
9333 sparc_vis_init_builtins (void)
9335 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
9336 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
9337 tree v4hi = build_vector_type (intHI_type_node, 4);
9338 tree v2hi = build_vector_type (intHI_type_node, 2);
9339 tree v2si = build_vector_type (intSI_type_node, 2);
9340 tree v1si = build_vector_type (intSI_type_node, 1);
9342 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
9343 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
9344 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
9345 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
9346 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
9347 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
9348 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
9349 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
9350 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
9351 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
9352 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
9353 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
9354 tree v2hi_ftype_v2hi_v2hi = build_function_type_list (v2hi, v2hi, v2hi, 0);
9355 tree v1si_ftype_v1si_v1si = build_function_type_list (v1si, v1si, v1si, 0);
9356 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
9358 intDI_type_node, 0);
9359 tree di_ftype_v8qi_v8qi = build_function_type_list (intDI_type_node,
9361 tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node,
9363 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
9365 intDI_type_node, 0);
9366 tree si_ftype_si_si = build_function_type_list (intSI_type_node,
9368 intSI_type_node, 0);
9369 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
9371 intSI_type_node, 0);
9372 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
9374 intDI_type_node, 0);
9375 tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
9378 tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node,
9381 tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node,
9383 tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
9385 tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node,
9387 tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node,
9389 tree void_ftype_di = build_function_type_list (void_type_node,
9390 intDI_type_node, 0);
9391 tree di_ftype_void = build_function_type_list (intDI_type_node,
9393 tree void_ftype_si = build_function_type_list (void_type_node,
9394 intSI_type_node, 0);
9395 tree sf_ftype_sf_sf = build_function_type_list (float_type_node,
9397 float_type_node, 0);
9398 tree df_ftype_df_df = build_function_type_list (double_type_node,
9400 double_type_node, 0);
9402 /* Packing and expanding vectors. */
9403 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
9405 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
9406 v8qi_ftype_v2si_v8qi);
9407 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
9409 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
9411 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
9412 v8qi_ftype_v4qi_v4qi);
9414 /* Multiplications. */
9415 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
9416 v4hi_ftype_v4qi_v4hi);
9417 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
9418 v4hi_ftype_v4qi_v2hi);
9419 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
9420 v4hi_ftype_v4qi_v2hi);
9421 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
9422 v4hi_ftype_v8qi_v4hi);
9423 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
9424 v4hi_ftype_v8qi_v4hi);
9425 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
9426 v2si_ftype_v4qi_v2hi);
9427 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
9428 v2si_ftype_v4qi_v2hi);
9430 /* Data aligning. */
9431 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
9432 v4hi_ftype_v4hi_v4hi);
9433 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
9434 v8qi_ftype_v8qi_v8qi);
9435 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
9436 v2si_ftype_v2si_v2si);
9437 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis,
9440 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis,
9442 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis,
9447 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
9449 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
9454 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
9456 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
9460 /* Pixel distance. */
9461 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
9462 di_ftype_v8qi_v8qi_di);
9464 /* Edge handling. */
9467 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis,
9469 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis,
9471 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis,
9473 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis,
9475 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis,
9477 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis,
9481 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis,
9483 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis,
9485 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis,
9487 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis,
9489 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis,
9491 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis,
9497 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis,
9499 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis,
9501 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis,
9503 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis,
9505 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis,
9507 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis,
9511 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis,
9513 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis,
9515 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis,
9517 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis,
9519 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis,
9521 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis,
9526 /* Pixel compare. */
9529 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis,
9530 di_ftype_v4hi_v4hi);
9531 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis,
9532 di_ftype_v2si_v2si);
9533 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis,
9534 di_ftype_v4hi_v4hi);
9535 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis,
9536 di_ftype_v2si_v2si);
9537 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis,
9538 di_ftype_v4hi_v4hi);
9539 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis,
9540 di_ftype_v2si_v2si);
9541 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis,
9542 di_ftype_v4hi_v4hi);
9543 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis,
9544 di_ftype_v2si_v2si);
9548 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis,
9549 si_ftype_v4hi_v4hi);
9550 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis,
9551 si_ftype_v2si_v2si);
9552 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis,
9553 si_ftype_v4hi_v4hi);
9554 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis,
9555 si_ftype_v2si_v2si);
9556 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis,
9557 si_ftype_v4hi_v4hi);
9558 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis,
9559 si_ftype_v2si_v2si);
9560 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis,
9561 si_ftype_v4hi_v4hi);
9562 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis,
9563 si_ftype_v2si_v2si);
9566 /* Addition and subtraction. */
9567 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3,
9568 v4hi_ftype_v4hi_v4hi);
9569 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3,
9570 v2hi_ftype_v2hi_v2hi);
9571 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3,
9572 v2si_ftype_v2si_v2si);
9573 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3,
9574 v1si_ftype_v1si_v1si);
9575 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3,
9576 v4hi_ftype_v4hi_v4hi);
9577 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3,
9578 v2hi_ftype_v2hi_v2hi);
9579 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3,
9580 v2si_ftype_v2si_v2si);
9581 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3,
9582 v1si_ftype_v1si_v1si);
9584 /* Three-dimensional array addressing. */
9587 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis,
9589 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis,
9591 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis,
9596 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis,
9598 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis,
9600 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis,
9606 /* Byte mask and shuffle */
9608 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis,
9611 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis,
9613 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis,
9614 v4hi_ftype_v4hi_v4hi);
9615 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis,
9616 v8qi_ftype_v8qi_v8qi);
9617 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis,
9618 v2si_ftype_v2si_v2si);
9619 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis,
9627 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis,
9629 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis,
9631 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis,
9636 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis,
9638 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis,
9640 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis,
9644 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis,
9645 v4hi_ftype_v4hi_v4hi);
9647 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3,
9648 v4hi_ftype_v4hi_v4hi);
9649 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3,
9650 v4hi_ftype_v4hi_v4hi);
9651 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3,
9652 v4hi_ftype_v4hi_v4hi);
9653 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3,
9654 v4hi_ftype_v4hi_v4hi);
9655 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3,
9656 v2si_ftype_v2si_v2si);
9657 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3,
9658 v2si_ftype_v2si_v2si);
9659 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3,
9660 v2si_ftype_v2si_v2si);
9661 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3,
9662 v2si_ftype_v2si_v2si);
9665 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis,
9666 di_ftype_v8qi_v8qi);
9668 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis,
9669 si_ftype_v8qi_v8qi);
9671 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis,
9672 v4hi_ftype_v4hi_v4hi);
9673 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis,
9675 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis,
9678 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3,
9679 v4hi_ftype_v4hi_v4hi);
9680 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3,
9681 v2hi_ftype_v2hi_v2hi);
9682 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3,
9683 v4hi_ftype_v4hi_v4hi);
9684 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3,
9685 v2hi_ftype_v2hi_v2hi);
9686 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3,
9687 v2si_ftype_v2si_v2si);
9688 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3,
9689 v1si_ftype_v1si_v1si);
9690 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3,
9691 v2si_ftype_v2si_v2si);
9692 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3,
9693 v1si_ftype_v1si_v1si);
9697 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis,
9698 di_ftype_v8qi_v8qi);
9699 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis,
9700 di_ftype_v8qi_v8qi);
9701 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis,
9702 di_ftype_v8qi_v8qi);
9703 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis,
9704 di_ftype_v8qi_v8qi);
9708 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis,
9709 si_ftype_v8qi_v8qi);
9710 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis,
9711 si_ftype_v8qi_v8qi);
9712 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis,
9713 si_ftype_v8qi_v8qi);
9714 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis,
9715 si_ftype_v8qi_v8qi);
9718 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
9720 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
9722 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
9724 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
9726 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
9728 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
9731 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
9733 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
9735 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
9740 /* Handle TARGET_EXPAND_BUILTIN target hook.
9741 Expand builtin functions for sparc intrinsics. */
9744 sparc_expand_builtin (tree exp, rtx target,
9745 rtx subtarget ATTRIBUTE_UNUSED,
9746 enum machine_mode tmode ATTRIBUTE_UNUSED,
9747 int ignore ATTRIBUTE_UNUSED)
9750 call_expr_arg_iterator iter;
9751 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9752 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
9757 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9761 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9763 || GET_MODE (target) != tmode
9764 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9765 op[0] = gen_reg_rtx (tmode);
9769 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9771 const struct insn_operand_data *insn_op;
9774 if (arg == error_mark_node)
9778 idx = arg_count - !nonvoid;
9779 insn_op = &insn_data[icode].operand[idx];
9780 op[arg_count] = expand_normal (arg);
9782 if (insn_op->mode == V1DImode
9783 && GET_MODE (op[arg_count]) == DImode)
9784 op[arg_count] = gen_lowpart (V1DImode, op[arg_count]);
9785 else if (insn_op->mode == V1SImode
9786 && GET_MODE (op[arg_count]) == SImode)
9787 op[arg_count] = gen_lowpart (V1SImode, op[arg_count]);
9789 if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count],
9791 op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]);
9797 pat = GEN_FCN (icode) (op[0]);
9801 pat = GEN_FCN (icode) (op[0], op[1]);
9803 pat = GEN_FCN (icode) (op[1]);
9806 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9809 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9827 sparc_vis_mul8x16 (int e8, int e16)
9829 return (e8 * e16 + 128) / 256;
9832 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9833 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9834 constants. A tree list with the results of the multiplications is returned,
9835 and each element in the list is of INNER_TYPE. */
9838 sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
9840 tree n_elts = NULL_TREE;
9845 case CODE_FOR_fmul8x16_vis:
9846 for (; elts0 && elts1;
9847 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9850 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9851 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
9852 n_elts = tree_cons (NULL_TREE,
9853 build_int_cst (inner_type, val),
9858 case CODE_FOR_fmul8x16au_vis:
9859 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9861 for (; elts0; elts0 = TREE_CHAIN (elts0))
9864 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9866 n_elts = tree_cons (NULL_TREE,
9867 build_int_cst (inner_type, val),
9872 case CODE_FOR_fmul8x16al_vis:
9873 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
9875 for (; elts0; elts0 = TREE_CHAIN (elts0))
9878 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9880 n_elts = tree_cons (NULL_TREE,
9881 build_int_cst (inner_type, val),
9890 return nreverse (n_elts);
9893 /* Handle TARGET_FOLD_BUILTIN target hook.
9894 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9895 result of the function call is ignored. NULL_TREE is returned if the
9896 function could not be folded. */
9899 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
9900 tree *args, bool ignore)
9902 tree arg0, arg1, arg2;
9903 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
9904 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
9908 /* Note that a switch statement instead of the sequence of tests would
9909 be incorrect as many of the CODE_FOR values could be CODE_FOR_nothing
9910 and that would yield multiple alternatives with identical values. */
9911 if (icode == CODE_FOR_alignaddrsi_vis
9912 || icode == CODE_FOR_alignaddrdi_vis
9913 || icode == CODE_FOR_wrgsr_vis
9914 || icode == CODE_FOR_bmasksi_vis
9915 || icode == CODE_FOR_bmaskdi_vis
9916 || icode == CODE_FOR_cmask8si_vis
9917 || icode == CODE_FOR_cmask8di_vis
9918 || icode == CODE_FOR_cmask16si_vis
9919 || icode == CODE_FOR_cmask16di_vis
9920 || icode == CODE_FOR_cmask32si_vis
9921 || icode == CODE_FOR_cmask32di_vis)
9924 return build_zero_cst (rtype);
9929 case CODE_FOR_fexpand_vis:
9933 if (TREE_CODE (arg0) == VECTOR_CST)
9935 tree inner_type = TREE_TYPE (rtype);
9936 tree elts = TREE_VECTOR_CST_ELTS (arg0);
9937 tree n_elts = NULL_TREE;
9939 for (; elts; elts = TREE_CHAIN (elts))
9941 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
9942 n_elts = tree_cons (NULL_TREE,
9943 build_int_cst (inner_type, val),
9946 return build_vector (rtype, nreverse (n_elts));
9950 case CODE_FOR_fmul8x16_vis:
9951 case CODE_FOR_fmul8x16au_vis:
9952 case CODE_FOR_fmul8x16al_vis:
9958 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9960 tree inner_type = TREE_TYPE (rtype);
9961 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9962 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9963 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
9966 return build_vector (rtype, n_elts);
9970 case CODE_FOR_fpmerge_vis:
9976 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9978 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9979 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9980 tree n_elts = NULL_TREE;
9982 for (; elts0 && elts1;
9983 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9985 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
9986 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
9989 return build_vector (rtype, nreverse (n_elts));
9993 case CODE_FOR_pdist_vis:
10001 if (TREE_CODE (arg0) == VECTOR_CST
10002 && TREE_CODE (arg1) == VECTOR_CST
10003 && TREE_CODE (arg2) == INTEGER_CST)
10006 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
10007 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
10008 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
10009 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
10011 for (; elts0 && elts1;
10012 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
10014 unsigned HOST_WIDE_INT
10015 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
10016 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
10017 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
10018 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
10020 unsigned HOST_WIDE_INT l;
10023 overflow |= neg_double (low1, high1, &l, &h);
10024 overflow |= add_double (low0, high0, l, h, &l, &h);
10026 overflow |= neg_double (l, h, &l, &h);
10028 overflow |= add_double (low, high, l, h, &low, &high);
10031 gcc_assert (overflow == 0);
10033 return build_int_cst_wide (rtype, low, high);
10043 /* ??? This duplicates information provided to the compiler by the
10044 ??? scheduler description. Some day, teach genautomata to output
10045 ??? the latencies and then CSE will just use that. */
10048 sparc_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
10049 int *total, bool speed ATTRIBUTE_UNUSED)
10051 enum machine_mode mode = GET_MODE (x);
10052 bool float_mode_p = FLOAT_MODE_P (mode);
10057 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
10075 if (GET_MODE (x) == VOIDmode
10076 && ((CONST_DOUBLE_HIGH (x) == 0
10077 && CONST_DOUBLE_LOW (x) < 0x1000)
10078 || (CONST_DOUBLE_HIGH (x) == -1
10079 && CONST_DOUBLE_LOW (x) < 0
10080 && CONST_DOUBLE_LOW (x) >= -0x1000)))
10087 /* If outer-code was a sign or zero extension, a cost
10088 of COSTS_N_INSNS (1) was already added in. This is
10089 why we are subtracting it back out. */
10090 if (outer_code == ZERO_EXTEND)
10092 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
10094 else if (outer_code == SIGN_EXTEND)
10096 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
10098 else if (float_mode_p)
10100 *total = sparc_costs->float_load;
10104 *total = sparc_costs->int_load;
10112 *total = sparc_costs->float_plusminus;
10114 *total = COSTS_N_INSNS (1);
10121 gcc_assert (float_mode_p);
10122 *total = sparc_costs->float_mul;
10125 if (GET_CODE (sub) == NEG)
10126 sub = XEXP (sub, 0);
10127 *total += rtx_cost (sub, FMA, 0, speed);
10130 if (GET_CODE (sub) == NEG)
10131 sub = XEXP (sub, 0);
10132 *total += rtx_cost (sub, FMA, 2, speed);
10138 *total = sparc_costs->float_mul;
10139 else if (! TARGET_HARD_MUL)
10140 *total = COSTS_N_INSNS (25);
10146 if (sparc_costs->int_mul_bit_factor)
10150 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
10152 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
10153 for (nbits = 0; value != 0; value &= value - 1)
10156 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
10157 && GET_MODE (XEXP (x, 1)) == VOIDmode)
10159 rtx x1 = XEXP (x, 1);
10160 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
10161 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
10163 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
10165 for (; value2 != 0; value2 &= value2 - 1)
10173 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
10174 bit_cost = COSTS_N_INSNS (bit_cost);
10177 if (mode == DImode)
10178 *total = sparc_costs->int_mulX + bit_cost;
10180 *total = sparc_costs->int_mul + bit_cost;
10187 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
10196 if (mode == DFmode)
10197 *total = sparc_costs->float_div_df;
10199 *total = sparc_costs->float_div_sf;
10203 if (mode == DImode)
10204 *total = sparc_costs->int_divX;
10206 *total = sparc_costs->int_div;
10211 if (! float_mode_p)
10213 *total = COSTS_N_INSNS (1);
10220 case UNSIGNED_FLOAT:
10224 case FLOAT_TRUNCATE:
10225 *total = sparc_costs->float_move;
10229 if (mode == DFmode)
10230 *total = sparc_costs->float_sqrt_df;
10232 *total = sparc_costs->float_sqrt_sf;
10237 *total = sparc_costs->float_cmp;
10239 *total = COSTS_N_INSNS (1);
10244 *total = sparc_costs->float_cmove;
10246 *total = sparc_costs->int_cmove;
10250 /* Handle the NAND vector patterns. */
10251 if (sparc_vector_mode_supported_p (GET_MODE (x))
10252 && GET_CODE (XEXP (x, 0)) == NOT
10253 && GET_CODE (XEXP (x, 1)) == NOT)
10255 *total = COSTS_N_INSNS (1);
10266 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
10269 general_or_i64_p (reg_class_t rclass)
10271 return (rclass == GENERAL_REGS || rclass == I64_REGS);
10274 /* Implement TARGET_REGISTER_MOVE_COST. */
10277 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10278 reg_class_t from, reg_class_t to)
10280 if ((FP_REG_CLASS_P (from) && general_or_i64_p (to))
10281 || (general_or_i64_p (from) && FP_REG_CLASS_P (to))
10282 || from == FPCC_REGS
10283 || to == FPCC_REGS)
10285 if (sparc_cpu == PROCESSOR_ULTRASPARC
10286 || sparc_cpu == PROCESSOR_ULTRASPARC3
10287 || sparc_cpu == PROCESSOR_NIAGARA
10288 || sparc_cpu == PROCESSOR_NIAGARA2
10289 || sparc_cpu == PROCESSOR_NIAGARA3
10290 || sparc_cpu == PROCESSOR_NIAGARA4)
10299 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
10300 This is achieved by means of a manual dynamic stack space allocation in
10301 the current frame. We make the assumption that SEQ doesn't contain any
10302 function calls, with the possible exception of calls to the GOT helper. */
10305 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
10307 /* We must preserve the lowest 16 words for the register save area. */
10308 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
10309 /* We really need only 2 words of fresh stack space. */
10310 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
10313 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
10314 SPARC_STACK_BIAS + offset));
10316 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
10317 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
10319 emit_insn (gen_rtx_SET (VOIDmode,
10320 adjust_address (slot, word_mode, UNITS_PER_WORD),
10324 emit_insn (gen_rtx_SET (VOIDmode,
10326 adjust_address (slot, word_mode, UNITS_PER_WORD)));
10327 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
10328 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
10331 /* Output the assembler code for a thunk function. THUNK_DECL is the
10332 declaration for the thunk function itself, FUNCTION is the decl for
10333 the target function. DELTA is an immediate constant offset to be
10334 added to THIS. If VCALL_OFFSET is nonzero, the word at address
10335 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
10338 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10339 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10342 rtx this_rtx, insn, funexp;
10343 unsigned int int_arg_first;
10345 reload_completed = 1;
10346 epilogue_completed = 1;
10348 emit_note (NOTE_INSN_PROLOGUE_END);
10352 sparc_leaf_function_p = 1;
10354 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
10356 else if (flag_delayed_branch)
10358 /* We will emit a regular sibcall below, so we need to instruct
10359 output_sibcall that we are in a leaf function. */
10360 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
10362 /* This will cause final.c to invoke leaf_renumber_regs so we
10363 must behave as if we were in a not-yet-leafified function. */
10364 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
10368 /* We will emit the sibcall manually below, so we will need to
10369 manually spill non-leaf registers. */
10370 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
10372 /* We really are in a leaf function. */
10373 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
10376 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
10377 returns a structure, the structure return pointer is there instead. */
10379 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10380 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
10382 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
10384 /* Add DELTA. When possible use a plain add, otherwise load it into
10385 a register first. */
10388 rtx delta_rtx = GEN_INT (delta);
10390 if (! SPARC_SIMM13_P (delta))
10392 rtx scratch = gen_rtx_REG (Pmode, 1);
10393 emit_move_insn (scratch, delta_rtx);
10394 delta_rtx = scratch;
10397 /* THIS_RTX += DELTA. */
10398 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
10401 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
10404 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10405 rtx scratch = gen_rtx_REG (Pmode, 1);
10407 gcc_assert (vcall_offset < 0);
10409 /* SCRATCH = *THIS_RTX. */
10410 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
10412 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10413 may not have any available scratch register at this point. */
10414 if (SPARC_SIMM13_P (vcall_offset))
10416 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10417 else if (! fixed_regs[5]
10418 /* The below sequence is made up of at least 2 insns,
10419 while the default method may need only one. */
10420 && vcall_offset < -8192)
10422 rtx scratch2 = gen_rtx_REG (Pmode, 5);
10423 emit_move_insn (scratch2, vcall_offset_rtx);
10424 vcall_offset_rtx = scratch2;
10428 rtx increment = GEN_INT (-4096);
10430 /* VCALL_OFFSET is a negative number whose typical range can be
10431 estimated as -32768..0 in 32-bit mode. In almost all cases
10432 it is therefore cheaper to emit multiple add insns than
10433 spilling and loading the constant into a register (at least
10435 while (! SPARC_SIMM13_P (vcall_offset))
10437 emit_insn (gen_add2_insn (scratch, increment));
10438 vcall_offset += 4096;
10440 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
10443 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10444 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
10445 gen_rtx_PLUS (Pmode,
10447 vcall_offset_rtx)));
10449 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10450 emit_insn (gen_add2_insn (this_rtx, scratch));
10453 /* Generate a tail call to the target function. */
10454 if (! TREE_USED (function))
10456 assemble_external (function);
10457 TREE_USED (function) = 1;
10459 funexp = XEXP (DECL_RTL (function), 0);
10461 if (flag_delayed_branch)
10463 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10464 insn = emit_call_insn (gen_sibcall (funexp));
10465 SIBLING_CALL_P (insn) = 1;
10469 /* The hoops we have to jump through in order to generate a sibcall
10470 without using delay slots... */
10471 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
10475 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
10477 load_got_register (); /* clobbers %o7 */
10478 scratch = sparc_legitimize_pic_address (funexp, scratch);
10479 seq = get_insns ();
10481 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
10483 else if (TARGET_ARCH32)
10485 emit_insn (gen_rtx_SET (VOIDmode,
10487 gen_rtx_HIGH (SImode, funexp)));
10488 emit_insn (gen_rtx_SET (VOIDmode,
10490 gen_rtx_LO_SUM (SImode, scratch, funexp)));
10492 else /* TARGET_ARCH64 */
10494 switch (sparc_cmodel)
10498 /* The destination can serve as a temporary. */
10499 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
10504 /* The destination cannot serve as a temporary. */
10505 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
10507 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
10508 seq = get_insns ();
10510 emit_and_preserve (seq, spill_reg, 0);
10514 gcc_unreachable ();
10518 emit_jump_insn (gen_indirect_jump (scratch));
10523 /* Run just enough of rest_of_compilation to get the insns emitted.
10524 There's not really enough bulk here to make other passes such as
10525 instruction scheduling worth while. Note that use_thunk calls
10526 assemble_start_function and assemble_end_function. */
10527 insn = get_insns ();
10528 insn_locators_alloc ();
10529 shorten_branches (insn);
10530 final_start_function (insn, file, 1);
10531 final (insn, file, 1);
10532 final_end_function ();
10534 reload_completed = 0;
10535 epilogue_completed = 0;
10538 /* Return true if sparc_output_mi_thunk would be able to output the
10539 assembler code for the thunk function specified by the arguments
10540 it is passed, and false otherwise. */
10542 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
10543 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
10544 HOST_WIDE_INT vcall_offset,
10545 const_tree function ATTRIBUTE_UNUSED)
10547 /* Bound the loop used in the default method above. */
10548 return (vcall_offset >= -32768 || ! fixed_regs[5]);
10551 /* We use the machine specific reorg pass to enable workarounds for errata. */
10558 /* The only erratum we handle for now is that of the AT697F processor. */
10559 if (!sparc_fix_at697f)
10562 /* We need to have the (essentially) final form of the insn stream in order
10563 to properly detect the various hazards. Run delay slot scheduling. */
10564 if (optimize > 0 && flag_delayed_branch)
10565 dbr_schedule (get_insns ());
10567 /* Now look for specific patterns in the insn stream. */
10568 for (insn = get_insns (); insn; insn = next)
10570 bool insert_nop = false;
10573 /* Look for a single-word load into an odd-numbered FP register. */
10574 if (NONJUMP_INSN_P (insn)
10575 && (set = single_set (insn)) != NULL_RTX
10576 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
10577 && MEM_P (SET_SRC (set))
10578 && REG_P (SET_DEST (set))
10579 && REGNO (SET_DEST (set)) > 31
10580 && REGNO (SET_DEST (set)) % 2 != 0)
10582 /* The wrong dependency is on the enclosing double register. */
10583 unsigned int x = REGNO (SET_DEST (set)) - 1;
10584 unsigned int src1, src2, dest;
10587 /* If the insn has a delay slot, then it cannot be problematic. */
10588 next = next_active_insn (insn);
10589 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
10593 extract_insn (next);
10594 code = INSN_CODE (next);
10599 case CODE_FOR_adddf3:
10600 case CODE_FOR_subdf3:
10601 case CODE_FOR_muldf3:
10602 case CODE_FOR_divdf3:
10603 dest = REGNO (recog_data.operand[0]);
10604 src1 = REGNO (recog_data.operand[1]);
10605 src2 = REGNO (recog_data.operand[2]);
10609 ld [address], %fx+1
10610 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
10611 if ((src1 == x || src2 == x)
10612 && (dest == src1 || dest == src2))
10618 ld [address], %fx+1
10619 FPOPd %fx, %fx, %fx */
10622 && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
10627 case CODE_FOR_sqrtdf2:
10628 dest = REGNO (recog_data.operand[0]);
10629 src1 = REGNO (recog_data.operand[1]);
10631 ld [address], %fx+1
10633 if (src1 == x && dest == src1)
10642 next = NEXT_INSN (insn);
10645 emit_insn_after (gen_nop (), insn);
10649 /* How to allocate a 'struct machine_function'. */
10651 static struct machine_function *
10652 sparc_init_machine_status (void)
10654 return ggc_alloc_cleared_machine_function ();
10657 /* Locate some local-dynamic symbol still in use by this function
10658 so that we can print its name in local-dynamic base patterns. */
10660 static const char *
10661 get_some_local_dynamic_name (void)
10665 if (cfun->machine->some_ld_name)
10666 return cfun->machine->some_ld_name;
10668 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10670 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10671 return cfun->machine->some_ld_name;
10673 gcc_unreachable ();
10677 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10682 && GET_CODE (x) == SYMBOL_REF
10683 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10685 cfun->machine->some_ld_name = XSTR (x, 0);
10692 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10693 We need to emit DTP-relative relocations. */
10696 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
10701 fputs ("\t.word\t%r_tls_dtpoff32(", file);
10704 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
10707 gcc_unreachable ();
10709 output_addr_const (file, x);
10713 /* Do whatever processing is required at the end of a file. */
10716 sparc_file_end (void)
10718 /* If we need to emit the special GOT helper function, do so now. */
10719 if (got_helper_rtx)
10721 const char *name = XSTR (got_helper_rtx, 0);
10722 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
10723 #ifdef DWARF2_UNWIND_INFO
10727 if (USE_HIDDEN_LINKONCE)
10729 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
10730 get_identifier (name),
10731 build_function_type_list (void_type_node,
10733 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
10734 NULL_TREE, void_type_node);
10735 TREE_STATIC (decl) = 1;
10736 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
10737 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
10738 DECL_VISIBILITY_SPECIFIED (decl) = 1;
10739 resolve_unique_section (decl, 0, flag_function_sections);
10740 allocate_struct_function (decl, true);
10741 cfun->is_thunk = 1;
10742 current_function_decl = decl;
10743 init_varasm_status ();
10744 assemble_start_function (decl, name);
10748 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
10749 switch_to_section (text_section);
10751 ASM_OUTPUT_ALIGN (asm_out_file, align);
10752 ASM_OUTPUT_LABEL (asm_out_file, name);
10755 #ifdef DWARF2_UNWIND_INFO
10756 do_cfi = dwarf2out_do_cfi_asm ();
10758 fprintf (asm_out_file, "\t.cfi_startproc\n");
10760 if (flag_delayed_branch)
10761 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10762 reg_name, reg_name);
10764 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10765 reg_name, reg_name);
10766 #ifdef DWARF2_UNWIND_INFO
10768 fprintf (asm_out_file, "\t.cfi_endproc\n");
10772 if (NEED_INDICATE_EXEC_STACK)
10773 file_end_indicate_exec_stack ();
10775 #ifdef TARGET_SOLARIS
10776 solaris_file_end ();
10780 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10781 /* Implement TARGET_MANGLE_TYPE. */
10783 static const char *
10784 sparc_mangle_type (const_tree type)
10787 && TYPE_MAIN_VARIANT (type) == long_double_type_node
10788 && TARGET_LONG_DOUBLE_128)
10791 /* For all other types, use normal C++ mangling. */
10796 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10797 compare and swap on the word containing the byte or half-word. */
10800 sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
10802 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
10803 rtx addr = gen_reg_rtx (Pmode);
10804 rtx off = gen_reg_rtx (SImode);
10805 rtx oldv = gen_reg_rtx (SImode);
10806 rtx newv = gen_reg_rtx (SImode);
10807 rtx oldvalue = gen_reg_rtx (SImode);
10808 rtx newvalue = gen_reg_rtx (SImode);
10809 rtx res = gen_reg_rtx (SImode);
10810 rtx resv = gen_reg_rtx (SImode);
10811 rtx memsi, val, mask, end_label, loop_label, cc;
10813 emit_insn (gen_rtx_SET (VOIDmode, addr,
10814 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
10816 if (Pmode != SImode)
10817 addr1 = gen_lowpart (SImode, addr1);
10818 emit_insn (gen_rtx_SET (VOIDmode, off,
10819 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
10821 memsi = gen_rtx_MEM (SImode, addr);
10822 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
10823 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
10825 val = force_reg (SImode, memsi);
10827 emit_insn (gen_rtx_SET (VOIDmode, off,
10828 gen_rtx_XOR (SImode, off,
10829 GEN_INT (GET_MODE (mem) == QImode
10832 emit_insn (gen_rtx_SET (VOIDmode, off,
10833 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
10835 if (GET_MODE (mem) == QImode)
10836 mask = force_reg (SImode, GEN_INT (0xff));
10838 mask = force_reg (SImode, GEN_INT (0xffff));
10840 emit_insn (gen_rtx_SET (VOIDmode, mask,
10841 gen_rtx_ASHIFT (SImode, mask, off)));
10843 emit_insn (gen_rtx_SET (VOIDmode, val,
10844 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10847 oldval = gen_lowpart (SImode, oldval);
10848 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10849 gen_rtx_ASHIFT (SImode, oldval, off)));
10851 newval = gen_lowpart_common (SImode, newval);
10852 emit_insn (gen_rtx_SET (VOIDmode, newv,
10853 gen_rtx_ASHIFT (SImode, newval, off)));
10855 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10856 gen_rtx_AND (SImode, oldv, mask)));
10858 emit_insn (gen_rtx_SET (VOIDmode, newv,
10859 gen_rtx_AND (SImode, newv, mask)));
10861 end_label = gen_label_rtx ();
10862 loop_label = gen_label_rtx ();
10863 emit_label (loop_label);
10865 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
10866 gen_rtx_IOR (SImode, oldv, val)));
10868 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
10869 gen_rtx_IOR (SImode, newv, val)));
10871 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue));
10873 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
10875 emit_insn (gen_rtx_SET (VOIDmode, resv,
10876 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10879 cc = gen_compare_reg_1 (NE, resv, val);
10880 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
10882 /* Use cbranchcc4 to separate the compare and branch! */
10883 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
10884 cc, const0_rtx, loop_label));
10886 emit_label (end_label);
10888 emit_insn (gen_rtx_SET (VOIDmode, res,
10889 gen_rtx_AND (SImode, res, mask)));
10891 emit_insn (gen_rtx_SET (VOIDmode, res,
10892 gen_rtx_LSHIFTRT (SImode, res, off)));
10894 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
10898 sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel)
10902 sel = gen_lowpart (DImode, sel);
10906 /* inp = xxxxxxxAxxxxxxxB */
10907 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
10908 NULL_RTX, 1, OPTAB_DIRECT);
10909 /* t_1 = ....xxxxxxxAxxx. */
10910 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
10911 GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT);
10912 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
10913 GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT);
10914 /* sel = .......B */
10915 /* t_1 = ...A.... */
10916 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
10917 /* sel = ...A...B */
10918 sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1);
10919 /* sel = AAAABBBB * 4 */
10920 t_1 = force_reg (SImode, GEN_INT (0x01230123));
10921 /* sel = { A*4, A*4+1, A*4+2, ... } */
10925 /* inp = xxxAxxxBxxxCxxxD */
10926 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
10927 NULL_RTX, 1, OPTAB_DIRECT);
10928 t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
10929 NULL_RTX, 1, OPTAB_DIRECT);
10930 t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24),
10931 NULL_RTX, 1, OPTAB_DIRECT);
10932 /* t_1 = ..xxxAxxxBxxxCxx */
10933 /* t_2 = ....xxxAxxxBxxxC */
10934 /* t_3 = ......xxxAxxxBxx */
10935 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
10937 NULL_RTX, 1, OPTAB_DIRECT);
10938 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
10940 NULL_RTX, 1, OPTAB_DIRECT);
10941 t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2),
10942 GEN_INT (0x070000),
10943 NULL_RTX, 1, OPTAB_DIRECT);
10944 t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3),
10945 GEN_INT (0x07000000),
10946 NULL_RTX, 1, OPTAB_DIRECT);
10947 /* sel = .......D */
10948 /* t_1 = .....C.. */
10949 /* t_2 = ...B.... */
10950 /* t_3 = .A...... */
10951 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
10952 t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT);
10953 sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT);
10954 /* sel = .A.B.C.D */
10955 sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1);
10956 /* sel = AABBCCDD * 2 */
10957 t_1 = force_reg (SImode, GEN_INT (0x01010101));
10958 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
10962 /* input = xAxBxCxDxExFxGxH */
10963 sel = expand_simple_binop (DImode, AND, sel,
10964 GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32
10966 NULL_RTX, 1, OPTAB_DIRECT);
10967 /* sel = .A.B.C.D.E.F.G.H */
10968 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4),
10969 NULL_RTX, 1, OPTAB_DIRECT);
10970 /* t_1 = ..A.B.C.D.E.F.G. */
10971 sel = expand_simple_binop (DImode, IOR, sel, t_1,
10972 NULL_RTX, 1, OPTAB_DIRECT);
10973 /* sel = .AABBCCDDEEFFGGH */
10974 sel = expand_simple_binop (DImode, AND, sel,
10975 GEN_INT ((HOST_WIDE_INT)0xff00ff << 32
10977 NULL_RTX, 1, OPTAB_DIRECT);
10978 /* sel = ..AB..CD..EF..GH */
10979 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
10980 NULL_RTX, 1, OPTAB_DIRECT);
10981 /* t_1 = ....AB..CD..EF.. */
10982 sel = expand_simple_binop (DImode, IOR, sel, t_1,
10983 NULL_RTX, 1, OPTAB_DIRECT);
10984 /* sel = ..ABABCDCDEFEFGH */
10985 sel = expand_simple_binop (DImode, AND, sel,
10986 GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff),
10987 NULL_RTX, 1, OPTAB_DIRECT);
10988 /* sel = ....ABCD....EFGH */
10989 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
10990 NULL_RTX, 1, OPTAB_DIRECT);
10991 /* t_1 = ........ABCD.... */
10992 sel = gen_lowpart (SImode, sel);
10993 t_1 = gen_lowpart (SImode, t_1);
10997 gcc_unreachable ();
11000 /* Always perform the final addition/merge within the bmask insn. */
11001 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
11004 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11007 sparc_frame_pointer_required (void)
11009 /* If the stack pointer is dynamically modified in the function, it cannot
11010 serve as the frame pointer. */
11011 if (cfun->calls_alloca)
11014 /* If the function receives nonlocal gotos, it needs to save the frame
11015 pointer in the nonlocal_goto_save_area object. */
11016 if (cfun->has_nonlocal_label)
11019 /* In flat mode, that's it. */
11023 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11024 return !(current_function_is_leaf && only_leaf_regs_used ());
11027 /* The way this is structured, we can't eliminate SFP in favor of SP
11028 if the frame pointer is required: we want to use the SFP->HFP elimination
11029 in that case. But the test in update_eliminables doesn't know we are
11030 assuming below that we only do the former elimination. */
11033 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
11035 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
11038 /* Return the hard frame pointer directly to bypass the stack bias. */
11041 sparc_builtin_setjmp_frame_value (void)
11043 return hard_frame_pointer_rtx;
11046 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
11047 they won't be allocated. */
11050 sparc_conditional_register_usage (void)
11052 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
11054 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11055 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11057 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
11058 /* then honor it. */
11059 if (TARGET_ARCH32 && fixed_regs[5])
11061 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
11066 for (regno = SPARC_FIRST_V9_FP_REG;
11067 regno <= SPARC_LAST_V9_FP_REG;
11069 fixed_regs[regno] = 1;
11070 /* %fcc0 is used by v8 and v9. */
11071 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
11072 regno <= SPARC_LAST_V9_FCC_REG;
11074 fixed_regs[regno] = 1;
11079 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
11080 fixed_regs[regno] = 1;
11082 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
11083 /* then honor it. Likewise with g3 and g4. */
11084 if (fixed_regs[2] == 2)
11085 fixed_regs[2] = ! TARGET_APP_REGS;
11086 if (fixed_regs[3] == 2)
11087 fixed_regs[3] = ! TARGET_APP_REGS;
11088 if (TARGET_ARCH32 && fixed_regs[4] == 2)
11089 fixed_regs[4] = ! TARGET_APP_REGS;
11090 else if (TARGET_CM_EMBMEDANY)
11092 else if (fixed_regs[4] == 2)
11097 /* Disable leaf functions. */
11098 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
11099 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
11100 leaf_reg_remap [regno] = regno;
11103 global_regs[SPARC_GSR_REG] = 1;
11106 /* Implement TARGET_PREFERRED_RELOAD_CLASS
11108 - We can't load constants into FP registers.
11109 - We can't load FP constants into integer registers when soft-float,
11110 because there is no soft-float pattern with a r/F constraint.
11111 - We can't load FP constants into integer registers for TFmode unless
11112 it is 0.0L, because there is no movtf pattern with a r/F constraint.
11113 - Try and reload integer constants (symbolic or otherwise) back into
11114 registers directly, rather than having them dumped to memory. */
11117 sparc_preferred_reload_class (rtx x, reg_class_t rclass)
11119 if (CONSTANT_P (x))
11121 if (FP_REG_CLASS_P (rclass)
11122 || rclass == GENERAL_OR_FP_REGS
11123 || rclass == GENERAL_OR_EXTRA_FP_REGS
11124 || (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT && ! TARGET_FPU)
11125 || (GET_MODE (x) == TFmode && ! const_zero_operand (x, TFmode)))
11128 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11129 return GENERAL_REGS;
11136 output_v8plus_mult (rtx insn, rtx *operands, const char *name)
11140 gcc_assert (! TARGET_ARCH64);
11142 if (sparc_check_64 (operands[1], insn) <= 0)
11143 output_asm_insn ("srl\t%L1, 0, %L1", operands);
11144 if (which_alternative == 1)
11145 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
11146 if (GET_CODE (operands[2]) == CONST_INT)
11148 if (which_alternative == 1)
11150 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11151 sprintf (mulstr, "%s\t%%H1, %%2, %%L0", name);
11152 output_asm_insn (mulstr, operands);
11153 return "srlx\t%L0, 32, %H0";
11157 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11158 output_asm_insn ("or\t%L1, %3, %3", operands);
11159 sprintf (mulstr, "%s\t%%3, %%2, %%3", name);
11160 output_asm_insn (mulstr, operands);
11161 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11162 return "mov\t%3, %L0";
11165 else if (rtx_equal_p (operands[1], operands[2]))
11167 if (which_alternative == 1)
11169 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11170 sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", name);
11171 output_asm_insn (mulstr, operands);
11172 return "srlx\t%L0, 32, %H0";
11176 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11177 output_asm_insn ("or\t%L1, %3, %3", operands);
11178 sprintf (mulstr, "%s\t%%3, %%3, %%3", name);
11179 output_asm_insn (mulstr, operands);
11180 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11181 return "mov\t%3, %L0";
11184 if (sparc_check_64 (operands[2], insn) <= 0)
11185 output_asm_insn ("srl\t%L2, 0, %L2", operands);
11186 if (which_alternative == 1)
11188 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11189 output_asm_insn ("sllx\t%H2, 32, %L1", operands);
11190 output_asm_insn ("or\t%L2, %L1, %L1", operands);
11191 sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", name);
11192 output_asm_insn (mulstr, operands);
11193 return "srlx\t%L0, 32, %H0";
11197 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11198 output_asm_insn ("sllx\t%H2, 32, %4", operands);
11199 output_asm_insn ("or\t%L1, %3, %3", operands);
11200 output_asm_insn ("or\t%L2, %4, %4", operands);
11201 sprintf (mulstr, "%s\t%%3, %%4, %%3", name);
11202 output_asm_insn (mulstr, operands);
11203 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11204 return "mov\t%3, %L0";
11209 sparc_expand_vector_init (rtx target, rtx vals)
11211 enum machine_mode mode = GET_MODE (target);
11212 enum machine_mode inner_mode = GET_MODE_INNER (mode);
11213 int n_elts = GET_MODE_NUNITS (mode);
11217 for (i = 0; i < n_elts; i++)
11219 rtx x = XVECEXP (vals, 0, i);
11220 if (!CONSTANT_P (x))
11226 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
11230 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
11231 for (i = 0; i < n_elts; i++)
11232 emit_move_insn (adjust_address_nv (mem, inner_mode,
11233 i * GET_MODE_SIZE (inner_mode)),
11234 XVECEXP (vals, 0, i));
11235 emit_move_insn (target, mem);
11239 sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
11240 enum machine_mode mode, secondary_reload_info *sri)
11242 enum reg_class rclass = (enum reg_class) rclass_i;
11244 /* We need a temporary when loading/storing a HImode/QImode value
11245 between memory and the FPU registers. This can happen when combine puts
11246 a paradoxical subreg in a float/fix conversion insn. */
11247 if (FP_REG_CLASS_P (rclass)
11248 && (mode == HImode || mode == QImode)
11249 && (GET_CODE (x) == MEM
11250 || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
11251 && true_regnum (x) == -1)))
11252 return GENERAL_REGS;
11254 /* On 32-bit we need a temporary when loading/storing a DFmode value
11255 between unaligned memory and the upper FPU registers. */
11257 && rclass == EXTRA_FP_REGS
11259 && GET_CODE (x) == MEM
11260 && ! mem_min_alignment (x, 8))
11263 if (((TARGET_CM_MEDANY
11264 && symbolic_operand (x, mode))
11265 || (TARGET_CM_EMBMEDANY
11266 && text_segment_operand (x, mode)))
11270 sri->icode = direct_optab_handler (reload_in_optab, mode);
11272 sri->icode = direct_optab_handler (reload_out_optab, mode);
11279 #include "gt-sparc.h"