1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
28 #include "stringpool.h"
29 #include "stor-layout.h"
34 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "insn-codes.h"
37 #include "conditions.h"
39 #include "insn-attr.h"
46 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "pointer-set.h"
54 #include "hash-table.h"
56 #include "basic-block.h"
57 #include "tree-ssa-alias.h"
58 #include "internal-fn.h"
59 #include "gimple-fold.h"
61 #include "gimple-expr.h"
65 #include "langhooks.h"
70 #include "tree-pass.h"
76 struct processor_costs {
80 /* Integer signed load */
83 /* Integer zeroed load */
89 /* fmov, fneg, fabs */
93 const int float_plusminus;
99 const int float_cmove;
105 const int float_div_sf;
108 const int float_div_df;
111 const int float_sqrt_sf;
114 const int float_sqrt_df;
122 /* integer multiply cost for each bit set past the most
123 significant 3, so the formula for multiply cost becomes:
126 highest_bit = highest_clear_bit(rs1);
128 highest_bit = highest_set_bit(rs1);
131 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
133 A value of zero indicates that the multiply costs is fixed,
135 const int int_mul_bit_factor;
146 /* penalty for shifts, due to scheduling rules etc. */
147 const int shift_penalty;
151 struct processor_costs cypress_costs = {
152 COSTS_N_INSNS (2), /* int load */
153 COSTS_N_INSNS (2), /* int signed load */
154 COSTS_N_INSNS (2), /* int zeroed load */
155 COSTS_N_INSNS (2), /* float load */
156 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
157 COSTS_N_INSNS (5), /* fadd, fsub */
158 COSTS_N_INSNS (1), /* fcmp */
159 COSTS_N_INSNS (1), /* fmov, fmovr */
160 COSTS_N_INSNS (7), /* fmul */
161 COSTS_N_INSNS (37), /* fdivs */
162 COSTS_N_INSNS (37), /* fdivd */
163 COSTS_N_INSNS (63), /* fsqrts */
164 COSTS_N_INSNS (63), /* fsqrtd */
165 COSTS_N_INSNS (1), /* imul */
166 COSTS_N_INSNS (1), /* imulX */
167 0, /* imul bit factor */
168 COSTS_N_INSNS (1), /* idiv */
169 COSTS_N_INSNS (1), /* idivX */
170 COSTS_N_INSNS (1), /* movcc/movr */
171 0, /* shift penalty */
175 struct processor_costs supersparc_costs = {
176 COSTS_N_INSNS (1), /* int load */
177 COSTS_N_INSNS (1), /* int signed load */
178 COSTS_N_INSNS (1), /* int zeroed load */
179 COSTS_N_INSNS (0), /* float load */
180 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
181 COSTS_N_INSNS (3), /* fadd, fsub */
182 COSTS_N_INSNS (3), /* fcmp */
183 COSTS_N_INSNS (1), /* fmov, fmovr */
184 COSTS_N_INSNS (3), /* fmul */
185 COSTS_N_INSNS (6), /* fdivs */
186 COSTS_N_INSNS (9), /* fdivd */
187 COSTS_N_INSNS (12), /* fsqrts */
188 COSTS_N_INSNS (12), /* fsqrtd */
189 COSTS_N_INSNS (4), /* imul */
190 COSTS_N_INSNS (4), /* imulX */
191 0, /* imul bit factor */
192 COSTS_N_INSNS (4), /* idiv */
193 COSTS_N_INSNS (4), /* idivX */
194 COSTS_N_INSNS (1), /* movcc/movr */
195 1, /* shift penalty */
199 struct processor_costs hypersparc_costs = {
200 COSTS_N_INSNS (1), /* int load */
201 COSTS_N_INSNS (1), /* int signed load */
202 COSTS_N_INSNS (1), /* int zeroed load */
203 COSTS_N_INSNS (1), /* float load */
204 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
205 COSTS_N_INSNS (1), /* fadd, fsub */
206 COSTS_N_INSNS (1), /* fcmp */
207 COSTS_N_INSNS (1), /* fmov, fmovr */
208 COSTS_N_INSNS (1), /* fmul */
209 COSTS_N_INSNS (8), /* fdivs */
210 COSTS_N_INSNS (12), /* fdivd */
211 COSTS_N_INSNS (17), /* fsqrts */
212 COSTS_N_INSNS (17), /* fsqrtd */
213 COSTS_N_INSNS (17), /* imul */
214 COSTS_N_INSNS (17), /* imulX */
215 0, /* imul bit factor */
216 COSTS_N_INSNS (17), /* idiv */
217 COSTS_N_INSNS (17), /* idivX */
218 COSTS_N_INSNS (1), /* movcc/movr */
219 0, /* shift penalty */
223 struct processor_costs leon_costs = {
224 COSTS_N_INSNS (1), /* int load */
225 COSTS_N_INSNS (1), /* int signed load */
226 COSTS_N_INSNS (1), /* int zeroed load */
227 COSTS_N_INSNS (1), /* float load */
228 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
229 COSTS_N_INSNS (1), /* fadd, fsub */
230 COSTS_N_INSNS (1), /* fcmp */
231 COSTS_N_INSNS (1), /* fmov, fmovr */
232 COSTS_N_INSNS (1), /* fmul */
233 COSTS_N_INSNS (15), /* fdivs */
234 COSTS_N_INSNS (15), /* fdivd */
235 COSTS_N_INSNS (23), /* fsqrts */
236 COSTS_N_INSNS (23), /* fsqrtd */
237 COSTS_N_INSNS (5), /* imul */
238 COSTS_N_INSNS (5), /* imulX */
239 0, /* imul bit factor */
240 COSTS_N_INSNS (5), /* idiv */
241 COSTS_N_INSNS (5), /* idivX */
242 COSTS_N_INSNS (1), /* movcc/movr */
243 0, /* shift penalty */
247 struct processor_costs leon3_costs = {
248 COSTS_N_INSNS (1), /* int load */
249 COSTS_N_INSNS (1), /* int signed load */
250 COSTS_N_INSNS (1), /* int zeroed load */
251 COSTS_N_INSNS (1), /* float load */
252 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
253 COSTS_N_INSNS (1), /* fadd, fsub */
254 COSTS_N_INSNS (1), /* fcmp */
255 COSTS_N_INSNS (1), /* fmov, fmovr */
256 COSTS_N_INSNS (1), /* fmul */
257 COSTS_N_INSNS (14), /* fdivs */
258 COSTS_N_INSNS (15), /* fdivd */
259 COSTS_N_INSNS (22), /* fsqrts */
260 COSTS_N_INSNS (23), /* fsqrtd */
261 COSTS_N_INSNS (5), /* imul */
262 COSTS_N_INSNS (5), /* imulX */
263 0, /* imul bit factor */
264 COSTS_N_INSNS (35), /* idiv */
265 COSTS_N_INSNS (35), /* idivX */
266 COSTS_N_INSNS (1), /* movcc/movr */
267 0, /* shift penalty */
271 struct processor_costs sparclet_costs = {
272 COSTS_N_INSNS (3), /* int load */
273 COSTS_N_INSNS (3), /* int signed load */
274 COSTS_N_INSNS (1), /* int zeroed load */
275 COSTS_N_INSNS (1), /* float load */
276 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
277 COSTS_N_INSNS (1), /* fadd, fsub */
278 COSTS_N_INSNS (1), /* fcmp */
279 COSTS_N_INSNS (1), /* fmov, fmovr */
280 COSTS_N_INSNS (1), /* fmul */
281 COSTS_N_INSNS (1), /* fdivs */
282 COSTS_N_INSNS (1), /* fdivd */
283 COSTS_N_INSNS (1), /* fsqrts */
284 COSTS_N_INSNS (1), /* fsqrtd */
285 COSTS_N_INSNS (5), /* imul */
286 COSTS_N_INSNS (5), /* imulX */
287 0, /* imul bit factor */
288 COSTS_N_INSNS (5), /* idiv */
289 COSTS_N_INSNS (5), /* idivX */
290 COSTS_N_INSNS (1), /* movcc/movr */
291 0, /* shift penalty */
295 struct processor_costs ultrasparc_costs = {
296 COSTS_N_INSNS (2), /* int load */
297 COSTS_N_INSNS (3), /* int signed load */
298 COSTS_N_INSNS (2), /* int zeroed load */
299 COSTS_N_INSNS (2), /* float load */
300 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
301 COSTS_N_INSNS (4), /* fadd, fsub */
302 COSTS_N_INSNS (1), /* fcmp */
303 COSTS_N_INSNS (2), /* fmov, fmovr */
304 COSTS_N_INSNS (4), /* fmul */
305 COSTS_N_INSNS (13), /* fdivs */
306 COSTS_N_INSNS (23), /* fdivd */
307 COSTS_N_INSNS (13), /* fsqrts */
308 COSTS_N_INSNS (23), /* fsqrtd */
309 COSTS_N_INSNS (4), /* imul */
310 COSTS_N_INSNS (4), /* imulX */
311 2, /* imul bit factor */
312 COSTS_N_INSNS (37), /* idiv */
313 COSTS_N_INSNS (68), /* idivX */
314 COSTS_N_INSNS (2), /* movcc/movr */
315 2, /* shift penalty */
319 struct processor_costs ultrasparc3_costs = {
320 COSTS_N_INSNS (2), /* int load */
321 COSTS_N_INSNS (3), /* int signed load */
322 COSTS_N_INSNS (3), /* int zeroed load */
323 COSTS_N_INSNS (2), /* float load */
324 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
325 COSTS_N_INSNS (4), /* fadd, fsub */
326 COSTS_N_INSNS (5), /* fcmp */
327 COSTS_N_INSNS (3), /* fmov, fmovr */
328 COSTS_N_INSNS (4), /* fmul */
329 COSTS_N_INSNS (17), /* fdivs */
330 COSTS_N_INSNS (20), /* fdivd */
331 COSTS_N_INSNS (20), /* fsqrts */
332 COSTS_N_INSNS (29), /* fsqrtd */
333 COSTS_N_INSNS (6), /* imul */
334 COSTS_N_INSNS (6), /* imulX */
335 0, /* imul bit factor */
336 COSTS_N_INSNS (40), /* idiv */
337 COSTS_N_INSNS (71), /* idivX */
338 COSTS_N_INSNS (2), /* movcc/movr */
339 0, /* shift penalty */
343 struct processor_costs niagara_costs = {
344 COSTS_N_INSNS (3), /* int load */
345 COSTS_N_INSNS (3), /* int signed load */
346 COSTS_N_INSNS (3), /* int zeroed load */
347 COSTS_N_INSNS (9), /* float load */
348 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
349 COSTS_N_INSNS (8), /* fadd, fsub */
350 COSTS_N_INSNS (26), /* fcmp */
351 COSTS_N_INSNS (8), /* fmov, fmovr */
352 COSTS_N_INSNS (29), /* fmul */
353 COSTS_N_INSNS (54), /* fdivs */
354 COSTS_N_INSNS (83), /* fdivd */
355 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
356 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
357 COSTS_N_INSNS (11), /* imul */
358 COSTS_N_INSNS (11), /* imulX */
359 0, /* imul bit factor */
360 COSTS_N_INSNS (72), /* idiv */
361 COSTS_N_INSNS (72), /* idivX */
362 COSTS_N_INSNS (1), /* movcc/movr */
363 0, /* shift penalty */
367 struct processor_costs niagara2_costs = {
368 COSTS_N_INSNS (3), /* int load */
369 COSTS_N_INSNS (3), /* int signed load */
370 COSTS_N_INSNS (3), /* int zeroed load */
371 COSTS_N_INSNS (3), /* float load */
372 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
373 COSTS_N_INSNS (6), /* fadd, fsub */
374 COSTS_N_INSNS (6), /* fcmp */
375 COSTS_N_INSNS (6), /* fmov, fmovr */
376 COSTS_N_INSNS (6), /* fmul */
377 COSTS_N_INSNS (19), /* fdivs */
378 COSTS_N_INSNS (33), /* fdivd */
379 COSTS_N_INSNS (19), /* fsqrts */
380 COSTS_N_INSNS (33), /* fsqrtd */
381 COSTS_N_INSNS (5), /* imul */
382 COSTS_N_INSNS (5), /* imulX */
383 0, /* imul bit factor */
384 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
385 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
386 COSTS_N_INSNS (1), /* movcc/movr */
387 0, /* shift penalty */
391 struct processor_costs niagara3_costs = {
392 COSTS_N_INSNS (3), /* int load */
393 COSTS_N_INSNS (3), /* int signed load */
394 COSTS_N_INSNS (3), /* int zeroed load */
395 COSTS_N_INSNS (3), /* float load */
396 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
397 COSTS_N_INSNS (9), /* fadd, fsub */
398 COSTS_N_INSNS (9), /* fcmp */
399 COSTS_N_INSNS (9), /* fmov, fmovr */
400 COSTS_N_INSNS (9), /* fmul */
401 COSTS_N_INSNS (23), /* fdivs */
402 COSTS_N_INSNS (37), /* fdivd */
403 COSTS_N_INSNS (23), /* fsqrts */
404 COSTS_N_INSNS (37), /* fsqrtd */
405 COSTS_N_INSNS (9), /* imul */
406 COSTS_N_INSNS (9), /* imulX */
407 0, /* imul bit factor */
408 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
409 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
410 COSTS_N_INSNS (1), /* movcc/movr */
411 0, /* shift penalty */
415 struct processor_costs niagara4_costs = {
416 COSTS_N_INSNS (5), /* int load */
417 COSTS_N_INSNS (5), /* int signed load */
418 COSTS_N_INSNS (5), /* int zeroed load */
419 COSTS_N_INSNS (5), /* float load */
420 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
421 COSTS_N_INSNS (11), /* fadd, fsub */
422 COSTS_N_INSNS (11), /* fcmp */
423 COSTS_N_INSNS (11), /* fmov, fmovr */
424 COSTS_N_INSNS (11), /* fmul */
425 COSTS_N_INSNS (24), /* fdivs */
426 COSTS_N_INSNS (37), /* fdivd */
427 COSTS_N_INSNS (24), /* fsqrts */
428 COSTS_N_INSNS (37), /* fsqrtd */
429 COSTS_N_INSNS (12), /* imul */
430 COSTS_N_INSNS (12), /* imulX */
431 0, /* imul bit factor */
432 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
433 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
434 COSTS_N_INSNS (1), /* movcc/movr */
435 0, /* shift penalty */
438 static const struct processor_costs *sparc_costs = &cypress_costs;
440 #ifdef HAVE_AS_RELAX_OPTION
441 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
442 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
443 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
444 somebody does not branch between the sethi and jmp. */
445 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
447 #define LEAF_SIBCALL_SLOT_RESERVED_P \
448 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
451 /* Vector to say how input registers are mapped to output registers.
452 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
453 eliminate it. You must use -fomit-frame-pointer to get that. */
454 char leaf_reg_remap[] =
455 { 0, 1, 2, 3, 4, 5, 6, 7,
456 -1, -1, -1, -1, -1, -1, 14, -1,
457 -1, -1, -1, -1, -1, -1, -1, -1,
458 8, 9, 10, 11, 12, 13, -1, 15,
460 32, 33, 34, 35, 36, 37, 38, 39,
461 40, 41, 42, 43, 44, 45, 46, 47,
462 48, 49, 50, 51, 52, 53, 54, 55,
463 56, 57, 58, 59, 60, 61, 62, 63,
464 64, 65, 66, 67, 68, 69, 70, 71,
465 72, 73, 74, 75, 76, 77, 78, 79,
466 80, 81, 82, 83, 84, 85, 86, 87,
467 88, 89, 90, 91, 92, 93, 94, 95,
468 96, 97, 98, 99, 100, 101, 102};
470 /* Vector, indexed by hard register number, which contains 1
471 for a register that is allowable in a candidate for leaf
472 function treatment. */
473 char sparc_leaf_regs[] =
474 { 1, 1, 1, 1, 1, 1, 1, 1,
475 0, 0, 0, 0, 0, 0, 1, 0,
476 0, 0, 0, 0, 0, 0, 0, 0,
477 1, 1, 1, 1, 1, 1, 0, 1,
478 1, 1, 1, 1, 1, 1, 1, 1,
479 1, 1, 1, 1, 1, 1, 1, 1,
480 1, 1, 1, 1, 1, 1, 1, 1,
481 1, 1, 1, 1, 1, 1, 1, 1,
482 1, 1, 1, 1, 1, 1, 1, 1,
483 1, 1, 1, 1, 1, 1, 1, 1,
484 1, 1, 1, 1, 1, 1, 1, 1,
485 1, 1, 1, 1, 1, 1, 1, 1,
486 1, 1, 1, 1, 1, 1, 1};
488 struct GTY(()) machine_function
490 /* Size of the frame of the function. */
491 HOST_WIDE_INT frame_size;
493 /* Size of the frame of the function minus the register window save area
494 and the outgoing argument area. */
495 HOST_WIDE_INT apparent_frame_size;
497 /* Register we pretend the frame pointer is allocated to. Normally, this
498 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
499 record "offset" separately as it may be too big for (reg + disp). */
501 HOST_WIDE_INT frame_base_offset;
503 /* Some local-dynamic TLS symbol name. */
504 const char *some_ld_name;
506 /* Number of global or FP registers to be saved (as 4-byte quantities). */
507 int n_global_fp_regs;
509 /* True if the current function is leaf and uses only leaf regs,
510 so that the SPARC leaf function optimization can be applied.
511 Private version of crtl->uses_only_leaf_regs, see
512 sparc_expand_prologue for the rationale. */
515 /* True if the prologue saves local or in registers. */
516 bool save_local_in_regs_p;
518 /* True if the data calculated by sparc_expand_prologue are valid. */
519 bool prologue_data_valid_p;
522 #define sparc_frame_size cfun->machine->frame_size
523 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
524 #define sparc_frame_base_reg cfun->machine->frame_base_reg
525 #define sparc_frame_base_offset cfun->machine->frame_base_offset
526 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
527 #define sparc_leaf_function_p cfun->machine->leaf_function_p
528 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
529 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
531 /* 1 if the next opcode is to be specially indented. */
532 int sparc_indent_opcode = 0;
534 static void sparc_option_override (void);
535 static void sparc_init_modes (void);
536 static void scan_record_type (const_tree, int *, int *, int *);
537 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
538 const_tree, bool, bool, int *, int *);
540 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
541 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
543 static void sparc_emit_set_const32 (rtx, rtx);
544 static void sparc_emit_set_const64 (rtx, rtx);
545 static void sparc_output_addr_vec (rtx);
546 static void sparc_output_addr_diff_vec (rtx);
547 static void sparc_output_deferred_case_vectors (void);
548 static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
549 static bool sparc_legitimate_constant_p (enum machine_mode, rtx);
550 static rtx sparc_builtin_saveregs (void);
551 static int epilogue_renumber (rtx *, int);
552 static bool sparc_assemble_integer (rtx, unsigned int, int);
553 static int set_extends (rtx);
554 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
555 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
556 #ifdef TARGET_SOLARIS
557 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
558 tree) ATTRIBUTE_UNUSED;
560 static int sparc_adjust_cost (rtx, rtx, rtx, int);
561 static int sparc_issue_rate (void);
562 static void sparc_sched_init (FILE *, int, int);
563 static int sparc_use_sched_lookahead (void);
565 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
566 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
567 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
568 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
569 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
571 static bool sparc_function_ok_for_sibcall (tree, tree);
572 static void sparc_init_libfuncs (void);
573 static void sparc_init_builtins (void);
574 static void sparc_fpu_init_builtins (void);
575 static void sparc_vis_init_builtins (void);
576 static tree sparc_builtin_decl (unsigned, bool);
577 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
578 static tree sparc_fold_builtin (tree, int, tree *, bool);
579 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
580 HOST_WIDE_INT, tree);
581 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
582 HOST_WIDE_INT, const_tree);
583 static struct machine_function * sparc_init_machine_status (void);
584 static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
585 static rtx sparc_tls_get_addr (void);
586 static rtx sparc_tls_got (void);
587 static const char *get_some_local_dynamic_name (void);
588 static int get_some_local_dynamic_name_1 (rtx *, void *);
589 static int sparc_register_move_cost (enum machine_mode,
590 reg_class_t, reg_class_t);
591 static bool sparc_rtx_costs (rtx, int, int, int, int *, bool);
592 static rtx sparc_function_value (const_tree, const_tree, bool);
593 static rtx sparc_libcall_value (enum machine_mode, const_rtx);
594 static bool sparc_function_value_regno_p (const unsigned int);
595 static rtx sparc_struct_value_rtx (tree, int);
596 static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
597 int *, const_tree, int);
598 static bool sparc_return_in_memory (const_tree, const_tree);
599 static bool sparc_strict_argument_naming (cumulative_args_t);
600 static void sparc_va_start (tree, rtx);
601 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
602 static bool sparc_vector_mode_supported_p (enum machine_mode);
603 static bool sparc_tls_referenced_p (rtx);
604 static rtx sparc_legitimize_tls_address (rtx);
605 static rtx sparc_legitimize_pic_address (rtx, rtx);
606 static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
607 static rtx sparc_delegitimize_address (rtx);
608 static bool sparc_mode_dependent_address_p (const_rtx, addr_space_t);
609 static bool sparc_pass_by_reference (cumulative_args_t,
610 enum machine_mode, const_tree, bool);
611 static void sparc_function_arg_advance (cumulative_args_t,
612 enum machine_mode, const_tree, bool);
613 static rtx sparc_function_arg_1 (cumulative_args_t,
614 enum machine_mode, const_tree, bool, bool);
615 static rtx sparc_function_arg (cumulative_args_t,
616 enum machine_mode, const_tree, bool);
617 static rtx sparc_function_incoming_arg (cumulative_args_t,
618 enum machine_mode, const_tree, bool);
619 static unsigned int sparc_function_arg_boundary (enum machine_mode,
621 static int sparc_arg_partial_bytes (cumulative_args_t,
622 enum machine_mode, tree, bool);
623 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
624 static void sparc_file_end (void);
625 static bool sparc_frame_pointer_required (void);
626 static bool sparc_can_eliminate (const int, const int);
627 static rtx sparc_builtin_setjmp_frame_value (void);
628 static void sparc_conditional_register_usage (void);
629 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
630 static const char *sparc_mangle_type (const_tree);
632 static void sparc_trampoline_init (rtx, tree, rtx);
633 static enum machine_mode sparc_preferred_simd_mode (enum machine_mode);
634 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
635 static bool sparc_print_operand_punct_valid_p (unsigned char);
636 static void sparc_print_operand (FILE *, rtx, int);
637 static void sparc_print_operand_address (FILE *, rtx);
638 static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t,
640 secondary_reload_info *);
641 static enum machine_mode sparc_cstore_mode (enum insn_code icode);
642 static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *);
644 #ifdef SUBTARGET_ATTRIBUTE_TABLE
645 /* Table of valid machine attributes. */
646 static const struct attribute_spec sparc_attribute_table[] =
648 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
650 SUBTARGET_ATTRIBUTE_TABLE,
651 { NULL, 0, 0, false, false, false, NULL, false }
655 /* Option handling. */
658 enum cmodel sparc_cmodel;
660 char sparc_hard_reg_printed[8];
662 /* Initialize the GCC target structure. */
664 /* The default is to use .half rather than .short for aligned HI objects. */
665 #undef TARGET_ASM_ALIGNED_HI_OP
666 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
668 #undef TARGET_ASM_UNALIGNED_HI_OP
669 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
670 #undef TARGET_ASM_UNALIGNED_SI_OP
671 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
672 #undef TARGET_ASM_UNALIGNED_DI_OP
673 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
675 /* The target hook has to handle DI-mode values. */
676 #undef TARGET_ASM_INTEGER
677 #define TARGET_ASM_INTEGER sparc_assemble_integer
679 #undef TARGET_ASM_FUNCTION_PROLOGUE
680 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
681 #undef TARGET_ASM_FUNCTION_EPILOGUE
682 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
684 #undef TARGET_SCHED_ADJUST_COST
685 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
686 #undef TARGET_SCHED_ISSUE_RATE
687 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
688 #undef TARGET_SCHED_INIT
689 #define TARGET_SCHED_INIT sparc_sched_init
690 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
691 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
693 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
694 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
696 #undef TARGET_INIT_LIBFUNCS
697 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
699 #undef TARGET_LEGITIMIZE_ADDRESS
700 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
701 #undef TARGET_DELEGITIMIZE_ADDRESS
702 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
703 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
704 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
706 #undef TARGET_INIT_BUILTINS
707 #define TARGET_INIT_BUILTINS sparc_init_builtins
708 #undef TARGET_BUILTIN_DECL
709 #define TARGET_BUILTIN_DECL sparc_builtin_decl
710 #undef TARGET_EXPAND_BUILTIN
711 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
712 #undef TARGET_FOLD_BUILTIN
713 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
716 #undef TARGET_HAVE_TLS
717 #define TARGET_HAVE_TLS true
720 #undef TARGET_CANNOT_FORCE_CONST_MEM
721 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
723 #undef TARGET_ASM_OUTPUT_MI_THUNK
724 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
725 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
726 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
728 #undef TARGET_RTX_COSTS
729 #define TARGET_RTX_COSTS sparc_rtx_costs
730 #undef TARGET_ADDRESS_COST
731 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
732 #undef TARGET_REGISTER_MOVE_COST
733 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
735 #undef TARGET_PROMOTE_FUNCTION_MODE
736 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
738 #undef TARGET_FUNCTION_VALUE
739 #define TARGET_FUNCTION_VALUE sparc_function_value
740 #undef TARGET_LIBCALL_VALUE
741 #define TARGET_LIBCALL_VALUE sparc_libcall_value
742 #undef TARGET_FUNCTION_VALUE_REGNO_P
743 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
745 #undef TARGET_STRUCT_VALUE_RTX
746 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
747 #undef TARGET_RETURN_IN_MEMORY
748 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
749 #undef TARGET_MUST_PASS_IN_STACK
750 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
751 #undef TARGET_PASS_BY_REFERENCE
752 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
753 #undef TARGET_ARG_PARTIAL_BYTES
754 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
755 #undef TARGET_FUNCTION_ARG_ADVANCE
756 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
757 #undef TARGET_FUNCTION_ARG
758 #define TARGET_FUNCTION_ARG sparc_function_arg
759 #undef TARGET_FUNCTION_INCOMING_ARG
760 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
761 #undef TARGET_FUNCTION_ARG_BOUNDARY
762 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
764 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
765 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
766 #undef TARGET_STRICT_ARGUMENT_NAMING
767 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
769 #undef TARGET_EXPAND_BUILTIN_VA_START
770 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
771 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
772 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
774 #undef TARGET_VECTOR_MODE_SUPPORTED_P
775 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
777 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
778 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
780 #ifdef SUBTARGET_INSERT_ATTRIBUTES
781 #undef TARGET_INSERT_ATTRIBUTES
782 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
785 #ifdef SUBTARGET_ATTRIBUTE_TABLE
786 #undef TARGET_ATTRIBUTE_TABLE
787 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
790 #undef TARGET_RELAXED_ORDERING
791 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
793 #undef TARGET_OPTION_OVERRIDE
794 #define TARGET_OPTION_OVERRIDE sparc_option_override
796 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
797 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
798 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
801 #undef TARGET_ASM_FILE_END
802 #define TARGET_ASM_FILE_END sparc_file_end
804 #undef TARGET_FRAME_POINTER_REQUIRED
805 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
807 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
808 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
810 #undef TARGET_CAN_ELIMINATE
811 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
813 #undef TARGET_PREFERRED_RELOAD_CLASS
814 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
816 #undef TARGET_SECONDARY_RELOAD
817 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
819 #undef TARGET_CONDITIONAL_REGISTER_USAGE
820 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
822 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
823 #undef TARGET_MANGLE_TYPE
824 #define TARGET_MANGLE_TYPE sparc_mangle_type
827 #undef TARGET_LEGITIMATE_ADDRESS_P
828 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
830 #undef TARGET_LEGITIMATE_CONSTANT_P
831 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
833 #undef TARGET_TRAMPOLINE_INIT
834 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
836 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
837 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
838 #undef TARGET_PRINT_OPERAND
839 #define TARGET_PRINT_OPERAND sparc_print_operand
840 #undef TARGET_PRINT_OPERAND_ADDRESS
841 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
843 /* The value stored by LDSTUB. */
844 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
845 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
847 #undef TARGET_CSTORE_MODE
848 #define TARGET_CSTORE_MODE sparc_cstore_mode
850 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
851 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
853 struct gcc_target targetm = TARGET_INITIALIZER;
855 /* Return the memory reference contained in X if any, zero otherwise. */
860 if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND)
869 /* We use a machine specific pass to enable workarounds for errata.
870 We need to have the (essentially) final form of the insn stream in order
871 to properly detect the various hazards. Therefore, this machine specific
872 pass runs as late as possible. The pass is inserted in the pass pipeline
873 at the end of sparc_option_override. */
876 sparc_do_work_around_errata (void)
880 /* Force all instructions to be split into their final form. */
881 split_all_insns_noflow ();
883 /* Now look for specific patterns in the insn stream. */
884 for (insn = get_insns (); insn; insn = next)
886 bool insert_nop = false;
889 /* Look into the instruction in a delay slot. */
890 if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
891 insn = XVECEXP (PATTERN (insn), 0, 1);
893 /* Look for a single-word load into an odd-numbered FP register. */
895 && NONJUMP_INSN_P (insn)
896 && (set = single_set (insn)) != NULL_RTX
897 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
898 && MEM_P (SET_SRC (set))
899 && REG_P (SET_DEST (set))
900 && REGNO (SET_DEST (set)) > 31
901 && REGNO (SET_DEST (set)) % 2 != 0)
903 /* The wrong dependency is on the enclosing double register. */
904 const unsigned int x = REGNO (SET_DEST (set)) - 1;
905 unsigned int src1, src2, dest;
908 next = next_active_insn (insn);
911 /* If the insn is a branch, then it cannot be problematic. */
912 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
916 code = INSN_CODE (next);
920 case CODE_FOR_adddf3:
921 case CODE_FOR_subdf3:
922 case CODE_FOR_muldf3:
923 case CODE_FOR_divdf3:
924 dest = REGNO (recog_data.operand[0]);
925 src1 = REGNO (recog_data.operand[1]);
926 src2 = REGNO (recog_data.operand[2]);
931 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
932 if ((src1 == x || src2 == x)
933 && (dest == src1 || dest == src2))
940 FPOPd %fx, %fx, %fx */
943 && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
948 case CODE_FOR_sqrtdf2:
949 dest = REGNO (recog_data.operand[0]);
950 src1 = REGNO (recog_data.operand[1]);
954 if (src1 == x && dest == src1)
963 /* Look for a single-word load into an integer register. */
964 else if (sparc_fix_ut699
965 && NONJUMP_INSN_P (insn)
966 && (set = single_set (insn)) != NULL_RTX
967 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4
968 && mem_ref (SET_SRC (set)) != NULL_RTX
969 && REG_P (SET_DEST (set))
970 && REGNO (SET_DEST (set)) < 32)
972 /* There is no problem if the second memory access has a data
973 dependency on the first single-cycle load. */
974 rtx x = SET_DEST (set);
976 next = next_active_insn (insn);
979 /* If the insn is a branch, then it cannot be problematic. */
980 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
983 /* Look for a second memory access to/from an integer register. */
984 if ((set = single_set (next)) != NULL_RTX)
986 rtx src = SET_SRC (set);
987 rtx dest = SET_DEST (set);
990 /* LDD is affected. */
991 if ((mem = mem_ref (src)) != NULL_RTX
994 && !reg_mentioned_p (x, XEXP (mem, 0)))
997 /* STD is *not* affected. */
998 else if (MEM_P (dest)
999 && GET_MODE_SIZE (GET_MODE (dest)) <= 4
1000 && (src == CONST0_RTX (GET_MODE (dest))
1003 && REGNO (src) != REGNO (x)))
1004 && !reg_mentioned_p (x, XEXP (dest, 0)))
1009 /* Look for a single-word load/operation into an FP register. */
1010 else if (sparc_fix_ut699
1011 && NONJUMP_INSN_P (insn)
1012 && (set = single_set (insn)) != NULL_RTX
1013 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
1014 && REG_P (SET_DEST (set))
1015 && REGNO (SET_DEST (set)) > 31)
1017 /* Number of instructions in the problematic window. */
1018 const int n_insns = 4;
1019 /* The problematic combination is with the sibling FP register. */
1020 const unsigned int x = REGNO (SET_DEST (set));
1021 const unsigned int y = x ^ 1;
1025 next = next_active_insn (insn);
1028 /* If the insn is a branch, then it cannot be problematic. */
1029 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
1032 /* Look for a second load/operation into the sibling FP register. */
1033 if (!((set = single_set (next)) != NULL_RTX
1034 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
1035 && REG_P (SET_DEST (set))
1036 && REGNO (SET_DEST (set)) == y))
1039 /* Look for a (possible) store from the FP register in the next N
1040 instructions, but bail out if it is again modified or if there
1041 is a store from the sibling FP register before this store. */
1042 for (after = next, i = 0; i < n_insns; i++)
1046 after = next_active_insn (after);
1050 /* This is a branch with an empty delay slot. */
1051 if (!NONJUMP_INSN_P (after))
1058 /* This is a branch with a filled delay slot. */
1059 else if (GET_CODE (PATTERN (after)) == SEQUENCE)
1064 after = XVECEXP (PATTERN (after), 0, 1);
1066 /* This is a regular instruction. */
1070 if (after && (set = single_set (after)) != NULL_RTX)
1072 const rtx src = SET_SRC (set);
1073 const rtx dest = SET_DEST (set);
1074 const unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
1076 /* If the FP register is again modified before the store,
1077 then the store isn't affected. */
1079 && (REGNO (dest) == x
1080 || (REGNO (dest) == y && size == 8)))
1083 if (MEM_P (dest) && REG_P (src))
1085 /* If there is a store from the sibling FP register
1086 before the store, then the store is not affected. */
1087 if (REGNO (src) == y || (REGNO (src) == x && size == 8))
1090 /* Otherwise, the store is affected. */
1091 if (REGNO (src) == x && size == 4)
1099 /* If we have a branch in the first M instructions, then we
1100 cannot see the (M+2)th instruction so we play safe. */
1101 if (branch_p && i <= (n_insns - 2))
1110 next = NEXT_INSN (insn);
1113 emit_insn_before (gen_nop (), next);
1121 const pass_data pass_data_work_around_errata =
1123 RTL_PASS, /* type */
1124 "errata", /* name */
1125 OPTGROUP_NONE, /* optinfo_flags */
1126 true, /* has_execute */
1127 TV_MACH_DEP, /* tv_id */
1128 0, /* properties_required */
1129 0, /* properties_provided */
1130 0, /* properties_destroyed */
1131 0, /* todo_flags_start */
1132 0, /* todo_flags_finish */
1135 class pass_work_around_errata : public rtl_opt_pass
1138 pass_work_around_errata(gcc::context *ctxt)
1139 : rtl_opt_pass(pass_data_work_around_errata, ctxt)
1142 /* opt_pass methods: */
1143 virtual bool gate (function *)
1145 /* The only errata we handle are those of the AT697F and UT699. */
1146 return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
1149 virtual unsigned int execute (function *)
1151 return sparc_do_work_around_errata ();
1154 }; // class pass_work_around_errata
1159 make_pass_work_around_errata (gcc::context *ctxt)
1161 return new pass_work_around_errata (ctxt);
1164 /* Helpers for TARGET_DEBUG_OPTIONS. */
1166 dump_target_flag_bits (const int flags)
1168 if (flags & MASK_64BIT)
1169 fprintf (stderr, "64BIT ");
1170 if (flags & MASK_APP_REGS)
1171 fprintf (stderr, "APP_REGS ");
1172 if (flags & MASK_FASTER_STRUCTS)
1173 fprintf (stderr, "FASTER_STRUCTS ");
1174 if (flags & MASK_FLAT)
1175 fprintf (stderr, "FLAT ");
1176 if (flags & MASK_FMAF)
1177 fprintf (stderr, "FMAF ");
1178 if (flags & MASK_FPU)
1179 fprintf (stderr, "FPU ");
1180 if (flags & MASK_HARD_QUAD)
1181 fprintf (stderr, "HARD_QUAD ");
1182 if (flags & MASK_POPC)
1183 fprintf (stderr, "POPC ");
1184 if (flags & MASK_PTR64)
1185 fprintf (stderr, "PTR64 ");
1186 if (flags & MASK_STACK_BIAS)
1187 fprintf (stderr, "STACK_BIAS ");
1188 if (flags & MASK_UNALIGNED_DOUBLES)
1189 fprintf (stderr, "UNALIGNED_DOUBLES ");
1190 if (flags & MASK_V8PLUS)
1191 fprintf (stderr, "V8PLUS ");
1192 if (flags & MASK_VIS)
1193 fprintf (stderr, "VIS ");
1194 if (flags & MASK_VIS2)
1195 fprintf (stderr, "VIS2 ");
1196 if (flags & MASK_VIS3)
1197 fprintf (stderr, "VIS3 ");
1198 if (flags & MASK_CBCOND)
1199 fprintf (stderr, "CBCOND ");
1200 if (flags & MASK_DEPRECATED_V8_INSNS)
1201 fprintf (stderr, "DEPRECATED_V8_INSNS ");
1202 if (flags & MASK_SPARCLET)
1203 fprintf (stderr, "SPARCLET ");
1204 if (flags & MASK_SPARCLITE)
1205 fprintf (stderr, "SPARCLITE ");
1206 if (flags & MASK_V8)
1207 fprintf (stderr, "V8 ");
1208 if (flags & MASK_V9)
1209 fprintf (stderr, "V9 ");
1213 dump_target_flags (const char *prefix, const int flags)
1215 fprintf (stderr, "%s: (%08x) [ ", prefix, flags);
1216 dump_target_flag_bits (flags);
1217 fprintf(stderr, "]\n");
1220 /* Validate and override various options, and do some machine dependent
1224 sparc_option_override (void)
1226 static struct code_model {
1227 const char *const name;
1228 const enum cmodel value;
1229 } const cmodels[] = {
1231 { "medlow", CM_MEDLOW },
1232 { "medmid", CM_MEDMID },
1233 { "medany", CM_MEDANY },
1234 { "embmedany", CM_EMBMEDANY },
1235 { NULL, (enum cmodel) 0 }
1237 const struct code_model *cmodel;
1238 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1239 static struct cpu_default {
1241 const enum processor_type processor;
1242 } const cpu_default[] = {
1243 /* There must be one entry here for each TARGET_CPU value. */
1244 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
1245 { TARGET_CPU_v8, PROCESSOR_V8 },
1246 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
1247 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
1248 { TARGET_CPU_leon, PROCESSOR_LEON },
1249 { TARGET_CPU_leon3, PROCESSOR_LEON3 },
1250 { TARGET_CPU_sparclite, PROCESSOR_F930 },
1251 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
1252 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
1253 { TARGET_CPU_v9, PROCESSOR_V9 },
1254 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
1255 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
1256 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
1257 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
1258 { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 },
1259 { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 },
1260 { -1, PROCESSOR_V7 }
1262 const struct cpu_default *def;
1263 /* Table of values for -m{cpu,tune}=. This must match the order of
1264 the enum processor_type in sparc-opts.h. */
1265 static struct cpu_table {
1266 const char *const name;
1269 } const cpu_table[] = {
1270 { "v7", MASK_ISA, 0 },
1271 { "cypress", MASK_ISA, 0 },
1272 { "v8", MASK_ISA, MASK_V8 },
1273 /* TI TMS390Z55 supersparc */
1274 { "supersparc", MASK_ISA, MASK_V8 },
1275 { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
1276 { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
1277 { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
1278 { "sparclite", MASK_ISA, MASK_SPARCLITE },
1279 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1280 { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
1281 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1282 { "f934", MASK_ISA, MASK_SPARCLITE|MASK_FPU },
1283 { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
1284 { "sparclet", MASK_ISA, MASK_SPARCLET },
1285 /* TEMIC sparclet */
1286 { "tsc701", MASK_ISA, MASK_SPARCLET },
1287 { "v9", MASK_ISA, MASK_V9 },
1288 /* UltraSPARC I, II, IIi */
1289 { "ultrasparc", MASK_ISA,
1290 /* Although insns using %y are deprecated, it is a clear win. */
1291 MASK_V9|MASK_DEPRECATED_V8_INSNS },
1292 /* UltraSPARC III */
1293 /* ??? Check if %y issue still holds true. */
1294 { "ultrasparc3", MASK_ISA,
1295 MASK_V9|MASK_DEPRECATED_V8_INSNS|MASK_VIS2 },
1297 { "niagara", MASK_ISA,
1298 MASK_V9|MASK_DEPRECATED_V8_INSNS },
1300 { "niagara2", MASK_ISA,
1301 MASK_V9|MASK_POPC|MASK_VIS2 },
1303 { "niagara3", MASK_ISA,
1304 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
1306 { "niagara4", MASK_ISA,
1307 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF|MASK_CBCOND },
1309 const struct cpu_table *cpu;
1313 if (sparc_debug_string != NULL)
1318 p = ASTRDUP (sparc_debug_string);
1319 while ((q = strtok (p, ",")) != NULL)
1333 if (! strcmp (q, "all"))
1334 mask = MASK_DEBUG_ALL;
1335 else if (! strcmp (q, "options"))
1336 mask = MASK_DEBUG_OPTIONS;
1338 error ("unknown -mdebug-%s switch", q);
1341 sparc_debug &= ~mask;
1343 sparc_debug |= mask;
1347 if (TARGET_DEBUG_OPTIONS)
1349 dump_target_flags("Initial target_flags", target_flags);
1350 dump_target_flags("target_flags_explicit", target_flags_explicit);
1353 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1354 SUBTARGET_OVERRIDE_OPTIONS;
1357 #ifndef SPARC_BI_ARCH
1358 /* Check for unsupported architecture size. */
1359 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
1360 error ("%s is not supported by this configuration",
1361 DEFAULT_ARCH32_P ? "-m64" : "-m32");
1364 /* We force all 64bit archs to use 128 bit long double */
1365 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
1367 error ("-mlong-double-64 not allowed with -m64");
1368 target_flags |= MASK_LONG_DOUBLE_128;
1371 /* Code model selection. */
1372 sparc_cmodel = SPARC_DEFAULT_CMODEL;
1374 #ifdef SPARC_BI_ARCH
1376 sparc_cmodel = CM_32;
1379 if (sparc_cmodel_string != NULL)
1383 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
1384 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
1386 if (cmodel->name == NULL)
1387 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
1389 sparc_cmodel = cmodel->value;
1392 error ("-mcmodel= is not supported on 32 bit systems");
1395 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1396 for (i = 8; i < 16; i++)
1397 if (!call_used_regs [i])
1399 error ("-fcall-saved-REG is not supported for out registers");
1400 call_used_regs [i] = 1;
1403 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
1405 /* Set the default CPU. */
1406 if (!global_options_set.x_sparc_cpu_and_features)
1408 for (def = &cpu_default[0]; def->cpu != -1; ++def)
1409 if (def->cpu == TARGET_CPU_DEFAULT)
1411 gcc_assert (def->cpu != -1);
1412 sparc_cpu_and_features = def->processor;
1415 if (!global_options_set.x_sparc_cpu)
1416 sparc_cpu = sparc_cpu_and_features;
1418 cpu = &cpu_table[(int) sparc_cpu_and_features];
1420 if (TARGET_DEBUG_OPTIONS)
1422 fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name);
1423 fprintf (stderr, "sparc_cpu: %s\n",
1424 cpu_table[(int) sparc_cpu].name);
1425 dump_target_flags ("cpu->disable", cpu->disable);
1426 dump_target_flags ("cpu->enable", cpu->enable);
1429 target_flags &= ~cpu->disable;
1430 target_flags |= (cpu->enable
1431 #ifndef HAVE_AS_FMAF_HPC_VIS3
1432 & ~(MASK_FMAF | MASK_VIS3)
1434 #ifndef HAVE_AS_SPARC4
1437 #ifndef HAVE_AS_LEON
1438 & ~(MASK_LEON | MASK_LEON3)
1442 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1443 the processor default. */
1444 if (target_flags_explicit & MASK_FPU)
1445 target_flags = (target_flags & ~MASK_FPU) | fpu;
1447 /* -mvis2 implies -mvis */
1449 target_flags |= MASK_VIS;
1451 /* -mvis3 implies -mvis2 and -mvis */
1453 target_flags |= MASK_VIS2 | MASK_VIS;
1455 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is
1458 target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_FMAF);
1460 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1462 -m64 also implies v9. */
1463 if (TARGET_VIS || TARGET_ARCH64)
1465 target_flags |= MASK_V9;
1466 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
1469 /* -mvis also implies -mv8plus on 32-bit */
1470 if (TARGET_VIS && ! TARGET_ARCH64)
1471 target_flags |= MASK_V8PLUS;
1473 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1474 if (TARGET_V9 && TARGET_ARCH32)
1475 target_flags |= MASK_DEPRECATED_V8_INSNS;
1477 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1478 if (! TARGET_V9 || TARGET_ARCH64)
1479 target_flags &= ~MASK_V8PLUS;
1481 /* Don't use stack biasing in 32 bit mode. */
1483 target_flags &= ~MASK_STACK_BIAS;
1485 /* Supply a default value for align_functions. */
1486 if (align_functions == 0
1487 && (sparc_cpu == PROCESSOR_ULTRASPARC
1488 || sparc_cpu == PROCESSOR_ULTRASPARC3
1489 || sparc_cpu == PROCESSOR_NIAGARA
1490 || sparc_cpu == PROCESSOR_NIAGARA2
1491 || sparc_cpu == PROCESSOR_NIAGARA3
1492 || sparc_cpu == PROCESSOR_NIAGARA4))
1493 align_functions = 32;
1495 /* Validate PCC_STRUCT_RETURN. */
1496 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
1497 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
1499 /* Only use .uaxword when compiling for a 64-bit target. */
1501 targetm.asm_out.unaligned_op.di = NULL;
1503 /* Do various machine dependent initializations. */
1504 sparc_init_modes ();
1506 /* Set up function hooks. */
1507 init_machine_status = sparc_init_machine_status;
1512 case PROCESSOR_CYPRESS:
1513 sparc_costs = &cypress_costs;
1516 case PROCESSOR_SPARCLITE:
1517 case PROCESSOR_SUPERSPARC:
1518 sparc_costs = &supersparc_costs;
1520 case PROCESSOR_F930:
1521 case PROCESSOR_F934:
1522 case PROCESSOR_HYPERSPARC:
1523 case PROCESSOR_SPARCLITE86X:
1524 sparc_costs = &hypersparc_costs;
1526 case PROCESSOR_LEON:
1527 sparc_costs = &leon_costs;
1529 case PROCESSOR_LEON3:
1530 sparc_costs = &leon3_costs;
1532 case PROCESSOR_SPARCLET:
1533 case PROCESSOR_TSC701:
1534 sparc_costs = &sparclet_costs;
1537 case PROCESSOR_ULTRASPARC:
1538 sparc_costs = &ultrasparc_costs;
1540 case PROCESSOR_ULTRASPARC3:
1541 sparc_costs = &ultrasparc3_costs;
1543 case PROCESSOR_NIAGARA:
1544 sparc_costs = &niagara_costs;
1546 case PROCESSOR_NIAGARA2:
1547 sparc_costs = &niagara2_costs;
1549 case PROCESSOR_NIAGARA3:
1550 sparc_costs = &niagara3_costs;
1552 case PROCESSOR_NIAGARA4:
1553 sparc_costs = &niagara4_costs;
1555 case PROCESSOR_NATIVE:
1559 if (sparc_memory_model == SMM_DEFAULT)
1561 /* Choose the memory model for the operating system. */
1562 enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL;
1563 if (os_default != SMM_DEFAULT)
1564 sparc_memory_model = os_default;
1565 /* Choose the most relaxed model for the processor. */
1567 sparc_memory_model = SMM_RMO;
1568 else if (TARGET_LEON3)
1569 sparc_memory_model = SMM_TSO;
1570 else if (TARGET_LEON)
1571 sparc_memory_model = SMM_SC;
1573 sparc_memory_model = SMM_PSO;
1575 sparc_memory_model = SMM_SC;
1578 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1579 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1580 target_flags |= MASK_LONG_DOUBLE_128;
1583 if (TARGET_DEBUG_OPTIONS)
1584 dump_target_flags ("Final target_flags", target_flags);
1586 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
1587 ((sparc_cpu == PROCESSOR_ULTRASPARC
1588 || sparc_cpu == PROCESSOR_NIAGARA
1589 || sparc_cpu == PROCESSOR_NIAGARA2
1590 || sparc_cpu == PROCESSOR_NIAGARA3
1591 || sparc_cpu == PROCESSOR_NIAGARA4)
1593 : (sparc_cpu == PROCESSOR_ULTRASPARC3
1595 global_options.x_param_values,
1596 global_options_set.x_param_values);
1597 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
1598 ((sparc_cpu == PROCESSOR_ULTRASPARC
1599 || sparc_cpu == PROCESSOR_ULTRASPARC3
1600 || sparc_cpu == PROCESSOR_NIAGARA
1601 || sparc_cpu == PROCESSOR_NIAGARA2
1602 || sparc_cpu == PROCESSOR_NIAGARA3
1603 || sparc_cpu == PROCESSOR_NIAGARA4)
1605 global_options.x_param_values,
1606 global_options_set.x_param_values);
1608 /* Disable save slot sharing for call-clobbered registers by default.
1609 The IRA sharing algorithm works on single registers only and this
1610 pessimizes for double floating-point registers. */
1611 if (!global_options_set.x_flag_ira_share_save_slots)
1612 flag_ira_share_save_slots = 0;
1614 /* We register a machine specific pass to work around errata, if any.
1615 The pass mut be scheduled as late as possible so that we have the
1616 (essentially) final form of the insn stream to work on.
1617 Registering the pass must be done at start up. It's convenient to
1619 opt_pass *errata_pass = make_pass_work_around_errata (g);
1620 struct register_pass_info insert_pass_work_around_errata =
1622 errata_pass, /* pass */
1623 "dbr", /* reference_pass_name */
1624 1, /* ref_pass_instance_number */
1625 PASS_POS_INSERT_AFTER /* po_op */
1627 register_pass (&insert_pass_work_around_errata);
1630 /* Miscellaneous utilities. */
1632 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1633 or branch on register contents instructions. */
1636 v9_regcmp_p (enum rtx_code code)
1638 return (code == EQ || code == NE || code == GE || code == LT
1639 || code == LE || code == GT);
1642 /* Nonzero if OP is a floating point constant which can
1643 be loaded into an integer register using a single
1644 sethi instruction. */
1649 if (GET_CODE (op) == CONST_DOUBLE)
1654 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1655 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1656 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
1662 /* Nonzero if OP is a floating point constant which can
1663 be loaded into an integer register using a single
1669 if (GET_CODE (op) == CONST_DOUBLE)
1674 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1675 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1676 return SPARC_SIMM13_P (i);
1682 /* Nonzero if OP is a floating point constant which can
1683 be loaded into an integer register using a high/losum
1684 instruction sequence. */
1687 fp_high_losum_p (rtx op)
1689 /* The constraints calling this should only be in
1690 SFmode move insns, so any constant which cannot
1691 be moved using a single insn will do. */
1692 if (GET_CODE (op) == CONST_DOUBLE)
1697 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1698 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1699 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
1705 /* Return true if the address of LABEL can be loaded by means of the
1706 mov{si,di}_pic_label_ref patterns in PIC mode. */
1709 can_use_mov_pic_label_ref (rtx label)
1711 /* VxWorks does not impose a fixed gap between segments; the run-time
1712 gap can be different from the object-file gap. We therefore can't
1713 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1714 are absolutely sure that X is in the same segment as the GOT.
1715 Unfortunately, the flexibility of linker scripts means that we
1716 can't be sure of that in general, so assume that GOT-relative
1717 accesses are never valid on VxWorks. */
1718 if (TARGET_VXWORKS_RTP)
1721 /* Similarly, if the label is non-local, it might end up being placed
1722 in a different section than the current one; now mov_pic_label_ref
1723 requires the label and the code to be in the same section. */
1724 if (LABEL_REF_NONLOCAL_P (label))
1727 /* Finally, if we are reordering basic blocks and partition into hot
1728 and cold sections, this might happen for any label. */
1729 if (flag_reorder_blocks_and_partition)
1735 /* Expand a move instruction. Return true if all work is done. */
1738 sparc_expand_move (enum machine_mode mode, rtx *operands)
1740 /* Handle sets of MEM first. */
1741 if (GET_CODE (operands[0]) == MEM)
1743 /* 0 is a register (or a pair of registers) on SPARC. */
1744 if (register_or_zero_operand (operands[1], mode))
1747 if (!reload_in_progress)
1749 operands[0] = validize_mem (operands[0]);
1750 operands[1] = force_reg (mode, operands[1]);
1754 /* Fixup TLS cases. */
1756 && CONSTANT_P (operands[1])
1757 && sparc_tls_referenced_p (operands [1]))
1759 operands[1] = sparc_legitimize_tls_address (operands[1]);
1763 /* Fixup PIC cases. */
1764 if (flag_pic && CONSTANT_P (operands[1]))
1766 if (pic_address_needs_scratch (operands[1]))
1767 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
1769 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1770 if (GET_CODE (operands[1]) == LABEL_REF
1771 && can_use_mov_pic_label_ref (operands[1]))
1775 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1781 gcc_assert (TARGET_ARCH64);
1782 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1787 if (symbolic_operand (operands[1], mode))
1790 = sparc_legitimize_pic_address (operands[1],
1792 ? operands[0] : NULL_RTX);
1797 /* If we are trying to toss an integer constant into FP registers,
1798 or loading a FP or vector constant, force it into memory. */
1799 if (CONSTANT_P (operands[1])
1800 && REG_P (operands[0])
1801 && (SPARC_FP_REG_P (REGNO (operands[0]))
1802 || SCALAR_FLOAT_MODE_P (mode)
1803 || VECTOR_MODE_P (mode)))
1805 /* emit_group_store will send such bogosity to us when it is
1806 not storing directly into memory. So fix this up to avoid
1807 crashes in output_constant_pool. */
1808 if (operands [1] == const0_rtx)
1809 operands[1] = CONST0_RTX (mode);
1811 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1812 always other regs. */
1813 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1814 && (const_zero_operand (operands[1], mode)
1815 || const_all_ones_operand (operands[1], mode)))
1818 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1819 /* We are able to build any SF constant in integer registers
1820 with at most 2 instructions. */
1822 /* And any DF constant in integer registers. */
1824 && ! can_create_pseudo_p ())))
1827 operands[1] = force_const_mem (mode, operands[1]);
1828 if (!reload_in_progress)
1829 operands[1] = validize_mem (operands[1]);
1833 /* Accept non-constants and valid constants unmodified. */
1834 if (!CONSTANT_P (operands[1])
1835 || GET_CODE (operands[1]) == HIGH
1836 || input_operand (operands[1], mode))
1842 /* All QImode constants require only one insn, so proceed. */
1847 sparc_emit_set_const32 (operands[0], operands[1]);
1851 /* input_operand should have filtered out 32-bit mode. */
1852 sparc_emit_set_const64 (operands[0], operands[1]);
1858 /* TImode isn't available in 32-bit mode. */
1859 split_double (operands[1], &high, &low);
1860 emit_insn (gen_movdi (operand_subword (operands[0], 0, 0, TImode),
1862 emit_insn (gen_movdi (operand_subword (operands[0], 1, 0, TImode),
1874 /* Load OP1, a 32-bit constant, into OP0, a register.
1875 We know it can't be done in one insn when we get
1876 here, the move expander guarantees this. */
1879 sparc_emit_set_const32 (rtx op0, rtx op1)
1881 enum machine_mode mode = GET_MODE (op0);
1884 if (can_create_pseudo_p ())
1885 temp = gen_reg_rtx (mode);
1887 if (GET_CODE (op1) == CONST_INT)
1889 gcc_assert (!small_int_operand (op1, mode)
1890 && !const_high_operand (op1, mode));
1892 /* Emit them as real moves instead of a HIGH/LO_SUM,
1893 this way CSE can see everything and reuse intermediate
1894 values if it wants. */
1895 emit_insn (gen_rtx_SET (VOIDmode, temp,
1896 GEN_INT (INTVAL (op1)
1897 & ~(HOST_WIDE_INT)0x3ff)));
1899 emit_insn (gen_rtx_SET (VOIDmode,
1901 gen_rtx_IOR (mode, temp,
1902 GEN_INT (INTVAL (op1) & 0x3ff))));
1906 /* A symbol, emit in the traditional way. */
1907 emit_insn (gen_rtx_SET (VOIDmode, temp,
1908 gen_rtx_HIGH (mode, op1)));
1909 emit_insn (gen_rtx_SET (VOIDmode,
1910 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1914 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1915 If TEMP is nonzero, we are forbidden to use any other scratch
1916 registers. Otherwise, we are allowed to generate them as needed.
1918 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1919 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1922 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1924 rtx temp1, temp2, temp3, temp4, temp5;
1927 if (temp && GET_MODE (temp) == TImode)
1930 temp = gen_rtx_REG (DImode, REGNO (temp));
1933 /* SPARC-V9 code-model support. */
1934 switch (sparc_cmodel)
1937 /* The range spanned by all instructions in the object is less
1938 than 2^31 bytes (2GB) and the distance from any instruction
1939 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1940 than 2^31 bytes (2GB).
1942 The executable must be in the low 4TB of the virtual address
1945 sethi %hi(symbol), %temp1
1946 or %temp1, %lo(symbol), %reg */
1948 temp1 = temp; /* op0 is allowed. */
1950 temp1 = gen_reg_rtx (DImode);
1952 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1953 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1957 /* The range spanned by all instructions in the object is less
1958 than 2^31 bytes (2GB) and the distance from any instruction
1959 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1960 than 2^31 bytes (2GB).
1962 The executable must be in the low 16TB of the virtual address
1965 sethi %h44(symbol), %temp1
1966 or %temp1, %m44(symbol), %temp2
1967 sllx %temp2, 12, %temp3
1968 or %temp3, %l44(symbol), %reg */
1973 temp3 = temp; /* op0 is allowed. */
1977 temp1 = gen_reg_rtx (DImode);
1978 temp2 = gen_reg_rtx (DImode);
1979 temp3 = gen_reg_rtx (DImode);
1982 emit_insn (gen_seth44 (temp1, op1));
1983 emit_insn (gen_setm44 (temp2, temp1, op1));
1984 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1985 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1986 emit_insn (gen_setl44 (op0, temp3, op1));
1990 /* The range spanned by all instructions in the object is less
1991 than 2^31 bytes (2GB) and the distance from any instruction
1992 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1993 than 2^31 bytes (2GB).
1995 The executable can be placed anywhere in the virtual address
1998 sethi %hh(symbol), %temp1
1999 sethi %lm(symbol), %temp2
2000 or %temp1, %hm(symbol), %temp3
2001 sllx %temp3, 32, %temp4
2002 or %temp4, %temp2, %temp5
2003 or %temp5, %lo(symbol), %reg */
2006 /* It is possible that one of the registers we got for operands[2]
2007 might coincide with that of operands[0] (which is why we made
2008 it TImode). Pick the other one to use as our scratch. */
2009 if (rtx_equal_p (temp, op0))
2011 gcc_assert (ti_temp);
2012 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
2015 temp2 = temp; /* op0 is _not_ allowed, see above. */
2022 temp1 = gen_reg_rtx (DImode);
2023 temp2 = gen_reg_rtx (DImode);
2024 temp3 = gen_reg_rtx (DImode);
2025 temp4 = gen_reg_rtx (DImode);
2026 temp5 = gen_reg_rtx (DImode);
2029 emit_insn (gen_sethh (temp1, op1));
2030 emit_insn (gen_setlm (temp2, op1));
2031 emit_insn (gen_sethm (temp3, temp1, op1));
2032 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2033 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
2034 emit_insn (gen_rtx_SET (VOIDmode, temp5,
2035 gen_rtx_PLUS (DImode, temp4, temp2)));
2036 emit_insn (gen_setlo (op0, temp5, op1));
2040 /* Old old old backwards compatibility kruft here.
2041 Essentially it is MEDLOW with a fixed 64-bit
2042 virtual base added to all data segment addresses.
2043 Text-segment stuff is computed like MEDANY, we can't
2044 reuse the code above because the relocation knobs
2047 Data segment: sethi %hi(symbol), %temp1
2048 add %temp1, EMBMEDANY_BASE_REG, %temp2
2049 or %temp2, %lo(symbol), %reg */
2050 if (data_segment_operand (op1, GET_MODE (op1)))
2054 temp1 = temp; /* op0 is allowed. */
2059 temp1 = gen_reg_rtx (DImode);
2060 temp2 = gen_reg_rtx (DImode);
2063 emit_insn (gen_embmedany_sethi (temp1, op1));
2064 emit_insn (gen_embmedany_brsum (temp2, temp1));
2065 emit_insn (gen_embmedany_losum (op0, temp2, op1));
2068 /* Text segment: sethi %uhi(symbol), %temp1
2069 sethi %hi(symbol), %temp2
2070 or %temp1, %ulo(symbol), %temp3
2071 sllx %temp3, 32, %temp4
2072 or %temp4, %temp2, %temp5
2073 or %temp5, %lo(symbol), %reg */
2078 /* It is possible that one of the registers we got for operands[2]
2079 might coincide with that of operands[0] (which is why we made
2080 it TImode). Pick the other one to use as our scratch. */
2081 if (rtx_equal_p (temp, op0))
2083 gcc_assert (ti_temp);
2084 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
2087 temp2 = temp; /* op0 is _not_ allowed, see above. */
2094 temp1 = gen_reg_rtx (DImode);
2095 temp2 = gen_reg_rtx (DImode);
2096 temp3 = gen_reg_rtx (DImode);
2097 temp4 = gen_reg_rtx (DImode);
2098 temp5 = gen_reg_rtx (DImode);
2101 emit_insn (gen_embmedany_textuhi (temp1, op1));
2102 emit_insn (gen_embmedany_texthi (temp2, op1));
2103 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
2104 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2105 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
2106 emit_insn (gen_rtx_SET (VOIDmode, temp5,
2107 gen_rtx_PLUS (DImode, temp4, temp2)));
2108 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
2117 #if HOST_BITS_PER_WIDE_INT == 32
2119 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
2124 /* These avoid problems when cross compiling. If we do not
2125 go through all this hair then the optimizer will see
2126 invalid REG_EQUAL notes or in some cases none at all. */
2127 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
2128 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
2129 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
2130 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
2132 /* The optimizer is not to assume anything about exactly
2133 which bits are set for a HIGH, they are unspecified.
2134 Unfortunately this leads to many missed optimizations
2135 during CSE. We mask out the non-HIGH bits, and matches
2136 a plain movdi, to alleviate this problem. */
2138 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
2140 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
2144 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
2146 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
2150 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
2152 return gen_rtx_IOR (DImode, src, GEN_INT (val));
2156 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
2158 return gen_rtx_XOR (DImode, src, GEN_INT (val));
2161 /* Worker routines for 64-bit constant formation on arch64.
2162 One of the key things to be doing in these emissions is
2163 to create as many temp REGs as possible. This makes it
2164 possible for half-built constants to be used later when
2165 such values are similar to something required later on.
2166 Without doing this, the optimizer cannot see such
2169 static void sparc_emit_set_const64_quick1 (rtx, rtx,
2170 unsigned HOST_WIDE_INT, int);
2173 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
2174 unsigned HOST_WIDE_INT low_bits, int is_neg)
2176 unsigned HOST_WIDE_INT high_bits;
2179 high_bits = (~low_bits) & 0xffffffff;
2181 high_bits = low_bits;
2183 emit_insn (gen_safe_HIGH64 (temp, high_bits));
2186 emit_insn (gen_rtx_SET (VOIDmode, op0,
2187 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2191 /* If we are XOR'ing with -1, then we should emit a one's complement
2192 instead. This way the combiner will notice logical operations
2193 such as ANDN later on and substitute. */
2194 if ((low_bits & 0x3ff) == 0x3ff)
2196 emit_insn (gen_rtx_SET (VOIDmode, op0,
2197 gen_rtx_NOT (DImode, temp)));
2201 emit_insn (gen_rtx_SET (VOIDmode, op0,
2202 gen_safe_XOR64 (temp,
2203 (-(HOST_WIDE_INT)0x400
2204 | (low_bits & 0x3ff)))));
2209 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
2210 unsigned HOST_WIDE_INT, int);
2213 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
2214 unsigned HOST_WIDE_INT high_bits,
2215 unsigned HOST_WIDE_INT low_immediate,
2220 if ((high_bits & 0xfffffc00) != 0)
2222 emit_insn (gen_safe_HIGH64 (temp, high_bits));
2223 if ((high_bits & ~0xfffffc00) != 0)
2224 emit_insn (gen_rtx_SET (VOIDmode, op0,
2225 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2231 emit_insn (gen_safe_SET64 (temp, high_bits));
2235 /* Now shift it up into place. */
2236 emit_insn (gen_rtx_SET (VOIDmode, op0,
2237 gen_rtx_ASHIFT (DImode, temp2,
2238 GEN_INT (shift_count))));
2240 /* If there is a low immediate part piece, finish up by
2241 putting that in as well. */
2242 if (low_immediate != 0)
2243 emit_insn (gen_rtx_SET (VOIDmode, op0,
2244 gen_safe_OR64 (op0, low_immediate)));
2247 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
2248 unsigned HOST_WIDE_INT);
2250 /* Full 64-bit constant decomposition. Even though this is the
2251 'worst' case, we still optimize a few things away. */
2253 sparc_emit_set_const64_longway (rtx op0, rtx temp,
2254 unsigned HOST_WIDE_INT high_bits,
2255 unsigned HOST_WIDE_INT low_bits)
2259 if (can_create_pseudo_p ())
2260 sub_temp = gen_reg_rtx (DImode);
2262 if ((high_bits & 0xfffffc00) != 0)
2264 emit_insn (gen_safe_HIGH64 (temp, high_bits));
2265 if ((high_bits & ~0xfffffc00) != 0)
2266 emit_insn (gen_rtx_SET (VOIDmode,
2268 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2274 emit_insn (gen_safe_SET64 (temp, high_bits));
2278 if (can_create_pseudo_p ())
2280 rtx temp2 = gen_reg_rtx (DImode);
2281 rtx temp3 = gen_reg_rtx (DImode);
2282 rtx temp4 = gen_reg_rtx (DImode);
2284 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2285 gen_rtx_ASHIFT (DImode, sub_temp,
2288 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
2289 if ((low_bits & ~0xfffffc00) != 0)
2291 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2292 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2293 emit_insn (gen_rtx_SET (VOIDmode, op0,
2294 gen_rtx_PLUS (DImode, temp4, temp3)));
2298 emit_insn (gen_rtx_SET (VOIDmode, op0,
2299 gen_rtx_PLUS (DImode, temp4, temp2)));
2304 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2305 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2306 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2309 /* We are in the middle of reload, so this is really
2310 painful. However we do still make an attempt to
2311 avoid emitting truly stupid code. */
2312 if (low1 != const0_rtx)
2314 emit_insn (gen_rtx_SET (VOIDmode, op0,
2315 gen_rtx_ASHIFT (DImode, sub_temp,
2316 GEN_INT (to_shift))));
2317 emit_insn (gen_rtx_SET (VOIDmode, op0,
2318 gen_rtx_IOR (DImode, op0, low1)));
2326 if (low2 != const0_rtx)
2328 emit_insn (gen_rtx_SET (VOIDmode, op0,
2329 gen_rtx_ASHIFT (DImode, sub_temp,
2330 GEN_INT (to_shift))));
2331 emit_insn (gen_rtx_SET (VOIDmode, op0,
2332 gen_rtx_IOR (DImode, op0, low2)));
2340 emit_insn (gen_rtx_SET (VOIDmode, op0,
2341 gen_rtx_ASHIFT (DImode, sub_temp,
2342 GEN_INT (to_shift))));
2343 if (low3 != const0_rtx)
2344 emit_insn (gen_rtx_SET (VOIDmode, op0,
2345 gen_rtx_IOR (DImode, op0, low3)));
2350 /* Analyze a 64-bit constant for certain properties. */
2351 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2352 unsigned HOST_WIDE_INT,
2353 int *, int *, int *);
2356 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2357 unsigned HOST_WIDE_INT low_bits,
2358 int *hbsp, int *lbsp, int *abbasp)
2360 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2363 lowest_bit_set = highest_bit_set = -1;
2367 if ((lowest_bit_set == -1)
2368 && ((low_bits >> i) & 1))
2370 if ((highest_bit_set == -1)
2371 && ((high_bits >> (32 - i - 1)) & 1))
2372 highest_bit_set = (64 - i - 1);
2375 && ((highest_bit_set == -1)
2376 || (lowest_bit_set == -1)));
2382 if ((lowest_bit_set == -1)
2383 && ((high_bits >> i) & 1))
2384 lowest_bit_set = i + 32;
2385 if ((highest_bit_set == -1)
2386 && ((low_bits >> (32 - i - 1)) & 1))
2387 highest_bit_set = 32 - i - 1;
2390 && ((highest_bit_set == -1)
2391 || (lowest_bit_set == -1)));
2393 /* If there are no bits set this should have gone out
2394 as one instruction! */
2395 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
2396 all_bits_between_are_set = 1;
2397 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2401 if ((low_bits & (1 << i)) != 0)
2406 if ((high_bits & (1 << (i - 32))) != 0)
2409 all_bits_between_are_set = 0;
2412 *hbsp = highest_bit_set;
2413 *lbsp = lowest_bit_set;
2414 *abbasp = all_bits_between_are_set;
2417 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2420 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2421 unsigned HOST_WIDE_INT low_bits)
2423 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2426 || high_bits == 0xffffffff)
2429 analyze_64bit_constant (high_bits, low_bits,
2430 &highest_bit_set, &lowest_bit_set,
2431 &all_bits_between_are_set);
2433 if ((highest_bit_set == 63
2434 || lowest_bit_set == 0)
2435 && all_bits_between_are_set != 0)
2438 if ((highest_bit_set - lowest_bit_set) < 21)
2444 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2445 unsigned HOST_WIDE_INT,
2448 static unsigned HOST_WIDE_INT
2449 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2450 unsigned HOST_WIDE_INT low_bits,
2451 int lowest_bit_set, int shift)
2453 HOST_WIDE_INT hi, lo;
2455 if (lowest_bit_set < 32)
2457 lo = (low_bits >> lowest_bit_set) << shift;
2458 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2463 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2465 gcc_assert (! (hi & lo));
2469 /* Here we are sure to be arch64 and this is an integer constant
2470 being loaded into a register. Emit the most efficient
2471 insn sequence possible. Detection of all the 1-insn cases
2472 has been done already. */
2474 sparc_emit_set_const64 (rtx op0, rtx op1)
2476 unsigned HOST_WIDE_INT high_bits, low_bits;
2477 int lowest_bit_set, highest_bit_set;
2478 int all_bits_between_are_set;
2481 /* Sanity check that we know what we are working with. */
2482 gcc_assert (TARGET_ARCH64
2483 && (GET_CODE (op0) == SUBREG
2484 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
2486 if (! can_create_pseudo_p ())
2489 if (GET_CODE (op1) != CONST_INT)
2491 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2496 temp = gen_reg_rtx (DImode);
2498 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2499 low_bits = (INTVAL (op1) & 0xffffffff);
2501 /* low_bits bits 0 --> 31
2502 high_bits bits 32 --> 63 */
2504 analyze_64bit_constant (high_bits, low_bits,
2505 &highest_bit_set, &lowest_bit_set,
2506 &all_bits_between_are_set);
2508 /* First try for a 2-insn sequence. */
2510 /* These situations are preferred because the optimizer can
2511 * do more things with them:
2513 * sllx %reg, shift, %reg
2515 * srlx %reg, shift, %reg
2516 * 3) mov some_small_const, %reg
2517 * sllx %reg, shift, %reg
2519 if (((highest_bit_set == 63
2520 || lowest_bit_set == 0)
2521 && all_bits_between_are_set != 0)
2522 || ((highest_bit_set - lowest_bit_set) < 12))
2524 HOST_WIDE_INT the_const = -1;
2525 int shift = lowest_bit_set;
2527 if ((highest_bit_set != 63
2528 && lowest_bit_set != 0)
2529 || all_bits_between_are_set == 0)
2532 create_simple_focus_bits (high_bits, low_bits,
2535 else if (lowest_bit_set == 0)
2536 shift = -(63 - highest_bit_set);
2538 gcc_assert (SPARC_SIMM13_P (the_const));
2539 gcc_assert (shift != 0);
2541 emit_insn (gen_safe_SET64 (temp, the_const));
2543 emit_insn (gen_rtx_SET (VOIDmode,
2545 gen_rtx_ASHIFT (DImode,
2549 emit_insn (gen_rtx_SET (VOIDmode,
2551 gen_rtx_LSHIFTRT (DImode,
2553 GEN_INT (-shift))));
2557 /* Now a range of 22 or less bits set somewhere.
2558 * 1) sethi %hi(focus_bits), %reg
2559 * sllx %reg, shift, %reg
2560 * 2) sethi %hi(focus_bits), %reg
2561 * srlx %reg, shift, %reg
2563 if ((highest_bit_set - lowest_bit_set) < 21)
2565 unsigned HOST_WIDE_INT focus_bits =
2566 create_simple_focus_bits (high_bits, low_bits,
2567 lowest_bit_set, 10);
2569 gcc_assert (SPARC_SETHI_P (focus_bits));
2570 gcc_assert (lowest_bit_set != 10);
2572 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
2574 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2575 if (lowest_bit_set < 10)
2576 emit_insn (gen_rtx_SET (VOIDmode,
2578 gen_rtx_LSHIFTRT (DImode, temp,
2579 GEN_INT (10 - lowest_bit_set))));
2580 else if (lowest_bit_set > 10)
2581 emit_insn (gen_rtx_SET (VOIDmode,
2583 gen_rtx_ASHIFT (DImode, temp,
2584 GEN_INT (lowest_bit_set - 10))));
2588 /* 1) sethi %hi(low_bits), %reg
2589 * or %reg, %lo(low_bits), %reg
2590 * 2) sethi %hi(~low_bits), %reg
2591 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2594 || high_bits == 0xffffffff)
2596 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2597 (high_bits == 0xffffffff));
2601 /* Now, try 3-insn sequences. */
2603 /* 1) sethi %hi(high_bits), %reg
2604 * or %reg, %lo(high_bits), %reg
2605 * sllx %reg, 32, %reg
2609 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2613 /* We may be able to do something quick
2614 when the constant is negated, so try that. */
2615 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2616 (~low_bits) & 0xfffffc00))
2618 /* NOTE: The trailing bits get XOR'd so we need the
2619 non-negated bits, not the negated ones. */
2620 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2622 if ((((~high_bits) & 0xffffffff) == 0
2623 && ((~low_bits) & 0x80000000) == 0)
2624 || (((~high_bits) & 0xffffffff) == 0xffffffff
2625 && ((~low_bits) & 0x80000000) != 0))
2627 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
2629 if ((SPARC_SETHI_P (fast_int)
2630 && (~high_bits & 0xffffffff) == 0)
2631 || SPARC_SIMM13_P (fast_int))
2632 emit_insn (gen_safe_SET64 (temp, fast_int));
2634 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
2639 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2640 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2641 sparc_emit_set_const64 (temp, negated_const);
2644 /* If we are XOR'ing with -1, then we should emit a one's complement
2645 instead. This way the combiner will notice logical operations
2646 such as ANDN later on and substitute. */
2647 if (trailing_bits == 0x3ff)
2649 emit_insn (gen_rtx_SET (VOIDmode, op0,
2650 gen_rtx_NOT (DImode, temp)));
2654 emit_insn (gen_rtx_SET (VOIDmode,
2656 gen_safe_XOR64 (temp,
2657 (-0x400 | trailing_bits))));
2662 /* 1) sethi %hi(xxx), %reg
2663 * or %reg, %lo(xxx), %reg
2664 * sllx %reg, yyy, %reg
2666 * ??? This is just a generalized version of the low_bits==0
2667 * thing above, FIXME...
2669 if ((highest_bit_set - lowest_bit_set) < 32)
2671 unsigned HOST_WIDE_INT focus_bits =
2672 create_simple_focus_bits (high_bits, low_bits,
2675 /* We can't get here in this state. */
2676 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
2678 /* So what we know is that the set bits straddle the
2679 middle of the 64-bit word. */
2680 sparc_emit_set_const64_quick2 (op0, temp,
2686 /* 1) sethi %hi(high_bits), %reg
2687 * or %reg, %lo(high_bits), %reg
2688 * sllx %reg, 32, %reg
2689 * or %reg, low_bits, %reg
2691 if (SPARC_SIMM13_P(low_bits)
2692 && ((int)low_bits > 0))
2694 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2698 /* The easiest way when all else fails, is full decomposition. */
2699 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2701 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2703 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2704 return the mode to be used for the comparison. For floating-point,
2705 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2706 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2707 processing is needed. */
2710 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2712 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2738 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2739 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2741 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2742 return CCX_NOOVmode;
2748 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2755 /* Emit the compare insn and return the CC reg for a CODE comparison
2756 with operands X and Y. */
2759 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
2761 enum machine_mode mode;
2764 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2767 mode = SELECT_CC_MODE (code, x, y);
2769 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2770 fcc regs (cse can't tell they're really call clobbered regs and will
2771 remove a duplicate comparison even if there is an intervening function
2772 call - it will then try to reload the cc reg via an int reg which is why
2773 we need the movcc patterns). It is possible to provide the movcc
2774 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2775 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2776 to tell cse that CCFPE mode registers (even pseudos) are call
2779 /* ??? This is an experiment. Rather than making changes to cse which may
2780 or may not be easy/clean, we do our own cse. This is possible because
2781 we will generate hard registers. Cse knows they're call clobbered (it
2782 doesn't know the same thing about pseudos). If we guess wrong, no big
2783 deal, but if we win, great! */
2785 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2786 #if 1 /* experiment */
2789 /* We cycle through the registers to ensure they're all exercised. */
2790 static int next_fcc_reg = 0;
2791 /* Previous x,y for each fcc reg. */
2792 static rtx prev_args[4][2];
2794 /* Scan prev_args for x,y. */
2795 for (reg = 0; reg < 4; reg++)
2796 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2801 prev_args[reg][0] = x;
2802 prev_args[reg][1] = y;
2803 next_fcc_reg = (next_fcc_reg + 1) & 3;
2805 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2808 cc_reg = gen_reg_rtx (mode);
2809 #endif /* ! experiment */
2810 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2811 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2813 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2815 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2816 will only result in an unrecognizable insn so no point in asserting. */
2817 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
2823 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2826 gen_compare_reg (rtx cmp)
2828 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
2831 /* This function is used for v9 only.
2832 DEST is the target of the Scc insn.
2833 CODE is the code for an Scc's comparison.
2834 X and Y are the values we compare.
2836 This function is needed to turn
2839 (gt (reg:CCX 100 %icc)
2843 (gt:DI (reg:CCX 100 %icc)
2846 IE: The instruction recognizer needs to see the mode of the comparison to
2847 find the right instruction. We could use "gt:DI" right in the
2848 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2851 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
2854 && (GET_MODE (x) == DImode
2855 || GET_MODE (dest) == DImode))
2858 /* Try to use the movrCC insns. */
2860 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2862 && v9_regcmp_p (compare_code))
2867 /* Special case for op0 != 0. This can be done with one instruction if
2870 if (compare_code == NE
2871 && GET_MODE (dest) == DImode
2872 && rtx_equal_p (op0, dest))
2874 emit_insn (gen_rtx_SET (VOIDmode, dest,
2875 gen_rtx_IF_THEN_ELSE (DImode,
2876 gen_rtx_fmt_ee (compare_code, DImode,
2883 if (reg_overlap_mentioned_p (dest, op0))
2885 /* Handle the case where dest == x.
2886 We "early clobber" the result. */
2887 op0 = gen_reg_rtx (GET_MODE (x));
2888 emit_move_insn (op0, x);
2891 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2892 if (GET_MODE (op0) != DImode)
2894 temp = gen_reg_rtx (DImode);
2895 convert_move (temp, op0, 0);
2899 emit_insn (gen_rtx_SET (VOIDmode, dest,
2900 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2901 gen_rtx_fmt_ee (compare_code, DImode,
2909 x = gen_compare_reg_1 (compare_code, x, y);
2912 gcc_assert (GET_MODE (x) != CC_NOOVmode
2913 && GET_MODE (x) != CCX_NOOVmode);
2915 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2916 emit_insn (gen_rtx_SET (VOIDmode, dest,
2917 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2918 gen_rtx_fmt_ee (compare_code,
2919 GET_MODE (x), x, y),
2920 const1_rtx, dest)));
2926 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2927 without jumps using the addx/subx instructions. */
2930 emit_scc_insn (rtx operands[])
2937 /* The quad-word fp compare library routines all return nonzero to indicate
2938 true, which is different from the equivalent libgcc routines, so we must
2939 handle them specially here. */
2940 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2942 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2943 GET_CODE (operands[1]));
2944 operands[2] = XEXP (operands[1], 0);
2945 operands[3] = XEXP (operands[1], 1);
2948 code = GET_CODE (operands[1]);
2952 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2953 more applications). The exception to this is "reg != 0" which can
2954 be done in one instruction on v9 (so we do it). */
2957 if (GET_MODE (x) == SImode)
2961 pat = gen_seqsidi_special (operands[0], x, y);
2963 pat = gen_seqsisi_special (operands[0], x, y);
2967 else if (GET_MODE (x) == DImode)
2969 rtx pat = gen_seqdi_special (operands[0], x, y);
2977 if (GET_MODE (x) == SImode)
2981 pat = gen_snesidi_special (operands[0], x, y);
2983 pat = gen_snesisi_special (operands[0], x, y);
2987 else if (GET_MODE (x) == DImode)
2991 pat = gen_snedi_special_vis3 (operands[0], x, y);
2993 pat = gen_snedi_special (operands[0], x, y);
3001 && GET_MODE (x) == DImode
3003 && (code == GTU || code == LTU))
3004 && gen_v9_scc (operands[0], code, x, y))
3007 /* We can do LTU and GEU using the addx/subx instructions too. And
3008 for GTU/LEU, if both operands are registers swap them and fall
3009 back to the easy case. */
3010 if (code == GTU || code == LEU)
3012 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
3013 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
3018 code = swap_condition (code);
3023 || (!TARGET_VIS3 && code == GEU))
3025 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3026 gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
3027 gen_compare_reg_1 (code, x, y),
3032 /* All the posibilities to use addx/subx based sequences has been
3033 exhausted, try for a 3 instruction sequence using v9 conditional
3035 if (TARGET_V9 && gen_v9_scc (operands[0], code, x, y))
3038 /* Nope, do branches. */
3042 /* Emit a conditional jump insn for the v9 architecture using comparison code
3043 CODE and jump target LABEL.
3044 This function exists to take advantage of the v9 brxx insns. */
3047 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
3049 emit_jump_insn (gen_rtx_SET (VOIDmode,
3051 gen_rtx_IF_THEN_ELSE (VOIDmode,
3052 gen_rtx_fmt_ee (code, GET_MODE (op0),
3054 gen_rtx_LABEL_REF (VOIDmode, label),
3058 /* Emit a conditional jump insn for the UA2011 architecture using
3059 comparison code CODE and jump target LABEL. This function exists
3060 to take advantage of the UA2011 Compare and Branch insns. */
3063 emit_cbcond_insn (enum rtx_code code, rtx op0, rtx op1, rtx label)
3067 if_then_else = gen_rtx_IF_THEN_ELSE (VOIDmode,
3068 gen_rtx_fmt_ee(code, GET_MODE(op0),
3070 gen_rtx_LABEL_REF (VOIDmode, label),
3073 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
3077 emit_conditional_branch_insn (rtx operands[])
3079 /* The quad-word fp compare library routines all return nonzero to indicate
3080 true, which is different from the equivalent libgcc routines, so we must
3081 handle them specially here. */
3082 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
3084 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
3085 GET_CODE (operands[0]));
3086 operands[1] = XEXP (operands[0], 0);
3087 operands[2] = XEXP (operands[0], 1);
3090 /* If we can tell early on that the comparison is against a constant
3091 that won't fit in the 5-bit signed immediate field of a cbcond,
3092 use one of the other v9 conditional branch sequences. */
3094 && GET_CODE (operands[1]) == REG
3095 && (GET_MODE (operands[1]) == SImode
3096 || (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
3097 && (GET_CODE (operands[2]) != CONST_INT
3098 || SPARC_SIMM5_P (INTVAL (operands[2]))))
3100 emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2], operands[3]);
3104 if (TARGET_ARCH64 && operands[2] == const0_rtx
3105 && GET_CODE (operands[1]) == REG
3106 && GET_MODE (operands[1]) == DImode)
3108 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
3112 operands[1] = gen_compare_reg (operands[0]);
3113 operands[2] = const0_rtx;
3114 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
3115 operands[1], operands[2]);
3116 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
3121 /* Generate a DFmode part of a hard TFmode register.
3122 REG is the TFmode hard register, LOW is 1 for the
3123 low 64bit of the register and 0 otherwise.
3126 gen_df_reg (rtx reg, int low)
3128 int regno = REGNO (reg);
3130 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
3131 regno += (TARGET_ARCH64 && SPARC_INT_REG_P (regno)) ? 1 : 2;
3132 return gen_rtx_REG (DFmode, regno);
3135 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3136 Unlike normal calls, TFmode operands are passed by reference. It is
3137 assumed that no more than 3 operands are required. */
3140 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
3142 rtx ret_slot = NULL, arg[3], func_sym;
3145 /* We only expect to be called for conversions, unary, and binary ops. */
3146 gcc_assert (nargs == 2 || nargs == 3);
3148 for (i = 0; i < nargs; ++i)
3150 rtx this_arg = operands[i];
3153 /* TFmode arguments and return values are passed by reference. */
3154 if (GET_MODE (this_arg) == TFmode)
3156 int force_stack_temp;
3158 force_stack_temp = 0;
3159 if (TARGET_BUGGY_QP_LIB && i == 0)
3160 force_stack_temp = 1;
3162 if (GET_CODE (this_arg) == MEM
3163 && ! force_stack_temp)
3165 tree expr = MEM_EXPR (this_arg);
3167 mark_addressable (expr);
3168 this_arg = XEXP (this_arg, 0);
3170 else if (CONSTANT_P (this_arg)
3171 && ! force_stack_temp)
3173 this_slot = force_const_mem (TFmode, this_arg);
3174 this_arg = XEXP (this_slot, 0);
3178 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode));
3180 /* Operand 0 is the return value. We'll copy it out later. */
3182 emit_move_insn (this_slot, this_arg);
3184 ret_slot = this_slot;
3186 this_arg = XEXP (this_slot, 0);
3193 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
3195 if (GET_MODE (operands[0]) == TFmode)
3198 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
3199 arg[0], GET_MODE (arg[0]),
3200 arg[1], GET_MODE (arg[1]));
3202 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
3203 arg[0], GET_MODE (arg[0]),
3204 arg[1], GET_MODE (arg[1]),
3205 arg[2], GET_MODE (arg[2]));
3208 emit_move_insn (operands[0], ret_slot);
3214 gcc_assert (nargs == 2);
3216 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
3217 GET_MODE (operands[0]), 1,
3218 arg[1], GET_MODE (arg[1]));
3220 if (ret != operands[0])
3221 emit_move_insn (operands[0], ret);
3225 /* Expand soft-float TFmode calls to sparc abi routines. */
3228 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
3250 emit_soft_tfmode_libcall (func, 3, operands);
3254 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
3258 gcc_assert (code == SQRT);
3261 emit_soft_tfmode_libcall (func, 2, operands);
3265 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
3272 switch (GET_MODE (operands[1]))
3285 case FLOAT_TRUNCATE:
3286 switch (GET_MODE (operands[0]))
3300 switch (GET_MODE (operands[1]))
3305 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
3315 case UNSIGNED_FLOAT:
3316 switch (GET_MODE (operands[1]))
3321 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
3332 switch (GET_MODE (operands[0]))
3346 switch (GET_MODE (operands[0]))
3363 emit_soft_tfmode_libcall (func, 2, operands);
3366 /* Expand a hard-float tfmode operation. All arguments must be in
3370 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
3374 if (GET_RTX_CLASS (code) == RTX_UNARY)
3376 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
3377 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
3381 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
3382 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
3383 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
3384 operands[1], operands[2]);
3387 if (register_operand (operands[0], VOIDmode))
3390 dest = gen_reg_rtx (GET_MODE (operands[0]));
3392 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
3394 if (dest != operands[0])
3395 emit_move_insn (operands[0], dest);
3399 emit_tfmode_binop (enum rtx_code code, rtx *operands)
3401 if (TARGET_HARD_QUAD)
3402 emit_hard_tfmode_operation (code, operands);
3404 emit_soft_tfmode_binop (code, operands);
3408 emit_tfmode_unop (enum rtx_code code, rtx *operands)
3410 if (TARGET_HARD_QUAD)
3411 emit_hard_tfmode_operation (code, operands);
3413 emit_soft_tfmode_unop (code, operands);
3417 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
3419 if (TARGET_HARD_QUAD)
3420 emit_hard_tfmode_operation (code, operands);
3422 emit_soft_tfmode_cvt (code, operands);
3425 /* Return nonzero if a branch/jump/call instruction will be emitting
3426 nop into its delay slot. */
3429 empty_delay_slot (rtx insn)
3433 /* If no previous instruction (should not happen), return true. */
3434 if (PREV_INSN (insn) == NULL)
3437 seq = NEXT_INSN (PREV_INSN (insn));
3438 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3444 /* Return nonzero if we should emit a nop after a cbcond instruction.
3445 The cbcond instruction does not have a delay slot, however there is
3446 a severe performance penalty if a control transfer appears right
3447 after a cbcond. Therefore we emit a nop when we detect this
3451 emit_cbcond_nop (rtx insn)
3453 rtx next = next_active_insn (insn);
3458 if (NONJUMP_INSN_P (next)
3459 && GET_CODE (PATTERN (next)) == SEQUENCE)
3460 next = XVECEXP (PATTERN (next), 0, 0);
3461 else if (CALL_P (next)
3462 && GET_CODE (PATTERN (next)) == PARALLEL)
3464 rtx delay = XVECEXP (PATTERN (next), 0, 1);
3466 if (GET_CODE (delay) == RETURN)
3468 /* It's a sibling call. Do not emit the nop if we're going
3469 to emit something other than the jump itself as the first
3470 instruction of the sibcall sequence. */
3471 if (sparc_leaf_function_p || TARGET_FLAT)
3476 if (NONJUMP_INSN_P (next))
3482 /* Return nonzero if TRIAL can go into the call delay slot. */
3485 eligible_for_call_delay (rtx trial)
3489 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
3493 call __tls_get_addr, %tgd_call (foo)
3494 add %l7, %o0, %o0, %tgd_add (foo)
3495 while Sun as/ld does not. */
3496 if (TARGET_GNU_TLS || !TARGET_TLS)
3499 pat = PATTERN (trial);
3501 /* We must reject tgd_add{32|64}, i.e.
3502 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3503 and tldm_add{32|64}, i.e.
3504 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3506 if (GET_CODE (pat) == SET
3507 && GET_CODE (SET_SRC (pat)) == PLUS)
3509 rtx unspec = XEXP (SET_SRC (pat), 1);
3511 if (GET_CODE (unspec) == UNSPEC
3512 && (XINT (unspec, 1) == UNSPEC_TLSGD
3513 || XINT (unspec, 1) == UNSPEC_TLSLDM))
3520 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3521 instruction. RETURN_P is true if the v9 variant 'return' is to be
3522 considered in the test too.
3524 TRIAL must be a SET whose destination is a REG appropriate for the
3525 'restore' instruction or, if RETURN_P is true, for the 'return'
3529 eligible_for_restore_insn (rtx trial, bool return_p)
3531 rtx pat = PATTERN (trial);
3532 rtx src = SET_SRC (pat);
3533 bool src_is_freg = false;
3536 /* Since we now can do moves between float and integer registers when
3537 VIS3 is enabled, we have to catch this case. We can allow such
3538 moves when doing a 'return' however. */
3540 if (GET_CODE (src_reg) == SUBREG)
3541 src_reg = SUBREG_REG (src_reg);
3542 if (GET_CODE (src_reg) == REG
3543 && SPARC_FP_REG_P (REGNO (src_reg)))
3546 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3547 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3548 && arith_operand (src, GET_MODE (src))
3552 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3554 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3557 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3558 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3559 && arith_double_operand (src, GET_MODE (src))
3561 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3563 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3564 else if (! TARGET_FPU && register_operand (src, SFmode))
3567 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3568 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3571 /* If we have the 'return' instruction, anything that does not use
3572 local or output registers and can go into a delay slot wins. */
3573 else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1))
3576 /* The 'restore src1,src2,dest' pattern for SImode. */
3577 else if (GET_CODE (src) == PLUS
3578 && register_operand (XEXP (src, 0), SImode)
3579 && arith_operand (XEXP (src, 1), SImode))
3582 /* The 'restore src1,src2,dest' pattern for DImode. */
3583 else if (GET_CODE (src) == PLUS
3584 && register_operand (XEXP (src, 0), DImode)
3585 && arith_double_operand (XEXP (src, 1), DImode))
3588 /* The 'restore src1,%lo(src2),dest' pattern. */
3589 else if (GET_CODE (src) == LO_SUM
3590 && ! TARGET_CM_MEDMID
3591 && ((register_operand (XEXP (src, 0), SImode)
3592 && immediate_operand (XEXP (src, 1), SImode))
3594 && register_operand (XEXP (src, 0), DImode)
3595 && immediate_operand (XEXP (src, 1), DImode))))
3598 /* The 'restore src,src,dest' pattern. */
3599 else if (GET_CODE (src) == ASHIFT
3600 && (register_operand (XEXP (src, 0), SImode)
3601 || register_operand (XEXP (src, 0), DImode))
3602 && XEXP (src, 1) == const1_rtx)
3608 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3611 eligible_for_return_delay (rtx trial)
3616 /* If the function uses __builtin_eh_return, the eh_return machinery
3617 occupies the delay slot. */
3618 if (crtl->calls_eh_return)
3621 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
3624 /* In the case of a leaf or flat function, anything can go into the slot. */
3625 if (sparc_leaf_function_p || TARGET_FLAT)
3628 if (!NONJUMP_INSN_P (trial))
3631 pat = PATTERN (trial);
3632 if (GET_CODE (pat) == PARALLEL)
3638 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
3640 rtx expr = XVECEXP (pat, 0, i);
3641 if (GET_CODE (expr) != SET)
3643 if (GET_CODE (SET_DEST (expr)) != REG)
3645 regno = REGNO (SET_DEST (expr));
3646 if (regno >= 8 && regno < 24)
3649 return !epilogue_renumber (&pat, 1);
3652 if (GET_CODE (pat) != SET)
3655 if (GET_CODE (SET_DEST (pat)) != REG)
3658 regno = REGNO (SET_DEST (pat));
3660 /* Otherwise, only operations which can be done in tandem with
3661 a `restore' or `return' insn can go into the delay slot. */
3662 if (regno >= 8 && regno < 24)
3665 /* If this instruction sets up floating point register and we have a return
3666 instruction, it can probably go in. But restore will not work
3668 if (! SPARC_INT_REG_P (regno))
3669 return TARGET_V9 && !epilogue_renumber (&pat, 1);
3671 return eligible_for_restore_insn (trial, true);
3674 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3677 eligible_for_sibcall_delay (rtx trial)
3681 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
3684 if (!NONJUMP_INSN_P (trial))
3687 pat = PATTERN (trial);
3689 if (sparc_leaf_function_p || TARGET_FLAT)
3691 /* If the tail call is done using the call instruction,
3692 we have to restore %o7 in the delay slot. */
3693 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3696 /* %g1 is used to build the function address */
3697 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3703 if (GET_CODE (pat) != SET)
3706 /* Otherwise, only operations which can be done in tandem with
3707 a `restore' insn can go into the delay slot. */
3708 if (GET_CODE (SET_DEST (pat)) != REG
3709 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3710 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat))))
3713 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3715 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3718 return eligible_for_restore_insn (trial, false);
3721 /* Determine if it's legal to put X into the constant pool. This
3722 is not possible if X contains the address of a symbol that is
3723 not constant (TLS) or not known at final link time (PIC). */
3726 sparc_cannot_force_const_mem (enum machine_mode mode, rtx x)
3728 switch (GET_CODE (x))
3733 /* Accept all non-symbolic constants. */
3737 /* Labels are OK iff we are non-PIC. */
3738 return flag_pic != 0;
3741 /* 'Naked' TLS symbol references are never OK,
3742 non-TLS symbols are OK iff we are non-PIC. */
3743 if (SYMBOL_REF_TLS_MODEL (x))
3746 return flag_pic != 0;
3749 return sparc_cannot_force_const_mem (mode, XEXP (x, 0));
3752 return sparc_cannot_force_const_mem (mode, XEXP (x, 0))
3753 || sparc_cannot_force_const_mem (mode, XEXP (x, 1));
3761 /* Global Offset Table support. */
3762 static GTY(()) rtx got_helper_rtx = NULL_RTX;
3763 static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
3765 /* Return the SYMBOL_REF for the Global Offset Table. */
3767 static GTY(()) rtx sparc_got_symbol = NULL_RTX;
3772 if (!sparc_got_symbol)
3773 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3775 return sparc_got_symbol;
3778 /* Ensure that we are not using patterns that are not OK with PIC. */
3788 op = recog_data.operand[i];
3789 gcc_assert (GET_CODE (op) != SYMBOL_REF
3790 && (GET_CODE (op) != CONST
3791 || (GET_CODE (XEXP (op, 0)) == MINUS
3792 && XEXP (XEXP (op, 0), 0) == sparc_got ()
3793 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
3800 /* Return true if X is an address which needs a temporary register when
3801 reloaded while generating PIC code. */
3804 pic_address_needs_scratch (rtx x)
3806 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3807 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3808 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3809 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3810 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3816 /* Determine if a given RTX is a valid constant. We already know this
3817 satisfies CONSTANT_P. */
3820 sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
3822 switch (GET_CODE (x))
3826 if (sparc_tls_referenced_p (x))
3831 if (GET_MODE (x) == VOIDmode)
3834 /* Floating point constants are generally not ok.
3835 The only exception is 0.0 and all-ones in VIS. */
3837 && SCALAR_FLOAT_MODE_P (mode)
3838 && (const_zero_operand (x, mode)
3839 || const_all_ones_operand (x, mode)))
3845 /* Vector constants are generally not ok.
3846 The only exception is 0 or -1 in VIS. */
3848 && (const_zero_operand (x, mode)
3849 || const_all_ones_operand (x, mode)))
3861 /* Determine if a given RTX is a valid constant address. */
3864 constant_address_p (rtx x)
3866 switch (GET_CODE (x))
3874 if (flag_pic && pic_address_needs_scratch (x))
3876 return sparc_legitimate_constant_p (Pmode, x);
3879 return !flag_pic && sparc_legitimate_constant_p (Pmode, x);
3886 /* Nonzero if the constant value X is a legitimate general operand
3887 when generating PIC code. It is given that flag_pic is on and
3888 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3891 legitimate_pic_operand_p (rtx x)
3893 if (pic_address_needs_scratch (x))
3895 if (sparc_tls_referenced_p (x))
3900 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3902 && INTVAL (X) >= -0x1000 \
3903 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3905 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3907 && INTVAL (X) >= -0x1000 \
3908 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3910 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3912 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3913 ordinarily. This changes a bit when generating PIC. */
3916 sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3918 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3920 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3922 else if (GET_CODE (addr) == PLUS)
3924 rs1 = XEXP (addr, 0);
3925 rs2 = XEXP (addr, 1);
3927 /* Canonicalize. REG comes first, if there are no regs,
3928 LO_SUM comes first. */
3930 && GET_CODE (rs1) != SUBREG
3932 || GET_CODE (rs2) == SUBREG
3933 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3935 rs1 = XEXP (addr, 1);
3936 rs2 = XEXP (addr, 0);
3940 && rs1 == pic_offset_table_rtx
3942 && GET_CODE (rs2) != SUBREG
3943 && GET_CODE (rs2) != LO_SUM
3944 && GET_CODE (rs2) != MEM
3945 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
3946 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3947 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3949 || GET_CODE (rs1) == SUBREG)
3950 && RTX_OK_FOR_OFFSET_P (rs2, mode)))
3955 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3956 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3958 /* We prohibit REG + REG for TFmode when there are no quad move insns
3959 and we consequently need to split. We do this because REG+REG
3960 is not an offsettable address. If we get the situation in reload
3961 where source and destination of a movtf pattern are both MEMs with
3962 REG+REG address, then only one of them gets converted to an
3963 offsettable address. */
3965 && ! (TARGET_ARCH64 && TARGET_HARD_QUAD))
3968 /* Likewise for TImode, but in all cases. */
3972 /* We prohibit REG + REG on ARCH32 if not optimizing for
3973 DFmode/DImode because then mem_min_alignment is likely to be zero
3974 after reload and the forced split would lack a matching splitter
3976 if (TARGET_ARCH32 && !optimize
3977 && (mode == DFmode || mode == DImode))
3980 else if (USE_AS_OFFSETABLE_LO10
3981 && GET_CODE (rs1) == LO_SUM
3983 && ! TARGET_CM_MEDMID
3984 && RTX_OK_FOR_OLO10_P (rs2, mode))
3987 imm1 = XEXP (rs1, 1);
3988 rs1 = XEXP (rs1, 0);
3989 if (!CONSTANT_P (imm1)
3990 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3994 else if (GET_CODE (addr) == LO_SUM)
3996 rs1 = XEXP (addr, 0);
3997 imm1 = XEXP (addr, 1);
3999 if (!CONSTANT_P (imm1)
4000 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
4003 /* We can't allow TFmode in 32-bit mode, because an offset greater
4004 than the alignment (8) may cause the LO_SUM to overflow. */
4005 if (mode == TFmode && TARGET_ARCH32)
4008 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
4013 if (GET_CODE (rs1) == SUBREG)
4014 rs1 = SUBREG_REG (rs1);
4020 if (GET_CODE (rs2) == SUBREG)
4021 rs2 = SUBREG_REG (rs2);
4028 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
4029 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
4034 if ((! SPARC_INT_REG_P (REGNO (rs1))
4035 && REGNO (rs1) != FRAME_POINTER_REGNUM
4036 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
4038 && (! SPARC_INT_REG_P (REGNO (rs2))
4039 && REGNO (rs2) != FRAME_POINTER_REGNUM
4040 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
4046 /* Return the SYMBOL_REF for the tls_get_addr function. */
4048 static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
4051 sparc_tls_get_addr (void)
4053 if (!sparc_tls_symbol)
4054 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
4056 return sparc_tls_symbol;
4059 /* Return the Global Offset Table to be used in TLS mode. */
4062 sparc_tls_got (void)
4064 /* In PIC mode, this is just the PIC offset table. */
4067 crtl->uses_pic_offset_table = 1;
4068 return pic_offset_table_rtx;
4071 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4072 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4073 if (TARGET_SUN_TLS && TARGET_ARCH32)
4075 load_got_register ();
4076 return global_offset_table_rtx;
4079 /* In all other cases, we load a new pseudo with the GOT symbol. */
4080 return copy_to_reg (sparc_got ());
4083 /* Return true if X contains a thread-local symbol. */
4086 sparc_tls_referenced_p (rtx x)
4088 if (!TARGET_HAVE_TLS)
4091 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
4092 x = XEXP (XEXP (x, 0), 0);
4094 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
4097 /* That's all we handle in sparc_legitimize_tls_address for now. */
4101 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4102 this (thread-local) address. */
4105 sparc_legitimize_tls_address (rtx addr)
4107 rtx temp1, temp2, temp3, ret, o0, got, insn;
4109 gcc_assert (can_create_pseudo_p ());
4111 if (GET_CODE (addr) == SYMBOL_REF)
4112 switch (SYMBOL_REF_TLS_MODEL (addr))
4114 case TLS_MODEL_GLOBAL_DYNAMIC:
4116 temp1 = gen_reg_rtx (SImode);
4117 temp2 = gen_reg_rtx (SImode);
4118 ret = gen_reg_rtx (Pmode);
4119 o0 = gen_rtx_REG (Pmode, 8);
4120 got = sparc_tls_got ();
4121 emit_insn (gen_tgd_hi22 (temp1, addr));
4122 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
4125 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
4126 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
4131 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
4132 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
4135 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
4136 insn = get_insns ();
4138 emit_libcall_block (insn, ret, o0, addr);
4141 case TLS_MODEL_LOCAL_DYNAMIC:
4143 temp1 = gen_reg_rtx (SImode);
4144 temp2 = gen_reg_rtx (SImode);
4145 temp3 = gen_reg_rtx (Pmode);
4146 ret = gen_reg_rtx (Pmode);
4147 o0 = gen_rtx_REG (Pmode, 8);
4148 got = sparc_tls_got ();
4149 emit_insn (gen_tldm_hi22 (temp1));
4150 emit_insn (gen_tldm_lo10 (temp2, temp1));
4153 emit_insn (gen_tldm_add32 (o0, got, temp2));
4154 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
4159 emit_insn (gen_tldm_add64 (o0, got, temp2));
4160 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
4163 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
4164 insn = get_insns ();
4166 emit_libcall_block (insn, temp3, o0,
4167 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
4168 UNSPEC_TLSLD_BASE));
4169 temp1 = gen_reg_rtx (SImode);
4170 temp2 = gen_reg_rtx (SImode);
4171 emit_insn (gen_tldo_hix22 (temp1, addr));
4172 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
4174 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
4176 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
4179 case TLS_MODEL_INITIAL_EXEC:
4180 temp1 = gen_reg_rtx (SImode);
4181 temp2 = gen_reg_rtx (SImode);
4182 temp3 = gen_reg_rtx (Pmode);
4183 got = sparc_tls_got ();
4184 emit_insn (gen_tie_hi22 (temp1, addr));
4185 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
4187 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
4189 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
4192 ret = gen_reg_rtx (Pmode);
4194 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
4197 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
4201 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
4204 case TLS_MODEL_LOCAL_EXEC:
4205 temp1 = gen_reg_rtx (Pmode);
4206 temp2 = gen_reg_rtx (Pmode);
4209 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
4210 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
4214 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
4215 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
4217 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
4224 else if (GET_CODE (addr) == CONST)
4228 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
4230 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
4231 offset = XEXP (XEXP (addr, 0), 1);
4233 base = force_operand (base, NULL_RTX);
4234 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
4235 offset = force_reg (Pmode, offset);
4236 ret = gen_rtx_PLUS (Pmode, base, offset);
4240 gcc_unreachable (); /* for now ... */
4245 /* Legitimize PIC addresses. If the address is already position-independent,
4246 we return ORIG. Newly generated position-independent addresses go into a
4247 reg. This is REG if nonzero, otherwise we allocate register(s) as
4251 sparc_legitimize_pic_address (rtx orig, rtx reg)
4253 bool gotdata_op = false;
4255 if (GET_CODE (orig) == SYMBOL_REF
4256 /* See the comment in sparc_expand_move. */
4257 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
4259 rtx pic_ref, address;
4264 gcc_assert (can_create_pseudo_p ());
4265 reg = gen_reg_rtx (Pmode);
4270 /* If not during reload, allocate another temp reg here for loading
4271 in the address, so that these instructions can be optimized
4273 rtx temp_reg = (! can_create_pseudo_p ()
4274 ? reg : gen_reg_rtx (Pmode));
4276 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4277 won't get confused into thinking that these two instructions
4278 are loading in the true address of the symbol. If in the
4279 future a PIC rtx exists, that should be used instead. */
4282 emit_insn (gen_movdi_high_pic (temp_reg, orig));
4283 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
4287 emit_insn (gen_movsi_high_pic (temp_reg, orig));
4288 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
4296 crtl->uses_pic_offset_table = 1;
4300 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
4301 pic_offset_table_rtx,
4304 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
4305 pic_offset_table_rtx,
4311 = gen_const_mem (Pmode,
4312 gen_rtx_PLUS (Pmode,
4313 pic_offset_table_rtx, address));
4314 insn = emit_move_insn (reg, pic_ref);
4317 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4319 set_unique_reg_note (insn, REG_EQUAL, orig);
4322 else if (GET_CODE (orig) == CONST)
4326 if (GET_CODE (XEXP (orig, 0)) == PLUS
4327 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
4332 gcc_assert (can_create_pseudo_p ());
4333 reg = gen_reg_rtx (Pmode);
4336 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
4337 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
4338 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
4339 base == reg ? NULL_RTX : reg);
4341 if (GET_CODE (offset) == CONST_INT)
4343 if (SMALL_INT (offset))
4344 return plus_constant (Pmode, base, INTVAL (offset));
4345 else if (can_create_pseudo_p ())
4346 offset = force_reg (Pmode, offset);
4348 /* If we reach here, then something is seriously wrong. */
4351 return gen_rtx_PLUS (Pmode, base, offset);
4353 else if (GET_CODE (orig) == LABEL_REF)
4354 /* ??? We ought to be checking that the register is live instead, in case
4355 it is eliminated. */
4356 crtl->uses_pic_offset_table = 1;
4361 /* Try machine-dependent ways of modifying an illegitimate address X
4362 to be legitimate. If we find one, return the new, valid address.
4364 OLDX is the address as it was before break_out_memory_refs was called.
4365 In some cases it is useful to look at this to decide what needs to be done.
4367 MODE is the mode of the operand pointed to by X.
4369 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4372 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
4373 enum machine_mode mode)
4377 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
4378 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
4379 force_operand (XEXP (x, 0), NULL_RTX));
4380 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
4381 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
4382 force_operand (XEXP (x, 1), NULL_RTX));
4383 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
4384 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
4386 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
4387 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
4388 force_operand (XEXP (x, 1), NULL_RTX));
4390 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
4393 if (sparc_tls_referenced_p (x))
4394 x = sparc_legitimize_tls_address (x);
4396 x = sparc_legitimize_pic_address (x, NULL_RTX);
4397 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
4398 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
4399 copy_to_mode_reg (Pmode, XEXP (x, 1)));
4400 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
4401 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
4402 copy_to_mode_reg (Pmode, XEXP (x, 0)));
4403 else if (GET_CODE (x) == SYMBOL_REF
4404 || GET_CODE (x) == CONST
4405 || GET_CODE (x) == LABEL_REF)
4406 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
4411 /* Delegitimize an address that was legitimized by the above function. */
4414 sparc_delegitimize_address (rtx x)
4416 x = delegitimize_mem_from_attrs (x);
4418 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
4419 switch (XINT (XEXP (x, 1), 1))
4421 case UNSPEC_MOVE_PIC:
4423 x = XVECEXP (XEXP (x, 1), 0, 0);
4424 gcc_assert (GET_CODE (x) == SYMBOL_REF);
4430 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4431 if (GET_CODE (x) == MINUS
4432 && REG_P (XEXP (x, 0))
4433 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4434 && GET_CODE (XEXP (x, 1)) == LO_SUM
4435 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
4436 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
4438 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
4439 gcc_assert (GET_CODE (x) == LABEL_REF);
4445 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4446 replace the input X, or the original X if no replacement is called for.
4447 The output parameter *WIN is 1 if the calling macro should goto WIN,
4450 For SPARC, we wish to handle addresses by splitting them into
4451 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4452 This cuts the number of extra insns by one.
4454 Do nothing when generating PIC code and the address is a symbolic
4455 operand or requires a scratch register. */
4458 sparc_legitimize_reload_address (rtx x, enum machine_mode mode,
4459 int opnum, int type,
4460 int ind_levels ATTRIBUTE_UNUSED, int *win)
4462 /* Decompose SImode constants into HIGH+LO_SUM. */
4464 && (mode != TFmode || TARGET_ARCH64)
4465 && GET_MODE (x) == SImode
4466 && GET_CODE (x) != LO_SUM
4467 && GET_CODE (x) != HIGH
4468 && sparc_cmodel <= CM_MEDLOW
4470 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
4472 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
4473 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4474 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4475 opnum, (enum reload_type)type);
4480 /* We have to recognize what we have already generated above. */
4481 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
4483 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4484 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4485 opnum, (enum reload_type)type);
4494 /* Return true if ADDR (a legitimate address expression)
4495 has an effect that depends on the machine mode it is used for.
4501 is not equivalent to
4503 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4505 because [%l7+a+1] is interpreted as the address of (a+1). */
4509 sparc_mode_dependent_address_p (const_rtx addr,
4510 addr_space_t as ATTRIBUTE_UNUSED)
4512 if (flag_pic && GET_CODE (addr) == PLUS)
4514 rtx op0 = XEXP (addr, 0);
4515 rtx op1 = XEXP (addr, 1);
4516 if (op0 == pic_offset_table_rtx
4517 && symbolic_operand (op1, VOIDmode))
4524 #ifdef HAVE_GAS_HIDDEN
4525 # define USE_HIDDEN_LINKONCE 1
4527 # define USE_HIDDEN_LINKONCE 0
4531 get_pc_thunk_name (char name[32], unsigned int regno)
4533 const char *reg_name = reg_names[regno];
4535 /* Skip the leading '%' as that cannot be used in a
4539 if (USE_HIDDEN_LINKONCE)
4540 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
4542 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
4545 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4548 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
4550 int orig_flag_pic = flag_pic;
4553 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4556 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
4558 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
4559 flag_pic = orig_flag_pic;
4564 /* Emit code to load the GOT register. */
4567 load_got_register (void)
4569 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4570 if (!global_offset_table_rtx)
4571 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
4573 if (TARGET_VXWORKS_RTP)
4574 emit_insn (gen_vxworks_load_got ());
4577 /* The GOT symbol is subject to a PC-relative relocation so we need a
4578 helper function to add the PC value and thus get the final value. */
4579 if (!got_helper_rtx)
4582 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
4583 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4586 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
4588 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
4591 /* Need to emit this whether or not we obey regdecls,
4592 since setjmp/longjmp can cause life info to screw up.
4593 ??? In the case where we don't obey regdecls, this is not sufficient
4594 since we may not fall out the bottom. */
4595 emit_use (global_offset_table_rtx);
4598 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4599 address of the call target. */
4602 sparc_emit_call_insn (rtx pat, rtx addr)
4606 insn = emit_call_insn (pat);
4608 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4609 if (TARGET_VXWORKS_RTP
4611 && GET_CODE (addr) == SYMBOL_REF
4612 && (SYMBOL_REF_DECL (addr)
4613 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
4614 : !SYMBOL_REF_LOCAL_P (addr)))
4616 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
4617 crtl->uses_pic_offset_table = 1;
4621 /* Return 1 if RTX is a MEM which is known to be aligned to at
4622 least a DESIRED byte boundary. */
4625 mem_min_alignment (rtx mem, int desired)
4627 rtx addr, base, offset;
4629 /* If it's not a MEM we can't accept it. */
4630 if (GET_CODE (mem) != MEM)
4634 if (!TARGET_UNALIGNED_DOUBLES
4635 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
4638 /* ??? The rest of the function predates MEM_ALIGN so
4639 there is probably a bit of redundancy. */
4640 addr = XEXP (mem, 0);
4641 base = offset = NULL_RTX;
4642 if (GET_CODE (addr) == PLUS)
4644 if (GET_CODE (XEXP (addr, 0)) == REG)
4646 base = XEXP (addr, 0);
4648 /* What we are saying here is that if the base
4649 REG is aligned properly, the compiler will make
4650 sure any REG based index upon it will be so
4652 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4653 offset = XEXP (addr, 1);
4655 offset = const0_rtx;
4658 else if (GET_CODE (addr) == REG)
4661 offset = const0_rtx;
4664 if (base != NULL_RTX)
4666 int regno = REGNO (base);
4668 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
4670 /* Check if the compiler has recorded some information
4671 about the alignment of the base REG. If reload has
4672 completed, we already matched with proper alignments.
4673 If not running global_alloc, reload might give us
4674 unaligned pointer to local stack though. */
4676 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4677 || (optimize && reload_completed))
4678 && (INTVAL (offset) & (desired - 1)) == 0)
4683 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4687 else if (! TARGET_UNALIGNED_DOUBLES
4688 || CONSTANT_P (addr)
4689 || GET_CODE (addr) == LO_SUM)
4691 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4692 is true, in which case we can only assume that an access is aligned if
4693 it is to a constant address, or the address involves a LO_SUM. */
4697 /* An obviously unaligned address. */
4702 /* Vectors to keep interesting information about registers where it can easily
4703 be got. We used to use the actual mode value as the bit number, but there
4704 are more than 32 modes now. Instead we use two tables: one indexed by
4705 hard register number, and one indexed by mode. */
4707 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4708 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4709 mapped into one sparc_mode_class mode. */
4711 enum sparc_mode_class {
4712 H_MODE, S_MODE, D_MODE, T_MODE, O_MODE,
4713 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4717 /* Modes for single-word and smaller quantities. */
4719 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4721 /* Modes for double-word and smaller quantities. */
4722 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4724 /* Modes for quad-word and smaller quantities. */
4725 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4727 /* Modes for 8-word and smaller quantities. */
4728 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4730 /* Modes for single-float quantities. */
4731 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4733 /* Modes for double-float and smaller quantities. */
4734 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4736 /* Modes for quad-float and smaller quantities. */
4737 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4739 /* Modes for quad-float pairs and smaller quantities. */
4740 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4742 /* Modes for double-float only quantities. */
4743 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4745 /* Modes for quad-float and double-float only quantities. */
4746 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4748 /* Modes for quad-float pairs and double-float only quantities. */
4749 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4751 /* Modes for condition codes. */
4752 #define CC_MODES (1 << (int) CC_MODE)
4753 #define CCFP_MODES (1 << (int) CCFP_MODE)
4755 /* Value is 1 if register/mode pair is acceptable on sparc.
4756 The funny mixture of D and T modes is because integer operations
4757 do not specially operate on tetra quantities, so non-quad-aligned
4758 registers can hold quadword quantities (except %o4 and %i4 because
4759 they cross fixed registers). */
4761 /* This points to either the 32 bit or the 64 bit version. */
4762 const int *hard_regno_mode_classes;
4764 static const int hard_32bit_mode_classes[] = {
4765 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4766 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4767 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4768 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4770 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4771 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4772 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4773 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4775 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4776 and none can hold SFmode/SImode values. */
4777 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4778 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4779 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4780 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4783 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4785 /* %icc, %sfp, %gsr */
4786 CC_MODES, 0, D_MODES
4789 static const int hard_64bit_mode_classes[] = {
4790 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4791 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4792 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4793 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4795 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4796 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4797 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4798 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4800 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4801 and none can hold SFmode/SImode values. */
4802 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4803 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4804 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4805 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4808 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4810 /* %icc, %sfp, %gsr */
4811 CC_MODES, 0, D_MODES
4814 int sparc_mode_class [NUM_MACHINE_MODES];
4816 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4819 sparc_init_modes (void)
4823 for (i = 0; i < NUM_MACHINE_MODES; i++)
4825 enum machine_mode m = (enum machine_mode) i;
4826 unsigned int size = GET_MODE_SIZE (m);
4828 switch (GET_MODE_CLASS (m))
4831 case MODE_PARTIAL_INT:
4832 case MODE_COMPLEX_INT:
4834 sparc_mode_class[i] = 1 << (int) H_MODE;
4836 sparc_mode_class[i] = 1 << (int) S_MODE;
4838 sparc_mode_class[i] = 1 << (int) D_MODE;
4839 else if (size == 16)
4840 sparc_mode_class[i] = 1 << (int) T_MODE;
4841 else if (size == 32)
4842 sparc_mode_class[i] = 1 << (int) O_MODE;
4844 sparc_mode_class[i] = 0;
4846 case MODE_VECTOR_INT:
4848 sparc_mode_class[i] = 1 << (int) SF_MODE;
4850 sparc_mode_class[i] = 1 << (int) DF_MODE;
4852 sparc_mode_class[i] = 0;
4855 case MODE_COMPLEX_FLOAT:
4857 sparc_mode_class[i] = 1 << (int) SF_MODE;
4859 sparc_mode_class[i] = 1 << (int) DF_MODE;
4860 else if (size == 16)
4861 sparc_mode_class[i] = 1 << (int) TF_MODE;
4862 else if (size == 32)
4863 sparc_mode_class[i] = 1 << (int) OF_MODE;
4865 sparc_mode_class[i] = 0;
4868 if (m == CCFPmode || m == CCFPEmode)
4869 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4871 sparc_mode_class[i] = 1 << (int) CC_MODE;
4874 sparc_mode_class[i] = 0;
4880 hard_regno_mode_classes = hard_64bit_mode_classes;
4882 hard_regno_mode_classes = hard_32bit_mode_classes;
4884 /* Initialize the array used by REGNO_REG_CLASS. */
4885 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4887 if (i < 16 && TARGET_V8PLUS)
4888 sparc_regno_reg_class[i] = I64_REGS;
4889 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4890 sparc_regno_reg_class[i] = GENERAL_REGS;
4892 sparc_regno_reg_class[i] = FP_REGS;
4894 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4896 sparc_regno_reg_class[i] = FPCC_REGS;
4898 sparc_regno_reg_class[i] = NO_REGS;
4902 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4905 save_global_or_fp_reg_p (unsigned int regno,
4906 int leaf_function ATTRIBUTE_UNUSED)
4908 return !call_used_regs[regno] && df_regs_ever_live_p (regno);
4911 /* Return whether the return address register (%i7) is needed. */
4914 return_addr_reg_needed_p (int leaf_function)
4916 /* If it is live, for example because of __builtin_return_address (0). */
4917 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM))
4920 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4922 /* Loading the GOT register clobbers %o7. */
4923 || crtl->uses_pic_offset_table
4924 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM))
4930 /* Return whether REGNO, a local or in register, must be saved/restored. */
4933 save_local_or_in_reg_p (unsigned int regno, int leaf_function)
4935 /* General case: call-saved registers live at some point. */
4936 if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
4939 /* Frame pointer register (%fp) if needed. */
4940 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
4943 /* Return address register (%i7) if needed. */
4944 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function))
4947 /* GOT register (%l7) if needed. */
4948 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
4951 /* If the function accesses prior frames, the frame pointer and the return
4952 address of the previous frame must be saved on the stack. */
4953 if (crtl->accesses_prior_frames
4954 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM))
4960 /* Compute the frame size required by the function. This function is called
4961 during the reload pass and also by sparc_expand_prologue. */
4964 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4966 HOST_WIDE_INT frame_size, apparent_frame_size;
4967 int args_size, n_global_fp_regs = 0;
4968 bool save_local_in_regs_p = false;
4971 /* If the function allocates dynamic stack space, the dynamic offset is
4972 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4973 if (leaf_function && !cfun->calls_alloca)
4976 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl);
4978 /* Calculate space needed for global registers. */
4980 for (i = 0; i < 8; i++)
4981 if (save_global_or_fp_reg_p (i, 0))
4982 n_global_fp_regs += 2;
4984 for (i = 0; i < 8; i += 2)
4985 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4986 n_global_fp_regs += 2;
4988 /* In the flat window model, find out which local and in registers need to
4989 be saved. We don't reserve space in the current frame for them as they
4990 will be spilled into the register window save area of the caller's frame.
4991 However, as soon as we use this register window save area, we must create
4992 that of the current frame to make it the live one. */
4994 for (i = 16; i < 32; i++)
4995 if (save_local_or_in_reg_p (i, leaf_function))
4997 save_local_in_regs_p = true;
5001 /* Calculate space needed for FP registers. */
5002 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
5003 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
5004 n_global_fp_regs += 2;
5007 && n_global_fp_regs == 0
5009 && !save_local_in_regs_p)
5010 frame_size = apparent_frame_size = 0;
5013 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5014 apparent_frame_size = (size - STARTING_FRAME_OFFSET + 7) & -8;
5015 apparent_frame_size += n_global_fp_regs * 4;
5017 /* We need to add the size of the outgoing argument area. */
5018 frame_size = apparent_frame_size + ((args_size + 7) & -8);
5020 /* And that of the register window save area. */
5021 frame_size += FIRST_PARM_OFFSET (cfun->decl);
5023 /* Finally, bump to the appropriate alignment. */
5024 frame_size = SPARC_STACK_ALIGN (frame_size);
5027 /* Set up values for use in prologue and epilogue. */
5028 sparc_frame_size = frame_size;
5029 sparc_apparent_frame_size = apparent_frame_size;
5030 sparc_n_global_fp_regs = n_global_fp_regs;
5031 sparc_save_local_in_regs_p = save_local_in_regs_p;
5036 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5039 sparc_initial_elimination_offset (int to)
5043 if (to == STACK_POINTER_REGNUM)
5044 offset = sparc_compute_frame_size (get_frame_size (), crtl->is_leaf);
5048 offset += SPARC_STACK_BIAS;
5052 /* Output any necessary .register pseudo-ops. */
5055 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
5057 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5063 /* Check if %g[2367] were used without
5064 .register being printed for them already. */
5065 for (i = 2; i < 8; i++)
5067 if (df_regs_ever_live_p (i)
5068 && ! sparc_hard_reg_printed [i])
5070 sparc_hard_reg_printed [i] = 1;
5071 /* %g7 is used as TLS base register, use #ignore
5072 for it instead of #scratch. */
5073 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
5074 i == 7 ? "ignore" : "scratch");
5081 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5083 #if PROBE_INTERVAL > 4096
5084 #error Cannot use indexed addressing mode for stack probing
5087 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5088 inclusive. These are offsets from the current stack pointer.
5090 Note that we don't use the REG+REG addressing mode for the probes because
5091 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5092 so the advantages of having a single code win here. */
5095 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
5097 rtx g1 = gen_rtx_REG (Pmode, 1);
5099 /* See if we have a constant small number of probes to generate. If so,
5100 that's the easy case. */
5101 if (size <= PROBE_INTERVAL)
5103 emit_move_insn (g1, GEN_INT (first));
5104 emit_insn (gen_rtx_SET (VOIDmode, g1,
5105 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
5106 emit_stack_probe (plus_constant (Pmode, g1, -size));
5109 /* The run-time loop is made up of 10 insns in the generic case while the
5110 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5111 else if (size <= 5 * PROBE_INTERVAL)
5115 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
5116 emit_insn (gen_rtx_SET (VOIDmode, g1,
5117 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
5118 emit_stack_probe (g1);
5120 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5121 it exceeds SIZE. If only two probes are needed, this will not
5122 generate any code. Then probe at FIRST + SIZE. */
5123 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
5125 emit_insn (gen_rtx_SET (VOIDmode, g1,
5126 plus_constant (Pmode, g1, -PROBE_INTERVAL)));
5127 emit_stack_probe (g1);
5130 emit_stack_probe (plus_constant (Pmode, g1,
5131 (i - PROBE_INTERVAL) - size));
5134 /* Otherwise, do the same as above, but in a loop. Note that we must be
5135 extra careful with variables wrapping around because we might be at
5136 the very top (or the very bottom) of the address space and we have
5137 to be able to handle this case properly; in particular, we use an
5138 equality test for the loop condition. */
5141 HOST_WIDE_INT rounded_size;
5142 rtx g4 = gen_rtx_REG (Pmode, 4);
5144 emit_move_insn (g1, GEN_INT (first));
5147 /* Step 1: round SIZE to the previous multiple of the interval. */
5149 rounded_size = size & -PROBE_INTERVAL;
5150 emit_move_insn (g4, GEN_INT (rounded_size));
5153 /* Step 2: compute initial and final value of the loop counter. */
5155 /* TEST_ADDR = SP + FIRST. */
5156 emit_insn (gen_rtx_SET (VOIDmode, g1,
5157 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
5159 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5160 emit_insn (gen_rtx_SET (VOIDmode, g4, gen_rtx_MINUS (Pmode, g1, g4)));
5165 while (TEST_ADDR != LAST_ADDR)
5167 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5171 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5172 until it is equal to ROUNDED_SIZE. */
5175 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
5177 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
5180 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5181 that SIZE is equal to ROUNDED_SIZE. */
5183 if (size != rounded_size)
5184 emit_stack_probe (plus_constant (Pmode, g4, rounded_size - size));
5187 /* Make sure nothing is scheduled before we are done. */
5188 emit_insn (gen_blockage ());
5191 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5192 absolute addresses. */
5195 output_probe_stack_range (rtx reg1, rtx reg2)
5197 static int labelno = 0;
5198 char loop_lab[32], end_lab[32];
5201 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
5202 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
5204 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
5206 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
5209 output_asm_insn ("cmp\t%0, %1", xops);
5211 fputs ("\tbe,pn\t%xcc,", asm_out_file);
5213 fputs ("\tbe\t", asm_out_file);
5214 assemble_name_raw (asm_out_file, end_lab);
5215 fputc ('\n', asm_out_file);
5217 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5218 xops[1] = GEN_INT (-PROBE_INTERVAL);
5219 output_asm_insn (" add\t%0, %1, %0", xops);
5221 /* Probe at TEST_ADDR and branch. */
5223 fputs ("\tba,pt\t%xcc,", asm_out_file);
5225 fputs ("\tba\t", asm_out_file);
5226 assemble_name_raw (asm_out_file, loop_lab);
5227 fputc ('\n', asm_out_file);
5228 xops[1] = GEN_INT (SPARC_STACK_BIAS);
5229 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
5231 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
5236 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5237 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5238 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5239 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5240 the action to be performed if it returns false. Return the new offset. */
5242 typedef bool (*sorr_pred_t) (unsigned int, int);
5243 typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t;
5246 emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base,
5247 int offset, int leaf_function, sorr_pred_t save_p,
5248 sorr_act_t action_true, sorr_act_t action_false)
5253 if (TARGET_ARCH64 && high <= 32)
5257 for (i = low; i < high; i++)
5259 if (save_p (i, leaf_function))
5261 mem = gen_frame_mem (DImode, plus_constant (Pmode,
5263 if (action_true == SORR_SAVE)
5265 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
5266 RTX_FRAME_RELATED_P (insn) = 1;
5268 else /* action_true == SORR_RESTORE */
5270 /* The frame pointer must be restored last since its old
5271 value may be used as base address for the frame. This
5272 is problematic in 64-bit mode only because of the lack
5273 of double-word load instruction. */
5274 if (i == HARD_FRAME_POINTER_REGNUM)
5277 emit_move_insn (gen_rtx_REG (DImode, i), mem);
5281 else if (action_false == SORR_ADVANCE)
5287 mem = gen_frame_mem (DImode, plus_constant (Pmode, base, fp_offset));
5288 emit_move_insn (hard_frame_pointer_rtx, mem);
5293 for (i = low; i < high; i += 2)
5295 bool reg0 = save_p (i, leaf_function);
5296 bool reg1 = save_p (i + 1, leaf_function);
5297 enum machine_mode mode;
5302 mode = SPARC_INT_REG_P (i) ? DImode : DFmode;
5307 mode = SPARC_INT_REG_P (i) ? SImode : SFmode;
5312 mode = SPARC_INT_REG_P (i) ? SImode : SFmode;
5318 if (action_false == SORR_ADVANCE)
5323 mem = gen_frame_mem (mode, plus_constant (Pmode, base, offset));
5324 if (action_true == SORR_SAVE)
5326 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
5327 RTX_FRAME_RELATED_P (insn) = 1;
5331 mem = gen_frame_mem (SImode, plus_constant (Pmode, base,
5333 set1 = gen_rtx_SET (VOIDmode, mem,
5334 gen_rtx_REG (SImode, regno));
5335 RTX_FRAME_RELATED_P (set1) = 1;
5337 = gen_frame_mem (SImode, plus_constant (Pmode, base,
5339 set2 = gen_rtx_SET (VOIDmode, mem,
5340 gen_rtx_REG (SImode, regno + 1));
5341 RTX_FRAME_RELATED_P (set2) = 1;
5342 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5343 gen_rtx_PARALLEL (VOIDmode,
5344 gen_rtvec (2, set1, set2)));
5347 else /* action_true == SORR_RESTORE */
5348 emit_move_insn (gen_rtx_REG (mode, regno), mem);
5350 /* Always preserve double-word alignment. */
5351 offset = (offset + 8) & -8;
5358 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5361 emit_adjust_base_to_offset (rtx base, int offset)
5363 /* ??? This might be optimized a little as %g1 might already have a
5364 value close enough that a single add insn will do. */
5365 /* ??? Although, all of this is probably only a temporary fix because
5366 if %g1 can hold a function result, then sparc_expand_epilogue will
5367 lose (the result will be clobbered). */
5368 rtx new_base = gen_rtx_REG (Pmode, 1);
5369 emit_move_insn (new_base, GEN_INT (offset));
5370 emit_insn (gen_rtx_SET (VOIDmode,
5371 new_base, gen_rtx_PLUS (Pmode, base, new_base)));
5375 /* Emit code to save/restore call-saved global and FP registers. */
5378 emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action)
5380 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095)
5382 base = emit_adjust_base_to_offset (base, offset);
5387 = emit_save_or_restore_regs (0, 8, base, offset, 0,
5388 save_global_or_fp_reg_p, action, SORR_NONE);
5389 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0,
5390 save_global_or_fp_reg_p, action, SORR_NONE);
5393 /* Emit code to save/restore call-saved local and in registers. */
5396 emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action)
5398 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095)
5400 base = emit_adjust_base_to_offset (base, offset);
5404 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p,
5405 save_local_or_in_reg_p, action, SORR_ADVANCE);
5408 /* Emit a window_save insn. */
5411 emit_window_save (rtx increment)
5413 rtx insn = emit_insn (gen_window_save (increment));
5414 RTX_FRAME_RELATED_P (insn) = 1;
5416 /* The incoming return address (%o7) is saved in %i7. */
5417 add_reg_note (insn, REG_CFA_REGISTER,
5418 gen_rtx_SET (VOIDmode,
5419 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM),
5421 INCOMING_RETURN_ADDR_REGNUM)));
5423 /* The window save event. */
5424 add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx);
5426 /* The CFA is %fp, the hard frame pointer. */
5427 add_reg_note (insn, REG_CFA_DEF_CFA,
5428 plus_constant (Pmode, hard_frame_pointer_rtx,
5429 INCOMING_FRAME_SP_OFFSET));
5434 /* Generate an increment for the stack pointer. */
5437 gen_stack_pointer_inc (rtx increment)
5439 return gen_rtx_SET (VOIDmode,
5441 gen_rtx_PLUS (Pmode,
5446 /* Expand the function prologue. The prologue is responsible for reserving
5447 storage for the frame, saving the call-saved registers and loading the
5448 GOT register if needed. */
5451 sparc_expand_prologue (void)
5456 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5457 on the final value of the flag means deferring the prologue/epilogue
5458 expansion until just before the second scheduling pass, which is too
5459 late to emit multiple epilogues or return insns.
5461 Of course we are making the assumption that the value of the flag
5462 will not change between now and its final value. Of the three parts
5463 of the formula, only the last one can reasonably vary. Let's take a
5464 closer look, after assuming that the first two ones are set to true
5465 (otherwise the last value is effectively silenced).
5467 If only_leaf_regs_used returns false, the global predicate will also
5468 be false so the actual frame size calculated below will be positive.
5469 As a consequence, the save_register_window insn will be emitted in
5470 the instruction stream; now this insn explicitly references %fp
5471 which is not a leaf register so only_leaf_regs_used will always
5472 return false subsequently.
5474 If only_leaf_regs_used returns true, we hope that the subsequent
5475 optimization passes won't cause non-leaf registers to pop up. For
5476 example, the regrename pass has special provisions to not rename to
5477 non-leaf registers in a leaf function. */
5478 sparc_leaf_function_p
5479 = optimize > 0 && crtl->is_leaf && only_leaf_regs_used ();
5481 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
5483 if (flag_stack_usage_info)
5484 current_function_static_stack_size = size;
5486 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
5488 if (crtl->is_leaf && !cfun->calls_alloca)
5490 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
5491 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT,
5492 size - STACK_CHECK_PROTECT);
5495 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
5500 else if (sparc_leaf_function_p)
5502 rtx size_int_rtx = GEN_INT (-size);
5505 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
5506 else if (size <= 8192)
5508 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5509 RTX_FRAME_RELATED_P (insn) = 1;
5511 /* %sp is still the CFA register. */
5512 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5516 rtx size_rtx = gen_rtx_REG (Pmode, 1);
5517 emit_move_insn (size_rtx, size_int_rtx);
5518 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
5519 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5520 gen_stack_pointer_inc (size_int_rtx));
5523 RTX_FRAME_RELATED_P (insn) = 1;
5527 rtx size_int_rtx = GEN_INT (-size);
5530 emit_window_save (size_int_rtx);
5531 else if (size <= 8192)
5533 emit_window_save (GEN_INT (-4096));
5535 /* %sp is not the CFA register anymore. */
5536 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5538 /* Make sure no %fp-based store is issued until after the frame is
5539 established. The offset between the frame pointer and the stack
5540 pointer is calculated relative to the value of the stack pointer
5541 at the end of the function prologue, and moving instructions that
5542 access the stack via the frame pointer between the instructions
5543 that decrement the stack pointer could result in accessing the
5544 register window save area, which is volatile. */
5545 emit_insn (gen_frame_blockage ());
5549 rtx size_rtx = gen_rtx_REG (Pmode, 1);
5550 emit_move_insn (size_rtx, size_int_rtx);
5551 emit_window_save (size_rtx);
5555 if (sparc_leaf_function_p)
5557 sparc_frame_base_reg = stack_pointer_rtx;
5558 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5562 sparc_frame_base_reg = hard_frame_pointer_rtx;
5563 sparc_frame_base_offset = SPARC_STACK_BIAS;
5566 if (sparc_n_global_fp_regs > 0)
5567 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5568 sparc_frame_base_offset
5569 - sparc_apparent_frame_size,
5572 /* Load the GOT register if needed. */
5573 if (crtl->uses_pic_offset_table)
5574 load_got_register ();
5576 /* Advertise that the data calculated just above are now valid. */
5577 sparc_prologue_data_valid_p = true;
5580 /* Expand the function prologue. The prologue is responsible for reserving
5581 storage for the frame, saving the call-saved registers and loading the
5582 GOT register if needed. */
5585 sparc_flat_expand_prologue (void)
5590 sparc_leaf_function_p = optimize > 0 && crtl->is_leaf;
5592 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
5594 if (flag_stack_usage_info)
5595 current_function_static_stack_size = size;
5597 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
5599 if (crtl->is_leaf && !cfun->calls_alloca)
5601 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
5602 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT,
5603 size - STACK_CHECK_PROTECT);
5606 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
5609 if (sparc_save_local_in_regs_p)
5610 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS,
5617 rtx size_int_rtx, size_rtx;
5619 size_rtx = size_int_rtx = GEN_INT (-size);
5621 /* We establish the frame (i.e. decrement the stack pointer) first, even
5622 if we use a frame pointer, because we cannot clobber any call-saved
5623 registers, including the frame pointer, if we haven't created a new
5624 register save area, for the sake of compatibility with the ABI. */
5626 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
5627 else if (size <= 8192 && !frame_pointer_needed)
5629 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5630 RTX_FRAME_RELATED_P (insn) = 1;
5631 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5635 size_rtx = gen_rtx_REG (Pmode, 1);
5636 emit_move_insn (size_rtx, size_int_rtx);
5637 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
5638 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5639 gen_stack_pointer_inc (size_int_rtx));
5641 RTX_FRAME_RELATED_P (insn) = 1;
5643 /* Ensure nothing is scheduled until after the frame is established. */
5644 emit_insn (gen_blockage ());
5646 if (frame_pointer_needed)
5648 insn = emit_insn (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5649 gen_rtx_MINUS (Pmode,
5652 RTX_FRAME_RELATED_P (insn) = 1;
5654 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5655 gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5656 plus_constant (Pmode, stack_pointer_rtx,
5660 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5662 rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM);
5663 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
5665 insn = emit_move_insn (i7, o7);
5666 RTX_FRAME_RELATED_P (insn) = 1;
5668 add_reg_note (insn, REG_CFA_REGISTER,
5669 gen_rtx_SET (VOIDmode, i7, o7));
5671 /* Prevent this instruction from ever being considered dead,
5672 even if this function has no epilogue. */
5677 if (frame_pointer_needed)
5679 sparc_frame_base_reg = hard_frame_pointer_rtx;
5680 sparc_frame_base_offset = SPARC_STACK_BIAS;
5684 sparc_frame_base_reg = stack_pointer_rtx;
5685 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5688 if (sparc_n_global_fp_regs > 0)
5689 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5690 sparc_frame_base_offset
5691 - sparc_apparent_frame_size,
5694 /* Load the GOT register if needed. */
5695 if (crtl->uses_pic_offset_table)
5696 load_got_register ();
5698 /* Advertise that the data calculated just above are now valid. */
5699 sparc_prologue_data_valid_p = true;
5702 /* This function generates the assembly code for function entry, which boils
5703 down to emitting the necessary .register directives. */
5706 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5708 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5710 gcc_assert (sparc_leaf_function_p == crtl->uses_only_leaf_regs);
5712 sparc_output_scratch_registers (file);
5715 /* Expand the function epilogue, either normal or part of a sibcall.
5716 We emit all the instructions except the return or the call. */
5719 sparc_expand_epilogue (bool for_eh)
5721 HOST_WIDE_INT size = sparc_frame_size;
5723 if (sparc_n_global_fp_regs > 0)
5724 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5725 sparc_frame_base_offset
5726 - sparc_apparent_frame_size,
5729 if (size == 0 || for_eh)
5731 else if (sparc_leaf_function_p)
5734 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
5735 else if (size <= 8192)
5737 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5738 emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096)));
5742 rtx reg = gen_rtx_REG (Pmode, 1);
5743 emit_move_insn (reg, GEN_INT (size));
5744 emit_insn (gen_stack_pointer_inc (reg));
5749 /* Expand the function epilogue, either normal or part of a sibcall.
5750 We emit all the instructions except the return or the call. */
5753 sparc_flat_expand_epilogue (bool for_eh)
5755 HOST_WIDE_INT size = sparc_frame_size;
5757 if (sparc_n_global_fp_regs > 0)
5758 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5759 sparc_frame_base_offset
5760 - sparc_apparent_frame_size,
5763 /* If we have a frame pointer, we'll need both to restore it before the
5764 frame is destroyed and use its current value in destroying the frame.
5765 Since we don't have an atomic way to do that in the flat window model,
5766 we save the current value into a temporary register (%g1). */
5767 if (frame_pointer_needed && !for_eh)
5768 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx);
5770 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5771 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM),
5772 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM));
5774 if (sparc_save_local_in_regs_p)
5775 emit_save_or_restore_local_in_regs (sparc_frame_base_reg,
5776 sparc_frame_base_offset,
5779 if (size == 0 || for_eh)
5781 else if (frame_pointer_needed)
5783 /* Make sure the frame is destroyed after everything else is done. */
5784 emit_insn (gen_blockage ());
5786 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1));
5791 emit_insn (gen_blockage ());
5794 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
5795 else if (size <= 8192)
5797 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5798 emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096)));
5802 rtx reg = gen_rtx_REG (Pmode, 1);
5803 emit_move_insn (reg, GEN_INT (size));
5804 emit_insn (gen_stack_pointer_inc (reg));
5809 /* Return true if it is appropriate to emit `return' instructions in the
5810 body of a function. */
5813 sparc_can_use_return_insn_p (void)
5815 return sparc_prologue_data_valid_p
5816 && sparc_n_global_fp_regs == 0
5818 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p)
5819 : (sparc_frame_size == 0 || !sparc_leaf_function_p);
5822 /* This function generates the assembly code for function exit. */
5825 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5827 /* If the last two instructions of a function are "call foo; dslot;"
5828 the return address might point to the first instruction in the next
5829 function and we have to output a dummy nop for the sake of sane
5830 backtraces in such cases. This is pointless for sibling calls since
5831 the return address is explicitly adjusted. */
5833 rtx insn, last_real_insn;
5835 insn = get_last_insn ();
5837 last_real_insn = prev_real_insn (insn);
5839 && NONJUMP_INSN_P (last_real_insn)
5840 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
5841 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
5844 && CALL_P (last_real_insn)
5845 && !SIBLING_CALL_P (last_real_insn))
5846 fputs("\tnop\n", file);
5848 sparc_output_deferred_case_vectors ();
5851 /* Output a 'restore' instruction. */
5854 output_restore (rtx pat)
5860 fputs ("\t restore\n", asm_out_file);
5864 gcc_assert (GET_CODE (pat) == SET);
5866 operands[0] = SET_DEST (pat);
5867 pat = SET_SRC (pat);
5869 switch (GET_CODE (pat))
5872 operands[1] = XEXP (pat, 0);
5873 operands[2] = XEXP (pat, 1);
5874 output_asm_insn (" restore %r1, %2, %Y0", operands);
5877 operands[1] = XEXP (pat, 0);
5878 operands[2] = XEXP (pat, 1);
5879 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
5882 operands[1] = XEXP (pat, 0);
5883 gcc_assert (XEXP (pat, 1) == const1_rtx);
5884 output_asm_insn (" restore %r1, %r1, %Y0", operands);
5888 output_asm_insn (" restore %%g0, %1, %Y0", operands);
5893 /* Output a return. */
5896 output_return (rtx insn)
5898 if (crtl->calls_eh_return)
5900 /* If the function uses __builtin_eh_return, the eh_return
5901 machinery occupies the delay slot. */
5902 gcc_assert (!final_sequence);
5904 if (flag_delayed_branch)
5906 if (!TARGET_FLAT && TARGET_V9)
5907 fputs ("\treturn\t%i7+8\n", asm_out_file);
5911 fputs ("\trestore\n", asm_out_file);
5913 fputs ("\tjmp\t%o7+8\n", asm_out_file);
5916 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
5921 fputs ("\trestore\n", asm_out_file);
5923 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file);
5924 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
5927 else if (sparc_leaf_function_p || TARGET_FLAT)
5929 /* This is a leaf or flat function so we don't have to bother restoring
5930 the register window, which frees us from dealing with the convoluted
5931 semantics of restore/return. We simply output the jump to the
5932 return address and the insn in the delay slot (if any). */
5934 return "jmp\t%%o7+%)%#";
5938 /* This is a regular function so we have to restore the register window.
5939 We may have a pending insn for the delay slot, which will be either
5940 combined with the 'restore' instruction or put in the delay slot of
5941 the 'return' instruction. */
5947 delay = NEXT_INSN (insn);
5950 pat = PATTERN (delay);
5952 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
5954 epilogue_renumber (&pat, 0);
5955 return "return\t%%i7+%)%#";
5959 output_asm_insn ("jmp\t%%i7+%)", NULL);
5960 output_restore (pat);
5961 PATTERN (delay) = gen_blockage ();
5962 INSN_CODE (delay) = -1;
5967 /* The delay slot is empty. */
5969 return "return\t%%i7+%)\n\t nop";
5970 else if (flag_delayed_branch)
5971 return "jmp\t%%i7+%)\n\t restore";
5973 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5980 /* Output a sibling call. */
5983 output_sibcall (rtx insn, rtx call_operand)
5987 gcc_assert (flag_delayed_branch);
5989 operands[0] = call_operand;
5991 if (sparc_leaf_function_p || TARGET_FLAT)
5993 /* This is a leaf or flat function so we don't have to bother restoring
5994 the register window. We simply output the jump to the function and
5995 the insn in the delay slot (if any). */
5997 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
6000 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6003 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6004 it into branch if possible. */
6005 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6010 /* This is a regular function so we have to restore the register window.
6011 We may have a pending insn for the delay slot, which will be combined
6012 with the 'restore' instruction. */
6014 output_asm_insn ("call\t%a0, 0", operands);
6018 rtx delay = NEXT_INSN (insn);
6021 output_restore (PATTERN (delay));
6023 PATTERN (delay) = gen_blockage ();
6024 INSN_CODE (delay) = -1;
6027 output_restore (NULL_RTX);
6033 /* Functions for handling argument passing.
6035 For 32-bit, the first 6 args are normally in registers and the rest are
6036 pushed. Any arg that starts within the first 6 words is at least
6037 partially passed in a register unless its data type forbids.
6039 For 64-bit, the argument registers are laid out as an array of 16 elements
6040 and arguments are added sequentially. The first 6 int args and up to the
6041 first 16 fp args (depending on size) are passed in regs.
6043 Slot Stack Integral Float Float in structure Double Long Double
6044 ---- ----- -------- ----- ------------------ ------ -----------
6045 15 [SP+248] %f31 %f30,%f31 %d30
6046 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6047 13 [SP+232] %f27 %f26,%f27 %d26
6048 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6049 11 [SP+216] %f23 %f22,%f23 %d22
6050 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6051 9 [SP+200] %f19 %f18,%f19 %d18
6052 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6053 7 [SP+184] %f15 %f14,%f15 %d14
6054 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6055 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6056 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6057 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6058 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6059 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6060 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6062 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6064 Integral arguments are always passed as 64-bit quantities appropriately
6067 Passing of floating point values is handled as follows.
6068 If a prototype is in scope:
6069 If the value is in a named argument (i.e. not a stdarg function or a
6070 value not part of the `...') then the value is passed in the appropriate
6072 If the value is part of the `...' and is passed in one of the first 6
6073 slots then the value is passed in the appropriate int reg.
6074 If the value is part of the `...' and is not passed in one of the first 6
6075 slots then the value is passed in memory.
6076 If a prototype is not in scope:
6077 If the value is one of the first 6 arguments the value is passed in the
6078 appropriate integer reg and the appropriate fp reg.
6079 If the value is not one of the first 6 arguments the value is passed in
6080 the appropriate fp reg and in memory.
6083 Summary of the calling conventions implemented by GCC on the SPARC:
6086 size argument return value
6088 small integer <4 int. reg. int. reg.
6089 word 4 int. reg. int. reg.
6090 double word 8 int. reg. int. reg.
6092 _Complex small integer <8 int. reg. int. reg.
6093 _Complex word 8 int. reg. int. reg.
6094 _Complex double word 16 memory int. reg.
6096 vector integer <=8 int. reg. FP reg.
6097 vector integer >8 memory memory
6099 float 4 int. reg. FP reg.
6100 double 8 int. reg. FP reg.
6101 long double 16 memory memory
6103 _Complex float 8 memory FP reg.
6104 _Complex double 16 memory FP reg.
6105 _Complex long double 32 memory FP reg.
6107 vector float any memory memory
6109 aggregate any memory memory
6114 size argument return value
6116 small integer <8 int. reg. int. reg.
6117 word 8 int. reg. int. reg.
6118 double word 16 int. reg. int. reg.
6120 _Complex small integer <16 int. reg. int. reg.
6121 _Complex word 16 int. reg. int. reg.
6122 _Complex double word 32 memory int. reg.
6124 vector integer <=16 FP reg. FP reg.
6125 vector integer 16<s<=32 memory FP reg.
6126 vector integer >32 memory memory
6128 float 4 FP reg. FP reg.
6129 double 8 FP reg. FP reg.
6130 long double 16 FP reg. FP reg.
6132 _Complex float 8 FP reg. FP reg.
6133 _Complex double 16 FP reg. FP reg.
6134 _Complex long double 32 memory FP reg.
6136 vector float <=16 FP reg. FP reg.
6137 vector float 16<s<=32 memory FP reg.
6138 vector float >32 memory memory
6140 aggregate <=16 reg. reg.
6141 aggregate 16<s<=32 memory reg.
6142 aggregate >32 memory memory
6146 Note #1: complex floating-point types follow the extended SPARC ABIs as
6147 implemented by the Sun compiler.
6149 Note #2: integral vector types follow the scalar floating-point types
6150 conventions to match what is implemented by the Sun VIS SDK.
6152 Note #3: floating-point vector types follow the aggregate types
6156 /* Maximum number of int regs for args. */
6157 #define SPARC_INT_ARG_MAX 6
6158 /* Maximum number of fp regs for args. */
6159 #define SPARC_FP_ARG_MAX 16
6161 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6163 /* Handle the INIT_CUMULATIVE_ARGS macro.
6164 Initialize a variable CUM of type CUMULATIVE_ARGS
6165 for a call to a function whose data type is FNTYPE.
6166 For a library call, FNTYPE is 0. */
6169 init_cumulative_args (struct sparc_args *cum, tree fntype,
6170 rtx libname ATTRIBUTE_UNUSED,
6171 tree fndecl ATTRIBUTE_UNUSED)
6174 cum->prototype_p = fntype && prototype_p (fntype);
6175 cum->libcall_p = fntype == 0;
6178 /* Handle promotion of pointer and integer arguments. */
6180 static enum machine_mode
6181 sparc_promote_function_mode (const_tree type,
6182 enum machine_mode mode,
6184 const_tree fntype ATTRIBUTE_UNUSED,
6185 int for_return ATTRIBUTE_UNUSED)
6187 if (type != NULL_TREE && POINTER_TYPE_P (type))
6189 *punsignedp = POINTERS_EXTEND_UNSIGNED;
6193 /* Integral arguments are passed as full words, as per the ABI. */
6194 if (GET_MODE_CLASS (mode) == MODE_INT
6195 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6201 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6204 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
6206 return TARGET_ARCH64 ? true : false;
6209 /* Scan the record type TYPE and return the following predicates:
6210 - INTREGS_P: the record contains at least one field or sub-field
6211 that is eligible for promotion in integer registers.
6212 - FP_REGS_P: the record contains at least one field or sub-field
6213 that is eligible for promotion in floating-point registers.
6214 - PACKED_P: the record contains at least one field that is packed.
6216 Sub-fields are not taken into account for the PACKED_P predicate. */
6219 scan_record_type (const_tree type, int *intregs_p, int *fpregs_p,
6224 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6226 if (TREE_CODE (field) == FIELD_DECL)
6228 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
6229 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
6230 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
6231 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
6237 if (packed_p && DECL_PACKED (field))
6243 /* Compute the slot number to pass an argument in.
6244 Return the slot number or -1 if passing on the stack.
6246 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6247 the preceding args and about the function being called.
6248 MODE is the argument's machine mode.
6249 TYPE is the data type of the argument (as a tree).
6250 This is null for libcalls where that information may
6252 NAMED is nonzero if this argument is a named parameter
6253 (otherwise it is an extra parameter matching an ellipsis).
6254 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6255 *PREGNO records the register number to use if scalar type.
6256 *PPADDING records the amount of padding needed in words. */
6259 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
6260 const_tree type, bool named, bool incoming_p,
6261 int *pregno, int *ppadding)
6263 int regbase = (incoming_p
6264 ? SPARC_INCOMING_INT_ARG_FIRST
6265 : SPARC_OUTGOING_INT_ARG_FIRST);
6266 int slotno = cum->words;
6267 enum mode_class mclass;
6272 if (type && TREE_ADDRESSABLE (type))
6278 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
6281 /* For SPARC64, objects requiring 16-byte alignment get it. */
6283 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
6284 && (slotno & 1) != 0)
6285 slotno++, *ppadding = 1;
6287 mclass = GET_MODE_CLASS (mode);
6288 if (type && TREE_CODE (type) == VECTOR_TYPE)
6290 /* Vector types deserve special treatment because they are
6291 polymorphic wrt their mode, depending upon whether VIS
6292 instructions are enabled. */
6293 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
6295 /* The SPARC port defines no floating-point vector modes. */
6296 gcc_assert (mode == BLKmode);
6300 /* Integral vector types should either have a vector
6301 mode or an integral mode, because we are guaranteed
6302 by pass_by_reference that their size is not greater
6303 than 16 bytes and TImode is 16-byte wide. */
6304 gcc_assert (mode != BLKmode);
6306 /* Vector integers are handled like floats according to
6308 mclass = MODE_FLOAT;
6315 case MODE_COMPLEX_FLOAT:
6316 case MODE_VECTOR_INT:
6317 if (TARGET_ARCH64 && TARGET_FPU && named)
6319 if (slotno >= SPARC_FP_ARG_MAX)
6321 regno = SPARC_FP_ARG_FIRST + slotno * 2;
6322 /* Arguments filling only one single FP register are
6323 right-justified in the outer double FP register. */
6324 if (GET_MODE_SIZE (mode) <= 4)
6331 case MODE_COMPLEX_INT:
6332 if (slotno >= SPARC_INT_ARG_MAX)
6334 regno = regbase + slotno;
6338 if (mode == VOIDmode)
6339 /* MODE is VOIDmode when generating the actual call. */
6342 gcc_assert (mode == BLKmode);
6346 || (TREE_CODE (type) != VECTOR_TYPE
6347 && TREE_CODE (type) != RECORD_TYPE))
6349 if (slotno >= SPARC_INT_ARG_MAX)
6351 regno = regbase + slotno;
6353 else /* TARGET_ARCH64 && type */
6355 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
6357 /* First see what kinds of registers we would need. */
6358 if (TREE_CODE (type) == VECTOR_TYPE)
6361 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
6363 /* The ABI obviously doesn't specify how packed structures
6364 are passed. These are defined to be passed in int regs
6365 if possible, otherwise memory. */
6366 if (packed_p || !named)
6367 fpregs_p = 0, intregs_p = 1;
6369 /* If all arg slots are filled, then must pass on stack. */
6370 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
6373 /* If there are only int args and all int arg slots are filled,
6374 then must pass on stack. */
6375 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
6378 /* Note that even if all int arg slots are filled, fp members may
6379 still be passed in regs if such regs are available.
6380 *PREGNO isn't set because there may be more than one, it's up
6381 to the caller to compute them. */
6394 /* Handle recursive register counting for structure field layout. */
6396 struct function_arg_record_value_parms
6398 rtx ret; /* return expression being built. */
6399 int slotno; /* slot number of the argument. */
6400 int named; /* whether the argument is named. */
6401 int regbase; /* regno of the base register. */
6402 int stack; /* 1 if part of the argument is on the stack. */
6403 int intoffset; /* offset of the first pending integer field. */
6404 unsigned int nregs; /* number of words passed in registers. */
6407 static void function_arg_record_value_3
6408 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
6409 static void function_arg_record_value_2
6410 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
6411 static void function_arg_record_value_1
6412 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
6413 static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
6414 static rtx function_arg_union_value (int, enum machine_mode, int, int);
6416 /* A subroutine of function_arg_record_value. Traverse the structure
6417 recursively and determine how many registers will be required. */
6420 function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
6421 struct function_arg_record_value_parms *parms,
6426 /* We need to compute how many registers are needed so we can
6427 allocate the PARALLEL but before we can do that we need to know
6428 whether there are any packed fields. The ABI obviously doesn't
6429 specify how structures are passed in this case, so they are
6430 defined to be passed in int regs if possible, otherwise memory,
6431 regardless of whether there are fp values present. */
6434 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6436 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
6443 /* Compute how many registers we need. */
6444 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6446 if (TREE_CODE (field) == FIELD_DECL)
6448 HOST_WIDE_INT bitpos = startbitpos;
6450 if (DECL_SIZE (field) != 0)
6452 if (integer_zerop (DECL_SIZE (field)))
6455 if (tree_fits_uhwi_p (bit_position (field)))
6456 bitpos += int_bit_position (field);
6459 /* ??? FIXME: else assume zero offset. */
6461 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
6462 function_arg_record_value_1 (TREE_TYPE (field),
6466 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
6467 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
6472 if (parms->intoffset != -1)
6474 unsigned int startbit, endbit;
6475 int intslots, this_slotno;
6477 startbit = parms->intoffset & -BITS_PER_WORD;
6478 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
6480 intslots = (endbit - startbit) / BITS_PER_WORD;
6481 this_slotno = parms->slotno + parms->intoffset
6484 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
6486 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
6487 /* We need to pass this field on the stack. */
6491 parms->nregs += intslots;
6492 parms->intoffset = -1;
6495 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
6496 If it wasn't true we wouldn't be here. */
6497 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
6498 && DECL_MODE (field) == BLKmode)
6499 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
6500 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
6507 if (parms->intoffset == -1)
6508 parms->intoffset = bitpos;
6514 /* A subroutine of function_arg_record_value. Assign the bits of the
6515 structure between parms->intoffset and bitpos to integer registers. */
6518 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
6519 struct function_arg_record_value_parms *parms)
6521 enum machine_mode mode;
6523 unsigned int startbit, endbit;
6524 int this_slotno, intslots, intoffset;
6527 if (parms->intoffset == -1)
6530 intoffset = parms->intoffset;
6531 parms->intoffset = -1;
6533 startbit = intoffset & -BITS_PER_WORD;
6534 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
6535 intslots = (endbit - startbit) / BITS_PER_WORD;
6536 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
6538 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
6542 /* If this is the trailing part of a word, only load that much into
6543 the register. Otherwise load the whole register. Note that in
6544 the latter case we may pick up unwanted bits. It's not a problem
6545 at the moment but may wish to revisit. */
6547 if (intoffset % BITS_PER_WORD != 0)
6548 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
6553 intoffset /= BITS_PER_UNIT;
6556 regno = parms->regbase + this_slotno;
6557 reg = gen_rtx_REG (mode, regno);
6558 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6559 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
6562 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
6567 while (intslots > 0);
6570 /* A subroutine of function_arg_record_value. Traverse the structure
6571 recursively and assign bits to floating point registers. Track which
6572 bits in between need integer registers; invoke function_arg_record_value_3
6573 to make that happen. */
6576 function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
6577 struct function_arg_record_value_parms *parms,
6583 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6585 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
6592 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6594 if (TREE_CODE (field) == FIELD_DECL)
6596 HOST_WIDE_INT bitpos = startbitpos;
6598 if (DECL_SIZE (field) != 0)
6600 if (integer_zerop (DECL_SIZE (field)))
6603 if (tree_fits_uhwi_p (bit_position (field)))
6604 bitpos += int_bit_position (field);
6607 /* ??? FIXME: else assume zero offset. */
6609 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
6610 function_arg_record_value_2 (TREE_TYPE (field),
6614 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
6615 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
6620 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
6621 int regno, nregs, pos;
6622 enum machine_mode mode = DECL_MODE (field);
6625 function_arg_record_value_3 (bitpos, parms);
6627 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
6630 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6631 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
6633 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
6635 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6641 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
6642 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
6644 reg = gen_rtx_REG (mode, regno);
6645 pos = bitpos / BITS_PER_UNIT;
6646 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6647 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6651 regno += GET_MODE_SIZE (mode) / 4;
6652 reg = gen_rtx_REG (mode, regno);
6653 pos += GET_MODE_SIZE (mode);
6654 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6655 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6661 if (parms->intoffset == -1)
6662 parms->intoffset = bitpos;
6668 /* Used by function_arg and sparc_function_value_1 to implement the complex
6669 conventions of the 64-bit ABI for passing and returning structures.
6670 Return an expression valid as a return value for the FUNCTION_ARG
6671 and TARGET_FUNCTION_VALUE.
6673 TYPE is the data type of the argument (as a tree).
6674 This is null for libcalls where that information may
6676 MODE is the argument's machine mode.
6677 SLOTNO is the index number of the argument's slot in the parameter array.
6678 NAMED is nonzero if this argument is a named parameter
6679 (otherwise it is an extra parameter matching an ellipsis).
6680 REGBASE is the regno of the base register for the parameter array. */
6683 function_arg_record_value (const_tree type, enum machine_mode mode,
6684 int slotno, int named, int regbase)
6686 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6687 struct function_arg_record_value_parms parms;
6690 parms.ret = NULL_RTX;
6691 parms.slotno = slotno;
6692 parms.named = named;
6693 parms.regbase = regbase;
6696 /* Compute how many registers we need. */
6698 parms.intoffset = 0;
6699 function_arg_record_value_1 (type, 0, &parms, false);
6701 /* Take into account pending integer fields. */
6702 if (parms.intoffset != -1)
6704 unsigned int startbit, endbit;
6705 int intslots, this_slotno;
6707 startbit = parms.intoffset & -BITS_PER_WORD;
6708 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
6709 intslots = (endbit - startbit) / BITS_PER_WORD;
6710 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
6712 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
6714 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
6715 /* We need to pass this field on the stack. */
6719 parms.nregs += intslots;
6721 nregs = parms.nregs;
6723 /* Allocate the vector and handle some annoying special cases. */
6726 /* ??? Empty structure has no value? Duh? */
6729 /* Though there's nothing really to store, return a word register
6730 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6731 leads to breakage due to the fact that there are zero bytes to
6733 return gen_rtx_REG (mode, regbase);
6737 /* ??? C++ has structures with no fields, and yet a size. Give up
6738 for now and pass everything back in integer registers. */
6739 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6741 if (nregs + slotno > SPARC_INT_ARG_MAX)
6742 nregs = SPARC_INT_ARG_MAX - slotno;
6744 gcc_assert (nregs != 0);
6746 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
6748 /* If at least one field must be passed on the stack, generate
6749 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6750 also be passed on the stack. We can't do much better because the
6751 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6752 of structures for which the fields passed exclusively in registers
6753 are not at the beginning of the structure. */
6755 XVECEXP (parms.ret, 0, 0)
6756 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6758 /* Fill in the entries. */
6760 parms.intoffset = 0;
6761 function_arg_record_value_2 (type, 0, &parms, false);
6762 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
6764 gcc_assert (parms.nregs == nregs);
6769 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6770 of the 64-bit ABI for passing and returning unions.
6771 Return an expression valid as a return value for the FUNCTION_ARG
6772 and TARGET_FUNCTION_VALUE.
6774 SIZE is the size in bytes of the union.
6775 MODE is the argument's machine mode.
6776 REGNO is the hard register the union will be passed in. */
6779 function_arg_union_value (int size, enum machine_mode mode, int slotno,
6782 int nwords = ROUND_ADVANCE (size), i;
6785 /* See comment in previous function for empty structures. */
6787 return gen_rtx_REG (mode, regno);
6789 if (slotno == SPARC_INT_ARG_MAX - 1)
6792 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
6794 for (i = 0; i < nwords; i++)
6796 /* Unions are passed left-justified. */
6797 XVECEXP (regs, 0, i)
6798 = gen_rtx_EXPR_LIST (VOIDmode,
6799 gen_rtx_REG (word_mode, regno),
6800 GEN_INT (UNITS_PER_WORD * i));
6807 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6808 for passing and returning large (BLKmode) vectors.
6809 Return an expression valid as a return value for the FUNCTION_ARG
6810 and TARGET_FUNCTION_VALUE.
6812 SIZE is the size in bytes of the vector (at least 8 bytes).
6813 REGNO is the FP hard register the vector will be passed in. */
6816 function_arg_vector_value (int size, int regno)
6818 int i, nregs = size / 8;
6821 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
6823 for (i = 0; i < nregs; i++)
6825 XVECEXP (regs, 0, i)
6826 = gen_rtx_EXPR_LIST (VOIDmode,
6827 gen_rtx_REG (DImode, regno + 2*i),
6834 /* Determine where to put an argument to a function.
6835 Value is zero to push the argument on the stack,
6836 or a hard register in which to store the argument.
6838 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6839 the preceding args and about the function being called.
6840 MODE is the argument's machine mode.
6841 TYPE is the data type of the argument (as a tree).
6842 This is null for libcalls where that information may
6844 NAMED is true if this argument is a named parameter
6845 (otherwise it is an extra parameter matching an ellipsis).
6846 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6847 TARGET_FUNCTION_INCOMING_ARG. */
6850 sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
6851 const_tree type, bool named, bool incoming_p)
6853 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6855 int regbase = (incoming_p
6856 ? SPARC_INCOMING_INT_ARG_FIRST
6857 : SPARC_OUTGOING_INT_ARG_FIRST);
6858 int slotno, regno, padding;
6859 enum mode_class mclass = GET_MODE_CLASS (mode);
6861 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
6866 /* Vector types deserve special treatment because they are polymorphic wrt
6867 their mode, depending upon whether VIS instructions are enabled. */
6868 if (type && TREE_CODE (type) == VECTOR_TYPE)
6870 HOST_WIDE_INT size = int_size_in_bytes (type);
6871 gcc_assert ((TARGET_ARCH32 && size <= 8)
6872 || (TARGET_ARCH64 && size <= 16));
6874 if (mode == BLKmode)
6875 return function_arg_vector_value (size,
6876 SPARC_FP_ARG_FIRST + 2*slotno);
6878 mclass = MODE_FLOAT;
6882 return gen_rtx_REG (mode, regno);
6884 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6885 and are promoted to registers if possible. */
6886 if (type && TREE_CODE (type) == RECORD_TYPE)
6888 HOST_WIDE_INT size = int_size_in_bytes (type);
6889 gcc_assert (size <= 16);
6891 return function_arg_record_value (type, mode, slotno, named, regbase);
6894 /* Unions up to 16 bytes in size are passed in integer registers. */
6895 else if (type && TREE_CODE (type) == UNION_TYPE)
6897 HOST_WIDE_INT size = int_size_in_bytes (type);
6898 gcc_assert (size <= 16);
6900 return function_arg_union_value (size, mode, slotno, regno);
6903 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6904 but also have the slot allocated for them.
6905 If no prototype is in scope fp values in register slots get passed
6906 in two places, either fp regs and int regs or fp regs and memory. */
6907 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6908 && SPARC_FP_REG_P (regno))
6910 rtx reg = gen_rtx_REG (mode, regno);
6911 if (cum->prototype_p || cum->libcall_p)
6913 /* "* 2" because fp reg numbers are recorded in 4 byte
6916 /* ??? This will cause the value to be passed in the fp reg and
6917 in the stack. When a prototype exists we want to pass the
6918 value in the reg but reserve space on the stack. That's an
6919 optimization, and is deferred [for a bit]. */
6920 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
6921 return gen_rtx_PARALLEL (mode,
6923 gen_rtx_EXPR_LIST (VOIDmode,
6924 NULL_RTX, const0_rtx),
6925 gen_rtx_EXPR_LIST (VOIDmode,
6929 /* ??? It seems that passing back a register even when past
6930 the area declared by REG_PARM_STACK_SPACE will allocate
6931 space appropriately, and will not copy the data onto the
6932 stack, exactly as we desire.
6934 This is due to locate_and_pad_parm being called in
6935 expand_call whenever reg_parm_stack_space > 0, which
6936 while beneficial to our example here, would seem to be
6937 in error from what had been intended. Ho hum... -- r~ */
6945 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
6949 /* On incoming, we don't need to know that the value
6950 is passed in %f0 and %i0, and it confuses other parts
6951 causing needless spillage even on the simplest cases. */
6955 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
6956 + (regno - SPARC_FP_ARG_FIRST) / 2);
6958 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6959 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
6961 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6965 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6966 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6967 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6972 /* All other aggregate types are passed in an integer register in a mode
6973 corresponding to the size of the type. */
6974 else if (type && AGGREGATE_TYPE_P (type))
6976 HOST_WIDE_INT size = int_size_in_bytes (type);
6977 gcc_assert (size <= 16);
6979 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6982 return gen_rtx_REG (mode, regno);
6985 /* Handle the TARGET_FUNCTION_ARG target hook. */
6988 sparc_function_arg (cumulative_args_t cum, enum machine_mode mode,
6989 const_tree type, bool named)
6991 return sparc_function_arg_1 (cum, mode, type, named, false);
6994 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6997 sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
6998 const_tree type, bool named)
7000 return sparc_function_arg_1 (cum, mode, type, named, true);
7003 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7006 sparc_function_arg_boundary (enum machine_mode mode, const_tree type)
7008 return ((TARGET_ARCH64
7009 && (GET_MODE_ALIGNMENT (mode) == 128
7010 || (type && TYPE_ALIGN (type) == 128)))
7015 /* For an arg passed partly in registers and partly in memory,
7016 this is the number of bytes of registers used.
7017 For args passed entirely in registers or entirely in memory, zero.
7019 Any arg that starts in the first 6 regs but won't entirely fit in them
7020 needs partial registers on v8. On v9, structures with integer
7021 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7022 values that begin in the last fp reg [where "last fp reg" varies with the
7023 mode] will be split between that reg and memory. */
7026 sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode,
7027 tree type, bool named)
7029 int slotno, regno, padding;
7031 /* We pass false for incoming_p here, it doesn't matter. */
7032 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
7033 false, ®no, &padding);
7040 if ((slotno + (mode == BLKmode
7041 ? ROUND_ADVANCE (int_size_in_bytes (type))
7042 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
7043 > SPARC_INT_ARG_MAX)
7044 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
7048 /* We are guaranteed by pass_by_reference that the size of the
7049 argument is not greater than 16 bytes, so we only need to return
7050 one word if the argument is partially passed in registers. */
7052 if (type && AGGREGATE_TYPE_P (type))
7054 int size = int_size_in_bytes (type);
7056 if (size > UNITS_PER_WORD
7057 && slotno == SPARC_INT_ARG_MAX - 1)
7058 return UNITS_PER_WORD;
7060 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
7061 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7062 && ! (TARGET_FPU && named)))
7064 /* The complex types are passed as packed types. */
7065 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
7066 && slotno == SPARC_INT_ARG_MAX - 1)
7067 return UNITS_PER_WORD;
7069 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7071 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
7073 return UNITS_PER_WORD;
7080 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7081 Specify whether to pass the argument by reference. */
7084 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
7085 enum machine_mode mode, const_tree type,
7086 bool named ATTRIBUTE_UNUSED)
7089 /* Original SPARC 32-bit ABI says that structures and unions,
7090 and quad-precision floats are passed by reference. For Pascal,
7091 also pass arrays by reference. All other base types are passed
7094 Extended ABI (as implemented by the Sun compiler) says that all
7095 complex floats are passed by reference. Pass complex integers
7096 in registers up to 8 bytes. More generally, enforce the 2-word
7097 cap for passing arguments in registers.
7099 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7100 integers are passed like floats of the same size, that is in
7101 registers up to 8 bytes. Pass all vector floats by reference
7102 like structure and unions. */
7103 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
7105 /* Catch CDImode, TFmode, DCmode and TCmode. */
7106 || GET_MODE_SIZE (mode) > 8
7108 && TREE_CODE (type) == VECTOR_TYPE
7109 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
7111 /* Original SPARC 64-bit ABI says that structures and unions
7112 smaller than 16 bytes are passed in registers, as well as
7113 all other base types.
7115 Extended ABI (as implemented by the Sun compiler) says that
7116 complex floats are passed in registers up to 16 bytes. Pass
7117 all complex integers in registers up to 16 bytes. More generally,
7118 enforce the 2-word cap for passing arguments in registers.
7120 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7121 integers are passed like floats of the same size, that is in
7122 registers (up to 16 bytes). Pass all vector floats like structure
7125 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
7126 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
7127 /* Catch CTImode and TCmode. */
7128 || GET_MODE_SIZE (mode) > 16);
7131 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7132 Update the data in CUM to advance over an argument
7133 of mode MODE and data type TYPE.
7134 TYPE is null for libcalls where that information may not be available. */
7137 sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
7138 const_tree type, bool named)
7140 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7143 /* We pass false for incoming_p here, it doesn't matter. */
7144 function_arg_slotno (cum, mode, type, named, false, ®no, &padding);
7146 /* If argument requires leading padding, add it. */
7147 cum->words += padding;
7151 cum->words += (mode != BLKmode
7152 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7153 : ROUND_ADVANCE (int_size_in_bytes (type)));
7157 if (type && AGGREGATE_TYPE_P (type))
7159 int size = int_size_in_bytes (type);
7163 else if (size <= 16)
7165 else /* passed by reference */
7170 cum->words += (mode != BLKmode
7171 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7172 : ROUND_ADVANCE (int_size_in_bytes (type)));
7177 /* Handle the FUNCTION_ARG_PADDING macro.
7178 For the 64 bit ABI structs are always stored left shifted in their
7182 function_arg_padding (enum machine_mode mode, const_tree type)
7184 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
7187 /* Fall back to the default. */
7188 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7191 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7192 Specify whether to return the return value in memory. */
7195 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7198 /* Original SPARC 32-bit ABI says that structures and unions,
7199 and quad-precision floats are returned in memory. All other
7200 base types are returned in registers.
7202 Extended ABI (as implemented by the Sun compiler) says that
7203 all complex floats are returned in registers (8 FP registers
7204 at most for '_Complex long double'). Return all complex integers
7205 in registers (4 at most for '_Complex long long').
7207 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7208 integers are returned like floats of the same size, that is in
7209 registers up to 8 bytes and in memory otherwise. Return all
7210 vector floats in memory like structure and unions; note that
7211 they always have BLKmode like the latter. */
7212 return (TYPE_MODE (type) == BLKmode
7213 || TYPE_MODE (type) == TFmode
7214 || (TREE_CODE (type) == VECTOR_TYPE
7215 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
7217 /* Original SPARC 64-bit ABI says that structures and unions
7218 smaller than 32 bytes are returned in registers, as well as
7219 all other base types.
7221 Extended ABI (as implemented by the Sun compiler) says that all
7222 complex floats are returned in registers (8 FP registers at most
7223 for '_Complex long double'). Return all complex integers in
7224 registers (4 at most for '_Complex TItype').
7226 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7227 integers are returned like floats of the same size, that is in
7228 registers. Return all vector floats like structure and unions;
7229 note that they always have BLKmode like the latter. */
7230 return (TYPE_MODE (type) == BLKmode
7231 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
7234 /* Handle the TARGET_STRUCT_VALUE target hook.
7235 Return where to find the structure return value address. */
7238 sparc_struct_value_rtx (tree fndecl, int incoming)
7247 mem = gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx,
7248 STRUCT_VALUE_OFFSET));
7250 mem = gen_frame_mem (Pmode, plus_constant (Pmode, stack_pointer_rtx,
7251 STRUCT_VALUE_OFFSET));
7253 /* Only follow the SPARC ABI for fixed-size structure returns.
7254 Variable size structure returns are handled per the normal
7255 procedures in GCC. This is enabled by -mstd-struct-return */
7257 && sparc_std_struct_return
7258 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
7259 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
7261 /* We must check and adjust the return address, as it is
7262 optional as to whether the return object is really
7264 rtx ret_reg = gen_rtx_REG (Pmode, 31);
7265 rtx scratch = gen_reg_rtx (SImode);
7266 rtx endlab = gen_label_rtx ();
7268 /* Calculate the return object size */
7269 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
7270 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
7271 /* Construct a temporary return value */
7273 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
7275 /* Implement SPARC 32-bit psABI callee return struct checking:
7277 Fetch the instruction where we will return to and see if
7278 it's an unimp instruction (the most significant 10 bits
7280 emit_move_insn (scratch, gen_rtx_MEM (SImode,
7281 plus_constant (Pmode,
7283 /* Assume the size is valid and pre-adjust */
7284 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4)));
7285 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
7287 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4)));
7288 /* Write the address of the memory pointed to by temp_val into
7289 the memory pointed to by mem */
7290 emit_move_insn (mem, XEXP (temp_val, 0));
7291 emit_label (endlab);
7298 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7299 For v9, function return values are subject to the same rules as arguments,
7300 except that up to 32 bytes may be returned in registers. */
7303 sparc_function_value_1 (const_tree type, enum machine_mode mode,
7306 /* Beware that the two values are swapped here wrt function_arg. */
7307 int regbase = (outgoing
7308 ? SPARC_INCOMING_INT_ARG_FIRST
7309 : SPARC_OUTGOING_INT_ARG_FIRST);
7310 enum mode_class mclass = GET_MODE_CLASS (mode);
7313 /* Vector types deserve special treatment because they are polymorphic wrt
7314 their mode, depending upon whether VIS instructions are enabled. */
7315 if (type && TREE_CODE (type) == VECTOR_TYPE)
7317 HOST_WIDE_INT size = int_size_in_bytes (type);
7318 gcc_assert ((TARGET_ARCH32 && size <= 8)
7319 || (TARGET_ARCH64 && size <= 32));
7321 if (mode == BLKmode)
7322 return function_arg_vector_value (size,
7323 SPARC_FP_ARG_FIRST);
7325 mclass = MODE_FLOAT;
7328 if (TARGET_ARCH64 && type)
7330 /* Structures up to 32 bytes in size are returned in registers. */
7331 if (TREE_CODE (type) == RECORD_TYPE)
7333 HOST_WIDE_INT size = int_size_in_bytes (type);
7334 gcc_assert (size <= 32);
7336 return function_arg_record_value (type, mode, 0, 1, regbase);
7339 /* Unions up to 32 bytes in size are returned in integer registers. */
7340 else if (TREE_CODE (type) == UNION_TYPE)
7342 HOST_WIDE_INT size = int_size_in_bytes (type);
7343 gcc_assert (size <= 32);
7345 return function_arg_union_value (size, mode, 0, regbase);
7348 /* Objects that require it are returned in FP registers. */
7349 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7352 /* All other aggregate types are returned in an integer register in a
7353 mode corresponding to the size of the type. */
7354 else if (AGGREGATE_TYPE_P (type))
7356 /* All other aggregate types are passed in an integer register
7357 in a mode corresponding to the size of the type. */
7358 HOST_WIDE_INT size = int_size_in_bytes (type);
7359 gcc_assert (size <= 32);
7361 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7363 /* ??? We probably should have made the same ABI change in
7364 3.4.0 as the one we made for unions. The latter was
7365 required by the SCD though, while the former is not
7366 specified, so we favored compatibility and efficiency.
7368 Now we're stuck for aggregates larger than 16 bytes,
7369 because OImode vanished in the meantime. Let's not
7370 try to be unduly clever, and simply follow the ABI
7371 for unions in that case. */
7372 if (mode == BLKmode)
7373 return function_arg_union_value (size, mode, 0, regbase);
7378 /* We should only have pointer and integer types at this point. This
7379 must match sparc_promote_function_mode. */
7380 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
7384 /* We should only have pointer and integer types at this point. This must
7385 match sparc_promote_function_mode. */
7386 else if (TARGET_ARCH32
7387 && mclass == MODE_INT
7388 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
7391 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
7392 regno = SPARC_FP_ARG_FIRST;
7396 return gen_rtx_REG (mode, regno);
7399 /* Handle TARGET_FUNCTION_VALUE.
7400 On the SPARC, the value is found in the first "output" register, but the
7401 called function leaves it in the first "input" register. */
7404 sparc_function_value (const_tree valtype,
7405 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
7408 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
7411 /* Handle TARGET_LIBCALL_VALUE. */
7414 sparc_libcall_value (enum machine_mode mode,
7415 const_rtx fun ATTRIBUTE_UNUSED)
7417 return sparc_function_value_1 (NULL_TREE, mode, false);
7420 /* Handle FUNCTION_VALUE_REGNO_P.
7421 On the SPARC, the first "output" reg is used for integer values, and the
7422 first floating point register is used for floating point values. */
7425 sparc_function_value_regno_p (const unsigned int regno)
7427 return (regno == 8 || regno == 32);
7430 /* Do what is necessary for `va_start'. We look at the current function
7431 to determine if stdarg or varargs is used and return the address of
7432 the first unnamed parameter. */
7435 sparc_builtin_saveregs (void)
7437 int first_reg = crtl->args.info.words;
7441 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
7442 emit_move_insn (gen_rtx_MEM (word_mode,
7443 gen_rtx_PLUS (Pmode,
7445 GEN_INT (FIRST_PARM_OFFSET (0)
7448 gen_rtx_REG (word_mode,
7449 SPARC_INCOMING_INT_ARG_FIRST + regno));
7451 address = gen_rtx_PLUS (Pmode,
7453 GEN_INT (FIRST_PARM_OFFSET (0)
7454 + UNITS_PER_WORD * first_reg));
7459 /* Implement `va_start' for stdarg. */
7462 sparc_va_start (tree valist, rtx nextarg)
7464 nextarg = expand_builtin_saveregs ();
7465 std_expand_builtin_va_start (valist, nextarg);
7468 /* Implement `va_arg' for stdarg. */
7471 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
7474 HOST_WIDE_INT size, rsize, align;
7477 tree ptrtype = build_pointer_type (type);
7479 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7482 size = rsize = UNITS_PER_WORD;
7488 size = int_size_in_bytes (type);
7489 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7494 /* For SPARC64, objects requiring 16-byte alignment get it. */
7495 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
7496 align = 2 * UNITS_PER_WORD;
7498 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7499 are left-justified in their slots. */
7500 if (AGGREGATE_TYPE_P (type))
7503 size = rsize = UNITS_PER_WORD;
7513 incr = fold_build_pointer_plus_hwi (incr, align - 1);
7514 incr = fold_convert (sizetype, incr);
7515 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
7517 incr = fold_convert (ptr_type_node, incr);
7520 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
7523 if (BYTES_BIG_ENDIAN && size < rsize)
7524 addr = fold_build_pointer_plus_hwi (incr, rsize - size);
7528 addr = fold_convert (build_pointer_type (ptrtype), addr);
7529 addr = build_va_arg_indirect_ref (addr);
7532 /* If the address isn't aligned properly for the type, we need a temporary.
7533 FIXME: This is inefficient, usually we can do this in registers. */
7534 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
7536 tree tmp = create_tmp_var (type, "va_arg_tmp");
7537 tree dest_addr = build_fold_addr_expr (tmp);
7538 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
7539 3, dest_addr, addr, size_int (rsize));
7540 TREE_ADDRESSABLE (tmp) = 1;
7541 gimplify_and_add (copy, pre_p);
7546 addr = fold_convert (ptrtype, addr);
7548 incr = fold_build_pointer_plus_hwi (incr, rsize);
7549 gimplify_assign (valist, incr, post_p);
7551 return build_va_arg_indirect_ref (addr);
7554 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7555 Specify whether the vector mode is supported by the hardware. */
7558 sparc_vector_mode_supported_p (enum machine_mode mode)
7560 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
7563 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7565 static enum machine_mode
7566 sparc_preferred_simd_mode (enum machine_mode mode)
7584 /* Return the string to output an unconditional branch to LABEL, which is
7585 the operand number of the label.
7587 DEST is the destination insn (i.e. the label), INSN is the source. */
7590 output_ubranch (rtx dest, rtx insn)
7592 static char string[64];
7593 bool v9_form = false;
7597 /* Even if we are trying to use cbcond for this, evaluate
7598 whether we can use V9 branches as our backup plan. */
7601 if (INSN_ADDRESSES_SET_P ())
7602 delta = (INSN_ADDRESSES (INSN_UID (dest))
7603 - INSN_ADDRESSES (INSN_UID (insn)));
7605 /* Leave some instructions for "slop". */
7606 if (TARGET_V9 && delta >= -260000 && delta < 260000)
7611 bool emit_nop = emit_cbcond_nop (insn);
7615 if (delta < -500 || delta > 500)
7621 rval = "ba,a,pt\t%%xcc, %l0";
7628 rval = "cwbe\t%%g0, %%g0, %l0\n\tnop";
7630 rval = "cwbe\t%%g0, %%g0, %l0";
7636 strcpy (string, "ba%*,pt\t%%xcc, ");
7638 strcpy (string, "b%*\t");
7640 p = strchr (string, '\0');
7651 /* Return the string to output a conditional branch to LABEL, which is
7652 the operand number of the label. OP is the conditional expression.
7653 XEXP (OP, 0) is assumed to be a condition code register (integer or
7654 floating point) and its mode specifies what kind of comparison we made.
7656 DEST is the destination insn (i.e. the label), INSN is the source.
7658 REVERSED is nonzero if we should reverse the sense of the comparison.
7660 ANNUL is nonzero if we should generate an annulling branch. */
7663 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
7666 static char string[64];
7667 enum rtx_code code = GET_CODE (op);
7668 rtx cc_reg = XEXP (op, 0);
7669 enum machine_mode mode = GET_MODE (cc_reg);
7670 const char *labelno, *branch;
7671 int spaces = 8, far;
7674 /* v9 branches are limited to +-1MB. If it is too far away,
7687 fbne,a,pn %fcc2, .LC29
7695 far = TARGET_V9 && (get_attr_length (insn) >= 3);
7698 /* Reversal of FP compares takes care -- an ordered compare
7699 becomes an unordered compare and vice versa. */
7700 if (mode == CCFPmode || mode == CCFPEmode)
7701 code = reverse_condition_maybe_unordered (code);
7703 code = reverse_condition (code);
7706 /* Start by writing the branch condition. */
7707 if (mode == CCFPmode || mode == CCFPEmode)
7758 /* ??? !v9: FP branches cannot be preceded by another floating point
7759 insn. Because there is currently no concept of pre-delay slots,
7760 we can fix this only by always emitting a nop before a floating
7765 strcpy (string, "nop\n\t");
7766 strcat (string, branch);
7779 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7791 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7812 strcpy (string, branch);
7814 spaces -= strlen (branch);
7815 p = strchr (string, '\0');
7817 /* Now add the annulling, the label, and a possible noop. */
7830 if (! far && insn && INSN_ADDRESSES_SET_P ())
7832 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7833 - INSN_ADDRESSES (INSN_UID (insn)));
7834 /* Leave some instructions for "slop". */
7835 if (delta < -260000 || delta >= 260000)
7839 if (mode == CCFPmode || mode == CCFPEmode)
7841 static char v9_fcc_labelno[] = "%%fccX, ";
7842 /* Set the char indicating the number of the fcc reg to use. */
7843 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
7844 labelno = v9_fcc_labelno;
7847 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
7851 else if (mode == CCXmode || mode == CCX_NOOVmode)
7853 labelno = "%%xcc, ";
7858 labelno = "%%icc, ";
7863 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7866 ((XINT (note, 0) >= REG_BR_PROB_BASE / 2) ^ far)
7879 strcpy (p, labelno);
7880 p = strchr (p, '\0');
7883 strcpy (p, ".+12\n\t nop\n\tb\t");
7884 /* Skip the next insn if requested or
7885 if we know that it will be a nop. */
7886 if (annul || ! final_sequence)
7900 /* Emit a library call comparison between floating point X and Y.
7901 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7902 Return the new operator to be used in the comparison sequence.
7904 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7905 values as arguments instead of the TFmode registers themselves,
7906 that's why we cannot call emit_float_lib_cmp. */
7909 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
7912 rtx slot0, slot1, result, tem, tem2, libfunc;
7913 enum machine_mode mode;
7914 enum rtx_code new_comparison;
7919 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
7923 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
7927 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
7931 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
7935 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
7939 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
7950 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
7961 tree expr = MEM_EXPR (x);
7963 mark_addressable (expr);
7968 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode));
7969 emit_move_insn (slot0, x);
7974 tree expr = MEM_EXPR (y);
7976 mark_addressable (expr);
7981 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode));
7982 emit_move_insn (slot1, y);
7985 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7986 emit_library_call (libfunc, LCT_NORMAL,
7988 XEXP (slot0, 0), Pmode,
7989 XEXP (slot1, 0), Pmode);
7994 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7995 emit_library_call (libfunc, LCT_NORMAL,
7997 x, TFmode, y, TFmode);
8002 /* Immediately move the result of the libcall into a pseudo
8003 register so reload doesn't clobber the value if it needs
8004 the return register for a spill reg. */
8005 result = gen_reg_rtx (mode);
8006 emit_move_insn (result, hard_libcall_value (mode, libfunc));
8011 return gen_rtx_NE (VOIDmode, result, const0_rtx);
8014 new_comparison = (comparison == UNORDERED ? EQ : NE);
8015 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
8018 new_comparison = (comparison == UNGT ? GT : NE);
8019 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
8021 return gen_rtx_NE (VOIDmode, result, const2_rtx);
8023 tem = gen_reg_rtx (mode);
8025 emit_insn (gen_andsi3 (tem, result, const1_rtx));
8027 emit_insn (gen_anddi3 (tem, result, const1_rtx));
8028 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
8031 tem = gen_reg_rtx (mode);
8033 emit_insn (gen_addsi3 (tem, result, const1_rtx));
8035 emit_insn (gen_adddi3 (tem, result, const1_rtx));
8036 tem2 = gen_reg_rtx (mode);
8038 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
8040 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
8041 new_comparison = (comparison == UNEQ ? EQ : NE);
8042 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
8048 /* Generate an unsigned DImode to FP conversion. This is the same code
8049 optabs would emit if we didn't have TFmode patterns. */
8052 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
8054 rtx neglab, donelab, i0, i1, f0, in, out;
8057 in = force_reg (DImode, operands[1]);
8058 neglab = gen_label_rtx ();
8059 donelab = gen_label_rtx ();
8060 i0 = gen_reg_rtx (DImode);
8061 i1 = gen_reg_rtx (DImode);
8062 f0 = gen_reg_rtx (mode);
8064 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
8066 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
8067 emit_jump_insn (gen_jump (donelab));
8070 emit_label (neglab);
8072 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
8073 emit_insn (gen_anddi3 (i1, in, const1_rtx));
8074 emit_insn (gen_iordi3 (i0, i0, i1));
8075 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
8076 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
8078 emit_label (donelab);
8081 /* Generate an FP to unsigned DImode conversion. This is the same code
8082 optabs would emit if we didn't have TFmode patterns. */
8085 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
8087 rtx neglab, donelab, i0, i1, f0, in, out, limit;
8090 in = force_reg (mode, operands[1]);
8091 neglab = gen_label_rtx ();
8092 donelab = gen_label_rtx ();
8093 i0 = gen_reg_rtx (DImode);
8094 i1 = gen_reg_rtx (DImode);
8095 limit = gen_reg_rtx (mode);
8096 f0 = gen_reg_rtx (mode);
8098 emit_move_insn (limit,
8099 CONST_DOUBLE_FROM_REAL_VALUE (
8100 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
8101 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
8103 emit_insn (gen_rtx_SET (VOIDmode,
8105 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
8106 emit_jump_insn (gen_jump (donelab));
8109 emit_label (neglab);
8111 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
8112 emit_insn (gen_rtx_SET (VOIDmode,
8114 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
8115 emit_insn (gen_movdi (i1, const1_rtx));
8116 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
8117 emit_insn (gen_xordi3 (out, i0, i1));
8119 emit_label (donelab);
8122 /* Return the string to output a compare and branch instruction to DEST.
8123 DEST is the destination insn (i.e. the label), INSN is the source,
8124 and OP is the conditional expression. */
8127 output_cbcond (rtx op, rtx dest, rtx insn)
8129 enum machine_mode mode = GET_MODE (XEXP (op, 0));
8130 enum rtx_code code = GET_CODE (op);
8131 const char *cond_str, *tmpl;
8132 int far, emit_nop, len;
8133 static char string[64];
8136 /* Compare and Branch is limited to +-2KB. If it is too far away,
8148 len = get_attr_length (insn);
8151 emit_nop = len == 2;
8154 code = reverse_condition (code);
8156 size_char = ((mode == SImode) ? 'w' : 'x');
8169 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
8184 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
8212 int veryfar = 1, delta;
8214 if (INSN_ADDRESSES_SET_P ())
8216 delta = (INSN_ADDRESSES (INSN_UID (dest))
8217 - INSN_ADDRESSES (INSN_UID (insn)));
8218 /* Leave some instructions for "slop". */
8219 if (delta >= -260000 && delta < 260000)
8224 tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8226 tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8231 tmpl = "c%cb%s\t%%1, %%2, %%3\n\tnop";
8233 tmpl = "c%cb%s\t%%1, %%2, %%3";
8236 snprintf (string, sizeof(string), tmpl, size_char, cond_str);
8241 /* Return the string to output a conditional branch to LABEL, testing
8242 register REG. LABEL is the operand number of the label; REG is the
8243 operand number of the reg. OP is the conditional expression. The mode
8244 of REG says what kind of comparison we made.
8246 DEST is the destination insn (i.e. the label), INSN is the source.
8248 REVERSED is nonzero if we should reverse the sense of the comparison.
8250 ANNUL is nonzero if we should generate an annulling branch. */
8253 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
8254 int annul, rtx insn)
8256 static char string[64];
8257 enum rtx_code code = GET_CODE (op);
8258 enum machine_mode mode = GET_MODE (XEXP (op, 0));
8263 /* branch on register are limited to +-128KB. If it is too far away,
8276 brgez,a,pn %o1, .LC29
8282 ba,pt %xcc, .LC29 */
8284 far = get_attr_length (insn) >= 3;
8286 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8288 code = reverse_condition (code);
8290 /* Only 64 bit versions of these instructions exist. */
8291 gcc_assert (mode == DImode);
8293 /* Start by writing the branch condition. */
8298 strcpy (string, "brnz");
8302 strcpy (string, "brz");
8306 strcpy (string, "brgez");
8310 strcpy (string, "brlz");
8314 strcpy (string, "brlez");
8318 strcpy (string, "brgz");
8325 p = strchr (string, '\0');
8327 /* Now add the annulling, reg, label, and nop. */
8334 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
8337 ((XINT (note, 0) >= REG_BR_PROB_BASE / 2) ^ far)
8342 *p = p < string + 8 ? '\t' : ' ';
8350 int veryfar = 1, delta;
8352 if (INSN_ADDRESSES_SET_P ())
8354 delta = (INSN_ADDRESSES (INSN_UID (dest))
8355 - INSN_ADDRESSES (INSN_UID (insn)));
8356 /* Leave some instructions for "slop". */
8357 if (delta >= -260000 && delta < 260000)
8361 strcpy (p, ".+12\n\t nop\n\t");
8362 /* Skip the next insn if requested or
8363 if we know that it will be a nop. */
8364 if (annul || ! final_sequence)
8374 strcpy (p, "ba,pt\t%%xcc, ");
8388 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8389 Such instructions cannot be used in the delay slot of return insn on v9.
8390 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8394 epilogue_renumber (register rtx *where, int test)
8396 register const char *fmt;
8398 register enum rtx_code code;
8403 code = GET_CODE (*where);
8408 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
8410 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
8411 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
8419 /* Do not replace the frame pointer with the stack pointer because
8420 it can cause the delayed instruction to load below the stack.
8421 This occurs when instructions like:
8423 (set (reg/i:SI 24 %i0)
8424 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8425 (const_int -20 [0xffffffec])) 0))
8427 are in the return delayed slot. */
8429 if (GET_CODE (XEXP (*where, 0)) == REG
8430 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
8431 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
8432 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
8437 if (SPARC_STACK_BIAS
8438 && GET_CODE (XEXP (*where, 0)) == REG
8439 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
8447 fmt = GET_RTX_FORMAT (code);
8449 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8454 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
8455 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
8458 else if (fmt[i] == 'e'
8459 && epilogue_renumber (&(XEXP (*where, i)), test))
8465 /* Leaf functions and non-leaf functions have different needs. */
8468 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
8471 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
8473 static const int *const reg_alloc_orders[] = {
8474 reg_leaf_alloc_order,
8475 reg_nonleaf_alloc_order};
8478 order_regs_for_local_alloc (void)
8480 static int last_order_nonleaf = 1;
8482 if (df_regs_ever_live_p (15) != last_order_nonleaf)
8484 last_order_nonleaf = !last_order_nonleaf;
8485 memcpy ((char *) reg_alloc_order,
8486 (const char *) reg_alloc_orders[last_order_nonleaf],
8487 FIRST_PSEUDO_REGISTER * sizeof (int));
8491 /* Return 1 if REG and MEM are legitimate enough to allow the various
8492 mem<-->reg splits to be run. */
8495 sparc_splitdi_legitimate (rtx reg, rtx mem)
8497 /* Punt if we are here by mistake. */
8498 gcc_assert (reload_completed);
8500 /* We must have an offsettable memory reference. */
8501 if (! offsettable_memref_p (mem))
8504 /* If we have legitimate args for ldd/std, we do not want
8505 the split to happen. */
8506 if ((REGNO (reg) % 2) == 0
8507 && mem_min_alignment (mem, 8))
8514 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8517 sparc_split_regreg_legitimate (rtx reg1, rtx reg2)
8521 if (GET_CODE (reg1) == SUBREG)
8522 reg1 = SUBREG_REG (reg1);
8523 if (GET_CODE (reg1) != REG)
8525 regno1 = REGNO (reg1);
8527 if (GET_CODE (reg2) == SUBREG)
8528 reg2 = SUBREG_REG (reg2);
8529 if (GET_CODE (reg2) != REG)
8531 regno2 = REGNO (reg2);
8533 if (SPARC_INT_REG_P (regno1) && SPARC_INT_REG_P (regno2))
8538 if ((SPARC_INT_REG_P (regno1) && SPARC_FP_REG_P (regno2))
8539 || (SPARC_FP_REG_P (regno1) && SPARC_INT_REG_P (regno2)))
8546 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8547 This makes them candidates for using ldd and std insns.
8549 Note reg1 and reg2 *must* be hard registers. */
8552 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
8554 /* We might have been passed a SUBREG. */
8555 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8558 if (REGNO (reg1) % 2 != 0)
8561 /* Integer ldd is deprecated in SPARC V9 */
8562 if (TARGET_V9 && SPARC_INT_REG_P (REGNO (reg1)))
8565 return (REGNO (reg1) == REGNO (reg2) - 1);
8568 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8571 This can only happen when addr1 and addr2, the addresses in mem1
8572 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8573 addr1 must also be aligned on a 64-bit boundary.
8575 Also iff dependent_reg_rtx is not null it should not be used to
8576 compute the address for mem1, i.e. we cannot optimize a sequence
8588 But, note that the transformation from:
8593 is perfectly fine. Thus, the peephole2 patterns always pass us
8594 the destination register of the first load, never the second one.
8596 For stores we don't have a similar problem, so dependent_reg_rtx is
8600 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
8604 HOST_WIDE_INT offset1;
8606 /* The mems cannot be volatile. */
8607 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8610 /* MEM1 should be aligned on a 64-bit boundary. */
8611 if (MEM_ALIGN (mem1) < 64)
8614 addr1 = XEXP (mem1, 0);
8615 addr2 = XEXP (mem2, 0);
8617 /* Extract a register number and offset (if used) from the first addr. */
8618 if (GET_CODE (addr1) == PLUS)
8620 /* If not a REG, return zero. */
8621 if (GET_CODE (XEXP (addr1, 0)) != REG)
8625 reg1 = REGNO (XEXP (addr1, 0));
8626 /* The offset must be constant! */
8627 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8629 offset1 = INTVAL (XEXP (addr1, 1));
8632 else if (GET_CODE (addr1) != REG)
8636 reg1 = REGNO (addr1);
8637 /* This was a simple (mem (reg)) expression. Offset is 0. */
8641 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8642 if (GET_CODE (addr2) != PLUS)
8645 if (GET_CODE (XEXP (addr2, 0)) != REG
8646 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8649 if (reg1 != REGNO (XEXP (addr2, 0)))
8652 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
8655 /* The first offset must be evenly divisible by 8 to ensure the
8656 address is 64 bit aligned. */
8657 if (offset1 % 8 != 0)
8660 /* The offset for the second addr must be 4 more than the first addr. */
8661 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
8664 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8669 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8672 widen_mem_for_ldd_peep (rtx mem1, rtx mem2, enum machine_mode mode)
8674 rtx x = widen_memory_access (mem1, mode, 0);
8675 MEM_NOTRAP_P (x) = MEM_NOTRAP_P (mem1) && MEM_NOTRAP_P (mem2);
8679 /* Return 1 if reg is a pseudo, or is the first register in
8680 a hard register pair. This makes it suitable for use in
8681 ldd and std insns. */
8684 register_ok_for_ldd (rtx reg)
8686 /* We might have been passed a SUBREG. */
8690 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
8691 return (REGNO (reg) % 2 == 0);
8696 /* Return 1 if OP, a MEM, has an address which is known to be
8697 aligned to an 8-byte boundary. */
8700 memory_ok_for_ldd (rtx op)
8702 /* In 64-bit mode, we assume that the address is word-aligned. */
8703 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
8706 if (! can_create_pseudo_p ()
8707 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
8713 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8716 sparc_print_operand_punct_valid_p (unsigned char code)
8729 /* Implement TARGET_PRINT_OPERAND.
8730 Print operand X (an rtx) in assembler syntax to file FILE.
8731 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8732 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8735 sparc_print_operand (FILE *file, rtx x, int code)
8740 /* Output an insn in a delay slot. */
8742 sparc_indent_opcode = 1;
8744 fputs ("\n\t nop", file);
8747 /* Output an annul flag if there's nothing for the delay slot and we
8748 are optimizing. This is always used with '(' below.
8749 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8750 this is a dbx bug. So, we only do this when optimizing.
8751 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8752 Always emit a nop in case the next instruction is a branch. */
8753 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
8757 /* Output a 'nop' if there's nothing for the delay slot and we are
8758 not optimizing. This is always used with '*' above. */
8759 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
8760 fputs ("\n\t nop", file);
8761 else if (final_sequence)
8762 sparc_indent_opcode = 1;
8765 /* Output the right displacement from the saved PC on function return.
8766 The caller may have placed an "unimp" insn immediately after the call
8767 so we have to account for it. This insn is used in the 32-bit ABI
8768 when calling a function that returns a non zero-sized structure. The
8769 64-bit ABI doesn't have it. Be careful to have this test be the same
8770 as that for the call. The exception is when sparc_std_struct_return
8771 is enabled, the psABI is followed exactly and the adjustment is made
8772 by the code in sparc_struct_value_rtx. The call emitted is the same
8773 when sparc_std_struct_return is enabled. */
8775 && cfun->returns_struct
8776 && !sparc_std_struct_return
8777 && DECL_SIZE (DECL_RESULT (current_function_decl))
8778 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
8780 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
8786 /* Output the Embedded Medium/Anywhere code model base register. */
8787 fputs (EMBMEDANY_BASE_REG, file);
8790 /* Print some local dynamic TLS name. */
8791 assemble_name (file, get_some_local_dynamic_name ());
8795 /* Adjust the operand to take into account a RESTORE operation. */
8796 if (GET_CODE (x) == CONST_INT)
8798 else if (GET_CODE (x) != REG)
8799 output_operand_lossage ("invalid %%Y operand");
8800 else if (REGNO (x) < 8)
8801 fputs (reg_names[REGNO (x)], file);
8802 else if (REGNO (x) >= 24 && REGNO (x) < 32)
8803 fputs (reg_names[REGNO (x)-16], file);
8805 output_operand_lossage ("invalid %%Y operand");
8808 /* Print out the low order register name of a register pair. */
8809 if (WORDS_BIG_ENDIAN)
8810 fputs (reg_names[REGNO (x)+1], file);
8812 fputs (reg_names[REGNO (x)], file);
8815 /* Print out the high order register name of a register pair. */
8816 if (WORDS_BIG_ENDIAN)
8817 fputs (reg_names[REGNO (x)], file);
8819 fputs (reg_names[REGNO (x)+1], file);
8822 /* Print out the second register name of a register pair or quad.
8823 I.e., R (%o0) => %o1. */
8824 fputs (reg_names[REGNO (x)+1], file);
8827 /* Print out the third register name of a register quad.
8828 I.e., S (%o0) => %o2. */
8829 fputs (reg_names[REGNO (x)+2], file);
8832 /* Print out the fourth register name of a register quad.
8833 I.e., T (%o0) => %o3. */
8834 fputs (reg_names[REGNO (x)+3], file);
8837 /* Print a condition code register. */
8838 if (REGNO (x) == SPARC_ICC_REG)
8840 /* We don't handle CC[X]_NOOVmode because they're not supposed
8842 if (GET_MODE (x) == CCmode)
8843 fputs ("%icc", file);
8844 else if (GET_MODE (x) == CCXmode)
8845 fputs ("%xcc", file);
8850 /* %fccN register */
8851 fputs (reg_names[REGNO (x)], file);
8854 /* Print the operand's address only. */
8855 output_address (XEXP (x, 0));
8858 /* In this case we need a register. Use %g0 if the
8859 operand is const0_rtx. */
8861 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
8863 fputs ("%g0", file);
8870 switch (GET_CODE (x))
8872 case IOR: fputs ("or", file); break;
8873 case AND: fputs ("and", file); break;
8874 case XOR: fputs ("xor", file); break;
8875 default: output_operand_lossage ("invalid %%A operand");
8880 switch (GET_CODE (x))
8882 case IOR: fputs ("orn", file); break;
8883 case AND: fputs ("andn", file); break;
8884 case XOR: fputs ("xnor", file); break;
8885 default: output_operand_lossage ("invalid %%B operand");
8889 /* This is used by the conditional move instructions. */
8892 enum rtx_code rc = GET_CODE (x);
8896 case NE: fputs ("ne", file); break;
8897 case EQ: fputs ("e", file); break;
8898 case GE: fputs ("ge", file); break;
8899 case GT: fputs ("g", file); break;
8900 case LE: fputs ("le", file); break;
8901 case LT: fputs ("l", file); break;
8902 case GEU: fputs ("geu", file); break;
8903 case GTU: fputs ("gu", file); break;
8904 case LEU: fputs ("leu", file); break;
8905 case LTU: fputs ("lu", file); break;
8906 case LTGT: fputs ("lg", file); break;
8907 case UNORDERED: fputs ("u", file); break;
8908 case ORDERED: fputs ("o", file); break;
8909 case UNLT: fputs ("ul", file); break;
8910 case UNLE: fputs ("ule", file); break;
8911 case UNGT: fputs ("ug", file); break;
8912 case UNGE: fputs ("uge", file); break;
8913 case UNEQ: fputs ("ue", file); break;
8914 default: output_operand_lossage ("invalid %%C operand");
8919 /* This are used by the movr instruction pattern. */
8922 enum rtx_code rc = GET_CODE (x);
8925 case NE: fputs ("ne", file); break;
8926 case EQ: fputs ("e", file); break;
8927 case GE: fputs ("gez", file); break;
8928 case LT: fputs ("lz", file); break;
8929 case LE: fputs ("lez", file); break;
8930 case GT: fputs ("gz", file); break;
8931 default: output_operand_lossage ("invalid %%D operand");
8938 /* Print a sign-extended character. */
8939 int i = trunc_int_for_mode (INTVAL (x), QImode);
8940 fprintf (file, "%d", i);
8945 /* Operand must be a MEM; write its address. */
8946 if (GET_CODE (x) != MEM)
8947 output_operand_lossage ("invalid %%f operand");
8948 output_address (XEXP (x, 0));
8953 /* Print a sign-extended 32-bit value. */
8955 if (GET_CODE(x) == CONST_INT)
8957 else if (GET_CODE(x) == CONST_DOUBLE)
8958 i = CONST_DOUBLE_LOW (x);
8961 output_operand_lossage ("invalid %%s operand");
8964 i = trunc_int_for_mode (i, SImode);
8965 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
8970 /* Do nothing special. */
8974 /* Undocumented flag. */
8975 output_operand_lossage ("invalid operand output code");
8978 if (GET_CODE (x) == REG)
8979 fputs (reg_names[REGNO (x)], file);
8980 else if (GET_CODE (x) == MEM)
8983 /* Poor Sun assembler doesn't understand absolute addressing. */
8984 if (CONSTANT_P (XEXP (x, 0)))
8985 fputs ("%g0+", file);
8986 output_address (XEXP (x, 0));
8989 else if (GET_CODE (x) == HIGH)
8991 fputs ("%hi(", file);
8992 output_addr_const (file, XEXP (x, 0));
8995 else if (GET_CODE (x) == LO_SUM)
8997 sparc_print_operand (file, XEXP (x, 0), 0);
8998 if (TARGET_CM_MEDMID)
8999 fputs ("+%l44(", file);
9001 fputs ("+%lo(", file);
9002 output_addr_const (file, XEXP (x, 1));
9005 else if (GET_CODE (x) == CONST_DOUBLE
9006 && (GET_MODE (x) == VOIDmode
9007 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
9009 if (CONST_DOUBLE_HIGH (x) == 0)
9010 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
9011 else if (CONST_DOUBLE_HIGH (x) == -1
9012 && CONST_DOUBLE_LOW (x) < 0)
9013 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
9015 output_operand_lossage ("long long constant not a valid immediate operand");
9017 else if (GET_CODE (x) == CONST_DOUBLE)
9018 output_operand_lossage ("floating point constant not a valid immediate operand");
9019 else { output_addr_const (file, x); }
9022 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9025 sparc_print_operand_address (FILE *file, rtx x)
9027 register rtx base, index = 0;
9029 register rtx addr = x;
9032 fputs (reg_names[REGNO (addr)], file);
9033 else if (GET_CODE (addr) == PLUS)
9035 if (CONST_INT_P (XEXP (addr, 0)))
9036 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
9037 else if (CONST_INT_P (XEXP (addr, 1)))
9038 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
9040 base = XEXP (addr, 0), index = XEXP (addr, 1);
9041 if (GET_CODE (base) == LO_SUM)
9043 gcc_assert (USE_AS_OFFSETABLE_LO10
9045 && ! TARGET_CM_MEDMID);
9046 output_operand (XEXP (base, 0), 0);
9047 fputs ("+%lo(", file);
9048 output_address (XEXP (base, 1));
9049 fprintf (file, ")+%d", offset);
9053 fputs (reg_names[REGNO (base)], file);
9055 fprintf (file, "%+d", offset);
9056 else if (REG_P (index))
9057 fprintf (file, "+%s", reg_names[REGNO (index)]);
9058 else if (GET_CODE (index) == SYMBOL_REF
9059 || GET_CODE (index) == LABEL_REF
9060 || GET_CODE (index) == CONST)
9061 fputc ('+', file), output_addr_const (file, index);
9062 else gcc_unreachable ();
9065 else if (GET_CODE (addr) == MINUS
9066 && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
9068 output_addr_const (file, XEXP (addr, 0));
9070 output_addr_const (file, XEXP (addr, 1));
9071 fputs ("-.)", file);
9073 else if (GET_CODE (addr) == LO_SUM)
9075 output_operand (XEXP (addr, 0), 0);
9076 if (TARGET_CM_MEDMID)
9077 fputs ("+%l44(", file);
9079 fputs ("+%lo(", file);
9080 output_address (XEXP (addr, 1));
9084 && GET_CODE (addr) == CONST
9085 && GET_CODE (XEXP (addr, 0)) == MINUS
9086 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST
9087 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS
9088 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)
9090 addr = XEXP (addr, 0);
9091 output_addr_const (file, XEXP (addr, 0));
9092 /* Group the args of the second CONST in parenthesis. */
9094 /* Skip past the second CONST--it does nothing for us. */
9095 output_addr_const (file, XEXP (XEXP (addr, 1), 0));
9096 /* Close the parenthesis. */
9101 output_addr_const (file, addr);
9105 /* Target hook for assembling integer objects. The sparc version has
9106 special handling for aligned DI-mode objects. */
9109 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
9111 /* ??? We only output .xword's for symbols and only then in environments
9112 where the assembler can handle them. */
9113 if (aligned_p && size == 8
9114 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
9118 assemble_integer_with_op ("\t.xword\t", x);
9123 assemble_aligned_integer (4, const0_rtx);
9124 assemble_aligned_integer (4, x);
9128 return default_assemble_integer (x, size, aligned_p);
9131 /* Return the value of a code used in the .proc pseudo-op that says
9132 what kind of result this function returns. For non-C types, we pick
9133 the closest C type. */
9135 #ifndef SHORT_TYPE_SIZE
9136 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9139 #ifndef INT_TYPE_SIZE
9140 #define INT_TYPE_SIZE BITS_PER_WORD
9143 #ifndef LONG_TYPE_SIZE
9144 #define LONG_TYPE_SIZE BITS_PER_WORD
9147 #ifndef LONG_LONG_TYPE_SIZE
9148 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9151 #ifndef FLOAT_TYPE_SIZE
9152 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9155 #ifndef DOUBLE_TYPE_SIZE
9156 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9159 #ifndef LONG_DOUBLE_TYPE_SIZE
9160 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9164 sparc_type_code (register tree type)
9166 register unsigned long qualifiers = 0;
9167 register unsigned shift;
9169 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9170 setting more, since some assemblers will give an error for this. Also,
9171 we must be careful to avoid shifts of 32 bits or more to avoid getting
9172 unpredictable results. */
9174 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
9176 switch (TREE_CODE (type))
9182 qualifiers |= (3 << shift);
9187 qualifiers |= (2 << shift);
9191 case REFERENCE_TYPE:
9193 qualifiers |= (1 << shift);
9197 return (qualifiers | 8);
9200 case QUAL_UNION_TYPE:
9201 return (qualifiers | 9);
9204 return (qualifiers | 10);
9207 return (qualifiers | 16);
9210 /* If this is a range type, consider it to be the underlying
9212 if (TREE_TYPE (type) != 0)
9215 /* Carefully distinguish all the standard types of C,
9216 without messing up if the language is not C. We do this by
9217 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9218 look at both the names and the above fields, but that's redundant.
9219 Any type whose size is between two C types will be considered
9220 to be the wider of the two types. Also, we do not have a
9221 special code to use for "long long", so anything wider than
9222 long is treated the same. Note that we can't distinguish
9223 between "int" and "long" in this code if they are the same
9224 size, but that's fine, since neither can the assembler. */
9226 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
9227 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
9229 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
9230 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
9232 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
9233 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
9236 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
9239 /* If this is a range type, consider it to be the underlying
9241 if (TREE_TYPE (type) != 0)
9244 /* Carefully distinguish all the standard types of C,
9245 without messing up if the language is not C. */
9247 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
9248 return (qualifiers | 6);
9251 return (qualifiers | 7);
9253 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
9254 /* ??? We need to distinguish between double and float complex types,
9255 but I don't know how yet because I can't reach this code from
9256 existing front-ends. */
9257 return (qualifiers | 7); /* Who knows? */
9260 case BOOLEAN_TYPE: /* Boolean truth value type. */
9266 gcc_unreachable (); /* Not a type! */
9273 /* Nested function support. */
9275 /* Emit RTL insns to initialize the variable parts of a trampoline.
9276 FNADDR is an RTX for the address of the function's pure code.
9277 CXT is an RTX for the static chain value for the function.
9279 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9280 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9281 (to store insns). This is a bit excessive. Perhaps a different
9282 mechanism would be better here.
9284 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9287 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
9289 /* SPARC 32-bit trampoline:
9292 sethi %hi(static), %g2
9294 or %g2, %lo(static), %g2
9296 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9297 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9301 (adjust_address (m_tramp, SImode, 0),
9302 expand_binop (SImode, ior_optab,
9303 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1),
9304 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
9305 NULL_RTX, 1, OPTAB_DIRECT));
9308 (adjust_address (m_tramp, SImode, 4),
9309 expand_binop (SImode, ior_optab,
9310 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1),
9311 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
9312 NULL_RTX, 1, OPTAB_DIRECT));
9315 (adjust_address (m_tramp, SImode, 8),
9316 expand_binop (SImode, ior_optab,
9317 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
9318 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
9319 NULL_RTX, 1, OPTAB_DIRECT));
9322 (adjust_address (m_tramp, SImode, 12),
9323 expand_binop (SImode, ior_optab,
9324 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
9325 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
9326 NULL_RTX, 1, OPTAB_DIRECT));
9328 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9329 aligned on a 16 byte boundary so one flush clears it all. */
9330 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 0))));
9331 if (sparc_cpu != PROCESSOR_ULTRASPARC
9332 && sparc_cpu != PROCESSOR_ULTRASPARC3
9333 && sparc_cpu != PROCESSOR_NIAGARA
9334 && sparc_cpu != PROCESSOR_NIAGARA2
9335 && sparc_cpu != PROCESSOR_NIAGARA3
9336 && sparc_cpu != PROCESSOR_NIAGARA4)
9337 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8))));
9339 /* Call __enable_execute_stack after writing onto the stack to make sure
9340 the stack address is accessible. */
9341 #ifdef HAVE_ENABLE_EXECUTE_STACK
9342 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
9343 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
9348 /* The 64-bit version is simpler because it makes more sense to load the
9349 values as "immediate" data out of the trampoline. It's also easier since
9350 we can read the PC without clobbering a register. */
9353 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
9355 /* SPARC 64-bit trampoline:
9364 emit_move_insn (adjust_address (m_tramp, SImode, 0),
9365 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
9366 emit_move_insn (adjust_address (m_tramp, SImode, 4),
9367 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
9368 emit_move_insn (adjust_address (m_tramp, SImode, 8),
9369 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
9370 emit_move_insn (adjust_address (m_tramp, SImode, 12),
9371 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
9372 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
9373 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
9374 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
9376 if (sparc_cpu != PROCESSOR_ULTRASPARC
9377 && sparc_cpu != PROCESSOR_ULTRASPARC3
9378 && sparc_cpu != PROCESSOR_NIAGARA
9379 && sparc_cpu != PROCESSOR_NIAGARA2
9380 && sparc_cpu != PROCESSOR_NIAGARA3
9381 && sparc_cpu != PROCESSOR_NIAGARA4)
9382 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
9384 /* Call __enable_execute_stack after writing onto the stack to make sure
9385 the stack address is accessible. */
9386 #ifdef HAVE_ENABLE_EXECUTE_STACK
9387 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
9388 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
9392 /* Worker for TARGET_TRAMPOLINE_INIT. */
9395 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9397 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
9398 cxt = force_reg (Pmode, cxt);
9400 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
9402 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
9405 /* Adjust the cost of a scheduling dependency. Return the new cost of
9406 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9409 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
9411 enum attr_type insn_type;
9413 if (! recog_memoized (insn))
9416 insn_type = get_attr_type (insn);
9418 if (REG_NOTE_KIND (link) == 0)
9420 /* Data dependency; DEP_INSN writes a register that INSN reads some
9423 /* if a load, then the dependence must be on the memory address;
9424 add an extra "cycle". Note that the cost could be two cycles
9425 if the reg was written late in an instruction group; we ca not tell
9427 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
9430 /* Get the delay only if the address of the store is the dependence. */
9431 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
9433 rtx pat = PATTERN(insn);
9434 rtx dep_pat = PATTERN (dep_insn);
9436 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
9437 return cost; /* This should not happen! */
9439 /* The dependency between the two instructions was on the data that
9440 is being stored. Assume that this implies that the address of the
9441 store is not dependent. */
9442 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
9445 return cost + 3; /* An approximation. */
9448 /* A shift instruction cannot receive its data from an instruction
9449 in the same cycle; add a one cycle penalty. */
9450 if (insn_type == TYPE_SHIFT)
9451 return cost + 3; /* Split before cascade into shift. */
9455 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9456 INSN writes some cycles later. */
9458 /* These are only significant for the fpu unit; writing a fp reg before
9459 the fpu has finished with it stalls the processor. */
9461 /* Reusing an integer register causes no problems. */
9462 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
9470 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
9472 enum attr_type insn_type, dep_type;
9473 rtx pat = PATTERN(insn);
9474 rtx dep_pat = PATTERN (dep_insn);
9476 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
9479 insn_type = get_attr_type (insn);
9480 dep_type = get_attr_type (dep_insn);
9482 switch (REG_NOTE_KIND (link))
9485 /* Data dependency; DEP_INSN writes a register that INSN reads some
9492 /* Get the delay iff the address of the store is the dependence. */
9493 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
9496 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
9503 /* If a load, then the dependence must be on the memory address. If
9504 the addresses aren't equal, then it might be a false dependency */
9505 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
9507 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
9508 || GET_CODE (SET_DEST (dep_pat)) != MEM
9509 || GET_CODE (SET_SRC (pat)) != MEM
9510 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
9511 XEXP (SET_SRC (pat), 0)))
9519 /* Compare to branch latency is 0. There is no benefit from
9520 separating compare and branch. */
9521 if (dep_type == TYPE_COMPARE)
9523 /* Floating point compare to branch latency is less than
9524 compare to conditional move. */
9525 if (dep_type == TYPE_FPCMP)
9534 /* Anti-dependencies only penalize the fpu unit. */
9535 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
9547 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
9551 case PROCESSOR_SUPERSPARC:
9552 cost = supersparc_adjust_cost (insn, link, dep, cost);
9554 case PROCESSOR_HYPERSPARC:
9555 case PROCESSOR_SPARCLITE86X:
9556 cost = hypersparc_adjust_cost (insn, link, dep, cost);
9565 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
9566 int sched_verbose ATTRIBUTE_UNUSED,
9567 int max_ready ATTRIBUTE_UNUSED)
9571 sparc_use_sched_lookahead (void)
9573 if (sparc_cpu == PROCESSOR_NIAGARA
9574 || sparc_cpu == PROCESSOR_NIAGARA2
9575 || sparc_cpu == PROCESSOR_NIAGARA3)
9577 if (sparc_cpu == PROCESSOR_NIAGARA4)
9579 if (sparc_cpu == PROCESSOR_ULTRASPARC
9580 || sparc_cpu == PROCESSOR_ULTRASPARC3)
9582 if ((1 << sparc_cpu) &
9583 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
9584 (1 << PROCESSOR_SPARCLITE86X)))
9590 sparc_issue_rate (void)
9594 case PROCESSOR_NIAGARA:
9595 case PROCESSOR_NIAGARA2:
9596 case PROCESSOR_NIAGARA3:
9599 case PROCESSOR_NIAGARA4:
9601 /* Assume V9 processors are capable of at least dual-issue. */
9603 case PROCESSOR_SUPERSPARC:
9605 case PROCESSOR_HYPERSPARC:
9606 case PROCESSOR_SPARCLITE86X:
9608 case PROCESSOR_ULTRASPARC:
9609 case PROCESSOR_ULTRASPARC3:
9615 set_extends (rtx insn)
9617 register rtx pat = PATTERN (insn);
9619 switch (GET_CODE (SET_SRC (pat)))
9621 /* Load and some shift instructions zero extend. */
9624 /* sethi clears the high bits */
9626 /* LO_SUM is used with sethi. sethi cleared the high
9627 bits and the values used with lo_sum are positive */
9629 /* Store flag stores 0 or 1 */
9639 rtx op0 = XEXP (SET_SRC (pat), 0);
9640 rtx op1 = XEXP (SET_SRC (pat), 1);
9641 if (GET_CODE (op1) == CONST_INT)
9642 return INTVAL (op1) >= 0;
9643 if (GET_CODE (op0) != REG)
9645 if (sparc_check_64 (op0, insn) == 1)
9647 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
9652 rtx op0 = XEXP (SET_SRC (pat), 0);
9653 rtx op1 = XEXP (SET_SRC (pat), 1);
9654 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
9656 if (GET_CODE (op1) == CONST_INT)
9657 return INTVAL (op1) >= 0;
9658 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
9661 return GET_MODE (SET_SRC (pat)) == SImode;
9662 /* Positive integers leave the high bits zero. */
9664 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
9666 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
9669 return - (GET_MODE (SET_SRC (pat)) == SImode);
9671 return sparc_check_64 (SET_SRC (pat), insn);
9677 /* We _ought_ to have only one kind per function, but... */
9678 static GTY(()) rtx sparc_addr_diff_list;
9679 static GTY(()) rtx sparc_addr_list;
9682 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
9684 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9686 sparc_addr_diff_list
9687 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
9689 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
9693 sparc_output_addr_vec (rtx vec)
9695 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
9696 int idx, vlen = XVECLEN (body, 0);
9698 #ifdef ASM_OUTPUT_ADDR_VEC_START
9699 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
9702 #ifdef ASM_OUTPUT_CASE_LABEL
9703 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
9706 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
9709 for (idx = 0; idx < vlen; idx++)
9711 ASM_OUTPUT_ADDR_VEC_ELT
9712 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9715 #ifdef ASM_OUTPUT_ADDR_VEC_END
9716 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
9721 sparc_output_addr_diff_vec (rtx vec)
9723 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
9724 rtx base = XEXP (XEXP (body, 0), 0);
9725 int idx, vlen = XVECLEN (body, 1);
9727 #ifdef ASM_OUTPUT_ADDR_VEC_START
9728 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
9731 #ifdef ASM_OUTPUT_CASE_LABEL
9732 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
9735 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
9738 for (idx = 0; idx < vlen; idx++)
9740 ASM_OUTPUT_ADDR_DIFF_ELT
9743 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
9744 CODE_LABEL_NUMBER (base));
9747 #ifdef ASM_OUTPUT_ADDR_VEC_END
9748 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
9753 sparc_output_deferred_case_vectors (void)
9758 if (sparc_addr_list == NULL_RTX
9759 && sparc_addr_diff_list == NULL_RTX)
9762 /* Align to cache line in the function's code section. */
9763 switch_to_section (current_function_section ());
9765 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9767 ASM_OUTPUT_ALIGN (asm_out_file, align);
9769 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
9770 sparc_output_addr_vec (XEXP (t, 0));
9771 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
9772 sparc_output_addr_diff_vec (XEXP (t, 0));
9774 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
9777 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9778 unknown. Return 1 if the high bits are zero, -1 if the register is
9781 sparc_check_64 (rtx x, rtx insn)
9783 /* If a register is set only once it is safe to ignore insns this
9784 code does not know how to handle. The loop will either recognize
9785 the single set and return the correct value or fail to recognize
9790 gcc_assert (GET_CODE (x) == REG);
9792 if (GET_MODE (x) == DImode)
9793 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
9795 if (flag_expensive_optimizations
9796 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
9802 insn = get_last_insn_anywhere ();
9807 while ((insn = PREV_INSN (insn)))
9809 switch (GET_CODE (insn))
9822 rtx pat = PATTERN (insn);
9823 if (GET_CODE (pat) != SET)
9825 if (rtx_equal_p (x, SET_DEST (pat)))
9826 return set_extends (insn);
9827 if (y && rtx_equal_p (y, SET_DEST (pat)))
9828 return set_extends (insn);
9829 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
9837 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9838 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9841 output_v8plus_shift (rtx insn, rtx *operands, const char *opcode)
9843 static char asm_code[60];
9845 /* The scratch register is only required when the destination
9846 register is not a 64-bit global or out register. */
9847 if (which_alternative != 2)
9848 operands[3] = operands[0];
9850 /* We can only shift by constants <= 63. */
9851 if (GET_CODE (operands[2]) == CONST_INT)
9852 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
9854 if (GET_CODE (operands[1]) == CONST_INT)
9856 output_asm_insn ("mov\t%1, %3", operands);
9860 output_asm_insn ("sllx\t%H1, 32, %3", operands);
9861 if (sparc_check_64 (operands[1], insn) <= 0)
9862 output_asm_insn ("srl\t%L1, 0, %L1", operands);
9863 output_asm_insn ("or\t%L1, %3, %3", operands);
9866 strcpy (asm_code, opcode);
9868 if (which_alternative != 2)
9869 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9872 strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9875 /* Output rtl to increment the profiler label LABELNO
9876 for profiling a function entry. */
9879 sparc_profile_hook (int labelno)
9884 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
9885 if (NO_PROFILE_COUNTERS)
9887 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
9891 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9892 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9893 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
9897 #ifdef TARGET_SOLARIS
9898 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9901 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
9902 tree decl ATTRIBUTE_UNUSED)
9904 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
9906 solaris_elf_asm_comdat_section (name, flags, decl);
9910 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
9912 if (!(flags & SECTION_DEBUG))
9913 fputs (",#alloc", asm_out_file);
9914 if (flags & SECTION_WRITE)
9915 fputs (",#write", asm_out_file);
9916 if (flags & SECTION_TLS)
9917 fputs (",#tls", asm_out_file);
9918 if (flags & SECTION_CODE)
9919 fputs (",#execinstr", asm_out_file);
9921 /* Sun as only supports #nobits/#progbits since Solaris 10. */
9922 if (HAVE_AS_SPARC_NOBITS)
9924 if (flags & SECTION_BSS)
9925 fputs (",#nobits", asm_out_file);
9927 fputs (",#progbits", asm_out_file);
9930 fputc ('\n', asm_out_file);
9932 #endif /* TARGET_SOLARIS */
9934 /* We do not allow indirect calls to be optimized into sibling calls.
9936 We cannot use sibling calls when delayed branches are disabled
9937 because they will likely require the call delay slot to be filled.
9939 Also, on SPARC 32-bit we cannot emit a sibling call when the
9940 current function returns a structure. This is because the "unimp
9941 after call" convention would cause the callee to return to the
9942 wrong place. The generic code already disallows cases where the
9943 function being called returns a structure.
9945 It may seem strange how this last case could occur. Usually there
9946 is code after the call which jumps to epilogue code which dumps the
9947 return value into the struct return area. That ought to invalidate
9948 the sibling call right? Well, in the C++ case we can end up passing
9949 the pointer to the struct return area to a constructor (which returns
9950 void) and then nothing else happens. Such a sibling call would look
9951 valid without the added check here.
9953 VxWorks PIC PLT entries require the global pointer to be initialized
9954 on entry. We therefore can't emit sibling calls to them. */
9956 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9959 && flag_delayed_branch
9960 && (TARGET_ARCH64 || ! cfun->returns_struct)
9961 && !(TARGET_VXWORKS_RTP
9963 && !targetm.binds_local_p (decl)));
9966 /* libfunc renaming. */
9969 sparc_init_libfuncs (void)
9973 /* Use the subroutines that Sun's library provides for integer
9974 multiply and divide. The `*' prevents an underscore from
9975 being prepended by the compiler. .umul is a little faster
9977 set_optab_libfunc (smul_optab, SImode, "*.umul");
9978 set_optab_libfunc (sdiv_optab, SImode, "*.div");
9979 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
9980 set_optab_libfunc (smod_optab, SImode, "*.rem");
9981 set_optab_libfunc (umod_optab, SImode, "*.urem");
9983 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9984 set_optab_libfunc (add_optab, TFmode, "_Q_add");
9985 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
9986 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
9987 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
9988 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
9990 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9991 is because with soft-float, the SFmode and DFmode sqrt
9992 instructions will be absent, and the compiler will notice and
9993 try to use the TFmode sqrt instruction for calls to the
9994 builtin function sqrt, but this fails. */
9996 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
9998 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
9999 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
10000 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
10001 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
10002 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
10003 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
10005 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
10006 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
10007 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
10008 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
10010 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
10011 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
10012 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
10013 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
10015 if (DITF_CONVERSION_LIBFUNCS)
10017 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
10018 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
10019 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
10020 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
10023 if (SUN_CONVERSION_LIBFUNCS)
10025 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
10026 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
10027 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
10028 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
10033 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10034 do not exist in the library. Make sure the compiler does not
10035 emit calls to them by accident. (It should always use the
10036 hardware instructions.) */
10037 set_optab_libfunc (smul_optab, SImode, 0);
10038 set_optab_libfunc (sdiv_optab, SImode, 0);
10039 set_optab_libfunc (udiv_optab, SImode, 0);
10040 set_optab_libfunc (smod_optab, SImode, 0);
10041 set_optab_libfunc (umod_optab, SImode, 0);
10043 if (SUN_INTEGER_MULTIPLY_64)
10045 set_optab_libfunc (smul_optab, DImode, "__mul64");
10046 set_optab_libfunc (sdiv_optab, DImode, "__div64");
10047 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
10048 set_optab_libfunc (smod_optab, DImode, "__rem64");
10049 set_optab_libfunc (umod_optab, DImode, "__urem64");
10052 if (SUN_CONVERSION_LIBFUNCS)
10054 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
10055 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
10056 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
10057 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
10062 /* SPARC builtins. */
10063 enum sparc_builtins
10065 /* FPU builtins. */
10066 SPARC_BUILTIN_LDFSR,
10067 SPARC_BUILTIN_STFSR,
10069 /* VIS 1.0 builtins. */
10070 SPARC_BUILTIN_FPACK16,
10071 SPARC_BUILTIN_FPACK32,
10072 SPARC_BUILTIN_FPACKFIX,
10073 SPARC_BUILTIN_FEXPAND,
10074 SPARC_BUILTIN_FPMERGE,
10075 SPARC_BUILTIN_FMUL8X16,
10076 SPARC_BUILTIN_FMUL8X16AU,
10077 SPARC_BUILTIN_FMUL8X16AL,
10078 SPARC_BUILTIN_FMUL8SUX16,
10079 SPARC_BUILTIN_FMUL8ULX16,
10080 SPARC_BUILTIN_FMULD8SUX16,
10081 SPARC_BUILTIN_FMULD8ULX16,
10082 SPARC_BUILTIN_FALIGNDATAV4HI,
10083 SPARC_BUILTIN_FALIGNDATAV8QI,
10084 SPARC_BUILTIN_FALIGNDATAV2SI,
10085 SPARC_BUILTIN_FALIGNDATADI,
10086 SPARC_BUILTIN_WRGSR,
10087 SPARC_BUILTIN_RDGSR,
10088 SPARC_BUILTIN_ALIGNADDR,
10089 SPARC_BUILTIN_ALIGNADDRL,
10090 SPARC_BUILTIN_PDIST,
10091 SPARC_BUILTIN_EDGE8,
10092 SPARC_BUILTIN_EDGE8L,
10093 SPARC_BUILTIN_EDGE16,
10094 SPARC_BUILTIN_EDGE16L,
10095 SPARC_BUILTIN_EDGE32,
10096 SPARC_BUILTIN_EDGE32L,
10097 SPARC_BUILTIN_FCMPLE16,
10098 SPARC_BUILTIN_FCMPLE32,
10099 SPARC_BUILTIN_FCMPNE16,
10100 SPARC_BUILTIN_FCMPNE32,
10101 SPARC_BUILTIN_FCMPGT16,
10102 SPARC_BUILTIN_FCMPGT32,
10103 SPARC_BUILTIN_FCMPEQ16,
10104 SPARC_BUILTIN_FCMPEQ32,
10105 SPARC_BUILTIN_FPADD16,
10106 SPARC_BUILTIN_FPADD16S,
10107 SPARC_BUILTIN_FPADD32,
10108 SPARC_BUILTIN_FPADD32S,
10109 SPARC_BUILTIN_FPSUB16,
10110 SPARC_BUILTIN_FPSUB16S,
10111 SPARC_BUILTIN_FPSUB32,
10112 SPARC_BUILTIN_FPSUB32S,
10113 SPARC_BUILTIN_ARRAY8,
10114 SPARC_BUILTIN_ARRAY16,
10115 SPARC_BUILTIN_ARRAY32,
10117 /* VIS 2.0 builtins. */
10118 SPARC_BUILTIN_EDGE8N,
10119 SPARC_BUILTIN_EDGE8LN,
10120 SPARC_BUILTIN_EDGE16N,
10121 SPARC_BUILTIN_EDGE16LN,
10122 SPARC_BUILTIN_EDGE32N,
10123 SPARC_BUILTIN_EDGE32LN,
10124 SPARC_BUILTIN_BMASK,
10125 SPARC_BUILTIN_BSHUFFLEV4HI,
10126 SPARC_BUILTIN_BSHUFFLEV8QI,
10127 SPARC_BUILTIN_BSHUFFLEV2SI,
10128 SPARC_BUILTIN_BSHUFFLEDI,
10130 /* VIS 3.0 builtins. */
10131 SPARC_BUILTIN_CMASK8,
10132 SPARC_BUILTIN_CMASK16,
10133 SPARC_BUILTIN_CMASK32,
10134 SPARC_BUILTIN_FCHKSM16,
10135 SPARC_BUILTIN_FSLL16,
10136 SPARC_BUILTIN_FSLAS16,
10137 SPARC_BUILTIN_FSRL16,
10138 SPARC_BUILTIN_FSRA16,
10139 SPARC_BUILTIN_FSLL32,
10140 SPARC_BUILTIN_FSLAS32,
10141 SPARC_BUILTIN_FSRL32,
10142 SPARC_BUILTIN_FSRA32,
10143 SPARC_BUILTIN_PDISTN,
10144 SPARC_BUILTIN_FMEAN16,
10145 SPARC_BUILTIN_FPADD64,
10146 SPARC_BUILTIN_FPSUB64,
10147 SPARC_BUILTIN_FPADDS16,
10148 SPARC_BUILTIN_FPADDS16S,
10149 SPARC_BUILTIN_FPSUBS16,
10150 SPARC_BUILTIN_FPSUBS16S,
10151 SPARC_BUILTIN_FPADDS32,
10152 SPARC_BUILTIN_FPADDS32S,
10153 SPARC_BUILTIN_FPSUBS32,
10154 SPARC_BUILTIN_FPSUBS32S,
10155 SPARC_BUILTIN_FUCMPLE8,
10156 SPARC_BUILTIN_FUCMPNE8,
10157 SPARC_BUILTIN_FUCMPGT8,
10158 SPARC_BUILTIN_FUCMPEQ8,
10159 SPARC_BUILTIN_FHADDS,
10160 SPARC_BUILTIN_FHADDD,
10161 SPARC_BUILTIN_FHSUBS,
10162 SPARC_BUILTIN_FHSUBD,
10163 SPARC_BUILTIN_FNHADDS,
10164 SPARC_BUILTIN_FNHADDD,
10165 SPARC_BUILTIN_UMULXHI,
10166 SPARC_BUILTIN_XMULX,
10167 SPARC_BUILTIN_XMULXHI,
10172 static GTY (()) tree sparc_builtins[(int) SPARC_BUILTIN_MAX];
10173 static enum insn_code sparc_builtins_icode[(int) SPARC_BUILTIN_MAX];
10175 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10176 function decl or NULL_TREE if the builtin was not added. */
10179 def_builtin (const char *name, enum insn_code icode, enum sparc_builtins code,
10183 = add_builtin_function (name, type, code, BUILT_IN_MD, NULL, NULL_TREE);
10187 sparc_builtins[code] = t;
10188 sparc_builtins_icode[code] = icode;
10194 /* Likewise, but also marks the function as "const". */
10197 def_builtin_const (const char *name, enum insn_code icode,
10198 enum sparc_builtins code, tree type)
10200 tree t = def_builtin (name, icode, code, type);
10203 TREE_READONLY (t) = 1;
10208 /* Implement the TARGET_INIT_BUILTINS target hook.
10209 Create builtin functions for special SPARC instructions. */
10212 sparc_init_builtins (void)
10215 sparc_fpu_init_builtins ();
10218 sparc_vis_init_builtins ();
10221 /* Create builtin functions for FPU instructions. */
10224 sparc_fpu_init_builtins (void)
10227 = build_function_type_list (void_type_node,
10228 build_pointer_type (unsigned_type_node), 0);
10229 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr,
10230 SPARC_BUILTIN_LDFSR, ftype);
10231 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr,
10232 SPARC_BUILTIN_STFSR, ftype);
10235 /* Create builtin functions for VIS instructions. */
10238 sparc_vis_init_builtins (void)
10240 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
10241 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
10242 tree v4hi = build_vector_type (intHI_type_node, 4);
10243 tree v2hi = build_vector_type (intHI_type_node, 2);
10244 tree v2si = build_vector_type (intSI_type_node, 2);
10245 tree v1si = build_vector_type (intSI_type_node, 1);
10247 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
10248 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
10249 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
10250 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
10251 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
10252 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
10253 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
10254 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
10255 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
10256 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
10257 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
10258 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
10259 tree v2hi_ftype_v2hi_v2hi = build_function_type_list (v2hi, v2hi, v2hi, 0);
10260 tree v1si_ftype_v1si_v1si = build_function_type_list (v1si, v1si, v1si, 0);
10261 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
10263 intDI_type_node, 0);
10264 tree di_ftype_v8qi_v8qi = build_function_type_list (intDI_type_node,
10266 tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node,
10268 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
10270 intDI_type_node, 0);
10271 tree si_ftype_si_si = build_function_type_list (intSI_type_node,
10273 intSI_type_node, 0);
10274 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
10276 intSI_type_node, 0);
10277 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
10279 intDI_type_node, 0);
10280 tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
10283 tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node,
10286 tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node,
10288 tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
10290 tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node,
10292 tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node,
10294 tree void_ftype_di = build_function_type_list (void_type_node,
10295 intDI_type_node, 0);
10296 tree di_ftype_void = build_function_type_list (intDI_type_node,
10297 void_type_node, 0);
10298 tree void_ftype_si = build_function_type_list (void_type_node,
10299 intSI_type_node, 0);
10300 tree sf_ftype_sf_sf = build_function_type_list (float_type_node,
10302 float_type_node, 0);
10303 tree df_ftype_df_df = build_function_type_list (double_type_node,
10305 double_type_node, 0);
10307 /* Packing and expanding vectors. */
10308 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
10309 SPARC_BUILTIN_FPACK16, v4qi_ftype_v4hi);
10310 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
10311 SPARC_BUILTIN_FPACK32, v8qi_ftype_v2si_v8qi);
10312 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
10313 SPARC_BUILTIN_FPACKFIX, v2hi_ftype_v2si);
10314 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
10315 SPARC_BUILTIN_FEXPAND, v4hi_ftype_v4qi);
10316 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
10317 SPARC_BUILTIN_FPMERGE, v8qi_ftype_v4qi_v4qi);
10319 /* Multiplications. */
10320 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
10321 SPARC_BUILTIN_FMUL8X16, v4hi_ftype_v4qi_v4hi);
10322 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
10323 SPARC_BUILTIN_FMUL8X16AU, v4hi_ftype_v4qi_v2hi);
10324 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
10325 SPARC_BUILTIN_FMUL8X16AL, v4hi_ftype_v4qi_v2hi);
10326 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
10327 SPARC_BUILTIN_FMUL8SUX16, v4hi_ftype_v8qi_v4hi);
10328 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
10329 SPARC_BUILTIN_FMUL8ULX16, v4hi_ftype_v8qi_v4hi);
10330 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
10331 SPARC_BUILTIN_FMULD8SUX16, v2si_ftype_v4qi_v2hi);
10332 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
10333 SPARC_BUILTIN_FMULD8ULX16, v2si_ftype_v4qi_v2hi);
10335 /* Data aligning. */
10336 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
10337 SPARC_BUILTIN_FALIGNDATAV4HI, v4hi_ftype_v4hi_v4hi);
10338 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
10339 SPARC_BUILTIN_FALIGNDATAV8QI, v8qi_ftype_v8qi_v8qi);
10340 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
10341 SPARC_BUILTIN_FALIGNDATAV2SI, v2si_ftype_v2si_v2si);
10342 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis,
10343 SPARC_BUILTIN_FALIGNDATADI, di_ftype_di_di);
10345 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis,
10346 SPARC_BUILTIN_WRGSR, void_ftype_di);
10347 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis,
10348 SPARC_BUILTIN_RDGSR, di_ftype_void);
10352 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
10353 SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_di);
10354 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
10355 SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_di);
10359 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
10360 SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_si);
10361 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
10362 SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_si);
10365 /* Pixel distance. */
10366 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
10367 SPARC_BUILTIN_PDIST, di_ftype_v8qi_v8qi_di);
10369 /* Edge handling. */
10372 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis,
10373 SPARC_BUILTIN_EDGE8, di_ftype_ptr_ptr);
10374 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis,
10375 SPARC_BUILTIN_EDGE8L, di_ftype_ptr_ptr);
10376 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis,
10377 SPARC_BUILTIN_EDGE16, di_ftype_ptr_ptr);
10378 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis,
10379 SPARC_BUILTIN_EDGE16L, di_ftype_ptr_ptr);
10380 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis,
10381 SPARC_BUILTIN_EDGE32, di_ftype_ptr_ptr);
10382 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis,
10383 SPARC_BUILTIN_EDGE32L, di_ftype_ptr_ptr);
10387 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis,
10388 SPARC_BUILTIN_EDGE8, si_ftype_ptr_ptr);
10389 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis,
10390 SPARC_BUILTIN_EDGE8L, si_ftype_ptr_ptr);
10391 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis,
10392 SPARC_BUILTIN_EDGE16, si_ftype_ptr_ptr);
10393 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis,
10394 SPARC_BUILTIN_EDGE16L, si_ftype_ptr_ptr);
10395 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis,
10396 SPARC_BUILTIN_EDGE32, si_ftype_ptr_ptr);
10397 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis,
10398 SPARC_BUILTIN_EDGE32L, si_ftype_ptr_ptr);
10401 /* Pixel compare. */
10404 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis,
10405 SPARC_BUILTIN_FCMPLE16, di_ftype_v4hi_v4hi);
10406 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis,
10407 SPARC_BUILTIN_FCMPLE32, di_ftype_v2si_v2si);
10408 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis,
10409 SPARC_BUILTIN_FCMPNE16, di_ftype_v4hi_v4hi);
10410 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis,
10411 SPARC_BUILTIN_FCMPNE32, di_ftype_v2si_v2si);
10412 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis,
10413 SPARC_BUILTIN_FCMPGT16, di_ftype_v4hi_v4hi);
10414 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis,
10415 SPARC_BUILTIN_FCMPGT32, di_ftype_v2si_v2si);
10416 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis,
10417 SPARC_BUILTIN_FCMPEQ16, di_ftype_v4hi_v4hi);
10418 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis,
10419 SPARC_BUILTIN_FCMPEQ32, di_ftype_v2si_v2si);
10423 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis,
10424 SPARC_BUILTIN_FCMPLE16, si_ftype_v4hi_v4hi);
10425 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis,
10426 SPARC_BUILTIN_FCMPLE32, si_ftype_v2si_v2si);
10427 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis,
10428 SPARC_BUILTIN_FCMPNE16, si_ftype_v4hi_v4hi);
10429 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis,
10430 SPARC_BUILTIN_FCMPNE32, si_ftype_v2si_v2si);
10431 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis,
10432 SPARC_BUILTIN_FCMPGT16, si_ftype_v4hi_v4hi);
10433 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis,
10434 SPARC_BUILTIN_FCMPGT32, si_ftype_v2si_v2si);
10435 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis,
10436 SPARC_BUILTIN_FCMPEQ16, si_ftype_v4hi_v4hi);
10437 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis,
10438 SPARC_BUILTIN_FCMPEQ32, si_ftype_v2si_v2si);
10441 /* Addition and subtraction. */
10442 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3,
10443 SPARC_BUILTIN_FPADD16, v4hi_ftype_v4hi_v4hi);
10444 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3,
10445 SPARC_BUILTIN_FPADD16S, v2hi_ftype_v2hi_v2hi);
10446 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3,
10447 SPARC_BUILTIN_FPADD32, v2si_ftype_v2si_v2si);
10448 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3,
10449 SPARC_BUILTIN_FPADD32S, v1si_ftype_v1si_v1si);
10450 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3,
10451 SPARC_BUILTIN_FPSUB16, v4hi_ftype_v4hi_v4hi);
10452 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3,
10453 SPARC_BUILTIN_FPSUB16S, v2hi_ftype_v2hi_v2hi);
10454 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3,
10455 SPARC_BUILTIN_FPSUB32, v2si_ftype_v2si_v2si);
10456 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3,
10457 SPARC_BUILTIN_FPSUB32S, v1si_ftype_v1si_v1si);
10459 /* Three-dimensional array addressing. */
10462 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis,
10463 SPARC_BUILTIN_ARRAY8, di_ftype_di_di);
10464 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis,
10465 SPARC_BUILTIN_ARRAY16, di_ftype_di_di);
10466 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis,
10467 SPARC_BUILTIN_ARRAY32, di_ftype_di_di);
10471 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis,
10472 SPARC_BUILTIN_ARRAY8, si_ftype_si_si);
10473 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis,
10474 SPARC_BUILTIN_ARRAY16, si_ftype_si_si);
10475 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis,
10476 SPARC_BUILTIN_ARRAY32, si_ftype_si_si);
10481 /* Edge handling. */
10484 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis,
10485 SPARC_BUILTIN_EDGE8N, di_ftype_ptr_ptr);
10486 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis,
10487 SPARC_BUILTIN_EDGE8LN, di_ftype_ptr_ptr);
10488 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis,
10489 SPARC_BUILTIN_EDGE16N, di_ftype_ptr_ptr);
10490 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis,
10491 SPARC_BUILTIN_EDGE16LN, di_ftype_ptr_ptr);
10492 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis,
10493 SPARC_BUILTIN_EDGE32N, di_ftype_ptr_ptr);
10494 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis,
10495 SPARC_BUILTIN_EDGE32LN, di_ftype_ptr_ptr);
10499 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis,
10500 SPARC_BUILTIN_EDGE8N, si_ftype_ptr_ptr);
10501 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis,
10502 SPARC_BUILTIN_EDGE8LN, si_ftype_ptr_ptr);
10503 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis,
10504 SPARC_BUILTIN_EDGE16N, si_ftype_ptr_ptr);
10505 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis,
10506 SPARC_BUILTIN_EDGE16LN, si_ftype_ptr_ptr);
10507 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis,
10508 SPARC_BUILTIN_EDGE32N, si_ftype_ptr_ptr);
10509 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis,
10510 SPARC_BUILTIN_EDGE32LN, si_ftype_ptr_ptr);
10513 /* Byte mask and shuffle. */
10515 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis,
10516 SPARC_BUILTIN_BMASK, di_ftype_di_di);
10518 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis,
10519 SPARC_BUILTIN_BMASK, si_ftype_si_si);
10520 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis,
10521 SPARC_BUILTIN_BSHUFFLEV4HI, v4hi_ftype_v4hi_v4hi);
10522 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis,
10523 SPARC_BUILTIN_BSHUFFLEV8QI, v8qi_ftype_v8qi_v8qi);
10524 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis,
10525 SPARC_BUILTIN_BSHUFFLEV2SI, v2si_ftype_v2si_v2si);
10526 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis,
10527 SPARC_BUILTIN_BSHUFFLEDI, di_ftype_di_di);
10534 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis,
10535 SPARC_BUILTIN_CMASK8, void_ftype_di);
10536 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis,
10537 SPARC_BUILTIN_CMASK16, void_ftype_di);
10538 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis,
10539 SPARC_BUILTIN_CMASK32, void_ftype_di);
10543 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis,
10544 SPARC_BUILTIN_CMASK8, void_ftype_si);
10545 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis,
10546 SPARC_BUILTIN_CMASK16, void_ftype_si);
10547 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis,
10548 SPARC_BUILTIN_CMASK32, void_ftype_si);
10551 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis,
10552 SPARC_BUILTIN_FCHKSM16, v4hi_ftype_v4hi_v4hi);
10554 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3,
10555 SPARC_BUILTIN_FSLL16, v4hi_ftype_v4hi_v4hi);
10556 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3,
10557 SPARC_BUILTIN_FSLAS16, v4hi_ftype_v4hi_v4hi);
10558 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3,
10559 SPARC_BUILTIN_FSRL16, v4hi_ftype_v4hi_v4hi);
10560 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3,
10561 SPARC_BUILTIN_FSRA16, v4hi_ftype_v4hi_v4hi);
10562 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3,
10563 SPARC_BUILTIN_FSLL32, v2si_ftype_v2si_v2si);
10564 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3,
10565 SPARC_BUILTIN_FSLAS32, v2si_ftype_v2si_v2si);
10566 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3,
10567 SPARC_BUILTIN_FSRL32, v2si_ftype_v2si_v2si);
10568 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3,
10569 SPARC_BUILTIN_FSRA32, v2si_ftype_v2si_v2si);
10572 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis,
10573 SPARC_BUILTIN_PDISTN, di_ftype_v8qi_v8qi);
10575 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis,
10576 SPARC_BUILTIN_PDISTN, si_ftype_v8qi_v8qi);
10578 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis,
10579 SPARC_BUILTIN_FMEAN16, v4hi_ftype_v4hi_v4hi);
10580 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis,
10581 SPARC_BUILTIN_FPADD64, di_ftype_di_di);
10582 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis,
10583 SPARC_BUILTIN_FPSUB64, di_ftype_di_di);
10585 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3,
10586 SPARC_BUILTIN_FPADDS16, v4hi_ftype_v4hi_v4hi);
10587 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3,
10588 SPARC_BUILTIN_FPADDS16S, v2hi_ftype_v2hi_v2hi);
10589 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3,
10590 SPARC_BUILTIN_FPSUBS16, v4hi_ftype_v4hi_v4hi);
10591 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3,
10592 SPARC_BUILTIN_FPSUBS16S, v2hi_ftype_v2hi_v2hi);
10593 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3,
10594 SPARC_BUILTIN_FPADDS32, v2si_ftype_v2si_v2si);
10595 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3,
10596 SPARC_BUILTIN_FPADDS32S, v1si_ftype_v1si_v1si);
10597 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3,
10598 SPARC_BUILTIN_FPSUBS32, v2si_ftype_v2si_v2si);
10599 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3,
10600 SPARC_BUILTIN_FPSUBS32S, v1si_ftype_v1si_v1si);
10604 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis,
10605 SPARC_BUILTIN_FUCMPLE8, di_ftype_v8qi_v8qi);
10606 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis,
10607 SPARC_BUILTIN_FUCMPNE8, di_ftype_v8qi_v8qi);
10608 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis,
10609 SPARC_BUILTIN_FUCMPGT8, di_ftype_v8qi_v8qi);
10610 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis,
10611 SPARC_BUILTIN_FUCMPEQ8, di_ftype_v8qi_v8qi);
10615 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis,
10616 SPARC_BUILTIN_FUCMPLE8, si_ftype_v8qi_v8qi);
10617 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis,
10618 SPARC_BUILTIN_FUCMPNE8, si_ftype_v8qi_v8qi);
10619 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis,
10620 SPARC_BUILTIN_FUCMPGT8, si_ftype_v8qi_v8qi);
10621 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis,
10622 SPARC_BUILTIN_FUCMPEQ8, si_ftype_v8qi_v8qi);
10625 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
10626 SPARC_BUILTIN_FHADDS, sf_ftype_sf_sf);
10627 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
10628 SPARC_BUILTIN_FHADDD, df_ftype_df_df);
10629 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
10630 SPARC_BUILTIN_FHSUBS, sf_ftype_sf_sf);
10631 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
10632 SPARC_BUILTIN_FHSUBD, df_ftype_df_df);
10633 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
10634 SPARC_BUILTIN_FNHADDS, sf_ftype_sf_sf);
10635 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
10636 SPARC_BUILTIN_FNHADDD, df_ftype_df_df);
10638 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
10639 SPARC_BUILTIN_UMULXHI, di_ftype_di_di);
10640 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
10641 SPARC_BUILTIN_XMULX, di_ftype_di_di);
10642 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
10643 SPARC_BUILTIN_XMULXHI, di_ftype_di_di);
10647 /* Implement TARGET_BUILTIN_DECL hook. */
10650 sparc_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10652 if (code >= SPARC_BUILTIN_MAX)
10653 return error_mark_node;
10655 return sparc_builtins[code];
10658 /* Implemented TARGET_EXPAND_BUILTIN hook. */
10661 sparc_expand_builtin (tree exp, rtx target,
10662 rtx subtarget ATTRIBUTE_UNUSED,
10663 enum machine_mode tmode ATTRIBUTE_UNUSED,
10664 int ignore ATTRIBUTE_UNUSED)
10666 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10667 enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl);
10668 enum insn_code icode = sparc_builtins_icode[code];
10669 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10670 call_expr_arg_iterator iter;
10677 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10679 || GET_MODE (target) != tmode
10680 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10681 op[0] = gen_reg_rtx (tmode);
10686 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10688 const struct insn_operand_data *insn_op;
10691 if (arg == error_mark_node)
10695 idx = arg_count - !nonvoid;
10696 insn_op = &insn_data[icode].operand[idx];
10697 op[arg_count] = expand_normal (arg);
10699 if (code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR)
10701 if (!address_operand (op[arg_count], SImode))
10703 op[arg_count] = convert_memory_address (Pmode, op[arg_count]);
10704 op[arg_count] = copy_addr_to_reg (op[arg_count]);
10706 op[arg_count] = gen_rtx_MEM (SImode, op[arg_count]);
10709 else if (insn_op->mode == V1DImode
10710 && GET_MODE (op[arg_count]) == DImode)
10711 op[arg_count] = gen_lowpart (V1DImode, op[arg_count]);
10713 else if (insn_op->mode == V1SImode
10714 && GET_MODE (op[arg_count]) == SImode)
10715 op[arg_count] = gen_lowpart (V1SImode, op[arg_count]);
10717 if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count],
10719 op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]);
10725 pat = GEN_FCN (icode) (op[0]);
10729 pat = GEN_FCN (icode) (op[0], op[1]);
10731 pat = GEN_FCN (icode) (op[1]);
10734 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
10737 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
10740 gcc_unreachable ();
10748 return (nonvoid ? op[0] : const0_rtx);
10751 /* Return the upper 16 bits of the 8x16 multiplication. */
10754 sparc_vis_mul8x16 (int e8, int e16)
10756 return (e8 * e16 + 128) / 256;
10759 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10760 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10763 sparc_handle_vis_mul8x16 (tree *n_elts, enum sparc_builtins fncode,
10764 tree inner_type, tree cst0, tree cst1)
10766 unsigned i, num = VECTOR_CST_NELTS (cst0);
10771 case SPARC_BUILTIN_FMUL8X16:
10772 for (i = 0; i < num; ++i)
10775 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)),
10776 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, i)));
10777 n_elts[i] = build_int_cst (inner_type, val);
10781 case SPARC_BUILTIN_FMUL8X16AU:
10782 scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 0));
10784 for (i = 0; i < num; ++i)
10787 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)),
10789 n_elts[i] = build_int_cst (inner_type, val);
10793 case SPARC_BUILTIN_FMUL8X16AL:
10794 scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 1));
10796 for (i = 0; i < num; ++i)
10799 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)),
10801 n_elts[i] = build_int_cst (inner_type, val);
10806 gcc_unreachable ();
10810 /* Implement TARGET_FOLD_BUILTIN hook.
10812 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10813 result of the function call is ignored. NULL_TREE is returned if the
10814 function could not be folded. */
10817 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
10818 tree *args, bool ignore)
10820 enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl);
10821 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
10822 tree arg0, arg1, arg2;
10827 case SPARC_BUILTIN_LDFSR:
10828 case SPARC_BUILTIN_STFSR:
10829 case SPARC_BUILTIN_ALIGNADDR:
10830 case SPARC_BUILTIN_WRGSR:
10831 case SPARC_BUILTIN_BMASK:
10832 case SPARC_BUILTIN_CMASK8:
10833 case SPARC_BUILTIN_CMASK16:
10834 case SPARC_BUILTIN_CMASK32:
10838 return build_zero_cst (rtype);
10843 case SPARC_BUILTIN_FEXPAND:
10847 if (TREE_CODE (arg0) == VECTOR_CST)
10849 tree inner_type = TREE_TYPE (rtype);
10853 n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0));
10854 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i)
10855 n_elts[i] = build_int_cst (inner_type,
10857 (VECTOR_CST_ELT (arg0, i)) << 4);
10858 return build_vector (rtype, n_elts);
10862 case SPARC_BUILTIN_FMUL8X16:
10863 case SPARC_BUILTIN_FMUL8X16AU:
10864 case SPARC_BUILTIN_FMUL8X16AL:
10870 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
10872 tree inner_type = TREE_TYPE (rtype);
10873 tree *n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0));
10874 sparc_handle_vis_mul8x16 (n_elts, code, inner_type, arg0, arg1);
10875 return build_vector (rtype, n_elts);
10879 case SPARC_BUILTIN_FPMERGE:
10885 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
10887 tree *n_elts = XALLOCAVEC (tree, 2 * VECTOR_CST_NELTS (arg0));
10889 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i)
10891 n_elts[2*i] = VECTOR_CST_ELT (arg0, i);
10892 n_elts[2*i+1] = VECTOR_CST_ELT (arg1, i);
10895 return build_vector (rtype, n_elts);
10899 case SPARC_BUILTIN_PDIST:
10900 case SPARC_BUILTIN_PDISTN:
10905 if (code == SPARC_BUILTIN_PDIST)
10911 arg2 = integer_zero_node;
10913 if (TREE_CODE (arg0) == VECTOR_CST
10914 && TREE_CODE (arg1) == VECTOR_CST
10915 && TREE_CODE (arg2) == INTEGER_CST)
10917 bool overflow = false;
10918 widest_int result = wi::to_widest (arg2);
10922 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i)
10924 tree e0 = VECTOR_CST_ELT (arg0, i);
10925 tree e1 = VECTOR_CST_ELT (arg1, i);
10927 bool neg1_ovf, neg2_ovf, add1_ovf, add2_ovf;
10929 tmp = wi::neg (wi::to_widest (e1), &neg1_ovf);
10930 tmp = wi::add (wi::to_widest (e0), tmp, SIGNED, &add1_ovf);
10931 if (wi::neg_p (tmp))
10932 tmp = wi::neg (tmp, &neg2_ovf);
10935 result = wi::add (result, tmp, SIGNED, &add2_ovf);
10936 overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf;
10939 gcc_assert (!overflow);
10941 return wide_int_to_tree (rtype, result);
10951 /* ??? This duplicates information provided to the compiler by the
10952 ??? scheduler description. Some day, teach genautomata to output
10953 ??? the latencies and then CSE will just use that. */
10956 sparc_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
10957 int *total, bool speed ATTRIBUTE_UNUSED)
10959 enum machine_mode mode = GET_MODE (x);
10960 bool float_mode_p = FLOAT_MODE_P (mode);
10965 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
10983 if (GET_MODE (x) == VOIDmode
10984 && ((CONST_DOUBLE_HIGH (x) == 0
10985 && CONST_DOUBLE_LOW (x) < 0x1000)
10986 || (CONST_DOUBLE_HIGH (x) == -1
10987 && CONST_DOUBLE_LOW (x) < 0
10988 && CONST_DOUBLE_LOW (x) >= -0x1000)))
10995 /* If outer-code was a sign or zero extension, a cost
10996 of COSTS_N_INSNS (1) was already added in. This is
10997 why we are subtracting it back out. */
10998 if (outer_code == ZERO_EXTEND)
11000 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
11002 else if (outer_code == SIGN_EXTEND)
11004 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
11006 else if (float_mode_p)
11008 *total = sparc_costs->float_load;
11012 *total = sparc_costs->int_load;
11020 *total = sparc_costs->float_plusminus;
11022 *total = COSTS_N_INSNS (1);
11029 gcc_assert (float_mode_p);
11030 *total = sparc_costs->float_mul;
11033 if (GET_CODE (sub) == NEG)
11034 sub = XEXP (sub, 0);
11035 *total += rtx_cost (sub, FMA, 0, speed);
11038 if (GET_CODE (sub) == NEG)
11039 sub = XEXP (sub, 0);
11040 *total += rtx_cost (sub, FMA, 2, speed);
11046 *total = sparc_costs->float_mul;
11047 else if (! TARGET_HARD_MUL)
11048 *total = COSTS_N_INSNS (25);
11054 if (sparc_costs->int_mul_bit_factor)
11058 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
11060 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
11061 for (nbits = 0; value != 0; value &= value - 1)
11064 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
11065 && GET_MODE (XEXP (x, 1)) == VOIDmode)
11067 rtx x1 = XEXP (x, 1);
11068 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
11069 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
11071 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
11073 for (; value2 != 0; value2 &= value2 - 1)
11081 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
11082 bit_cost = COSTS_N_INSNS (bit_cost);
11085 if (mode == DImode)
11086 *total = sparc_costs->int_mulX + bit_cost;
11088 *total = sparc_costs->int_mul + bit_cost;
11095 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
11104 if (mode == DFmode)
11105 *total = sparc_costs->float_div_df;
11107 *total = sparc_costs->float_div_sf;
11111 if (mode == DImode)
11112 *total = sparc_costs->int_divX;
11114 *total = sparc_costs->int_div;
11119 if (! float_mode_p)
11121 *total = COSTS_N_INSNS (1);
11128 case UNSIGNED_FLOAT:
11132 case FLOAT_TRUNCATE:
11133 *total = sparc_costs->float_move;
11137 if (mode == DFmode)
11138 *total = sparc_costs->float_sqrt_df;
11140 *total = sparc_costs->float_sqrt_sf;
11145 *total = sparc_costs->float_cmp;
11147 *total = COSTS_N_INSNS (1);
11152 *total = sparc_costs->float_cmove;
11154 *total = sparc_costs->int_cmove;
11158 /* Handle the NAND vector patterns. */
11159 if (sparc_vector_mode_supported_p (GET_MODE (x))
11160 && GET_CODE (XEXP (x, 0)) == NOT
11161 && GET_CODE (XEXP (x, 1)) == NOT)
11163 *total = COSTS_N_INSNS (1);
11174 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11177 general_or_i64_p (reg_class_t rclass)
11179 return (rclass == GENERAL_REGS || rclass == I64_REGS);
11182 /* Implement TARGET_REGISTER_MOVE_COST. */
11185 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11186 reg_class_t from, reg_class_t to)
11188 bool need_memory = false;
11190 if (from == FPCC_REGS || to == FPCC_REGS)
11191 need_memory = true;
11192 else if ((FP_REG_CLASS_P (from) && general_or_i64_p (to))
11193 || (general_or_i64_p (from) && FP_REG_CLASS_P (to)))
11197 int size = GET_MODE_SIZE (mode);
11198 if (size == 8 || size == 4)
11200 if (! TARGET_ARCH32 || size == 4)
11206 need_memory = true;
11211 if (sparc_cpu == PROCESSOR_ULTRASPARC
11212 || sparc_cpu == PROCESSOR_ULTRASPARC3
11213 || sparc_cpu == PROCESSOR_NIAGARA
11214 || sparc_cpu == PROCESSOR_NIAGARA2
11215 || sparc_cpu == PROCESSOR_NIAGARA3
11216 || sparc_cpu == PROCESSOR_NIAGARA4)
11225 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11226 This is achieved by means of a manual dynamic stack space allocation in
11227 the current frame. We make the assumption that SEQ doesn't contain any
11228 function calls, with the possible exception of calls to the GOT helper. */
11231 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
11233 /* We must preserve the lowest 16 words for the register save area. */
11234 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
11235 /* We really need only 2 words of fresh stack space. */
11236 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
11239 = gen_rtx_MEM (word_mode, plus_constant (Pmode, stack_pointer_rtx,
11240 SPARC_STACK_BIAS + offset));
11242 emit_insn (gen_stack_pointer_inc (GEN_INT (-size)));
11243 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
11245 emit_insn (gen_rtx_SET (VOIDmode,
11246 adjust_address (slot, word_mode, UNITS_PER_WORD),
11250 emit_insn (gen_rtx_SET (VOIDmode,
11252 adjust_address (slot, word_mode, UNITS_PER_WORD)));
11253 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
11254 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
11257 /* Output the assembler code for a thunk function. THUNK_DECL is the
11258 declaration for the thunk function itself, FUNCTION is the decl for
11259 the target function. DELTA is an immediate constant offset to be
11260 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11261 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11264 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11265 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11268 rtx this_rtx, insn, funexp;
11269 unsigned int int_arg_first;
11271 reload_completed = 1;
11272 epilogue_completed = 1;
11274 emit_note (NOTE_INSN_PROLOGUE_END);
11278 sparc_leaf_function_p = 1;
11280 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
11282 else if (flag_delayed_branch)
11284 /* We will emit a regular sibcall below, so we need to instruct
11285 output_sibcall that we are in a leaf function. */
11286 sparc_leaf_function_p = crtl->uses_only_leaf_regs = 1;
11288 /* This will cause final.c to invoke leaf_renumber_regs so we
11289 must behave as if we were in a not-yet-leafified function. */
11290 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
11294 /* We will emit the sibcall manually below, so we will need to
11295 manually spill non-leaf registers. */
11296 sparc_leaf_function_p = crtl->uses_only_leaf_regs = 0;
11298 /* We really are in a leaf function. */
11299 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
11302 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11303 returns a structure, the structure return pointer is there instead. */
11305 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11306 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
11308 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
11310 /* Add DELTA. When possible use a plain add, otherwise load it into
11311 a register first. */
11314 rtx delta_rtx = GEN_INT (delta);
11316 if (! SPARC_SIMM13_P (delta))
11318 rtx scratch = gen_rtx_REG (Pmode, 1);
11319 emit_move_insn (scratch, delta_rtx);
11320 delta_rtx = scratch;
11323 /* THIS_RTX += DELTA. */
11324 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
11327 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11330 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
11331 rtx scratch = gen_rtx_REG (Pmode, 1);
11333 gcc_assert (vcall_offset < 0);
11335 /* SCRATCH = *THIS_RTX. */
11336 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
11338 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11339 may not have any available scratch register at this point. */
11340 if (SPARC_SIMM13_P (vcall_offset))
11342 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11343 else if (! fixed_regs[5]
11344 /* The below sequence is made up of at least 2 insns,
11345 while the default method may need only one. */
11346 && vcall_offset < -8192)
11348 rtx scratch2 = gen_rtx_REG (Pmode, 5);
11349 emit_move_insn (scratch2, vcall_offset_rtx);
11350 vcall_offset_rtx = scratch2;
11354 rtx increment = GEN_INT (-4096);
11356 /* VCALL_OFFSET is a negative number whose typical range can be
11357 estimated as -32768..0 in 32-bit mode. In almost all cases
11358 it is therefore cheaper to emit multiple add insns than
11359 spilling and loading the constant into a register (at least
11361 while (! SPARC_SIMM13_P (vcall_offset))
11363 emit_insn (gen_add2_insn (scratch, increment));
11364 vcall_offset += 4096;
11366 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
11369 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11370 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
11371 gen_rtx_PLUS (Pmode,
11373 vcall_offset_rtx)));
11375 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11376 emit_insn (gen_add2_insn (this_rtx, scratch));
11379 /* Generate a tail call to the target function. */
11380 if (! TREE_USED (function))
11382 assemble_external (function);
11383 TREE_USED (function) = 1;
11385 funexp = XEXP (DECL_RTL (function), 0);
11387 if (flag_delayed_branch)
11389 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
11390 insn = emit_call_insn (gen_sibcall (funexp));
11391 SIBLING_CALL_P (insn) = 1;
11395 /* The hoops we have to jump through in order to generate a sibcall
11396 without using delay slots... */
11397 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
11401 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
11403 load_got_register (); /* clobbers %o7 */
11404 scratch = sparc_legitimize_pic_address (funexp, scratch);
11405 seq = get_insns ();
11407 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
11409 else if (TARGET_ARCH32)
11411 emit_insn (gen_rtx_SET (VOIDmode,
11413 gen_rtx_HIGH (SImode, funexp)));
11414 emit_insn (gen_rtx_SET (VOIDmode,
11416 gen_rtx_LO_SUM (SImode, scratch, funexp)));
11418 else /* TARGET_ARCH64 */
11420 switch (sparc_cmodel)
11424 /* The destination can serve as a temporary. */
11425 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
11430 /* The destination cannot serve as a temporary. */
11431 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
11433 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
11434 seq = get_insns ();
11436 emit_and_preserve (seq, spill_reg, 0);
11440 gcc_unreachable ();
11444 emit_jump_insn (gen_indirect_jump (scratch));
11449 /* Run just enough of rest_of_compilation to get the insns emitted.
11450 There's not really enough bulk here to make other passes such as
11451 instruction scheduling worth while. Note that use_thunk calls
11452 assemble_start_function and assemble_end_function. */
11453 insn = get_insns ();
11454 shorten_branches (insn);
11455 final_start_function (insn, file, 1);
11456 final (insn, file, 1);
11457 final_end_function ();
11459 reload_completed = 0;
11460 epilogue_completed = 0;
11463 /* Return true if sparc_output_mi_thunk would be able to output the
11464 assembler code for the thunk function specified by the arguments
11465 it is passed, and false otherwise. */
11467 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
11468 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
11469 HOST_WIDE_INT vcall_offset,
11470 const_tree function ATTRIBUTE_UNUSED)
11472 /* Bound the loop used in the default method above. */
11473 return (vcall_offset >= -32768 || ! fixed_regs[5]);
11476 /* How to allocate a 'struct machine_function'. */
11478 static struct machine_function *
11479 sparc_init_machine_status (void)
11481 return ggc_cleared_alloc<machine_function> ();
11484 /* Locate some local-dynamic symbol still in use by this function
11485 so that we can print its name in local-dynamic base patterns. */
11487 static const char *
11488 get_some_local_dynamic_name (void)
11492 if (cfun->machine->some_ld_name)
11493 return cfun->machine->some_ld_name;
11495 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11497 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11498 return cfun->machine->some_ld_name;
11500 gcc_unreachable ();
11504 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11509 && GET_CODE (x) == SYMBOL_REF
11510 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11512 cfun->machine->some_ld_name = XSTR (x, 0);
11519 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11520 We need to emit DTP-relative relocations. */
11523 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
11528 fputs ("\t.word\t%r_tls_dtpoff32(", file);
11531 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
11534 gcc_unreachable ();
11536 output_addr_const (file, x);
11540 /* Do whatever processing is required at the end of a file. */
11543 sparc_file_end (void)
11545 /* If we need to emit the special GOT helper function, do so now. */
11546 if (got_helper_rtx)
11548 const char *name = XSTR (got_helper_rtx, 0);
11549 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
11550 #ifdef DWARF2_UNWIND_INFO
11554 if (USE_HIDDEN_LINKONCE)
11556 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
11557 get_identifier (name),
11558 build_function_type_list (void_type_node,
11560 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
11561 NULL_TREE, void_type_node);
11562 TREE_PUBLIC (decl) = 1;
11563 TREE_STATIC (decl) = 1;
11564 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
11565 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
11566 DECL_VISIBILITY_SPECIFIED (decl) = 1;
11567 resolve_unique_section (decl, 0, flag_function_sections);
11568 allocate_struct_function (decl, true);
11569 cfun->is_thunk = 1;
11570 current_function_decl = decl;
11571 init_varasm_status ();
11572 assemble_start_function (decl, name);
11576 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
11577 switch_to_section (text_section);
11579 ASM_OUTPUT_ALIGN (asm_out_file, align);
11580 ASM_OUTPUT_LABEL (asm_out_file, name);
11583 #ifdef DWARF2_UNWIND_INFO
11584 do_cfi = dwarf2out_do_cfi_asm ();
11586 fprintf (asm_out_file, "\t.cfi_startproc\n");
11588 if (flag_delayed_branch)
11589 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11590 reg_name, reg_name);
11592 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11593 reg_name, reg_name);
11594 #ifdef DWARF2_UNWIND_INFO
11596 fprintf (asm_out_file, "\t.cfi_endproc\n");
11600 if (NEED_INDICATE_EXEC_STACK)
11601 file_end_indicate_exec_stack ();
11603 #ifdef TARGET_SOLARIS
11604 solaris_file_end ();
11608 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11609 /* Implement TARGET_MANGLE_TYPE. */
11611 static const char *
11612 sparc_mangle_type (const_tree type)
11615 && TYPE_MAIN_VARIANT (type) == long_double_type_node
11616 && TARGET_LONG_DOUBLE_128)
11619 /* For all other types, use normal C++ mangling. */
11624 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11625 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11626 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11629 sparc_emit_membar_for_model (enum memmodel model,
11630 int load_store, int before_after)
11632 /* Bits for the MEMBAR mmask field. */
11633 const int LoadLoad = 1;
11634 const int StoreLoad = 2;
11635 const int LoadStore = 4;
11636 const int StoreStore = 8;
11638 int mm = 0, implied = 0;
11640 switch (sparc_memory_model)
11643 /* Sequential Consistency. All memory transactions are immediately
11644 visible in sequential execution order. No barriers needed. */
11645 implied = LoadLoad | StoreLoad | LoadStore | StoreStore;
11649 /* Total Store Ordering: all memory transactions with store semantics
11650 are followed by an implied StoreStore. */
11651 implied |= StoreStore;
11653 /* If we're not looking for a raw barrer (before+after), then atomic
11654 operations get the benefit of being both load and store. */
11655 if (load_store == 3 && before_after == 1)
11656 implied |= StoreLoad;
11660 /* Partial Store Ordering: all memory transactions with load semantics
11661 are followed by an implied LoadLoad | LoadStore. */
11662 implied |= LoadLoad | LoadStore;
11664 /* If we're not looking for a raw barrer (before+after), then atomic
11665 operations get the benefit of being both load and store. */
11666 if (load_store == 3 && before_after == 2)
11667 implied |= StoreLoad | StoreStore;
11671 /* Relaxed Memory Ordering: no implicit bits. */
11675 gcc_unreachable ();
11678 if (before_after & 1)
11680 if (model == MEMMODEL_RELEASE
11681 || model == MEMMODEL_ACQ_REL
11682 || model == MEMMODEL_SEQ_CST)
11684 if (load_store & 1)
11685 mm |= LoadLoad | StoreLoad;
11686 if (load_store & 2)
11687 mm |= LoadStore | StoreStore;
11690 if (before_after & 2)
11692 if (model == MEMMODEL_ACQUIRE
11693 || model == MEMMODEL_ACQ_REL
11694 || model == MEMMODEL_SEQ_CST)
11696 if (load_store & 1)
11697 mm |= LoadLoad | LoadStore;
11698 if (load_store & 2)
11699 mm |= StoreLoad | StoreStore;
11703 /* Remove the bits implied by the system memory model. */
11706 /* For raw barriers (before+after), always emit a barrier.
11707 This will become a compile-time barrier if needed. */
11708 if (mm || before_after == 3)
11709 emit_insn (gen_membar (GEN_INT (mm)));
11712 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11713 compare and swap on the word containing the byte or half-word. */
11716 sparc_expand_compare_and_swap_12 (rtx bool_result, rtx result, rtx mem,
11717 rtx oldval, rtx newval)
11719 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
11720 rtx addr = gen_reg_rtx (Pmode);
11721 rtx off = gen_reg_rtx (SImode);
11722 rtx oldv = gen_reg_rtx (SImode);
11723 rtx newv = gen_reg_rtx (SImode);
11724 rtx oldvalue = gen_reg_rtx (SImode);
11725 rtx newvalue = gen_reg_rtx (SImode);
11726 rtx res = gen_reg_rtx (SImode);
11727 rtx resv = gen_reg_rtx (SImode);
11728 rtx memsi, val, mask, end_label, loop_label, cc;
11730 emit_insn (gen_rtx_SET (VOIDmode, addr,
11731 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
11733 if (Pmode != SImode)
11734 addr1 = gen_lowpart (SImode, addr1);
11735 emit_insn (gen_rtx_SET (VOIDmode, off,
11736 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
11738 memsi = gen_rtx_MEM (SImode, addr);
11739 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
11740 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
11742 val = copy_to_reg (memsi);
11744 emit_insn (gen_rtx_SET (VOIDmode, off,
11745 gen_rtx_XOR (SImode, off,
11746 GEN_INT (GET_MODE (mem) == QImode
11749 emit_insn (gen_rtx_SET (VOIDmode, off,
11750 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
11752 if (GET_MODE (mem) == QImode)
11753 mask = force_reg (SImode, GEN_INT (0xff));
11755 mask = force_reg (SImode, GEN_INT (0xffff));
11757 emit_insn (gen_rtx_SET (VOIDmode, mask,
11758 gen_rtx_ASHIFT (SImode, mask, off)));
11760 emit_insn (gen_rtx_SET (VOIDmode, val,
11761 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
11764 oldval = gen_lowpart (SImode, oldval);
11765 emit_insn (gen_rtx_SET (VOIDmode, oldv,
11766 gen_rtx_ASHIFT (SImode, oldval, off)));
11768 newval = gen_lowpart_common (SImode, newval);
11769 emit_insn (gen_rtx_SET (VOIDmode, newv,
11770 gen_rtx_ASHIFT (SImode, newval, off)));
11772 emit_insn (gen_rtx_SET (VOIDmode, oldv,
11773 gen_rtx_AND (SImode, oldv, mask)));
11775 emit_insn (gen_rtx_SET (VOIDmode, newv,
11776 gen_rtx_AND (SImode, newv, mask)));
11778 end_label = gen_label_rtx ();
11779 loop_label = gen_label_rtx ();
11780 emit_label (loop_label);
11782 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
11783 gen_rtx_IOR (SImode, oldv, val)));
11785 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
11786 gen_rtx_IOR (SImode, newv, val)));
11788 emit_move_insn (bool_result, const1_rtx);
11790 emit_insn (gen_atomic_compare_and_swapsi_1 (res, memsi, oldvalue, newvalue));
11792 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
11794 emit_insn (gen_rtx_SET (VOIDmode, resv,
11795 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
11798 emit_move_insn (bool_result, const0_rtx);
11800 cc = gen_compare_reg_1 (NE, resv, val);
11801 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
11803 /* Use cbranchcc4 to separate the compare and branch! */
11804 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
11805 cc, const0_rtx, loop_label));
11807 emit_label (end_label);
11809 emit_insn (gen_rtx_SET (VOIDmode, res,
11810 gen_rtx_AND (SImode, res, mask)));
11812 emit_insn (gen_rtx_SET (VOIDmode, res,
11813 gen_rtx_LSHIFTRT (SImode, res, off)));
11815 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
11818 /* Expand code to perform a compare-and-swap. */
11821 sparc_expand_compare_and_swap (rtx operands[])
11823 rtx bval, retval, mem, oldval, newval;
11824 enum machine_mode mode;
11825 enum memmodel model;
11827 bval = operands[0];
11828 retval = operands[1];
11830 oldval = operands[3];
11831 newval = operands[4];
11832 model = (enum memmodel) INTVAL (operands[6]);
11833 mode = GET_MODE (mem);
11835 sparc_emit_membar_for_model (model, 3, 1);
11837 if (reg_overlap_mentioned_p (retval, oldval))
11838 oldval = copy_to_reg (oldval);
11840 if (mode == QImode || mode == HImode)
11841 sparc_expand_compare_and_swap_12 (bval, retval, mem, oldval, newval);
11844 rtx (*gen) (rtx, rtx, rtx, rtx);
11847 if (mode == SImode)
11848 gen = gen_atomic_compare_and_swapsi_1;
11850 gen = gen_atomic_compare_and_swapdi_1;
11851 emit_insn (gen (retval, mem, oldval, newval));
11853 x = emit_store_flag (bval, EQ, retval, oldval, mode, 1, 1);
11855 convert_move (bval, x, 1);
11858 sparc_emit_membar_for_model (model, 3, 2);
11862 sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel)
11866 sel = gen_lowpart (DImode, sel);
11870 /* inp = xxxxxxxAxxxxxxxB */
11871 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11872 NULL_RTX, 1, OPTAB_DIRECT);
11873 /* t_1 = ....xxxxxxxAxxx. */
11874 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
11875 GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT);
11876 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
11877 GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT);
11878 /* sel = .......B */
11879 /* t_1 = ...A.... */
11880 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
11881 /* sel = ...A...B */
11882 sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1);
11883 /* sel = AAAABBBB * 4 */
11884 t_1 = force_reg (SImode, GEN_INT (0x01230123));
11885 /* sel = { A*4, A*4+1, A*4+2, ... } */
11889 /* inp = xxxAxxxBxxxCxxxD */
11890 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
11891 NULL_RTX, 1, OPTAB_DIRECT);
11892 t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11893 NULL_RTX, 1, OPTAB_DIRECT);
11894 t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24),
11895 NULL_RTX, 1, OPTAB_DIRECT);
11896 /* t_1 = ..xxxAxxxBxxxCxx */
11897 /* t_2 = ....xxxAxxxBxxxC */
11898 /* t_3 = ......xxxAxxxBxx */
11899 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
11901 NULL_RTX, 1, OPTAB_DIRECT);
11902 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
11904 NULL_RTX, 1, OPTAB_DIRECT);
11905 t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2),
11906 GEN_INT (0x070000),
11907 NULL_RTX, 1, OPTAB_DIRECT);
11908 t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3),
11909 GEN_INT (0x07000000),
11910 NULL_RTX, 1, OPTAB_DIRECT);
11911 /* sel = .......D */
11912 /* t_1 = .....C.. */
11913 /* t_2 = ...B.... */
11914 /* t_3 = .A...... */
11915 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
11916 t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT);
11917 sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT);
11918 /* sel = .A.B.C.D */
11919 sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1);
11920 /* sel = AABBCCDD * 2 */
11921 t_1 = force_reg (SImode, GEN_INT (0x01010101));
11922 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11926 /* input = xAxBxCxDxExFxGxH */
11927 sel = expand_simple_binop (DImode, AND, sel,
11928 GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32
11930 NULL_RTX, 1, OPTAB_DIRECT);
11931 /* sel = .A.B.C.D.E.F.G.H */
11932 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4),
11933 NULL_RTX, 1, OPTAB_DIRECT);
11934 /* t_1 = ..A.B.C.D.E.F.G. */
11935 sel = expand_simple_binop (DImode, IOR, sel, t_1,
11936 NULL_RTX, 1, OPTAB_DIRECT);
11937 /* sel = .AABBCCDDEEFFGGH */
11938 sel = expand_simple_binop (DImode, AND, sel,
11939 GEN_INT ((HOST_WIDE_INT)0xff00ff << 32
11941 NULL_RTX, 1, OPTAB_DIRECT);
11942 /* sel = ..AB..CD..EF..GH */
11943 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
11944 NULL_RTX, 1, OPTAB_DIRECT);
11945 /* t_1 = ....AB..CD..EF.. */
11946 sel = expand_simple_binop (DImode, IOR, sel, t_1,
11947 NULL_RTX, 1, OPTAB_DIRECT);
11948 /* sel = ..ABABCDCDEFEFGH */
11949 sel = expand_simple_binop (DImode, AND, sel,
11950 GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff),
11951 NULL_RTX, 1, OPTAB_DIRECT);
11952 /* sel = ....ABCD....EFGH */
11953 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11954 NULL_RTX, 1, OPTAB_DIRECT);
11955 /* t_1 = ........ABCD.... */
11956 sel = gen_lowpart (SImode, sel);
11957 t_1 = gen_lowpart (SImode, t_1);
11961 gcc_unreachable ();
11964 /* Always perform the final addition/merge within the bmask insn. */
11965 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1));
11968 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11971 sparc_frame_pointer_required (void)
11973 /* If the stack pointer is dynamically modified in the function, it cannot
11974 serve as the frame pointer. */
11975 if (cfun->calls_alloca)
11978 /* If the function receives nonlocal gotos, it needs to save the frame
11979 pointer in the nonlocal_goto_save_area object. */
11980 if (cfun->has_nonlocal_label)
11983 /* In flat mode, that's it. */
11987 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11988 return !(crtl->is_leaf && only_leaf_regs_used ());
11991 /* The way this is structured, we can't eliminate SFP in favor of SP
11992 if the frame pointer is required: we want to use the SFP->HFP elimination
11993 in that case. But the test in update_eliminables doesn't know we are
11994 assuming below that we only do the former elimination. */
11997 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
11999 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
12002 /* Return the hard frame pointer directly to bypass the stack bias. */
12005 sparc_builtin_setjmp_frame_value (void)
12007 return hard_frame_pointer_rtx;
12010 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12011 they won't be allocated. */
12014 sparc_conditional_register_usage (void)
12016 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
12018 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12019 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12021 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12022 /* then honor it. */
12023 if (TARGET_ARCH32 && fixed_regs[5])
12025 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
12030 for (regno = SPARC_FIRST_V9_FP_REG;
12031 regno <= SPARC_LAST_V9_FP_REG;
12033 fixed_regs[regno] = 1;
12034 /* %fcc0 is used by v8 and v9. */
12035 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
12036 regno <= SPARC_LAST_V9_FCC_REG;
12038 fixed_regs[regno] = 1;
12043 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
12044 fixed_regs[regno] = 1;
12046 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12047 /* then honor it. Likewise with g3 and g4. */
12048 if (fixed_regs[2] == 2)
12049 fixed_regs[2] = ! TARGET_APP_REGS;
12050 if (fixed_regs[3] == 2)
12051 fixed_regs[3] = ! TARGET_APP_REGS;
12052 if (TARGET_ARCH32 && fixed_regs[4] == 2)
12053 fixed_regs[4] = ! TARGET_APP_REGS;
12054 else if (TARGET_CM_EMBMEDANY)
12056 else if (fixed_regs[4] == 2)
12061 /* Disable leaf functions. */
12062 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
12063 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
12064 leaf_reg_remap [regno] = regno;
12067 global_regs[SPARC_GSR_REG] = 1;
12070 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12072 - We can't load constants into FP registers.
12073 - We can't load FP constants into integer registers when soft-float,
12074 because there is no soft-float pattern with a r/F constraint.
12075 - We can't load FP constants into integer registers for TFmode unless
12076 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12077 - Try and reload integer constants (symbolic or otherwise) back into
12078 registers directly, rather than having them dumped to memory. */
12081 sparc_preferred_reload_class (rtx x, reg_class_t rclass)
12083 enum machine_mode mode = GET_MODE (x);
12084 if (CONSTANT_P (x))
12086 if (FP_REG_CLASS_P (rclass)
12087 || rclass == GENERAL_OR_FP_REGS
12088 || rclass == GENERAL_OR_EXTRA_FP_REGS
12089 || (GET_MODE_CLASS (mode) == MODE_FLOAT && ! TARGET_FPU)
12090 || (mode == TFmode && ! const_zero_operand (x, mode)))
12093 if (GET_MODE_CLASS (mode) == MODE_INT)
12094 return GENERAL_REGS;
12096 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12098 if (! FP_REG_CLASS_P (rclass)
12099 || !(const_zero_operand (x, mode)
12100 || const_all_ones_operand (x, mode)))
12107 && (rclass == EXTRA_FP_REGS
12108 || rclass == GENERAL_OR_EXTRA_FP_REGS))
12110 int regno = true_regnum (x);
12112 if (SPARC_INT_REG_P (regno))
12113 return (rclass == EXTRA_FP_REGS
12114 ? FP_REGS : GENERAL_OR_FP_REGS);
12120 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12121 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12124 output_v8plus_mult (rtx insn, rtx *operands, const char *opcode)
12128 gcc_assert (! TARGET_ARCH64);
12130 if (sparc_check_64 (operands[1], insn) <= 0)
12131 output_asm_insn ("srl\t%L1, 0, %L1", operands);
12132 if (which_alternative == 1)
12133 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
12134 if (GET_CODE (operands[2]) == CONST_INT)
12136 if (which_alternative == 1)
12138 output_asm_insn ("or\t%L1, %H1, %H1", operands);
12139 sprintf (mulstr, "%s\t%%H1, %%2, %%L0", opcode);
12140 output_asm_insn (mulstr, operands);
12141 return "srlx\t%L0, 32, %H0";
12145 output_asm_insn ("sllx\t%H1, 32, %3", operands);
12146 output_asm_insn ("or\t%L1, %3, %3", operands);
12147 sprintf (mulstr, "%s\t%%3, %%2, %%3", opcode);
12148 output_asm_insn (mulstr, operands);
12149 output_asm_insn ("srlx\t%3, 32, %H0", operands);
12150 return "mov\t%3, %L0";
12153 else if (rtx_equal_p (operands[1], operands[2]))
12155 if (which_alternative == 1)
12157 output_asm_insn ("or\t%L1, %H1, %H1", operands);
12158 sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", opcode);
12159 output_asm_insn (mulstr, operands);
12160 return "srlx\t%L0, 32, %H0";
12164 output_asm_insn ("sllx\t%H1, 32, %3", operands);
12165 output_asm_insn ("or\t%L1, %3, %3", operands);
12166 sprintf (mulstr, "%s\t%%3, %%3, %%3", opcode);
12167 output_asm_insn (mulstr, operands);
12168 output_asm_insn ("srlx\t%3, 32, %H0", operands);
12169 return "mov\t%3, %L0";
12172 if (sparc_check_64 (operands[2], insn) <= 0)
12173 output_asm_insn ("srl\t%L2, 0, %L2", operands);
12174 if (which_alternative == 1)
12176 output_asm_insn ("or\t%L1, %H1, %H1", operands);
12177 output_asm_insn ("sllx\t%H2, 32, %L1", operands);
12178 output_asm_insn ("or\t%L2, %L1, %L1", operands);
12179 sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", opcode);
12180 output_asm_insn (mulstr, operands);
12181 return "srlx\t%L0, 32, %H0";
12185 output_asm_insn ("sllx\t%H1, 32, %3", operands);
12186 output_asm_insn ("sllx\t%H2, 32, %4", operands);
12187 output_asm_insn ("or\t%L1, %3, %3", operands);
12188 output_asm_insn ("or\t%L2, %4, %4", operands);
12189 sprintf (mulstr, "%s\t%%3, %%4, %%3", opcode);
12190 output_asm_insn (mulstr, operands);
12191 output_asm_insn ("srlx\t%3, 32, %H0", operands);
12192 return "mov\t%3, %L0";
12196 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12197 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12198 and INNER_MODE are the modes describing TARGET. */
12201 vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
12202 enum machine_mode inner_mode)
12204 rtx t1, final_insn, sel;
12207 t1 = gen_reg_rtx (mode);
12209 elt = convert_modes (SImode, inner_mode, elt, true);
12210 emit_move_insn (gen_lowpart(SImode, t1), elt);
12215 final_insn = gen_bshufflev2si_vis (target, t1, t1);
12216 bmask = 0x45674567;
12219 final_insn = gen_bshufflev4hi_vis (target, t1, t1);
12220 bmask = 0x67676767;
12223 final_insn = gen_bshufflev8qi_vis (target, t1, t1);
12224 bmask = 0x77777777;
12227 gcc_unreachable ();
12230 sel = force_reg (SImode, GEN_INT (bmask));
12231 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
12232 emit_insn (final_insn);
12235 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12236 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12239 vector_init_fpmerge (rtx target, rtx elt)
12241 rtx t1, t2, t2_low, t3, t3_low;
12243 t1 = gen_reg_rtx (V4QImode);
12244 elt = convert_modes (SImode, QImode, elt, true);
12245 emit_move_insn (gen_lowpart (SImode, t1), elt);
12247 t2 = gen_reg_rtx (V8QImode);
12248 t2_low = gen_lowpart (V4QImode, t2);
12249 emit_insn (gen_fpmerge_vis (t2, t1, t1));
12251 t3 = gen_reg_rtx (V8QImode);
12252 t3_low = gen_lowpart (V4QImode, t3);
12253 emit_insn (gen_fpmerge_vis (t3, t2_low, t2_low));
12255 emit_insn (gen_fpmerge_vis (target, t3_low, t3_low));
12258 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12259 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12262 vector_init_faligndata (rtx target, rtx elt)
12264 rtx t1 = gen_reg_rtx (V4HImode);
12267 elt = convert_modes (SImode, HImode, elt, true);
12268 emit_move_insn (gen_lowpart (SImode, t1), elt);
12270 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode),
12271 force_reg (SImode, GEN_INT (6)),
12274 for (i = 0; i < 4; i++)
12275 emit_insn (gen_faligndatav4hi_vis (target, t1, target));
12278 /* Emit code to initialize TARGET to values for individual fields VALS. */
12281 sparc_expand_vector_init (rtx target, rtx vals)
12283 const enum machine_mode mode = GET_MODE (target);
12284 const enum machine_mode inner_mode = GET_MODE_INNER (mode);
12285 const int n_elts = GET_MODE_NUNITS (mode);
12291 for (i = 0; i < n_elts; i++)
12293 rtx x = XVECEXP (vals, 0, i);
12294 if (!CONSTANT_P (x))
12297 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
12303 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
12307 if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (mode))
12309 if (GET_MODE_SIZE (inner_mode) == 4)
12311 emit_move_insn (gen_lowpart (SImode, target),
12312 gen_lowpart (SImode, XVECEXP (vals, 0, 0)));
12315 else if (GET_MODE_SIZE (inner_mode) == 8)
12317 emit_move_insn (gen_lowpart (DImode, target),
12318 gen_lowpart (DImode, XVECEXP (vals, 0, 0)));
12322 else if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (word_mode)
12323 && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode))
12325 emit_move_insn (gen_highpart (word_mode, target),
12326 gen_lowpart (word_mode, XVECEXP (vals, 0, 0)));
12327 emit_move_insn (gen_lowpart (word_mode, target),
12328 gen_lowpart (word_mode, XVECEXP (vals, 0, 1)));
12332 if (all_same && GET_MODE_SIZE (mode) == 8)
12336 vector_init_bshuffle (target, XVECEXP (vals, 0, 0), mode, inner_mode);
12339 if (mode == V8QImode)
12341 vector_init_fpmerge (target, XVECEXP (vals, 0, 0));
12344 if (mode == V4HImode)
12346 vector_init_faligndata (target, XVECEXP (vals, 0, 0));
12351 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
12352 for (i = 0; i < n_elts; i++)
12353 emit_move_insn (adjust_address_nv (mem, inner_mode,
12354 i * GET_MODE_SIZE (inner_mode)),
12355 XVECEXP (vals, 0, i));
12356 emit_move_insn (target, mem);
12359 /* Implement TARGET_SECONDARY_RELOAD. */
12362 sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
12363 enum machine_mode mode, secondary_reload_info *sri)
12365 enum reg_class rclass = (enum reg_class) rclass_i;
12367 sri->icode = CODE_FOR_nothing;
12368 sri->extra_cost = 0;
12370 /* We need a temporary when loading/storing a HImode/QImode value
12371 between memory and the FPU registers. This can happen when combine puts
12372 a paradoxical subreg in a float/fix conversion insn. */
12373 if (FP_REG_CLASS_P (rclass)
12374 && (mode == HImode || mode == QImode)
12375 && (GET_CODE (x) == MEM
12376 || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
12377 && true_regnum (x) == -1)))
12378 return GENERAL_REGS;
12380 /* On 32-bit we need a temporary when loading/storing a DFmode value
12381 between unaligned memory and the upper FPU registers. */
12383 && rclass == EXTRA_FP_REGS
12385 && GET_CODE (x) == MEM
12386 && ! mem_min_alignment (x, 8))
12389 if (((TARGET_CM_MEDANY
12390 && symbolic_operand (x, mode))
12391 || (TARGET_CM_EMBMEDANY
12392 && text_segment_operand (x, mode)))
12396 sri->icode = direct_optab_handler (reload_in_optab, mode);
12398 sri->icode = direct_optab_handler (reload_out_optab, mode);
12402 if (TARGET_VIS3 && TARGET_ARCH32)
12404 int regno = true_regnum (x);
12406 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12407 to move 8-byte values in 4-byte pieces. This only works via
12408 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12409 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12410 an FP_REGS intermediate move. */
12411 if ((rclass == EXTRA_FP_REGS && SPARC_INT_REG_P (regno))
12412 || ((general_or_i64_p (rclass)
12413 || rclass == GENERAL_OR_FP_REGS)
12414 && SPARC_FP_REG_P (regno)))
12416 sri->extra_cost = 2;
12424 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12425 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12428 sparc_expand_conditional_move (enum machine_mode mode, rtx *operands)
12430 enum rtx_code rc = GET_CODE (operands[1]);
12431 enum machine_mode cmp_mode;
12432 rtx cc_reg, dst, cmp;
12435 if (GET_MODE (XEXP (cmp, 0)) == DImode && !TARGET_ARCH64)
12438 if (GET_MODE (XEXP (cmp, 0)) == TFmode && !TARGET_HARD_QUAD)
12439 cmp = sparc_emit_float_lib_cmp (XEXP (cmp, 0), XEXP (cmp, 1), rc);
12441 cmp_mode = GET_MODE (XEXP (cmp, 0));
12442 rc = GET_CODE (cmp);
12445 if (! rtx_equal_p (operands[2], dst)
12446 && ! rtx_equal_p (operands[3], dst))
12448 if (reg_overlap_mentioned_p (dst, cmp))
12449 dst = gen_reg_rtx (mode);
12451 emit_move_insn (dst, operands[3]);
12453 else if (operands[2] == dst)
12455 operands[2] = operands[3];
12457 if (GET_MODE_CLASS (cmp_mode) == MODE_FLOAT)
12458 rc = reverse_condition_maybe_unordered (rc);
12460 rc = reverse_condition (rc);
12463 if (XEXP (cmp, 1) == const0_rtx
12464 && GET_CODE (XEXP (cmp, 0)) == REG
12465 && cmp_mode == DImode
12466 && v9_regcmp_p (rc))
12467 cc_reg = XEXP (cmp, 0);
12469 cc_reg = gen_compare_reg_1 (rc, XEXP (cmp, 0), XEXP (cmp, 1));
12471 cmp = gen_rtx_fmt_ee (rc, GET_MODE (cc_reg), cc_reg, const0_rtx);
12473 emit_insn (gen_rtx_SET (VOIDmode, dst,
12474 gen_rtx_IF_THEN_ELSE (mode, cmp, operands[2], dst)));
12476 if (dst != operands[0])
12477 emit_move_insn (operands[0], dst);
12482 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
12483 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
12484 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
12485 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
12486 code to be used for the condition mask. */
12489 sparc_expand_vcond (enum machine_mode mode, rtx *operands, int ccode, int fcode)
12491 rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr;
12492 enum rtx_code code = GET_CODE (operands[3]);
12494 mask = gen_reg_rtx (Pmode);
12495 cop0 = operands[4];
12496 cop1 = operands[5];
12497 if (code == LT || code == GE)
12501 code = swap_condition (code);
12502 t = cop0; cop0 = cop1; cop1 = t;
12505 gsr = gen_rtx_REG (DImode, SPARC_GSR_REG);
12507 fcmp = gen_rtx_UNSPEC (Pmode,
12508 gen_rtvec (1, gen_rtx_fmt_ee (code, mode, cop0, cop1)),
12511 cmask = gen_rtx_UNSPEC (DImode,
12512 gen_rtvec (2, mask, gsr),
12515 bshuf = gen_rtx_UNSPEC (mode,
12516 gen_rtvec (3, operands[1], operands[2], gsr),
12519 emit_insn (gen_rtx_SET (VOIDmode, mask, fcmp));
12520 emit_insn (gen_rtx_SET (VOIDmode, gsr, cmask));
12522 emit_insn (gen_rtx_SET (VOIDmode, operands[0], bshuf));
12525 /* On sparc, any mode which naturally allocates into the float
12526 registers should return 4 here. */
12529 sparc_regmode_natural_size (enum machine_mode mode)
12531 int size = UNITS_PER_WORD;
12535 enum mode_class mclass = GET_MODE_CLASS (mode);
12537 if (mclass == MODE_FLOAT || mclass == MODE_VECTOR_INT)
12544 /* Return TRUE if it is a good idea to tie two pseudo registers
12545 when one has mode MODE1 and one has mode MODE2.
12546 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12547 for any hard reg, then this must be FALSE for correct output.
12549 For V9 we have to deal with the fact that only the lower 32 floating
12550 point registers are 32-bit addressable. */
12553 sparc_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
12555 enum mode_class mclass1, mclass2;
12556 unsigned short size1, size2;
12558 if (mode1 == mode2)
12561 mclass1 = GET_MODE_CLASS (mode1);
12562 mclass2 = GET_MODE_CLASS (mode2);
12563 if (mclass1 != mclass2)
12569 /* Classes are the same and we are V9 so we have to deal with upper
12570 vs. lower floating point registers. If one of the modes is a
12571 4-byte mode, and the other is not, we have to mark them as not
12572 tieable because only the lower 32 floating point register are
12573 addressable 32-bits at a time.
12575 We can't just test explicitly for SFmode, otherwise we won't
12576 cover the vector mode cases properly. */
12578 if (mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT)
12581 size1 = GET_MODE_SIZE (mode1);
12582 size2 = GET_MODE_SIZE (mode2);
12583 if ((size1 > 4 && size2 == 4)
12584 || (size2 > 4 && size1 == 4))
12590 /* Implement TARGET_CSTORE_MODE. */
12592 static enum machine_mode
12593 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED)
12595 return (TARGET_ARCH64 ? DImode : SImode);
12598 /* Return the compound expression made of T1 and T2. */
12601 compound_expr (tree t1, tree t2)
12603 return build2 (COMPOUND_EXPR, void_type_node, t1, t2);
12606 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
12609 sparc_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
12614 const unsigned HOST_WIDE_INT accrued_exception_mask = 0x1f << 5;
12615 const unsigned HOST_WIDE_INT trap_enable_mask = 0x1f << 23;
12617 /* We generate the equivalent of feholdexcept (&fenv_var):
12619 unsigned int fenv_var;
12620 __builtin_store_fsr (&fenv_var);
12622 unsigned int tmp1_var;
12623 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
12625 __builtin_load_fsr (&tmp1_var); */
12627 tree fenv_var = create_tmp_var (unsigned_type_node, NULL);
12628 mark_addressable (fenv_var);
12629 tree fenv_addr = build_fold_addr_expr (fenv_var);
12630 tree stfsr = sparc_builtins[SPARC_BUILTIN_STFSR];
12631 tree hold_stfsr = build_call_expr (stfsr, 1, fenv_addr);
12633 tree tmp1_var = create_tmp_var (unsigned_type_node, NULL);
12634 mark_addressable (tmp1_var);
12635 tree masked_fenv_var
12636 = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var,
12637 build_int_cst (unsigned_type_node,
12638 ~(accrued_exception_mask | trap_enable_mask)));
12640 = build2 (MODIFY_EXPR, void_type_node, tmp1_var, masked_fenv_var);
12642 tree tmp1_addr = build_fold_addr_expr (tmp1_var);
12643 tree ldfsr = sparc_builtins[SPARC_BUILTIN_LDFSR];
12644 tree hold_ldfsr = build_call_expr (ldfsr, 1, tmp1_addr);
12646 *hold = compound_expr (compound_expr (hold_stfsr, hold_mask), hold_ldfsr);
12648 /* We reload the value of tmp1_var to clear the exceptions:
12650 __builtin_load_fsr (&tmp1_var); */
12652 *clear = build_call_expr (ldfsr, 1, tmp1_addr);
12654 /* We generate the equivalent of feupdateenv (&fenv_var):
12656 unsigned int tmp2_var;
12657 __builtin_store_fsr (&tmp2_var);
12659 __builtin_load_fsr (&fenv_var);
12661 if (SPARC_LOW_FE_EXCEPT_VALUES)
12663 __atomic_feraiseexcept ((int) tmp2_var); */
12665 tree tmp2_var = create_tmp_var (unsigned_type_node, NULL);
12666 mark_addressable (tmp2_var);
12667 tree tmp3_addr = build_fold_addr_expr (tmp2_var);
12668 tree update_stfsr = build_call_expr (stfsr, 1, tmp3_addr);
12670 tree update_ldfsr = build_call_expr (ldfsr, 1, fenv_addr);
12672 tree atomic_feraiseexcept
12673 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
12675 = build_call_expr (atomic_feraiseexcept, 1,
12676 fold_convert (integer_type_node, tmp2_var));
12678 if (SPARC_LOW_FE_EXCEPT_VALUES)
12680 tree shifted_tmp2_var
12681 = build2 (RSHIFT_EXPR, unsigned_type_node, tmp2_var,
12682 build_int_cst (unsigned_type_node, 5));
12684 = build2 (MODIFY_EXPR, void_type_node, tmp2_var, shifted_tmp2_var);
12685 update_call = compound_expr (update_shift, update_call);
12689 = compound_expr (compound_expr (update_stfsr, update_ldfsr), update_call);
12692 #include "gt-sparc.h"