1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
33 #include "stringpool.h"
39 #include "diagnostic-core.h"
41 #include "fold-const.h"
42 #include "stor-layout.h"
46 #include "insn-attr.h"
50 #include "common/common-target.h"
52 #include "langhooks.h"
55 #include "tree-pass.h"
59 /* This file should be included last. */
60 #include "target-def.h"
64 struct processor_costs {
68 /* Integer signed load */
71 /* Integer zeroed load */
77 /* fmov, fneg, fabs */
81 const int float_plusminus;
87 const int float_cmove;
93 const int float_div_sf;
96 const int float_div_df;
99 const int float_sqrt_sf;
102 const int float_sqrt_df;
110 /* integer multiply cost for each bit set past the most
111 significant 3, so the formula for multiply cost becomes:
114 highest_bit = highest_clear_bit(rs1);
116 highest_bit = highest_set_bit(rs1);
119 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
121 A value of zero indicates that the multiply costs is fixed,
123 const int int_mul_bit_factor;
134 /* penalty for shifts, due to scheduling rules etc. */
135 const int shift_penalty;
139 struct processor_costs cypress_costs = {
140 COSTS_N_INSNS (2), /* int load */
141 COSTS_N_INSNS (2), /* int signed load */
142 COSTS_N_INSNS (2), /* int zeroed load */
143 COSTS_N_INSNS (2), /* float load */
144 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
145 COSTS_N_INSNS (5), /* fadd, fsub */
146 COSTS_N_INSNS (1), /* fcmp */
147 COSTS_N_INSNS (1), /* fmov, fmovr */
148 COSTS_N_INSNS (7), /* fmul */
149 COSTS_N_INSNS (37), /* fdivs */
150 COSTS_N_INSNS (37), /* fdivd */
151 COSTS_N_INSNS (63), /* fsqrts */
152 COSTS_N_INSNS (63), /* fsqrtd */
153 COSTS_N_INSNS (1), /* imul */
154 COSTS_N_INSNS (1), /* imulX */
155 0, /* imul bit factor */
156 COSTS_N_INSNS (1), /* idiv */
157 COSTS_N_INSNS (1), /* idivX */
158 COSTS_N_INSNS (1), /* movcc/movr */
159 0, /* shift penalty */
163 struct processor_costs supersparc_costs = {
164 COSTS_N_INSNS (1), /* int load */
165 COSTS_N_INSNS (1), /* int signed load */
166 COSTS_N_INSNS (1), /* int zeroed load */
167 COSTS_N_INSNS (0), /* float load */
168 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
169 COSTS_N_INSNS (3), /* fadd, fsub */
170 COSTS_N_INSNS (3), /* fcmp */
171 COSTS_N_INSNS (1), /* fmov, fmovr */
172 COSTS_N_INSNS (3), /* fmul */
173 COSTS_N_INSNS (6), /* fdivs */
174 COSTS_N_INSNS (9), /* fdivd */
175 COSTS_N_INSNS (12), /* fsqrts */
176 COSTS_N_INSNS (12), /* fsqrtd */
177 COSTS_N_INSNS (4), /* imul */
178 COSTS_N_INSNS (4), /* imulX */
179 0, /* imul bit factor */
180 COSTS_N_INSNS (4), /* idiv */
181 COSTS_N_INSNS (4), /* idivX */
182 COSTS_N_INSNS (1), /* movcc/movr */
183 1, /* shift penalty */
187 struct processor_costs hypersparc_costs = {
188 COSTS_N_INSNS (1), /* int load */
189 COSTS_N_INSNS (1), /* int signed load */
190 COSTS_N_INSNS (1), /* int zeroed load */
191 COSTS_N_INSNS (1), /* float load */
192 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
193 COSTS_N_INSNS (1), /* fadd, fsub */
194 COSTS_N_INSNS (1), /* fcmp */
195 COSTS_N_INSNS (1), /* fmov, fmovr */
196 COSTS_N_INSNS (1), /* fmul */
197 COSTS_N_INSNS (8), /* fdivs */
198 COSTS_N_INSNS (12), /* fdivd */
199 COSTS_N_INSNS (17), /* fsqrts */
200 COSTS_N_INSNS (17), /* fsqrtd */
201 COSTS_N_INSNS (17), /* imul */
202 COSTS_N_INSNS (17), /* imulX */
203 0, /* imul bit factor */
204 COSTS_N_INSNS (17), /* idiv */
205 COSTS_N_INSNS (17), /* idivX */
206 COSTS_N_INSNS (1), /* movcc/movr */
207 0, /* shift penalty */
211 struct processor_costs leon_costs = {
212 COSTS_N_INSNS (1), /* int load */
213 COSTS_N_INSNS (1), /* int signed load */
214 COSTS_N_INSNS (1), /* int zeroed load */
215 COSTS_N_INSNS (1), /* float load */
216 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
217 COSTS_N_INSNS (1), /* fadd, fsub */
218 COSTS_N_INSNS (1), /* fcmp */
219 COSTS_N_INSNS (1), /* fmov, fmovr */
220 COSTS_N_INSNS (1), /* fmul */
221 COSTS_N_INSNS (15), /* fdivs */
222 COSTS_N_INSNS (15), /* fdivd */
223 COSTS_N_INSNS (23), /* fsqrts */
224 COSTS_N_INSNS (23), /* fsqrtd */
225 COSTS_N_INSNS (5), /* imul */
226 COSTS_N_INSNS (5), /* imulX */
227 0, /* imul bit factor */
228 COSTS_N_INSNS (5), /* idiv */
229 COSTS_N_INSNS (5), /* idivX */
230 COSTS_N_INSNS (1), /* movcc/movr */
231 0, /* shift penalty */
235 struct processor_costs leon3_costs = {
236 COSTS_N_INSNS (1), /* int load */
237 COSTS_N_INSNS (1), /* int signed load */
238 COSTS_N_INSNS (1), /* int zeroed load */
239 COSTS_N_INSNS (1), /* float load */
240 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
241 COSTS_N_INSNS (1), /* fadd, fsub */
242 COSTS_N_INSNS (1), /* fcmp */
243 COSTS_N_INSNS (1), /* fmov, fmovr */
244 COSTS_N_INSNS (1), /* fmul */
245 COSTS_N_INSNS (14), /* fdivs */
246 COSTS_N_INSNS (15), /* fdivd */
247 COSTS_N_INSNS (22), /* fsqrts */
248 COSTS_N_INSNS (23), /* fsqrtd */
249 COSTS_N_INSNS (5), /* imul */
250 COSTS_N_INSNS (5), /* imulX */
251 0, /* imul bit factor */
252 COSTS_N_INSNS (35), /* idiv */
253 COSTS_N_INSNS (35), /* idivX */
254 COSTS_N_INSNS (1), /* movcc/movr */
255 0, /* shift penalty */
259 struct processor_costs sparclet_costs = {
260 COSTS_N_INSNS (3), /* int load */
261 COSTS_N_INSNS (3), /* int signed load */
262 COSTS_N_INSNS (1), /* int zeroed load */
263 COSTS_N_INSNS (1), /* float load */
264 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
265 COSTS_N_INSNS (1), /* fadd, fsub */
266 COSTS_N_INSNS (1), /* fcmp */
267 COSTS_N_INSNS (1), /* fmov, fmovr */
268 COSTS_N_INSNS (1), /* fmul */
269 COSTS_N_INSNS (1), /* fdivs */
270 COSTS_N_INSNS (1), /* fdivd */
271 COSTS_N_INSNS (1), /* fsqrts */
272 COSTS_N_INSNS (1), /* fsqrtd */
273 COSTS_N_INSNS (5), /* imul */
274 COSTS_N_INSNS (5), /* imulX */
275 0, /* imul bit factor */
276 COSTS_N_INSNS (5), /* idiv */
277 COSTS_N_INSNS (5), /* idivX */
278 COSTS_N_INSNS (1), /* movcc/movr */
279 0, /* shift penalty */
283 struct processor_costs ultrasparc_costs = {
284 COSTS_N_INSNS (2), /* int load */
285 COSTS_N_INSNS (3), /* int signed load */
286 COSTS_N_INSNS (2), /* int zeroed load */
287 COSTS_N_INSNS (2), /* float load */
288 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
289 COSTS_N_INSNS (4), /* fadd, fsub */
290 COSTS_N_INSNS (1), /* fcmp */
291 COSTS_N_INSNS (2), /* fmov, fmovr */
292 COSTS_N_INSNS (4), /* fmul */
293 COSTS_N_INSNS (13), /* fdivs */
294 COSTS_N_INSNS (23), /* fdivd */
295 COSTS_N_INSNS (13), /* fsqrts */
296 COSTS_N_INSNS (23), /* fsqrtd */
297 COSTS_N_INSNS (4), /* imul */
298 COSTS_N_INSNS (4), /* imulX */
299 2, /* imul bit factor */
300 COSTS_N_INSNS (37), /* idiv */
301 COSTS_N_INSNS (68), /* idivX */
302 COSTS_N_INSNS (2), /* movcc/movr */
303 2, /* shift penalty */
307 struct processor_costs ultrasparc3_costs = {
308 COSTS_N_INSNS (2), /* int load */
309 COSTS_N_INSNS (3), /* int signed load */
310 COSTS_N_INSNS (3), /* int zeroed load */
311 COSTS_N_INSNS (2), /* float load */
312 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
313 COSTS_N_INSNS (4), /* fadd, fsub */
314 COSTS_N_INSNS (5), /* fcmp */
315 COSTS_N_INSNS (3), /* fmov, fmovr */
316 COSTS_N_INSNS (4), /* fmul */
317 COSTS_N_INSNS (17), /* fdivs */
318 COSTS_N_INSNS (20), /* fdivd */
319 COSTS_N_INSNS (20), /* fsqrts */
320 COSTS_N_INSNS (29), /* fsqrtd */
321 COSTS_N_INSNS (6), /* imul */
322 COSTS_N_INSNS (6), /* imulX */
323 0, /* imul bit factor */
324 COSTS_N_INSNS (40), /* idiv */
325 COSTS_N_INSNS (71), /* idivX */
326 COSTS_N_INSNS (2), /* movcc/movr */
327 0, /* shift penalty */
331 struct processor_costs niagara_costs = {
332 COSTS_N_INSNS (3), /* int load */
333 COSTS_N_INSNS (3), /* int signed load */
334 COSTS_N_INSNS (3), /* int zeroed load */
335 COSTS_N_INSNS (9), /* float load */
336 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
337 COSTS_N_INSNS (8), /* fadd, fsub */
338 COSTS_N_INSNS (26), /* fcmp */
339 COSTS_N_INSNS (8), /* fmov, fmovr */
340 COSTS_N_INSNS (29), /* fmul */
341 COSTS_N_INSNS (54), /* fdivs */
342 COSTS_N_INSNS (83), /* fdivd */
343 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
344 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
345 COSTS_N_INSNS (11), /* imul */
346 COSTS_N_INSNS (11), /* imulX */
347 0, /* imul bit factor */
348 COSTS_N_INSNS (72), /* idiv */
349 COSTS_N_INSNS (72), /* idivX */
350 COSTS_N_INSNS (1), /* movcc/movr */
351 0, /* shift penalty */
355 struct processor_costs niagara2_costs = {
356 COSTS_N_INSNS (3), /* int load */
357 COSTS_N_INSNS (3), /* int signed load */
358 COSTS_N_INSNS (3), /* int zeroed load */
359 COSTS_N_INSNS (3), /* float load */
360 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
361 COSTS_N_INSNS (6), /* fadd, fsub */
362 COSTS_N_INSNS (6), /* fcmp */
363 COSTS_N_INSNS (6), /* fmov, fmovr */
364 COSTS_N_INSNS (6), /* fmul */
365 COSTS_N_INSNS (19), /* fdivs */
366 COSTS_N_INSNS (33), /* fdivd */
367 COSTS_N_INSNS (19), /* fsqrts */
368 COSTS_N_INSNS (33), /* fsqrtd */
369 COSTS_N_INSNS (5), /* imul */
370 COSTS_N_INSNS (5), /* imulX */
371 0, /* imul bit factor */
372 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
373 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
374 COSTS_N_INSNS (1), /* movcc/movr */
375 0, /* shift penalty */
379 struct processor_costs niagara3_costs = {
380 COSTS_N_INSNS (3), /* int load */
381 COSTS_N_INSNS (3), /* int signed load */
382 COSTS_N_INSNS (3), /* int zeroed load */
383 COSTS_N_INSNS (3), /* float load */
384 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
385 COSTS_N_INSNS (9), /* fadd, fsub */
386 COSTS_N_INSNS (9), /* fcmp */
387 COSTS_N_INSNS (9), /* fmov, fmovr */
388 COSTS_N_INSNS (9), /* fmul */
389 COSTS_N_INSNS (23), /* fdivs */
390 COSTS_N_INSNS (37), /* fdivd */
391 COSTS_N_INSNS (23), /* fsqrts */
392 COSTS_N_INSNS (37), /* fsqrtd */
393 COSTS_N_INSNS (9), /* imul */
394 COSTS_N_INSNS (9), /* imulX */
395 0, /* imul bit factor */
396 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
397 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
398 COSTS_N_INSNS (1), /* movcc/movr */
399 0, /* shift penalty */
403 struct processor_costs niagara4_costs = {
404 COSTS_N_INSNS (5), /* int load */
405 COSTS_N_INSNS (5), /* int signed load */
406 COSTS_N_INSNS (5), /* int zeroed load */
407 COSTS_N_INSNS (5), /* float load */
408 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
409 COSTS_N_INSNS (11), /* fadd, fsub */
410 COSTS_N_INSNS (11), /* fcmp */
411 COSTS_N_INSNS (11), /* fmov, fmovr */
412 COSTS_N_INSNS (11), /* fmul */
413 COSTS_N_INSNS (24), /* fdivs */
414 COSTS_N_INSNS (37), /* fdivd */
415 COSTS_N_INSNS (24), /* fsqrts */
416 COSTS_N_INSNS (37), /* fsqrtd */
417 COSTS_N_INSNS (12), /* imul */
418 COSTS_N_INSNS (12), /* imulX */
419 0, /* imul bit factor */
420 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
421 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
422 COSTS_N_INSNS (1), /* movcc/movr */
423 0, /* shift penalty */
426 static const struct processor_costs *sparc_costs = &cypress_costs;
428 #ifdef HAVE_AS_RELAX_OPTION
429 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
430 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
431 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
432 somebody does not branch between the sethi and jmp. */
433 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
435 #define LEAF_SIBCALL_SLOT_RESERVED_P \
436 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
439 /* Vector to say how input registers are mapped to output registers.
440 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
441 eliminate it. You must use -fomit-frame-pointer to get that. */
442 char leaf_reg_remap[] =
443 { 0, 1, 2, 3, 4, 5, 6, 7,
444 -1, -1, -1, -1, -1, -1, 14, -1,
445 -1, -1, -1, -1, -1, -1, -1, -1,
446 8, 9, 10, 11, 12, 13, -1, 15,
448 32, 33, 34, 35, 36, 37, 38, 39,
449 40, 41, 42, 43, 44, 45, 46, 47,
450 48, 49, 50, 51, 52, 53, 54, 55,
451 56, 57, 58, 59, 60, 61, 62, 63,
452 64, 65, 66, 67, 68, 69, 70, 71,
453 72, 73, 74, 75, 76, 77, 78, 79,
454 80, 81, 82, 83, 84, 85, 86, 87,
455 88, 89, 90, 91, 92, 93, 94, 95,
456 96, 97, 98, 99, 100, 101, 102};
458 /* Vector, indexed by hard register number, which contains 1
459 for a register that is allowable in a candidate for leaf
460 function treatment. */
461 char sparc_leaf_regs[] =
462 { 1, 1, 1, 1, 1, 1, 1, 1,
463 0, 0, 0, 0, 0, 0, 1, 0,
464 0, 0, 0, 0, 0, 0, 0, 0,
465 1, 1, 1, 1, 1, 1, 0, 1,
466 1, 1, 1, 1, 1, 1, 1, 1,
467 1, 1, 1, 1, 1, 1, 1, 1,
468 1, 1, 1, 1, 1, 1, 1, 1,
469 1, 1, 1, 1, 1, 1, 1, 1,
470 1, 1, 1, 1, 1, 1, 1, 1,
471 1, 1, 1, 1, 1, 1, 1, 1,
472 1, 1, 1, 1, 1, 1, 1, 1,
473 1, 1, 1, 1, 1, 1, 1, 1,
474 1, 1, 1, 1, 1, 1, 1};
476 struct GTY(()) machine_function
478 /* Size of the frame of the function. */
479 HOST_WIDE_INT frame_size;
481 /* Size of the frame of the function minus the register window save area
482 and the outgoing argument area. */
483 HOST_WIDE_INT apparent_frame_size;
485 /* Register we pretend the frame pointer is allocated to. Normally, this
486 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
487 record "offset" separately as it may be too big for (reg + disp). */
489 HOST_WIDE_INT frame_base_offset;
491 /* Number of global or FP registers to be saved (as 4-byte quantities). */
492 int n_global_fp_regs;
494 /* True if the current function is leaf and uses only leaf regs,
495 so that the SPARC leaf function optimization can be applied.
496 Private version of crtl->uses_only_leaf_regs, see
497 sparc_expand_prologue for the rationale. */
500 /* True if the prologue saves local or in registers. */
501 bool save_local_in_regs_p;
503 /* True if the data calculated by sparc_expand_prologue are valid. */
504 bool prologue_data_valid_p;
507 #define sparc_frame_size cfun->machine->frame_size
508 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
509 #define sparc_frame_base_reg cfun->machine->frame_base_reg
510 #define sparc_frame_base_offset cfun->machine->frame_base_offset
511 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
512 #define sparc_leaf_function_p cfun->machine->leaf_function_p
513 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
514 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
516 /* 1 if the next opcode is to be specially indented. */
517 int sparc_indent_opcode = 0;
519 static void sparc_option_override (void);
520 static void sparc_init_modes (void);
521 static int function_arg_slotno (const CUMULATIVE_ARGS *, machine_mode,
522 const_tree, bool, bool, int *, int *);
524 static int supersparc_adjust_cost (rtx_insn *, rtx, rtx_insn *, int);
525 static int hypersparc_adjust_cost (rtx_insn *, rtx, rtx_insn *, int);
527 static void sparc_emit_set_const32 (rtx, rtx);
528 static void sparc_emit_set_const64 (rtx, rtx);
529 static void sparc_output_addr_vec (rtx);
530 static void sparc_output_addr_diff_vec (rtx);
531 static void sparc_output_deferred_case_vectors (void);
532 static bool sparc_legitimate_address_p (machine_mode, rtx, bool);
533 static bool sparc_legitimate_constant_p (machine_mode, rtx);
534 static rtx sparc_builtin_saveregs (void);
535 static int epilogue_renumber (rtx *, int);
536 static bool sparc_assemble_integer (rtx, unsigned int, int);
537 static int set_extends (rtx_insn *);
538 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
539 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
540 #ifdef TARGET_SOLARIS
541 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
542 tree) ATTRIBUTE_UNUSED;
544 static int sparc_adjust_cost (rtx_insn *, rtx, rtx_insn *, int);
545 static int sparc_issue_rate (void);
546 static void sparc_sched_init (FILE *, int, int);
547 static int sparc_use_sched_lookahead (void);
549 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
550 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
551 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
552 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
553 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
555 static bool sparc_function_ok_for_sibcall (tree, tree);
556 static void sparc_init_libfuncs (void);
557 static void sparc_init_builtins (void);
558 static void sparc_fpu_init_builtins (void);
559 static void sparc_vis_init_builtins (void);
560 static tree sparc_builtin_decl (unsigned, bool);
561 static rtx sparc_expand_builtin (tree, rtx, rtx, machine_mode, int);
562 static tree sparc_fold_builtin (tree, int, tree *, bool);
563 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
564 HOST_WIDE_INT, tree);
565 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
566 HOST_WIDE_INT, const_tree);
567 static struct machine_function * sparc_init_machine_status (void);
568 static bool sparc_cannot_force_const_mem (machine_mode, rtx);
569 static rtx sparc_tls_get_addr (void);
570 static rtx sparc_tls_got (void);
571 static int sparc_register_move_cost (machine_mode,
572 reg_class_t, reg_class_t);
573 static bool sparc_rtx_costs (rtx, machine_mode, int, int, int *, bool);
574 static rtx sparc_function_value (const_tree, const_tree, bool);
575 static rtx sparc_libcall_value (machine_mode, const_rtx);
576 static bool sparc_function_value_regno_p (const unsigned int);
577 static rtx sparc_struct_value_rtx (tree, int);
578 static machine_mode sparc_promote_function_mode (const_tree, machine_mode,
579 int *, const_tree, int);
580 static bool sparc_return_in_memory (const_tree, const_tree);
581 static bool sparc_strict_argument_naming (cumulative_args_t);
582 static void sparc_va_start (tree, rtx);
583 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
584 static bool sparc_vector_mode_supported_p (machine_mode);
585 static bool sparc_tls_referenced_p (rtx);
586 static rtx sparc_legitimize_tls_address (rtx);
587 static rtx sparc_legitimize_pic_address (rtx, rtx);
588 static rtx sparc_legitimize_address (rtx, rtx, machine_mode);
589 static rtx sparc_delegitimize_address (rtx);
590 static bool sparc_mode_dependent_address_p (const_rtx, addr_space_t);
591 static bool sparc_pass_by_reference (cumulative_args_t,
592 machine_mode, const_tree, bool);
593 static void sparc_function_arg_advance (cumulative_args_t,
594 machine_mode, const_tree, bool);
595 static rtx sparc_function_arg_1 (cumulative_args_t,
596 machine_mode, const_tree, bool, bool);
597 static rtx sparc_function_arg (cumulative_args_t,
598 machine_mode, const_tree, bool);
599 static rtx sparc_function_incoming_arg (cumulative_args_t,
600 machine_mode, const_tree, bool);
601 static unsigned int sparc_function_arg_boundary (machine_mode,
603 static int sparc_arg_partial_bytes (cumulative_args_t,
604 machine_mode, tree, bool);
605 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
606 static void sparc_file_end (void);
607 static bool sparc_frame_pointer_required (void);
608 static bool sparc_can_eliminate (const int, const int);
609 static rtx sparc_builtin_setjmp_frame_value (void);
610 static void sparc_conditional_register_usage (void);
611 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
612 static const char *sparc_mangle_type (const_tree);
614 static void sparc_trampoline_init (rtx, tree, rtx);
615 static machine_mode sparc_preferred_simd_mode (machine_mode);
616 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
617 static bool sparc_print_operand_punct_valid_p (unsigned char);
618 static void sparc_print_operand (FILE *, rtx, int);
619 static void sparc_print_operand_address (FILE *, machine_mode, rtx);
620 static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t,
622 secondary_reload_info *);
623 static machine_mode sparc_cstore_mode (enum insn_code icode);
624 static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *);
626 #ifdef SUBTARGET_ATTRIBUTE_TABLE
627 /* Table of valid machine attributes. */
628 static const struct attribute_spec sparc_attribute_table[] =
630 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
632 SUBTARGET_ATTRIBUTE_TABLE,
633 { NULL, 0, 0, false, false, false, NULL, false }
637 /* Option handling. */
640 enum cmodel sparc_cmodel;
642 char sparc_hard_reg_printed[8];
644 /* Initialize the GCC target structure. */
646 /* The default is to use .half rather than .short for aligned HI objects. */
647 #undef TARGET_ASM_ALIGNED_HI_OP
648 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
650 #undef TARGET_ASM_UNALIGNED_HI_OP
651 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
652 #undef TARGET_ASM_UNALIGNED_SI_OP
653 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
654 #undef TARGET_ASM_UNALIGNED_DI_OP
655 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
657 /* The target hook has to handle DI-mode values. */
658 #undef TARGET_ASM_INTEGER
659 #define TARGET_ASM_INTEGER sparc_assemble_integer
661 #undef TARGET_ASM_FUNCTION_PROLOGUE
662 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
663 #undef TARGET_ASM_FUNCTION_EPILOGUE
664 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
666 #undef TARGET_SCHED_ADJUST_COST
667 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
668 #undef TARGET_SCHED_ISSUE_RATE
669 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
670 #undef TARGET_SCHED_INIT
671 #define TARGET_SCHED_INIT sparc_sched_init
672 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
673 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
675 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
676 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
678 #undef TARGET_INIT_LIBFUNCS
679 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
681 #undef TARGET_LEGITIMIZE_ADDRESS
682 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
683 #undef TARGET_DELEGITIMIZE_ADDRESS
684 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
685 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
686 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
688 #undef TARGET_INIT_BUILTINS
689 #define TARGET_INIT_BUILTINS sparc_init_builtins
690 #undef TARGET_BUILTIN_DECL
691 #define TARGET_BUILTIN_DECL sparc_builtin_decl
692 #undef TARGET_EXPAND_BUILTIN
693 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
694 #undef TARGET_FOLD_BUILTIN
695 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
698 #undef TARGET_HAVE_TLS
699 #define TARGET_HAVE_TLS true
702 #undef TARGET_CANNOT_FORCE_CONST_MEM
703 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
705 #undef TARGET_ASM_OUTPUT_MI_THUNK
706 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
707 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
708 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
710 #undef TARGET_RTX_COSTS
711 #define TARGET_RTX_COSTS sparc_rtx_costs
712 #undef TARGET_ADDRESS_COST
713 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
714 #undef TARGET_REGISTER_MOVE_COST
715 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
717 #undef TARGET_PROMOTE_FUNCTION_MODE
718 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
720 #undef TARGET_FUNCTION_VALUE
721 #define TARGET_FUNCTION_VALUE sparc_function_value
722 #undef TARGET_LIBCALL_VALUE
723 #define TARGET_LIBCALL_VALUE sparc_libcall_value
724 #undef TARGET_FUNCTION_VALUE_REGNO_P
725 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
727 #undef TARGET_STRUCT_VALUE_RTX
728 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
729 #undef TARGET_RETURN_IN_MEMORY
730 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
731 #undef TARGET_MUST_PASS_IN_STACK
732 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
733 #undef TARGET_PASS_BY_REFERENCE
734 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
735 #undef TARGET_ARG_PARTIAL_BYTES
736 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
737 #undef TARGET_FUNCTION_ARG_ADVANCE
738 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
739 #undef TARGET_FUNCTION_ARG
740 #define TARGET_FUNCTION_ARG sparc_function_arg
741 #undef TARGET_FUNCTION_INCOMING_ARG
742 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
743 #undef TARGET_FUNCTION_ARG_BOUNDARY
744 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
746 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
747 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
748 #undef TARGET_STRICT_ARGUMENT_NAMING
749 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
751 #undef TARGET_EXPAND_BUILTIN_VA_START
752 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
753 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
754 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
756 #undef TARGET_VECTOR_MODE_SUPPORTED_P
757 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
759 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
760 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
762 #ifdef SUBTARGET_INSERT_ATTRIBUTES
763 #undef TARGET_INSERT_ATTRIBUTES
764 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
767 #ifdef SUBTARGET_ATTRIBUTE_TABLE
768 #undef TARGET_ATTRIBUTE_TABLE
769 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
772 #undef TARGET_OPTION_OVERRIDE
773 #define TARGET_OPTION_OVERRIDE sparc_option_override
775 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
776 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
777 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
780 #undef TARGET_ASM_FILE_END
781 #define TARGET_ASM_FILE_END sparc_file_end
783 #undef TARGET_FRAME_POINTER_REQUIRED
784 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
786 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
787 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
789 #undef TARGET_CAN_ELIMINATE
790 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
792 #undef TARGET_PREFERRED_RELOAD_CLASS
793 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
795 #undef TARGET_SECONDARY_RELOAD
796 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
798 #undef TARGET_CONDITIONAL_REGISTER_USAGE
799 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
801 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
802 #undef TARGET_MANGLE_TYPE
803 #define TARGET_MANGLE_TYPE sparc_mangle_type
806 #undef TARGET_LEGITIMATE_ADDRESS_P
807 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
809 #undef TARGET_LEGITIMATE_CONSTANT_P
810 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
812 #undef TARGET_TRAMPOLINE_INIT
813 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
815 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
816 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
817 #undef TARGET_PRINT_OPERAND
818 #define TARGET_PRINT_OPERAND sparc_print_operand
819 #undef TARGET_PRINT_OPERAND_ADDRESS
820 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
822 /* The value stored by LDSTUB. */
823 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
824 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
826 #undef TARGET_CSTORE_MODE
827 #define TARGET_CSTORE_MODE sparc_cstore_mode
829 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
830 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
832 struct gcc_target targetm = TARGET_INITIALIZER;
834 /* Return the memory reference contained in X if any, zero otherwise. */
839 if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND)
848 /* We use a machine specific pass to enable workarounds for errata.
849 We need to have the (essentially) final form of the insn stream in order
850 to properly detect the various hazards. Therefore, this machine specific
851 pass runs as late as possible. The pass is inserted in the pass pipeline
852 at the end of sparc_option_override. */
855 sparc_do_work_around_errata (void)
857 rtx_insn *insn, *next;
859 /* Force all instructions to be split into their final form. */
860 split_all_insns_noflow ();
862 /* Now look for specific patterns in the insn stream. */
863 for (insn = get_insns (); insn; insn = next)
865 bool insert_nop = false;
868 /* Look into the instruction in a delay slot. */
869 if (NONJUMP_INSN_P (insn))
870 if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
871 insn = seq->insn (1);
873 /* Look for a single-word load into an odd-numbered FP register. */
875 && NONJUMP_INSN_P (insn)
876 && (set = single_set (insn)) != NULL_RTX
877 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
878 && MEM_P (SET_SRC (set))
879 && REG_P (SET_DEST (set))
880 && REGNO (SET_DEST (set)) > 31
881 && REGNO (SET_DEST (set)) % 2 != 0)
883 /* The wrong dependency is on the enclosing double register. */
884 const unsigned int x = REGNO (SET_DEST (set)) - 1;
885 unsigned int src1, src2, dest;
888 next = next_active_insn (insn);
891 /* If the insn is a branch, then it cannot be problematic. */
892 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
896 code = INSN_CODE (next);
900 case CODE_FOR_adddf3:
901 case CODE_FOR_subdf3:
902 case CODE_FOR_muldf3:
903 case CODE_FOR_divdf3:
904 dest = REGNO (recog_data.operand[0]);
905 src1 = REGNO (recog_data.operand[1]);
906 src2 = REGNO (recog_data.operand[2]);
911 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
912 if ((src1 == x || src2 == x)
913 && (dest == src1 || dest == src2))
920 FPOPd %fx, %fx, %fx */
923 && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
928 case CODE_FOR_sqrtdf2:
929 dest = REGNO (recog_data.operand[0]);
930 src1 = REGNO (recog_data.operand[1]);
934 if (src1 == x && dest == src1)
943 /* Look for a single-word load into an integer register. */
944 else if (sparc_fix_ut699
945 && NONJUMP_INSN_P (insn)
946 && (set = single_set (insn)) != NULL_RTX
947 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4
948 && mem_ref (SET_SRC (set)) != NULL_RTX
949 && REG_P (SET_DEST (set))
950 && REGNO (SET_DEST (set)) < 32)
952 /* There is no problem if the second memory access has a data
953 dependency on the first single-cycle load. */
954 rtx x = SET_DEST (set);
956 next = next_active_insn (insn);
959 /* If the insn is a branch, then it cannot be problematic. */
960 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
963 /* Look for a second memory access to/from an integer register. */
964 if ((set = single_set (next)) != NULL_RTX)
966 rtx src = SET_SRC (set);
967 rtx dest = SET_DEST (set);
970 /* LDD is affected. */
971 if ((mem = mem_ref (src)) != NULL_RTX
974 && !reg_mentioned_p (x, XEXP (mem, 0)))
977 /* STD is *not* affected. */
978 else if (MEM_P (dest)
979 && GET_MODE_SIZE (GET_MODE (dest)) <= 4
980 && (src == CONST0_RTX (GET_MODE (dest))
983 && REGNO (src) != REGNO (x)))
984 && !reg_mentioned_p (x, XEXP (dest, 0)))
989 /* Look for a single-word load/operation into an FP register. */
990 else if (sparc_fix_ut699
991 && NONJUMP_INSN_P (insn)
992 && (set = single_set (insn)) != NULL_RTX
993 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
994 && REG_P (SET_DEST (set))
995 && REGNO (SET_DEST (set)) > 31)
997 /* Number of instructions in the problematic window. */
998 const int n_insns = 4;
999 /* The problematic combination is with the sibling FP register. */
1000 const unsigned int x = REGNO (SET_DEST (set));
1001 const unsigned int y = x ^ 1;
1005 next = next_active_insn (insn);
1008 /* If the insn is a branch, then it cannot be problematic. */
1009 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE)
1012 /* Look for a second load/operation into the sibling FP register. */
1013 if (!((set = single_set (next)) != NULL_RTX
1014 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
1015 && REG_P (SET_DEST (set))
1016 && REGNO (SET_DEST (set)) == y))
1019 /* Look for a (possible) store from the FP register in the next N
1020 instructions, but bail out if it is again modified or if there
1021 is a store from the sibling FP register before this store. */
1022 for (after = next, i = 0; i < n_insns; i++)
1026 after = next_active_insn (after);
1030 /* This is a branch with an empty delay slot. */
1031 if (!NONJUMP_INSN_P (after))
1038 /* This is a branch with a filled delay slot. */
1039 else if (rtx_sequence *seq =
1040 dyn_cast <rtx_sequence *> (PATTERN (after)))
1045 after = seq->insn (1);
1047 /* This is a regular instruction. */
1051 if (after && (set = single_set (after)) != NULL_RTX)
1053 const rtx src = SET_SRC (set);
1054 const rtx dest = SET_DEST (set);
1055 const unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
1057 /* If the FP register is again modified before the store,
1058 then the store isn't affected. */
1060 && (REGNO (dest) == x
1061 || (REGNO (dest) == y && size == 8)))
1064 if (MEM_P (dest) && REG_P (src))
1066 /* If there is a store from the sibling FP register
1067 before the store, then the store is not affected. */
1068 if (REGNO (src) == y || (REGNO (src) == x && size == 8))
1071 /* Otherwise, the store is affected. */
1072 if (REGNO (src) == x && size == 4)
1080 /* If we have a branch in the first M instructions, then we
1081 cannot see the (M+2)th instruction so we play safe. */
1082 if (branch_p && i <= (n_insns - 2))
1091 next = NEXT_INSN (insn);
1094 emit_insn_before (gen_nop (), next);
1102 const pass_data pass_data_work_around_errata =
1104 RTL_PASS, /* type */
1105 "errata", /* name */
1106 OPTGROUP_NONE, /* optinfo_flags */
1107 TV_MACH_DEP, /* tv_id */
1108 0, /* properties_required */
1109 0, /* properties_provided */
1110 0, /* properties_destroyed */
1111 0, /* todo_flags_start */
1112 0, /* todo_flags_finish */
1115 class pass_work_around_errata : public rtl_opt_pass
1118 pass_work_around_errata(gcc::context *ctxt)
1119 : rtl_opt_pass(pass_data_work_around_errata, ctxt)
1122 /* opt_pass methods: */
1123 virtual bool gate (function *)
1125 /* The only errata we handle are those of the AT697F and UT699. */
1126 return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
1129 virtual unsigned int execute (function *)
1131 return sparc_do_work_around_errata ();
1134 }; // class pass_work_around_errata
1139 make_pass_work_around_errata (gcc::context *ctxt)
1141 return new pass_work_around_errata (ctxt);
1144 /* Helpers for TARGET_DEBUG_OPTIONS. */
1146 dump_target_flag_bits (const int flags)
1148 if (flags & MASK_64BIT)
1149 fprintf (stderr, "64BIT ");
1150 if (flags & MASK_APP_REGS)
1151 fprintf (stderr, "APP_REGS ");
1152 if (flags & MASK_FASTER_STRUCTS)
1153 fprintf (stderr, "FASTER_STRUCTS ");
1154 if (flags & MASK_FLAT)
1155 fprintf (stderr, "FLAT ");
1156 if (flags & MASK_FMAF)
1157 fprintf (stderr, "FMAF ");
1158 if (flags & MASK_FPU)
1159 fprintf (stderr, "FPU ");
1160 if (flags & MASK_HARD_QUAD)
1161 fprintf (stderr, "HARD_QUAD ");
1162 if (flags & MASK_POPC)
1163 fprintf (stderr, "POPC ");
1164 if (flags & MASK_PTR64)
1165 fprintf (stderr, "PTR64 ");
1166 if (flags & MASK_STACK_BIAS)
1167 fprintf (stderr, "STACK_BIAS ");
1168 if (flags & MASK_UNALIGNED_DOUBLES)
1169 fprintf (stderr, "UNALIGNED_DOUBLES ");
1170 if (flags & MASK_V8PLUS)
1171 fprintf (stderr, "V8PLUS ");
1172 if (flags & MASK_VIS)
1173 fprintf (stderr, "VIS ");
1174 if (flags & MASK_VIS2)
1175 fprintf (stderr, "VIS2 ");
1176 if (flags & MASK_VIS3)
1177 fprintf (stderr, "VIS3 ");
1178 if (flags & MASK_CBCOND)
1179 fprintf (stderr, "CBCOND ");
1180 if (flags & MASK_DEPRECATED_V8_INSNS)
1181 fprintf (stderr, "DEPRECATED_V8_INSNS ");
1182 if (flags & MASK_SPARCLET)
1183 fprintf (stderr, "SPARCLET ");
1184 if (flags & MASK_SPARCLITE)
1185 fprintf (stderr, "SPARCLITE ");
1186 if (flags & MASK_V8)
1187 fprintf (stderr, "V8 ");
1188 if (flags & MASK_V9)
1189 fprintf (stderr, "V9 ");
1193 dump_target_flags (const char *prefix, const int flags)
1195 fprintf (stderr, "%s: (%08x) [ ", prefix, flags);
1196 dump_target_flag_bits (flags);
1197 fprintf(stderr, "]\n");
1200 /* Validate and override various options, and do some machine dependent
1204 sparc_option_override (void)
1206 static struct code_model {
1207 const char *const name;
1208 const enum cmodel value;
1209 } const cmodels[] = {
1211 { "medlow", CM_MEDLOW },
1212 { "medmid", CM_MEDMID },
1213 { "medany", CM_MEDANY },
1214 { "embmedany", CM_EMBMEDANY },
1215 { NULL, (enum cmodel) 0 }
1217 const struct code_model *cmodel;
1218 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1219 static struct cpu_default {
1221 const enum processor_type processor;
1222 } const cpu_default[] = {
1223 /* There must be one entry here for each TARGET_CPU value. */
1224 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
1225 { TARGET_CPU_v8, PROCESSOR_V8 },
1226 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
1227 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
1228 { TARGET_CPU_leon, PROCESSOR_LEON },
1229 { TARGET_CPU_leon3, PROCESSOR_LEON3 },
1230 { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 },
1231 { TARGET_CPU_sparclite, PROCESSOR_F930 },
1232 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
1233 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
1234 { TARGET_CPU_v9, PROCESSOR_V9 },
1235 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
1236 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
1237 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
1238 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
1239 { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 },
1240 { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 },
1241 { -1, PROCESSOR_V7 }
1243 const struct cpu_default *def;
1244 /* Table of values for -m{cpu,tune}=. This must match the order of
1245 the enum processor_type in sparc-opts.h. */
1246 static struct cpu_table {
1247 const char *const name;
1250 } const cpu_table[] = {
1251 { "v7", MASK_ISA, 0 },
1252 { "cypress", MASK_ISA, 0 },
1253 { "v8", MASK_ISA, MASK_V8 },
1254 /* TI TMS390Z55 supersparc */
1255 { "supersparc", MASK_ISA, MASK_V8 },
1256 { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
1257 { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
1258 { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
1259 { "leon3v7", MASK_ISA, MASK_LEON3|MASK_FPU },
1260 { "sparclite", MASK_ISA, MASK_SPARCLITE },
1261 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1262 { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
1263 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1264 { "f934", MASK_ISA, MASK_SPARCLITE|MASK_FPU },
1265 { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
1266 { "sparclet", MASK_ISA, MASK_SPARCLET },
1267 /* TEMIC sparclet */
1268 { "tsc701", MASK_ISA, MASK_SPARCLET },
1269 { "v9", MASK_ISA, MASK_V9 },
1270 /* UltraSPARC I, II, IIi */
1271 { "ultrasparc", MASK_ISA,
1272 /* Although insns using %y are deprecated, it is a clear win. */
1273 MASK_V9|MASK_DEPRECATED_V8_INSNS },
1274 /* UltraSPARC III */
1275 /* ??? Check if %y issue still holds true. */
1276 { "ultrasparc3", MASK_ISA,
1277 MASK_V9|MASK_DEPRECATED_V8_INSNS|MASK_VIS2 },
1279 { "niagara", MASK_ISA,
1280 MASK_V9|MASK_DEPRECATED_V8_INSNS },
1282 { "niagara2", MASK_ISA,
1283 MASK_V9|MASK_POPC|MASK_VIS2 },
1285 { "niagara3", MASK_ISA,
1286 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
1288 { "niagara4", MASK_ISA,
1289 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF|MASK_CBCOND },
1291 const struct cpu_table *cpu;
1295 if (sparc_debug_string != NULL)
1300 p = ASTRDUP (sparc_debug_string);
1301 while ((q = strtok (p, ",")) != NULL)
1315 if (! strcmp (q, "all"))
1316 mask = MASK_DEBUG_ALL;
1317 else if (! strcmp (q, "options"))
1318 mask = MASK_DEBUG_OPTIONS;
1320 error ("unknown -mdebug-%s switch", q);
1323 sparc_debug &= ~mask;
1325 sparc_debug |= mask;
1329 if (TARGET_DEBUG_OPTIONS)
1331 dump_target_flags("Initial target_flags", target_flags);
1332 dump_target_flags("target_flags_explicit", target_flags_explicit);
1335 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1336 SUBTARGET_OVERRIDE_OPTIONS;
1339 #ifndef SPARC_BI_ARCH
1340 /* Check for unsupported architecture size. */
1341 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
1342 error ("%s is not supported by this configuration",
1343 DEFAULT_ARCH32_P ? "-m64" : "-m32");
1346 /* We force all 64bit archs to use 128 bit long double */
1347 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
1349 error ("-mlong-double-64 not allowed with -m64");
1350 target_flags |= MASK_LONG_DOUBLE_128;
1353 /* Code model selection. */
1354 sparc_cmodel = SPARC_DEFAULT_CMODEL;
1356 #ifdef SPARC_BI_ARCH
1358 sparc_cmodel = CM_32;
1361 if (sparc_cmodel_string != NULL)
1365 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
1366 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
1368 if (cmodel->name == NULL)
1369 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
1371 sparc_cmodel = cmodel->value;
1374 error ("-mcmodel= is not supported on 32 bit systems");
1377 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1378 for (i = 8; i < 16; i++)
1379 if (!call_used_regs [i])
1381 error ("-fcall-saved-REG is not supported for out registers");
1382 call_used_regs [i] = 1;
1385 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
1387 /* Set the default CPU. */
1388 if (!global_options_set.x_sparc_cpu_and_features)
1390 for (def = &cpu_default[0]; def->cpu != -1; ++def)
1391 if (def->cpu == TARGET_CPU_DEFAULT)
1393 gcc_assert (def->cpu != -1);
1394 sparc_cpu_and_features = def->processor;
1397 if (!global_options_set.x_sparc_cpu)
1398 sparc_cpu = sparc_cpu_and_features;
1400 cpu = &cpu_table[(int) sparc_cpu_and_features];
1402 if (TARGET_DEBUG_OPTIONS)
1404 fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name);
1405 fprintf (stderr, "sparc_cpu: %s\n",
1406 cpu_table[(int) sparc_cpu].name);
1407 dump_target_flags ("cpu->disable", cpu->disable);
1408 dump_target_flags ("cpu->enable", cpu->enable);
1411 target_flags &= ~cpu->disable;
1412 target_flags |= (cpu->enable
1413 #ifndef HAVE_AS_FMAF_HPC_VIS3
1414 & ~(MASK_FMAF | MASK_VIS3)
1416 #ifndef HAVE_AS_SPARC4
1419 #ifndef HAVE_AS_LEON
1420 & ~(MASK_LEON | MASK_LEON3)
1424 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1425 the processor default. */
1426 if (target_flags_explicit & MASK_FPU)
1427 target_flags = (target_flags & ~MASK_FPU) | fpu;
1429 /* -mvis2 implies -mvis */
1431 target_flags |= MASK_VIS;
1433 /* -mvis3 implies -mvis2 and -mvis */
1435 target_flags |= MASK_VIS2 | MASK_VIS;
1437 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is
1440 target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_FMAF);
1442 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1444 -m64 also implies v9. */
1445 if (TARGET_VIS || TARGET_ARCH64)
1447 target_flags |= MASK_V9;
1448 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
1451 /* -mvis also implies -mv8plus on 32-bit */
1452 if (TARGET_VIS && ! TARGET_ARCH64)
1453 target_flags |= MASK_V8PLUS;
1455 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1456 if (TARGET_V9 && TARGET_ARCH32)
1457 target_flags |= MASK_DEPRECATED_V8_INSNS;
1459 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1460 if (! TARGET_V9 || TARGET_ARCH64)
1461 target_flags &= ~MASK_V8PLUS;
1463 /* Don't use stack biasing in 32 bit mode. */
1465 target_flags &= ~MASK_STACK_BIAS;
1467 /* Supply a default value for align_functions. */
1468 if (align_functions == 0
1469 && (sparc_cpu == PROCESSOR_ULTRASPARC
1470 || sparc_cpu == PROCESSOR_ULTRASPARC3
1471 || sparc_cpu == PROCESSOR_NIAGARA
1472 || sparc_cpu == PROCESSOR_NIAGARA2
1473 || sparc_cpu == PROCESSOR_NIAGARA3
1474 || sparc_cpu == PROCESSOR_NIAGARA4))
1475 align_functions = 32;
1477 /* Validate PCC_STRUCT_RETURN. */
1478 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
1479 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
1481 /* Only use .uaxword when compiling for a 64-bit target. */
1483 targetm.asm_out.unaligned_op.di = NULL;
1485 /* Do various machine dependent initializations. */
1486 sparc_init_modes ();
1488 /* Set up function hooks. */
1489 init_machine_status = sparc_init_machine_status;
1494 case PROCESSOR_CYPRESS:
1495 sparc_costs = &cypress_costs;
1498 case PROCESSOR_SPARCLITE:
1499 case PROCESSOR_SUPERSPARC:
1500 sparc_costs = &supersparc_costs;
1502 case PROCESSOR_F930:
1503 case PROCESSOR_F934:
1504 case PROCESSOR_HYPERSPARC:
1505 case PROCESSOR_SPARCLITE86X:
1506 sparc_costs = &hypersparc_costs;
1508 case PROCESSOR_LEON:
1509 sparc_costs = &leon_costs;
1511 case PROCESSOR_LEON3:
1512 case PROCESSOR_LEON3V7:
1513 sparc_costs = &leon3_costs;
1515 case PROCESSOR_SPARCLET:
1516 case PROCESSOR_TSC701:
1517 sparc_costs = &sparclet_costs;
1520 case PROCESSOR_ULTRASPARC:
1521 sparc_costs = &ultrasparc_costs;
1523 case PROCESSOR_ULTRASPARC3:
1524 sparc_costs = &ultrasparc3_costs;
1526 case PROCESSOR_NIAGARA:
1527 sparc_costs = &niagara_costs;
1529 case PROCESSOR_NIAGARA2:
1530 sparc_costs = &niagara2_costs;
1532 case PROCESSOR_NIAGARA3:
1533 sparc_costs = &niagara3_costs;
1535 case PROCESSOR_NIAGARA4:
1536 sparc_costs = &niagara4_costs;
1538 case PROCESSOR_NATIVE:
1542 if (sparc_memory_model == SMM_DEFAULT)
1544 /* Choose the memory model for the operating system. */
1545 enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL;
1546 if (os_default != SMM_DEFAULT)
1547 sparc_memory_model = os_default;
1548 /* Choose the most relaxed model for the processor. */
1550 sparc_memory_model = SMM_RMO;
1551 else if (TARGET_LEON3)
1552 sparc_memory_model = SMM_TSO;
1553 else if (TARGET_LEON)
1554 sparc_memory_model = SMM_SC;
1556 sparc_memory_model = SMM_PSO;
1558 sparc_memory_model = SMM_SC;
1561 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1562 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1563 target_flags |= MASK_LONG_DOUBLE_128;
1566 if (TARGET_DEBUG_OPTIONS)
1567 dump_target_flags ("Final target_flags", target_flags);
1569 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
1570 ((sparc_cpu == PROCESSOR_ULTRASPARC
1571 || sparc_cpu == PROCESSOR_NIAGARA
1572 || sparc_cpu == PROCESSOR_NIAGARA2
1573 || sparc_cpu == PROCESSOR_NIAGARA3
1574 || sparc_cpu == PROCESSOR_NIAGARA4)
1576 : (sparc_cpu == PROCESSOR_ULTRASPARC3
1578 global_options.x_param_values,
1579 global_options_set.x_param_values);
1580 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
1581 ((sparc_cpu == PROCESSOR_ULTRASPARC
1582 || sparc_cpu == PROCESSOR_ULTRASPARC3
1583 || sparc_cpu == PROCESSOR_NIAGARA
1584 || sparc_cpu == PROCESSOR_NIAGARA2
1585 || sparc_cpu == PROCESSOR_NIAGARA3
1586 || sparc_cpu == PROCESSOR_NIAGARA4)
1588 global_options.x_param_values,
1589 global_options_set.x_param_values);
1591 /* Disable save slot sharing for call-clobbered registers by default.
1592 The IRA sharing algorithm works on single registers only and this
1593 pessimizes for double floating-point registers. */
1594 if (!global_options_set.x_flag_ira_share_save_slots)
1595 flag_ira_share_save_slots = 0;
1597 /* We register a machine specific pass to work around errata, if any.
1598 The pass mut be scheduled as late as possible so that we have the
1599 (essentially) final form of the insn stream to work on.
1600 Registering the pass must be done at start up. It's convenient to
1602 opt_pass *errata_pass = make_pass_work_around_errata (g);
1603 struct register_pass_info insert_pass_work_around_errata =
1605 errata_pass, /* pass */
1606 "dbr", /* reference_pass_name */
1607 1, /* ref_pass_instance_number */
1608 PASS_POS_INSERT_AFTER /* po_op */
1610 register_pass (&insert_pass_work_around_errata);
1613 /* Miscellaneous utilities. */
1615 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1616 or branch on register contents instructions. */
1619 v9_regcmp_p (enum rtx_code code)
1621 return (code == EQ || code == NE || code == GE || code == LT
1622 || code == LE || code == GT);
1625 /* Nonzero if OP is a floating point constant which can
1626 be loaded into an integer register using a single
1627 sethi instruction. */
1632 if (GET_CODE (op) == CONST_DOUBLE)
1636 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i);
1637 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
1643 /* Nonzero if OP is a floating point constant which can
1644 be loaded into an integer register using a single
1650 if (GET_CODE (op) == CONST_DOUBLE)
1654 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i);
1655 return SPARC_SIMM13_P (i);
1661 /* Nonzero if OP is a floating point constant which can
1662 be loaded into an integer register using a high/losum
1663 instruction sequence. */
1666 fp_high_losum_p (rtx op)
1668 /* The constraints calling this should only be in
1669 SFmode move insns, so any constant which cannot
1670 be moved using a single insn will do. */
1671 if (GET_CODE (op) == CONST_DOUBLE)
1675 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i);
1676 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
1682 /* Return true if the address of LABEL can be loaded by means of the
1683 mov{si,di}_pic_label_ref patterns in PIC mode. */
1686 can_use_mov_pic_label_ref (rtx label)
1688 /* VxWorks does not impose a fixed gap between segments; the run-time
1689 gap can be different from the object-file gap. We therefore can't
1690 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1691 are absolutely sure that X is in the same segment as the GOT.
1692 Unfortunately, the flexibility of linker scripts means that we
1693 can't be sure of that in general, so assume that GOT-relative
1694 accesses are never valid on VxWorks. */
1695 if (TARGET_VXWORKS_RTP)
1698 /* Similarly, if the label is non-local, it might end up being placed
1699 in a different section than the current one; now mov_pic_label_ref
1700 requires the label and the code to be in the same section. */
1701 if (LABEL_REF_NONLOCAL_P (label))
1704 /* Finally, if we are reordering basic blocks and partition into hot
1705 and cold sections, this might happen for any label. */
1706 if (flag_reorder_blocks_and_partition)
1712 /* Expand a move instruction. Return true if all work is done. */
1715 sparc_expand_move (machine_mode mode, rtx *operands)
1717 /* Handle sets of MEM first. */
1718 if (GET_CODE (operands[0]) == MEM)
1720 /* 0 is a register (or a pair of registers) on SPARC. */
1721 if (register_or_zero_operand (operands[1], mode))
1724 if (!reload_in_progress)
1726 operands[0] = validize_mem (operands[0]);
1727 operands[1] = force_reg (mode, operands[1]);
1731 /* Fixup TLS cases. */
1733 && CONSTANT_P (operands[1])
1734 && sparc_tls_referenced_p (operands [1]))
1736 operands[1] = sparc_legitimize_tls_address (operands[1]);
1740 /* Fixup PIC cases. */
1741 if (flag_pic && CONSTANT_P (operands[1]))
1743 if (pic_address_needs_scratch (operands[1]))
1744 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
1746 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1747 if (GET_CODE (operands[1]) == LABEL_REF
1748 && can_use_mov_pic_label_ref (operands[1]))
1752 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1758 gcc_assert (TARGET_ARCH64);
1759 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1764 if (symbolic_operand (operands[1], mode))
1767 = sparc_legitimize_pic_address (operands[1],
1769 ? operands[0] : NULL_RTX);
1774 /* If we are trying to toss an integer constant into FP registers,
1775 or loading a FP or vector constant, force it into memory. */
1776 if (CONSTANT_P (operands[1])
1777 && REG_P (operands[0])
1778 && (SPARC_FP_REG_P (REGNO (operands[0]))
1779 || SCALAR_FLOAT_MODE_P (mode)
1780 || VECTOR_MODE_P (mode)))
1782 /* emit_group_store will send such bogosity to us when it is
1783 not storing directly into memory. So fix this up to avoid
1784 crashes in output_constant_pool. */
1785 if (operands [1] == const0_rtx)
1786 operands[1] = CONST0_RTX (mode);
1788 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1789 always other regs. */
1790 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1791 && (const_zero_operand (operands[1], mode)
1792 || const_all_ones_operand (operands[1], mode)))
1795 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1796 /* We are able to build any SF constant in integer registers
1797 with at most 2 instructions. */
1799 /* And any DF constant in integer registers. */
1801 && ! can_create_pseudo_p ())))
1804 operands[1] = force_const_mem (mode, operands[1]);
1805 if (!reload_in_progress)
1806 operands[1] = validize_mem (operands[1]);
1810 /* Accept non-constants and valid constants unmodified. */
1811 if (!CONSTANT_P (operands[1])
1812 || GET_CODE (operands[1]) == HIGH
1813 || input_operand (operands[1], mode))
1819 /* All QImode constants require only one insn, so proceed. */
1824 sparc_emit_set_const32 (operands[0], operands[1]);
1828 /* input_operand should have filtered out 32-bit mode. */
1829 sparc_emit_set_const64 (operands[0], operands[1]);
1835 /* TImode isn't available in 32-bit mode. */
1836 split_double (operands[1], &high, &low);
1837 emit_insn (gen_movdi (operand_subword (operands[0], 0, 0, TImode),
1839 emit_insn (gen_movdi (operand_subword (operands[0], 1, 0, TImode),
1851 /* Load OP1, a 32-bit constant, into OP0, a register.
1852 We know it can't be done in one insn when we get
1853 here, the move expander guarantees this. */
1856 sparc_emit_set_const32 (rtx op0, rtx op1)
1858 machine_mode mode = GET_MODE (op0);
1861 if (can_create_pseudo_p ())
1862 temp = gen_reg_rtx (mode);
1864 if (GET_CODE (op1) == CONST_INT)
1866 gcc_assert (!small_int_operand (op1, mode)
1867 && !const_high_operand (op1, mode));
1869 /* Emit them as real moves instead of a HIGH/LO_SUM,
1870 this way CSE can see everything and reuse intermediate
1871 values if it wants. */
1872 emit_insn (gen_rtx_SET (temp, GEN_INT (INTVAL (op1)
1873 & ~(HOST_WIDE_INT) 0x3ff)));
1875 emit_insn (gen_rtx_SET (op0,
1876 gen_rtx_IOR (mode, temp,
1877 GEN_INT (INTVAL (op1) & 0x3ff))));
1881 /* A symbol, emit in the traditional way. */
1882 emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (mode, op1)));
1883 emit_insn (gen_rtx_SET (op0, gen_rtx_LO_SUM (mode, temp, op1)));
1887 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1888 If TEMP is nonzero, we are forbidden to use any other scratch
1889 registers. Otherwise, we are allowed to generate them as needed.
1891 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1892 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1895 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1897 rtx temp1, temp2, temp3, temp4, temp5;
1900 if (temp && GET_MODE (temp) == TImode)
1903 temp = gen_rtx_REG (DImode, REGNO (temp));
1906 /* SPARC-V9 code-model support. */
1907 switch (sparc_cmodel)
1910 /* The range spanned by all instructions in the object is less
1911 than 2^31 bytes (2GB) and the distance from any instruction
1912 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1913 than 2^31 bytes (2GB).
1915 The executable must be in the low 4TB of the virtual address
1918 sethi %hi(symbol), %temp1
1919 or %temp1, %lo(symbol), %reg */
1921 temp1 = temp; /* op0 is allowed. */
1923 temp1 = gen_reg_rtx (DImode);
1925 emit_insn (gen_rtx_SET (temp1, gen_rtx_HIGH (DImode, op1)));
1926 emit_insn (gen_rtx_SET (op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1930 /* The range spanned by all instructions in the object is less
1931 than 2^31 bytes (2GB) and the distance from any instruction
1932 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1933 than 2^31 bytes (2GB).
1935 The executable must be in the low 16TB of the virtual address
1938 sethi %h44(symbol), %temp1
1939 or %temp1, %m44(symbol), %temp2
1940 sllx %temp2, 12, %temp3
1941 or %temp3, %l44(symbol), %reg */
1946 temp3 = temp; /* op0 is allowed. */
1950 temp1 = gen_reg_rtx (DImode);
1951 temp2 = gen_reg_rtx (DImode);
1952 temp3 = gen_reg_rtx (DImode);
1955 emit_insn (gen_seth44 (temp1, op1));
1956 emit_insn (gen_setm44 (temp2, temp1, op1));
1957 emit_insn (gen_rtx_SET (temp3,
1958 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1959 emit_insn (gen_setl44 (op0, temp3, op1));
1963 /* The range spanned by all instructions in the object is less
1964 than 2^31 bytes (2GB) and the distance from any instruction
1965 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1966 than 2^31 bytes (2GB).
1968 The executable can be placed anywhere in the virtual address
1971 sethi %hh(symbol), %temp1
1972 sethi %lm(symbol), %temp2
1973 or %temp1, %hm(symbol), %temp3
1974 sllx %temp3, 32, %temp4
1975 or %temp4, %temp2, %temp5
1976 or %temp5, %lo(symbol), %reg */
1979 /* It is possible that one of the registers we got for operands[2]
1980 might coincide with that of operands[0] (which is why we made
1981 it TImode). Pick the other one to use as our scratch. */
1982 if (rtx_equal_p (temp, op0))
1984 gcc_assert (ti_temp);
1985 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1988 temp2 = temp; /* op0 is _not_ allowed, see above. */
1995 temp1 = gen_reg_rtx (DImode);
1996 temp2 = gen_reg_rtx (DImode);
1997 temp3 = gen_reg_rtx (DImode);
1998 temp4 = gen_reg_rtx (DImode);
1999 temp5 = gen_reg_rtx (DImode);
2002 emit_insn (gen_sethh (temp1, op1));
2003 emit_insn (gen_setlm (temp2, op1));
2004 emit_insn (gen_sethm (temp3, temp1, op1));
2005 emit_insn (gen_rtx_SET (temp4,
2006 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
2007 emit_insn (gen_rtx_SET (temp5, gen_rtx_PLUS (DImode, temp4, temp2)));
2008 emit_insn (gen_setlo (op0, temp5, op1));
2012 /* Old old old backwards compatibility kruft here.
2013 Essentially it is MEDLOW with a fixed 64-bit
2014 virtual base added to all data segment addresses.
2015 Text-segment stuff is computed like MEDANY, we can't
2016 reuse the code above because the relocation knobs
2019 Data segment: sethi %hi(symbol), %temp1
2020 add %temp1, EMBMEDANY_BASE_REG, %temp2
2021 or %temp2, %lo(symbol), %reg */
2022 if (data_segment_operand (op1, GET_MODE (op1)))
2026 temp1 = temp; /* op0 is allowed. */
2031 temp1 = gen_reg_rtx (DImode);
2032 temp2 = gen_reg_rtx (DImode);
2035 emit_insn (gen_embmedany_sethi (temp1, op1));
2036 emit_insn (gen_embmedany_brsum (temp2, temp1));
2037 emit_insn (gen_embmedany_losum (op0, temp2, op1));
2040 /* Text segment: sethi %uhi(symbol), %temp1
2041 sethi %hi(symbol), %temp2
2042 or %temp1, %ulo(symbol), %temp3
2043 sllx %temp3, 32, %temp4
2044 or %temp4, %temp2, %temp5
2045 or %temp5, %lo(symbol), %reg */
2050 /* It is possible that one of the registers we got for operands[2]
2051 might coincide with that of operands[0] (which is why we made
2052 it TImode). Pick the other one to use as our scratch. */
2053 if (rtx_equal_p (temp, op0))
2055 gcc_assert (ti_temp);
2056 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
2059 temp2 = temp; /* op0 is _not_ allowed, see above. */
2066 temp1 = gen_reg_rtx (DImode);
2067 temp2 = gen_reg_rtx (DImode);
2068 temp3 = gen_reg_rtx (DImode);
2069 temp4 = gen_reg_rtx (DImode);
2070 temp5 = gen_reg_rtx (DImode);
2073 emit_insn (gen_embmedany_textuhi (temp1, op1));
2074 emit_insn (gen_embmedany_texthi (temp2, op1));
2075 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
2076 emit_insn (gen_rtx_SET (temp4,
2077 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
2078 emit_insn (gen_rtx_SET (temp5, gen_rtx_PLUS (DImode, temp4, temp2)));
2079 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
2088 /* These avoid problems when cross compiling. If we do not
2089 go through all this hair then the optimizer will see
2090 invalid REG_EQUAL notes or in some cases none at all. */
2091 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
2092 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
2093 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
2094 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
2096 /* The optimizer is not to assume anything about exactly
2097 which bits are set for a HIGH, they are unspecified.
2098 Unfortunately this leads to many missed optimizations
2099 during CSE. We mask out the non-HIGH bits, and matches
2100 a plain movdi, to alleviate this problem. */
2102 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
2104 return gen_rtx_SET (dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
2108 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
2110 return gen_rtx_SET (dest, GEN_INT (val));
2114 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
2116 return gen_rtx_IOR (DImode, src, GEN_INT (val));
2120 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
2122 return gen_rtx_XOR (DImode, src, GEN_INT (val));
2125 /* Worker routines for 64-bit constant formation on arch64.
2126 One of the key things to be doing in these emissions is
2127 to create as many temp REGs as possible. This makes it
2128 possible for half-built constants to be used later when
2129 such values are similar to something required later on.
2130 Without doing this, the optimizer cannot see such
2133 static void sparc_emit_set_const64_quick1 (rtx, rtx,
2134 unsigned HOST_WIDE_INT, int);
2137 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
2138 unsigned HOST_WIDE_INT low_bits, int is_neg)
2140 unsigned HOST_WIDE_INT high_bits;
2143 high_bits = (~low_bits) & 0xffffffff;
2145 high_bits = low_bits;
2147 emit_insn (gen_safe_HIGH64 (temp, high_bits));
2150 emit_insn (gen_rtx_SET (op0, gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2154 /* If we are XOR'ing with -1, then we should emit a one's complement
2155 instead. This way the combiner will notice logical operations
2156 such as ANDN later on and substitute. */
2157 if ((low_bits & 0x3ff) == 0x3ff)
2159 emit_insn (gen_rtx_SET (op0, gen_rtx_NOT (DImode, temp)));
2163 emit_insn (gen_rtx_SET (op0,
2164 gen_safe_XOR64 (temp,
2165 (-(HOST_WIDE_INT)0x400
2166 | (low_bits & 0x3ff)))));
2171 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
2172 unsigned HOST_WIDE_INT, int);
2175 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
2176 unsigned HOST_WIDE_INT high_bits,
2177 unsigned HOST_WIDE_INT low_immediate,
2182 if ((high_bits & 0xfffffc00) != 0)
2184 emit_insn (gen_safe_HIGH64 (temp, high_bits));
2185 if ((high_bits & ~0xfffffc00) != 0)
2186 emit_insn (gen_rtx_SET (op0,
2187 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2193 emit_insn (gen_safe_SET64 (temp, high_bits));
2197 /* Now shift it up into place. */
2198 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, temp2,
2199 GEN_INT (shift_count))));
2201 /* If there is a low immediate part piece, finish up by
2202 putting that in as well. */
2203 if (low_immediate != 0)
2204 emit_insn (gen_rtx_SET (op0, gen_safe_OR64 (op0, low_immediate)));
2207 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
2208 unsigned HOST_WIDE_INT);
2210 /* Full 64-bit constant decomposition. Even though this is the
2211 'worst' case, we still optimize a few things away. */
2213 sparc_emit_set_const64_longway (rtx op0, rtx temp,
2214 unsigned HOST_WIDE_INT high_bits,
2215 unsigned HOST_WIDE_INT low_bits)
2219 if (can_create_pseudo_p ())
2220 sub_temp = gen_reg_rtx (DImode);
2222 if ((high_bits & 0xfffffc00) != 0)
2224 emit_insn (gen_safe_HIGH64 (temp, high_bits));
2225 if ((high_bits & ~0xfffffc00) != 0)
2226 emit_insn (gen_rtx_SET (sub_temp,
2227 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2233 emit_insn (gen_safe_SET64 (temp, high_bits));
2237 if (can_create_pseudo_p ())
2239 rtx temp2 = gen_reg_rtx (DImode);
2240 rtx temp3 = gen_reg_rtx (DImode);
2241 rtx temp4 = gen_reg_rtx (DImode);
2243 emit_insn (gen_rtx_SET (temp4, gen_rtx_ASHIFT (DImode, sub_temp,
2246 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
2247 if ((low_bits & ~0xfffffc00) != 0)
2249 emit_insn (gen_rtx_SET (temp3,
2250 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2251 emit_insn (gen_rtx_SET (op0, gen_rtx_PLUS (DImode, temp4, temp3)));
2255 emit_insn (gen_rtx_SET (op0, gen_rtx_PLUS (DImode, temp4, temp2)));
2260 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2261 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2262 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2265 /* We are in the middle of reload, so this is really
2266 painful. However we do still make an attempt to
2267 avoid emitting truly stupid code. */
2268 if (low1 != const0_rtx)
2270 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp,
2271 GEN_INT (to_shift))));
2272 emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low1)));
2280 if (low2 != const0_rtx)
2282 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp,
2283 GEN_INT (to_shift))));
2284 emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low2)));
2292 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp,
2293 GEN_INT (to_shift))));
2294 if (low3 != const0_rtx)
2295 emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low3)));
2300 /* Analyze a 64-bit constant for certain properties. */
2301 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2302 unsigned HOST_WIDE_INT,
2303 int *, int *, int *);
2306 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2307 unsigned HOST_WIDE_INT low_bits,
2308 int *hbsp, int *lbsp, int *abbasp)
2310 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2313 lowest_bit_set = highest_bit_set = -1;
2317 if ((lowest_bit_set == -1)
2318 && ((low_bits >> i) & 1))
2320 if ((highest_bit_set == -1)
2321 && ((high_bits >> (32 - i - 1)) & 1))
2322 highest_bit_set = (64 - i - 1);
2325 && ((highest_bit_set == -1)
2326 || (lowest_bit_set == -1)));
2332 if ((lowest_bit_set == -1)
2333 && ((high_bits >> i) & 1))
2334 lowest_bit_set = i + 32;
2335 if ((highest_bit_set == -1)
2336 && ((low_bits >> (32 - i - 1)) & 1))
2337 highest_bit_set = 32 - i - 1;
2340 && ((highest_bit_set == -1)
2341 || (lowest_bit_set == -1)));
2343 /* If there are no bits set this should have gone out
2344 as one instruction! */
2345 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
2346 all_bits_between_are_set = 1;
2347 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2351 if ((low_bits & (1 << i)) != 0)
2356 if ((high_bits & (1 << (i - 32))) != 0)
2359 all_bits_between_are_set = 0;
2362 *hbsp = highest_bit_set;
2363 *lbsp = lowest_bit_set;
2364 *abbasp = all_bits_between_are_set;
2367 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2370 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2371 unsigned HOST_WIDE_INT low_bits)
2373 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2376 || high_bits == 0xffffffff)
2379 analyze_64bit_constant (high_bits, low_bits,
2380 &highest_bit_set, &lowest_bit_set,
2381 &all_bits_between_are_set);
2383 if ((highest_bit_set == 63
2384 || lowest_bit_set == 0)
2385 && all_bits_between_are_set != 0)
2388 if ((highest_bit_set - lowest_bit_set) < 21)
2394 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2395 unsigned HOST_WIDE_INT,
2398 static unsigned HOST_WIDE_INT
2399 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2400 unsigned HOST_WIDE_INT low_bits,
2401 int lowest_bit_set, int shift)
2403 HOST_WIDE_INT hi, lo;
2405 if (lowest_bit_set < 32)
2407 lo = (low_bits >> lowest_bit_set) << shift;
2408 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2413 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2415 gcc_assert (! (hi & lo));
2419 /* Here we are sure to be arch64 and this is an integer constant
2420 being loaded into a register. Emit the most efficient
2421 insn sequence possible. Detection of all the 1-insn cases
2422 has been done already. */
2424 sparc_emit_set_const64 (rtx op0, rtx op1)
2426 unsigned HOST_WIDE_INT high_bits, low_bits;
2427 int lowest_bit_set, highest_bit_set;
2428 int all_bits_between_are_set;
2431 /* Sanity check that we know what we are working with. */
2432 gcc_assert (TARGET_ARCH64
2433 && (GET_CODE (op0) == SUBREG
2434 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
2436 if (! can_create_pseudo_p ())
2439 if (GET_CODE (op1) != CONST_INT)
2441 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2446 temp = gen_reg_rtx (DImode);
2448 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2449 low_bits = (INTVAL (op1) & 0xffffffff);
2451 /* low_bits bits 0 --> 31
2452 high_bits bits 32 --> 63 */
2454 analyze_64bit_constant (high_bits, low_bits,
2455 &highest_bit_set, &lowest_bit_set,
2456 &all_bits_between_are_set);
2458 /* First try for a 2-insn sequence. */
2460 /* These situations are preferred because the optimizer can
2461 * do more things with them:
2463 * sllx %reg, shift, %reg
2465 * srlx %reg, shift, %reg
2466 * 3) mov some_small_const, %reg
2467 * sllx %reg, shift, %reg
2469 if (((highest_bit_set == 63
2470 || lowest_bit_set == 0)
2471 && all_bits_between_are_set != 0)
2472 || ((highest_bit_set - lowest_bit_set) < 12))
2474 HOST_WIDE_INT the_const = -1;
2475 int shift = lowest_bit_set;
2477 if ((highest_bit_set != 63
2478 && lowest_bit_set != 0)
2479 || all_bits_between_are_set == 0)
2482 create_simple_focus_bits (high_bits, low_bits,
2485 else if (lowest_bit_set == 0)
2486 shift = -(63 - highest_bit_set);
2488 gcc_assert (SPARC_SIMM13_P (the_const));
2489 gcc_assert (shift != 0);
2491 emit_insn (gen_safe_SET64 (temp, the_const));
2493 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, temp,
2496 emit_insn (gen_rtx_SET (op0, gen_rtx_LSHIFTRT (DImode, temp,
2497 GEN_INT (-shift))));
2501 /* Now a range of 22 or less bits set somewhere.
2502 * 1) sethi %hi(focus_bits), %reg
2503 * sllx %reg, shift, %reg
2504 * 2) sethi %hi(focus_bits), %reg
2505 * srlx %reg, shift, %reg
2507 if ((highest_bit_set - lowest_bit_set) < 21)
2509 unsigned HOST_WIDE_INT focus_bits =
2510 create_simple_focus_bits (high_bits, low_bits,
2511 lowest_bit_set, 10);
2513 gcc_assert (SPARC_SETHI_P (focus_bits));
2514 gcc_assert (lowest_bit_set != 10);
2516 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
2518 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2519 if (lowest_bit_set < 10)
2520 emit_insn (gen_rtx_SET (op0,
2521 gen_rtx_LSHIFTRT (DImode, temp,
2522 GEN_INT (10 - lowest_bit_set))));
2523 else if (lowest_bit_set > 10)
2524 emit_insn (gen_rtx_SET (op0,
2525 gen_rtx_ASHIFT (DImode, temp,
2526 GEN_INT (lowest_bit_set - 10))));
2530 /* 1) sethi %hi(low_bits), %reg
2531 * or %reg, %lo(low_bits), %reg
2532 * 2) sethi %hi(~low_bits), %reg
2533 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2536 || high_bits == 0xffffffff)
2538 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2539 (high_bits == 0xffffffff));
2543 /* Now, try 3-insn sequences. */
2545 /* 1) sethi %hi(high_bits), %reg
2546 * or %reg, %lo(high_bits), %reg
2547 * sllx %reg, 32, %reg
2551 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2555 /* We may be able to do something quick
2556 when the constant is negated, so try that. */
2557 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2558 (~low_bits) & 0xfffffc00))
2560 /* NOTE: The trailing bits get XOR'd so we need the
2561 non-negated bits, not the negated ones. */
2562 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2564 if ((((~high_bits) & 0xffffffff) == 0
2565 && ((~low_bits) & 0x80000000) == 0)
2566 || (((~high_bits) & 0xffffffff) == 0xffffffff
2567 && ((~low_bits) & 0x80000000) != 0))
2569 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
2571 if ((SPARC_SETHI_P (fast_int)
2572 && (~high_bits & 0xffffffff) == 0)
2573 || SPARC_SIMM13_P (fast_int))
2574 emit_insn (gen_safe_SET64 (temp, fast_int));
2576 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
2581 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2582 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2583 sparc_emit_set_const64 (temp, negated_const);
2586 /* If we are XOR'ing with -1, then we should emit a one's complement
2587 instead. This way the combiner will notice logical operations
2588 such as ANDN later on and substitute. */
2589 if (trailing_bits == 0x3ff)
2591 emit_insn (gen_rtx_SET (op0, gen_rtx_NOT (DImode, temp)));
2595 emit_insn (gen_rtx_SET (op0,
2596 gen_safe_XOR64 (temp,
2597 (-0x400 | trailing_bits))));
2602 /* 1) sethi %hi(xxx), %reg
2603 * or %reg, %lo(xxx), %reg
2604 * sllx %reg, yyy, %reg
2606 * ??? This is just a generalized version of the low_bits==0
2607 * thing above, FIXME...
2609 if ((highest_bit_set - lowest_bit_set) < 32)
2611 unsigned HOST_WIDE_INT focus_bits =
2612 create_simple_focus_bits (high_bits, low_bits,
2615 /* We can't get here in this state. */
2616 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
2618 /* So what we know is that the set bits straddle the
2619 middle of the 64-bit word. */
2620 sparc_emit_set_const64_quick2 (op0, temp,
2626 /* 1) sethi %hi(high_bits), %reg
2627 * or %reg, %lo(high_bits), %reg
2628 * sllx %reg, 32, %reg
2629 * or %reg, low_bits, %reg
2631 if (SPARC_SIMM13_P (low_bits) && ((int)low_bits > 0))
2633 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2637 /* The easiest way when all else fails, is full decomposition. */
2638 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2641 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2642 return the mode to be used for the comparison. For floating-point,
2643 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2644 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2645 processing is needed. */
2648 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2650 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2676 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2677 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2679 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2680 return CCX_NOOVmode;
2686 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2693 /* Emit the compare insn and return the CC reg for a CODE comparison
2694 with operands X and Y. */
2697 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
2702 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2705 mode = SELECT_CC_MODE (code, x, y);
2707 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2708 fcc regs (cse can't tell they're really call clobbered regs and will
2709 remove a duplicate comparison even if there is an intervening function
2710 call - it will then try to reload the cc reg via an int reg which is why
2711 we need the movcc patterns). It is possible to provide the movcc
2712 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2713 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2714 to tell cse that CCFPE mode registers (even pseudos) are call
2717 /* ??? This is an experiment. Rather than making changes to cse which may
2718 or may not be easy/clean, we do our own cse. This is possible because
2719 we will generate hard registers. Cse knows they're call clobbered (it
2720 doesn't know the same thing about pseudos). If we guess wrong, no big
2721 deal, but if we win, great! */
2723 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2724 #if 1 /* experiment */
2727 /* We cycle through the registers to ensure they're all exercised. */
2728 static int next_fcc_reg = 0;
2729 /* Previous x,y for each fcc reg. */
2730 static rtx prev_args[4][2];
2732 /* Scan prev_args for x,y. */
2733 for (reg = 0; reg < 4; reg++)
2734 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2739 prev_args[reg][0] = x;
2740 prev_args[reg][1] = y;
2741 next_fcc_reg = (next_fcc_reg + 1) & 3;
2743 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2746 cc_reg = gen_reg_rtx (mode);
2747 #endif /* ! experiment */
2748 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2749 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2751 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2753 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2754 will only result in an unrecognizable insn so no point in asserting. */
2755 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (mode, x, y)));
2761 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2764 gen_compare_reg (rtx cmp)
2766 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
2769 /* This function is used for v9 only.
2770 DEST is the target of the Scc insn.
2771 CODE is the code for an Scc's comparison.
2772 X and Y are the values we compare.
2774 This function is needed to turn
2777 (gt (reg:CCX 100 %icc)
2781 (gt:DI (reg:CCX 100 %icc)
2784 IE: The instruction recognizer needs to see the mode of the comparison to
2785 find the right instruction. We could use "gt:DI" right in the
2786 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2789 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
2792 && (GET_MODE (x) == DImode
2793 || GET_MODE (dest) == DImode))
2796 /* Try to use the movrCC insns. */
2798 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2800 && v9_regcmp_p (compare_code))
2805 /* Special case for op0 != 0. This can be done with one instruction if
2808 if (compare_code == NE
2809 && GET_MODE (dest) == DImode
2810 && rtx_equal_p (op0, dest))
2812 emit_insn (gen_rtx_SET (dest,
2813 gen_rtx_IF_THEN_ELSE (DImode,
2814 gen_rtx_fmt_ee (compare_code, DImode,
2821 if (reg_overlap_mentioned_p (dest, op0))
2823 /* Handle the case where dest == x.
2824 We "early clobber" the result. */
2825 op0 = gen_reg_rtx (GET_MODE (x));
2826 emit_move_insn (op0, x);
2829 emit_insn (gen_rtx_SET (dest, const0_rtx));
2830 if (GET_MODE (op0) != DImode)
2832 temp = gen_reg_rtx (DImode);
2833 convert_move (temp, op0, 0);
2837 emit_insn (gen_rtx_SET (dest,
2838 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2839 gen_rtx_fmt_ee (compare_code, DImode,
2847 x = gen_compare_reg_1 (compare_code, x, y);
2850 gcc_assert (GET_MODE (x) != CC_NOOVmode
2851 && GET_MODE (x) != CCX_NOOVmode);
2853 emit_insn (gen_rtx_SET (dest, const0_rtx));
2854 emit_insn (gen_rtx_SET (dest,
2855 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2856 gen_rtx_fmt_ee (compare_code,
2857 GET_MODE (x), x, y),
2858 const1_rtx, dest)));
2864 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2865 without jumps using the addx/subx instructions. */
2868 emit_scc_insn (rtx operands[])
2875 /* The quad-word fp compare library routines all return nonzero to indicate
2876 true, which is different from the equivalent libgcc routines, so we must
2877 handle them specially here. */
2878 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2880 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2881 GET_CODE (operands[1]));
2882 operands[2] = XEXP (operands[1], 0);
2883 operands[3] = XEXP (operands[1], 1);
2886 code = GET_CODE (operands[1]);
2890 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2891 more applications). The exception to this is "reg != 0" which can
2892 be done in one instruction on v9 (so we do it). */
2895 if (GET_MODE (x) == SImode)
2899 pat = gen_seqsidi_special (operands[0], x, y);
2901 pat = gen_seqsisi_special (operands[0], x, y);
2905 else if (GET_MODE (x) == DImode)
2907 rtx pat = gen_seqdi_special (operands[0], x, y);
2915 if (GET_MODE (x) == SImode)
2919 pat = gen_snesidi_special (operands[0], x, y);
2921 pat = gen_snesisi_special (operands[0], x, y);
2925 else if (GET_MODE (x) == DImode)
2929 pat = gen_snedi_special_vis3 (operands[0], x, y);
2931 pat = gen_snedi_special (operands[0], x, y);
2939 && GET_MODE (x) == DImode
2941 && (code == GTU || code == LTU))
2942 && gen_v9_scc (operands[0], code, x, y))
2945 /* We can do LTU and GEU using the addx/subx instructions too. And
2946 for GTU/LEU, if both operands are registers swap them and fall
2947 back to the easy case. */
2948 if (code == GTU || code == LEU)
2950 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2951 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2956 code = swap_condition (code);
2961 || (!TARGET_VIS3 && code == GEU))
2963 emit_insn (gen_rtx_SET (operands[0],
2964 gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2965 gen_compare_reg_1 (code, x, y),
2970 /* All the posibilities to use addx/subx based sequences has been
2971 exhausted, try for a 3 instruction sequence using v9 conditional
2973 if (TARGET_V9 && gen_v9_scc (operands[0], code, x, y))
2976 /* Nope, do branches. */
2980 /* Emit a conditional jump insn for the v9 architecture using comparison code
2981 CODE and jump target LABEL.
2982 This function exists to take advantage of the v9 brxx insns. */
2985 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2987 emit_jump_insn (gen_rtx_SET (pc_rtx,
2988 gen_rtx_IF_THEN_ELSE (VOIDmode,
2989 gen_rtx_fmt_ee (code, GET_MODE (op0),
2991 gen_rtx_LABEL_REF (VOIDmode, label),
2995 /* Emit a conditional jump insn for the UA2011 architecture using
2996 comparison code CODE and jump target LABEL. This function exists
2997 to take advantage of the UA2011 Compare and Branch insns. */
3000 emit_cbcond_insn (enum rtx_code code, rtx op0, rtx op1, rtx label)
3004 if_then_else = gen_rtx_IF_THEN_ELSE (VOIDmode,
3005 gen_rtx_fmt_ee(code, GET_MODE(op0),
3007 gen_rtx_LABEL_REF (VOIDmode, label),
3010 emit_jump_insn (gen_rtx_SET (pc_rtx, if_then_else));
3014 emit_conditional_branch_insn (rtx operands[])
3016 /* The quad-word fp compare library routines all return nonzero to indicate
3017 true, which is different from the equivalent libgcc routines, so we must
3018 handle them specially here. */
3019 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
3021 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
3022 GET_CODE (operands[0]));
3023 operands[1] = XEXP (operands[0], 0);
3024 operands[2] = XEXP (operands[0], 1);
3027 /* If we can tell early on that the comparison is against a constant
3028 that won't fit in the 5-bit signed immediate field of a cbcond,
3029 use one of the other v9 conditional branch sequences. */
3031 && GET_CODE (operands[1]) == REG
3032 && (GET_MODE (operands[1]) == SImode
3033 || (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
3034 && (GET_CODE (operands[2]) != CONST_INT
3035 || SPARC_SIMM5_P (INTVAL (operands[2]))))
3037 emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2], operands[3]);
3041 if (TARGET_ARCH64 && operands[2] == const0_rtx
3042 && GET_CODE (operands[1]) == REG
3043 && GET_MODE (operands[1]) == DImode)
3045 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
3049 operands[1] = gen_compare_reg (operands[0]);
3050 operands[2] = const0_rtx;
3051 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
3052 operands[1], operands[2]);
3053 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
3058 /* Generate a DFmode part of a hard TFmode register.
3059 REG is the TFmode hard register, LOW is 1 for the
3060 low 64bit of the register and 0 otherwise.
3063 gen_df_reg (rtx reg, int low)
3065 int regno = REGNO (reg);
3067 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
3068 regno += (TARGET_ARCH64 && SPARC_INT_REG_P (regno)) ? 1 : 2;
3069 return gen_rtx_REG (DFmode, regno);
3072 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3073 Unlike normal calls, TFmode operands are passed by reference. It is
3074 assumed that no more than 3 operands are required. */
3077 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
3079 rtx ret_slot = NULL, arg[3], func_sym;
3082 /* We only expect to be called for conversions, unary, and binary ops. */
3083 gcc_assert (nargs == 2 || nargs == 3);
3085 for (i = 0; i < nargs; ++i)
3087 rtx this_arg = operands[i];
3090 /* TFmode arguments and return values are passed by reference. */
3091 if (GET_MODE (this_arg) == TFmode)
3093 int force_stack_temp;
3095 force_stack_temp = 0;
3096 if (TARGET_BUGGY_QP_LIB && i == 0)
3097 force_stack_temp = 1;
3099 if (GET_CODE (this_arg) == MEM
3100 && ! force_stack_temp)
3102 tree expr = MEM_EXPR (this_arg);
3104 mark_addressable (expr);
3105 this_arg = XEXP (this_arg, 0);
3107 else if (CONSTANT_P (this_arg)
3108 && ! force_stack_temp)
3110 this_slot = force_const_mem (TFmode, this_arg);
3111 this_arg = XEXP (this_slot, 0);
3115 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode));
3117 /* Operand 0 is the return value. We'll copy it out later. */
3119 emit_move_insn (this_slot, this_arg);
3121 ret_slot = this_slot;
3123 this_arg = XEXP (this_slot, 0);
3130 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
3132 if (GET_MODE (operands[0]) == TFmode)
3135 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
3136 arg[0], GET_MODE (arg[0]),
3137 arg[1], GET_MODE (arg[1]));
3139 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
3140 arg[0], GET_MODE (arg[0]),
3141 arg[1], GET_MODE (arg[1]),
3142 arg[2], GET_MODE (arg[2]));
3145 emit_move_insn (operands[0], ret_slot);
3151 gcc_assert (nargs == 2);
3153 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
3154 GET_MODE (operands[0]), 1,
3155 arg[1], GET_MODE (arg[1]));
3157 if (ret != operands[0])
3158 emit_move_insn (operands[0], ret);
3162 /* Expand soft-float TFmode calls to sparc abi routines. */
3165 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
3187 emit_soft_tfmode_libcall (func, 3, operands);
3191 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
3195 gcc_assert (code == SQRT);
3198 emit_soft_tfmode_libcall (func, 2, operands);
3202 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
3209 switch (GET_MODE (operands[1]))
3222 case FLOAT_TRUNCATE:
3223 switch (GET_MODE (operands[0]))
3237 switch (GET_MODE (operands[1]))
3242 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
3252 case UNSIGNED_FLOAT:
3253 switch (GET_MODE (operands[1]))
3258 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
3269 switch (GET_MODE (operands[0]))
3283 switch (GET_MODE (operands[0]))
3300 emit_soft_tfmode_libcall (func, 2, operands);
3303 /* Expand a hard-float tfmode operation. All arguments must be in
3307 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
3311 if (GET_RTX_CLASS (code) == RTX_UNARY)
3313 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
3314 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
3318 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
3319 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
3320 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
3321 operands[1], operands[2]);
3324 if (register_operand (operands[0], VOIDmode))
3327 dest = gen_reg_rtx (GET_MODE (operands[0]));
3329 emit_insn (gen_rtx_SET (dest, op));
3331 if (dest != operands[0])
3332 emit_move_insn (operands[0], dest);
3336 emit_tfmode_binop (enum rtx_code code, rtx *operands)
3338 if (TARGET_HARD_QUAD)
3339 emit_hard_tfmode_operation (code, operands);
3341 emit_soft_tfmode_binop (code, operands);
3345 emit_tfmode_unop (enum rtx_code code, rtx *operands)
3347 if (TARGET_HARD_QUAD)
3348 emit_hard_tfmode_operation (code, operands);
3350 emit_soft_tfmode_unop (code, operands);
3354 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
3356 if (TARGET_HARD_QUAD)
3357 emit_hard_tfmode_operation (code, operands);
3359 emit_soft_tfmode_cvt (code, operands);
3362 /* Return nonzero if a branch/jump/call instruction will be emitting
3363 nop into its delay slot. */
3366 empty_delay_slot (rtx_insn *insn)
3370 /* If no previous instruction (should not happen), return true. */
3371 if (PREV_INSN (insn) == NULL)
3374 seq = NEXT_INSN (PREV_INSN (insn));
3375 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3381 /* Return nonzero if we should emit a nop after a cbcond instruction.
3382 The cbcond instruction does not have a delay slot, however there is
3383 a severe performance penalty if a control transfer appears right
3384 after a cbcond. Therefore we emit a nop when we detect this
3388 emit_cbcond_nop (rtx insn)
3390 rtx next = next_active_insn (insn);
3395 if (NONJUMP_INSN_P (next)
3396 && GET_CODE (PATTERN (next)) == SEQUENCE)
3397 next = XVECEXP (PATTERN (next), 0, 0);
3398 else if (CALL_P (next)
3399 && GET_CODE (PATTERN (next)) == PARALLEL)
3401 rtx delay = XVECEXP (PATTERN (next), 0, 1);
3403 if (GET_CODE (delay) == RETURN)
3405 /* It's a sibling call. Do not emit the nop if we're going
3406 to emit something other than the jump itself as the first
3407 instruction of the sibcall sequence. */
3408 if (sparc_leaf_function_p || TARGET_FLAT)
3413 if (NONJUMP_INSN_P (next))
3419 /* Return nonzero if TRIAL can go into the call delay slot. */
3422 eligible_for_call_delay (rtx_insn *trial)
3426 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
3430 call __tls_get_addr, %tgd_call (foo)
3431 add %l7, %o0, %o0, %tgd_add (foo)
3432 while Sun as/ld does not. */
3433 if (TARGET_GNU_TLS || !TARGET_TLS)
3436 pat = PATTERN (trial);
3438 /* We must reject tgd_add{32|64}, i.e.
3439 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3440 and tldm_add{32|64}, i.e.
3441 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3443 if (GET_CODE (pat) == SET
3444 && GET_CODE (SET_SRC (pat)) == PLUS)
3446 rtx unspec = XEXP (SET_SRC (pat), 1);
3448 if (GET_CODE (unspec) == UNSPEC
3449 && (XINT (unspec, 1) == UNSPEC_TLSGD
3450 || XINT (unspec, 1) == UNSPEC_TLSLDM))
3457 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3458 instruction. RETURN_P is true if the v9 variant 'return' is to be
3459 considered in the test too.
3461 TRIAL must be a SET whose destination is a REG appropriate for the
3462 'restore' instruction or, if RETURN_P is true, for the 'return'
3466 eligible_for_restore_insn (rtx trial, bool return_p)
3468 rtx pat = PATTERN (trial);
3469 rtx src = SET_SRC (pat);
3470 bool src_is_freg = false;
3473 /* Since we now can do moves between float and integer registers when
3474 VIS3 is enabled, we have to catch this case. We can allow such
3475 moves when doing a 'return' however. */
3477 if (GET_CODE (src_reg) == SUBREG)
3478 src_reg = SUBREG_REG (src_reg);
3479 if (GET_CODE (src_reg) == REG
3480 && SPARC_FP_REG_P (REGNO (src_reg)))
3483 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3484 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3485 && arith_operand (src, GET_MODE (src))
3489 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3491 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3494 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3495 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3496 && arith_double_operand (src, GET_MODE (src))
3498 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3500 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3501 else if (! TARGET_FPU && register_operand (src, SFmode))
3504 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3505 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3508 /* If we have the 'return' instruction, anything that does not use
3509 local or output registers and can go into a delay slot wins. */
3510 else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1))
3513 /* The 'restore src1,src2,dest' pattern for SImode. */
3514 else if (GET_CODE (src) == PLUS
3515 && register_operand (XEXP (src, 0), SImode)
3516 && arith_operand (XEXP (src, 1), SImode))
3519 /* The 'restore src1,src2,dest' pattern for DImode. */
3520 else if (GET_CODE (src) == PLUS
3521 && register_operand (XEXP (src, 0), DImode)
3522 && arith_double_operand (XEXP (src, 1), DImode))
3525 /* The 'restore src1,%lo(src2),dest' pattern. */
3526 else if (GET_CODE (src) == LO_SUM
3527 && ! TARGET_CM_MEDMID
3528 && ((register_operand (XEXP (src, 0), SImode)
3529 && immediate_operand (XEXP (src, 1), SImode))
3531 && register_operand (XEXP (src, 0), DImode)
3532 && immediate_operand (XEXP (src, 1), DImode))))
3535 /* The 'restore src,src,dest' pattern. */
3536 else if (GET_CODE (src) == ASHIFT
3537 && (register_operand (XEXP (src, 0), SImode)
3538 || register_operand (XEXP (src, 0), DImode))
3539 && XEXP (src, 1) == const1_rtx)
3545 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3548 eligible_for_return_delay (rtx_insn *trial)
3553 /* If the function uses __builtin_eh_return, the eh_return machinery
3554 occupies the delay slot. */
3555 if (crtl->calls_eh_return)
3558 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
3561 /* In the case of a leaf or flat function, anything can go into the slot. */
3562 if (sparc_leaf_function_p || TARGET_FLAT)
3565 if (!NONJUMP_INSN_P (trial))
3568 pat = PATTERN (trial);
3569 if (GET_CODE (pat) == PARALLEL)
3575 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
3577 rtx expr = XVECEXP (pat, 0, i);
3578 if (GET_CODE (expr) != SET)
3580 if (GET_CODE (SET_DEST (expr)) != REG)
3582 regno = REGNO (SET_DEST (expr));
3583 if (regno >= 8 && regno < 24)
3586 return !epilogue_renumber (&pat, 1);
3589 if (GET_CODE (pat) != SET)
3592 if (GET_CODE (SET_DEST (pat)) != REG)
3595 regno = REGNO (SET_DEST (pat));
3597 /* Otherwise, only operations which can be done in tandem with
3598 a `restore' or `return' insn can go into the delay slot. */
3599 if (regno >= 8 && regno < 24)
3602 /* If this instruction sets up floating point register and we have a return
3603 instruction, it can probably go in. But restore will not work
3605 if (! SPARC_INT_REG_P (regno))
3606 return TARGET_V9 && !epilogue_renumber (&pat, 1);
3608 return eligible_for_restore_insn (trial, true);
3611 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3614 eligible_for_sibcall_delay (rtx_insn *trial)
3618 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE)
3621 if (!NONJUMP_INSN_P (trial))
3624 pat = PATTERN (trial);
3626 if (sparc_leaf_function_p || TARGET_FLAT)
3628 /* If the tail call is done using the call instruction,
3629 we have to restore %o7 in the delay slot. */
3630 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3633 /* %g1 is used to build the function address */
3634 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3640 if (GET_CODE (pat) != SET)
3643 /* Otherwise, only operations which can be done in tandem with
3644 a `restore' insn can go into the delay slot. */
3645 if (GET_CODE (SET_DEST (pat)) != REG
3646 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3647 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat))))
3650 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3652 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3655 return eligible_for_restore_insn (trial, false);
3658 /* Determine if it's legal to put X into the constant pool. This
3659 is not possible if X contains the address of a symbol that is
3660 not constant (TLS) or not known at final link time (PIC). */
3663 sparc_cannot_force_const_mem (machine_mode mode, rtx x)
3665 switch (GET_CODE (x))
3668 case CONST_WIDE_INT:
3671 /* Accept all non-symbolic constants. */
3675 /* Labels are OK iff we are non-PIC. */
3676 return flag_pic != 0;
3679 /* 'Naked' TLS symbol references are never OK,
3680 non-TLS symbols are OK iff we are non-PIC. */
3681 if (SYMBOL_REF_TLS_MODEL (x))
3684 return flag_pic != 0;
3687 return sparc_cannot_force_const_mem (mode, XEXP (x, 0));
3690 return sparc_cannot_force_const_mem (mode, XEXP (x, 0))
3691 || sparc_cannot_force_const_mem (mode, XEXP (x, 1));
3699 /* Global Offset Table support. */
3700 static GTY(()) rtx got_helper_rtx = NULL_RTX;
3701 static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
3703 /* Return the SYMBOL_REF for the Global Offset Table. */
3705 static GTY(()) rtx sparc_got_symbol = NULL_RTX;
3710 if (!sparc_got_symbol)
3711 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3713 return sparc_got_symbol;
3716 /* Ensure that we are not using patterns that are not OK with PIC. */
3726 op = recog_data.operand[i];
3727 gcc_assert (GET_CODE (op) != SYMBOL_REF
3728 && (GET_CODE (op) != CONST
3729 || (GET_CODE (XEXP (op, 0)) == MINUS
3730 && XEXP (XEXP (op, 0), 0) == sparc_got ()
3731 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
3738 /* Return true if X is an address which needs a temporary register when
3739 reloaded while generating PIC code. */
3742 pic_address_needs_scratch (rtx x)
3744 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3745 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3746 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3747 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3748 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3754 /* Determine if a given RTX is a valid constant. We already know this
3755 satisfies CONSTANT_P. */
3758 sparc_legitimate_constant_p (machine_mode mode, rtx x)
3760 switch (GET_CODE (x))
3764 if (sparc_tls_referenced_p (x))
3769 /* Floating point constants are generally not ok.
3770 The only exception is 0.0 and all-ones in VIS. */
3772 && SCALAR_FLOAT_MODE_P (mode)
3773 && (const_zero_operand (x, mode)
3774 || const_all_ones_operand (x, mode)))
3780 /* Vector constants are generally not ok.
3781 The only exception is 0 or -1 in VIS. */
3783 && (const_zero_operand (x, mode)
3784 || const_all_ones_operand (x, mode)))
3796 /* Determine if a given RTX is a valid constant address. */
3799 constant_address_p (rtx x)
3801 switch (GET_CODE (x))
3809 if (flag_pic && pic_address_needs_scratch (x))
3811 return sparc_legitimate_constant_p (Pmode, x);
3814 return !flag_pic && sparc_legitimate_constant_p (Pmode, x);
3821 /* Nonzero if the constant value X is a legitimate general operand
3822 when generating PIC code. It is given that flag_pic is on and
3823 that X satisfies CONSTANT_P. */
3826 legitimate_pic_operand_p (rtx x)
3828 if (pic_address_needs_scratch (x))
3830 if (sparc_tls_referenced_p (x))
3835 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3837 && INTVAL (X) >= -0x1000 \
3838 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
3840 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3842 && INTVAL (X) >= -0x1000 \
3843 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
3845 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3847 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3848 ordinarily. This changes a bit when generating PIC. */
3851 sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
3853 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3855 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3857 else if (GET_CODE (addr) == PLUS)
3859 rs1 = XEXP (addr, 0);
3860 rs2 = XEXP (addr, 1);
3862 /* Canonicalize. REG comes first, if there are no regs,
3863 LO_SUM comes first. */
3865 && GET_CODE (rs1) != SUBREG
3867 || GET_CODE (rs2) == SUBREG
3868 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3870 rs1 = XEXP (addr, 1);
3871 rs2 = XEXP (addr, 0);
3875 && rs1 == pic_offset_table_rtx
3877 && GET_CODE (rs2) != SUBREG
3878 && GET_CODE (rs2) != LO_SUM
3879 && GET_CODE (rs2) != MEM
3880 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
3881 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3882 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3884 || GET_CODE (rs1) == SUBREG)
3885 && RTX_OK_FOR_OFFSET_P (rs2, mode)))
3890 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3891 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3893 /* We prohibit REG + REG for TFmode when there are no quad move insns
3894 and we consequently need to split. We do this because REG+REG
3895 is not an offsettable address. If we get the situation in reload
3896 where source and destination of a movtf pattern are both MEMs with
3897 REG+REG address, then only one of them gets converted to an
3898 offsettable address. */
3900 && ! (TARGET_ARCH64 && TARGET_HARD_QUAD))
3903 /* Likewise for TImode, but in all cases. */
3907 /* We prohibit REG + REG on ARCH32 if not optimizing for
3908 DFmode/DImode because then mem_min_alignment is likely to be zero
3909 after reload and the forced split would lack a matching splitter
3911 if (TARGET_ARCH32 && !optimize
3912 && (mode == DFmode || mode == DImode))
3915 else if (USE_AS_OFFSETABLE_LO10
3916 && GET_CODE (rs1) == LO_SUM
3918 && ! TARGET_CM_MEDMID
3919 && RTX_OK_FOR_OLO10_P (rs2, mode))
3922 imm1 = XEXP (rs1, 1);
3923 rs1 = XEXP (rs1, 0);
3924 if (!CONSTANT_P (imm1)
3925 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3929 else if (GET_CODE (addr) == LO_SUM)
3931 rs1 = XEXP (addr, 0);
3932 imm1 = XEXP (addr, 1);
3934 if (!CONSTANT_P (imm1)
3935 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3938 /* We can't allow TFmode in 32-bit mode, because an offset greater
3939 than the alignment (8) may cause the LO_SUM to overflow. */
3940 if (mode == TFmode && TARGET_ARCH32)
3943 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3948 if (GET_CODE (rs1) == SUBREG)
3949 rs1 = SUBREG_REG (rs1);
3955 if (GET_CODE (rs2) == SUBREG)
3956 rs2 = SUBREG_REG (rs2);
3963 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3964 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3969 if ((! SPARC_INT_REG_P (REGNO (rs1))
3970 && REGNO (rs1) != FRAME_POINTER_REGNUM
3971 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3973 && (! SPARC_INT_REG_P (REGNO (rs2))
3974 && REGNO (rs2) != FRAME_POINTER_REGNUM
3975 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3981 /* Return the SYMBOL_REF for the tls_get_addr function. */
3983 static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
3986 sparc_tls_get_addr (void)
3988 if (!sparc_tls_symbol)
3989 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3991 return sparc_tls_symbol;
3994 /* Return the Global Offset Table to be used in TLS mode. */
3997 sparc_tls_got (void)
3999 /* In PIC mode, this is just the PIC offset table. */
4002 crtl->uses_pic_offset_table = 1;
4003 return pic_offset_table_rtx;
4006 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4007 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4008 if (TARGET_SUN_TLS && TARGET_ARCH32)
4010 load_got_register ();
4011 return global_offset_table_rtx;
4014 /* In all other cases, we load a new pseudo with the GOT symbol. */
4015 return copy_to_reg (sparc_got ());
4018 /* Return true if X contains a thread-local symbol. */
4021 sparc_tls_referenced_p (rtx x)
4023 if (!TARGET_HAVE_TLS)
4026 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
4027 x = XEXP (XEXP (x, 0), 0);
4029 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
4032 /* That's all we handle in sparc_legitimize_tls_address for now. */
4036 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4037 this (thread-local) address. */
4040 sparc_legitimize_tls_address (rtx addr)
4042 rtx temp1, temp2, temp3, ret, o0, got;
4045 gcc_assert (can_create_pseudo_p ());
4047 if (GET_CODE (addr) == SYMBOL_REF)
4048 switch (SYMBOL_REF_TLS_MODEL (addr))
4050 case TLS_MODEL_GLOBAL_DYNAMIC:
4052 temp1 = gen_reg_rtx (SImode);
4053 temp2 = gen_reg_rtx (SImode);
4054 ret = gen_reg_rtx (Pmode);
4055 o0 = gen_rtx_REG (Pmode, 8);
4056 got = sparc_tls_got ();
4057 emit_insn (gen_tgd_hi22 (temp1, addr));
4058 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
4061 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
4062 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
4067 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
4068 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
4071 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
4072 insn = get_insns ();
4074 emit_libcall_block (insn, ret, o0, addr);
4077 case TLS_MODEL_LOCAL_DYNAMIC:
4079 temp1 = gen_reg_rtx (SImode);
4080 temp2 = gen_reg_rtx (SImode);
4081 temp3 = gen_reg_rtx (Pmode);
4082 ret = gen_reg_rtx (Pmode);
4083 o0 = gen_rtx_REG (Pmode, 8);
4084 got = sparc_tls_got ();
4085 emit_insn (gen_tldm_hi22 (temp1));
4086 emit_insn (gen_tldm_lo10 (temp2, temp1));
4089 emit_insn (gen_tldm_add32 (o0, got, temp2));
4090 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
4095 emit_insn (gen_tldm_add64 (o0, got, temp2));
4096 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
4099 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
4100 insn = get_insns ();
4102 emit_libcall_block (insn, temp3, o0,
4103 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
4104 UNSPEC_TLSLD_BASE));
4105 temp1 = gen_reg_rtx (SImode);
4106 temp2 = gen_reg_rtx (SImode);
4107 emit_insn (gen_tldo_hix22 (temp1, addr));
4108 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
4110 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
4112 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
4115 case TLS_MODEL_INITIAL_EXEC:
4116 temp1 = gen_reg_rtx (SImode);
4117 temp2 = gen_reg_rtx (SImode);
4118 temp3 = gen_reg_rtx (Pmode);
4119 got = sparc_tls_got ();
4120 emit_insn (gen_tie_hi22 (temp1, addr));
4121 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
4123 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
4125 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
4128 ret = gen_reg_rtx (Pmode);
4130 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
4133 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
4137 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
4140 case TLS_MODEL_LOCAL_EXEC:
4141 temp1 = gen_reg_rtx (Pmode);
4142 temp2 = gen_reg_rtx (Pmode);
4145 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
4146 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
4150 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
4151 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
4153 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
4160 else if (GET_CODE (addr) == CONST)
4164 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
4166 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
4167 offset = XEXP (XEXP (addr, 0), 1);
4169 base = force_operand (base, NULL_RTX);
4170 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
4171 offset = force_reg (Pmode, offset);
4172 ret = gen_rtx_PLUS (Pmode, base, offset);
4176 gcc_unreachable (); /* for now ... */
4181 /* Legitimize PIC addresses. If the address is already position-independent,
4182 we return ORIG. Newly generated position-independent addresses go into a
4183 reg. This is REG if nonzero, otherwise we allocate register(s) as
4187 sparc_legitimize_pic_address (rtx orig, rtx reg)
4189 bool gotdata_op = false;
4191 if (GET_CODE (orig) == SYMBOL_REF
4192 /* See the comment in sparc_expand_move. */
4193 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
4195 rtx pic_ref, address;
4200 gcc_assert (can_create_pseudo_p ());
4201 reg = gen_reg_rtx (Pmode);
4206 /* If not during reload, allocate another temp reg here for loading
4207 in the address, so that these instructions can be optimized
4209 rtx temp_reg = (! can_create_pseudo_p ()
4210 ? reg : gen_reg_rtx (Pmode));
4212 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4213 won't get confused into thinking that these two instructions
4214 are loading in the true address of the symbol. If in the
4215 future a PIC rtx exists, that should be used instead. */
4218 emit_insn (gen_movdi_high_pic (temp_reg, orig));
4219 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
4223 emit_insn (gen_movsi_high_pic (temp_reg, orig));
4224 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
4232 crtl->uses_pic_offset_table = 1;
4236 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
4237 pic_offset_table_rtx,
4240 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
4241 pic_offset_table_rtx,
4247 = gen_const_mem (Pmode,
4248 gen_rtx_PLUS (Pmode,
4249 pic_offset_table_rtx, address));
4250 insn = emit_move_insn (reg, pic_ref);
4253 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4255 set_unique_reg_note (insn, REG_EQUAL, orig);
4258 else if (GET_CODE (orig) == CONST)
4262 if (GET_CODE (XEXP (orig, 0)) == PLUS
4263 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
4268 gcc_assert (can_create_pseudo_p ());
4269 reg = gen_reg_rtx (Pmode);
4272 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
4273 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
4274 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
4275 base == reg ? NULL_RTX : reg);
4277 if (GET_CODE (offset) == CONST_INT)
4279 if (SMALL_INT (offset))
4280 return plus_constant (Pmode, base, INTVAL (offset));
4281 else if (can_create_pseudo_p ())
4282 offset = force_reg (Pmode, offset);
4284 /* If we reach here, then something is seriously wrong. */
4287 return gen_rtx_PLUS (Pmode, base, offset);
4289 else if (GET_CODE (orig) == LABEL_REF)
4290 /* ??? We ought to be checking that the register is live instead, in case
4291 it is eliminated. */
4292 crtl->uses_pic_offset_table = 1;
4297 /* Try machine-dependent ways of modifying an illegitimate address X
4298 to be legitimate. If we find one, return the new, valid address.
4300 OLDX is the address as it was before break_out_memory_refs was called.
4301 In some cases it is useful to look at this to decide what needs to be done.
4303 MODE is the mode of the operand pointed to by X.
4305 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4308 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
4313 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
4314 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
4315 force_operand (XEXP (x, 0), NULL_RTX));
4316 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
4317 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
4318 force_operand (XEXP (x, 1), NULL_RTX));
4319 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
4320 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
4322 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
4323 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
4324 force_operand (XEXP (x, 1), NULL_RTX));
4326 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
4329 if (sparc_tls_referenced_p (x))
4330 x = sparc_legitimize_tls_address (x);
4332 x = sparc_legitimize_pic_address (x, NULL_RTX);
4333 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
4334 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
4335 copy_to_mode_reg (Pmode, XEXP (x, 1)));
4336 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
4337 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
4338 copy_to_mode_reg (Pmode, XEXP (x, 0)));
4339 else if (GET_CODE (x) == SYMBOL_REF
4340 || GET_CODE (x) == CONST
4341 || GET_CODE (x) == LABEL_REF)
4342 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
4347 /* Delegitimize an address that was legitimized by the above function. */
4350 sparc_delegitimize_address (rtx x)
4352 x = delegitimize_mem_from_attrs (x);
4354 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
4355 switch (XINT (XEXP (x, 1), 1))
4357 case UNSPEC_MOVE_PIC:
4359 x = XVECEXP (XEXP (x, 1), 0, 0);
4360 gcc_assert (GET_CODE (x) == SYMBOL_REF);
4366 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4367 if (GET_CODE (x) == MINUS
4368 && REG_P (XEXP (x, 0))
4369 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4370 && GET_CODE (XEXP (x, 1)) == LO_SUM
4371 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
4372 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
4374 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
4375 gcc_assert (GET_CODE (x) == LABEL_REF);
4381 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4382 replace the input X, or the original X if no replacement is called for.
4383 The output parameter *WIN is 1 if the calling macro should goto WIN,
4386 For SPARC, we wish to handle addresses by splitting them into
4387 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4388 This cuts the number of extra insns by one.
4390 Do nothing when generating PIC code and the address is a symbolic
4391 operand or requires a scratch register. */
4394 sparc_legitimize_reload_address (rtx x, machine_mode mode,
4395 int opnum, int type,
4396 int ind_levels ATTRIBUTE_UNUSED, int *win)
4398 /* Decompose SImode constants into HIGH+LO_SUM. */
4400 && (mode != TFmode || TARGET_ARCH64)
4401 && GET_MODE (x) == SImode
4402 && GET_CODE (x) != LO_SUM
4403 && GET_CODE (x) != HIGH
4404 && sparc_cmodel <= CM_MEDLOW
4406 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
4408 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
4409 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4410 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4411 opnum, (enum reload_type)type);
4416 /* We have to recognize what we have already generated above. */
4417 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
4419 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4420 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4421 opnum, (enum reload_type)type);
4430 /* Return true if ADDR (a legitimate address expression)
4431 has an effect that depends on the machine mode it is used for.
4437 is not equivalent to
4439 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4441 because [%l7+a+1] is interpreted as the address of (a+1). */
4445 sparc_mode_dependent_address_p (const_rtx addr,
4446 addr_space_t as ATTRIBUTE_UNUSED)
4448 if (flag_pic && GET_CODE (addr) == PLUS)
4450 rtx op0 = XEXP (addr, 0);
4451 rtx op1 = XEXP (addr, 1);
4452 if (op0 == pic_offset_table_rtx
4453 && symbolic_operand (op1, VOIDmode))
4460 #ifdef HAVE_GAS_HIDDEN
4461 # define USE_HIDDEN_LINKONCE 1
4463 # define USE_HIDDEN_LINKONCE 0
4467 get_pc_thunk_name (char name[32], unsigned int regno)
4469 const char *reg_name = reg_names[regno];
4471 /* Skip the leading '%' as that cannot be used in a
4475 if (USE_HIDDEN_LINKONCE)
4476 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
4478 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
4481 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4484 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
4486 int orig_flag_pic = flag_pic;
4489 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4492 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
4494 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
4495 flag_pic = orig_flag_pic;
4500 /* Emit code to load the GOT register. */
4503 load_got_register (void)
4505 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4506 if (!global_offset_table_rtx)
4507 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
4509 if (TARGET_VXWORKS_RTP)
4510 emit_insn (gen_vxworks_load_got ());
4513 /* The GOT symbol is subject to a PC-relative relocation so we need a
4514 helper function to add the PC value and thus get the final value. */
4515 if (!got_helper_rtx)
4518 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
4519 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4522 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
4524 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
4527 /* Need to emit this whether or not we obey regdecls,
4528 since setjmp/longjmp can cause life info to screw up.
4529 ??? In the case where we don't obey regdecls, this is not sufficient
4530 since we may not fall out the bottom. */
4531 emit_use (global_offset_table_rtx);
4534 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4535 address of the call target. */
4538 sparc_emit_call_insn (rtx pat, rtx addr)
4542 insn = emit_call_insn (pat);
4544 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4545 if (TARGET_VXWORKS_RTP
4547 && GET_CODE (addr) == SYMBOL_REF
4548 && (SYMBOL_REF_DECL (addr)
4549 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
4550 : !SYMBOL_REF_LOCAL_P (addr)))
4552 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
4553 crtl->uses_pic_offset_table = 1;
4557 /* Return 1 if RTX is a MEM which is known to be aligned to at
4558 least a DESIRED byte boundary. */
4561 mem_min_alignment (rtx mem, int desired)
4563 rtx addr, base, offset;
4565 /* If it's not a MEM we can't accept it. */
4566 if (GET_CODE (mem) != MEM)
4570 if (!TARGET_UNALIGNED_DOUBLES
4571 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
4574 /* ??? The rest of the function predates MEM_ALIGN so
4575 there is probably a bit of redundancy. */
4576 addr = XEXP (mem, 0);
4577 base = offset = NULL_RTX;
4578 if (GET_CODE (addr) == PLUS)
4580 if (GET_CODE (XEXP (addr, 0)) == REG)
4582 base = XEXP (addr, 0);
4584 /* What we are saying here is that if the base
4585 REG is aligned properly, the compiler will make
4586 sure any REG based index upon it will be so
4588 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4589 offset = XEXP (addr, 1);
4591 offset = const0_rtx;
4594 else if (GET_CODE (addr) == REG)
4597 offset = const0_rtx;
4600 if (base != NULL_RTX)
4602 int regno = REGNO (base);
4604 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
4606 /* Check if the compiler has recorded some information
4607 about the alignment of the base REG. If reload has
4608 completed, we already matched with proper alignments.
4609 If not running global_alloc, reload might give us
4610 unaligned pointer to local stack though. */
4612 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4613 || (optimize && reload_completed))
4614 && (INTVAL (offset) & (desired - 1)) == 0)
4619 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4623 else if (! TARGET_UNALIGNED_DOUBLES
4624 || CONSTANT_P (addr)
4625 || GET_CODE (addr) == LO_SUM)
4627 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4628 is true, in which case we can only assume that an access is aligned if
4629 it is to a constant address, or the address involves a LO_SUM. */
4633 /* An obviously unaligned address. */
4638 /* Vectors to keep interesting information about registers where it can easily
4639 be got. We used to use the actual mode value as the bit number, but there
4640 are more than 32 modes now. Instead we use two tables: one indexed by
4641 hard register number, and one indexed by mode. */
4643 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4644 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4645 mapped into one sparc_mode_class mode. */
4647 enum sparc_mode_class {
4648 H_MODE, S_MODE, D_MODE, T_MODE, O_MODE,
4649 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4653 /* Modes for single-word and smaller quantities. */
4655 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4657 /* Modes for double-word and smaller quantities. */
4658 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4660 /* Modes for quad-word and smaller quantities. */
4661 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4663 /* Modes for 8-word and smaller quantities. */
4664 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4666 /* Modes for single-float quantities. */
4667 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4669 /* Modes for double-float and smaller quantities. */
4670 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4672 /* Modes for quad-float and smaller quantities. */
4673 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4675 /* Modes for quad-float pairs and smaller quantities. */
4676 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4678 /* Modes for double-float only quantities. */
4679 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4681 /* Modes for quad-float and double-float only quantities. */
4682 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4684 /* Modes for quad-float pairs and double-float only quantities. */
4685 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4687 /* Modes for condition codes. */
4688 #define CC_MODES (1 << (int) CC_MODE)
4689 #define CCFP_MODES (1 << (int) CCFP_MODE)
4691 /* Value is 1 if register/mode pair is acceptable on sparc.
4693 The funny mixture of D and T modes is because integer operations
4694 do not specially operate on tetra quantities, so non-quad-aligned
4695 registers can hold quadword quantities (except %o4 and %i4 because
4696 they cross fixed registers).
4698 ??? Note that, despite the settings, non-double-aligned parameter
4699 registers can hold double-word quantities in 32-bit mode. */
4701 /* This points to either the 32 bit or the 64 bit version. */
4702 const int *hard_regno_mode_classes;
4704 static const int hard_32bit_mode_classes[] = {
4705 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4706 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4707 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4708 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4710 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4711 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4712 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4713 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4715 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4716 and none can hold SFmode/SImode values. */
4717 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4718 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4719 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4720 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4723 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4725 /* %icc, %sfp, %gsr */
4726 CC_MODES, 0, D_MODES
4729 static const int hard_64bit_mode_classes[] = {
4730 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4731 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4732 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4733 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4735 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4736 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4737 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4738 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4740 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4741 and none can hold SFmode/SImode values. */
4742 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4743 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4744 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4745 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4748 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4750 /* %icc, %sfp, %gsr */
4751 CC_MODES, 0, D_MODES
4754 int sparc_mode_class [NUM_MACHINE_MODES];
4756 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4759 sparc_init_modes (void)
4763 for (i = 0; i < NUM_MACHINE_MODES; i++)
4765 machine_mode m = (machine_mode) i;
4766 unsigned int size = GET_MODE_SIZE (m);
4768 switch (GET_MODE_CLASS (m))
4771 case MODE_PARTIAL_INT:
4772 case MODE_COMPLEX_INT:
4774 sparc_mode_class[i] = 1 << (int) H_MODE;
4776 sparc_mode_class[i] = 1 << (int) S_MODE;
4778 sparc_mode_class[i] = 1 << (int) D_MODE;
4779 else if (size == 16)
4780 sparc_mode_class[i] = 1 << (int) T_MODE;
4781 else if (size == 32)
4782 sparc_mode_class[i] = 1 << (int) O_MODE;
4784 sparc_mode_class[i] = 0;
4786 case MODE_VECTOR_INT:
4788 sparc_mode_class[i] = 1 << (int) SF_MODE;
4790 sparc_mode_class[i] = 1 << (int) DF_MODE;
4792 sparc_mode_class[i] = 0;
4795 case MODE_COMPLEX_FLOAT:
4797 sparc_mode_class[i] = 1 << (int) SF_MODE;
4799 sparc_mode_class[i] = 1 << (int) DF_MODE;
4800 else if (size == 16)
4801 sparc_mode_class[i] = 1 << (int) TF_MODE;
4802 else if (size == 32)
4803 sparc_mode_class[i] = 1 << (int) OF_MODE;
4805 sparc_mode_class[i] = 0;
4808 if (m == CCFPmode || m == CCFPEmode)
4809 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4811 sparc_mode_class[i] = 1 << (int) CC_MODE;
4814 sparc_mode_class[i] = 0;
4820 hard_regno_mode_classes = hard_64bit_mode_classes;
4822 hard_regno_mode_classes = hard_32bit_mode_classes;
4824 /* Initialize the array used by REGNO_REG_CLASS. */
4825 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4827 if (i < 16 && TARGET_V8PLUS)
4828 sparc_regno_reg_class[i] = I64_REGS;
4829 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4830 sparc_regno_reg_class[i] = GENERAL_REGS;
4832 sparc_regno_reg_class[i] = FP_REGS;
4834 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4836 sparc_regno_reg_class[i] = FPCC_REGS;
4838 sparc_regno_reg_class[i] = NO_REGS;
4842 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4845 save_global_or_fp_reg_p (unsigned int regno,
4846 int leaf_function ATTRIBUTE_UNUSED)
4848 return !call_used_regs[regno] && df_regs_ever_live_p (regno);
4851 /* Return whether the return address register (%i7) is needed. */
4854 return_addr_reg_needed_p (int leaf_function)
4856 /* If it is live, for example because of __builtin_return_address (0). */
4857 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM))
4860 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4862 /* Loading the GOT register clobbers %o7. */
4863 || crtl->uses_pic_offset_table
4864 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM))
4870 /* Return whether REGNO, a local or in register, must be saved/restored. */
4873 save_local_or_in_reg_p (unsigned int regno, int leaf_function)
4875 /* General case: call-saved registers live at some point. */
4876 if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
4879 /* Frame pointer register (%fp) if needed. */
4880 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
4883 /* Return address register (%i7) if needed. */
4884 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function))
4887 /* GOT register (%l7) if needed. */
4888 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
4891 /* If the function accesses prior frames, the frame pointer and the return
4892 address of the previous frame must be saved on the stack. */
4893 if (crtl->accesses_prior_frames
4894 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM))
4900 /* Compute the frame size required by the function. This function is called
4901 during the reload pass and also by sparc_expand_prologue. */
4904 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4906 HOST_WIDE_INT frame_size, apparent_frame_size;
4907 int args_size, n_global_fp_regs = 0;
4908 bool save_local_in_regs_p = false;
4911 /* If the function allocates dynamic stack space, the dynamic offset is
4912 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4913 if (leaf_function && !cfun->calls_alloca)
4916 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl);
4918 /* Calculate space needed for global registers. */
4921 for (i = 0; i < 8; i++)
4922 if (save_global_or_fp_reg_p (i, 0))
4923 n_global_fp_regs += 2;
4927 for (i = 0; i < 8; i += 2)
4928 if (save_global_or_fp_reg_p (i, 0)
4929 || save_global_or_fp_reg_p (i + 1, 0))
4930 n_global_fp_regs += 2;
4933 /* In the flat window model, find out which local and in registers need to
4934 be saved. We don't reserve space in the current frame for them as they
4935 will be spilled into the register window save area of the caller's frame.
4936 However, as soon as we use this register window save area, we must create
4937 that of the current frame to make it the live one. */
4939 for (i = 16; i < 32; i++)
4940 if (save_local_or_in_reg_p (i, leaf_function))
4942 save_local_in_regs_p = true;
4946 /* Calculate space needed for FP registers. */
4947 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4948 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4949 n_global_fp_regs += 2;
4952 && n_global_fp_regs == 0
4954 && !save_local_in_regs_p)
4955 frame_size = apparent_frame_size = 0;
4958 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4959 apparent_frame_size = ROUND_UP (size - STARTING_FRAME_OFFSET, 8);
4960 apparent_frame_size += n_global_fp_regs * 4;
4962 /* We need to add the size of the outgoing argument area. */
4963 frame_size = apparent_frame_size + ROUND_UP (args_size, 8);
4965 /* And that of the register window save area. */
4966 frame_size += FIRST_PARM_OFFSET (cfun->decl);
4968 /* Finally, bump to the appropriate alignment. */
4969 frame_size = SPARC_STACK_ALIGN (frame_size);
4972 /* Set up values for use in prologue and epilogue. */
4973 sparc_frame_size = frame_size;
4974 sparc_apparent_frame_size = apparent_frame_size;
4975 sparc_n_global_fp_regs = n_global_fp_regs;
4976 sparc_save_local_in_regs_p = save_local_in_regs_p;
4981 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
4984 sparc_initial_elimination_offset (int to)
4988 if (to == STACK_POINTER_REGNUM)
4989 offset = sparc_compute_frame_size (get_frame_size (), crtl->is_leaf);
4993 offset += SPARC_STACK_BIAS;
4997 /* Output any necessary .register pseudo-ops. */
5000 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
5002 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5008 /* Check if %g[2367] were used without
5009 .register being printed for them already. */
5010 for (i = 2; i < 8; i++)
5012 if (df_regs_ever_live_p (i)
5013 && ! sparc_hard_reg_printed [i])
5015 sparc_hard_reg_printed [i] = 1;
5016 /* %g7 is used as TLS base register, use #ignore
5017 for it instead of #scratch. */
5018 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
5019 i == 7 ? "ignore" : "scratch");
5026 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5028 #if PROBE_INTERVAL > 4096
5029 #error Cannot use indexed addressing mode for stack probing
5032 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5033 inclusive. These are offsets from the current stack pointer.
5035 Note that we don't use the REG+REG addressing mode for the probes because
5036 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5037 so the advantages of having a single code win here. */
5040 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
5042 rtx g1 = gen_rtx_REG (Pmode, 1);
5044 /* See if we have a constant small number of probes to generate. If so,
5045 that's the easy case. */
5046 if (size <= PROBE_INTERVAL)
5048 emit_move_insn (g1, GEN_INT (first));
5049 emit_insn (gen_rtx_SET (g1,
5050 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
5051 emit_stack_probe (plus_constant (Pmode, g1, -size));
5054 /* The run-time loop is made up of 9 insns in the generic case while the
5055 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5056 else if (size <= 4 * PROBE_INTERVAL)
5060 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
5061 emit_insn (gen_rtx_SET (g1,
5062 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
5063 emit_stack_probe (g1);
5065 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5066 it exceeds SIZE. If only two probes are needed, this will not
5067 generate any code. Then probe at FIRST + SIZE. */
5068 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
5070 emit_insn (gen_rtx_SET (g1,
5071 plus_constant (Pmode, g1, -PROBE_INTERVAL)));
5072 emit_stack_probe (g1);
5075 emit_stack_probe (plus_constant (Pmode, g1,
5076 (i - PROBE_INTERVAL) - size));
5079 /* Otherwise, do the same as above, but in a loop. Note that we must be
5080 extra careful with variables wrapping around because we might be at
5081 the very top (or the very bottom) of the address space and we have
5082 to be able to handle this case properly; in particular, we use an
5083 equality test for the loop condition. */
5086 HOST_WIDE_INT rounded_size;
5087 rtx g4 = gen_rtx_REG (Pmode, 4);
5089 emit_move_insn (g1, GEN_INT (first));
5092 /* Step 1: round SIZE to the previous multiple of the interval. */
5094 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
5095 emit_move_insn (g4, GEN_INT (rounded_size));
5098 /* Step 2: compute initial and final value of the loop counter. */
5100 /* TEST_ADDR = SP + FIRST. */
5101 emit_insn (gen_rtx_SET (g1,
5102 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
5104 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5105 emit_insn (gen_rtx_SET (g4, gen_rtx_MINUS (Pmode, g1, g4)));
5110 while (TEST_ADDR != LAST_ADDR)
5112 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5116 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5117 until it is equal to ROUNDED_SIZE. */
5120 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
5122 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
5125 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5126 that SIZE is equal to ROUNDED_SIZE. */
5128 if (size != rounded_size)
5129 emit_stack_probe (plus_constant (Pmode, g4, rounded_size - size));
5132 /* Make sure nothing is scheduled before we are done. */
5133 emit_insn (gen_blockage ());
5136 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5137 absolute addresses. */
5140 output_probe_stack_range (rtx reg1, rtx reg2)
5142 static int labelno = 0;
5146 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
5149 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
5151 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5153 xops[1] = GEN_INT (-PROBE_INTERVAL);
5154 output_asm_insn ("add\t%0, %1, %0", xops);
5156 /* Test if TEST_ADDR == LAST_ADDR. */
5158 output_asm_insn ("cmp\t%0, %1", xops);
5160 /* Probe at TEST_ADDR and branch. */
5162 fputs ("\tbne,pt\t%xcc,", asm_out_file);
5164 fputs ("\tbne\t", asm_out_file);
5165 assemble_name_raw (asm_out_file, loop_lab);
5166 fputc ('\n', asm_out_file);
5167 xops[1] = GEN_INT (SPARC_STACK_BIAS);
5168 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
5173 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5174 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5175 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5176 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5177 the action to be performed if it returns false. Return the new offset. */
5179 typedef bool (*sorr_pred_t) (unsigned int, int);
5180 typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t;
5183 emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base,
5184 int offset, int leaf_function, sorr_pred_t save_p,
5185 sorr_act_t action_true, sorr_act_t action_false)
5191 if (TARGET_ARCH64 && high <= 32)
5195 for (i = low; i < high; i++)
5197 if (save_p (i, leaf_function))
5199 mem = gen_frame_mem (DImode, plus_constant (Pmode,
5201 if (action_true == SORR_SAVE)
5203 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
5204 RTX_FRAME_RELATED_P (insn) = 1;
5206 else /* action_true == SORR_RESTORE */
5208 /* The frame pointer must be restored last since its old
5209 value may be used as base address for the frame. This
5210 is problematic in 64-bit mode only because of the lack
5211 of double-word load instruction. */
5212 if (i == HARD_FRAME_POINTER_REGNUM)
5215 emit_move_insn (gen_rtx_REG (DImode, i), mem);
5219 else if (action_false == SORR_ADVANCE)
5225 mem = gen_frame_mem (DImode, plus_constant (Pmode, base, fp_offset));
5226 emit_move_insn (hard_frame_pointer_rtx, mem);
5231 for (i = low; i < high; i += 2)
5233 bool reg0 = save_p (i, leaf_function);
5234 bool reg1 = save_p (i + 1, leaf_function);
5240 mode = SPARC_INT_REG_P (i) ? DImode : DFmode;
5245 mode = SPARC_INT_REG_P (i) ? SImode : SFmode;
5250 mode = SPARC_INT_REG_P (i) ? SImode : SFmode;
5256 if (action_false == SORR_ADVANCE)
5261 mem = gen_frame_mem (mode, plus_constant (Pmode, base, offset));
5262 if (action_true == SORR_SAVE)
5264 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
5265 RTX_FRAME_RELATED_P (insn) = 1;
5269 mem = gen_frame_mem (SImode, plus_constant (Pmode, base,
5271 set1 = gen_rtx_SET (mem, gen_rtx_REG (SImode, regno));
5272 RTX_FRAME_RELATED_P (set1) = 1;
5274 = gen_frame_mem (SImode, plus_constant (Pmode, base,
5276 set2 = gen_rtx_SET (mem, gen_rtx_REG (SImode, regno + 1));
5277 RTX_FRAME_RELATED_P (set2) = 1;
5278 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5279 gen_rtx_PARALLEL (VOIDmode,
5280 gen_rtvec (2, set1, set2)));
5283 else /* action_true == SORR_RESTORE */
5284 emit_move_insn (gen_rtx_REG (mode, regno), mem);
5286 /* Bump and round down to double word
5287 in case we already bumped by 4. */
5288 offset = ROUND_DOWN (offset + 8, 8);
5295 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5298 emit_adjust_base_to_offset (rtx base, int offset)
5300 /* ??? This might be optimized a little as %g1 might already have a
5301 value close enough that a single add insn will do. */
5302 /* ??? Although, all of this is probably only a temporary fix because
5303 if %g1 can hold a function result, then sparc_expand_epilogue will
5304 lose (the result will be clobbered). */
5305 rtx new_base = gen_rtx_REG (Pmode, 1);
5306 emit_move_insn (new_base, GEN_INT (offset));
5307 emit_insn (gen_rtx_SET (new_base, gen_rtx_PLUS (Pmode, base, new_base)));
5311 /* Emit code to save/restore call-saved global and FP registers. */
5314 emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action)
5316 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095)
5318 base = emit_adjust_base_to_offset (base, offset);
5323 = emit_save_or_restore_regs (0, 8, base, offset, 0,
5324 save_global_or_fp_reg_p, action, SORR_NONE);
5325 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0,
5326 save_global_or_fp_reg_p, action, SORR_NONE);
5329 /* Emit code to save/restore call-saved local and in registers. */
5332 emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action)
5334 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095)
5336 base = emit_adjust_base_to_offset (base, offset);
5340 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p,
5341 save_local_or_in_reg_p, action, SORR_ADVANCE);
5344 /* Emit a window_save insn. */
5347 emit_window_save (rtx increment)
5349 rtx_insn *insn = emit_insn (gen_window_save (increment));
5350 RTX_FRAME_RELATED_P (insn) = 1;
5352 /* The incoming return address (%o7) is saved in %i7. */
5353 add_reg_note (insn, REG_CFA_REGISTER,
5354 gen_rtx_SET (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM),
5356 INCOMING_RETURN_ADDR_REGNUM)));
5358 /* The window save event. */
5359 add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx);
5361 /* The CFA is %fp, the hard frame pointer. */
5362 add_reg_note (insn, REG_CFA_DEF_CFA,
5363 plus_constant (Pmode, hard_frame_pointer_rtx,
5364 INCOMING_FRAME_SP_OFFSET));
5369 /* Generate an increment for the stack pointer. */
5372 gen_stack_pointer_inc (rtx increment)
5374 return gen_rtx_SET (stack_pointer_rtx,
5375 gen_rtx_PLUS (Pmode,
5380 /* Expand the function prologue. The prologue is responsible for reserving
5381 storage for the frame, saving the call-saved registers and loading the
5382 GOT register if needed. */
5385 sparc_expand_prologue (void)
5390 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5391 on the final value of the flag means deferring the prologue/epilogue
5392 expansion until just before the second scheduling pass, which is too
5393 late to emit multiple epilogues or return insns.
5395 Of course we are making the assumption that the value of the flag
5396 will not change between now and its final value. Of the three parts
5397 of the formula, only the last one can reasonably vary. Let's take a
5398 closer look, after assuming that the first two ones are set to true
5399 (otherwise the last value is effectively silenced).
5401 If only_leaf_regs_used returns false, the global predicate will also
5402 be false so the actual frame size calculated below will be positive.
5403 As a consequence, the save_register_window insn will be emitted in
5404 the instruction stream; now this insn explicitly references %fp
5405 which is not a leaf register so only_leaf_regs_used will always
5406 return false subsequently.
5408 If only_leaf_regs_used returns true, we hope that the subsequent
5409 optimization passes won't cause non-leaf registers to pop up. For
5410 example, the regrename pass has special provisions to not rename to
5411 non-leaf registers in a leaf function. */
5412 sparc_leaf_function_p
5413 = optimize > 0 && crtl->is_leaf && only_leaf_regs_used ();
5415 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
5417 if (flag_stack_usage_info)
5418 current_function_static_stack_size = size;
5420 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
5422 if (crtl->is_leaf && !cfun->calls_alloca)
5424 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
5425 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT,
5426 size - STACK_CHECK_PROTECT);
5429 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
5434 else if (sparc_leaf_function_p)
5436 rtx size_int_rtx = GEN_INT (-size);
5439 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
5440 else if (size <= 8192)
5442 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5443 RTX_FRAME_RELATED_P (insn) = 1;
5445 /* %sp is still the CFA register. */
5446 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5450 rtx size_rtx = gen_rtx_REG (Pmode, 1);
5451 emit_move_insn (size_rtx, size_int_rtx);
5452 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
5453 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5454 gen_stack_pointer_inc (size_int_rtx));
5457 RTX_FRAME_RELATED_P (insn) = 1;
5461 rtx size_int_rtx = GEN_INT (-size);
5464 emit_window_save (size_int_rtx);
5465 else if (size <= 8192)
5467 emit_window_save (GEN_INT (-4096));
5469 /* %sp is not the CFA register anymore. */
5470 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5472 /* Make sure no %fp-based store is issued until after the frame is
5473 established. The offset between the frame pointer and the stack
5474 pointer is calculated relative to the value of the stack pointer
5475 at the end of the function prologue, and moving instructions that
5476 access the stack via the frame pointer between the instructions
5477 that decrement the stack pointer could result in accessing the
5478 register window save area, which is volatile. */
5479 emit_insn (gen_frame_blockage ());
5483 rtx size_rtx = gen_rtx_REG (Pmode, 1);
5484 emit_move_insn (size_rtx, size_int_rtx);
5485 emit_window_save (size_rtx);
5489 if (sparc_leaf_function_p)
5491 sparc_frame_base_reg = stack_pointer_rtx;
5492 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5496 sparc_frame_base_reg = hard_frame_pointer_rtx;
5497 sparc_frame_base_offset = SPARC_STACK_BIAS;
5500 if (sparc_n_global_fp_regs > 0)
5501 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5502 sparc_frame_base_offset
5503 - sparc_apparent_frame_size,
5506 /* Load the GOT register if needed. */
5507 if (crtl->uses_pic_offset_table)
5508 load_got_register ();
5510 /* Advertise that the data calculated just above are now valid. */
5511 sparc_prologue_data_valid_p = true;
5514 /* Expand the function prologue. The prologue is responsible for reserving
5515 storage for the frame, saving the call-saved registers and loading the
5516 GOT register if needed. */
5519 sparc_flat_expand_prologue (void)
5524 sparc_leaf_function_p = optimize > 0 && crtl->is_leaf;
5526 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
5528 if (flag_stack_usage_info)
5529 current_function_static_stack_size = size;
5531 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
5533 if (crtl->is_leaf && !cfun->calls_alloca)
5535 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
5536 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT,
5537 size - STACK_CHECK_PROTECT);
5540 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
5543 if (sparc_save_local_in_regs_p)
5544 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS,
5551 rtx size_int_rtx, size_rtx;
5553 size_rtx = size_int_rtx = GEN_INT (-size);
5555 /* We establish the frame (i.e. decrement the stack pointer) first, even
5556 if we use a frame pointer, because we cannot clobber any call-saved
5557 registers, including the frame pointer, if we haven't created a new
5558 register save area, for the sake of compatibility with the ABI. */
5560 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
5561 else if (size <= 8192 && !frame_pointer_needed)
5563 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5564 RTX_FRAME_RELATED_P (insn) = 1;
5565 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5569 size_rtx = gen_rtx_REG (Pmode, 1);
5570 emit_move_insn (size_rtx, size_int_rtx);
5571 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
5572 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5573 gen_stack_pointer_inc (size_int_rtx));
5575 RTX_FRAME_RELATED_P (insn) = 1;
5577 /* Ensure nothing is scheduled until after the frame is established. */
5578 emit_insn (gen_blockage ());
5580 if (frame_pointer_needed)
5582 insn = emit_insn (gen_rtx_SET (hard_frame_pointer_rtx,
5583 gen_rtx_MINUS (Pmode,
5586 RTX_FRAME_RELATED_P (insn) = 1;
5588 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5589 gen_rtx_SET (hard_frame_pointer_rtx,
5590 plus_constant (Pmode, stack_pointer_rtx,
5594 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5596 rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM);
5597 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
5599 insn = emit_move_insn (i7, o7);
5600 RTX_FRAME_RELATED_P (insn) = 1;
5602 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (i7, o7));
5604 /* Prevent this instruction from ever being considered dead,
5605 even if this function has no epilogue. */
5610 if (frame_pointer_needed)
5612 sparc_frame_base_reg = hard_frame_pointer_rtx;
5613 sparc_frame_base_offset = SPARC_STACK_BIAS;
5617 sparc_frame_base_reg = stack_pointer_rtx;
5618 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5621 if (sparc_n_global_fp_regs > 0)
5622 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5623 sparc_frame_base_offset
5624 - sparc_apparent_frame_size,
5627 /* Load the GOT register if needed. */
5628 if (crtl->uses_pic_offset_table)
5629 load_got_register ();
5631 /* Advertise that the data calculated just above are now valid. */
5632 sparc_prologue_data_valid_p = true;
5635 /* This function generates the assembly code for function entry, which boils
5636 down to emitting the necessary .register directives. */
5639 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5641 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5643 gcc_assert (sparc_leaf_function_p == crtl->uses_only_leaf_regs);
5645 sparc_output_scratch_registers (file);
5648 /* Expand the function epilogue, either normal or part of a sibcall.
5649 We emit all the instructions except the return or the call. */
5652 sparc_expand_epilogue (bool for_eh)
5654 HOST_WIDE_INT size = sparc_frame_size;
5656 if (sparc_n_global_fp_regs > 0)
5657 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5658 sparc_frame_base_offset
5659 - sparc_apparent_frame_size,
5662 if (size == 0 || for_eh)
5664 else if (sparc_leaf_function_p)
5667 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
5668 else if (size <= 8192)
5670 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5671 emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096)));
5675 rtx reg = gen_rtx_REG (Pmode, 1);
5676 emit_move_insn (reg, GEN_INT (size));
5677 emit_insn (gen_stack_pointer_inc (reg));
5682 /* Expand the function epilogue, either normal or part of a sibcall.
5683 We emit all the instructions except the return or the call. */
5686 sparc_flat_expand_epilogue (bool for_eh)
5688 HOST_WIDE_INT size = sparc_frame_size;
5690 if (sparc_n_global_fp_regs > 0)
5691 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5692 sparc_frame_base_offset
5693 - sparc_apparent_frame_size,
5696 /* If we have a frame pointer, we'll need both to restore it before the
5697 frame is destroyed and use its current value in destroying the frame.
5698 Since we don't have an atomic way to do that in the flat window model,
5699 we save the current value into a temporary register (%g1). */
5700 if (frame_pointer_needed && !for_eh)
5701 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx);
5703 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5704 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM),
5705 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM));
5707 if (sparc_save_local_in_regs_p)
5708 emit_save_or_restore_local_in_regs (sparc_frame_base_reg,
5709 sparc_frame_base_offset,
5712 if (size == 0 || for_eh)
5714 else if (frame_pointer_needed)
5716 /* Make sure the frame is destroyed after everything else is done. */
5717 emit_insn (gen_blockage ());
5719 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1));
5724 emit_insn (gen_blockage ());
5727 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
5728 else if (size <= 8192)
5730 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5731 emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096)));
5735 rtx reg = gen_rtx_REG (Pmode, 1);
5736 emit_move_insn (reg, GEN_INT (size));
5737 emit_insn (gen_stack_pointer_inc (reg));
5742 /* Return true if it is appropriate to emit `return' instructions in the
5743 body of a function. */
5746 sparc_can_use_return_insn_p (void)
5748 return sparc_prologue_data_valid_p
5749 && sparc_n_global_fp_regs == 0
5751 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p)
5752 : (sparc_frame_size == 0 || !sparc_leaf_function_p);
5755 /* This function generates the assembly code for function exit. */
5758 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5760 /* If the last two instructions of a function are "call foo; dslot;"
5761 the return address might point to the first instruction in the next
5762 function and we have to output a dummy nop for the sake of sane
5763 backtraces in such cases. This is pointless for sibling calls since
5764 the return address is explicitly adjusted. */
5766 rtx insn, last_real_insn;
5768 insn = get_last_insn ();
5770 last_real_insn = prev_real_insn (insn);
5772 && NONJUMP_INSN_P (last_real_insn)
5773 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
5774 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
5777 && CALL_P (last_real_insn)
5778 && !SIBLING_CALL_P (last_real_insn))
5779 fputs("\tnop\n", file);
5781 sparc_output_deferred_case_vectors ();
5784 /* Output a 'restore' instruction. */
5787 output_restore (rtx pat)
5793 fputs ("\t restore\n", asm_out_file);
5797 gcc_assert (GET_CODE (pat) == SET);
5799 operands[0] = SET_DEST (pat);
5800 pat = SET_SRC (pat);
5802 switch (GET_CODE (pat))
5805 operands[1] = XEXP (pat, 0);
5806 operands[2] = XEXP (pat, 1);
5807 output_asm_insn (" restore %r1, %2, %Y0", operands);
5810 operands[1] = XEXP (pat, 0);
5811 operands[2] = XEXP (pat, 1);
5812 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
5815 operands[1] = XEXP (pat, 0);
5816 gcc_assert (XEXP (pat, 1) == const1_rtx);
5817 output_asm_insn (" restore %r1, %r1, %Y0", operands);
5821 output_asm_insn (" restore %%g0, %1, %Y0", operands);
5826 /* Output a return. */
5829 output_return (rtx_insn *insn)
5831 if (crtl->calls_eh_return)
5833 /* If the function uses __builtin_eh_return, the eh_return
5834 machinery occupies the delay slot. */
5835 gcc_assert (!final_sequence);
5837 if (flag_delayed_branch)
5839 if (!TARGET_FLAT && TARGET_V9)
5840 fputs ("\treturn\t%i7+8\n", asm_out_file);
5844 fputs ("\trestore\n", asm_out_file);
5846 fputs ("\tjmp\t%o7+8\n", asm_out_file);
5849 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
5854 fputs ("\trestore\n", asm_out_file);
5856 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file);
5857 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
5860 else if (sparc_leaf_function_p || TARGET_FLAT)
5862 /* This is a leaf or flat function so we don't have to bother restoring
5863 the register window, which frees us from dealing with the convoluted
5864 semantics of restore/return. We simply output the jump to the
5865 return address and the insn in the delay slot (if any). */
5867 return "jmp\t%%o7+%)%#";
5871 /* This is a regular function so we have to restore the register window.
5872 We may have a pending insn for the delay slot, which will be either
5873 combined with the 'restore' instruction or put in the delay slot of
5874 the 'return' instruction. */
5880 delay = NEXT_INSN (insn);
5883 pat = PATTERN (delay);
5885 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
5887 epilogue_renumber (&pat, 0);
5888 return "return\t%%i7+%)%#";
5892 output_asm_insn ("jmp\t%%i7+%)", NULL);
5893 output_restore (pat);
5894 PATTERN (delay) = gen_blockage ();
5895 INSN_CODE (delay) = -1;
5900 /* The delay slot is empty. */
5902 return "return\t%%i7+%)\n\t nop";
5903 else if (flag_delayed_branch)
5904 return "jmp\t%%i7+%)\n\t restore";
5906 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5913 /* Output a sibling call. */
5916 output_sibcall (rtx_insn *insn, rtx call_operand)
5920 gcc_assert (flag_delayed_branch);
5922 operands[0] = call_operand;
5924 if (sparc_leaf_function_p || TARGET_FLAT)
5926 /* This is a leaf or flat function so we don't have to bother restoring
5927 the register window. We simply output the jump to the function and
5928 the insn in the delay slot (if any). */
5930 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
5933 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5936 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5937 it into branch if possible. */
5938 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5943 /* This is a regular function so we have to restore the register window.
5944 We may have a pending insn for the delay slot, which will be combined
5945 with the 'restore' instruction. */
5947 output_asm_insn ("call\t%a0, 0", operands);
5951 rtx_insn *delay = NEXT_INSN (insn);
5954 output_restore (PATTERN (delay));
5956 PATTERN (delay) = gen_blockage ();
5957 INSN_CODE (delay) = -1;
5960 output_restore (NULL_RTX);
5966 /* Functions for handling argument passing.
5968 For 32-bit, the first 6 args are normally in registers and the rest are
5969 pushed. Any arg that starts within the first 6 words is at least
5970 partially passed in a register unless its data type forbids.
5972 For 64-bit, the argument registers are laid out as an array of 16 elements
5973 and arguments are added sequentially. The first 6 int args and up to the
5974 first 16 fp args (depending on size) are passed in regs.
5976 Slot Stack Integral Float Float in structure Double Long Double
5977 ---- ----- -------- ----- ------------------ ------ -----------
5978 15 [SP+248] %f31 %f30,%f31 %d30
5979 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5980 13 [SP+232] %f27 %f26,%f27 %d26
5981 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5982 11 [SP+216] %f23 %f22,%f23 %d22
5983 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5984 9 [SP+200] %f19 %f18,%f19 %d18
5985 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5986 7 [SP+184] %f15 %f14,%f15 %d14
5987 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5988 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5989 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5990 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5991 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5992 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5993 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5995 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5997 Integral arguments are always passed as 64-bit quantities appropriately
6000 Passing of floating point values is handled as follows.
6001 If a prototype is in scope:
6002 If the value is in a named argument (i.e. not a stdarg function or a
6003 value not part of the `...') then the value is passed in the appropriate
6005 If the value is part of the `...' and is passed in one of the first 6
6006 slots then the value is passed in the appropriate int reg.
6007 If the value is part of the `...' and is not passed in one of the first 6
6008 slots then the value is passed in memory.
6009 If a prototype is not in scope:
6010 If the value is one of the first 6 arguments the value is passed in the
6011 appropriate integer reg and the appropriate fp reg.
6012 If the value is not one of the first 6 arguments the value is passed in
6013 the appropriate fp reg and in memory.
6016 Summary of the calling conventions implemented by GCC on the SPARC:
6019 size argument return value
6021 small integer <4 int. reg. int. reg.
6022 word 4 int. reg. int. reg.
6023 double word 8 int. reg. int. reg.
6025 _Complex small integer <8 int. reg. int. reg.
6026 _Complex word 8 int. reg. int. reg.
6027 _Complex double word 16 memory int. reg.
6029 vector integer <=8 int. reg. FP reg.
6030 vector integer >8 memory memory
6032 float 4 int. reg. FP reg.
6033 double 8 int. reg. FP reg.
6034 long double 16 memory memory
6036 _Complex float 8 memory FP reg.
6037 _Complex double 16 memory FP reg.
6038 _Complex long double 32 memory FP reg.
6040 vector float any memory memory
6042 aggregate any memory memory
6047 size argument return value
6049 small integer <8 int. reg. int. reg.
6050 word 8 int. reg. int. reg.
6051 double word 16 int. reg. int. reg.
6053 _Complex small integer <16 int. reg. int. reg.
6054 _Complex word 16 int. reg. int. reg.
6055 _Complex double word 32 memory int. reg.
6057 vector integer <=16 FP reg. FP reg.
6058 vector integer 16<s<=32 memory FP reg.
6059 vector integer >32 memory memory
6061 float 4 FP reg. FP reg.
6062 double 8 FP reg. FP reg.
6063 long double 16 FP reg. FP reg.
6065 _Complex float 8 FP reg. FP reg.
6066 _Complex double 16 FP reg. FP reg.
6067 _Complex long double 32 memory FP reg.
6069 vector float <=16 FP reg. FP reg.
6070 vector float 16<s<=32 memory FP reg.
6071 vector float >32 memory memory
6073 aggregate <=16 reg. reg.
6074 aggregate 16<s<=32 memory reg.
6075 aggregate >32 memory memory
6079 Note #1: complex floating-point types follow the extended SPARC ABIs as
6080 implemented by the Sun compiler.
6082 Note #2: integral vector types follow the scalar floating-point types
6083 conventions to match what is implemented by the Sun VIS SDK.
6085 Note #3: floating-point vector types follow the aggregate types
6089 /* Maximum number of int regs for args. */
6090 #define SPARC_INT_ARG_MAX 6
6091 /* Maximum number of fp regs for args. */
6092 #define SPARC_FP_ARG_MAX 16
6093 /* Number of words (partially) occupied for a given size in units. */
6094 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6096 /* Handle the INIT_CUMULATIVE_ARGS macro.
6097 Initialize a variable CUM of type CUMULATIVE_ARGS
6098 for a call to a function whose data type is FNTYPE.
6099 For a library call, FNTYPE is 0. */
6102 init_cumulative_args (struct sparc_args *cum, tree fntype, rtx, tree)
6105 cum->prototype_p = fntype && prototype_p (fntype);
6106 cum->libcall_p = !fntype;
6109 /* Handle promotion of pointer and integer arguments. */
6112 sparc_promote_function_mode (const_tree type, machine_mode mode,
6113 int *punsignedp, const_tree, int)
6115 if (type && POINTER_TYPE_P (type))
6117 *punsignedp = POINTERS_EXTEND_UNSIGNED;
6121 /* Integral arguments are passed as full words, as per the ABI. */
6122 if (GET_MODE_CLASS (mode) == MODE_INT
6123 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6129 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6132 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
6134 return TARGET_ARCH64 ? true : false;
6137 /* Traverse the record TYPE recursively and call FUNC on its fields.
6138 NAMED is true if this is for a named parameter. DATA is passed
6139 to FUNC for each field. OFFSET is the starting position and
6140 PACKED is true if we are inside a packed record. */
6142 template <typename T, void Func (const_tree, HOST_WIDE_INT, bool, T*)>
6144 traverse_record_type (const_tree type, bool named, T *data,
6145 HOST_WIDE_INT offset = 0, bool packed = false)
6147 /* The ABI obviously doesn't specify how packed structures are passed.
6148 These are passed in integer regs if possible, otherwise memory. */
6150 for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6151 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
6157 /* Walk the real fields, but skip those with no size or a zero size.
6158 ??? Fields with variable offset are handled as having zero offset. */
6159 for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6160 if (TREE_CODE (field) == FIELD_DECL)
6162 if (!DECL_SIZE (field) || integer_zerop (DECL_SIZE (field)))
6165 HOST_WIDE_INT bitpos = offset;
6166 if (TREE_CODE (DECL_FIELD_OFFSET (field)) == INTEGER_CST)
6167 bitpos += int_bit_position (field);
6169 tree field_type = TREE_TYPE (field);
6170 if (TREE_CODE (field_type) == RECORD_TYPE)
6171 traverse_record_type<T, Func> (field_type, named, data, bitpos,
6176 = FLOAT_TYPE_P (field_type) || VECTOR_TYPE_P (field_type);
6177 Func (field, bitpos, fp_type && named && !packed && TARGET_FPU,
6183 /* Handle recursive register classifying for structure layout. */
6187 bool int_regs; /* true if field eligible to int registers. */
6188 bool fp_regs; /* true if field eligible to FP registers. */
6189 bool fp_regs_in_first_word; /* true if such field in first word. */
6192 /* A subroutine of function_arg_slotno. Classify the field. */
6195 classify_registers (const_tree, HOST_WIDE_INT bitpos, bool fp,
6196 classify_data_t *data)
6200 data->fp_regs = true;
6201 if (bitpos < BITS_PER_WORD)
6202 data->fp_regs_in_first_word = true;
6205 data->int_regs = true;
6208 /* Compute the slot number to pass an argument in.
6209 Return the slot number or -1 if passing on the stack.
6211 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6212 the preceding args and about the function being called.
6213 MODE is the argument's machine mode.
6214 TYPE is the data type of the argument (as a tree).
6215 This is null for libcalls where that information may
6217 NAMED is nonzero if this argument is a named parameter
6218 (otherwise it is an extra parameter matching an ellipsis).
6219 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6220 *PREGNO records the register number to use if scalar type.
6221 *PPADDING records the amount of padding needed in words. */
6224 function_arg_slotno (const struct sparc_args *cum, machine_mode mode,
6225 const_tree type, bool named, bool incoming,
6226 int *pregno, int *ppadding)
6228 int regbase = (incoming
6229 ? SPARC_INCOMING_INT_ARG_FIRST
6230 : SPARC_OUTGOING_INT_ARG_FIRST);
6231 int slotno = cum->words;
6232 enum mode_class mclass;
6237 if (type && TREE_ADDRESSABLE (type))
6243 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
6246 /* For SPARC64, objects requiring 16-byte alignment get it. */
6248 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
6249 && (slotno & 1) != 0)
6250 slotno++, *ppadding = 1;
6252 mclass = GET_MODE_CLASS (mode);
6253 if (type && TREE_CODE (type) == VECTOR_TYPE)
6255 /* Vector types deserve special treatment because they are
6256 polymorphic wrt their mode, depending upon whether VIS
6257 instructions are enabled. */
6258 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
6260 /* The SPARC port defines no floating-point vector modes. */
6261 gcc_assert (mode == BLKmode);
6265 /* Integral vector types should either have a vector
6266 mode or an integral mode, because we are guaranteed
6267 by pass_by_reference that their size is not greater
6268 than 16 bytes and TImode is 16-byte wide. */
6269 gcc_assert (mode != BLKmode);
6271 /* Vector integers are handled like floats according to
6273 mclass = MODE_FLOAT;
6280 case MODE_COMPLEX_FLOAT:
6281 case MODE_VECTOR_INT:
6282 if (TARGET_ARCH64 && TARGET_FPU && named)
6284 /* If all arg slots are filled, then must pass on stack. */
6285 if (slotno >= SPARC_FP_ARG_MAX)
6288 regno = SPARC_FP_ARG_FIRST + slotno * 2;
6289 /* Arguments filling only one single FP register are
6290 right-justified in the outer double FP register. */
6291 if (GET_MODE_SIZE (mode) <= 4)
6298 case MODE_COMPLEX_INT:
6299 /* If all arg slots are filled, then must pass on stack. */
6300 if (slotno >= SPARC_INT_ARG_MAX)
6303 regno = regbase + slotno;
6307 if (mode == VOIDmode)
6308 /* MODE is VOIDmode when generating the actual call. */
6311 gcc_assert (mode == BLKmode);
6315 || (TREE_CODE (type) != RECORD_TYPE
6316 && TREE_CODE (type) != VECTOR_TYPE))
6318 /* If all arg slots are filled, then must pass on stack. */
6319 if (slotno >= SPARC_INT_ARG_MAX)
6322 regno = regbase + slotno;
6324 else /* TARGET_ARCH64 && type */
6326 /* If all arg slots are filled, then must pass on stack. */
6327 if (slotno >= SPARC_FP_ARG_MAX)
6330 if (TREE_CODE (type) == RECORD_TYPE)
6332 classify_data_t data = { false, false, false };
6333 traverse_record_type<classify_data_t, classify_registers>
6334 (type, named, &data);
6336 /* If all slots are filled except for the last one, but there
6337 is no FP field in the first word, then must pass on stack. */
6339 && !data.fp_regs_in_first_word
6340 && slotno >= SPARC_FP_ARG_MAX - 1)
6343 /* If there are only int args and all int slots are filled,
6344 then must pass on stack. */
6347 && slotno >= SPARC_INT_ARG_MAX)
6351 /* PREGNO isn't set since both int and FP regs can be used. */
6364 /* Handle recursive register counting/assigning for structure layout. */
6368 int slotno; /* slot number of the argument. */
6369 int regbase; /* regno of the base register. */
6370 int intoffset; /* offset of the first pending integer field. */
6371 int nregs; /* number of words passed in registers. */
6372 bool stack; /* true if part of the argument is on the stack. */
6373 rtx ret; /* return expression being built. */
6376 /* A subroutine of function_arg_record_value. Compute the number of integer
6377 registers to be assigned between PARMS->intoffset and BITPOS. Return
6378 true if at least one integer register is assigned or false otherwise. */
6381 compute_int_layout (HOST_WIDE_INT bitpos, assign_data_t *data, int *pnregs)
6383 if (data->intoffset < 0)
6386 const int intoffset = data->intoffset;
6387 data->intoffset = -1;
6389 const int this_slotno = data->slotno + intoffset / BITS_PER_WORD;
6390 const unsigned int startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
6391 const unsigned int endbit = ROUND_UP (bitpos, BITS_PER_WORD);
6392 int nregs = (endbit - startbit) / BITS_PER_WORD;
6394 if (nregs > 0 && nregs > SPARC_INT_ARG_MAX - this_slotno)
6396 nregs = SPARC_INT_ARG_MAX - this_slotno;
6398 /* We need to pass this field (partly) on the stack. */
6409 /* A subroutine of function_arg_record_value. Compute the number and the mode
6410 of the FP registers to be assigned for FIELD. Return true if at least one
6411 FP register is assigned or false otherwise. */
6414 compute_fp_layout (const_tree field, HOST_WIDE_INT bitpos,
6415 assign_data_t *data,
6416 int *pnregs, machine_mode *pmode)
6418 const int this_slotno = data->slotno + bitpos / BITS_PER_WORD;
6419 machine_mode mode = DECL_MODE (field);
6422 /* Slots are counted as words while regs are counted as having the size of
6423 the (inner) mode. */
6424 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE && mode == BLKmode)
6426 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6427 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
6429 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
6431 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6437 nslots = CEIL_NWORDS (nregs * GET_MODE_SIZE (mode));
6439 if (nslots > SPARC_FP_ARG_MAX - this_slotno)
6441 nslots = SPARC_FP_ARG_MAX - this_slotno;
6442 nregs = (nslots * UNITS_PER_WORD) / GET_MODE_SIZE (mode);
6444 /* We need to pass this field (partly) on the stack. */
6456 /* A subroutine of function_arg_record_value. Count the number of registers
6457 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
6460 count_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp,
6461 assign_data_t *data)
6468 if (compute_int_layout (bitpos, data, &nregs))
6469 data->nregs += nregs;
6471 if (compute_fp_layout (field, bitpos, data, &nregs, &mode))
6472 data->nregs += nregs;
6476 if (data->intoffset < 0)
6477 data->intoffset = bitpos;
6481 /* A subroutine of function_arg_record_value. Assign the bits of the
6482 structure between PARMS->intoffset and BITPOS to integer registers. */
6485 assign_int_registers (HOST_WIDE_INT bitpos, assign_data_t *data)
6487 int intoffset = data->intoffset;
6491 if (!compute_int_layout (bitpos, data, &nregs))
6494 /* If this is the trailing part of a word, only load that much into
6495 the register. Otherwise load the whole register. Note that in
6496 the latter case we may pick up unwanted bits. It's not a problem
6497 at the moment but may wish to revisit. */
6498 if (intoffset % BITS_PER_WORD != 0)
6499 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
6504 const int this_slotno = data->slotno + intoffset / BITS_PER_WORD;
6505 unsigned int regno = data->regbase + this_slotno;
6506 intoffset /= BITS_PER_UNIT;
6510 rtx reg = gen_rtx_REG (mode, regno);
6511 XVECEXP (data->ret, 0, data->stack + data->nregs)
6512 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
6516 intoffset = (intoffset | (UNITS_PER_WORD - 1)) + 1;
6518 while (--nregs > 0);
6521 /* A subroutine of function_arg_record_value. Assign FIELD at position
6522 BITPOS to FP registers. */
6525 assign_fp_registers (const_tree field, HOST_WIDE_INT bitpos,
6526 assign_data_t *data)
6531 if (!compute_fp_layout (field, bitpos, data, &nregs, &mode))
6534 const int this_slotno = data->slotno + bitpos / BITS_PER_WORD;
6535 int regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
6536 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
6538 int pos = bitpos / BITS_PER_UNIT;
6542 rtx reg = gen_rtx_REG (mode, regno);
6543 XVECEXP (data->ret, 0, data->stack + data->nregs)
6544 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6546 regno += GET_MODE_SIZE (mode) / 4;
6547 pos += GET_MODE_SIZE (mode);
6549 while (--nregs > 0);
6552 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
6553 the structure between PARMS->intoffset and BITPOS to registers. */
6556 assign_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp,
6557 assign_data_t *data)
6561 assign_int_registers (bitpos, data);
6563 assign_fp_registers (field, bitpos, data);
6567 if (data->intoffset < 0)
6568 data->intoffset = bitpos;
6572 /* Used by function_arg and sparc_function_value_1 to implement the complex
6573 conventions of the 64-bit ABI for passing and returning structures.
6574 Return an expression valid as a return value for the FUNCTION_ARG
6575 and TARGET_FUNCTION_VALUE.
6577 TYPE is the data type of the argument (as a tree).
6578 This is null for libcalls where that information may
6580 MODE is the argument's machine mode.
6581 SLOTNO is the index number of the argument's slot in the parameter array.
6582 NAMED is true if this argument is a named parameter
6583 (otherwise it is an extra parameter matching an ellipsis).
6584 REGBASE is the regno of the base register for the parameter array. */
6587 function_arg_record_value (const_tree type, machine_mode mode,
6588 int slotno, bool named, int regbase)
6590 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6594 data.slotno = slotno;
6595 data.regbase = regbase;
6597 /* Count how many registers we need. */
6601 traverse_record_type<assign_data_t, count_registers> (type, named, &data);
6603 /* Take into account pending integer fields. */
6604 if (compute_int_layout (typesize * BITS_PER_UNIT, &data, &nregs))
6605 data.nregs += nregs;
6607 /* Allocate the vector and handle some annoying special cases. */
6612 /* ??? Empty structure has no value? Duh? */
6615 /* Though there's nothing really to store, return a word register
6616 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6617 leads to breakage due to the fact that there are zero bytes to
6619 return gen_rtx_REG (mode, regbase);
6622 /* ??? C++ has structures with no fields, and yet a size. Give up
6623 for now and pass everything back in integer registers. */
6624 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6625 if (nregs + slotno > SPARC_INT_ARG_MAX)
6626 nregs = SPARC_INT_ARG_MAX - slotno;
6629 gcc_assert (nregs > 0);
6631 data.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (data.stack + nregs));
6633 /* If at least one field must be passed on the stack, generate
6634 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6635 also be passed on the stack. We can't do much better because the
6636 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6637 of structures for which the fields passed exclusively in registers
6638 are not at the beginning of the structure. */
6640 XVECEXP (data.ret, 0, 0)
6641 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6643 /* Assign the registers. */
6646 traverse_record_type<assign_data_t, assign_registers> (type, named, &data);
6648 /* Assign pending integer fields. */
6649 assign_int_registers (typesize * BITS_PER_UNIT, &data);
6651 gcc_assert (data.nregs == nregs);
6656 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6657 of the 64-bit ABI for passing and returning unions.
6658 Return an expression valid as a return value for the FUNCTION_ARG
6659 and TARGET_FUNCTION_VALUE.
6661 SIZE is the size in bytes of the union.
6662 MODE is the argument's machine mode.
6663 REGNO is the hard register the union will be passed in. */
6666 function_arg_union_value (int size, machine_mode mode, int slotno,
6669 int nwords = CEIL_NWORDS (size), i;
6672 /* See comment in previous function for empty structures. */
6674 return gen_rtx_REG (mode, regno);
6676 if (slotno == SPARC_INT_ARG_MAX - 1)
6679 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
6681 for (i = 0; i < nwords; i++)
6683 /* Unions are passed left-justified. */
6684 XVECEXP (regs, 0, i)
6685 = gen_rtx_EXPR_LIST (VOIDmode,
6686 gen_rtx_REG (word_mode, regno),
6687 GEN_INT (UNITS_PER_WORD * i));
6694 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6695 for passing and returning BLKmode vectors.
6696 Return an expression valid as a return value for the FUNCTION_ARG
6697 and TARGET_FUNCTION_VALUE.
6699 SIZE is the size in bytes of the vector.
6700 REGNO is the FP hard register the vector will be passed in. */
6703 function_arg_vector_value (int size, int regno)
6705 const int nregs = MAX (1, size / 8);
6706 rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
6709 XVECEXP (regs, 0, 0)
6710 = gen_rtx_EXPR_LIST (VOIDmode,
6711 gen_rtx_REG (SImode, regno),
6714 for (int i = 0; i < nregs; i++)
6715 XVECEXP (regs, 0, i)
6716 = gen_rtx_EXPR_LIST (VOIDmode,
6717 gen_rtx_REG (DImode, regno + 2*i),
6723 /* Determine where to put an argument to a function.
6724 Value is zero to push the argument on the stack,
6725 or a hard register in which to store the argument.
6727 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6728 the preceding args and about the function being called.
6729 MODE is the argument's machine mode.
6730 TYPE is the data type of the argument (as a tree).
6731 This is null for libcalls where that information may
6733 NAMED is true if this argument is a named parameter
6734 (otherwise it is an extra parameter matching an ellipsis).
6735 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6736 TARGET_FUNCTION_INCOMING_ARG. */
6739 sparc_function_arg_1 (cumulative_args_t cum_v, machine_mode mode,
6740 const_tree type, bool named, bool incoming)
6742 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6744 int regbase = (incoming
6745 ? SPARC_INCOMING_INT_ARG_FIRST
6746 : SPARC_OUTGOING_INT_ARG_FIRST);
6747 int slotno, regno, padding;
6748 enum mode_class mclass = GET_MODE_CLASS (mode);
6750 slotno = function_arg_slotno (cum, mode, type, named, incoming,
6755 /* Vector types deserve special treatment because they are polymorphic wrt
6756 their mode, depending upon whether VIS instructions are enabled. */
6757 if (type && TREE_CODE (type) == VECTOR_TYPE)
6759 HOST_WIDE_INT size = int_size_in_bytes (type);
6760 gcc_assert ((TARGET_ARCH32 && size <= 8)
6761 || (TARGET_ARCH64 && size <= 16));
6763 if (mode == BLKmode)
6764 return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno);
6766 mclass = MODE_FLOAT;
6770 return gen_rtx_REG (mode, regno);
6772 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6773 and are promoted to registers if possible. */
6774 if (type && TREE_CODE (type) == RECORD_TYPE)
6776 HOST_WIDE_INT size = int_size_in_bytes (type);
6777 gcc_assert (size <= 16);
6779 return function_arg_record_value (type, mode, slotno, named, regbase);
6782 /* Unions up to 16 bytes in size are passed in integer registers. */
6783 else if (type && TREE_CODE (type) == UNION_TYPE)
6785 HOST_WIDE_INT size = int_size_in_bytes (type);
6786 gcc_assert (size <= 16);
6788 return function_arg_union_value (size, mode, slotno, regno);
6791 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6792 but also have the slot allocated for them.
6793 If no prototype is in scope fp values in register slots get passed
6794 in two places, either fp regs and int regs or fp regs and memory. */
6795 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6796 && SPARC_FP_REG_P (regno))
6798 rtx reg = gen_rtx_REG (mode, regno);
6799 if (cum->prototype_p || cum->libcall_p)
6805 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
6809 /* On incoming, we don't need to know that the value
6810 is passed in %f0 and %i0, and it confuses other parts
6811 causing needless spillage even on the simplest cases. */
6815 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
6816 + (regno - SPARC_FP_ARG_FIRST) / 2);
6818 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6819 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
6821 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6825 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6826 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6827 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6832 /* All other aggregate types are passed in an integer register in a mode
6833 corresponding to the size of the type. */
6834 else if (type && AGGREGATE_TYPE_P (type))
6836 HOST_WIDE_INT size = int_size_in_bytes (type);
6837 gcc_assert (size <= 16);
6839 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6842 return gen_rtx_REG (mode, regno);
6845 /* Handle the TARGET_FUNCTION_ARG target hook. */
6848 sparc_function_arg (cumulative_args_t cum, machine_mode mode,
6849 const_tree type, bool named)
6851 return sparc_function_arg_1 (cum, mode, type, named, false);
6854 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6857 sparc_function_incoming_arg (cumulative_args_t cum, machine_mode mode,
6858 const_tree type, bool named)
6860 return sparc_function_arg_1 (cum, mode, type, named, true);
6863 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6866 sparc_function_arg_boundary (machine_mode mode, const_tree type)
6868 return ((TARGET_ARCH64
6869 && (GET_MODE_ALIGNMENT (mode) == 128
6870 || (type && TYPE_ALIGN (type) == 128)))
6875 /* For an arg passed partly in registers and partly in memory,
6876 this is the number of bytes of registers used.
6877 For args passed entirely in registers or entirely in memory, zero.
6879 Any arg that starts in the first 6 regs but won't entirely fit in them
6880 needs partial registers on v8. On v9, structures with integer
6881 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6882 values that begin in the last fp reg [where "last fp reg" varies with the
6883 mode] will be split between that reg and memory. */
6886 sparc_arg_partial_bytes (cumulative_args_t cum, machine_mode mode,
6887 tree type, bool named)
6889 int slotno, regno, padding;
6891 /* We pass false for incoming here, it doesn't matter. */
6892 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
6893 false, ®no, &padding);
6900 if ((slotno + (mode == BLKmode
6901 ? CEIL_NWORDS (int_size_in_bytes (type))
6902 : CEIL_NWORDS (GET_MODE_SIZE (mode))))
6903 > SPARC_INT_ARG_MAX)
6904 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
6908 /* We are guaranteed by pass_by_reference that the size of the
6909 argument is not greater than 16 bytes, so we only need to return
6910 one word if the argument is partially passed in registers. */
6912 if (type && AGGREGATE_TYPE_P (type))
6914 int size = int_size_in_bytes (type);
6916 if (size > UNITS_PER_WORD
6917 && (slotno == SPARC_INT_ARG_MAX - 1
6918 || slotno == SPARC_FP_ARG_MAX - 1))
6919 return UNITS_PER_WORD;
6921 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
6922 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6923 && ! (TARGET_FPU && named)))
6925 /* The complex types are passed as packed types. */
6926 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
6927 && slotno == SPARC_INT_ARG_MAX - 1)
6928 return UNITS_PER_WORD;
6930 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6932 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
6934 return UNITS_PER_WORD;
6941 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6942 Specify whether to pass the argument by reference. */
6945 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
6946 machine_mode mode, const_tree type,
6947 bool named ATTRIBUTE_UNUSED)
6950 /* Original SPARC 32-bit ABI says that structures and unions,
6951 and quad-precision floats are passed by reference. For Pascal,
6952 also pass arrays by reference. All other base types are passed
6955 Extended ABI (as implemented by the Sun compiler) says that all
6956 complex floats are passed by reference. Pass complex integers
6957 in registers up to 8 bytes. More generally, enforce the 2-word
6958 cap for passing arguments in registers.
6960 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6961 integers are passed like floats of the same size, that is in
6962 registers up to 8 bytes. Pass all vector floats by reference
6963 like structure and unions. */
6964 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
6966 /* Catch CDImode, TFmode, DCmode and TCmode. */
6967 || GET_MODE_SIZE (mode) > 8
6969 && TREE_CODE (type) == VECTOR_TYPE
6970 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6972 /* Original SPARC 64-bit ABI says that structures and unions
6973 smaller than 16 bytes are passed in registers, as well as
6974 all other base types.
6976 Extended ABI (as implemented by the Sun compiler) says that
6977 complex floats are passed in registers up to 16 bytes. Pass
6978 all complex integers in registers up to 16 bytes. More generally,
6979 enforce the 2-word cap for passing arguments in registers.
6981 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6982 integers are passed like floats of the same size, that is in
6983 registers (up to 16 bytes). Pass all vector floats like structure
6986 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
6987 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
6988 /* Catch CTImode and TCmode. */
6989 || GET_MODE_SIZE (mode) > 16);
6992 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6993 Update the data in CUM to advance over an argument
6994 of mode MODE and data type TYPE.
6995 TYPE is null for libcalls where that information may not be available. */
6998 sparc_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
6999 const_tree type, bool named)
7001 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7004 /* We pass false for incoming here, it doesn't matter. */
7005 function_arg_slotno (cum, mode, type, named, false, ®no, &padding);
7007 /* If argument requires leading padding, add it. */
7008 cum->words += padding;
7011 cum->words += (mode == BLKmode
7012 ? CEIL_NWORDS (int_size_in_bytes (type))
7013 : CEIL_NWORDS (GET_MODE_SIZE (mode)));
7016 if (type && AGGREGATE_TYPE_P (type))
7018 int size = int_size_in_bytes (type);
7022 else if (size <= 16)
7024 else /* passed by reference */
7028 cum->words += (mode == BLKmode
7029 ? CEIL_NWORDS (int_size_in_bytes (type))
7030 : CEIL_NWORDS (GET_MODE_SIZE (mode)));
7034 /* Handle the FUNCTION_ARG_PADDING macro.
7035 For the 64 bit ABI structs are always stored left shifted in their
7039 function_arg_padding (machine_mode mode, const_tree type)
7041 if (TARGET_ARCH64 && type && AGGREGATE_TYPE_P (type))
7044 /* Fall back to the default. */
7045 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7048 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7049 Specify whether to return the return value in memory. */
7052 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7055 /* Original SPARC 32-bit ABI says that structures and unions,
7056 and quad-precision floats are returned in memory. All other
7057 base types are returned in registers.
7059 Extended ABI (as implemented by the Sun compiler) says that
7060 all complex floats are returned in registers (8 FP registers
7061 at most for '_Complex long double'). Return all complex integers
7062 in registers (4 at most for '_Complex long long').
7064 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7065 integers are returned like floats of the same size, that is in
7066 registers up to 8 bytes and in memory otherwise. Return all
7067 vector floats in memory like structure and unions; note that
7068 they always have BLKmode like the latter. */
7069 return (TYPE_MODE (type) == BLKmode
7070 || TYPE_MODE (type) == TFmode
7071 || (TREE_CODE (type) == VECTOR_TYPE
7072 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
7074 /* Original SPARC 64-bit ABI says that structures and unions
7075 smaller than 32 bytes are returned in registers, as well as
7076 all other base types.
7078 Extended ABI (as implemented by the Sun compiler) says that all
7079 complex floats are returned in registers (8 FP registers at most
7080 for '_Complex long double'). Return all complex integers in
7081 registers (4 at most for '_Complex TItype').
7083 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7084 integers are returned like floats of the same size, that is in
7085 registers. Return all vector floats like structure and unions;
7086 note that they always have BLKmode like the latter. */
7087 return (TYPE_MODE (type) == BLKmode
7088 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
7091 /* Handle the TARGET_STRUCT_VALUE target hook.
7092 Return where to find the structure return value address. */
7095 sparc_struct_value_rtx (tree fndecl, int incoming)
7104 mem = gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx,
7105 STRUCT_VALUE_OFFSET));
7107 mem = gen_frame_mem (Pmode, plus_constant (Pmode, stack_pointer_rtx,
7108 STRUCT_VALUE_OFFSET));
7110 /* Only follow the SPARC ABI for fixed-size structure returns.
7111 Variable size structure returns are handled per the normal
7112 procedures in GCC. This is enabled by -mstd-struct-return */
7114 && sparc_std_struct_return
7115 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
7116 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
7118 /* We must check and adjust the return address, as it is optional
7119 as to whether the return object is really provided. */
7120 rtx ret_reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
7121 rtx scratch = gen_reg_rtx (SImode);
7122 rtx_code_label *endlab = gen_label_rtx ();
7124 /* Calculate the return object size. */
7125 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
7126 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
7127 /* Construct a temporary return value. */
7129 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
7131 /* Implement SPARC 32-bit psABI callee return struct checking:
7133 Fetch the instruction where we will return to and see if
7134 it's an unimp instruction (the most significant 10 bits
7136 emit_move_insn (scratch, gen_rtx_MEM (SImode,
7137 plus_constant (Pmode,
7139 /* Assume the size is valid and pre-adjust. */
7140 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4)));
7141 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
7143 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4)));
7144 /* Write the address of the memory pointed to by temp_val into
7145 the memory pointed to by mem. */
7146 emit_move_insn (mem, XEXP (temp_val, 0));
7147 emit_label (endlab);
7154 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7155 For v9, function return values are subject to the same rules as arguments,
7156 except that up to 32 bytes may be returned in registers. */
7159 sparc_function_value_1 (const_tree type, machine_mode mode,
7162 /* Beware that the two values are swapped here wrt function_arg. */
7163 int regbase = (outgoing
7164 ? SPARC_INCOMING_INT_ARG_FIRST
7165 : SPARC_OUTGOING_INT_ARG_FIRST);
7166 enum mode_class mclass = GET_MODE_CLASS (mode);
7169 /* Vector types deserve special treatment because they are polymorphic wrt
7170 their mode, depending upon whether VIS instructions are enabled. */
7171 if (type && TREE_CODE (type) == VECTOR_TYPE)
7173 HOST_WIDE_INT size = int_size_in_bytes (type);
7174 gcc_assert ((TARGET_ARCH32 && size <= 8)
7175 || (TARGET_ARCH64 && size <= 32));
7177 if (mode == BLKmode)
7178 return function_arg_vector_value (size, SPARC_FP_ARG_FIRST);
7180 mclass = MODE_FLOAT;
7183 if (TARGET_ARCH64 && type)
7185 /* Structures up to 32 bytes in size are returned in registers. */
7186 if (TREE_CODE (type) == RECORD_TYPE)
7188 HOST_WIDE_INT size = int_size_in_bytes (type);
7189 gcc_assert (size <= 32);
7191 return function_arg_record_value (type, mode, 0, 1, regbase);
7194 /* Unions up to 32 bytes in size are returned in integer registers. */
7195 else if (TREE_CODE (type) == UNION_TYPE)
7197 HOST_WIDE_INT size = int_size_in_bytes (type);
7198 gcc_assert (size <= 32);
7200 return function_arg_union_value (size, mode, 0, regbase);
7203 /* Objects that require it are returned in FP registers. */
7204 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7207 /* All other aggregate types are returned in an integer register in a
7208 mode corresponding to the size of the type. */
7209 else if (AGGREGATE_TYPE_P (type))
7211 /* All other aggregate types are passed in an integer register
7212 in a mode corresponding to the size of the type. */
7213 HOST_WIDE_INT size = int_size_in_bytes (type);
7214 gcc_assert (size <= 32);
7216 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7218 /* ??? We probably should have made the same ABI change in
7219 3.4.0 as the one we made for unions. The latter was
7220 required by the SCD though, while the former is not
7221 specified, so we favored compatibility and efficiency.
7223 Now we're stuck for aggregates larger than 16 bytes,
7224 because OImode vanished in the meantime. Let's not
7225 try to be unduly clever, and simply follow the ABI
7226 for unions in that case. */
7227 if (mode == BLKmode)
7228 return function_arg_union_value (size, mode, 0, regbase);
7233 /* We should only have pointer and integer types at this point. This
7234 must match sparc_promote_function_mode. */
7235 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
7239 /* We should only have pointer and integer types at this point, except with
7240 -freg-struct-return. This must match sparc_promote_function_mode. */
7241 else if (TARGET_ARCH32
7242 && !(type && AGGREGATE_TYPE_P (type))
7243 && mclass == MODE_INT
7244 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
7247 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
7248 regno = SPARC_FP_ARG_FIRST;
7252 return gen_rtx_REG (mode, regno);
7255 /* Handle TARGET_FUNCTION_VALUE.
7256 On the SPARC, the value is found in the first "output" register, but the
7257 called function leaves it in the first "input" register. */
7260 sparc_function_value (const_tree valtype,
7261 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
7264 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
7267 /* Handle TARGET_LIBCALL_VALUE. */
7270 sparc_libcall_value (machine_mode mode,
7271 const_rtx fun ATTRIBUTE_UNUSED)
7273 return sparc_function_value_1 (NULL_TREE, mode, false);
7276 /* Handle FUNCTION_VALUE_REGNO_P.
7277 On the SPARC, the first "output" reg is used for integer values, and the
7278 first floating point register is used for floating point values. */
7281 sparc_function_value_regno_p (const unsigned int regno)
7283 return (regno == 8 || (TARGET_FPU && regno == 32));
7286 /* Do what is necessary for `va_start'. We look at the current function
7287 to determine if stdarg or varargs is used and return the address of
7288 the first unnamed parameter. */
7291 sparc_builtin_saveregs (void)
7293 int first_reg = crtl->args.info.words;
7297 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
7298 emit_move_insn (gen_rtx_MEM (word_mode,
7299 gen_rtx_PLUS (Pmode,
7301 GEN_INT (FIRST_PARM_OFFSET (0)
7304 gen_rtx_REG (word_mode,
7305 SPARC_INCOMING_INT_ARG_FIRST + regno));
7307 address = gen_rtx_PLUS (Pmode,
7309 GEN_INT (FIRST_PARM_OFFSET (0)
7310 + UNITS_PER_WORD * first_reg));
7315 /* Implement `va_start' for stdarg. */
7318 sparc_va_start (tree valist, rtx nextarg)
7320 nextarg = expand_builtin_saveregs ();
7321 std_expand_builtin_va_start (valist, nextarg);
7324 /* Implement `va_arg' for stdarg. */
7327 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
7330 HOST_WIDE_INT size, rsize, align;
7333 tree ptrtype = build_pointer_type (type);
7335 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7338 size = rsize = UNITS_PER_WORD;
7344 size = int_size_in_bytes (type);
7345 rsize = ROUND_UP (size, UNITS_PER_WORD);
7350 /* For SPARC64, objects requiring 16-byte alignment get it. */
7351 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
7352 align = 2 * UNITS_PER_WORD;
7354 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7355 are left-justified in their slots. */
7356 if (AGGREGATE_TYPE_P (type))
7359 size = rsize = UNITS_PER_WORD;
7369 incr = fold_build_pointer_plus_hwi (incr, align - 1);
7370 incr = fold_convert (sizetype, incr);
7371 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
7373 incr = fold_convert (ptr_type_node, incr);
7376 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
7379 if (BYTES_BIG_ENDIAN && size < rsize)
7380 addr = fold_build_pointer_plus_hwi (incr, rsize - size);
7384 addr = fold_convert (build_pointer_type (ptrtype), addr);
7385 addr = build_va_arg_indirect_ref (addr);
7388 /* If the address isn't aligned properly for the type, we need a temporary.
7389 FIXME: This is inefficient, usually we can do this in registers. */
7390 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
7392 tree tmp = create_tmp_var (type, "va_arg_tmp");
7393 tree dest_addr = build_fold_addr_expr (tmp);
7394 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
7395 3, dest_addr, addr, size_int (rsize));
7396 TREE_ADDRESSABLE (tmp) = 1;
7397 gimplify_and_add (copy, pre_p);
7402 addr = fold_convert (ptrtype, addr);
7404 incr = fold_build_pointer_plus_hwi (incr, rsize);
7405 gimplify_assign (valist, incr, post_p);
7407 return build_va_arg_indirect_ref (addr);
7410 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7411 Specify whether the vector mode is supported by the hardware. */
7414 sparc_vector_mode_supported_p (machine_mode mode)
7416 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
7419 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7422 sparc_preferred_simd_mode (machine_mode mode)
7440 /* Return the string to output an unconditional branch to LABEL, which is
7441 the operand number of the label.
7443 DEST is the destination insn (i.e. the label), INSN is the source. */
7446 output_ubranch (rtx dest, rtx_insn *insn)
7448 static char string[64];
7449 bool v9_form = false;
7453 /* Even if we are trying to use cbcond for this, evaluate
7454 whether we can use V9 branches as our backup plan. */
7457 if (INSN_ADDRESSES_SET_P ())
7458 delta = (INSN_ADDRESSES (INSN_UID (dest))
7459 - INSN_ADDRESSES (INSN_UID (insn)));
7461 /* Leave some instructions for "slop". */
7462 if (TARGET_V9 && delta >= -260000 && delta < 260000)
7467 bool emit_nop = emit_cbcond_nop (insn);
7471 if (delta < -500 || delta > 500)
7477 rval = "ba,a,pt\t%%xcc, %l0";
7484 rval = "cwbe\t%%g0, %%g0, %l0\n\tnop";
7486 rval = "cwbe\t%%g0, %%g0, %l0";
7492 strcpy (string, "ba%*,pt\t%%xcc, ");
7494 strcpy (string, "b%*\t");
7496 p = strchr (string, '\0');
7507 /* Return the string to output a conditional branch to LABEL, which is
7508 the operand number of the label. OP is the conditional expression.
7509 XEXP (OP, 0) is assumed to be a condition code register (integer or
7510 floating point) and its mode specifies what kind of comparison we made.
7512 DEST is the destination insn (i.e. the label), INSN is the source.
7514 REVERSED is nonzero if we should reverse the sense of the comparison.
7516 ANNUL is nonzero if we should generate an annulling branch. */
7519 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
7522 static char string[64];
7523 enum rtx_code code = GET_CODE (op);
7524 rtx cc_reg = XEXP (op, 0);
7525 machine_mode mode = GET_MODE (cc_reg);
7526 const char *labelno, *branch;
7527 int spaces = 8, far;
7530 /* v9 branches are limited to +-1MB. If it is too far away,
7543 fbne,a,pn %fcc2, .LC29
7551 far = TARGET_V9 && (get_attr_length (insn) >= 3);
7554 /* Reversal of FP compares takes care -- an ordered compare
7555 becomes an unordered compare and vice versa. */
7556 if (mode == CCFPmode || mode == CCFPEmode)
7557 code = reverse_condition_maybe_unordered (code);
7559 code = reverse_condition (code);
7562 /* Start by writing the branch condition. */
7563 if (mode == CCFPmode || mode == CCFPEmode)
7614 /* ??? !v9: FP branches cannot be preceded by another floating point
7615 insn. Because there is currently no concept of pre-delay slots,
7616 we can fix this only by always emitting a nop before a floating
7621 strcpy (string, "nop\n\t");
7622 strcat (string, branch);
7635 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7647 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7668 strcpy (string, branch);
7670 spaces -= strlen (branch);
7671 p = strchr (string, '\0');
7673 /* Now add the annulling, the label, and a possible noop. */
7686 if (! far && insn && INSN_ADDRESSES_SET_P ())
7688 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7689 - INSN_ADDRESSES (INSN_UID (insn)));
7690 /* Leave some instructions for "slop". */
7691 if (delta < -260000 || delta >= 260000)
7695 if (mode == CCFPmode || mode == CCFPEmode)
7697 static char v9_fcc_labelno[] = "%%fccX, ";
7698 /* Set the char indicating the number of the fcc reg to use. */
7699 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
7700 labelno = v9_fcc_labelno;
7703 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
7707 else if (mode == CCXmode || mode == CCX_NOOVmode)
7709 labelno = "%%xcc, ";
7714 labelno = "%%icc, ";
7719 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7722 ((XINT (note, 0) >= REG_BR_PROB_BASE / 2) ^ far)
7735 strcpy (p, labelno);
7736 p = strchr (p, '\0');
7739 strcpy (p, ".+12\n\t nop\n\tb\t");
7740 /* Skip the next insn if requested or
7741 if we know that it will be a nop. */
7742 if (annul || ! final_sequence)
7756 /* Emit a library call comparison between floating point X and Y.
7757 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7758 Return the new operator to be used in the comparison sequence.
7760 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7761 values as arguments instead of the TFmode registers themselves,
7762 that's why we cannot call emit_float_lib_cmp. */
7765 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
7768 rtx slot0, slot1, result, tem, tem2, libfunc;
7770 enum rtx_code new_comparison;
7775 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
7779 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
7783 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
7787 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
7791 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
7795 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
7806 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
7817 tree expr = MEM_EXPR (x);
7819 mark_addressable (expr);
7824 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode));
7825 emit_move_insn (slot0, x);
7830 tree expr = MEM_EXPR (y);
7832 mark_addressable (expr);
7837 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode));
7838 emit_move_insn (slot1, y);
7841 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7842 emit_library_call (libfunc, LCT_NORMAL,
7844 XEXP (slot0, 0), Pmode,
7845 XEXP (slot1, 0), Pmode);
7850 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7851 emit_library_call (libfunc, LCT_NORMAL,
7853 x, TFmode, y, TFmode);
7858 /* Immediately move the result of the libcall into a pseudo
7859 register so reload doesn't clobber the value if it needs
7860 the return register for a spill reg. */
7861 result = gen_reg_rtx (mode);
7862 emit_move_insn (result, hard_libcall_value (mode, libfunc));
7867 return gen_rtx_NE (VOIDmode, result, const0_rtx);
7870 new_comparison = (comparison == UNORDERED ? EQ : NE);
7871 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
7874 new_comparison = (comparison == UNGT ? GT : NE);
7875 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
7877 return gen_rtx_NE (VOIDmode, result, const2_rtx);
7879 tem = gen_reg_rtx (mode);
7881 emit_insn (gen_andsi3 (tem, result, const1_rtx));
7883 emit_insn (gen_anddi3 (tem, result, const1_rtx));
7884 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
7887 tem = gen_reg_rtx (mode);
7889 emit_insn (gen_addsi3 (tem, result, const1_rtx));
7891 emit_insn (gen_adddi3 (tem, result, const1_rtx));
7892 tem2 = gen_reg_rtx (mode);
7894 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
7896 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
7897 new_comparison = (comparison == UNEQ ? EQ : NE);
7898 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
7904 /* Generate an unsigned DImode to FP conversion. This is the same code
7905 optabs would emit if we didn't have TFmode patterns. */
7908 sparc_emit_floatunsdi (rtx *operands, machine_mode mode)
7910 rtx i0, i1, f0, in, out;
7913 in = force_reg (DImode, operands[1]);
7914 rtx_code_label *neglab = gen_label_rtx ();
7915 rtx_code_label *donelab = gen_label_rtx ();
7916 i0 = gen_reg_rtx (DImode);
7917 i1 = gen_reg_rtx (DImode);
7918 f0 = gen_reg_rtx (mode);
7920 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
7922 emit_insn (gen_rtx_SET (out, gen_rtx_FLOAT (mode, in)));
7923 emit_jump_insn (gen_jump (donelab));
7926 emit_label (neglab);
7928 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
7929 emit_insn (gen_anddi3 (i1, in, const1_rtx));
7930 emit_insn (gen_iordi3 (i0, i0, i1));
7931 emit_insn (gen_rtx_SET (f0, gen_rtx_FLOAT (mode, i0)));
7932 emit_insn (gen_rtx_SET (out, gen_rtx_PLUS (mode, f0, f0)));
7934 emit_label (donelab);
7937 /* Generate an FP to unsigned DImode conversion. This is the same code
7938 optabs would emit if we didn't have TFmode patterns. */
7941 sparc_emit_fixunsdi (rtx *operands, machine_mode mode)
7943 rtx i0, i1, f0, in, out, limit;
7946 in = force_reg (mode, operands[1]);
7947 rtx_code_label *neglab = gen_label_rtx ();
7948 rtx_code_label *donelab = gen_label_rtx ();
7949 i0 = gen_reg_rtx (DImode);
7950 i1 = gen_reg_rtx (DImode);
7951 limit = gen_reg_rtx (mode);
7952 f0 = gen_reg_rtx (mode);
7954 emit_move_insn (limit,
7955 const_double_from_real_value (
7956 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
7957 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
7959 emit_insn (gen_rtx_SET (out,
7960 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
7961 emit_jump_insn (gen_jump (donelab));
7964 emit_label (neglab);
7966 emit_insn (gen_rtx_SET (f0, gen_rtx_MINUS (mode, in, limit)));
7967 emit_insn (gen_rtx_SET (i0,
7968 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
7969 emit_insn (gen_movdi (i1, const1_rtx));
7970 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
7971 emit_insn (gen_xordi3 (out, i0, i1));
7973 emit_label (donelab);
7976 /* Return the string to output a compare and branch instruction to DEST.
7977 DEST is the destination insn (i.e. the label), INSN is the source,
7978 and OP is the conditional expression. */
7981 output_cbcond (rtx op, rtx dest, rtx_insn *insn)
7983 machine_mode mode = GET_MODE (XEXP (op, 0));
7984 enum rtx_code code = GET_CODE (op);
7985 const char *cond_str, *tmpl;
7986 int far, emit_nop, len;
7987 static char string[64];
7990 /* Compare and Branch is limited to +-2KB. If it is too far away,
8002 len = get_attr_length (insn);
8005 emit_nop = len == 2;
8008 code = reverse_condition (code);
8010 size_char = ((mode == SImode) ? 'w' : 'x');
8023 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
8038 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
8066 int veryfar = 1, delta;
8068 if (INSN_ADDRESSES_SET_P ())
8070 delta = (INSN_ADDRESSES (INSN_UID (dest))
8071 - INSN_ADDRESSES (INSN_UID (insn)));
8072 /* Leave some instructions for "slop". */
8073 if (delta >= -260000 && delta < 260000)
8078 tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8080 tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8085 tmpl = "c%cb%s\t%%1, %%2, %%3\n\tnop";
8087 tmpl = "c%cb%s\t%%1, %%2, %%3";
8090 snprintf (string, sizeof(string), tmpl, size_char, cond_str);
8095 /* Return the string to output a conditional branch to LABEL, testing
8096 register REG. LABEL is the operand number of the label; REG is the
8097 operand number of the reg. OP is the conditional expression. The mode
8098 of REG says what kind of comparison we made.
8100 DEST is the destination insn (i.e. the label), INSN is the source.
8102 REVERSED is nonzero if we should reverse the sense of the comparison.
8104 ANNUL is nonzero if we should generate an annulling branch. */
8107 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
8108 int annul, rtx_insn *insn)
8110 static char string[64];
8111 enum rtx_code code = GET_CODE (op);
8112 machine_mode mode = GET_MODE (XEXP (op, 0));
8117 /* branch on register are limited to +-128KB. If it is too far away,
8130 brgez,a,pn %o1, .LC29
8136 ba,pt %xcc, .LC29 */
8138 far = get_attr_length (insn) >= 3;
8140 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8142 code = reverse_condition (code);
8144 /* Only 64 bit versions of these instructions exist. */
8145 gcc_assert (mode == DImode);
8147 /* Start by writing the branch condition. */
8152 strcpy (string, "brnz");
8156 strcpy (string, "brz");
8160 strcpy (string, "brgez");
8164 strcpy (string, "brlz");
8168 strcpy (string, "brlez");
8172 strcpy (string, "brgz");
8179 p = strchr (string, '\0');
8181 /* Now add the annulling, reg, label, and nop. */
8188 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
8191 ((XINT (note, 0) >= REG_BR_PROB_BASE / 2) ^ far)
8196 *p = p < string + 8 ? '\t' : ' ';
8204 int veryfar = 1, delta;
8206 if (INSN_ADDRESSES_SET_P ())
8208 delta = (INSN_ADDRESSES (INSN_UID (dest))
8209 - INSN_ADDRESSES (INSN_UID (insn)));
8210 /* Leave some instructions for "slop". */
8211 if (delta >= -260000 && delta < 260000)
8215 strcpy (p, ".+12\n\t nop\n\t");
8216 /* Skip the next insn if requested or
8217 if we know that it will be a nop. */
8218 if (annul || ! final_sequence)
8228 strcpy (p, "ba,pt\t%%xcc, ");
8242 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8243 Such instructions cannot be used in the delay slot of return insn on v9.
8244 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8248 epilogue_renumber (register rtx *where, int test)
8250 register const char *fmt;
8252 register enum rtx_code code;
8257 code = GET_CODE (*where);
8262 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
8264 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
8265 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
8270 case CONST_WIDE_INT:
8274 /* Do not replace the frame pointer with the stack pointer because
8275 it can cause the delayed instruction to load below the stack.
8276 This occurs when instructions like:
8278 (set (reg/i:SI 24 %i0)
8279 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8280 (const_int -20 [0xffffffec])) 0))
8282 are in the return delayed slot. */
8284 if (GET_CODE (XEXP (*where, 0)) == REG
8285 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
8286 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
8287 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
8292 if (SPARC_STACK_BIAS
8293 && GET_CODE (XEXP (*where, 0)) == REG
8294 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
8302 fmt = GET_RTX_FORMAT (code);
8304 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8309 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
8310 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
8313 else if (fmt[i] == 'e'
8314 && epilogue_renumber (&(XEXP (*where, i)), test))
8320 /* Leaf functions and non-leaf functions have different needs. */
8323 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
8326 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
8328 static const int *const reg_alloc_orders[] = {
8329 reg_leaf_alloc_order,
8330 reg_nonleaf_alloc_order};
8333 order_regs_for_local_alloc (void)
8335 static int last_order_nonleaf = 1;
8337 if (df_regs_ever_live_p (15) != last_order_nonleaf)
8339 last_order_nonleaf = !last_order_nonleaf;
8340 memcpy ((char *) reg_alloc_order,
8341 (const char *) reg_alloc_orders[last_order_nonleaf],
8342 FIRST_PSEUDO_REGISTER * sizeof (int));
8346 /* Return 1 if REG and MEM are legitimate enough to allow the various
8347 mem<-->reg splits to be run. */
8350 sparc_splitdi_legitimate (rtx reg, rtx mem)
8352 /* Punt if we are here by mistake. */
8353 gcc_assert (reload_completed);
8355 /* We must have an offsettable memory reference. */
8356 if (! offsettable_memref_p (mem))
8359 /* If we have legitimate args for ldd/std, we do not want
8360 the split to happen. */
8361 if ((REGNO (reg) % 2) == 0
8362 && mem_min_alignment (mem, 8))
8369 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8372 sparc_split_regreg_legitimate (rtx reg1, rtx reg2)
8376 if (GET_CODE (reg1) == SUBREG)
8377 reg1 = SUBREG_REG (reg1);
8378 if (GET_CODE (reg1) != REG)
8380 regno1 = REGNO (reg1);
8382 if (GET_CODE (reg2) == SUBREG)
8383 reg2 = SUBREG_REG (reg2);
8384 if (GET_CODE (reg2) != REG)
8386 regno2 = REGNO (reg2);
8388 if (SPARC_INT_REG_P (regno1) && SPARC_INT_REG_P (regno2))
8393 if ((SPARC_INT_REG_P (regno1) && SPARC_FP_REG_P (regno2))
8394 || (SPARC_FP_REG_P (regno1) && SPARC_INT_REG_P (regno2)))
8401 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8402 This makes them candidates for using ldd and std insns.
8404 Note reg1 and reg2 *must* be hard registers. */
8407 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
8409 /* We might have been passed a SUBREG. */
8410 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8413 if (REGNO (reg1) % 2 != 0)
8416 /* Integer ldd is deprecated in SPARC V9 */
8417 if (TARGET_V9 && SPARC_INT_REG_P (REGNO (reg1)))
8420 return (REGNO (reg1) == REGNO (reg2) - 1);
8423 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8426 This can only happen when addr1 and addr2, the addresses in mem1
8427 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8428 addr1 must also be aligned on a 64-bit boundary.
8430 Also iff dependent_reg_rtx is not null it should not be used to
8431 compute the address for mem1, i.e. we cannot optimize a sequence
8443 But, note that the transformation from:
8448 is perfectly fine. Thus, the peephole2 patterns always pass us
8449 the destination register of the first load, never the second one.
8451 For stores we don't have a similar problem, so dependent_reg_rtx is
8455 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
8459 HOST_WIDE_INT offset1;
8461 /* The mems cannot be volatile. */
8462 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8465 /* MEM1 should be aligned on a 64-bit boundary. */
8466 if (MEM_ALIGN (mem1) < 64)
8469 addr1 = XEXP (mem1, 0);
8470 addr2 = XEXP (mem2, 0);
8472 /* Extract a register number and offset (if used) from the first addr. */
8473 if (GET_CODE (addr1) == PLUS)
8475 /* If not a REG, return zero. */
8476 if (GET_CODE (XEXP (addr1, 0)) != REG)
8480 reg1 = REGNO (XEXP (addr1, 0));
8481 /* The offset must be constant! */
8482 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8484 offset1 = INTVAL (XEXP (addr1, 1));
8487 else if (GET_CODE (addr1) != REG)
8491 reg1 = REGNO (addr1);
8492 /* This was a simple (mem (reg)) expression. Offset is 0. */
8496 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8497 if (GET_CODE (addr2) != PLUS)
8500 if (GET_CODE (XEXP (addr2, 0)) != REG
8501 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8504 if (reg1 != REGNO (XEXP (addr2, 0)))
8507 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
8510 /* The first offset must be evenly divisible by 8 to ensure the
8511 address is 64 bit aligned. */
8512 if (offset1 % 8 != 0)
8515 /* The offset for the second addr must be 4 more than the first addr. */
8516 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
8519 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8524 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8527 widen_mem_for_ldd_peep (rtx mem1, rtx mem2, machine_mode mode)
8529 rtx x = widen_memory_access (mem1, mode, 0);
8530 MEM_NOTRAP_P (x) = MEM_NOTRAP_P (mem1) && MEM_NOTRAP_P (mem2);
8534 /* Return 1 if reg is a pseudo, or is the first register in
8535 a hard register pair. This makes it suitable for use in
8536 ldd and std insns. */
8539 register_ok_for_ldd (rtx reg)
8541 /* We might have been passed a SUBREG. */
8545 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
8546 return (REGNO (reg) % 2 == 0);
8551 /* Return 1 if OP, a MEM, has an address which is known to be
8552 aligned to an 8-byte boundary. */
8555 memory_ok_for_ldd (rtx op)
8557 /* In 64-bit mode, we assume that the address is word-aligned. */
8558 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
8561 if (! can_create_pseudo_p ()
8562 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
8568 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8571 sparc_print_operand_punct_valid_p (unsigned char code)
8584 /* Implement TARGET_PRINT_OPERAND.
8585 Print operand X (an rtx) in assembler syntax to file FILE.
8586 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8587 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8590 sparc_print_operand (FILE *file, rtx x, int code)
8595 /* Output an insn in a delay slot. */
8597 sparc_indent_opcode = 1;
8599 fputs ("\n\t nop", file);
8602 /* Output an annul flag if there's nothing for the delay slot and we
8603 are optimizing. This is always used with '(' below.
8604 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8605 this is a dbx bug. So, we only do this when optimizing.
8606 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8607 Always emit a nop in case the next instruction is a branch. */
8608 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
8612 /* Output a 'nop' if there's nothing for the delay slot and we are
8613 not optimizing. This is always used with '*' above. */
8614 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
8615 fputs ("\n\t nop", file);
8616 else if (final_sequence)
8617 sparc_indent_opcode = 1;
8620 /* Output the right displacement from the saved PC on function return.
8621 The caller may have placed an "unimp" insn immediately after the call
8622 so we have to account for it. This insn is used in the 32-bit ABI
8623 when calling a function that returns a non zero-sized structure. The
8624 64-bit ABI doesn't have it. Be careful to have this test be the same
8625 as that for the call. The exception is when sparc_std_struct_return
8626 is enabled, the psABI is followed exactly and the adjustment is made
8627 by the code in sparc_struct_value_rtx. The call emitted is the same
8628 when sparc_std_struct_return is enabled. */
8630 && cfun->returns_struct
8631 && !sparc_std_struct_return
8632 && DECL_SIZE (DECL_RESULT (current_function_decl))
8633 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
8635 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
8641 /* Output the Embedded Medium/Anywhere code model base register. */
8642 fputs (EMBMEDANY_BASE_REG, file);
8645 /* Print some local dynamic TLS name. */
8646 if (const char *name = get_some_local_dynamic_name ())
8647 assemble_name (file, name);
8649 output_operand_lossage ("'%%&' used without any "
8650 "local dynamic TLS references");
8654 /* Adjust the operand to take into account a RESTORE operation. */
8655 if (GET_CODE (x) == CONST_INT)
8657 else if (GET_CODE (x) != REG)
8658 output_operand_lossage ("invalid %%Y operand");
8659 else if (REGNO (x) < 8)
8660 fputs (reg_names[REGNO (x)], file);
8661 else if (REGNO (x) >= 24 && REGNO (x) < 32)
8662 fputs (reg_names[REGNO (x)-16], file);
8664 output_operand_lossage ("invalid %%Y operand");
8667 /* Print out the low order register name of a register pair. */
8668 if (WORDS_BIG_ENDIAN)
8669 fputs (reg_names[REGNO (x)+1], file);
8671 fputs (reg_names[REGNO (x)], file);
8674 /* Print out the high order register name of a register pair. */
8675 if (WORDS_BIG_ENDIAN)
8676 fputs (reg_names[REGNO (x)], file);
8678 fputs (reg_names[REGNO (x)+1], file);
8681 /* Print out the second register name of a register pair or quad.
8682 I.e., R (%o0) => %o1. */
8683 fputs (reg_names[REGNO (x)+1], file);
8686 /* Print out the third register name of a register quad.
8687 I.e., S (%o0) => %o2. */
8688 fputs (reg_names[REGNO (x)+2], file);
8691 /* Print out the fourth register name of a register quad.
8692 I.e., T (%o0) => %o3. */
8693 fputs (reg_names[REGNO (x)+3], file);
8696 /* Print a condition code register. */
8697 if (REGNO (x) == SPARC_ICC_REG)
8699 /* We don't handle CC[X]_NOOVmode because they're not supposed
8701 if (GET_MODE (x) == CCmode)
8702 fputs ("%icc", file);
8703 else if (GET_MODE (x) == CCXmode)
8704 fputs ("%xcc", file);
8709 /* %fccN register */
8710 fputs (reg_names[REGNO (x)], file);
8713 /* Print the operand's address only. */
8714 output_address (GET_MODE (x), XEXP (x, 0));
8717 /* In this case we need a register. Use %g0 if the
8718 operand is const0_rtx. */
8720 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
8722 fputs ("%g0", file);
8729 switch (GET_CODE (x))
8731 case IOR: fputs ("or", file); break;
8732 case AND: fputs ("and", file); break;
8733 case XOR: fputs ("xor", file); break;
8734 default: output_operand_lossage ("invalid %%A operand");
8739 switch (GET_CODE (x))
8741 case IOR: fputs ("orn", file); break;
8742 case AND: fputs ("andn", file); break;
8743 case XOR: fputs ("xnor", file); break;
8744 default: output_operand_lossage ("invalid %%B operand");
8748 /* This is used by the conditional move instructions. */
8751 enum rtx_code rc = GET_CODE (x);
8755 case NE: fputs ("ne", file); break;
8756 case EQ: fputs ("e", file); break;
8757 case GE: fputs ("ge", file); break;
8758 case GT: fputs ("g", file); break;
8759 case LE: fputs ("le", file); break;
8760 case LT: fputs ("l", file); break;
8761 case GEU: fputs ("geu", file); break;
8762 case GTU: fputs ("gu", file); break;
8763 case LEU: fputs ("leu", file); break;
8764 case LTU: fputs ("lu", file); break;
8765 case LTGT: fputs ("lg", file); break;
8766 case UNORDERED: fputs ("u", file); break;
8767 case ORDERED: fputs ("o", file); break;
8768 case UNLT: fputs ("ul", file); break;
8769 case UNLE: fputs ("ule", file); break;
8770 case UNGT: fputs ("ug", file); break;
8771 case UNGE: fputs ("uge", file); break;
8772 case UNEQ: fputs ("ue", file); break;
8773 default: output_operand_lossage ("invalid %%C operand");
8778 /* This are used by the movr instruction pattern. */
8781 enum rtx_code rc = GET_CODE (x);
8784 case NE: fputs ("ne", file); break;
8785 case EQ: fputs ("e", file); break;
8786 case GE: fputs ("gez", file); break;
8787 case LT: fputs ("lz", file); break;
8788 case LE: fputs ("lez", file); break;
8789 case GT: fputs ("gz", file); break;
8790 default: output_operand_lossage ("invalid %%D operand");
8797 /* Print a sign-extended character. */
8798 int i = trunc_int_for_mode (INTVAL (x), QImode);
8799 fprintf (file, "%d", i);
8804 /* Operand must be a MEM; write its address. */
8805 if (GET_CODE (x) != MEM)
8806 output_operand_lossage ("invalid %%f operand");
8807 output_address (GET_MODE (x), XEXP (x, 0));
8812 /* Print a sign-extended 32-bit value. */
8814 if (GET_CODE(x) == CONST_INT)
8818 output_operand_lossage ("invalid %%s operand");
8821 i = trunc_int_for_mode (i, SImode);
8822 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
8827 /* Do nothing special. */
8831 /* Undocumented flag. */
8832 output_operand_lossage ("invalid operand output code");
8835 if (GET_CODE (x) == REG)
8836 fputs (reg_names[REGNO (x)], file);
8837 else if (GET_CODE (x) == MEM)
8840 /* Poor Sun assembler doesn't understand absolute addressing. */
8841 if (CONSTANT_P (XEXP (x, 0)))
8842 fputs ("%g0+", file);
8843 output_address (GET_MODE (x), XEXP (x, 0));
8846 else if (GET_CODE (x) == HIGH)
8848 fputs ("%hi(", file);
8849 output_addr_const (file, XEXP (x, 0));
8852 else if (GET_CODE (x) == LO_SUM)
8854 sparc_print_operand (file, XEXP (x, 0), 0);
8855 if (TARGET_CM_MEDMID)
8856 fputs ("+%l44(", file);
8858 fputs ("+%lo(", file);
8859 output_addr_const (file, XEXP (x, 1));
8862 else if (GET_CODE (x) == CONST_DOUBLE)
8863 output_operand_lossage ("floating-point constant not a valid immediate operand");
8865 output_addr_const (file, x);
8868 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8871 sparc_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x)
8873 register rtx base, index = 0;
8875 register rtx addr = x;
8878 fputs (reg_names[REGNO (addr)], file);
8879 else if (GET_CODE (addr) == PLUS)
8881 if (CONST_INT_P (XEXP (addr, 0)))
8882 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
8883 else if (CONST_INT_P (XEXP (addr, 1)))
8884 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
8886 base = XEXP (addr, 0), index = XEXP (addr, 1);
8887 if (GET_CODE (base) == LO_SUM)
8889 gcc_assert (USE_AS_OFFSETABLE_LO10
8891 && ! TARGET_CM_MEDMID);
8892 output_operand (XEXP (base, 0), 0);
8893 fputs ("+%lo(", file);
8894 output_address (VOIDmode, XEXP (base, 1));
8895 fprintf (file, ")+%d", offset);
8899 fputs (reg_names[REGNO (base)], file);
8901 fprintf (file, "%+d", offset);
8902 else if (REG_P (index))
8903 fprintf (file, "+%s", reg_names[REGNO (index)]);
8904 else if (GET_CODE (index) == SYMBOL_REF
8905 || GET_CODE (index) == LABEL_REF
8906 || GET_CODE (index) == CONST)
8907 fputc ('+', file), output_addr_const (file, index);
8908 else gcc_unreachable ();
8911 else if (GET_CODE (addr) == MINUS
8912 && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
8914 output_addr_const (file, XEXP (addr, 0));
8916 output_addr_const (file, XEXP (addr, 1));
8917 fputs ("-.)", file);
8919 else if (GET_CODE (addr) == LO_SUM)
8921 output_operand (XEXP (addr, 0), 0);
8922 if (TARGET_CM_MEDMID)
8923 fputs ("+%l44(", file);
8925 fputs ("+%lo(", file);
8926 output_address (VOIDmode, XEXP (addr, 1));
8930 && GET_CODE (addr) == CONST
8931 && GET_CODE (XEXP (addr, 0)) == MINUS
8932 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST
8933 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS
8934 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)
8936 addr = XEXP (addr, 0);
8937 output_addr_const (file, XEXP (addr, 0));
8938 /* Group the args of the second CONST in parenthesis. */
8940 /* Skip past the second CONST--it does nothing for us. */
8941 output_addr_const (file, XEXP (XEXP (addr, 1), 0));
8942 /* Close the parenthesis. */
8947 output_addr_const (file, addr);
8951 /* Target hook for assembling integer objects. The sparc version has
8952 special handling for aligned DI-mode objects. */
8955 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
8957 /* ??? We only output .xword's for symbols and only then in environments
8958 where the assembler can handle them. */
8959 if (aligned_p && size == 8 && GET_CODE (x) != CONST_INT)
8963 assemble_integer_with_op ("\t.xword\t", x);
8968 assemble_aligned_integer (4, const0_rtx);
8969 assemble_aligned_integer (4, x);
8973 return default_assemble_integer (x, size, aligned_p);
8976 /* Return the value of a code used in the .proc pseudo-op that says
8977 what kind of result this function returns. For non-C types, we pick
8978 the closest C type. */
8980 #ifndef SHORT_TYPE_SIZE
8981 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8984 #ifndef INT_TYPE_SIZE
8985 #define INT_TYPE_SIZE BITS_PER_WORD
8988 #ifndef LONG_TYPE_SIZE
8989 #define LONG_TYPE_SIZE BITS_PER_WORD
8992 #ifndef LONG_LONG_TYPE_SIZE
8993 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8996 #ifndef FLOAT_TYPE_SIZE
8997 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9000 #ifndef DOUBLE_TYPE_SIZE
9001 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9004 #ifndef LONG_DOUBLE_TYPE_SIZE
9005 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9009 sparc_type_code (register tree type)
9011 register unsigned long qualifiers = 0;
9012 register unsigned shift;
9014 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9015 setting more, since some assemblers will give an error for this. Also,
9016 we must be careful to avoid shifts of 32 bits or more to avoid getting
9017 unpredictable results. */
9019 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
9021 switch (TREE_CODE (type))
9027 qualifiers |= (3 << shift);
9032 qualifiers |= (2 << shift);
9036 case REFERENCE_TYPE:
9038 qualifiers |= (1 << shift);
9042 return (qualifiers | 8);
9045 case QUAL_UNION_TYPE:
9046 return (qualifiers | 9);
9049 return (qualifiers | 10);
9052 return (qualifiers | 16);
9055 /* If this is a range type, consider it to be the underlying
9057 if (TREE_TYPE (type) != 0)
9060 /* Carefully distinguish all the standard types of C,
9061 without messing up if the language is not C. We do this by
9062 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9063 look at both the names and the above fields, but that's redundant.
9064 Any type whose size is between two C types will be considered
9065 to be the wider of the two types. Also, we do not have a
9066 special code to use for "long long", so anything wider than
9067 long is treated the same. Note that we can't distinguish
9068 between "int" and "long" in this code if they are the same
9069 size, but that's fine, since neither can the assembler. */
9071 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
9072 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
9074 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
9075 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
9077 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
9078 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
9081 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
9084 /* If this is a range type, consider it to be the underlying
9086 if (TREE_TYPE (type) != 0)
9089 /* Carefully distinguish all the standard types of C,
9090 without messing up if the language is not C. */
9092 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
9093 return (qualifiers | 6);
9096 return (qualifiers | 7);
9098 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
9099 /* ??? We need to distinguish between double and float complex types,
9100 but I don't know how yet because I can't reach this code from
9101 existing front-ends. */
9102 return (qualifiers | 7); /* Who knows? */
9105 case BOOLEAN_TYPE: /* Boolean truth value type. */
9111 gcc_unreachable (); /* Not a type! */
9118 /* Nested function support. */
9120 /* Emit RTL insns to initialize the variable parts of a trampoline.
9121 FNADDR is an RTX for the address of the function's pure code.
9122 CXT is an RTX for the static chain value for the function.
9124 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9125 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9126 (to store insns). This is a bit excessive. Perhaps a different
9127 mechanism would be better here.
9129 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9132 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
9134 /* SPARC 32-bit trampoline:
9137 sethi %hi(static), %g2
9139 or %g2, %lo(static), %g2
9141 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9142 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9146 (adjust_address (m_tramp, SImode, 0),
9147 expand_binop (SImode, ior_optab,
9148 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1),
9149 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
9150 NULL_RTX, 1, OPTAB_DIRECT));
9153 (adjust_address (m_tramp, SImode, 4),
9154 expand_binop (SImode, ior_optab,
9155 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1),
9156 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
9157 NULL_RTX, 1, OPTAB_DIRECT));
9160 (adjust_address (m_tramp, SImode, 8),
9161 expand_binop (SImode, ior_optab,
9162 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
9163 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
9164 NULL_RTX, 1, OPTAB_DIRECT));
9167 (adjust_address (m_tramp, SImode, 12),
9168 expand_binop (SImode, ior_optab,
9169 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
9170 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
9171 NULL_RTX, 1, OPTAB_DIRECT));
9173 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9174 aligned on a 16 byte boundary so one flush clears it all. */
9175 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 0))));
9176 if (sparc_cpu != PROCESSOR_ULTRASPARC
9177 && sparc_cpu != PROCESSOR_ULTRASPARC3
9178 && sparc_cpu != PROCESSOR_NIAGARA
9179 && sparc_cpu != PROCESSOR_NIAGARA2
9180 && sparc_cpu != PROCESSOR_NIAGARA3
9181 && sparc_cpu != PROCESSOR_NIAGARA4)
9182 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8))));
9184 /* Call __enable_execute_stack after writing onto the stack to make sure
9185 the stack address is accessible. */
9186 #ifdef HAVE_ENABLE_EXECUTE_STACK
9187 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
9188 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
9193 /* The 64-bit version is simpler because it makes more sense to load the
9194 values as "immediate" data out of the trampoline. It's also easier since
9195 we can read the PC without clobbering a register. */
9198 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
9200 /* SPARC 64-bit trampoline:
9209 emit_move_insn (adjust_address (m_tramp, SImode, 0),
9210 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
9211 emit_move_insn (adjust_address (m_tramp, SImode, 4),
9212 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
9213 emit_move_insn (adjust_address (m_tramp, SImode, 8),
9214 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
9215 emit_move_insn (adjust_address (m_tramp, SImode, 12),
9216 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
9217 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
9218 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
9219 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
9221 if (sparc_cpu != PROCESSOR_ULTRASPARC
9222 && sparc_cpu != PROCESSOR_ULTRASPARC3
9223 && sparc_cpu != PROCESSOR_NIAGARA
9224 && sparc_cpu != PROCESSOR_NIAGARA2
9225 && sparc_cpu != PROCESSOR_NIAGARA3
9226 && sparc_cpu != PROCESSOR_NIAGARA4)
9227 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
9229 /* Call __enable_execute_stack after writing onto the stack to make sure
9230 the stack address is accessible. */
9231 #ifdef HAVE_ENABLE_EXECUTE_STACK
9232 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
9233 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
9237 /* Worker for TARGET_TRAMPOLINE_INIT. */
9240 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9242 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
9243 cxt = force_reg (Pmode, cxt);
9245 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
9247 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
9250 /* Adjust the cost of a scheduling dependency. Return the new cost of
9251 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9254 supersparc_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
9256 enum attr_type insn_type;
9258 if (recog_memoized (insn) < 0)
9261 insn_type = get_attr_type (insn);
9263 if (REG_NOTE_KIND (link) == 0)
9265 /* Data dependency; DEP_INSN writes a register that INSN reads some
9268 /* if a load, then the dependence must be on the memory address;
9269 add an extra "cycle". Note that the cost could be two cycles
9270 if the reg was written late in an instruction group; we ca not tell
9272 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
9275 /* Get the delay only if the address of the store is the dependence. */
9276 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
9278 rtx pat = PATTERN(insn);
9279 rtx dep_pat = PATTERN (dep_insn);
9281 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
9282 return cost; /* This should not happen! */
9284 /* The dependency between the two instructions was on the data that
9285 is being stored. Assume that this implies that the address of the
9286 store is not dependent. */
9287 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
9290 return cost + 3; /* An approximation. */
9293 /* A shift instruction cannot receive its data from an instruction
9294 in the same cycle; add a one cycle penalty. */
9295 if (insn_type == TYPE_SHIFT)
9296 return cost + 3; /* Split before cascade into shift. */
9300 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9301 INSN writes some cycles later. */
9303 /* These are only significant for the fpu unit; writing a fp reg before
9304 the fpu has finished with it stalls the processor. */
9306 /* Reusing an integer register causes no problems. */
9307 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
9315 hypersparc_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
9317 enum attr_type insn_type, dep_type;
9318 rtx pat = PATTERN(insn);
9319 rtx dep_pat = PATTERN (dep_insn);
9321 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
9324 insn_type = get_attr_type (insn);
9325 dep_type = get_attr_type (dep_insn);
9327 switch (REG_NOTE_KIND (link))
9330 /* Data dependency; DEP_INSN writes a register that INSN reads some
9337 /* Get the delay iff the address of the store is the dependence. */
9338 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
9341 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
9348 /* If a load, then the dependence must be on the memory address. If
9349 the addresses aren't equal, then it might be a false dependency */
9350 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
9352 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
9353 || GET_CODE (SET_DEST (dep_pat)) != MEM
9354 || GET_CODE (SET_SRC (pat)) != MEM
9355 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
9356 XEXP (SET_SRC (pat), 0)))
9364 /* Compare to branch latency is 0. There is no benefit from
9365 separating compare and branch. */
9366 if (dep_type == TYPE_COMPARE)
9368 /* Floating point compare to branch latency is less than
9369 compare to conditional move. */
9370 if (dep_type == TYPE_FPCMP)
9379 /* Anti-dependencies only penalize the fpu unit. */
9380 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
9392 sparc_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep, int cost)
9396 case PROCESSOR_SUPERSPARC:
9397 cost = supersparc_adjust_cost (insn, link, dep, cost);
9399 case PROCESSOR_HYPERSPARC:
9400 case PROCESSOR_SPARCLITE86X:
9401 cost = hypersparc_adjust_cost (insn, link, dep, cost);
9410 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
9411 int sched_verbose ATTRIBUTE_UNUSED,
9412 int max_ready ATTRIBUTE_UNUSED)
9416 sparc_use_sched_lookahead (void)
9418 if (sparc_cpu == PROCESSOR_NIAGARA
9419 || sparc_cpu == PROCESSOR_NIAGARA2
9420 || sparc_cpu == PROCESSOR_NIAGARA3)
9422 if (sparc_cpu == PROCESSOR_NIAGARA4)
9424 if (sparc_cpu == PROCESSOR_ULTRASPARC
9425 || sparc_cpu == PROCESSOR_ULTRASPARC3)
9427 if ((1 << sparc_cpu) &
9428 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
9429 (1 << PROCESSOR_SPARCLITE86X)))
9435 sparc_issue_rate (void)
9439 case PROCESSOR_NIAGARA:
9440 case PROCESSOR_NIAGARA2:
9441 case PROCESSOR_NIAGARA3:
9444 case PROCESSOR_NIAGARA4:
9446 /* Assume V9 processors are capable of at least dual-issue. */
9448 case PROCESSOR_SUPERSPARC:
9450 case PROCESSOR_HYPERSPARC:
9451 case PROCESSOR_SPARCLITE86X:
9453 case PROCESSOR_ULTRASPARC:
9454 case PROCESSOR_ULTRASPARC3:
9460 set_extends (rtx_insn *insn)
9462 register rtx pat = PATTERN (insn);
9464 switch (GET_CODE (SET_SRC (pat)))
9466 /* Load and some shift instructions zero extend. */
9469 /* sethi clears the high bits */
9471 /* LO_SUM is used with sethi. sethi cleared the high
9472 bits and the values used with lo_sum are positive */
9474 /* Store flag stores 0 or 1 */
9484 rtx op0 = XEXP (SET_SRC (pat), 0);
9485 rtx op1 = XEXP (SET_SRC (pat), 1);
9486 if (GET_CODE (op1) == CONST_INT)
9487 return INTVAL (op1) >= 0;
9488 if (GET_CODE (op0) != REG)
9490 if (sparc_check_64 (op0, insn) == 1)
9492 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
9497 rtx op0 = XEXP (SET_SRC (pat), 0);
9498 rtx op1 = XEXP (SET_SRC (pat), 1);
9499 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
9501 if (GET_CODE (op1) == CONST_INT)
9502 return INTVAL (op1) >= 0;
9503 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
9506 return GET_MODE (SET_SRC (pat)) == SImode;
9507 /* Positive integers leave the high bits zero. */
9509 return !(INTVAL (SET_SRC (pat)) & 0x80000000);
9512 return - (GET_MODE (SET_SRC (pat)) == SImode);
9514 return sparc_check_64 (SET_SRC (pat), insn);
9520 /* We _ought_ to have only one kind per function, but... */
9521 static GTY(()) rtx sparc_addr_diff_list;
9522 static GTY(()) rtx sparc_addr_list;
9525 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
9527 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9529 sparc_addr_diff_list
9530 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
9532 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
9536 sparc_output_addr_vec (rtx vec)
9538 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
9539 int idx, vlen = XVECLEN (body, 0);
9541 #ifdef ASM_OUTPUT_ADDR_VEC_START
9542 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
9545 #ifdef ASM_OUTPUT_CASE_LABEL
9546 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
9549 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
9552 for (idx = 0; idx < vlen; idx++)
9554 ASM_OUTPUT_ADDR_VEC_ELT
9555 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9558 #ifdef ASM_OUTPUT_ADDR_VEC_END
9559 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
9564 sparc_output_addr_diff_vec (rtx vec)
9566 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
9567 rtx base = XEXP (XEXP (body, 0), 0);
9568 int idx, vlen = XVECLEN (body, 1);
9570 #ifdef ASM_OUTPUT_ADDR_VEC_START
9571 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
9574 #ifdef ASM_OUTPUT_CASE_LABEL
9575 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
9578 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
9581 for (idx = 0; idx < vlen; idx++)
9583 ASM_OUTPUT_ADDR_DIFF_ELT
9586 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
9587 CODE_LABEL_NUMBER (base));
9590 #ifdef ASM_OUTPUT_ADDR_VEC_END
9591 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
9596 sparc_output_deferred_case_vectors (void)
9601 if (sparc_addr_list == NULL_RTX
9602 && sparc_addr_diff_list == NULL_RTX)
9605 /* Align to cache line in the function's code section. */
9606 switch_to_section (current_function_section ());
9608 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9610 ASM_OUTPUT_ALIGN (asm_out_file, align);
9612 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
9613 sparc_output_addr_vec (XEXP (t, 0));
9614 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
9615 sparc_output_addr_diff_vec (XEXP (t, 0));
9617 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
9620 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9621 unknown. Return 1 if the high bits are zero, -1 if the register is
9624 sparc_check_64 (rtx x, rtx_insn *insn)
9626 /* If a register is set only once it is safe to ignore insns this
9627 code does not know how to handle. The loop will either recognize
9628 the single set and return the correct value or fail to recognize
9633 gcc_assert (GET_CODE (x) == REG);
9635 if (GET_MODE (x) == DImode)
9636 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
9638 if (flag_expensive_optimizations
9639 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
9645 insn = get_last_insn_anywhere ();
9650 while ((insn = PREV_INSN (insn)))
9652 switch (GET_CODE (insn))
9665 rtx pat = PATTERN (insn);
9666 if (GET_CODE (pat) != SET)
9668 if (rtx_equal_p (x, SET_DEST (pat)))
9669 return set_extends (insn);
9670 if (y && rtx_equal_p (y, SET_DEST (pat)))
9671 return set_extends (insn);
9672 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
9680 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9681 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9684 output_v8plus_shift (rtx_insn *insn, rtx *operands, const char *opcode)
9686 static char asm_code[60];
9688 /* The scratch register is only required when the destination
9689 register is not a 64-bit global or out register. */
9690 if (which_alternative != 2)
9691 operands[3] = operands[0];
9693 /* We can only shift by constants <= 63. */
9694 if (GET_CODE (operands[2]) == CONST_INT)
9695 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
9697 if (GET_CODE (operands[1]) == CONST_INT)
9699 output_asm_insn ("mov\t%1, %3", operands);
9703 output_asm_insn ("sllx\t%H1, 32, %3", operands);
9704 if (sparc_check_64 (operands[1], insn) <= 0)
9705 output_asm_insn ("srl\t%L1, 0, %L1", operands);
9706 output_asm_insn ("or\t%L1, %3, %3", operands);
9709 strcpy (asm_code, opcode);
9711 if (which_alternative != 2)
9712 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9715 strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9718 /* Output rtl to increment the profiler label LABELNO
9719 for profiling a function entry. */
9722 sparc_profile_hook (int labelno)
9727 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
9728 if (NO_PROFILE_COUNTERS)
9730 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
9734 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9735 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9736 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
9740 #ifdef TARGET_SOLARIS
9741 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9744 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
9745 tree decl ATTRIBUTE_UNUSED)
9747 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
9749 solaris_elf_asm_comdat_section (name, flags, decl);
9753 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
9755 if (!(flags & SECTION_DEBUG))
9756 fputs (",#alloc", asm_out_file);
9757 if (flags & SECTION_WRITE)
9758 fputs (",#write", asm_out_file);
9759 if (flags & SECTION_TLS)
9760 fputs (",#tls", asm_out_file);
9761 if (flags & SECTION_CODE)
9762 fputs (",#execinstr", asm_out_file);
9764 if (flags & SECTION_NOTYPE)
9766 else if (flags & SECTION_BSS)
9767 fputs (",#nobits", asm_out_file);
9769 fputs (",#progbits", asm_out_file);
9771 fputc ('\n', asm_out_file);
9773 #endif /* TARGET_SOLARIS */
9775 /* We do not allow indirect calls to be optimized into sibling calls.
9777 We cannot use sibling calls when delayed branches are disabled
9778 because they will likely require the call delay slot to be filled.
9780 Also, on SPARC 32-bit we cannot emit a sibling call when the
9781 current function returns a structure. This is because the "unimp
9782 after call" convention would cause the callee to return to the
9783 wrong place. The generic code already disallows cases where the
9784 function being called returns a structure.
9786 It may seem strange how this last case could occur. Usually there
9787 is code after the call which jumps to epilogue code which dumps the
9788 return value into the struct return area. That ought to invalidate
9789 the sibling call right? Well, in the C++ case we can end up passing
9790 the pointer to the struct return area to a constructor (which returns
9791 void) and then nothing else happens. Such a sibling call would look
9792 valid without the added check here.
9794 VxWorks PIC PLT entries require the global pointer to be initialized
9795 on entry. We therefore can't emit sibling calls to them. */
9797 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9800 && flag_delayed_branch
9801 && (TARGET_ARCH64 || ! cfun->returns_struct)
9802 && !(TARGET_VXWORKS_RTP
9804 && !targetm.binds_local_p (decl)));
9807 /* libfunc renaming. */
9810 sparc_init_libfuncs (void)
9814 /* Use the subroutines that Sun's library provides for integer
9815 multiply and divide. The `*' prevents an underscore from
9816 being prepended by the compiler. .umul is a little faster
9818 set_optab_libfunc (smul_optab, SImode, "*.umul");
9819 set_optab_libfunc (sdiv_optab, SImode, "*.div");
9820 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
9821 set_optab_libfunc (smod_optab, SImode, "*.rem");
9822 set_optab_libfunc (umod_optab, SImode, "*.urem");
9824 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9825 set_optab_libfunc (add_optab, TFmode, "_Q_add");
9826 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
9827 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
9828 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
9829 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
9831 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9832 is because with soft-float, the SFmode and DFmode sqrt
9833 instructions will be absent, and the compiler will notice and
9834 try to use the TFmode sqrt instruction for calls to the
9835 builtin function sqrt, but this fails. */
9837 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
9839 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
9840 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
9841 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
9842 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
9843 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
9844 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
9846 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
9847 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
9848 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
9849 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
9851 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
9852 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
9853 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9854 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
9856 if (DITF_CONVERSION_LIBFUNCS)
9858 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
9859 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
9860 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9861 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
9864 if (SUN_CONVERSION_LIBFUNCS)
9866 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9867 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9868 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9869 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9874 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9875 do not exist in the library. Make sure the compiler does not
9876 emit calls to them by accident. (It should always use the
9877 hardware instructions.) */
9878 set_optab_libfunc (smul_optab, SImode, 0);
9879 set_optab_libfunc (sdiv_optab, SImode, 0);
9880 set_optab_libfunc (udiv_optab, SImode, 0);
9881 set_optab_libfunc (smod_optab, SImode, 0);
9882 set_optab_libfunc (umod_optab, SImode, 0);
9884 if (SUN_INTEGER_MULTIPLY_64)
9886 set_optab_libfunc (smul_optab, DImode, "__mul64");
9887 set_optab_libfunc (sdiv_optab, DImode, "__div64");
9888 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
9889 set_optab_libfunc (smod_optab, DImode, "__rem64");
9890 set_optab_libfunc (umod_optab, DImode, "__urem64");
9893 if (SUN_CONVERSION_LIBFUNCS)
9895 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
9896 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
9897 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
9898 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
9903 /* SPARC builtins. */
9907 SPARC_BUILTIN_LDFSR,
9908 SPARC_BUILTIN_STFSR,
9910 /* VIS 1.0 builtins. */
9911 SPARC_BUILTIN_FPACK16,
9912 SPARC_BUILTIN_FPACK32,
9913 SPARC_BUILTIN_FPACKFIX,
9914 SPARC_BUILTIN_FEXPAND,
9915 SPARC_BUILTIN_FPMERGE,
9916 SPARC_BUILTIN_FMUL8X16,
9917 SPARC_BUILTIN_FMUL8X16AU,
9918 SPARC_BUILTIN_FMUL8X16AL,
9919 SPARC_BUILTIN_FMUL8SUX16,
9920 SPARC_BUILTIN_FMUL8ULX16,
9921 SPARC_BUILTIN_FMULD8SUX16,
9922 SPARC_BUILTIN_FMULD8ULX16,
9923 SPARC_BUILTIN_FALIGNDATAV4HI,
9924 SPARC_BUILTIN_FALIGNDATAV8QI,
9925 SPARC_BUILTIN_FALIGNDATAV2SI,
9926 SPARC_BUILTIN_FALIGNDATADI,
9927 SPARC_BUILTIN_WRGSR,
9928 SPARC_BUILTIN_RDGSR,
9929 SPARC_BUILTIN_ALIGNADDR,
9930 SPARC_BUILTIN_ALIGNADDRL,
9931 SPARC_BUILTIN_PDIST,
9932 SPARC_BUILTIN_EDGE8,
9933 SPARC_BUILTIN_EDGE8L,
9934 SPARC_BUILTIN_EDGE16,
9935 SPARC_BUILTIN_EDGE16L,
9936 SPARC_BUILTIN_EDGE32,
9937 SPARC_BUILTIN_EDGE32L,
9938 SPARC_BUILTIN_FCMPLE16,
9939 SPARC_BUILTIN_FCMPLE32,
9940 SPARC_BUILTIN_FCMPNE16,
9941 SPARC_BUILTIN_FCMPNE32,
9942 SPARC_BUILTIN_FCMPGT16,
9943 SPARC_BUILTIN_FCMPGT32,
9944 SPARC_BUILTIN_FCMPEQ16,
9945 SPARC_BUILTIN_FCMPEQ32,
9946 SPARC_BUILTIN_FPADD16,
9947 SPARC_BUILTIN_FPADD16S,
9948 SPARC_BUILTIN_FPADD32,
9949 SPARC_BUILTIN_FPADD32S,
9950 SPARC_BUILTIN_FPSUB16,
9951 SPARC_BUILTIN_FPSUB16S,
9952 SPARC_BUILTIN_FPSUB32,
9953 SPARC_BUILTIN_FPSUB32S,
9954 SPARC_BUILTIN_ARRAY8,
9955 SPARC_BUILTIN_ARRAY16,
9956 SPARC_BUILTIN_ARRAY32,
9958 /* VIS 2.0 builtins. */
9959 SPARC_BUILTIN_EDGE8N,
9960 SPARC_BUILTIN_EDGE8LN,
9961 SPARC_BUILTIN_EDGE16N,
9962 SPARC_BUILTIN_EDGE16LN,
9963 SPARC_BUILTIN_EDGE32N,
9964 SPARC_BUILTIN_EDGE32LN,
9965 SPARC_BUILTIN_BMASK,
9966 SPARC_BUILTIN_BSHUFFLEV4HI,
9967 SPARC_BUILTIN_BSHUFFLEV8QI,
9968 SPARC_BUILTIN_BSHUFFLEV2SI,
9969 SPARC_BUILTIN_BSHUFFLEDI,
9971 /* VIS 3.0 builtins. */
9972 SPARC_BUILTIN_CMASK8,
9973 SPARC_BUILTIN_CMASK16,
9974 SPARC_BUILTIN_CMASK32,
9975 SPARC_BUILTIN_FCHKSM16,
9976 SPARC_BUILTIN_FSLL16,
9977 SPARC_BUILTIN_FSLAS16,
9978 SPARC_BUILTIN_FSRL16,
9979 SPARC_BUILTIN_FSRA16,
9980 SPARC_BUILTIN_FSLL32,
9981 SPARC_BUILTIN_FSLAS32,
9982 SPARC_BUILTIN_FSRL32,
9983 SPARC_BUILTIN_FSRA32,
9984 SPARC_BUILTIN_PDISTN,
9985 SPARC_BUILTIN_FMEAN16,
9986 SPARC_BUILTIN_FPADD64,
9987 SPARC_BUILTIN_FPSUB64,
9988 SPARC_BUILTIN_FPADDS16,
9989 SPARC_BUILTIN_FPADDS16S,
9990 SPARC_BUILTIN_FPSUBS16,
9991 SPARC_BUILTIN_FPSUBS16S,
9992 SPARC_BUILTIN_FPADDS32,
9993 SPARC_BUILTIN_FPADDS32S,
9994 SPARC_BUILTIN_FPSUBS32,
9995 SPARC_BUILTIN_FPSUBS32S,
9996 SPARC_BUILTIN_FUCMPLE8,
9997 SPARC_BUILTIN_FUCMPNE8,
9998 SPARC_BUILTIN_FUCMPGT8,
9999 SPARC_BUILTIN_FUCMPEQ8,
10000 SPARC_BUILTIN_FHADDS,
10001 SPARC_BUILTIN_FHADDD,
10002 SPARC_BUILTIN_FHSUBS,
10003 SPARC_BUILTIN_FHSUBD,
10004 SPARC_BUILTIN_FNHADDS,
10005 SPARC_BUILTIN_FNHADDD,
10006 SPARC_BUILTIN_UMULXHI,
10007 SPARC_BUILTIN_XMULX,
10008 SPARC_BUILTIN_XMULXHI,
10013 static GTY (()) tree sparc_builtins[(int) SPARC_BUILTIN_MAX];
10014 static enum insn_code sparc_builtins_icode[(int) SPARC_BUILTIN_MAX];
10016 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10017 function decl or NULL_TREE if the builtin was not added. */
10020 def_builtin (const char *name, enum insn_code icode, enum sparc_builtins code,
10024 = add_builtin_function (name, type, code, BUILT_IN_MD, NULL, NULL_TREE);
10028 sparc_builtins[code] = t;
10029 sparc_builtins_icode[code] = icode;
10035 /* Likewise, but also marks the function as "const". */
10038 def_builtin_const (const char *name, enum insn_code icode,
10039 enum sparc_builtins code, tree type)
10041 tree t = def_builtin (name, icode, code, type);
10044 TREE_READONLY (t) = 1;
10049 /* Implement the TARGET_INIT_BUILTINS target hook.
10050 Create builtin functions for special SPARC instructions. */
10053 sparc_init_builtins (void)
10056 sparc_fpu_init_builtins ();
10059 sparc_vis_init_builtins ();
10062 /* Create builtin functions for FPU instructions. */
10065 sparc_fpu_init_builtins (void)
10068 = build_function_type_list (void_type_node,
10069 build_pointer_type (unsigned_type_node), 0);
10070 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr,
10071 SPARC_BUILTIN_LDFSR, ftype);
10072 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr,
10073 SPARC_BUILTIN_STFSR, ftype);
10076 /* Create builtin functions for VIS instructions. */
10079 sparc_vis_init_builtins (void)
10081 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
10082 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
10083 tree v4hi = build_vector_type (intHI_type_node, 4);
10084 tree v2hi = build_vector_type (intHI_type_node, 2);
10085 tree v2si = build_vector_type (intSI_type_node, 2);
10086 tree v1si = build_vector_type (intSI_type_node, 1);
10088 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
10089 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
10090 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
10091 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
10092 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
10093 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
10094 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
10095 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
10096 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
10097 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
10098 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
10099 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
10100 tree v2hi_ftype_v2hi_v2hi = build_function_type_list (v2hi, v2hi, v2hi, 0);
10101 tree v1si_ftype_v1si_v1si = build_function_type_list (v1si, v1si, v1si, 0);
10102 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
10104 intDI_type_node, 0);
10105 tree di_ftype_v8qi_v8qi = build_function_type_list (intDI_type_node,
10107 tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node,
10109 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
10111 intDI_type_node, 0);
10112 tree si_ftype_si_si = build_function_type_list (intSI_type_node,
10114 intSI_type_node, 0);
10115 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
10117 intSI_type_node, 0);
10118 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
10120 intDI_type_node, 0);
10121 tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
10124 tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node,
10127 tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node,
10129 tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
10131 tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node,
10133 tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node,
10135 tree void_ftype_di = build_function_type_list (void_type_node,
10136 intDI_type_node, 0);
10137 tree di_ftype_void = build_function_type_list (intDI_type_node,
10138 void_type_node, 0);
10139 tree void_ftype_si = build_function_type_list (void_type_node,
10140 intSI_type_node, 0);
10141 tree sf_ftype_sf_sf = build_function_type_list (float_type_node,
10143 float_type_node, 0);
10144 tree df_ftype_df_df = build_function_type_list (double_type_node,
10146 double_type_node, 0);
10148 /* Packing and expanding vectors. */
10149 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
10150 SPARC_BUILTIN_FPACK16, v4qi_ftype_v4hi);
10151 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
10152 SPARC_BUILTIN_FPACK32, v8qi_ftype_v2si_v8qi);
10153 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
10154 SPARC_BUILTIN_FPACKFIX, v2hi_ftype_v2si);
10155 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
10156 SPARC_BUILTIN_FEXPAND, v4hi_ftype_v4qi);
10157 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
10158 SPARC_BUILTIN_FPMERGE, v8qi_ftype_v4qi_v4qi);
10160 /* Multiplications. */
10161 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
10162 SPARC_BUILTIN_FMUL8X16, v4hi_ftype_v4qi_v4hi);
10163 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
10164 SPARC_BUILTIN_FMUL8X16AU, v4hi_ftype_v4qi_v2hi);
10165 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
10166 SPARC_BUILTIN_FMUL8X16AL, v4hi_ftype_v4qi_v2hi);
10167 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
10168 SPARC_BUILTIN_FMUL8SUX16, v4hi_ftype_v8qi_v4hi);
10169 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
10170 SPARC_BUILTIN_FMUL8ULX16, v4hi_ftype_v8qi_v4hi);
10171 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
10172 SPARC_BUILTIN_FMULD8SUX16, v2si_ftype_v4qi_v2hi);
10173 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
10174 SPARC_BUILTIN_FMULD8ULX16, v2si_ftype_v4qi_v2hi);
10176 /* Data aligning. */
10177 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
10178 SPARC_BUILTIN_FALIGNDATAV4HI, v4hi_ftype_v4hi_v4hi);
10179 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
10180 SPARC_BUILTIN_FALIGNDATAV8QI, v8qi_ftype_v8qi_v8qi);
10181 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
10182 SPARC_BUILTIN_FALIGNDATAV2SI, v2si_ftype_v2si_v2si);
10183 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis,
10184 SPARC_BUILTIN_FALIGNDATADI, di_ftype_di_di);
10186 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis,
10187 SPARC_BUILTIN_WRGSR, void_ftype_di);
10188 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis,
10189 SPARC_BUILTIN_RDGSR, di_ftype_void);
10193 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
10194 SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_di);
10195 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
10196 SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_di);
10200 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
10201 SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_si);
10202 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
10203 SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_si);
10206 /* Pixel distance. */
10207 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
10208 SPARC_BUILTIN_PDIST, di_ftype_v8qi_v8qi_di);
10210 /* Edge handling. */
10213 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis,
10214 SPARC_BUILTIN_EDGE8, di_ftype_ptr_ptr);
10215 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis,
10216 SPARC_BUILTIN_EDGE8L, di_ftype_ptr_ptr);
10217 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis,
10218 SPARC_BUILTIN_EDGE16, di_ftype_ptr_ptr);
10219 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis,
10220 SPARC_BUILTIN_EDGE16L, di_ftype_ptr_ptr);
10221 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis,
10222 SPARC_BUILTIN_EDGE32, di_ftype_ptr_ptr);
10223 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis,
10224 SPARC_BUILTIN_EDGE32L, di_ftype_ptr_ptr);
10228 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis,
10229 SPARC_BUILTIN_EDGE8, si_ftype_ptr_ptr);
10230 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis,
10231 SPARC_BUILTIN_EDGE8L, si_ftype_ptr_ptr);
10232 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis,
10233 SPARC_BUILTIN_EDGE16, si_ftype_ptr_ptr);
10234 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis,
10235 SPARC_BUILTIN_EDGE16L, si_ftype_ptr_ptr);
10236 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis,
10237 SPARC_BUILTIN_EDGE32, si_ftype_ptr_ptr);
10238 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis,
10239 SPARC_BUILTIN_EDGE32L, si_ftype_ptr_ptr);
10242 /* Pixel compare. */
10245 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis,
10246 SPARC_BUILTIN_FCMPLE16, di_ftype_v4hi_v4hi);
10247 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis,
10248 SPARC_BUILTIN_FCMPLE32, di_ftype_v2si_v2si);
10249 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis,
10250 SPARC_BUILTIN_FCMPNE16, di_ftype_v4hi_v4hi);
10251 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis,
10252 SPARC_BUILTIN_FCMPNE32, di_ftype_v2si_v2si);
10253 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis,
10254 SPARC_BUILTIN_FCMPGT16, di_ftype_v4hi_v4hi);
10255 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis,
10256 SPARC_BUILTIN_FCMPGT32, di_ftype_v2si_v2si);
10257 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis,
10258 SPARC_BUILTIN_FCMPEQ16, di_ftype_v4hi_v4hi);
10259 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis,
10260 SPARC_BUILTIN_FCMPEQ32, di_ftype_v2si_v2si);
10264 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis,
10265 SPARC_BUILTIN_FCMPLE16, si_ftype_v4hi_v4hi);
10266 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis,
10267 SPARC_BUILTIN_FCMPLE32, si_ftype_v2si_v2si);
10268 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis,
10269 SPARC_BUILTIN_FCMPNE16, si_ftype_v4hi_v4hi);
10270 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis,
10271 SPARC_BUILTIN_FCMPNE32, si_ftype_v2si_v2si);
10272 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis,
10273 SPARC_BUILTIN_FCMPGT16, si_ftype_v4hi_v4hi);
10274 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis,
10275 SPARC_BUILTIN_FCMPGT32, si_ftype_v2si_v2si);
10276 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis,
10277 SPARC_BUILTIN_FCMPEQ16, si_ftype_v4hi_v4hi);
10278 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis,
10279 SPARC_BUILTIN_FCMPEQ32, si_ftype_v2si_v2si);
10282 /* Addition and subtraction. */
10283 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3,
10284 SPARC_BUILTIN_FPADD16, v4hi_ftype_v4hi_v4hi);
10285 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3,
10286 SPARC_BUILTIN_FPADD16S, v2hi_ftype_v2hi_v2hi);
10287 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3,
10288 SPARC_BUILTIN_FPADD32, v2si_ftype_v2si_v2si);
10289 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3,
10290 SPARC_BUILTIN_FPADD32S, v1si_ftype_v1si_v1si);
10291 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3,
10292 SPARC_BUILTIN_FPSUB16, v4hi_ftype_v4hi_v4hi);
10293 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3,
10294 SPARC_BUILTIN_FPSUB16S, v2hi_ftype_v2hi_v2hi);
10295 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3,
10296 SPARC_BUILTIN_FPSUB32, v2si_ftype_v2si_v2si);
10297 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3,
10298 SPARC_BUILTIN_FPSUB32S, v1si_ftype_v1si_v1si);
10300 /* Three-dimensional array addressing. */
10303 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis,
10304 SPARC_BUILTIN_ARRAY8, di_ftype_di_di);
10305 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis,
10306 SPARC_BUILTIN_ARRAY16, di_ftype_di_di);
10307 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis,
10308 SPARC_BUILTIN_ARRAY32, di_ftype_di_di);
10312 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis,
10313 SPARC_BUILTIN_ARRAY8, si_ftype_si_si);
10314 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis,
10315 SPARC_BUILTIN_ARRAY16, si_ftype_si_si);
10316 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis,
10317 SPARC_BUILTIN_ARRAY32, si_ftype_si_si);
10322 /* Edge handling. */
10325 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis,
10326 SPARC_BUILTIN_EDGE8N, di_ftype_ptr_ptr);
10327 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis,
10328 SPARC_BUILTIN_EDGE8LN, di_ftype_ptr_ptr);
10329 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis,
10330 SPARC_BUILTIN_EDGE16N, di_ftype_ptr_ptr);
10331 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis,
10332 SPARC_BUILTIN_EDGE16LN, di_ftype_ptr_ptr);
10333 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis,
10334 SPARC_BUILTIN_EDGE32N, di_ftype_ptr_ptr);
10335 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis,
10336 SPARC_BUILTIN_EDGE32LN, di_ftype_ptr_ptr);
10340 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis,
10341 SPARC_BUILTIN_EDGE8N, si_ftype_ptr_ptr);
10342 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis,
10343 SPARC_BUILTIN_EDGE8LN, si_ftype_ptr_ptr);
10344 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis,
10345 SPARC_BUILTIN_EDGE16N, si_ftype_ptr_ptr);
10346 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis,
10347 SPARC_BUILTIN_EDGE16LN, si_ftype_ptr_ptr);
10348 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis,
10349 SPARC_BUILTIN_EDGE32N, si_ftype_ptr_ptr);
10350 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis,
10351 SPARC_BUILTIN_EDGE32LN, si_ftype_ptr_ptr);
10354 /* Byte mask and shuffle. */
10356 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis,
10357 SPARC_BUILTIN_BMASK, di_ftype_di_di);
10359 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis,
10360 SPARC_BUILTIN_BMASK, si_ftype_si_si);
10361 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis,
10362 SPARC_BUILTIN_BSHUFFLEV4HI, v4hi_ftype_v4hi_v4hi);
10363 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis,
10364 SPARC_BUILTIN_BSHUFFLEV8QI, v8qi_ftype_v8qi_v8qi);
10365 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis,
10366 SPARC_BUILTIN_BSHUFFLEV2SI, v2si_ftype_v2si_v2si);
10367 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis,
10368 SPARC_BUILTIN_BSHUFFLEDI, di_ftype_di_di);
10375 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis,
10376 SPARC_BUILTIN_CMASK8, void_ftype_di);
10377 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis,
10378 SPARC_BUILTIN_CMASK16, void_ftype_di);
10379 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis,
10380 SPARC_BUILTIN_CMASK32, void_ftype_di);
10384 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis,
10385 SPARC_BUILTIN_CMASK8, void_ftype_si);
10386 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis,
10387 SPARC_BUILTIN_CMASK16, void_ftype_si);
10388 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis,
10389 SPARC_BUILTIN_CMASK32, void_ftype_si);
10392 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis,
10393 SPARC_BUILTIN_FCHKSM16, v4hi_ftype_v4hi_v4hi);
10395 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3,
10396 SPARC_BUILTIN_FSLL16, v4hi_ftype_v4hi_v4hi);
10397 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3,
10398 SPARC_BUILTIN_FSLAS16, v4hi_ftype_v4hi_v4hi);
10399 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3,
10400 SPARC_BUILTIN_FSRL16, v4hi_ftype_v4hi_v4hi);
10401 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3,
10402 SPARC_BUILTIN_FSRA16, v4hi_ftype_v4hi_v4hi);
10403 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3,
10404 SPARC_BUILTIN_FSLL32, v2si_ftype_v2si_v2si);
10405 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3,
10406 SPARC_BUILTIN_FSLAS32, v2si_ftype_v2si_v2si);
10407 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3,
10408 SPARC_BUILTIN_FSRL32, v2si_ftype_v2si_v2si);
10409 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3,
10410 SPARC_BUILTIN_FSRA32, v2si_ftype_v2si_v2si);
10413 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis,
10414 SPARC_BUILTIN_PDISTN, di_ftype_v8qi_v8qi);
10416 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis,
10417 SPARC_BUILTIN_PDISTN, si_ftype_v8qi_v8qi);
10419 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis,
10420 SPARC_BUILTIN_FMEAN16, v4hi_ftype_v4hi_v4hi);
10421 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis,
10422 SPARC_BUILTIN_FPADD64, di_ftype_di_di);
10423 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis,
10424 SPARC_BUILTIN_FPSUB64, di_ftype_di_di);
10426 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3,
10427 SPARC_BUILTIN_FPADDS16, v4hi_ftype_v4hi_v4hi);
10428 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3,
10429 SPARC_BUILTIN_FPADDS16S, v2hi_ftype_v2hi_v2hi);
10430 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3,
10431 SPARC_BUILTIN_FPSUBS16, v4hi_ftype_v4hi_v4hi);
10432 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3,
10433 SPARC_BUILTIN_FPSUBS16S, v2hi_ftype_v2hi_v2hi);
10434 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3,
10435 SPARC_BUILTIN_FPADDS32, v2si_ftype_v2si_v2si);
10436 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3,
10437 SPARC_BUILTIN_FPADDS32S, v1si_ftype_v1si_v1si);
10438 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3,
10439 SPARC_BUILTIN_FPSUBS32, v2si_ftype_v2si_v2si);
10440 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3,
10441 SPARC_BUILTIN_FPSUBS32S, v1si_ftype_v1si_v1si);
10445 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis,
10446 SPARC_BUILTIN_FUCMPLE8, di_ftype_v8qi_v8qi);
10447 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis,
10448 SPARC_BUILTIN_FUCMPNE8, di_ftype_v8qi_v8qi);
10449 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis,
10450 SPARC_BUILTIN_FUCMPGT8, di_ftype_v8qi_v8qi);
10451 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis,
10452 SPARC_BUILTIN_FUCMPEQ8, di_ftype_v8qi_v8qi);
10456 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis,
10457 SPARC_BUILTIN_FUCMPLE8, si_ftype_v8qi_v8qi);
10458 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis,
10459 SPARC_BUILTIN_FUCMPNE8, si_ftype_v8qi_v8qi);
10460 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis,
10461 SPARC_BUILTIN_FUCMPGT8, si_ftype_v8qi_v8qi);
10462 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis,
10463 SPARC_BUILTIN_FUCMPEQ8, si_ftype_v8qi_v8qi);
10466 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
10467 SPARC_BUILTIN_FHADDS, sf_ftype_sf_sf);
10468 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
10469 SPARC_BUILTIN_FHADDD, df_ftype_df_df);
10470 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
10471 SPARC_BUILTIN_FHSUBS, sf_ftype_sf_sf);
10472 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
10473 SPARC_BUILTIN_FHSUBD, df_ftype_df_df);
10474 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
10475 SPARC_BUILTIN_FNHADDS, sf_ftype_sf_sf);
10476 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
10477 SPARC_BUILTIN_FNHADDD, df_ftype_df_df);
10479 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
10480 SPARC_BUILTIN_UMULXHI, di_ftype_di_di);
10481 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
10482 SPARC_BUILTIN_XMULX, di_ftype_di_di);
10483 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
10484 SPARC_BUILTIN_XMULXHI, di_ftype_di_di);
10488 /* Implement TARGET_BUILTIN_DECL hook. */
10491 sparc_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10493 if (code >= SPARC_BUILTIN_MAX)
10494 return error_mark_node;
10496 return sparc_builtins[code];
10499 /* Implemented TARGET_EXPAND_BUILTIN hook. */
10502 sparc_expand_builtin (tree exp, rtx target,
10503 rtx subtarget ATTRIBUTE_UNUSED,
10504 machine_mode tmode ATTRIBUTE_UNUSED,
10505 int ignore ATTRIBUTE_UNUSED)
10507 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10508 enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl);
10509 enum insn_code icode = sparc_builtins_icode[code];
10510 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10511 call_expr_arg_iterator iter;
10518 machine_mode tmode = insn_data[icode].operand[0].mode;
10520 || GET_MODE (target) != tmode
10521 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10522 op[0] = gen_reg_rtx (tmode);
10527 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10529 const struct insn_operand_data *insn_op;
10532 if (arg == error_mark_node)
10536 idx = arg_count - !nonvoid;
10537 insn_op = &insn_data[icode].operand[idx];
10538 op[arg_count] = expand_normal (arg);
10540 if (code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR)
10542 if (!address_operand (op[arg_count], SImode))
10544 op[arg_count] = convert_memory_address (Pmode, op[arg_count]);
10545 op[arg_count] = copy_addr_to_reg (op[arg_count]);
10547 op[arg_count] = gen_rtx_MEM (SImode, op[arg_count]);
10550 else if (insn_op->mode == V1DImode
10551 && GET_MODE (op[arg_count]) == DImode)
10552 op[arg_count] = gen_lowpart (V1DImode, op[arg_count]);
10554 else if (insn_op->mode == V1SImode
10555 && GET_MODE (op[arg_count]) == SImode)
10556 op[arg_count] = gen_lowpart (V1SImode, op[arg_count]);
10558 if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count],
10560 op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]);
10566 pat = GEN_FCN (icode) (op[0]);
10570 pat = GEN_FCN (icode) (op[0], op[1]);
10572 pat = GEN_FCN (icode) (op[1]);
10575 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
10578 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
10581 gcc_unreachable ();
10589 return (nonvoid ? op[0] : const0_rtx);
10592 /* Return the upper 16 bits of the 8x16 multiplication. */
10595 sparc_vis_mul8x16 (int e8, int e16)
10597 return (e8 * e16 + 128) / 256;
10600 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10601 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10604 sparc_handle_vis_mul8x16 (tree *n_elts, enum sparc_builtins fncode,
10605 tree inner_type, tree cst0, tree cst1)
10607 unsigned i, num = VECTOR_CST_NELTS (cst0);
10612 case SPARC_BUILTIN_FMUL8X16:
10613 for (i = 0; i < num; ++i)
10616 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)),
10617 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, i)));
10618 n_elts[i] = build_int_cst (inner_type, val);
10622 case SPARC_BUILTIN_FMUL8X16AU:
10623 scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 0));
10625 for (i = 0; i < num; ++i)
10628 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)),
10630 n_elts[i] = build_int_cst (inner_type, val);
10634 case SPARC_BUILTIN_FMUL8X16AL:
10635 scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 1));
10637 for (i = 0; i < num; ++i)
10640 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)),
10642 n_elts[i] = build_int_cst (inner_type, val);
10647 gcc_unreachable ();
10651 /* Implement TARGET_FOLD_BUILTIN hook.
10653 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10654 result of the function call is ignored. NULL_TREE is returned if the
10655 function could not be folded. */
10658 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
10659 tree *args, bool ignore)
10661 enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl);
10662 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
10663 tree arg0, arg1, arg2;
10668 case SPARC_BUILTIN_LDFSR:
10669 case SPARC_BUILTIN_STFSR:
10670 case SPARC_BUILTIN_ALIGNADDR:
10671 case SPARC_BUILTIN_WRGSR:
10672 case SPARC_BUILTIN_BMASK:
10673 case SPARC_BUILTIN_CMASK8:
10674 case SPARC_BUILTIN_CMASK16:
10675 case SPARC_BUILTIN_CMASK32:
10679 return build_zero_cst (rtype);
10684 case SPARC_BUILTIN_FEXPAND:
10688 if (TREE_CODE (arg0) == VECTOR_CST)
10690 tree inner_type = TREE_TYPE (rtype);
10694 n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0));
10695 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i)
10696 n_elts[i] = build_int_cst (inner_type,
10698 (VECTOR_CST_ELT (arg0, i)) << 4);
10699 return build_vector (rtype, n_elts);
10703 case SPARC_BUILTIN_FMUL8X16:
10704 case SPARC_BUILTIN_FMUL8X16AU:
10705 case SPARC_BUILTIN_FMUL8X16AL:
10711 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
10713 tree inner_type = TREE_TYPE (rtype);
10714 tree *n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0));
10715 sparc_handle_vis_mul8x16 (n_elts, code, inner_type, arg0, arg1);
10716 return build_vector (rtype, n_elts);
10720 case SPARC_BUILTIN_FPMERGE:
10726 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
10728 tree *n_elts = XALLOCAVEC (tree, 2 * VECTOR_CST_NELTS (arg0));
10730 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i)
10732 n_elts[2*i] = VECTOR_CST_ELT (arg0, i);
10733 n_elts[2*i+1] = VECTOR_CST_ELT (arg1, i);
10736 return build_vector (rtype, n_elts);
10740 case SPARC_BUILTIN_PDIST:
10741 case SPARC_BUILTIN_PDISTN:
10746 if (code == SPARC_BUILTIN_PDIST)
10752 arg2 = integer_zero_node;
10754 if (TREE_CODE (arg0) == VECTOR_CST
10755 && TREE_CODE (arg1) == VECTOR_CST
10756 && TREE_CODE (arg2) == INTEGER_CST)
10758 bool overflow = false;
10759 widest_int result = wi::to_widest (arg2);
10763 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i)
10765 tree e0 = VECTOR_CST_ELT (arg0, i);
10766 tree e1 = VECTOR_CST_ELT (arg1, i);
10768 bool neg1_ovf, neg2_ovf, add1_ovf, add2_ovf;
10770 tmp = wi::neg (wi::to_widest (e1), &neg1_ovf);
10771 tmp = wi::add (wi::to_widest (e0), tmp, SIGNED, &add1_ovf);
10772 if (wi::neg_p (tmp))
10773 tmp = wi::neg (tmp, &neg2_ovf);
10776 result = wi::add (result, tmp, SIGNED, &add2_ovf);
10777 overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf;
10780 gcc_assert (!overflow);
10782 return wide_int_to_tree (rtype, result);
10792 /* ??? This duplicates information provided to the compiler by the
10793 ??? scheduler description. Some day, teach genautomata to output
10794 ??? the latencies and then CSE will just use that. */
10797 sparc_rtx_costs (rtx x, machine_mode mode, int outer_code,
10798 int opno ATTRIBUTE_UNUSED,
10799 int *total, bool speed ATTRIBUTE_UNUSED)
10801 int code = GET_CODE (x);
10802 bool float_mode_p = FLOAT_MODE_P (mode);
10813 case CONST_WIDE_INT:
10815 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x, 0)))
10817 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x, 1)))
10836 /* If outer-code was a sign or zero extension, a cost
10837 of COSTS_N_INSNS (1) was already added in. This is
10838 why we are subtracting it back out. */
10839 if (outer_code == ZERO_EXTEND)
10841 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
10843 else if (outer_code == SIGN_EXTEND)
10845 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
10847 else if (float_mode_p)
10849 *total = sparc_costs->float_load;
10853 *total = sparc_costs->int_load;
10861 *total = sparc_costs->float_plusminus;
10863 *total = COSTS_N_INSNS (1);
10870 gcc_assert (float_mode_p);
10871 *total = sparc_costs->float_mul;
10874 if (GET_CODE (sub) == NEG)
10875 sub = XEXP (sub, 0);
10876 *total += rtx_cost (sub, mode, FMA, 0, speed);
10879 if (GET_CODE (sub) == NEG)
10880 sub = XEXP (sub, 0);
10881 *total += rtx_cost (sub, mode, FMA, 2, speed);
10887 *total = sparc_costs->float_mul;
10888 else if (TARGET_ARCH32 && !TARGET_HARD_MUL)
10889 *total = COSTS_N_INSNS (25);
10895 if (sparc_costs->int_mul_bit_factor)
10899 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
10901 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
10902 for (nbits = 0; value != 0; value &= value - 1)
10910 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
10911 bit_cost = COSTS_N_INSNS (bit_cost);
10914 if (mode == DImode || !TARGET_HARD_MUL)
10915 *total = sparc_costs->int_mulX + bit_cost;
10917 *total = sparc_costs->int_mul + bit_cost;
10924 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
10933 if (mode == DFmode)
10934 *total = sparc_costs->float_div_df;
10936 *total = sparc_costs->float_div_sf;
10940 if (mode == DImode)
10941 *total = sparc_costs->int_divX;
10943 *total = sparc_costs->int_div;
10948 if (! float_mode_p)
10950 *total = COSTS_N_INSNS (1);
10957 case UNSIGNED_FLOAT:
10961 case FLOAT_TRUNCATE:
10962 *total = sparc_costs->float_move;
10966 if (mode == DFmode)
10967 *total = sparc_costs->float_sqrt_df;
10969 *total = sparc_costs->float_sqrt_sf;
10974 *total = sparc_costs->float_cmp;
10976 *total = COSTS_N_INSNS (1);
10981 *total = sparc_costs->float_cmove;
10983 *total = sparc_costs->int_cmove;
10987 /* Handle the NAND vector patterns. */
10988 if (sparc_vector_mode_supported_p (mode)
10989 && GET_CODE (XEXP (x, 0)) == NOT
10990 && GET_CODE (XEXP (x, 1)) == NOT)
10992 *total = COSTS_N_INSNS (1);
11003 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11006 general_or_i64_p (reg_class_t rclass)
11008 return (rclass == GENERAL_REGS || rclass == I64_REGS);
11011 /* Implement TARGET_REGISTER_MOVE_COST. */
11014 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
11015 reg_class_t from, reg_class_t to)
11017 bool need_memory = false;
11019 if (from == FPCC_REGS || to == FPCC_REGS)
11020 need_memory = true;
11021 else if ((FP_REG_CLASS_P (from) && general_or_i64_p (to))
11022 || (general_or_i64_p (from) && FP_REG_CLASS_P (to)))
11026 int size = GET_MODE_SIZE (mode);
11027 if (size == 8 || size == 4)
11029 if (! TARGET_ARCH32 || size == 4)
11035 need_memory = true;
11040 if (sparc_cpu == PROCESSOR_ULTRASPARC
11041 || sparc_cpu == PROCESSOR_ULTRASPARC3
11042 || sparc_cpu == PROCESSOR_NIAGARA
11043 || sparc_cpu == PROCESSOR_NIAGARA2
11044 || sparc_cpu == PROCESSOR_NIAGARA3
11045 || sparc_cpu == PROCESSOR_NIAGARA4)
11054 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11055 This is achieved by means of a manual dynamic stack space allocation in
11056 the current frame. We make the assumption that SEQ doesn't contain any
11057 function calls, with the possible exception of calls to the GOT helper. */
11060 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
11062 /* We must preserve the lowest 16 words for the register save area. */
11063 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
11064 /* We really need only 2 words of fresh stack space. */
11065 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
11068 = gen_rtx_MEM (word_mode, plus_constant (Pmode, stack_pointer_rtx,
11069 SPARC_STACK_BIAS + offset));
11071 emit_insn (gen_stack_pointer_inc (GEN_INT (-size)));
11072 emit_insn (gen_rtx_SET (slot, reg));
11074 emit_insn (gen_rtx_SET (adjust_address (slot, word_mode, UNITS_PER_WORD),
11078 emit_insn (gen_rtx_SET (reg2,
11079 adjust_address (slot, word_mode, UNITS_PER_WORD)));
11080 emit_insn (gen_rtx_SET (reg, slot));
11081 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
11084 /* Output the assembler code for a thunk function. THUNK_DECL is the
11085 declaration for the thunk function itself, FUNCTION is the decl for
11086 the target function. DELTA is an immediate constant offset to be
11087 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11088 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11091 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11092 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11095 rtx this_rtx, funexp;
11097 unsigned int int_arg_first;
11099 reload_completed = 1;
11100 epilogue_completed = 1;
11102 emit_note (NOTE_INSN_PROLOGUE_END);
11106 sparc_leaf_function_p = 1;
11108 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
11110 else if (flag_delayed_branch)
11112 /* We will emit a regular sibcall below, so we need to instruct
11113 output_sibcall that we are in a leaf function. */
11114 sparc_leaf_function_p = crtl->uses_only_leaf_regs = 1;
11116 /* This will cause final.c to invoke leaf_renumber_regs so we
11117 must behave as if we were in a not-yet-leafified function. */
11118 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
11122 /* We will emit the sibcall manually below, so we will need to
11123 manually spill non-leaf registers. */
11124 sparc_leaf_function_p = crtl->uses_only_leaf_regs = 0;
11126 /* We really are in a leaf function. */
11127 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
11130 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11131 returns a structure, the structure return pointer is there instead. */
11133 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11134 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
11136 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
11138 /* Add DELTA. When possible use a plain add, otherwise load it into
11139 a register first. */
11142 rtx delta_rtx = GEN_INT (delta);
11144 if (! SPARC_SIMM13_P (delta))
11146 rtx scratch = gen_rtx_REG (Pmode, 1);
11147 emit_move_insn (scratch, delta_rtx);
11148 delta_rtx = scratch;
11151 /* THIS_RTX += DELTA. */
11152 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
11155 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11158 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
11159 rtx scratch = gen_rtx_REG (Pmode, 1);
11161 gcc_assert (vcall_offset < 0);
11163 /* SCRATCH = *THIS_RTX. */
11164 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
11166 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11167 may not have any available scratch register at this point. */
11168 if (SPARC_SIMM13_P (vcall_offset))
11170 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11171 else if (! fixed_regs[5]
11172 /* The below sequence is made up of at least 2 insns,
11173 while the default method may need only one. */
11174 && vcall_offset < -8192)
11176 rtx scratch2 = gen_rtx_REG (Pmode, 5);
11177 emit_move_insn (scratch2, vcall_offset_rtx);
11178 vcall_offset_rtx = scratch2;
11182 rtx increment = GEN_INT (-4096);
11184 /* VCALL_OFFSET is a negative number whose typical range can be
11185 estimated as -32768..0 in 32-bit mode. In almost all cases
11186 it is therefore cheaper to emit multiple add insns than
11187 spilling and loading the constant into a register (at least
11189 while (! SPARC_SIMM13_P (vcall_offset))
11191 emit_insn (gen_add2_insn (scratch, increment));
11192 vcall_offset += 4096;
11194 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
11197 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11198 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
11199 gen_rtx_PLUS (Pmode,
11201 vcall_offset_rtx)));
11203 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11204 emit_insn (gen_add2_insn (this_rtx, scratch));
11207 /* Generate a tail call to the target function. */
11208 if (! TREE_USED (function))
11210 assemble_external (function);
11211 TREE_USED (function) = 1;
11213 funexp = XEXP (DECL_RTL (function), 0);
11215 if (flag_delayed_branch)
11217 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
11218 insn = emit_call_insn (gen_sibcall (funexp));
11219 SIBLING_CALL_P (insn) = 1;
11223 /* The hoops we have to jump through in order to generate a sibcall
11224 without using delay slots... */
11225 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
11229 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
11231 load_got_register (); /* clobbers %o7 */
11232 scratch = sparc_legitimize_pic_address (funexp, scratch);
11233 seq = get_insns ();
11235 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
11237 else if (TARGET_ARCH32)
11239 emit_insn (gen_rtx_SET (scratch,
11240 gen_rtx_HIGH (SImode, funexp)));
11241 emit_insn (gen_rtx_SET (scratch,
11242 gen_rtx_LO_SUM (SImode, scratch, funexp)));
11244 else /* TARGET_ARCH64 */
11246 switch (sparc_cmodel)
11250 /* The destination can serve as a temporary. */
11251 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
11256 /* The destination cannot serve as a temporary. */
11257 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
11259 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
11260 seq = get_insns ();
11262 emit_and_preserve (seq, spill_reg, 0);
11266 gcc_unreachable ();
11270 emit_jump_insn (gen_indirect_jump (scratch));
11275 /* Run just enough of rest_of_compilation to get the insns emitted.
11276 There's not really enough bulk here to make other passes such as
11277 instruction scheduling worth while. Note that use_thunk calls
11278 assemble_start_function and assemble_end_function. */
11279 insn = get_insns ();
11280 shorten_branches (insn);
11281 final_start_function (insn, file, 1);
11282 final (insn, file, 1);
11283 final_end_function ();
11285 reload_completed = 0;
11286 epilogue_completed = 0;
11289 /* Return true if sparc_output_mi_thunk would be able to output the
11290 assembler code for the thunk function specified by the arguments
11291 it is passed, and false otherwise. */
11293 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
11294 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
11295 HOST_WIDE_INT vcall_offset,
11296 const_tree function ATTRIBUTE_UNUSED)
11298 /* Bound the loop used in the default method above. */
11299 return (vcall_offset >= -32768 || ! fixed_regs[5]);
11302 /* How to allocate a 'struct machine_function'. */
11304 static struct machine_function *
11305 sparc_init_machine_status (void)
11307 return ggc_cleared_alloc<machine_function> ();
11310 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11311 We need to emit DTP-relative relocations. */
11314 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
11319 fputs ("\t.word\t%r_tls_dtpoff32(", file);
11322 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
11325 gcc_unreachable ();
11327 output_addr_const (file, x);
11331 /* Do whatever processing is required at the end of a file. */
11334 sparc_file_end (void)
11336 /* If we need to emit the special GOT helper function, do so now. */
11337 if (got_helper_rtx)
11339 const char *name = XSTR (got_helper_rtx, 0);
11340 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
11341 #ifdef DWARF2_UNWIND_INFO
11345 if (USE_HIDDEN_LINKONCE)
11347 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
11348 get_identifier (name),
11349 build_function_type_list (void_type_node,
11351 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
11352 NULL_TREE, void_type_node);
11353 TREE_PUBLIC (decl) = 1;
11354 TREE_STATIC (decl) = 1;
11355 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
11356 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
11357 DECL_VISIBILITY_SPECIFIED (decl) = 1;
11358 resolve_unique_section (decl, 0, flag_function_sections);
11359 allocate_struct_function (decl, true);
11360 cfun->is_thunk = 1;
11361 current_function_decl = decl;
11362 init_varasm_status ();
11363 assemble_start_function (decl, name);
11367 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
11368 switch_to_section (text_section);
11370 ASM_OUTPUT_ALIGN (asm_out_file, align);
11371 ASM_OUTPUT_LABEL (asm_out_file, name);
11374 #ifdef DWARF2_UNWIND_INFO
11375 do_cfi = dwarf2out_do_cfi_asm ();
11377 fprintf (asm_out_file, "\t.cfi_startproc\n");
11379 if (flag_delayed_branch)
11380 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11381 reg_name, reg_name);
11383 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11384 reg_name, reg_name);
11385 #ifdef DWARF2_UNWIND_INFO
11387 fprintf (asm_out_file, "\t.cfi_endproc\n");
11391 if (NEED_INDICATE_EXEC_STACK)
11392 file_end_indicate_exec_stack ();
11394 #ifdef TARGET_SOLARIS
11395 solaris_file_end ();
11399 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11400 /* Implement TARGET_MANGLE_TYPE. */
11402 static const char *
11403 sparc_mangle_type (const_tree type)
11406 && TYPE_MAIN_VARIANT (type) == long_double_type_node
11407 && TARGET_LONG_DOUBLE_128)
11410 /* For all other types, use normal C++ mangling. */
11415 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11416 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11417 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11420 sparc_emit_membar_for_model (enum memmodel model,
11421 int load_store, int before_after)
11423 /* Bits for the MEMBAR mmask field. */
11424 const int LoadLoad = 1;
11425 const int StoreLoad = 2;
11426 const int LoadStore = 4;
11427 const int StoreStore = 8;
11429 int mm = 0, implied = 0;
11431 switch (sparc_memory_model)
11434 /* Sequential Consistency. All memory transactions are immediately
11435 visible in sequential execution order. No barriers needed. */
11436 implied = LoadLoad | StoreLoad | LoadStore | StoreStore;
11440 /* Total Store Ordering: all memory transactions with store semantics
11441 are followed by an implied StoreStore. */
11442 implied |= StoreStore;
11444 /* If we're not looking for a raw barrer (before+after), then atomic
11445 operations get the benefit of being both load and store. */
11446 if (load_store == 3 && before_after == 1)
11447 implied |= StoreLoad;
11451 /* Partial Store Ordering: all memory transactions with load semantics
11452 are followed by an implied LoadLoad | LoadStore. */
11453 implied |= LoadLoad | LoadStore;
11455 /* If we're not looking for a raw barrer (before+after), then atomic
11456 operations get the benefit of being both load and store. */
11457 if (load_store == 3 && before_after == 2)
11458 implied |= StoreLoad | StoreStore;
11462 /* Relaxed Memory Ordering: no implicit bits. */
11466 gcc_unreachable ();
11469 if (before_after & 1)
11471 if (is_mm_release (model) || is_mm_acq_rel (model)
11472 || is_mm_seq_cst (model))
11474 if (load_store & 1)
11475 mm |= LoadLoad | StoreLoad;
11476 if (load_store & 2)
11477 mm |= LoadStore | StoreStore;
11480 if (before_after & 2)
11482 if (is_mm_acquire (model) || is_mm_acq_rel (model)
11483 || is_mm_seq_cst (model))
11485 if (load_store & 1)
11486 mm |= LoadLoad | LoadStore;
11487 if (load_store & 2)
11488 mm |= StoreLoad | StoreStore;
11492 /* Remove the bits implied by the system memory model. */
11495 /* For raw barriers (before+after), always emit a barrier.
11496 This will become a compile-time barrier if needed. */
11497 if (mm || before_after == 3)
11498 emit_insn (gen_membar (GEN_INT (mm)));
11501 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11502 compare and swap on the word containing the byte or half-word. */
11505 sparc_expand_compare_and_swap_12 (rtx bool_result, rtx result, rtx mem,
11506 rtx oldval, rtx newval)
11508 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
11509 rtx addr = gen_reg_rtx (Pmode);
11510 rtx off = gen_reg_rtx (SImode);
11511 rtx oldv = gen_reg_rtx (SImode);
11512 rtx newv = gen_reg_rtx (SImode);
11513 rtx oldvalue = gen_reg_rtx (SImode);
11514 rtx newvalue = gen_reg_rtx (SImode);
11515 rtx res = gen_reg_rtx (SImode);
11516 rtx resv = gen_reg_rtx (SImode);
11517 rtx memsi, val, mask, cc;
11519 emit_insn (gen_rtx_SET (addr, gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
11521 if (Pmode != SImode)
11522 addr1 = gen_lowpart (SImode, addr1);
11523 emit_insn (gen_rtx_SET (off, gen_rtx_AND (SImode, addr1, GEN_INT (3))));
11525 memsi = gen_rtx_MEM (SImode, addr);
11526 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
11527 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
11529 val = copy_to_reg (memsi);
11531 emit_insn (gen_rtx_SET (off,
11532 gen_rtx_XOR (SImode, off,
11533 GEN_INT (GET_MODE (mem) == QImode
11536 emit_insn (gen_rtx_SET (off, gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
11538 if (GET_MODE (mem) == QImode)
11539 mask = force_reg (SImode, GEN_INT (0xff));
11541 mask = force_reg (SImode, GEN_INT (0xffff));
11543 emit_insn (gen_rtx_SET (mask, gen_rtx_ASHIFT (SImode, mask, off)));
11545 emit_insn (gen_rtx_SET (val,
11546 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
11549 oldval = gen_lowpart (SImode, oldval);
11550 emit_insn (gen_rtx_SET (oldv, gen_rtx_ASHIFT (SImode, oldval, off)));
11552 newval = gen_lowpart_common (SImode, newval);
11553 emit_insn (gen_rtx_SET (newv, gen_rtx_ASHIFT (SImode, newval, off)));
11555 emit_insn (gen_rtx_SET (oldv, gen_rtx_AND (SImode, oldv, mask)));
11557 emit_insn (gen_rtx_SET (newv, gen_rtx_AND (SImode, newv, mask)));
11559 rtx_code_label *end_label = gen_label_rtx ();
11560 rtx_code_label *loop_label = gen_label_rtx ();
11561 emit_label (loop_label);
11563 emit_insn (gen_rtx_SET (oldvalue, gen_rtx_IOR (SImode, oldv, val)));
11565 emit_insn (gen_rtx_SET (newvalue, gen_rtx_IOR (SImode, newv, val)));
11567 emit_move_insn (bool_result, const1_rtx);
11569 emit_insn (gen_atomic_compare_and_swapsi_1 (res, memsi, oldvalue, newvalue));
11571 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
11573 emit_insn (gen_rtx_SET (resv,
11574 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
11577 emit_move_insn (bool_result, const0_rtx);
11579 cc = gen_compare_reg_1 (NE, resv, val);
11580 emit_insn (gen_rtx_SET (val, resv));
11582 /* Use cbranchcc4 to separate the compare and branch! */
11583 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
11584 cc, const0_rtx, loop_label));
11586 emit_label (end_label);
11588 emit_insn (gen_rtx_SET (res, gen_rtx_AND (SImode, res, mask)));
11590 emit_insn (gen_rtx_SET (res, gen_rtx_LSHIFTRT (SImode, res, off)));
11592 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
11595 /* Expand code to perform a compare-and-swap. */
11598 sparc_expand_compare_and_swap (rtx operands[])
11600 rtx bval, retval, mem, oldval, newval;
11602 enum memmodel model;
11604 bval = operands[0];
11605 retval = operands[1];
11607 oldval = operands[3];
11608 newval = operands[4];
11609 model = (enum memmodel) INTVAL (operands[6]);
11610 mode = GET_MODE (mem);
11612 sparc_emit_membar_for_model (model, 3, 1);
11614 if (reg_overlap_mentioned_p (retval, oldval))
11615 oldval = copy_to_reg (oldval);
11617 if (mode == QImode || mode == HImode)
11618 sparc_expand_compare_and_swap_12 (bval, retval, mem, oldval, newval);
11621 rtx (*gen) (rtx, rtx, rtx, rtx);
11624 if (mode == SImode)
11625 gen = gen_atomic_compare_and_swapsi_1;
11627 gen = gen_atomic_compare_and_swapdi_1;
11628 emit_insn (gen (retval, mem, oldval, newval));
11630 x = emit_store_flag (bval, EQ, retval, oldval, mode, 1, 1);
11632 convert_move (bval, x, 1);
11635 sparc_emit_membar_for_model (model, 3, 2);
11639 sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel)
11643 sel = gen_lowpart (DImode, sel);
11647 /* inp = xxxxxxxAxxxxxxxB */
11648 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11649 NULL_RTX, 1, OPTAB_DIRECT);
11650 /* t_1 = ....xxxxxxxAxxx. */
11651 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
11652 GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT);
11653 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
11654 GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT);
11655 /* sel = .......B */
11656 /* t_1 = ...A.... */
11657 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
11658 /* sel = ...A...B */
11659 sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1);
11660 /* sel = AAAABBBB * 4 */
11661 t_1 = force_reg (SImode, GEN_INT (0x01230123));
11662 /* sel = { A*4, A*4+1, A*4+2, ... } */
11666 /* inp = xxxAxxxBxxxCxxxD */
11667 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
11668 NULL_RTX, 1, OPTAB_DIRECT);
11669 t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11670 NULL_RTX, 1, OPTAB_DIRECT);
11671 t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24),
11672 NULL_RTX, 1, OPTAB_DIRECT);
11673 /* t_1 = ..xxxAxxxBxxxCxx */
11674 /* t_2 = ....xxxAxxxBxxxC */
11675 /* t_3 = ......xxxAxxxBxx */
11676 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
11678 NULL_RTX, 1, OPTAB_DIRECT);
11679 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
11681 NULL_RTX, 1, OPTAB_DIRECT);
11682 t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2),
11683 GEN_INT (0x070000),
11684 NULL_RTX, 1, OPTAB_DIRECT);
11685 t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3),
11686 GEN_INT (0x07000000),
11687 NULL_RTX, 1, OPTAB_DIRECT);
11688 /* sel = .......D */
11689 /* t_1 = .....C.. */
11690 /* t_2 = ...B.... */
11691 /* t_3 = .A...... */
11692 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
11693 t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT);
11694 sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT);
11695 /* sel = .A.B.C.D */
11696 sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1);
11697 /* sel = AABBCCDD * 2 */
11698 t_1 = force_reg (SImode, GEN_INT (0x01010101));
11699 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11703 /* input = xAxBxCxDxExFxGxH */
11704 sel = expand_simple_binop (DImode, AND, sel,
11705 GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32
11707 NULL_RTX, 1, OPTAB_DIRECT);
11708 /* sel = .A.B.C.D.E.F.G.H */
11709 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4),
11710 NULL_RTX, 1, OPTAB_DIRECT);
11711 /* t_1 = ..A.B.C.D.E.F.G. */
11712 sel = expand_simple_binop (DImode, IOR, sel, t_1,
11713 NULL_RTX, 1, OPTAB_DIRECT);
11714 /* sel = .AABBCCDDEEFFGGH */
11715 sel = expand_simple_binop (DImode, AND, sel,
11716 GEN_INT ((HOST_WIDE_INT)0xff00ff << 32
11718 NULL_RTX, 1, OPTAB_DIRECT);
11719 /* sel = ..AB..CD..EF..GH */
11720 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
11721 NULL_RTX, 1, OPTAB_DIRECT);
11722 /* t_1 = ....AB..CD..EF.. */
11723 sel = expand_simple_binop (DImode, IOR, sel, t_1,
11724 NULL_RTX, 1, OPTAB_DIRECT);
11725 /* sel = ..ABABCDCDEFEFGH */
11726 sel = expand_simple_binop (DImode, AND, sel,
11727 GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff),
11728 NULL_RTX, 1, OPTAB_DIRECT);
11729 /* sel = ....ABCD....EFGH */
11730 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11731 NULL_RTX, 1, OPTAB_DIRECT);
11732 /* t_1 = ........ABCD.... */
11733 sel = gen_lowpart (SImode, sel);
11734 t_1 = gen_lowpart (SImode, t_1);
11738 gcc_unreachable ();
11741 /* Always perform the final addition/merge within the bmask insn. */
11742 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1));
11745 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11748 sparc_frame_pointer_required (void)
11750 /* If the stack pointer is dynamically modified in the function, it cannot
11751 serve as the frame pointer. */
11752 if (cfun->calls_alloca)
11755 /* If the function receives nonlocal gotos, it needs to save the frame
11756 pointer in the nonlocal_goto_save_area object. */
11757 if (cfun->has_nonlocal_label)
11760 /* In flat mode, that's it. */
11764 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11765 return !(crtl->is_leaf && only_leaf_regs_used ());
11768 /* The way this is structured, we can't eliminate SFP in favor of SP
11769 if the frame pointer is required: we want to use the SFP->HFP elimination
11770 in that case. But the test in update_eliminables doesn't know we are
11771 assuming below that we only do the former elimination. */
11774 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
11776 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
11779 /* Return the hard frame pointer directly to bypass the stack bias. */
11782 sparc_builtin_setjmp_frame_value (void)
11784 return hard_frame_pointer_rtx;
11787 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
11788 they won't be allocated. */
11791 sparc_conditional_register_usage (void)
11793 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
11795 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11796 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11798 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
11799 /* then honor it. */
11800 if (TARGET_ARCH32 && fixed_regs[5])
11802 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
11807 for (regno = SPARC_FIRST_V9_FP_REG;
11808 regno <= SPARC_LAST_V9_FP_REG;
11810 fixed_regs[regno] = 1;
11811 /* %fcc0 is used by v8 and v9. */
11812 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
11813 regno <= SPARC_LAST_V9_FCC_REG;
11815 fixed_regs[regno] = 1;
11820 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
11821 fixed_regs[regno] = 1;
11823 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
11824 /* then honor it. Likewise with g3 and g4. */
11825 if (fixed_regs[2] == 2)
11826 fixed_regs[2] = ! TARGET_APP_REGS;
11827 if (fixed_regs[3] == 2)
11828 fixed_regs[3] = ! TARGET_APP_REGS;
11829 if (TARGET_ARCH32 && fixed_regs[4] == 2)
11830 fixed_regs[4] = ! TARGET_APP_REGS;
11831 else if (TARGET_CM_EMBMEDANY)
11833 else if (fixed_regs[4] == 2)
11838 /* Disable leaf functions. */
11839 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
11840 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
11841 leaf_reg_remap [regno] = regno;
11844 global_regs[SPARC_GSR_REG] = 1;
11847 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
11849 - We can't load constants into FP registers.
11850 - We can't load FP constants into integer registers when soft-float,
11851 because there is no soft-float pattern with a r/F constraint.
11852 - We can't load FP constants into integer registers for TFmode unless
11853 it is 0.0L, because there is no movtf pattern with a r/F constraint.
11854 - Try and reload integer constants (symbolic or otherwise) back into
11855 registers directly, rather than having them dumped to memory. */
11858 sparc_preferred_reload_class (rtx x, reg_class_t rclass)
11860 machine_mode mode = GET_MODE (x);
11861 if (CONSTANT_P (x))
11863 if (FP_REG_CLASS_P (rclass)
11864 || rclass == GENERAL_OR_FP_REGS
11865 || rclass == GENERAL_OR_EXTRA_FP_REGS
11866 || (GET_MODE_CLASS (mode) == MODE_FLOAT && ! TARGET_FPU)
11867 || (mode == TFmode && ! const_zero_operand (x, mode)))
11870 if (GET_MODE_CLASS (mode) == MODE_INT)
11871 return GENERAL_REGS;
11873 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
11875 if (! FP_REG_CLASS_P (rclass)
11876 || !(const_zero_operand (x, mode)
11877 || const_all_ones_operand (x, mode)))
11884 && (rclass == EXTRA_FP_REGS
11885 || rclass == GENERAL_OR_EXTRA_FP_REGS))
11887 int regno = true_regnum (x);
11889 if (SPARC_INT_REG_P (regno))
11890 return (rclass == EXTRA_FP_REGS
11891 ? FP_REGS : GENERAL_OR_FP_REGS);
11897 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
11898 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
11901 output_v8plus_mult (rtx_insn *insn, rtx *operands, const char *opcode)
11905 gcc_assert (! TARGET_ARCH64);
11907 if (sparc_check_64 (operands[1], insn) <= 0)
11908 output_asm_insn ("srl\t%L1, 0, %L1", operands);
11909 if (which_alternative == 1)
11910 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
11911 if (GET_CODE (operands[2]) == CONST_INT)
11913 if (which_alternative == 1)
11915 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11916 sprintf (mulstr, "%s\t%%H1, %%2, %%L0", opcode);
11917 output_asm_insn (mulstr, operands);
11918 return "srlx\t%L0, 32, %H0";
11922 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11923 output_asm_insn ("or\t%L1, %3, %3", operands);
11924 sprintf (mulstr, "%s\t%%3, %%2, %%3", opcode);
11925 output_asm_insn (mulstr, operands);
11926 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11927 return "mov\t%3, %L0";
11930 else if (rtx_equal_p (operands[1], operands[2]))
11932 if (which_alternative == 1)
11934 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11935 sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", opcode);
11936 output_asm_insn (mulstr, operands);
11937 return "srlx\t%L0, 32, %H0";
11941 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11942 output_asm_insn ("or\t%L1, %3, %3", operands);
11943 sprintf (mulstr, "%s\t%%3, %%3, %%3", opcode);
11944 output_asm_insn (mulstr, operands);
11945 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11946 return "mov\t%3, %L0";
11949 if (sparc_check_64 (operands[2], insn) <= 0)
11950 output_asm_insn ("srl\t%L2, 0, %L2", operands);
11951 if (which_alternative == 1)
11953 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11954 output_asm_insn ("sllx\t%H2, 32, %L1", operands);
11955 output_asm_insn ("or\t%L2, %L1, %L1", operands);
11956 sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", opcode);
11957 output_asm_insn (mulstr, operands);
11958 return "srlx\t%L0, 32, %H0";
11962 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11963 output_asm_insn ("sllx\t%H2, 32, %4", operands);
11964 output_asm_insn ("or\t%L1, %3, %3", operands);
11965 output_asm_insn ("or\t%L2, %4, %4", operands);
11966 sprintf (mulstr, "%s\t%%3, %%4, %%3", opcode);
11967 output_asm_insn (mulstr, operands);
11968 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11969 return "mov\t%3, %L0";
11973 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
11974 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
11975 and INNER_MODE are the modes describing TARGET. */
11978 vector_init_bshuffle (rtx target, rtx elt, machine_mode mode,
11979 machine_mode inner_mode)
11981 rtx t1, final_insn, sel;
11984 t1 = gen_reg_rtx (mode);
11986 elt = convert_modes (SImode, inner_mode, elt, true);
11987 emit_move_insn (gen_lowpart(SImode, t1), elt);
11992 final_insn = gen_bshufflev2si_vis (target, t1, t1);
11993 bmask = 0x45674567;
11996 final_insn = gen_bshufflev4hi_vis (target, t1, t1);
11997 bmask = 0x67676767;
12000 final_insn = gen_bshufflev8qi_vis (target, t1, t1);
12001 bmask = 0x77777777;
12004 gcc_unreachable ();
12007 sel = force_reg (SImode, GEN_INT (bmask));
12008 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
12009 emit_insn (final_insn);
12012 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12013 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12016 vector_init_fpmerge (rtx target, rtx elt)
12018 rtx t1, t2, t2_low, t3, t3_low;
12020 t1 = gen_reg_rtx (V4QImode);
12021 elt = convert_modes (SImode, QImode, elt, true);
12022 emit_move_insn (gen_lowpart (SImode, t1), elt);
12024 t2 = gen_reg_rtx (V8QImode);
12025 t2_low = gen_lowpart (V4QImode, t2);
12026 emit_insn (gen_fpmerge_vis (t2, t1, t1));
12028 t3 = gen_reg_rtx (V8QImode);
12029 t3_low = gen_lowpart (V4QImode, t3);
12030 emit_insn (gen_fpmerge_vis (t3, t2_low, t2_low));
12032 emit_insn (gen_fpmerge_vis (target, t3_low, t3_low));
12035 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12036 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12039 vector_init_faligndata (rtx target, rtx elt)
12041 rtx t1 = gen_reg_rtx (V4HImode);
12044 elt = convert_modes (SImode, HImode, elt, true);
12045 emit_move_insn (gen_lowpart (SImode, t1), elt);
12047 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode),
12048 force_reg (SImode, GEN_INT (6)),
12051 for (i = 0; i < 4; i++)
12052 emit_insn (gen_faligndatav4hi_vis (target, t1, target));
12055 /* Emit code to initialize TARGET to values for individual fields VALS. */
12058 sparc_expand_vector_init (rtx target, rtx vals)
12060 const machine_mode mode = GET_MODE (target);
12061 const machine_mode inner_mode = GET_MODE_INNER (mode);
12062 const int n_elts = GET_MODE_NUNITS (mode);
12068 for (i = 0; i < n_elts; i++)
12070 rtx x = XVECEXP (vals, 0, i);
12071 if (!CONSTANT_P (x))
12074 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
12080 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
12084 if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (mode))
12086 if (GET_MODE_SIZE (inner_mode) == 4)
12088 emit_move_insn (gen_lowpart (SImode, target),
12089 gen_lowpart (SImode, XVECEXP (vals, 0, 0)));
12092 else if (GET_MODE_SIZE (inner_mode) == 8)
12094 emit_move_insn (gen_lowpart (DImode, target),
12095 gen_lowpart (DImode, XVECEXP (vals, 0, 0)));
12099 else if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (word_mode)
12100 && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode))
12102 emit_move_insn (gen_highpart (word_mode, target),
12103 gen_lowpart (word_mode, XVECEXP (vals, 0, 0)));
12104 emit_move_insn (gen_lowpart (word_mode, target),
12105 gen_lowpart (word_mode, XVECEXP (vals, 0, 1)));
12109 if (all_same && GET_MODE_SIZE (mode) == 8)
12113 vector_init_bshuffle (target, XVECEXP (vals, 0, 0), mode, inner_mode);
12116 if (mode == V8QImode)
12118 vector_init_fpmerge (target, XVECEXP (vals, 0, 0));
12121 if (mode == V4HImode)
12123 vector_init_faligndata (target, XVECEXP (vals, 0, 0));
12128 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
12129 for (i = 0; i < n_elts; i++)
12130 emit_move_insn (adjust_address_nv (mem, inner_mode,
12131 i * GET_MODE_SIZE (inner_mode)),
12132 XVECEXP (vals, 0, i));
12133 emit_move_insn (target, mem);
12136 /* Implement TARGET_SECONDARY_RELOAD. */
12139 sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
12140 machine_mode mode, secondary_reload_info *sri)
12142 enum reg_class rclass = (enum reg_class) rclass_i;
12144 sri->icode = CODE_FOR_nothing;
12145 sri->extra_cost = 0;
12147 /* We need a temporary when loading/storing a HImode/QImode value
12148 between memory and the FPU registers. This can happen when combine puts
12149 a paradoxical subreg in a float/fix conversion insn. */
12150 if (FP_REG_CLASS_P (rclass)
12151 && (mode == HImode || mode == QImode)
12152 && (GET_CODE (x) == MEM
12153 || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
12154 && true_regnum (x) == -1)))
12155 return GENERAL_REGS;
12157 /* On 32-bit we need a temporary when loading/storing a DFmode value
12158 between unaligned memory and the upper FPU registers. */
12160 && rclass == EXTRA_FP_REGS
12162 && GET_CODE (x) == MEM
12163 && ! mem_min_alignment (x, 8))
12166 if (((TARGET_CM_MEDANY
12167 && symbolic_operand (x, mode))
12168 || (TARGET_CM_EMBMEDANY
12169 && text_segment_operand (x, mode)))
12173 sri->icode = direct_optab_handler (reload_in_optab, mode);
12175 sri->icode = direct_optab_handler (reload_out_optab, mode);
12179 if (TARGET_VIS3 && TARGET_ARCH32)
12181 int regno = true_regnum (x);
12183 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12184 to move 8-byte values in 4-byte pieces. This only works via
12185 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12186 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12187 an FP_REGS intermediate move. */
12188 if ((rclass == EXTRA_FP_REGS && SPARC_INT_REG_P (regno))
12189 || ((general_or_i64_p (rclass)
12190 || rclass == GENERAL_OR_FP_REGS)
12191 && SPARC_FP_REG_P (regno)))
12193 sri->extra_cost = 2;
12201 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12202 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12205 sparc_expand_conditional_move (machine_mode mode, rtx *operands)
12207 enum rtx_code rc = GET_CODE (operands[1]);
12208 machine_mode cmp_mode;
12209 rtx cc_reg, dst, cmp;
12212 if (GET_MODE (XEXP (cmp, 0)) == DImode && !TARGET_ARCH64)
12215 if (GET_MODE (XEXP (cmp, 0)) == TFmode && !TARGET_HARD_QUAD)
12216 cmp = sparc_emit_float_lib_cmp (XEXP (cmp, 0), XEXP (cmp, 1), rc);
12218 cmp_mode = GET_MODE (XEXP (cmp, 0));
12219 rc = GET_CODE (cmp);
12222 if (! rtx_equal_p (operands[2], dst)
12223 && ! rtx_equal_p (operands[3], dst))
12225 if (reg_overlap_mentioned_p (dst, cmp))
12226 dst = gen_reg_rtx (mode);
12228 emit_move_insn (dst, operands[3]);
12230 else if (operands[2] == dst)
12232 operands[2] = operands[3];
12234 if (GET_MODE_CLASS (cmp_mode) == MODE_FLOAT)
12235 rc = reverse_condition_maybe_unordered (rc);
12237 rc = reverse_condition (rc);
12240 if (XEXP (cmp, 1) == const0_rtx
12241 && GET_CODE (XEXP (cmp, 0)) == REG
12242 && cmp_mode == DImode
12243 && v9_regcmp_p (rc))
12244 cc_reg = XEXP (cmp, 0);
12246 cc_reg = gen_compare_reg_1 (rc, XEXP (cmp, 0), XEXP (cmp, 1));
12248 cmp = gen_rtx_fmt_ee (rc, GET_MODE (cc_reg), cc_reg, const0_rtx);
12250 emit_insn (gen_rtx_SET (dst,
12251 gen_rtx_IF_THEN_ELSE (mode, cmp, operands[2], dst)));
12253 if (dst != operands[0])
12254 emit_move_insn (operands[0], dst);
12259 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
12260 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
12261 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
12262 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
12263 code to be used for the condition mask. */
12266 sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode)
12268 rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr;
12269 enum rtx_code code = GET_CODE (operands[3]);
12271 mask = gen_reg_rtx (Pmode);
12272 cop0 = operands[4];
12273 cop1 = operands[5];
12274 if (code == LT || code == GE)
12278 code = swap_condition (code);
12279 t = cop0; cop0 = cop1; cop1 = t;
12282 gsr = gen_rtx_REG (DImode, SPARC_GSR_REG);
12284 fcmp = gen_rtx_UNSPEC (Pmode,
12285 gen_rtvec (1, gen_rtx_fmt_ee (code, mode, cop0, cop1)),
12288 cmask = gen_rtx_UNSPEC (DImode,
12289 gen_rtvec (2, mask, gsr),
12292 bshuf = gen_rtx_UNSPEC (mode,
12293 gen_rtvec (3, operands[1], operands[2], gsr),
12296 emit_insn (gen_rtx_SET (mask, fcmp));
12297 emit_insn (gen_rtx_SET (gsr, cmask));
12299 emit_insn (gen_rtx_SET (operands[0], bshuf));
12302 /* On sparc, any mode which naturally allocates into the float
12303 registers should return 4 here. */
12306 sparc_regmode_natural_size (machine_mode mode)
12308 int size = UNITS_PER_WORD;
12312 enum mode_class mclass = GET_MODE_CLASS (mode);
12314 if (mclass == MODE_FLOAT || mclass == MODE_VECTOR_INT)
12321 /* Return TRUE if it is a good idea to tie two pseudo registers
12322 when one has mode MODE1 and one has mode MODE2.
12323 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12324 for any hard reg, then this must be FALSE for correct output.
12326 For V9 we have to deal with the fact that only the lower 32 floating
12327 point registers are 32-bit addressable. */
12330 sparc_modes_tieable_p (machine_mode mode1, machine_mode mode2)
12332 enum mode_class mclass1, mclass2;
12333 unsigned short size1, size2;
12335 if (mode1 == mode2)
12338 mclass1 = GET_MODE_CLASS (mode1);
12339 mclass2 = GET_MODE_CLASS (mode2);
12340 if (mclass1 != mclass2)
12346 /* Classes are the same and we are V9 so we have to deal with upper
12347 vs. lower floating point registers. If one of the modes is a
12348 4-byte mode, and the other is not, we have to mark them as not
12349 tieable because only the lower 32 floating point register are
12350 addressable 32-bits at a time.
12352 We can't just test explicitly for SFmode, otherwise we won't
12353 cover the vector mode cases properly. */
12355 if (mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT)
12358 size1 = GET_MODE_SIZE (mode1);
12359 size2 = GET_MODE_SIZE (mode2);
12360 if ((size1 > 4 && size2 == 4)
12361 || (size2 > 4 && size1 == 4))
12367 /* Implement TARGET_CSTORE_MODE. */
12369 static machine_mode
12370 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED)
12372 return (TARGET_ARCH64 ? DImode : SImode);
12375 /* Return the compound expression made of T1 and T2. */
12378 compound_expr (tree t1, tree t2)
12380 return build2 (COMPOUND_EXPR, void_type_node, t1, t2);
12383 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
12386 sparc_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
12391 const unsigned HOST_WIDE_INT accrued_exception_mask = 0x1f << 5;
12392 const unsigned HOST_WIDE_INT trap_enable_mask = 0x1f << 23;
12394 /* We generate the equivalent of feholdexcept (&fenv_var):
12396 unsigned int fenv_var;
12397 __builtin_store_fsr (&fenv_var);
12399 unsigned int tmp1_var;
12400 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
12402 __builtin_load_fsr (&tmp1_var); */
12404 tree fenv_var = create_tmp_var_raw (unsigned_type_node);
12405 TREE_ADDRESSABLE (fenv_var) = 1;
12406 tree fenv_addr = build_fold_addr_expr (fenv_var);
12407 tree stfsr = sparc_builtins[SPARC_BUILTIN_STFSR];
12409 = build4 (TARGET_EXPR, unsigned_type_node, fenv_var,
12410 build_call_expr (stfsr, 1, fenv_addr), NULL_TREE, NULL_TREE);
12412 tree tmp1_var = create_tmp_var_raw (unsigned_type_node);
12413 TREE_ADDRESSABLE (tmp1_var) = 1;
12414 tree masked_fenv_var
12415 = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var,
12416 build_int_cst (unsigned_type_node,
12417 ~(accrued_exception_mask | trap_enable_mask)));
12419 = build4 (TARGET_EXPR, unsigned_type_node, tmp1_var, masked_fenv_var,
12420 NULL_TREE, NULL_TREE);
12422 tree tmp1_addr = build_fold_addr_expr (tmp1_var);
12423 tree ldfsr = sparc_builtins[SPARC_BUILTIN_LDFSR];
12424 tree hold_ldfsr = build_call_expr (ldfsr, 1, tmp1_addr);
12426 *hold = compound_expr (compound_expr (hold_stfsr, hold_mask), hold_ldfsr);
12428 /* We reload the value of tmp1_var to clear the exceptions:
12430 __builtin_load_fsr (&tmp1_var); */
12432 *clear = build_call_expr (ldfsr, 1, tmp1_addr);
12434 /* We generate the equivalent of feupdateenv (&fenv_var):
12436 unsigned int tmp2_var;
12437 __builtin_store_fsr (&tmp2_var);
12439 __builtin_load_fsr (&fenv_var);
12441 if (SPARC_LOW_FE_EXCEPT_VALUES)
12443 __atomic_feraiseexcept ((int) tmp2_var); */
12445 tree tmp2_var = create_tmp_var_raw (unsigned_type_node);
12446 TREE_ADDRESSABLE (tmp2_var) = 1;
12447 tree tmp2_addr = build_fold_addr_expr (tmp2_var);
12449 = build4 (TARGET_EXPR, unsigned_type_node, tmp2_var,
12450 build_call_expr (stfsr, 1, tmp2_addr), NULL_TREE, NULL_TREE);
12452 tree update_ldfsr = build_call_expr (ldfsr, 1, fenv_addr);
12454 tree atomic_feraiseexcept
12455 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
12457 = build_call_expr (atomic_feraiseexcept, 1,
12458 fold_convert (integer_type_node, tmp2_var));
12460 if (SPARC_LOW_FE_EXCEPT_VALUES)
12462 tree shifted_tmp2_var
12463 = build2 (RSHIFT_EXPR, unsigned_type_node, tmp2_var,
12464 build_int_cst (unsigned_type_node, 5));
12466 = build2 (MODIFY_EXPR, void_type_node, tmp2_var, shifted_tmp2_var);
12467 update_call = compound_expr (update_shift, update_call);
12471 = compound_expr (compound_expr (update_stfsr, update_ldfsr), update_call);
12474 #include "gt-sparc.h"