1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993-2013 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "config/vxworks-dummy.h"
27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
28 include it here, because bconfig.h is also included by gencodes.c . */
29 /* ??? No longer true. */
30 extern int code_for_indirect_jump_scratch;
32 #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
34 /* Value should be nonzero if functions must have frame pointers.
35 Zero means the frame pointer need not be set up (and parms may be accessed
36 via the stack pointer) in functions that seem suitable. */
38 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
39 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
43 /* Nonzero if this is an ELF target - compile time only */
46 /* Nonzero if we should generate code using type 2E insns. */
47 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
49 /* Nonzero if we should generate code using type 2A insns. */
50 #define TARGET_SH2A TARGET_HARD_SH2A
51 /* Nonzero if we should generate code using type 2A SF insns. */
52 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
53 /* Nonzero if we should generate code using type 2A DF insns. */
54 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
56 /* Nonzero if we should generate code using type 3E insns. */
57 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
59 /* Nonzero if we schedule for a superscalar implementation. */
60 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A)
62 /* Nonzero if a double-precision FPU is available. */
63 #define TARGET_FPU_DOUBLE \
64 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
66 /* Nonzero if an FPU is available. */
67 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
69 /* Nonzero if we should generate code using type 4 insns. */
71 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
73 /* Nonzero if we're generating code for the common subset of
74 instructions present on both SH4a and SH4al-dsp. */
75 #define TARGET_SH4A_ARCH TARGET_SH4A
77 /* Nonzero if we're generating code for SH4a, unless the use of the
78 FPU is disabled (which makes it compatible with SH4al-dsp). */
79 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
81 /* Nonzero if we should generate code using the SHcompact instruction
82 set and 32-bit ABI. */
83 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
85 /* Nonzero if we should generate code using the SHmedia instruction
87 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
89 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
91 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
93 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
95 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
97 /* Nonzero if we should generate code using SHmedia FPU instructions. */
98 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
100 /* This is not used by the SH2E calling convention */
101 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
102 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
103 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
105 #ifndef TARGET_CPU_DEFAULT
106 #define TARGET_CPU_DEFAULT SELECT_SH1
107 #define SUPPORT_SH1 1
108 #define SUPPORT_SH2E 1
109 #define SUPPORT_SH4 1
110 #define SUPPORT_SH4_SINGLE 1
111 #define SUPPORT_SH2A 1
112 #define SUPPORT_SH2A_SINGLE 1
115 #define TARGET_DIVIDE_INV \
116 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
117 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
118 || sh_div_strategy == SH_DIV_INV_CALL \
119 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
120 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
121 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
122 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
123 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
124 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
125 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
126 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
127 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
128 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
129 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
130 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
132 #define SELECT_SH1 (MASK_SH1)
133 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
134 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
136 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
137 | MASK_HARD_SH2A_DOUBLE \
138 | MASK_SH2 | MASK_SH1)
139 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
140 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
141 | MASK_SH1 | MASK_FPU_SINGLE \
142 | MASK_FPU_SINGLE_ONLY)
143 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
144 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
145 | MASK_SH2 | MASK_SH1)
146 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
147 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
148 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
149 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \
150 | MASK_FPU_SINGLE_ONLY)
151 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
153 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
154 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
155 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
156 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
157 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
158 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
159 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
160 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
161 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
162 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
163 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
166 #define SUPPORT_SH2 1
169 #define SUPPORT_SH3 1
170 #define SUPPORT_SH2A_NOFPU 1
173 #define SUPPORT_SH4_NOFPU 1
175 #if SUPPORT_SH4_NOFPU
176 #define SUPPORT_SH4A_NOFPU 1
177 #define SUPPORT_SH4AL 1
181 #define SUPPORT_SH3E 1
182 #define SUPPORT_SH2A_SINGLE_ONLY 1
185 #define SUPPORT_SH4_SINGLE_ONLY 1
187 #if SUPPORT_SH4_SINGLE_ONLY
188 #define SUPPORT_SH4A_SINGLE_ONLY 1
192 #define SUPPORT_SH4A 1
195 #if SUPPORT_SH4_SINGLE
196 #define SUPPORT_SH4A_SINGLE 1
199 #if SUPPORT_SH5_COMPAT
200 #define SUPPORT_SH5_32MEDIA 1
203 #if SUPPORT_SH5_COMPACT_NOFPU
204 #define SUPPORT_SH5_32MEDIA_NOFPU 1
207 #define SUPPORT_ANY_SH5_32MEDIA \
208 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
209 #define SUPPORT_ANY_SH5_64MEDIA \
210 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
211 #define SUPPORT_ANY_SH5 \
212 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
214 /* Reset all target-selection flags. */
215 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
216 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
217 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
218 | MASK_FPU_SINGLE_ONLY)
220 /* This defaults us to big-endian. */
221 #ifndef TARGET_ENDIAN_DEFAULT
222 #define TARGET_ENDIAN_DEFAULT 0
225 #ifndef TARGET_OPT_DEFAULT
226 #define TARGET_OPT_DEFAULT 0
229 #define TARGET_DEFAULT \
230 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
232 #ifndef SH_MULTILIB_CPU_DEFAULT
233 #define SH_MULTILIB_CPU_DEFAULT "m1"
236 #if TARGET_ENDIAN_DEFAULT
237 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
239 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
242 #define CPP_SPEC " %(subtarget_cpp_spec) "
244 #ifndef SUBTARGET_CPP_SPEC
245 #define SUBTARGET_CPP_SPEC ""
248 #ifndef SUBTARGET_EXTRA_SPECS
249 #define SUBTARGET_EXTRA_SPECS
252 #define EXTRA_SPECS \
253 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
254 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
255 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
256 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
257 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
258 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
259 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
260 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
261 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
262 SUBTARGET_EXTRA_SPECS
264 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
265 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
267 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
270 #define SH_ASM_SPEC \
271 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \
272 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
274 %{m2a-single:--isa=sh2a} \
275 %{m2a-single-only:--isa=sh2a} \
276 %{m2a-nofpu:--isa=sh2a-nofpu} \
277 %{m5-compact*:--isa=SHcompact} \
278 %{m5-32media*:--isa=SHmedia --abi=32} \
279 %{m5-64media*:--isa=SHmedia --abi=64} \
280 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
282 #define ASM_SPEC SH_ASM_SPEC
284 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
285 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
286 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
288 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
292 #if STRICT_NOFPU == 1
293 /* Strict nofpu means that the compiler should tell the assembler
294 to reject FPU instructions. E.g. from ASM inserts. */
295 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
296 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
298 /* If there were an -isa option for sh5-nofpu then it would also go here. */
299 #define SUBTARGET_ASM_ISA_SPEC \
300 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
302 #else /* ! STRICT_NOFPU */
303 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
306 #ifndef SUBTARGET_ASM_SPEC
307 #define SUBTARGET_ASM_SPEC ""
310 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
311 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
313 #define LINK_EMUL_PREFIX "sh%{ml:l}"
316 #if TARGET_CPU_DEFAULT & MASK_SH5
317 #if TARGET_CPU_DEFAULT & MASK_SH_E
318 #define LINK_DEFAULT_CPU_EMUL "32"
319 #if TARGET_CPU_DEFAULT & MASK_SH1
320 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
322 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
323 #endif /* MASK_SH1 */
324 #else /* !MASK_SH_E */
325 #define LINK_DEFAULT_CPU_EMUL "64"
326 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
327 #endif /* MASK_SH_E */
328 #define ASM_ISA_DEFAULT_SPEC \
329 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
330 #else /* !MASK_SH5 */
331 #define LINK_DEFAULT_CPU_EMUL ""
332 #define ASM_ISA_DEFAULT_SPEC ""
333 #endif /* MASK_SH5 */
335 #define SUBTARGET_LINK_EMUL_SUFFIX ""
336 #define SUBTARGET_LINK_SPEC ""
338 /* Go via SH_LINK_SPEC to avoid code replication. */
339 #define LINK_SPEC SH_LINK_SPEC
341 #define SH_LINK_SPEC "\
342 -m %(link_emul_prefix)\
343 %{m5-compact*|m5-32media*:32}\
345 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
346 %(subtarget_link_emul_suffix) \
347 %{mrelax:-relax} %(subtarget_link_spec)"
349 #ifndef SH_DIV_STR_FOR_SIZE
350 #define SH_DIV_STR_FOR_SIZE "call"
353 /* SH2A does not support little-endian. Catch such combinations
354 taking into account the default configuration. */
355 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
356 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
358 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
361 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
362 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
363 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}"
365 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
366 "%{m2a*:%eSH2a does not support little-endian}}"
369 #undef DRIVER_SELF_SPECS
370 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
372 #define ASSEMBLER_DIALECT assembler_dialect
374 extern int assembler_dialect;
376 enum sh_divide_strategy_e {
377 /* SH5 strategies. */
380 SH_DIV_FP, /* We could do this also for SH4. */
388 /* SH1 .. SH4 strategies. Because of the small number of registers
389 available, the compiler uses knowledge of the actual set of registers
390 being clobbered by the different functions called. */
391 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
392 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
393 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
397 extern enum sh_divide_strategy_e sh_div_strategy;
399 #ifndef SH_DIV_STRATEGY_DEFAULT
400 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
403 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
406 /* Target machine storage layout. */
408 /* Define this if most significant bit is lowest numbered
409 in instructions that operate on numbered bit-fields. */
410 #define BITS_BIG_ENDIAN 0
412 /* Define this if most significant byte of a word is the lowest numbered. */
413 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
415 /* Define this if most significant word of a multiword number is the lowest
417 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
419 #define MAX_BITS_PER_WORD 64
421 /* Width in bits of an `int'. We want just 32-bits, even if words are
423 #define INT_TYPE_SIZE 32
425 /* Width in bits of a `long'. */
426 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
428 /* Width in bits of a `long long'. */
429 #define LONG_LONG_TYPE_SIZE 64
431 /* Width in bits of a `long double'. */
432 #define LONG_DOUBLE_TYPE_SIZE 64
434 /* Width of a word, in units (bytes). */
435 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
436 #define MIN_UNITS_PER_WORD 4
438 /* Scaling factor for Dwarf data offsets for CFI information.
439 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
440 SHmedia; however, since we do partial register saves for the registers
441 visible to SHcompact, and for target registers for SHMEDIA32, we have
442 to allow saves that are only 4-byte aligned. */
443 #define DWARF_CIE_DATA_ALIGNMENT -4
445 /* Width in bits of a pointer.
446 See also the macro `Pmode' defined below. */
447 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
449 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
450 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
452 /* Boundary (in *bits*) on which stack pointer should be aligned. */
453 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
455 /* The log (base 2) of the cache line size, in bytes. Processors prior to
456 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
457 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
458 #define CACHE_LOG ((TARGET_HARD_SH4 || TARGET_SH5) ? 5 : TARGET_SH2 ? 4 : 2)
460 /* ABI given & required minimum allocation boundary (in *bits*) for the
461 code of a function. */
462 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
464 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
465 the vbit must go into the delta field of
466 pointers-to-member-functions. */
467 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
468 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
470 /* Alignment of field after `int : 0' in a structure. */
471 #define EMPTY_FIELD_BOUNDARY 32
473 /* No data type wants to be aligned rounder than this. */
474 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
476 /* The best alignment to use in cases where we have a choice. */
477 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
479 /* Make strings word-aligned so strcpy from constants will be faster. */
480 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
481 ((TREE_CODE (EXP) == STRING_CST \
482 && (ALIGN) < FASTEST_ALIGNMENT) \
483 ? FASTEST_ALIGNMENT : (ALIGN))
485 /* get_mode_alignment assumes complex values are always held in multiple
486 registers, but that is not the case on the SH; CQImode and CHImode are
487 held in a single integer register. SH5 also holds CSImode and SCmode
488 values in integer registers. This is relevant for argument passing on
489 SHcompact as we use a stack temp in order to pass CSImode by reference. */
490 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
491 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
492 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
493 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
494 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
496 /* Make arrays of chars word-aligned for the same reasons. */
497 #define DATA_ALIGNMENT(TYPE, ALIGN) \
498 (TREE_CODE (TYPE) == ARRAY_TYPE \
499 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
500 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
502 /* Number of bits which any structure or union's size must be a
503 multiple of. Each structure or union's size is rounded up to a
505 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
507 /* Set this nonzero if move instructions will actually fail to work
508 when given unaligned data. */
509 #define STRICT_ALIGNMENT 1
511 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
512 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
513 barrier_align (LABEL_AFTER_BARRIER)
515 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL)
517 #define LABEL_ALIGN(A_LABEL) \
519 (PREV_INSN (A_LABEL) \
520 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
521 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
522 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
523 /* explicit alignment insn in constant tables. */ \
524 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
527 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
528 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
530 /* The base two logarithm of the known minimum alignment of an insn length. */
531 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
532 (NONJUMP_INSN_P (A_INSN) \
533 ? 1 << TARGET_SHMEDIA \
534 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
535 ? 1 << TARGET_SHMEDIA \
538 /* Standard register usage. */
540 /* Register allocation for the Renesas calling convention:
546 r14 frame pointer/call saved
548 ap arg pointer (doesn't really exist, always eliminated)
549 pr subroutine return address
551 mach multiply/accumulate result, high part
552 macl multiply/accumulate result, low part.
553 fpul fp/int communication register
554 rap return address pointer register
556 fr1..fr3 scratch floating point registers
558 fr12..fr15 call saved floating point registers */
560 #define MAX_REGISTER_NAME_LENGTH 5
561 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
563 #define SH_REGISTER_NAMES_INITIALIZER \
565 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
566 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
567 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
568 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
569 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
570 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
571 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
572 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
573 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
574 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
575 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
576 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
577 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
578 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
579 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
580 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
581 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
582 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
583 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
587 #define REGNAMES_ARR_INDEX_1(index) \
588 (sh_register_names[index])
589 #define REGNAMES_ARR_INDEX_2(index) \
590 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
591 #define REGNAMES_ARR_INDEX_4(index) \
592 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
593 #define REGNAMES_ARR_INDEX_8(index) \
594 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
595 #define REGNAMES_ARR_INDEX_16(index) \
596 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
597 #define REGNAMES_ARR_INDEX_32(index) \
598 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
599 #define REGNAMES_ARR_INDEX_64(index) \
600 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
602 #define REGISTER_NAMES \
604 REGNAMES_ARR_INDEX_64 (0), \
605 REGNAMES_ARR_INDEX_64 (64), \
606 REGNAMES_ARR_INDEX_8 (128), \
607 REGNAMES_ARR_INDEX_8 (136), \
608 REGNAMES_ARR_INDEX_8 (144), \
609 REGNAMES_ARR_INDEX_2 (152) \
612 #define ADDREGNAMES_SIZE 32
613 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
614 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
615 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
617 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
619 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
620 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
621 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
622 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
625 #define ADDREGNAMES_REGNO(index) \
626 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
629 #define ADDREGNAMES_ARR_INDEX_1(index) \
630 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
631 #define ADDREGNAMES_ARR_INDEX_2(index) \
632 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
633 #define ADDREGNAMES_ARR_INDEX_4(index) \
634 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
635 #define ADDREGNAMES_ARR_INDEX_8(index) \
636 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
637 #define ADDREGNAMES_ARR_INDEX_16(index) \
638 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
639 #define ADDREGNAMES_ARR_INDEX_32(index) \
640 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
642 #define ADDITIONAL_REGISTER_NAMES \
644 ADDREGNAMES_ARR_INDEX_32 (0) \
647 /* Number of actual hardware registers.
648 The hardware registers are assigned numbers for the compiler
649 from 0 to just below FIRST_PSEUDO_REGISTER.
650 All registers that the compiler knows about must be given numbers,
651 even those that are not normally considered general registers. */
653 /* There are many other relevant definitions in sh.md's md_constants. */
655 #define FIRST_GENERAL_REG R0_REG
656 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
657 #define FIRST_FP_REG DR0_REG
658 #define LAST_FP_REG (FIRST_FP_REG + \
659 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
660 #define FIRST_XD_REG XD0_REG
661 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
662 #define FIRST_TARGET_REG TR0_REG
663 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
665 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
666 #define FIRST_BANKED_REG R0_REG
667 #define LAST_BANKED_REG R7_REG
669 #define BANKED_REGISTER_P(REGNO) \
671 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
672 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
674 #define GENERAL_REGISTER_P(REGNO) \
676 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
677 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
679 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
680 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
681 || ((REGNO) == FRAME_POINTER_REGNUM))
683 #define FP_REGISTER_P(REGNO) \
684 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
686 #define XD_REGISTER_P(REGNO) \
687 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
689 #define FP_OR_XD_REGISTER_P(REGNO) \
690 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
692 #define FP_ANY_REGISTER_P(REGNO) \
693 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
695 #define SPECIAL_REGISTER_P(REGNO) \
696 ((REGNO) == GBR_REG || (REGNO) == T_REG \
697 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
699 #define TARGET_REGISTER_P(REGNO) \
700 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
702 #define SHMEDIA_REGISTER_P(REGNO) \
703 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
704 || TARGET_REGISTER_P (REGNO))
706 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
707 registers that should be fixed. */
708 #define VALID_REGISTER_P(REGNO) \
709 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
710 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
711 || (REGNO) == FRAME_POINTER_REGNUM \
712 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
713 || (TARGET_SH2E && (REGNO) == FPUL_REG))
715 /* The mode that should be generally used to store a register by
716 itself in the stack, or to load it back. */
717 #define REGISTER_NATURAL_MODE(REGNO) \
718 (FP_REGISTER_P (REGNO) ? SFmode \
719 : XD_REGISTER_P (REGNO) ? DFmode \
720 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
724 #define FIRST_PSEUDO_REGISTER 154
726 /* Don't count soft frame pointer. */
727 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
729 /* 1 for registers that have pervasive standard uses
730 and are not available for the register allocator.
732 Mach register is fixed 'cause it's only 10 bits wide for SH1.
733 It is 32 bits wide for SH2. */
734 #define FIXED_REGISTERS \
736 /* Regular registers. */ \
737 0, 0, 0, 0, 0, 0, 0, 0, \
738 0, 0, 0, 0, 0, 0, 0, 1, \
739 /* r16 is reserved, r18 is the former pr. */ \
740 1, 0, 0, 0, 0, 0, 0, 0, \
741 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
742 /* r26 is a global variable data pointer; r27 is for constants. */ \
743 1, 1, 1, 1, 0, 0, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, \
745 0, 0, 0, 0, 0, 0, 0, 0, \
746 0, 0, 0, 0, 0, 0, 0, 0, \
747 0, 0, 0, 0, 0, 0, 0, 1, \
748 /* FP registers. */ \
749 0, 0, 0, 0, 0, 0, 0, 0, \
750 0, 0, 0, 0, 0, 0, 0, 0, \
751 0, 0, 0, 0, 0, 0, 0, 0, \
752 0, 0, 0, 0, 0, 0, 0, 0, \
753 0, 0, 0, 0, 0, 0, 0, 0, \
754 0, 0, 0, 0, 0, 0, 0, 0, \
755 0, 0, 0, 0, 0, 0, 0, 0, \
756 0, 0, 0, 0, 0, 0, 0, 0, \
757 /* Branch target registers. */ \
758 0, 0, 0, 0, 0, 0, 0, 0, \
759 /* XD registers. */ \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
762 1, 1, 1, 1, 1, 1, 0, 1, \
767 /* 1 for registers not available across function calls.
768 These must include the FIXED_REGISTERS and also any
769 registers that can be used without being saved.
770 The latter must include the registers where values are returned
771 and the register where structure-value addresses are passed.
772 Aside from that, you can include as many other registers as you like. */
773 #define CALL_USED_REGISTERS \
775 /* Regular registers. */ \
776 1, 1, 1, 1, 1, 1, 1, 1, \
777 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
778 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
779 across SH5 function calls. */ \
780 0, 0, 0, 0, 0, 0, 0, 1, \
781 1, 1, 1, 1, 1, 1, 1, 1, \
782 1, 1, 1, 1, 0, 0, 0, 0, \
783 0, 0, 0, 0, 1, 1, 1, 1, \
784 1, 1, 1, 1, 0, 0, 0, 0, \
785 0, 0, 0, 0, 0, 0, 0, 0, \
786 0, 0, 0, 0, 1, 1, 1, 1, \
787 /* FP registers. */ \
788 1, 1, 1, 1, 1, 1, 1, 1, \
789 1, 1, 1, 1, 0, 0, 0, 0, \
790 1, 1, 1, 1, 1, 1, 1, 1, \
791 1, 1, 1, 1, 1, 1, 1, 1, \
792 1, 1, 1, 1, 0, 0, 0, 0, \
793 0, 0, 0, 0, 0, 0, 0, 0, \
794 0, 0, 0, 0, 0, 0, 0, 0, \
795 0, 0, 0, 0, 0, 0, 0, 0, \
796 /* Branch target registers. */ \
797 1, 1, 1, 1, 1, 0, 0, 0, \
798 /* XD registers. */ \
799 1, 1, 1, 1, 1, 1, 0, 0, \
800 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
801 1, 1, 1, 1, 1, 1, 1, 1, \
806 /* TARGET_CONDITIONAL_REGISTER_USAGE might want to make a register
807 call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
808 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
810 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
811 across SHcompact function calls. We can't tell whether a called
812 function is SHmedia or SHcompact, so we assume it may be when
813 compiling SHmedia code with the 32-bit ABI, since that's the only
814 ABI that can be linked with SHcompact code. */
815 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
817 && GET_MODE_SIZE (MODE) > 4 \
818 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
819 && (REGNO) <= FIRST_GENERAL_REG + 15) \
820 || TARGET_REGISTER_P (REGNO) \
821 || (REGNO) == PR_MEDIA_REG))
823 /* Return number of consecutive hard regs needed starting at reg REGNO
824 to hold something of mode MODE.
825 This is ordinarily the length in words of a value of mode MODE
826 but can be less for certain modes in special long registers.
828 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
829 #define HARD_REGNO_NREGS(REGNO, MODE) \
830 (XD_REGISTER_P (REGNO) \
831 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
832 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
833 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
834 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
836 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
837 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
838 sh_hard_regno_mode_ok ((REGNO), (MODE))
840 /* Value is 1 if it is a good idea to tie two pseudo registers
841 when one has mode MODE1 and one has mode MODE2.
842 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
843 for any hard reg, then this must be 0 for correct output.
844 That's the case for xd registers: we don't hold SFmode values in
845 them, so we can't tie an SFmode pseudos with one in another
846 floating-point mode. */
847 #define MODES_TIEABLE_P(MODE1, MODE2) \
848 ((MODE1) == (MODE2) \
850 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
851 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
852 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
853 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
854 && (GET_MODE_SIZE (MODE2) <= 4)) \
855 : ((MODE1) != SFmode && (MODE2) != SFmode))))
857 /* A C expression that is nonzero if hard register NEW_REG can be
858 considered for use as a rename register for OLD_REG register */
859 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
860 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
862 /* Specify the registers used for certain standard purposes.
863 The values of these macros are register numbers. */
865 /* Define this if the program counter is overloaded on a register. */
866 /* #define PC_REGNUM 15*/
868 /* Register to use for pushing function arguments. */
869 #define STACK_POINTER_REGNUM SP_REG
871 /* Base register for access to local variables of the function. */
872 #define HARD_FRAME_POINTER_REGNUM FP_REG
874 /* Base register for access to local variables of the function. */
875 #define FRAME_POINTER_REGNUM 153
877 /* Fake register that holds the address on the stack of the
878 current function's return address. */
879 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
881 /* Register to hold the addressing base for position independent
882 code access to data items. */
883 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
885 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
887 /* Definitions for register eliminations.
889 We have three registers that can be eliminated on the SH. First, the
890 frame pointer register can often be eliminated in favor of the stack
891 pointer register. Secondly, the argument pointer register can always be
892 eliminated; it is replaced with either the stack or frame pointer.
893 Third, there is the return address pointer, which can also be replaced
894 with either the stack or the frame pointer.
896 This is an array of structures. Each structure initializes one pair
897 of eliminable registers. The "from" register number is given first,
898 followed by "to". Eliminations of the same "from" register are listed
899 in order of preference.
901 If you add any registers here that are not actually hard registers,
902 and that have any alternative of elimination that doesn't always
903 apply, you need to amend calc_live_regs to exclude it, because
904 reload spills all eliminable registers where it sees an
905 can_eliminate == 0 entry, thus making them 'live' .
906 If you add any hard registers that can be eliminated in different
907 ways, you have to patch reload to spill them only when all alternatives
908 of elimination fail. */
909 #define ELIMINABLE_REGS \
910 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
911 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
912 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
913 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
914 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
915 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
916 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
918 /* Define the offset between two registers, one to be eliminated, and the other
919 its replacement, at the start of a routine. */
920 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
921 OFFSET = initial_elimination_offset ((FROM), (TO))
923 /* Base register for access to arguments of the function. */
924 #define ARG_POINTER_REGNUM AP_REG
926 /* Register in which the static-chain is passed to a function. */
927 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
929 /* Don't default to pcc-struct-return, because we have already specified
930 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
932 #define DEFAULT_PCC_STRUCT_RETURN 0
934 #define SHMEDIA_REGS_STACK_ADJUST() \
935 (TARGET_SHCOMPACT && crtl->saves_all_registers \
936 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
937 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
941 /* Define the classes of registers for register constraints in the
942 machine description. Also define ranges of constants.
944 One of the classes must always be named ALL_REGS and include all hard regs.
945 If there is more than one class, another class must be named NO_REGS
946 and contain no registers.
948 The name GENERAL_REGS must be the name of a class (or an alias for
949 another name such as ALL_REGS). This is the class of registers
950 that is allowed by "g" or "r" in a register constraint.
951 Also, registers outside this class are allocated only when
952 instructions express preferences for them.
954 The classes must be numbered in nondecreasing order; that is,
955 a larger-numbered class must never be contained completely
956 in a smaller-numbered class.
958 For any two classes, it is very desirable that there be another
959 class that represents their union.
961 The SH has two sorts of general registers, R0 and the rest. R0 can
962 be used as the destination of some of the arithmetic ops. There are
963 also some special purpose registers; the T bit register, the
964 Procedure Return Register and the Multiply Accumulate Registers.
966 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
967 reg_class_subunion. We don't want to have an actual union class
968 of these, because it would only be used when both classes are calculated
969 to give the same cost, but there is only one FPUL register.
970 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
971 applying to the actual instruction alternative considered. E.g., the
972 y/r alternative of movsi_ie is considered to have no more cost that
973 the r/r alternative, which is patently untrue. */
997 #define N_REG_CLASSES (int) LIM_REG_CLASSES
999 /* Give names of register classes as strings for dump file. */
1000 #define REG_CLASS_NAMES \
1016 "GENERAL_FP_REGS", \
1017 "GENERAL_DF_REGS", \
1022 /* Define which registers fit in which classes.
1023 This is an initializer for a vector of HARD_REG_SET
1024 of length N_REG_CLASSES. */
1025 #define REG_CLASS_CONTENTS \
1028 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1030 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1032 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1034 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1036 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1038 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1039 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1040 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1041 /* NON_SP_REGS: */ \
1042 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1043 /* GENERAL_REGS: */ \
1044 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1046 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1048 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1049 /* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1050 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1052 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1054 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1055 /* GENERAL_FP_REGS: */ \
1056 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1057 /* GENERAL_DF_REGS: */ \
1058 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1059 /* TARGET_REGS: */ \
1060 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1062 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1065 /* The same information, inverted:
1066 Return the class number of the smallest class containing
1067 reg number REGNO. This could be a conditional expression
1068 or could index an array. */
1069 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1070 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1072 /* When this hook returns true for MODE, the compiler allows
1073 registers explicitly used in the rtl to be used as spill registers
1074 but prevents the compiler from extending the lifetime of these
1076 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1077 sh_small_register_classes_for_mode_p
1079 /* The order in which register should be allocated. */
1080 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1081 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1082 spilled or used otherwise, we better have the FP_REGS allocated first. */
1083 #define REG_ALLOC_ORDER \
1084 {/* Caller-saved FPRs */ \
1085 65, 66, 67, 68, 69, 70, 71, 64, \
1086 72, 73, 74, 75, 80, 81, 82, 83, \
1087 84, 85, 86, 87, 88, 89, 90, 91, \
1088 92, 93, 94, 95, 96, 97, 98, 99, \
1089 /* Callee-saved FPRs */ \
1090 76, 77, 78, 79,100,101,102,103, \
1091 104,105,106,107,108,109,110,111, \
1092 112,113,114,115,116,117,118,119, \
1093 120,121,122,123,124,125,126,127, \
1094 136,137,138,139,140,141,142,143, \
1096 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1097 1, 2, 3, 7, 6, 5, 4, 0, \
1098 8, 9, 17, 19, 20, 21, 22, 23, \
1099 36, 37, 38, 39, 40, 41, 42, 43, \
1101 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1102 10, 11, 12, 13, 14, 18, \
1103 /* SH5 callee-saved GPRs */ \
1104 28, 29, 30, 31, 32, 33, 34, 35, \
1105 44, 45, 46, 47, 48, 49, 50, 51, \
1106 52, 53, 54, 55, 56, 57, 58, 59, \
1108 /* SH5 branch target registers */ \
1109 128,129,130,131,132,133,134,135, \
1110 /* Fixed registers */ \
1111 15, 16, 24, 25, 26, 27, 63,144, \
1112 145,146,147,148,149,152,153 }
1114 /* The class value for index registers, and the one for base regs. */
1115 #define INDEX_REG_CLASS \
1116 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1117 #define BASE_REG_CLASS GENERAL_REGS
1119 /* Defines for sh.md and constraints.md. */
1121 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1122 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1123 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1124 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1126 #define CONST_OK_FOR_J16(VALUE) \
1127 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1128 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1130 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1131 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1133 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1134 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1136 /* Return the maximum number of consecutive registers
1137 needed to represent mode MODE in a register of class CLASS.
1139 If TARGET_SHMEDIA, we need two FP registers per word.
1140 Otherwise we will need at most one register per word. */
1141 #define CLASS_MAX_NREGS(CLASS, MODE) \
1143 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1144 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1145 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1147 /* If defined, gives a class of registers that cannot be used as the
1148 operand of a SUBREG that changes the mode of the object illegally.
1149 ??? We need to renumber the internal numbers for the frnn registers
1150 when in little endian in order to allow mode size changes. */
1151 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1152 sh_cannot_change_mode_class (FROM, TO, CLASS)
1154 /* Stack layout; function entry, exit and calling. */
1156 /* Define the number of registers that can hold parameters.
1157 These macros are used only in other macro definitions below. */
1158 #define NPARM_REGS(MODE) \
1159 (TARGET_FPU_ANY && (MODE) == SFmode \
1160 ? (TARGET_SH5 ? 12 : 8) \
1161 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
1162 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1163 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1164 ? (TARGET_SH5 ? 12 : 8) \
1165 : (TARGET_SH5 ? 8 : 4))
1167 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1168 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1170 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1171 #define FIRST_FP_RET_REG FIRST_FP_REG
1173 /* Define this if pushing a word on the stack
1174 makes the stack pointer a smaller address. */
1175 #define STACK_GROWS_DOWNWARD
1177 /* Define this macro to nonzero if the addresses of local variable slots
1178 are at negative offsets from the frame pointer. */
1179 #define FRAME_GROWS_DOWNWARD 1
1181 /* Offset from the frame pointer to the first local variable slot to
1183 #define STARTING_FRAME_OFFSET 0
1185 /* If we generate an insn to push BYTES bytes,
1186 this says how many the stack pointer really advances by. */
1187 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1188 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1189 do correct alignment. */
1191 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1194 /* Offset of first parameter from the argument pointer register value. */
1195 #define FIRST_PARM_OFFSET(FNDECL) 0
1197 /* Value is the number of bytes of arguments automatically popped when
1198 calling a subroutine.
1199 CUM is the accumulated argument list.
1201 On SHcompact, the call trampoline pops arguments off the stack. */
1202 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1204 /* Some subroutine macros specific to this machine. */
1206 #define BASE_RETURN_VALUE_REG(MODE) \
1207 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1208 ? FIRST_FP_RET_REG \
1209 : TARGET_FPU_ANY && (MODE) == SCmode \
1210 ? FIRST_FP_RET_REG \
1211 : (TARGET_FPU_DOUBLE \
1212 && ((MODE) == DFmode || (MODE) == SFmode \
1213 || (MODE) == DCmode || (MODE) == SCmode )) \
1214 ? FIRST_FP_RET_REG \
1217 #define BASE_ARG_REG(MODE) \
1218 ((TARGET_SH2E && ((MODE) == SFmode)) \
1219 ? FIRST_FP_PARM_REG \
1220 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1221 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1222 ? FIRST_FP_PARM_REG \
1225 /* 1 if N is a possible register number for function argument passing. */
1226 /* ??? There are some callers that pass REGNO as int, and others that pass
1227 it as unsigned. We get warnings unless we do casts everywhere. */
1228 #define FUNCTION_ARG_REGNO_P(REGNO) \
1229 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1230 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1231 || (TARGET_FPU_ANY \
1232 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1233 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1234 + NPARM_REGS (SFmode))))
1236 /* Define a data type for recording info about an argument list
1237 during the scan of that argument list. This data type should
1238 hold all necessary information about the function itself
1239 and about the args processed so far, enough to enable macros
1240 such as FUNCTION_ARG to determine where the next arg should go.
1242 On SH, this is a single integer, which is a number of words
1243 of arguments scanned so far (including the invisible argument,
1244 if any, which holds the structure-value-address).
1245 Thus NARGREGS or more means all following args should go on the stack. */
1246 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1250 /* Nonzero if a prototype is available for the function. */
1252 /* The number of an odd floating-point register, that should be used
1253 for the next argument of type float. */
1254 int free_single_fp_reg;
1255 /* Whether we're processing an outgoing function call. */
1257 /* The number of general-purpose registers that should have been
1258 used to pass partial arguments, that are passed totally on the
1259 stack. On SHcompact, a call trampoline will pop them off the
1260 stack before calling the actual function, and, if the called
1261 function is implemented in SHcompact mode, the incoming arguments
1262 decoder will push such arguments back onto the stack. For
1263 incoming arguments, STACK_REGS also takes into account other
1264 arguments passed by reference, that the decoder will also push
1267 /* The number of general-purpose registers that should have been
1268 used to pass arguments, if the arguments didn't have to be passed
1271 /* Set as by shcompact_byref if the current argument is to be passed
1275 /* call_cookie is a bitmask used by call expanders, as well as
1276 function prologue and epilogues, to allow SHcompact to comply
1277 with the SH5 32-bit ABI, that requires 64-bit registers to be
1278 used even though only the lower 32-bit half is visible in
1279 SHcompact mode. The strategy is to call SHmedia trampolines.
1281 The alternatives for each of the argument-passing registers are
1282 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1283 contents from the address in it; (d) add 8 to it, storing the
1284 result in the next register, then (c); (e) copy it from some
1285 floating-point register,
1287 Regarding copies from floating-point registers, r2 may only be
1288 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1289 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1290 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1291 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1294 The bit mask is structured as follows:
1296 - 1 bit to tell whether to set up a return trampoline.
1298 - 3 bits to count the number consecutive registers to pop off the
1301 - 4 bits for each of r9, r8, r7 and r6.
1303 - 3 bits for each of r5, r4, r3 and r2.
1305 - 3 bits set to 0 (the most significant ones)
1308 1098 7654 3210 9876 5432 1098 7654 3210
1309 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1310 2223 3344 4555 6666 7777 8888 9999 SSS-
1312 - If F is set, the register must be copied from an FP register,
1313 whose number is encoded in the remaining bits.
1315 - Else, if L is set, the register must be loaded from the address
1316 contained in it. If the P bit is *not* set, the address of the
1317 following dword should be computed first, and stored in the
1320 - Else, if P is set, the register alone should be popped off the
1323 - After all this processing, the number of registers represented
1324 in SSS will be popped off the stack. This is an optimization
1325 for pushing/popping consecutive registers, typically used for
1326 varargs and large arguments partially passed in registers.
1328 - If T is set, a return trampoline will be set up for 64-bit
1329 return values to be split into 2 32-bit registers. */
1332 /* This is set to nonzero when the call in question must use the Renesas ABI,
1333 even without the -mrenesas option. */
1337 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1338 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1339 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1340 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1341 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1342 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1343 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1344 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1345 #define CALL_COOKIE_INT_REG(REG, VAL) \
1346 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1347 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1348 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1350 #define CUMULATIVE_ARGS struct sh_args
1352 #define GET_SH_ARG_CLASS(MODE) \
1353 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1355 /* There's no mention of complex float types in the SH5 ABI, so we
1356 should presumably handle them as aggregate types. */ \
1357 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1359 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1360 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1361 ? SH_ARG_FLOAT : SH_ARG_INT)
1363 #define ROUND_ADVANCE(SIZE) \
1364 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1366 /* Round a register number up to a proper boundary for an arg of mode
1369 The SH doesn't care about double alignment, so we only
1370 round doubles to even regs when asked to explicitly. */
1371 #define ROUND_REG(CUM, MODE) \
1372 (((TARGET_ALIGN_DOUBLE \
1373 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
1374 && ((MODE) == DFmode || (MODE) == DCmode) \
1375 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE))) \
1376 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1377 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1378 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1379 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1381 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1382 for a call to a function whose data type is FNTYPE.
1383 For a library call, FNTYPE is 0.
1385 On SH, the offset always starts at 0: the first parm reg is always
1386 the same reg for a given argument class.
1388 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1389 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1390 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
1391 (N_NAMED_ARGS), VOIDmode)
1393 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1394 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1396 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1397 This macro is only used in this file. */
1398 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1400 || (! TREE_ADDRESSABLE ((TYPE)) \
1401 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1402 || ! (AGGREGATE_TYPE_P (TYPE) \
1403 || (!TARGET_FPU_ANY \
1404 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1405 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1406 && ! (CUM).force_mem \
1408 ? ((MODE) == BLKmode \
1409 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1410 + int_size_in_bytes (TYPE)) \
1411 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1412 : ((ROUND_REG((CUM), (MODE)) \
1413 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1414 <= NPARM_REGS (MODE))) \
1415 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1417 /* By accident we got stuck with passing SCmode on SH4 little endian
1418 in two registers that are nominally successive - which is different from
1419 two single SFmode values, where we take endianness translation into
1420 account. That does not work at all if an odd number of registers is
1421 already in use, so that got fixed, but library functions are still more
1422 likely to use complex numbers without mixing them with SFmode arguments
1423 (which in C would have to be structures), so for the sake of ABI
1424 compatibility the way SCmode values are passed when an even number of
1425 FP registers is in use remains different from a pair of SFmode values for
1428 foo (double); a: fr5,fr4
1429 foo (float a, float b); a: fr5 b: fr4
1430 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1431 this should be the other way round...
1432 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1433 #define FUNCTION_ARG_SCmode_WART 1
1435 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1436 register in SHcompact mode, it must be padded in the most
1437 significant end. This means that passing it by reference wouldn't
1438 pad properly on a big-endian machine. In this particular case, we
1439 pass this argument on the stack, in a way that the call trampoline
1440 will load its value into the appropriate register. */
1441 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1442 ((MODE) == BLKmode \
1443 && TARGET_SHCOMPACT \
1444 && ! TARGET_LITTLE_ENDIAN \
1445 && int_size_in_bytes (TYPE) > 4 \
1446 && int_size_in_bytes (TYPE) < 8)
1448 /* Minimum alignment for an argument to be passed by callee-copy
1449 reference. We need such arguments to be aligned to 8 byte
1450 boundaries, because they'll be loaded using quad loads. */
1451 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1453 /* The SH5 ABI requires floating-point arguments to be passed to
1454 functions without a prototype in both an FP register and a regular
1455 register or the stack. When passing the argument in both FP and
1456 general-purpose registers, list the FP register first. */
1457 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1463 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1464 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1465 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1470 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1471 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1472 + (CUM).arg_count[(int) SH_ARG_INT]) \
1473 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1474 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1477 /* The SH5 ABI requires regular registers or stack slots to be
1478 reserved for floating-point arguments. Registers are taken care of
1479 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1480 Unfortunately, there's no way to just reserve a stack slot, so
1481 we'll end up needlessly storing a copy of the argument in the
1482 stack. For incoming arguments, however, the PARALLEL will be
1483 optimized to the register-only form, and the value in the stack
1484 slot won't be used at all. */
1485 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1486 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1487 ? gen_rtx_REG ((MODE), (REG)) \
1488 : gen_rtx_PARALLEL ((MODE), \
1491 (VOIDmode, NULL_RTX, \
1494 (VOIDmode, gen_rtx_REG ((MODE), \
1498 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1500 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1501 || (MODE) == DCmode) \
1502 && ((CUM).arg_count[(int) SH_ARG_INT] \
1503 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1504 : GET_MODE_SIZE (MODE)) \
1505 + 7) / 8) > NPARM_REGS (SImode))
1507 /* Perform any needed actions needed for a function that is receiving a
1508 variable number of arguments. */
1510 /* Call the function profiler with a given profile label.
1511 We use two .aligns, so as to make sure that both the .long is aligned
1512 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1513 from the trapa instruction. */
1514 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1516 if (TARGET_SHMEDIA) \
1518 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1519 fprintf((STREAM), "\ttrapa\tr0\n"); \
1520 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1524 fprintf((STREAM), "\t.align\t2\n"); \
1525 fprintf((STREAM), "\ttrapa\t#33\n"); \
1526 fprintf((STREAM), "\t.align\t2\n"); \
1527 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1531 /* Define this macro if the code for function profiling should come
1532 before the function prologue. Normally, the profiling code comes
1534 #define PROFILE_BEFORE_PROLOGUE
1536 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1537 the stack pointer does not matter. The value is tested only in
1538 functions that have frame pointers.
1539 No definition is equivalent to always zero. */
1540 #define EXIT_IGNORE_STACK 1
1543 On the SH, the trampoline looks like
1544 2 0002 D202 mov.l l2,r2
1545 1 0000 D301 mov.l l1,r3
1548 5 0008 00000000 l1: .long area
1549 6 000c 00000000 l2: .long function */
1551 /* Length in units of the trampoline for entering a nested function. */
1552 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1554 /* Alignment required for a trampoline in bits. */
1555 #define TRAMPOLINE_ALIGNMENT \
1557 || (optimize_size && ! (TARGET_HARD_SH4 || TARGET_SH5))) ? 32 \
1558 : TARGET_SHMEDIA ? 256 : 64)
1560 /* A C expression whose value is RTL representing the value of the return
1561 address for the frame COUNT steps up from the current frame.
1562 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1563 can ignore COUNT. */
1564 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1565 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
1567 /* A C expression whose value is RTL representing the location of the
1568 incoming return address at the beginning of any function, before the
1569 prologue. This RTL is either a REG, indicating that the return
1570 value is saved in REG, or a MEM representing a location in
1572 #define INCOMING_RETURN_ADDR_RTX \
1573 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1575 /* Addressing modes, and classification of registers for them. */
1576 #define HAVE_POST_INCREMENT TARGET_SH1
1577 #define HAVE_PRE_DECREMENT TARGET_SH1
1579 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1581 #define USE_LOAD_PRE_DECREMENT(mode) 0
1582 #define USE_STORE_POST_INCREMENT(mode) 0
1583 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1586 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1587 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1588 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1590 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1591 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1592 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1594 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1596 /* Macros to check register numbers against specific register classes. */
1598 /* These assume that REGNO is a hard or pseudo reg number.
1599 They give nonzero only if REGNO is a hard reg of the suitable class
1600 or a pseudo reg currently allocated to a suitable hard reg.
1601 Since they use reg_renumber, they are safe only once reg_renumber
1602 has been allocated, which happens in reginfo.c during register
1604 #define REGNO_OK_FOR_BASE_P(REGNO) \
1605 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1606 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1607 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1609 ? (GENERAL_REGISTER_P (REGNO) \
1610 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1611 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1613 /* Maximum number of registers that can appear in a valid memory
1615 #define MAX_REGS_PER_ADDRESS 2
1617 /* Recognize any constant value that is a valid address. */
1618 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1620 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1621 and check its validity for a certain class.
1622 The suitable hard regs are always accepted and all pseudo regs
1623 are also accepted if STRICT is not set. */
1625 /* Nonzero if X is a reg that can be used as a base reg. */
1626 #define REG_OK_FOR_BASE_P(X, STRICT) \
1627 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1628 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1630 /* Nonzero if X is a reg that can be used as an index. */
1631 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1632 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1633 : REGNO (X) == R0_REG) \
1634 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1636 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1637 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1638 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1639 : REGNO (X) == R0_REG && OFFSET == 0) \
1640 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1642 /* Macros for extra constraints. */
1644 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1645 ((GET_CODE ((OP)) == LABEL_REF) \
1646 || (GET_CODE ((OP)) == CONST \
1647 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1648 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1649 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1651 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1653 && !CONST_INT_P (OP) \
1654 && GET_CODE (OP) != CONST_DOUBLE \
1656 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1657 && !PIC_ADDR_P (OP) \
1658 && GET_CODE (OP) != LABEL_REF)))
1660 /* Check whether OP is a datalabel unspec. */
1661 #define DATALABEL_REF_NO_CONST_P(OP) \
1662 (GET_CODE (OP) == UNSPEC \
1663 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1664 && XVECLEN ((OP), 0) == 1 \
1665 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1667 #define GOT_ENTRY_P(OP) \
1668 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1669 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1671 #define GOTPLT_ENTRY_P(OP) \
1672 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1673 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1675 #define UNSPEC_GOTOFF_P(OP) \
1676 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1678 #define GOTOFF_P(OP) \
1679 (GET_CODE (OP) == CONST \
1680 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1681 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1682 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1683 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1685 #define PIC_ADDR_P(OP) \
1686 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1687 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1689 #define PCREL_SYMOFF_P(OP) \
1690 (GET_CODE (OP) == CONST \
1691 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1692 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1694 #define NON_PIC_REFERENCE_P(OP) \
1695 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1696 || (GET_CODE (OP) == CONST \
1697 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1698 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1699 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1700 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1701 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1702 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1703 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1704 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1706 #define PIC_REFERENCE_P(OP) \
1707 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1708 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1710 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1712 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1713 || PCREL_SYMOFF_P (OP)) \
1714 : NON_PIC_REFERENCE_P (OP))
1716 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1717 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1718 || (GET_CODE (X) == SUBREG \
1719 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1720 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1721 && REG_P (SUBREG_REG (X)) \
1722 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1724 /* Since this must be r0, which is a single register class, we must check
1725 SUBREGs more carefully, to be sure that we don't accept one that extends
1726 outside the class. */
1727 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1728 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1729 || (GET_CODE (X) == SUBREG \
1730 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1731 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1732 && REG_P (SUBREG_REG (X)) \
1733 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1735 #ifdef REG_OK_STRICT
1736 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1737 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1739 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1740 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1743 #define ALLOW_INDEXED_ADDRESS \
1744 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1746 /* A C compound statement that attempts to replace X, which is an address
1747 that needs reloading, with a valid memory address for an operand of
1748 mode MODE. WIN is a C statement label elsewhere in the code. */
1749 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1751 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1755 /* Specify the machine mode that this machine uses
1756 for the index in the tablejump instruction. */
1757 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1759 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1760 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1761 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1762 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1763 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1764 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1767 /* Define as C expression which evaluates to nonzero if the tablejump
1768 instruction expects the table to contain offsets from the address of the
1770 Do not define this if the table should contain absolute addresses. */
1771 #define CASE_VECTOR_PC_RELATIVE 1
1773 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1774 #define FLOAT_TYPE_SIZE 32
1776 /* Since the SH2e has only `float' support, it is desirable to make all
1777 floating point types equivalent to `float'. */
1778 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE)\
1781 /* 'char' is signed by default. */
1782 #define DEFAULT_SIGNED_CHAR 1
1784 /* The type of size_t unsigned int. */
1785 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
1788 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
1790 #define WCHAR_TYPE "short unsigned int"
1791 #define WCHAR_TYPE_SIZE 16
1793 #define SH_ELF_WCHAR_TYPE "long int"
1795 /* Max number of bytes we can move from memory to memory
1796 in one reasonably fast instruction. */
1797 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
1799 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1800 MOVE_MAX is not a compile-time constant. */
1801 #define MAX_MOVE_MAX 8
1803 /* Max number of bytes we want move_by_pieces to be able to copy
1805 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
1807 /* Define if operations between registers always perform the operation
1808 on the full register even if a narrower mode is specified. */
1809 #define WORD_REGISTER_OPERATIONS
1811 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1812 will either zero-extend or sign-extend. The value of this macro should
1813 be the code that says which one of the two operations is implicitly
1814 done, UNKNOWN if none.
1815 For SHmedia, we can truncate to QImode easier using zero extension.
1816 FP registers can load SImode values, but don't implicitly sign-extend
1818 #define LOAD_EXTEND_OP(MODE) \
1819 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
1820 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1822 /* Define if loading short immediate values into registers sign extends. */
1823 #define SHORT_IMMEDIATES_SIGN_EXTEND
1825 /* Nonzero if access to memory by bytes is no faster than for words. */
1826 #define SLOW_BYTE_ACCESS 1
1828 /* Nonzero if the target supports dynamic shift instructions
1829 like shad and shld. */
1830 #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
1832 /* The cost of using the dynamic shift insns (shad, shld) are the same
1833 if they are available. If they are not available a library function will
1834 be emitted instead, which is more expensive. */
1835 #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20)
1837 /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like
1838 (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1839 This is not generally true when hardware dynamic shifts (shad, shld) are
1840 used, because they check the sign bit _before_ the modulo op. The sign
1841 bit determines whether it is a left shift or a right shift:
1843 return X << (Y & 31);
1845 return X >> (-Y) & 31);
1847 The dynamic shift library routines in lib1funcs.S do not use the sign bit
1848 like the hardware dynamic shifts and truncate the shift count to 31.
1849 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count
1850 truncation in the library function call patterns, as this gives slightly
1851 more compact code. */
1852 #define SHIFT_COUNT_TRUNCATED (0)
1854 /* All integers have the same format so truncation is easy. */
1855 /* But SHmedia must sign-extend DImode when truncating to SImode. */
1856 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
1857 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
1859 /* Define this if addresses of constant functions
1860 shouldn't be put through pseudo regs where they can be cse'd.
1861 Desirable on machines where ordinary constants are expensive
1862 but a CALL with constant address is cheap. */
1863 /*#define NO_FUNCTION_CSE 1*/
1865 /* The machine modes of pointers and functions. */
1866 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
1867 #define FUNCTION_MODE Pmode
1869 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1870 are actually function calls with some special constraints on arguments
1873 These macros tell reorg that the references to arguments and
1874 register clobbers for insns of type sfunc do not appear to happen
1875 until after the millicode call. This allows reorg to put insns
1876 which set the argument registers into the delay slot of the millicode
1877 call -- thus they act more like traditional CALL_INSNs.
1879 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1880 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1883 #define INSN_SETS_ARE_DELAYED(X) \
1884 ((NONJUMP_INSN_P (X) \
1885 && GET_CODE (PATTERN (X)) != SEQUENCE \
1886 && GET_CODE (PATTERN (X)) != USE \
1887 && GET_CODE (PATTERN (X)) != CLOBBER \
1888 && get_attr_is_sfunc (X)))
1890 #define INSN_REFERENCES_ARE_DELAYED(X) \
1891 ((NONJUMP_INSN_P (X) \
1892 && GET_CODE (PATTERN (X)) != SEQUENCE \
1893 && GET_CODE (PATTERN (X)) != USE \
1894 && GET_CODE (PATTERN (X)) != CLOBBER \
1895 && get_attr_is_sfunc (X)))
1898 /* Position Independent Code. */
1900 /* We can't directly access anything that contains a symbol,
1901 nor can we indirect via the constant pool. */
1902 #define LEGITIMATE_PIC_OPERAND_P(X) \
1903 ((! nonpic_symbol_mentioned_p (X) \
1904 && (GET_CODE (X) != SYMBOL_REF \
1905 || ! CONSTANT_POOL_ADDRESS_P (X) \
1906 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
1907 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
1909 #define SYMBOLIC_CONST_P(X) \
1910 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1911 && nonpic_symbol_mentioned_p (X))
1913 /* Compute extra cost of moving data between one register class
1916 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
1917 uses this information. Hence, the general register <-> floating point
1918 register information here is not used for SFmode. */
1919 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
1920 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
1921 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
1923 #define REGCLASS_HAS_FP_REG(CLASS) \
1924 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
1925 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
1927 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1928 would be so that people with slow memory systems could generate
1929 different code that does fewer memory accesses. */
1931 /* A C expression for the cost of a branch instruction. A value of 1
1932 is the default; other values are interpreted relative to that. */
1933 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
1935 /* Assembler output control. */
1937 /* A C string constant describing how to begin a comment in the target
1938 assembler language. The compiler assumes that the comment will end at
1939 the end of the line. */
1940 #define ASM_COMMENT_START "!"
1942 #define ASM_APP_ON ""
1943 #define ASM_APP_OFF ""
1944 #define FILE_ASM_OP "\t.file\n"
1945 #define SET_ASM_OP "\t.set\t"
1947 /* How to change between sections. */
1948 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 \
1949 ? "\t.section\t.text..SHmedia32,\"ax\"" \
1951 #define DATA_SECTION_ASM_OP "\t.data"
1953 #if defined CRT_BEGIN || defined CRT_END
1954 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
1955 # undef TEXT_SECTION_ASM_OP
1956 # if __SHMEDIA__ == 1 && __SH5__ == 32
1957 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
1959 # define TEXT_SECTION_ASM_OP "\t.text"
1963 #ifndef BSS_SECTION_ASM_OP
1964 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1967 #ifndef ASM_OUTPUT_ALIGNED_BSS
1968 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1969 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1972 /* Define this so that jump tables go in same section as the current function,
1973 which could be text or it could be a user defined section. */
1974 #define JUMP_TABLES_IN_TEXT_SECTION 1
1976 #undef DO_GLOBAL_CTORS_BODY
1977 #define DO_GLOBAL_CTORS_BODY \
1979 typedef void (*pfunc) (void); \
1980 extern pfunc __ctors[]; \
1981 extern pfunc __ctors_end[]; \
1983 for (p = __ctors_end; p > __ctors; ) \
1989 #undef DO_GLOBAL_DTORS_BODY
1990 #define DO_GLOBAL_DTORS_BODY \
1992 typedef void (*pfunc) (void); \
1993 extern pfunc __dtors[]; \
1994 extern pfunc __dtors_end[]; \
1996 for (p = __dtors; p < __dtors_end; p++) \
2002 #define ASM_OUTPUT_REG_PUSH(file, v) \
2004 if (TARGET_SHMEDIA) \
2006 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2007 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2010 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2013 #define ASM_OUTPUT_REG_POP(file, v) \
2015 if (TARGET_SHMEDIA) \
2017 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2018 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2021 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2024 /* DBX register number for a given compiler register number. */
2025 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2027 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2028 register exists, so we should return -1 for invalid register numbers. */
2029 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2031 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2032 used to use the encodings 245..260, but that doesn't make sense:
2033 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2034 the FP registers stay the same when switching between compact and media
2035 mode. Hence, we also need to use the same dwarf frame columns.
2036 Likewise, we need to support unwind information for SHmedia registers
2037 even in compact code. */
2038 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2039 (IN_RANGE ((REGNO), \
2040 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2041 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2042 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2043 : ((int) (REGNO) >= FIRST_FP_REG \
2045 <= (FIRST_FP_REG + \
2046 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2047 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2048 + (TARGET_SH5 ? 77 : 25)) \
2049 : XD_REGISTER_P (REGNO) \
2050 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2051 : TARGET_REGISTER_P (REGNO) \
2052 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2053 : (REGNO) == PR_REG \
2054 ? (TARGET_SH5 ? 18 : 17) \
2055 : (REGNO) == PR_MEDIA_REG \
2056 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2057 : (REGNO) == GBR_REG \
2058 ? (TARGET_SH5 ? 238 : 18) \
2059 : (REGNO) == MACH_REG \
2060 ? (TARGET_SH5 ? 239 : 20) \
2061 : (REGNO) == MACL_REG \
2062 ? (TARGET_SH5 ? 240 : 21) \
2063 : (REGNO) == T_REG \
2064 ? (TARGET_SH5 ? 242 : 22) \
2065 : (REGNO) == FPUL_REG \
2066 ? (TARGET_SH5 ? 244 : 23) \
2067 : (REGNO) == FPSCR_REG \
2068 ? (TARGET_SH5 ? 243 : 24) \
2071 /* This is how to output a reference to a symbol_ref. On SH5,
2072 references to non-code symbols must be preceded by `datalabel'. */
2073 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2076 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2077 fputs ("datalabel ", (FILE)); \
2078 assemble_name ((FILE), XSTR ((SYM), 0)); \
2082 /* This is how to output an assembler line
2083 that says to advance the location counter
2084 to a multiple of 2**LOG bytes. */
2086 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2088 fprintf ((FILE), "\t.align %d\n", (LOG))
2090 /* Globalizing directive for a label. */
2091 #define GLOBAL_ASM_OP "\t.global\t"
2093 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2095 /* Output a relative address table. */
2096 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2097 switch (GET_MODE (BODY)) \
2102 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2106 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2111 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2115 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2120 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2124 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2130 /* Output an absolute table element. */
2131 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2132 if (! optimize || TARGET_BIGTABLE) \
2133 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2135 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2138 /* A C statement to be executed just prior to the output of
2139 assembler code for INSN, to modify the extracted operands so
2140 they will be output differently.
2142 Here the argument OPVEC is the vector containing the operands
2143 extracted from INSN, and NOPERANDS is the number of elements of
2144 the vector which contain meaningful data for this insn.
2145 The contents of this vector are what will be used to convert the insn
2146 template into assembler code, so you can change the assembler output
2147 by changing the contents of the vector. */
2148 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2149 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2152 extern rtx sh_compare_op0;
2153 extern rtx sh_compare_op1;
2155 /* Which processor to schedule for. The elements of the enumeration must
2156 match exactly the cpu attribute in the sh.md file. */
2157 enum processor_type {
2169 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2170 extern enum processor_type sh_cpu;
2172 enum mdep_reorg_phase_e
2174 SH_BEFORE_MDEP_REORG,
2175 SH_INSERT_USES_LABELS,
2176 SH_SHORTEN_BRANCHES0,
2178 SH_SHORTEN_BRANCHES1,
2182 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2184 /* Handle Renesas compiler's pragmas. */
2185 #define REGISTER_TARGET_PRAGMAS() do { \
2186 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2187 c_register_pragma (0, "trapa", sh_pr_trapa); \
2188 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2191 extern tree sh_deferred_function_attributes;
2192 extern tree *sh_deferred_function_attributes_tail;
2194 /* Set when processing a function with interrupt attribute. */
2195 extern int current_function_interrupt;
2198 /* Instructions with unfilled delay slots take up an
2199 extra two bytes for the nop in the delay slot.
2200 sh-dsp parallel processing insns are four bytes long. */
2201 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2202 (LENGTH) += sh_insn_length_adjustment (X);
2204 /* Define this macro if it is advisable to hold scalars in registers
2205 in a wider mode than that declared by the program. In such cases,
2206 the value is constrained to be within the bounds of the declared
2207 type, but kept valid in the wider mode. The signedness of the
2208 extension may differ from that of the type.
2210 Leaving the unsignedp unchanged gives better code than always setting it
2211 to 0. This is despite the fact that we have only signed char and short
2212 load instructions. */
2213 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2214 if (GET_MODE_CLASS (MODE) == MODE_INT \
2215 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2216 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2217 (MODE) = (TARGET_SH1 ? SImode \
2218 : TARGET_SHMEDIA32 ? SImode : DImode);
2220 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2222 /* Better to allocate once the maximum space for outgoing args in the
2223 prologue rather than duplicate around each call. */
2224 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2226 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2228 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2230 #define ACTUAL_NORMAL_MODE(ENTITY) \
2231 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2233 #define NORMAL_MODE(ENTITY) \
2234 (sh_cfun_interrupt_handler_p () \
2235 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2236 : ACTUAL_NORMAL_MODE (ENTITY))
2238 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2240 #define MODE_EXIT(ENTITY) \
2241 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2243 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2244 && (REGNO) == FPSCR_REG)
2246 #define MODE_NEEDED(ENTITY, INSN) \
2247 (recog_memoized (INSN) >= 0 \
2248 ? get_attr_fp_mode (INSN) \
2251 #define MODE_AFTER(ENTITY, MODE, INSN) \
2253 && recog_memoized (INSN) >= 0 \
2254 && get_attr_fp_set (INSN) != FP_SET_NONE \
2255 ? (int) get_attr_fp_set (INSN) \
2258 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2259 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2261 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2262 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2264 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2265 sh_can_redirect_branch ((INSN), (SEQ))
2267 #define DWARF_FRAME_RETURN_COLUMN \
2268 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2270 #define EH_RETURN_DATA_REGNO(N) \
2271 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2273 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2274 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2276 /* We have to distinguish between code and data, so that we apply
2277 datalabel where and only where appropriate. Use sdataN for data. */
2278 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2279 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2280 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2281 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2283 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2284 indirect are handled automatically. */
2285 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2287 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2288 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2290 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2291 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2296 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2297 /* SH constant pool breaks the devices in crtstuff.c to control section
2298 in where code resides. We have to write it as asm code. */
2299 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2300 asm (SECTION_OP "\n\
2306 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2307 2:\n" TEXT_SECTION_ASM_OP);
2308 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2310 #endif /* ! GCC_SH_H */
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