1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "insn-config.h"
37 #include "hard-reg-set.h"
39 #include "insn-attr.h"
40 #include "diagnostic-core.h"
42 #include "integrate.h"
46 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
57 #include "alloc-pool.h"
58 #include "tm-constrs.h"
62 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
64 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
65 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
67 /* These are some macros to abstract register modes. */
68 #define CONST_OK_FOR_ADD(size) \
69 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
70 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
71 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
72 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
74 /* Used to simplify the logic below. Find the attributes wherever
76 #define SH_ATTRIBUTES(decl) \
77 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
78 : DECL_ATTRIBUTES (decl) \
79 ? (DECL_ATTRIBUTES (decl)) \
80 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
82 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
83 int current_function_interrupt;
85 tree sh_deferred_function_attributes;
86 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
88 /* Global variables for machine-dependent things. */
90 /* Which cpu are we scheduling for. */
91 enum processor_type sh_cpu;
93 /* Definitions used in ready queue reordering for first scheduling pass. */
95 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
96 static short *regmode_weight[2];
98 /* Total SFmode and SImode weights of scheduled insns. */
99 static int curr_regmode_pressure[2];
101 /* Number of r0 life regions. */
102 static int r0_life_regions;
104 /* If true, skip cycles for Q -> R movement. */
105 static int skip_cycles = 0;
107 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
108 and returned from sh_reorder2. */
109 static short cached_can_issue_more;
111 /* Unique number for UNSPEC_BBR pattern. */
112 static unsigned int unspec_bbr_uid = 1;
114 /* Provides the class number of the smallest class containing
117 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
119 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
156 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
157 GENERAL_REGS, GENERAL_REGS,
160 char sh_register_names[FIRST_PSEUDO_REGISTER] \
161 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
163 char sh_additional_register_names[ADDREGNAMES_SIZE] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
167 int assembler_dialect;
169 static bool shmedia_space_reserved_for_target_registers;
171 static void split_branches (rtx);
172 static int branch_dest (rtx);
173 static void force_into (rtx, rtx);
174 static void print_slot (rtx);
175 static rtx add_constant (rtx, enum machine_mode, rtx);
176 static void dump_table (rtx, rtx);
177 static int hi_const (rtx);
178 static int broken_move (rtx);
179 static int mova_p (rtx);
180 static rtx find_barrier (int, rtx, rtx);
181 static int noncall_uses_reg (rtx, rtx, rtx *);
182 static rtx gen_block_redirect (rtx, int, int);
183 static void sh_reorg (void);
184 static void sh_option_override (void);
185 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
186 static rtx frame_insn (rtx);
187 static rtx push (int);
188 static void pop (int);
189 static void push_regs (HARD_REG_SET *, int);
190 static int calc_live_regs (HARD_REG_SET *);
191 static HOST_WIDE_INT rounded_frame_size (int);
192 static bool sh_frame_pointer_required (void);
193 static rtx mark_constant_pool_use (rtx);
194 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_resbank_handler_attribute (tree *, tree,
197 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
199 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
200 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
202 static void sh_print_operand (FILE *, rtx, int);
203 static void sh_print_operand_address (FILE *, rtx);
204 static bool sh_print_operand_punct_valid_p (unsigned char code);
205 static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);
206 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
207 static void sh_insert_attributes (tree, tree *);
208 static const char *sh_check_pch_target_flags (int);
209 static int sh_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
210 static int sh_adjust_cost (rtx, rtx, rtx, int);
211 static int sh_issue_rate (void);
212 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
213 static short find_set_regmode_weight (rtx, enum machine_mode);
214 static short find_insn_regmode_weight (rtx, enum machine_mode);
215 static void find_regmode_weight (basic_block, enum machine_mode);
216 static int find_r0_life_regions (basic_block);
217 static void sh_md_init_global (FILE *, int, int);
218 static void sh_md_finish_global (FILE *, int);
219 static int rank_for_reorder (const void *, const void *);
220 static void swap_reorder (rtx *, int);
221 static void ready_reorder (rtx *, int);
222 static short high_pressure (enum machine_mode);
223 static int sh_reorder (FILE *, int, rtx *, int *, int);
224 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
225 static void sh_md_init (FILE *, int, int);
226 static int sh_variable_issue (FILE *, int, rtx, int);
228 static bool sh_function_ok_for_sibcall (tree, tree);
230 static bool sh_cannot_modify_jumps_p (void);
231 static reg_class_t sh_target_reg_class (void);
232 static bool sh_optimize_target_register_callee_saved (bool);
233 static bool sh_ms_bitfield_layout_p (const_tree);
235 static void sh_init_builtins (void);
236 static tree sh_builtin_decl (unsigned, bool);
237 static void sh_media_init_builtins (void);
238 static tree sh_media_builtin_decl (unsigned, bool);
239 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
240 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
241 static void sh_file_start (void);
242 static int flow_dependent_p (rtx, rtx);
243 static void flow_dependent_p_1 (rtx, const_rtx, void *);
244 static int shiftcosts (rtx);
245 static int and_xor_ior_costs (rtx, int);
246 static int addsubcosts (rtx);
247 static int multcosts (rtx);
248 static bool unspec_caller_rtx_p (rtx);
249 static bool sh_cannot_copy_insn_p (rtx);
250 static bool sh_rtx_costs (rtx, int, int, int, int *, bool);
251 static int sh_address_cost (rtx, bool);
252 static int sh_pr_n_sets (void);
253 static rtx sh_allocate_initial_value (rtx);
254 static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);
255 static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
257 struct secondary_reload_info *);
258 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
259 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
260 static rtx sh_delegitimize_address (rtx);
261 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
262 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
263 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
264 static int scavenge_reg (HARD_REG_SET *s);
265 struct save_schedule_s;
266 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
267 struct save_schedule_s *, int);
269 static rtx sh_struct_value_rtx (tree, int);
270 static rtx sh_function_value (const_tree, const_tree, bool);
271 static bool sh_function_value_regno_p (const unsigned int);
272 static rtx sh_libcall_value (enum machine_mode, const_rtx);
273 static bool sh_return_in_memory (const_tree, const_tree);
274 static rtx sh_builtin_saveregs (void);
275 static void sh_setup_incoming_varargs (cumulative_args_t, enum machine_mode, tree, int *, int);
276 static bool sh_strict_argument_naming (cumulative_args_t);
277 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t);
278 static tree sh_build_builtin_va_list (void);
279 static void sh_va_start (tree, rtx);
280 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
281 static bool sh_promote_prototypes (const_tree);
282 static enum machine_mode sh_promote_function_mode (const_tree type,
287 static bool sh_pass_by_reference (cumulative_args_t, enum machine_mode,
289 static bool sh_callee_copies (cumulative_args_t, enum machine_mode,
291 static int sh_arg_partial_bytes (cumulative_args_t, enum machine_mode,
293 static void sh_function_arg_advance (cumulative_args_t, enum machine_mode,
295 static rtx sh_function_arg (cumulative_args_t, enum machine_mode,
297 static bool sh_scalar_mode_supported_p (enum machine_mode);
298 static int sh_dwarf_calling_convention (const_tree);
299 static void sh_encode_section_info (tree, rtx, int);
300 static int sh2a_function_vector_p (tree);
301 static void sh_trampoline_init (rtx, tree, rtx);
302 static rtx sh_trampoline_adjust_address (rtx);
303 static void sh_conditional_register_usage (void);
304 static bool sh_legitimate_constant_p (enum machine_mode, rtx);
306 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
308 static const struct attribute_spec sh_attribute_table[] =
310 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
311 affects_type_identity } */
312 { "interrupt_handler", 0, 0, true, false, false,
313 sh_handle_interrupt_handler_attribute, false },
314 { "sp_switch", 1, 1, true, false, false,
315 sh_handle_sp_switch_attribute, false },
316 { "trap_exit", 1, 1, true, false, false,
317 sh_handle_trap_exit_attribute, false },
318 { "renesas", 0, 0, false, true, false,
319 sh_handle_renesas_attribute, false },
320 { "trapa_handler", 0, 0, true, false, false,
321 sh_handle_interrupt_handler_attribute, false },
322 { "nosave_low_regs", 0, 0, true, false, false,
323 sh_handle_interrupt_handler_attribute, false },
324 { "resbank", 0, 0, true, false, false,
325 sh_handle_resbank_handler_attribute, false },
326 { "function_vector", 1, 1, true, false, false,
327 sh2a_handle_function_vector_handler_attribute, false },
328 { NULL, 0, 0, false, false, false, NULL, false }
331 /* Initialize the GCC target structure. */
332 #undef TARGET_ATTRIBUTE_TABLE
333 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
335 /* The next two are used for debug info when compiling with -gdwarf. */
336 #undef TARGET_ASM_UNALIGNED_HI_OP
337 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
338 #undef TARGET_ASM_UNALIGNED_SI_OP
339 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
341 /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
342 #undef TARGET_ASM_UNALIGNED_DI_OP
343 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
344 #undef TARGET_ASM_ALIGNED_DI_OP
345 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
347 #undef TARGET_OPTION_OVERRIDE
348 #define TARGET_OPTION_OVERRIDE sh_option_override
350 #undef TARGET_PRINT_OPERAND
351 #define TARGET_PRINT_OPERAND sh_print_operand
352 #undef TARGET_PRINT_OPERAND_ADDRESS
353 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
354 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
355 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
356 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
357 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
359 #undef TARGET_ASM_FUNCTION_EPILOGUE
360 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
362 #undef TARGET_ASM_OUTPUT_MI_THUNK
363 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
365 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
366 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
368 #undef TARGET_ASM_FILE_START
369 #define TARGET_ASM_FILE_START sh_file_start
370 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
371 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
373 #undef TARGET_REGISTER_MOVE_COST
374 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
376 #undef TARGET_INSERT_ATTRIBUTES
377 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
379 #undef TARGET_SCHED_ADJUST_COST
380 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
382 #undef TARGET_SCHED_ISSUE_RATE
383 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
385 /* The next 5 hooks have been implemented for reenabling sched1. With the
386 help of these macros we are limiting the movement of insns in sched1 to
387 reduce the register pressure. The overall idea is to keep count of SImode
388 and SFmode regs required by already scheduled insns. When these counts
389 cross some threshold values; give priority to insns that free registers.
390 The insn that frees registers is most likely to be the insn with lowest
391 LUID (original insn order); but such an insn might be there in the stalled
392 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
393 upto a max of 8 cycles so that such insns may move from Q -> R.
395 The description of the hooks are as below:
397 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
398 scheduler; it is called inside the sched_init function just after
399 find_insn_reg_weights function call. It is used to calculate the SImode
400 and SFmode weights of insns of basic blocks; much similar to what
401 find_insn_reg_weights does.
402 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
404 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
405 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
408 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
409 high; reorder the ready queue so that the insn with lowest LUID will be
412 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
413 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
415 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
416 can be returned from TARGET_SCHED_REORDER2.
418 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
420 #undef TARGET_SCHED_DFA_NEW_CYCLE
421 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
423 #undef TARGET_SCHED_INIT_GLOBAL
424 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
426 #undef TARGET_SCHED_FINISH_GLOBAL
427 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
429 #undef TARGET_SCHED_VARIABLE_ISSUE
430 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
432 #undef TARGET_SCHED_REORDER
433 #define TARGET_SCHED_REORDER sh_reorder
435 #undef TARGET_SCHED_REORDER2
436 #define TARGET_SCHED_REORDER2 sh_reorder2
438 #undef TARGET_SCHED_INIT
439 #define TARGET_SCHED_INIT sh_md_init
441 #undef TARGET_DELEGITIMIZE_ADDRESS
442 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
444 #undef TARGET_LEGITIMIZE_ADDRESS
445 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
447 #undef TARGET_CANNOT_MODIFY_JUMPS_P
448 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
449 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
450 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
451 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
452 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
453 sh_optimize_target_register_callee_saved
455 #undef TARGET_MS_BITFIELD_LAYOUT_P
456 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
458 #undef TARGET_INIT_BUILTINS
459 #define TARGET_INIT_BUILTINS sh_init_builtins
460 #undef TARGET_BUILTIN_DECL
461 #define TARGET_BUILTIN_DECL sh_builtin_decl
462 #undef TARGET_EXPAND_BUILTIN
463 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
465 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
466 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
468 #undef TARGET_CANNOT_COPY_INSN_P
469 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
470 #undef TARGET_RTX_COSTS
471 #define TARGET_RTX_COSTS sh_rtx_costs
472 #undef TARGET_ADDRESS_COST
473 #define TARGET_ADDRESS_COST sh_address_cost
474 #undef TARGET_ALLOCATE_INITIAL_VALUE
475 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
477 #undef TARGET_MACHINE_DEPENDENT_REORG
478 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
480 #undef TARGET_DWARF_REGISTER_SPAN
481 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
484 #undef TARGET_HAVE_TLS
485 #define TARGET_HAVE_TLS true
488 #undef TARGET_PROMOTE_PROTOTYPES
489 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
490 #undef TARGET_PROMOTE_FUNCTION_MODE
491 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
493 #undef TARGET_FUNCTION_VALUE
494 #define TARGET_FUNCTION_VALUE sh_function_value
495 #undef TARGET_FUNCTION_VALUE_REGNO_P
496 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
497 #undef TARGET_LIBCALL_VALUE
498 #define TARGET_LIBCALL_VALUE sh_libcall_value
499 #undef TARGET_STRUCT_VALUE_RTX
500 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
501 #undef TARGET_RETURN_IN_MEMORY
502 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
504 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
505 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
506 #undef TARGET_SETUP_INCOMING_VARARGS
507 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
508 #undef TARGET_STRICT_ARGUMENT_NAMING
509 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
510 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
511 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
512 #undef TARGET_MUST_PASS_IN_STACK
513 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
514 #undef TARGET_PASS_BY_REFERENCE
515 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
516 #undef TARGET_CALLEE_COPIES
517 #define TARGET_CALLEE_COPIES sh_callee_copies
518 #undef TARGET_ARG_PARTIAL_BYTES
519 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
520 #undef TARGET_FUNCTION_ARG
521 #define TARGET_FUNCTION_ARG sh_function_arg
522 #undef TARGET_FUNCTION_ARG_ADVANCE
523 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
525 #undef TARGET_BUILD_BUILTIN_VA_LIST
526 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
527 #undef TARGET_EXPAND_BUILTIN_VA_START
528 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
529 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
530 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
532 #undef TARGET_SCALAR_MODE_SUPPORTED_P
533 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
534 #undef TARGET_VECTOR_MODE_SUPPORTED_P
535 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
537 #undef TARGET_CHECK_PCH_TARGET_FLAGS
538 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
540 #undef TARGET_DWARF_CALLING_CONVENTION
541 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
543 #undef TARGET_FRAME_POINTER_REQUIRED
544 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
546 /* Return regmode weight for insn. */
547 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
549 /* Return current register pressure for regmode. */
550 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
552 #undef TARGET_ENCODE_SECTION_INFO
553 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
555 #undef TARGET_SECONDARY_RELOAD
556 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
558 #undef TARGET_PREFERRED_RELOAD_CLASS
559 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
561 #undef TARGET_CONDITIONAL_REGISTER_USAGE
562 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
564 #undef TARGET_LEGITIMATE_ADDRESS_P
565 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
567 #undef TARGET_TRAMPOLINE_INIT
568 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
569 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
570 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
572 #undef TARGET_LEGITIMATE_CONSTANT_P
573 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
575 /* Machine-specific symbol_ref flags. */
576 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
578 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
579 is used by optabs.c atomic op expansion code as well as in sync.md. */
580 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
581 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
583 struct gcc_target targetm = TARGET_INITIALIZER;
585 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
586 various options, and do some machine dependent initialization. */
588 sh_option_override (void)
592 SUBTARGET_OVERRIDE_OPTIONS;
593 if (optimize > 1 && !optimize_size)
594 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
595 sh_cpu = PROCESSOR_SH1;
596 assembler_dialect = 0;
598 sh_cpu = PROCESSOR_SH2;
600 sh_cpu = PROCESSOR_SH2E;
602 sh_cpu = PROCESSOR_SH2A;
604 sh_cpu = PROCESSOR_SH3;
606 sh_cpu = PROCESSOR_SH3E;
609 assembler_dialect = 1;
610 sh_cpu = PROCESSOR_SH4;
612 if (TARGET_SH4A_ARCH)
614 assembler_dialect = 1;
615 sh_cpu = PROCESSOR_SH4A;
619 sh_cpu = PROCESSOR_SH5;
620 target_flags |= MASK_ALIGN_DOUBLE;
621 if (TARGET_SHMEDIA_FPU)
622 target_flags |= MASK_FMOVD;
625 /* There are no delay slots on SHmedia. */
626 flag_delayed_branch = 0;
627 /* Relaxation isn't yet supported for SHmedia */
628 target_flags &= ~MASK_RELAX;
629 /* After reload, if conversion does little good but can cause
631 - find_if_block doesn't do anything for SH because we don't
632 have conditional execution patterns. (We use conditional
633 move patterns, which are handled differently, and only
635 - find_cond_trap doesn't do anything for the SH because we
636 don't have conditional traps.
637 - find_if_case_1 uses redirect_edge_and_branch_force in
638 the only path that does an optimization, and this causes
639 an ICE when branch targets are in registers.
640 - find_if_case_2 doesn't do anything for the SHmedia after
641 reload except when it can redirect a tablejump - and
642 that's rather rare. */
643 flag_if_conversion2 = 0;
644 if (! strcmp (sh_div_str, "call"))
645 sh_div_strategy = SH_DIV_CALL;
646 else if (! strcmp (sh_div_str, "call2"))
647 sh_div_strategy = SH_DIV_CALL2;
648 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
649 sh_div_strategy = SH_DIV_FP;
650 else if (! strcmp (sh_div_str, "inv"))
651 sh_div_strategy = SH_DIV_INV;
652 else if (! strcmp (sh_div_str, "inv:minlat"))
653 sh_div_strategy = SH_DIV_INV_MINLAT;
654 else if (! strcmp (sh_div_str, "inv20u"))
655 sh_div_strategy = SH_DIV_INV20U;
656 else if (! strcmp (sh_div_str, "inv20l"))
657 sh_div_strategy = SH_DIV_INV20L;
658 else if (! strcmp (sh_div_str, "inv:call2"))
659 sh_div_strategy = SH_DIV_INV_CALL2;
660 else if (! strcmp (sh_div_str, "inv:call"))
661 sh_div_strategy = SH_DIV_INV_CALL;
662 else if (! strcmp (sh_div_str, "inv:fp"))
665 sh_div_strategy = SH_DIV_INV_FP;
667 sh_div_strategy = SH_DIV_INV;
669 TARGET_CBRANCHDI4 = 0;
670 /* Assembler CFI isn't yet fully supported for SHmedia. */
671 flag_dwarf2_cfi_asm = 0;
676 /* Only the sh64-elf assembler fully supports .quad properly. */
677 targetm.asm_out.aligned_op.di = NULL;
678 targetm.asm_out.unaligned_op.di = NULL;
682 if (! strcmp (sh_div_str, "call-div1"))
683 sh_div_strategy = SH_DIV_CALL_DIV1;
684 else if (! strcmp (sh_div_str, "call-fp")
685 && (TARGET_FPU_DOUBLE || TARGET_FPU_SINGLE_ONLY
686 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
687 sh_div_strategy = SH_DIV_CALL_FP;
688 else if (! strcmp (sh_div_str, "call-table")
689 && (TARGET_SH3 || TARGET_SH2A))
690 sh_div_strategy = SH_DIV_CALL_TABLE;
692 /* Pick one that makes most sense for the target in general.
693 It is not much good to use different functions depending
694 on -Os, since then we'll end up with two different functions
695 when some of the code is compiled for size, and some for
698 /* SH4 tends to emphasize speed. */
700 sh_div_strategy = SH_DIV_CALL_TABLE;
701 /* These have their own way of doing things. */
702 else if (TARGET_SH2A)
703 sh_div_strategy = SH_DIV_INTRINSIC;
704 /* ??? Should we use the integer SHmedia function instead? */
705 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
706 sh_div_strategy = SH_DIV_CALL_FP;
707 /* SH1 .. SH3 cores often go into small-footprint systems, so
708 default to the smallest implementation available. */
710 sh_div_strategy = SH_DIV_CALL_DIV1;
713 TARGET_PRETEND_CMOVE = 0;
714 if (sh_divsi3_libfunc[0])
715 ; /* User supplied - leave it alone. */
716 else if (TARGET_DIVIDE_CALL_FP)
717 sh_divsi3_libfunc = "__sdivsi3_i4";
718 else if (TARGET_DIVIDE_CALL_TABLE)
719 sh_divsi3_libfunc = "__sdivsi3_i4i";
721 sh_divsi3_libfunc = "__sdivsi3_1";
723 sh_divsi3_libfunc = "__sdivsi3";
724 if (sh_branch_cost == -1)
728 /* The SH1 does not have delay slots, hence we get a pipeline stall
729 at every branch. The SH4 is superscalar, so the single delay slot
730 is not sufficient to keep both pipelines filled. */
731 if (! TARGET_SH2 || TARGET_HARD_SH4)
735 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
736 if (! VALID_REGISTER_P (regno))
737 sh_register_names[regno][0] = '\0';
739 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
740 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
741 sh_additional_register_names[regno][0] = '\0';
743 if ((flag_pic && ! TARGET_PREFERGOT)
744 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
745 flag_no_function_cse = 1;
747 if (targetm.small_register_classes_for_mode_p (VOIDmode)) \
749 /* Never run scheduling before reload, since that can
750 break global alloc, and generates slower code anyway due
751 to the pressure on R0. */
752 /* Enable sched1 for SH4 if the user explicitly requests.
753 When sched1 is enabled, the ready queue will be reordered by
754 the target hooks if pressure is high. We can not do this for
755 PIC, SH3 and lower as they give spill failures for R0. */
756 if (!TARGET_HARD_SH4 || flag_pic)
757 flag_schedule_insns = 0;
758 /* ??? Current exception handling places basic block boundaries
759 after call_insns. It causes the high pressure on R0 and gives
760 spill failures for R0 in reload. See PR 22553 and the thread
762 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
763 else if (flag_exceptions)
765 if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
766 warning (0, "ignoring -fschedule-insns because of exception handling bug");
767 flag_schedule_insns = 0;
769 else if (flag_schedule_insns
770 && !global_options_set.x_flag_schedule_insns)
771 flag_schedule_insns = 0;
774 /* Unwind info is not correct around the CFG unless either a frame
775 pointer is present or M_A_O_A is set. Fixing this requires rewriting
776 unwind info generation to be aware of the CFG and propagating states
778 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
779 || flag_exceptions || flag_non_call_exceptions)
780 && flag_omit_frame_pointer && !TARGET_ACCUMULATE_OUTGOING_ARGS)
782 warning (0, "unwind tables currently require either a frame pointer "
783 "or -maccumulate-outgoing-args for correctness");
784 TARGET_ACCUMULATE_OUTGOING_ARGS = 1;
787 /* Unwinding with -freorder-blocks-and-partition does not work on this
788 architecture, because it requires far jumps to label crossing between
789 hot/cold sections which are rejected on this architecture. */
790 if (flag_reorder_blocks_and_partition)
794 inform (input_location,
795 "-freorder-blocks-and-partition does not work with "
796 "exceptions on this architecture");
797 flag_reorder_blocks_and_partition = 0;
798 flag_reorder_blocks = 1;
800 else if (flag_unwind_tables)
802 inform (input_location,
803 "-freorder-blocks-and-partition does not support unwind "
804 "info on this architecture");
805 flag_reorder_blocks_and_partition = 0;
806 flag_reorder_blocks = 1;
810 if (align_loops == 0)
811 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
812 if (align_jumps == 0)
813 align_jumps = 1 << CACHE_LOG;
814 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
815 align_jumps = TARGET_SHMEDIA ? 4 : 2;
817 /* Allocation boundary (in *bytes*) for the code of a function.
818 SH1: 32 bit alignment is faster, because instructions are always
819 fetched as a pair from a longword boundary.
820 SH2 .. SH5 : align to cache line start. */
821 if (align_functions == 0)
823 = optimize_size ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
824 /* The linker relaxation code breaks when a function contains
825 alignments that are larger than that at the start of a
830 = align_loops > align_jumps ? align_loops : align_jumps;
832 /* Also take possible .long constants / mova tables int account. */
835 if (align_functions < min_align)
836 align_functions = min_align;
839 /* If the -mieee option was not explicitly set by the user, turn it on
840 unless -ffinite-math-only was specified. See also PR 33135. */
841 if (! global_options_set.x_TARGET_IEEE)
842 TARGET_IEEE = ! flag_finite_math_only;
844 if (sh_fixed_range_str)
845 sh_fix_range (sh_fixed_range_str);
847 /* This target defaults to strict volatile bitfields. */
848 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
849 flag_strict_volatile_bitfields = 1;
852 /* Print the operand address in x to the stream. */
855 sh_print_operand_address (FILE *stream, rtx x)
857 switch (GET_CODE (x))
861 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
866 rtx base = XEXP (x, 0);
867 rtx index = XEXP (x, 1);
869 switch (GET_CODE (index))
872 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
873 reg_names[true_regnum (base)]);
879 int base_num = true_regnum (base);
880 int index_num = true_regnum (index);
882 fprintf (stream, "@(r0,%s)",
883 reg_names[MAX (base_num, index_num)]);
894 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
898 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
902 x = mark_constant_pool_use (x);
903 output_addr_const (stream, x);
908 /* Print operand x (an rtx) in assembler syntax to file stream
909 according to modifier code.
911 '.' print a .s if insn needs delay slot
912 ',' print LOCAL_LABEL_PREFIX
913 '@' print trap, rte or rts depending upon pragma interruptness
914 '#' output a nop if there is nothing to put in the delay slot
915 ''' print likelihood suffix (/u for unlikely).
916 '>' print branch target if -fverbose-asm
917 'O' print a constant without the #
918 'R' print the LSW of a dp value - changes if in little endian
919 'S' print the MSW of a dp value - changes if in little endian
920 'T' print the next word of a dp value - same as 'R' in big endian mode.
921 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
922 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
923 'N' print 'r63' if the operand is (const_int 0).
924 'd' print a V2SF reg as dN instead of fpN.
925 'm' print a pair `base,offset' or `base,index', for LD and ST.
926 'U' Likewise for {LD,ST}{HI,LO}.
927 'V' print the position of a single bit set.
928 'W' print the position of a single bit cleared.
929 't' print a memory address which is a register.
930 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
931 'o' output an operator. */
934 sh_print_operand (FILE *stream, rtx x, int code)
937 enum machine_mode mode;
945 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
946 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
947 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
950 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
953 trapa_attr = lookup_attribute ("trap_exit",
954 DECL_ATTRIBUTES (current_function_decl));
956 fprintf (stream, "trapa #%ld",
957 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
958 else if (sh_cfun_interrupt_handler_p ())
960 if (sh_cfun_resbank_handler_p ())
961 fprintf (stream, "resbank\n");
962 fprintf (stream, "rte");
965 fprintf (stream, "rts");
968 /* Output a nop if there's nothing in the delay slot. */
969 if (dbr_sequence_length () == 0)
970 fprintf (stream, "\n\tnop");
974 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
976 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
977 fputs ("/u", stream);
981 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
983 fputs ("\t! target: ", stream);
984 output_addr_const (stream, JUMP_LABEL (current_output_insn));
988 x = mark_constant_pool_use (x);
989 output_addr_const (stream, x);
991 /* N.B.: %R / %S / %T adjust memory addresses by four.
992 For SHMEDIA, that means they can be used to access the first and
993 second 32 bit part of a 64 bit (or larger) value that
994 might be held in floating point registers or memory.
995 While they can be used to access 64 bit parts of a larger value
996 held in general purpose registers, that won't work with memory -
997 neither for fp registers, since the frxx names are used. */
999 if (REG_P (x) || GET_CODE (x) == SUBREG)
1001 regno = true_regnum (x);
1002 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1003 fputs (reg_names[regno], (stream));
1007 x = adjust_address (x, SImode, 4 * LSW);
1008 sh_print_operand_address (stream, XEXP (x, 0));
1014 mode = GET_MODE (x);
1015 if (mode == VOIDmode)
1017 if (GET_MODE_SIZE (mode) >= 8)
1018 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1020 sh_print_operand (stream, sub, 0);
1022 output_operand_lossage ("invalid operand to %%R");
1026 if (REG_P (x) || GET_CODE (x) == SUBREG)
1028 regno = true_regnum (x);
1029 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1030 fputs (reg_names[regno], (stream));
1034 x = adjust_address (x, SImode, 4 * MSW);
1035 sh_print_operand_address (stream, XEXP (x, 0));
1041 mode = GET_MODE (x);
1042 if (mode == VOIDmode)
1044 if (GET_MODE_SIZE (mode) >= 8)
1045 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1047 sh_print_operand (stream, sub, 0);
1049 output_operand_lossage ("invalid operand to %%S");
1053 /* Next word of a double. */
1054 switch (GET_CODE (x))
1057 fputs (reg_names[REGNO (x) + 1], (stream));
1060 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1061 && GET_CODE (XEXP (x, 0)) != POST_INC)
1062 x = adjust_address (x, SImode, 4);
1063 sh_print_operand_address (stream, XEXP (x, 0));
1071 gcc_assert (MEM_P (x));
1073 switch (GET_CODE (x))
1077 sh_print_operand (stream, x, 0);
1085 switch (GET_CODE (x))
1087 case PLUS: fputs ("add", stream); break;
1088 case MINUS: fputs ("sub", stream); break;
1089 case MULT: fputs ("mul", stream); break;
1090 case DIV: fputs ("div", stream); break;
1091 case EQ: fputs ("eq", stream); break;
1092 case NE: fputs ("ne", stream); break;
1093 case GT: case LT: fputs ("gt", stream); break;
1094 case GE: case LE: fputs ("ge", stream); break;
1095 case GTU: case LTU: fputs ("gtu", stream); break;
1096 case GEU: case LEU: fputs ("geu", stream); break;
1105 && GET_CODE (XEXP (x, 0)) == PLUS
1106 && (REG_P (XEXP (XEXP (x, 0), 1))
1107 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1108 fputc ('x', stream);
1114 switch (GET_MODE (x))
1116 case QImode: fputs (".b", stream); break;
1117 case HImode: fputs (".w", stream); break;
1118 case SImode: fputs (".l", stream); break;
1119 case SFmode: fputs (".s", stream); break;
1120 case DFmode: fputs (".d", stream); break;
1121 default: gcc_unreachable ();
1128 gcc_assert (MEM_P (x));
1132 switch (GET_CODE (x))
1136 sh_print_operand (stream, x, 0);
1137 fputs (", 0", stream);
1141 sh_print_operand (stream, XEXP (x, 0), 0);
1142 fputs (", ", stream);
1143 sh_print_operand (stream, XEXP (x, 1), 0);
1153 int num = exact_log2 (INTVAL (x));
1154 gcc_assert (num >= 0);
1155 fprintf (stream, "#%d", num);
1161 int num = exact_log2 (~INTVAL (x));
1162 gcc_assert (num >= 0);
1163 fprintf (stream, "#%d", num);
1168 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1170 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1174 if (x == CONST0_RTX (GET_MODE (x)))
1176 fprintf ((stream), "r63");
1179 goto default_output;
1181 if (CONST_INT_P (x))
1183 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1191 mode = GET_MODE (x);
1193 switch (GET_CODE (x))
1197 rtx inner = XEXP (x, 0);
1199 enum machine_mode inner_mode;
1201 /* We might see SUBREGs with vector mode registers inside. */
1202 if (GET_CODE (inner) == SUBREG
1203 && (GET_MODE_SIZE (GET_MODE (inner))
1204 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1205 && subreg_lowpart_p (inner))
1206 inner = SUBREG_REG (inner);
1207 if (CONST_INT_P (inner))
1209 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1210 goto default_output;
1212 inner_mode = GET_MODE (inner);
1213 if (GET_CODE (inner) == SUBREG
1214 && (GET_MODE_SIZE (GET_MODE (inner))
1215 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1216 && REG_P (SUBREG_REG (inner)))
1218 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1219 GET_MODE (SUBREG_REG (inner)),
1220 SUBREG_BYTE (inner),
1222 inner = SUBREG_REG (inner);
1224 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1226 /* Floating point register pairs are always big endian;
1227 general purpose registers are 64 bit wide. */
1228 regno = REGNO (inner);
1229 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1230 - HARD_REGNO_NREGS (regno, mode))
1238 /* FIXME: We need this on SHmedia32 because reload generates
1239 some sign-extended HI or QI loads into DImode registers
1240 but, because Pmode is SImode, the address ends up with a
1241 subreg:SI of the DImode register. Maybe reload should be
1242 fixed so as to apply alter_subreg to such loads? */
1244 gcc_assert (trapping_target_operand (x, VOIDmode));
1245 x = XEXP (XEXP (x, 2), 0);
1246 goto default_output;
1248 gcc_assert (SUBREG_BYTE (x) == 0
1249 && REG_P (SUBREG_REG (x)));
1257 if (FP_REGISTER_P (regno)
1258 && mode == V16SFmode)
1259 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1260 else if (FP_REGISTER_P (REGNO (x))
1261 && mode == V4SFmode)
1262 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1264 && mode == V2SFmode)
1265 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1266 else if (FP_REGISTER_P (REGNO (x))
1267 && GET_MODE_SIZE (mode) > 4)
1268 fprintf ((stream), "d%s", reg_names[regno] + 1);
1270 fputs (reg_names[regno], (stream));
1274 output_address (XEXP (x, 0));
1279 fputc ('#', stream);
1280 output_addr_const (stream, x);
1288 sh_print_operand_punct_valid_p (unsigned char code)
1290 return (code == '.' || code == '#' || code == '@' || code == ','
1291 || code == '$' || code == '\'' || code == '>');
1294 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1297 sh_asm_output_addr_const_extra (FILE *file, rtx x)
1299 if (GET_CODE (x) == UNSPEC)
1301 switch (XINT (x, 1))
1303 case UNSPEC_DATALABEL:
1304 fputs ("datalabel ", file);
1305 output_addr_const (file, XVECEXP (x, 0, 0));
1308 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1309 output_addr_const (file, XVECEXP (x, 0, 0));
1312 output_addr_const (file, XVECEXP (x, 0, 0));
1313 fputs ("@GOT", file);
1316 output_addr_const (file, XVECEXP (x, 0, 0));
1317 fputs ("@GOTOFF", file);
1320 output_addr_const (file, XVECEXP (x, 0, 0));
1321 fputs ("@PLT", file);
1324 output_addr_const (file, XVECEXP (x, 0, 0));
1325 fputs ("@GOTPLT", file);
1328 output_addr_const (file, XVECEXP (x, 0, 0));
1329 fputs ("@DTPOFF", file);
1331 case UNSPEC_GOTTPOFF:
1332 output_addr_const (file, XVECEXP (x, 0, 0));
1333 fputs ("@GOTTPOFF", file);
1336 output_addr_const (file, XVECEXP (x, 0, 0));
1337 fputs ("@TPOFF", file);
1342 /* LPCS stands for Label for PIC Call Site. */
1343 targetm.asm_out.generate_internal_label (name, "LPCS",
1344 INTVAL (XVECEXP (x, 0, 0)));
1345 assemble_name (file, name);
1348 case UNSPEC_EXTRACT_S16:
1349 case UNSPEC_EXTRACT_U16:
1353 val = XVECEXP (x, 0, 0);
1354 shift = XVECEXP (x, 0, 1);
1356 if (shift != const0_rtx)
1358 if (GET_CODE (val) == CONST
1359 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ)
1362 output_addr_const (file, val);
1366 output_addr_const (file, val);
1367 if (shift != const0_rtx)
1369 fputs (" >> ", file);
1370 output_addr_const (file, shift);
1373 fputs (" & 65535)", file);
1377 output_addr_const (file, XVECEXP (x, 0, 0));
1379 if (GET_CODE (XVECEXP (x, 0, 1)) == CONST)
1382 output_addr_const (file, XVECEXP (x, 0, 1));
1386 output_addr_const (file, XVECEXP (x, 0, 1));
1388 case UNSPEC_PCREL_SYMOFF:
1389 output_addr_const (file, XVECEXP (x, 0, 0));
1391 output_addr_const (file, XVECEXP (x, 0, 1));
1392 fputs ("-.)", file);
1404 /* Encode symbol attributes of a SYMBOL_REF into its
1405 SYMBOL_REF_FLAGS. */
1407 sh_encode_section_info (tree decl, rtx rtl, int first)
1409 default_encode_section_info (decl, rtl, first);
1411 if (TREE_CODE (decl) == FUNCTION_DECL
1412 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1413 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1416 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1418 force_into (rtx value, rtx target)
1420 value = force_operand (value, target);
1421 if (! rtx_equal_p (value, target))
1422 emit_insn (gen_move_insn (target, value));
1425 /* Emit code to perform a block move. Choose the best method.
1427 OPERANDS[0] is the destination.
1428 OPERANDS[1] is the source.
1429 OPERANDS[2] is the size.
1430 OPERANDS[3] is the alignment safe to use. */
1433 expand_block_move (rtx *operands)
1435 int align = INTVAL (operands[3]);
1436 int constp = (CONST_INT_P (operands[2]));
1437 int bytes = (constp ? INTVAL (operands[2]) : 0);
1442 /* If we could use mov.l to move words and dest is word-aligned, we
1443 can use movua.l for loads and still generate a relatively short
1444 and efficient sequence. */
1445 if (TARGET_SH4A_ARCH && align < 4
1446 && MEM_ALIGN (operands[0]) >= 32
1447 && can_move_by_pieces (bytes, 32))
1449 rtx dest = copy_rtx (operands[0]);
1450 rtx src = copy_rtx (operands[1]);
1451 /* We could use different pseudos for each copied word, but
1452 since movua can only load into r0, it's kind of
1454 rtx temp = gen_reg_rtx (SImode);
1455 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1458 while (copied + 4 <= bytes)
1460 rtx to = adjust_address (dest, SImode, copied);
1461 rtx from = adjust_automodify_address (src, BLKmode,
1464 set_mem_size (from, 4);
1465 emit_insn (gen_movua (temp, from));
1466 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1467 emit_move_insn (to, temp);
1472 move_by_pieces (adjust_address (dest, BLKmode, copied),
1473 adjust_automodify_address (src, BLKmode,
1475 bytes - copied, align, 0);
1480 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1481 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1482 if (align < 4 || (bytes % 4 != 0))
1485 if (TARGET_HARD_SH4)
1489 else if (bytes == 12)
1491 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1492 rtx r4 = gen_rtx_REG (SImode, 4);
1493 rtx r5 = gen_rtx_REG (SImode, 5);
1495 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1496 force_into (XEXP (operands[0], 0), r4);
1497 force_into (XEXP (operands[1], 0), r5);
1498 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1501 else if (! optimize_size)
1503 const char *entry_name;
1504 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1506 rtx r4 = gen_rtx_REG (SImode, 4);
1507 rtx r5 = gen_rtx_REG (SImode, 5);
1508 rtx r6 = gen_rtx_REG (SImode, 6);
1510 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1511 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1512 force_into (XEXP (operands[0], 0), r4);
1513 force_into (XEXP (operands[1], 0), r5);
1515 dwords = bytes >> 3;
1516 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1517 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1526 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1527 rtx r4 = gen_rtx_REG (SImode, 4);
1528 rtx r5 = gen_rtx_REG (SImode, 5);
1530 sprintf (entry, "__movmemSI%d", bytes);
1531 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1532 force_into (XEXP (operands[0], 0), r4);
1533 force_into (XEXP (operands[1], 0), r5);
1534 emit_insn (gen_block_move_real (func_addr_rtx));
1538 /* This is the same number of bytes as a memcpy call, but to a different
1539 less common function name, so this will occasionally use more space. */
1540 if (! optimize_size)
1542 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1543 int final_switch, while_loop;
1544 rtx r4 = gen_rtx_REG (SImode, 4);
1545 rtx r5 = gen_rtx_REG (SImode, 5);
1546 rtx r6 = gen_rtx_REG (SImode, 6);
1548 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1549 force_into (XEXP (operands[0], 0), r4);
1550 force_into (XEXP (operands[1], 0), r5);
1552 /* r6 controls the size of the move. 16 is decremented from it
1553 for each 64 bytes moved. Then the negative bit left over is used
1554 as an index into a list of move instructions. e.g., a 72 byte move
1555 would be set up with size(r6) = 14, for one iteration through the
1556 big while loop, and a switch of -2 for the last part. */
1558 final_switch = 16 - ((bytes / 4) % 16);
1559 while_loop = ((bytes / 4) / 16 - 1) * 16;
1560 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1561 emit_insn (gen_block_lump_real (func_addr_rtx));
1568 /* Prepare operands for a move define_expand; specifically, one of the
1569 operands must be in a register. */
1572 prepare_move_operands (rtx operands[], enum machine_mode mode)
1574 if ((mode == SImode || mode == DImode)
1576 && ! ((mode == Pmode || mode == ptr_mode)
1577 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1580 if (SYMBOLIC_CONST_P (operands[1]))
1582 if (MEM_P (operands[0]))
1583 operands[1] = force_reg (Pmode, operands[1]);
1584 else if (TARGET_SHMEDIA
1585 && GET_CODE (operands[1]) == LABEL_REF
1586 && target_reg_operand (operands[0], mode))
1590 temp = (!can_create_pseudo_p ()
1592 : gen_reg_rtx (Pmode));
1593 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1596 else if (GET_CODE (operands[1]) == CONST
1597 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1598 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1600 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1601 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1603 operands[1] = expand_binop (mode, add_optab, temp,
1604 XEXP (XEXP (operands[1], 0), 1),
1605 (!can_create_pseudo_p ()
1607 : gen_reg_rtx (Pmode)),
1608 0, OPTAB_LIB_WIDEN);
1612 if (! reload_in_progress && ! reload_completed)
1614 /* Copy the source to a register if both operands aren't registers. */
1615 if (! register_operand (operands[0], mode)
1616 && ! sh_register_operand (operands[1], mode))
1617 operands[1] = copy_to_mode_reg (mode, operands[1]);
1619 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1621 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1622 except that we can't use that function because it is static. */
1623 rtx new_rtx = change_address (operands[0], mode, 0);
1624 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1625 operands[0] = new_rtx;
1628 /* This case can happen while generating code to move the result
1629 of a library call to the target. Reject `st r0,@(rX,rY)' because
1630 reload will fail to find a spill register for rX, since r0 is already
1631 being used for the source. */
1633 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1634 && MEM_P (operands[0])
1635 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1636 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1637 operands[1] = copy_to_mode_reg (mode, operands[1]);
1640 if (mode == Pmode || mode == ptr_mode)
1643 enum tls_model tls_kind;
1647 if (GET_CODE (op1) == CONST
1648 && GET_CODE (XEXP (op1, 0)) == PLUS
1649 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1652 opc = XEXP (XEXP (op1, 0), 1);
1653 op1 = XEXP (XEXP (op1, 0), 0);
1658 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1660 rtx tga_op1, tga_ret, tmp, tmp2;
1663 && (tls_kind == TLS_MODEL_GLOBAL_DYNAMIC
1664 || tls_kind == TLS_MODEL_LOCAL_DYNAMIC
1665 || tls_kind == TLS_MODEL_INITIAL_EXEC))
1667 /* Don't schedule insns for getting GOT address when
1668 the first scheduling is enabled, to avoid spill
1670 if (flag_schedule_insns)
1671 emit_insn (gen_blockage ());
1672 emit_insn (gen_GOTaddr2picreg ());
1673 emit_use (gen_rtx_REG (SImode, PIC_REG));
1674 if (flag_schedule_insns)
1675 emit_insn (gen_blockage ());
1680 case TLS_MODEL_GLOBAL_DYNAMIC:
1681 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1682 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1683 tmp = gen_reg_rtx (Pmode);
1684 emit_move_insn (tmp, tga_ret);
1688 case TLS_MODEL_LOCAL_DYNAMIC:
1689 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1690 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1692 tmp = gen_reg_rtx (Pmode);
1693 emit_move_insn (tmp, tga_ret);
1695 if (register_operand (op0, Pmode))
1698 tmp2 = gen_reg_rtx (Pmode);
1700 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1704 case TLS_MODEL_INITIAL_EXEC:
1705 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1706 tmp = gen_sym2GOTTPOFF (op1);
1707 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1711 case TLS_MODEL_LOCAL_EXEC:
1712 tmp2 = gen_reg_rtx (Pmode);
1713 emit_insn (gen_load_gbr (tmp2));
1714 tmp = gen_reg_rtx (Pmode);
1715 emit_insn (gen_symTPOFF2reg (tmp, op1));
1717 if (register_operand (op0, Pmode))
1720 op1 = gen_reg_rtx (Pmode);
1722 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1729 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1738 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1739 enum rtx_code comparison)
1742 rtx scratch = NULL_RTX;
1744 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1745 comparison = GET_CODE (operands[0]);
1747 scratch = operands[4];
1748 if (CONST_INT_P (operands[1])
1749 && !CONST_INT_P (operands[2]))
1751 rtx tmp = operands[1];
1753 operands[1] = operands[2];
1755 comparison = swap_condition (comparison);
1757 if (CONST_INT_P (operands[2]))
1759 HOST_WIDE_INT val = INTVAL (operands[2]);
1760 if ((val == -1 || val == -0x81)
1761 && (comparison == GT || comparison == LE))
1763 comparison = (comparison == GT) ? GE : LT;
1764 operands[2] = gen_int_mode (val + 1, mode);
1766 else if ((val == 1 || val == 0x80)
1767 && (comparison == GE || comparison == LT))
1769 comparison = (comparison == GE) ? GT : LE;
1770 operands[2] = gen_int_mode (val - 1, mode);
1772 else if (val == 1 && (comparison == GEU || comparison == LTU))
1774 comparison = (comparison == GEU) ? NE : EQ;
1775 operands[2] = CONST0_RTX (mode);
1777 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1779 comparison = (comparison == GEU) ? GTU : LEU;
1780 operands[2] = gen_int_mode (val - 1, mode);
1782 else if (val == 0 && (comparison == GTU || comparison == LEU))
1783 comparison = (comparison == GTU) ? NE : EQ;
1784 else if (mode == SImode
1785 && ((val == 0x7fffffff
1786 && (comparison == GTU || comparison == LEU))
1787 || ((unsigned HOST_WIDE_INT) val
1788 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1789 && (comparison == GEU || comparison == LTU))))
1791 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1792 operands[2] = CONST0_RTX (mode);
1796 if (can_create_pseudo_p ())
1797 operands[1] = force_reg (mode, op1);
1798 /* When we are handling DImode comparisons, we want to keep constants so
1799 that we can optimize the component comparisons; however, memory loads
1800 are better issued as a whole so that they can be scheduled well.
1801 SImode equality comparisons allow I08 constants, but only when they
1802 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1803 into a register, that register might as well be r0, and we allow the
1804 constant. If it is already in a register, this is likely to be
1805 allocated to a different hard register, thus we load the constant into
1806 a register unless it is zero. */
1807 if (!REG_P (operands[2])
1808 && (!CONST_INT_P (operands[2])
1809 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1810 && ((comparison != EQ && comparison != NE)
1811 || (REG_P (op1) && REGNO (op1) != R0_REG)
1812 || !satisfies_constraint_I08 (operands[2])))))
1814 if (scratch && GET_MODE (scratch) == mode)
1816 emit_move_insn (scratch, operands[2]);
1817 operands[2] = scratch;
1819 else if (can_create_pseudo_p ())
1820 operands[2] = force_reg (mode, operands[2]);
1826 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1828 rtx (*branch_expander) (rtx) = gen_branch_true;
1831 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1834 case NE: case LT: case LE: case LTU: case LEU:
1835 comparison = reverse_condition (comparison);
1836 branch_expander = gen_branch_false;
1839 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1840 gen_rtx_fmt_ee (comparison, SImode,
1841 operands[1], operands[2])));
1842 jump = emit_jump_insn (branch_expander (operands[3]));
1843 if (probability >= 0)
1844 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1848 /* ??? How should we distribute probabilities when more than one branch
1849 is generated. So far we only have some ad-hoc observations:
1850 - If the operands are random, they are likely to differ in both parts.
1851 - If comparing items in a hash chain, the operands are random or equal;
1852 operation should be EQ or NE.
1853 - If items are searched in an ordered tree from the root, we can expect
1854 the highpart to be unequal about half of the time; operation should be
1855 an inequality comparison, operands non-constant, and overall probability
1856 about 50%. Likewise for quicksort.
1857 - Range checks will be often made against constants. Even if we assume for
1858 simplicity an even distribution of the non-constant operand over a
1859 sub-range here, the same probability could be generated with differently
1860 wide sub-ranges - as long as the ratio of the part of the subrange that
1861 is before the threshold to the part that comes after the threshold stays
1862 the same. Thus, we can't really tell anything here;
1863 assuming random distribution is at least simple.
1867 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1869 enum rtx_code msw_taken, msw_skip, lsw_taken;
1870 rtx skip_label = NULL_RTX;
1871 rtx op1h, op1l, op2h, op2l;
1874 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1875 rtx scratch = operands[4];
1877 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1878 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1879 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1880 op1l = gen_lowpart (SImode, operands[1]);
1881 op2l = gen_lowpart (SImode, operands[2]);
1882 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1883 prob = split_branch_probability;
1884 rev_prob = REG_BR_PROB_BASE - prob;
1887 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1888 That costs 1 cycle more when the first branch can be predicted taken,
1889 but saves us mispredicts because only one branch needs prediction.
1890 It also enables generating the cmpeqdi_t-1 pattern. */
1892 if (TARGET_CMPEQDI_T)
1894 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1895 emit_jump_insn (gen_branch_true (operands[3]));
1902 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1904 msw_skip_prob = rev_prob;
1905 if (REG_BR_PROB_BASE <= 65535)
1906 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1909 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1913 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1914 / ((HOST_WIDEST_INT) prob << 32)))
1920 if (TARGET_CMPEQDI_T)
1922 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1923 emit_jump_insn (gen_branch_false (operands[3]));
1927 msw_taken_prob = prob;
1932 msw_taken = comparison;
1933 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1935 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1936 msw_skip = swap_condition (msw_taken);
1940 if (op2l == CONST0_RTX (SImode))
1941 msw_taken = comparison;
1944 msw_taken = comparison == GE ? GT : GTU;
1945 msw_skip = swap_condition (msw_taken);
1950 msw_taken = comparison;
1951 if (op2l == CONST0_RTX (SImode))
1953 msw_skip = swap_condition (msw_taken);
1957 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1958 msw_taken = comparison;
1962 if (comparison == LE)
1964 else if (op2h != CONST0_RTX (SImode))
1968 msw_skip = swap_condition (LTU);
1971 msw_skip = swap_condition (msw_taken);
1974 default: return false;
1976 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1977 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1978 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1979 if (comparison != EQ && comparison != NE && num_branches > 1)
1981 if (!CONSTANT_P (operands[2])
1982 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1983 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1985 msw_taken_prob = prob / 2U;
1987 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1988 lsw_taken_prob = prob;
1992 msw_taken_prob = prob;
1993 msw_skip_prob = REG_BR_PROB_BASE;
1994 /* ??? If we have a constant op2h, should we use that when
1995 calculating lsw_taken_prob? */
1996 lsw_taken_prob = prob;
2001 operands[4] = NULL_RTX;
2002 if (reload_completed
2003 && ! arith_reg_or_0_operand (op2h, SImode)
2004 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
2005 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
2006 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
2008 emit_move_insn (scratch, operands[2]);
2009 operands[2] = scratch;
2011 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2012 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
2013 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2015 rtx taken_label = operands[3];
2017 /* Operands were possibly modified, but msw_skip doesn't expect this.
2018 Always use the original ones. */
2019 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2023 if (reload_completed
2024 && ! arith_reg_or_0_operand (op2h, SImode)
2025 && (true_regnum (op1h) || (comparison != EQ && comparison != NE)))
2027 emit_move_insn (scratch, operands[2]);
2028 operands[2] = scratch;
2032 operands[3] = skip_label = gen_label_rtx ();
2033 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2034 operands[3] = taken_label;
2038 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
2040 if (reload_completed
2041 && ! arith_reg_or_0_operand (op2l, SImode)
2042 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
2044 emit_move_insn (scratch, operands[2]);
2045 operands[2] = scratch;
2047 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2049 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2050 emit_label (skip_label);
2054 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2057 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2059 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2061 insn = gen_rtx_PARALLEL (VOIDmode,
2063 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2064 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2070 /* Prepare the operands for an scc instruction; make sure that the
2071 compare has been done and the result is in T_REG. */
2073 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2075 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2076 enum rtx_code oldcode = code;
2077 enum machine_mode mode;
2079 /* First need a compare insn. */
2083 /* It isn't possible to handle this case. */
2100 if (code != oldcode)
2107 mode = GET_MODE (op0);
2108 if (mode == VOIDmode)
2109 mode = GET_MODE (op1);
2111 op0 = force_reg (mode, op0);
2112 if ((code != EQ && code != NE
2113 && (op1 != const0_rtx
2114 || code == GTU || code == GEU || code == LTU || code == LEU))
2115 || (mode == DImode && op1 != const0_rtx)
2116 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2117 op1 = force_reg (mode, op1);
2119 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2120 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2125 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2128 rtx target = gen_reg_rtx (SImode);
2131 gcc_assert (TARGET_SHMEDIA);
2140 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2141 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2151 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2152 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2170 rtx t2 = gen_reg_rtx (DImode);
2171 emit_insn (gen_extendsidi2 (t2, target));
2175 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2178 /* Called from the md file, set up the operands of a compare instruction. */
2181 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2183 enum rtx_code code = GET_CODE (operands[0]);
2184 enum rtx_code branch_code;
2185 rtx op0 = operands[1];
2186 rtx op1 = operands[2];
2188 bool need_ccmpeq = false;
2190 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2192 op0 = force_reg (mode, op0);
2193 op1 = force_reg (mode, op1);
2197 if (code != EQ || mode == DImode)
2199 /* Force args into regs, since we can't use constants here. */
2200 op0 = force_reg (mode, op0);
2201 if (op1 != const0_rtx || code == GTU || code == GEU)
2202 op1 = force_reg (mode, op1);
2206 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2209 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2210 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2212 tem = op0, op0 = op1, op1 = tem;
2213 code = swap_condition (code);
2216 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2219 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2224 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2225 to EQ/GT respectively. */
2226 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2243 branch_code = reverse_condition (code);
2249 insn = gen_rtx_SET (VOIDmode,
2250 gen_rtx_REG (SImode, T_REG),
2251 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2253 sh_emit_set_t_insn (insn, mode);
2255 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2257 if (branch_code == code)
2258 emit_jump_insn (gen_branch_true (operands[3]));
2260 emit_jump_insn (gen_branch_false (operands[3]));
2264 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2266 enum rtx_code code = GET_CODE (operands[1]);
2267 rtx op0 = operands[2];
2268 rtx op1 = operands[3];
2270 bool invert = false;
2273 op0 = force_reg (mode, op0);
2274 if ((code != EQ && code != NE
2275 && (op1 != const0_rtx
2276 || code == GTU || code == GEU || code == LTU || code == LEU))
2277 || (mode == DImode && op1 != const0_rtx)
2278 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2279 op1 = force_reg (mode, op1);
2281 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2283 if (code == LT || code == LE)
2285 code = swap_condition (code);
2286 tem = op0, op0 = op1, op1 = tem;
2292 lab = gen_label_rtx ();
2293 sh_emit_scc_to_t (EQ, op0, op1);
2294 emit_jump_insn (gen_branch_true (lab));
2311 sh_emit_scc_to_t (code, op0, op1);
2315 emit_insn (gen_movnegt (operands[0]));
2317 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2320 /* Functions to output assembly code. */
2322 /* Return a sequence of instructions to perform DI or DF move.
2324 Since the SH cannot move a DI or DF in one instruction, we have
2325 to take care when we see overlapping source and dest registers. */
2328 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2329 enum machine_mode mode)
2331 rtx dst = operands[0];
2332 rtx src = operands[1];
2335 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2336 return "mov.l %T1,%0\n\tmov.l %1,%0";
2338 if (register_operand (dst, mode)
2339 && register_operand (src, mode))
2341 if (REGNO (src) == MACH_REG)
2342 return "sts mach,%S0\n\tsts macl,%R0";
2344 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2345 when mov.d r1,r0 do r1->r0 then r2->r1. */
2347 if (REGNO (src) + 1 == REGNO (dst))
2348 return "mov %T1,%T0\n\tmov %1,%0";
2350 return "mov %1,%0\n\tmov %T1,%T0";
2352 else if (CONST_INT_P (src))
2354 if (INTVAL (src) < 0)
2355 output_asm_insn ("mov #-1,%S0", operands);
2357 output_asm_insn ("mov #0,%S0", operands);
2359 return "mov %1,%R0";
2361 else if (MEM_P (src))
2364 int dreg = REGNO (dst);
2365 rtx inside = XEXP (src, 0);
2367 switch (GET_CODE (inside))
2370 ptrreg = REGNO (inside);
2374 ptrreg = subreg_regno (inside);
2378 ptrreg = REGNO (XEXP (inside, 0));
2379 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2380 an offsettable address. Unfortunately, offsettable addresses use
2381 QImode to check the offset, and a QImode offsettable address
2382 requires r0 for the other operand, which is not currently
2383 supported, so we can't use the 'o' constraint.
2384 Thus we must check for and handle r0+REG addresses here.
2385 We punt for now, since this is likely very rare. */
2386 gcc_assert (!REG_P (XEXP (inside, 1)));
2390 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2392 return "mov.l %1,%0\n\tmov.l %1,%T0";
2397 /* Work out the safe way to copy. Copy into the second half first. */
2399 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2402 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2405 /* Print an instruction which would have gone into a delay slot after
2406 another instruction, but couldn't because the other instruction expanded
2407 into a sequence where putting the slot insn at the end wouldn't work. */
2410 print_slot (rtx insn)
2412 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2414 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2418 output_far_jump (rtx insn, rtx op)
2420 struct { rtx lab, reg, op; } this_jmp;
2421 rtx braf_base_lab = NULL_RTX;
2424 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2427 this_jmp.lab = gen_label_rtx ();
2431 && offset - get_attr_length (insn) <= 32766)
2434 jump = "mov.w %O0,%1; braf %1";
2442 jump = "mov.l %O0,%1; braf %1";
2444 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2447 jump = "mov.l %O0,%1; jmp @%1";
2449 /* If we have a scratch register available, use it. */
2450 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2451 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2453 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2454 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2455 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2456 output_asm_insn (jump, &this_jmp.lab);
2457 if (dbr_sequence_length ())
2458 print_slot (final_sequence);
2460 output_asm_insn ("nop", 0);
2464 /* Output the delay slot insn first if any. */
2465 if (dbr_sequence_length ())
2466 print_slot (final_sequence);
2468 this_jmp.reg = gen_rtx_REG (SImode, 13);
2469 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2470 Fortunately, MACL is fixed and call-clobbered, and we never
2471 need its value across jumps, so save r13 in it instead of in
2474 output_asm_insn ("lds r13, macl", 0);
2476 output_asm_insn ("mov.l r13,@-r15", 0);
2477 output_asm_insn (jump, &this_jmp.lab);
2479 output_asm_insn ("sts macl, r13", 0);
2481 output_asm_insn ("mov.l @r15+,r13", 0);
2483 if (far && flag_pic && TARGET_SH2)
2485 braf_base_lab = gen_label_rtx ();
2486 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2487 CODE_LABEL_NUMBER (braf_base_lab));
2490 output_asm_insn (".align 2", 0);
2491 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2493 if (far && flag_pic)
2496 this_jmp.lab = braf_base_lab;
2497 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2500 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2504 /* Local label counter, used for constants in the pool and inside
2505 pattern branches. */
2507 static int lf = 100;
2509 /* Output code for ordinary branches. */
2512 output_branch (int logic, rtx insn, rtx *operands)
2514 switch (get_attr_length (insn))
2517 /* This can happen if filling the delay slot has caused a forward
2518 branch to exceed its range (we could reverse it, but only
2519 when we know we won't overextend other branches; this should
2520 best be handled by relaxation).
2521 It can also happen when other condbranches hoist delay slot insn
2522 from their destination, thus leading to code size increase.
2523 But the branch will still be in the range -4092..+4098 bytes. */
2528 /* The call to print_slot will clobber the operands. */
2529 rtx op0 = operands[0];
2531 /* If the instruction in the delay slot is annulled (true), then
2532 there is no delay slot where we can put it now. The only safe
2533 place for it is after the label. final will do that by default. */
2536 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2537 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2539 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2540 ASSEMBLER_DIALECT ? "/" : ".", label);
2541 print_slot (final_sequence);
2544 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2546 output_asm_insn ("bra\t%l0", &op0);
2547 fprintf (asm_out_file, "\tnop\n");
2548 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2552 /* When relaxing, handle this like a short branch. The linker
2553 will fix it up if it still doesn't fit after relaxation. */
2555 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2557 /* These are for SH2e, in which we have to account for the
2558 extra nop because of the hardware bug in annulled branches. */
2564 gcc_assert (!final_sequence
2565 || !(INSN_ANNULLED_BRANCH_P
2566 (XVECEXP (final_sequence, 0, 0))));
2567 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2569 ASSEMBLER_DIALECT ? "/" : ".", label);
2570 fprintf (asm_out_file, "\tnop\n");
2571 output_asm_insn ("bra\t%l0", operands);
2572 fprintf (asm_out_file, "\tnop\n");
2573 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2577 /* When relaxing, fall through. */
2582 sprintf (buffer, "b%s%ss\t%%l0",
2584 ASSEMBLER_DIALECT ? "/" : ".");
2585 output_asm_insn (buffer, &operands[0]);
2590 /* There should be no longer branches now - that would
2591 indicate that something has destroyed the branches set
2592 up in machine_dependent_reorg. */
2597 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2598 fill in operands 9 as a label to the successor insn.
2599 We try to use jump threading where possible.
2600 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2601 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2602 follow jmp and bt, if the address is in range. */
2604 output_branchy_insn (enum rtx_code code, const char *templ,
2605 rtx insn, rtx *operands)
2607 rtx next_insn = NEXT_INSN (insn);
2609 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2611 rtx src = SET_SRC (PATTERN (next_insn));
2612 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2614 /* Following branch not taken */
2615 operands[9] = gen_label_rtx ();
2616 emit_label_after (operands[9], next_insn);
2617 INSN_ADDRESSES_NEW (operands[9],
2618 INSN_ADDRESSES (INSN_UID (next_insn))
2619 + get_attr_length (next_insn));
2624 int offset = (branch_dest (next_insn)
2625 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2626 if (offset >= -252 && offset <= 258)
2628 if (GET_CODE (src) == IF_THEN_ELSE)
2630 src = XEXP (src, 1);
2636 operands[9] = gen_label_rtx ();
2637 emit_label_after (operands[9], insn);
2638 INSN_ADDRESSES_NEW (operands[9],
2639 INSN_ADDRESSES (INSN_UID (insn))
2640 + get_attr_length (insn));
2645 output_ieee_ccmpeq (rtx insn, rtx *operands)
2647 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2651 /* Output the start of the assembler file. */
2654 sh_file_start (void)
2656 default_file_start ();
2659 /* We need to show the text section with the proper
2660 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2661 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2662 will complain. We can teach GAS specifically about the
2663 default attributes for our choice of text section, but
2664 then we would have to change GAS again if/when we change
2665 the text section name. */
2666 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2668 /* Switch to the data section so that the coffsem symbol
2669 isn't in the text section. */
2670 switch_to_section (data_section);
2672 if (TARGET_LITTLE_ENDIAN)
2673 fputs ("\t.little\n", asm_out_file);
2677 if (TARGET_SHCOMPACT)
2678 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2679 else if (TARGET_SHMEDIA)
2680 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2681 TARGET_SHMEDIA64 ? 64 : 32);
2685 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2688 unspec_caller_rtx_p (rtx pat)
2693 split_const (pat, &base, &offset);
2694 if (GET_CODE (base) == UNSPEC)
2696 if (XINT (base, 1) == UNSPEC_CALLER)
2698 for (i = 0; i < XVECLEN (base, 0); i++)
2699 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2705 /* Indicate that INSN cannot be duplicated. This is true for insn
2706 that generates a unique label. */
2709 sh_cannot_copy_insn_p (rtx insn)
2713 if (!reload_completed || !flag_pic)
2716 if (!NONJUMP_INSN_P (insn))
2718 if (asm_noperands (insn) >= 0)
2721 pat = PATTERN (insn);
2722 if (GET_CODE (pat) != SET)
2724 pat = SET_SRC (pat);
2726 if (unspec_caller_rtx_p (pat))
2732 /* Actual number of instructions used to make a shift by N. */
2733 static const char ashiftrt_insns[] =
2734 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2736 /* Left shift and logical right shift are the same. */
2737 static const char shift_insns[] =
2738 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2740 /* Individual shift amounts needed to get the above length sequences.
2741 One bit right shifts clobber the T bit, so when possible, put one bit
2742 shifts in the middle of the sequence, so the ends are eligible for
2743 branch delay slots. */
2744 static const short shift_amounts[32][5] = {
2745 {0}, {1}, {2}, {2, 1},
2746 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2747 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2748 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2749 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2750 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2751 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2752 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2754 /* Likewise, but for shift amounts < 16, up to three highmost bits
2755 might be clobbered. This is typically used when combined with some
2756 kind of sign or zero extension. */
2758 static const char ext_shift_insns[] =
2759 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2761 static const short ext_shift_amounts[32][4] = {
2762 {0}, {1}, {2}, {2, 1},
2763 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2764 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2765 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2766 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2767 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2768 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2769 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2771 /* Assuming we have a value that has been sign-extended by at least one bit,
2772 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2773 to shift it by N without data loss, and quicker than by other means? */
2774 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2776 /* This is used in length attributes in sh.md to help compute the length
2777 of arbitrary constant shift instructions. */
2780 shift_insns_rtx (rtx insn)
2782 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2783 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2784 enum rtx_code shift_code = GET_CODE (set_src);
2789 return ashiftrt_insns[shift_count];
2792 return shift_insns[shift_count];
2798 /* Return the cost of a shift. */
2805 /* There is no pattern for constant first operand. */
2806 if (CONST_INT_P (XEXP (x, 0)))
2810 return COSTS_N_INSNS (1);
2812 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2814 if (GET_MODE (x) == DImode
2815 && CONST_INT_P (XEXP (x, 1))
2816 && INTVAL (XEXP (x, 1)) == 1)
2817 return COSTS_N_INSNS (2);
2819 /* Everything else is invalid, because there is no pattern for it. */
2822 /* If shift by a non constant, then this will be expensive. */
2823 if (!CONST_INT_P (XEXP (x, 1)))
2824 return COSTS_N_INSNS (SH_DYNAMIC_SHIFT_COST);
2826 /* Otherwise, return the true cost in instructions. Cope with out of range
2827 shift counts more or less arbitrarily. */
2828 value = INTVAL (XEXP (x, 1)) & 31;
2830 if (GET_CODE (x) == ASHIFTRT)
2832 int cost = ashiftrt_insns[value];
2833 /* If SH3, then we put the constant in a reg and use shad. */
2834 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2835 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2836 return COSTS_N_INSNS (cost);
2839 return COSTS_N_INSNS (shift_insns[value]);
2842 /* Return the cost of an AND/XOR/IOR operation. */
2845 and_xor_ior_costs (rtx x, int code)
2849 /* A logical operation with two registers is a single cycle
2851 if (!CONST_INT_P (XEXP (x, 1)))
2854 i = INTVAL (XEXP (x, 1));
2858 if (satisfies_constraint_I10 (XEXP (x, 1))
2859 || satisfies_constraint_J16 (XEXP (x, 1)))
2862 return 1 + rtx_cost (XEXP (x, 1), AND, 1, !optimize_size);
2865 /* These constants are single cycle extu.[bw] instructions. */
2866 if ((i == 0xff || i == 0xffff) && code == AND)
2868 /* Constants that can be used in an instruction as an immediate are
2869 a single cycle, but this requires r0, so make it a little more
2871 if (CONST_OK_FOR_K08 (i))
2873 /* Constants that can be loaded with a mov immediate need one more cycle.
2874 This case is probably unnecessary. */
2875 if (CONST_OK_FOR_I08 (i))
2877 /* Any other constant requires an additional 2 cycle pc-relative load.
2878 This case is probably unnecessary. */
2882 /* Return the cost of an addition or a subtraction. */
2887 /* Adding a register is a single cycle insn. */
2888 if (REG_P (XEXP (x, 1))
2889 || GET_CODE (XEXP (x, 1)) == SUBREG)
2892 /* Likewise for small constants. */
2893 if (CONST_INT_P (XEXP (x, 1))
2894 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2898 switch (GET_CODE (XEXP (x, 1)))
2903 return TARGET_SHMEDIA64 ? 5 : 3;
2906 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2908 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2910 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2918 /* Any other constant requires a 2 cycle pc-relative load plus an
2923 /* Return the cost of a multiply. */
2925 multcosts (rtx x ATTRIBUTE_UNUSED)
2927 if (sh_multcost >= 0)
2930 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2931 accept constants. Ideally, we would use a cost of one or two and
2932 add the cost of the operand, but disregard the latter when inside loops
2933 and loop invariant code motion is still to follow.
2934 Using a multiply first and splitting it later if it's a loss
2935 doesn't work because of different sign / zero extension semantics
2936 of multiplies vs. shifts. */
2937 return optimize_size ? 2 : 3;
2941 /* We have a mul insn, so we can never take more than the mul and the
2942 read of the mac reg, but count more because of the latency and extra
2949 /* If we're aiming at small code, then just count the number of
2950 insns in a multiply call sequence. */
2954 /* Otherwise count all the insns in the routine we'd be calling too. */
2958 /* Compute a (partial) cost for rtx X. Return true if the complete
2959 cost has been computed, and false if subexpressions should be
2960 scanned. In either case, *TOTAL contains the cost result. */
2963 sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2964 int *total, bool speed ATTRIBUTE_UNUSED)
2971 if (INTVAL (x) == 0)
2973 else if (outer_code == AND && and_operand ((x), DImode))
2975 else if ((outer_code == IOR || outer_code == XOR
2976 || outer_code == PLUS)
2977 && CONST_OK_FOR_I10 (INTVAL (x)))
2979 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2980 *total = COSTS_N_INSNS (outer_code != SET);
2981 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2982 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2983 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2984 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2986 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2989 if (CONST_OK_FOR_I08 (INTVAL (x)))
2991 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2992 && CONST_OK_FOR_K08 (INTVAL (x)))
2994 /* prepare_cmp_insn will force costly constants int registers before
2995 the cbranch[sd]i4 patterns can see them, so preserve potentially
2996 interesting ones not covered by I08 above. */
2997 else if (outer_code == COMPARE
2998 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2999 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
3000 || INTVAL (x) == 0x7fffffff
3001 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
3008 /* An and with a constant compared against zero is
3009 most likely going to be a TST #imm, R0 instruction.
3010 Notice that this does not catch the zero_extract variants from
3012 if (GET_CODE (XEXP (x, 0)) == AND
3013 && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 0)
3024 if (TARGET_SHMEDIA64)
3025 *total = COSTS_N_INSNS (4);
3026 else if (TARGET_SHMEDIA32)
3027 *total = COSTS_N_INSNS (2);
3034 *total = COSTS_N_INSNS (4);
3035 /* prepare_cmp_insn will force costly constants int registers before
3036 the cbranchdi4 pattern can see them, so preserve potentially
3037 interesting ones. */
3038 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
3044 if (x == CONST0_RTX (GET_MODE (x)))
3046 else if (sh_1el_vec (x, VOIDmode))
3047 *total = outer_code != SET;
3048 if (sh_rep_vec (x, VOIDmode))
3049 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3050 + (outer_code != SET));
3051 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3056 *total = COSTS_N_INSNS (addsubcosts (x));
3062 *total = COSTS_N_INSNS (and_xor_ior_costs (x, code));
3066 *total = COSTS_N_INSNS (multcosts (x));
3072 *total = shiftcosts (x);
3079 *total = COSTS_N_INSNS (20);
3083 if (sh_1el_vec (x, VOIDmode))
3084 *total = outer_code != SET;
3085 if (sh_rep_vec (x, VOIDmode))
3086 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3087 + (outer_code != SET));
3088 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3101 /* Compute the cost of an address. For the SH, all valid addresses are
3102 the same cost. Use a slightly higher cost for reg + reg addressing,
3103 since it increases pressure on r0. */
3106 sh_address_cost (rtx X,
3107 bool speed ATTRIBUTE_UNUSED)
3109 return (GET_CODE (X) == PLUS
3110 && ! CONSTANT_P (XEXP (X, 1))
3111 && ! TARGET_SHMEDIA ? 1 : 0);
3114 /* Code to expand a shift. */
3117 gen_ashift (int type, int n, rtx reg)
3119 /* Negative values here come from the shift_amounts array. */
3132 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3136 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3138 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3141 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3146 /* Same for HImode */
3149 gen_ashift_hi (int type, int n, rtx reg)
3151 /* Negative values here come from the shift_amounts array. */
3165 /* We don't have HImode right shift operations because using the
3166 ordinary 32 bit shift instructions for that doesn't generate proper
3167 zero/sign extension.
3168 gen_ashift_hi is only called in contexts where we know that the
3169 sign extension works out correctly. */
3172 if (GET_CODE (reg) == SUBREG)
3174 offset = SUBREG_BYTE (reg);
3175 reg = SUBREG_REG (reg);
3177 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3181 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3186 /* Output RTL to split a constant shift into its component SH constant
3187 shift instructions. */
3190 gen_shifty_op (int code, rtx *operands)
3192 int value = INTVAL (operands[2]);
3195 /* Truncate the shift count in case it is out of bounds. */
3200 if (code == LSHIFTRT)
3202 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3203 emit_insn (gen_movt (operands[0]));
3206 else if (code == ASHIFT)
3208 /* There is a two instruction sequence for 31 bit left shifts,
3209 but it requires r0. */
3210 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3212 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3213 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3218 else if (value == 0)
3220 /* This can happen even when optimizing, if there were subregs before
3221 reload. Don't output a nop here, as this is never optimized away;
3222 use a no-op move instead. */
3223 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3227 max = shift_insns[value];
3228 for (i = 0; i < max; i++)
3229 gen_ashift (code, shift_amounts[value][i], operands[0]);
3232 /* Same as above, but optimized for values where the topmost bits don't
3236 gen_shifty_hi_op (int code, rtx *operands)
3238 int value = INTVAL (operands[2]);
3240 void (*gen_fun) (int, int, rtx);
3242 /* This operation is used by and_shl for SImode values with a few
3243 high bits known to be cleared. */
3247 emit_insn (gen_nop ());
3251 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3254 max = ext_shift_insns[value];
3255 for (i = 0; i < max; i++)
3256 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3259 /* When shifting right, emit the shifts in reverse order, so that
3260 solitary negative values come first. */
3261 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3262 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3265 /* Output RTL for an arithmetic right shift. */
3267 /* ??? Rewrite to use super-optimizer sequences. */
3270 expand_ashiftrt (rtx *operands)
3276 if (TARGET_SH3 || TARGET_SH2A)
3278 if (!CONST_INT_P (operands[2]))
3280 rtx count = copy_to_mode_reg (SImode, operands[2]);
3281 emit_insn (gen_negsi2 (count, count));
3282 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3285 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3286 > 1 + SH_DYNAMIC_SHIFT_COST)
3289 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3290 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3294 if (!CONST_INT_P (operands[2]))
3297 value = INTVAL (operands[2]) & 31;
3301 /* If we are called from abs expansion, arrange things so that we
3302 we can use a single MT instruction that doesn't clobber the source,
3303 if LICM can hoist out the load of the constant zero. */
3304 if (currently_expanding_to_rtl)
3306 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3308 emit_insn (gen_mov_neg_si_t (operands[0]));
3311 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3314 else if (value >= 16 && value <= 19)
3316 wrk = gen_reg_rtx (SImode);
3317 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3320 gen_ashift (ASHIFTRT, 1, wrk);
3321 emit_move_insn (operands[0], wrk);
3324 /* Expand a short sequence inline, longer call a magic routine. */
3325 else if (value <= 5)
3327 wrk = gen_reg_rtx (SImode);
3328 emit_move_insn (wrk, operands[1]);
3330 gen_ashift (ASHIFTRT, 1, wrk);
3331 emit_move_insn (operands[0], wrk);
3335 wrk = gen_reg_rtx (Pmode);
3337 /* Load the value into an arg reg and call a helper. */
3338 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3339 sprintf (func, "__ashiftrt_r4_%d", value);
3340 function_symbol (wrk, func, SFUNC_STATIC);
3341 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3342 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3347 sh_dynamicalize_shift_p (rtx count)
3349 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3352 /* Try to find a good way to implement the combiner pattern
3353 [(set (match_operand:SI 0 "register_operand" "r")
3354 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3355 (match_operand:SI 2 "const_int_operand" "n"))
3356 (match_operand:SI 3 "const_int_operand" "n"))) .
3357 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3358 return 0 for simple right / left or left/right shift combination.
3359 return 1 for a combination of shifts with zero_extend.
3360 return 2 for a combination of shifts with an AND that needs r0.
3361 return 3 for a combination of shifts with an AND that needs an extra
3362 scratch register, when the three highmost bits of the AND mask are clear.
3363 return 4 for a combination of shifts with an AND that needs an extra
3364 scratch register, when any of the three highmost bits of the AND mask
3366 If ATTRP is set, store an initial right shift width in ATTRP[0],
3367 and the instruction length in ATTRP[1] . These values are not valid
3369 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3370 shift_amounts for the last shift value that is to be used before the
3373 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3375 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3376 int left = INTVAL (left_rtx), right;
3378 int cost, best_cost = 10000;
3379 int best_right = 0, best_len = 0;
3383 if (left < 0 || left > 31)
3385 if (CONST_INT_P (mask_rtx))
3386 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3388 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3389 /* Can this be expressed as a right shift / left shift pair? */
3390 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3391 right = exact_log2 (lsb);
3392 mask2 = ~(mask + lsb - 1);
3393 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3394 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3396 best_cost = shift_insns[right] + shift_insns[right + left];
3397 /* mask has no trailing zeroes <==> ! right */
3398 else if (! right && mask2 == ~(lsb2 - 1))
3400 int late_right = exact_log2 (lsb2);
3401 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3403 /* Try to use zero extend. */
3404 if (mask2 == ~(lsb2 - 1))
3408 for (width = 8; width <= 16; width += 8)
3410 /* Can we zero-extend right away? */
3411 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3414 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3415 if (cost < best_cost)
3426 /* ??? Could try to put zero extend into initial right shift,
3427 or even shift a bit left before the right shift. */
3428 /* Determine value of first part of left shift, to get to the
3429 zero extend cut-off point. */
3430 first = width - exact_log2 (lsb2) + right;
3431 if (first >= 0 && right + left - first >= 0)
3433 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3434 + ext_shift_insns[right + left - first];
3435 if (cost < best_cost)
3447 /* Try to use r0 AND pattern */
3448 for (i = 0; i <= 2; i++)
3452 if (! CONST_OK_FOR_K08 (mask >> i))
3454 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3455 if (cost < best_cost)
3460 best_len = cost - 1;
3463 /* Try to use a scratch register to hold the AND operand. */
3464 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3465 for (i = 0; i <= 2; i++)
3469 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3470 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3471 if (cost < best_cost)
3476 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3482 attrp[0] = best_right;
3483 attrp[1] = best_len;
3488 /* This is used in length attributes of the unnamed instructions
3489 corresponding to shl_and_kind return values of 1 and 2. */
3491 shl_and_length (rtx insn)
3493 rtx set_src, left_rtx, mask_rtx;
3496 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3497 left_rtx = XEXP (XEXP (set_src, 0), 1);
3498 mask_rtx = XEXP (set_src, 1);
3499 shl_and_kind (left_rtx, mask_rtx, attributes);
3500 return attributes[1];
3503 /* This is used in length attribute of the and_shl_scratch instruction. */
3506 shl_and_scr_length (rtx insn)
3508 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3509 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3510 rtx op = XEXP (set_src, 0);
3511 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3512 op = XEXP (XEXP (op, 0), 0);
3513 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3516 /* Generate rtl for instructions for which shl_and_kind advised a particular
3517 method of generating them, i.e. returned zero. */
3520 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3523 unsigned HOST_WIDE_INT mask;
3524 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3525 int right, total_shift;
3526 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3528 right = attributes[0];
3529 total_shift = INTVAL (left_rtx) + right;
3530 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3537 int first = attributes[2];
3542 emit_insn ((mask << right) <= 0xff
3543 ? gen_zero_extendqisi2 (dest,
3544 gen_lowpart (QImode, source))
3545 : gen_zero_extendhisi2 (dest,
3546 gen_lowpart (HImode, source)));
3550 emit_insn (gen_movsi (dest, source));
3554 operands[2] = GEN_INT (right);
3555 gen_shifty_hi_op (LSHIFTRT, operands);
3559 operands[2] = GEN_INT (first);
3560 gen_shifty_hi_op (ASHIFT, operands);
3561 total_shift -= first;
3565 emit_insn (mask <= 0xff
3566 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3567 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3568 if (total_shift > 0)
3570 operands[2] = GEN_INT (total_shift);
3571 gen_shifty_hi_op (ASHIFT, operands);
3576 shift_gen_fun = gen_shifty_op;
3578 /* If the topmost bit that matters is set, set the topmost bits
3579 that don't matter. This way, we might be able to get a shorter
3581 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3582 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3584 /* Don't expand fine-grained when combining, because that will
3585 make the pattern fail. */
3586 if (currently_expanding_to_rtl
3587 || reload_in_progress || reload_completed)
3591 /* Cases 3 and 4 should be handled by this split
3592 only while combining */
3593 gcc_assert (kind <= 2);
3596 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3599 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3604 operands[2] = GEN_INT (total_shift);
3605 shift_gen_fun (ASHIFT, operands);
3612 if (kind != 4 && total_shift < 16)
3614 neg = -ext_shift_amounts[total_shift][1];
3616 neg -= ext_shift_amounts[total_shift][2];
3620 emit_insn (gen_and_shl_scratch (dest, source,
3623 GEN_INT (total_shift + neg),
3625 emit_insn (gen_movsi (dest, dest));
3632 /* Try to find a good way to implement the combiner pattern
3633 [(set (match_operand:SI 0 "register_operand" "=r")
3634 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3635 (match_operand:SI 2 "const_int_operand" "n")
3636 (match_operand:SI 3 "const_int_operand" "n")
3638 (clobber (reg:SI T_REG))]
3639 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3640 return 0 for simple left / right shift combination.
3641 return 1 for left shift / 8 bit sign extend / left shift.
3642 return 2 for left shift / 16 bit sign extend / left shift.
3643 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3644 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3645 return 5 for left shift / 16 bit sign extend / right shift
3646 return 6 for < 8 bit sign extend / left shift.
3647 return 7 for < 8 bit sign extend / left shift / single right shift.
3648 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3651 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3653 int left, size, insize, ext;
3654 int cost = 0, best_cost;
3657 left = INTVAL (left_rtx);
3658 size = INTVAL (size_rtx);
3659 insize = size - left;
3660 gcc_assert (insize > 0);
3661 /* Default to left / right shift. */
3663 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3666 /* 16 bit shift / sign extend / 16 bit shift */
3667 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3668 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3669 below, by alternative 3 or something even better. */
3670 if (cost < best_cost)
3676 /* Try a plain sign extend between two shifts. */
3677 for (ext = 16; ext >= insize; ext -= 8)
3681 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3682 if (cost < best_cost)
3684 kind = ext / (unsigned) 8;
3688 /* Check if we can do a sloppy shift with a final signed shift
3689 restoring the sign. */
3690 if (EXT_SHIFT_SIGNED (size - ext))
3691 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3692 /* If not, maybe it's still cheaper to do the second shift sloppy,
3693 and do a final sign extend? */
3694 else if (size <= 16)
3695 cost = ext_shift_insns[ext - insize] + 1
3696 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3699 if (cost < best_cost)
3701 kind = ext / (unsigned) 8 + 2;
3705 /* Check if we can sign extend in r0 */
3708 cost = 3 + shift_insns[left];
3709 if (cost < best_cost)
3714 /* Try the same with a final signed shift. */
3717 cost = 3 + ext_shift_insns[left + 1] + 1;
3718 if (cost < best_cost)
3725 if (TARGET_SH3 || TARGET_SH2A)
3727 /* Try to use a dynamic shift. */
3728 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3729 if (cost < best_cost)
3740 /* Function to be used in the length attribute of the instructions
3741 implementing this pattern. */
3744 shl_sext_length (rtx insn)
3746 rtx set_src, left_rtx, size_rtx;
3749 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3750 left_rtx = XEXP (XEXP (set_src, 0), 1);
3751 size_rtx = XEXP (set_src, 1);
3752 shl_sext_kind (left_rtx, size_rtx, &cost);
3756 /* Generate rtl for this pattern */
3759 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3762 int left, size, insize, cost;
3765 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3766 left = INTVAL (left_rtx);
3767 size = INTVAL (size_rtx);
3768 insize = size - left;
3776 int ext = kind & 1 ? 8 : 16;
3777 int shift2 = size - ext;
3779 /* Don't expand fine-grained when combining, because that will
3780 make the pattern fail. */
3781 if (! currently_expanding_to_rtl
3782 && ! reload_in_progress && ! reload_completed)
3784 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3785 emit_insn (gen_movsi (dest, source));
3789 emit_insn (gen_movsi (dest, source));
3793 operands[2] = GEN_INT (ext - insize);
3794 gen_shifty_hi_op (ASHIFT, operands);
3797 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3798 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3803 operands[2] = GEN_INT (shift2);
3804 gen_shifty_op (ASHIFT, operands);
3811 if (EXT_SHIFT_SIGNED (shift2))
3813 operands[2] = GEN_INT (shift2 + 1);
3814 gen_shifty_op (ASHIFT, operands);
3815 operands[2] = const1_rtx;
3816 gen_shifty_op (ASHIFTRT, operands);
3819 operands[2] = GEN_INT (shift2);
3820 gen_shifty_hi_op (ASHIFT, operands);
3824 operands[2] = GEN_INT (-shift2);
3825 gen_shifty_hi_op (LSHIFTRT, operands);
3827 emit_insn (size <= 8
3828 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3829 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3836 if (! currently_expanding_to_rtl
3837 && ! reload_in_progress && ! reload_completed)
3838 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3842 operands[2] = GEN_INT (16 - insize);
3843 gen_shifty_hi_op (ASHIFT, operands);
3844 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3846 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3848 gen_ashift (ASHIFTRT, 1, dest);
3853 /* Don't expand fine-grained when combining, because that will
3854 make the pattern fail. */
3855 if (! currently_expanding_to_rtl
3856 && ! reload_in_progress && ! reload_completed)
3858 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3859 emit_insn (gen_movsi (dest, source));
3862 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3863 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3864 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3866 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3867 gen_shifty_op (ASHIFT, operands);
3869 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3877 /* Prefix a symbol_ref name with "datalabel". */
3880 gen_datalabel_ref (rtx sym)
3884 if (GET_CODE (sym) == LABEL_REF)
3885 return gen_rtx_CONST (GET_MODE (sym),
3886 gen_rtx_UNSPEC (GET_MODE (sym),
3890 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3892 str = XSTR (sym, 0);
3893 /* Share all SYMBOL_REF strings with the same value - that is important
3895 str = IDENTIFIER_POINTER (get_identifier (str));
3896 XSTR (sym, 0) = str;
3902 static alloc_pool label_ref_list_pool;
3904 typedef struct label_ref_list_d
3907 struct label_ref_list_d *next;
3908 } *label_ref_list_t;
3910 /* The SH cannot load a large constant into a register, constants have to
3911 come from a pc relative load. The reference of a pc relative load
3912 instruction must be less than 1k in front of the instruction. This
3913 means that we often have to dump a constant inside a function, and
3914 generate code to branch around it.
3916 It is important to minimize this, since the branches will slow things
3917 down and make things bigger.
3919 Worst case code looks like:
3937 We fix this by performing a scan before scheduling, which notices which
3938 instructions need to have their operands fetched from the constant table
3939 and builds the table.
3943 scan, find an instruction which needs a pcrel move. Look forward, find the
3944 last barrier which is within MAX_COUNT bytes of the requirement.
3945 If there isn't one, make one. Process all the instructions between
3946 the find and the barrier.
3948 In the above example, we can tell that L3 is within 1k of L1, so
3949 the first move can be shrunk from the 3 insn+constant sequence into
3950 just 1 insn, and the constant moved to L3 to make:
3961 Then the second move becomes the target for the shortening process. */
3965 rtx value; /* Value in table. */
3966 rtx label; /* Label of value. */
3967 label_ref_list_t wend; /* End of window. */
3968 enum machine_mode mode; /* Mode of value. */
3970 /* True if this constant is accessed as part of a post-increment
3971 sequence. Note that HImode constants are never accessed in this way. */
3972 bool part_of_sequence_p;
3975 /* The maximum number of constants that can fit into one pool, since
3976 constants in the range 0..510 are at least 2 bytes long, and in the
3977 range from there to 1018 at least 4 bytes. */
3979 #define MAX_POOL_SIZE 372
3980 static pool_node pool_vector[MAX_POOL_SIZE];
3981 static int pool_size;
3982 static rtx pool_window_label;
3983 static int pool_window_last;
3985 static int max_labelno_before_reorg;
3987 /* ??? If we need a constant in HImode which is the truncated value of a
3988 constant we need in SImode, we could combine the two entries thus saving
3989 two bytes. Is this common enough to be worth the effort of implementing
3992 /* ??? This stuff should be done at the same time that we shorten branches.
3993 As it is now, we must assume that all branches are the maximum size, and
3994 this causes us to almost always output constant pools sooner than
3997 /* Add a constant to the pool and return its label. */
4000 add_constant (rtx x, enum machine_mode mode, rtx last_value)
4004 label_ref_list_t ref, newref;
4006 /* First see if we've already got it. */
4007 for (i = 0; i < pool_size; i++)
4009 if (x->code == pool_vector[i].value->code
4010 && mode == pool_vector[i].mode)
4012 if (x->code == CODE_LABEL)
4014 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4017 if (rtx_equal_p (x, pool_vector[i].value))
4022 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
4024 new_rtx = gen_label_rtx ();
4025 LABEL_REFS (new_rtx) = pool_vector[i].label;
4026 pool_vector[i].label = lab = new_rtx;
4028 if (lab && pool_window_label)
4030 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4031 newref->label = pool_window_label;
4032 ref = pool_vector[pool_window_last].wend;
4034 pool_vector[pool_window_last].wend = newref;
4037 pool_window_label = new_rtx;
4038 pool_window_last = i;
4044 /* Need a new one. */
4045 pool_vector[pool_size].value = x;
4046 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
4049 pool_vector[pool_size - 1].part_of_sequence_p = true;
4052 lab = gen_label_rtx ();
4053 pool_vector[pool_size].mode = mode;
4054 pool_vector[pool_size].label = lab;
4055 pool_vector[pool_size].wend = NULL;
4056 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
4057 if (lab && pool_window_label)
4059 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4060 newref->label = pool_window_label;
4061 ref = pool_vector[pool_window_last].wend;
4063 pool_vector[pool_window_last].wend = newref;
4066 pool_window_label = lab;
4067 pool_window_last = pool_size;
4072 /* Output the literal table. START, if nonzero, is the first instruction
4073 this table is needed for, and also indicates that there is at least one
4074 casesi_worker_2 instruction; We have to emit the operand3 labels from
4075 these insns at a 4-byte aligned position. BARRIER is the barrier
4076 after which we are to place the table. */
4079 dump_table (rtx start, rtx barrier)
4085 label_ref_list_t ref;
4088 /* Do two passes, first time dump out the HI sized constants. */
4090 for (i = 0; i < pool_size; i++)
4092 pool_node *p = &pool_vector[i];
4094 if (p->mode == HImode)
4098 scan = emit_insn_after (gen_align_2 (), scan);
4101 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4102 scan = emit_label_after (lab, scan);
4103 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4105 for (ref = p->wend; ref; ref = ref->next)
4108 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4111 else if (p->mode == DFmode)
4119 scan = emit_insn_after (gen_align_4 (), scan);
4121 for (; start != barrier; start = NEXT_INSN (start))
4122 if (NONJUMP_INSN_P (start)
4123 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4125 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4126 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4128 scan = emit_label_after (lab, scan);
4131 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4133 rtx align_insn = NULL_RTX;
4135 scan = emit_label_after (gen_label_rtx (), scan);
4136 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4139 for (i = 0; i < pool_size; i++)
4141 pool_node *p = &pool_vector[i];
4149 if (align_insn && !p->part_of_sequence_p)
4151 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4152 emit_label_before (lab, align_insn);
4153 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4155 for (ref = p->wend; ref; ref = ref->next)
4158 emit_insn_before (gen_consttable_window_end (lab),
4161 delete_insn (align_insn);
4162 align_insn = NULL_RTX;
4167 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4168 scan = emit_label_after (lab, scan);
4169 scan = emit_insn_after (gen_consttable_4 (p->value,
4171 need_align = ! need_align;
4177 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4182 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4183 scan = emit_label_after (lab, scan);
4184 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4191 if (p->mode != HImode)
4193 for (ref = p->wend; ref; ref = ref->next)
4196 scan = emit_insn_after (gen_consttable_window_end (lab),
4205 for (i = 0; i < pool_size; i++)
4207 pool_node *p = &pool_vector[i];
4218 scan = emit_label_after (gen_label_rtx (), scan);
4219 scan = emit_insn_after (gen_align_4 (), scan);
4221 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4222 scan = emit_label_after (lab, scan);
4223 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4231 scan = emit_label_after (gen_label_rtx (), scan);
4232 scan = emit_insn_after (gen_align_4 (), scan);
4234 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4235 scan = emit_label_after (lab, scan);
4236 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4243 if (p->mode != HImode)
4245 for (ref = p->wend; ref; ref = ref->next)
4248 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4253 scan = emit_insn_after (gen_consttable_end (), scan);
4254 scan = emit_barrier_after (scan);
4256 pool_window_label = NULL_RTX;
4257 pool_window_last = 0;
4260 /* Return nonzero if constant would be an ok source for a
4261 mov.w instead of a mov.l. */
4266 return (CONST_INT_P (src)
4267 && INTVAL (src) >= -32768
4268 && INTVAL (src) <= 32767);
4271 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4273 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4275 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4276 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4277 need to fix it if the input value is CONST_OK_FOR_I08. */
4280 broken_move (rtx insn)
4282 if (NONJUMP_INSN_P (insn))
4284 rtx pat = PATTERN (insn);
4285 if (GET_CODE (pat) == PARALLEL)
4286 pat = XVECEXP (pat, 0, 0);
4287 if (GET_CODE (pat) == SET
4288 /* We can load any 8-bit value if we don't care what the high
4289 order bits end up as. */
4290 && GET_MODE (SET_DEST (pat)) != QImode
4291 && (CONSTANT_P (SET_SRC (pat))
4292 /* Match mova_const. */
4293 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4294 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4295 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4297 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4298 && (fp_zero_operand (SET_SRC (pat))
4299 || fp_one_operand (SET_SRC (pat)))
4300 /* In general we don't know the current setting of fpscr, so disable fldi.
4301 There is an exception if this was a register-register move
4302 before reload - and hence it was ascertained that we have
4303 single precision setting - and in a post-reload optimization
4304 we changed this to do a constant load. In that case
4305 we don't have an r0 clobber, hence we must use fldi. */
4307 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4309 && REG_P (SET_DEST (pat))
4310 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4312 && GET_MODE (SET_DEST (pat)) == SImode
4313 && (satisfies_constraint_I20 (SET_SRC (pat))
4314 || satisfies_constraint_I28 (SET_SRC (pat))))
4315 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4325 return (NONJUMP_INSN_P (insn)
4326 && GET_CODE (PATTERN (insn)) == SET
4327 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4328 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4329 /* Don't match mova_const. */
4330 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4333 /* Fix up a mova from a switch that went out of range. */
4335 fixup_mova (rtx mova)
4337 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4340 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4341 INSN_CODE (mova) = -1;
4346 rtx lab = gen_label_rtx ();
4347 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4351 worker = NEXT_INSN (worker);
4353 && !LABEL_P (worker)
4354 && !JUMP_P (worker));
4355 } while (NOTE_P (worker)
4356 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4357 wpat = PATTERN (worker);
4358 wpat0 = XVECEXP (wpat, 0, 0);
4359 wpat1 = XVECEXP (wpat, 0, 1);
4360 wsrc = SET_SRC (wpat0);
4361 PATTERN (worker) = (gen_casesi_worker_2
4362 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4363 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4365 INSN_CODE (worker) = -1;
4366 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4367 base = gen_rtx_LABEL_REF (Pmode, lab);
4368 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4369 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4370 INSN_CODE (mova) = -1;
4374 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4375 *num_mova, and check if the new mova is not nested within the first one.
4376 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4377 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4379 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4381 int n_addr = 0; /* Initialization to shut up spurious warning. */
4382 int f_target, n_target = 0; /* Likewise. */
4386 /* If NEW_MOVA has no address yet, it will be handled later. */
4387 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4390 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4391 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4392 if (n_addr > n_target || n_addr + 1022 < n_target)
4394 /* Change the mova into a load.
4395 broken_move will then return true for it. */
4396 fixup_mova (new_mova);
4402 *first_mova = new_mova;
4407 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4412 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4413 > n_target - n_addr)
4415 fixup_mova (*first_mova);
4420 fixup_mova (new_mova);
4425 /* Find the last barrier from insn FROM which is close enough to hold the
4426 constant pool. If we can't find one, then create one near the end of
4430 find_barrier (int num_mova, rtx mova, rtx from)
4439 int leading_mova = num_mova;
4440 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4444 rtx last_got = NULL_RTX;
4445 rtx last_symoff = NULL_RTX;
4447 /* For HImode: range is 510, add 4 because pc counts from address of
4448 second instruction after this one, subtract 2 for the jump instruction
4449 that we may need to emit before the table, subtract 2 for the instruction
4450 that fills the jump delay slot (in very rare cases, reorg will take an
4451 instruction from after the constant pool or will leave the delay slot
4452 empty). This gives 510.
4453 For SImode: range is 1020, add 4 because pc counts from address of
4454 second instruction after this one, subtract 2 in case pc is 2 byte
4455 aligned, subtract 2 for the jump instruction that we may need to emit
4456 before the table, subtract 2 for the instruction that fills the jump
4457 delay slot. This gives 1018. */
4459 /* The branch will always be shortened now that the reference address for
4460 forward branches is the successor address, thus we need no longer make
4461 adjustments to the [sh]i_limit for -O0. */
4466 while (from && count_si < si_limit && count_hi < hi_limit)
4468 int inc = get_attr_length (from);
4471 /* If this is a label that existed at the time of the compute_alignments
4472 call, determine the alignment. N.B. When find_barrier recurses for
4473 an out-of-reach mova, we might see labels at the start of previously
4474 inserted constant tables. */
4476 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4479 new_align = 1 << label_to_alignment (from);
4480 else if (BARRIER_P (prev_nonnote_insn (from)))
4481 new_align = 1 << barrier_align (from);
4486 /* In case we are scanning a constant table because of recursion, check
4487 for explicit alignments. If the table is long, we might be forced
4488 to emit the new table in front of it; the length of the alignment
4489 might be the last straw. */
4490 else if (NONJUMP_INSN_P (from)
4491 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4492 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4493 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4494 /* When we find the end of a constant table, paste the new constant
4495 at the end. That is better than putting it in front because
4496 this way, we don't need extra alignment for adding a 4-byte-aligned
4497 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4498 else if (NONJUMP_INSN_P (from)
4499 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4500 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4503 if (BARRIER_P (from))
4507 found_barrier = from;
4509 /* If we are at the end of the function, or in front of an alignment
4510 instruction, we need not insert an extra alignment. We prefer
4511 this kind of barrier. */
4512 if (barrier_align (from) > 2)
4513 good_barrier = from;
4515 /* If we are at the end of a hot/cold block, dump the constants
4517 next = NEXT_INSN (from);
4520 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4524 if (broken_move (from))
4527 enum machine_mode mode;
4529 pat = PATTERN (from);
4530 if (GET_CODE (pat) == PARALLEL)
4531 pat = XVECEXP (pat, 0, 0);
4532 src = SET_SRC (pat);
4533 dst = SET_DEST (pat);
4534 mode = GET_MODE (dst);
4536 /* GOT pcrelat setting comes in pair of
4539 instructions. (plus add r0,r12).
4540 Remember if we see one without the other. */
4541 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
4542 last_got = last_got ? NULL_RTX : from;
4543 else if (PIC_ADDR_P (src))
4544 last_got = last_got ? NULL_RTX : from;
4546 /* We must explicitly check the mode, because sometimes the
4547 front end will generate code to load unsigned constants into
4548 HImode targets without properly sign extending them. */
4550 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4553 /* We put the short constants before the long constants, so
4554 we must count the length of short constants in the range
4555 for the long constants. */
4556 /* ??? This isn't optimal, but is easy to do. */
4561 /* We dump DF/DI constants before SF/SI ones, because
4562 the limit is the same, but the alignment requirements
4563 are higher. We may waste up to 4 additional bytes
4564 for alignment, and the DF/DI constant may have
4565 another SF/SI constant placed before it. */
4566 if (TARGET_SHCOMPACT
4568 && (mode == DFmode || mode == DImode))
4573 while (si_align > 2 && found_si + si_align - 2 > count_si)
4575 if (found_si > count_si)
4576 count_si = found_si;
4577 found_si += GET_MODE_SIZE (mode);
4579 si_limit -= GET_MODE_SIZE (mode);
4585 switch (untangle_mova (&num_mova, &mova, from))
4590 rtx src = SET_SRC (PATTERN (from));
4591 if (GET_CODE (src) == CONST
4592 && GET_CODE (XEXP (src, 0)) == UNSPEC
4593 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
4597 case 0: return find_barrier (0, 0, mova);
4602 = good_barrier ? good_barrier : found_barrier;
4606 if (found_si > count_si)
4607 count_si = found_si;
4609 else if (JUMP_TABLE_DATA_P (from))
4611 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4613 && (prev_nonnote_insn (from)
4614 == XEXP (MOVA_LABELREF (mova), 0))))
4616 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4618 /* We have just passed the barrier in front of the
4619 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4620 the ADDR_DIFF_VEC is accessed as data, just like our pool
4621 constants, this is a good opportunity to accommodate what
4622 we have gathered so far.
4623 If we waited any longer, we could end up at a barrier in
4624 front of code, which gives worse cache usage for separated
4625 instruction / data caches. */
4626 good_barrier = found_barrier;
4631 rtx body = PATTERN (from);
4632 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4635 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4636 else if (JUMP_P (from)
4641 /* There is a possibility that a bf is transformed into a bf/s by the
4642 delay slot scheduler. */
4643 if (JUMP_P (from) && !JUMP_TABLE_DATA_P (from)
4644 && get_attr_type (from) == TYPE_CBRANCH
4645 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (from)))) != SEQUENCE)
4651 if (new_align > si_align)
4653 si_limit -= (count_si - 1) & (new_align - si_align);
4654 si_align = new_align;
4656 count_si = (count_si + new_align - 1) & -new_align;
4661 if (new_align > hi_align)
4663 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4664 hi_align = new_align;
4666 count_hi = (count_hi + new_align - 1) & -new_align;
4668 from = NEXT_INSN (from);
4675 /* Try as we might, the leading mova is out of range. Change
4676 it into a load (which will become a pcload) and retry. */
4678 return find_barrier (0, 0, mova);
4682 /* Insert the constant pool table before the mova instruction,
4683 to prevent the mova label reference from going out of range. */
4685 good_barrier = found_barrier = barrier_before_mova;
4691 if (good_barrier && next_real_insn (found_barrier))
4692 found_barrier = good_barrier;
4696 /* We didn't find a barrier in time to dump our stuff,
4697 so we'll make one. */
4698 rtx label = gen_label_rtx ();
4700 /* Don't emit a constant table in the middle of insns for
4701 casesi_worker_2. This is a bit overkill but is enough
4702 because casesi_worker_2 wouldn't appear so frequently. */
4706 /* If we exceeded the range, then we must back up over the last
4707 instruction we looked at. Otherwise, we just need to undo the
4708 NEXT_INSN at the end of the loop. */
4709 if (PREV_INSN (from) != orig
4710 && (count_hi > hi_limit || count_si > si_limit))
4711 from = PREV_INSN (PREV_INSN (from));
4713 from = PREV_INSN (from);
4715 /* Don't emit a constant table int the middle of global pointer setting,
4716 since that that would move the addressing base GOT into another table.
4717 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
4718 in the pool anyway, so just move up the whole constant pool.
4719 However, avoid doing so when the last single GOT mov is the starting
4720 insn itself. Going past above the start insn would create a negative
4721 offset, causing errors. */
4722 if (last_got && last_got != orig)
4723 from = PREV_INSN (last_got);
4725 /* Don't insert the constant pool table at the position which
4726 may be the landing pad. */
4729 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
4730 from = PREV_INSN (from);
4732 /* Walk back to be just before any jump or label.
4733 Putting it before a label reduces the number of times the branch
4734 around the constant pool table will be hit. Putting it before
4735 a jump makes it more likely that the bra delay slot will be
4737 while (NOTE_P (from) || JUMP_P (from)
4739 from = PREV_INSN (from);
4741 /* Make sure we do not split between a call and its corresponding
4742 CALL_ARG_LOCATION note. */
4745 rtx next = NEXT_INSN (from);
4746 if (next && NOTE_P (next)
4747 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
4751 from = emit_jump_insn_after (gen_jump (label), from);
4752 JUMP_LABEL (from) = label;
4753 LABEL_NUSES (label) = 1;
4754 found_barrier = emit_barrier_after (from);
4755 emit_label_after (label, found_barrier);
4758 return found_barrier;
4761 /* If the instruction INSN is implemented by a special function, and we can
4762 positively find the register that is used to call the sfunc, and this
4763 register is not used anywhere else in this instruction - except as the
4764 destination of a set, return this register; else, return 0. */
4766 sfunc_uses_reg (rtx insn)
4769 rtx pattern, part, reg_part, reg;
4771 if (!NONJUMP_INSN_P (insn))
4773 pattern = PATTERN (insn);
4774 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4777 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4779 part = XVECEXP (pattern, 0, i);
4780 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4785 reg = XEXP (reg_part, 0);
4786 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4788 part = XVECEXP (pattern, 0, i);
4789 if (part == reg_part || GET_CODE (part) == CLOBBER)
4791 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4792 && REG_P (SET_DEST (part)))
4793 ? SET_SRC (part) : part)))
4799 /* See if the only way in which INSN uses REG is by calling it, or by
4800 setting it while calling it. Set *SET to a SET rtx if the register
4804 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4810 reg2 = sfunc_uses_reg (insn);
4811 if (reg2 && REGNO (reg2) == REGNO (reg))
4813 pattern = single_set (insn);
4815 && REG_P (SET_DEST (pattern))
4816 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4822 /* We don't use rtx_equal_p because we don't care if the mode is
4824 pattern = single_set (insn);
4826 && REG_P (SET_DEST (pattern))
4827 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4833 par = PATTERN (insn);
4834 if (GET_CODE (par) == PARALLEL)
4835 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4837 part = XVECEXP (par, 0, i);
4838 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4841 return reg_mentioned_p (reg, SET_SRC (pattern));
4847 pattern = PATTERN (insn);
4849 if (GET_CODE (pattern) == PARALLEL)
4853 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4854 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4856 pattern = XVECEXP (pattern, 0, 0);
4859 if (GET_CODE (pattern) == SET)
4861 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4863 /* We don't use rtx_equal_p, because we don't care if the
4864 mode is different. */
4865 if (!REG_P (SET_DEST (pattern))
4866 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4872 pattern = SET_SRC (pattern);
4875 if (GET_CODE (pattern) != CALL
4876 || !MEM_P (XEXP (pattern, 0))
4877 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4883 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4884 general registers. Bits 0..15 mean that the respective registers
4885 are used as inputs in the instruction. Bits 16..31 mean that the
4886 registers 0..15, respectively, are used as outputs, or are clobbered.
4887 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4889 regs_used (rtx x, int is_dest)
4897 code = GET_CODE (x);
4902 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4903 << (REGNO (x) + is_dest));
4907 rtx y = SUBREG_REG (x);
4912 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4914 subreg_regno_offset (REGNO (y),
4917 GET_MODE (x)) + is_dest));
4921 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4923 /* If there was a return value, it must have been indicated with USE. */
4938 fmt = GET_RTX_FORMAT (code);
4940 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4945 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4946 used |= regs_used (XVECEXP (x, i, j), is_dest);
4948 else if (fmt[i] == 'e')
4949 used |= regs_used (XEXP (x, i), is_dest);
4954 /* Create an instruction that prevents redirection of a conditional branch
4955 to the destination of the JUMP with address ADDR.
4956 If the branch needs to be implemented as an indirect jump, try to find
4957 a scratch register for it.
4958 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4959 If any preceding insn that doesn't fit into a delay slot is good enough,
4960 pass 1. Pass 2 if a definite blocking insn is needed.
4961 -1 is used internally to avoid deep recursion.
4962 If a blocking instruction is made or recognized, return it. */
4965 gen_block_redirect (rtx jump, int addr, int need_block)
4968 rtx prev = prev_nonnote_insn (jump);
4971 /* First, check if we already have an instruction that satisfies our need. */
4972 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4974 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4976 if (GET_CODE (PATTERN (prev)) == USE
4977 || GET_CODE (PATTERN (prev)) == CLOBBER
4978 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4980 else if ((need_block &= ~1) < 0)
4982 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4985 if (GET_CODE (PATTERN (jump)) == RETURN)
4989 /* Reorg even does nasty things with return insns that cause branches
4990 to go out of range - see find_end_label and callers. */
4991 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4993 /* We can't use JUMP_LABEL here because it might be undefined
4994 when not optimizing. */
4995 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4996 /* If the branch is out of range, try to find a scratch register for it. */
4998 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5002 /* Don't look for the stack pointer as a scratch register,
5003 it would cause trouble if an interrupt occurred. */
5004 unsigned attempt = 0x7fff, used;
5005 int jump_left = flag_expensive_optimizations + 1;
5007 /* It is likely that the most recent eligible instruction is wanted for
5008 the delay slot. Therefore, find out which registers it uses, and
5009 try to avoid using them. */
5011 for (scan = jump; (scan = PREV_INSN (scan)); )
5015 if (INSN_DELETED_P (scan))
5017 code = GET_CODE (scan);
5018 if (code == CODE_LABEL || code == JUMP_INSN)
5021 && GET_CODE (PATTERN (scan)) != USE
5022 && GET_CODE (PATTERN (scan)) != CLOBBER
5023 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
5025 attempt &= ~regs_used (PATTERN (scan), 0);
5029 for (used = dead = 0, scan = JUMP_LABEL (jump);
5030 (scan = NEXT_INSN (scan)); )
5034 if (INSN_DELETED_P (scan))
5036 code = GET_CODE (scan);
5039 used |= regs_used (PATTERN (scan), 0);
5040 if (code == CALL_INSN)
5041 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
5042 dead |= (used >> 16) & ~used;
5048 if (code == JUMP_INSN)
5050 if (jump_left-- && simplejump_p (scan))
5051 scan = JUMP_LABEL (scan);
5057 /* Mask out the stack pointer again, in case it was
5058 the only 'free' register we have found. */
5061 /* If the immediate destination is still in range, check for possible
5062 threading with a jump beyond the delay slot insn.
5063 Don't check if we are called recursively; the jump has been or will be
5064 checked in a different invocation then. */
5066 else if (optimize && need_block >= 0)
5068 rtx next = next_active_insn (next_active_insn (dest));
5069 if (next && JUMP_P (next)
5070 && GET_CODE (PATTERN (next)) == SET
5071 && recog_memoized (next) == CODE_FOR_jump_compact)
5073 dest = JUMP_LABEL (next);
5075 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5077 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
5083 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
5085 /* It would be nice if we could convert the jump into an indirect
5086 jump / far branch right now, and thus exposing all constituent
5087 instructions to further optimization. However, reorg uses
5088 simplejump_p to determine if there is an unconditional jump where
5089 it should try to schedule instructions from the target of the
5090 branch; simplejump_p fails for indirect jumps even if they have
5092 rtx insn = emit_insn_before (gen_indirect_jump_scratch
5093 (reg, GEN_INT (unspec_bbr_uid++)),
5095 /* ??? We would like this to have the scope of the jump, but that
5096 scope will change when a delay slot insn of an inner scope is added.
5097 Hence, after delay slot scheduling, we'll have to expect
5098 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5101 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
5102 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5105 else if (need_block)
5106 /* We can't use JUMP_LABEL here because it might be undefined
5107 when not optimizing. */
5108 return emit_insn_before (gen_block_branch_redirect
5109 (GEN_INT (unspec_bbr_uid++)),
5114 #define CONDJUMP_MIN -252
5115 #define CONDJUMP_MAX 262
5118 /* A label (to be placed) in front of the jump
5119 that jumps to our ultimate destination. */
5121 /* Where we are going to insert it if we cannot move the jump any farther,
5122 or the jump itself if we have picked up an existing jump. */
5124 /* The ultimate destination. */
5126 struct far_branch *prev;
5127 /* If the branch has already been created, its address;
5128 else the address of its first prospective user. */
5132 static void gen_far_branch (struct far_branch *);
5133 enum mdep_reorg_phase_e mdep_reorg_phase;
5135 gen_far_branch (struct far_branch *bp)
5137 rtx insn = bp->insert_place;
5139 rtx label = gen_label_rtx ();
5142 emit_label_after (label, insn);
5145 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5146 LABEL_NUSES (bp->far_label)++;
5149 jump = emit_jump_insn_after (gen_return (), insn);
5151 /* Emit a barrier so that reorg knows that any following instructions
5152 are not reachable via a fall-through path.
5153 But don't do this when not optimizing, since we wouldn't suppress the
5154 alignment for the barrier then, and could end up with out-of-range
5155 pc-relative loads. */
5157 emit_barrier_after (jump);
5158 emit_label_after (bp->near_label, insn);
5161 JUMP_LABEL (jump) = bp->far_label;
5164 rtx pat = PATTERN (jump);
5165 gcc_assert (ANY_RETURN_P (pat));
5166 JUMP_LABEL (jump) = pat;
5169 ok = invert_jump (insn, label, 1);
5172 /* If we are branching around a jump (rather than a return), prevent
5173 reorg from using an insn from the jump target as the delay slot insn -
5174 when reorg did this, it pessimized code (we rather hide the delay slot)
5175 and it could cause branches to go out of range. */
5178 (gen_stuff_delay_slot
5179 (GEN_INT (unspec_bbr_uid++),
5180 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5182 /* Prevent reorg from undoing our splits. */
5183 gen_block_redirect (jump, bp->address += 2, 2);
5186 /* Fix up ADDR_DIFF_VECs. */
5188 fixup_addr_diff_vecs (rtx first)
5192 for (insn = first; insn; insn = NEXT_INSN (insn))
5194 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5197 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5199 pat = PATTERN (insn);
5200 vec_lab = XEXP (XEXP (pat, 0), 0);
5202 /* Search the matching casesi_jump_2. */
5203 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5207 prevpat = PATTERN (prev);
5208 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5210 x = XVECEXP (prevpat, 0, 1);
5211 if (GET_CODE (x) != USE)
5214 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5217 /* FIXME: This is a bug in the optimizer, but it seems harmless
5218 to just avoid panicing. */
5222 /* Emit the reference label of the braf where it belongs, right after
5223 the casesi_jump_2 (i.e. braf). */
5224 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5225 emit_label_after (braf_label, prev);
5227 /* Fix up the ADDR_DIF_VEC to be relative
5228 to the reference address of the braf. */
5229 XEXP (XEXP (pat, 0), 0) = braf_label;
5233 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5234 a barrier. Return the base 2 logarithm of the desired alignment. */
5236 barrier_align (rtx barrier_or_label)
5238 rtx next = next_real_insn (barrier_or_label), pat, prev;
5239 int slot, credit, jump_to_next = 0;
5244 pat = PATTERN (next);
5246 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5249 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5250 /* This is a barrier in front of a constant table. */
5253 prev = prev_real_insn (barrier_or_label);
5254 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5256 pat = PATTERN (prev);
5257 /* If this is a very small table, we want to keep the alignment after
5258 the table to the minimum for proper code alignment. */
5259 return ((optimize_size
5260 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5261 <= (unsigned) 1 << (CACHE_LOG - 2)))
5262 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5268 if (! TARGET_SH2 || ! optimize)
5269 return align_jumps_log;
5271 /* When fixing up pcloads, a constant table might be inserted just before
5272 the basic block that ends with the barrier. Thus, we can't trust the
5273 instruction lengths before that. */
5274 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5276 /* Check if there is an immediately preceding branch to the insn beyond
5277 the barrier. We must weight the cost of discarding useful information
5278 from the current cache line when executing this branch and there is
5279 an alignment, against that of fetching unneeded insn in front of the
5280 branch target when there is no alignment. */
5282 /* There are two delay_slot cases to consider. One is the simple case
5283 where the preceding branch is to the insn beyond the barrier (simple
5284 delay slot filling), and the other is where the preceding branch has
5285 a delay slot that is a duplicate of the insn after the barrier
5286 (fill_eager_delay_slots) and the branch is to the insn after the insn
5287 after the barrier. */
5289 /* PREV is presumed to be the JUMP_INSN for the barrier under
5290 investigation. Skip to the insn before it. */
5291 prev = prev_real_insn (prev);
5293 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5294 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5295 prev = prev_real_insn (prev))
5298 if (GET_CODE (PATTERN (prev)) == USE
5299 || GET_CODE (PATTERN (prev)) == CLOBBER)
5301 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5303 prev = XVECEXP (PATTERN (prev), 0, 1);
5304 if (INSN_UID (prev) == INSN_UID (next))
5306 /* Delay slot was filled with insn at jump target. */
5313 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5315 credit -= get_attr_length (prev);
5317 if (prev && jump_to_label_p (prev))
5321 || next_real_insn (JUMP_LABEL (prev)) == next
5322 /* If relax_delay_slots() decides NEXT was redundant
5323 with some previous instruction, it will have
5324 redirected PREV's jump to the following insn. */
5325 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5326 /* There is no upper bound on redundant instructions
5327 that might have been skipped, but we must not put an
5328 alignment where none had been before. */
5329 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5331 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5332 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5333 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5335 rtx pat = PATTERN (prev);
5336 if (GET_CODE (pat) == PARALLEL)
5337 pat = XVECEXP (pat, 0, 0);
5338 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5344 return align_jumps_log;
5347 /* If we are inside a phony loop, almost any kind of label can turn up as the
5348 first one in the loop. Aligning a braf label causes incorrect switch
5349 destination addresses; we can detect braf labels because they are
5350 followed by a BARRIER.
5351 Applying loop alignment to small constant or switch tables is a waste
5352 of space, so we suppress this too. */
5354 sh_loop_align (rtx label)
5359 next = next_nonnote_insn (next);
5360 while (next && LABEL_P (next));
5364 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5365 || recog_memoized (next) == CODE_FOR_consttable_2)
5368 return align_loops_log;
5371 /* Do a final pass over the function, just before delayed branch
5377 rtx first, insn, mova = NULL_RTX;
5379 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5380 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5382 first = get_insns ();
5383 max_labelno_before_reorg = max_label_num ();
5385 /* We must split call insns before introducing `mova's. If we're
5386 optimizing, they'll have already been split. Otherwise, make
5387 sure we don't split them too late. */
5389 split_all_insns_noflow ();
5394 /* If relaxing, generate pseudo-ops to associate function calls with
5395 the symbols they call. It does no harm to not generate these
5396 pseudo-ops. However, when we can generate them, it enables the
5397 linker to potentially relax the jsr to a bsr, and eliminate the
5398 register load and, possibly, the constant pool entry. */
5400 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5403 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5404 own purposes. This works because none of the remaining passes
5405 need to look at them.
5407 ??? But it may break in the future. We should use a machine
5408 dependent REG_NOTE, or some other approach entirely. */
5409 for (insn = first; insn; insn = NEXT_INSN (insn))
5415 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5417 remove_note (insn, note);
5421 for (insn = first; insn; insn = NEXT_INSN (insn))
5423 rtx pattern, reg, link, set, scan, dies, label;
5424 int rescan = 0, foundinsn = 0;
5428 pattern = PATTERN (insn);
5430 if (GET_CODE (pattern) == PARALLEL)
5431 pattern = XVECEXP (pattern, 0, 0);
5432 if (GET_CODE (pattern) == SET)
5433 pattern = SET_SRC (pattern);
5435 if (GET_CODE (pattern) != CALL
5436 || !MEM_P (XEXP (pattern, 0)))
5439 reg = XEXP (XEXP (pattern, 0), 0);
5443 reg = sfunc_uses_reg (insn);
5451 /* Try scanning backward to find where the register is set. */
5453 for (scan = PREV_INSN (insn);
5454 scan && !LABEL_P (scan);
5455 scan = PREV_INSN (scan))
5457 if (! INSN_P (scan))
5460 if (! reg_mentioned_p (reg, scan))
5463 if (noncall_uses_reg (reg, scan, &set))
5476 /* The register is set at LINK. */
5478 /* We can only optimize the function call if the register is
5479 being set to a symbol. In theory, we could sometimes
5480 optimize calls to a constant location, but the assembler
5481 and linker do not support that at present. */
5482 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5483 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5486 /* Scan forward from LINK to the place where REG dies, and
5487 make sure that the only insns which use REG are
5488 themselves function calls. */
5490 /* ??? This doesn't work for call targets that were allocated
5491 by reload, since there may not be a REG_DEAD note for the
5495 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5499 /* Don't try to trace forward past a CODE_LABEL if we haven't
5500 seen INSN yet. Ordinarily, we will only find the setting insn
5501 if it is in the same basic block. However,
5502 cross-jumping can insert code labels in between the load and
5503 the call, and can result in situations where a single call
5504 insn may have two targets depending on where we came from. */
5506 if (LABEL_P (scan) && ! foundinsn)
5509 if (! INSN_P (scan))
5512 /* Don't try to trace forward past a JUMP. To optimize
5513 safely, we would have to check that all the
5514 instructions at the jump destination did not use REG. */
5519 if (! reg_mentioned_p (reg, scan))
5522 if (noncall_uses_reg (reg, scan, &scanset))
5529 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5531 /* There is a function call to this register other
5532 than the one we are checking. If we optimize
5533 this call, we need to rescan again below. */
5537 /* ??? We shouldn't have to worry about SCANSET here.
5538 We should just be able to check for a REG_DEAD note
5539 on a function call. However, the REG_DEAD notes are
5540 apparently not dependable around libcalls; c-torture
5541 execute/920501-2 is a test case. If SCANSET is set,
5542 then this insn sets the register, so it must have
5543 died earlier. Unfortunately, this will only handle
5544 the cases in which the register is, in fact, set in a
5547 /* ??? We shouldn't have to use FOUNDINSN here.
5548 This dates back to when we used LOG_LINKS to find
5549 the most recent insn which sets the register. */
5553 || find_reg_note (scan, REG_DEAD, reg)))
5562 /* Either there was a branch, or some insn used REG
5563 other than as a function call address. */
5567 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5568 on the insn which sets the register, and on each call insn
5569 which uses the register. In final_prescan_insn we look for
5570 the REG_LABEL_OPERAND notes, and output the appropriate label
5573 label = gen_label_rtx ();
5574 add_reg_note (link, REG_LABEL_OPERAND, label);
5575 add_reg_note (insn, REG_LABEL_OPERAND, label);
5583 scan = NEXT_INSN (scan);
5586 && reg_mentioned_p (reg, scan))
5587 || ((reg2 = sfunc_uses_reg (scan))
5588 && REGNO (reg2) == REGNO (reg))))
5589 add_reg_note (scan, REG_LABEL_OPERAND, label);
5591 while (scan != dies);
5597 fixup_addr_diff_vecs (first);
5601 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5602 shorten_branches (first);
5605 /* Scan the function looking for move instructions which have to be
5606 changed to pc-relative loads and insert the literal tables. */
5607 label_ref_list_pool = create_alloc_pool ("label references list",
5608 sizeof (struct label_ref_list_d),
5610 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5611 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5615 /* ??? basic block reordering can move a switch table dispatch
5616 below the switch table. Check if that has happened.
5617 We only have the addresses available when optimizing; but then,
5618 this check shouldn't be needed when not optimizing. */
5619 if (!untangle_mova (&num_mova, &mova, insn))
5625 else if (JUMP_P (insn)
5626 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5628 /* ??? loop invariant motion can also move a mova out of a
5629 loop. Since loop does this code motion anyway, maybe we
5630 should wrap UNSPEC_MOVA into a CONST, so that reload can
5633 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5634 || (prev_nonnote_insn (insn)
5635 == XEXP (MOVA_LABELREF (mova), 0))))
5642 /* Some code might have been inserted between the mova and
5643 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5644 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5645 total += get_attr_length (scan);
5647 /* range of mova is 1020, add 4 because pc counts from address of
5648 second instruction after this one, subtract 2 in case pc is 2
5649 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5650 cancels out with alignment effects of the mova itself. */
5653 /* Change the mova into a load, and restart scanning
5654 there. broken_move will then return true for mova. */
5659 if (broken_move (insn)
5660 || (NONJUMP_INSN_P (insn)
5661 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5664 /* Scan ahead looking for a barrier to stick the constant table
5666 rtx barrier = find_barrier (num_mova, mova, insn);
5667 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5668 int need_aligned_label = 0;
5670 if (num_mova && ! mova_p (mova))
5672 /* find_barrier had to change the first mova into a
5673 pcload; thus, we have to start with this new pcload. */
5677 /* Now find all the moves between the points and modify them. */
5678 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5682 if (NONJUMP_INSN_P (scan)
5683 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5684 need_aligned_label = 1;
5685 if (broken_move (scan))
5687 rtx *patp = &PATTERN (scan), pat = *patp;
5691 enum machine_mode mode;
5693 if (GET_CODE (pat) == PARALLEL)
5694 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5695 src = SET_SRC (pat);
5696 dst = SET_DEST (pat);
5697 mode = GET_MODE (dst);
5699 if (mode == SImode && hi_const (src)
5700 && REGNO (dst) != FPUL_REG)
5705 while (GET_CODE (dst) == SUBREG)
5707 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5708 GET_MODE (SUBREG_REG (dst)),
5711 dst = SUBREG_REG (dst);
5713 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5715 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5717 /* This must be an insn that clobbers r0. */
5718 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5719 XVECLEN (PATTERN (scan), 0)
5721 rtx clobber = *clobberp;
5723 gcc_assert (GET_CODE (clobber) == CLOBBER
5724 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5727 && reg_set_between_p (r0_rtx, last_float_move, scan))
5731 && GET_MODE_SIZE (mode) != 4
5732 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5734 lab = add_constant (src, mode, last_float);
5736 emit_insn_before (gen_mova (lab), scan);
5739 /* There will be a REG_UNUSED note for r0 on
5740 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5741 lest reorg:mark_target_live_regs will not
5742 consider r0 to be used, and we end up with delay
5743 slot insn in front of SCAN that clobbers r0. */
5745 = find_regno_note (last_float_move, REG_UNUSED, 0);
5747 /* If we are not optimizing, then there may not be
5750 PUT_REG_NOTE_KIND (note, REG_INC);
5752 *last_float_addr = r0_inc_rtx;
5754 last_float_move = scan;
5756 newsrc = gen_const_mem (mode,
5757 (((TARGET_SH4 && ! TARGET_FMOVD)
5758 || REGNO (dst) == FPUL_REG)
5761 last_float_addr = &XEXP (newsrc, 0);
5763 /* Remove the clobber of r0. */
5764 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5765 gen_rtx_SCRATCH (Pmode));
5767 /* This is a mova needing a label. Create it. */
5768 else if (GET_CODE (src) == UNSPEC
5769 && XINT (src, 1) == UNSPEC_MOVA
5770 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5772 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5773 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5774 newsrc = gen_rtx_UNSPEC (SImode,
5775 gen_rtvec (1, newsrc),
5780 lab = add_constant (src, mode, 0);
5781 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5782 newsrc = gen_const_mem (mode, newsrc);
5784 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5785 INSN_CODE (scan) = -1;
5788 dump_table (need_aligned_label ? insn : 0, barrier);
5792 free_alloc_pool (label_ref_list_pool);
5793 for (insn = first; insn; insn = NEXT_INSN (insn))
5794 PUT_MODE (insn, VOIDmode);
5796 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5797 INSN_ADDRESSES_FREE ();
5798 split_branches (first);
5800 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5801 also has an effect on the register that holds the address of the sfunc.
5802 Insert an extra dummy insn in front of each sfunc that pretends to
5803 use this register. */
5804 if (flag_delayed_branch)
5806 for (insn = first; insn; insn = NEXT_INSN (insn))
5808 rtx reg = sfunc_uses_reg (insn);
5812 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5816 /* fpscr is not actually a user variable, but we pretend it is for the
5817 sake of the previous optimization passes, since we want it handled like
5818 one. However, we don't have any debugging information for it, so turn
5819 it into a non-user variable now. */
5821 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5823 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5827 get_dest_uid (rtx label, int max_uid)
5829 rtx dest = next_real_insn (label);
5832 /* This can happen for an undefined label. */
5834 dest_uid = INSN_UID (dest);
5835 /* If this is a newly created branch redirection blocking instruction,
5836 we cannot index the branch_uid or insn_addresses arrays with its
5837 uid. But then, we won't need to, because the actual destination is
5838 the following branch. */
5839 while (dest_uid >= max_uid)
5841 dest = NEXT_INSN (dest);
5842 dest_uid = INSN_UID (dest);
5844 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5849 /* Split condbranches that are out of range. Also add clobbers for
5850 scratch registers that are needed in far jumps.
5851 We do this before delay slot scheduling, so that it can take our
5852 newly created instructions into account. It also allows us to
5853 find branches with common targets more easily. */
5856 split_branches (rtx first)
5859 struct far_branch **uid_branch, *far_branch_list = 0;
5860 int max_uid = get_max_uid ();
5863 /* Find out which branches are out of range. */
5864 shorten_branches (first);
5866 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5867 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5869 for (insn = first; insn; insn = NEXT_INSN (insn))
5870 if (! INSN_P (insn))
5872 else if (INSN_DELETED_P (insn))
5874 /* Shorten_branches would split this instruction again,
5875 so transform it into a note. */
5876 SET_INSN_DELETED (insn);
5878 else if (JUMP_P (insn)
5879 /* Don't mess with ADDR_DIFF_VEC */
5880 && (GET_CODE (PATTERN (insn)) == SET
5881 || GET_CODE (PATTERN (insn)) == RETURN))
5883 enum attr_type type = get_attr_type (insn);
5884 if (type == TYPE_CBRANCH)
5888 if (get_attr_length (insn) > 4)
5890 rtx src = SET_SRC (PATTERN (insn));
5891 rtx olabel = XEXP (XEXP (src, 1), 0);
5892 int addr = INSN_ADDRESSES (INSN_UID (insn));
5894 int dest_uid = get_dest_uid (olabel, max_uid);
5895 struct far_branch *bp = uid_branch[dest_uid];
5897 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5898 the label if the LABEL_NUSES count drops to zero. There is
5899 always a jump_optimize pass that sets these values, but it
5900 proceeds to delete unreferenced code, and then if not
5901 optimizing, to un-delete the deleted instructions, thus
5902 leaving labels with too low uses counts. */
5905 JUMP_LABEL (insn) = olabel;
5906 LABEL_NUSES (olabel)++;
5910 bp = (struct far_branch *) alloca (sizeof *bp);
5911 uid_branch[dest_uid] = bp;
5912 bp->prev = far_branch_list;
5913 far_branch_list = bp;
5915 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5916 LABEL_NUSES (bp->far_label)++;
5920 label = bp->near_label;
5921 if (! label && bp->address - addr >= CONDJUMP_MIN)
5923 rtx block = bp->insert_place;
5925 if (GET_CODE (PATTERN (block)) == RETURN)
5926 block = PREV_INSN (block);
5928 block = gen_block_redirect (block,
5930 label = emit_label_after (gen_label_rtx (),
5932 bp->near_label = label;
5934 else if (label && ! NEXT_INSN (label))
5936 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5937 bp->insert_place = insn;
5939 gen_far_branch (bp);
5943 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5945 bp->near_label = label = gen_label_rtx ();
5946 bp->insert_place = insn;
5949 ok = redirect_jump (insn, label, 0);
5954 /* get_attr_length (insn) == 2 */
5955 /* Check if we have a pattern where reorg wants to redirect
5956 the branch to a label from an unconditional branch that
5958 /* We can't use JUMP_LABEL here because it might be undefined
5959 when not optimizing. */
5960 /* A syntax error might cause beyond to be NULL_RTX. */
5962 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5967 || ((beyond = next_active_insn (beyond))
5968 && JUMP_P (beyond)))
5969 && GET_CODE (PATTERN (beyond)) == SET
5970 && recog_memoized (beyond) == CODE_FOR_jump_compact
5972 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5973 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5975 gen_block_redirect (beyond,
5976 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5979 next = next_active_insn (insn);
5983 || ((next = next_active_insn (next))
5985 && GET_CODE (PATTERN (next)) == SET
5986 && recog_memoized (next) == CODE_FOR_jump_compact
5988 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5989 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5991 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5993 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5995 int addr = INSN_ADDRESSES (INSN_UID (insn));
5998 struct far_branch *bp;
6000 if (type == TYPE_JUMP)
6002 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
6003 dest_uid = get_dest_uid (far_label, max_uid);
6006 /* Parse errors can lead to labels outside
6008 if (! NEXT_INSN (far_label))
6013 JUMP_LABEL (insn) = far_label;
6014 LABEL_NUSES (far_label)++;
6016 redirect_jump (insn, ret_rtx, 1);
6020 bp = uid_branch[dest_uid];
6023 bp = (struct far_branch *) alloca (sizeof *bp);
6024 uid_branch[dest_uid] = bp;
6025 bp->prev = far_branch_list;
6026 far_branch_list = bp;
6028 bp->far_label = far_label;
6030 LABEL_NUSES (far_label)++;
6032 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
6033 if (addr - bp->address <= CONDJUMP_MAX)
6034 emit_label_after (bp->near_label, PREV_INSN (insn));
6037 gen_far_branch (bp);
6043 bp->insert_place = insn;
6045 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
6047 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
6050 /* Generate all pending far branches,
6051 and free our references to the far labels. */
6052 while (far_branch_list)
6054 if (far_branch_list->near_label
6055 && ! NEXT_INSN (far_branch_list->near_label))
6056 gen_far_branch (far_branch_list);
6058 && far_branch_list->far_label
6059 && ! --LABEL_NUSES (far_branch_list->far_label))
6060 delete_insn (far_branch_list->far_label);
6061 far_branch_list = far_branch_list->prev;
6064 /* Instruction length information is no longer valid due to the new
6065 instructions that have been generated. */
6066 init_insn_lengths ();
6069 /* Dump out instruction addresses, which is useful for debugging the
6070 constant pool table stuff.
6072 If relaxing, output the label and pseudo-ops used to link together
6073 calls and the instruction which set the registers. */
6075 /* ??? The addresses printed by this routine for insns are nonsense for
6076 insns which are inside of a sequence where none of the inner insns have
6077 variable length. This is because the second pass of shorten_branches
6078 does not bother to update them. */
6081 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
6082 int noperands ATTRIBUTE_UNUSED)
6084 if (TARGET_DUMPISIZE)
6085 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
6091 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
6096 pattern = PATTERN (insn);
6097 if (GET_CODE (pattern) == PARALLEL)
6098 pattern = XVECEXP (pattern, 0, 0);
6099 switch (GET_CODE (pattern))
6102 if (GET_CODE (SET_SRC (pattern)) != CALL
6103 && get_attr_type (insn) != TYPE_SFUNC)
6105 targetm.asm_out.internal_label
6106 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6109 /* else FALLTHROUGH */
6111 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6112 CODE_LABEL_NUMBER (XEXP (note, 0)));
6122 /* Dump out any constants accumulated in the final pass. These will
6126 output_jump_label_table (void)
6132 fprintf (asm_out_file, "\t.align 2\n");
6133 for (i = 0; i < pool_size; i++)
6135 pool_node *p = &pool_vector[i];
6137 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6138 CODE_LABEL_NUMBER (p->label));
6139 output_asm_insn (".long %O0", &p->value);
6147 /* A full frame looks like:
6151 [ if current_function_anonymous_args
6164 local-0 <- fp points here. */
6166 /* Number of bytes pushed for anonymous args, used to pass information
6167 between expand_prologue and expand_epilogue. */
6169 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6170 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6171 for an epilogue and a negative value means that it's for a sibcall
6172 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6173 all the registers that are about to be restored, and hence dead. */
6176 output_stack_adjust (int size, rtx reg, int epilogue_p,
6177 HARD_REG_SET *live_regs_mask, bool frame_p)
6179 rtx (*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn;
6182 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6184 /* This test is bogus, as output_stack_adjust is used to re-align the
6187 gcc_assert (!(size % align));
6190 if (CONST_OK_FOR_ADD (size))
6191 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6192 /* Try to do it with two partial adjustments; however, we must make
6193 sure that the stack is properly aligned at all times, in case
6194 an interrupt occurs between the two partial adjustments. */
6195 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6196 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6198 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6199 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6205 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6208 /* If TEMP is invalid, we could temporarily save a general
6209 register to MACL. However, there is currently no need
6210 to handle this case, so just die when we see it. */
6212 || current_function_interrupt
6213 || ! call_really_used_regs[temp] || fixed_regs[temp])
6215 if (temp < 0 && ! current_function_interrupt
6216 && (TARGET_SHMEDIA || epilogue_p >= 0))
6219 COPY_HARD_REG_SET (temps, call_used_reg_set);
6220 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6224 if (crtl->return_rtx)
6226 enum machine_mode mode;
6227 mode = GET_MODE (crtl->return_rtx);
6228 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6229 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6231 for (i = 0; i < nreg; i++)
6232 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6233 if (crtl->calls_eh_return)
6235 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6236 for (i = 0; i <= 3; i++)
6237 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6240 if (TARGET_SHMEDIA && epilogue_p < 0)
6241 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6242 CLEAR_HARD_REG_BIT (temps, i);
6243 if (epilogue_p <= 0)
6245 for (i = FIRST_PARM_REG;
6246 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6247 CLEAR_HARD_REG_BIT (temps, i);
6248 if (cfun->static_chain_decl != NULL)
6249 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6251 temp = scavenge_reg (&temps);
6253 if (temp < 0 && live_regs_mask)
6257 COPY_HARD_REG_SET (temps, *live_regs_mask);
6258 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6259 temp = scavenge_reg (&temps);
6263 rtx adj_reg, tmp_reg, mem;
6265 /* If we reached here, the most likely case is the (sibcall)
6266 epilogue for non SHmedia. Put a special push/pop sequence
6267 for such case as the last resort. This looks lengthy but
6268 would not be problem because it seems to be very
6271 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6274 /* ??? There is still the slight possibility that r4 or
6275 r5 have been reserved as fixed registers or assigned
6276 as global registers, and they change during an
6277 interrupt. There are possible ways to handle this:
6279 - If we are adjusting the frame pointer (r14), we can do
6280 with a single temp register and an ordinary push / pop
6282 - Grab any call-used or call-saved registers (i.e. not
6283 fixed or globals) for the temps we need. We might
6284 also grab r14 if we are adjusting the stack pointer.
6285 If we can't find enough available registers, issue
6286 a diagnostic and die - the user must have reserved
6287 way too many registers.
6288 But since all this is rather unlikely to happen and
6289 would require extra testing, we just die if r4 / r5
6290 are not available. */
6291 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6292 && !global_regs[4] && !global_regs[5]);
6294 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6295 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6296 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6297 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6298 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6299 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6300 emit_move_insn (mem, tmp_reg);
6301 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6302 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6303 emit_move_insn (mem, tmp_reg);
6304 emit_move_insn (reg, adj_reg);
6305 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6306 emit_move_insn (adj_reg, mem);
6307 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6308 emit_move_insn (tmp_reg, mem);
6309 /* Tell flow the insns that pop r4/r5 aren't dead. */
6314 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6316 /* If SIZE is negative, subtract the positive value.
6317 This sometimes allows a constant pool entry to be shared
6318 between prologue and epilogue code. */
6321 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6322 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6326 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6327 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6330 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6331 gen_rtx_SET (VOIDmode, reg,
6332 gen_rtx_PLUS (SImode, reg,
6342 RTX_FRAME_RELATED_P (x) = 1;
6346 /* Output RTL to push register RN onto the stack. */
6353 x = gen_push_fpul ();
6354 else if (rn == FPSCR_REG)
6355 x = gen_push_fpscr ();
6356 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6357 && FP_OR_XD_REGISTER_P (rn))
6359 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6361 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6363 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6364 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6366 x = gen_push (gen_rtx_REG (SImode, rn));
6369 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6373 /* Output RTL to pop register RN from the stack. */
6380 x = gen_pop_fpul ();
6381 else if (rn == FPSCR_REG)
6382 x = gen_pop_fpscr ();
6383 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6384 && FP_OR_XD_REGISTER_P (rn))
6386 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6388 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6390 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6391 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6393 x = gen_pop (gen_rtx_REG (SImode, rn));
6396 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6399 /* Generate code to push the regs specified in the mask. */
6402 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6404 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6407 /* Push PR last; this gives better latencies after the prologue, and
6408 candidates for the return delay slot when there are no general
6409 registers pushed. */
6410 for (; i < FIRST_PSEUDO_REGISTER; i++)
6412 /* If this is an interrupt handler, and the SZ bit varies,
6413 and we have to push any floating point register, we need
6414 to switch to the correct precision first. */
6415 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6416 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6418 HARD_REG_SET unsaved;
6421 COMPL_HARD_REG_SET (unsaved, *mask);
6422 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6426 && (i != FPSCR_REG || ! skip_fpscr)
6427 && TEST_HARD_REG_BIT (*mask, i))
6429 /* If the ISR has RESBANK attribute assigned, don't push any of
6430 the following registers - R0-R14, MACH, MACL and GBR. */
6431 if (! (sh_cfun_resbank_handler_p ()
6432 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6440 /* Push banked registers last to improve delay slot opportunities. */
6441 if (interrupt_handler)
6443 bool use_movml = false;
6447 unsigned int count = 0;
6449 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6450 if (TEST_HARD_REG_BIT (*mask, i))
6455 /* Use movml when all banked registers are pushed. */
6456 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
6462 rtx x, mem, reg, set;
6463 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6465 /* We must avoid scheduling multiple store insn with another
6467 emit_insn (gen_blockage ());
6468 x = gen_movml_push_banked (sp_reg);
6470 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6472 mem = gen_rtx_MEM (SImode, plus_constant (sp_reg, i * 4));
6473 reg = gen_rtx_REG (SImode, i);
6474 add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (SImode, mem, reg));
6477 set = gen_rtx_SET (SImode, sp_reg, plus_constant (sp_reg, - 32));
6478 add_reg_note (x, REG_CFA_ADJUST_CFA, set);
6479 emit_insn (gen_blockage ());
6482 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6483 if (TEST_HARD_REG_BIT (*mask, i))
6487 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6488 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6492 /* Calculate how much extra space is needed to save all callee-saved
6494 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6497 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6500 int stack_space = 0;
6501 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6503 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6504 if ((! call_really_used_regs[reg] || interrupt_handler)
6505 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6506 /* Leave space to save this target register on the stack,
6507 in case target register allocation wants to use it. */
6508 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6512 /* Decide whether we should reserve space for callee-save target registers,
6513 in case target register allocation wants to use them. REGS_SAVED is
6514 the space, in bytes, that is already required for register saves.
6515 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6518 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6519 HARD_REG_SET *live_regs_mask)
6523 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6526 /* Decide how much space to reserve for callee-save target registers
6527 in case target register allocation wants to use them.
6528 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6531 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6533 if (shmedia_space_reserved_for_target_registers)
6534 return shmedia_target_regs_stack_space (live_regs_mask);
6539 /* Work out the registers which need to be saved, both as a mask and a
6540 count of saved words. Return the count.
6542 If doing a pragma interrupt function, then push all regs used by the
6543 function, and if we call another function (we can tell by looking at PR),
6544 make sure that all the regs it clobbers are safe too. */
6547 calc_live_regs (HARD_REG_SET *live_regs_mask)
6552 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6553 bool nosave_low_regs;
6554 int pr_live, has_call;
6556 attrs = DECL_ATTRIBUTES (current_function_decl);
6557 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6558 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6559 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6560 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6562 CLEAR_HARD_REG_SET (*live_regs_mask);
6563 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6564 && df_regs_ever_live_p (FPSCR_REG))
6565 target_flags &= ~MASK_FPU_SINGLE;
6566 /* If we can save a lot of saves by switching to double mode, do that. */
6567 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6568 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6569 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6570 && (! call_really_used_regs[reg]
6571 || interrupt_handler)
6574 target_flags &= ~MASK_FPU_SINGLE;
6577 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6578 knows how to use it. That means the pseudo originally allocated for
6579 the initial value can become the PR_MEDIA_REG hard register, as seen for
6580 execute/20010122-1.c:test9. */
6582 /* ??? this function is called from initial_elimination_offset, hence we
6583 can't use the result of sh_media_register_for_return here. */
6584 pr_live = sh_pr_n_sets ();
6587 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6588 pr_live = (pr_initial
6589 ? (!REG_P (pr_initial)
6590 || REGNO (pr_initial) != (PR_REG))
6591 : df_regs_ever_live_p (PR_REG));
6592 /* For Shcompact, if not optimizing, we end up with a memory reference
6593 using the return address pointer for __builtin_return_address even
6594 though there is no actual need to put the PR register on the stack. */
6595 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6597 /* Force PR to be live if the prologue has to call the SHmedia
6598 argument decoder or register saver. */
6599 if (TARGET_SHCOMPACT
6600 && ((crtl->args.info.call_cookie
6601 & ~ CALL_COOKIE_RET_TRAMP (1))
6602 || crtl->saves_all_registers))
6604 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6605 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6607 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6610 ? (/* Need to save all the regs ever live. */
6611 (df_regs_ever_live_p (reg)
6612 || (call_really_used_regs[reg]
6613 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6614 || reg == PIC_OFFSET_TABLE_REGNUM)
6616 || (TARGET_SHMEDIA && has_call
6617 && REGISTER_NATURAL_MODE (reg) == SImode
6618 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6619 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6620 && reg != RETURN_ADDRESS_POINTER_REGNUM
6621 && reg != T_REG && reg != GBR_REG
6622 /* Push fpscr only on targets which have FPU */
6623 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6624 : (/* Only push those regs which are used and need to be saved. */
6627 && crtl->args.info.call_cookie
6628 && reg == PIC_OFFSET_TABLE_REGNUM)
6629 || (df_regs_ever_live_p (reg)
6630 && ((!call_really_used_regs[reg]
6631 && !(reg != PIC_OFFSET_TABLE_REGNUM
6632 && fixed_regs[reg] && call_used_regs[reg]))
6633 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6634 || (crtl->calls_eh_return
6635 && (reg == EH_RETURN_DATA_REGNO (0)
6636 || reg == EH_RETURN_DATA_REGNO (1)
6637 || reg == EH_RETURN_DATA_REGNO (2)
6638 || reg == EH_RETURN_DATA_REGNO (3)))
6639 || ((reg == MACL_REG || reg == MACH_REG)
6640 && df_regs_ever_live_p (reg)
6641 && sh_cfun_attr_renesas_p ())
6644 SET_HARD_REG_BIT (*live_regs_mask, reg);
6645 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6647 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6648 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6650 if (FP_REGISTER_P (reg))
6652 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6654 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6655 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6658 else if (XD_REGISTER_P (reg))
6660 /* Must switch to double mode to access these registers. */
6661 target_flags &= ~MASK_FPU_SINGLE;
6665 if (nosave_low_regs && reg == R8_REG)
6668 /* If we have a target register optimization pass after prologue / epilogue
6669 threading, we need to assume all target registers will be live even if
6671 if (flag_branch_target_load_optimize2
6672 && TARGET_SAVE_ALL_TARGET_REGS
6673 && shmedia_space_reserved_for_target_registers)
6674 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6675 if ((! call_really_used_regs[reg] || interrupt_handler)
6676 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6678 SET_HARD_REG_BIT (*live_regs_mask, reg);
6679 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6681 /* If this is an interrupt handler, we don't have any call-clobbered
6682 registers we can conveniently use for target register save/restore.
6683 Make sure we save at least one general purpose register when we need
6684 to save target registers. */
6685 if (interrupt_handler
6686 && hard_reg_set_intersect_p (*live_regs_mask,
6687 reg_class_contents[TARGET_REGS])
6688 && ! hard_reg_set_intersect_p (*live_regs_mask,
6689 reg_class_contents[GENERAL_REGS]))
6691 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6692 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6698 /* Code to generate prologue and epilogue sequences */
6700 /* PUSHED is the number of bytes that are being pushed on the
6701 stack for register saves. Return the frame size, padded
6702 appropriately so that the stack stays properly aligned. */
6703 static HOST_WIDE_INT
6704 rounded_frame_size (int pushed)
6706 HOST_WIDE_INT size = get_frame_size ();
6707 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6709 if (ACCUMULATE_OUTGOING_ARGS)
6710 size += crtl->outgoing_args_size;
6712 return ((size + pushed + align - 1) & -align) - pushed;
6715 /* Choose a call-clobbered target-branch register that remains
6716 unchanged along the whole function. We set it up as the return
6717 value in the prologue. */
6719 sh_media_register_for_return (void)
6724 if (! current_function_is_leaf)
6726 if (lookup_attribute ("interrupt_handler",
6727 DECL_ATTRIBUTES (current_function_decl)))
6729 if (sh_cfun_interrupt_handler_p ())
6732 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6734 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6735 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6741 /* The maximum registers we need to save are:
6742 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6743 - 32 floating point registers (for each pair, we save none,
6744 one single precision value, or a double precision value).
6745 - 8 target registers
6746 - add 1 entry for a delimiter. */
6747 #define MAX_SAVED_REGS (62+32+8)
6749 typedef struct save_entry_s
6758 /* There will be a delimiter entry with VOIDmode both at the start and the
6759 end of a filled in schedule. The end delimiter has the offset of the
6760 save with the smallest (i.e. most negative) offset. */
6761 typedef struct save_schedule_s
6763 save_entry entries[MAX_SAVED_REGS + 2];
6764 int temps[MAX_TEMPS+1];
6767 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6768 use reverse order. Returns the last entry written to (not counting
6769 the delimiter). OFFSET_BASE is a number to be added to all offset
6773 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6777 save_entry *entry = schedule->entries;
6781 if (! current_function_interrupt)
6782 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6783 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6784 && ! FUNCTION_ARG_REGNO_P (i)
6785 && i != FIRST_RET_REG
6786 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6787 && ! (crtl->calls_eh_return
6788 && (i == EH_RETURN_STACKADJ_REGNO
6789 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6790 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6791 schedule->temps[tmpx++] = i;
6793 entry->mode = VOIDmode;
6794 entry->offset = offset_base;
6796 /* We loop twice: first, we save 8-byte aligned registers in the
6797 higher addresses, that are known to be aligned. Then, we
6798 proceed to saving 32-bit registers that don't need 8-byte
6800 If this is an interrupt function, all registers that need saving
6801 need to be saved in full. moreover, we need to postpone saving
6802 target registers till we have saved some general purpose registers
6803 we can then use as scratch registers. */
6804 offset = offset_base;
6805 for (align = 1; align >= 0; align--)
6807 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6808 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6810 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6813 if (current_function_interrupt)
6815 if (TARGET_REGISTER_P (i))
6817 if (GENERAL_REGISTER_P (i))
6820 if (mode == SFmode && (i % 2) == 1
6821 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6822 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6829 /* If we're doing the aligned pass and this is not aligned,
6830 or we're doing the unaligned pass and this is aligned,
6832 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6836 if (current_function_interrupt
6837 && GENERAL_REGISTER_P (i)
6838 && tmpx < MAX_TEMPS)
6839 schedule->temps[tmpx++] = i;
6841 offset -= GET_MODE_SIZE (mode);
6844 entry->offset = offset;
6847 if (align && current_function_interrupt)
6848 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6849 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6851 offset -= GET_MODE_SIZE (DImode);
6853 entry->mode = DImode;
6854 entry->offset = offset;
6859 entry->mode = VOIDmode;
6860 entry->offset = offset;
6861 schedule->temps[tmpx] = -1;
6866 sh_expand_prologue (void)
6868 HARD_REG_SET live_regs_mask;
6871 int save_flags = target_flags;
6875 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6877 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6879 /* We have pretend args if we had an object sent partially in registers
6880 and partially on the stack, e.g. a large structure. */
6881 pretend_args = crtl->args.pretend_args_size;
6882 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6883 && (NPARM_REGS(SImode)
6884 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6887 output_stack_adjust (-pretend_args
6888 - crtl->args.info.stack_regs * 8,
6889 stack_pointer_rtx, 0, NULL, true);
6890 stack_usage = pretend_args + crtl->args.info.stack_regs * 8;
6892 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6893 /* We're going to use the PIC register to load the address of the
6894 incoming-argument decoder and/or of the return trampoline from
6895 the GOT, so make sure the PIC register is preserved and
6897 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6899 if (TARGET_SHCOMPACT
6900 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6904 /* First, make all registers with incoming arguments that will
6905 be pushed onto the stack live, so that register renaming
6906 doesn't overwrite them. */
6907 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6908 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6909 >= NPARM_REGS (SImode) - reg)
6910 for (; reg < NPARM_REGS (SImode); reg++)
6911 emit_insn (gen_shcompact_preserve_incoming_args
6912 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6913 else if (CALL_COOKIE_INT_REG_GET
6914 (crtl->args.info.call_cookie, reg) == 1)
6915 emit_insn (gen_shcompact_preserve_incoming_args
6916 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6918 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6920 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6921 GEN_INT (crtl->args.info.call_cookie));
6922 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6923 gen_rtx_REG (SImode, R0_REG));
6925 else if (TARGET_SHMEDIA)
6927 int tr = sh_media_register_for_return ();
6930 emit_move_insn (gen_rtx_REG (DImode, tr),
6931 gen_rtx_REG (DImode, PR_MEDIA_REG));
6934 /* Emit the code for SETUP_VARARGS. */
6937 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6939 /* Push arg regs as if they'd been provided by caller in stack. */
6940 for (i = 0; i < NPARM_REGS(SImode); i++)
6942 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6944 if (i >= (NPARM_REGS(SImode)
6945 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6949 stack_usage += GET_MODE_SIZE (SImode);
6954 /* If we're supposed to switch stacks at function entry, do so now. */
6958 /* The argument specifies a variable holding the address of the
6959 stack the interrupt function should switch to/from at entry/exit. */
6960 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
6962 = ggc_strdup (TREE_STRING_POINTER (arg));
6963 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6965 lab = add_constant (sp_switch, SImode, 0);
6966 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6967 newsrc = gen_const_mem (SImode, newsrc);
6969 emit_insn (gen_sp_switch_1 (newsrc));
6972 d = calc_live_regs (&live_regs_mask);
6973 /* ??? Maybe we could save some switching if we can move a mode switch
6974 that already happens to be at the function start into the prologue. */
6975 if (target_flags != save_flags && ! current_function_interrupt)
6976 emit_insn (gen_toggle_sz ());
6980 int offset_base, offset;
6982 int offset_in_r0 = -1;
6984 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6985 int total_size, save_size;
6986 save_schedule schedule;
6990 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6991 && ! current_function_interrupt)
6992 r0 = gen_rtx_REG (Pmode, R0_REG);
6994 /* D is the actual number of bytes that we need for saving registers,
6995 however, in initial_elimination_offset we have committed to using
6996 an additional TREGS_SPACE amount of bytes - in order to keep both
6997 addresses to arguments supplied by the caller and local variables
6998 valid, we must keep this gap. Place it between the incoming
6999 arguments and the actually saved registers in a bid to optimize
7000 locality of reference. */
7001 total_size = d + tregs_space;
7002 total_size += rounded_frame_size (total_size);
7003 save_size = total_size - rounded_frame_size (d);
7004 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
7005 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7006 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
7008 /* If adjusting the stack in a single step costs nothing extra, do so.
7009 I.e. either if a single addi is enough, or we need a movi anyway,
7010 and we don't exceed the maximum offset range (the test for the
7011 latter is conservative for simplicity). */
7013 && (CONST_OK_FOR_I10 (-total_size)
7014 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
7015 && total_size <= 2044)))
7016 d_rounding = total_size - save_size;
7018 offset_base = d + d_rounding;
7020 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
7022 stack_usage += save_size + d_rounding;
7024 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
7025 tmp_pnt = schedule.temps;
7026 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7028 enum machine_mode mode = (enum machine_mode) entry->mode;
7029 unsigned int reg = entry->reg;
7030 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
7033 offset = entry->offset;
7035 reg_rtx = gen_rtx_REG (mode, reg);
7037 mem_rtx = gen_frame_mem (mode,
7038 gen_rtx_PLUS (Pmode,
7042 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7048 if (HAVE_PRE_DECREMENT
7049 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
7050 || mem_rtx == NULL_RTX
7051 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7053 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
7055 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
7060 offset += GET_MODE_SIZE (mode);
7064 if (mem_rtx != NULL_RTX)
7067 if (offset_in_r0 == -1)
7069 emit_move_insn (r0, GEN_INT (offset));
7070 offset_in_r0 = offset;
7072 else if (offset != offset_in_r0)
7077 GEN_INT (offset - offset_in_r0)));
7078 offset_in_r0 += offset - offset_in_r0;
7081 if (pre_dec != NULL_RTX)
7087 (Pmode, r0, stack_pointer_rtx));
7091 offset -= GET_MODE_SIZE (mode);
7092 offset_in_r0 -= GET_MODE_SIZE (mode);
7097 mem_rtx = gen_frame_mem (mode, r0);
7099 mem_rtx = gen_frame_mem (mode,
7100 gen_rtx_PLUS (Pmode,
7104 /* We must not use an r0-based address for target-branch
7105 registers or for special registers without pre-dec
7106 memory addresses, since we store their values in r0
7108 gcc_assert (!TARGET_REGISTER_P (reg)
7109 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7110 || mem_rtx == pre_dec));
7113 orig_reg_rtx = reg_rtx;
7114 if (TARGET_REGISTER_P (reg)
7115 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7116 && mem_rtx != pre_dec))
7118 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
7120 emit_move_insn (tmp_reg, reg_rtx);
7122 if (REGNO (tmp_reg) == R0_REG)
7126 gcc_assert (!refers_to_regno_p
7127 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
7130 if (*++tmp_pnt <= 0)
7131 tmp_pnt = schedule.temps;
7138 /* Mark as interesting for dwarf cfi generator */
7139 insn = emit_move_insn (mem_rtx, reg_rtx);
7140 RTX_FRAME_RELATED_P (insn) = 1;
7141 /* If we use an intermediate register for the save, we can't
7142 describe this exactly in cfi as a copy of the to-be-saved
7143 register into the temporary register and then the temporary
7144 register on the stack, because the temporary register can
7145 have a different natural size than the to-be-saved register.
7146 Thus, we gloss over the intermediate copy and pretend we do
7147 a direct save from the to-be-saved register. */
7148 if (REGNO (reg_rtx) != reg)
7152 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
7153 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7156 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
7158 rtx reg_rtx = gen_rtx_REG (mode, reg);
7160 rtx mem_rtx = gen_frame_mem (mode,
7161 gen_rtx_PLUS (Pmode,
7165 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
7166 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7171 gcc_assert (entry->offset == d_rounding);
7175 push_regs (&live_regs_mask, current_function_interrupt);
7179 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7180 emit_insn (gen_GOTaddr2picreg ());
7182 if (SHMEDIA_REGS_STACK_ADJUST ())
7184 /* This must NOT go through the PLT, otherwise mach and macl
7185 may be clobbered. */
7186 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7188 ? "__GCC_push_shmedia_regs"
7189 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
7190 emit_insn (gen_shmedia_save_restore_regs_compact
7191 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7194 if (target_flags != save_flags && ! current_function_interrupt)
7195 emit_insn (gen_toggle_sz ());
7197 target_flags = save_flags;
7199 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
7200 stack_pointer_rtx, 0, NULL, true);
7201 stack_usage += rounded_frame_size (d) - d_rounding;
7203 if (frame_pointer_needed)
7204 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7206 if (TARGET_SHCOMPACT
7207 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7209 /* This must NOT go through the PLT, otherwise mach and macl
7210 may be clobbered. */
7211 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7212 "__GCC_shcompact_incoming_args", SFUNC_GOT);
7213 emit_insn (gen_shcompact_incoming_args ());
7216 /* If we are profiling, make sure no instructions are scheduled before
7217 the call to mcount. Similarly if some call instructions are swapped
7218 before frame related insns, it'll confuse the unwinder because
7219 currently SH has no unwind info for function epilogues. */
7220 if (crtl->profile || flag_exceptions || flag_unwind_tables)
7221 emit_insn (gen_blockage ());
7223 if (flag_stack_usage_info)
7224 current_function_static_stack_size = stack_usage;
7228 sh_expand_epilogue (bool sibcall_p)
7230 HARD_REG_SET live_regs_mask;
7234 int save_flags = target_flags;
7235 int frame_size, save_size;
7236 int fpscr_deferred = 0;
7237 int e = sibcall_p ? -1 : 1;
7239 d = calc_live_regs (&live_regs_mask);
7242 frame_size = rounded_frame_size (d);
7246 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7248 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7249 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7250 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7252 total_size = d + tregs_space;
7253 total_size += rounded_frame_size (total_size);
7254 save_size = total_size - frame_size;
7256 /* If adjusting the stack in a single step costs nothing extra, do so.
7257 I.e. either if a single addi is enough, or we need a movi anyway,
7258 and we don't exceed the maximum offset range (the test for the
7259 latter is conservative for simplicity). */
7261 && ! frame_pointer_needed
7262 && (CONST_OK_FOR_I10 (total_size)
7263 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7264 && total_size <= 2044)))
7265 d_rounding = frame_size;
7267 frame_size -= d_rounding;
7270 if (frame_pointer_needed)
7272 /* We must avoid scheduling the epilogue with previous basic blocks.
7273 See PR/18032 and PR/40313. */
7274 emit_insn (gen_blockage ());
7275 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7276 &live_regs_mask, false);
7278 /* We must avoid moving the stack pointer adjustment past code
7279 which reads from the local frame, else an interrupt could
7280 occur after the SP adjustment and clobber data in the local
7282 emit_insn (gen_blockage ());
7283 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7285 else if (frame_size)
7287 /* We must avoid moving the stack pointer adjustment past code
7288 which reads from the local frame, else an interrupt could
7289 occur after the SP adjustment and clobber data in the local
7291 emit_insn (gen_blockage ());
7292 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7293 &live_regs_mask, false);
7296 if (SHMEDIA_REGS_STACK_ADJUST ())
7298 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7300 ? "__GCC_pop_shmedia_regs"
7301 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7302 /* This must NOT go through the PLT, otherwise mach and macl
7303 may be clobbered. */
7304 emit_insn (gen_shmedia_save_restore_regs_compact
7305 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7308 /* Pop all the registers. */
7310 if (target_flags != save_flags && ! current_function_interrupt)
7311 emit_insn (gen_toggle_sz ());
7314 int offset_base, offset;
7315 int offset_in_r0 = -1;
7317 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7318 save_schedule schedule;
7322 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7323 offset_base = -entry[1].offset + d_rounding;
7324 tmp_pnt = schedule.temps;
7325 for (; entry->mode != VOIDmode; entry--)
7327 enum machine_mode mode = (enum machine_mode) entry->mode;
7328 int reg = entry->reg;
7329 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX;
7331 offset = offset_base + entry->offset;
7332 reg_rtx = gen_rtx_REG (mode, reg);
7334 mem_rtx = gen_frame_mem (mode,
7335 gen_rtx_PLUS (Pmode,
7339 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7342 if (HAVE_POST_INCREMENT
7343 && (offset == offset_in_r0
7344 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7345 && mem_rtx == NULL_RTX)
7346 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7348 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7350 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7351 post_inc = NULL_RTX;
7356 if (mem_rtx != NULL_RTX)
7359 if (offset_in_r0 == -1)
7361 emit_move_insn (r0, GEN_INT (offset));
7362 offset_in_r0 = offset;
7364 else if (offset != offset_in_r0)
7369 GEN_INT (offset - offset_in_r0)));
7370 offset_in_r0 += offset - offset_in_r0;
7373 if (post_inc != NULL_RTX)
7379 (Pmode, r0, stack_pointer_rtx));
7385 offset_in_r0 += GET_MODE_SIZE (mode);
7388 mem_rtx = gen_frame_mem (mode, r0);
7390 mem_rtx = gen_frame_mem (mode,
7391 gen_rtx_PLUS (Pmode,
7395 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7396 || mem_rtx == post_inc);
7399 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7400 && mem_rtx != post_inc)
7402 emit_move_insn (r0, mem_rtx);
7405 else if (TARGET_REGISTER_P (reg))
7407 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7409 /* Give the scheduler a bit of freedom by using up to
7410 MAX_TEMPS registers in a round-robin fashion. */
7411 emit_move_insn (tmp_reg, mem_rtx);
7414 tmp_pnt = schedule.temps;
7417 emit_move_insn (reg_rtx, mem_rtx);
7420 gcc_assert (entry->offset + offset_base == d + d_rounding);
7422 else /* ! TARGET_SH5 */
7427 /* For an ISR with RESBANK attribute assigned, don't pop PR
7429 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7430 && !sh_cfun_resbank_handler_p ())
7432 if (!frame_pointer_needed)
7433 emit_insn (gen_blockage ());
7437 /* Banked registers are popped first to avoid being scheduled in the
7438 delay slot. RTE switches banks before the ds instruction. */
7439 if (current_function_interrupt)
7441 bool use_movml = false;
7445 unsigned int count = 0;
7447 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7448 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7453 /* Use movml when all banked register are poped. */
7454 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
7460 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
7462 /* We must avoid scheduling multiple load insn with another
7464 emit_insn (gen_blockage ());
7465 emit_insn (gen_movml_pop_banked (sp_reg));
7466 emit_insn (gen_blockage ());
7469 for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7470 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7473 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7476 last_reg = FIRST_PSEUDO_REGISTER;
7478 for (i = 0; i < last_reg; i++)
7480 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7482 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7483 && hard_reg_set_intersect_p (live_regs_mask,
7484 reg_class_contents[DF_REGS]))
7486 /* For an ISR with RESBANK attribute assigned, don't pop
7487 following registers, R0-R14, MACH, MACL and GBR. */
7488 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7489 && ! (sh_cfun_resbank_handler_p ()
7490 && ((j >= FIRST_GENERAL_REG
7491 && j < LAST_GENERAL_REG)
7497 if (j == FIRST_FP_REG && fpscr_deferred)
7501 if (target_flags != save_flags && ! current_function_interrupt)
7502 emit_insn (gen_toggle_sz ());
7503 target_flags = save_flags;
7505 output_stack_adjust (crtl->args.pretend_args_size
7506 + save_size + d_rounding
7507 + crtl->args.info.stack_regs * 8,
7508 stack_pointer_rtx, e, NULL, false);
7510 if (crtl->calls_eh_return)
7511 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7512 EH_RETURN_STACKADJ_RTX));
7514 /* Switch back to the normal stack if necessary. */
7515 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7516 emit_insn (gen_sp_switch_2 ());
7518 /* Tell flow the insn that pops PR isn't dead. */
7519 /* PR_REG will never be live in SHmedia mode, and we don't need to
7520 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7521 by the return pattern. */
7522 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7523 emit_use (gen_rtx_REG (SImode, PR_REG));
7526 static int sh_need_epilogue_known = 0;
7529 sh_need_epilogue (void)
7531 if (! sh_need_epilogue_known)
7536 sh_expand_epilogue (0);
7537 epilogue = get_insns ();
7539 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7541 return sh_need_epilogue_known > 0;
7544 /* Emit code to change the current function's return address to RA.
7545 TEMP is available as a scratch register, if needed. */
7548 sh_set_return_address (rtx ra, rtx tmp)
7550 HARD_REG_SET live_regs_mask;
7552 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7555 d = calc_live_regs (&live_regs_mask);
7557 /* If pr_reg isn't life, we can set it (or the register given in
7558 sh_media_register_for_return) directly. */
7559 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7565 int rr_regno = sh_media_register_for_return ();
7570 rr = gen_rtx_REG (DImode, rr_regno);
7573 rr = gen_rtx_REG (SImode, pr_reg);
7575 emit_insn (GEN_MOV (rr, ra));
7576 /* Tell flow the register for return isn't dead. */
7584 save_schedule schedule;
7587 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7588 offset = entry[1].offset;
7589 for (; entry->mode != VOIDmode; entry--)
7590 if (entry->reg == pr_reg)
7593 /* We can't find pr register. */
7597 offset = entry->offset - offset;
7598 pr_offset = (rounded_frame_size (d) + offset
7599 + SHMEDIA_REGS_STACK_ADJUST ());
7602 pr_offset = rounded_frame_size (d);
7604 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7606 if (frame_pointer_needed)
7607 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7609 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
7611 tmp = gen_frame_mem (Pmode, tmp);
7612 emit_insn (GEN_MOV (tmp, ra));
7613 /* Tell this store isn't dead. */
7617 /* Clear variables at function end. */
7620 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7621 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7623 sh_need_epilogue_known = 0;
7627 sh_builtin_saveregs (void)
7629 /* First unnamed integer register. */
7630 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7631 /* Number of integer registers we need to save. */
7632 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7633 /* First unnamed SFmode float reg */
7634 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7635 /* Number of SFmode float regs to save. */
7636 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7639 alias_set_type alias_set;
7645 int pushregs = n_intregs;
7647 while (pushregs < NPARM_REGS (SImode) - 1
7648 && (CALL_COOKIE_INT_REG_GET
7649 (crtl->args.info.call_cookie,
7650 NPARM_REGS (SImode) - pushregs)
7653 crtl->args.info.call_cookie
7654 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7659 if (pushregs == NPARM_REGS (SImode))
7660 crtl->args.info.call_cookie
7661 |= (CALL_COOKIE_INT_REG (0, 1)
7662 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7664 crtl->args.info.call_cookie
7665 |= CALL_COOKIE_STACKSEQ (pushregs);
7667 crtl->args.pretend_args_size += 8 * n_intregs;
7669 if (TARGET_SHCOMPACT)
7673 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7675 error ("__builtin_saveregs not supported by this subtarget");
7682 /* Allocate block of memory for the regs. */
7683 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7684 Or can assign_stack_local accept a 0 SIZE argument? */
7685 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7688 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7689 else if (n_floatregs & 1)
7693 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7694 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7695 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7696 regbuf = change_address (regbuf, BLKmode, addr);
7698 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7702 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7703 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7704 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7705 emit_insn (gen_andsi3 (addr, addr, mask));
7706 regbuf = change_address (regbuf, BLKmode, addr);
7709 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7710 alias_set = get_varargs_alias_set ();
7711 set_mem_alias_set (regbuf, alias_set);
7714 This is optimized to only save the regs that are necessary. Explicitly
7715 named args need not be saved. */
7717 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7718 adjust_address (regbuf, BLKmode,
7719 n_floatregs * UNITS_PER_WORD),
7723 /* Return the address of the regbuf. */
7724 return XEXP (regbuf, 0);
7727 This is optimized to only save the regs that are necessary. Explicitly
7728 named args need not be saved.
7729 We explicitly build a pointer to the buffer because it halves the insn
7730 count when not optimizing (otherwise the pointer is built for each reg
7732 We emit the moves in reverse order so that we can use predecrement. */
7734 fpregs = copy_to_mode_reg (Pmode,
7735 plus_constant (XEXP (regbuf, 0),
7736 n_floatregs * UNITS_PER_WORD));
7737 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7740 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7742 emit_insn (gen_addsi3 (fpregs, fpregs,
7743 GEN_INT (-2 * UNITS_PER_WORD)));
7744 mem = change_address (regbuf, DFmode, fpregs);
7745 emit_move_insn (mem,
7746 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7748 regno = first_floatreg;
7751 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7752 mem = change_address (regbuf, SFmode, fpregs);
7753 emit_move_insn (mem,
7754 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7755 - (TARGET_LITTLE_ENDIAN != 0)));
7759 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7763 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7764 mem = change_address (regbuf, SFmode, fpregs);
7765 emit_move_insn (mem,
7766 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7769 /* Return the address of the regbuf. */
7770 return XEXP (regbuf, 0);
7773 /* Define the `__builtin_va_list' type for the ABI. */
7776 sh_build_builtin_va_list (void)
7778 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7779 tree record, type_decl;
7781 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7782 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7783 return ptr_type_node;
7785 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7786 type_decl = build_decl (BUILTINS_LOCATION,
7787 TYPE_DECL, get_identifier ("__va_list_tag"), record);
7789 f_next_o = build_decl (BUILTINS_LOCATION,
7790 FIELD_DECL, get_identifier ("__va_next_o"),
7792 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7794 get_identifier ("__va_next_o_limit"),
7796 f_next_fp = build_decl (BUILTINS_LOCATION,
7797 FIELD_DECL, get_identifier ("__va_next_fp"),
7799 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7801 get_identifier ("__va_next_fp_limit"),
7803 f_next_stack = build_decl (BUILTINS_LOCATION,
7804 FIELD_DECL, get_identifier ("__va_next_stack"),
7807 DECL_FIELD_CONTEXT (f_next_o) = record;
7808 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7809 DECL_FIELD_CONTEXT (f_next_fp) = record;
7810 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7811 DECL_FIELD_CONTEXT (f_next_stack) = record;
7813 TYPE_STUB_DECL (record) = type_decl;
7814 TYPE_NAME (record) = type_decl;
7815 TYPE_FIELDS (record) = f_next_o;
7816 DECL_CHAIN (f_next_o) = f_next_o_limit;
7817 DECL_CHAIN (f_next_o_limit) = f_next_fp;
7818 DECL_CHAIN (f_next_fp) = f_next_fp_limit;
7819 DECL_CHAIN (f_next_fp_limit) = f_next_stack;
7821 layout_type (record);
7826 /* Implement `va_start' for varargs and stdarg. */
7829 sh_va_start (tree valist, rtx nextarg)
7831 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7832 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7838 expand_builtin_saveregs ();
7839 std_expand_builtin_va_start (valist, nextarg);
7843 if ((! TARGET_SH2E && ! TARGET_SH4)
7844 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7846 std_expand_builtin_va_start (valist, nextarg);
7850 f_next_o = TYPE_FIELDS (va_list_type_node);
7851 f_next_o_limit = DECL_CHAIN (f_next_o);
7852 f_next_fp = DECL_CHAIN (f_next_o_limit);
7853 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7854 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7856 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7858 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7859 valist, f_next_o_limit, NULL_TREE);
7860 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7862 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7863 valist, f_next_fp_limit, NULL_TREE);
7864 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7865 valist, f_next_stack, NULL_TREE);
7867 /* Call __builtin_saveregs. */
7868 u = make_tree (sizetype, expand_builtin_saveregs ());
7869 u = fold_convert (ptr_type_node, u);
7870 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7871 TREE_SIDE_EFFECTS (t) = 1;
7872 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7874 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7879 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nfp);
7880 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7881 TREE_SIDE_EFFECTS (t) = 1;
7882 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7884 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7885 TREE_SIDE_EFFECTS (t) = 1;
7886 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7888 nint = crtl->args.info.arg_count[SH_ARG_INT];
7893 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nint);
7894 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7895 TREE_SIDE_EFFECTS (t) = 1;
7896 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7898 u = make_tree (ptr_type_node, nextarg);
7899 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7900 TREE_SIDE_EFFECTS (t) = 1;
7901 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7904 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7905 member, return it. */
7907 find_sole_member (tree type)
7909 tree field, member = NULL_TREE;
7911 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
7913 if (TREE_CODE (field) != FIELD_DECL)
7915 if (!DECL_SIZE (field))
7917 if (integer_zerop (DECL_SIZE (field)))
7925 /* Implement `va_arg'. */
7928 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7929 gimple_seq *post_p ATTRIBUTE_UNUSED)
7931 HOST_WIDE_INT size, rsize;
7932 tree tmp, pptr_type_node;
7933 tree addr, lab_over = NULL, result = NULL;
7937 if (!VOID_TYPE_P (type))
7938 pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7940 pass_by_ref = false;
7943 type = build_pointer_type (type);
7945 size = int_size_in_bytes (type);
7946 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7947 pptr_type_node = build_pointer_type (ptr_type_node);
7949 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7950 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7952 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7953 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7958 f_next_o = TYPE_FIELDS (va_list_type_node);
7959 f_next_o_limit = DECL_CHAIN (f_next_o);
7960 f_next_fp = DECL_CHAIN (f_next_o_limit);
7961 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7962 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7964 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7966 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7967 valist, f_next_o_limit, NULL_TREE);
7968 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7969 valist, f_next_fp, NULL_TREE);
7970 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7971 valist, f_next_fp_limit, NULL_TREE);
7972 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7973 valist, f_next_stack, NULL_TREE);
7975 /* Structures with a single member with a distinct mode are passed
7976 like their member. This is relevant if the latter has a REAL_TYPE
7977 or COMPLEX_TYPE type. */
7979 while (TREE_CODE (eff_type) == RECORD_TYPE
7980 && (member = find_sole_member (eff_type))
7981 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7982 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7983 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7985 tree field_type = TREE_TYPE (member);
7987 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7988 eff_type = field_type;
7991 gcc_assert ((TYPE_ALIGN (eff_type)
7992 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7993 || (TYPE_ALIGN (eff_type)
7994 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7999 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8001 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
8002 || (TREE_CODE (eff_type) == COMPLEX_TYPE
8003 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
8008 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
8011 addr = create_tmp_var (pptr_type_node, NULL);
8012 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8013 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8015 valist = build_simple_mem_ref (addr);
8019 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
8021 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
8023 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
8024 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8026 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
8027 tmp = next_fp_limit;
8028 if (size > 4 && !is_double)
8029 tmp = fold_build_pointer_plus_hwi (unshare_expr (tmp), 4 - size);
8030 tmp = build2 (GE_EXPR, boolean_type_node,
8031 unshare_expr (next_fp_tmp), unshare_expr (tmp));
8032 cmp = build3 (COND_EXPR, void_type_node, tmp,
8033 build1 (GOTO_EXPR, void_type_node,
8034 unshare_expr (lab_false)), NULL_TREE);
8036 gimplify_and_add (cmp, pre_p);
8038 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
8039 || (is_double || size == 16))
8041 tmp = fold_convert (sizetype, next_fp_tmp);
8042 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
8043 size_int (UNITS_PER_WORD));
8044 tmp = fold_build_pointer_plus (unshare_expr (next_fp_tmp), tmp);
8045 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
8048 gimplify_and_add (cmp, pre_p);
8050 #ifdef FUNCTION_ARG_SCmode_WART
8051 if (TYPE_MODE (eff_type) == SCmode
8052 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
8054 tree subtype = TREE_TYPE (eff_type);
8058 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8059 imag = get_initialized_tmp_var (imag, pre_p, NULL);
8062 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8063 real = get_initialized_tmp_var (real, pre_p, NULL);
8065 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
8066 if (type != eff_type)
8067 result = build1 (VIEW_CONVERT_EXPR, type, result);
8068 result = get_initialized_tmp_var (result, pre_p, NULL);
8070 #endif /* FUNCTION_ARG_SCmode_WART */
8072 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8073 gimplify_and_add (tmp, pre_p);
8075 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8076 gimplify_and_add (tmp, pre_p);
8078 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8079 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8080 gimplify_assign (unshare_expr (next_fp_tmp),
8081 unshare_expr (valist), pre_p);
8083 gimplify_assign (unshare_expr (valist),
8084 unshare_expr (next_fp_tmp), post_p);
8085 valist = next_fp_tmp;
8089 tmp = fold_build_pointer_plus_hwi (unshare_expr (next_o), rsize);
8090 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
8091 unshare_expr (next_o_limit));
8092 tmp = build3 (COND_EXPR, void_type_node, tmp,
8093 build1 (GOTO_EXPR, void_type_node,
8094 unshare_expr (lab_false)),
8096 gimplify_and_add (tmp, pre_p);
8098 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
8099 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8101 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8102 gimplify_and_add (tmp, pre_p);
8104 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8105 gimplify_and_add (tmp, pre_p);
8107 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
8108 gimplify_assign (unshare_expr (next_o),
8109 unshare_expr (next_o_limit), pre_p);
8111 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8112 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8117 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8118 gimplify_and_add (tmp, pre_p);
8122 /* ??? In va-sh.h, there had been code to make values larger than
8123 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8125 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
8128 gimplify_assign (result, tmp, pre_p);
8129 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
8130 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8131 gimplify_and_add (tmp, pre_p);
8137 result = build_va_arg_indirect_ref (result);
8142 /* 64 bit floating points memory transfers are paired single precision loads
8143 or store. So DWARF information needs fixing in little endian (unless
8144 PR=SZ=1 in FPSCR). */
8146 sh_dwarf_register_span (rtx reg)
8148 unsigned regno = REGNO (reg);
8150 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
8154 gen_rtx_PARALLEL (VOIDmode,
8156 gen_rtx_REG (SFmode, regno + 1),
8157 gen_rtx_REG (SFmode, regno)));
8160 static enum machine_mode
8161 sh_promote_function_mode (const_tree type, enum machine_mode mode,
8162 int *punsignedp, const_tree funtype,
8165 if (sh_promote_prototypes (funtype))
8166 return promote_mode (type, mode, punsignedp);
8168 return default_promote_function_mode (type, mode, punsignedp, funtype,
8173 sh_promote_prototypes (const_tree type)
8179 return ! sh_attr_renesas_p (type);
8182 /* Whether an argument must be passed by reference. On SHcompact, we
8183 pretend arguments wider than 32-bits that would have been passed in
8184 registers are passed by reference, so that an SHmedia trampoline
8185 loads them into the full 64-bits registers. */
8188 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8189 const_tree type, bool named)
8191 unsigned HOST_WIDE_INT size;
8194 size = int_size_in_bytes (type);
8196 size = GET_MODE_SIZE (mode);
8198 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
8200 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
8201 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
8202 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
8204 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
8205 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8212 sh_pass_by_reference (cumulative_args_t cum_v, enum machine_mode mode,
8213 const_tree type, bool named)
8215 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8217 if (targetm.calls.must_pass_in_stack (mode, type))
8220 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8221 wants to know about pass-by-reference semantics for incoming
8226 if (TARGET_SHCOMPACT)
8228 cum->byref = shcompact_byref (cum, mode, type, named);
8229 return cum->byref != 0;
8236 sh_callee_copies (cumulative_args_t cum, enum machine_mode mode,
8237 const_tree type, bool named ATTRIBUTE_UNUSED)
8239 /* ??? How can it possibly be correct to return true only on the
8240 caller side of the equation? Is there someplace else in the
8241 sh backend that's magically producing the copies? */
8242 return (get_cumulative_args (cum)->outgoing
8243 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8244 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8248 sh_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8249 tree type, bool named ATTRIBUTE_UNUSED)
8251 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8255 && PASS_IN_REG_P (*cum, mode, type)
8256 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8257 && (ROUND_REG (*cum, mode)
8259 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8260 : ROUND_ADVANCE (int_size_in_bytes (type)))
8261 > NPARM_REGS (mode)))
8262 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8264 else if (!TARGET_SHCOMPACT
8265 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8266 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8268 return words * UNITS_PER_WORD;
8272 /* Define where to put the arguments to a function.
8273 Value is zero to push the argument on the stack,
8274 or a hard register in which to store the argument.
8276 MODE is the argument's machine mode.
8277 TYPE is the data type of the argument (as a tree).
8278 This is null for libcalls where that information may
8280 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8281 the preceding args and about the function being called.
8282 NAMED is nonzero if this argument is a named parameter
8283 (otherwise it is an extra parameter matching an ellipsis).
8285 On SH the first args are normally in registers
8286 and the rest are pushed. Any arg that starts within the first
8287 NPARM_REGS words is at least partially passed in a register unless
8288 its data type forbids. */
8291 sh_function_arg (cumulative_args_t ca_v, enum machine_mode mode,
8292 const_tree type, bool named)
8294 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8296 if (! TARGET_SH5 && mode == VOIDmode)
8297 return GEN_INT (ca->renesas_abi ? 1 : 0);
8300 && PASS_IN_REG_P (*ca, mode, type)
8301 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8305 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8306 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8308 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8309 gen_rtx_REG (SFmode,
8311 + (ROUND_REG (*ca, mode) ^ 1)),
8313 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8314 gen_rtx_REG (SFmode,
8316 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8318 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8321 /* If the alignment of a DF value causes an SF register to be
8322 skipped, we will use that skipped register for the next SF
8324 if ((TARGET_HITACHI || ca->renesas_abi)
8325 && ca->free_single_fp_reg
8327 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8329 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8330 ^ (mode == SFmode && TARGET_SH4
8331 && TARGET_LITTLE_ENDIAN != 0
8332 && ! TARGET_HITACHI && ! ca->renesas_abi);
8333 return gen_rtx_REG (mode, regno);
8339 if (mode == VOIDmode && TARGET_SHCOMPACT)
8340 return GEN_INT (ca->call_cookie);
8342 /* The following test assumes unnamed arguments are promoted to
8344 if (mode == SFmode && ca->free_single_fp_reg)
8345 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8347 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8348 && (named || ! ca->prototype_p)
8349 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8351 if (! ca->prototype_p && TARGET_SHMEDIA)
8352 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8354 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8356 + ca->arg_count[(int) SH_ARG_FLOAT]);
8359 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8360 && (! TARGET_SHCOMPACT
8361 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8362 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8365 return gen_rtx_REG (mode, (FIRST_PARM_REG
8366 + ca->arg_count[(int) SH_ARG_INT]));
8375 /* Update the data in CUM to advance over an argument
8376 of mode MODE and data type TYPE.
8377 (TYPE is null for libcalls where that information may not be
8381 sh_function_arg_advance (cumulative_args_t ca_v, enum machine_mode mode,
8382 const_tree type, bool named)
8384 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8388 else if (TARGET_SH5)
8390 const_tree type2 = (ca->byref && type
8393 enum machine_mode mode2 = (ca->byref && type
8396 int dwords = ((ca->byref
8399 ? int_size_in_bytes (type2)
8400 : GET_MODE_SIZE (mode2)) + 7) / 8;
8401 int numregs = MIN (dwords, NPARM_REGS (SImode)
8402 - ca->arg_count[(int) SH_ARG_INT]);
8406 ca->arg_count[(int) SH_ARG_INT] += numregs;
8407 if (TARGET_SHCOMPACT
8408 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8411 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8413 /* N.B. We want this also for outgoing. */
8414 ca->stack_regs += numregs;
8419 ca->stack_regs += numregs;
8420 ca->byref_regs += numregs;
8424 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8428 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8431 else if (dwords > numregs)
8433 int pushregs = numregs;
8435 if (TARGET_SHCOMPACT)
8436 ca->stack_regs += numregs;
8437 while (pushregs < NPARM_REGS (SImode) - 1
8438 && (CALL_COOKIE_INT_REG_GET
8440 NPARM_REGS (SImode) - pushregs)
8444 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8448 if (numregs == NPARM_REGS (SImode))
8450 |= CALL_COOKIE_INT_REG (0, 1)
8451 | CALL_COOKIE_STACKSEQ (numregs - 1);
8454 |= CALL_COOKIE_STACKSEQ (numregs);
8457 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8458 && (named || ! ca->prototype_p))
8460 if (mode2 == SFmode && ca->free_single_fp_reg)
8461 ca->free_single_fp_reg = 0;
8462 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8463 < NPARM_REGS (SFmode))
8466 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8468 - ca->arg_count[(int) SH_ARG_FLOAT]);
8470 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8472 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8474 if (ca->outgoing && numregs > 0)
8478 |= (CALL_COOKIE_INT_REG
8479 (ca->arg_count[(int) SH_ARG_INT]
8480 - numregs + ((numfpregs - 2) / 2),
8481 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8484 while (numfpregs -= 2);
8486 else if (mode2 == SFmode && (named)
8487 && (ca->arg_count[(int) SH_ARG_FLOAT]
8488 < NPARM_REGS (SFmode)))
8489 ca->free_single_fp_reg
8490 = FIRST_FP_PARM_REG - numfpregs
8491 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8497 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8499 /* Note that we've used the skipped register. */
8500 if (mode == SFmode && ca->free_single_fp_reg)
8502 ca->free_single_fp_reg = 0;
8505 /* When we have a DF after an SF, there's an SF register that get
8506 skipped in order to align the DF value. We note this skipped
8507 register, because the next SF value will use it, and not the
8508 SF that follows the DF. */
8510 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8512 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8513 + BASE_ARG_REG (mode));
8517 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8518 || PASS_IN_REG_P (*ca, mode, type))
8519 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8520 = (ROUND_REG (*ca, mode)
8522 ? ROUND_ADVANCE (int_size_in_bytes (type))
8523 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8526 /* The Renesas calling convention doesn't quite fit into this scheme since
8527 the address is passed like an invisible argument, but one that is always
8528 passed in memory. */
8530 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8532 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8534 return gen_rtx_REG (Pmode, 2);
8537 /* Worker function for TARGET_FUNCTION_VALUE.
8539 For the SH, this is like LIBCALL_VALUE, except that we must change the
8540 mode like PROMOTE_MODE does.
8541 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8542 tested here has to be kept in sync with the one in explow.c:promote_mode.
8546 sh_function_value (const_tree valtype,
8547 const_tree fn_decl_or_type,
8548 bool outgoing ATTRIBUTE_UNUSED)
8551 && !DECL_P (fn_decl_or_type))
8552 fn_decl_or_type = NULL;
8554 return gen_rtx_REG (
8555 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8556 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8557 && (TREE_CODE (valtype) == INTEGER_TYPE
8558 || TREE_CODE (valtype) == ENUMERAL_TYPE
8559 || TREE_CODE (valtype) == BOOLEAN_TYPE
8560 || TREE_CODE (valtype) == REAL_TYPE
8561 || TREE_CODE (valtype) == OFFSET_TYPE))
8562 && sh_promote_prototypes (fn_decl_or_type)
8563 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)),
8564 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8567 /* Worker function for TARGET_LIBCALL_VALUE. */
8570 sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8572 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8575 /* Return true if N is a possible register number of function value. */
8578 sh_function_value_regno_p (const unsigned int regno)
8580 return ((regno) == FIRST_RET_REG
8581 || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG)
8582 || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG));
8585 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8588 sh_return_in_memory (const_tree type, const_tree fndecl)
8592 if (TYPE_MODE (type) == BLKmode)
8593 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8595 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8599 return (TYPE_MODE (type) == BLKmode
8600 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8601 && TREE_CODE (type) == RECORD_TYPE));
8605 /* We actually emit the code in sh_expand_prologue. We used to use
8606 a static variable to flag that we need to emit this code, but that
8607 doesn't when inlining, when functions are deferred and then emitted
8608 later. Fortunately, we already have two flags that are part of struct
8609 function that tell if a function uses varargs or stdarg. */
8611 sh_setup_incoming_varargs (cumulative_args_t ca,
8612 enum machine_mode mode,
8614 int *pretend_arg_size,
8615 int second_time ATTRIBUTE_UNUSED)
8617 gcc_assert (cfun->stdarg);
8618 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8620 int named_parm_regs, anon_parm_regs;
8622 named_parm_regs = (ROUND_REG (*get_cumulative_args (ca), mode)
8624 ? ROUND_ADVANCE (int_size_in_bytes (type))
8625 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8626 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8627 if (anon_parm_regs > 0)
8628 *pretend_arg_size = anon_parm_regs * 4;
8633 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
8639 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v)
8641 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8643 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8647 /* Define the offset between two registers, one to be eliminated, and
8648 the other its replacement, at the start of a routine. */
8651 initial_elimination_offset (int from, int to)
8654 int regs_saved_rounding = 0;
8655 int total_saved_regs_space;
8656 int total_auto_space;
8657 int save_flags = target_flags;
8659 HARD_REG_SET live_regs_mask;
8661 shmedia_space_reserved_for_target_registers = false;
8662 regs_saved = calc_live_regs (&live_regs_mask);
8663 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8665 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8667 shmedia_space_reserved_for_target_registers = true;
8668 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8671 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8672 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8673 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8675 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8676 copy_flags = target_flags;
8677 target_flags = save_flags;
8679 total_saved_regs_space = regs_saved + regs_saved_rounding;
8681 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8682 return total_saved_regs_space + total_auto_space
8683 + crtl->args.info.byref_regs * 8;
8685 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8686 return total_saved_regs_space + total_auto_space
8687 + crtl->args.info.byref_regs * 8;
8689 /* Initial gap between fp and sp is 0. */
8690 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8693 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8694 return rounded_frame_size (0);
8696 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8697 return rounded_frame_size (0);
8699 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8700 && (to == HARD_FRAME_POINTER_REGNUM
8701 || to == STACK_POINTER_REGNUM));
8704 int n = total_saved_regs_space;
8705 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8706 save_schedule schedule;
8709 n += total_auto_space;
8711 /* If it wasn't saved, there's not much we can do. */
8712 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8715 target_flags = copy_flags;
8717 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8718 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8719 if (entry->reg == pr_reg)
8721 target_flags = save_flags;
8722 return entry->offset;
8727 return total_auto_space;
8730 /* Parse the -mfixed-range= option string. */
8732 sh_fix_range (const char *const_str)
8735 char *str, *dash, *comma;
8737 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8738 REG2 are either register names or register numbers. The effect
8739 of this option is to mark the registers in the range from REG1 to
8740 REG2 as ``fixed'' so they won't be used by the compiler. */
8742 i = strlen (const_str);
8743 str = (char *) alloca (i + 1);
8744 memcpy (str, const_str, i + 1);
8748 dash = strchr (str, '-');
8751 warning (0, "value of -mfixed-range must have form REG1-REG2");
8755 comma = strchr (dash + 1, ',');
8759 first = decode_reg_name (str);
8762 warning (0, "unknown register name: %s", str);
8766 last = decode_reg_name (dash + 1);
8769 warning (0, "unknown register name: %s", dash + 1);
8777 warning (0, "%s-%s is an empty range", str, dash + 1);
8781 for (i = first; i <= last; ++i)
8782 fixed_regs[i] = call_used_regs[i] = 1;
8792 /* Insert any deferred function attributes from earlier pragmas. */
8794 sh_insert_attributes (tree node, tree *attributes)
8798 if (TREE_CODE (node) != FUNCTION_DECL)
8801 /* We are only interested in fields. */
8805 /* Append the attributes to the deferred attributes. */
8806 *sh_deferred_function_attributes_tail = *attributes;
8807 attrs = sh_deferred_function_attributes;
8811 /* Some attributes imply or require the interrupt attribute. */
8812 if (!lookup_attribute ("interrupt_handler", attrs)
8813 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8815 /* If we have a trapa_handler, but no interrupt_handler attribute,
8816 insert an interrupt_handler attribute. */
8817 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8818 /* We can't use sh_pr_interrupt here because that's not in the
8821 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8822 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8823 if the interrupt attribute is missing, we ignore the attribute
8825 else if (lookup_attribute ("sp_switch", attrs)
8826 || lookup_attribute ("trap_exit", attrs)
8827 || lookup_attribute ("nosave_low_regs", attrs)
8828 || lookup_attribute ("resbank", attrs))
8832 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8834 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8835 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8836 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8837 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8838 warning (OPT_Wattributes,
8839 "%qE attribute only applies to interrupt functions",
8840 TREE_PURPOSE (attrs));
8843 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8845 tail = &TREE_CHAIN (*tail);
8848 attrs = *attributes;
8852 /* Install the processed list. */
8853 *attributes = attrs;
8855 /* Clear deferred attributes. */
8856 sh_deferred_function_attributes = NULL_TREE;
8857 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8862 /* Supported attributes:
8864 interrupt_handler -- specifies this function is an interrupt handler.
8866 trapa_handler - like above, but don't save all registers.
8868 sp_switch -- specifies an alternate stack for an interrupt handler
8871 trap_exit -- use a trapa to exit an interrupt function instead of
8874 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8875 This is useful on the SH3 and upwards,
8876 which has a separate set of low regs for User and Supervisor modes.
8877 This should only be used for the lowest level of interrupts. Higher levels
8878 of interrupts must save the registers in case they themselves are
8881 renesas -- use Renesas calling/layout conventions (functions and
8884 resbank -- In case of an ISR, use a register bank to save registers
8885 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8888 /* Handle a 'resbank' attribute. */
8890 sh_handle_resbank_handler_attribute (tree * node, tree name,
8891 tree args ATTRIBUTE_UNUSED,
8892 int flags ATTRIBUTE_UNUSED,
8893 bool * no_add_attrs)
8897 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8899 *no_add_attrs = true;
8901 if (TREE_CODE (*node) != FUNCTION_DECL)
8903 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8905 *no_add_attrs = true;
8911 /* Handle an "interrupt_handler" attribute; arguments as in
8912 struct attribute_spec.handler. */
8914 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8915 tree args ATTRIBUTE_UNUSED,
8916 int flags ATTRIBUTE_UNUSED,
8919 if (TREE_CODE (*node) != FUNCTION_DECL)
8921 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8923 *no_add_attrs = true;
8925 else if (TARGET_SHCOMPACT)
8927 error ("attribute interrupt_handler is not compatible with -m5-compact");
8928 *no_add_attrs = true;
8934 /* Handle an 'function_vector' attribute; arguments as in
8935 struct attribute_spec.handler. */
8937 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8938 tree args ATTRIBUTE_UNUSED,
8939 int flags ATTRIBUTE_UNUSED,
8940 bool * no_add_attrs)
8944 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8946 *no_add_attrs = true;
8948 else if (TREE_CODE (*node) != FUNCTION_DECL)
8950 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8952 *no_add_attrs = true;
8954 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8956 /* The argument must be a constant integer. */
8957 warning (OPT_Wattributes,
8958 "%qE attribute argument not an integer constant",
8960 *no_add_attrs = true;
8962 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8964 /* The argument value must be between 0 to 255. */
8965 warning (OPT_Wattributes,
8966 "%qE attribute argument should be between 0 to 255",
8968 *no_add_attrs = true;
8973 /* Returns 1 if current function has been assigned the attribute
8974 'function_vector'. */
8976 sh2a_is_function_vector_call (rtx x)
8978 if (GET_CODE (x) == SYMBOL_REF
8979 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8981 tree tr = SYMBOL_REF_DECL (x);
8983 if (sh2a_function_vector_p (tr))
8990 /* Returns the function vector number, if the attribute
8991 'function_vector' is assigned, otherwise returns zero. */
8993 sh2a_get_function_vector_number (rtx x)
8998 if ((GET_CODE (x) == SYMBOL_REF)
8999 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
9001 t = SYMBOL_REF_DECL (x);
9003 if (TREE_CODE (t) != FUNCTION_DECL)
9006 list = SH_ATTRIBUTES (t);
9009 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9011 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
9015 list = TREE_CHAIN (list);
9024 /* Handle an "sp_switch" attribute; arguments as in
9025 struct attribute_spec.handler. */
9027 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
9028 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9030 if (TREE_CODE (*node) != FUNCTION_DECL)
9032 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9034 *no_add_attrs = true;
9036 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
9038 /* The argument must be a constant string. */
9039 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
9041 *no_add_attrs = true;
9047 /* Handle an "trap_exit" attribute; arguments as in
9048 struct attribute_spec.handler. */
9050 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
9051 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9053 if (TREE_CODE (*node) != FUNCTION_DECL)
9055 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9057 *no_add_attrs = true;
9059 /* The argument specifies a trap number to be used in a trapa instruction
9060 at function exit (instead of an rte instruction). */
9061 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
9063 /* The argument must be a constant integer. */
9064 warning (OPT_Wattributes, "%qE attribute argument not an "
9065 "integer constant", name);
9066 *no_add_attrs = true;
9073 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
9074 tree name ATTRIBUTE_UNUSED,
9075 tree args ATTRIBUTE_UNUSED,
9076 int flags ATTRIBUTE_UNUSED,
9077 bool *no_add_attrs ATTRIBUTE_UNUSED)
9082 /* True if __attribute__((renesas)) or -mrenesas. */
9084 sh_attr_renesas_p (const_tree td)
9091 td = TREE_TYPE (td);
9092 if (td == error_mark_node)
9094 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
9098 /* True if __attribute__((renesas)) or -mrenesas, for the current
9101 sh_cfun_attr_renesas_p (void)
9103 return sh_attr_renesas_p (current_function_decl);
9107 sh_cfun_interrupt_handler_p (void)
9109 return (lookup_attribute ("interrupt_handler",
9110 DECL_ATTRIBUTES (current_function_decl))
9114 /* Returns 1 if FUNC has been assigned the attribute
9115 "function_vector". */
9117 sh2a_function_vector_p (tree func)
9120 if (TREE_CODE (func) != FUNCTION_DECL)
9123 list = SH_ATTRIBUTES (func);
9126 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9129 list = TREE_CHAIN (list);
9134 /* Returns TRUE if given tree has the "resbank" attribute. */
9137 sh_cfun_resbank_handler_p (void)
9139 return ((lookup_attribute ("resbank",
9140 DECL_ATTRIBUTES (current_function_decl))
9142 && (lookup_attribute ("interrupt_handler",
9143 DECL_ATTRIBUTES (current_function_decl))
9144 != NULL_TREE) && TARGET_SH2A);
9147 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9150 sh_check_pch_target_flags (int old_flags)
9152 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
9153 | MASK_SH_E | MASK_HARD_SH4
9154 | MASK_FPU_SINGLE | MASK_SH4))
9155 return _("created and used with different architectures / ABIs");
9156 if ((old_flags ^ target_flags) & MASK_HITACHI)
9157 return _("created and used with different ABIs");
9158 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
9159 return _("created and used with different endianness");
9163 /* Predicates used by the templates. */
9165 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
9166 Used only in general_movsrc_operand. */
9169 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9181 /* Nonzero if OP is a floating point value with value 0.0. */
9184 fp_zero_operand (rtx op)
9188 if (GET_MODE (op) != SFmode)
9191 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9192 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
9195 /* Nonzero if OP is a floating point value with value 1.0. */
9198 fp_one_operand (rtx op)
9202 if (GET_MODE (op) != SFmode)
9205 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9206 return REAL_VALUES_EQUAL (r, dconst1);
9209 /* In general mode switching is used. If we are
9210 compiling without -mfmovd, movsf_ie isn't taken into account for
9211 mode switching. We could check in machine_dependent_reorg for
9212 cases where we know we are in single precision mode, but there is
9213 interface to find that out during reload, so we must avoid
9214 choosing an fldi alternative during reload and thus failing to
9215 allocate a scratch register for the constant loading. */
9222 /* Return the TLS type for TLS symbols, 0 for otherwise. */
9224 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9226 if (GET_CODE (op) != SYMBOL_REF)
9227 return TLS_MODEL_NONE;
9228 return SYMBOL_REF_TLS_MODEL (op);
9231 /* Return the destination address of a branch. */
9234 branch_dest (rtx branch)
9236 rtx dest = SET_SRC (PATTERN (branch));
9239 if (GET_CODE (dest) == IF_THEN_ELSE)
9240 dest = XEXP (dest, 1);
9241 dest = XEXP (dest, 0);
9242 dest_uid = INSN_UID (dest);
9243 return INSN_ADDRESSES (dest_uid);
9246 /* Return nonzero if REG is not used after INSN.
9247 We assume REG is a reload reg, and therefore does
9248 not live past labels. It may live past calls or jumps though. */
9250 reg_unused_after (rtx reg, rtx insn)
9255 /* If the reg is set by this instruction, then it is safe for our
9256 case. Disregard the case where this is a store to memory, since
9257 we are checking a register used in the store address. */
9258 set = single_set (insn);
9259 if (set && !MEM_P (SET_DEST (set))
9260 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9263 while ((insn = NEXT_INSN (insn)))
9269 code = GET_CODE (insn);
9272 /* If this is a label that existed before reload, then the register
9273 is dead here. However, if this is a label added by reorg, then
9274 the register may still be live here. We can't tell the difference,
9275 so we just ignore labels completely. */
9276 if (code == CODE_LABEL)
9281 if (code == JUMP_INSN)
9284 /* If this is a sequence, we must handle them all at once.
9285 We could have for instance a call that sets the target register,
9286 and an insn in a delay slot that uses the register. In this case,
9287 we must return 0. */
9288 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
9293 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9295 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9296 rtx set = single_set (this_insn);
9298 if (CALL_P (this_insn))
9300 else if (JUMP_P (this_insn))
9302 if (INSN_ANNULLED_BRANCH_P (this_insn))
9307 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9309 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9311 if (!MEM_P (SET_DEST (set)))
9317 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9322 else if (code == JUMP_INSN)
9326 set = single_set (insn);
9327 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9329 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9330 return !MEM_P (SET_DEST (set));
9331 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9334 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9342 static GTY(()) rtx fpscr_rtx;
9344 get_fpscr_rtx (void)
9348 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9349 REG_USERVAR_P (fpscr_rtx) = 1;
9350 mark_user_reg (fpscr_rtx);
9352 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9353 mark_user_reg (fpscr_rtx);
9357 static GTY(()) tree fpscr_values;
9360 emit_fpu_switch (rtx scratch, int index)
9364 if (fpscr_values == NULL)
9368 t = build_index_type (integer_one_node);
9369 t = build_array_type (integer_type_node, t);
9370 t = build_decl (BUILTINS_LOCATION,
9371 VAR_DECL, get_identifier ("__fpscr_values"), t);
9372 DECL_ARTIFICIAL (t) = 1;
9373 DECL_IGNORED_P (t) = 1;
9374 DECL_EXTERNAL (t) = 1;
9375 TREE_STATIC (t) = 1;
9376 TREE_PUBLIC (t) = 1;
9382 src = DECL_RTL (fpscr_values);
9383 if (!can_create_pseudo_p ())
9385 emit_move_insn (scratch, XEXP (src, 0));
9387 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9388 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9391 src = adjust_address (src, PSImode, index * 4);
9393 dst = get_fpscr_rtx ();
9394 emit_move_insn (dst, src);
9398 emit_sf_insn (rtx pat)
9404 emit_df_insn (rtx pat)
9410 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9412 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9416 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9418 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9423 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9425 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9429 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9431 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9435 static rtx get_free_reg (HARD_REG_SET);
9437 /* This function returns a register to use to load the address to load
9438 the fpscr from. Currently it always returns r1 or r7, but when we are
9439 able to use pseudo registers after combine, or have a better mechanism
9440 for choosing a register, it should be done here. */
9441 /* REGS_LIVE is the liveness information for the point for which we
9442 need this allocation. In some bare-bones exit blocks, r1 is live at the
9443 start. We can even have all of r0..r3 being live:
9444 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9445 INSN before which new insns are placed with will clobber the register
9446 we return. If a basic block consists only of setting the return value
9447 register to a pseudo and using that register, the return value is not
9448 live before or after this block, yet we we'll insert our insns right in
9452 get_free_reg (HARD_REG_SET regs_live)
9454 if (! TEST_HARD_REG_BIT (regs_live, 1))
9455 return gen_rtx_REG (Pmode, 1);
9457 /* Hard reg 1 is live; since this is a small register classes target,
9458 there shouldn't be anything but a jump before the function end. */
9459 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9460 return gen_rtx_REG (Pmode, 7);
9463 /* This function will set the fpscr from memory.
9464 MODE is the mode we are setting it to. */
9466 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9468 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9469 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9472 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9473 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9476 /* Is the given character a logical line separator for the assembler? */
9477 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9478 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9482 sh_insn_length_adjustment (rtx insn)
9484 /* Instructions with unfilled delay slots take up an extra two bytes for
9485 the nop in the delay slot. */
9486 if (((NONJUMP_INSN_P (insn)
9487 && GET_CODE (PATTERN (insn)) != USE
9488 && GET_CODE (PATTERN (insn)) != CLOBBER)
9490 || (JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)))
9491 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9492 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9495 /* SH2e has a bug that prevents the use of annulled branches, so if
9496 the delay slot is not filled, we'll have to put a NOP in it. */
9497 if (sh_cpu_attr == CPU_SH2E
9498 && JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)
9499 && get_attr_type (insn) == TYPE_CBRANCH
9500 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9503 /* sh-dsp parallel processing insn take four bytes instead of two. */
9505 if (NONJUMP_INSN_P (insn))
9508 rtx body = PATTERN (insn);
9511 int maybe_label = 1;
9513 if (GET_CODE (body) == ASM_INPUT)
9514 templ = XSTR (body, 0);
9515 else if (asm_noperands (body) >= 0)
9517 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9526 while (c == ' ' || c == '\t');
9527 /* all sh-dsp parallel-processing insns start with p.
9528 The only non-ppi sh insn starting with p is pref.
9529 The only ppi starting with pr is prnd. */
9530 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9532 /* The repeat pseudo-insn expands two three insns, a total of
9533 six bytes in size. */
9534 else if ((c == 'r' || c == 'R')
9535 && ! strncasecmp ("epeat", templ, 5))
9537 while (c && c != '\n'
9538 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9540 /* If this is a label, it is obviously not a ppi insn. */
9541 if (c == ':' && maybe_label)
9546 else if (c == '\'' || c == '"')
9551 maybe_label = c != ':';
9559 /* Return TRUE for a valid displacement for the REG+disp addressing
9562 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9563 into the FRx registers. We implement this by setting the maximum offset
9564 to zero when the value is SFmode. This also restricts loading of SFmode
9565 values into the integer registers, but that can't be helped. */
9567 /* The SH allows a displacement in a QI or HI amode, but only when the
9568 other operand is R0. GCC doesn't handle this very well, so we forgot
9571 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9572 DI can be any number 0..60. */
9575 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9577 if (CONST_INT_P (op))
9583 /* Check if this is the address of an unaligned load / store. */
9584 if (mode == VOIDmode)
9585 return CONST_OK_FOR_I06 (INTVAL (op));
9587 size = GET_MODE_SIZE (mode);
9588 return (!(INTVAL (op) & (size - 1))
9589 && INTVAL (op) >= -512 * size
9590 && INTVAL (op) < 512 * size);
9595 if (GET_MODE_SIZE (mode) == 1
9596 && (unsigned) INTVAL (op) < 4096)
9600 if ((GET_MODE_SIZE (mode) == 4
9601 && (unsigned) INTVAL (op) < 64
9602 && !(INTVAL (op) & 3)
9603 && !(TARGET_SH2E && mode == SFmode))
9604 || (GET_MODE_SIZE (mode) == 4
9605 && (unsigned) INTVAL (op) < 16383
9606 && !(INTVAL (op) & 3) && TARGET_SH2A))
9609 if ((GET_MODE_SIZE (mode) == 8
9610 && (unsigned) INTVAL (op) < 60
9611 && !(INTVAL (op) & 3)
9612 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9613 || ((GET_MODE_SIZE (mode)==8)
9614 && (unsigned) INTVAL (op) < 8192
9615 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9616 && (TARGET_SH2A && mode == DFmode)))
9623 /* Recognize an RTL expression that is a valid memory address for
9625 The MODE argument is the machine mode for the MEM expression
9626 that wants to use this address.
9634 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9636 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9638 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9640 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9642 else if (GET_CODE (x) == PLUS
9643 && (mode != PSImode || reload_completed))
9645 rtx xop0 = XEXP (x, 0);
9646 rtx xop1 = XEXP (x, 1);
9648 if (GET_MODE_SIZE (mode) <= 8
9649 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9650 && sh_legitimate_index_p (mode, xop1))
9653 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9654 || ((xop0 == stack_pointer_rtx
9655 || xop0 == hard_frame_pointer_rtx)
9656 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9657 || ((xop1 == stack_pointer_rtx
9658 || xop1 == hard_frame_pointer_rtx)
9659 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9660 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9661 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9662 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9663 && TARGET_FMOVD && mode == DFmode)))
9665 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9666 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9668 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9669 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9677 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9678 isn't protected by a PIC unspec. */
9680 nonpic_symbol_mentioned_p (rtx x)
9682 register const char *fmt;
9685 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9686 || GET_CODE (x) == PC)
9689 /* We don't want to look into the possible MEM location of a
9690 CONST_DOUBLE, since we're not going to use it, in general. */
9691 if (GET_CODE (x) == CONST_DOUBLE)
9694 if (GET_CODE (x) == UNSPEC
9695 && (XINT (x, 1) == UNSPEC_PIC
9696 || XINT (x, 1) == UNSPEC_GOT
9697 || XINT (x, 1) == UNSPEC_GOTOFF
9698 || XINT (x, 1) == UNSPEC_GOTPLT
9699 || XINT (x, 1) == UNSPEC_GOTTPOFF
9700 || XINT (x, 1) == UNSPEC_DTPOFF
9701 || XINT (x, 1) == UNSPEC_TPOFF
9702 || XINT (x, 1) == UNSPEC_PLT
9703 || XINT (x, 1) == UNSPEC_SYMOFF
9704 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9707 fmt = GET_RTX_FORMAT (GET_CODE (x));
9708 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9714 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9715 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9718 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9725 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9726 @GOTOFF in `reg'. */
9728 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9731 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9734 if (GET_CODE (orig) == LABEL_REF
9735 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9738 reg = gen_reg_rtx (Pmode);
9740 emit_insn (gen_symGOTOFF2reg (reg, orig));
9743 else if (GET_CODE (orig) == SYMBOL_REF)
9746 reg = gen_reg_rtx (Pmode);
9748 emit_insn (gen_symGOT2reg (reg, orig));
9754 /* Try machine-dependent ways of modifying an illegitimate address
9755 to be legitimate. If we find one, return the new, valid address.
9756 Otherwise, return X.
9758 For the SH, if X is almost suitable for indexing, but the offset is
9759 out of range, convert it into a normal form so that CSE has a chance
9760 of reducing the number of address registers used. */
9763 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9766 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9768 if (GET_CODE (x) == PLUS
9769 && (GET_MODE_SIZE (mode) == 4
9770 || GET_MODE_SIZE (mode) == 8)
9771 && CONST_INT_P (XEXP (x, 1))
9772 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9774 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9775 && ! (TARGET_SH2E && mode == SFmode))
9777 rtx index_rtx = XEXP (x, 1);
9778 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9781 /* On rare occasions, we might get an unaligned pointer
9782 that is indexed in a way to give an aligned address.
9783 Therefore, keep the lower two bits in offset_base. */
9784 /* Instead of offset_base 128..131 use 124..127, so that
9785 simple add suffices. */
9787 offset_base = ((offset + 4) & ~60) - 4;
9789 offset_base = offset & ~60;
9791 /* Sometimes the normal form does not suit DImode. We
9792 could avoid that by using smaller ranges, but that
9793 would give less optimized code when SImode is
9795 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9797 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9798 GEN_INT (offset_base), NULL_RTX, 0,
9801 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9808 /* Attempt to replace *P, which is an address that needs reloading, with
9809 a valid memory address for an operand of mode MODE.
9810 Like for sh_legitimize_address, for the SH we try to get a normal form
9811 of the address. That will allow inheritance of the address reloads. */
9814 sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
9817 enum reload_type type = (enum reload_type) itype;
9819 if (GET_CODE (*p) == PLUS
9820 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9821 && CONST_INT_P (XEXP (*p, 1))
9822 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)
9824 && ! (TARGET_SH4 && mode == DFmode)
9825 && ! (mode == PSImode && type == RELOAD_FOR_INPUT_ADDRESS)
9826 && (ALLOW_INDEXED_ADDRESS
9827 || XEXP (*p, 0) == stack_pointer_rtx
9828 || XEXP (*p, 0) == hard_frame_pointer_rtx))
9830 rtx index_rtx = XEXP (*p, 1);
9831 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9834 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9836 push_reload (*p, NULL_RTX, p, NULL,
9837 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9840 if (TARGET_SH2E && mode == SFmode)
9843 push_reload (*p, NULL_RTX, p, NULL,
9844 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9847 /* Instead of offset_base 128..131 use 124..127, so that
9848 simple add suffices. */
9850 offset_base = ((offset + 4) & ~60) - 4;
9852 offset_base = offset & ~60;
9853 /* Sometimes the normal form does not suit DImode. We could avoid
9854 that by using smaller ranges, but that would give less optimized
9855 code when SImode is prevalent. */
9856 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9858 sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), GEN_INT (offset_base));
9859 *p = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9860 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9861 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9865 /* We must re-recognize what we created before. */
9866 else if (GET_CODE (*p) == PLUS
9867 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9868 && GET_CODE (XEXP (*p, 0)) == PLUS
9869 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
9870 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
9871 && CONST_INT_P (XEXP (*p, 1))
9873 && ! (TARGET_SH2E && mode == SFmode))
9875 /* Because this address is so complex, we know it must have
9876 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9877 it is already unshared, and needs no further unsharing. */
9878 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
9879 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9889 /* In the name of slightly smaller debug output, and to cater to
9890 general assembler lossage, recognize various UNSPEC sequences
9891 and turn them back into a direct symbol reference. */
9894 sh_delegitimize_address (rtx orig_x)
9898 orig_x = delegitimize_mem_from_attrs (orig_x);
9903 if (GET_CODE (x) == CONST)
9906 if (GET_CODE (y) == UNSPEC)
9908 if (XINT (y, 1) == UNSPEC_GOT
9909 || XINT (y, 1) == UNSPEC_GOTOFF
9910 || XINT (y, 1) == UNSPEC_SYMOFF)
9911 return XVECEXP (y, 0, 0);
9912 else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF)
9914 if (GET_CODE (XVECEXP (y, 0, 0)) == CONST)
9916 rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
9918 if (GET_CODE (symplt) == UNSPEC
9919 && XINT (symplt, 1) == UNSPEC_PLT)
9920 return XVECEXP (symplt, 0, 0);
9923 else if (TARGET_SHMEDIA
9924 && (XINT (y, 1) == UNSPEC_EXTRACT_S16
9925 || XINT (y, 1) == UNSPEC_EXTRACT_U16))
9927 rtx offset = XVECEXP (y, 0, 1);
9929 x = gen_rtx_PLUS (Pmode, XVECEXP (y, 0, 0), offset);
9931 x = replace_equiv_address_nv (orig_x, x);
9940 /* Mark the use of a constant in the literal table. If the constant
9941 has multiple labels, make it unique. */
9943 mark_constant_pool_use (rtx x)
9945 rtx insn, lab, pattern;
9950 switch (GET_CODE (x))
9960 /* Get the first label in the list of labels for the same constant
9961 and delete another labels in the list. */
9963 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9966 || LABEL_REFS (insn) != NEXT_INSN (insn))
9971 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9972 INSN_DELETED_P (insn) = 1;
9974 /* Mark constants in a window. */
9975 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9977 if (!NONJUMP_INSN_P (insn))
9980 pattern = PATTERN (insn);
9981 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9984 switch (XINT (pattern, 1))
9986 case UNSPECV_CONST2:
9987 case UNSPECV_CONST4:
9988 case UNSPECV_CONST8:
9989 XVECEXP (pattern, 0, 1) = const1_rtx;
9991 case UNSPECV_WINDOW_END:
9992 if (XVECEXP (pattern, 0, 0) == x)
9995 case UNSPECV_CONST_END:
10005 /* Return true if it's possible to redirect BRANCH1 to the destination
10006 of an unconditional jump BRANCH2. We only want to do this if the
10007 resulting branch will have a short displacement. */
10009 sh_can_redirect_branch (rtx branch1, rtx branch2)
10011 if (flag_expensive_optimizations && simplejump_p (branch2))
10013 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
10017 for (distance = 0, insn = NEXT_INSN (branch1);
10018 insn && distance < 256;
10019 insn = PREV_INSN (insn))
10024 distance += get_attr_length (insn);
10026 for (distance = 0, insn = NEXT_INSN (branch1);
10027 insn && distance < 256;
10028 insn = NEXT_INSN (insn))
10033 distance += get_attr_length (insn);
10039 /* Return nonzero if register old_reg can be renamed to register new_reg. */
10041 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
10042 unsigned int new_reg)
10044 /* Interrupt functions can only use registers that have already been
10045 saved by the prologue, even if they would normally be
10048 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
10054 /* Function to update the integer COST
10055 based on the relationship between INSN that is dependent on
10056 DEP_INSN through the dependence LINK. The default is to make no
10057 adjustment to COST. This can be used for example to specify to
10058 the scheduler that an output- or anti-dependence does not incur
10059 the same cost as a data-dependence. The return value should be
10060 the new value for COST. */
10062 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
10066 if (TARGET_SHMEDIA)
10068 /* On SHmedia, if the dependence is an anti-dependence or
10069 output-dependence, there is no cost. */
10070 if (REG_NOTE_KIND (link) != 0)
10072 /* However, dependencies between target register loads and
10073 uses of the register in a subsequent block that are separated
10074 by a conditional branch are not modelled - we have to do with
10075 the anti-dependency between the target register load and the
10076 conditional branch that ends the current block. */
10077 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
10078 && GET_CODE (PATTERN (dep_insn)) == SET
10079 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
10080 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
10081 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
10083 int orig_cost = cost;
10084 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
10085 rtx target = ((! note
10086 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
10087 ? insn : JUMP_LABEL (insn));
10088 /* On the likely path, the branch costs 1, on the unlikely path,
10092 target = next_active_insn (target);
10093 while (target && ! flow_dependent_p (target, dep_insn)
10095 /* If two branches are executed in immediate succession, with the
10096 first branch properly predicted, this causes a stall at the
10097 second branch, hence we won't need the target for the
10098 second branch for two cycles after the launch of the first
10100 if (cost > orig_cost - 2)
10101 cost = orig_cost - 2;
10107 else if (get_attr_is_mac_media (insn)
10108 && get_attr_is_mac_media (dep_insn))
10111 else if (! reload_completed
10112 && GET_CODE (PATTERN (insn)) == SET
10113 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
10114 && GET_CODE (PATTERN (dep_insn)) == SET
10115 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
10118 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10119 that is needed at the target. */
10120 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
10121 && ! flow_dependent_p (insn, dep_insn))
10124 else if (REG_NOTE_KIND (link) == 0)
10126 enum attr_type type;
10129 if (recog_memoized (insn) < 0
10130 || recog_memoized (dep_insn) < 0)
10133 dep_set = single_set (dep_insn);
10135 /* The latency that we specify in the scheduling description refers
10136 to the actual output, not to an auto-increment register; for that,
10137 the latency is one. */
10138 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
10140 rtx set = single_set (insn);
10143 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
10144 && (!MEM_P (SET_DEST (set))
10145 || !reg_mentioned_p (SET_DEST (dep_set),
10146 XEXP (SET_DEST (set), 0))))
10149 /* The only input for a call that is timing-critical is the
10150 function's address. */
10153 rtx call = PATTERN (insn);
10155 if (GET_CODE (call) == PARALLEL)
10156 call = XVECEXP (call, 0 ,0);
10157 if (GET_CODE (call) == SET)
10158 call = SET_SRC (call);
10159 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
10160 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10161 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
10162 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
10163 cost -= TARGET_SH4_300 ? 3 : 6;
10165 /* Likewise, the most timing critical input for an sfuncs call
10166 is the function address. However, sfuncs typically start
10167 using their arguments pretty quickly.
10168 Assume a four cycle delay for SH4 before they are needed.
10169 Cached ST40-300 calls are quicker, so assume only a one
10171 ??? Maybe we should encode the delays till input registers
10172 are needed by sfuncs into the sfunc call insn. */
10173 /* All sfunc calls are parallels with at least four components.
10174 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10175 else if (GET_CODE (PATTERN (insn)) == PARALLEL
10176 && XVECLEN (PATTERN (insn), 0) >= 4
10177 && (reg = sfunc_uses_reg (insn)))
10179 if (! reg_set_p (reg, dep_insn))
10180 cost -= TARGET_SH4_300 ? 1 : 4;
10182 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
10184 enum attr_type dep_type = get_attr_type (dep_insn);
10186 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
10188 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
10189 && (type = get_attr_type (insn)) != TYPE_CALL
10190 && type != TYPE_SFUNC)
10192 /* When the preceding instruction loads the shift amount of
10193 the following SHAD/SHLD, the latency of the load is increased
10195 if (get_attr_type (insn) == TYPE_DYN_SHIFT
10196 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
10197 && reg_overlap_mentioned_p (SET_DEST (dep_set),
10198 XEXP (SET_SRC (single_set (insn)),
10201 /* When an LS group instruction with a latency of less than
10202 3 cycles is followed by a double-precision floating-point
10203 instruction, FIPR, or FTRV, the latency of the first
10204 instruction is increased to 3 cycles. */
10206 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
10207 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
10209 /* The lsw register of a double-precision computation is ready one
10211 else if (reload_completed
10212 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
10213 && (use_pat = single_set (insn))
10214 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
10215 SET_SRC (use_pat)))
10218 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
10219 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
10222 else if (TARGET_SH4_300)
10224 /* Stores need their input register two cycles later. */
10225 if (dep_set && cost >= 1
10226 && ((type = get_attr_type (insn)) == TYPE_STORE
10227 || type == TYPE_PSTORE
10228 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
10230 rtx set = single_set (insn);
10232 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
10233 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
10236 /* But don't reduce the cost below 1 if the address depends
10237 on a side effect of dep_insn. */
10239 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
10245 /* An anti-dependence penalty of two applies if the first insn is a double
10246 precision fadd / fsub / fmul. */
10247 else if (!TARGET_SH4_300
10248 && REG_NOTE_KIND (link) == REG_DEP_ANTI
10249 && recog_memoized (dep_insn) >= 0
10250 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
10251 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
10252 /* A lot of alleged anti-flow dependences are fake,
10253 so check this one is real. */
10254 && flow_dependent_p (dep_insn, insn))
10260 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10261 if DEP_INSN is anti-flow dependent on INSN. */
10263 flow_dependent_p (rtx insn, rtx dep_insn)
10265 rtx tmp = PATTERN (insn);
10267 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
10268 return tmp == NULL_RTX;
10271 /* A helper function for flow_dependent_p called through note_stores. */
10273 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
10275 rtx * pinsn = (rtx *) data;
10277 if (*pinsn && reg_referenced_p (x, *pinsn))
10281 /* For use by sh_allocate_initial_value. Note that sh.md contains some
10282 'special function' patterns (type sfunc) that clobber pr, but that
10283 do not look like function calls to leaf_function_p. Hence we must
10284 do this extra check. */
10286 sh_pr_n_sets (void)
10288 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10291 /* Return where to allocate pseudo for a given hard register initial
10294 sh_allocate_initial_value (rtx hard_reg)
10298 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
10300 if (current_function_is_leaf
10301 && ! sh_pr_n_sets ()
10302 && ! (TARGET_SHCOMPACT
10303 && ((crtl->args.info.call_cookie
10304 & ~ CALL_COOKIE_RET_TRAMP (1))
10305 || crtl->saves_all_registers)))
10308 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
10316 /* This function returns "2" to indicate dual issue for the SH4
10317 processor. To be used by the DFA pipeline description. */
10319 sh_issue_rate (void)
10321 if (TARGET_SUPERSCALAR)
10327 /* Functions for ready queue reordering for sched1. */
10329 /* Get weight for mode for a set x. */
10331 find_set_regmode_weight (rtx x, enum machine_mode mode)
10333 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
10335 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
10337 if (REG_P (SET_DEST (x)))
10339 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
10349 /* Get regmode weight for insn. */
10351 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
10353 short reg_weight = 0;
10356 /* Increment weight for each register born here. */
10357 x = PATTERN (insn);
10358 reg_weight += find_set_regmode_weight (x, mode);
10359 if (GET_CODE (x) == PARALLEL)
10362 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
10364 x = XVECEXP (PATTERN (insn), 0, j);
10365 reg_weight += find_set_regmode_weight (x, mode);
10368 /* Decrement weight for each register that dies here. */
10369 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
10371 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
10373 rtx note = XEXP (x, 0);
10374 if (REG_P (note) && GET_MODE (note) == mode)
10381 /* Calculate regmode weights for all insns of a basic block. */
10383 find_regmode_weight (basic_block b, enum machine_mode mode)
10385 rtx insn, next_tail, head, tail;
10387 get_ebb_head_tail (b, b, &head, &tail);
10388 next_tail = NEXT_INSN (tail);
10390 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
10392 /* Handle register life information. */
10393 if (!INSN_P (insn))
10396 if (mode == SFmode)
10397 INSN_REGMODE_WEIGHT (insn, mode) =
10398 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
10399 else if (mode == SImode)
10400 INSN_REGMODE_WEIGHT (insn, mode) =
10401 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
10405 /* Comparison function for ready queue sorting. */
10407 rank_for_reorder (const void *x, const void *y)
10409 rtx tmp = *(const rtx *) y;
10410 rtx tmp2 = *(const rtx *) x;
10412 /* The insn in a schedule group should be issued the first. */
10413 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10414 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10416 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10417 minimizes instruction movement, thus minimizing sched's effect on
10418 register pressure. */
10419 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10422 /* Resort the array A in which only element at index N may be out of order. */
10424 swap_reorder (rtx *a, int n)
10426 rtx insn = a[n - 1];
10429 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10437 #define SCHED_REORDER(READY, N_READY) \
10440 if ((N_READY) == 2) \
10441 swap_reorder (READY, N_READY); \
10442 else if ((N_READY) > 2) \
10443 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10447 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10450 ready_reorder (rtx *ready, int nready)
10452 SCHED_REORDER (ready, nready);
10455 /* Count life regions of r0 for a block. */
10457 find_r0_life_regions (basic_block b)
10466 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10477 insn = BB_HEAD (b);
10479 r0_reg = gen_rtx_REG (SImode, R0_REG);
10484 if (find_regno_note (insn, REG_DEAD, R0_REG))
10490 && (pset = single_set (insn))
10491 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10492 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10500 insn = NEXT_INSN (insn);
10502 return set - death;
10505 /* Calculate regmode weights for all insns of all basic block. */
10507 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10508 int verbose ATTRIBUTE_UNUSED,
10513 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10514 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10515 r0_life_regions = 0;
10517 FOR_EACH_BB_REVERSE (b)
10519 find_regmode_weight (b, SImode);
10520 find_regmode_weight (b, SFmode);
10521 if (!reload_completed)
10522 r0_life_regions += find_r0_life_regions (b);
10525 CURR_REGMODE_PRESSURE (SImode) = 0;
10526 CURR_REGMODE_PRESSURE (SFmode) = 0;
10532 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10533 int verbose ATTRIBUTE_UNUSED)
10535 if (regmode_weight[0])
10537 free (regmode_weight[0]);
10538 regmode_weight[0] = NULL;
10540 if (regmode_weight[1])
10542 free (regmode_weight[1]);
10543 regmode_weight[1] = NULL;
10547 /* The scalar modes supported differs from the default version in TImode
10548 for 32-bit SHMEDIA. */
10550 sh_scalar_mode_supported_p (enum machine_mode mode)
10552 if (TARGET_SHMEDIA32 && mode == TImode)
10555 return default_scalar_mode_supported_p (mode);
10558 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10559 keep count of register pressures on SImode and SFmode. */
10561 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10562 int sched_verbose ATTRIBUTE_UNUSED,
10564 int can_issue_more)
10566 if (GET_CODE (PATTERN (insn)) != USE
10567 && GET_CODE (PATTERN (insn)) != CLOBBER)
10568 cached_can_issue_more = can_issue_more - 1;
10570 cached_can_issue_more = can_issue_more;
10572 if (reload_completed)
10573 return cached_can_issue_more;
10575 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10576 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10578 return cached_can_issue_more;
10582 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10583 int verbose ATTRIBUTE_UNUSED,
10584 int veclen ATTRIBUTE_UNUSED)
10586 CURR_REGMODE_PRESSURE (SImode) = 0;
10587 CURR_REGMODE_PRESSURE (SFmode) = 0;
10590 /* Some magic numbers. */
10591 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10592 functions that already have high pressure on r0. */
10593 #define R0_MAX_LIFE_REGIONS 2
10594 /* Register Pressure thresholds for SImode and SFmode registers. */
10595 #define SIMODE_MAX_WEIGHT 5
10596 #define SFMODE_MAX_WEIGHT 10
10598 /* Return true if the pressure is high for MODE. */
10600 high_pressure (enum machine_mode mode)
10602 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10603 functions that already have high pressure on r0. */
10604 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10607 if (mode == SFmode)
10608 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10610 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10613 /* Reorder ready queue if register pressure is high. */
10615 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10616 int sched_verbose ATTRIBUTE_UNUSED,
10619 int clock_var ATTRIBUTE_UNUSED)
10621 if (reload_completed)
10622 return sh_issue_rate ();
10624 if (high_pressure (SFmode) || high_pressure (SImode))
10626 ready_reorder (ready, *n_readyp);
10629 return sh_issue_rate ();
10632 /* Skip cycles if the current register pressure is high. */
10634 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10635 int sched_verbose ATTRIBUTE_UNUSED,
10636 rtx *ready ATTRIBUTE_UNUSED,
10637 int *n_readyp ATTRIBUTE_UNUSED,
10638 int clock_var ATTRIBUTE_UNUSED)
10640 if (reload_completed)
10641 return cached_can_issue_more;
10643 if (high_pressure(SFmode) || high_pressure (SImode))
10646 return cached_can_issue_more;
10649 /* Skip cycles without sorting the ready queue. This will move insn from
10650 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10651 queue by sh_reorder. */
10653 /* Generally, skipping these many cycles are sufficient for all insns to move
10655 #define MAX_SKIPS 8
10658 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10659 int sched_verbose ATTRIBUTE_UNUSED,
10660 rtx insn ATTRIBUTE_UNUSED,
10661 int last_clock_var,
10665 if (reload_completed)
10670 if ((clock_var - last_clock_var) < MAX_SKIPS)
10675 /* If this is the last cycle we are skipping, allow reordering of R. */
10676 if ((clock_var - last_clock_var) == MAX_SKIPS)
10688 /* SHmedia requires registers for branches, so we can't generate new
10689 branches past reload. */
10691 sh_cannot_modify_jumps_p (void)
10693 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10697 sh_target_reg_class (void)
10699 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10703 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10705 HARD_REG_SET dummy;
10710 if (! shmedia_space_reserved_for_target_registers)
10712 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10714 if (calc_live_regs (&dummy) >= 6 * 8)
10720 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10722 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10726 On the SH1..SH4, the trampoline looks like
10727 2 0002 D202 mov.l l2,r2
10728 1 0000 D301 mov.l l1,r3
10729 3 0004 422B jmp @r2
10731 5 0008 00000000 l1: .long area
10732 6 000c 00000000 l2: .long function
10734 SH5 (compact) uses r1 instead of r3 for the static chain. */
10737 /* Emit RTL insns to initialize the variable parts of a trampoline.
10738 FNADDR is an RTX for the address of the function's pure code.
10739 CXT is an RTX for the static chain value for the function. */
10742 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10744 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10745 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10747 if (TARGET_SHMEDIA64)
10752 rtx movi1 = GEN_INT (0xcc000010);
10753 rtx shori1 = GEN_INT (0xc8000010);
10756 /* The following trampoline works within a +- 128 KB range for cxt:
10757 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10758 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10759 gettr tr1,r1; blink tr0,r63 */
10760 /* Address rounding makes it hard to compute the exact bounds of the
10761 offset for this trampoline, but we have a rather generous offset
10762 range, so frame_offset should do fine as an upper bound. */
10763 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10765 /* ??? could optimize this trampoline initialization
10766 by writing DImode words with two insns each. */
10767 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10768 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10769 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10770 insn = gen_rtx_AND (DImode, insn, mask);
10771 /* Or in ptb/u .,tr1 pattern */
10772 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10773 insn = force_operand (insn, NULL_RTX);
10774 insn = gen_lowpart (SImode, insn);
10775 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10776 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10777 insn = gen_rtx_AND (DImode, insn, mask);
10778 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10779 insn = gen_lowpart (SImode, insn);
10780 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10781 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10782 insn = gen_rtx_AND (DImode, insn, mask);
10783 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10784 insn = gen_lowpart (SImode, insn);
10785 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10786 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10787 insn = gen_rtx_AND (DImode, insn, mask);
10788 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10789 insn = gen_lowpart (SImode, insn);
10790 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10791 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10792 insn = gen_rtx_AND (DImode, insn, mask);
10793 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10794 insn = gen_lowpart (SImode, insn);
10795 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10796 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10797 GEN_INT (0x6bf10600));
10798 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10799 GEN_INT (0x4415fc10));
10800 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10801 GEN_INT (0x4401fff0));
10802 emit_insn (gen_ic_invalidate_line (tramp));
10805 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10806 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10808 tramp_templ = gen_datalabel_ref (tramp_templ);
10810 src = gen_const_mem (BLKmode, tramp_templ);
10811 set_mem_align (dst, 256);
10812 set_mem_align (src, 64);
10813 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10815 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10816 emit_move_insn (adjust_address (tramp_mem, Pmode,
10817 fixed_len + GET_MODE_SIZE (Pmode)),
10819 emit_insn (gen_ic_invalidate_line (tramp));
10822 else if (TARGET_SHMEDIA)
10824 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10825 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10826 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10827 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10828 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10829 rotated 10 right, and higher 16 bit of every 32 selected. */
10831 = force_reg (V2HImode, (simplify_gen_subreg
10832 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10833 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10834 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10836 fnaddr = force_reg (SImode, fnaddr);
10837 cxt = force_reg (SImode, cxt);
10838 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10839 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10841 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10842 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10843 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10844 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10845 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10846 gen_rtx_SUBREG (V2HImode, cxt, 0),
10848 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10849 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10850 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10851 if (TARGET_LITTLE_ENDIAN)
10853 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10854 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10858 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10859 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10861 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10862 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10863 emit_insn (gen_ic_invalidate_line (tramp));
10866 else if (TARGET_SHCOMPACT)
10868 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10871 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10872 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10874 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10875 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10877 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10878 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10879 if (TARGET_HARVARD)
10881 if (!TARGET_INLINE_IC_INVALIDATE
10882 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10883 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10884 FUNCTION_ORDINARY),
10885 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10887 emit_insn (gen_ic_invalidate_line (tramp));
10891 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10894 sh_trampoline_adjust_address (rtx tramp)
10896 if (TARGET_SHMEDIA)
10897 tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx,
10898 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN);
10902 /* FIXME: This is overly conservative. A SHcompact function that
10903 receives arguments ``by reference'' will have them stored in its
10904 own stack frame, so it must not pass pointers or references to
10905 these arguments to other functions by means of sibling calls. */
10906 /* If PIC, we cannot make sibling calls to global functions
10907 because the PLT requires r12 to be live. */
10909 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10912 && (! TARGET_SHCOMPACT
10913 || crtl->args.info.stack_regs == 0)
10914 && ! sh_cfun_interrupt_handler_p ()
10916 || (decl && ! TREE_PUBLIC (decl))
10917 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10920 /* Machine specific built-in functions. */
10922 struct builtin_description
10924 const enum insn_code icode;
10925 const char *const name;
10930 /* describe number and signedness of arguments; arg[0] == result
10931 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10932 /* 9: 64-bit pointer, 10: 32-bit pointer */
10933 static const char signature_args[][4] =
10935 #define SH_BLTIN_V2SI2 0
10937 #define SH_BLTIN_V4HI2 1
10939 #define SH_BLTIN_V2SI3 2
10941 #define SH_BLTIN_V4HI3 3
10943 #define SH_BLTIN_V8QI3 4
10945 #define SH_BLTIN_MAC_HISI 5
10947 #define SH_BLTIN_SH_HI 6
10949 #define SH_BLTIN_SH_SI 7
10951 #define SH_BLTIN_V4HI2V2SI 8
10953 #define SH_BLTIN_V4HI2V8QI 9
10955 #define SH_BLTIN_SISF 10
10957 #define SH_BLTIN_LDUA_L 11
10959 #define SH_BLTIN_LDUA_Q 12
10961 #define SH_BLTIN_STUA_L 13
10963 #define SH_BLTIN_STUA_Q 14
10965 #define SH_BLTIN_LDUA_L64 15
10967 #define SH_BLTIN_LDUA_Q64 16
10969 #define SH_BLTIN_STUA_L64 17
10971 #define SH_BLTIN_STUA_Q64 18
10973 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10974 #define SH_BLTIN_2 19
10975 #define SH_BLTIN_SU 19
10977 #define SH_BLTIN_3 20
10978 #define SH_BLTIN_SUS 20
10980 #define SH_BLTIN_PSSV 21
10982 #define SH_BLTIN_XXUU 22
10983 #define SH_BLTIN_UUUU 22
10985 #define SH_BLTIN_PV 23
10988 /* mcmv: operands considered unsigned. */
10989 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10990 /* mperm: control value considered unsigned int. */
10991 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10992 /* mshards_q: returns signed short. */
10993 /* nsb: takes long long arg, returns unsigned char. */
10994 static struct builtin_description bdesc[] =
10996 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 },
10997 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 },
10998 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 },
10999 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 },
11000 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 },
11001 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 },
11002 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 },
11003 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 },
11004 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 },
11005 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 },
11006 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 },
11007 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 },
11008 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 },
11009 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 },
11010 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 },
11011 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 },
11012 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 },
11013 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 },
11014 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 },
11015 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 },
11016 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 },
11017 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 },
11018 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 },
11019 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 },
11020 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 },
11021 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 },
11022 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 },
11023 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 },
11024 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 },
11025 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 },
11026 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 },
11027 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 },
11028 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 },
11029 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 },
11030 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 },
11031 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 },
11032 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 },
11033 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 },
11034 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 },
11035 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 },
11036 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 },
11037 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 },
11038 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 },
11039 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 },
11040 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 },
11041 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 },
11042 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 },
11043 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 },
11044 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 },
11045 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 },
11046 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 },
11047 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 },
11048 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 },
11049 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 },
11050 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 },
11051 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 },
11052 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 },
11053 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 },
11054 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 },
11055 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 },
11056 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 },
11057 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3, 0 },
11058 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 },
11059 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 },
11060 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 },
11061 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 },
11062 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 },
11063 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 },
11064 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 },
11065 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 },
11066 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 },
11067 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 },
11068 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 },
11069 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 },
11070 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 },
11071 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 },
11072 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 },
11073 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 },
11074 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 },
11075 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 },
11076 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 },
11077 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 },
11078 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 },
11079 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 },
11083 sh_media_init_builtins (void)
11085 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
11086 struct builtin_description *d;
11088 memset (shared, 0, sizeof shared);
11089 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
11091 tree type, arg_type = 0;
11092 int signature = d->signature;
11095 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
11096 type = shared[signature];
11099 int has_result = signature_args[signature][0] != 0;
11102 if ((signature_args[signature][1] & 8)
11103 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
11104 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
11106 if (! TARGET_FPU_ANY
11107 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
11109 for (i = 0; i < (int) ARRAY_SIZE (args); i++)
11110 args[i] = NULL_TREE;
11113 int arg = signature_args[signature][i];
11114 int opno = i - 1 + has_result;
11117 arg_type = ptr_type_node;
11119 arg_type = (*lang_hooks.types.type_for_mode)
11120 (insn_data[d->icode].operand[opno].mode,
11125 arg_type = void_type_node;
11128 args[i-1] = arg_type;
11130 type = build_function_type_list (arg_type, args[0], args[1],
11131 args[2], NULL_TREE);
11132 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
11133 shared[signature] = type;
11136 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
11141 /* Returns the shmedia builtin decl for CODE. */
11144 sh_media_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11146 if (code >= ARRAY_SIZE (bdesc))
11147 return error_mark_node;
11149 return bdesc[code].fndecl;
11152 /* Implements target hook vector_mode_supported_p. */
11154 sh_vector_mode_supported_p (enum machine_mode mode)
11157 && ((mode == V2SFmode)
11158 || (mode == V4SFmode)
11159 || (mode == V16SFmode)))
11162 else if (TARGET_SHMEDIA
11163 && ((mode == V8QImode)
11164 || (mode == V2HImode)
11165 || (mode == V4HImode)
11166 || (mode == V2SImode)))
11173 sh_frame_pointer_required (void)
11175 /* If needed override this in other tm.h files to cope with various OS
11176 lossage requiring a frame pointer. */
11177 if (SUBTARGET_FRAME_POINTER_REQUIRED)
11186 /* Implements target hook dwarf_calling_convention. Return an enum
11187 of dwarf_calling_convention. */
11189 sh_dwarf_calling_convention (const_tree func)
11191 if (sh_attr_renesas_p (func))
11192 return DW_CC_GNU_renesas_sh;
11194 return DW_CC_normal;
11198 sh_init_builtins (void)
11200 if (TARGET_SHMEDIA)
11201 sh_media_init_builtins ();
11204 /* Returns the sh builtin decl for CODE. */
11207 sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11209 if (TARGET_SHMEDIA)
11210 return sh_media_builtin_decl (code, initialize_p);
11212 return error_mark_node;
11215 /* Expand an expression EXP that calls a built-in function,
11216 with result going to TARGET if that's convenient
11217 (and in mode MODE if that's convenient).
11218 SUBTARGET may be used as the target for computing one of EXP's operands.
11219 IGNORE is nonzero if the value is to be ignored. */
11222 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11223 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
11225 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11226 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
11227 const struct builtin_description *d = &bdesc[fcode];
11228 enum insn_code icode = d->icode;
11229 int signature = d->signature;
11230 enum machine_mode tmode = VOIDmode;
11235 if (signature_args[signature][0])
11240 tmode = insn_data[icode].operand[0].mode;
11242 || GET_MODE (target) != tmode
11243 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11244 target = gen_reg_rtx (tmode);
11245 op[nop++] = target;
11250 for (i = 1; i <= 3; i++, nop++)
11253 enum machine_mode opmode, argmode;
11256 if (! signature_args[signature][i])
11258 arg = CALL_EXPR_ARG (exp, i - 1);
11259 if (arg == error_mark_node)
11261 if (signature_args[signature][i] & 8)
11264 optype = ptr_type_node;
11268 opmode = insn_data[icode].operand[nop].mode;
11269 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
11271 argmode = TYPE_MODE (TREE_TYPE (arg));
11272 if (argmode != opmode)
11273 arg = build1 (NOP_EXPR, optype, arg);
11274 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
11275 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
11276 op[nop] = copy_to_mode_reg (opmode, op[nop]);
11282 pat = (*insn_data[d->icode].genfun) (op[0]);
11285 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
11288 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
11291 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
11294 gcc_unreachable ();
11303 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
11305 rtx sel0 = const0_rtx;
11306 rtx sel1 = const1_rtx;
11307 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
11308 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
11310 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
11311 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
11315 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
11317 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
11319 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
11320 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
11323 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
11324 We can allow any mode in any general register. The special registers
11325 only allow SImode. Don't allow any mode in the PR.
11327 We cannot hold DCmode values in the XD registers because alter_reg
11328 handles subregs of them incorrectly. We could work around this by
11329 spacing the XD registers like the DR registers, but this would require
11330 additional memory in every compilation to hold larger register vectors.
11331 We could hold SFmode / SCmode values in XD registers, but that
11332 would require a tertiary reload when reloading from / to memory,
11333 and a secondary reload to reload from / to general regs; that
11334 seems to be a loosing proposition.
11336 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
11337 it won't be ferried through GP registers first. */
11340 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11342 if (SPECIAL_REGISTER_P (regno))
11343 return mode == SImode;
11345 if (regno == FPUL_REG)
11346 return (mode == SImode || mode == SFmode);
11348 if (FP_REGISTER_P (regno) && mode == SFmode)
11351 if (mode == V2SFmode)
11353 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
11354 || GENERAL_REGISTER_P (regno)))
11360 if (mode == V4SFmode)
11362 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
11363 || GENERAL_REGISTER_P (regno))
11369 if (mode == V16SFmode)
11371 if (TARGET_SHMEDIA)
11373 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
11379 return regno == FIRST_XD_REG;
11382 if (FP_REGISTER_P (regno))
11386 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
11387 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
11390 && (mode == DFmode || mode == DImode
11391 || mode == V2SFmode || mode == TImode)))
11392 && ((regno - FIRST_FP_REG) & 1) == 0)
11393 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
11394 && ((regno - FIRST_FP_REG) & 3) == 0))
11400 if (XD_REGISTER_P (regno))
11401 return mode == DFmode;
11403 if (TARGET_REGISTER_P (regno))
11404 return (mode == DImode || mode == SImode || mode == PDImode);
11406 if (regno == PR_REG)
11407 return mode == SImode;
11409 if (regno == FPSCR_REG)
11410 return mode == PSImode;
11412 /* FIXME. This works around PR target/37633 for -O0. */
11413 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
11415 unsigned int n = GET_MODE_SIZE (mode) / 8;
11417 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
11418 && regno <= FIRST_GENERAL_REG + 14)
11425 /* Return the class of registers for which a mode change from FROM to TO
11428 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
11429 enum reg_class rclass)
11431 /* We want to enable the use of SUBREGs as a means to
11432 VEC_SELECT a single element of a vector. */
11433 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
11434 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
11436 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
11438 if (TARGET_LITTLE_ENDIAN)
11440 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
11441 return reg_classes_intersect_p (DF_REGS, rclass);
11445 if (GET_MODE_SIZE (from) < 8)
11446 return reg_classes_intersect_p (DF_HI_REGS, rclass);
11452 /* Return true if registers in machine mode MODE will likely be
11453 allocated to registers in small register classes. */
11456 sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
11458 return (! TARGET_SHMEDIA);
11461 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11462 that label is used. */
11465 sh_mark_label (rtx address, int nuses)
11467 if (GOTOFF_P (address))
11469 /* Extract the label or symbol. */
11470 address = XEXP (address, 0);
11471 if (GET_CODE (address) == PLUS)
11472 address = XEXP (address, 0);
11473 address = XVECEXP (address, 0, 0);
11475 if (GET_CODE (address) == LABEL_REF
11476 && LABEL_P (XEXP (address, 0)))
11477 LABEL_NUSES (XEXP (address, 0)) += nuses;
11480 /* Compute extra cost of moving data between one register class
11483 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11484 uses this information. Hence, the general register <-> floating point
11485 register information here is not used for SFmode. */
11488 sh_register_move_cost (enum machine_mode mode,
11489 reg_class_t srcclass, reg_class_t dstclass)
11491 if (dstclass == T_REGS || dstclass == PR_REGS)
11494 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11497 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11498 && REGCLASS_HAS_FP_REG (srcclass)
11499 && REGCLASS_HAS_FP_REG (dstclass))
11502 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11503 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11505 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11506 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11509 if ((REGCLASS_HAS_FP_REG (dstclass)
11510 && REGCLASS_HAS_GENERAL_REG (srcclass))
11511 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11512 && REGCLASS_HAS_FP_REG (srcclass)))
11514 /* Discourage trying to use fp regs for a pointer. This also
11515 discourages fp regs with SImode because Pmode is an alias
11516 of SImode on this target. See PR target/48596. */
11517 int addend = (mode == Pmode) ? 40 : 0;
11519 return (((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12) + addend)
11520 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11523 if ((dstclass == FPUL_REGS
11524 && REGCLASS_HAS_GENERAL_REG (srcclass))
11525 || (srcclass == FPUL_REGS
11526 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11529 if ((dstclass == FPUL_REGS
11530 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11531 || (srcclass == FPUL_REGS
11532 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11535 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11536 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11539 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11541 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11543 if (sh_gettrcost >= 0)
11544 return sh_gettrcost;
11545 else if (!TARGET_PT_FIXED)
11549 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11550 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11555 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11556 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11557 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11559 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11562 static rtx emit_load_ptr (rtx, rtx);
11565 emit_load_ptr (rtx reg, rtx addr)
11567 rtx mem = gen_const_mem (ptr_mode, addr);
11569 if (Pmode != ptr_mode)
11570 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11571 return emit_move_insn (reg, mem);
11575 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11576 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11579 CUMULATIVE_ARGS cum;
11580 int structure_value_byref = 0;
11581 rtx this_rtx, this_value, sibcall, insns, funexp;
11582 tree funtype = TREE_TYPE (function);
11583 int simple_add = CONST_OK_FOR_ADD (delta);
11585 rtx scratch0, scratch1, scratch2;
11588 reload_completed = 1;
11589 epilogue_completed = 1;
11590 current_function_uses_only_leaf_regs = 1;
11592 emit_note (NOTE_INSN_PROLOGUE_END);
11594 /* Find the "this" pointer. We have such a wide range of ABIs for the
11595 SH that it's best to do this completely machine independently.
11596 "this" is passed as first argument, unless a structure return pointer
11597 comes first, in which case "this" comes second. */
11598 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11599 #ifndef PCC_STATIC_STRUCT_RETURN
11600 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11601 structure_value_byref = 1;
11602 #endif /* not PCC_STATIC_STRUCT_RETURN */
11603 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11605 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11607 sh_function_arg_advance (pack_cumulative_args (&cum), Pmode, ptype, true);
11610 = sh_function_arg (pack_cumulative_args (&cum), Pmode, ptr_type_node, true);
11612 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11613 static chain pointer (even if you can't have nested virtual functions
11614 right now, someone might implement them sometime), and the rest of the
11615 registers are used for argument passing, are callee-saved, or reserved. */
11616 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11617 -ffixed-reg has been used. */
11618 if (! call_used_regs[0] || fixed_regs[0])
11619 error ("r0 needs to be available as a call-clobbered register");
11620 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11623 if (call_used_regs[1] && ! fixed_regs[1])
11624 scratch1 = gen_rtx_REG (ptr_mode, 1);
11625 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11626 pointing where to return struct values. */
11627 if (call_used_regs[3] && ! fixed_regs[3])
11628 scratch2 = gen_rtx_REG (Pmode, 3);
11630 else if (TARGET_SHMEDIA)
11632 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11633 if (i != REGNO (scratch0) &&
11634 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11636 scratch1 = gen_rtx_REG (ptr_mode, i);
11639 if (scratch1 == scratch0)
11640 error ("need a second call-clobbered general purpose register");
11641 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11642 if (call_used_regs[i] && ! fixed_regs[i])
11644 scratch2 = gen_rtx_REG (Pmode, i);
11647 if (scratch2 == scratch0)
11648 error ("need a call-clobbered target register");
11651 this_value = plus_constant (this_rtx, delta);
11653 && (simple_add || scratch0 != scratch1)
11654 && strict_memory_address_p (ptr_mode, this_value))
11656 emit_load_ptr (scratch0, this_value);
11661 ; /* Do nothing. */
11662 else if (simple_add)
11663 emit_move_insn (this_rtx, this_value);
11666 emit_move_insn (scratch1, GEN_INT (delta));
11667 emit_insn (gen_add2_insn (this_rtx, scratch1));
11675 emit_load_ptr (scratch0, this_rtx);
11677 offset_addr = plus_constant (scratch0, vcall_offset);
11678 if (strict_memory_address_p (ptr_mode, offset_addr))
11679 ; /* Do nothing. */
11680 else if (! TARGET_SH5 && scratch0 != scratch1)
11682 /* scratch0 != scratch1, and we have indexed loads. Get better
11683 schedule by loading the offset into r1 and using an indexed
11684 load - then the load of r1 can issue before the load from
11685 (this_rtx + delta) finishes. */
11686 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11687 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11689 else if (CONST_OK_FOR_ADD (vcall_offset))
11691 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11692 offset_addr = scratch0;
11694 else if (scratch0 != scratch1)
11696 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11697 emit_insn (gen_add2_insn (scratch0, scratch1));
11698 offset_addr = scratch0;
11701 gcc_unreachable (); /* FIXME */
11702 emit_load_ptr (scratch0, offset_addr);
11704 if (Pmode != ptr_mode)
11705 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11706 emit_insn (gen_add2_insn (this_rtx, scratch0));
11709 /* Generate a tail call to the target function. */
11710 if (! TREE_USED (function))
11712 assemble_external (function);
11713 TREE_USED (function) = 1;
11715 funexp = XEXP (DECL_RTL (function), 0);
11716 /* If the function is overridden, so is the thunk, hence we don't
11717 need GOT addressing even if this is a public symbol. */
11719 if (TARGET_SH1 && ! flag_weak)
11720 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11723 if (TARGET_SH2 && flag_pic)
11725 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11726 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11730 if (TARGET_SHMEDIA && flag_pic)
11732 funexp = gen_sym2PIC (funexp);
11733 PUT_MODE (funexp, Pmode);
11735 emit_move_insn (scratch2, funexp);
11736 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11737 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11739 sibcall = emit_call_insn (sibcall);
11740 SIBLING_CALL_P (sibcall) = 1;
11741 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11744 /* Run just enough of rest_of_compilation to do scheduling and get
11745 the insns emitted. Note that use_thunk calls
11746 assemble_start_function and assemble_end_function. */
11748 insn_locators_alloc ();
11749 insns = get_insns ();
11755 split_all_insns_noflow ();
11759 shorten_branches (insns);
11760 final_start_function (insns, file, 1);
11761 final (insns, file, 1);
11762 final_end_function ();
11764 reload_completed = 0;
11765 epilogue_completed = 0;
11769 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11773 /* If this is not an ordinary function, the name usually comes from a
11774 string literal or an sprintf buffer. Make sure we use the same
11775 string consistently, so that cse will be able to unify address loads. */
11776 if (kind != FUNCTION_ORDINARY)
11777 name = IDENTIFIER_POINTER (get_identifier (name));
11778 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11779 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11783 case FUNCTION_ORDINARY:
11787 rtx reg = target ? target : gen_reg_rtx (Pmode);
11789 emit_insn (gen_symGOT2reg (reg, sym));
11795 /* ??? To allow cse to work, we use GOTOFF relocations.
11796 we could add combiner patterns to transform this into
11797 straight pc-relative calls with sym2PIC / bsrf when
11798 label load and function call are still 1:1 and in the
11799 same basic block during combine. */
11800 rtx reg = target ? target : gen_reg_rtx (Pmode);
11802 emit_insn (gen_symGOTOFF2reg (reg, sym));
11807 if (target && sym != target)
11809 emit_move_insn (target, sym);
11815 /* Find the number of a general purpose register in S. */
11817 scavenge_reg (HARD_REG_SET *s)
11820 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11821 if (TEST_HARD_REG_BIT (*s, r))
11827 sh_get_pr_initial_val (void)
11831 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11832 PR register on SHcompact, because it might be clobbered by the prologue.
11833 We check first if that is known to be the case. */
11834 if (TARGET_SHCOMPACT
11835 && ((crtl->args.info.call_cookie
11836 & ~ CALL_COOKIE_RET_TRAMP (1))
11837 || crtl->saves_all_registers))
11838 return gen_frame_mem (SImode, return_address_pointer_rtx);
11840 /* If we haven't finished rtl generation, there might be a nonlocal label
11841 that we haven't seen yet.
11842 ??? get_hard_reg_initial_val fails if it is called after register
11843 allocation has started, unless it has been called before for the
11844 same register. And even then, we end in trouble if we didn't use
11845 the register in the same basic block before. So call
11846 get_hard_reg_initial_val now and wrap it in an unspec if we might
11847 need to replace it. */
11848 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11849 combine can put the pseudo returned by get_hard_reg_initial_val into
11850 instructions that need a general purpose registers, which will fail to
11851 be recognized when the pseudo becomes allocated to PR. */
11853 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11855 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11860 sh_expand_t_scc (rtx operands[])
11862 enum rtx_code code = GET_CODE (operands[1]);
11863 rtx target = operands[0];
11864 rtx op0 = operands[2];
11865 rtx op1 = operands[3];
11866 rtx result = target;
11869 if (!REG_P (op0) || REGNO (op0) != T_REG
11870 || !CONST_INT_P (op1))
11872 if (!REG_P (result))
11873 result = gen_reg_rtx (SImode);
11874 val = INTVAL (op1);
11875 if ((code == EQ && val == 1) || (code == NE && val == 0))
11876 emit_insn (gen_movt (result));
11877 else if (TARGET_SH2A && ((code == EQ && val == 0)
11878 || (code == NE && val == 1)))
11879 emit_insn (gen_xorsi3_movrt (result));
11880 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11882 emit_clobber (result);
11883 emit_insn (gen_subc (result, result, result));
11884 emit_insn (gen_addsi3 (result, result, const1_rtx));
11886 else if (code == EQ || code == NE)
11887 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11890 if (result != target)
11891 emit_move_insn (target, result);
11895 /* INSN is an sfunc; return the rtx that describes the address used. */
11897 extract_sfunc_addr (rtx insn)
11899 rtx pattern, part = NULL_RTX;
11902 pattern = PATTERN (insn);
11903 len = XVECLEN (pattern, 0);
11904 for (i = 0; i < len; i++)
11906 part = XVECEXP (pattern, 0, i);
11907 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11908 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11909 return XEXP (part, 0);
11911 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11912 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11915 /* Verify that the register in use_sfunc_addr still agrees with the address
11916 used in the sfunc. This prevents fill_slots_from_thread from changing
11918 INSN is the use_sfunc_addr instruction, and REG is the register it
11921 check_use_sfunc_addr (rtx insn, rtx reg)
11923 /* Search for the sfunc. It should really come right after INSN. */
11924 while ((insn = NEXT_INSN (insn)))
11926 if (LABEL_P (insn) || JUMP_P (insn))
11928 if (! INSN_P (insn))
11931 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11932 insn = XVECEXP (PATTERN (insn), 0, 0);
11933 if (GET_CODE (PATTERN (insn)) != PARALLEL
11934 || get_attr_type (insn) != TYPE_SFUNC)
11936 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11938 gcc_unreachable ();
11941 /* This function returns a constant rtx that represents pi / 2**15 in
11942 SFmode. it's used to scale SFmode angles, in radians, to a
11943 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11944 maps to 0x10000). */
11946 static GTY(()) rtx sh_fsca_sf2int_rtx;
11949 sh_fsca_sf2int (void)
11951 if (! sh_fsca_sf2int_rtx)
11953 REAL_VALUE_TYPE rv;
11955 real_from_string (&rv, "10430.378350470453");
11956 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11959 return sh_fsca_sf2int_rtx;
11962 /* This function returns a constant rtx that represents pi / 2**15 in
11963 DFmode. it's used to scale DFmode angles, in radians, to a
11964 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11965 maps to 0x10000). */
11967 static GTY(()) rtx sh_fsca_df2int_rtx;
11970 sh_fsca_df2int (void)
11972 if (! sh_fsca_df2int_rtx)
11974 REAL_VALUE_TYPE rv;
11976 real_from_string (&rv, "10430.378350470453");
11977 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11980 return sh_fsca_df2int_rtx;
11983 /* This function returns a constant rtx that represents 2**15 / pi in
11984 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11985 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11988 static GTY(()) rtx sh_fsca_int2sf_rtx;
11991 sh_fsca_int2sf (void)
11993 if (! sh_fsca_int2sf_rtx)
11995 REAL_VALUE_TYPE rv;
11997 real_from_string (&rv, "9.587379924285257e-5");
11998 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
12001 return sh_fsca_int2sf_rtx;
12004 /* Initialize the CUMULATIVE_ARGS structure. */
12007 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
12009 rtx libname ATTRIBUTE_UNUSED,
12011 signed int n_named_args,
12012 enum machine_mode mode)
12014 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
12015 pcum->free_single_fp_reg = 0;
12016 pcum->stack_regs = 0;
12017 pcum->byref_regs = 0;
12019 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
12021 /* XXX - Should we check TARGET_HITACHI here ??? */
12022 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
12026 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
12027 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
12028 pcum->prototype_p = prototype_p (fntype);
12029 pcum->arg_count [(int) SH_ARG_INT]
12030 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
12033 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12034 && pcum->arg_count [(int) SH_ARG_INT] == 0
12035 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
12036 ? int_size_in_bytes (TREE_TYPE (fntype))
12037 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
12038 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
12039 == FIRST_RET_REG));
12043 pcum->arg_count [(int) SH_ARG_INT] = 0;
12044 pcum->prototype_p = FALSE;
12045 if (mode != VOIDmode)
12047 pcum->call_cookie =
12048 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12049 && GET_MODE_SIZE (mode) > 4
12050 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
12052 /* If the default ABI is the Renesas ABI then all library
12053 calls must assume that the library will be using the
12054 Renesas ABI. So if the function would return its result
12055 in memory then we must force the address of this memory
12056 block onto the stack. Ideally we would like to call
12057 targetm.calls.return_in_memory() here but we do not have
12058 the TYPE or the FNDECL available so we synthesize the
12059 contents of that function as best we can. */
12061 (TARGET_DEFAULT & MASK_HITACHI)
12062 && (mode == BLKmode
12063 || (GET_MODE_SIZE (mode) > 4
12064 && !(mode == DFmode
12065 && TARGET_FPU_DOUBLE)));
12069 pcum->call_cookie = 0;
12070 pcum->force_mem = FALSE;
12075 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
12076 not enter into CONST_DOUBLE for the replace.
12078 Note that copying is not done so X must not be shared unless all copies
12079 are to be modified.
12081 This is like replace_rtx, except that we operate on N_REPLACEMENTS
12082 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
12083 replacements[n*2+1] - and that we take mode changes into account.
12085 If a replacement is ambiguous, return NULL_RTX.
12087 If MODIFY is zero, don't modify any rtl in place,
12088 just return zero or nonzero for failure / success. */
12091 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
12096 /* The following prevents loops occurrence when we change MEM in
12097 CONST_DOUBLE onto the same CONST_DOUBLE. */
12098 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
12101 for (i = n_replacements - 1; i >= 0 ; i--)
12102 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
12103 return replacements[i*2+1];
12105 /* Allow this function to make replacements in EXPR_LISTs. */
12109 if (GET_CODE (x) == SUBREG)
12111 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
12112 n_replacements, modify);
12114 if (CONST_INT_P (new_rtx))
12116 x = simplify_subreg (GET_MODE (x), new_rtx,
12117 GET_MODE (SUBREG_REG (x)),
12123 SUBREG_REG (x) = new_rtx;
12127 else if (REG_P (x))
12129 unsigned regno = REGNO (x);
12130 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
12131 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12132 rtx result = NULL_RTX;
12134 for (i = n_replacements - 1; i >= 0; i--)
12136 rtx from = replacements[i*2];
12137 rtx to = replacements[i*2+1];
12138 unsigned from_regno, from_nregs, to_regno, new_regno;
12142 from_regno = REGNO (from);
12143 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
12144 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
12145 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
12147 if (regno < from_regno
12148 || regno + nregs > from_regno + nregs
12152 to_regno = REGNO (to);
12153 if (to_regno < FIRST_PSEUDO_REGISTER)
12155 new_regno = regno + to_regno - from_regno;
12156 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
12159 result = gen_rtx_REG (GET_MODE (x), new_regno);
12161 else if (GET_MODE (x) <= GET_MODE (to))
12162 result = gen_lowpart_common (GET_MODE (x), to);
12164 result = gen_lowpart_SUBREG (GET_MODE (x), to);
12167 return result ? result : x;
12169 else if (GET_CODE (x) == ZERO_EXTEND)
12171 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
12172 n_replacements, modify);
12174 if (CONST_INT_P (new_rtx))
12176 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
12177 new_rtx, GET_MODE (XEXP (x, 0)));
12182 XEXP (x, 0) = new_rtx;
12187 fmt = GET_RTX_FORMAT (GET_CODE (x));
12188 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
12194 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
12195 n_replacements, modify);
12199 XEXP (x, i) = new_rtx;
12201 else if (fmt[i] == 'E')
12202 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12204 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
12205 n_replacements, modify);
12209 XVECEXP (x, i, j) = new_rtx;
12217 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
12219 enum rtx_code code = TRUNCATE;
12221 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
12223 rtx inner = XEXP (x, 0);
12224 enum machine_mode inner_mode = GET_MODE (inner);
12226 if (inner_mode == mode)
12228 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
12230 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
12231 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
12233 code = GET_CODE (x);
12237 return gen_rtx_fmt_e (code, mode, x);
12240 /* called via for_each_rtx after reload, to clean up truncates of
12241 registers that span multiple actual hard registers. */
12243 shmedia_cleanup_truncate (rtx *p, void *n_changes)
12247 if (GET_CODE (x) != TRUNCATE)
12250 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
12252 enum machine_mode reg_mode = GET_MODE (reg);
12253 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
12254 subreg_lowpart_offset (DImode, reg_mode));
12255 *(int*) n_changes += 1;
12261 /* Load and store depend on the highpart of the address. However,
12262 set_attr_alternative does not give well-defined results before reload,
12263 so we must look at the rtl ourselves to see if any of the feeding
12264 registers is used in a memref. */
12266 /* Called by sh_contains_memref_p via for_each_rtx. */
12268 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
12270 return (MEM_P (*loc));
12273 /* Return nonzero iff INSN contains a MEM. */
12275 sh_contains_memref_p (rtx insn)
12277 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
12280 /* Return nonzero iff INSN loads a banked register. */
12282 sh_loads_bankedreg_p (rtx insn)
12284 if (GET_CODE (PATTERN (insn)) == SET)
12286 rtx op = SET_DEST (PATTERN(insn));
12287 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
12294 /* FNADDR is the MEM expression from a call expander. Return an address
12295 to use in an SHmedia insn pattern. */
12297 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
12301 fnaddr = XEXP (fnaddr, 0);
12302 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
12303 if (flag_pic && is_sym)
12305 if (! SYMBOL_REF_LOCAL_P (fnaddr))
12307 rtx reg = gen_reg_rtx (Pmode);
12309 /* We must not use GOTPLT for sibcalls, because PIC_REG
12310 must be restored before the PLT code gets to run. */
12312 emit_insn (gen_symGOT2reg (reg, fnaddr));
12314 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
12319 fnaddr = gen_sym2PIC (fnaddr);
12320 PUT_MODE (fnaddr, Pmode);
12323 /* If ptabs might trap, make this visible to the rest of the compiler.
12324 We generally assume that symbols pertain to valid locations, but
12325 it is possible to generate invalid symbols with asm or linker tricks.
12326 In a list of functions where each returns its successor, an invalid
12327 symbol might denote an empty list. */
12328 if (!TARGET_PT_FIXED
12329 && (!is_sym || TARGET_INVALID_SYMBOLS)
12330 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
12332 rtx tr = gen_reg_rtx (PDImode);
12334 emit_insn (gen_ptabs (tr, fnaddr));
12337 else if (! target_reg_operand (fnaddr, Pmode))
12338 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
12342 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12345 sh_preferred_reload_class (rtx x, reg_class_t rclass)
12347 if (rclass == NO_REGS
12349 && (CONST_DOUBLE_P (x)
12350 || GET_CODE (x) == SYMBOL_REF
12351 || PIC_ADDR_P (x)))
12352 return GENERAL_REGS;
12357 /* Implement TARGET_SECONDARY_RELOAD. */
12360 sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
12361 enum machine_mode mode, secondary_reload_info *sri)
12363 enum reg_class rclass = (enum reg_class) rclass_i;
12367 if (REGCLASS_HAS_FP_REG (rclass)
12368 && ! TARGET_SHMEDIA
12369 && immediate_operand ((x), mode)
12370 && ! ((fp_zero_operand (x) || fp_one_operand (x))
12371 && mode == SFmode && fldi_ok ()))
12375 sri->icode = CODE_FOR_reload_insf__frn;
12378 sri->icode = CODE_FOR_reload_indf__frn;
12381 /* ??? If we knew that we are in the appropriate mode -
12382 single precision - we could use a reload pattern directly. */
12387 if (rclass == FPUL_REGS
12389 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
12390 || REGNO (x) == T_REG))
12391 || GET_CODE (x) == PLUS))
12392 return GENERAL_REGS;
12393 if (rclass == FPUL_REGS && immediate_operand (x, mode))
12395 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
12396 return GENERAL_REGS;
12397 else if (mode == SFmode)
12399 sri->icode = CODE_FOR_reload_insi__i_fpul;
12402 if (rclass == FPSCR_REGS
12403 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
12404 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
12405 return GENERAL_REGS;
12406 if (REGCLASS_HAS_FP_REG (rclass)
12408 && immediate_operand (x, mode)
12409 && x != CONST0_RTX (GET_MODE (x))
12410 && GET_MODE (x) != V4SFmode)
12411 return GENERAL_REGS;
12412 if ((mode == QImode || mode == HImode)
12413 && TARGET_SHMEDIA && inqhi_operand (x, mode))
12415 sri->icode = ((mode == QImode)
12416 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
12419 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
12420 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
12421 return TARGET_REGS;
12422 } /* end of input-only processing. */
12424 if (((REGCLASS_HAS_FP_REG (rclass)
12426 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
12427 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
12428 && TARGET_FMOVD))))
12429 || (REGCLASS_HAS_GENERAL_REG (rclass)
12431 && FP_REGISTER_P (REGNO (x))))
12432 && ! TARGET_SHMEDIA
12433 && (mode == SFmode || mode == SImode))
12435 if ((rclass == FPUL_REGS
12436 || (REGCLASS_HAS_FP_REG (rclass)
12437 && ! TARGET_SHMEDIA && mode == SImode))
12440 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
12441 || REGNO (x) == T_REG
12442 || system_reg_operand (x, VOIDmode)))))
12444 if (rclass == FPUL_REGS)
12445 return GENERAL_REGS;
12448 if ((rclass == TARGET_REGS
12449 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
12450 && !satisfies_constraint_Csy (x)
12451 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
12452 return GENERAL_REGS;
12453 if ((rclass == MAC_REGS || rclass == PR_REGS)
12454 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
12455 && rclass != REGNO_REG_CLASS (REGNO (x)))
12456 return GENERAL_REGS;
12457 if (rclass != GENERAL_REGS && REG_P (x)
12458 && TARGET_REGISTER_P (REGNO (x)))
12459 return GENERAL_REGS;
12461 /* If here fall back to loading FPUL register through general registers.
12462 This case can happen when movsi_ie insn is picked initially to
12463 load/store the FPUL register from/to another register, and then the
12464 other register is allocated on the stack. */
12465 if (rclass == FPUL_REGS && true_regnum (x) == -1)
12466 return GENERAL_REGS;
12472 sh_conditional_register_usage (void)
12475 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
12476 if (! VALID_REGISTER_P (regno))
12477 fixed_regs[regno] = call_used_regs[regno] = 1;
12478 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
12481 call_used_regs[FIRST_GENERAL_REG + 8]
12482 = call_used_regs[FIRST_GENERAL_REG + 9] = 1;
12483 call_really_used_regs[FIRST_GENERAL_REG + 8]
12484 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1;
12486 if (TARGET_SHMEDIA)
12488 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS;
12489 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]);
12490 regno_reg_class[FIRST_FP_REG] = FP_REGS;
12494 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12495 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12497 /* Renesas saves and restores mac registers on call. */
12498 if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
12500 call_really_used_regs[MACH_REG] = 0;
12501 call_really_used_regs[MACL_REG] = 0;
12503 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0);
12504 regno <= LAST_FP_REG; regno += 2)
12505 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno);
12506 if (TARGET_SHMEDIA)
12508 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)
12509 if (! fixed_regs[regno] && call_really_used_regs[regno])
12510 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12513 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)
12514 if (! fixed_regs[regno] && call_really_used_regs[regno])
12515 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12518 /* Implement TARGET_LEGITIMATE_CONSTANT_P
12520 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
12523 sh_legitimate_constant_p (enum machine_mode mode, rtx x)
12525 return (TARGET_SHMEDIA
12526 ? ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
12527 || x == CONST0_RTX (mode)
12528 || !TARGET_SHMEDIA_FPU
12529 || TARGET_SHMEDIA64)
12530 : (GET_CODE (x) != CONST_DOUBLE
12531 || mode == DFmode || mode == SFmode
12532 || mode == DImode || GET_MODE (x) == VOIDmode));
12535 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
12538 sh_init_sync_libfuncs (void)
12540 init_sync_libfuncs (UNITS_PER_WORD);