1 ;; Predicate definitions for Renesas / SuperH SH.
2 ;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; TODO: Add a comment here.
21 (define_predicate "trapping_target_operand"
22 (match_code "if_then_else")
24 rtx cond, mem, res, tar, and_expr;
26 if (GET_MODE (op) != PDImode)
32 || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
35 if (!rtx_equal_p (XEXP (mem, 0), tar)
36 || GET_MODE (tar) != Pmode)
38 if (GET_CODE (cond) == CONST)
40 cond = XEXP (cond, 0);
41 if (!satisfies_constraint_Csy (tar))
43 if (GET_CODE (tar) == CONST)
46 else if (!arith_reg_operand (tar, VOIDmode)
47 && ! satisfies_constraint_Csy (tar))
49 if (GET_CODE (cond) != EQ)
51 and_expr = XEXP (cond, 0);
52 return (GET_CODE (and_expr) == AND
53 && rtx_equal_p (XEXP (and_expr, 0), tar)
54 && CONST_INT_P (XEXP (and_expr, 1))
55 && CONST_INT_P (XEXP (cond, 1))
56 && INTVAL (XEXP (and_expr, 1)) == 3
57 && INTVAL (XEXP (cond, 1)) == 3);
60 ;; A logical operand that can be used in an shmedia and insn.
61 (define_predicate "and_operand"
62 (match_code "subreg,reg,const_int")
64 if (logical_operand (op, mode))
67 /* Check mshflo.l / mshflhi.l opportunities. */
70 && satisfies_constraint_J16 (op))
76 ;; Like arith_reg_dest, but this predicate is defined with
77 ;; define_special_predicate, not define_predicate.
78 (define_special_predicate "any_arith_reg_dest"
79 (match_code "subreg,reg")
81 return arith_reg_dest (op, mode);
84 ;; Like register_operand, but this predicate is defined with
85 ;; define_special_predicate, not define_predicate.
86 (define_special_predicate "any_register_operand"
87 (match_code "subreg,reg")
89 return register_operand (op, mode);
92 ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
93 (define_predicate "arith_operand"
94 (match_code "subreg,reg,const_int,truncate")
96 if (arith_reg_operand (op, mode))
101 /* FIXME: We should be checking whether the CONST_INT fits in a
102 signed 16-bit here, but this causes reload_cse to crash when
103 attempting to transform a sequence of two 64-bit sets of the
104 same register from literal constants into a set and an add,
105 when the difference is too wide for an add. */
107 || satisfies_constraint_Css (op))
109 else if (GET_CODE (op) == TRUNCATE
110 && REG_P (XEXP (op, 0))
111 && ! system_reg_operand (XEXP (op, 0), VOIDmode)
112 && (mode == VOIDmode || mode == GET_MODE (op))
113 && (GET_MODE_SIZE (GET_MODE (op))
114 < GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
115 && (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
116 || GET_MODE_SIZE (GET_MODE (op)) == 4))
117 return register_operand (XEXP (op, 0), VOIDmode);
121 else if (satisfies_constraint_I08 (op))
127 ;; Like above, but for DImode destinations: forbid paradoxical DImode
128 ;; subregs, because this would lead to missing sign extensions when
129 ;; truncating from DImode to SImode.
130 (define_predicate "arith_reg_dest"
131 (match_code "subreg,reg")
133 if (mode == DImode && GET_CODE (op) == SUBREG
134 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
137 return arith_reg_operand (op, mode);
140 ;; Returns 1 if OP is a normal arithmetic register.
141 (define_predicate "arith_reg_operand"
142 (match_code "subreg,reg,sign_extend")
144 if (register_operand (op, mode))
150 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
151 regno = REGNO (SUBREG_REG (op));
155 return (regno != T_REG && regno != PR_REG
156 && ! TARGET_REGISTER_P (regno)
157 && (regno != FPUL_REG || TARGET_SH4)
158 && regno != MACH_REG && regno != MACL_REG);
160 /* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
161 We allow SImode here, as not using an FP register is just a matter of
162 proper register allocation. */
164 && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
165 && GET_MODE (XEXP (op, 0)) == SImode
166 && GET_CODE (XEXP (op, 0)) != SUBREG)
167 return register_operand (XEXP (op, 0), VOIDmode);
168 #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
169 if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
170 && GET_MODE (XEXP (op, 0)) == HImode
171 && REG_P (XEXP (op, 0))
172 && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
173 return register_operand (XEXP (op, 0), VOIDmode);
175 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
176 && GET_CODE (op) == SUBREG
177 && GET_MODE (SUBREG_REG (op)) == DImode
178 && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
179 && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
180 && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
181 return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
185 ;; Returns 1 if OP is a valid source operand for a compare insn.
186 (define_predicate "arith_reg_or_0_operand"
187 (match_code "subreg,reg,const_int,const_vector")
189 if (arith_reg_operand (op, mode))
192 if (satisfies_constraint_Z (op))
198 ;; Returns 1 if OP is a floating point operator with two operands.
199 (define_predicate "binary_float_operator"
200 (and (match_code "plus,minus,mult,div")
201 (match_test "GET_MODE (op) == mode")))
203 ;; Returns 1 if OP is a logical operator with two operands.
204 (define_predicate "binary_logical_operator"
205 (and (match_code "and,ior,xor")
206 (match_test "GET_MODE (op) == mode")))
208 ;; Return 1 if OP is an address suitable for a cache manipulation operation.
209 ;; MODE has the meaning as in address_operand.
210 (define_special_predicate "cache_address_operand"
211 (match_code "plus,reg")
213 if (GET_CODE (op) == PLUS)
215 if (!REG_P (XEXP (op, 0)))
217 if (!CONST_INT_P (XEXP (op, 1))
218 || (INTVAL (XEXP (op, 1)) & 31))
221 else if (!REG_P (op))
223 return address_operand (op, mode);
226 ;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
227 (define_predicate "cmp_operand"
228 (match_code "subreg,reg,const_int")
230 if (satisfies_constraint_N (op))
233 && mode != DImode && GET_CODE (op) == SUBREG
234 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
236 return arith_reg_operand (op, mode);
239 ;; Returns true if OP is an operand that can be used as the first operand in
240 ;; the cstoresi4 expander pattern.
241 (define_predicate "cmpsi_operand"
242 (match_code "subreg,reg,const_int")
244 if (REG_P (op) && REGNO (op) == T_REG
245 && GET_MODE (op) == SImode
248 return arith_operand (op, mode);
251 ;; Returns true if OP is a comutative float operator.
252 ;; This predicate is currently unused.
253 ;;(define_predicate "commutative_float_operator"
254 ;; (and (match_code "plus,mult")
255 ;; (match_test "GET_MODE (op) == mode")))
257 ;; Returns true if OP is a equal or not equal operator.
258 (define_predicate "equality_comparison_operator"
259 (match_code "eq,ne"))
261 ;; Returns true if OP is an arithmetic operand that is zero extended during
263 (define_predicate "extend_reg_operand"
264 (match_code "subreg,reg,truncate")
266 return (GET_CODE (op) == TRUNCATE
268 : arith_reg_operand) (op, mode);
271 ;; Like extend_reg_operand, but also allow a constant 0.
272 (define_predicate "extend_reg_or_0_operand"
273 (match_code "subreg,reg,truncate,const_int")
275 return (GET_CODE (op) == TRUNCATE
277 : arith_reg_or_0_operand) (op, mode);
280 ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
281 (define_predicate "ext_dest_operand"
282 (match_code "subreg,reg")
284 return arith_reg_operand (op, mode);
287 ;; Returns true if OP can be used as a destination register for shmedia floating
288 ;; point to integer conversions.
289 (define_predicate "fp_arith_reg_dest"
290 (match_code "subreg,reg")
292 if (mode == DImode && GET_CODE (op) == SUBREG
293 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
295 return fp_arith_reg_operand (op, mode);
298 ;; Returns true if OP is a floating point register that can be used in floating
299 ;; point arithmetic operations.
300 (define_predicate "fp_arith_reg_operand"
301 (match_code "subreg,reg")
303 if (register_operand (op, mode))
309 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
310 regno = REGNO (SUBREG_REG (op));
314 return (regno >= FIRST_PSEUDO_REGISTER
315 || FP_REGISTER_P (regno));
320 ;; Returns true if OP is the FPSCR.
321 (define_predicate "fpscr_operand"
325 && (REGNO (op) == FPSCR_REG
326 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
327 && !(reload_in_progress || reload_completed)))
328 && GET_MODE (op) == PSImode);
331 ;; Returns true if OP is an operand that is either the fpul hard reg or
332 ;; a pseudo. This prevents combine from propagating function arguments
333 ;; in hard regs into insns that need the operand in fpul. If it's a pseudo
334 ;; reload can fix it up.
335 (define_predicate "fpul_operand"
339 return fp_arith_reg_operand (op, mode);
342 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
343 && GET_MODE (op) == mode);
346 ;; Returns true if OP is a valid fpul input operand for the fsca insn.
347 ;; The value in fpul is a fixed-point value and its scaling is described
348 ;; in the fsca insn by a mult:SF. To allow pre-scaled fixed-point inputs
349 ;; in fpul we have to permit things like
351 ;; (fix:SF (float:SF (reg:SI)))
352 (define_predicate "fpul_fsca_operand"
353 (match_code "fix,reg")
355 if (fpul_operand (op, SImode))
357 if (GET_CODE (op) == FIX && GET_MODE (op) == SImode
358 && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode)
359 return fpul_fsca_operand (XEXP (XEXP (op, 0), 0),
360 GET_MODE (XEXP (XEXP (op, 0), 0)));
364 ;; Returns true if OP is a valid constant scale factor for the fsca insn.
365 (define_predicate "fsca_scale_factor"
366 (and (match_code "const_double")
367 (match_test "op == sh_fsca_int2sf ()")))
369 ;; Returns true if OP is an operand that is zero extended during an operation.
370 (define_predicate "general_extend_operand"
371 (match_code "subreg,reg,mem,truncate")
373 return (GET_CODE (op) == TRUNCATE
375 : nonimmediate_operand) (op, mode);
378 ;; Returns 1 if OP is a simple register address.
379 (define_predicate "simple_mem_operand"
380 (and (match_code "mem")
381 (match_test "arith_reg_operand (XEXP (op, 0), SImode)")))
383 ;; Returns 1 if OP is a valid displacement address.
384 (define_predicate "displacement_mem_operand"
385 (and (match_code "mem")
386 (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
387 (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)")
388 (match_test "sh_legitimate_index_p (GET_MODE (op),
389 XEXP (XEXP (op, 0), 1),
390 TARGET_SH2A, true)")))
392 ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.
393 (define_predicate "zero_extend_movu_operand"
394 (and (match_operand 0 "displacement_mem_operand")
395 (match_test "GET_MODE (op) == QImode || GET_MODE (op) == HImode")))
397 ;; Returns 1 if the operand can be used in a zero_extend.
398 (define_predicate "zero_extend_operand"
399 (ior (and (match_test "TARGET_SHMEDIA")
400 (match_operand 0 "general_extend_operand"))
401 (and (match_test "! TARGET_SHMEDIA")
402 (match_operand 0 "arith_reg_operand"))
403 (and (match_test "TARGET_SH2A")
404 (match_operand 0 "zero_extend_movu_operand"))))
406 ;; Returns 1 if OP can be source of a simple move operation. Same as
407 ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
408 ;; are subregs of system registers.
409 (define_predicate "general_movsrc_operand"
410 (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,
413 if (t_reg_operand (op, mode))
418 rtx inside = XEXP (op, 0);
420 /* Disallow mems with GBR address here. They have to go through
421 separate special patterns. */
422 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
423 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
424 && REGNO (XEXP (inside, 0)) == GBR_REG))
427 if (GET_CODE (inside) == CONST)
428 inside = XEXP (inside, 0);
430 if (GET_CODE (inside) == LABEL_REF)
433 if (GET_CODE (inside) == PLUS
434 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
435 && CONST_INT_P (XEXP (inside, 1)))
438 /* Only post inc allowed. */
439 if (GET_CODE (inside) == PRE_DEC)
443 if ((mode == QImode || mode == HImode)
444 && mode == GET_MODE (op)
446 || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
448 rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
450 if (GET_CODE (x) == PLUS
451 && REG_P (XEXP (x, 0))
452 && CONST_INT_P (XEXP (x, 1)))
453 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
457 && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
458 && sh_rep_vec (op, mode))
460 if (TARGET_SHMEDIA && 1
461 && GET_CODE (op) == SUBREG && GET_MODE (op) == mode
462 && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
463 /* FIXME */ abort (); /* return 1; */
464 return general_operand (op, mode);
467 ;; Returns 1 if OP is a MEM that does not use displacement addressing.
468 (define_predicate "movsrc_no_disp_mem_operand"
471 return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
474 ;; Returns 1 if OP can be a destination of a move. Same as
475 ;; general_operand, but no preinc allowed.
476 (define_predicate "general_movdst_operand"
477 (match_code "subreg,reg,mem")
479 if (t_reg_operand (op, mode))
484 rtx inside = XEXP (op, 0);
485 /* Disallow mems with GBR address here. They have to go through
486 separate special patterns. */
487 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
488 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
489 && REGNO (XEXP (inside, 0)) == GBR_REG))
493 /* Only pre dec allowed. */
494 if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
496 if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
497 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
498 && ! (reload_in_progress || reload_completed))
501 if ((mode == QImode || mode == HImode)
502 && mode == GET_MODE (op)
504 || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
506 rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
508 if (GET_CODE (x) == PLUS
509 && REG_P (XEXP (x, 0))
510 && CONST_INT_P (XEXP (x, 1)))
511 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
514 return general_operand (op, mode);
517 ;; Returns 1 if OP is a POST_INC on stack pointer register.
518 (define_predicate "sh_no_delay_pop_operand"
522 inside = XEXP (op, 0);
524 if (GET_CODE (op) == MEM && GET_MODE (op) == SImode
525 && GET_CODE (inside) == POST_INC
526 && GET_CODE (XEXP (inside, 0)) == REG
527 && REGNO (XEXP (inside, 0)) == SP_REG)
533 ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
534 (define_predicate "unaligned_load_operand"
539 if (!MEM_P (op) || GET_MODE (op) != mode)
542 inside = XEXP (op, 0);
544 if (GET_CODE (inside) == POST_INC)
545 inside = XEXP (inside, 0);
553 ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner
555 (define_predicate "mem_index_disp_operand"
558 rtx plus0_rtx, plus1_rtx, mult_rtx;
560 plus0_rtx = XEXP (op, 0);
561 if (GET_CODE (plus0_rtx) != PLUS)
564 plus1_rtx = XEXP (plus0_rtx, 0);
565 if (GET_CODE (plus1_rtx) != PLUS)
567 if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1))))
570 mult_rtx = XEXP (plus1_rtx, 0);
571 if (GET_CODE (mult_rtx) != MULT)
573 if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0)))
574 || ! CONST_INT_P (XEXP (mult_rtx, 1)))
577 return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0
578 && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
581 ;; Returns true if OP is some kind of greater comparision.
582 (define_predicate "greater_comparison_operator"
583 (match_code "gt,ge,gtu,geu"))
585 ;; Returns true if OP is an operand suitable for shmedia reload_inqi and
586 ;; reload_inhi insns.
587 (define_predicate "inqhi_operand"
588 (match_code "truncate")
590 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
593 /* Can't use true_regnum here because copy_cost wants to know about
594 SECONDARY_INPUT_RELOAD_CLASS. */
595 return REG_P (op) && FP_REGISTER_P (REGNO (op));
598 ;; Returns true if OP is a general purpose integer register.
599 ;; This predicate is currently unused.
600 ;;(define_special_predicate "int_gpr_dest"
601 ;; (match_code "subreg,reg")
603 ;; enum machine_mode op_mode = GET_MODE (op);
605 ;; if (GET_MODE_CLASS (op_mode) != MODE_INT
606 ;; || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
608 ;; if (! reload_completed)
610 ;; return true_regnum (op) <= LAST_GENERAL_REG;
613 ;; Returns true if OP is some kind of less comparison.
614 (define_predicate "less_comparison_operator"
615 (match_code "lt,le,ltu,leu"))
617 ;; Returns 1 if OP is a valid source operand for a logical operation.
618 (define_predicate "logical_operand"
619 (match_code "subreg,reg,const_int")
622 && mode != DImode && GET_CODE (op) == SUBREG
623 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
626 if (arith_reg_operand (op, mode))
631 if (satisfies_constraint_I10 (op))
636 else if (satisfies_constraint_K08 (op))
642 ;; Like logical_operand but allows additional constant values which can be
643 ;; done with zero extensions. Used for the second operand of and insns.
644 (define_predicate "logical_and_operand"
645 (match_code "subreg,reg,const_int")
647 if (logical_operand (op, mode))
651 && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op)))
657 ;; Returns true if OP is a logical operator.
658 (define_predicate "logical_operator"
659 (match_code "and,ior,xor"))
661 ;; Like arith_reg_operand, but for register source operands of narrow
662 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
663 (define_predicate "logical_reg_operand"
664 (match_code "subreg,reg")
667 && GET_CODE (op) == SUBREG
668 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
671 return arith_reg_operand (op, mode);
674 ;; Returns true if OP is a valid bit offset value for the shmedia mextr insns.
675 (define_predicate "mextr_bit_offset"
676 (match_code "const_int")
680 if (!CONST_INT_P (op))
683 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
686 ;; Returns true if OP is a constant -1, 0 or an zero extended register that
687 ;; can be used as an operator in the *subsi3_media insn.
688 (define_predicate "minuend_operand"
689 (match_code "subreg,reg,truncate,const_int")
691 return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
694 ;; Returns true if OP is a noncommutative floating point operator.
695 ;; This predicate is currently unused.
696 ;;(define_predicate "noncommutative_float_operator"
697 ;; (and (match_code "minus,div")
698 ;; (match_test "GET_MODE (op) == mode")))
700 ;; UNORDERED is only supported on SHMEDIA.
702 (define_predicate "sh_float_comparison_operator"
703 (ior (match_operand 0 "ordered_comparison_operator")
704 (and (match_test "TARGET_SHMEDIA")
705 (match_code "unordered"))))
707 (define_predicate "shmedia_cbranch_comparison_operator"
708 (ior (match_operand 0 "equality_comparison_operator")
709 (match_operand 0 "greater_comparison_operator")))
711 ;; Returns true if OP is a constant vector.
712 (define_predicate "sh_const_vec"
713 (match_code "const_vector")
717 if (GET_CODE (op) != CONST_VECTOR
718 || (GET_MODE (op) != mode && mode != VOIDmode))
720 i = XVECLEN (op, 0) - 1;
722 if (!CONST_INT_P (XVECEXP (op, 0, i)))
727 ;; Determine if OP is a constant vector matching MODE with only one
728 ;; element that is not a sign extension. Two byte-sized elements
730 (define_predicate "sh_1el_vec"
731 (match_code "const_vector")
734 int i, last, least, sign_ix;
737 if (GET_CODE (op) != CONST_VECTOR
738 || (GET_MODE (op) != mode && mode != VOIDmode))
740 /* Determine numbers of last and of least significant elements. */
741 last = XVECLEN (op, 0) - 1;
742 least = TARGET_LITTLE_ENDIAN ? 0 : last;
743 if (!CONST_INT_P (XVECEXP (op, 0, least)))
746 if (GET_MODE_UNIT_SIZE (mode) == 1)
747 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
748 if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
750 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
751 sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
752 ? constm1_rtx : const0_rtx);
753 i = XVECLEN (op, 0) - 1;
755 if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
761 ;; Like register_operand, but take into account that SHMEDIA can use
762 ;; the constant zero like a general register.
763 (define_predicate "sh_register_operand"
764 (match_code "reg,subreg,const_int,const_double")
766 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
768 return register_operand (op, mode);
771 ;; Returns true if OP is a vector which is composed of one element that is
773 (define_predicate "sh_rep_vec"
774 (match_code "const_vector,parallel")
779 if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
780 || (GET_MODE (op) != mode && mode != VOIDmode))
782 i = XVECLEN (op, 0) - 2;
783 x = XVECEXP (op, 0, i + 1);
784 if (GET_MODE_UNIT_SIZE (mode) == 1)
786 y = XVECEXP (op, 0, i);
787 for (i -= 2; i >= 0; i -= 2)
788 if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
789 || ! rtx_equal_p (XVECEXP (op, 0, i), y))
794 if (XVECEXP (op, 0, i) != x)
799 ;; Returns true if OP is a valid shift count operand for shift operations.
800 (define_predicate "shift_count_operand"
801 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,
802 zero_extend,sign_extend")
804 /* Allow T_REG as shift count for dynamic shifts, although it is not
805 really possible. It will then be copied to a general purpose reg. */
806 if (! TARGET_SHMEDIA)
807 return const_int_operand (op, mode) || arith_reg_operand (op, mode)
808 || (TARGET_DYNSHIFT && t_reg_operand (op, mode));
810 return (CONSTANT_P (op)
812 ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
813 : nonmemory_operand (op, mode))
814 : shift_count_reg_operand (op, mode));
817 ;; Returns true if OP is a valid shift count operand in a register which can
818 ;; be used by shmedia shift insns.
819 (define_predicate "shift_count_reg_operand"
820 (match_code "subreg,reg,zero_extend,sign_extend")
822 if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
823 || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
824 && (mode == VOIDmode || mode == GET_MODE (op))
825 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
826 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
831 while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
832 || GET_CODE (op) == TRUNCATE)
833 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
834 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
837 return arith_reg_operand (op, mode);
840 ;; Predicates for matching operands that are constant shift
841 ;; amounts 1, 2, 8, 16.
842 (define_predicate "p27_shift_count_operand"
843 (and (match_code "const_int")
844 (match_test "satisfies_constraint_P27 (op)")))
846 (define_predicate "not_p27_shift_count_operand"
847 (and (match_code "const_int")
848 (match_test "! satisfies_constraint_P27 (op)")))
850 ;; For right shifts the constant 1 is a special case because the shlr insn
851 ;; clobbers the T_REG and is handled by the T_REG clobbering version of the
852 ;; insn, which is also used for non-P27 shift sequences.
853 (define_predicate "p27_rshift_count_operand"
854 (and (match_code "const_int")
855 (match_test "satisfies_constraint_P27 (op)")
856 (match_test "! satisfies_constraint_M (op)")))
858 (define_predicate "not_p27_rshift_count_operand"
859 (and (match_code "const_int")
860 (ior (match_test "! satisfies_constraint_P27 (op)")
861 (match_test "satisfies_constraint_M (op)"))))
863 ;; Returns true if OP is some kind of a shift operator.
864 (define_predicate "shift_operator"
865 (match_code "ashift,ashiftrt,lshiftrt"))
867 ;; Returns true if OP is a symbol reference.
868 (define_predicate "symbol_ref_operand"
869 (match_code "symbol_ref"))
871 ;; Same as target_reg_operand, except that label_refs and symbol_refs
872 ;; are accepted before reload.
873 (define_special_predicate "target_operand"
874 (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
876 if (mode != VOIDmode && mode != Pmode)
879 if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
880 && satisfies_constraint_Csy (op))
881 return ! reload_completed;
883 return target_reg_operand (op, mode);
886 ;; A predicate that accepts pseudos and branch target registers.
887 (define_special_predicate "target_reg_operand"
888 (match_code "subreg,reg")
891 ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
892 : mode != GET_MODE (op))
895 if (GET_CODE (op) == SUBREG)
901 /* We must protect ourselves from matching pseudos that are virtual
902 register, because they will eventually be replaced with hardware
903 registers that aren't branch-target registers. */
904 if (REGNO (op) > LAST_VIRTUAL_REGISTER
905 || TARGET_REGISTER_P (REGNO (op)))
911 ;; Returns true if OP is a valid operand for the shmedia mperm.w insn.
912 (define_special_predicate "trunc_hi_operand"
913 (match_code "subreg,reg,truncate")
915 enum machine_mode op_mode = GET_MODE (op);
917 if (op_mode != SImode && op_mode != DImode
918 && op_mode != V4HImode && op_mode != V2SImode)
920 return extend_reg_operand (op, mode);
923 ;; Returns true if OP is an address suitable for an unaligned access
925 (define_special_predicate "ua_address_operand"
926 (match_code "subreg,reg,plus")
928 if (GET_CODE (op) == PLUS
929 && (! satisfies_constraint_I06 (XEXP (op, 1))))
931 return address_operand (op, QImode);
934 ;; Returns true if OP is a valid offset for an unaligned memory address.
935 (define_predicate "ua_offset"
936 (match_code "const_int")
938 return satisfies_constraint_I06 (op);
941 ;; Returns true if OP is a floating point operator with one operand.
942 (define_predicate "unary_float_operator"
943 (and (match_code "abs,neg,sqrt")
944 (match_test "GET_MODE (op) == mode")))
946 ;; Return 1 if OP is a valid source operand for xor.
947 (define_predicate "xor_operand"
948 (match_code "subreg,reg,const_int")
950 if (CONST_INT_P (op))
951 return (TARGET_SHMEDIA
952 ? (satisfies_constraint_I06 (op)
953 || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
954 : satisfies_constraint_K08 (op));
956 && mode != DImode && GET_CODE (op) == SUBREG
957 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
959 return arith_reg_operand (op, mode);
962 (define_predicate "bitwise_memory_operand"
967 if (REG_P (XEXP (op, 0)))
970 if (GET_CODE (XEXP (op, 0)) == PLUS
971 && REG_P (XEXP (XEXP (op, 0), 0))
972 && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))
978 ;; The atomic_* operand predicates are used for the atomic patterns.
979 ;; Depending on the particular pattern some operands can be immediate
980 ;; values. Using these predicates avoids the usage of 'force_reg' in the
982 (define_predicate "atomic_arith_operand"
983 (ior (match_code "subreg,reg")
984 (and (match_test "satisfies_constraint_I08 (op)")
985 (match_test "mode != QImode")
986 (match_test "mode != HImode")
987 (match_test "TARGET_SH4A_ARCH"))))
989 (define_predicate "atomic_logical_operand"
990 (ior (match_code "subreg,reg")
991 (and (match_test "satisfies_constraint_K08 (op)")
992 (match_test "mode != QImode")
993 (match_test "mode != HImode")
994 (match_test "TARGET_SH4A_ARCH"))))
996 ;; A predicate describing the T bit register in any form.
997 (define_predicate "t_reg_operand"
998 (match_code "reg,subreg,sign_extend,zero_extend")
1000 switch (GET_CODE (op))
1003 return REGNO (op) == T_REG;
1006 return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG;
1010 return GET_CODE (XEXP (op, 0)) == SUBREG
1011 && REG_P (SUBREG_REG (XEXP (op, 0)))
1012 && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
1019 ;; A predicate describing a negated T bit register.
1020 (define_predicate "negt_reg_operand"
1021 (match_code "subreg,xor")
1023 switch (GET_CODE (op))
1026 return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))
1027 && satisfies_constraint_M (XEXP (op, 1));
1030 return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)));
1037 ;; A predicate that returns true if OP is a valid construct around the T bit
1038 ;; that can be used as an operand for conditional branches.
1039 (define_predicate "cbranch_treg_value"
1040 (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend")
1042 return sh_eval_treg_value (op) >= 0;
1045 ;; Returns true if OP is arith_reg_operand or t_reg_operand.
1046 (define_predicate "arith_reg_or_t_reg_operand"
1047 (ior (match_operand 0 "arith_reg_operand")
1048 (match_operand 0 "t_reg_operand")))
1050 ;; A predicate describing the negated value of the T bit register shifted
1052 (define_predicate "negt_reg_shl31_operand"
1053 (match_code "plus,minus,if_then_else")
1055 /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand")
1056 (const_int -2147483648)) ;; 0xffffffff80000000
1057 (const_int -2147483648))
1059 if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1))
1060 && GET_CODE (XEXP (op, 0)) == MULT
1061 && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode)
1062 && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1)))
1065 /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000
1066 (mult:SI (match_operand:SI 1 "t_reg_operand")
1067 (const_int -2147483648)))
1069 if (GET_CODE (op) == MINUS
1070 && satisfies_constraint_Jhb (XEXP (op, 0))
1071 && GET_CODE (XEXP (op, 1)) == MULT
1072 && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode)
1073 && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1)))
1076 /* (if_then_else:SI (match_operand:SI 1 "t_reg_operand")
1078 (const_int -2147483648)) ;; 0xffffffff80000000
1080 if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode)
1081 && satisfies_constraint_Z (XEXP (op, 1))
1082 && satisfies_constraint_Jhb (XEXP (op, 2)))
1088 ;; A predicate that determines whether a given constant is a valid
1089 ;; displacement for a GBR load/store of the specified mode.
1090 (define_predicate "gbr_displacement"
1091 (match_code "const_int")
1093 const int mode_sz = GET_MODE_SIZE (mode);
1094 const int move_sz = mode_sz > GET_MODE_SIZE (SImode)
1095 ? GET_MODE_SIZE (SImode)
1097 int max_disp = 255 * move_sz;
1098 if (mode_sz > move_sz)
1099 max_disp -= mode_sz - move_sz;
1101 return INTVAL (op) >= 0 && INTVAL (op) <= max_disp;
1104 ;; A predicate that determines whether OP is a valid GBR addressing mode
1105 ;; memory reference.
1106 (define_predicate "gbr_address_mem"
1109 rtx addr = XEXP (op, 0);
1111 if (REG_P (addr) && REGNO (addr) == GBR_REG)
1113 if (GET_CODE (addr) == PLUS
1114 && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG
1115 && gbr_displacement (XEXP (addr, 1), mode))