1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/rs6000/rs6000-opts.h"
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
35 #include "config/rs6000/rs6000-modes.h"
38 /* Definitions for the object file format. These are set at
41 #define OBJECT_XCOFF 1
43 #define OBJECT_MACHO 4
45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
54 #define TARGET_AIX_OS 0
57 /* Control whether function entry points use a "dot" symbol when
61 /* Default string to use for cpu if not specified. */
62 #ifndef TARGET_CPU_DEFAULT
63 #define TARGET_CPU_DEFAULT ((char *)0)
66 /* If configured for PPC405, support PPC405CR Erratum77. */
67 #ifdef CONFIG_PPC405CR
68 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
70 #define PPC405_ERRATUM77 0
74 #define ASM_OPT_ANY ""
76 #define ASM_OPT_ANY " -many"
79 /* Common ASM definitions used by ASM_SPEC among the various targets for
80 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
81 provide the default assembler options if the user uses -mcpu=native, so if
82 you make changes here, make them also there. PR63177: Do not pass -mpower8
83 to the assembler if -mpower9-vector was also used. */
84 #define ASM_CPU_SPEC \
85 "%{mcpu=native: %(asm_cpu_native); \
86 mcpu=power9: -mpower9; \
87 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \
88 mcpu=power7: -mpower7; \
89 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
90 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
91 mcpu=power5+: -mpower5; \
92 mcpu=power5: -mpower5; \
93 mcpu=power4: -mpower4; \
94 mcpu=power3: -mppc64; \
95 mcpu=powerpc: -mppc; \
96 mcpu=powerpc64: -mppc64; \
115 mcpu=ec603e: -mppc; \
123 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
124 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
125 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
130 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
131 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
134 mcpu=e300c2: -me300; \
135 mcpu=e300c3: -me300; \
136 mcpu=e500mc: -me500mc; \
137 mcpu=e500mc64: -me500mc64; \
138 mcpu=e5500: -me5500; \
139 mcpu=e6500: -me6500; \
140 mcpu=titan: -mtitan; \
141 mcpu=future: -mfuture; \
142 !mcpu*: %{mpower9-vector: -mpower9; \
143 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
145 mpowerpc64: -mppc64;: %(asm_default)}; \
146 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \
147 %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \
150 #define CPP_DEFAULT_SPEC ""
152 #define ASM_DEFAULT_SPEC ""
154 /* This macro defines names of additional specifications to put in the specs
155 that can be used in various specifications like CC1_SPEC. Its definition
156 is an initializer with a subgrouping for each command option.
158 Each subgrouping contains a string constant, that defines the
159 specification name, and a string constant that used by the GCC driver
162 Do not define this macro if it does not need to do anything. */
164 #define SUBTARGET_EXTRA_SPECS
166 #define EXTRA_SPECS \
167 { "cpp_default", CPP_DEFAULT_SPEC }, \
168 { "asm_cpu", ASM_CPU_SPEC }, \
169 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
170 { "asm_default", ASM_DEFAULT_SPEC }, \
171 { "cc1_cpu", CC1_CPU_SPEC }, \
172 SUBTARGET_EXTRA_SPECS
174 /* -mcpu=native handling only makes sense with compiler running on
175 an PowerPC chip. If changing this condition, also change
176 the condition in driver-rs6000.c. */
177 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
178 /* In driver-rs6000.c. */
179 extern const char *host_detect_local_cpu (int argc, const char **argv);
180 #define EXTRA_SPEC_FUNCTIONS \
181 { "local_cpu_detect", host_detect_local_cpu },
182 #define HAVE_LOCAL_CPU_DETECT
183 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
186 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
190 #ifdef HAVE_LOCAL_CPU_DETECT
191 #define CC1_CPU_SPEC \
192 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
193 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
195 #define CC1_CPU_SPEC ""
199 /* Architecture type. */
201 /* Define TARGET_MFCRF if the target assembler does not support the
202 optional field operand for mfcr. */
204 #ifndef HAVE_AS_MFCRF
206 #define TARGET_MFCRF 0
209 /* Define TARGET_TLS_MARKERS if the target assembler does not support
210 arg markers for __tls_get_addr calls. */
211 #ifndef HAVE_AS_TLS_MARKERS
212 #undef TARGET_TLS_MARKERS
213 #define TARGET_TLS_MARKERS 0
215 #define TARGET_TLS_MARKERS tls_markers
218 #ifndef TARGET_SECURE_PLT
219 #define TARGET_SECURE_PLT 0
222 #ifndef TARGET_CMODEL
223 #define TARGET_CMODEL CMODEL_SMALL
226 #define TARGET_32BIT (! TARGET_64BIT)
229 #define HAVE_AS_TLS 0
232 #ifndef HAVE_AS_PLTSEQ
233 #define HAVE_AS_PLTSEQ 0
236 #ifndef TARGET_PLTSEQ
237 #define TARGET_PLTSEQ 0
240 #ifndef TARGET_LINK_STACK
241 #define TARGET_LINK_STACK 0
244 #ifndef SET_TARGET_LINK_STACK
245 #define SET_TARGET_LINK_STACK(X) do { } while (0)
248 #ifndef TARGET_FLOAT128_ENABLE_TYPE
249 #define TARGET_FLOAT128_ENABLE_TYPE 0
252 /* Return 1 for a symbol ref for a thread-local storage symbol. */
253 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
254 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0)
257 /* For libgcc2 we make sure this is a compile time constant */
258 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
259 #undef TARGET_POWERPC64
260 #define TARGET_POWERPC64 1
262 #undef TARGET_POWERPC64
263 #define TARGET_POWERPC64 0
266 /* The option machinery will define this. */
269 #define TARGET_DEFAULT (MASK_MULTIPLE)
271 /* Define generic processor types based upon current deployment. */
272 #define PROCESSOR_COMMON PROCESSOR_PPC601
273 #define PROCESSOR_POWERPC PROCESSOR_PPC604
274 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
276 /* Define the default processor. This is overridden by other tm.h files. */
277 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
278 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
280 /* Specify the dialect of assembler to use. Only new mnemonics are supported
281 starting with GCC 4.8, i.e. just one dialect, but for backwards
282 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
284 #define ASSEMBLER_DIALECT 1
287 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
288 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
289 #define MASK_DEBUG_REG 0x04 /* debug register handling */
290 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
291 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
292 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
293 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
294 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
299 | MASK_DEBUG_TARGET \
300 | MASK_DEBUG_BUILTIN)
302 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
303 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
304 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
305 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
306 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
307 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
308 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
310 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
311 long double format that uses a pair of doubles, or IEEE 128-bit floating
312 point. KFmode was added as a way to represent IEEE 128-bit floating point,
313 even if the default for long double is the IBM long double format.
314 Similarly IFmode is the IBM long double format even if the default is IEEE
315 128-bit. Don't allow IFmode if -msoft-float. */
316 #define FLOAT128_IEEE_P(MODE) \
317 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
318 && ((MODE) == TFmode || (MODE) == TCmode)) \
319 || ((MODE) == KFmode) || ((MODE) == KCmode))
321 #define FLOAT128_IBM_P(MODE) \
322 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
323 && ((MODE) == TFmode || (MODE) == TCmode)) \
324 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
326 /* Helper macros to say whether a 128-bit floating point type can go in a
327 single vector register, or whether it needs paired scalar values. */
328 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
330 #define FLOAT128_2REG_P(MODE) \
331 (FLOAT128_IBM_P (MODE) \
332 || ((MODE) == TDmode) \
333 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
335 /* Return true for floating point that does not use a vector register. */
336 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
337 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
339 /* Describe the vector unit used for arithmetic operations. */
340 extern enum rs6000_vector rs6000_vector_unit[];
342 #define VECTOR_UNIT_NONE_P(MODE) \
343 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
345 #define VECTOR_UNIT_VSX_P(MODE) \
346 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
348 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
349 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
351 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
352 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
354 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
355 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
357 (int)VECTOR_P8_VECTOR))
359 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
360 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
361 compatible, so allow it as well, rather than changing all of the uses of the
363 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
364 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
365 (int)VECTOR_ALTIVEC, \
366 (int)VECTOR_P8_VECTOR))
368 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
369 same unit as the vector unit we are using, but we may want to migrate to
370 using VSX style loads even for types handled by altivec. */
371 extern enum rs6000_vector rs6000_vector_mem[];
373 #define VECTOR_MEM_NONE_P(MODE) \
374 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
376 #define VECTOR_MEM_VSX_P(MODE) \
377 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
379 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
380 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
382 #define VECTOR_MEM_ALTIVEC_P(MODE) \
383 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
385 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
386 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
388 (int)VECTOR_P8_VECTOR))
390 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
391 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
392 (int)VECTOR_ALTIVEC, \
393 (int)VECTOR_P8_VECTOR))
395 /* Return the alignment of a given vector type, which is set based on the
396 vector unit use. VSX for instance can load 32 or 64 bit aligned words
397 without problems, while Altivec requires 128-bit aligned vectors. */
398 extern int rs6000_vector_align[];
400 #define VECTOR_ALIGN(MODE) \
401 ((rs6000_vector_align[(MODE)] != 0) \
402 ? rs6000_vector_align[(MODE)] \
403 : (int)GET_MODE_BITSIZE ((MODE)))
405 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
406 with scalar instructions. */
407 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
409 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
410 with the ISA 3.0 MFVSRLD instructions. */
411 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
413 /* Alignment options for fields in structures for sub-targets following
415 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
416 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
418 Override the macro definitions when compiling libobjc to avoid undefined
419 reference to rs6000_alignment_flags due to library's use of GCC alignment
420 macros which use the macros below. */
422 #ifndef IN_TARGET_LIBS
423 #define MASK_ALIGN_POWER 0x00000000
424 #define MASK_ALIGN_NATURAL 0x00000001
425 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
427 #define TARGET_ALIGN_NATURAL 0
430 /* We use values 126..128 to pick the appropriate long double type (IFmode,
432 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
433 #define TARGET_IEEEQUAD rs6000_ieeequad
434 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
435 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
437 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
438 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
439 #define TARGET_FCFID (TARGET_POWERPC64 \
440 || TARGET_PPC_GPOPT /* 970/power4 */ \
441 || TARGET_POPCNTB /* ISA 2.02 */ \
442 || TARGET_CMPB /* ISA 2.05 */ \
443 || TARGET_POPCNTD) /* ISA 2.06 */
445 #define TARGET_FCTIDZ TARGET_FCFID
446 #define TARGET_STFIWX TARGET_PPC_GFXOPT
447 #define TARGET_LFIWAX TARGET_CMPB
448 #define TARGET_LFIWZX TARGET_POPCNTD
449 #define TARGET_FCFIDS TARGET_POPCNTD
450 #define TARGET_FCFIDU TARGET_POPCNTD
451 #define TARGET_FCFIDUS TARGET_POPCNTD
452 #define TARGET_FCTIDUZ TARGET_POPCNTD
453 #define TARGET_FCTIWUZ TARGET_POPCNTD
454 #define TARGET_CTZ TARGET_MODULO
455 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
456 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
458 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
459 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
460 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
461 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
463 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
466 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
467 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
468 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
470 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
472 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
474 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
475 in power7, so conditionalize them on p8 features. TImode syncs need quad
477 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
478 || TARGET_QUAD_MEMORY_ATOMIC \
479 || TARGET_DIRECT_MOVE)
481 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
483 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
484 to allocate the SDmode stack slot to get the value into the proper location
486 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
488 /* ISA 3.0 has new min/max functions that don't need fast math that are being
489 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
490 answers if the arguments are not in the normal range. */
491 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
492 && (TARGET_P9_MINMAX || !flag_trapping_math))
494 /* In switching from using target_flags to using rs6000_isa_flags, the options
495 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
496 OPTION_MASK_<xxx> back into MASK_<xxx>. */
497 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
498 #define MASK_CMPB OPTION_MASK_CMPB
499 #define MASK_CRYPTO OPTION_MASK_CRYPTO
500 #define MASK_DFP OPTION_MASK_DFP
501 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
502 #define MASK_DLMZB OPTION_MASK_DLMZB
503 #define MASK_EABI OPTION_MASK_EABI
504 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
505 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
506 #define MASK_FPRND OPTION_MASK_FPRND
507 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
508 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
509 #define MASK_HTM OPTION_MASK_HTM
510 #define MASK_ISEL OPTION_MASK_ISEL
511 #define MASK_MFCRF OPTION_MASK_MFCRF
512 #define MASK_MFPGPR OPTION_MASK_MFPGPR
513 #define MASK_MULHW OPTION_MASK_MULHW
514 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
515 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
516 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
517 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
518 #define MASK_P9_MISC OPTION_MASK_P9_MISC
519 #define MASK_POPCNTB OPTION_MASK_POPCNTB
520 #define MASK_POPCNTD OPTION_MASK_POPCNTD
521 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
522 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
523 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
524 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
525 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
526 #define MASK_UPDATE OPTION_MASK_UPDATE
527 #define MASK_VSX OPTION_MASK_VSX
528 #define MASK_FUTURE OPTION_MASK_FUTURE
531 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
535 #define MASK_64BIT OPTION_MASK_64BIT
538 #ifdef TARGET_LITTLE_ENDIAN
539 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
542 #ifdef TARGET_REGNAMES
543 #define MASK_REGNAMES OPTION_MASK_REGNAMES
546 #ifdef TARGET_PROTOTYPE
547 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
551 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
555 /* For power systems, we want to enable Altivec and VSX builtins even if the
556 user did not use -maltivec or -mvsx to allow the builtins to be used inside
557 of #pragma GCC target or the target attribute to change the code level for a
560 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
561 || TARGET_PPC_GPOPT /* 970/power4 */ \
562 || TARGET_POPCNTB /* ISA 2.02 */ \
563 || TARGET_CMPB /* ISA 2.05 */ \
564 || TARGET_POPCNTD /* ISA 2.06 */ \
567 || TARGET_HARD_FLOAT)
569 /* E500 cores only support plain "sync", not lwsync. */
570 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
571 || rs6000_cpu == PROCESSOR_PPC8548)
574 /* Which machine supports the various reciprocal estimate instructions. */
575 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
577 #define TARGET_FRE (TARGET_HARD_FLOAT \
578 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
580 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
581 && TARGET_PPC_GFXOPT)
583 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
584 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
586 /* Macro to say whether we can do optimizations where we need to do parts of
587 the calculation in 64-bit GPRs and then is transfered to the vector
589 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
590 && TARGET_P8_VECTOR \
593 /* Whether the various reciprocal divide/square root estimate instructions
594 exist, and whether we should automatically generate code for the instruction
596 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
597 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
598 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
599 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
601 extern unsigned char rs6000_recip_bits[];
603 #define RS6000_RECIP_HAVE_RE_P(MODE) \
604 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
606 #define RS6000_RECIP_AUTO_RE_P(MODE) \
607 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
609 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
610 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
612 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
613 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
615 /* The default CPU for TARGET_OPTION_OVERRIDE. */
616 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
619 #define REGISTER_TARGET_PRAGMAS() do { \
620 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
621 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
622 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
623 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
626 /* Target #defines. */
627 #define TARGET_CPU_CPP_BUILTINS() \
628 rs6000_cpu_cpp_builtins (pfile)
630 /* Target CPU versions for D. */
631 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions
633 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
634 we're compiling for. Some configurations may need to override it. */
635 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
638 if (BYTES_BIG_ENDIAN) \
640 builtin_define ("__BIG_ENDIAN__"); \
641 builtin_define ("_BIG_ENDIAN"); \
642 builtin_assert ("machine=bigendian"); \
646 builtin_define ("__LITTLE_ENDIAN__"); \
647 builtin_define ("_LITTLE_ENDIAN"); \
648 builtin_assert ("machine=littleendian"); \
653 /* Target machine storage layout. */
655 /* Define this macro if it is advisable to hold scalars in registers
656 in a wider mode than that declared by the program. In such cases,
657 the value is constrained to be within the bounds of the declared
658 type, but kept valid in the wider mode. The signedness of the
659 extension may differ from that of the type. */
661 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
662 if (GET_MODE_CLASS (MODE) == MODE_INT \
663 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
664 (MODE) = TARGET_32BIT ? SImode : DImode;
666 /* Define this if most significant bit is lowest numbered
667 in instructions that operate on numbered bit-fields. */
668 /* That is true on RS/6000. */
669 #define BITS_BIG_ENDIAN 1
671 /* Define this if most significant byte of a word is the lowest numbered. */
672 /* That is true on RS/6000. */
673 #define BYTES_BIG_ENDIAN 1
675 /* Define this if most significant word of a multiword number is lowest
678 For RS/6000 we can decide arbitrarily since there are no machine
679 instructions for them. Might as well be consistent with bits and bytes. */
680 #define WORDS_BIG_ENDIAN 1
682 /* This says that for the IBM long double the larger magnitude double
683 comes first. It's really a two element double array, and arrays
684 don't index differently between little- and big-endian. */
685 #define LONG_DOUBLE_LARGE_FIRST 1
687 #define MAX_BITS_PER_WORD 64
689 /* Width of a word, in units (bytes). */
690 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
692 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
694 #define MIN_UNITS_PER_WORD 4
696 #define UNITS_PER_FP_WORD 8
697 #define UNITS_PER_ALTIVEC_WORD 16
698 #define UNITS_PER_VSX_WORD 16
700 /* Type used for ptrdiff_t, as a string used in a declaration. */
701 #define PTRDIFF_TYPE "int"
703 /* Type used for size_t, as a string used in a declaration. */
704 #define SIZE_TYPE "long unsigned int"
706 /* Type used for wchar_t, as a string used in a declaration. */
707 #define WCHAR_TYPE "short unsigned int"
709 /* Width of wchar_t in bits. */
710 #define WCHAR_TYPE_SIZE 16
712 /* A C expression for the size in bits of the type `short' on the
713 target machine. If you don't define this, the default is half a
714 word. (If this would be less than one storage unit, it is
715 rounded up to one unit.) */
716 #define SHORT_TYPE_SIZE 16
718 /* A C expression for the size in bits of the type `int' on the
719 target machine. If you don't define this, the default is one
721 #define INT_TYPE_SIZE 32
723 /* A C expression for the size in bits of the type `long' on the
724 target machine. If you don't define this, the default is one
726 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
728 /* A C expression for the size in bits of the type `long long' on the
729 target machine. If you don't define this, the default is two
731 #define LONG_LONG_TYPE_SIZE 64
733 /* A C expression for the size in bits of the type `float' on the
734 target machine. If you don't define this, the default is one
736 #define FLOAT_TYPE_SIZE 32
738 /* A C expression for the size in bits of the type `double' on the
739 target machine. If you don't define this, the default is two
741 #define DOUBLE_TYPE_SIZE 64
743 /* A C expression for the size in bits of the type `long double' on the target
744 machine. If you don't define this, the default is two words. */
745 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
747 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
748 #define WIDEST_HARDWARE_FP_SIZE 64
750 /* Width in bits of a pointer.
751 See also the macro `Pmode' defined below. */
752 extern unsigned rs6000_pointer_size;
753 #define POINTER_SIZE rs6000_pointer_size
755 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
756 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
758 /* Boundary (in *bits*) on which stack pointer should be aligned. */
759 #define STACK_BOUNDARY \
760 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
763 /* Allocation boundary (in *bits*) for the code of a function. */
764 #define FUNCTION_BOUNDARY 32
766 /* No data type wants to be aligned rounder than this. */
767 #define BIGGEST_ALIGNMENT 128
769 /* Alignment of field after `int : 0' in a structure. */
770 #define EMPTY_FIELD_BOUNDARY 32
772 /* Every structure's size must be a multiple of this. */
773 #define STRUCTURE_SIZE_BOUNDARY 8
775 /* A bit-field declared as `int' forces `int' alignment for the struct. */
776 #define PCC_BITFIELD_TYPE_MATTERS 1
778 enum data_align { align_abi, align_opt, align_both };
780 /* A C expression to compute the alignment for a variables in the
781 local store. TYPE is the data type, and ALIGN is the alignment
782 that the object would ordinarily have. */
783 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
784 rs6000_data_alignment (TYPE, ALIGN, align_both)
786 /* Make arrays of chars word-aligned for the same reasons. */
787 #define DATA_ALIGNMENT(TYPE, ALIGN) \
788 rs6000_data_alignment (TYPE, ALIGN, align_opt)
790 /* Align vectors to 128 bits. */
791 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
792 rs6000_data_alignment (TYPE, ALIGN, align_abi)
794 /* Nonzero if move instructions will actually fail to work
795 when given unaligned data. */
796 #define STRICT_ALIGNMENT 0
798 /* Standard register usage. */
800 /* Number of actual hardware registers.
801 The hardware registers are assigned numbers for the compiler
802 from 0 to just below FIRST_PSEUDO_REGISTER.
803 All registers that the compiler knows about must be given numbers,
804 even those that are not normally considered general registers.
806 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
807 a count register, a link register, and 8 condition register fields,
808 which we view here as separate registers. AltiVec adds 32 vector
809 registers and a VRsave register.
811 In addition, the difference between the frame and argument pointers is
812 a function of the number of registers saved, so we need to have a
813 register for AP that will later be eliminated in favor of SP or FP.
814 This is a normal register, but it is fixed.
816 We also create a pseudo register for float/int conversions, that will
817 really represent the memory location used. It is represented here as
818 a register, in order to work around problems in allocating stack storage
821 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
822 pointer, which is eventually eliminated in favor of SP or FP. */
824 #define FIRST_PSEUDO_REGISTER 111
826 /* Use standard DWARF numbering for DWARF debugging information. */
827 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
829 /* Use gcc hard register numbering for eh_frame. */
830 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
832 /* Map register numbers held in the call frame info that gcc has
833 collected using DWARF_FRAME_REGNUM to those that should be output in
834 .debug_frame and .eh_frame. */
835 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
836 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1)
838 /* 1 for registers that have pervasive standard uses
839 and are not available for the register allocator.
841 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
842 as a local register; for all other OS's r2 is the TOC pointer.
844 On System V implementations, r13 is fixed and not available for use. */
846 #define FIXED_REGISTERS \
848 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
849 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
851 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
852 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
855 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
859 0, 0, 0, 0, 0, 0, 0, 0, \
860 /* vrsave vscr sfp */ \
864 /* 1 for registers not available across function calls.
865 These must include the FIXED_REGISTERS and also any
866 registers that can be used without being saved.
867 The latter must include the registers where values are returned
868 and the register where structure-value addresses are passed.
869 Aside from that, you can include as many other registers as you like. */
871 #define CALL_USED_REGISTERS \
873 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
874 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
876 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
877 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
880 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
884 1, 1, 0, 0, 0, 1, 1, 1, \
885 /* vrsave vscr sfp */ \
889 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
890 the entire set of `FIXED_REGISTERS' be included.
891 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
892 This macro is optional. If not specified, it defaults to the value
893 of `CALL_USED_REGISTERS'. */
895 #define CALL_REALLY_USED_REGISTERS \
897 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
900 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
903 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
904 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
908 1, 1, 0, 0, 0, 1, 1, 1, \
909 /* vrsave vscr sfp */ \
913 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
915 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
916 #define FIRST_SAVED_FP_REGNO (14+32)
917 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
919 /* List the order in which to allocate registers. Each register must be
920 listed once, even those in FIXED_REGISTERS.
922 We allocate in the following order:
923 fp0 (not saved or used for anything)
924 fp13 - fp2 (not saved; incoming fp arg registers)
925 fp1 (not saved; return value)
926 fp31 - fp14 (saved; order given to save least number)
927 cr7, cr5 (not saved or special)
928 cr6 (not saved, but used for vector operations)
929 cr1 (not saved, but used for FP operations)
930 cr0 (not saved, but used for arithmetic operations)
931 cr4, cr3, cr2 (saved)
932 r9 (not saved; best for TImode)
933 r10, r8-r4 (not saved; highest first for less conflict with params)
934 r3 (not saved; return value register)
935 r11 (not saved; later alloc to help shrink-wrap)
936 r0 (not saved; cannot be base reg)
937 r31 - r13 (saved; order given to save least number)
938 r12 (not saved; if used for DImode or DFmode would use r13)
939 ctr (not saved; when we have the choice ctr is better)
941 r1, r2, ap, ca (fixed)
942 v0 - v1 (not saved or used for anything)
943 v13 - v3 (not saved; incoming vector arg registers)
944 v2 (not saved; incoming vector arg reg; return value)
945 v19 - v14 (not saved or used for anything)
946 v31 - v20 (saved; order given to save least number)
952 #define MAYBE_R2_AVAILABLE
953 #define MAYBE_R2_FIXED 2,
955 #define MAYBE_R2_AVAILABLE 2,
956 #define MAYBE_R2_FIXED
960 #define EARLY_R12 12,
967 #define REG_ALLOC_ORDER \
969 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
970 /* not use fr14 which is a saved register. */ \
971 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
973 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
974 50, 49, 48, 47, 46, \
975 100, 107, 105, 106, 101, 104, 103, 102, \
977 9, 10, 8, 7, 6, 5, 4, \
978 3, EARLY_R12 11, 0, \
979 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
980 18, 17, 16, 15, 14, 13, LATE_R12 \
982 1, MAYBE_R2_FIXED 99, 98, \
983 /* AltiVec registers. */ \
985 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \
987 83, 82, 81, 80, 79, 78, \
988 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \
993 /* True if register is floating-point. */
994 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
996 /* True if register is a condition register. */
997 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
999 /* True if register is a condition register, but not cr0. */
1000 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1002 /* True if register is an integer register. */
1003 #define INT_REGNO_P(N) \
1004 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1006 /* True if register is the CA register. */
1007 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1009 /* True if register is an AltiVec register. */
1010 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1012 /* True if register is a VSX register. */
1013 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1015 /* Alternate name for any vector register supporting floating point, no matter
1016 which instruction set(s) are available. */
1017 #define VFLOAT_REGNO_P(N) \
1018 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1020 /* Alternate name for any vector register supporting integer, no matter which
1021 instruction set(s) are available. */
1022 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1024 /* Alternate name for any vector register supporting logical operations, no
1025 matter which instruction set(s) are available. Allow GPRs as well as the
1026 vector registers. */
1027 #define VLOGICAL_REGNO_P(N) \
1028 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1029 || (TARGET_VSX && FP_REGNO_P (N))) \
1031 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1032 enough space to account for vectors in FP regs. However, TFmode/TDmode
1033 should not use VSX instructions to do a caller save. */
1034 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1035 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1038 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1039 && FP_REGNO_P (REGNO) \
1041 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1043 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
1045 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1047 #define VSX_VECTOR_MODE(MODE) \
1048 ((MODE) == V4SFmode \
1049 || (MODE) == V2DFmode) \
1051 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1052 really a vector, but we want to treat it as a vector for moves, and
1055 #define ALTIVEC_VECTOR_MODE(MODE) \
1056 ((MODE) == V16QImode \
1057 || (MODE) == V8HImode \
1058 || (MODE) == V4SFmode \
1059 || (MODE) == V4SImode \
1060 || FLOAT128_VECTOR_P (MODE))
1062 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1063 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1064 || (MODE) == V2DImode || (MODE) == V1TImode)
1066 /* Post-reload, we can't use any new AltiVec registers, as we already
1067 emitted the vrsave mask. */
1069 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1070 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1072 /* Specify the cost of a branch insn; roughly the number of extra insns that
1073 should be added to avoid a branch.
1075 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1076 unscheduled conditional branch. */
1078 #define BRANCH_COST(speed_p, predictable_p) 3
1080 /* Override BRANCH_COST heuristic which empirically produces worse
1081 performance for removing short circuiting from the logical ops. */
1083 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1085 /* Specify the registers used for certain standard purposes.
1086 The values of these macros are register numbers. */
1088 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1089 /* #define PC_REGNUM */
1091 /* Register to use for pushing function arguments. */
1092 #define STACK_POINTER_REGNUM 1
1094 /* Base register for access to local variables of the function. */
1095 #define HARD_FRAME_POINTER_REGNUM 31
1097 /* Base register for access to local variables of the function. */
1098 #define FRAME_POINTER_REGNUM 110
1100 /* Base register for access to arguments of the function. */
1101 #define ARG_POINTER_REGNUM 99
1103 /* Place to put static chain when calling a function that requires it. */
1104 #define STATIC_CHAIN_REGNUM 11
1106 /* Base register for access to thread local storage variables. */
1107 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1110 /* Define the classes of registers for register constraints in the
1111 machine description. Also define ranges of constants.
1113 One of the classes must always be named ALL_REGS and include all hard regs.
1114 If there is more than one class, another class must be named NO_REGS
1115 and contain no registers.
1117 The name GENERAL_REGS must be the name of a class (or an alias for
1118 another name such as ALL_REGS). This is the class of registers
1119 that is allowed by "g" or "r" in a register constraint.
1120 Also, registers outside this class are allocated only when
1121 instructions express preferences for them.
1123 The classes must be numbered in nondecreasing order; that is,
1124 a larger-numbered class must never be contained completely
1125 in a smaller-numbered class.
1127 For any two classes, it is very desirable that there be another
1128 class that represents their union. */
1130 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1131 condition registers, plus three special registers, CTR, and the link
1132 register. AltiVec adds a vector register class. VSX registers overlap the
1133 FPR registers and the Altivec registers.
1135 However, r0 is special in that it cannot be used as a base register.
1136 So make a class for registers valid as base registers.
1138 Also, cr0 is the only condition code register that can be used in
1139 arithmetic insns, so make a separate class for it. */
1166 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1168 /* Give names of register classes as strings for dump file. */
1170 #define REG_CLASS_NAMES \
1180 "GEN_OR_FLOAT_REGS", \
1181 "GEN_OR_VSX_REGS", \
1184 "LINK_OR_CTR_REGS", \
1186 "SPEC_OR_GEN_REGS", \
1194 /* Define which registers fit in which classes.
1195 This is an initializer for a vector of HARD_REG_SET
1196 of length N_REG_CLASSES. */
1198 #define REG_CLASS_CONTENTS \
1201 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1203 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \
1204 /* GENERAL_REGS. */ \
1205 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \
1207 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1208 /* ALTIVEC_REGS. */ \
1209 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \
1211 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1212 /* VRSAVE_REGS. */ \
1213 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \
1215 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1216 /* GEN_OR_FLOAT_REGS. */ \
1217 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \
1218 /* GEN_OR_VSX_REGS. */ \
1219 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \
1221 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \
1223 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \
1224 /* LINK_OR_CTR_REGS. */ \
1225 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \
1226 /* SPECIAL_REGS. */ \
1227 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \
1228 /* SPEC_OR_GEN_REGS. */ \
1229 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \
1231 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \
1233 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \
1234 /* NON_FLOAT_REGS. */ \
1235 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \
1237 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
1239 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
1242 /* The same information, inverted:
1243 Return the class number of the smallest class containing
1244 reg number REGNO. This could be a conditional expression
1245 or could index an array. */
1247 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1249 #define REGNO_REG_CLASS(REGNO) \
1250 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1251 rs6000_regno_regclass[(REGNO)])
1253 /* Register classes for various constraints that are based on the target
1255 enum r6000_reg_class_enum {
1256 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1257 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1258 RS6000_CONSTRAINT_v, /* Altivec registers */
1259 RS6000_CONSTRAINT_wa, /* Any VSX register */
1260 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1261 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
1262 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1263 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
1264 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
1265 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
1266 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
1267 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1268 RS6000_CONSTRAINT_wt, /* VSX register for TImode */
1269 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
1270 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
1271 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
1272 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
1273 RS6000_CONSTRAINT_MAX
1276 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1278 /* The class value for index registers, and the one for base regs. */
1279 #define INDEX_REG_CLASS GENERAL_REGS
1280 #define BASE_REG_CLASS BASE_REGS
1282 /* Return whether a given register class can hold VSX objects. */
1283 #define VSX_REG_CLASS_P(CLASS) \
1284 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1286 /* Return whether a given register class targets general purpose registers. */
1287 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1289 /* Given an rtx X being reloaded into a reg required to be
1290 in class CLASS, return the class of reg to actually use.
1291 In general this is just CLASS; but on some machines
1292 in some cases it is preferable to use a more restrictive class.
1294 On the RS/6000, we have to return NO_REGS when we want to reload a
1295 floating-point CONST_DOUBLE to force it to be copied to memory.
1297 We also don't want to reload integer values into floating-point
1298 registers if we can at all help it. In fact, this can
1299 cause reload to die, if it tries to generate a reload of CTR
1300 into a FP register and discovers it doesn't have the memory location
1303 ??? Would it be a good idea to have reload do the converse, that is
1304 try to reload floating modes into FP registers if possible?
1307 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1308 rs6000_preferred_reload_class_ptr (X, CLASS)
1310 /* Return the register class of a scratch register needed to copy IN into
1311 or out of a register in CLASS in MODE. If it can be done directly,
1312 NO_REGS is returned. */
1314 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1315 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1317 /* Return the maximum number of consecutive registers
1318 needed to represent mode MODE in a register of class CLASS.
1320 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1321 a single reg is enough for two words, unless we have VSX, where the FP
1322 registers can hold 128 bits. */
1323 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1325 /* Stack layout; function entry, exit and calling. */
1327 /* Define this if pushing a word on the stack
1328 makes the stack pointer a smaller address. */
1329 #define STACK_GROWS_DOWNWARD 1
1331 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1332 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1334 /* Define this to nonzero if the nominal address of the stack frame
1335 is at the high-address end of the local variables;
1336 that is, each additional local variable allocated
1337 goes at a more negative offset in the frame.
1339 On the RS/6000, we grow upwards, from the area after the outgoing
1341 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1342 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1344 /* Size of the fixed area on the stack */
1345 #define RS6000_SAVE_AREA \
1346 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1347 << (TARGET_64BIT ? 1 : 0))
1349 /* Stack offset for toc save slot. */
1350 #define RS6000_TOC_SAVE_SLOT \
1351 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1353 /* Align an address */
1354 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1356 /* Offset within stack frame to start allocating local variables at.
1357 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1358 first local allocated. Otherwise, it is the offset to the BEGINNING
1359 of the first local allocated.
1361 On the RS/6000, the frame pointer is the same as the stack pointer,
1362 except for dynamic allocations. So we start after the fixed area and
1363 outgoing parameter area.
1365 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1366 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1367 sizes of the fixed area and the parameter area must be a multiple of
1370 #define RS6000_STARTING_FRAME_OFFSET \
1371 (cfun->calls_alloca \
1372 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1373 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1374 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1375 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1376 + RS6000_SAVE_AREA))
1378 /* Offset from the stack pointer register to an item dynamically
1379 allocated on the stack, e.g., by `alloca'.
1381 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1382 length of the outgoing arguments. The default is correct for most
1383 machines. See `function.c' for details.
1385 This value must be a multiple of STACK_BOUNDARY (hard coded in
1387 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1388 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1389 + STACK_POINTER_OFFSET, \
1390 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1392 /* If we generate an insn to push BYTES bytes,
1393 this says how many the stack pointer really advances by.
1394 On RS/6000, don't define this because there are no push insns. */
1395 /* #define PUSH_ROUNDING(BYTES) */
1397 /* Offset of first parameter from the argument pointer register value.
1398 On the RS/6000, we define the argument pointer to the start of the fixed
1400 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1402 /* Offset from the argument pointer register value to the top of
1403 stack. This is different from FIRST_PARM_OFFSET because of the
1404 register save area. */
1405 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1407 /* Define this if stack space is still allocated for a parameter passed
1408 in a register. The value is the number of bytes allocated to this
1410 #define REG_PARM_STACK_SPACE(FNDECL) \
1411 rs6000_reg_parm_stack_space ((FNDECL), false)
1413 /* Define this macro if space guaranteed when compiling a function body
1414 is different to space required when making a call, a situation that
1415 can arise with K&R style function definitions. */
1416 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1417 rs6000_reg_parm_stack_space ((FNDECL), true)
1419 /* Define this if the above stack space is to be considered part of the
1420 space allocated by the caller. */
1421 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1423 /* This is the difference between the logical top of stack and the actual sp.
1425 For the RS/6000, sp points past the fixed area. */
1426 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1428 /* Define this if the maximum size of all the outgoing args is to be
1429 accumulated and pushed during the prologue. The amount can be
1430 found in the variable crtl->outgoing_args_size. */
1431 #define ACCUMULATE_OUTGOING_ARGS 1
1433 /* Define how to find the value returned by a library function
1434 assuming the value has mode MODE. */
1436 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1438 /* DRAFT_V4_STRUCT_RET defaults off. */
1439 #define DRAFT_V4_STRUCT_RET 0
1441 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1442 #define DEFAULT_PCC_STRUCT_RETURN 0
1444 /* Mode of stack savearea.
1445 FUNCTION is VOIDmode because calling convention maintains SP.
1446 BLOCK needs Pmode for SP.
1447 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1448 #define STACK_SAVEAREA_MODE(LEVEL) \
1449 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1450 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1452 /* Minimum and maximum general purpose registers used to hold arguments. */
1453 #define GP_ARG_MIN_REG 3
1454 #define GP_ARG_MAX_REG 10
1455 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1457 /* Minimum and maximum floating point registers used to hold arguments. */
1458 #define FP_ARG_MIN_REG 33
1459 #define FP_ARG_AIX_MAX_REG 45
1460 #define FP_ARG_V4_MAX_REG 40
1461 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1462 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1463 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1465 /* Minimum and maximum AltiVec registers used to hold arguments. */
1466 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1467 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1468 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1470 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1471 #define AGGR_ARG_NUM_REG 8
1473 /* Return registers */
1474 #define GP_ARG_RETURN GP_ARG_MIN_REG
1475 #define FP_ARG_RETURN FP_ARG_MIN_REG
1476 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1477 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1478 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1479 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1480 ? (ALTIVEC_ARG_RETURN \
1481 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1482 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1484 /* Flags for the call/call_value rtl operations set up by function_arg */
1485 #define CALL_NORMAL 0x00000000 /* no special processing */
1486 /* Bits in 0x00000001 are unused. */
1487 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1488 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1489 #define CALL_LONG 0x00000008 /* always call indirect */
1490 #define CALL_LIBCALL 0x00000010 /* libcall */
1492 /* Identify PLT sequence for rs6000_pltseq_template. */
1493 enum rs6000_pltseq_enum {
1494 RS6000_PLTSEQ_TOCSAVE,
1495 RS6000_PLTSEQ_PLT16_HA,
1496 RS6000_PLTSEQ_PLT16_LO,
1497 RS6000_PLTSEQ_MTCTR,
1498 RS6000_PLTSEQ_PLT_PCREL34
1501 #define IS_V4_FP_ARGS(OP) \
1502 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0)
1504 /* Whether OP is an UNSPEC used in !TARGET_TLS_MARKER calls. */
1505 #define IS_NOMARK_TLSGETADDR(OP) \
1506 (!TARGET_TLS_MARKERS \
1507 && GET_CODE (OP) == UNSPEC \
1508 && (XINT (OP, 1) == UNSPEC_TLSGD \
1509 || XINT (OP, 1) == UNSPEC_TLSLD))
1511 /* We don't have prologue and epilogue functions to save/restore
1512 everything for most ABIs. */
1513 #define WORLD_SAVE_P(INFO) 0
1515 /* 1 if N is a possible register number for a function value
1516 as seen by the caller.
1518 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1519 #define FUNCTION_VALUE_REGNO_P(N) \
1520 ((N) == GP_ARG_RETURN \
1521 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1522 && TARGET_HARD_FLOAT) \
1523 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1524 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1526 /* 1 if N is a possible register number for function argument passing.
1527 On RS/6000, these are r3-r10 and fp1-fp13.
1528 On AltiVec, v2 - v13 are used for passing vectors. */
1529 #define FUNCTION_ARG_REGNO_P(N) \
1530 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1531 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1532 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1533 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1534 && TARGET_HARD_FLOAT))
1536 /* Define a data type for recording info about an argument list
1537 during the scan of that argument list. This data type should
1538 hold all necessary information about the function itself
1539 and about the args processed so far, enough to enable macros
1540 such as FUNCTION_ARG to determine where the next arg should go.
1542 On the RS/6000, this is a structure. The first element is the number of
1543 total argument words, the second is used to store the next
1544 floating-point register number, and the third says how many more args we
1545 have prototype types for.
1547 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1548 the next available GP register, `fregno' is the next available FP
1549 register, and `words' is the number of words used on the stack.
1551 The varargs/stdarg support requires that this structure's size
1552 be a multiple of sizeof(int). */
1554 typedef struct rs6000_args
1556 int words; /* # words used for passing GP registers */
1557 int fregno; /* next available FP register */
1558 int vregno; /* next available AltiVec register */
1559 int nargs_prototype; /* # args left in the current prototype */
1560 int prototype; /* Whether a prototype was defined */
1561 int stdarg; /* Whether function is a stdarg function. */
1562 int call_cookie; /* Do special things for this call */
1563 int sysv_gregno; /* next available GP register */
1564 int intoffset; /* running offset in struct (darwin64) */
1565 int use_stack; /* any part of struct on stack (darwin64) */
1566 int floats_in_gpr; /* count of SFmode floats taking up
1567 GPR space (darwin64) */
1568 int named; /* false for varargs params */
1569 int escapes; /* if function visible outside tu */
1570 int libcall; /* If this is a compiler generated call. */
1573 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1574 for a call to a function whose data type is FNTYPE.
1575 For a library call, FNTYPE is 0. */
1577 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1578 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1579 N_NAMED_ARGS, FNDECL, VOIDmode)
1581 /* Similar, but when scanning the definition of a procedure. We always
1582 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1584 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1585 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1586 1000, current_function_decl, VOIDmode)
1588 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1590 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1591 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1594 #define PAD_VARARGS_DOWN \
1595 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1597 /* Output assembler code to FILE to increment profiler label # LABELNO
1598 for profiling a function entry. */
1600 #define FUNCTION_PROFILER(FILE, LABELNO) \
1601 output_function_profiler ((FILE), (LABELNO));
1603 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1604 the stack pointer does not matter. No definition is equivalent to
1607 On the RS/6000, this is nonzero because we can restore the stack from
1608 its backpointer, which we maintain. */
1609 #define EXIT_IGNORE_STACK 1
1611 /* Define this macro as a C expression that is nonzero for registers
1612 that are used by the epilogue or the return' pattern. The stack
1613 and frame pointer registers are already be assumed to be used as
1616 #define EPILOGUE_USES(REGNO) \
1617 ((reload_completed && (REGNO) == LR_REGNO) \
1618 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1619 || (crtl->calls_eh_return \
1624 /* Length in units of the trampoline for entering a nested function. */
1626 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1628 /* Definitions for __builtin_return_address and __builtin_frame_address.
1629 __builtin_return_address (0) should give link register (LR_REGNO), enable
1631 /* This should be uncommented, so that the link register is used, but
1632 currently this would result in unmatched insns and spilling fixed
1633 registers so we'll leave it for another day. When these problems are
1634 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1636 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1638 /* Number of bytes into the frame return addresses can be found. See
1639 rs6000_stack_info in rs6000.c for more information on how the different
1640 abi's store the return address. */
1641 #define RETURN_ADDRESS_OFFSET \
1642 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1644 /* The current return address is in the link register. The return address
1645 of anything farther back is accessed normally at an offset of 8 from the
1647 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1648 (rs6000_return_addr (COUNT, FRAME))
1651 /* Definitions for register eliminations.
1653 We have two registers that can be eliminated on the RS/6000. First, the
1654 frame pointer register can often be eliminated in favor of the stack
1655 pointer register. Secondly, the argument pointer register can always be
1656 eliminated; it is replaced with either the stack or frame pointer.
1658 In addition, we use the elimination mechanism to see if r30 is needed
1659 Initially we assume that it isn't. If it is, we spill it. This is done
1660 by making it an eliminable register. We replace it with itself so that
1661 if it isn't needed, then existing uses won't be modified. */
1663 /* This is an array of structures. Each structure initializes one pair
1664 of eliminable registers. The "from" register number is given first,
1665 followed by "to". Eliminations of the same "from" register are listed
1666 in order of preference. */
1667 #define ELIMINABLE_REGS \
1668 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1669 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1670 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1671 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1672 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1673 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1675 /* Define the offset between two registers, one to be eliminated, and the other
1676 its replacement, at the start of a routine. */
1677 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1678 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1680 /* Addressing modes, and classification of registers for them. */
1682 #define HAVE_PRE_DECREMENT 1
1683 #define HAVE_PRE_INCREMENT 1
1684 #define HAVE_PRE_MODIFY_DISP 1
1685 #define HAVE_PRE_MODIFY_REG 1
1687 /* Macros to check register numbers against specific register classes. */
1689 /* These assume that REGNO is a hard or pseudo reg number.
1690 They give nonzero only if REGNO is a hard reg of the suitable class
1691 or a pseudo reg currently allocated to a suitable hard reg.
1692 Since they use reg_renumber, they are safe only once reg_renumber
1693 has been allocated, which happens in reginfo.c during register
1696 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1697 (HARD_REGISTER_NUM_P (REGNO) \
1699 || (REGNO) == ARG_POINTER_REGNUM \
1700 || (REGNO) == FRAME_POINTER_REGNUM \
1701 : (reg_renumber[REGNO] >= 0 \
1702 && (reg_renumber[REGNO] <= 31 \
1703 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1704 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1706 #define REGNO_OK_FOR_BASE_P(REGNO) \
1707 (HARD_REGISTER_NUM_P (REGNO) \
1708 ? ((REGNO) > 0 && (REGNO) <= 31) \
1709 || (REGNO) == ARG_POINTER_REGNUM \
1710 || (REGNO) == FRAME_POINTER_REGNUM \
1711 : (reg_renumber[REGNO] > 0 \
1712 && (reg_renumber[REGNO] <= 31 \
1713 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1714 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1716 /* Nonzero if X is a hard reg that can be used as an index
1717 or if it is a pseudo reg in the non-strict case. */
1718 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1719 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1720 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1722 /* Nonzero if X is a hard reg that can be used as a base reg
1723 or if it is a pseudo reg in the non-strict case. */
1724 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1725 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1726 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1729 /* Maximum number of registers that can appear in a valid memory address. */
1731 #define MAX_REGS_PER_ADDRESS 2
1733 /* Recognize any constant value that is a valid address. */
1735 #define CONSTANT_ADDRESS_P(X) \
1736 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \
1737 || CONST_INT_P (X) || GET_CODE (X) == CONST \
1738 || GET_CODE (X) == HIGH)
1740 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1741 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1742 && EASY_VECTOR_15((n) >> 1) \
1745 #define EASY_VECTOR_MSB(n,mode) \
1746 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1747 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1750 #define FIND_BASE_TERM rs6000_find_base_term
1752 /* The register number of the register used to address a table of
1753 static data addresses in memory. In some cases this register is
1754 defined by a processor's "application binary interface" (ABI).
1755 When this macro is defined, RTL is generated for this register
1756 once, as with the stack pointer and frame pointer registers. If
1757 this macro is not defined, it is up to the machine-dependent files
1758 to allocate such a register (if necessary). */
1760 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1761 #define PIC_OFFSET_TABLE_REGNUM \
1762 (TARGET_TOC ? TOC_REGISTER \
1763 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1766 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1768 /* Define this macro if the register defined by
1769 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1770 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1772 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1774 /* A C expression that is nonzero if X is a legitimate immediate
1775 operand on the target machine when generating position independent
1776 code. You can assume that X satisfies `CONSTANT_P', so you need
1777 not check this. You can also assume FLAG_PIC is true, so you need
1778 not check it either. You need not define this macro if all
1779 constants (including `SYMBOL_REF') can be immediate operands when
1780 generating position independent code. */
1782 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1784 /* Specify the machine mode that this machine uses
1785 for the index in the tablejump instruction. */
1786 #define CASE_VECTOR_MODE SImode
1788 /* Define as C expression which evaluates to nonzero if the tablejump
1789 instruction expects the table to contain offsets from the address of the
1791 Do not define this if the table should contain absolute addresses. */
1792 #define CASE_VECTOR_PC_RELATIVE 1
1794 /* Define this as 1 if `char' should by default be signed; else as 0. */
1795 #define DEFAULT_SIGNED_CHAR 0
1797 /* An integer expression for the size in bits of the largest integer machine
1798 mode that should actually be used. */
1800 /* Allow pairs of registers to be used, which is the intent of the default. */
1801 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1803 /* Max number of bytes we can move from memory to memory
1804 in one reasonably fast instruction. */
1805 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1806 #define MAX_MOVE_MAX 8
1808 /* Nonzero if access to memory by bytes is no faster than for words.
1809 Also nonzero if doing byte operations (specifically shifts) in registers
1811 #define SLOW_BYTE_ACCESS 1
1813 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1814 will either zero-extend or sign-extend. The value of this macro should
1815 be the code that says which one of the two operations is implicitly
1816 done, UNKNOWN if none. */
1817 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1819 /* Define if loading short immediate values into registers sign extends. */
1820 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1822 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1823 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1824 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1826 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1827 zero. The hardware instructions added in Power9 and the sequences using
1828 popcount return 32 or 64. */
1829 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1830 (TARGET_CTZ || TARGET_POPCNTD \
1831 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1832 : ((VALUE) = -1, 2))
1834 /* Specify the machine mode that pointers have.
1835 After generation of rtl, the compiler makes no further distinction
1836 between pointers and any other objects of this machine mode. */
1837 extern scalar_int_mode rs6000_pmode;
1838 #define Pmode rs6000_pmode
1840 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1841 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1843 /* Mode of a function address in a call instruction (for indexing purposes).
1844 Doesn't matter on RS/6000. */
1845 #define FUNCTION_MODE SImode
1847 /* Define this if addresses of constant functions
1848 shouldn't be put through pseudo regs where they can be cse'd.
1849 Desirable on machines where ordinary constants are expensive
1850 but a CALL with constant address is cheap. */
1851 #define NO_FUNCTION_CSE 1
1853 /* Define this to be nonzero if shift instructions ignore all but the low-order
1856 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1857 have been dropped from the PowerPC architecture. */
1858 #define SHIFT_COUNT_TRUNCATED 0
1860 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1861 should be adjusted to reflect any required changes. This macro is used when
1862 there is some systematic length adjustment required that would be difficult
1863 to express in the length attribute. */
1865 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1867 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1868 COMPARE, return the mode to be used for the comparison. For
1869 floating-point, CCFPmode should be used. CCUNSmode should be used
1870 for unsigned comparisons. CCEQmode should be used when we are
1871 doing an inequality comparison on the result of a
1872 comparison. CCmode should be used in all other cases. */
1874 #define SELECT_CC_MODE(OP,X,Y) \
1875 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1876 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1877 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1878 ? CCEQmode : CCmode))
1880 /* Can the condition code MODE be safely reversed? This is safe in
1881 all cases on this port, because at present it doesn't use the
1882 trapping FP comparisons (fcmpo). */
1883 #define REVERSIBLE_CC_MODE(MODE) 1
1885 /* Given a condition code and a mode, return the inverse condition. */
1886 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1889 /* Target cpu costs. */
1891 struct processor_costs {
1892 const int mulsi; /* cost of SImode multiplication. */
1893 const int mulsi_const; /* cost of SImode multiplication by constant. */
1894 const int mulsi_const9; /* cost of SImode mult by short constant. */
1895 const int muldi; /* cost of DImode multiplication. */
1896 const int divsi; /* cost of SImode division. */
1897 const int divdi; /* cost of DImode division. */
1898 const int fp; /* cost of simple SFmode and DFmode insns. */
1899 const int dmul; /* cost of DFmode multiplication (and fmadd). */
1900 const int sdiv; /* cost of SFmode division (fdivs). */
1901 const int ddiv; /* cost of DFmode division (fdiv). */
1902 const int cache_line_size; /* cache line size in bytes. */
1903 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
1904 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
1905 const int simultaneous_prefetches; /* number of parallel prefetch
1907 const int sfdf_convert; /* cost of SF->DF conversion. */
1910 extern const struct processor_costs *rs6000_cost;
1912 /* Control the assembler format that we output. */
1914 /* A C string constant describing how to begin a comment in the target
1915 assembler language. The compiler assumes that the comment will end at
1916 the end of the line. */
1917 #define ASM_COMMENT_START " #"
1919 /* Flag to say the TOC is initialized */
1920 extern int toc_initialized;
1922 /* Macro to output a special constant pool entry. Go to WIN if we output
1923 it. Otherwise, it is written the usual way.
1925 On the RS/6000, toc entries are handled this way. */
1927 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1928 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1930 output_toc (FILE, X, LABELNO, MODE); \
1935 #ifdef HAVE_GAS_WEAK
1936 #define RS6000_WEAK 1
1938 #define RS6000_WEAK 0
1942 /* Used in lieu of ASM_WEAKEN_LABEL. */
1943 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1944 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
1947 #if HAVE_GAS_WEAKREF
1948 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1951 fputs ("\t.weakref\t", (FILE)); \
1952 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1953 fputs (", ", (FILE)); \
1954 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1955 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1956 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1958 fputs ("\n\t.weakref\t.", (FILE)); \
1959 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1960 fputs (", .", (FILE)); \
1961 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1963 fputc ('\n', (FILE)); \
1967 /* This implements the `alias' attribute. */
1968 #undef ASM_OUTPUT_DEF_FROM_DECLS
1969 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1972 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1973 const char *name = IDENTIFIER_POINTER (TARGET); \
1974 if (TREE_CODE (DECL) == FUNCTION_DECL \
1975 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1977 if (TREE_PUBLIC (DECL)) \
1979 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1981 fputs ("\t.globl\t.", FILE); \
1982 RS6000_OUTPUT_BASENAME (FILE, alias); \
1983 putc ('\n', FILE); \
1986 else if (TARGET_XCOFF) \
1988 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1990 fputs ("\t.lglobl\t.", FILE); \
1991 RS6000_OUTPUT_BASENAME (FILE, alias); \
1992 putc ('\n', FILE); \
1993 fputs ("\t.lglobl\t", FILE); \
1994 RS6000_OUTPUT_BASENAME (FILE, alias); \
1995 putc ('\n', FILE); \
1998 fputs ("\t.set\t.", FILE); \
1999 RS6000_OUTPUT_BASENAME (FILE, alias); \
2000 fputs (",.", FILE); \
2001 RS6000_OUTPUT_BASENAME (FILE, name); \
2002 fputc ('\n', FILE); \
2004 ASM_OUTPUT_DEF (FILE, alias, name); \
2008 #define TARGET_ASM_FILE_START rs6000_file_start
2010 /* Output to assembler file text saying following lines
2011 may contain character constants, extra white space, comments, etc. */
2013 #define ASM_APP_ON ""
2015 /* Output to assembler file text saying following lines
2016 no longer contain unusual constructs. */
2018 #define ASM_APP_OFF ""
2020 /* How to refer to registers in assembler output.
2021 This sequence is indexed by compiler's hard-register-number (see above). */
2023 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2025 #define REGISTER_NAMES \
2027 &rs6000_reg_names[ 0][0], /* r0 */ \
2028 &rs6000_reg_names[ 1][0], /* r1 */ \
2029 &rs6000_reg_names[ 2][0], /* r2 */ \
2030 &rs6000_reg_names[ 3][0], /* r3 */ \
2031 &rs6000_reg_names[ 4][0], /* r4 */ \
2032 &rs6000_reg_names[ 5][0], /* r5 */ \
2033 &rs6000_reg_names[ 6][0], /* r6 */ \
2034 &rs6000_reg_names[ 7][0], /* r7 */ \
2035 &rs6000_reg_names[ 8][0], /* r8 */ \
2036 &rs6000_reg_names[ 9][0], /* r9 */ \
2037 &rs6000_reg_names[10][0], /* r10 */ \
2038 &rs6000_reg_names[11][0], /* r11 */ \
2039 &rs6000_reg_names[12][0], /* r12 */ \
2040 &rs6000_reg_names[13][0], /* r13 */ \
2041 &rs6000_reg_names[14][0], /* r14 */ \
2042 &rs6000_reg_names[15][0], /* r15 */ \
2043 &rs6000_reg_names[16][0], /* r16 */ \
2044 &rs6000_reg_names[17][0], /* r17 */ \
2045 &rs6000_reg_names[18][0], /* r18 */ \
2046 &rs6000_reg_names[19][0], /* r19 */ \
2047 &rs6000_reg_names[20][0], /* r20 */ \
2048 &rs6000_reg_names[21][0], /* r21 */ \
2049 &rs6000_reg_names[22][0], /* r22 */ \
2050 &rs6000_reg_names[23][0], /* r23 */ \
2051 &rs6000_reg_names[24][0], /* r24 */ \
2052 &rs6000_reg_names[25][0], /* r25 */ \
2053 &rs6000_reg_names[26][0], /* r26 */ \
2054 &rs6000_reg_names[27][0], /* r27 */ \
2055 &rs6000_reg_names[28][0], /* r28 */ \
2056 &rs6000_reg_names[29][0], /* r29 */ \
2057 &rs6000_reg_names[30][0], /* r30 */ \
2058 &rs6000_reg_names[31][0], /* r31 */ \
2060 &rs6000_reg_names[32][0], /* fr0 */ \
2061 &rs6000_reg_names[33][0], /* fr1 */ \
2062 &rs6000_reg_names[34][0], /* fr2 */ \
2063 &rs6000_reg_names[35][0], /* fr3 */ \
2064 &rs6000_reg_names[36][0], /* fr4 */ \
2065 &rs6000_reg_names[37][0], /* fr5 */ \
2066 &rs6000_reg_names[38][0], /* fr6 */ \
2067 &rs6000_reg_names[39][0], /* fr7 */ \
2068 &rs6000_reg_names[40][0], /* fr8 */ \
2069 &rs6000_reg_names[41][0], /* fr9 */ \
2070 &rs6000_reg_names[42][0], /* fr10 */ \
2071 &rs6000_reg_names[43][0], /* fr11 */ \
2072 &rs6000_reg_names[44][0], /* fr12 */ \
2073 &rs6000_reg_names[45][0], /* fr13 */ \
2074 &rs6000_reg_names[46][0], /* fr14 */ \
2075 &rs6000_reg_names[47][0], /* fr15 */ \
2076 &rs6000_reg_names[48][0], /* fr16 */ \
2077 &rs6000_reg_names[49][0], /* fr17 */ \
2078 &rs6000_reg_names[50][0], /* fr18 */ \
2079 &rs6000_reg_names[51][0], /* fr19 */ \
2080 &rs6000_reg_names[52][0], /* fr20 */ \
2081 &rs6000_reg_names[53][0], /* fr21 */ \
2082 &rs6000_reg_names[54][0], /* fr22 */ \
2083 &rs6000_reg_names[55][0], /* fr23 */ \
2084 &rs6000_reg_names[56][0], /* fr24 */ \
2085 &rs6000_reg_names[57][0], /* fr25 */ \
2086 &rs6000_reg_names[58][0], /* fr26 */ \
2087 &rs6000_reg_names[59][0], /* fr27 */ \
2088 &rs6000_reg_names[60][0], /* fr28 */ \
2089 &rs6000_reg_names[61][0], /* fr29 */ \
2090 &rs6000_reg_names[62][0], /* fr30 */ \
2091 &rs6000_reg_names[63][0], /* fr31 */ \
2093 &rs6000_reg_names[64][0], /* vr0 */ \
2094 &rs6000_reg_names[65][0], /* vr1 */ \
2095 &rs6000_reg_names[66][0], /* vr2 */ \
2096 &rs6000_reg_names[67][0], /* vr3 */ \
2097 &rs6000_reg_names[68][0], /* vr4 */ \
2098 &rs6000_reg_names[69][0], /* vr5 */ \
2099 &rs6000_reg_names[70][0], /* vr6 */ \
2100 &rs6000_reg_names[71][0], /* vr7 */ \
2101 &rs6000_reg_names[72][0], /* vr8 */ \
2102 &rs6000_reg_names[73][0], /* vr9 */ \
2103 &rs6000_reg_names[74][0], /* vr10 */ \
2104 &rs6000_reg_names[75][0], /* vr11 */ \
2105 &rs6000_reg_names[76][0], /* vr12 */ \
2106 &rs6000_reg_names[77][0], /* vr13 */ \
2107 &rs6000_reg_names[78][0], /* vr14 */ \
2108 &rs6000_reg_names[79][0], /* vr15 */ \
2109 &rs6000_reg_names[80][0], /* vr16 */ \
2110 &rs6000_reg_names[81][0], /* vr17 */ \
2111 &rs6000_reg_names[82][0], /* vr18 */ \
2112 &rs6000_reg_names[83][0], /* vr19 */ \
2113 &rs6000_reg_names[84][0], /* vr20 */ \
2114 &rs6000_reg_names[85][0], /* vr21 */ \
2115 &rs6000_reg_names[86][0], /* vr22 */ \
2116 &rs6000_reg_names[87][0], /* vr23 */ \
2117 &rs6000_reg_names[88][0], /* vr24 */ \
2118 &rs6000_reg_names[89][0], /* vr25 */ \
2119 &rs6000_reg_names[90][0], /* vr26 */ \
2120 &rs6000_reg_names[91][0], /* vr27 */ \
2121 &rs6000_reg_names[92][0], /* vr28 */ \
2122 &rs6000_reg_names[93][0], /* vr29 */ \
2123 &rs6000_reg_names[94][0], /* vr30 */ \
2124 &rs6000_reg_names[95][0], /* vr31 */ \
2126 &rs6000_reg_names[96][0], /* lr */ \
2127 &rs6000_reg_names[97][0], /* ctr */ \
2128 &rs6000_reg_names[98][0], /* ca */ \
2129 &rs6000_reg_names[99][0], /* ap */ \
2131 &rs6000_reg_names[100][0], /* cr0 */ \
2132 &rs6000_reg_names[101][0], /* cr1 */ \
2133 &rs6000_reg_names[102][0], /* cr2 */ \
2134 &rs6000_reg_names[103][0], /* cr3 */ \
2135 &rs6000_reg_names[104][0], /* cr4 */ \
2136 &rs6000_reg_names[105][0], /* cr5 */ \
2137 &rs6000_reg_names[106][0], /* cr6 */ \
2138 &rs6000_reg_names[107][0], /* cr7 */ \
2140 &rs6000_reg_names[108][0], /* vrsave */ \
2141 &rs6000_reg_names[109][0], /* vscr */ \
2143 &rs6000_reg_names[110][0] /* sfp */ \
2146 /* Table of additional register names to use in user input. */
2148 #define ADDITIONAL_REGISTER_NAMES \
2149 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2150 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2151 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2152 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2153 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2154 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2155 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2156 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2157 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2158 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2159 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2160 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2161 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2162 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2163 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2164 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2165 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \
2166 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \
2167 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \
2168 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \
2169 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \
2170 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \
2171 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \
2172 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \
2173 {"vrsave", 108}, {"vscr", 109}, \
2174 /* no additional names for: lr, ctr, ap */ \
2175 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \
2176 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \
2177 {"cc", 100},{"sp", 1}, {"toc", 2}, \
2178 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2180 /* VSX registers overlaid on top of FR, Altivec registers */ \
2181 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2182 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2183 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2184 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2185 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2186 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2187 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2188 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2189 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \
2190 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \
2191 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \
2192 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \
2193 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \
2194 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \
2195 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \
2196 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \
2199 /* This is how to output an element of a case-vector that is relative. */
2201 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2202 do { char buf[100]; \
2203 fputs ("\t.long ", FILE); \
2204 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2205 assemble_name (FILE, buf); \
2207 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2208 assemble_name (FILE, buf); \
2209 putc ('\n', FILE); \
2212 /* This is how to output an assembler line
2213 that says to advance the location counter
2214 to a multiple of 2**LOG bytes. */
2216 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2218 fprintf (FILE, "\t.align %d\n", (LOG))
2220 /* How to align the given loop. */
2221 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2223 /* Alignment guaranteed by __builtin_malloc. */
2224 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2225 However, specifying the stronger guarantee currently leads to
2226 a regression in SPEC CPU2006 437.leslie3d. The stronger
2227 guarantee should be implemented here once that's fixed. */
2228 #define MALLOC_ABI_ALIGNMENT (64)
2230 /* Pick up the return address upon entry to a procedure. Used for
2231 dwarf2 unwind information. This also enables the table driven
2234 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2235 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2237 /* Describe how we implement __builtin_eh_return. */
2238 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2239 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2241 /* Print operand X (an rtx) in assembler syntax to file FILE.
2242 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2243 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2245 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2247 /* Define which CODE values are valid. */
2249 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2251 /* Print a memory address as an operand to reference that memory location. */
2253 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2255 /* For switching between functions with different target attributes. */
2256 #define SWITCHABLE_TARGET 1
2258 /* uncomment for disabling the corresponding default options */
2259 /* #define MACHINE_no_sched_interblock */
2260 /* #define MACHINE_no_sched_speculative */
2261 /* #define MACHINE_no_sched_speculative_load */
2263 /* General flags. */
2264 extern int frame_pointer_needed;
2266 /* Classification of the builtin functions as to which switches enable the
2267 builtin, and what attributes it should have. We used to use the target
2268 flags macros, but we've run out of bits, so we now map the options into new
2269 settings used here. */
2271 /* Builtin attributes. */
2272 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2273 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2274 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2275 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2276 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2277 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2278 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2279 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2281 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2282 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
2283 modifies global state. */
2284 #define RS6000_BTC_PURE 0x00000200 /* reads global
2286 not modify global state. */
2287 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2288 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2290 /* Miscellaneous information. */
2291 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2292 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2293 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */
2294 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */
2295 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2297 /* Convenience macros to document the instruction type. */
2298 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2299 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2301 /* Builtin targets. For now, we reuse the masks for those options that are in
2302 target flags, and pick a random bit for ldbl128, which isn't in
2304 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2305 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2306 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2307 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2308 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2309 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2310 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2311 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2312 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2313 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2314 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2315 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2316 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2317 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2318 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2319 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2320 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2321 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2322 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2323 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
2324 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
2325 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
2327 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2329 | RS6000_BTM_P8_VECTOR \
2330 | RS6000_BTM_P9_VECTOR \
2331 | RS6000_BTM_P9_MISC \
2332 | RS6000_BTM_MODULO \
2333 | RS6000_BTM_CRYPTO \
2336 | RS6000_BTM_FRSQRTE \
2337 | RS6000_BTM_FRSQRTES \
2339 | RS6000_BTM_POPCNTD \
2342 | RS6000_BTM_HARD_FLOAT \
2343 | RS6000_BTM_LDBL128 \
2344 | RS6000_BTM_POWERPC64 \
2345 | RS6000_BTM_FLOAT128 \
2346 | RS6000_BTM_FLOAT128_HW)
2348 /* Define builtin enum index. */
2350 #undef RS6000_BUILTIN_0
2351 #undef RS6000_BUILTIN_1
2352 #undef RS6000_BUILTIN_2
2353 #undef RS6000_BUILTIN_3
2354 #undef RS6000_BUILTIN_A
2355 #undef RS6000_BUILTIN_D
2356 #undef RS6000_BUILTIN_H
2357 #undef RS6000_BUILTIN_P
2358 #undef RS6000_BUILTIN_X
2360 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2361 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2362 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2363 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2364 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2365 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2366 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2367 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2368 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2370 enum rs6000_builtins
2372 #include "rs6000-builtin.def"
2374 RS6000_BUILTIN_COUNT
2377 #undef RS6000_BUILTIN_0
2378 #undef RS6000_BUILTIN_1
2379 #undef RS6000_BUILTIN_2
2380 #undef RS6000_BUILTIN_3
2381 #undef RS6000_BUILTIN_A
2382 #undef RS6000_BUILTIN_D
2383 #undef RS6000_BUILTIN_H
2384 #undef RS6000_BUILTIN_P
2385 #undef RS6000_BUILTIN_X
2387 enum rs6000_builtin_type_index
2389 RS6000_BTI_NOT_OPAQUE,
2390 RS6000_BTI_opaque_V4SI,
2391 RS6000_BTI_V16QI, /* __vector signed char */
2399 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */
2400 RS6000_BTI_unsigned_V1TI,
2401 RS6000_BTI_unsigned_V8HI,
2402 RS6000_BTI_unsigned_V4SI,
2403 RS6000_BTI_unsigned_V2DI,
2404 RS6000_BTI_bool_char, /* __bool char */
2405 RS6000_BTI_bool_short, /* __bool short */
2406 RS6000_BTI_bool_int, /* __bool int */
2407 RS6000_BTI_bool_long_long, /* __bool long long */
2408 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4
2409 channels of 1, 5, 5, and 5 bits
2410 respectively as packed with the
2411 vpkpx insn. __pixel is only
2412 meaningful as a vector type.
2413 There is no corresponding scalar
2414 __pixel data type.) */
2415 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2416 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2417 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2418 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2419 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2420 RS6000_BTI_long, /* long_integer_type_node */
2421 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2422 RS6000_BTI_long_long, /* long_long_integer_type_node */
2423 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2424 RS6000_BTI_INTQI, /* (signed) intQI_type_node */
2425 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2426 RS6000_BTI_INTHI, /* intHI_type_node */
2427 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2428 RS6000_BTI_INTSI, /* intSI_type_node (signed) */
2429 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2430 RS6000_BTI_INTDI, /* intDI_type_node */
2431 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2432 RS6000_BTI_INTTI, /* intTI_type_node */
2433 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */
2434 RS6000_BTI_float, /* float_type_node */
2435 RS6000_BTI_double, /* double_type_node */
2436 RS6000_BTI_long_double, /* long_double_type_node */
2437 RS6000_BTI_dfloat64, /* dfloat64_type_node */
2438 RS6000_BTI_dfloat128, /* dfloat128_type_node */
2439 RS6000_BTI_void, /* void_type_node */
2440 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */
2441 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */
2442 RS6000_BTI_const_str, /* pointer to const char * */
2447 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2448 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2449 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2450 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2451 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2452 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2453 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2454 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2455 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2456 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2457 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2458 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2459 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2460 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2461 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2462 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2463 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2464 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2465 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2466 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2467 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2468 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2469 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2470 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2472 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2473 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2474 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2475 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2476 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2477 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2478 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2479 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2480 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2481 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2482 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2483 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2484 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2485 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2486 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2487 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2488 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2489 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2490 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2491 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2492 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2493 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2494 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2496 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2497 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
2499 #define TARGET_SUPPORTS_WIDE_INT 1
2501 #if (GCC_VERSION >= 3000)
2502 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128
2505 /* Whether a given VALUE is a valid 16- or 34-bit signed offset. EXTRA is the
2506 amount that we can't touch at the high end of the range (typically if the
2507 address is split into smaller addresses, the extra covers the addresses
2508 which might be generated when the insn is split). */
2509 #define SIGNED_16BIT_OFFSET_P(VALUE, EXTRA) \
2511 -(HOST_WIDE_INT_1 << 15), \
2512 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA))
2514 #define SIGNED_34BIT_OFFSET_P(VALUE, EXTRA) \
2516 -(HOST_WIDE_INT_1 << 33), \
2517 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA))
2519 /* Flag to mark SYMBOL_REF objects to say they are local addresses and are used
2520 in pc-relative addresses. */
2521 #define SYMBOL_FLAG_PCREL SYMBOL_FLAG_MACH_DEP
2523 #define SYMBOL_REF_PCREL_P(X) \
2524 (SYMBOL_REF_P (X) && SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_PCREL)