1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/rs6000/rs6000-opts.h"
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
35 #include "config/rs6000/rs6000-modes.h"
38 /* Definitions for the object file format. These are set at
41 #define OBJECT_XCOFF 1
43 #define OBJECT_MACHO 4
45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
54 #define TARGET_AIX_OS 0
57 /* Control whether function entry points use a "dot" symbol when
61 /* Default string to use for cpu if not specified. */
62 #ifndef TARGET_CPU_DEFAULT
63 #define TARGET_CPU_DEFAULT ((char *)0)
66 /* If configured for PPC405, support PPC405CR Erratum77. */
67 #ifdef CONFIG_PPC405CR
68 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
70 #define PPC405_ERRATUM77 0
74 #define ASM_OPT_ANY ""
76 #define ASM_OPT_ANY " -many"
79 /* Common ASM definitions used by ASM_SPEC among the various targets for
80 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
81 provide the default assembler options if the user uses -mcpu=native, so if
82 you make changes here, make them also there. PR63177: Do not pass -mpower8
83 to the assembler if -mpower9-vector was also used. */
84 #define ASM_CPU_SPEC \
85 "%{mcpu=native: %(asm_cpu_native); \
86 mcpu=power9: -mpower9; \
87 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \
88 mcpu=power7: -mpower7; \
89 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
90 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
91 mcpu=power5+: -mpower5; \
92 mcpu=power5: -mpower5; \
93 mcpu=power4: -mpower4; \
94 mcpu=power3: -mppc64; \
95 mcpu=powerpc: -mppc; \
96 mcpu=powerpc64: -mppc64; \
115 mcpu=ec603e: -mppc; \
123 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
124 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
125 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
130 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
131 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
134 mcpu=e300c2: -me300; \
135 mcpu=e300c3: -me300; \
136 mcpu=e500mc: -me500mc; \
137 mcpu=e500mc64: -me500mc64; \
138 mcpu=e5500: -me5500; \
139 mcpu=e6500: -me6500; \
140 mcpu=titan: -mtitan; \
141 !mcpu*: %{mpower9-vector: -mpower9; \
142 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
144 mpowerpc64: -mppc64;: %(asm_default)}; \
145 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \
146 %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \
149 #define CPP_DEFAULT_SPEC ""
151 #define ASM_DEFAULT_SPEC ""
153 /* This macro defines names of additional specifications to put in the specs
154 that can be used in various specifications like CC1_SPEC. Its definition
155 is an initializer with a subgrouping for each command option.
157 Each subgrouping contains a string constant, that defines the
158 specification name, and a string constant that used by the GCC driver
161 Do not define this macro if it does not need to do anything. */
163 #define SUBTARGET_EXTRA_SPECS
165 #define EXTRA_SPECS \
166 { "cpp_default", CPP_DEFAULT_SPEC }, \
167 { "asm_cpu", ASM_CPU_SPEC }, \
168 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
169 { "asm_default", ASM_DEFAULT_SPEC }, \
170 { "cc1_cpu", CC1_CPU_SPEC }, \
171 SUBTARGET_EXTRA_SPECS
173 /* -mcpu=native handling only makes sense with compiler running on
174 an PowerPC chip. If changing this condition, also change
175 the condition in driver-rs6000.c. */
176 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
177 /* In driver-rs6000.c. */
178 extern const char *host_detect_local_cpu (int argc, const char **argv);
179 #define EXTRA_SPEC_FUNCTIONS \
180 { "local_cpu_detect", host_detect_local_cpu },
181 #define HAVE_LOCAL_CPU_DETECT
182 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
185 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
189 #ifdef HAVE_LOCAL_CPU_DETECT
190 #define CC1_CPU_SPEC \
191 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
192 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
194 #define CC1_CPU_SPEC ""
198 /* Architecture type. */
200 /* Define TARGET_MFCRF if the target assembler does not support the
201 optional field operand for mfcr. */
203 #ifndef HAVE_AS_MFCRF
205 #define TARGET_MFCRF 0
208 /* Define TARGET_TLS_MARKERS if the target assembler does not support
209 arg markers for __tls_get_addr calls. */
210 #ifndef HAVE_AS_TLS_MARKERS
211 #undef TARGET_TLS_MARKERS
212 #define TARGET_TLS_MARKERS 0
214 #define TARGET_TLS_MARKERS tls_markers
217 #ifndef TARGET_SECURE_PLT
218 #define TARGET_SECURE_PLT 0
221 #ifndef TARGET_CMODEL
222 #define TARGET_CMODEL CMODEL_SMALL
225 #define TARGET_32BIT (! TARGET_64BIT)
228 #define HAVE_AS_TLS 0
231 #ifndef HAVE_AS_PLTSEQ
232 #define HAVE_AS_PLTSEQ 0
235 #ifndef TARGET_PLTSEQ
236 #define TARGET_PLTSEQ 0
239 #ifndef TARGET_LINK_STACK
240 #define TARGET_LINK_STACK 0
243 #ifndef SET_TARGET_LINK_STACK
244 #define SET_TARGET_LINK_STACK(X) do { } while (0)
247 #ifndef TARGET_FLOAT128_ENABLE_TYPE
248 #define TARGET_FLOAT128_ENABLE_TYPE 0
251 /* Return 1 for a symbol ref for a thread-local storage symbol. */
252 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
253 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0)
256 /* For libgcc2 we make sure this is a compile time constant */
257 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
258 #undef TARGET_POWERPC64
259 #define TARGET_POWERPC64 1
261 #undef TARGET_POWERPC64
262 #define TARGET_POWERPC64 0
265 /* The option machinery will define this. */
268 #define TARGET_DEFAULT (MASK_MULTIPLE)
270 /* Define generic processor types based upon current deployment. */
271 #define PROCESSOR_COMMON PROCESSOR_PPC601
272 #define PROCESSOR_POWERPC PROCESSOR_PPC604
273 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
275 /* Define the default processor. This is overridden by other tm.h files. */
276 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
277 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
279 /* Specify the dialect of assembler to use. Only new mnemonics are supported
280 starting with GCC 4.8, i.e. just one dialect, but for backwards
281 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
283 #define ASSEMBLER_DIALECT 1
286 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
287 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
288 #define MASK_DEBUG_REG 0x04 /* debug register handling */
289 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
290 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
291 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
292 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
293 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
298 | MASK_DEBUG_TARGET \
299 | MASK_DEBUG_BUILTIN)
301 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
302 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
303 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
304 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
305 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
306 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
307 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
309 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
310 long double format that uses a pair of doubles, or IEEE 128-bit floating
311 point. KFmode was added as a way to represent IEEE 128-bit floating point,
312 even if the default for long double is the IBM long double format.
313 Similarly IFmode is the IBM long double format even if the default is IEEE
314 128-bit. Don't allow IFmode if -msoft-float. */
315 #define FLOAT128_IEEE_P(MODE) \
316 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
317 && ((MODE) == TFmode || (MODE) == TCmode)) \
318 || ((MODE) == KFmode) || ((MODE) == KCmode))
320 #define FLOAT128_IBM_P(MODE) \
321 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
322 && ((MODE) == TFmode || (MODE) == TCmode)) \
323 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
325 /* Helper macros to say whether a 128-bit floating point type can go in a
326 single vector register, or whether it needs paired scalar values. */
327 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
329 #define FLOAT128_2REG_P(MODE) \
330 (FLOAT128_IBM_P (MODE) \
331 || ((MODE) == TDmode) \
332 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
334 /* Return true for floating point that does not use a vector register. */
335 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
336 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
338 /* Describe the vector unit used for arithmetic operations. */
339 extern enum rs6000_vector rs6000_vector_unit[];
341 #define VECTOR_UNIT_NONE_P(MODE) \
342 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
344 #define VECTOR_UNIT_VSX_P(MODE) \
345 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
347 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
348 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
350 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
351 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
353 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
354 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
356 (int)VECTOR_P8_VECTOR))
358 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
359 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
360 compatible, so allow it as well, rather than changing all of the uses of the
362 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
363 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
364 (int)VECTOR_ALTIVEC, \
365 (int)VECTOR_P8_VECTOR))
367 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
368 same unit as the vector unit we are using, but we may want to migrate to
369 using VSX style loads even for types handled by altivec. */
370 extern enum rs6000_vector rs6000_vector_mem[];
372 #define VECTOR_MEM_NONE_P(MODE) \
373 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
375 #define VECTOR_MEM_VSX_P(MODE) \
376 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
378 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
379 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
381 #define VECTOR_MEM_ALTIVEC_P(MODE) \
382 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
384 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
385 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
387 (int)VECTOR_P8_VECTOR))
389 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
390 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
391 (int)VECTOR_ALTIVEC, \
392 (int)VECTOR_P8_VECTOR))
394 /* Return the alignment of a given vector type, which is set based on the
395 vector unit use. VSX for instance can load 32 or 64 bit aligned words
396 without problems, while Altivec requires 128-bit aligned vectors. */
397 extern int rs6000_vector_align[];
399 #define VECTOR_ALIGN(MODE) \
400 ((rs6000_vector_align[(MODE)] != 0) \
401 ? rs6000_vector_align[(MODE)] \
402 : (int)GET_MODE_BITSIZE ((MODE)))
404 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
405 with scalar instructions. */
406 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
408 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
409 with the ISA 3.0 MFVSRLD instructions. */
410 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
412 /* Alignment options for fields in structures for sub-targets following
414 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
415 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
417 Override the macro definitions when compiling libobjc to avoid undefined
418 reference to rs6000_alignment_flags due to library's use of GCC alignment
419 macros which use the macros below. */
421 #ifndef IN_TARGET_LIBS
422 #define MASK_ALIGN_POWER 0x00000000
423 #define MASK_ALIGN_NATURAL 0x00000001
424 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
426 #define TARGET_ALIGN_NATURAL 0
429 /* We use values 126..128 to pick the appropriate long double type (IFmode,
431 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
432 #define TARGET_IEEEQUAD rs6000_ieeequad
433 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
434 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
436 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
437 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
438 #define TARGET_FCFID (TARGET_POWERPC64 \
439 || TARGET_PPC_GPOPT /* 970/power4 */ \
440 || TARGET_POPCNTB /* ISA 2.02 */ \
441 || TARGET_CMPB /* ISA 2.05 */ \
442 || TARGET_POPCNTD) /* ISA 2.06 */
444 #define TARGET_FCTIDZ TARGET_FCFID
445 #define TARGET_STFIWX TARGET_PPC_GFXOPT
446 #define TARGET_LFIWAX TARGET_CMPB
447 #define TARGET_LFIWZX TARGET_POPCNTD
448 #define TARGET_FCFIDS TARGET_POPCNTD
449 #define TARGET_FCFIDU TARGET_POPCNTD
450 #define TARGET_FCFIDUS TARGET_POPCNTD
451 #define TARGET_FCTIDUZ TARGET_POPCNTD
452 #define TARGET_FCTIWUZ TARGET_POPCNTD
453 #define TARGET_CTZ TARGET_MODULO
454 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
455 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
457 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
458 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
459 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
460 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
462 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
465 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
466 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
467 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
469 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
471 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
473 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
474 in power7, so conditionalize them on p8 features. TImode syncs need quad
476 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
477 || TARGET_QUAD_MEMORY_ATOMIC \
478 || TARGET_DIRECT_MOVE)
480 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
482 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
483 to allocate the SDmode stack slot to get the value into the proper location
485 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
487 /* ISA 3.0 has new min/max functions that don't need fast math that are being
488 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
489 answers if the arguments are not in the normal range. */
490 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
491 && (TARGET_P9_MINMAX || !flag_trapping_math))
493 /* In switching from using target_flags to using rs6000_isa_flags, the options
494 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
495 OPTION_MASK_<xxx> back into MASK_<xxx>. */
496 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
497 #define MASK_CMPB OPTION_MASK_CMPB
498 #define MASK_CRYPTO OPTION_MASK_CRYPTO
499 #define MASK_DFP OPTION_MASK_DFP
500 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
501 #define MASK_DLMZB OPTION_MASK_DLMZB
502 #define MASK_EABI OPTION_MASK_EABI
503 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
504 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
505 #define MASK_FPRND OPTION_MASK_FPRND
506 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
507 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
508 #define MASK_HTM OPTION_MASK_HTM
509 #define MASK_ISEL OPTION_MASK_ISEL
510 #define MASK_MFCRF OPTION_MASK_MFCRF
511 #define MASK_MFPGPR OPTION_MASK_MFPGPR
512 #define MASK_MULHW OPTION_MASK_MULHW
513 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
514 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
515 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
516 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
517 #define MASK_P9_MISC OPTION_MASK_P9_MISC
518 #define MASK_POPCNTB OPTION_MASK_POPCNTB
519 #define MASK_POPCNTD OPTION_MASK_POPCNTD
520 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
521 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
522 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
523 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
524 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
525 #define MASK_UPDATE OPTION_MASK_UPDATE
526 #define MASK_VSX OPTION_MASK_VSX
529 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
533 #define MASK_64BIT OPTION_MASK_64BIT
536 #ifdef TARGET_LITTLE_ENDIAN
537 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
540 #ifdef TARGET_REGNAMES
541 #define MASK_REGNAMES OPTION_MASK_REGNAMES
544 #ifdef TARGET_PROTOTYPE
545 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
549 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
553 /* For power systems, we want to enable Altivec and VSX builtins even if the
554 user did not use -maltivec or -mvsx to allow the builtins to be used inside
555 of #pragma GCC target or the target attribute to change the code level for a
558 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
559 || TARGET_PPC_GPOPT /* 970/power4 */ \
560 || TARGET_POPCNTB /* ISA 2.02 */ \
561 || TARGET_CMPB /* ISA 2.05 */ \
562 || TARGET_POPCNTD /* ISA 2.06 */ \
565 || TARGET_HARD_FLOAT)
567 /* E500 cores only support plain "sync", not lwsync. */
568 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
569 || rs6000_cpu == PROCESSOR_PPC8548)
572 /* Which machine supports the various reciprocal estimate instructions. */
573 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
575 #define TARGET_FRE (TARGET_HARD_FLOAT \
576 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
578 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
579 && TARGET_PPC_GFXOPT)
581 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
582 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
584 /* Macro to say whether we can do optimizations where we need to do parts of
585 the calculation in 64-bit GPRs and then is transfered to the vector
587 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
588 && TARGET_P8_VECTOR \
591 /* Whether the various reciprocal divide/square root estimate instructions
592 exist, and whether we should automatically generate code for the instruction
594 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
595 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
596 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
597 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
599 extern unsigned char rs6000_recip_bits[];
601 #define RS6000_RECIP_HAVE_RE_P(MODE) \
602 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
604 #define RS6000_RECIP_AUTO_RE_P(MODE) \
605 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
607 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
608 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
610 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
611 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
613 /* The default CPU for TARGET_OPTION_OVERRIDE. */
614 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
617 #define REGISTER_TARGET_PRAGMAS() do { \
618 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
619 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
620 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
621 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
624 /* Target #defines. */
625 #define TARGET_CPU_CPP_BUILTINS() \
626 rs6000_cpu_cpp_builtins (pfile)
628 /* Target CPU versions for D. */
629 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions
631 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
632 we're compiling for. Some configurations may need to override it. */
633 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
636 if (BYTES_BIG_ENDIAN) \
638 builtin_define ("__BIG_ENDIAN__"); \
639 builtin_define ("_BIG_ENDIAN"); \
640 builtin_assert ("machine=bigendian"); \
644 builtin_define ("__LITTLE_ENDIAN__"); \
645 builtin_define ("_LITTLE_ENDIAN"); \
646 builtin_assert ("machine=littleendian"); \
651 /* Target machine storage layout. */
653 /* Define this macro if it is advisable to hold scalars in registers
654 in a wider mode than that declared by the program. In such cases,
655 the value is constrained to be within the bounds of the declared
656 type, but kept valid in the wider mode. The signedness of the
657 extension may differ from that of the type. */
659 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
660 if (GET_MODE_CLASS (MODE) == MODE_INT \
661 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
662 (MODE) = TARGET_32BIT ? SImode : DImode;
664 /* Define this if most significant bit is lowest numbered
665 in instructions that operate on numbered bit-fields. */
666 /* That is true on RS/6000. */
667 #define BITS_BIG_ENDIAN 1
669 /* Define this if most significant byte of a word is the lowest numbered. */
670 /* That is true on RS/6000. */
671 #define BYTES_BIG_ENDIAN 1
673 /* Define this if most significant word of a multiword number is lowest
676 For RS/6000 we can decide arbitrarily since there are no machine
677 instructions for them. Might as well be consistent with bits and bytes. */
678 #define WORDS_BIG_ENDIAN 1
680 /* This says that for the IBM long double the larger magnitude double
681 comes first. It's really a two element double array, and arrays
682 don't index differently between little- and big-endian. */
683 #define LONG_DOUBLE_LARGE_FIRST 1
685 #define MAX_BITS_PER_WORD 64
687 /* Width of a word, in units (bytes). */
688 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
690 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
692 #define MIN_UNITS_PER_WORD 4
694 #define UNITS_PER_FP_WORD 8
695 #define UNITS_PER_ALTIVEC_WORD 16
696 #define UNITS_PER_VSX_WORD 16
698 /* Type used for ptrdiff_t, as a string used in a declaration. */
699 #define PTRDIFF_TYPE "int"
701 /* Type used for size_t, as a string used in a declaration. */
702 #define SIZE_TYPE "long unsigned int"
704 /* Type used for wchar_t, as a string used in a declaration. */
705 #define WCHAR_TYPE "short unsigned int"
707 /* Width of wchar_t in bits. */
708 #define WCHAR_TYPE_SIZE 16
710 /* A C expression for the size in bits of the type `short' on the
711 target machine. If you don't define this, the default is half a
712 word. (If this would be less than one storage unit, it is
713 rounded up to one unit.) */
714 #define SHORT_TYPE_SIZE 16
716 /* A C expression for the size in bits of the type `int' on the
717 target machine. If you don't define this, the default is one
719 #define INT_TYPE_SIZE 32
721 /* A C expression for the size in bits of the type `long' on the
722 target machine. If you don't define this, the default is one
724 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
726 /* A C expression for the size in bits of the type `long long' on the
727 target machine. If you don't define this, the default is two
729 #define LONG_LONG_TYPE_SIZE 64
731 /* A C expression for the size in bits of the type `float' on the
732 target machine. If you don't define this, the default is one
734 #define FLOAT_TYPE_SIZE 32
736 /* A C expression for the size in bits of the type `double' on the
737 target machine. If you don't define this, the default is two
739 #define DOUBLE_TYPE_SIZE 64
741 /* A C expression for the size in bits of the type `long double' on the target
742 machine. If you don't define this, the default is two words. */
743 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
745 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
746 #define WIDEST_HARDWARE_FP_SIZE 64
748 /* Width in bits of a pointer.
749 See also the macro `Pmode' defined below. */
750 extern unsigned rs6000_pointer_size;
751 #define POINTER_SIZE rs6000_pointer_size
753 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
754 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
756 /* Boundary (in *bits*) on which stack pointer should be aligned. */
757 #define STACK_BOUNDARY \
758 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
761 /* Allocation boundary (in *bits*) for the code of a function. */
762 #define FUNCTION_BOUNDARY 32
764 /* No data type wants to be aligned rounder than this. */
765 #define BIGGEST_ALIGNMENT 128
767 /* Alignment of field after `int : 0' in a structure. */
768 #define EMPTY_FIELD_BOUNDARY 32
770 /* Every structure's size must be a multiple of this. */
771 #define STRUCTURE_SIZE_BOUNDARY 8
773 /* A bit-field declared as `int' forces `int' alignment for the struct. */
774 #define PCC_BITFIELD_TYPE_MATTERS 1
776 enum data_align { align_abi, align_opt, align_both };
778 /* A C expression to compute the alignment for a variables in the
779 local store. TYPE is the data type, and ALIGN is the alignment
780 that the object would ordinarily have. */
781 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
782 rs6000_data_alignment (TYPE, ALIGN, align_both)
784 /* Make arrays of chars word-aligned for the same reasons. */
785 #define DATA_ALIGNMENT(TYPE, ALIGN) \
786 rs6000_data_alignment (TYPE, ALIGN, align_opt)
788 /* Align vectors to 128 bits. */
789 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
790 rs6000_data_alignment (TYPE, ALIGN, align_abi)
792 /* Nonzero if move instructions will actually fail to work
793 when given unaligned data. */
794 #define STRICT_ALIGNMENT 0
796 /* Standard register usage. */
798 /* Number of actual hardware registers.
799 The hardware registers are assigned numbers for the compiler
800 from 0 to just below FIRST_PSEUDO_REGISTER.
801 All registers that the compiler knows about must be given numbers,
802 even those that are not normally considered general registers.
804 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
805 a count register, a link register, and 8 condition register fields,
806 which we view here as separate registers. AltiVec adds 32 vector
807 registers and a VRsave register.
809 In addition, the difference between the frame and argument pointers is
810 a function of the number of registers saved, so we need to have a
811 register for AP that will later be eliminated in favor of SP or FP.
812 This is a normal register, but it is fixed.
814 We also create a pseudo register for float/int conversions, that will
815 really represent the memory location used. It is represented here as
816 a register, in order to work around problems in allocating stack storage
819 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
820 pointer, which is eventually eliminated in favor of SP or FP. */
822 #define FIRST_PSEUDO_REGISTER 111
824 /* Use standard DWARF numbering for DWARF debugging information. */
825 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
827 /* Use gcc hard register numbering for eh_frame. */
828 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
830 /* Map register numbers held in the call frame info that gcc has
831 collected using DWARF_FRAME_REGNUM to those that should be output in
832 .debug_frame and .eh_frame. */
833 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
834 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1)
836 /* 1 for registers that have pervasive standard uses
837 and are not available for the register allocator.
839 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
840 as a local register; for all other OS's r2 is the TOC pointer.
842 On System V implementations, r13 is fixed and not available for use. */
844 #define FIXED_REGISTERS \
846 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
847 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
849 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
850 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
852 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
857 0, 0, 0, 0, 0, 0, 0, 0, \
858 /* vrsave vscr sfp */ \
862 /* 1 for registers not available across function calls.
863 These must include the FIXED_REGISTERS and also any
864 registers that can be used without being saved.
865 The latter must include the registers where values are returned
866 and the register where structure-value addresses are passed.
867 Aside from that, you can include as many other registers as you like. */
869 #define CALL_USED_REGISTERS \
871 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
874 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
875 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
877 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
878 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
882 1, 1, 0, 0, 0, 1, 1, 1, \
883 /* vrsave vscr sfp */ \
887 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
888 the entire set of `FIXED_REGISTERS' be included.
889 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
890 This macro is optional. If not specified, it defaults to the value
891 of `CALL_USED_REGISTERS'. */
893 #define CALL_REALLY_USED_REGISTERS \
895 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
898 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
906 1, 1, 0, 0, 0, 1, 1, 1, \
907 /* vrsave vscr sfp */ \
911 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
913 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
914 #define FIRST_SAVED_FP_REGNO (14+32)
915 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
917 /* List the order in which to allocate registers. Each register must be
918 listed once, even those in FIXED_REGISTERS.
920 We allocate in the following order:
921 fp0 (not saved or used for anything)
922 fp13 - fp2 (not saved; incoming fp arg registers)
923 fp1 (not saved; return value)
924 fp31 - fp14 (saved; order given to save least number)
925 cr7, cr5 (not saved or special)
926 cr6 (not saved, but used for vector operations)
927 cr1 (not saved, but used for FP operations)
928 cr0 (not saved, but used for arithmetic operations)
929 cr4, cr3, cr2 (saved)
930 r9 (not saved; best for TImode)
931 r10, r8-r4 (not saved; highest first for less conflict with params)
932 r3 (not saved; return value register)
933 r11 (not saved; later alloc to help shrink-wrap)
934 r0 (not saved; cannot be base reg)
935 r31 - r13 (saved; order given to save least number)
936 r12 (not saved; if used for DImode or DFmode would use r13)
937 ctr (not saved; when we have the choice ctr is better)
939 r1, r2, ap, ca (fixed)
940 v0 - v1 (not saved or used for anything)
941 v13 - v3 (not saved; incoming vector arg registers)
942 v2 (not saved; incoming vector arg reg; return value)
943 v19 - v14 (not saved or used for anything)
944 v31 - v20 (saved; order given to save least number)
950 #define MAYBE_R2_AVAILABLE
951 #define MAYBE_R2_FIXED 2,
953 #define MAYBE_R2_AVAILABLE 2,
954 #define MAYBE_R2_FIXED
958 #define EARLY_R12 12,
965 #define REG_ALLOC_ORDER \
967 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
968 /* not use fr14 which is a saved register. */ \
969 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
971 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
972 50, 49, 48, 47, 46, \
973 100, 107, 105, 106, 101, 104, 103, 102, \
975 9, 10, 8, 7, 6, 5, 4, \
976 3, EARLY_R12 11, 0, \
977 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
978 18, 17, 16, 15, 14, 13, LATE_R12 \
980 1, MAYBE_R2_FIXED 99, 98, \
981 /* AltiVec registers. */ \
983 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \
985 83, 82, 81, 80, 79, 78, \
986 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \
991 /* True if register is floating-point. */
992 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
994 /* True if register is a condition register. */
995 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
997 /* True if register is a condition register, but not cr0. */
998 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1000 /* True if register is an integer register. */
1001 #define INT_REGNO_P(N) \
1002 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1004 /* True if register is the CA register. */
1005 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1007 /* True if register is an AltiVec register. */
1008 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1010 /* True if register is a VSX register. */
1011 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1013 /* Alternate name for any vector register supporting floating point, no matter
1014 which instruction set(s) are available. */
1015 #define VFLOAT_REGNO_P(N) \
1016 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1018 /* Alternate name for any vector register supporting integer, no matter which
1019 instruction set(s) are available. */
1020 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1022 /* Alternate name for any vector register supporting logical operations, no
1023 matter which instruction set(s) are available. Allow GPRs as well as the
1024 vector registers. */
1025 #define VLOGICAL_REGNO_P(N) \
1026 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1027 || (TARGET_VSX && FP_REGNO_P (N))) \
1029 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1030 enough space to account for vectors in FP regs. However, TFmode/TDmode
1031 should not use VSX instructions to do a caller save. */
1032 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1033 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1036 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1037 && FP_REGNO_P (REGNO) \
1039 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1041 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
1043 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1045 #define VSX_VECTOR_MODE(MODE) \
1046 ((MODE) == V4SFmode \
1047 || (MODE) == V2DFmode) \
1049 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1050 really a vector, but we want to treat it as a vector for moves, and
1053 #define ALTIVEC_VECTOR_MODE(MODE) \
1054 ((MODE) == V16QImode \
1055 || (MODE) == V8HImode \
1056 || (MODE) == V4SFmode \
1057 || (MODE) == V4SImode \
1058 || FLOAT128_VECTOR_P (MODE))
1060 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1061 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1062 || (MODE) == V2DImode || (MODE) == V1TImode)
1064 /* Post-reload, we can't use any new AltiVec registers, as we already
1065 emitted the vrsave mask. */
1067 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1068 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1070 /* Specify the cost of a branch insn; roughly the number of extra insns that
1071 should be added to avoid a branch.
1073 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1074 unscheduled conditional branch. */
1076 #define BRANCH_COST(speed_p, predictable_p) 3
1078 /* Override BRANCH_COST heuristic which empirically produces worse
1079 performance for removing short circuiting from the logical ops. */
1081 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1083 /* Specify the registers used for certain standard purposes.
1084 The values of these macros are register numbers. */
1086 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1087 /* #define PC_REGNUM */
1089 /* Register to use for pushing function arguments. */
1090 #define STACK_POINTER_REGNUM 1
1092 /* Base register for access to local variables of the function. */
1093 #define HARD_FRAME_POINTER_REGNUM 31
1095 /* Base register for access to local variables of the function. */
1096 #define FRAME_POINTER_REGNUM 110
1098 /* Base register for access to arguments of the function. */
1099 #define ARG_POINTER_REGNUM 99
1101 /* Place to put static chain when calling a function that requires it. */
1102 #define STATIC_CHAIN_REGNUM 11
1104 /* Base register for access to thread local storage variables. */
1105 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1108 /* Define the classes of registers for register constraints in the
1109 machine description. Also define ranges of constants.
1111 One of the classes must always be named ALL_REGS and include all hard regs.
1112 If there is more than one class, another class must be named NO_REGS
1113 and contain no registers.
1115 The name GENERAL_REGS must be the name of a class (or an alias for
1116 another name such as ALL_REGS). This is the class of registers
1117 that is allowed by "g" or "r" in a register constraint.
1118 Also, registers outside this class are allocated only when
1119 instructions express preferences for them.
1121 The classes must be numbered in nondecreasing order; that is,
1122 a larger-numbered class must never be contained completely
1123 in a smaller-numbered class.
1125 For any two classes, it is very desirable that there be another
1126 class that represents their union. */
1128 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1129 condition registers, plus three special registers, CTR, and the link
1130 register. AltiVec adds a vector register class. VSX registers overlap the
1131 FPR registers and the Altivec registers.
1133 However, r0 is special in that it cannot be used as a base register.
1134 So make a class for registers valid as base registers.
1136 Also, cr0 is the only condition code register that can be used in
1137 arithmetic insns, so make a separate class for it. */
1164 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1166 /* Give names of register classes as strings for dump file. */
1168 #define REG_CLASS_NAMES \
1178 "GEN_OR_FLOAT_REGS", \
1179 "GEN_OR_VSX_REGS", \
1182 "LINK_OR_CTR_REGS", \
1184 "SPEC_OR_GEN_REGS", \
1192 /* Define which registers fit in which classes.
1193 This is an initializer for a vector of HARD_REG_SET
1194 of length N_REG_CLASSES. */
1196 #define REG_CLASS_CONTENTS \
1199 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1201 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \
1202 /* GENERAL_REGS. */ \
1203 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \
1205 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1206 /* ALTIVEC_REGS. */ \
1207 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \
1209 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1210 /* VRSAVE_REGS. */ \
1211 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \
1213 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1214 /* GEN_OR_FLOAT_REGS. */ \
1215 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \
1216 /* GEN_OR_VSX_REGS. */ \
1217 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \
1219 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \
1221 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \
1222 /* LINK_OR_CTR_REGS. */ \
1223 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \
1224 /* SPECIAL_REGS. */ \
1225 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \
1226 /* SPEC_OR_GEN_REGS. */ \
1227 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \
1229 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \
1231 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \
1232 /* NON_FLOAT_REGS. */ \
1233 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \
1235 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
1237 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
1240 /* The same information, inverted:
1241 Return the class number of the smallest class containing
1242 reg number REGNO. This could be a conditional expression
1243 or could index an array. */
1245 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1247 #define REGNO_REG_CLASS(REGNO) \
1248 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1249 rs6000_regno_regclass[(REGNO)])
1251 /* Register classes for various constraints that are based on the target
1253 enum r6000_reg_class_enum {
1254 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1255 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1256 RS6000_CONSTRAINT_v, /* Altivec registers */
1257 RS6000_CONSTRAINT_wa, /* Any VSX register */
1258 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1259 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
1260 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1261 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
1262 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
1263 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
1264 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
1265 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
1266 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1267 RS6000_CONSTRAINT_wt, /* VSX register for TImode */
1268 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
1269 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
1270 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
1271 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
1272 RS6000_CONSTRAINT_MAX
1275 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1277 /* The class value for index registers, and the one for base regs. */
1278 #define INDEX_REG_CLASS GENERAL_REGS
1279 #define BASE_REG_CLASS BASE_REGS
1281 /* Return whether a given register class can hold VSX objects. */
1282 #define VSX_REG_CLASS_P(CLASS) \
1283 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1285 /* Return whether a given register class targets general purpose registers. */
1286 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1288 /* Given an rtx X being reloaded into a reg required to be
1289 in class CLASS, return the class of reg to actually use.
1290 In general this is just CLASS; but on some machines
1291 in some cases it is preferable to use a more restrictive class.
1293 On the RS/6000, we have to return NO_REGS when we want to reload a
1294 floating-point CONST_DOUBLE to force it to be copied to memory.
1296 We also don't want to reload integer values into floating-point
1297 registers if we can at all help it. In fact, this can
1298 cause reload to die, if it tries to generate a reload of CTR
1299 into a FP register and discovers it doesn't have the memory location
1302 ??? Would it be a good idea to have reload do the converse, that is
1303 try to reload floating modes into FP registers if possible?
1306 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1307 rs6000_preferred_reload_class_ptr (X, CLASS)
1309 /* Return the register class of a scratch register needed to copy IN into
1310 or out of a register in CLASS in MODE. If it can be done directly,
1311 NO_REGS is returned. */
1313 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1314 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1316 /* Return the maximum number of consecutive registers
1317 needed to represent mode MODE in a register of class CLASS.
1319 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1320 a single reg is enough for two words, unless we have VSX, where the FP
1321 registers can hold 128 bits. */
1322 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1324 /* Stack layout; function entry, exit and calling. */
1326 /* Define this if pushing a word on the stack
1327 makes the stack pointer a smaller address. */
1328 #define STACK_GROWS_DOWNWARD 1
1330 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1331 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1333 /* Define this to nonzero if the nominal address of the stack frame
1334 is at the high-address end of the local variables;
1335 that is, each additional local variable allocated
1336 goes at a more negative offset in the frame.
1338 On the RS/6000, we grow upwards, from the area after the outgoing
1340 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1341 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1343 /* Size of the fixed area on the stack */
1344 #define RS6000_SAVE_AREA \
1345 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1346 << (TARGET_64BIT ? 1 : 0))
1348 /* Stack offset for toc save slot. */
1349 #define RS6000_TOC_SAVE_SLOT \
1350 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1352 /* Align an address */
1353 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1355 /* Offset within stack frame to start allocating local variables at.
1356 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1357 first local allocated. Otherwise, it is the offset to the BEGINNING
1358 of the first local allocated.
1360 On the RS/6000, the frame pointer is the same as the stack pointer,
1361 except for dynamic allocations. So we start after the fixed area and
1362 outgoing parameter area.
1364 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1365 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1366 sizes of the fixed area and the parameter area must be a multiple of
1369 #define RS6000_STARTING_FRAME_OFFSET \
1370 (cfun->calls_alloca \
1371 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1372 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1373 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1374 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1375 + RS6000_SAVE_AREA))
1377 /* Offset from the stack pointer register to an item dynamically
1378 allocated on the stack, e.g., by `alloca'.
1380 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1381 length of the outgoing arguments. The default is correct for most
1382 machines. See `function.c' for details.
1384 This value must be a multiple of STACK_BOUNDARY (hard coded in
1386 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1387 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1388 + STACK_POINTER_OFFSET, \
1389 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1391 /* If we generate an insn to push BYTES bytes,
1392 this says how many the stack pointer really advances by.
1393 On RS/6000, don't define this because there are no push insns. */
1394 /* #define PUSH_ROUNDING(BYTES) */
1396 /* Offset of first parameter from the argument pointer register value.
1397 On the RS/6000, we define the argument pointer to the start of the fixed
1399 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1401 /* Offset from the argument pointer register value to the top of
1402 stack. This is different from FIRST_PARM_OFFSET because of the
1403 register save area. */
1404 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1406 /* Define this if stack space is still allocated for a parameter passed
1407 in a register. The value is the number of bytes allocated to this
1409 #define REG_PARM_STACK_SPACE(FNDECL) \
1410 rs6000_reg_parm_stack_space ((FNDECL), false)
1412 /* Define this macro if space guaranteed when compiling a function body
1413 is different to space required when making a call, a situation that
1414 can arise with K&R style function definitions. */
1415 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1416 rs6000_reg_parm_stack_space ((FNDECL), true)
1418 /* Define this if the above stack space is to be considered part of the
1419 space allocated by the caller. */
1420 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1422 /* This is the difference between the logical top of stack and the actual sp.
1424 For the RS/6000, sp points past the fixed area. */
1425 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1427 /* Define this if the maximum size of all the outgoing args is to be
1428 accumulated and pushed during the prologue. The amount can be
1429 found in the variable crtl->outgoing_args_size. */
1430 #define ACCUMULATE_OUTGOING_ARGS 1
1432 /* Define how to find the value returned by a library function
1433 assuming the value has mode MODE. */
1435 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1437 /* DRAFT_V4_STRUCT_RET defaults off. */
1438 #define DRAFT_V4_STRUCT_RET 0
1440 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1441 #define DEFAULT_PCC_STRUCT_RETURN 0
1443 /* Mode of stack savearea.
1444 FUNCTION is VOIDmode because calling convention maintains SP.
1445 BLOCK needs Pmode for SP.
1446 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1447 #define STACK_SAVEAREA_MODE(LEVEL) \
1448 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1449 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1451 /* Minimum and maximum general purpose registers used to hold arguments. */
1452 #define GP_ARG_MIN_REG 3
1453 #define GP_ARG_MAX_REG 10
1454 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1456 /* Minimum and maximum floating point registers used to hold arguments. */
1457 #define FP_ARG_MIN_REG 33
1458 #define FP_ARG_AIX_MAX_REG 45
1459 #define FP_ARG_V4_MAX_REG 40
1460 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1461 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1462 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1464 /* Minimum and maximum AltiVec registers used to hold arguments. */
1465 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1466 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1467 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1469 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1470 #define AGGR_ARG_NUM_REG 8
1472 /* Return registers */
1473 #define GP_ARG_RETURN GP_ARG_MIN_REG
1474 #define FP_ARG_RETURN FP_ARG_MIN_REG
1475 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1476 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1477 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1478 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1479 ? (ALTIVEC_ARG_RETURN \
1480 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1481 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1483 /* Flags for the call/call_value rtl operations set up by function_arg */
1484 #define CALL_NORMAL 0x00000000 /* no special processing */
1485 /* Bits in 0x00000001 are unused. */
1486 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1487 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1488 #define CALL_LONG 0x00000008 /* always call indirect */
1489 #define CALL_LIBCALL 0x00000010 /* libcall */
1491 #define IS_V4_FP_ARGS(OP) \
1492 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0)
1494 /* Whether OP is an UNSPEC used in !TARGET_TLS_MARKER calls. */
1495 #define IS_NOMARK_TLSGETADDR(OP) \
1496 (!TARGET_TLS_MARKERS \
1497 && GET_CODE (OP) == UNSPEC \
1498 && (XINT (OP, 1) == UNSPEC_TLSGD \
1499 || XINT (OP, 1) == UNSPEC_TLSLD))
1501 /* We don't have prologue and epilogue functions to save/restore
1502 everything for most ABIs. */
1503 #define WORLD_SAVE_P(INFO) 0
1505 /* 1 if N is a possible register number for a function value
1506 as seen by the caller.
1508 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1509 #define FUNCTION_VALUE_REGNO_P(N) \
1510 ((N) == GP_ARG_RETURN \
1511 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1512 && TARGET_HARD_FLOAT) \
1513 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1514 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1516 /* 1 if N is a possible register number for function argument passing.
1517 On RS/6000, these are r3-r10 and fp1-fp13.
1518 On AltiVec, v2 - v13 are used for passing vectors. */
1519 #define FUNCTION_ARG_REGNO_P(N) \
1520 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1521 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1522 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1523 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1524 && TARGET_HARD_FLOAT))
1526 /* Define a data type for recording info about an argument list
1527 during the scan of that argument list. This data type should
1528 hold all necessary information about the function itself
1529 and about the args processed so far, enough to enable macros
1530 such as FUNCTION_ARG to determine where the next arg should go.
1532 On the RS/6000, this is a structure. The first element is the number of
1533 total argument words, the second is used to store the next
1534 floating-point register number, and the third says how many more args we
1535 have prototype types for.
1537 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1538 the next available GP register, `fregno' is the next available FP
1539 register, and `words' is the number of words used on the stack.
1541 The varargs/stdarg support requires that this structure's size
1542 be a multiple of sizeof(int). */
1544 typedef struct rs6000_args
1546 int words; /* # words used for passing GP registers */
1547 int fregno; /* next available FP register */
1548 int vregno; /* next available AltiVec register */
1549 int nargs_prototype; /* # args left in the current prototype */
1550 int prototype; /* Whether a prototype was defined */
1551 int stdarg; /* Whether function is a stdarg function. */
1552 int call_cookie; /* Do special things for this call */
1553 int sysv_gregno; /* next available GP register */
1554 int intoffset; /* running offset in struct (darwin64) */
1555 int use_stack; /* any part of struct on stack (darwin64) */
1556 int floats_in_gpr; /* count of SFmode floats taking up
1557 GPR space (darwin64) */
1558 int named; /* false for varargs params */
1559 int escapes; /* if function visible outside tu */
1560 int libcall; /* If this is a compiler generated call. */
1563 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1564 for a call to a function whose data type is FNTYPE.
1565 For a library call, FNTYPE is 0. */
1567 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1568 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1569 N_NAMED_ARGS, FNDECL, VOIDmode)
1571 /* Similar, but when scanning the definition of a procedure. We always
1572 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1574 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1575 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1576 1000, current_function_decl, VOIDmode)
1578 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1580 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1581 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1584 #define PAD_VARARGS_DOWN \
1585 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1587 /* Output assembler code to FILE to increment profiler label # LABELNO
1588 for profiling a function entry. */
1590 #define FUNCTION_PROFILER(FILE, LABELNO) \
1591 output_function_profiler ((FILE), (LABELNO));
1593 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1594 the stack pointer does not matter. No definition is equivalent to
1597 On the RS/6000, this is nonzero because we can restore the stack from
1598 its backpointer, which we maintain. */
1599 #define EXIT_IGNORE_STACK 1
1601 /* Define this macro as a C expression that is nonzero for registers
1602 that are used by the epilogue or the return' pattern. The stack
1603 and frame pointer registers are already be assumed to be used as
1606 #define EPILOGUE_USES(REGNO) \
1607 ((reload_completed && (REGNO) == LR_REGNO) \
1608 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1609 || (crtl->calls_eh_return \
1614 /* Length in units of the trampoline for entering a nested function. */
1616 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1618 /* Definitions for __builtin_return_address and __builtin_frame_address.
1619 __builtin_return_address (0) should give link register (LR_REGNO), enable
1621 /* This should be uncommented, so that the link register is used, but
1622 currently this would result in unmatched insns and spilling fixed
1623 registers so we'll leave it for another day. When these problems are
1624 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1626 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1628 /* Number of bytes into the frame return addresses can be found. See
1629 rs6000_stack_info in rs6000.c for more information on how the different
1630 abi's store the return address. */
1631 #define RETURN_ADDRESS_OFFSET \
1632 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1634 /* The current return address is in the link register. The return address
1635 of anything farther back is accessed normally at an offset of 8 from the
1637 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1638 (rs6000_return_addr (COUNT, FRAME))
1641 /* Definitions for register eliminations.
1643 We have two registers that can be eliminated on the RS/6000. First, the
1644 frame pointer register can often be eliminated in favor of the stack
1645 pointer register. Secondly, the argument pointer register can always be
1646 eliminated; it is replaced with either the stack or frame pointer.
1648 In addition, we use the elimination mechanism to see if r30 is needed
1649 Initially we assume that it isn't. If it is, we spill it. This is done
1650 by making it an eliminable register. We replace it with itself so that
1651 if it isn't needed, then existing uses won't be modified. */
1653 /* This is an array of structures. Each structure initializes one pair
1654 of eliminable registers. The "from" register number is given first,
1655 followed by "to". Eliminations of the same "from" register are listed
1656 in order of preference. */
1657 #define ELIMINABLE_REGS \
1658 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1659 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1660 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1661 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1662 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1663 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1665 /* Define the offset between two registers, one to be eliminated, and the other
1666 its replacement, at the start of a routine. */
1667 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1668 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1670 /* Addressing modes, and classification of registers for them. */
1672 #define HAVE_PRE_DECREMENT 1
1673 #define HAVE_PRE_INCREMENT 1
1674 #define HAVE_PRE_MODIFY_DISP 1
1675 #define HAVE_PRE_MODIFY_REG 1
1677 /* Macros to check register numbers against specific register classes. */
1679 /* These assume that REGNO is a hard or pseudo reg number.
1680 They give nonzero only if REGNO is a hard reg of the suitable class
1681 or a pseudo reg currently allocated to a suitable hard reg.
1682 Since they use reg_renumber, they are safe only once reg_renumber
1683 has been allocated, which happens in reginfo.c during register
1686 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1687 (HARD_REGISTER_NUM_P (REGNO) \
1689 || (REGNO) == ARG_POINTER_REGNUM \
1690 || (REGNO) == FRAME_POINTER_REGNUM \
1691 : (reg_renumber[REGNO] >= 0 \
1692 && (reg_renumber[REGNO] <= 31 \
1693 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1694 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1696 #define REGNO_OK_FOR_BASE_P(REGNO) \
1697 (HARD_REGISTER_NUM_P (REGNO) \
1698 ? ((REGNO) > 0 && (REGNO) <= 31) \
1699 || (REGNO) == ARG_POINTER_REGNUM \
1700 || (REGNO) == FRAME_POINTER_REGNUM \
1701 : (reg_renumber[REGNO] > 0 \
1702 && (reg_renumber[REGNO] <= 31 \
1703 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1704 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1706 /* Nonzero if X is a hard reg that can be used as an index
1707 or if it is a pseudo reg in the non-strict case. */
1708 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1709 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1710 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1712 /* Nonzero if X is a hard reg that can be used as a base reg
1713 or if it is a pseudo reg in the non-strict case. */
1714 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1715 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1716 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1719 /* Maximum number of registers that can appear in a valid memory address. */
1721 #define MAX_REGS_PER_ADDRESS 2
1723 /* Recognize any constant value that is a valid address. */
1725 #define CONSTANT_ADDRESS_P(X) \
1726 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \
1727 || CONST_INT_P (X) || GET_CODE (X) == CONST \
1728 || GET_CODE (X) == HIGH)
1730 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1731 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1732 && EASY_VECTOR_15((n) >> 1) \
1735 #define EASY_VECTOR_MSB(n,mode) \
1736 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1737 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1740 #define FIND_BASE_TERM rs6000_find_base_term
1742 /* The register number of the register used to address a table of
1743 static data addresses in memory. In some cases this register is
1744 defined by a processor's "application binary interface" (ABI).
1745 When this macro is defined, RTL is generated for this register
1746 once, as with the stack pointer and frame pointer registers. If
1747 this macro is not defined, it is up to the machine-dependent files
1748 to allocate such a register (if necessary). */
1750 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1751 #define PIC_OFFSET_TABLE_REGNUM \
1752 (TARGET_TOC ? TOC_REGISTER \
1753 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1756 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1758 /* Define this macro if the register defined by
1759 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1760 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1762 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1764 /* A C expression that is nonzero if X is a legitimate immediate
1765 operand on the target machine when generating position independent
1766 code. You can assume that X satisfies `CONSTANT_P', so you need
1767 not check this. You can also assume FLAG_PIC is true, so you need
1768 not check it either. You need not define this macro if all
1769 constants (including `SYMBOL_REF') can be immediate operands when
1770 generating position independent code. */
1772 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1774 /* Specify the machine mode that this machine uses
1775 for the index in the tablejump instruction. */
1776 #define CASE_VECTOR_MODE SImode
1778 /* Define as C expression which evaluates to nonzero if the tablejump
1779 instruction expects the table to contain offsets from the address of the
1781 Do not define this if the table should contain absolute addresses. */
1782 #define CASE_VECTOR_PC_RELATIVE 1
1784 /* Define this as 1 if `char' should by default be signed; else as 0. */
1785 #define DEFAULT_SIGNED_CHAR 0
1787 /* An integer expression for the size in bits of the largest integer machine
1788 mode that should actually be used. */
1790 /* Allow pairs of registers to be used, which is the intent of the default. */
1791 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1793 /* Max number of bytes we can move from memory to memory
1794 in one reasonably fast instruction. */
1795 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1796 #define MAX_MOVE_MAX 8
1798 /* Nonzero if access to memory by bytes is no faster than for words.
1799 Also nonzero if doing byte operations (specifically shifts) in registers
1801 #define SLOW_BYTE_ACCESS 1
1803 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1804 will either zero-extend or sign-extend. The value of this macro should
1805 be the code that says which one of the two operations is implicitly
1806 done, UNKNOWN if none. */
1807 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1809 /* Define if loading short immediate values into registers sign extends. */
1810 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1812 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1813 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1814 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1816 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1817 zero. The hardware instructions added in Power9 and the sequences using
1818 popcount return 32 or 64. */
1819 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1820 (TARGET_CTZ || TARGET_POPCNTD \
1821 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1822 : ((VALUE) = -1, 2))
1824 /* Specify the machine mode that pointers have.
1825 After generation of rtl, the compiler makes no further distinction
1826 between pointers and any other objects of this machine mode. */
1827 extern scalar_int_mode rs6000_pmode;
1828 #define Pmode rs6000_pmode
1830 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1831 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1833 /* Mode of a function address in a call instruction (for indexing purposes).
1834 Doesn't matter on RS/6000. */
1835 #define FUNCTION_MODE SImode
1837 /* Define this if addresses of constant functions
1838 shouldn't be put through pseudo regs where they can be cse'd.
1839 Desirable on machines where ordinary constants are expensive
1840 but a CALL with constant address is cheap. */
1841 #define NO_FUNCTION_CSE 1
1843 /* Define this to be nonzero if shift instructions ignore all but the low-order
1846 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1847 have been dropped from the PowerPC architecture. */
1848 #define SHIFT_COUNT_TRUNCATED 0
1850 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1851 should be adjusted to reflect any required changes. This macro is used when
1852 there is some systematic length adjustment required that would be difficult
1853 to express in the length attribute. */
1855 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1857 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1858 COMPARE, return the mode to be used for the comparison. For
1859 floating-point, CCFPmode should be used. CCUNSmode should be used
1860 for unsigned comparisons. CCEQmode should be used when we are
1861 doing an inequality comparison on the result of a
1862 comparison. CCmode should be used in all other cases. */
1864 #define SELECT_CC_MODE(OP,X,Y) \
1865 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1866 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1867 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1868 ? CCEQmode : CCmode))
1870 /* Can the condition code MODE be safely reversed? This is safe in
1871 all cases on this port, because at present it doesn't use the
1872 trapping FP comparisons (fcmpo). */
1873 #define REVERSIBLE_CC_MODE(MODE) 1
1875 /* Given a condition code and a mode, return the inverse condition. */
1876 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1879 /* Target cpu costs. */
1881 struct processor_costs {
1882 const int mulsi; /* cost of SImode multiplication. */
1883 const int mulsi_const; /* cost of SImode multiplication by constant. */
1884 const int mulsi_const9; /* cost of SImode mult by short constant. */
1885 const int muldi; /* cost of DImode multiplication. */
1886 const int divsi; /* cost of SImode division. */
1887 const int divdi; /* cost of DImode division. */
1888 const int fp; /* cost of simple SFmode and DFmode insns. */
1889 const int dmul; /* cost of DFmode multiplication (and fmadd). */
1890 const int sdiv; /* cost of SFmode division (fdivs). */
1891 const int ddiv; /* cost of DFmode division (fdiv). */
1892 const int cache_line_size; /* cache line size in bytes. */
1893 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
1894 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
1895 const int simultaneous_prefetches; /* number of parallel prefetch
1897 const int sfdf_convert; /* cost of SF->DF conversion. */
1900 extern const struct processor_costs *rs6000_cost;
1902 /* Control the assembler format that we output. */
1904 /* A C string constant describing how to begin a comment in the target
1905 assembler language. The compiler assumes that the comment will end at
1906 the end of the line. */
1907 #define ASM_COMMENT_START " #"
1909 /* Flag to say the TOC is initialized */
1910 extern int toc_initialized;
1912 /* Macro to output a special constant pool entry. Go to WIN if we output
1913 it. Otherwise, it is written the usual way.
1915 On the RS/6000, toc entries are handled this way. */
1917 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1918 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1920 output_toc (FILE, X, LABELNO, MODE); \
1925 #ifdef HAVE_GAS_WEAK
1926 #define RS6000_WEAK 1
1928 #define RS6000_WEAK 0
1932 /* Used in lieu of ASM_WEAKEN_LABEL. */
1933 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1934 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
1937 #if HAVE_GAS_WEAKREF
1938 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1941 fputs ("\t.weakref\t", (FILE)); \
1942 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1943 fputs (", ", (FILE)); \
1944 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1945 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1946 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1948 fputs ("\n\t.weakref\t.", (FILE)); \
1949 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1950 fputs (", .", (FILE)); \
1951 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1953 fputc ('\n', (FILE)); \
1957 /* This implements the `alias' attribute. */
1958 #undef ASM_OUTPUT_DEF_FROM_DECLS
1959 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1962 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1963 const char *name = IDENTIFIER_POINTER (TARGET); \
1964 if (TREE_CODE (DECL) == FUNCTION_DECL \
1965 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1967 if (TREE_PUBLIC (DECL)) \
1969 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1971 fputs ("\t.globl\t.", FILE); \
1972 RS6000_OUTPUT_BASENAME (FILE, alias); \
1973 putc ('\n', FILE); \
1976 else if (TARGET_XCOFF) \
1978 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1980 fputs ("\t.lglobl\t.", FILE); \
1981 RS6000_OUTPUT_BASENAME (FILE, alias); \
1982 putc ('\n', FILE); \
1983 fputs ("\t.lglobl\t", FILE); \
1984 RS6000_OUTPUT_BASENAME (FILE, alias); \
1985 putc ('\n', FILE); \
1988 fputs ("\t.set\t.", FILE); \
1989 RS6000_OUTPUT_BASENAME (FILE, alias); \
1990 fputs (",.", FILE); \
1991 RS6000_OUTPUT_BASENAME (FILE, name); \
1992 fputc ('\n', FILE); \
1994 ASM_OUTPUT_DEF (FILE, alias, name); \
1998 #define TARGET_ASM_FILE_START rs6000_file_start
2000 /* Output to assembler file text saying following lines
2001 may contain character constants, extra white space, comments, etc. */
2003 #define ASM_APP_ON ""
2005 /* Output to assembler file text saying following lines
2006 no longer contain unusual constructs. */
2008 #define ASM_APP_OFF ""
2010 /* How to refer to registers in assembler output.
2011 This sequence is indexed by compiler's hard-register-number (see above). */
2013 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2015 #define REGISTER_NAMES \
2017 &rs6000_reg_names[ 0][0], /* r0 */ \
2018 &rs6000_reg_names[ 1][0], /* r1 */ \
2019 &rs6000_reg_names[ 2][0], /* r2 */ \
2020 &rs6000_reg_names[ 3][0], /* r3 */ \
2021 &rs6000_reg_names[ 4][0], /* r4 */ \
2022 &rs6000_reg_names[ 5][0], /* r5 */ \
2023 &rs6000_reg_names[ 6][0], /* r6 */ \
2024 &rs6000_reg_names[ 7][0], /* r7 */ \
2025 &rs6000_reg_names[ 8][0], /* r8 */ \
2026 &rs6000_reg_names[ 9][0], /* r9 */ \
2027 &rs6000_reg_names[10][0], /* r10 */ \
2028 &rs6000_reg_names[11][0], /* r11 */ \
2029 &rs6000_reg_names[12][0], /* r12 */ \
2030 &rs6000_reg_names[13][0], /* r13 */ \
2031 &rs6000_reg_names[14][0], /* r14 */ \
2032 &rs6000_reg_names[15][0], /* r15 */ \
2033 &rs6000_reg_names[16][0], /* r16 */ \
2034 &rs6000_reg_names[17][0], /* r17 */ \
2035 &rs6000_reg_names[18][0], /* r18 */ \
2036 &rs6000_reg_names[19][0], /* r19 */ \
2037 &rs6000_reg_names[20][0], /* r20 */ \
2038 &rs6000_reg_names[21][0], /* r21 */ \
2039 &rs6000_reg_names[22][0], /* r22 */ \
2040 &rs6000_reg_names[23][0], /* r23 */ \
2041 &rs6000_reg_names[24][0], /* r24 */ \
2042 &rs6000_reg_names[25][0], /* r25 */ \
2043 &rs6000_reg_names[26][0], /* r26 */ \
2044 &rs6000_reg_names[27][0], /* r27 */ \
2045 &rs6000_reg_names[28][0], /* r28 */ \
2046 &rs6000_reg_names[29][0], /* r29 */ \
2047 &rs6000_reg_names[30][0], /* r30 */ \
2048 &rs6000_reg_names[31][0], /* r31 */ \
2050 &rs6000_reg_names[32][0], /* fr0 */ \
2051 &rs6000_reg_names[33][0], /* fr1 */ \
2052 &rs6000_reg_names[34][0], /* fr2 */ \
2053 &rs6000_reg_names[35][0], /* fr3 */ \
2054 &rs6000_reg_names[36][0], /* fr4 */ \
2055 &rs6000_reg_names[37][0], /* fr5 */ \
2056 &rs6000_reg_names[38][0], /* fr6 */ \
2057 &rs6000_reg_names[39][0], /* fr7 */ \
2058 &rs6000_reg_names[40][0], /* fr8 */ \
2059 &rs6000_reg_names[41][0], /* fr9 */ \
2060 &rs6000_reg_names[42][0], /* fr10 */ \
2061 &rs6000_reg_names[43][0], /* fr11 */ \
2062 &rs6000_reg_names[44][0], /* fr12 */ \
2063 &rs6000_reg_names[45][0], /* fr13 */ \
2064 &rs6000_reg_names[46][0], /* fr14 */ \
2065 &rs6000_reg_names[47][0], /* fr15 */ \
2066 &rs6000_reg_names[48][0], /* fr16 */ \
2067 &rs6000_reg_names[49][0], /* fr17 */ \
2068 &rs6000_reg_names[50][0], /* fr18 */ \
2069 &rs6000_reg_names[51][0], /* fr19 */ \
2070 &rs6000_reg_names[52][0], /* fr20 */ \
2071 &rs6000_reg_names[53][0], /* fr21 */ \
2072 &rs6000_reg_names[54][0], /* fr22 */ \
2073 &rs6000_reg_names[55][0], /* fr23 */ \
2074 &rs6000_reg_names[56][0], /* fr24 */ \
2075 &rs6000_reg_names[57][0], /* fr25 */ \
2076 &rs6000_reg_names[58][0], /* fr26 */ \
2077 &rs6000_reg_names[59][0], /* fr27 */ \
2078 &rs6000_reg_names[60][0], /* fr28 */ \
2079 &rs6000_reg_names[61][0], /* fr29 */ \
2080 &rs6000_reg_names[62][0], /* fr30 */ \
2081 &rs6000_reg_names[63][0], /* fr31 */ \
2083 &rs6000_reg_names[64][0], /* vr0 */ \
2084 &rs6000_reg_names[65][0], /* vr1 */ \
2085 &rs6000_reg_names[66][0], /* vr2 */ \
2086 &rs6000_reg_names[67][0], /* vr3 */ \
2087 &rs6000_reg_names[68][0], /* vr4 */ \
2088 &rs6000_reg_names[69][0], /* vr5 */ \
2089 &rs6000_reg_names[70][0], /* vr6 */ \
2090 &rs6000_reg_names[71][0], /* vr7 */ \
2091 &rs6000_reg_names[72][0], /* vr8 */ \
2092 &rs6000_reg_names[73][0], /* vr9 */ \
2093 &rs6000_reg_names[74][0], /* vr10 */ \
2094 &rs6000_reg_names[75][0], /* vr11 */ \
2095 &rs6000_reg_names[76][0], /* vr12 */ \
2096 &rs6000_reg_names[77][0], /* vr13 */ \
2097 &rs6000_reg_names[78][0], /* vr14 */ \
2098 &rs6000_reg_names[79][0], /* vr15 */ \
2099 &rs6000_reg_names[80][0], /* vr16 */ \
2100 &rs6000_reg_names[81][0], /* vr17 */ \
2101 &rs6000_reg_names[82][0], /* vr18 */ \
2102 &rs6000_reg_names[83][0], /* vr19 */ \
2103 &rs6000_reg_names[84][0], /* vr20 */ \
2104 &rs6000_reg_names[85][0], /* vr21 */ \
2105 &rs6000_reg_names[86][0], /* vr22 */ \
2106 &rs6000_reg_names[87][0], /* vr23 */ \
2107 &rs6000_reg_names[88][0], /* vr24 */ \
2108 &rs6000_reg_names[89][0], /* vr25 */ \
2109 &rs6000_reg_names[90][0], /* vr26 */ \
2110 &rs6000_reg_names[91][0], /* vr27 */ \
2111 &rs6000_reg_names[92][0], /* vr28 */ \
2112 &rs6000_reg_names[93][0], /* vr29 */ \
2113 &rs6000_reg_names[94][0], /* vr30 */ \
2114 &rs6000_reg_names[95][0], /* vr31 */ \
2116 &rs6000_reg_names[96][0], /* lr */ \
2117 &rs6000_reg_names[97][0], /* ctr */ \
2118 &rs6000_reg_names[98][0], /* ca */ \
2119 &rs6000_reg_names[99][0], /* ap */ \
2121 &rs6000_reg_names[100][0], /* cr0 */ \
2122 &rs6000_reg_names[101][0], /* cr1 */ \
2123 &rs6000_reg_names[102][0], /* cr2 */ \
2124 &rs6000_reg_names[103][0], /* cr3 */ \
2125 &rs6000_reg_names[104][0], /* cr4 */ \
2126 &rs6000_reg_names[105][0], /* cr5 */ \
2127 &rs6000_reg_names[106][0], /* cr6 */ \
2128 &rs6000_reg_names[107][0], /* cr7 */ \
2130 &rs6000_reg_names[108][0], /* vrsave */ \
2131 &rs6000_reg_names[109][0], /* vscr */ \
2133 &rs6000_reg_names[110][0] /* sfp */ \
2136 /* Table of additional register names to use in user input. */
2138 #define ADDITIONAL_REGISTER_NAMES \
2139 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2140 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2141 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2142 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2143 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2144 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2145 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2146 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2147 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2148 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2149 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2150 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2151 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2152 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2153 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2154 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2155 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \
2156 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \
2157 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \
2158 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \
2159 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \
2160 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \
2161 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \
2162 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \
2163 {"vrsave", 108}, {"vscr", 109}, \
2164 /* no additional names for: lr, ctr, ap */ \
2165 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \
2166 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \
2167 {"cc", 100},{"sp", 1}, {"toc", 2}, \
2168 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2170 /* VSX registers overlaid on top of FR, Altivec registers */ \
2171 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2172 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2173 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2174 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2175 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2176 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2177 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2178 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2179 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \
2180 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \
2181 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \
2182 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \
2183 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \
2184 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \
2185 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \
2186 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \
2189 /* This is how to output an element of a case-vector that is relative. */
2191 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2192 do { char buf[100]; \
2193 fputs ("\t.long ", FILE); \
2194 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2195 assemble_name (FILE, buf); \
2197 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2198 assemble_name (FILE, buf); \
2199 putc ('\n', FILE); \
2202 /* This is how to output an assembler line
2203 that says to advance the location counter
2204 to a multiple of 2**LOG bytes. */
2206 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2208 fprintf (FILE, "\t.align %d\n", (LOG))
2210 /* How to align the given loop. */
2211 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2213 /* Alignment guaranteed by __builtin_malloc. */
2214 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2215 However, specifying the stronger guarantee currently leads to
2216 a regression in SPEC CPU2006 437.leslie3d. The stronger
2217 guarantee should be implemented here once that's fixed. */
2218 #define MALLOC_ABI_ALIGNMENT (64)
2220 /* Pick up the return address upon entry to a procedure. Used for
2221 dwarf2 unwind information. This also enables the table driven
2224 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2225 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2227 /* Describe how we implement __builtin_eh_return. */
2228 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2229 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2231 /* Print operand X (an rtx) in assembler syntax to file FILE.
2232 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2233 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2235 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2237 /* Define which CODE values are valid. */
2239 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2241 /* Print a memory address as an operand to reference that memory location. */
2243 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2245 /* For switching between functions with different target attributes. */
2246 #define SWITCHABLE_TARGET 1
2248 /* uncomment for disabling the corresponding default options */
2249 /* #define MACHINE_no_sched_interblock */
2250 /* #define MACHINE_no_sched_speculative */
2251 /* #define MACHINE_no_sched_speculative_load */
2253 /* General flags. */
2254 extern int frame_pointer_needed;
2256 /* Classification of the builtin functions as to which switches enable the
2257 builtin, and what attributes it should have. We used to use the target
2258 flags macros, but we've run out of bits, so we now map the options into new
2259 settings used here. */
2261 /* Builtin attributes. */
2262 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2263 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2264 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2265 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2266 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2267 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2268 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2269 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2271 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2272 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
2273 modifies global state. */
2274 #define RS6000_BTC_PURE 0x00000200 /* reads global
2276 not modify global state. */
2277 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2278 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2280 /* Miscellaneous information. */
2281 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2282 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2283 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */
2284 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */
2285 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2287 /* Convenience macros to document the instruction type. */
2288 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2289 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2291 /* Builtin targets. For now, we reuse the masks for those options that are in
2292 target flags, and pick a random bit for ldbl128, which isn't in
2294 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2295 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2296 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2297 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2298 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2299 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2300 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2301 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2302 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2303 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2304 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2305 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2306 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2307 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2308 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2309 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2310 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2311 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2312 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2313 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
2314 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
2315 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
2317 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2319 | RS6000_BTM_P8_VECTOR \
2320 | RS6000_BTM_P9_VECTOR \
2321 | RS6000_BTM_P9_MISC \
2322 | RS6000_BTM_MODULO \
2323 | RS6000_BTM_CRYPTO \
2326 | RS6000_BTM_FRSQRTE \
2327 | RS6000_BTM_FRSQRTES \
2329 | RS6000_BTM_POPCNTD \
2332 | RS6000_BTM_HARD_FLOAT \
2333 | RS6000_BTM_LDBL128 \
2334 | RS6000_BTM_POWERPC64 \
2335 | RS6000_BTM_FLOAT128 \
2336 | RS6000_BTM_FLOAT128_HW)
2338 /* Define builtin enum index. */
2340 #undef RS6000_BUILTIN_0
2341 #undef RS6000_BUILTIN_1
2342 #undef RS6000_BUILTIN_2
2343 #undef RS6000_BUILTIN_3
2344 #undef RS6000_BUILTIN_A
2345 #undef RS6000_BUILTIN_D
2346 #undef RS6000_BUILTIN_H
2347 #undef RS6000_BUILTIN_P
2348 #undef RS6000_BUILTIN_X
2350 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2351 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2352 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2353 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2354 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2355 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2356 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2357 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2358 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2360 enum rs6000_builtins
2362 #include "rs6000-builtin.def"
2364 RS6000_BUILTIN_COUNT
2367 #undef RS6000_BUILTIN_0
2368 #undef RS6000_BUILTIN_1
2369 #undef RS6000_BUILTIN_2
2370 #undef RS6000_BUILTIN_3
2371 #undef RS6000_BUILTIN_A
2372 #undef RS6000_BUILTIN_D
2373 #undef RS6000_BUILTIN_H
2374 #undef RS6000_BUILTIN_P
2375 #undef RS6000_BUILTIN_X
2377 enum rs6000_builtin_type_index
2379 RS6000_BTI_NOT_OPAQUE,
2380 RS6000_BTI_opaque_V4SI,
2381 RS6000_BTI_V16QI, /* __vector signed char */
2389 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */
2390 RS6000_BTI_unsigned_V1TI,
2391 RS6000_BTI_unsigned_V8HI,
2392 RS6000_BTI_unsigned_V4SI,
2393 RS6000_BTI_unsigned_V2DI,
2394 RS6000_BTI_bool_char, /* __bool char */
2395 RS6000_BTI_bool_short, /* __bool short */
2396 RS6000_BTI_bool_int, /* __bool int */
2397 RS6000_BTI_bool_long_long, /* __bool long long */
2398 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4
2399 channels of 1, 5, 5, and 5 bits
2400 respectively as packed with the
2401 vpkpx insn. __pixel is only
2402 meaningful as a vector type.
2403 There is no corresponding scalar
2404 __pixel data type.) */
2405 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2406 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2407 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2408 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2409 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2410 RS6000_BTI_long, /* long_integer_type_node */
2411 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2412 RS6000_BTI_long_long, /* long_long_integer_type_node */
2413 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2414 RS6000_BTI_INTQI, /* (signed) intQI_type_node */
2415 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2416 RS6000_BTI_INTHI, /* intHI_type_node */
2417 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2418 RS6000_BTI_INTSI, /* intSI_type_node (signed) */
2419 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2420 RS6000_BTI_INTDI, /* intDI_type_node */
2421 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2422 RS6000_BTI_INTTI, /* intTI_type_node */
2423 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */
2424 RS6000_BTI_float, /* float_type_node */
2425 RS6000_BTI_double, /* double_type_node */
2426 RS6000_BTI_long_double, /* long_double_type_node */
2427 RS6000_BTI_dfloat64, /* dfloat64_type_node */
2428 RS6000_BTI_dfloat128, /* dfloat128_type_node */
2429 RS6000_BTI_void, /* void_type_node */
2430 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */
2431 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */
2432 RS6000_BTI_const_str, /* pointer to const char * */
2437 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2438 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2439 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2440 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2441 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2442 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2443 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2444 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2445 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2446 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2447 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2448 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2449 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2450 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2451 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2452 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2453 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2454 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2455 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2456 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2457 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2458 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2459 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2460 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2462 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2463 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2464 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2465 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2466 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2467 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2468 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2469 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2470 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2471 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2472 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2473 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2474 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2475 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2476 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2477 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2478 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2479 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2480 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2481 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2482 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2483 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2484 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2486 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2487 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
2489 #define TARGET_SUPPORTS_WIDE_INT 1
2491 #if (GCC_VERSION >= 3000)
2492 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128