1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/rs6000/rs6000-opts.h"
33 /* Definitions for the object file format. These are set at
36 #define OBJECT_XCOFF 1
39 #define OBJECT_MACHO 4
41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
51 #define TARGET_AIX_OS 0
54 /* Control whether function entry points use a "dot" symbol when
58 /* Default string to use for cpu if not specified. */
59 #ifndef TARGET_CPU_DEFAULT
60 #define TARGET_CPU_DEFAULT ((char *)0)
63 /* If configured for PPC405, support PPC405CR Erratum77. */
64 #ifdef CONFIG_PPC405CR
65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
67 #define PPC405_ERRATUM77 0
70 #ifdef HAVE_AS_POPCNTB
71 #define ASM_CPU_POWER5_SPEC "-mpower5"
73 #define ASM_CPU_POWER5_SPEC "-mpower4"
77 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
79 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
82 #ifdef HAVE_AS_POPCNTD
83 #define ASM_CPU_POWER7_SPEC "-mpower7"
85 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
89 #define ASM_CPU_POWER8_SPEC "-mpower8"
91 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC
95 #define ASM_CPU_POWER9_SPEC "-mpower9"
97 #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC
101 #define ASM_CPU_476_SPEC "-m476"
103 #define ASM_CPU_476_SPEC "-mpower4"
106 /* Common ASM definitions used by ASM_SPEC among the various targets for
107 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
108 provide the default assembler options if the user uses -mcpu=native, so if
109 you make changes here, make them also there. */
110 #define ASM_CPU_SPEC \
112 %{mpowerpc64*: -mppc64} \
113 %{!mpowerpc64*: %(asm_default)}} \
114 %{mcpu=native: %(asm_cpu_native)} \
115 %{mcpu=cell: -mcell} \
116 %{mcpu=power3: -mppc64} \
117 %{mcpu=power4: -mpower4} \
118 %{mcpu=power5: %(asm_cpu_power5)} \
119 %{mcpu=power5+: %(asm_cpu_power5)} \
120 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
121 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
122 %{mcpu=power7: %(asm_cpu_power7)} \
123 %{mcpu=power8: %(asm_cpu_power8)} \
124 %{mcpu=power9: %(asm_cpu_power9)} \
126 %{mcpu=powerpc: -mppc} \
127 %{mcpu=powerpc64le: %(asm_cpu_power8)} \
128 %{mcpu=rs64a: -mppc64} \
132 %{mcpu=405fp: -m405} \
134 %{mcpu=440fp: -m440} \
136 %{mcpu=464fp: -m440} \
137 %{mcpu=476: %(asm_cpu_476)} \
138 %{mcpu=476fp: %(asm_cpu_476)} \
143 %{mcpu=603e: -mppc} \
144 %{mcpu=ec603e: -mppc} \
146 %{mcpu=604e: -mppc} \
147 %{mcpu=620: -mppc64} \
148 %{mcpu=630: -mppc64} \
152 %{mcpu=7400: -mppc -maltivec} \
153 %{mcpu=7450: -mppc -maltivec} \
154 %{mcpu=G4: -mppc -maltivec} \
159 %{mcpu=970: -mpower4 -maltivec} \
160 %{mcpu=G5: -mpower4 -maltivec} \
161 %{mcpu=8540: -me500} \
162 %{mcpu=8548: -me500} \
163 %{mcpu=e300c2: -me300} \
164 %{mcpu=e300c3: -me300} \
165 %{mcpu=e500mc: -me500mc} \
166 %{mcpu=e500mc64: -me500mc64} \
167 %{mcpu=e5500: -me5500} \
168 %{mcpu=e6500: -me6500} \
169 %{maltivec: -maltivec} \
170 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
171 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
174 #define CPP_DEFAULT_SPEC ""
176 #define ASM_DEFAULT_SPEC ""
178 /* This macro defines names of additional specifications to put in the specs
179 that can be used in various specifications like CC1_SPEC. Its definition
180 is an initializer with a subgrouping for each command option.
182 Each subgrouping contains a string constant, that defines the
183 specification name, and a string constant that used by the GCC driver
186 Do not define this macro if it does not need to do anything. */
188 #define SUBTARGET_EXTRA_SPECS
190 #define EXTRA_SPECS \
191 { "cpp_default", CPP_DEFAULT_SPEC }, \
192 { "asm_cpu", ASM_CPU_SPEC }, \
193 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
194 { "asm_default", ASM_DEFAULT_SPEC }, \
195 { "cc1_cpu", CC1_CPU_SPEC }, \
196 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
197 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
198 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
199 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \
200 { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \
201 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
202 SUBTARGET_EXTRA_SPECS
204 /* -mcpu=native handling only makes sense with compiler running on
205 an PowerPC chip. If changing this condition, also change
206 the condition in driver-rs6000.c. */
207 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
208 /* In driver-rs6000.c. */
209 extern const char *host_detect_local_cpu (int argc, const char **argv);
210 #define EXTRA_SPEC_FUNCTIONS \
211 { "local_cpu_detect", host_detect_local_cpu },
212 #define HAVE_LOCAL_CPU_DETECT
213 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
216 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
220 #ifdef HAVE_LOCAL_CPU_DETECT
221 #define CC1_CPU_SPEC \
222 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
223 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
225 #define CC1_CPU_SPEC ""
229 /* Architecture type. */
231 /* Define TARGET_MFCRF if the target assembler does not support the
232 optional field operand for mfcr. */
234 #ifndef HAVE_AS_MFCRF
236 #define TARGET_MFCRF 0
239 /* Define TARGET_POPCNTB if the target assembler does not support the
240 popcount byte instruction. */
242 #ifndef HAVE_AS_POPCNTB
243 #undef TARGET_POPCNTB
244 #define TARGET_POPCNTB 0
247 /* Define TARGET_FPRND if the target assembler does not support the
248 fp rounding instructions. */
250 #ifndef HAVE_AS_FPRND
252 #define TARGET_FPRND 0
255 /* Define TARGET_CMPB if the target assembler does not support the
260 #define TARGET_CMPB 0
263 /* Define TARGET_MFPGPR if the target assembler does not support the
264 mffpr and mftgpr instructions. */
266 #ifndef HAVE_AS_MFPGPR
268 #define TARGET_MFPGPR 0
271 /* Define TARGET_DFP if the target assembler does not support decimal
272 floating point instructions. */
278 /* Define TARGET_POPCNTD if the target assembler does not support the
279 popcount word and double word instructions. */
281 #ifndef HAVE_AS_POPCNTD
282 #undef TARGET_POPCNTD
283 #define TARGET_POPCNTD 0
286 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the
287 waitasecond instruction. Allow -mpower8-fusion, since it does not add new
290 #ifndef HAVE_AS_POWER8
291 #undef TARGET_DIRECT_MOVE
294 #undef TARGET_P8_VECTOR
295 #define TARGET_DIRECT_MOVE 0
296 #define TARGET_CRYPTO 0
298 #define TARGET_P8_VECTOR 0
301 /* Define the ISA 3.0 flags as 0 if the target assembler does not support
302 Power9 instructions. Allow -mpower9-fusion, since it does not add new
303 instructions. Allow -misel, since it predates ISA 3.0 and does
304 not require any Power9 features. */
306 #ifndef HAVE_AS_POWER9
307 #undef TARGET_FLOAT128_HW
309 #undef TARGET_P9_VECTOR
310 #undef TARGET_P9_MINMAX
311 #undef TARGET_P9_MISC
312 #define TARGET_FLOAT128_HW 0
313 #define TARGET_MODULO 0
314 #define TARGET_P9_VECTOR 0
315 #define TARGET_P9_MINMAX 0
316 #define TARGET_P9_MISC 0
319 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
320 not, generate the lwsync code as an integer constant. */
321 #ifdef HAVE_AS_LWSYNC
322 #define TARGET_LWSYNC_INSTRUCTION 1
324 #define TARGET_LWSYNC_INSTRUCTION 0
327 /* Define TARGET_TLS_MARKERS if the target assembler does not support
328 arg markers for __tls_get_addr calls. */
329 #ifndef HAVE_AS_TLS_MARKERS
330 #undef TARGET_TLS_MARKERS
331 #define TARGET_TLS_MARKERS 0
333 #define TARGET_TLS_MARKERS tls_markers
336 #ifndef TARGET_SECURE_PLT
337 #define TARGET_SECURE_PLT 0
340 #ifndef TARGET_CMODEL
341 #define TARGET_CMODEL CMODEL_SMALL
344 #define TARGET_32BIT (! TARGET_64BIT)
347 #define HAVE_AS_TLS 0
350 #ifndef TARGET_LINK_STACK
351 #define TARGET_LINK_STACK 0
354 #ifndef SET_TARGET_LINK_STACK
355 #define SET_TARGET_LINK_STACK(X) do { } while (0)
358 #ifndef TARGET_FLOAT128_ENABLE_TYPE
359 #define TARGET_FLOAT128_ENABLE_TYPE 0
362 /* Return 1 for a symbol ref for a thread-local storage symbol. */
363 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
364 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
367 /* For libgcc2 we make sure this is a compile time constant */
368 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
369 #undef TARGET_POWERPC64
370 #define TARGET_POWERPC64 1
372 #undef TARGET_POWERPC64
373 #define TARGET_POWERPC64 0
376 /* The option machinery will define this. */
379 #define TARGET_DEFAULT (MASK_MULTIPLE)
381 /* Define generic processor types based upon current deployment. */
382 #define PROCESSOR_COMMON PROCESSOR_PPC601
383 #define PROCESSOR_POWERPC PROCESSOR_PPC604
384 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
386 /* Define the default processor. This is overridden by other tm.h files. */
387 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
388 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
390 /* Specify the dialect of assembler to use. Only new mnemonics are supported
391 starting with GCC 4.8, i.e. just one dialect, but for backwards
392 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
394 #define ASSEMBLER_DIALECT 1
397 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
398 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
399 #define MASK_DEBUG_REG 0x04 /* debug register handling */
400 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
401 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
402 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
403 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
404 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
409 | MASK_DEBUG_TARGET \
410 | MASK_DEBUG_BUILTIN)
412 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
413 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
414 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
415 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
416 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
417 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
418 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
420 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
421 long double format that uses a pair of doubles, or IEEE 128-bit floating
422 point. KFmode was added as a way to represent IEEE 128-bit floating point,
423 even if the default for long double is the IBM long double format.
424 Similarly IFmode is the IBM long double format even if the default is IEEE
425 128-bit. Don't allow IFmode if -msoft-float. */
426 #define FLOAT128_IEEE_P(MODE) \
427 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
428 && ((MODE) == TFmode || (MODE) == TCmode)) \
429 || ((MODE) == KFmode) || ((MODE) == KCmode))
431 #define FLOAT128_IBM_P(MODE) \
432 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
433 && ((MODE) == TFmode || (MODE) == TCmode)) \
434 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
436 /* Helper macros to say whether a 128-bit floating point type can go in a
437 single vector register, or whether it needs paired scalar values. */
438 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
440 #define FLOAT128_2REG_P(MODE) \
441 (FLOAT128_IBM_P (MODE) \
442 || ((MODE) == TDmode) \
443 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
445 /* Return true for floating point that does not use a vector register. */
446 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
447 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
449 /* Describe the vector unit used for arithmetic operations. */
450 extern enum rs6000_vector rs6000_vector_unit[];
452 #define VECTOR_UNIT_NONE_P(MODE) \
453 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
455 #define VECTOR_UNIT_VSX_P(MODE) \
456 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
458 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
459 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
461 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
462 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
464 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
465 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
467 (int)VECTOR_P8_VECTOR))
469 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
470 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
471 compatible, so allow it as well, rather than changing all of the uses of the
473 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
474 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
475 (int)VECTOR_ALTIVEC, \
476 (int)VECTOR_P8_VECTOR))
478 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
479 same unit as the vector unit we are using, but we may want to migrate to
480 using VSX style loads even for types handled by altivec. */
481 extern enum rs6000_vector rs6000_vector_mem[];
483 #define VECTOR_MEM_NONE_P(MODE) \
484 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
486 #define VECTOR_MEM_VSX_P(MODE) \
487 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
489 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
490 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
492 #define VECTOR_MEM_ALTIVEC_P(MODE) \
493 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
495 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
496 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
498 (int)VECTOR_P8_VECTOR))
500 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
501 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
502 (int)VECTOR_ALTIVEC, \
503 (int)VECTOR_P8_VECTOR))
505 /* Return the alignment of a given vector type, which is set based on the
506 vector unit use. VSX for instance can load 32 or 64 bit aligned words
507 without problems, while Altivec requires 128-bit aligned vectors. */
508 extern int rs6000_vector_align[];
510 #define VECTOR_ALIGN(MODE) \
511 ((rs6000_vector_align[(MODE)] != 0) \
512 ? rs6000_vector_align[(MODE)] \
513 : (int)GET_MODE_BITSIZE ((MODE)))
515 /* Determine the element order to use for vector instructions. By
516 default we use big-endian element order when targeting big-endian,
517 and little-endian element order when targeting little-endian. For
518 programs being ported from BE Power to LE Power, it can sometimes
519 be useful to use big-endian element order when targeting little-endian.
520 This is set via -maltivec=be, for example. */
521 #define VECTOR_ELT_ORDER_BIG \
522 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
524 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
525 with scalar instructions. */
526 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
528 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
529 with the ISA 3.0 MFVSRLD instructions. */
530 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
532 /* Alignment options for fields in structures for sub-targets following
534 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
535 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
537 Override the macro definitions when compiling libobjc to avoid undefined
538 reference to rs6000_alignment_flags due to library's use of GCC alignment
539 macros which use the macros below. */
541 #ifndef IN_TARGET_LIBS
542 #define MASK_ALIGN_POWER 0x00000000
543 #define MASK_ALIGN_NATURAL 0x00000001
544 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
546 #define TARGET_ALIGN_NATURAL 0
549 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
550 #define TARGET_IEEEQUAD rs6000_ieeequad
551 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
552 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
554 /* Define as 1 if we support multilibs for switching long double between IEEE
555 128-bit floating point and IBM extended double. */
556 #ifndef TARGET_IEEEQUAD_MULTILIB
557 #define TARGET_IEEEQUAD_MULTILIB 0
560 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
561 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
562 #define TARGET_FCFID (TARGET_POWERPC64 \
563 || TARGET_PPC_GPOPT /* 970/power4 */ \
564 || TARGET_POPCNTB /* ISA 2.02 */ \
565 || TARGET_CMPB /* ISA 2.05 */ \
566 || TARGET_POPCNTD) /* ISA 2.06 */
568 #define TARGET_FCTIDZ TARGET_FCFID
569 #define TARGET_STFIWX TARGET_PPC_GFXOPT
570 #define TARGET_LFIWAX TARGET_CMPB
571 #define TARGET_LFIWZX TARGET_POPCNTD
572 #define TARGET_FCFIDS TARGET_POPCNTD
573 #define TARGET_FCFIDU TARGET_POPCNTD
574 #define TARGET_FCFIDUS TARGET_POPCNTD
575 #define TARGET_FCTIDUZ TARGET_POPCNTD
576 #define TARGET_FCTIWUZ TARGET_POPCNTD
577 #define TARGET_CTZ TARGET_MODULO
578 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
579 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
581 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
582 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
583 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
584 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
586 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
589 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
590 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
591 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
593 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
595 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
597 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
598 in power7, so conditionalize them on p8 features. TImode syncs need quad
600 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
601 || TARGET_QUAD_MEMORY_ATOMIC \
602 || TARGET_DIRECT_MOVE)
604 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
606 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
607 to allocate the SDmode stack slot to get the value into the proper location
609 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
611 /* ISA 3.0 has new min/max functions that don't need fast math that are being
612 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
613 answers if the arguments are not in the normal range. */
614 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
615 && (TARGET_P9_MINMAX || !flag_trapping_math))
617 /* In switching from using target_flags to using rs6000_isa_flags, the options
618 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
619 OPTION_MASK_<xxx> back into MASK_<xxx>. */
620 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
621 #define MASK_CMPB OPTION_MASK_CMPB
622 #define MASK_CRYPTO OPTION_MASK_CRYPTO
623 #define MASK_DFP OPTION_MASK_DFP
624 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
625 #define MASK_DLMZB OPTION_MASK_DLMZB
626 #define MASK_EABI OPTION_MASK_EABI
627 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
628 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
629 #define MASK_FPRND OPTION_MASK_FPRND
630 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
631 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
632 #define MASK_HTM OPTION_MASK_HTM
633 #define MASK_ISEL OPTION_MASK_ISEL
634 #define MASK_MFCRF OPTION_MASK_MFCRF
635 #define MASK_MFPGPR OPTION_MASK_MFPGPR
636 #define MASK_MULHW OPTION_MASK_MULHW
637 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
638 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
639 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
640 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
641 #define MASK_P9_MISC OPTION_MASK_P9_MISC
642 #define MASK_POPCNTB OPTION_MASK_POPCNTB
643 #define MASK_POPCNTD OPTION_MASK_POPCNTD
644 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
645 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
646 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
647 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
648 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
649 #define MASK_UPDATE OPTION_MASK_UPDATE
650 #define MASK_VSX OPTION_MASK_VSX
653 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
657 #define MASK_64BIT OPTION_MASK_64BIT
660 #ifdef TARGET_LITTLE_ENDIAN
661 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
664 #ifdef TARGET_REGNAMES
665 #define MASK_REGNAMES OPTION_MASK_REGNAMES
668 #ifdef TARGET_PROTOTYPE
669 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
673 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
677 /* For power systems, we want to enable Altivec and VSX builtins even if the
678 user did not use -maltivec or -mvsx to allow the builtins to be used inside
679 of #pragma GCC target or the target attribute to change the code level for a
682 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
683 || TARGET_PPC_GPOPT /* 970/power4 */ \
684 || TARGET_POPCNTB /* ISA 2.02 */ \
685 || TARGET_CMPB /* ISA 2.05 */ \
686 || TARGET_POPCNTD /* ISA 2.06 */ \
689 || TARGET_HARD_FLOAT)
691 /* E500 cores only support plain "sync", not lwsync. */
692 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
693 || rs6000_cpu == PROCESSOR_PPC8548)
696 /* Which machine supports the various reciprocal estimate instructions. */
697 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
699 #define TARGET_FRE (TARGET_HARD_FLOAT \
700 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
702 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
703 && TARGET_PPC_GFXOPT)
705 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
706 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
708 /* Conditions to allow TOC fusion for loading/storing integers. */
709 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \
710 && TARGET_TOC_FUSION \
711 && (TARGET_CMODEL != CMODEL_SMALL) \
714 /* Conditions to allow TOC fusion for loading/storing floating point. */
715 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \
716 && TARGET_TOC_FUSION \
717 && (TARGET_CMODEL != CMODEL_SMALL) \
718 && TARGET_POWERPC64 \
719 && TARGET_HARD_FLOAT)
721 /* Macro to say whether we can do optimizations where we need to do parts of
722 the calculation in 64-bit GPRs and then is transfered to the vector
723 registers. Do not allow -maltivec=be for these optimizations, because it
724 adds to the complexity of the code. */
725 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
726 && TARGET_P8_VECTOR \
727 && TARGET_POWERPC64 \
728 && (rs6000_altivec_element_order != 2))
730 /* Whether the various reciprocal divide/square root estimate instructions
731 exist, and whether we should automatically generate code for the instruction
733 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
734 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
735 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
736 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
738 extern unsigned char rs6000_recip_bits[];
740 #define RS6000_RECIP_HAVE_RE_P(MODE) \
741 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
743 #define RS6000_RECIP_AUTO_RE_P(MODE) \
744 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
746 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
747 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
749 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
750 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
752 /* The default CPU for TARGET_OPTION_OVERRIDE. */
753 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
756 #define REGISTER_TARGET_PRAGMAS() do { \
757 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
758 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
759 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
760 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
763 /* Target #defines. */
764 #define TARGET_CPU_CPP_BUILTINS() \
765 rs6000_cpu_cpp_builtins (pfile)
767 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
768 we're compiling for. Some configurations may need to override it. */
769 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
772 if (BYTES_BIG_ENDIAN) \
774 builtin_define ("__BIG_ENDIAN__"); \
775 builtin_define ("_BIG_ENDIAN"); \
776 builtin_assert ("machine=bigendian"); \
780 builtin_define ("__LITTLE_ENDIAN__"); \
781 builtin_define ("_LITTLE_ENDIAN"); \
782 builtin_assert ("machine=littleendian"); \
787 /* Target machine storage layout. */
789 /* Define this macro if it is advisable to hold scalars in registers
790 in a wider mode than that declared by the program. In such cases,
791 the value is constrained to be within the bounds of the declared
792 type, but kept valid in the wider mode. The signedness of the
793 extension may differ from that of the type. */
795 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
796 if (GET_MODE_CLASS (MODE) == MODE_INT \
797 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
798 (MODE) = TARGET_32BIT ? SImode : DImode;
800 /* Define this if most significant bit is lowest numbered
801 in instructions that operate on numbered bit-fields. */
802 /* That is true on RS/6000. */
803 #define BITS_BIG_ENDIAN 1
805 /* Define this if most significant byte of a word is the lowest numbered. */
806 /* That is true on RS/6000. */
807 #define BYTES_BIG_ENDIAN 1
809 /* Define this if most significant word of a multiword number is lowest
812 For RS/6000 we can decide arbitrarily since there are no machine
813 instructions for them. Might as well be consistent with bits and bytes. */
814 #define WORDS_BIG_ENDIAN 1
816 /* This says that for the IBM long double the larger magnitude double
817 comes first. It's really a two element double array, and arrays
818 don't index differently between little- and big-endian. */
819 #define LONG_DOUBLE_LARGE_FIRST 1
821 #define MAX_BITS_PER_WORD 64
823 /* Width of a word, in units (bytes). */
824 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
826 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
828 #define MIN_UNITS_PER_WORD 4
830 #define UNITS_PER_FP_WORD 8
831 #define UNITS_PER_ALTIVEC_WORD 16
832 #define UNITS_PER_VSX_WORD 16
834 /* Type used for ptrdiff_t, as a string used in a declaration. */
835 #define PTRDIFF_TYPE "int"
837 /* Type used for size_t, as a string used in a declaration. */
838 #define SIZE_TYPE "long unsigned int"
840 /* Type used for wchar_t, as a string used in a declaration. */
841 #define WCHAR_TYPE "short unsigned int"
843 /* Width of wchar_t in bits. */
844 #define WCHAR_TYPE_SIZE 16
846 /* A C expression for the size in bits of the type `short' on the
847 target machine. If you don't define this, the default is half a
848 word. (If this would be less than one storage unit, it is
849 rounded up to one unit.) */
850 #define SHORT_TYPE_SIZE 16
852 /* A C expression for the size in bits of the type `int' on the
853 target machine. If you don't define this, the default is one
855 #define INT_TYPE_SIZE 32
857 /* A C expression for the size in bits of the type `long' on the
858 target machine. If you don't define this, the default is one
860 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
862 /* A C expression for the size in bits of the type `long long' on the
863 target machine. If you don't define this, the default is two
865 #define LONG_LONG_TYPE_SIZE 64
867 /* A C expression for the size in bits of the type `float' on the
868 target machine. If you don't define this, the default is one
870 #define FLOAT_TYPE_SIZE 32
872 /* A C expression for the size in bits of the type `double' on the
873 target machine. If you don't define this, the default is two
875 #define DOUBLE_TYPE_SIZE 64
877 /* A C expression for the size in bits of the type `long double' on
878 the target machine. If you don't define this, the default is two
880 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
882 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
883 #define WIDEST_HARDWARE_FP_SIZE 64
885 /* Width in bits of a pointer.
886 See also the macro `Pmode' defined below. */
887 extern unsigned rs6000_pointer_size;
888 #define POINTER_SIZE rs6000_pointer_size
890 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
891 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
893 /* Boundary (in *bits*) on which stack pointer should be aligned. */
894 #define STACK_BOUNDARY \
895 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
898 /* Allocation boundary (in *bits*) for the code of a function. */
899 #define FUNCTION_BOUNDARY 32
901 /* No data type wants to be aligned rounder than this. */
902 #define BIGGEST_ALIGNMENT 128
904 /* Alignment of field after `int : 0' in a structure. */
905 #define EMPTY_FIELD_BOUNDARY 32
907 /* Every structure's size must be a multiple of this. */
908 #define STRUCTURE_SIZE_BOUNDARY 8
910 /* A bit-field declared as `int' forces `int' alignment for the struct. */
911 #define PCC_BITFIELD_TYPE_MATTERS 1
913 enum data_align { align_abi, align_opt, align_both };
915 /* A C expression to compute the alignment for a variables in the
916 local store. TYPE is the data type, and ALIGN is the alignment
917 that the object would ordinarily have. */
918 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
919 rs6000_data_alignment (TYPE, ALIGN, align_both)
921 /* Make arrays of chars word-aligned for the same reasons. */
922 #define DATA_ALIGNMENT(TYPE, ALIGN) \
923 rs6000_data_alignment (TYPE, ALIGN, align_opt)
925 /* Align vectors to 128 bits. */
926 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
927 rs6000_data_alignment (TYPE, ALIGN, align_abi)
929 /* Nonzero if move instructions will actually fail to work
930 when given unaligned data. */
931 #define STRICT_ALIGNMENT 0
933 /* Standard register usage. */
935 /* Number of actual hardware registers.
936 The hardware registers are assigned numbers for the compiler
937 from 0 to just below FIRST_PSEUDO_REGISTER.
938 All registers that the compiler knows about must be given numbers,
939 even those that are not normally considered general registers.
941 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
942 a count register, a link register, and 8 condition register fields,
943 which we view here as separate registers. AltiVec adds 32 vector
944 registers and a VRsave register.
946 In addition, the difference between the frame and argument pointers is
947 a function of the number of registers saved, so we need to have a
948 register for AP that will later be eliminated in favor of SP or FP.
949 This is a normal register, but it is fixed.
951 We also create a pseudo register for float/int conversions, that will
952 really represent the memory location used. It is represented here as
953 a register, in order to work around problems in allocating stack storage
956 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
957 pointer, which is eventually eliminated in favor of SP or FP.
959 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
961 #define FIRST_PSEUDO_REGISTER 115
963 /* This must be included for pre gcc 3.0 glibc compatibility. */
964 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
966 /* The sfp register and 3 HTM registers
967 aren't included in DWARF_FRAME_REGISTERS. */
968 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
970 /* Use standard DWARF numbering for DWARF debugging information. */
971 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
973 /* Use gcc hard register numbering for eh_frame. */
974 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
976 /* Map register numbers held in the call frame info that gcc has
977 collected using DWARF_FRAME_REGNUM to those that should be output in
978 .debug_frame and .eh_frame. */
979 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
980 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
982 /* 1 for registers that have pervasive standard uses
983 and are not available for the register allocator.
985 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
986 as a local register; for all other OS's r2 is the TOC pointer.
988 On System V implementations, r13 is fixed and not available for use. */
990 #define FIXED_REGISTERS \
991 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
992 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
993 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
994 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
995 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
996 /* AltiVec registers. */ \
997 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
998 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1003 /* 1 for registers not available across function calls.
1004 These must include the FIXED_REGISTERS and also any
1005 registers that can be used without being saved.
1006 The latter must include the registers where values are returned
1007 and the register where structure-value addresses are passed.
1008 Aside from that, you can include as many other registers as you like. */
1010 #define CALL_USED_REGISTERS \
1011 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1012 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1013 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1014 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1015 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1016 /* AltiVec registers. */ \
1017 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1018 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1023 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
1024 the entire set of `FIXED_REGISTERS' be included.
1025 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
1026 This macro is optional. If not specified, it defaults to the value
1027 of `CALL_USED_REGISTERS'. */
1029 #define CALL_REALLY_USED_REGISTERS \
1030 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1031 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1032 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1033 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1034 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1035 /* AltiVec registers. */ \
1036 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1037 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1042 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
1044 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
1045 #define FIRST_SAVED_FP_REGNO (14+32)
1046 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
1048 /* List the order in which to allocate registers. Each register must be
1049 listed once, even those in FIXED_REGISTERS.
1051 We allocate in the following order:
1052 fp0 (not saved or used for anything)
1053 fp13 - fp2 (not saved; incoming fp arg registers)
1054 fp1 (not saved; return value)
1055 fp31 - fp14 (saved; order given to save least number)
1056 cr7, cr5 (not saved or special)
1057 cr6 (not saved, but used for vector operations)
1058 cr1 (not saved, but used for FP operations)
1059 cr0 (not saved, but used for arithmetic operations)
1060 cr4, cr3, cr2 (saved)
1061 r9 (not saved; best for TImode)
1062 r10, r8-r4 (not saved; highest first for less conflict with params)
1063 r3 (not saved; return value register)
1064 r11 (not saved; later alloc to help shrink-wrap)
1065 r0 (not saved; cannot be base reg)
1066 r31 - r13 (saved; order given to save least number)
1067 r12 (not saved; if used for DImode or DFmode would use r13)
1068 ctr (not saved; when we have the choice ctr is better)
1070 r1, r2, ap, ca (fixed)
1071 v0 - v1 (not saved or used for anything)
1072 v13 - v3 (not saved; incoming vector arg registers)
1073 v2 (not saved; incoming vector arg reg; return value)
1074 v19 - v14 (not saved or used for anything)
1075 v31 - v20 (saved; order given to save least number)
1076 vrsave, vscr (fixed)
1084 #define MAYBE_R2_AVAILABLE
1085 #define MAYBE_R2_FIXED 2,
1087 #define MAYBE_R2_AVAILABLE 2,
1088 #define MAYBE_R2_FIXED
1092 #define EARLY_R12 12,
1096 #define LATE_R12 12,
1099 #define REG_ALLOC_ORDER \
1101 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
1102 /* not use fr14 which is a saved register. */ \
1103 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
1105 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1106 50, 49, 48, 47, 46, \
1107 75, 73, 74, 69, 68, 72, 71, 70, \
1108 MAYBE_R2_AVAILABLE \
1109 9, 10, 8, 7, 6, 5, 4, \
1110 3, EARLY_R12 11, 0, \
1111 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1112 18, 17, 16, 15, 14, 13, LATE_R12 \
1114 1, MAYBE_R2_FIXED 67, 76, \
1115 /* AltiVec registers. */ \
1117 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1119 96, 95, 94, 93, 92, 91, \
1120 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1122 111, 112, 113, 114 \
1125 /* True if register is floating-point. */
1126 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1128 /* True if register is a condition register. */
1129 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
1131 /* True if register is a condition register, but not cr0. */
1132 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1134 /* True if register is an integer register. */
1135 #define INT_REGNO_P(N) \
1136 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1138 /* True if register is the CA register. */
1139 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1141 /* True if register is an AltiVec register. */
1142 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1144 /* True if register is a VSX register. */
1145 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1147 /* Alternate name for any vector register supporting floating point, no matter
1148 which instruction set(s) are available. */
1149 #define VFLOAT_REGNO_P(N) \
1150 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1152 /* Alternate name for any vector register supporting integer, no matter which
1153 instruction set(s) are available. */
1154 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1156 /* Alternate name for any vector register supporting logical operations, no
1157 matter which instruction set(s) are available. Allow GPRs as well as the
1158 vector registers. */
1159 #define VLOGICAL_REGNO_P(N) \
1160 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1161 || (TARGET_VSX && FP_REGNO_P (N))) \
1163 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1164 enough space to account for vectors in FP regs. However, TFmode/TDmode
1165 should not use VSX instructions to do a caller save. */
1166 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1167 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1170 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1171 && FP_REGNO_P (REGNO) \
1173 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1175 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
1177 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1179 #define VSX_VECTOR_MODE(MODE) \
1180 ((MODE) == V4SFmode \
1181 || (MODE) == V2DFmode) \
1183 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1184 really a vector, but we want to treat it as a vector for moves, and
1187 #define ALTIVEC_VECTOR_MODE(MODE) \
1188 ((MODE) == V16QImode \
1189 || (MODE) == V8HImode \
1190 || (MODE) == V4SFmode \
1191 || (MODE) == V4SImode \
1192 || FLOAT128_VECTOR_P (MODE))
1194 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1195 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1196 || (MODE) == V2DImode || (MODE) == V1TImode)
1198 /* Post-reload, we can't use any new AltiVec registers, as we already
1199 emitted the vrsave mask. */
1201 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1202 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1204 /* Specify the cost of a branch insn; roughly the number of extra insns that
1205 should be added to avoid a branch.
1207 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1208 unscheduled conditional branch. */
1210 #define BRANCH_COST(speed_p, predictable_p) 3
1212 /* Override BRANCH_COST heuristic which empirically produces worse
1213 performance for removing short circuiting from the logical ops. */
1215 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1217 /* Specify the registers used for certain standard purposes.
1218 The values of these macros are register numbers. */
1220 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1221 /* #define PC_REGNUM */
1223 /* Register to use for pushing function arguments. */
1224 #define STACK_POINTER_REGNUM 1
1226 /* Base register for access to local variables of the function. */
1227 #define HARD_FRAME_POINTER_REGNUM 31
1229 /* Base register for access to local variables of the function. */
1230 #define FRAME_POINTER_REGNUM 111
1232 /* Base register for access to arguments of the function. */
1233 #define ARG_POINTER_REGNUM 67
1235 /* Place to put static chain when calling a function that requires it. */
1236 #define STATIC_CHAIN_REGNUM 11
1238 /* Base register for access to thread local storage variables. */
1239 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1242 /* Define the classes of registers for register constraints in the
1243 machine description. Also define ranges of constants.
1245 One of the classes must always be named ALL_REGS and include all hard regs.
1246 If there is more than one class, another class must be named NO_REGS
1247 and contain no registers.
1249 The name GENERAL_REGS must be the name of a class (or an alias for
1250 another name such as ALL_REGS). This is the class of registers
1251 that is allowed by "g" or "r" in a register constraint.
1252 Also, registers outside this class are allocated only when
1253 instructions express preferences for them.
1255 The classes must be numbered in nondecreasing order; that is,
1256 a larger-numbered class must never be contained completely
1257 in a smaller-numbered class.
1259 For any two classes, it is very desirable that there be another
1260 class that represents their union. */
1262 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1263 condition registers, plus three special registers, CTR, and the link
1264 register. AltiVec adds a vector register class. VSX registers overlap the
1265 FPR registers and the Altivec registers.
1267 However, r0 is special in that it cannot be used as a base register.
1268 So make a class for registers valid as base registers.
1270 Also, cr0 is the only condition code register that can be used in
1271 arithmetic insns, so make a separate class for it. */
1298 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1300 /* Give names of register classes as strings for dump file. */
1302 #define REG_CLASS_NAMES \
1313 "NON_SPECIAL_REGS", \
1316 "LINK_OR_CTR_REGS", \
1318 "SPEC_OR_GEN_REGS", \
1326 /* Define which registers fit in which classes.
1327 This is an initializer for a vector of HARD_REG_SET
1328 of length N_REG_CLASSES. */
1330 #define REG_CLASS_CONTENTS \
1333 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1335 { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \
1336 /* GENERAL_REGS. */ \
1337 { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \
1339 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1340 /* ALTIVEC_REGS. */ \
1341 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \
1343 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \
1344 /* VRSAVE_REGS. */ \
1345 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1347 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
1349 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
1350 /* NON_SPECIAL_REGS. */ \
1351 { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \
1353 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
1355 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \
1356 /* LINK_OR_CTR_REGS. */ \
1357 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \
1358 /* SPECIAL_REGS. */ \
1359 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
1360 /* SPEC_OR_GEN_REGS. */ \
1361 { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \
1363 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
1365 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
1366 /* NON_FLOAT_REGS. */ \
1367 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \
1369 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
1371 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \
1374 /* The same information, inverted:
1375 Return the class number of the smallest class containing
1376 reg number REGNO. This could be a conditional expression
1377 or could index an array. */
1379 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1381 #define REGNO_REG_CLASS(REGNO) \
1382 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1383 rs6000_regno_regclass[(REGNO)])
1385 /* Register classes for various constraints that are based on the target
1387 enum r6000_reg_class_enum {
1388 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1389 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1390 RS6000_CONSTRAINT_v, /* Altivec registers */
1391 RS6000_CONSTRAINT_wa, /* Any VSX register */
1392 RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */
1393 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1394 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
1395 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1396 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
1397 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
1398 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
1399 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */
1400 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
1401 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
1402 RS6000_CONSTRAINT_wm, /* VSX register for direct move */
1403 RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */
1404 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
1405 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
1406 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
1407 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1408 RS6000_CONSTRAINT_wt, /* VSX register for TImode */
1409 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */
1410 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
1411 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
1412 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
1413 RS6000_CONSTRAINT_wy, /* VSX register for SF */
1414 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
1415 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
1416 RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
1417 RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
1418 RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */
1419 RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */
1420 RS6000_CONSTRAINT_MAX
1423 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1425 /* The class value for index registers, and the one for base regs. */
1426 #define INDEX_REG_CLASS GENERAL_REGS
1427 #define BASE_REG_CLASS BASE_REGS
1429 /* Return whether a given register class can hold VSX objects. */
1430 #define VSX_REG_CLASS_P(CLASS) \
1431 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1433 /* Return whether a given register class targets general purpose registers. */
1434 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1436 /* Given an rtx X being reloaded into a reg required to be
1437 in class CLASS, return the class of reg to actually use.
1438 In general this is just CLASS; but on some machines
1439 in some cases it is preferable to use a more restrictive class.
1441 On the RS/6000, we have to return NO_REGS when we want to reload a
1442 floating-point CONST_DOUBLE to force it to be copied to memory.
1444 We also don't want to reload integer values into floating-point
1445 registers if we can at all help it. In fact, this can
1446 cause reload to die, if it tries to generate a reload of CTR
1447 into a FP register and discovers it doesn't have the memory location
1450 ??? Would it be a good idea to have reload do the converse, that is
1451 try to reload floating modes into FP registers if possible?
1454 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1455 rs6000_preferred_reload_class_ptr (X, CLASS)
1457 /* Return the register class of a scratch register needed to copy IN into
1458 or out of a register in CLASS in MODE. If it can be done directly,
1459 NO_REGS is returned. */
1461 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1462 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1464 /* Return the maximum number of consecutive registers
1465 needed to represent mode MODE in a register of class CLASS.
1467 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1468 a single reg is enough for two words, unless we have VSX, where the FP
1469 registers can hold 128 bits. */
1470 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1472 /* Stack layout; function entry, exit and calling. */
1474 /* Define this if pushing a word on the stack
1475 makes the stack pointer a smaller address. */
1476 #define STACK_GROWS_DOWNWARD 1
1478 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1479 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1481 /* Define this to nonzero if the nominal address of the stack frame
1482 is at the high-address end of the local variables;
1483 that is, each additional local variable allocated
1484 goes at a more negative offset in the frame.
1486 On the RS/6000, we grow upwards, from the area after the outgoing
1488 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1489 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1491 /* Size of the fixed area on the stack */
1492 #define RS6000_SAVE_AREA \
1493 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1494 << (TARGET_64BIT ? 1 : 0))
1496 /* Stack offset for toc save slot. */
1497 #define RS6000_TOC_SAVE_SLOT \
1498 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1500 /* Align an address */
1501 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1503 /* Offset within stack frame to start allocating local variables at.
1504 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1505 first local allocated. Otherwise, it is the offset to the BEGINNING
1506 of the first local allocated.
1508 On the RS/6000, the frame pointer is the same as the stack pointer,
1509 except for dynamic allocations. So we start after the fixed area and
1510 outgoing parameter area.
1512 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1513 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1514 sizes of the fixed area and the parameter area must be a multiple of
1517 #define RS6000_STARTING_FRAME_OFFSET \
1518 (cfun->calls_alloca \
1519 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1520 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1521 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1522 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1523 + RS6000_SAVE_AREA))
1525 /* Offset from the stack pointer register to an item dynamically
1526 allocated on the stack, e.g., by `alloca'.
1528 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1529 length of the outgoing arguments. The default is correct for most
1530 machines. See `function.c' for details.
1532 This value must be a multiple of STACK_BOUNDARY (hard coded in
1534 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1535 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1536 + STACK_POINTER_OFFSET, \
1537 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1539 /* If we generate an insn to push BYTES bytes,
1540 this says how many the stack pointer really advances by.
1541 On RS/6000, don't define this because there are no push insns. */
1542 /* #define PUSH_ROUNDING(BYTES) */
1544 /* Offset of first parameter from the argument pointer register value.
1545 On the RS/6000, we define the argument pointer to the start of the fixed
1547 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1549 /* Offset from the argument pointer register value to the top of
1550 stack. This is different from FIRST_PARM_OFFSET because of the
1551 register save area. */
1552 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1554 /* Define this if stack space is still allocated for a parameter passed
1555 in a register. The value is the number of bytes allocated to this
1557 #define REG_PARM_STACK_SPACE(FNDECL) \
1558 rs6000_reg_parm_stack_space ((FNDECL), false)
1560 /* Define this macro if space guaranteed when compiling a function body
1561 is different to space required when making a call, a situation that
1562 can arise with K&R style function definitions. */
1563 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1564 rs6000_reg_parm_stack_space ((FNDECL), true)
1566 /* Define this if the above stack space is to be considered part of the
1567 space allocated by the caller. */
1568 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1570 /* This is the difference between the logical top of stack and the actual sp.
1572 For the RS/6000, sp points past the fixed area. */
1573 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1575 /* Define this if the maximum size of all the outgoing args is to be
1576 accumulated and pushed during the prologue. The amount can be
1577 found in the variable crtl->outgoing_args_size. */
1578 #define ACCUMULATE_OUTGOING_ARGS 1
1580 /* Define how to find the value returned by a library function
1581 assuming the value has mode MODE. */
1583 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1585 /* DRAFT_V4_STRUCT_RET defaults off. */
1586 #define DRAFT_V4_STRUCT_RET 0
1588 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1589 #define DEFAULT_PCC_STRUCT_RETURN 0
1591 /* Mode of stack savearea.
1592 FUNCTION is VOIDmode because calling convention maintains SP.
1593 BLOCK needs Pmode for SP.
1594 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1595 #define STACK_SAVEAREA_MODE(LEVEL) \
1596 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1597 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1599 /* Minimum and maximum general purpose registers used to hold arguments. */
1600 #define GP_ARG_MIN_REG 3
1601 #define GP_ARG_MAX_REG 10
1602 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1604 /* Minimum and maximum floating point registers used to hold arguments. */
1605 #define FP_ARG_MIN_REG 33
1606 #define FP_ARG_AIX_MAX_REG 45
1607 #define FP_ARG_V4_MAX_REG 40
1608 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1609 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1610 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1612 /* Minimum and maximum AltiVec registers used to hold arguments. */
1613 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1614 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1615 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1617 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1618 #define AGGR_ARG_NUM_REG 8
1620 /* Return registers */
1621 #define GP_ARG_RETURN GP_ARG_MIN_REG
1622 #define FP_ARG_RETURN FP_ARG_MIN_REG
1623 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1624 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1625 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1626 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1627 ? (ALTIVEC_ARG_RETURN \
1628 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1629 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1631 /* Flags for the call/call_value rtl operations set up by function_arg */
1632 #define CALL_NORMAL 0x00000000 /* no special processing */
1633 /* Bits in 0x00000001 are unused. */
1634 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1635 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1636 #define CALL_LONG 0x00000008 /* always call indirect */
1637 #define CALL_LIBCALL 0x00000010 /* libcall */
1639 /* We don't have prologue and epilogue functions to save/restore
1640 everything for most ABIs. */
1641 #define WORLD_SAVE_P(INFO) 0
1643 /* 1 if N is a possible register number for a function value
1644 as seen by the caller.
1646 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1647 #define FUNCTION_VALUE_REGNO_P(N) \
1648 ((N) == GP_ARG_RETURN \
1649 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1650 && TARGET_HARD_FLOAT) \
1651 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1652 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1654 /* 1 if N is a possible register number for function argument passing.
1655 On RS/6000, these are r3-r10 and fp1-fp13.
1656 On AltiVec, v2 - v13 are used for passing vectors. */
1657 #define FUNCTION_ARG_REGNO_P(N) \
1658 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1659 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1660 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1661 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1662 && TARGET_HARD_FLOAT))
1664 /* Define a data type for recording info about an argument list
1665 during the scan of that argument list. This data type should
1666 hold all necessary information about the function itself
1667 and about the args processed so far, enough to enable macros
1668 such as FUNCTION_ARG to determine where the next arg should go.
1670 On the RS/6000, this is a structure. The first element is the number of
1671 total argument words, the second is used to store the next
1672 floating-point register number, and the third says how many more args we
1673 have prototype types for.
1675 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1676 the next available GP register, `fregno' is the next available FP
1677 register, and `words' is the number of words used on the stack.
1679 The varargs/stdarg support requires that this structure's size
1680 be a multiple of sizeof(int). */
1682 typedef struct rs6000_args
1684 int words; /* # words used for passing GP registers */
1685 int fregno; /* next available FP register */
1686 int vregno; /* next available AltiVec register */
1687 int nargs_prototype; /* # args left in the current prototype */
1688 int prototype; /* Whether a prototype was defined */
1689 int stdarg; /* Whether function is a stdarg function. */
1690 int call_cookie; /* Do special things for this call */
1691 int sysv_gregno; /* next available GP register */
1692 int intoffset; /* running offset in struct (darwin64) */
1693 int use_stack; /* any part of struct on stack (darwin64) */
1694 int floats_in_gpr; /* count of SFmode floats taking up
1695 GPR space (darwin64) */
1696 int named; /* false for varargs params */
1697 int escapes; /* if function visible outside tu */
1698 int libcall; /* If this is a compiler generated call. */
1701 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1702 for a call to a function whose data type is FNTYPE.
1703 For a library call, FNTYPE is 0. */
1705 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1706 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1707 N_NAMED_ARGS, FNDECL, VOIDmode)
1709 /* Similar, but when scanning the definition of a procedure. We always
1710 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1712 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1713 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1714 1000, current_function_decl, VOIDmode)
1716 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1718 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1719 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1722 #define PAD_VARARGS_DOWN \
1723 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1725 /* Output assembler code to FILE to increment profiler label # LABELNO
1726 for profiling a function entry. */
1728 #define FUNCTION_PROFILER(FILE, LABELNO) \
1729 output_function_profiler ((FILE), (LABELNO));
1731 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1732 the stack pointer does not matter. No definition is equivalent to
1735 On the RS/6000, this is nonzero because we can restore the stack from
1736 its backpointer, which we maintain. */
1737 #define EXIT_IGNORE_STACK 1
1739 /* Define this macro as a C expression that is nonzero for registers
1740 that are used by the epilogue or the return' pattern. The stack
1741 and frame pointer registers are already be assumed to be used as
1744 #define EPILOGUE_USES(REGNO) \
1745 ((reload_completed && (REGNO) == LR_REGNO) \
1746 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1747 || (crtl->calls_eh_return \
1752 /* Length in units of the trampoline for entering a nested function. */
1754 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1756 /* Definitions for __builtin_return_address and __builtin_frame_address.
1757 __builtin_return_address (0) should give link register (LR_REGNO), enable
1759 /* This should be uncommented, so that the link register is used, but
1760 currently this would result in unmatched insns and spilling fixed
1761 registers so we'll leave it for another day. When these problems are
1762 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1764 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1766 /* Number of bytes into the frame return addresses can be found. See
1767 rs6000_stack_info in rs6000.c for more information on how the different
1768 abi's store the return address. */
1769 #define RETURN_ADDRESS_OFFSET \
1770 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1772 /* The current return address is in link register (65). The return address
1773 of anything farther back is accessed normally at an offset of 8 from the
1775 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1776 (rs6000_return_addr (COUNT, FRAME))
1779 /* Definitions for register eliminations.
1781 We have two registers that can be eliminated on the RS/6000. First, the
1782 frame pointer register can often be eliminated in favor of the stack
1783 pointer register. Secondly, the argument pointer register can always be
1784 eliminated; it is replaced with either the stack or frame pointer.
1786 In addition, we use the elimination mechanism to see if r30 is needed
1787 Initially we assume that it isn't. If it is, we spill it. This is done
1788 by making it an eliminable register. We replace it with itself so that
1789 if it isn't needed, then existing uses won't be modified. */
1791 /* This is an array of structures. Each structure initializes one pair
1792 of eliminable registers. The "from" register number is given first,
1793 followed by "to". Eliminations of the same "from" register are listed
1794 in order of preference. */
1795 #define ELIMINABLE_REGS \
1796 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1797 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1798 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1799 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1800 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1801 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1803 /* Define the offset between two registers, one to be eliminated, and the other
1804 its replacement, at the start of a routine. */
1805 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1806 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1808 /* Addressing modes, and classification of registers for them. */
1810 #define HAVE_PRE_DECREMENT 1
1811 #define HAVE_PRE_INCREMENT 1
1812 #define HAVE_PRE_MODIFY_DISP 1
1813 #define HAVE_PRE_MODIFY_REG 1
1815 /* Macros to check register numbers against specific register classes. */
1817 /* These assume that REGNO is a hard or pseudo reg number.
1818 They give nonzero only if REGNO is a hard reg of the suitable class
1819 or a pseudo reg currently allocated to a suitable hard reg.
1820 Since they use reg_renumber, they are safe only once reg_renumber
1821 has been allocated, which happens in reginfo.c during register
1824 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1825 ((REGNO) < FIRST_PSEUDO_REGISTER \
1826 ? (REGNO) <= 31 || (REGNO) == 67 \
1827 || (REGNO) == FRAME_POINTER_REGNUM \
1828 : (reg_renumber[REGNO] >= 0 \
1829 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1830 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1832 #define REGNO_OK_FOR_BASE_P(REGNO) \
1833 ((REGNO) < FIRST_PSEUDO_REGISTER \
1834 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1835 || (REGNO) == FRAME_POINTER_REGNUM \
1836 : (reg_renumber[REGNO] > 0 \
1837 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1838 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1840 /* Nonzero if X is a hard reg that can be used as an index
1841 or if it is a pseudo reg in the non-strict case. */
1842 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1843 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1844 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1846 /* Nonzero if X is a hard reg that can be used as a base reg
1847 or if it is a pseudo reg in the non-strict case. */
1848 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1849 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1850 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1853 /* Maximum number of registers that can appear in a valid memory address. */
1855 #define MAX_REGS_PER_ADDRESS 2
1857 /* Recognize any constant value that is a valid address. */
1859 #define CONSTANT_ADDRESS_P(X) \
1860 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1861 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1862 || GET_CODE (X) == HIGH)
1864 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1865 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1866 && EASY_VECTOR_15((n) >> 1) \
1869 #define EASY_VECTOR_MSB(n,mode) \
1870 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1871 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1874 /* Try a machine-dependent way of reloading an illegitimate address
1875 operand. If we find one, push the reload and jump to WIN. This
1876 macro is used in only one place: `find_reloads_address' in reload.c.
1878 Implemented on rs6000 by rs6000_legitimize_reload_address.
1879 Note that (X) is evaluated twice; this is safe in current usage. */
1881 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1884 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1885 (int)(TYPE), (IND_LEVELS), &win); \
1890 #define FIND_BASE_TERM rs6000_find_base_term
1892 /* The register number of the register used to address a table of
1893 static data addresses in memory. In some cases this register is
1894 defined by a processor's "application binary interface" (ABI).
1895 When this macro is defined, RTL is generated for this register
1896 once, as with the stack pointer and frame pointer registers. If
1897 this macro is not defined, it is up to the machine-dependent files
1898 to allocate such a register (if necessary). */
1900 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1901 #define PIC_OFFSET_TABLE_REGNUM \
1902 (TARGET_TOC ? TOC_REGISTER \
1903 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1906 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1908 /* Define this macro if the register defined by
1909 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1910 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1912 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1914 /* A C expression that is nonzero if X is a legitimate immediate
1915 operand on the target machine when generating position independent
1916 code. You can assume that X satisfies `CONSTANT_P', so you need
1917 not check this. You can also assume FLAG_PIC is true, so you need
1918 not check it either. You need not define this macro if all
1919 constants (including `SYMBOL_REF') can be immediate operands when
1920 generating position independent code. */
1922 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1924 /* Specify the machine mode that this machine uses
1925 for the index in the tablejump instruction. */
1926 #define CASE_VECTOR_MODE SImode
1928 /* Define as C expression which evaluates to nonzero if the tablejump
1929 instruction expects the table to contain offsets from the address of the
1931 Do not define this if the table should contain absolute addresses. */
1932 #define CASE_VECTOR_PC_RELATIVE 1
1934 /* Define this as 1 if `char' should by default be signed; else as 0. */
1935 #define DEFAULT_SIGNED_CHAR 0
1937 /* An integer expression for the size in bits of the largest integer machine
1938 mode that should actually be used. */
1940 /* Allow pairs of registers to be used, which is the intent of the default. */
1941 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1943 /* Max number of bytes we can move from memory to memory
1944 in one reasonably fast instruction. */
1945 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1946 #define MAX_MOVE_MAX 8
1948 /* Nonzero if access to memory by bytes is no faster than for words.
1949 Also nonzero if doing byte operations (specifically shifts) in registers
1951 #define SLOW_BYTE_ACCESS 1
1953 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1954 will either zero-extend or sign-extend. The value of this macro should
1955 be the code that says which one of the two operations is implicitly
1956 done, UNKNOWN if none. */
1957 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1959 /* Define if loading short immediate values into registers sign extends. */
1960 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1962 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1963 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1964 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1966 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1967 zero. The hardware instructions added in Power9 and the sequences using
1968 popcount return 32 or 64. */
1969 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1970 (TARGET_CTZ || TARGET_POPCNTD \
1971 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1972 : ((VALUE) = -1, 2))
1974 /* Specify the machine mode that pointers have.
1975 After generation of rtl, the compiler makes no further distinction
1976 between pointers and any other objects of this machine mode. */
1977 extern scalar_int_mode rs6000_pmode;
1978 #define Pmode rs6000_pmode
1980 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1981 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1983 /* Mode of a function address in a call instruction (for indexing purposes).
1984 Doesn't matter on RS/6000. */
1985 #define FUNCTION_MODE SImode
1987 /* Define this if addresses of constant functions
1988 shouldn't be put through pseudo regs where they can be cse'd.
1989 Desirable on machines where ordinary constants are expensive
1990 but a CALL with constant address is cheap. */
1991 #define NO_FUNCTION_CSE 1
1993 /* Define this to be nonzero if shift instructions ignore all but the low-order
1996 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1997 have been dropped from the PowerPC architecture. */
1998 #define SHIFT_COUNT_TRUNCATED 0
2000 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2001 should be adjusted to reflect any required changes. This macro is used when
2002 there is some systematic length adjustment required that would be difficult
2003 to express in the length attribute. */
2005 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2007 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2008 COMPARE, return the mode to be used for the comparison. For
2009 floating-point, CCFPmode should be used. CCUNSmode should be used
2010 for unsigned comparisons. CCEQmode should be used when we are
2011 doing an inequality comparison on the result of a
2012 comparison. CCmode should be used in all other cases. */
2014 #define SELECT_CC_MODE(OP,X,Y) \
2015 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2016 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2017 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2018 ? CCEQmode : CCmode))
2020 /* Can the condition code MODE be safely reversed? This is safe in
2021 all cases on this port, because at present it doesn't use the
2022 trapping FP comparisons (fcmpo). */
2023 #define REVERSIBLE_CC_MODE(MODE) 1
2025 /* Given a condition code and a mode, return the inverse condition. */
2026 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2029 /* Target cpu costs. */
2031 struct processor_costs {
2032 const int mulsi; /* cost of SImode multiplication. */
2033 const int mulsi_const; /* cost of SImode multiplication by constant. */
2034 const int mulsi_const9; /* cost of SImode mult by short constant. */
2035 const int muldi; /* cost of DImode multiplication. */
2036 const int divsi; /* cost of SImode division. */
2037 const int divdi; /* cost of DImode division. */
2038 const int fp; /* cost of simple SFmode and DFmode insns. */
2039 const int dmul; /* cost of DFmode multiplication (and fmadd). */
2040 const int sdiv; /* cost of SFmode division (fdivs). */
2041 const int ddiv; /* cost of DFmode division (fdiv). */
2042 const int cache_line_size; /* cache line size in bytes. */
2043 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
2044 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
2045 const int simultaneous_prefetches; /* number of parallel prefetch
2047 const int sfdf_convert; /* cost of SF->DF conversion. */
2050 extern const struct processor_costs *rs6000_cost;
2052 /* Control the assembler format that we output. */
2054 /* A C string constant describing how to begin a comment in the target
2055 assembler language. The compiler assumes that the comment will end at
2056 the end of the line. */
2057 #define ASM_COMMENT_START " #"
2059 /* Flag to say the TOC is initialized */
2060 extern int toc_initialized;
2062 /* Macro to output a special constant pool entry. Go to WIN if we output
2063 it. Otherwise, it is written the usual way.
2065 On the RS/6000, toc entries are handled this way. */
2067 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2068 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2070 output_toc (FILE, X, LABELNO, MODE); \
2075 #ifdef HAVE_GAS_WEAK
2076 #define RS6000_WEAK 1
2078 #define RS6000_WEAK 0
2082 /* Used in lieu of ASM_WEAKEN_LABEL. */
2083 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2084 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
2087 #if HAVE_GAS_WEAKREF
2088 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2091 fputs ("\t.weakref\t", (FILE)); \
2092 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2093 fputs (", ", (FILE)); \
2094 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2095 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2096 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2098 fputs ("\n\t.weakref\t.", (FILE)); \
2099 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2100 fputs (", .", (FILE)); \
2101 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2103 fputc ('\n', (FILE)); \
2107 /* This implements the `alias' attribute. */
2108 #undef ASM_OUTPUT_DEF_FROM_DECLS
2109 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2112 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2113 const char *name = IDENTIFIER_POINTER (TARGET); \
2114 if (TREE_CODE (DECL) == FUNCTION_DECL \
2115 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2117 if (TREE_PUBLIC (DECL)) \
2119 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2121 fputs ("\t.globl\t.", FILE); \
2122 RS6000_OUTPUT_BASENAME (FILE, alias); \
2123 putc ('\n', FILE); \
2126 else if (TARGET_XCOFF) \
2128 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2130 fputs ("\t.lglobl\t.", FILE); \
2131 RS6000_OUTPUT_BASENAME (FILE, alias); \
2132 putc ('\n', FILE); \
2133 fputs ("\t.lglobl\t", FILE); \
2134 RS6000_OUTPUT_BASENAME (FILE, alias); \
2135 putc ('\n', FILE); \
2138 fputs ("\t.set\t.", FILE); \
2139 RS6000_OUTPUT_BASENAME (FILE, alias); \
2140 fputs (",.", FILE); \
2141 RS6000_OUTPUT_BASENAME (FILE, name); \
2142 fputc ('\n', FILE); \
2144 ASM_OUTPUT_DEF (FILE, alias, name); \
2148 #define TARGET_ASM_FILE_START rs6000_file_start
2150 /* Output to assembler file text saying following lines
2151 may contain character constants, extra white space, comments, etc. */
2153 #define ASM_APP_ON ""
2155 /* Output to assembler file text saying following lines
2156 no longer contain unusual constructs. */
2158 #define ASM_APP_OFF ""
2160 /* How to refer to registers in assembler output.
2161 This sequence is indexed by compiler's hard-register-number (see above). */
2163 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2165 #define REGISTER_NAMES \
2167 &rs6000_reg_names[ 0][0], /* r0 */ \
2168 &rs6000_reg_names[ 1][0], /* r1 */ \
2169 &rs6000_reg_names[ 2][0], /* r2 */ \
2170 &rs6000_reg_names[ 3][0], /* r3 */ \
2171 &rs6000_reg_names[ 4][0], /* r4 */ \
2172 &rs6000_reg_names[ 5][0], /* r5 */ \
2173 &rs6000_reg_names[ 6][0], /* r6 */ \
2174 &rs6000_reg_names[ 7][0], /* r7 */ \
2175 &rs6000_reg_names[ 8][0], /* r8 */ \
2176 &rs6000_reg_names[ 9][0], /* r9 */ \
2177 &rs6000_reg_names[10][0], /* r10 */ \
2178 &rs6000_reg_names[11][0], /* r11 */ \
2179 &rs6000_reg_names[12][0], /* r12 */ \
2180 &rs6000_reg_names[13][0], /* r13 */ \
2181 &rs6000_reg_names[14][0], /* r14 */ \
2182 &rs6000_reg_names[15][0], /* r15 */ \
2183 &rs6000_reg_names[16][0], /* r16 */ \
2184 &rs6000_reg_names[17][0], /* r17 */ \
2185 &rs6000_reg_names[18][0], /* r18 */ \
2186 &rs6000_reg_names[19][0], /* r19 */ \
2187 &rs6000_reg_names[20][0], /* r20 */ \
2188 &rs6000_reg_names[21][0], /* r21 */ \
2189 &rs6000_reg_names[22][0], /* r22 */ \
2190 &rs6000_reg_names[23][0], /* r23 */ \
2191 &rs6000_reg_names[24][0], /* r24 */ \
2192 &rs6000_reg_names[25][0], /* r25 */ \
2193 &rs6000_reg_names[26][0], /* r26 */ \
2194 &rs6000_reg_names[27][0], /* r27 */ \
2195 &rs6000_reg_names[28][0], /* r28 */ \
2196 &rs6000_reg_names[29][0], /* r29 */ \
2197 &rs6000_reg_names[30][0], /* r30 */ \
2198 &rs6000_reg_names[31][0], /* r31 */ \
2200 &rs6000_reg_names[32][0], /* fr0 */ \
2201 &rs6000_reg_names[33][0], /* fr1 */ \
2202 &rs6000_reg_names[34][0], /* fr2 */ \
2203 &rs6000_reg_names[35][0], /* fr3 */ \
2204 &rs6000_reg_names[36][0], /* fr4 */ \
2205 &rs6000_reg_names[37][0], /* fr5 */ \
2206 &rs6000_reg_names[38][0], /* fr6 */ \
2207 &rs6000_reg_names[39][0], /* fr7 */ \
2208 &rs6000_reg_names[40][0], /* fr8 */ \
2209 &rs6000_reg_names[41][0], /* fr9 */ \
2210 &rs6000_reg_names[42][0], /* fr10 */ \
2211 &rs6000_reg_names[43][0], /* fr11 */ \
2212 &rs6000_reg_names[44][0], /* fr12 */ \
2213 &rs6000_reg_names[45][0], /* fr13 */ \
2214 &rs6000_reg_names[46][0], /* fr14 */ \
2215 &rs6000_reg_names[47][0], /* fr15 */ \
2216 &rs6000_reg_names[48][0], /* fr16 */ \
2217 &rs6000_reg_names[49][0], /* fr17 */ \
2218 &rs6000_reg_names[50][0], /* fr18 */ \
2219 &rs6000_reg_names[51][0], /* fr19 */ \
2220 &rs6000_reg_names[52][0], /* fr20 */ \
2221 &rs6000_reg_names[53][0], /* fr21 */ \
2222 &rs6000_reg_names[54][0], /* fr22 */ \
2223 &rs6000_reg_names[55][0], /* fr23 */ \
2224 &rs6000_reg_names[56][0], /* fr24 */ \
2225 &rs6000_reg_names[57][0], /* fr25 */ \
2226 &rs6000_reg_names[58][0], /* fr26 */ \
2227 &rs6000_reg_names[59][0], /* fr27 */ \
2228 &rs6000_reg_names[60][0], /* fr28 */ \
2229 &rs6000_reg_names[61][0], /* fr29 */ \
2230 &rs6000_reg_names[62][0], /* fr30 */ \
2231 &rs6000_reg_names[63][0], /* fr31 */ \
2233 &rs6000_reg_names[64][0], /* was mq */ \
2234 &rs6000_reg_names[65][0], /* lr */ \
2235 &rs6000_reg_names[66][0], /* ctr */ \
2236 &rs6000_reg_names[67][0], /* ap */ \
2238 &rs6000_reg_names[68][0], /* cr0 */ \
2239 &rs6000_reg_names[69][0], /* cr1 */ \
2240 &rs6000_reg_names[70][0], /* cr2 */ \
2241 &rs6000_reg_names[71][0], /* cr3 */ \
2242 &rs6000_reg_names[72][0], /* cr4 */ \
2243 &rs6000_reg_names[73][0], /* cr5 */ \
2244 &rs6000_reg_names[74][0], /* cr6 */ \
2245 &rs6000_reg_names[75][0], /* cr7 */ \
2247 &rs6000_reg_names[76][0], /* ca */ \
2249 &rs6000_reg_names[77][0], /* v0 */ \
2250 &rs6000_reg_names[78][0], /* v1 */ \
2251 &rs6000_reg_names[79][0], /* v2 */ \
2252 &rs6000_reg_names[80][0], /* v3 */ \
2253 &rs6000_reg_names[81][0], /* v4 */ \
2254 &rs6000_reg_names[82][0], /* v5 */ \
2255 &rs6000_reg_names[83][0], /* v6 */ \
2256 &rs6000_reg_names[84][0], /* v7 */ \
2257 &rs6000_reg_names[85][0], /* v8 */ \
2258 &rs6000_reg_names[86][0], /* v9 */ \
2259 &rs6000_reg_names[87][0], /* v10 */ \
2260 &rs6000_reg_names[88][0], /* v11 */ \
2261 &rs6000_reg_names[89][0], /* v12 */ \
2262 &rs6000_reg_names[90][0], /* v13 */ \
2263 &rs6000_reg_names[91][0], /* v14 */ \
2264 &rs6000_reg_names[92][0], /* v15 */ \
2265 &rs6000_reg_names[93][0], /* v16 */ \
2266 &rs6000_reg_names[94][0], /* v17 */ \
2267 &rs6000_reg_names[95][0], /* v18 */ \
2268 &rs6000_reg_names[96][0], /* v19 */ \
2269 &rs6000_reg_names[97][0], /* v20 */ \
2270 &rs6000_reg_names[98][0], /* v21 */ \
2271 &rs6000_reg_names[99][0], /* v22 */ \
2272 &rs6000_reg_names[100][0], /* v23 */ \
2273 &rs6000_reg_names[101][0], /* v24 */ \
2274 &rs6000_reg_names[102][0], /* v25 */ \
2275 &rs6000_reg_names[103][0], /* v26 */ \
2276 &rs6000_reg_names[104][0], /* v27 */ \
2277 &rs6000_reg_names[105][0], /* v28 */ \
2278 &rs6000_reg_names[106][0], /* v29 */ \
2279 &rs6000_reg_names[107][0], /* v30 */ \
2280 &rs6000_reg_names[108][0], /* v31 */ \
2281 &rs6000_reg_names[109][0], /* vrsave */ \
2282 &rs6000_reg_names[110][0], /* vscr */ \
2283 &rs6000_reg_names[111][0], /* sfp */ \
2284 &rs6000_reg_names[112][0], /* tfhar */ \
2285 &rs6000_reg_names[113][0], /* tfiar */ \
2286 &rs6000_reg_names[114][0], /* texasr */ \
2289 /* Table of additional register names to use in user input. */
2291 #define ADDITIONAL_REGISTER_NAMES \
2292 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2293 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2294 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2295 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2296 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2297 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2298 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2299 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2300 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2301 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2302 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2303 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2304 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2305 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2306 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2307 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2308 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2309 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2310 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2311 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2312 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2313 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2314 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2315 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2316 {"vrsave", 109}, {"vscr", 110}, \
2317 /* no additional names for: lr, ctr, ap */ \
2318 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2319 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2320 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2321 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2323 /* VSX registers overlaid on top of FR, Altivec registers */ \
2324 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2325 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2326 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2327 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2328 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2329 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2330 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2331 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2332 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2333 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2334 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2335 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2336 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2337 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2338 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2339 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
2340 /* Transactional Memory Facility (HTM) Registers. */ \
2341 {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \
2344 /* This is how to output an element of a case-vector that is relative. */
2346 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2347 do { char buf[100]; \
2348 fputs ("\t.long ", FILE); \
2349 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2350 assemble_name (FILE, buf); \
2352 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2353 assemble_name (FILE, buf); \
2354 putc ('\n', FILE); \
2357 /* This is how to output an assembler line
2358 that says to advance the location counter
2359 to a multiple of 2**LOG bytes. */
2361 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2363 fprintf (FILE, "\t.align %d\n", (LOG))
2365 /* How to align the given loop. */
2366 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2368 /* Alignment guaranteed by __builtin_malloc. */
2369 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2370 However, specifying the stronger guarantee currently leads to
2371 a regression in SPEC CPU2006 437.leslie3d. The stronger
2372 guarantee should be implemented here once that's fixed. */
2373 #define MALLOC_ABI_ALIGNMENT (64)
2375 /* Pick up the return address upon entry to a procedure. Used for
2376 dwarf2 unwind information. This also enables the table driven
2379 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2380 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2382 /* Describe how we implement __builtin_eh_return. */
2383 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2384 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2386 /* Print operand X (an rtx) in assembler syntax to file FILE.
2387 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2388 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2390 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2392 /* Define which CODE values are valid. */
2394 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2396 /* Print a memory address as an operand to reference that memory location. */
2398 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2400 /* For switching between functions with different target attributes. */
2401 #define SWITCHABLE_TARGET 1
2403 /* uncomment for disabling the corresponding default options */
2404 /* #define MACHINE_no_sched_interblock */
2405 /* #define MACHINE_no_sched_speculative */
2406 /* #define MACHINE_no_sched_speculative_load */
2408 /* General flags. */
2409 extern int frame_pointer_needed;
2411 /* Classification of the builtin functions as to which switches enable the
2412 builtin, and what attributes it should have. We used to use the target
2413 flags macros, but we've run out of bits, so we now map the options into new
2414 settings used here. */
2416 /* Builtin attributes. */
2417 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2418 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2419 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2420 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2421 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2422 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2423 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2424 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2426 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2427 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
2428 modifies global state. */
2429 #define RS6000_BTC_PURE 0x00000200 /* reads global
2431 not modify global state. */
2432 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2433 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2435 /* Miscellaneous information. */
2436 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2437 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2438 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */
2439 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */
2440 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2442 /* Convenience macros to document the instruction type. */
2443 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2444 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2446 /* Builtin targets. For now, we reuse the masks for those options that are in
2447 target flags, and pick a random bit for ldbl128, which isn't in
2449 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2450 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2451 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2452 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2453 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2454 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2455 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2456 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2457 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2458 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2459 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2460 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2461 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2462 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2463 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2464 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2465 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2466 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2467 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2468 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
2469 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
2470 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
2472 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2474 | RS6000_BTM_P8_VECTOR \
2475 | RS6000_BTM_P9_VECTOR \
2476 | RS6000_BTM_P9_MISC \
2477 | RS6000_BTM_MODULO \
2478 | RS6000_BTM_CRYPTO \
2481 | RS6000_BTM_FRSQRTE \
2482 | RS6000_BTM_FRSQRTES \
2484 | RS6000_BTM_POPCNTD \
2487 | RS6000_BTM_HARD_FLOAT \
2488 | RS6000_BTM_LDBL128 \
2489 | RS6000_BTM_POWERPC64 \
2490 | RS6000_BTM_FLOAT128 \
2491 | RS6000_BTM_FLOAT128_HW)
2493 /* Define builtin enum index. */
2495 #undef RS6000_BUILTIN_0
2496 #undef RS6000_BUILTIN_1
2497 #undef RS6000_BUILTIN_2
2498 #undef RS6000_BUILTIN_3
2499 #undef RS6000_BUILTIN_A
2500 #undef RS6000_BUILTIN_D
2501 #undef RS6000_BUILTIN_H
2502 #undef RS6000_BUILTIN_P
2503 #undef RS6000_BUILTIN_X
2505 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2506 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2507 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2508 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2509 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2510 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2511 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2512 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2513 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2515 enum rs6000_builtins
2517 #include "rs6000-builtin.def"
2519 RS6000_BUILTIN_COUNT
2522 #undef RS6000_BUILTIN_0
2523 #undef RS6000_BUILTIN_1
2524 #undef RS6000_BUILTIN_2
2525 #undef RS6000_BUILTIN_3
2526 #undef RS6000_BUILTIN_A
2527 #undef RS6000_BUILTIN_D
2528 #undef RS6000_BUILTIN_H
2529 #undef RS6000_BUILTIN_P
2530 #undef RS6000_BUILTIN_X
2532 enum rs6000_builtin_type_index
2534 RS6000_BTI_NOT_OPAQUE,
2535 RS6000_BTI_opaque_V4SI,
2536 RS6000_BTI_V16QI, /* __vector signed char */
2544 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */
2545 RS6000_BTI_unsigned_V1TI,
2546 RS6000_BTI_unsigned_V8HI,
2547 RS6000_BTI_unsigned_V4SI,
2548 RS6000_BTI_unsigned_V2DI,
2549 RS6000_BTI_bool_char, /* __bool char */
2550 RS6000_BTI_bool_short, /* __bool short */
2551 RS6000_BTI_bool_int, /* __bool int */
2552 RS6000_BTI_bool_long_long, /* __bool long long */
2553 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4
2554 channels of 1, 5, 5, and 5 bits
2555 respectively as packed with the
2556 vpkpx insn. __pixel is only
2557 meaningful as a vector type.
2558 There is no corresponding scalar
2559 __pixel data type.) */
2560 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2561 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2562 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2563 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2564 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2565 RS6000_BTI_long, /* long_integer_type_node */
2566 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2567 RS6000_BTI_long_long, /* long_long_integer_type_node */
2568 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2569 RS6000_BTI_INTQI, /* (signed) intQI_type_node */
2570 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2571 RS6000_BTI_INTHI, /* intHI_type_node */
2572 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2573 RS6000_BTI_INTSI, /* intSI_type_node (signed) */
2574 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2575 RS6000_BTI_INTDI, /* intDI_type_node */
2576 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2577 RS6000_BTI_INTTI, /* intTI_type_node */
2578 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */
2579 RS6000_BTI_float, /* float_type_node */
2580 RS6000_BTI_double, /* double_type_node */
2581 RS6000_BTI_long_double, /* long_double_type_node */
2582 RS6000_BTI_dfloat64, /* dfloat64_type_node */
2583 RS6000_BTI_dfloat128, /* dfloat128_type_node */
2584 RS6000_BTI_void, /* void_type_node */
2585 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */
2586 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */
2587 RS6000_BTI_const_str, /* pointer to const char * */
2592 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2593 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2594 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2595 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2596 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2597 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2598 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2599 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2600 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2601 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2602 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2603 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2604 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2605 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2606 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2607 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2608 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2609 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2610 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2611 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2612 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2613 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2614 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2615 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2617 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2618 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2619 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2620 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2621 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2622 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2623 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2624 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2625 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2626 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2627 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2628 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2629 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2630 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2631 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2632 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2633 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2634 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2635 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2636 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2637 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2638 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2639 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2641 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2642 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
2644 #define TARGET_SUPPORTS_WIDE_INT 1
2646 #if (GCC_VERSION >= 3000)
2647 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128