1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 /* This file should be included last. */
86 #include "target-def.h"
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
93 systems will also set long double to be IEEE 128-bit. AIX and Darwin
94 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
95 those systems will not pick up this default. This needs to be after all
96 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
98 #ifndef TARGET_IEEEQUAD_DEFAULT
99 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
100 #define TARGET_IEEEQUAD_DEFAULT 1
102 #define TARGET_IEEEQUAD_DEFAULT 0
106 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
108 /* Structure used to define the rs6000 stack */
109 typedef struct rs6000_stack {
110 int reload_completed; /* stack info won't change from here on */
111 int first_gp_reg_save; /* first callee saved GP register used */
112 int first_fp_reg_save; /* first callee saved FP register used */
113 int first_altivec_reg_save; /* first callee saved AltiVec register used */
114 int lr_save_p; /* true if the link reg needs to be saved */
115 int cr_save_p; /* true if the CR reg needs to be saved */
116 unsigned int vrsave_mask; /* mask of vec registers to save */
117 int push_p; /* true if we need to allocate stack space */
118 int calls_p; /* true if the function makes any calls */
119 int world_save_p; /* true if we're saving *everything*:
120 r13-r31, cr, f14-f31, vrsave, v20-v31 */
121 enum rs6000_abi abi; /* which ABI to use */
122 int gp_save_offset; /* offset to save GP regs from initial SP */
123 int fp_save_offset; /* offset to save FP regs from initial SP */
124 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
125 int lr_save_offset; /* offset to save LR from initial SP */
126 int cr_save_offset; /* offset to save CR from initial SP */
127 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
128 int varargs_save_offset; /* offset to save the varargs registers */
129 int ehrd_offset; /* offset to EH return data */
130 int ehcr_offset; /* offset to EH CR field data */
131 int reg_size; /* register size (4 or 8) */
132 HOST_WIDE_INT vars_size; /* variable save area size */
133 int parm_size; /* outgoing parameter size */
134 int save_size; /* save area size */
135 int fixed_size; /* fixed size of stack frame */
136 int gp_size; /* size of saved GP registers */
137 int fp_size; /* size of saved FP registers */
138 int altivec_size; /* size of saved AltiVec registers */
139 int cr_size; /* size to hold CR if not in fixed area */
140 int vrsave_size; /* size to hold VRSAVE */
141 int altivec_padding_size; /* size of altivec alignment padding */
142 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
146 /* A C structure for machine-specific, per-function data.
147 This is added to the cfun structure. */
148 typedef struct GTY(()) machine_function
150 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
151 int ra_needs_full_frame;
152 /* Flags if __builtin_return_address (0) was used. */
154 /* Cache lr_save_p after expansion of builtin_eh_return. */
156 /* Whether we need to save the TOC to the reserved stack location in the
157 function prologue. */
158 bool save_toc_in_prologue;
159 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
160 varargs save area. */
161 HOST_WIDE_INT varargs_save_offset;
162 /* Alternative internal arg pointer for -fsplit-stack. */
163 rtx split_stack_arg_pointer;
164 bool split_stack_argp_used;
165 /* Flag if r2 setup is needed with ELFv2 ABI. */
166 bool r2_setup_needed;
167 /* The number of components we use for separate shrink-wrapping. */
169 /* The components already handled by separate shrink-wrapping, which should
170 not be considered by the prologue and epilogue. */
171 bool gpr_is_wrapped_separately[32];
172 bool fpr_is_wrapped_separately[32];
173 bool lr_is_wrapped_separately;
174 bool toc_is_wrapped_separately;
177 /* Support targetm.vectorize.builtin_mask_for_load. */
178 static GTY(()) tree altivec_builtin_mask_for_load;
180 /* Set to nonzero once AIX common-mode calls have been defined. */
181 static GTY(()) int common_mode_defined;
183 /* Label number of label created for -mrelocatable, to call to so we can
184 get the address of the GOT section */
185 static int rs6000_pic_labelno;
188 /* Counter for labels which are to be placed in .fixup. */
189 int fixuplabelno = 0;
192 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
195 /* Specify the machine mode that pointers have. After generation of rtl, the
196 compiler makes no further distinction between pointers and any other objects
197 of this machine mode. */
198 scalar_int_mode rs6000_pmode;
201 /* Note whether IEEE 128-bit floating point was passed or returned, either as
202 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
203 floating point. We changed the default C++ mangling for these types and we
204 may want to generate a weak alias of the old mangling (U10__float128) to the
205 new mangling (u9__ieee128). */
206 static bool rs6000_passes_ieee128;
209 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
210 name used in current releases (i.e. u9__ieee128). */
211 static bool ieee128_mangling_gcc_8_1;
213 /* Width in bits of a pointer. */
214 unsigned rs6000_pointer_size;
216 #ifdef HAVE_AS_GNU_ATTRIBUTE
217 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
218 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
220 /* Flag whether floating point values have been passed/returned.
221 Note that this doesn't say whether fprs are used, since the
222 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
223 should be set for soft-float values passed in gprs and ieee128
224 values passed in vsx registers. */
225 static bool rs6000_passes_float;
226 static bool rs6000_passes_long_double;
227 /* Flag whether vector values have been passed/returned. */
228 static bool rs6000_passes_vector;
229 /* Flag whether small (<= 8 byte) structures have been returned. */
230 static bool rs6000_returns_struct;
233 /* Value is TRUE if register/mode pair is acceptable. */
234 static bool rs6000_hard_regno_mode_ok_p
235 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
237 /* Maximum number of registers needed for a given register class and mode. */
238 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
240 /* How many registers are needed for a given register and mode. */
241 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
243 /* Map register number to register class. */
244 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
246 static int dbg_cost_ctrl;
248 /* Built in types. */
249 tree rs6000_builtin_types[RS6000_BTI_MAX];
250 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
252 /* Flag to say the TOC is initialized */
253 int toc_initialized, need_toc_init;
254 char toc_label_name[10];
256 /* Cached value of rs6000_variable_issue. This is cached in
257 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
258 static short cached_can_issue_more;
260 static GTY(()) section *read_only_data_section;
261 static GTY(()) section *private_data_section;
262 static GTY(()) section *tls_data_section;
263 static GTY(()) section *tls_private_data_section;
264 static GTY(()) section *read_only_private_data_section;
265 static GTY(()) section *sdata2_section;
266 static GTY(()) section *toc_section;
268 struct builtin_description
270 const HOST_WIDE_INT mask;
271 const enum insn_code icode;
272 const char *const name;
273 const enum rs6000_builtins code;
276 /* Describe the vector unit used for modes. */
277 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
278 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
280 /* Register classes for various constraints that are based on the target
282 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
284 /* Describe the alignment of a vector. */
285 int rs6000_vector_align[NUM_MACHINE_MODES];
287 /* Map selected modes to types for builtins. */
288 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
290 /* What modes to automatically generate reciprocal divide estimate (fre) and
291 reciprocal sqrt (frsqrte) for. */
292 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
294 /* Masks to determine which reciprocal esitmate instructions to generate
296 enum rs6000_recip_mask {
297 RECIP_SF_DIV = 0x001, /* Use divide estimate */
298 RECIP_DF_DIV = 0x002,
299 RECIP_V4SF_DIV = 0x004,
300 RECIP_V2DF_DIV = 0x008,
302 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
303 RECIP_DF_RSQRT = 0x020,
304 RECIP_V4SF_RSQRT = 0x040,
305 RECIP_V2DF_RSQRT = 0x080,
307 /* Various combination of flags for -mrecip=xxx. */
309 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
310 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
311 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
313 RECIP_HIGH_PRECISION = RECIP_ALL,
315 /* On low precision machines like the power5, don't enable double precision
316 reciprocal square root estimate, since it isn't accurate enough. */
317 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
320 /* -mrecip options. */
323 const char *string; /* option name */
324 unsigned int mask; /* mask bits to set */
325 } recip_options[] = {
326 { "all", RECIP_ALL },
327 { "none", RECIP_NONE },
328 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
330 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
331 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
332 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
333 | RECIP_V2DF_RSQRT) },
334 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
335 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
338 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
344 { "power9", PPC_PLATFORM_POWER9 },
345 { "power8", PPC_PLATFORM_POWER8 },
346 { "power7", PPC_PLATFORM_POWER7 },
347 { "power6x", PPC_PLATFORM_POWER6X },
348 { "power6", PPC_PLATFORM_POWER6 },
349 { "power5+", PPC_PLATFORM_POWER5_PLUS },
350 { "power5", PPC_PLATFORM_POWER5 },
351 { "ppc970", PPC_PLATFORM_PPC970 },
352 { "power4", PPC_PLATFORM_POWER4 },
353 { "ppca2", PPC_PLATFORM_PPCA2 },
354 { "ppc476", PPC_PLATFORM_PPC476 },
355 { "ppc464", PPC_PLATFORM_PPC464 },
356 { "ppc440", PPC_PLATFORM_PPC440 },
357 { "ppc405", PPC_PLATFORM_PPC405 },
358 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
361 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
367 } cpu_supports_info[] = {
368 /* AT_HWCAP masks. */
369 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
370 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
371 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
372 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
373 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
374 { "booke", PPC_FEATURE_BOOKE, 0 },
375 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
376 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
377 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
378 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
379 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
380 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
381 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
382 { "notb", PPC_FEATURE_NO_TB, 0 },
383 { "pa6t", PPC_FEATURE_PA6T, 0 },
384 { "power4", PPC_FEATURE_POWER4, 0 },
385 { "power5", PPC_FEATURE_POWER5, 0 },
386 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
387 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
388 { "ppc32", PPC_FEATURE_32, 0 },
389 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
390 { "ppc64", PPC_FEATURE_64, 0 },
391 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
392 { "smt", PPC_FEATURE_SMT, 0 },
393 { "spe", PPC_FEATURE_HAS_SPE, 0 },
394 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
395 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
396 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
398 /* AT_HWCAP2 masks. */
399 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
400 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
401 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
402 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
403 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
404 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
405 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
406 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
407 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
408 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
409 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
410 { "darn", PPC_FEATURE2_DARN, 1 },
411 { "scv", PPC_FEATURE2_SCV, 1 }
414 /* On PowerPC, we have a limited number of target clones that we care about
415 which means we can use an array to hold the options, rather than having more
416 elaborate data structures to identify each possible variation. Order the
417 clones from the default to the highest ISA. */
419 CLONE_DEFAULT = 0, /* default clone. */
420 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
421 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
422 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
423 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
427 /* Map compiler ISA bits into HWCAP names. */
429 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
430 const char *name; /* name to use in __builtin_cpu_supports. */
433 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
434 { 0, "" }, /* Default options. */
435 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
436 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
437 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
438 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
442 /* Newer LIBCs explicitly export this symbol to declare that they provide
443 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
444 reference to this symbol whenever we expand a CPU builtin, so that
445 we never link against an old LIBC. */
446 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
448 /* True if we have expanded a CPU builtin. */
451 /* Pointer to function (in rs6000-c.c) that can define or undefine target
452 macros that have changed. Languages that don't support the preprocessor
453 don't link in rs6000-c.c, so we can't call it directly. */
454 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
456 /* Simplfy register classes into simpler classifications. We assume
457 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
458 check for standard register classes (gpr/floating/altivec/vsx) and
459 floating/vector classes (float/altivec/vsx). */
461 enum rs6000_reg_type {
472 /* Map register class to register type. */
473 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
475 /* First/last register type for the 'normal' register types (i.e. general
476 purpose, floating point, altivec, and VSX registers). */
477 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
479 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
482 /* Register classes we care about in secondary reload or go if legitimate
483 address. We only need to worry about GPR, FPR, and Altivec registers here,
484 along an ANY field that is the OR of the 3 register classes. */
486 enum rs6000_reload_reg_type {
487 RELOAD_REG_GPR, /* General purpose registers. */
488 RELOAD_REG_FPR, /* Traditional floating point regs. */
489 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
490 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
494 /* For setting up register classes, loop through the 3 register classes mapping
495 into real registers, and skip the ANY class, which is just an OR of the
497 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
498 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
500 /* Map reload register type to a register in the register class. */
501 struct reload_reg_map_type {
502 const char *name; /* Register class name. */
503 int reg; /* Register in the register class. */
506 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
507 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
508 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
509 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
510 { "Any", -1 }, /* RELOAD_REG_ANY. */
513 /* Mask bits for each register class, indexed per mode. Historically the
514 compiler has been more restrictive which types can do PRE_MODIFY instead of
515 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
516 typedef unsigned char addr_mask_type;
518 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
519 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
520 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
521 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
522 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
523 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
524 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
525 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
527 /* Register type masks based on the type, of valid addressing modes. */
528 struct rs6000_reg_addr {
529 enum insn_code reload_load; /* INSN to reload for loading. */
530 enum insn_code reload_store; /* INSN to reload for storing. */
531 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
532 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
533 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
534 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
535 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
538 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
540 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
542 mode_supports_pre_incdec_p (machine_mode mode)
544 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
548 /* Helper function to say whether a mode supports PRE_MODIFY. */
550 mode_supports_pre_modify_p (machine_mode mode)
552 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
556 /* Return true if we have D-form addressing in altivec registers. */
558 mode_supports_vmx_dform (machine_mode mode)
560 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
563 /* Return true if we have D-form addressing in VSX registers. This addressing
564 is more limited than normal d-form addressing in that the offset must be
565 aligned on a 16-byte boundary. */
567 mode_supports_dq_form (machine_mode mode)
569 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
573 /* Given that there exists at least one variable that is set (produced)
574 by OUT_INSN and read (consumed) by IN_INSN, return true iff
575 IN_INSN represents one or more memory store operations and none of
576 the variables set by OUT_INSN is used by IN_INSN as the address of a
577 store operation. If either IN_INSN or OUT_INSN does not represent
578 a "single" RTL SET expression (as loosely defined by the
579 implementation of the single_set function) or a PARALLEL with only
580 SETs, CLOBBERs, and USEs inside, this function returns false.
582 This rs6000-specific version of store_data_bypass_p checks for
583 certain conditions that result in assertion failures (and internal
584 compiler errors) in the generic store_data_bypass_p function and
585 returns false rather than calling store_data_bypass_p if one of the
586 problematic conditions is detected. */
589 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
596 in_set = single_set (in_insn);
599 if (MEM_P (SET_DEST (in_set)))
601 out_set = single_set (out_insn);
604 out_pat = PATTERN (out_insn);
605 if (GET_CODE (out_pat) == PARALLEL)
607 for (i = 0; i < XVECLEN (out_pat, 0); i++)
609 out_exp = XVECEXP (out_pat, 0, i);
610 if ((GET_CODE (out_exp) == CLOBBER)
611 || (GET_CODE (out_exp) == USE))
613 else if (GET_CODE (out_exp) != SET)
622 in_pat = PATTERN (in_insn);
623 if (GET_CODE (in_pat) != PARALLEL)
626 for (i = 0; i < XVECLEN (in_pat, 0); i++)
628 in_exp = XVECEXP (in_pat, 0, i);
629 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
631 else if (GET_CODE (in_exp) != SET)
634 if (MEM_P (SET_DEST (in_exp)))
636 out_set = single_set (out_insn);
639 out_pat = PATTERN (out_insn);
640 if (GET_CODE (out_pat) != PARALLEL)
642 for (j = 0; j < XVECLEN (out_pat, 0); j++)
644 out_exp = XVECEXP (out_pat, 0, j);
645 if ((GET_CODE (out_exp) == CLOBBER)
646 || (GET_CODE (out_exp) == USE))
648 else if (GET_CODE (out_exp) != SET)
655 return store_data_bypass_p (out_insn, in_insn);
659 /* Processor costs (relative to an add) */
661 const struct processor_costs *rs6000_cost;
663 /* Instruction size costs on 32bit processors. */
665 struct processor_costs size32_cost = {
666 COSTS_N_INSNS (1), /* mulsi */
667 COSTS_N_INSNS (1), /* mulsi_const */
668 COSTS_N_INSNS (1), /* mulsi_const9 */
669 COSTS_N_INSNS (1), /* muldi */
670 COSTS_N_INSNS (1), /* divsi */
671 COSTS_N_INSNS (1), /* divdi */
672 COSTS_N_INSNS (1), /* fp */
673 COSTS_N_INSNS (1), /* dmul */
674 COSTS_N_INSNS (1), /* sdiv */
675 COSTS_N_INSNS (1), /* ddiv */
676 32, /* cache line size */
680 0, /* SF->DF convert */
683 /* Instruction size costs on 64bit processors. */
685 struct processor_costs size64_cost = {
686 COSTS_N_INSNS (1), /* mulsi */
687 COSTS_N_INSNS (1), /* mulsi_const */
688 COSTS_N_INSNS (1), /* mulsi_const9 */
689 COSTS_N_INSNS (1), /* muldi */
690 COSTS_N_INSNS (1), /* divsi */
691 COSTS_N_INSNS (1), /* divdi */
692 COSTS_N_INSNS (1), /* fp */
693 COSTS_N_INSNS (1), /* dmul */
694 COSTS_N_INSNS (1), /* sdiv */
695 COSTS_N_INSNS (1), /* ddiv */
696 128, /* cache line size */
700 0, /* SF->DF convert */
703 /* Instruction costs on RS64A processors. */
705 struct processor_costs rs64a_cost = {
706 COSTS_N_INSNS (20), /* mulsi */
707 COSTS_N_INSNS (12), /* mulsi_const */
708 COSTS_N_INSNS (8), /* mulsi_const9 */
709 COSTS_N_INSNS (34), /* muldi */
710 COSTS_N_INSNS (65), /* divsi */
711 COSTS_N_INSNS (67), /* divdi */
712 COSTS_N_INSNS (4), /* fp */
713 COSTS_N_INSNS (4), /* dmul */
714 COSTS_N_INSNS (31), /* sdiv */
715 COSTS_N_INSNS (31), /* ddiv */
716 128, /* cache line size */
720 0, /* SF->DF convert */
723 /* Instruction costs on MPCCORE processors. */
725 struct processor_costs mpccore_cost = {
726 COSTS_N_INSNS (2), /* mulsi */
727 COSTS_N_INSNS (2), /* mulsi_const */
728 COSTS_N_INSNS (2), /* mulsi_const9 */
729 COSTS_N_INSNS (2), /* muldi */
730 COSTS_N_INSNS (6), /* divsi */
731 COSTS_N_INSNS (6), /* divdi */
732 COSTS_N_INSNS (4), /* fp */
733 COSTS_N_INSNS (5), /* dmul */
734 COSTS_N_INSNS (10), /* sdiv */
735 COSTS_N_INSNS (17), /* ddiv */
736 32, /* cache line size */
740 0, /* SF->DF convert */
743 /* Instruction costs on PPC403 processors. */
745 struct processor_costs ppc403_cost = {
746 COSTS_N_INSNS (4), /* mulsi */
747 COSTS_N_INSNS (4), /* mulsi_const */
748 COSTS_N_INSNS (4), /* mulsi_const9 */
749 COSTS_N_INSNS (4), /* muldi */
750 COSTS_N_INSNS (33), /* divsi */
751 COSTS_N_INSNS (33), /* divdi */
752 COSTS_N_INSNS (11), /* fp */
753 COSTS_N_INSNS (11), /* dmul */
754 COSTS_N_INSNS (11), /* sdiv */
755 COSTS_N_INSNS (11), /* ddiv */
756 32, /* cache line size */
760 0, /* SF->DF convert */
763 /* Instruction costs on PPC405 processors. */
765 struct processor_costs ppc405_cost = {
766 COSTS_N_INSNS (5), /* mulsi */
767 COSTS_N_INSNS (4), /* mulsi_const */
768 COSTS_N_INSNS (3), /* mulsi_const9 */
769 COSTS_N_INSNS (5), /* muldi */
770 COSTS_N_INSNS (35), /* divsi */
771 COSTS_N_INSNS (35), /* divdi */
772 COSTS_N_INSNS (11), /* fp */
773 COSTS_N_INSNS (11), /* dmul */
774 COSTS_N_INSNS (11), /* sdiv */
775 COSTS_N_INSNS (11), /* ddiv */
776 32, /* cache line size */
780 0, /* SF->DF convert */
783 /* Instruction costs on PPC440 processors. */
785 struct processor_costs ppc440_cost = {
786 COSTS_N_INSNS (3), /* mulsi */
787 COSTS_N_INSNS (2), /* mulsi_const */
788 COSTS_N_INSNS (2), /* mulsi_const9 */
789 COSTS_N_INSNS (3), /* muldi */
790 COSTS_N_INSNS (34), /* divsi */
791 COSTS_N_INSNS (34), /* divdi */
792 COSTS_N_INSNS (5), /* fp */
793 COSTS_N_INSNS (5), /* dmul */
794 COSTS_N_INSNS (19), /* sdiv */
795 COSTS_N_INSNS (33), /* ddiv */
796 32, /* cache line size */
800 0, /* SF->DF convert */
803 /* Instruction costs on PPC476 processors. */
805 struct processor_costs ppc476_cost = {
806 COSTS_N_INSNS (4), /* mulsi */
807 COSTS_N_INSNS (4), /* mulsi_const */
808 COSTS_N_INSNS (4), /* mulsi_const9 */
809 COSTS_N_INSNS (4), /* muldi */
810 COSTS_N_INSNS (11), /* divsi */
811 COSTS_N_INSNS (11), /* divdi */
812 COSTS_N_INSNS (6), /* fp */
813 COSTS_N_INSNS (6), /* dmul */
814 COSTS_N_INSNS (19), /* sdiv */
815 COSTS_N_INSNS (33), /* ddiv */
816 32, /* l1 cache line size */
820 0, /* SF->DF convert */
823 /* Instruction costs on PPC601 processors. */
825 struct processor_costs ppc601_cost = {
826 COSTS_N_INSNS (5), /* mulsi */
827 COSTS_N_INSNS (5), /* mulsi_const */
828 COSTS_N_INSNS (5), /* mulsi_const9 */
829 COSTS_N_INSNS (5), /* muldi */
830 COSTS_N_INSNS (36), /* divsi */
831 COSTS_N_INSNS (36), /* divdi */
832 COSTS_N_INSNS (4), /* fp */
833 COSTS_N_INSNS (5), /* dmul */
834 COSTS_N_INSNS (17), /* sdiv */
835 COSTS_N_INSNS (31), /* ddiv */
836 32, /* cache line size */
840 0, /* SF->DF convert */
843 /* Instruction costs on PPC603 processors. */
845 struct processor_costs ppc603_cost = {
846 COSTS_N_INSNS (5), /* mulsi */
847 COSTS_N_INSNS (3), /* mulsi_const */
848 COSTS_N_INSNS (2), /* mulsi_const9 */
849 COSTS_N_INSNS (5), /* muldi */
850 COSTS_N_INSNS (37), /* divsi */
851 COSTS_N_INSNS (37), /* divdi */
852 COSTS_N_INSNS (3), /* fp */
853 COSTS_N_INSNS (4), /* dmul */
854 COSTS_N_INSNS (18), /* sdiv */
855 COSTS_N_INSNS (33), /* ddiv */
856 32, /* cache line size */
860 0, /* SF->DF convert */
863 /* Instruction costs on PPC604 processors. */
865 struct processor_costs ppc604_cost = {
866 COSTS_N_INSNS (4), /* mulsi */
867 COSTS_N_INSNS (4), /* mulsi_const */
868 COSTS_N_INSNS (4), /* mulsi_const9 */
869 COSTS_N_INSNS (4), /* muldi */
870 COSTS_N_INSNS (20), /* divsi */
871 COSTS_N_INSNS (20), /* divdi */
872 COSTS_N_INSNS (3), /* fp */
873 COSTS_N_INSNS (3), /* dmul */
874 COSTS_N_INSNS (18), /* sdiv */
875 COSTS_N_INSNS (32), /* ddiv */
876 32, /* cache line size */
880 0, /* SF->DF convert */
883 /* Instruction costs on PPC604e processors. */
885 struct processor_costs ppc604e_cost = {
886 COSTS_N_INSNS (2), /* mulsi */
887 COSTS_N_INSNS (2), /* mulsi_const */
888 COSTS_N_INSNS (2), /* mulsi_const9 */
889 COSTS_N_INSNS (2), /* muldi */
890 COSTS_N_INSNS (20), /* divsi */
891 COSTS_N_INSNS (20), /* divdi */
892 COSTS_N_INSNS (3), /* fp */
893 COSTS_N_INSNS (3), /* dmul */
894 COSTS_N_INSNS (18), /* sdiv */
895 COSTS_N_INSNS (32), /* ddiv */
896 32, /* cache line size */
900 0, /* SF->DF convert */
903 /* Instruction costs on PPC620 processors. */
905 struct processor_costs ppc620_cost = {
906 COSTS_N_INSNS (5), /* mulsi */
907 COSTS_N_INSNS (4), /* mulsi_const */
908 COSTS_N_INSNS (3), /* mulsi_const9 */
909 COSTS_N_INSNS (7), /* muldi */
910 COSTS_N_INSNS (21), /* divsi */
911 COSTS_N_INSNS (37), /* divdi */
912 COSTS_N_INSNS (3), /* fp */
913 COSTS_N_INSNS (3), /* dmul */
914 COSTS_N_INSNS (18), /* sdiv */
915 COSTS_N_INSNS (32), /* ddiv */
916 128, /* cache line size */
920 0, /* SF->DF convert */
923 /* Instruction costs on PPC630 processors. */
925 struct processor_costs ppc630_cost = {
926 COSTS_N_INSNS (5), /* mulsi */
927 COSTS_N_INSNS (4), /* mulsi_const */
928 COSTS_N_INSNS (3), /* mulsi_const9 */
929 COSTS_N_INSNS (7), /* muldi */
930 COSTS_N_INSNS (21), /* divsi */
931 COSTS_N_INSNS (37), /* divdi */
932 COSTS_N_INSNS (3), /* fp */
933 COSTS_N_INSNS (3), /* dmul */
934 COSTS_N_INSNS (17), /* sdiv */
935 COSTS_N_INSNS (21), /* ddiv */
936 128, /* cache line size */
940 0, /* SF->DF convert */
943 /* Instruction costs on Cell processor. */
944 /* COSTS_N_INSNS (1) ~ one add. */
946 struct processor_costs ppccell_cost = {
947 COSTS_N_INSNS (9/2)+2, /* mulsi */
948 COSTS_N_INSNS (6/2), /* mulsi_const */
949 COSTS_N_INSNS (6/2), /* mulsi_const9 */
950 COSTS_N_INSNS (15/2)+2, /* muldi */
951 COSTS_N_INSNS (38/2), /* divsi */
952 COSTS_N_INSNS (70/2), /* divdi */
953 COSTS_N_INSNS (10/2), /* fp */
954 COSTS_N_INSNS (10/2), /* dmul */
955 COSTS_N_INSNS (74/2), /* sdiv */
956 COSTS_N_INSNS (74/2), /* ddiv */
957 128, /* cache line size */
961 0, /* SF->DF convert */
964 /* Instruction costs on PPC750 and PPC7400 processors. */
966 struct processor_costs ppc750_cost = {
967 COSTS_N_INSNS (5), /* mulsi */
968 COSTS_N_INSNS (3), /* mulsi_const */
969 COSTS_N_INSNS (2), /* mulsi_const9 */
970 COSTS_N_INSNS (5), /* muldi */
971 COSTS_N_INSNS (17), /* divsi */
972 COSTS_N_INSNS (17), /* divdi */
973 COSTS_N_INSNS (3), /* fp */
974 COSTS_N_INSNS (3), /* dmul */
975 COSTS_N_INSNS (17), /* sdiv */
976 COSTS_N_INSNS (31), /* ddiv */
977 32, /* cache line size */
981 0, /* SF->DF convert */
984 /* Instruction costs on PPC7450 processors. */
986 struct processor_costs ppc7450_cost = {
987 COSTS_N_INSNS (4), /* mulsi */
988 COSTS_N_INSNS (3), /* mulsi_const */
989 COSTS_N_INSNS (3), /* mulsi_const9 */
990 COSTS_N_INSNS (4), /* muldi */
991 COSTS_N_INSNS (23), /* divsi */
992 COSTS_N_INSNS (23), /* divdi */
993 COSTS_N_INSNS (5), /* fp */
994 COSTS_N_INSNS (5), /* dmul */
995 COSTS_N_INSNS (21), /* sdiv */
996 COSTS_N_INSNS (35), /* ddiv */
997 32, /* cache line size */
1001 0, /* SF->DF convert */
1004 /* Instruction costs on PPC8540 processors. */
1006 struct processor_costs ppc8540_cost = {
1007 COSTS_N_INSNS (4), /* mulsi */
1008 COSTS_N_INSNS (4), /* mulsi_const */
1009 COSTS_N_INSNS (4), /* mulsi_const9 */
1010 COSTS_N_INSNS (4), /* muldi */
1011 COSTS_N_INSNS (19), /* divsi */
1012 COSTS_N_INSNS (19), /* divdi */
1013 COSTS_N_INSNS (4), /* fp */
1014 COSTS_N_INSNS (4), /* dmul */
1015 COSTS_N_INSNS (29), /* sdiv */
1016 COSTS_N_INSNS (29), /* ddiv */
1017 32, /* cache line size */
1020 1, /* prefetch streams /*/
1021 0, /* SF->DF convert */
1024 /* Instruction costs on E300C2 and E300C3 cores. */
1026 struct processor_costs ppce300c2c3_cost = {
1027 COSTS_N_INSNS (4), /* mulsi */
1028 COSTS_N_INSNS (4), /* mulsi_const */
1029 COSTS_N_INSNS (4), /* mulsi_const9 */
1030 COSTS_N_INSNS (4), /* muldi */
1031 COSTS_N_INSNS (19), /* divsi */
1032 COSTS_N_INSNS (19), /* divdi */
1033 COSTS_N_INSNS (3), /* fp */
1034 COSTS_N_INSNS (4), /* dmul */
1035 COSTS_N_INSNS (18), /* sdiv */
1036 COSTS_N_INSNS (33), /* ddiv */
1040 1, /* prefetch streams /*/
1041 0, /* SF->DF convert */
1044 /* Instruction costs on PPCE500MC processors. */
1046 struct processor_costs ppce500mc_cost = {
1047 COSTS_N_INSNS (4), /* mulsi */
1048 COSTS_N_INSNS (4), /* mulsi_const */
1049 COSTS_N_INSNS (4), /* mulsi_const9 */
1050 COSTS_N_INSNS (4), /* muldi */
1051 COSTS_N_INSNS (14), /* divsi */
1052 COSTS_N_INSNS (14), /* divdi */
1053 COSTS_N_INSNS (8), /* fp */
1054 COSTS_N_INSNS (10), /* dmul */
1055 COSTS_N_INSNS (36), /* sdiv */
1056 COSTS_N_INSNS (66), /* ddiv */
1057 64, /* cache line size */
1060 1, /* prefetch streams /*/
1061 0, /* SF->DF convert */
1064 /* Instruction costs on PPCE500MC64 processors. */
1066 struct processor_costs ppce500mc64_cost = {
1067 COSTS_N_INSNS (4), /* mulsi */
1068 COSTS_N_INSNS (4), /* mulsi_const */
1069 COSTS_N_INSNS (4), /* mulsi_const9 */
1070 COSTS_N_INSNS (4), /* muldi */
1071 COSTS_N_INSNS (14), /* divsi */
1072 COSTS_N_INSNS (14), /* divdi */
1073 COSTS_N_INSNS (4), /* fp */
1074 COSTS_N_INSNS (10), /* dmul */
1075 COSTS_N_INSNS (36), /* sdiv */
1076 COSTS_N_INSNS (66), /* ddiv */
1077 64, /* cache line size */
1080 1, /* prefetch streams /*/
1081 0, /* SF->DF convert */
1084 /* Instruction costs on PPCE5500 processors. */
1086 struct processor_costs ppce5500_cost = {
1087 COSTS_N_INSNS (5), /* mulsi */
1088 COSTS_N_INSNS (5), /* mulsi_const */
1089 COSTS_N_INSNS (4), /* mulsi_const9 */
1090 COSTS_N_INSNS (5), /* muldi */
1091 COSTS_N_INSNS (14), /* divsi */
1092 COSTS_N_INSNS (14), /* divdi */
1093 COSTS_N_INSNS (7), /* fp */
1094 COSTS_N_INSNS (10), /* dmul */
1095 COSTS_N_INSNS (36), /* sdiv */
1096 COSTS_N_INSNS (66), /* ddiv */
1097 64, /* cache line size */
1100 1, /* prefetch streams /*/
1101 0, /* SF->DF convert */
1104 /* Instruction costs on PPCE6500 processors. */
1106 struct processor_costs ppce6500_cost = {
1107 COSTS_N_INSNS (5), /* mulsi */
1108 COSTS_N_INSNS (5), /* mulsi_const */
1109 COSTS_N_INSNS (4), /* mulsi_const9 */
1110 COSTS_N_INSNS (5), /* muldi */
1111 COSTS_N_INSNS (14), /* divsi */
1112 COSTS_N_INSNS (14), /* divdi */
1113 COSTS_N_INSNS (7), /* fp */
1114 COSTS_N_INSNS (10), /* dmul */
1115 COSTS_N_INSNS (36), /* sdiv */
1116 COSTS_N_INSNS (66), /* ddiv */
1117 64, /* cache line size */
1120 1, /* prefetch streams /*/
1121 0, /* SF->DF convert */
1124 /* Instruction costs on AppliedMicro Titan processors. */
1126 struct processor_costs titan_cost = {
1127 COSTS_N_INSNS (5), /* mulsi */
1128 COSTS_N_INSNS (5), /* mulsi_const */
1129 COSTS_N_INSNS (5), /* mulsi_const9 */
1130 COSTS_N_INSNS (5), /* muldi */
1131 COSTS_N_INSNS (18), /* divsi */
1132 COSTS_N_INSNS (18), /* divdi */
1133 COSTS_N_INSNS (10), /* fp */
1134 COSTS_N_INSNS (10), /* dmul */
1135 COSTS_N_INSNS (46), /* sdiv */
1136 COSTS_N_INSNS (72), /* ddiv */
1137 32, /* cache line size */
1140 1, /* prefetch streams /*/
1141 0, /* SF->DF convert */
1144 /* Instruction costs on POWER4 and POWER5 processors. */
1146 struct processor_costs power4_cost = {
1147 COSTS_N_INSNS (3), /* mulsi */
1148 COSTS_N_INSNS (2), /* mulsi_const */
1149 COSTS_N_INSNS (2), /* mulsi_const9 */
1150 COSTS_N_INSNS (4), /* muldi */
1151 COSTS_N_INSNS (18), /* divsi */
1152 COSTS_N_INSNS (34), /* divdi */
1153 COSTS_N_INSNS (3), /* fp */
1154 COSTS_N_INSNS (3), /* dmul */
1155 COSTS_N_INSNS (17), /* sdiv */
1156 COSTS_N_INSNS (17), /* ddiv */
1157 128, /* cache line size */
1159 1024, /* l2 cache */
1160 8, /* prefetch streams /*/
1161 0, /* SF->DF convert */
1164 /* Instruction costs on POWER6 processors. */
1166 struct processor_costs power6_cost = {
1167 COSTS_N_INSNS (8), /* mulsi */
1168 COSTS_N_INSNS (8), /* mulsi_const */
1169 COSTS_N_INSNS (8), /* mulsi_const9 */
1170 COSTS_N_INSNS (8), /* muldi */
1171 COSTS_N_INSNS (22), /* divsi */
1172 COSTS_N_INSNS (28), /* divdi */
1173 COSTS_N_INSNS (3), /* fp */
1174 COSTS_N_INSNS (3), /* dmul */
1175 COSTS_N_INSNS (13), /* sdiv */
1176 COSTS_N_INSNS (16), /* ddiv */
1177 128, /* cache line size */
1179 2048, /* l2 cache */
1180 16, /* prefetch streams */
1181 0, /* SF->DF convert */
1184 /* Instruction costs on POWER7 processors. */
1186 struct processor_costs power7_cost = {
1187 COSTS_N_INSNS (2), /* mulsi */
1188 COSTS_N_INSNS (2), /* mulsi_const */
1189 COSTS_N_INSNS (2), /* mulsi_const9 */
1190 COSTS_N_INSNS (2), /* muldi */
1191 COSTS_N_INSNS (18), /* divsi */
1192 COSTS_N_INSNS (34), /* divdi */
1193 COSTS_N_INSNS (3), /* fp */
1194 COSTS_N_INSNS (3), /* dmul */
1195 COSTS_N_INSNS (13), /* sdiv */
1196 COSTS_N_INSNS (16), /* ddiv */
1197 128, /* cache line size */
1200 12, /* prefetch streams */
1201 COSTS_N_INSNS (3), /* SF->DF convert */
1204 /* Instruction costs on POWER8 processors. */
1206 struct processor_costs power8_cost = {
1207 COSTS_N_INSNS (3), /* mulsi */
1208 COSTS_N_INSNS (3), /* mulsi_const */
1209 COSTS_N_INSNS (3), /* mulsi_const9 */
1210 COSTS_N_INSNS (3), /* muldi */
1211 COSTS_N_INSNS (19), /* divsi */
1212 COSTS_N_INSNS (35), /* divdi */
1213 COSTS_N_INSNS (3), /* fp */
1214 COSTS_N_INSNS (3), /* dmul */
1215 COSTS_N_INSNS (14), /* sdiv */
1216 COSTS_N_INSNS (17), /* ddiv */
1217 128, /* cache line size */
1220 12, /* prefetch streams */
1221 COSTS_N_INSNS (3), /* SF->DF convert */
1224 /* Instruction costs on POWER9 processors. */
1226 struct processor_costs power9_cost = {
1227 COSTS_N_INSNS (3), /* mulsi */
1228 COSTS_N_INSNS (3), /* mulsi_const */
1229 COSTS_N_INSNS (3), /* mulsi_const9 */
1230 COSTS_N_INSNS (3), /* muldi */
1231 COSTS_N_INSNS (8), /* divsi */
1232 COSTS_N_INSNS (12), /* divdi */
1233 COSTS_N_INSNS (3), /* fp */
1234 COSTS_N_INSNS (3), /* dmul */
1235 COSTS_N_INSNS (13), /* sdiv */
1236 COSTS_N_INSNS (18), /* ddiv */
1237 128, /* cache line size */
1240 8, /* prefetch streams */
1241 COSTS_N_INSNS (3), /* SF->DF convert */
1244 /* Instruction costs on POWER A2 processors. */
1246 struct processor_costs ppca2_cost = {
1247 COSTS_N_INSNS (16), /* mulsi */
1248 COSTS_N_INSNS (16), /* mulsi_const */
1249 COSTS_N_INSNS (16), /* mulsi_const9 */
1250 COSTS_N_INSNS (16), /* muldi */
1251 COSTS_N_INSNS (22), /* divsi */
1252 COSTS_N_INSNS (28), /* divdi */
1253 COSTS_N_INSNS (3), /* fp */
1254 COSTS_N_INSNS (3), /* dmul */
1255 COSTS_N_INSNS (59), /* sdiv */
1256 COSTS_N_INSNS (72), /* ddiv */
1259 2048, /* l2 cache */
1260 16, /* prefetch streams */
1261 0, /* SF->DF convert */
1265 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1266 #undef RS6000_BUILTIN_0
1267 #undef RS6000_BUILTIN_1
1268 #undef RS6000_BUILTIN_2
1269 #undef RS6000_BUILTIN_3
1270 #undef RS6000_BUILTIN_A
1271 #undef RS6000_BUILTIN_D
1272 #undef RS6000_BUILTIN_H
1273 #undef RS6000_BUILTIN_P
1274 #undef RS6000_BUILTIN_X
1276 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1277 { NAME, ICODE, MASK, ATTR },
1279 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1280 { NAME, ICODE, MASK, ATTR },
1282 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1283 { NAME, ICODE, MASK, ATTR },
1285 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1286 { NAME, ICODE, MASK, ATTR },
1288 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1289 { NAME, ICODE, MASK, ATTR },
1291 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1292 { NAME, ICODE, MASK, ATTR },
1294 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1295 { NAME, ICODE, MASK, ATTR },
1297 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1298 { NAME, ICODE, MASK, ATTR },
1300 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1301 { NAME, ICODE, MASK, ATTR },
1303 struct rs6000_builtin_info_type {
1305 const enum insn_code icode;
1306 const HOST_WIDE_INT mask;
1307 const unsigned attr;
1310 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1312 #include "rs6000-builtin.def"
1315 #undef RS6000_BUILTIN_0
1316 #undef RS6000_BUILTIN_1
1317 #undef RS6000_BUILTIN_2
1318 #undef RS6000_BUILTIN_3
1319 #undef RS6000_BUILTIN_A
1320 #undef RS6000_BUILTIN_D
1321 #undef RS6000_BUILTIN_H
1322 #undef RS6000_BUILTIN_P
1323 #undef RS6000_BUILTIN_X
1325 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1326 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1329 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1330 static struct machine_function * rs6000_init_machine_status (void);
1331 static int rs6000_ra_ever_killed (void);
1332 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1333 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1334 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1335 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1336 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1337 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1338 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1339 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1341 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1343 static bool is_microcoded_insn (rtx_insn *);
1344 static bool is_nonpipeline_insn (rtx_insn *);
1345 static bool is_cracked_insn (rtx_insn *);
1346 static bool is_load_insn (rtx, rtx *);
1347 static bool is_store_insn (rtx, rtx *);
1348 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1349 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1350 static bool insn_must_be_first_in_group (rtx_insn *);
1351 static bool insn_must_be_last_in_group (rtx_insn *);
1352 static void altivec_init_builtins (void);
1353 static tree builtin_function_type (machine_mode, machine_mode,
1354 machine_mode, machine_mode,
1355 enum rs6000_builtins, const char *name);
1356 static void rs6000_common_init_builtins (void);
1357 static void htm_init_builtins (void);
1358 static rs6000_stack_t *rs6000_stack_info (void);
1359 static void is_altivec_return_reg (rtx, void *);
1360 int easy_vector_constant (rtx, machine_mode);
1361 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1362 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1363 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1366 static void macho_branch_islands (void);
1368 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1370 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1372 static bool rs6000_mode_dependent_address (const_rtx);
1373 static bool rs6000_debug_mode_dependent_address (const_rtx);
1374 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1375 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1377 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1380 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1381 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1383 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1386 static bool rs6000_debug_can_change_mode_class (machine_mode,
1389 static bool rs6000_save_toc_in_prologue_p (void);
1390 static rtx rs6000_internal_arg_pointer (void);
1392 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1394 = rs6000_legitimize_reload_address;
1396 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1397 = rs6000_mode_dependent_address;
1399 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1401 = rs6000_secondary_reload_class;
1403 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1404 = rs6000_preferred_reload_class;
1406 const int INSN_NOT_AVAILABLE = -1;
1408 static void rs6000_print_isa_options (FILE *, int, const char *,
1410 static void rs6000_print_builtin_options (FILE *, int, const char *,
1412 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1414 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1415 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1416 enum rs6000_reg_type,
1418 secondary_reload_info *,
1420 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1421 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1422 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1424 /* Hash table stuff for keeping track of TOC entries. */
1426 struct GTY((for_user)) toc_hash_struct
1428 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1429 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1431 machine_mode key_mode;
1435 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1437 static hashval_t hash (toc_hash_struct *);
1438 static bool equal (toc_hash_struct *, toc_hash_struct *);
1441 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1443 /* Hash table to keep track of the argument types for builtin functions. */
1445 struct GTY((for_user)) builtin_hash_struct
1448 machine_mode mode[4]; /* return value + 3 arguments. */
1449 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1452 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1454 static hashval_t hash (builtin_hash_struct *);
1455 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1458 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1461 /* Default register names. */
1462 char rs6000_reg_names[][8] =
1464 "0", "1", "2", "3", "4", "5", "6", "7",
1465 "8", "9", "10", "11", "12", "13", "14", "15",
1466 "16", "17", "18", "19", "20", "21", "22", "23",
1467 "24", "25", "26", "27", "28", "29", "30", "31",
1468 "0", "1", "2", "3", "4", "5", "6", "7",
1469 "8", "9", "10", "11", "12", "13", "14", "15",
1470 "16", "17", "18", "19", "20", "21", "22", "23",
1471 "24", "25", "26", "27", "28", "29", "30", "31",
1472 "mq", "lr", "ctr","ap",
1473 "0", "1", "2", "3", "4", "5", "6", "7",
1475 /* AltiVec registers. */
1476 "0", "1", "2", "3", "4", "5", "6", "7",
1477 "8", "9", "10", "11", "12", "13", "14", "15",
1478 "16", "17", "18", "19", "20", "21", "22", "23",
1479 "24", "25", "26", "27", "28", "29", "30", "31",
1481 /* Soft frame pointer. */
1483 /* HTM SPR registers. */
1484 "tfhar", "tfiar", "texasr"
1487 #ifdef TARGET_REGNAMES
1488 static const char alt_reg_names[][8] =
1490 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1491 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1492 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1493 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1494 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1495 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1496 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1497 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1498 "mq", "lr", "ctr", "ap",
1499 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1501 /* AltiVec registers. */
1502 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1503 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1504 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1505 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1507 /* Soft frame pointer. */
1509 /* HTM SPR registers. */
1510 "tfhar", "tfiar", "texasr"
1514 /* Table of valid machine attributes. */
1516 static const struct attribute_spec rs6000_attribute_table[] =
1518 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1519 affects_type_identity, handler, exclude } */
1520 { "altivec", 1, 1, false, true, false, false,
1521 rs6000_handle_altivec_attribute, NULL },
1522 { "longcall", 0, 0, false, true, true, false,
1523 rs6000_handle_longcall_attribute, NULL },
1524 { "shortcall", 0, 0, false, true, true, false,
1525 rs6000_handle_longcall_attribute, NULL },
1526 { "ms_struct", 0, 0, false, false, false, false,
1527 rs6000_handle_struct_attribute, NULL },
1528 { "gcc_struct", 0, 0, false, false, false, false,
1529 rs6000_handle_struct_attribute, NULL },
1530 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1531 SUBTARGET_ATTRIBUTE_TABLE,
1533 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1536 #ifndef TARGET_PROFILE_KERNEL
1537 #define TARGET_PROFILE_KERNEL 0
1540 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1541 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1543 /* Initialize the GCC target structure. */
1544 #undef TARGET_ATTRIBUTE_TABLE
1545 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1546 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1547 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1548 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1549 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1551 #undef TARGET_ASM_ALIGNED_DI_OP
1552 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1554 /* Default unaligned ops are only provided for ELF. Find the ops needed
1555 for non-ELF systems. */
1556 #ifndef OBJECT_FORMAT_ELF
1558 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1560 #undef TARGET_ASM_UNALIGNED_HI_OP
1561 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1562 #undef TARGET_ASM_UNALIGNED_SI_OP
1563 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1564 #undef TARGET_ASM_UNALIGNED_DI_OP
1565 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1568 #undef TARGET_ASM_UNALIGNED_HI_OP
1569 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1570 #undef TARGET_ASM_UNALIGNED_SI_OP
1571 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1572 #undef TARGET_ASM_UNALIGNED_DI_OP
1573 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1574 #undef TARGET_ASM_ALIGNED_DI_OP
1575 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1579 /* This hook deals with fixups for relocatable code and DI-mode objects
1581 #undef TARGET_ASM_INTEGER
1582 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1584 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1585 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1586 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1589 #undef TARGET_SET_UP_BY_PROLOGUE
1590 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1592 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1593 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1594 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1595 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1596 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1597 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1598 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1599 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1600 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1601 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1602 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1603 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1605 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1606 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1608 #undef TARGET_INTERNAL_ARG_POINTER
1609 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1611 #undef TARGET_HAVE_TLS
1612 #define TARGET_HAVE_TLS HAVE_AS_TLS
1614 #undef TARGET_CANNOT_FORCE_CONST_MEM
1615 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1617 #undef TARGET_DELEGITIMIZE_ADDRESS
1618 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1620 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1621 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1623 #undef TARGET_LEGITIMATE_COMBINED_INSN
1624 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1626 #undef TARGET_ASM_FUNCTION_PROLOGUE
1627 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1628 #undef TARGET_ASM_FUNCTION_EPILOGUE
1629 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1631 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1632 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1634 #undef TARGET_LEGITIMIZE_ADDRESS
1635 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1637 #undef TARGET_SCHED_VARIABLE_ISSUE
1638 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1640 #undef TARGET_SCHED_ISSUE_RATE
1641 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1642 #undef TARGET_SCHED_ADJUST_COST
1643 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1644 #undef TARGET_SCHED_ADJUST_PRIORITY
1645 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1646 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1647 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1648 #undef TARGET_SCHED_INIT
1649 #define TARGET_SCHED_INIT rs6000_sched_init
1650 #undef TARGET_SCHED_FINISH
1651 #define TARGET_SCHED_FINISH rs6000_sched_finish
1652 #undef TARGET_SCHED_REORDER
1653 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1654 #undef TARGET_SCHED_REORDER2
1655 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1657 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1658 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1660 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1661 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1663 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1664 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1665 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1666 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1667 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1668 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1669 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1670 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1672 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1673 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1675 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1676 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1677 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1678 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1679 rs6000_builtin_support_vector_misalignment
1680 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1681 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1682 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1683 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1684 rs6000_builtin_vectorization_cost
1685 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1686 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1687 rs6000_preferred_simd_mode
1688 #undef TARGET_VECTORIZE_INIT_COST
1689 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1690 #undef TARGET_VECTORIZE_ADD_STMT_COST
1691 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1692 #undef TARGET_VECTORIZE_FINISH_COST
1693 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1694 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1695 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1697 #undef TARGET_INIT_BUILTINS
1698 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1699 #undef TARGET_BUILTIN_DECL
1700 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1702 #undef TARGET_FOLD_BUILTIN
1703 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1704 #undef TARGET_GIMPLE_FOLD_BUILTIN
1705 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1707 #undef TARGET_EXPAND_BUILTIN
1708 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1710 #undef TARGET_MANGLE_TYPE
1711 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1713 #undef TARGET_INIT_LIBFUNCS
1714 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1717 #undef TARGET_BINDS_LOCAL_P
1718 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1721 #undef TARGET_MS_BITFIELD_LAYOUT_P
1722 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1724 #undef TARGET_ASM_OUTPUT_MI_THUNK
1725 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1727 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1728 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1730 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1731 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1733 #undef TARGET_REGISTER_MOVE_COST
1734 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1735 #undef TARGET_MEMORY_MOVE_COST
1736 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1737 #undef TARGET_CANNOT_COPY_INSN_P
1738 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1739 #undef TARGET_RTX_COSTS
1740 #define TARGET_RTX_COSTS rs6000_rtx_costs
1741 #undef TARGET_ADDRESS_COST
1742 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1743 #undef TARGET_INSN_COST
1744 #define TARGET_INSN_COST rs6000_insn_cost
1746 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1747 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1749 #undef TARGET_PROMOTE_FUNCTION_MODE
1750 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1752 #undef TARGET_RETURN_IN_MEMORY
1753 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1755 #undef TARGET_RETURN_IN_MSB
1756 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1758 #undef TARGET_SETUP_INCOMING_VARARGS
1759 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1761 /* Always strict argument naming on rs6000. */
1762 #undef TARGET_STRICT_ARGUMENT_NAMING
1763 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1765 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1766 #undef TARGET_SPLIT_COMPLEX_ARG
1767 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1768 #undef TARGET_MUST_PASS_IN_STACK
1769 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1770 #undef TARGET_PASS_BY_REFERENCE
1771 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1772 #undef TARGET_ARG_PARTIAL_BYTES
1773 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1774 #undef TARGET_FUNCTION_ARG_ADVANCE
1775 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1776 #undef TARGET_FUNCTION_ARG
1777 #define TARGET_FUNCTION_ARG rs6000_function_arg
1778 #undef TARGET_FUNCTION_ARG_PADDING
1779 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1780 #undef TARGET_FUNCTION_ARG_BOUNDARY
1781 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1783 #undef TARGET_BUILD_BUILTIN_VA_LIST
1784 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1786 #undef TARGET_EXPAND_BUILTIN_VA_START
1787 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1789 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1790 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1792 #undef TARGET_EH_RETURN_FILTER_MODE
1793 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1795 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1796 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1798 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1799 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1801 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1802 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1804 #undef TARGET_FLOATN_MODE
1805 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1807 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1808 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1810 #undef TARGET_MD_ASM_ADJUST
1811 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1813 #undef TARGET_OPTION_OVERRIDE
1814 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1816 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1817 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1818 rs6000_builtin_vectorized_function
1820 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1821 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1822 rs6000_builtin_md_vectorized_function
1824 #undef TARGET_STACK_PROTECT_GUARD
1825 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1828 #undef TARGET_STACK_PROTECT_FAIL
1829 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1833 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1834 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1837 /* Use a 32-bit anchor range. This leads to sequences like:
1839 addis tmp,anchor,high
1842 where tmp itself acts as an anchor, and can be shared between
1843 accesses to the same 64k page. */
1844 #undef TARGET_MIN_ANCHOR_OFFSET
1845 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1846 #undef TARGET_MAX_ANCHOR_OFFSET
1847 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1848 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1849 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1850 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1851 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1853 #undef TARGET_BUILTIN_RECIPROCAL
1854 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1856 #undef TARGET_SECONDARY_RELOAD
1857 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED
1859 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1860 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1861 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1863 #undef TARGET_LEGITIMATE_ADDRESS_P
1864 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1866 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1867 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1869 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1870 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1872 #undef TARGET_CAN_ELIMINATE
1873 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1875 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1876 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1878 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1879 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1881 #undef TARGET_TRAMPOLINE_INIT
1882 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1884 #undef TARGET_FUNCTION_VALUE
1885 #define TARGET_FUNCTION_VALUE rs6000_function_value
1887 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1888 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1890 #undef TARGET_OPTION_SAVE
1891 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1893 #undef TARGET_OPTION_RESTORE
1894 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1896 #undef TARGET_OPTION_PRINT
1897 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1899 #undef TARGET_CAN_INLINE_P
1900 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1902 #undef TARGET_SET_CURRENT_FUNCTION
1903 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1905 #undef TARGET_LEGITIMATE_CONSTANT_P
1906 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1908 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1909 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1911 #undef TARGET_CAN_USE_DOLOOP_P
1912 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1914 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1915 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1917 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1918 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1919 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1920 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1921 #undef TARGET_UNWIND_WORD_MODE
1922 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1924 #undef TARGET_OFFLOAD_OPTIONS
1925 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1927 #undef TARGET_C_MODE_FOR_SUFFIX
1928 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1930 #undef TARGET_INVALID_BINARY_OP
1931 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1933 #undef TARGET_OPTAB_SUPPORTED_P
1934 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1936 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1937 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1939 #undef TARGET_COMPARE_VERSION_PRIORITY
1940 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1942 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1943 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1944 rs6000_generate_version_dispatcher_body
1946 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1947 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1948 rs6000_get_function_versions_dispatcher
1950 #undef TARGET_OPTION_FUNCTION_VERSIONS
1951 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1953 #undef TARGET_HARD_REGNO_NREGS
1954 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1955 #undef TARGET_HARD_REGNO_MODE_OK
1956 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1958 #undef TARGET_MODES_TIEABLE_P
1959 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1961 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1962 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1963 rs6000_hard_regno_call_part_clobbered
1965 #undef TARGET_SLOW_UNALIGNED_ACCESS
1966 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1968 #undef TARGET_CAN_CHANGE_MODE_CLASS
1969 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1971 #undef TARGET_CONSTANT_ALIGNMENT
1972 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1974 #undef TARGET_STARTING_FRAME_OFFSET
1975 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1977 #if TARGET_ELF && RS6000_WEAK
1978 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1979 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1982 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1983 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1985 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1986 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1989 /* Processor table. */
1992 const char *const name; /* Canonical processor name. */
1993 const enum processor_type processor; /* Processor type enum value. */
1994 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1997 static struct rs6000_ptt const processor_target_table[] =
1999 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
2000 #include "rs6000-cpus.def"
2004 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2008 rs6000_cpu_name_lookup (const char *name)
2014 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2015 if (! strcmp (name, processor_target_table[i].name))
2023 /* Return number of consecutive hard regs needed starting at reg REGNO
2024 to hold something of mode MODE.
2025 This is ordinarily the length in words of a value of mode MODE
2026 but can be less for certain modes in special long registers.
2028 POWER and PowerPC GPRs hold 32 bits worth;
2029 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2032 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2034 unsigned HOST_WIDE_INT reg_size;
2036 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2037 128-bit floating point that can go in vector registers, which has VSX
2038 memory addressing. */
2039 if (FP_REGNO_P (regno))
2040 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2041 ? UNITS_PER_VSX_WORD
2042 : UNITS_PER_FP_WORD);
2044 else if (ALTIVEC_REGNO_P (regno))
2045 reg_size = UNITS_PER_ALTIVEC_WORD;
2048 reg_size = UNITS_PER_WORD;
2050 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2053 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2056 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2058 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2060 if (COMPLEX_MODE_P (mode))
2061 mode = GET_MODE_INNER (mode);
2063 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2064 register combinations, and use PTImode where we need to deal with quad
2065 word memory operations. Don't allow quad words in the argument or frame
2066 pointer registers, just registers 0..31. */
2067 if (mode == PTImode)
2068 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2069 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2070 && ((regno & 1) == 0));
2072 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2073 implementations. Don't allow an item to be split between a FP register
2074 and an Altivec register. Allow TImode in all VSX registers if the user
2076 if (TARGET_VSX && VSX_REGNO_P (regno)
2077 && (VECTOR_MEM_VSX_P (mode)
2078 || FLOAT128_VECTOR_P (mode)
2079 || reg_addr[mode].scalar_in_vmx_p
2081 || (TARGET_VADDUQM && mode == V1TImode)))
2083 if (FP_REGNO_P (regno))
2084 return FP_REGNO_P (last_regno);
2086 if (ALTIVEC_REGNO_P (regno))
2088 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2091 return ALTIVEC_REGNO_P (last_regno);
2095 /* The GPRs can hold any mode, but values bigger than one register
2096 cannot go past R31. */
2097 if (INT_REGNO_P (regno))
2098 return INT_REGNO_P (last_regno);
2100 /* The float registers (except for VSX vector modes) can only hold floating
2101 modes and DImode. */
2102 if (FP_REGNO_P (regno))
2104 if (FLOAT128_VECTOR_P (mode))
2107 if (SCALAR_FLOAT_MODE_P (mode)
2108 && (mode != TDmode || (regno % 2) == 0)
2109 && FP_REGNO_P (last_regno))
2112 if (GET_MODE_CLASS (mode) == MODE_INT)
2114 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2117 if (TARGET_P8_VECTOR && (mode == SImode))
2120 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2127 /* The CR register can only hold CC modes. */
2128 if (CR_REGNO_P (regno))
2129 return GET_MODE_CLASS (mode) == MODE_CC;
2131 if (CA_REGNO_P (regno))
2132 return mode == Pmode || mode == SImode;
2134 /* AltiVec only in AldyVec registers. */
2135 if (ALTIVEC_REGNO_P (regno))
2136 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2137 || mode == V1TImode);
2139 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2140 and it must be able to fit within the register set. */
2142 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2145 /* Implement TARGET_HARD_REGNO_NREGS. */
2148 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2150 return rs6000_hard_regno_nregs[mode][regno];
2153 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2156 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2158 return rs6000_hard_regno_mode_ok_p[mode][regno];
2161 /* Implement TARGET_MODES_TIEABLE_P.
2163 PTImode cannot tie with other modes because PTImode is restricted to even
2164 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2167 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2168 128-bit floating point on VSX systems ties with other vectors. */
2171 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2173 if (mode1 == PTImode)
2174 return mode2 == PTImode;
2175 if (mode2 == PTImode)
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2179 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2180 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2183 if (SCALAR_FLOAT_MODE_P (mode1))
2184 return SCALAR_FLOAT_MODE_P (mode2);
2185 if (SCALAR_FLOAT_MODE_P (mode2))
2188 if (GET_MODE_CLASS (mode1) == MODE_CC)
2189 return GET_MODE_CLASS (mode2) == MODE_CC;
2190 if (GET_MODE_CLASS (mode2) == MODE_CC)
2196 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2199 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2203 && GET_MODE_SIZE (mode) > 4
2204 && INT_REGNO_P (regno))
2208 && FP_REGNO_P (regno)
2209 && GET_MODE_SIZE (mode) > 8
2210 && !FLOAT128_2REG_P (mode))
2216 /* Print interesting facts about registers. */
2218 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2222 for (r = first_regno; r <= last_regno; ++r)
2224 const char *comma = "";
2227 if (first_regno == last_regno)
2228 fprintf (stderr, "%s:\t", reg_name);
2230 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2233 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2234 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2238 fprintf (stderr, ",\n\t");
2243 if (rs6000_hard_regno_nregs[m][r] > 1)
2244 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2245 rs6000_hard_regno_nregs[m][r]);
2247 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2252 if (call_used_regs[r])
2256 fprintf (stderr, ",\n\t");
2261 len += fprintf (stderr, "%s%s", comma, "call-used");
2269 fprintf (stderr, ",\n\t");
2274 len += fprintf (stderr, "%s%s", comma, "fixed");
2280 fprintf (stderr, ",\n\t");
2284 len += fprintf (stderr, "%sreg-class = %s", comma,
2285 reg_class_names[(int)rs6000_regno_regclass[r]]);
2290 fprintf (stderr, ",\n\t");
2294 fprintf (stderr, "%sregno = %d\n", comma, r);
2299 rs6000_debug_vector_unit (enum rs6000_vector v)
2305 case VECTOR_NONE: ret = "none"; break;
2306 case VECTOR_ALTIVEC: ret = "altivec"; break;
2307 case VECTOR_VSX: ret = "vsx"; break;
2308 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2309 default: ret = "unknown"; break;
2315 /* Inner function printing just the address mask for a particular reload
2317 DEBUG_FUNCTION char *
2318 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2323 if ((mask & RELOAD_REG_VALID) != 0)
2325 else if (keep_spaces)
2328 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2330 else if (keep_spaces)
2333 if ((mask & RELOAD_REG_INDEXED) != 0)
2335 else if (keep_spaces)
2338 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2340 else if ((mask & RELOAD_REG_OFFSET) != 0)
2342 else if (keep_spaces)
2345 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2347 else if (keep_spaces)
2350 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2352 else if (keep_spaces)
2355 if ((mask & RELOAD_REG_AND_M16) != 0)
2357 else if (keep_spaces)
2365 /* Print the address masks in a human readble fashion. */
2367 rs6000_debug_print_mode (ssize_t m)
2372 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2373 for (rc = 0; rc < N_RELOAD_REG; rc++)
2374 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2375 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2377 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2378 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2380 fprintf (stderr, "%*s Reload=%c%c", spaces, "",
2381 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2382 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2386 spaces += sizeof (" Reload=sl") - 1;
2388 if (reg_addr[m].scalar_in_vmx_p)
2390 fprintf (stderr, "%*s Upper=y", spaces, "");
2394 spaces += sizeof (" Upper=y") - 1;
2396 if (rs6000_vector_unit[m] != VECTOR_NONE
2397 || rs6000_vector_mem[m] != VECTOR_NONE)
2399 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2401 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2402 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2405 fputs ("\n", stderr);
2408 #define DEBUG_FMT_ID "%-32s= "
2409 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2410 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2411 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2413 /* Print various interesting information with -mdebug=reg. */
2415 rs6000_debug_reg_global (void)
2417 static const char *const tf[2] = { "false", "true" };
2418 const char *nl = (const char *)0;
2421 char costly_num[20];
2423 char flags_buffer[40];
2424 const char *costly_str;
2425 const char *nop_str;
2426 const char *trace_str;
2427 const char *abi_str;
2428 const char *cmodel_str;
2429 struct cl_target_option cl_opts;
2431 /* Modes we want tieable information on. */
2432 static const machine_mode print_tieable_modes[] = {
2466 /* Virtual regs we are interested in. */
2467 const static struct {
2468 int regno; /* register number. */
2469 const char *name; /* register name. */
2470 } virtual_regs[] = {
2471 { STACK_POINTER_REGNUM, "stack pointer:" },
2472 { TOC_REGNUM, "toc: " },
2473 { STATIC_CHAIN_REGNUM, "static chain: " },
2474 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2475 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2476 { ARG_POINTER_REGNUM, "arg pointer: " },
2477 { FRAME_POINTER_REGNUM, "frame pointer:" },
2478 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2479 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2480 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2481 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2482 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2483 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2484 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2485 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2486 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2489 fputs ("\nHard register information:\n", stderr);
2490 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2491 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2492 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2495 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2496 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2497 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2498 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2499 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2500 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2502 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2503 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2504 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2508 "d reg_class = %s\n"
2509 "f reg_class = %s\n"
2510 "v reg_class = %s\n"
2511 "wa reg_class = %s\n"
2512 "wb reg_class = %s\n"
2513 "wd reg_class = %s\n"
2514 "we reg_class = %s\n"
2515 "wf reg_class = %s\n"
2516 "wg reg_class = %s\n"
2517 "wh reg_class = %s\n"
2518 "wi reg_class = %s\n"
2519 "wj reg_class = %s\n"
2520 "wk reg_class = %s\n"
2521 "wl reg_class = %s\n"
2522 "wm reg_class = %s\n"
2523 "wo reg_class = %s\n"
2524 "wp reg_class = %s\n"
2525 "wq reg_class = %s\n"
2526 "wr reg_class = %s\n"
2527 "ws reg_class = %s\n"
2528 "wt reg_class = %s\n"
2529 "wu reg_class = %s\n"
2530 "wv reg_class = %s\n"
2531 "ww reg_class = %s\n"
2532 "wx reg_class = %s\n"
2533 "wy reg_class = %s\n"
2534 "wz reg_class = %s\n"
2535 "wA reg_class = %s\n"
2536 "wH reg_class = %s\n"
2537 "wI reg_class = %s\n"
2538 "wJ reg_class = %s\n"
2539 "wK reg_class = %s\n"
2541 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2542 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2543 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2544 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2545 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2546 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2547 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2548 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2549 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2550 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2551 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2552 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2553 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2554 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2555 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2556 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2557 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2558 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2559 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2560 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2561 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2562 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2563 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2564 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2565 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2566 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2567 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2568 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2569 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2570 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2571 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2572 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2575 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2576 rs6000_debug_print_mode (m);
2578 fputs ("\n", stderr);
2580 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2582 machine_mode mode1 = print_tieable_modes[m1];
2583 bool first_time = true;
2585 nl = (const char *)0;
2586 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2588 machine_mode mode2 = print_tieable_modes[m2];
2589 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2593 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2598 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2603 fputs ("\n", stderr);
2609 if (rs6000_recip_control)
2611 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2613 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2614 if (rs6000_recip_bits[m])
2617 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2619 (RS6000_RECIP_AUTO_RE_P (m)
2621 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2622 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2624 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2627 fputs ("\n", stderr);
2630 if (rs6000_cpu_index >= 0)
2632 const char *name = processor_target_table[rs6000_cpu_index].name;
2634 = processor_target_table[rs6000_cpu_index].target_enable;
2636 sprintf (flags_buffer, "-mcpu=%s flags", name);
2637 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2640 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2642 if (rs6000_tune_index >= 0)
2644 const char *name = processor_target_table[rs6000_tune_index].name;
2646 = processor_target_table[rs6000_tune_index].target_enable;
2648 sprintf (flags_buffer, "-mtune=%s flags", name);
2649 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2652 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2654 cl_target_option_save (&cl_opts, &global_options);
2655 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2658 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2659 rs6000_isa_flags_explicit);
2661 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2662 rs6000_builtin_mask);
2664 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2666 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2667 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2669 switch (rs6000_sched_costly_dep)
2671 case max_dep_latency:
2672 costly_str = "max_dep_latency";
2676 costly_str = "no_dep_costly";
2679 case all_deps_costly:
2680 costly_str = "all_deps_costly";
2683 case true_store_to_load_dep_costly:
2684 costly_str = "true_store_to_load_dep_costly";
2687 case store_to_load_dep_costly:
2688 costly_str = "store_to_load_dep_costly";
2692 costly_str = costly_num;
2693 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2697 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2699 switch (rs6000_sched_insert_nops)
2701 case sched_finish_regroup_exact:
2702 nop_str = "sched_finish_regroup_exact";
2705 case sched_finish_pad_groups:
2706 nop_str = "sched_finish_pad_groups";
2709 case sched_finish_none:
2710 nop_str = "sched_finish_none";
2715 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2719 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2721 switch (rs6000_sdata)
2728 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2732 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2736 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2741 switch (rs6000_traceback)
2743 case traceback_default: trace_str = "default"; break;
2744 case traceback_none: trace_str = "none"; break;
2745 case traceback_part: trace_str = "part"; break;
2746 case traceback_full: trace_str = "full"; break;
2747 default: trace_str = "unknown"; break;
2750 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2752 switch (rs6000_current_cmodel)
2754 case CMODEL_SMALL: cmodel_str = "small"; break;
2755 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2756 case CMODEL_LARGE: cmodel_str = "large"; break;
2757 default: cmodel_str = "unknown"; break;
2760 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2762 switch (rs6000_current_abi)
2764 case ABI_NONE: abi_str = "none"; break;
2765 case ABI_AIX: abi_str = "aix"; break;
2766 case ABI_ELFv2: abi_str = "ELFv2"; break;
2767 case ABI_V4: abi_str = "V4"; break;
2768 case ABI_DARWIN: abi_str = "darwin"; break;
2769 default: abi_str = "unknown"; break;
2772 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2774 if (rs6000_altivec_abi)
2775 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2777 if (rs6000_darwin64_abi)
2778 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2780 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2781 (TARGET_SOFT_FLOAT ? "true" : "false"));
2783 if (TARGET_LINK_STACK)
2784 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2786 if (TARGET_P8_FUSION)
2790 strcpy (options, "power8");
2791 if (TARGET_P8_FUSION_SIGN)
2792 strcat (options, ", sign");
2794 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2797 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2798 TARGET_SECURE_PLT ? "secure" : "bss");
2799 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2800 aix_struct_return ? "aix" : "sysv");
2801 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2802 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2803 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2804 tf[!!rs6000_align_branch_targets]);
2805 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2806 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2807 rs6000_long_double_type_size);
2808 if (rs6000_long_double_type_size > 64)
2810 fprintf (stderr, DEBUG_FMT_S, "long double type",
2811 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2812 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2813 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2815 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2816 (int)rs6000_sched_restricted_insns_priority);
2817 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2819 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2820 (int)RS6000_BUILTIN_COUNT);
2822 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2823 (int)TARGET_FLOAT128_ENABLE_TYPE);
2826 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2827 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2829 if (TARGET_DIRECT_MOVE_128)
2830 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2831 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2835 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2836 legitimate address support to figure out the appropriate addressing to
2840 rs6000_setup_reg_addr_masks (void)
2842 ssize_t rc, reg, m, nregs;
2843 addr_mask_type any_addr_mask, addr_mask;
2845 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2847 machine_mode m2 = (machine_mode) m;
2848 bool complex_p = false;
2849 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2852 if (COMPLEX_MODE_P (m2))
2855 m2 = GET_MODE_INNER (m2);
2858 msize = GET_MODE_SIZE (m2);
2860 /* SDmode is special in that we want to access it only via REG+REG
2861 addressing on power7 and above, since we want to use the LFIWZX and
2862 STFIWZX instructions to load it. */
2863 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2866 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2869 reg = reload_reg_map[rc].reg;
2871 /* Can mode values go in the GPR/FPR/Altivec registers? */
2872 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2874 bool small_int_vsx_p = (small_int_p
2875 && (rc == RELOAD_REG_FPR
2876 || rc == RELOAD_REG_VMX));
2878 nregs = rs6000_hard_regno_nregs[m][reg];
2879 addr_mask |= RELOAD_REG_VALID;
2881 /* Indicate if the mode takes more than 1 physical register. If
2882 it takes a single register, indicate it can do REG+REG
2883 addressing. Small integers in VSX registers can only do
2884 REG+REG addressing. */
2885 if (small_int_vsx_p)
2886 addr_mask |= RELOAD_REG_INDEXED;
2887 else if (nregs > 1 || m == BLKmode || complex_p)
2888 addr_mask |= RELOAD_REG_MULTIPLE;
2890 addr_mask |= RELOAD_REG_INDEXED;
2892 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2893 addressing. If we allow scalars into Altivec registers,
2894 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2896 For VSX systems, we don't allow update addressing for
2897 DFmode/SFmode if those registers can go in both the
2898 traditional floating point registers and Altivec registers.
2899 The load/store instructions for the Altivec registers do not
2900 have update forms. If we allowed update addressing, it seems
2901 to break IV-OPT code using floating point if the index type is
2902 int instead of long (PR target/81550 and target/84042). */
2905 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2907 && !VECTOR_MODE_P (m2)
2908 && !FLOAT128_VECTOR_P (m2)
2910 && (m != E_DFmode || !TARGET_VSX)
2911 && (m != E_SFmode || !TARGET_P8_VECTOR)
2912 && !small_int_vsx_p)
2914 addr_mask |= RELOAD_REG_PRE_INCDEC;
2916 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2917 we don't allow PRE_MODIFY for some multi-register
2922 addr_mask |= RELOAD_REG_PRE_MODIFY;
2926 if (TARGET_POWERPC64)
2927 addr_mask |= RELOAD_REG_PRE_MODIFY;
2932 if (TARGET_HARD_FLOAT)
2933 addr_mask |= RELOAD_REG_PRE_MODIFY;
2939 /* GPR and FPR registers can do REG+OFFSET addressing, except
2940 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2941 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2942 if ((addr_mask != 0) && !indexed_only_p
2944 && (rc == RELOAD_REG_GPR
2945 || ((msize == 8 || m2 == SFmode)
2946 && (rc == RELOAD_REG_FPR
2947 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
2948 addr_mask |= RELOAD_REG_OFFSET;
2950 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2951 instructions are enabled. The offset for 128-bit VSX registers is
2952 only 12-bits. While GPRs can handle the full offset range, VSX
2953 registers can only handle the restricted range. */
2954 else if ((addr_mask != 0) && !indexed_only_p
2955 && msize == 16 && TARGET_P9_VECTOR
2956 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
2957 || (m2 == TImode && TARGET_VSX)))
2959 addr_mask |= RELOAD_REG_OFFSET;
2960 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
2961 addr_mask |= RELOAD_REG_QUAD_OFFSET;
2964 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2965 addressing on 128-bit types. */
2966 if (rc == RELOAD_REG_VMX && msize == 16
2967 && (addr_mask & RELOAD_REG_VALID) != 0)
2968 addr_mask |= RELOAD_REG_AND_M16;
2970 reg_addr[m].addr_mask[rc] = addr_mask;
2971 any_addr_mask |= addr_mask;
2974 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
2979 /* Initialize the various global tables that are based on register size. */
2981 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2987 /* Precalculate REGNO_REG_CLASS. */
2988 rs6000_regno_regclass[0] = GENERAL_REGS;
2989 for (r = 1; r < 32; ++r)
2990 rs6000_regno_regclass[r] = BASE_REGS;
2992 for (r = 32; r < 64; ++r)
2993 rs6000_regno_regclass[r] = FLOAT_REGS;
2995 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
2996 rs6000_regno_regclass[r] = NO_REGS;
2998 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2999 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3001 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3002 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3003 rs6000_regno_regclass[r] = CR_REGS;
3005 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3006 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3007 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3008 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3009 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3010 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3011 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3012 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3013 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3014 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3016 /* Precalculate register class to simpler reload register class. We don't
3017 need all of the register classes that are combinations of different
3018 classes, just the simple ones that have constraint letters. */
3019 for (c = 0; c < N_REG_CLASSES; c++)
3020 reg_class_to_reg_type[c] = NO_REG_TYPE;
3022 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3023 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3024 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3025 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3026 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3027 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3028 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3029 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3030 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3031 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3035 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3036 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3040 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3041 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3044 /* Precalculate the valid memory formats as well as the vector information,
3045 this must be set up before the rs6000_hard_regno_nregs_internal calls
3047 gcc_assert ((int)VECTOR_NONE == 0);
3048 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3049 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3051 gcc_assert ((int)CODE_FOR_nothing == 0);
3052 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3054 gcc_assert ((int)NO_REGS == 0);
3055 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3057 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3058 believes it can use native alignment or still uses 128-bit alignment. */
3059 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3070 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3071 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3072 if (TARGET_FLOAT128_TYPE)
3074 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3075 rs6000_vector_align[KFmode] = 128;
3077 if (FLOAT128_IEEE_P (TFmode))
3079 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3080 rs6000_vector_align[TFmode] = 128;
3084 /* V2DF mode, VSX only. */
3087 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3088 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3089 rs6000_vector_align[V2DFmode] = align64;
3092 /* V4SF mode, either VSX or Altivec. */
3095 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3096 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3097 rs6000_vector_align[V4SFmode] = align32;
3099 else if (TARGET_ALTIVEC)
3101 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3102 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3103 rs6000_vector_align[V4SFmode] = align32;
3106 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3110 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3111 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3112 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3113 rs6000_vector_align[V4SImode] = align32;
3114 rs6000_vector_align[V8HImode] = align32;
3115 rs6000_vector_align[V16QImode] = align32;
3119 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3120 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3121 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3125 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3126 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3127 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3131 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3132 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3135 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3136 rs6000_vector_unit[V2DImode]
3137 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3138 rs6000_vector_align[V2DImode] = align64;
3140 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3141 rs6000_vector_unit[V1TImode]
3142 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3143 rs6000_vector_align[V1TImode] = 128;
3146 /* DFmode, see if we want to use the VSX unit. Memory is handled
3147 differently, so don't set rs6000_vector_mem. */
3150 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3151 rs6000_vector_align[DFmode] = 64;
3154 /* SFmode, see if we want to use the VSX unit. */
3155 if (TARGET_P8_VECTOR)
3157 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3158 rs6000_vector_align[SFmode] = 32;
3161 /* Allow TImode in VSX register and set the VSX memory macros. */
3164 rs6000_vector_mem[TImode] = VECTOR_VSX;
3165 rs6000_vector_align[TImode] = align64;
3168 /* Register class constraints for the constraints that depend on compile
3169 switches. When the VSX code was added, different constraints were added
3170 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3171 of the VSX registers are used. The register classes for scalar floating
3172 point types is set, based on whether we allow that type into the upper
3173 (Altivec) registers. GCC has register classes to target the Altivec
3174 registers for load/store operations, to select using a VSX memory
3175 operation instead of the traditional floating point operation. The
3178 d - Register class to use with traditional DFmode instructions.
3179 f - Register class to use with traditional SFmode instructions.
3180 v - Altivec register.
3181 wa - Any VSX register.
3182 wc - Reserved to represent individual CR bits (used in LLVM).
3183 wd - Preferred register class for V2DFmode.
3184 wf - Preferred register class for V4SFmode.
3185 wg - Float register for power6x move insns.
3186 wh - FP register for direct move instructions.
3187 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3188 wj - FP or VSX register to hold 64-bit integers for direct moves.
3189 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3190 wl - Float register if we can do 32-bit signed int loads.
3191 wm - VSX register for ISA 2.07 direct move operations.
3192 wn - always NO_REGS.
3193 wr - GPR if 64-bit mode is permitted.
3194 ws - Register class to do ISA 2.06 DF operations.
3195 wt - VSX register for TImode in VSX registers.
3196 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3197 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3198 ww - Register class to do SF conversions in with VSX operations.
3199 wx - Float register if we can do 32-bit int stores.
3200 wy - Register class to do ISA 2.07 SF operations.
3201 wz - Float register if we can do 32-bit unsigned int loads.
3202 wH - Altivec register if SImode is allowed in VSX registers.
3203 wI - VSX register if SImode is allowed in VSX registers.
3204 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3205 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3207 if (TARGET_HARD_FLOAT)
3209 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3210 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3215 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3216 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3217 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3218 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3219 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3220 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3221 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3224 /* Add conditional constraints based on various options, to allow us to
3225 collapse multiple insn patterns. */
3227 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3229 if (TARGET_MFPGPR) /* DFmode */
3230 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3233 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3235 if (TARGET_DIRECT_MOVE)
3237 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3238 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3239 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3240 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3241 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3242 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3245 if (TARGET_POWERPC64)
3247 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3248 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3251 if (TARGET_P8_VECTOR) /* SFmode */
3253 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3254 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3255 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3257 else if (TARGET_VSX)
3258 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3261 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3264 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3266 if (TARGET_FLOAT128_TYPE)
3268 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3269 if (FLOAT128_IEEE_P (TFmode))
3270 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3273 if (TARGET_P9_VECTOR)
3275 /* Support for new D-form instructions. */
3276 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3278 /* Support for ISA 3.0 (power9) vectors. */
3279 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3282 /* Support for new direct moves (ISA 3.0 + 64bit). */
3283 if (TARGET_DIRECT_MOVE_128)
3284 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3286 /* Support small integers in VSX registers. */
3287 if (TARGET_P8_VECTOR)
3289 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3290 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3291 if (TARGET_P9_VECTOR)
3293 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3294 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3298 /* Set up the reload helper and direct move functions. */
3299 if (TARGET_VSX || TARGET_ALTIVEC)
3303 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3304 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3305 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3306 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3307 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3308 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3309 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3310 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3311 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3312 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3313 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3314 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3315 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3316 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3317 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3318 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3319 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3320 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3321 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3322 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3324 if (FLOAT128_VECTOR_P (KFmode))
3326 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3327 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3330 if (FLOAT128_VECTOR_P (TFmode))
3332 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3333 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3336 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3338 if (TARGET_NO_SDMODE_STACK)
3340 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3341 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3346 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3347 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3350 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3352 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3353 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3354 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3355 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3356 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3357 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3358 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3359 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3360 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3362 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3363 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3364 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3365 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3366 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3367 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3368 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3369 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3370 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3372 if (FLOAT128_VECTOR_P (KFmode))
3374 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3375 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3378 if (FLOAT128_VECTOR_P (TFmode))
3380 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3381 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3387 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3388 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3389 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3390 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3391 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3392 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3393 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3394 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3395 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3396 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3397 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3398 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3399 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3400 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3401 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3402 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3403 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3404 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3405 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3406 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3408 if (FLOAT128_VECTOR_P (KFmode))
3410 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3411 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3414 if (FLOAT128_IEEE_P (TFmode))
3416 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3417 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3420 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3422 if (TARGET_NO_SDMODE_STACK)
3424 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3425 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3430 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3431 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3434 if (TARGET_DIRECT_MOVE)
3436 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3437 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3438 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3442 reg_addr[DFmode].scalar_in_vmx_p = true;
3443 reg_addr[DImode].scalar_in_vmx_p = true;
3445 if (TARGET_P8_VECTOR)
3447 reg_addr[SFmode].scalar_in_vmx_p = true;
3448 reg_addr[SImode].scalar_in_vmx_p = true;
3450 if (TARGET_P9_VECTOR)
3452 reg_addr[HImode].scalar_in_vmx_p = true;
3453 reg_addr[QImode].scalar_in_vmx_p = true;
3458 /* Precalculate HARD_REGNO_NREGS. */
3459 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3460 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3461 rs6000_hard_regno_nregs[m][r]
3462 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3464 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3465 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3466 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3467 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3468 rs6000_hard_regno_mode_ok_p[m][r] = true;
3470 /* Precalculate CLASS_MAX_NREGS sizes. */
3471 for (c = 0; c < LIM_REG_CLASSES; ++c)
3475 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3476 reg_size = UNITS_PER_VSX_WORD;
3478 else if (c == ALTIVEC_REGS)
3479 reg_size = UNITS_PER_ALTIVEC_WORD;
3481 else if (c == FLOAT_REGS)
3482 reg_size = UNITS_PER_FP_WORD;
3485 reg_size = UNITS_PER_WORD;
3487 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3489 machine_mode m2 = (machine_mode)m;
3490 int reg_size2 = reg_size;
3492 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3494 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3495 reg_size2 = UNITS_PER_FP_WORD;
3497 rs6000_class_max_nregs[m][c]
3498 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3502 /* Calculate which modes to automatically generate code to use a the
3503 reciprocal divide and square root instructions. In the future, possibly
3504 automatically generate the instructions even if the user did not specify
3505 -mrecip. The older machines double precision reciprocal sqrt estimate is
3506 not accurate enough. */
3507 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3509 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3511 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3512 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3513 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3514 if (VECTOR_UNIT_VSX_P (V2DFmode))
3515 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3517 if (TARGET_FRSQRTES)
3518 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3520 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3521 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3522 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3523 if (VECTOR_UNIT_VSX_P (V2DFmode))
3524 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3526 if (rs6000_recip_control)
3528 if (!flag_finite_math_only)
3529 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3531 if (flag_trapping_math)
3532 warning (0, "%qs requires %qs or %qs", "-mrecip",
3533 "-fno-trapping-math", "-ffast-math");
3534 if (!flag_reciprocal_math)
3535 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3537 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3539 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3540 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3541 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3543 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3544 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3545 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3547 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3548 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3549 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3551 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3552 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3553 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3555 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3556 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3557 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3559 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3560 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3561 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3563 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3564 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3565 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3567 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3568 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3569 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3573 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3574 legitimate address support to figure out the appropriate addressing to
3576 rs6000_setup_reg_addr_masks ();
3578 if (global_init_p || TARGET_DEBUG_TARGET)
3580 if (TARGET_DEBUG_REG)
3581 rs6000_debug_reg_global ();
3583 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3585 "SImode variable mult cost = %d\n"
3586 "SImode constant mult cost = %d\n"
3587 "SImode short constant mult cost = %d\n"
3588 "DImode multipliciation cost = %d\n"
3589 "SImode division cost = %d\n"
3590 "DImode division cost = %d\n"
3591 "Simple fp operation cost = %d\n"
3592 "DFmode multiplication cost = %d\n"
3593 "SFmode division cost = %d\n"
3594 "DFmode division cost = %d\n"
3595 "cache line size = %d\n"
3596 "l1 cache size = %d\n"
3597 "l2 cache size = %d\n"
3598 "simultaneous prefetches = %d\n"
3601 rs6000_cost->mulsi_const,
3602 rs6000_cost->mulsi_const9,
3610 rs6000_cost->cache_line_size,
3611 rs6000_cost->l1_cache_size,
3612 rs6000_cost->l2_cache_size,
3613 rs6000_cost->simultaneous_prefetches);
3618 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3621 darwin_rs6000_override_options (void)
3623 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3625 rs6000_altivec_abi = 1;
3626 TARGET_ALTIVEC_VRSAVE = 1;
3627 rs6000_current_abi = ABI_DARWIN;
3629 if (DEFAULT_ABI == ABI_DARWIN
3631 darwin_one_byte_bool = 1;
3633 if (TARGET_64BIT && ! TARGET_POWERPC64)
3635 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3636 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3640 rs6000_default_long_calls = 1;
3641 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3644 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3646 if (!flag_mkernel && !flag_apple_kext
3648 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3649 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3651 /* Unless the user (not the configurer) has explicitly overridden
3652 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3653 G4 unless targeting the kernel. */
3656 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3657 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3658 && ! global_options_set.x_rs6000_cpu_index)
3660 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3665 /* If not otherwise specified by a target, make 'long double' equivalent to
3668 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3669 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3672 /* Return the builtin mask of the various options used that could affect which
3673 builtins were used. In the past we used target_flags, but we've run out of
3674 bits, and some options are no longer in target_flags. */
3677 rs6000_builtin_mask_calculate (void)
3679 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3680 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3681 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3682 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3683 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3684 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3685 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3686 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3687 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3688 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3689 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3690 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3691 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3692 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3693 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3694 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3695 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3696 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3697 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3698 | ((TARGET_LONG_DOUBLE_128
3699 && TARGET_HARD_FLOAT
3700 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3701 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3702 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3705 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3706 to clobber the XER[CA] bit because clobbering that bit without telling
3707 the compiler worked just fine with versions of GCC before GCC 5, and
3708 breaking a lot of older code in ways that are hard to track down is
3709 not such a great idea. */
3712 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3713 vec<const char *> &/*constraints*/,
3714 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3716 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3717 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3721 /* Override command line options.
3723 Combine build-specific configuration information with options
3724 specified on the command line to set various state variables which
3725 influence code generation, optimization, and expansion of built-in
3726 functions. Assure that command-line configuration preferences are
3727 compatible with each other and with the build configuration; issue
3728 warnings while adjusting configuration or error messages while
3729 rejecting configuration.
3731 Upon entry to this function:
3733 This function is called once at the beginning of
3734 compilation, and then again at the start and end of compiling
3735 each section of code that has a different configuration, as
3736 indicated, for example, by adding the
3738 __attribute__((__target__("cpu=power9")))
3740 qualifier to a function definition or, for example, by bracketing
3743 #pragma GCC target("altivec")
3747 #pragma GCC reset_options
3749 directives. Parameter global_init_p is true for the initial
3750 invocation, which initializes global variables, and false for all
3751 subsequent invocations.
3754 Various global state information is assumed to be valid. This
3755 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3756 default CPU specified at build configure time, TARGET_DEFAULT,
3757 representing the default set of option flags for the default
3758 target, and global_options_set.x_rs6000_isa_flags, representing
3759 which options were requested on the command line.
3761 Upon return from this function:
3763 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3764 was set by name on the command line. Additionally, if certain
3765 attributes are automatically enabled or disabled by this function
3766 in order to assure compatibility between options and
3767 configuration, the flags associated with those attributes are
3768 also set. By setting these "explicit bits", we avoid the risk
3769 that other code might accidentally overwrite these particular
3770 attributes with "default values".
3772 The various bits of rs6000_isa_flags are set to indicate the
3773 target options that have been selected for the most current
3774 compilation efforts. This has the effect of also turning on the
3775 associated TARGET_XXX values since these are macros which are
3776 generally defined to test the corresponding bit of the
3777 rs6000_isa_flags variable.
3779 The variable rs6000_builtin_mask is set to represent the target
3780 options for the most current compilation efforts, consistent with
3781 the current contents of rs6000_isa_flags. This variable controls
3782 expansion of built-in functions.
3784 Various other global variables and fields of global structures
3785 (over 50 in all) are initialized to reflect the desired options
3786 for the most current compilation efforts. */
3789 rs6000_option_override_internal (bool global_init_p)
3793 HOST_WIDE_INT set_masks;
3794 HOST_WIDE_INT ignore_masks;
3797 struct cl_target_option *main_target_opt
3798 = ((global_init_p || target_option_default_node == NULL)
3799 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
3801 /* Print defaults. */
3802 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
3803 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
3805 /* Remember the explicit arguments. */
3807 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
3809 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3810 library functions, so warn about it. The flag may be useful for
3811 performance studies from time to time though, so don't disable it
3813 if (global_options_set.x_rs6000_alignment_flags
3814 && rs6000_alignment_flags == MASK_ALIGN_POWER
3815 && DEFAULT_ABI == ABI_DARWIN
3817 warning (0, "%qs is not supported for 64-bit Darwin;"
3818 " it is incompatible with the installed C and C++ libraries",
3821 /* Numerous experiment shows that IRA based loop pressure
3822 calculation works better for RTL loop invariant motion on targets
3823 with enough (>= 32) registers. It is an expensive optimization.
3824 So it is on only for peak performance. */
3825 if (optimize >= 3 && global_init_p
3826 && !global_options_set.x_flag_ira_loop_pressure)
3827 flag_ira_loop_pressure = 1;
3829 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3830 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3831 options were already specified. */
3832 if (flag_sanitize & SANITIZE_USER_ADDRESS
3833 && !global_options_set.x_flag_asynchronous_unwind_tables)
3834 flag_asynchronous_unwind_tables = 1;
3836 /* Set the pointer size. */
3839 rs6000_pmode = DImode;
3840 rs6000_pointer_size = 64;
3844 rs6000_pmode = SImode;
3845 rs6000_pointer_size = 32;
3848 /* Some OSs don't support saving the high part of 64-bit registers on context
3849 switch. Other OSs don't support saving Altivec registers. On those OSs,
3850 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3851 if the user wants either, the user must explicitly specify them and we
3852 won't interfere with the user's specification. */
3854 set_masks = POWERPC_MASKS;
3855 #ifdef OS_MISSING_POWERPC64
3856 if (OS_MISSING_POWERPC64)
3857 set_masks &= ~OPTION_MASK_POWERPC64;
3859 #ifdef OS_MISSING_ALTIVEC
3860 if (OS_MISSING_ALTIVEC)
3861 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
3862 | OTHER_VSX_VECTOR_MASKS);
3865 /* Don't override by the processor default if given explicitly. */
3866 set_masks &= ~rs6000_isa_flags_explicit;
3868 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3869 the cpu in a target attribute or pragma, but did not specify a tuning
3870 option, use the cpu for the tuning option rather than the option specified
3871 with -mtune on the command line. Process a '--with-cpu' configuration
3872 request as an implicit --cpu. */
3873 if (rs6000_cpu_index >= 0)
3874 cpu_index = rs6000_cpu_index;
3875 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
3876 cpu_index = main_target_opt->x_rs6000_cpu_index;
3877 else if (OPTION_TARGET_CPU_DEFAULT)
3878 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
3880 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3881 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3882 with those from the cpu, except for options that were explicitly set. If
3883 we don't have a cpu, do not override the target bits set in
3887 rs6000_cpu_index = cpu_index;
3888 rs6000_isa_flags &= ~set_masks;
3889 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3894 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3895 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3896 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3897 to using rs6000_isa_flags, we need to do the initialization here.
3899 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3900 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3901 HOST_WIDE_INT flags;
3903 flags = TARGET_DEFAULT;
3906 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3907 const char *default_cpu = (!TARGET_POWERPC64
3912 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
3913 flags = processor_target_table[default_cpu_index].target_enable;
3915 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
3918 if (rs6000_tune_index >= 0)
3919 tune_index = rs6000_tune_index;
3920 else if (cpu_index >= 0)
3921 rs6000_tune_index = tune_index = cpu_index;
3925 enum processor_type tune_proc
3926 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
3929 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
3930 if (processor_target_table[i].processor == tune_proc)
3938 rs6000_cpu = processor_target_table[cpu_index].processor;
3940 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
3942 gcc_assert (tune_index >= 0);
3943 rs6000_tune = processor_target_table[tune_index].processor;
3945 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
3946 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
3947 || rs6000_cpu == PROCESSOR_PPCE5500)
3950 error ("AltiVec not supported in this target");
3953 /* If we are optimizing big endian systems for space, use the load/store
3954 multiple instructions. */
3955 if (BYTES_BIG_ENDIAN && optimize_size)
3956 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
3958 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3959 because the hardware doesn't support the instructions used in little
3960 endian mode, and causes an alignment trap. The 750 does not cause an
3961 alignment trap (except when the target is unaligned). */
3963 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
3965 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
3966 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
3967 warning (0, "%qs is not supported on little endian systems",
3971 /* If little-endian, default to -mstrict-align on older processors.
3972 Testing for htm matches power8 and later. */
3973 if (!BYTES_BIG_ENDIAN
3974 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
3975 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
3977 if (!rs6000_fold_gimple)
3979 "gimple folding of rs6000 builtins has been disabled.\n");
3981 /* Add some warnings for VSX. */
3984 const char *msg = NULL;
3985 if (!TARGET_HARD_FLOAT)
3987 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3988 msg = N_("-mvsx requires hardware floating point");
3991 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3992 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3995 else if (TARGET_AVOID_XFORM > 0)
3996 msg = N_("-mvsx needs indexed addressing");
3997 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
3998 & OPTION_MASK_ALTIVEC))
4000 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4001 msg = N_("-mvsx and -mno-altivec are incompatible");
4003 msg = N_("-mno-altivec disables vsx");
4009 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4010 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4014 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4015 the -mcpu setting to enable options that conflict. */
4016 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4017 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4018 | OPTION_MASK_ALTIVEC
4019 | OPTION_MASK_VSX)) != 0)
4020 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4021 | OPTION_MASK_DIRECT_MOVE)
4022 & ~rs6000_isa_flags_explicit);
4024 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4025 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4027 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4028 off all of the options that depend on those flags. */
4029 ignore_masks = rs6000_disable_incompatible_switches ();
4031 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4032 unless the user explicitly used the -mno-<option> to disable the code. */
4033 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4034 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4035 else if (TARGET_P9_MINMAX)
4039 if (cpu_index == PROCESSOR_POWER9)
4041 /* legacy behavior: allow -mcpu=power9 with certain
4042 capabilities explicitly disabled. */
4043 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4046 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4047 "for <xxx> less than power9", "-mcpu");
4049 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4050 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4051 & rs6000_isa_flags_explicit))
4052 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4053 were explicitly cleared. */
4054 error ("%qs incompatible with explicitly disabled options",
4057 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4059 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4060 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4061 else if (TARGET_VSX)
4062 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4063 else if (TARGET_POPCNTD)
4064 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4065 else if (TARGET_DFP)
4066 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4067 else if (TARGET_CMPB)
4068 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4069 else if (TARGET_FPRND)
4070 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4071 else if (TARGET_POPCNTB)
4072 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4073 else if (TARGET_ALTIVEC)
4074 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4076 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4078 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4079 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4080 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4083 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4085 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4086 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4087 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4090 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4092 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4093 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4094 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4097 if (TARGET_P8_VECTOR && !TARGET_VSX)
4099 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4100 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4101 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4102 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4104 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4105 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4106 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4110 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4112 rs6000_isa_flags |= OPTION_MASK_VSX;
4113 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4117 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4119 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4120 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4121 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4124 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4125 silently turn off quad memory mode. */
4126 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4128 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4129 warning (0, N_("-mquad-memory requires 64-bit mode"));
4131 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4132 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4134 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4135 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4138 /* Non-atomic quad memory load/store are disabled for little endian, since
4139 the words are reversed, but atomic operations can still be done by
4140 swapping the words. */
4141 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4143 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4144 warning (0, N_("-mquad-memory is not available in little endian "
4147 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4150 /* Assume if the user asked for normal quad memory instructions, they want
4151 the atomic versions as well, unless they explicity told us not to use quad
4152 word atomic instructions. */
4153 if (TARGET_QUAD_MEMORY
4154 && !TARGET_QUAD_MEMORY_ATOMIC
4155 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4156 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4158 /* If we can shrink-wrap the TOC register save separately, then use
4159 -msave-toc-indirect unless explicitly disabled. */
4160 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4161 && flag_shrink_wrap_separate
4162 && optimize_function_for_speed_p (cfun))
4163 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4165 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4166 generating power8 instructions. Power9 does not optimize power8 fusion
4168 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4170 if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
4171 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4173 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4176 /* Setting additional fusion flags turns on base fusion. */
4177 if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
4179 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4181 if (TARGET_P8_FUSION_SIGN)
4182 error ("%qs requires %qs", "-mpower8-fusion-sign",
4185 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4188 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4191 /* Power8 does not fuse sign extended loads with the addis. If we are
4192 optimizing at high levels for speed, convert a sign extended load into a
4193 zero extending load, and an explicit sign extension. */
4194 if (TARGET_P8_FUSION
4195 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4196 && optimize_function_for_speed_p (cfun)
4198 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4200 /* ISA 3.0 vector instructions include ISA 2.07. */
4201 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4203 /* We prefer to not mention undocumented options in
4204 error messages. However, if users have managed to select
4205 power9-vector without selecting power8-vector, they
4206 already know about undocumented flags. */
4207 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4208 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4209 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4210 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4212 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4213 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4214 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4218 /* OPTION_MASK_P9_VECTOR is explicit and
4219 OPTION_MASK_P8_VECTOR is not explicit. */
4220 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4221 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4225 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4226 support. If we only have ISA 2.06 support, and the user did not specify
4227 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4228 but we don't enable the full vectorization support */
4229 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4230 TARGET_ALLOW_MOVMISALIGN = 1;
4232 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4234 if (TARGET_ALLOW_MOVMISALIGN > 0
4235 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4236 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4238 TARGET_ALLOW_MOVMISALIGN = 0;
4241 /* Determine when unaligned vector accesses are permitted, and when
4242 they are preferred over masked Altivec loads. Note that if
4243 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4244 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4246 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4250 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4251 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4253 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4256 else if (!TARGET_ALLOW_MOVMISALIGN)
4258 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4259 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4260 "-mallow-movmisalign");
4262 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4266 /* Use long double size to select the appropriate long double. We use
4267 TYPE_PRECISION to differentiate the 3 different long double types. We map
4268 128 into the precision used for TFmode. */
4269 int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
4271 : FLOAT_PRECISION_TFmode);
4273 /* Set long double size before the IEEE 128-bit tests. */
4274 if (!global_options_set.x_rs6000_long_double_type_size)
4276 if (main_target_opt != NULL
4277 && (main_target_opt->x_rs6000_long_double_type_size
4278 != default_long_double_size))
4279 error ("target attribute or pragma changes long double size");
4281 rs6000_long_double_type_size = default_long_double_size;
4283 else if (rs6000_long_double_type_size == 128)
4284 rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
4286 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4287 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4288 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4289 those systems will not pick up this default. Warn if the user changes the
4290 default unless -Wno-psabi. */
4291 if (!global_options_set.x_rs6000_ieeequad)
4292 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4294 else if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4296 static bool warned_change_long_double;
4297 if (!warned_change_long_double)
4299 warned_change_long_double = true;
4300 if (TARGET_IEEEQUAD)
4301 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4303 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4307 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4308 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4309 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4310 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4311 the keyword as well as the type. */
4312 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4314 /* IEEE 128-bit floating point requires VSX support. */
4315 if (TARGET_FLOAT128_KEYWORD)
4319 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4320 error ("%qs requires VSX support", "-mfloat128");
4322 TARGET_FLOAT128_TYPE = 0;
4323 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4324 | OPTION_MASK_FLOAT128_HW);
4326 else if (!TARGET_FLOAT128_TYPE)
4328 TARGET_FLOAT128_TYPE = 1;
4329 warning (0, "The -mfloat128 option may not be fully supported");
4333 /* Enable the __float128 keyword under Linux by default. */
4334 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4335 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4336 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4338 /* If we have are supporting the float128 type and full ISA 3.0 support,
4339 enable -mfloat128-hardware by default. However, don't enable the
4340 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4341 because sometimes the compiler wants to put things in an integer
4342 container, and if we don't have __int128 support, it is impossible. */
4343 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4344 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4345 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4346 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4348 if (TARGET_FLOAT128_HW
4349 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4351 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4352 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4354 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4357 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4359 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4360 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4362 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4365 /* Print the options after updating the defaults. */
4366 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4367 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4369 /* E500mc does "better" if we inline more aggressively. Respect the
4370 user's opinion, though. */
4371 if (rs6000_block_move_inline_limit == 0
4372 && (rs6000_tune == PROCESSOR_PPCE500MC
4373 || rs6000_tune == PROCESSOR_PPCE500MC64
4374 || rs6000_tune == PROCESSOR_PPCE5500
4375 || rs6000_tune == PROCESSOR_PPCE6500))
4376 rs6000_block_move_inline_limit = 128;
4378 /* store_one_arg depends on expand_block_move to handle at least the
4379 size of reg_parm_stack_space. */
4380 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4381 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4385 /* If the appropriate debug option is enabled, replace the target hooks
4386 with debug versions that call the real version and then prints
4387 debugging information. */
4388 if (TARGET_DEBUG_COST)
4390 targetm.rtx_costs = rs6000_debug_rtx_costs;
4391 targetm.address_cost = rs6000_debug_address_cost;
4392 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4395 if (TARGET_DEBUG_ADDR)
4397 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4398 targetm.legitimize_address = rs6000_debug_legitimize_address;
4399 rs6000_secondary_reload_class_ptr
4400 = rs6000_debug_secondary_reload_class;
4401 targetm.secondary_memory_needed
4402 = rs6000_debug_secondary_memory_needed;
4403 targetm.can_change_mode_class
4404 = rs6000_debug_can_change_mode_class;
4405 rs6000_preferred_reload_class_ptr
4406 = rs6000_debug_preferred_reload_class;
4407 rs6000_legitimize_reload_address_ptr
4408 = rs6000_debug_legitimize_reload_address;
4409 rs6000_mode_dependent_address_ptr
4410 = rs6000_debug_mode_dependent_address;
4413 if (rs6000_veclibabi_name)
4415 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4416 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4419 error ("unknown vectorization library ABI type (%qs) for "
4420 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4426 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4427 target attribute or pragma which automatically enables both options,
4428 unless the altivec ABI was set. This is set by default for 64-bit, but
4430 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4432 TARGET_FLOAT128_TYPE = 0;
4433 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4434 | OPTION_MASK_FLOAT128_KEYWORD)
4435 & ~rs6000_isa_flags_explicit);
4438 /* Enable Altivec ABI for AIX -maltivec. */
4439 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4441 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4442 error ("target attribute or pragma changes AltiVec ABI");
4444 rs6000_altivec_abi = 1;
4447 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4448 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4449 be explicitly overridden in either case. */
4452 if (!global_options_set.x_rs6000_altivec_abi
4453 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4455 if (main_target_opt != NULL &&
4456 !main_target_opt->x_rs6000_altivec_abi)
4457 error ("target attribute or pragma changes AltiVec ABI");
4459 rs6000_altivec_abi = 1;
4463 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4464 So far, the only darwin64 targets are also MACH-O. */
4466 && DEFAULT_ABI == ABI_DARWIN
4469 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4470 error ("target attribute or pragma changes darwin64 ABI");
4473 rs6000_darwin64_abi = 1;
4474 /* Default to natural alignment, for better performance. */
4475 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4479 /* Place FP constants in the constant pool instead of TOC
4480 if section anchors enabled. */
4481 if (flag_section_anchors
4482 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4483 TARGET_NO_FP_IN_TOC = 1;
4485 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4486 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4488 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4489 SUBTARGET_OVERRIDE_OPTIONS;
4491 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4492 SUBSUBTARGET_OVERRIDE_OPTIONS;
4494 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4495 SUB3TARGET_OVERRIDE_OPTIONS;
4498 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4499 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4501 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4502 && rs6000_tune != PROCESSOR_POWER5
4503 && rs6000_tune != PROCESSOR_POWER6
4504 && rs6000_tune != PROCESSOR_POWER7
4505 && rs6000_tune != PROCESSOR_POWER8
4506 && rs6000_tune != PROCESSOR_POWER9
4507 && rs6000_tune != PROCESSOR_PPCA2
4508 && rs6000_tune != PROCESSOR_CELL
4509 && rs6000_tune != PROCESSOR_PPC476);
4510 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4511 || rs6000_tune == PROCESSOR_POWER5
4512 || rs6000_tune == PROCESSOR_POWER7
4513 || rs6000_tune == PROCESSOR_POWER8);
4514 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4515 || rs6000_tune == PROCESSOR_POWER5
4516 || rs6000_tune == PROCESSOR_POWER6
4517 || rs6000_tune == PROCESSOR_POWER7
4518 || rs6000_tune == PROCESSOR_POWER8
4519 || rs6000_tune == PROCESSOR_POWER9
4520 || rs6000_tune == PROCESSOR_PPCE500MC
4521 || rs6000_tune == PROCESSOR_PPCE500MC64
4522 || rs6000_tune == PROCESSOR_PPCE5500
4523 || rs6000_tune == PROCESSOR_PPCE6500);
4525 /* Allow debug switches to override the above settings. These are set to -1
4526 in rs6000.opt to indicate the user hasn't directly set the switch. */
4527 if (TARGET_ALWAYS_HINT >= 0)
4528 rs6000_always_hint = TARGET_ALWAYS_HINT;
4530 if (TARGET_SCHED_GROUPS >= 0)
4531 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4533 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4534 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4536 rs6000_sched_restricted_insns_priority
4537 = (rs6000_sched_groups ? 1 : 0);
4539 /* Handle -msched-costly-dep option. */
4540 rs6000_sched_costly_dep
4541 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4543 if (rs6000_sched_costly_dep_str)
4545 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4546 rs6000_sched_costly_dep = no_dep_costly;
4547 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4548 rs6000_sched_costly_dep = all_deps_costly;
4549 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4550 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4551 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4552 rs6000_sched_costly_dep = store_to_load_dep_costly;
4554 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4555 atoi (rs6000_sched_costly_dep_str));
4558 /* Handle -minsert-sched-nops option. */
4559 rs6000_sched_insert_nops
4560 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4562 if (rs6000_sched_insert_nops_str)
4564 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4565 rs6000_sched_insert_nops = sched_finish_none;
4566 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4567 rs6000_sched_insert_nops = sched_finish_pad_groups;
4568 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4569 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4571 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4572 atoi (rs6000_sched_insert_nops_str));
4575 /* Handle stack protector */
4576 if (!global_options_set.x_rs6000_stack_protector_guard)
4577 #ifdef TARGET_THREAD_SSP_OFFSET
4578 rs6000_stack_protector_guard = SSP_TLS;
4580 rs6000_stack_protector_guard = SSP_GLOBAL;
4583 #ifdef TARGET_THREAD_SSP_OFFSET
4584 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4585 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4588 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4591 const char *str = rs6000_stack_protector_guard_offset_str;
4594 long offset = strtol (str, &endp, 0);
4595 if (!*str || *endp || errno)
4596 error ("%qs is not a valid number in %qs", str,
4597 "-mstack-protector-guard-offset=");
4599 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4600 || (TARGET_64BIT && (offset & 3)))
4601 error ("%qs is not a valid offset in %qs", str,
4602 "-mstack-protector-guard-offset=");
4604 rs6000_stack_protector_guard_offset = offset;
4607 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4609 const char *str = rs6000_stack_protector_guard_reg_str;
4610 int reg = decode_reg_name (str);
4612 if (!IN_RANGE (reg, 1, 31))
4613 error ("%qs is not a valid base register in %qs", str,
4614 "-mstack-protector-guard-reg=");
4616 rs6000_stack_protector_guard_reg = reg;
4619 if (rs6000_stack_protector_guard == SSP_TLS
4620 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4621 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4625 #ifdef TARGET_REGNAMES
4626 /* If the user desires alternate register names, copy in the
4627 alternate names now. */
4628 if (TARGET_REGNAMES)
4629 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4632 /* Set aix_struct_return last, after the ABI is determined.
4633 If -maix-struct-return or -msvr4-struct-return was explicitly
4634 used, don't override with the ABI default. */
4635 if (!global_options_set.x_aix_struct_return)
4636 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4639 /* IBM XL compiler defaults to unsigned bitfields. */
4640 if (TARGET_XL_COMPAT)
4641 flag_signed_bitfields = 0;
4644 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4645 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4647 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4649 /* We can only guarantee the availability of DI pseudo-ops when
4650 assembling for 64-bit targets. */
4653 targetm.asm_out.aligned_op.di = NULL;
4654 targetm.asm_out.unaligned_op.di = NULL;
4658 /* Set branch target alignment, if not optimizing for size. */
4661 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4662 aligned 8byte to avoid misprediction by the branch predictor. */
4663 if (rs6000_tune == PROCESSOR_TITAN
4664 || rs6000_tune == PROCESSOR_CELL)
4666 if (flag_align_functions && !str_align_functions)
4667 str_align_functions = "8";
4668 if (flag_align_jumps && !str_align_jumps)
4669 str_align_jumps = "8";
4670 if (flag_align_loops && !str_align_loops)
4671 str_align_loops = "8";
4673 if (rs6000_align_branch_targets)
4675 if (flag_align_functions && !str_align_functions)
4676 str_align_functions = "16";
4677 if (flag_align_jumps && !str_align_jumps)
4678 str_align_jumps = "16";
4679 if (flag_align_loops && !str_align_loops)
4681 can_override_loop_align = 1;
4682 str_align_loops = "16";
4686 if (flag_align_jumps && !str_align_jumps)
4687 str_align_jumps = "16";
4688 if (flag_align_loops && !str_align_loops)
4689 str_align_loops = "16";
4692 /* Arrange to save and restore machine status around nested functions. */
4693 init_machine_status = rs6000_init_machine_status;
4695 /* We should always be splitting complex arguments, but we can't break
4696 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4697 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4698 targetm.calls.split_complex_arg = NULL;
4700 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4701 if (DEFAULT_ABI == ABI_AIX)
4702 targetm.calls.custom_function_descriptors = 0;
4705 /* Initialize rs6000_cost with the appropriate target costs. */
4707 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4709 switch (rs6000_tune)
4711 case PROCESSOR_RS64A:
4712 rs6000_cost = &rs64a_cost;
4715 case PROCESSOR_MPCCORE:
4716 rs6000_cost = &mpccore_cost;
4719 case PROCESSOR_PPC403:
4720 rs6000_cost = &ppc403_cost;
4723 case PROCESSOR_PPC405:
4724 rs6000_cost = &ppc405_cost;
4727 case PROCESSOR_PPC440:
4728 rs6000_cost = &ppc440_cost;
4731 case PROCESSOR_PPC476:
4732 rs6000_cost = &ppc476_cost;
4735 case PROCESSOR_PPC601:
4736 rs6000_cost = &ppc601_cost;
4739 case PROCESSOR_PPC603:
4740 rs6000_cost = &ppc603_cost;
4743 case PROCESSOR_PPC604:
4744 rs6000_cost = &ppc604_cost;
4747 case PROCESSOR_PPC604e:
4748 rs6000_cost = &ppc604e_cost;
4751 case PROCESSOR_PPC620:
4752 rs6000_cost = &ppc620_cost;
4755 case PROCESSOR_PPC630:
4756 rs6000_cost = &ppc630_cost;
4759 case PROCESSOR_CELL:
4760 rs6000_cost = &ppccell_cost;
4763 case PROCESSOR_PPC750:
4764 case PROCESSOR_PPC7400:
4765 rs6000_cost = &ppc750_cost;
4768 case PROCESSOR_PPC7450:
4769 rs6000_cost = &ppc7450_cost;
4772 case PROCESSOR_PPC8540:
4773 case PROCESSOR_PPC8548:
4774 rs6000_cost = &ppc8540_cost;
4777 case PROCESSOR_PPCE300C2:
4778 case PROCESSOR_PPCE300C3:
4779 rs6000_cost = &ppce300c2c3_cost;
4782 case PROCESSOR_PPCE500MC:
4783 rs6000_cost = &ppce500mc_cost;
4786 case PROCESSOR_PPCE500MC64:
4787 rs6000_cost = &ppce500mc64_cost;
4790 case PROCESSOR_PPCE5500:
4791 rs6000_cost = &ppce5500_cost;
4794 case PROCESSOR_PPCE6500:
4795 rs6000_cost = &ppce6500_cost;
4798 case PROCESSOR_TITAN:
4799 rs6000_cost = &titan_cost;
4802 case PROCESSOR_POWER4:
4803 case PROCESSOR_POWER5:
4804 rs6000_cost = &power4_cost;
4807 case PROCESSOR_POWER6:
4808 rs6000_cost = &power6_cost;
4811 case PROCESSOR_POWER7:
4812 rs6000_cost = &power7_cost;
4815 case PROCESSOR_POWER8:
4816 rs6000_cost = &power8_cost;
4819 case PROCESSOR_POWER9:
4820 rs6000_cost = &power9_cost;
4823 case PROCESSOR_PPCA2:
4824 rs6000_cost = &ppca2_cost;
4833 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
4834 rs6000_cost->simultaneous_prefetches,
4835 global_options.x_param_values,
4836 global_options_set.x_param_values);
4837 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
4838 global_options.x_param_values,
4839 global_options_set.x_param_values);
4840 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
4841 rs6000_cost->cache_line_size,
4842 global_options.x_param_values,
4843 global_options_set.x_param_values);
4844 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
4845 global_options.x_param_values,
4846 global_options_set.x_param_values);
4848 /* Increase loop peeling limits based on performance analysis. */
4849 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
4850 global_options.x_param_values,
4851 global_options_set.x_param_values);
4852 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
4853 global_options.x_param_values,
4854 global_options_set.x_param_values);
4856 /* Use the 'model' -fsched-pressure algorithm by default. */
4857 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
4858 SCHED_PRESSURE_MODEL,
4859 global_options.x_param_values,
4860 global_options_set.x_param_values);
4862 /* If using typedef char *va_list, signal that
4863 __builtin_va_start (&ap, 0) can be optimized to
4864 ap = __builtin_next_arg (0). */
4865 if (DEFAULT_ABI != ABI_V4)
4866 targetm.expand_builtin_va_start = NULL;
4869 /* If not explicitly specified via option, decide whether to generate indexed
4870 load/store instructions. A value of -1 indicates that the
4871 initial value of this variable has not been overwritten. During
4872 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4873 if (TARGET_AVOID_XFORM == -1)
4874 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4875 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4876 need indexed accesses and the type used is the scalar type of the element
4877 being loaded or stored. */
4878 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
4879 && !TARGET_ALTIVEC);
4881 /* Set the -mrecip options. */
4882 if (rs6000_recip_name)
4884 char *p = ASTRDUP (rs6000_recip_name);
4886 unsigned int mask, i;
4889 while ((q = strtok (p, ",")) != NULL)
4900 if (!strcmp (q, "default"))
4901 mask = ((TARGET_RECIP_PRECISION)
4902 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
4905 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
4906 if (!strcmp (q, recip_options[i].string))
4908 mask = recip_options[i].mask;
4912 if (i == ARRAY_SIZE (recip_options))
4914 error ("unknown option for %<%s=%s%>", "-mrecip", q);
4922 rs6000_recip_control &= ~mask;
4924 rs6000_recip_control |= mask;
4928 /* Set the builtin mask of the various options used that could affect which
4929 builtins were used. In the past we used target_flags, but we've run out
4930 of bits, and some options are no longer in target_flags. */
4931 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
4932 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
4933 rs6000_print_builtin_options (stderr, 0, "builtin mask",
4934 rs6000_builtin_mask);
4936 /* Initialize all of the registers. */
4937 rs6000_init_hard_regno_mode_ok (global_init_p);
4939 /* Save the initial options in case the user does function specific options */
4941 target_option_default_node = target_option_current_node
4942 = build_target_option_node (&global_options);
4944 /* If not explicitly specified via option, decide whether to generate the
4945 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4946 if (TARGET_LINK_STACK == -1)
4947 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
4949 /* Deprecate use of -mno-speculate-indirect-jumps. */
4950 if (!rs6000_speculate_indirect_jumps)
4951 warning (0, "%qs is deprecated and not recommended in any circumstances",
4952 "-mno-speculate-indirect-jumps");
4957 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4958 define the target cpu type. */
4961 rs6000_option_override (void)
4963 (void) rs6000_option_override_internal (true);
4967 /* Implement targetm.vectorize.builtin_mask_for_load. */
4969 rs6000_builtin_mask_for_load (void)
4971 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4972 if ((TARGET_ALTIVEC && !TARGET_VSX)
4973 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
4974 return altivec_builtin_mask_for_load;
4979 /* Implement LOOP_ALIGN. */
4981 rs6000_loop_align (rtx label)
4986 /* Don't override loop alignment if -falign-loops was specified. */
4987 if (!can_override_loop_align)
4990 bb = BLOCK_FOR_INSN (label);
4991 ninsns = num_loop_insns(bb->loop_father);
4993 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4994 if (ninsns > 4 && ninsns <= 8
4995 && (rs6000_tune == PROCESSOR_POWER4
4996 || rs6000_tune == PROCESSOR_POWER5
4997 || rs6000_tune == PROCESSOR_POWER6
4998 || rs6000_tune == PROCESSOR_POWER7
4999 || rs6000_tune == PROCESSOR_POWER8))
5000 return align_flags (5);
5005 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5006 after applying N number of iterations. This routine does not determine
5007 how may iterations are required to reach desired alignment. */
5010 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5017 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5020 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5030 /* Assuming that all other types are naturally aligned. CHECKME! */
5035 /* Return true if the vector misalignment factor is supported by the
5038 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5045 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5048 /* Return if movmisalign pattern is not supported for this mode. */
5049 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5052 if (misalignment == -1)
5054 /* Misalignment factor is unknown at compile time but we know
5055 it's word aligned. */
5056 if (rs6000_vector_alignment_reachable (type, is_packed))
5058 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5060 if (element_size == 64 || element_size == 32)
5067 /* VSX supports word-aligned vector. */
5068 if (misalignment % 4 == 0)
5074 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5076 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5077 tree vectype, int misalign)
5082 switch (type_of_cost)
5092 case cond_branch_not_taken:
5101 case vec_promote_demote:
5107 case cond_branch_taken:
5110 case unaligned_load:
5111 case vector_gather_load:
5112 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5115 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5117 elements = TYPE_VECTOR_SUBPARTS (vectype);
5119 /* Double word aligned. */
5127 /* Double word aligned. */
5131 /* Unknown misalignment. */
5144 /* Misaligned loads are not supported. */
5149 case unaligned_store:
5150 case vector_scatter_store:
5151 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5154 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5156 elements = TYPE_VECTOR_SUBPARTS (vectype);
5158 /* Double word aligned. */
5166 /* Double word aligned. */
5170 /* Unknown misalignment. */
5183 /* Misaligned stores are not supported. */
5189 /* This is a rough approximation assuming non-constant elements
5190 constructed into a vector via element insertion. FIXME:
5191 vec_construct is not granular enough for uniformly good
5192 decisions. If the initialization is a splat, this is
5193 cheaper than we estimate. Improve this someday. */
5194 elem_type = TREE_TYPE (vectype);
5195 /* 32-bit vectors loaded into registers are stored as double
5196 precision, so we need 2 permutes, 2 converts, and 1 merge
5197 to construct a vector of short floats from them. */
5198 if (SCALAR_FLOAT_TYPE_P (elem_type)
5199 && TYPE_PRECISION (elem_type) == 32)
5201 /* On POWER9, integer vector types are built up in GPRs and then
5202 use a direct move (2 cycles). For POWER8 this is even worse,
5203 as we need two direct moves and a merge, and the direct moves
5205 else if (INTEGRAL_TYPE_P (elem_type))
5207 if (TARGET_P9_VECTOR)
5208 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5210 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5213 /* V2DFmode doesn't need a direct move. */
5221 /* Implement targetm.vectorize.preferred_simd_mode. */
5224 rs6000_preferred_simd_mode (scalar_mode mode)
5233 if (TARGET_ALTIVEC || TARGET_VSX)
5253 typedef struct _rs6000_cost_data
5255 struct loop *loop_info;
5259 /* Test for likely overcommitment of vector hardware resources. If a
5260 loop iteration is relatively large, and too large a percentage of
5261 instructions in the loop are vectorized, the cost model may not
5262 adequately reflect delays from unavailable vector resources.
5263 Penalize the loop body cost for this case. */
5266 rs6000_density_test (rs6000_cost_data *data)
5268 const int DENSITY_PCT_THRESHOLD = 85;
5269 const int DENSITY_SIZE_THRESHOLD = 70;
5270 const int DENSITY_PENALTY = 10;
5271 struct loop *loop = data->loop_info;
5272 basic_block *bbs = get_loop_body (loop);
5273 int nbbs = loop->num_nodes;
5274 loop_vec_info loop_vinfo = loop_vec_info_for_loop (data->loop_info);
5275 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5278 for (i = 0; i < nbbs; i++)
5280 basic_block bb = bbs[i];
5281 gimple_stmt_iterator gsi;
5283 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5285 gimple *stmt = gsi_stmt (gsi);
5286 stmt_vec_info stmt_info = loop_vinfo->lookup_stmt (stmt);
5288 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5289 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5295 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5297 if (density_pct > DENSITY_PCT_THRESHOLD
5298 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5300 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5301 if (dump_enabled_p ())
5302 dump_printf_loc (MSG_NOTE, vect_location,
5303 "density %d%%, cost %d exceeds threshold, penalizing "
5304 "loop body cost by %d%%", density_pct,
5305 vec_cost + not_vec_cost, DENSITY_PENALTY);
5309 /* Implement targetm.vectorize.init_cost. */
5311 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5312 instruction is needed by the vectorization. */
5313 static bool rs6000_vect_nonmem;
5316 rs6000_init_cost (struct loop *loop_info)
5318 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5319 data->loop_info = loop_info;
5320 data->cost[vect_prologue] = 0;
5321 data->cost[vect_body] = 0;
5322 data->cost[vect_epilogue] = 0;
5323 rs6000_vect_nonmem = false;
5327 /* Implement targetm.vectorize.add_stmt_cost. */
5330 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5331 struct _stmt_vec_info *stmt_info, int misalign,
5332 enum vect_cost_model_location where)
5334 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5335 unsigned retval = 0;
5337 if (flag_vect_cost_model)
5339 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5340 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5342 /* Statements in an inner loop relative to the loop being
5343 vectorized are weighted more heavily. The value here is
5344 arbitrary and could potentially be improved with analysis. */
5345 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5346 count *= 50; /* FIXME. */
5348 retval = (unsigned) (count * stmt_cost);
5349 cost_data->cost[where] += retval;
5351 /* Check whether we're doing something other than just a copy loop.
5352 Not all such loops may be profitably vectorized; see
5353 rs6000_finish_cost. */
5354 if ((kind == vec_to_scalar || kind == vec_perm
5355 || kind == vec_promote_demote || kind == vec_construct
5356 || kind == scalar_to_vec)
5357 || (where == vect_body && kind == vector_stmt))
5358 rs6000_vect_nonmem = true;
5364 /* Implement targetm.vectorize.finish_cost. */
5367 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5368 unsigned *body_cost, unsigned *epilogue_cost)
5370 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5372 if (cost_data->loop_info)
5373 rs6000_density_test (cost_data);
5375 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5376 that require versioning for any reason. The vectorization is at
5377 best a wash inside the loop, and the versioning checks make
5378 profitability highly unlikely and potentially quite harmful. */
5379 if (cost_data->loop_info)
5381 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5382 if (!rs6000_vect_nonmem
5383 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5384 && LOOP_REQUIRES_VERSIONING (vec_info))
5385 cost_data->cost[vect_body] += 10000;
5388 *prologue_cost = cost_data->cost[vect_prologue];
5389 *body_cost = cost_data->cost[vect_body];
5390 *epilogue_cost = cost_data->cost[vect_epilogue];
5393 /* Implement targetm.vectorize.destroy_cost_data. */
5396 rs6000_destroy_cost_data (void *data)
5401 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5402 library with vectorized intrinsics. */
5405 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5409 const char *suffix = NULL;
5410 tree fntype, new_fndecl, bdecl = NULL_TREE;
5413 machine_mode el_mode, in_mode;
5416 /* Libmass is suitable for unsafe math only as it does not correctly support
5417 parts of IEEE with the required precision such as denormals. Only support
5418 it if we have VSX to use the simd d2 or f4 functions.
5419 XXX: Add variable length support. */
5420 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5423 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5424 n = TYPE_VECTOR_SUBPARTS (type_out);
5425 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5426 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5427 if (el_mode != in_mode
5463 if (el_mode == DFmode && n == 2)
5465 bdecl = mathfn_built_in (double_type_node, fn);
5466 suffix = "d2"; /* pow -> powd2 */
5468 else if (el_mode == SFmode && n == 4)
5470 bdecl = mathfn_built_in (float_type_node, fn);
5471 suffix = "4"; /* powf -> powf4 */
5483 gcc_assert (suffix != NULL);
5484 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5488 strcpy (name, bname + sizeof ("__builtin_") - 1);
5489 strcat (name, suffix);
5492 fntype = build_function_type_list (type_out, type_in, NULL);
5493 else if (n_args == 2)
5494 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5498 /* Build a function declaration for the vectorized function. */
5499 new_fndecl = build_decl (BUILTINS_LOCATION,
5500 FUNCTION_DECL, get_identifier (name), fntype);
5501 TREE_PUBLIC (new_fndecl) = 1;
5502 DECL_EXTERNAL (new_fndecl) = 1;
5503 DECL_IS_NOVOPS (new_fndecl) = 1;
5504 TREE_READONLY (new_fndecl) = 1;
5509 /* Returns a function decl for a vectorized version of the builtin function
5510 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5511 if it is not available. */
5514 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5517 machine_mode in_mode, out_mode;
5520 if (TARGET_DEBUG_BUILTIN)
5521 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5522 combined_fn_name (combined_fn (fn)),
5523 GET_MODE_NAME (TYPE_MODE (type_out)),
5524 GET_MODE_NAME (TYPE_MODE (type_in)));
5526 if (TREE_CODE (type_out) != VECTOR_TYPE
5527 || TREE_CODE (type_in) != VECTOR_TYPE)
5530 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5531 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5532 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5533 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5538 if (VECTOR_UNIT_VSX_P (V2DFmode)
5539 && out_mode == DFmode && out_n == 2
5540 && in_mode == DFmode && in_n == 2)
5541 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5542 if (VECTOR_UNIT_VSX_P (V4SFmode)
5543 && out_mode == SFmode && out_n == 4
5544 && in_mode == SFmode && in_n == 4)
5545 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5546 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5547 && out_mode == SFmode && out_n == 4
5548 && in_mode == SFmode && in_n == 4)
5549 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5552 if (VECTOR_UNIT_VSX_P (V2DFmode)
5553 && out_mode == DFmode && out_n == 2
5554 && in_mode == DFmode && in_n == 2)
5555 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5556 if (VECTOR_UNIT_VSX_P (V4SFmode)
5557 && out_mode == SFmode && out_n == 4
5558 && in_mode == SFmode && in_n == 4)
5559 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5560 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5561 && out_mode == SFmode && out_n == 4
5562 && in_mode == SFmode && in_n == 4)
5563 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5566 if (VECTOR_UNIT_VSX_P (V2DFmode)
5567 && out_mode == DFmode && out_n == 2
5568 && in_mode == DFmode && in_n == 2)
5569 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5570 if (VECTOR_UNIT_VSX_P (V4SFmode)
5571 && out_mode == SFmode && out_n == 4
5572 && in_mode == SFmode && in_n == 4)
5573 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5574 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5575 && out_mode == SFmode && out_n == 4
5576 && in_mode == SFmode && in_n == 4)
5577 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5580 if (VECTOR_UNIT_VSX_P (V2DFmode)
5581 && out_mode == DFmode && out_n == 2
5582 && in_mode == DFmode && in_n == 2)
5583 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5584 if (VECTOR_UNIT_VSX_P (V4SFmode)
5585 && out_mode == SFmode && out_n == 4
5586 && in_mode == SFmode && in_n == 4)
5587 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5588 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5589 && out_mode == SFmode && out_n == 4
5590 && in_mode == SFmode && in_n == 4)
5591 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5594 if (VECTOR_UNIT_VSX_P (V2DFmode)
5595 && out_mode == DFmode && out_n == 2
5596 && in_mode == DFmode && in_n == 2)
5597 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5598 if (VECTOR_UNIT_VSX_P (V4SFmode)
5599 && out_mode == SFmode && out_n == 4
5600 && in_mode == SFmode && in_n == 4)
5601 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5602 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5603 && out_mode == SFmode && out_n == 4
5604 && in_mode == SFmode && in_n == 4)
5605 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5608 if (VECTOR_UNIT_VSX_P (V2DFmode)
5609 && flag_unsafe_math_optimizations
5610 && out_mode == DFmode && out_n == 2
5611 && in_mode == DFmode && in_n == 2)
5612 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5613 if (VECTOR_UNIT_VSX_P (V4SFmode)
5614 && flag_unsafe_math_optimizations
5615 && out_mode == SFmode && out_n == 4
5616 && in_mode == SFmode && in_n == 4)
5617 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5620 if (VECTOR_UNIT_VSX_P (V2DFmode)
5621 && !flag_trapping_math
5622 && out_mode == DFmode && out_n == 2
5623 && in_mode == DFmode && in_n == 2)
5624 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5625 if (VECTOR_UNIT_VSX_P (V4SFmode)
5626 && !flag_trapping_math
5627 && out_mode == SFmode && out_n == 4
5628 && in_mode == SFmode && in_n == 4)
5629 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5635 /* Generate calls to libmass if appropriate. */
5636 if (rs6000_veclib_handler)
5637 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5642 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5645 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5648 machine_mode in_mode, out_mode;
5651 if (TARGET_DEBUG_BUILTIN)
5652 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5653 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5654 GET_MODE_NAME (TYPE_MODE (type_out)),
5655 GET_MODE_NAME (TYPE_MODE (type_in)));
5657 if (TREE_CODE (type_out) != VECTOR_TYPE
5658 || TREE_CODE (type_in) != VECTOR_TYPE)
5661 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5662 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5663 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5664 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5666 enum rs6000_builtins fn
5667 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5670 case RS6000_BUILTIN_RSQRTF:
5671 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5672 && out_mode == SFmode && out_n == 4
5673 && in_mode == SFmode && in_n == 4)
5674 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5676 case RS6000_BUILTIN_RSQRT:
5677 if (VECTOR_UNIT_VSX_P (V2DFmode)
5678 && out_mode == DFmode && out_n == 2
5679 && in_mode == DFmode && in_n == 2)
5680 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5682 case RS6000_BUILTIN_RECIPF:
5683 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5684 && out_mode == SFmode && out_n == 4
5685 && in_mode == SFmode && in_n == 4)
5686 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5688 case RS6000_BUILTIN_RECIP:
5689 if (VECTOR_UNIT_VSX_P (V2DFmode)
5690 && out_mode == DFmode && out_n == 2
5691 && in_mode == DFmode && in_n == 2)
5692 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5700 /* Default CPU string for rs6000*_file_start functions. */
5701 static const char *rs6000_default_cpu;
5703 /* Do anything needed at the start of the asm file. */
5706 rs6000_file_start (void)
5709 const char *start = buffer;
5710 FILE *file = asm_out_file;
5712 rs6000_default_cpu = TARGET_CPU_DEFAULT;
5714 default_file_start ();
5716 if (flag_verbose_asm)
5718 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
5720 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
5722 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
5726 if (global_options_set.x_rs6000_cpu_index)
5728 fprintf (file, "%s -mcpu=%s", start,
5729 processor_target_table[rs6000_cpu_index].name);
5733 if (global_options_set.x_rs6000_tune_index)
5735 fprintf (file, "%s -mtune=%s", start,
5736 processor_target_table[rs6000_tune_index].name);
5740 if (PPC405_ERRATUM77)
5742 fprintf (file, "%s PPC405CR_ERRATUM77", start);
5746 #ifdef USING_ELFOS_H
5747 switch (rs6000_sdata)
5749 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
5750 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
5751 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
5752 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
5755 if (rs6000_sdata && g_switch_value)
5757 fprintf (file, "%s -G %d", start,
5767 #ifdef USING_ELFOS_H
5768 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
5769 && !global_options_set.x_rs6000_cpu_index)
5771 fputs ("\t.machine ", asm_out_file);
5772 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
5773 fputs ("power9\n", asm_out_file);
5774 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
5775 fputs ("power8\n", asm_out_file);
5776 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
5777 fputs ("power7\n", asm_out_file);
5778 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
5779 fputs ("power6\n", asm_out_file);
5780 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
5781 fputs ("power5\n", asm_out_file);
5782 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
5783 fputs ("power4\n", asm_out_file);
5784 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
5785 fputs ("ppc64\n", asm_out_file);
5787 fputs ("ppc\n", asm_out_file);
5791 if (DEFAULT_ABI == ABI_ELFv2)
5792 fprintf (file, "\t.abiversion 2\n");
5796 /* Return nonzero if this function is known to have a null epilogue. */
5799 direct_return (void)
5801 if (reload_completed)
5803 rs6000_stack_t *info = rs6000_stack_info ();
5805 if (info->first_gp_reg_save == 32
5806 && info->first_fp_reg_save == 64
5807 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
5808 && ! info->lr_save_p
5809 && ! info->cr_save_p
5810 && info->vrsave_size == 0
5818 /* Return the number of instructions it takes to form a constant in an
5819 integer register. */
5822 num_insns_constant_wide (HOST_WIDE_INT value)
5824 /* signed constant loadable with addi */
5825 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
5828 /* constant loadable with addis */
5829 else if ((value & 0xffff) == 0
5830 && (value >> 31 == -1 || value >> 31 == 0))
5833 else if (TARGET_POWERPC64)
5835 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
5836 HOST_WIDE_INT high = value >> 31;
5838 if (high == 0 || high == -1)
5844 return num_insns_constant_wide (high) + 1;
5846 return num_insns_constant_wide (low) + 1;
5848 return (num_insns_constant_wide (high)
5849 + num_insns_constant_wide (low) + 1);
5857 num_insns_constant (rtx op, machine_mode mode)
5859 HOST_WIDE_INT low, high;
5861 switch (GET_CODE (op))
5864 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
5865 && rs6000_is_valid_and_mask (op, mode))
5868 return num_insns_constant_wide (INTVAL (op));
5870 case CONST_WIDE_INT:
5873 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
5874 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
5875 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
5880 if (mode == SFmode || mode == SDmode)
5884 if (DECIMAL_FLOAT_MODE_P (mode))
5885 REAL_VALUE_TO_TARGET_DECIMAL32
5886 (*CONST_DOUBLE_REAL_VALUE (op), l);
5888 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
5889 return num_insns_constant_wide ((HOST_WIDE_INT) l);
5893 if (DECIMAL_FLOAT_MODE_P (mode))
5894 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
5896 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
5897 high = l[WORDS_BIG_ENDIAN == 0];
5898 low = l[WORDS_BIG_ENDIAN != 0];
5901 return (num_insns_constant_wide (low)
5902 + num_insns_constant_wide (high));
5905 if ((high == 0 && low >= 0)
5906 || (high == -1 && low < 0))
5907 return num_insns_constant_wide (low);
5909 else if (rs6000_is_valid_and_mask (op, mode))
5913 return num_insns_constant_wide (high) + 1;
5916 return (num_insns_constant_wide (high)
5917 + num_insns_constant_wide (low) + 1);
5925 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5926 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5927 corresponding element of the vector, but for V4SFmode, the
5928 corresponding "float" is interpreted as an SImode integer. */
5931 const_vector_elt_as_int (rtx op, unsigned int elt)
5935 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5936 gcc_assert (GET_MODE (op) != V2DImode
5937 && GET_MODE (op) != V2DFmode);
5939 tmp = CONST_VECTOR_ELT (op, elt);
5940 if (GET_MODE (op) == V4SFmode)
5941 tmp = gen_lowpart (SImode, tmp);
5942 return INTVAL (tmp);
5945 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5946 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5947 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5948 all items are set to the same value and contain COPIES replicas of the
5949 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5950 operand and the others are set to the value of the operand's msb. */
5953 vspltis_constant (rtx op, unsigned step, unsigned copies)
5955 machine_mode mode = GET_MODE (op);
5956 machine_mode inner = GET_MODE_INNER (mode);
5964 HOST_WIDE_INT splat_val;
5965 HOST_WIDE_INT msb_val;
5967 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
5970 nunits = GET_MODE_NUNITS (mode);
5971 bitsize = GET_MODE_BITSIZE (inner);
5972 mask = GET_MODE_MASK (inner);
5974 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5976 msb_val = val >= 0 ? 0 : -1;
5978 /* Construct the value to be splatted, if possible. If not, return 0. */
5979 for (i = 2; i <= copies; i *= 2)
5981 HOST_WIDE_INT small_val;
5983 small_val = splat_val >> bitsize;
5985 if (splat_val != ((HOST_WIDE_INT)
5986 ((unsigned HOST_WIDE_INT) small_val << bitsize)
5987 | (small_val & mask)))
5989 splat_val = small_val;
5992 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5993 if (EASY_VECTOR_15 (splat_val))
5996 /* Also check if we can splat, and then add the result to itself. Do so if
5997 the value is positive, of if the splat instruction is using OP's mode;
5998 for splat_val < 0, the splat and the add should use the same mode. */
5999 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6000 && (splat_val >= 0 || (step == 1 && copies == 1)))
6003 /* Also check if are loading up the most significant bit which can be done by
6004 loading up -1 and shifting the value left by -1. */
6005 else if (EASY_VECTOR_MSB (splat_val, inner))
6011 /* Check if VAL is present in every STEP-th element, and the
6012 other elements are filled with its most significant bit. */
6013 for (i = 1; i < nunits; ++i)
6015 HOST_WIDE_INT desired_val;
6016 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6017 if ((i & (step - 1)) == 0)
6020 desired_val = msb_val;
6022 if (desired_val != const_vector_elt_as_int (op, elt))
6029 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6030 instruction, filling in the bottom elements with 0 or -1.
6032 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6033 for the number of zeroes to shift in, or negative for the number of 0xff
6036 OP is a CONST_VECTOR. */
6039 vspltis_shifted (rtx op)
6041 machine_mode mode = GET_MODE (op);
6042 machine_mode inner = GET_MODE_INNER (mode);
6050 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6053 /* We need to create pseudo registers to do the shift, so don't recognize
6054 shift vector constants after reload. */
6055 if (!can_create_pseudo_p ())
6058 nunits = GET_MODE_NUNITS (mode);
6059 mask = GET_MODE_MASK (inner);
6061 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6063 /* Check if the value can really be the operand of a vspltis[bhw]. */
6064 if (EASY_VECTOR_15 (val))
6067 /* Also check if we are loading up the most significant bit which can be done
6068 by loading up -1 and shifting the value left by -1. */
6069 else if (EASY_VECTOR_MSB (val, inner))
6075 /* Check if VAL is present in every STEP-th element until we find elements
6076 that are 0 or all 1 bits. */
6077 for (i = 1; i < nunits; ++i)
6079 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6080 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6082 /* If the value isn't the splat value, check for the remaining elements
6088 for (j = i+1; j < nunits; ++j)
6090 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6091 if (const_vector_elt_as_int (op, elt2) != 0)
6095 return (nunits - i) * GET_MODE_SIZE (inner);
6098 else if ((elt_val & mask) == mask)
6100 for (j = i+1; j < nunits; ++j)
6102 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6103 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6107 return -((nunits - i) * GET_MODE_SIZE (inner));
6115 /* If all elements are equal, we don't need to do VLSDOI. */
6120 /* Return true if OP is of the given MODE and can be synthesized
6121 with a vspltisb, vspltish or vspltisw. */
6124 easy_altivec_constant (rtx op, machine_mode mode)
6126 unsigned step, copies;
6128 if (mode == VOIDmode)
6129 mode = GET_MODE (op);
6130 else if (mode != GET_MODE (op))
6133 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6135 if (mode == V2DFmode)
6136 return zero_constant (op, mode);
6138 else if (mode == V2DImode)
6140 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6141 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6144 if (zero_constant (op, mode))
6147 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6148 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6154 /* V1TImode is a special container for TImode. Ignore for now. */
6155 else if (mode == V1TImode)
6158 /* Start with a vspltisw. */
6159 step = GET_MODE_NUNITS (mode) / 4;
6162 if (vspltis_constant (op, step, copies))
6165 /* Then try with a vspltish. */
6171 if (vspltis_constant (op, step, copies))
6174 /* And finally a vspltisb. */
6180 if (vspltis_constant (op, step, copies))
6183 if (vspltis_shifted (op) != 0)
6189 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6190 result is OP. Abort if it is not possible. */
6193 gen_easy_altivec_constant (rtx op)
6195 machine_mode mode = GET_MODE (op);
6196 int nunits = GET_MODE_NUNITS (mode);
6197 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6198 unsigned step = nunits / 4;
6199 unsigned copies = 1;
6201 /* Start with a vspltisw. */
6202 if (vspltis_constant (op, step, copies))
6203 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6205 /* Then try with a vspltish. */
6211 if (vspltis_constant (op, step, copies))
6212 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6214 /* And finally a vspltisb. */
6220 if (vspltis_constant (op, step, copies))
6221 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6226 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6227 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6229 Return the number of instructions needed (1 or 2) into the address pointed
6232 Return the constant that is being split via CONSTANT_PTR. */
6235 xxspltib_constant_p (rtx op,
6240 size_t nunits = GET_MODE_NUNITS (mode);
6242 HOST_WIDE_INT value;
6245 /* Set the returned values to out of bound values. */
6246 *num_insns_ptr = -1;
6247 *constant_ptr = 256;
6249 if (!TARGET_P9_VECTOR)
6252 if (mode == VOIDmode)
6253 mode = GET_MODE (op);
6255 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6258 /* Handle (vec_duplicate <constant>). */
6259 if (GET_CODE (op) == VEC_DUPLICATE)
6261 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6262 && mode != V2DImode)
6265 element = XEXP (op, 0);
6266 if (!CONST_INT_P (element))
6269 value = INTVAL (element);
6270 if (!IN_RANGE (value, -128, 127))
6274 /* Handle (const_vector [...]). */
6275 else if (GET_CODE (op) == CONST_VECTOR)
6277 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6278 && mode != V2DImode)
6281 element = CONST_VECTOR_ELT (op, 0);
6282 if (!CONST_INT_P (element))
6285 value = INTVAL (element);
6286 if (!IN_RANGE (value, -128, 127))
6289 for (i = 1; i < nunits; i++)
6291 element = CONST_VECTOR_ELT (op, i);
6292 if (!CONST_INT_P (element))
6295 if (value != INTVAL (element))
6300 /* Handle integer constants being loaded into the upper part of the VSX
6301 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6302 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6303 else if (CONST_INT_P (op))
6305 if (!SCALAR_INT_MODE_P (mode))
6308 value = INTVAL (op);
6309 if (!IN_RANGE (value, -128, 127))
6312 if (!IN_RANGE (value, -1, 0))
6314 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6317 if (EASY_VECTOR_15 (value))
6325 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6326 sign extend. Special case 0/-1 to allow getting any VSX register instead
6327 of an Altivec register. */
6328 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6329 && EASY_VECTOR_15 (value))
6332 /* Return # of instructions and the constant byte for XXSPLTIB. */
6333 if (mode == V16QImode)
6336 else if (IN_RANGE (value, -1, 0))
6342 *constant_ptr = (int) value;
6347 output_vec_const_move (rtx *operands)
6355 mode = GET_MODE (dest);
6359 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6360 int xxspltib_value = 256;
6363 if (zero_constant (vec, mode))
6365 if (TARGET_P9_VECTOR)
6366 return "xxspltib %x0,0";
6368 else if (dest_vmx_p)
6369 return "vspltisw %0,0";
6372 return "xxlxor %x0,%x0,%x0";
6375 if (all_ones_constant (vec, mode))
6377 if (TARGET_P9_VECTOR)
6378 return "xxspltib %x0,255";
6380 else if (dest_vmx_p)
6381 return "vspltisw %0,-1";
6383 else if (TARGET_P8_VECTOR)
6384 return "xxlorc %x0,%x0,%x0";
6390 if (TARGET_P9_VECTOR
6391 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6395 operands[2] = GEN_INT (xxspltib_value & 0xff);
6396 return "xxspltib %x0,%2";
6407 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6408 if (zero_constant (vec, mode))
6409 return "vspltisw %0,0";
6411 if (all_ones_constant (vec, mode))
6412 return "vspltisw %0,-1";
6414 /* Do we need to construct a value using VSLDOI? */
6415 shift = vspltis_shifted (vec);
6419 splat_vec = gen_easy_altivec_constant (vec);
6420 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6421 operands[1] = XEXP (splat_vec, 0);
6422 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6425 switch (GET_MODE (splat_vec))
6428 return "vspltisw %0,%1";
6431 return "vspltish %0,%1";
6434 return "vspltisb %0,%1";
6444 /* Initialize vector TARGET to VALS. */
6447 rs6000_expand_vector_init (rtx target, rtx vals)
6449 machine_mode mode = GET_MODE (target);
6450 machine_mode inner_mode = GET_MODE_INNER (mode);
6451 int n_elts = GET_MODE_NUNITS (mode);
6452 int n_var = 0, one_var = -1;
6453 bool all_same = true, all_const_zero = true;
6457 for (i = 0; i < n_elts; ++i)
6459 x = XVECEXP (vals, 0, i);
6460 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6461 ++n_var, one_var = i;
6462 else if (x != CONST0_RTX (inner_mode))
6463 all_const_zero = false;
6465 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6471 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6472 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6473 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6475 /* Zero register. */
6476 emit_move_insn (target, CONST0_RTX (mode));
6479 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6481 /* Splat immediate. */
6482 emit_insn (gen_rtx_SET (target, const_vec));
6487 /* Load from constant pool. */
6488 emit_move_insn (target, const_vec);
6493 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6494 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6498 size_t num_elements = all_same ? 1 : 2;
6499 for (i = 0; i < num_elements; i++)
6501 op[i] = XVECEXP (vals, 0, i);
6502 /* Just in case there is a SUBREG with a smaller mode, do a
6504 if (GET_MODE (op[i]) != inner_mode)
6506 rtx tmp = gen_reg_rtx (inner_mode);
6507 convert_move (tmp, op[i], 0);
6510 /* Allow load with splat double word. */
6511 else if (MEM_P (op[i]))
6514 op[i] = force_reg (inner_mode, op[i]);
6516 else if (!REG_P (op[i]))
6517 op[i] = force_reg (inner_mode, op[i]);
6522 if (mode == V2DFmode)
6523 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6525 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6529 if (mode == V2DFmode)
6530 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6532 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6537 /* Special case initializing vector int if we are on 64-bit systems with
6538 direct move or we have the ISA 3.0 instructions. */
6539 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6540 && TARGET_DIRECT_MOVE_64BIT)
6544 rtx element0 = XVECEXP (vals, 0, 0);
6545 if (MEM_P (element0))
6546 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6548 element0 = force_reg (SImode, element0);
6550 if (TARGET_P9_VECTOR)
6551 emit_insn (gen_vsx_splat_v4si (target, element0));
6554 rtx tmp = gen_reg_rtx (DImode);
6555 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6556 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6565 for (i = 0; i < 4; i++)
6566 elements[i] = force_reg (SImode, XVECEXP (vals, 0, i));
6568 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6569 elements[2], elements[3]));
6574 /* With single precision floating point on VSX, know that internally single
6575 precision is actually represented as a double, and either make 2 V2DF
6576 vectors, and convert these vectors to single precision, or do one
6577 conversion, and splat the result to the other elements. */
6578 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6582 rtx element0 = XVECEXP (vals, 0, 0);
6584 if (TARGET_P9_VECTOR)
6586 if (MEM_P (element0))
6587 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6589 emit_insn (gen_vsx_splat_v4sf (target, element0));
6594 rtx freg = gen_reg_rtx (V4SFmode);
6595 rtx sreg = force_reg (SFmode, element0);
6596 rtx cvt = (TARGET_XSCVDPSPN
6597 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6598 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6601 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6607 rtx dbl_even = gen_reg_rtx (V2DFmode);
6608 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6609 rtx flt_even = gen_reg_rtx (V4SFmode);
6610 rtx flt_odd = gen_reg_rtx (V4SFmode);
6611 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6612 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6613 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6614 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6616 /* Use VMRGEW if we can instead of doing a permute. */
6617 if (TARGET_P8_VECTOR)
6619 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6620 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6621 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6622 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6623 if (BYTES_BIG_ENDIAN)
6624 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6626 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6630 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6631 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6632 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6633 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6634 rs6000_expand_extract_even (target, flt_even, flt_odd);
6640 /* Special case initializing vector short/char that are splats if we are on
6641 64-bit systems with direct move. */
6642 if (all_same && TARGET_DIRECT_MOVE_64BIT
6643 && (mode == V16QImode || mode == V8HImode))
6645 rtx op0 = XVECEXP (vals, 0, 0);
6646 rtx di_tmp = gen_reg_rtx (DImode);
6649 op0 = force_reg (GET_MODE_INNER (mode), op0);
6651 if (mode == V16QImode)
6653 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6654 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6658 if (mode == V8HImode)
6660 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6661 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6666 /* Store value to stack temp. Load vector element. Splat. However, splat
6667 of 64-bit items is not supported on Altivec. */
6668 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6670 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6671 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6672 XVECEXP (vals, 0, 0));
6673 x = gen_rtx_UNSPEC (VOIDmode,
6674 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6675 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6677 gen_rtx_SET (target, mem),
6679 x = gen_rtx_VEC_SELECT (inner_mode, target,
6680 gen_rtx_PARALLEL (VOIDmode,
6681 gen_rtvec (1, const0_rtx)));
6682 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6686 /* One field is non-constant. Load constant then overwrite
6690 rtx copy = copy_rtx (vals);
6692 /* Load constant part of vector, substitute neighboring value for
6694 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6695 rs6000_expand_vector_init (target, copy);
6697 /* Insert variable. */
6698 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
6702 /* Construct the vector in memory one field at a time
6703 and load the whole vector. */
6704 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6705 for (i = 0; i < n_elts; i++)
6706 emit_move_insn (adjust_address_nv (mem, inner_mode,
6707 i * GET_MODE_SIZE (inner_mode)),
6708 XVECEXP (vals, 0, i));
6709 emit_move_insn (target, mem);
6712 /* Set field ELT of TARGET to VAL. */
6715 rs6000_expand_vector_set (rtx target, rtx val, int elt)
6717 machine_mode mode = GET_MODE (target);
6718 machine_mode inner_mode = GET_MODE_INNER (mode);
6719 rtx reg = gen_reg_rtx (mode);
6721 int width = GET_MODE_SIZE (inner_mode);
6724 val = force_reg (GET_MODE (val), val);
6726 if (VECTOR_MEM_VSX_P (mode))
6728 rtx insn = NULL_RTX;
6729 rtx elt_rtx = GEN_INT (elt);
6731 if (mode == V2DFmode)
6732 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
6734 else if (mode == V2DImode)
6735 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
6737 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
6739 if (mode == V4SImode)
6740 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
6741 else if (mode == V8HImode)
6742 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
6743 else if (mode == V16QImode)
6744 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
6745 else if (mode == V4SFmode)
6746 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
6756 /* Simplify setting single element vectors like V1TImode. */
6757 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
6759 emit_move_insn (target, gen_lowpart (mode, val));
6763 /* Load single variable value. */
6764 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6765 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
6766 x = gen_rtx_UNSPEC (VOIDmode,
6767 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6768 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6770 gen_rtx_SET (reg, mem),
6773 /* Linear sequence. */
6774 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
6775 for (i = 0; i < 16; ++i)
6776 XVECEXP (mask, 0, i) = GEN_INT (i);
6778 /* Set permute mask to insert element into target. */
6779 for (i = 0; i < width; ++i)
6780 XVECEXP (mask, 0, elt*width + i)
6781 = GEN_INT (i + 0x10);
6782 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
6784 if (BYTES_BIG_ENDIAN)
6785 x = gen_rtx_UNSPEC (mode,
6786 gen_rtvec (3, target, reg,
6787 force_reg (V16QImode, x)),
6791 if (TARGET_P9_VECTOR)
6792 x = gen_rtx_UNSPEC (mode,
6793 gen_rtvec (3, reg, target,
6794 force_reg (V16QImode, x)),
6798 /* Invert selector. We prefer to generate VNAND on P8 so
6799 that future fusion opportunities can kick in, but must
6800 generate VNOR elsewhere. */
6801 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
6802 rtx iorx = (TARGET_P8_VECTOR
6803 ? gen_rtx_IOR (V16QImode, notx, notx)
6804 : gen_rtx_AND (V16QImode, notx, notx));
6805 rtx tmp = gen_reg_rtx (V16QImode);
6806 emit_insn (gen_rtx_SET (tmp, iorx));
6808 /* Permute with operands reversed and adjusted selector. */
6809 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
6814 emit_insn (gen_rtx_SET (target, x));
6817 /* Extract field ELT from VEC into TARGET. */
6820 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
6822 machine_mode mode = GET_MODE (vec);
6823 machine_mode inner_mode = GET_MODE_INNER (mode);
6826 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
6833 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
6834 emit_move_insn (target, gen_lowpart (TImode, vec));
6837 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
6840 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
6843 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
6846 if (TARGET_DIRECT_MOVE_64BIT)
6848 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
6854 if (TARGET_DIRECT_MOVE_64BIT)
6856 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
6862 if (TARGET_DIRECT_MOVE_64BIT)
6864 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
6870 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
6871 && TARGET_DIRECT_MOVE_64BIT)
6873 if (GET_MODE (elt) != DImode)
6875 rtx tmp = gen_reg_rtx (DImode);
6876 convert_move (tmp, elt, 0);
6879 else if (!REG_P (elt))
6880 elt = force_reg (DImode, elt);
6885 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
6889 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
6893 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
6897 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
6901 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
6905 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
6913 gcc_assert (CONST_INT_P (elt));
6915 /* Allocate mode-sized buffer. */
6916 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6918 emit_move_insn (mem, vec);
6920 /* Add offset to field within buffer matching vector element. */
6921 mem = adjust_address_nv (mem, inner_mode,
6922 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
6924 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
6927 /* Helper function to return the register number of a RTX. */
6929 regno_or_subregno (rtx op)
6933 else if (SUBREG_P (op))
6934 return subreg_regno (op);
6939 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6940 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6941 temporary (BASE_TMP) to fixup the address. Return the new memory address
6942 that is valid for reads or writes to a given register (SCALAR_REG). */
6945 rs6000_adjust_vec_address (rtx scalar_reg,
6949 machine_mode scalar_mode)
6951 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
6952 rtx addr = XEXP (mem, 0);
6957 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6958 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
6960 /* Calculate what we need to add to the address to get the element
6962 if (CONST_INT_P (element))
6963 element_offset = GEN_INT (INTVAL (element) * scalar_size);
6966 int byte_shift = exact_log2 (scalar_size);
6967 gcc_assert (byte_shift >= 0);
6969 if (byte_shift == 0)
6970 element_offset = element;
6974 if (TARGET_POWERPC64)
6975 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
6977 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
6979 element_offset = base_tmp;
6983 /* Create the new address pointing to the element within the vector. If we
6984 are adding 0, we don't have to change the address. */
6985 if (element_offset == const0_rtx)
6988 /* A simple indirect address can be converted into a reg + offset
6990 else if (REG_P (addr) || SUBREG_P (addr))
6991 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
6993 /* Optimize D-FORM addresses with constant offset with a constant element, to
6994 include the element offset in the address directly. */
6995 else if (GET_CODE (addr) == PLUS)
6997 rtx op0 = XEXP (addr, 0);
6998 rtx op1 = XEXP (addr, 1);
7001 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7002 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7004 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7005 rtx offset_rtx = GEN_INT (offset);
7007 if (IN_RANGE (offset, -32768, 32767)
7008 && (scalar_size < 8 || (offset & 0x3) == 0))
7009 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7012 emit_move_insn (base_tmp, offset_rtx);
7013 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7018 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7019 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7021 /* Note, ADDI requires the register being added to be a base
7022 register. If the register was R0, load it up into the temporary
7025 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7027 insn = gen_add3_insn (base_tmp, op1, element_offset);
7028 gcc_assert (insn != NULL_RTX);
7033 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7035 insn = gen_add3_insn (base_tmp, element_offset, op1);
7036 gcc_assert (insn != NULL_RTX);
7042 emit_move_insn (base_tmp, op1);
7043 emit_insn (gen_add2_insn (base_tmp, element_offset));
7046 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7052 emit_move_insn (base_tmp, addr);
7053 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7056 /* If we have a PLUS, we need to see whether the particular register class
7057 allows for D-FORM or X-FORM addressing. */
7058 if (GET_CODE (new_addr) == PLUS)
7060 rtx op1 = XEXP (new_addr, 1);
7061 addr_mask_type addr_mask;
7062 int scalar_regno = regno_or_subregno (scalar_reg);
7064 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7065 if (INT_REGNO_P (scalar_regno))
7066 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7068 else if (FP_REGNO_P (scalar_regno))
7069 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7071 else if (ALTIVEC_REGNO_P (scalar_regno))
7072 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7077 if (REG_P (op1) || SUBREG_P (op1))
7078 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7080 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7083 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7084 valid_addr_p = true;
7087 valid_addr_p = false;
7091 emit_move_insn (base_tmp, new_addr);
7092 new_addr = base_tmp;
7095 return change_address (mem, scalar_mode, new_addr);
7098 /* Split a variable vec_extract operation into the component instructions. */
7101 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7104 machine_mode mode = GET_MODE (src);
7105 machine_mode scalar_mode = GET_MODE (dest);
7106 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7107 int byte_shift = exact_log2 (scalar_size);
7109 gcc_assert (byte_shift >= 0);
7111 /* If we are given a memory address, optimize to load just the element. We
7112 don't have to adjust the vector element number on little endian
7116 gcc_assert (REG_P (tmp_gpr));
7117 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7118 tmp_gpr, scalar_mode));
7122 else if (REG_P (src) || SUBREG_P (src))
7124 int bit_shift = byte_shift + 3;
7126 int dest_regno = regno_or_subregno (dest);
7127 int src_regno = regno_or_subregno (src);
7128 int element_regno = regno_or_subregno (element);
7130 gcc_assert (REG_P (tmp_gpr));
7132 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7133 a general purpose register. */
7134 if (TARGET_P9_VECTOR
7135 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7136 && INT_REGNO_P (dest_regno)
7137 && ALTIVEC_REGNO_P (src_regno)
7138 && INT_REGNO_P (element_regno))
7140 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7141 rtx element_si = gen_rtx_REG (SImode, element_regno);
7143 if (mode == V16QImode)
7144 emit_insn (BYTES_BIG_ENDIAN
7145 ? gen_vextublx (dest_si, element_si, src)
7146 : gen_vextubrx (dest_si, element_si, src));
7148 else if (mode == V8HImode)
7150 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7151 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7152 emit_insn (BYTES_BIG_ENDIAN
7153 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7154 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7160 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7161 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7162 emit_insn (BYTES_BIG_ENDIAN
7163 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7164 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7171 gcc_assert (REG_P (tmp_altivec));
7173 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7174 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7175 will shift the element into the upper position (adding 3 to convert a
7176 byte shift into a bit shift). */
7177 if (scalar_size == 8)
7179 if (!BYTES_BIG_ENDIAN)
7181 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7187 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7189 emit_insn (gen_rtx_SET (tmp_gpr,
7190 gen_rtx_AND (DImode,
7191 gen_rtx_ASHIFT (DImode,
7198 if (!BYTES_BIG_ENDIAN)
7200 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7202 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7203 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7209 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7212 /* Get the value into the lower byte of the Altivec register where VSLO
7214 if (TARGET_P9_VECTOR)
7215 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7216 else if (can_create_pseudo_p ())
7217 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7220 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7221 emit_move_insn (tmp_di, tmp_gpr);
7222 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7225 /* Do the VSLO to get the value into the final location. */
7229 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7233 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7238 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7239 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7240 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7241 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7244 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7252 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7253 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7254 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7255 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7257 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7258 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7259 GEN_INT (64 - (8 * scalar_size))));
7273 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7274 selects whether the alignment is abi mandated, optional, or
7275 both abi and optional alignment. */
7278 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7280 if (how != align_opt)
7282 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7286 if (how != align_abi)
7288 if (TREE_CODE (type) == ARRAY_TYPE
7289 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7291 if (align < BITS_PER_WORD)
7292 align = BITS_PER_WORD;
7299 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7300 instructions simply ignore the low bits; VSX memory instructions
7301 are aligned to 4 or 8 bytes. */
7304 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7306 return (STRICT_ALIGNMENT
7307 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7308 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7309 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7310 && (int) align < VECTOR_ALIGN (mode)))));
7313 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7316 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7318 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7320 if (computed != 128)
7323 if (!warned && warn_psabi)
7326 inform (input_location,
7327 "the layout of aggregates containing vectors with"
7328 " %d-byte alignment has changed in GCC 5",
7329 computed / BITS_PER_UNIT);
7332 /* In current GCC there is no special case. */
7339 /* AIX increases natural record alignment to doubleword if the first
7340 field is an FP double while the FP fields remain word aligned. */
7343 rs6000_special_round_type_align (tree type, unsigned int computed,
7344 unsigned int specified)
7346 unsigned int align = MAX (computed, specified);
7347 tree field = TYPE_FIELDS (type);
7349 /* Skip all non field decls */
7350 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7351 field = DECL_CHAIN (field);
7353 if (field != NULL && field != type)
7355 type = TREE_TYPE (field);
7356 while (TREE_CODE (type) == ARRAY_TYPE)
7357 type = TREE_TYPE (type);
7359 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7360 align = MAX (align, 64);
7366 /* Darwin increases record alignment to the natural alignment of
7370 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7371 unsigned int specified)
7373 unsigned int align = MAX (computed, specified);
7375 if (TYPE_PACKED (type))
7378 /* Find the first field, looking down into aggregates. */
7380 tree field = TYPE_FIELDS (type);
7381 /* Skip all non field decls */
7382 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7383 field = DECL_CHAIN (field);
7386 /* A packed field does not contribute any extra alignment. */
7387 if (DECL_PACKED (field))
7389 type = TREE_TYPE (field);
7390 while (TREE_CODE (type) == ARRAY_TYPE)
7391 type = TREE_TYPE (type);
7392 } while (AGGREGATE_TYPE_P (type));
7394 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7395 align = MAX (align, TYPE_ALIGN (type));
7400 /* Return 1 for an operand in small memory on V.4/eabi. */
7403 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7404 machine_mode mode ATTRIBUTE_UNUSED)
7409 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7412 if (DEFAULT_ABI != ABI_V4)
7415 if (GET_CODE (op) == SYMBOL_REF)
7418 else if (GET_CODE (op) != CONST
7419 || GET_CODE (XEXP (op, 0)) != PLUS
7420 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
7421 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7426 rtx sum = XEXP (op, 0);
7427 HOST_WIDE_INT summand;
7429 /* We have to be careful here, because it is the referenced address
7430 that must be 32k from _SDA_BASE_, not just the symbol. */
7431 summand = INTVAL (XEXP (sum, 1));
7432 if (summand < 0 || summand > g_switch_value)
7435 sym_ref = XEXP (sum, 0);
7438 return SYMBOL_REF_SMALL_P (sym_ref);
7444 /* Return true if either operand is a general purpose register. */
7447 gpr_or_gpr_p (rtx op0, rtx op1)
7449 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7450 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7453 /* Return true if this is a move direct operation between GPR registers and
7454 floating point/VSX registers. */
7457 direct_move_p (rtx op0, rtx op1)
7461 if (!REG_P (op0) || !REG_P (op1))
7464 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
7467 regno0 = REGNO (op0);
7468 regno1 = REGNO (op1);
7469 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
7472 if (INT_REGNO_P (regno0))
7473 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
7475 else if (INT_REGNO_P (regno1))
7477 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
7480 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
7487 /* Return true if the OFFSET is valid for the quad address instructions that
7488 use d-form (register + offset) addressing. */
7491 quad_address_offset_p (HOST_WIDE_INT offset)
7493 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7496 /* Return true if the ADDR is an acceptable address for a quad memory
7497 operation of mode MODE (either LQ/STQ for general purpose registers, or
7498 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7499 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7500 3.0 LXV/STXV instruction. */
7503 quad_address_p (rtx addr, machine_mode mode, bool strict)
7507 if (GET_MODE_SIZE (mode) != 16)
7510 if (legitimate_indirect_address_p (addr, strict))
7513 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7516 if (GET_CODE (addr) != PLUS)
7519 op0 = XEXP (addr, 0);
7520 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7523 op1 = XEXP (addr, 1);
7524 if (!CONST_INT_P (op1))
7527 return quad_address_offset_p (INTVAL (op1));
7530 /* Return true if this is a load or store quad operation. This function does
7531 not handle the atomic quad memory instructions. */
7534 quad_load_store_p (rtx op0, rtx op1)
7538 if (!TARGET_QUAD_MEMORY)
7541 else if (REG_P (op0) && MEM_P (op1))
7542 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7543 && quad_memory_operand (op1, GET_MODE (op1))
7544 && !reg_overlap_mentioned_p (op0, op1));
7546 else if (MEM_P (op0) && REG_P (op1))
7547 ret = (quad_memory_operand (op0, GET_MODE (op0))
7548 && quad_int_reg_operand (op1, GET_MODE (op1)));
7553 if (TARGET_DEBUG_ADDR)
7555 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7556 ret ? "true" : "false");
7557 debug_rtx (gen_rtx_SET (op0, op1));
7563 /* Given an address, return a constant offset term if one exists. */
7566 address_offset (rtx op)
7568 if (GET_CODE (op) == PRE_INC
7569 || GET_CODE (op) == PRE_DEC)
7571 else if (GET_CODE (op) == PRE_MODIFY
7572 || GET_CODE (op) == LO_SUM)
7575 if (GET_CODE (op) == CONST)
7578 if (GET_CODE (op) == PLUS)
7581 if (CONST_INT_P (op))
7587 /* Return true if the MEM operand is a memory operand suitable for use
7588 with a (full width, possibly multiple) gpr load/store. On
7589 powerpc64 this means the offset must be divisible by 4.
7590 Implements 'Y' constraint.
7592 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7593 a constraint function we know the operand has satisfied a suitable
7594 memory predicate. Also accept some odd rtl generated by reload
7595 (see rs6000_legitimize_reload_address for various forms). It is
7596 important that reload rtl be accepted by appropriate constraints
7597 but not by the operand predicate.
7599 Offsetting a lo_sum should not be allowed, except where we know by
7600 alignment that a 32k boundary is not crossed, but see the ???
7601 comment in rs6000_legitimize_reload_address. Note that by
7602 "offsetting" here we mean a further offset to access parts of the
7603 MEM. It's fine to have a lo_sum where the inner address is offset
7604 from a sym, since the same sym+offset will appear in the high part
7605 of the address calculation. */
7608 mem_operand_gpr (rtx op, machine_mode mode)
7610 unsigned HOST_WIDE_INT offset;
7612 rtx addr = XEXP (op, 0);
7614 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7616 && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
7617 && mode_supports_pre_incdec_p (mode)
7618 && legitimate_indirect_address_p (XEXP (addr, 0), false))
7621 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7622 if (!rs6000_offsettable_memref_p (op, mode, false))
7625 op = address_offset (addr);
7629 offset = INTVAL (op);
7630 if (TARGET_POWERPC64 && (offset & 3) != 0)
7633 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7637 if (GET_CODE (addr) == LO_SUM)
7638 /* For lo_sum addresses, we must allow any offset except one that
7639 causes a wrap, so test only the low 16 bits. */
7640 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7642 return offset + 0x8000 < 0x10000u - extra;
7645 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7646 enforce an offset divisible by 4 even for 32-bit. */
7649 mem_operand_ds_form (rtx op, machine_mode mode)
7651 unsigned HOST_WIDE_INT offset;
7653 rtx addr = XEXP (op, 0);
7655 if (!offsettable_address_p (false, mode, addr))
7658 op = address_offset (addr);
7662 offset = INTVAL (op);
7663 if ((offset & 3) != 0)
7666 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7670 if (GET_CODE (addr) == LO_SUM)
7671 /* For lo_sum addresses, we must allow any offset except one that
7672 causes a wrap, so test only the low 16 bits. */
7673 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7675 return offset + 0x8000 < 0x10000u - extra;
7678 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7681 reg_offset_addressing_ok_p (machine_mode mode)
7695 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7696 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7697 a vector mode, if we want to use the VSX registers to move it around,
7698 we need to restrict ourselves to reg+reg addressing. Similarly for
7699 IEEE 128-bit floating point that is passed in a single vector
7701 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
7702 return mode_supports_dq_form (mode);
7706 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7707 addressing for the LFIWZX and STFIWX instructions. */
7708 if (TARGET_NO_SDMODE_STACK)
7720 virtual_stack_registers_memory_p (rtx op)
7724 if (GET_CODE (op) == REG)
7725 regnum = REGNO (op);
7727 else if (GET_CODE (op) == PLUS
7728 && GET_CODE (XEXP (op, 0)) == REG
7729 && GET_CODE (XEXP (op, 1)) == CONST_INT)
7730 regnum = REGNO (XEXP (op, 0));
7735 return (regnum >= FIRST_VIRTUAL_REGISTER
7736 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
7739 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7740 is known to not straddle a 32k boundary. This function is used
7741 to determine whether -mcmodel=medium code can use TOC pointer
7742 relative addressing for OP. This means the alignment of the TOC
7743 pointer must also be taken into account, and unfortunately that is
7746 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7747 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7751 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
7755 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
7757 if (GET_CODE (op) != SYMBOL_REF)
7760 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7762 if (mode_supports_dq_form (mode))
7765 dsize = GET_MODE_SIZE (mode);
7766 decl = SYMBOL_REF_DECL (op);
7772 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7773 replacing memory addresses with an anchor plus offset. We
7774 could find the decl by rummaging around in the block->objects
7775 VEC for the given offset but that seems like too much work. */
7776 dalign = BITS_PER_UNIT;
7777 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
7778 && SYMBOL_REF_ANCHOR_P (op)
7779 && SYMBOL_REF_BLOCK (op) != NULL)
7781 struct object_block *block = SYMBOL_REF_BLOCK (op);
7783 dalign = block->alignment;
7784 offset += SYMBOL_REF_BLOCK_OFFSET (op);
7786 else if (CONSTANT_POOL_ADDRESS_P (op))
7788 /* It would be nice to have get_pool_align().. */
7789 machine_mode cmode = get_pool_mode (op);
7791 dalign = GET_MODE_ALIGNMENT (cmode);
7794 else if (DECL_P (decl))
7796 dalign = DECL_ALIGN (decl);
7800 /* Allow BLKmode when the entire object is known to not
7801 cross a 32k boundary. */
7802 if (!DECL_SIZE_UNIT (decl))
7805 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
7808 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
7812 dalign /= BITS_PER_UNIT;
7813 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7814 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7815 return dalign >= dsize;
7821 /* Find how many bits of the alignment we know for this access. */
7822 dalign /= BITS_PER_UNIT;
7823 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7824 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7826 lsb = offset & -offset;
7830 return dalign >= dsize;
7834 constant_pool_expr_p (rtx op)
7838 split_const (op, &base, &offset);
7839 return (GET_CODE (base) == SYMBOL_REF
7840 && CONSTANT_POOL_ADDRESS_P (base)
7841 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
7844 /* These are only used to pass through from print_operand/print_operand_address
7845 to rs6000_output_addr_const_extra over the intervening function
7846 output_addr_const which is not target code. */
7847 static const_rtx tocrel_base_oac, tocrel_offset_oac;
7849 /* Return true if OP is a toc pointer relative address (the output
7850 of create_TOC_reference). If STRICT, do not match non-split
7851 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7852 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7853 TOCREL_OFFSET_RET respectively. */
7856 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
7857 const_rtx *tocrel_offset_ret)
7862 if (TARGET_CMODEL != CMODEL_SMALL)
7864 /* When strict ensure we have everything tidy. */
7866 && !(GET_CODE (op) == LO_SUM
7867 && REG_P (XEXP (op, 0))
7868 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
7871 /* When not strict, allow non-split TOC addresses and also allow
7872 (lo_sum (high ..)) TOC addresses created during reload. */
7873 if (GET_CODE (op) == LO_SUM)
7877 const_rtx tocrel_base = op;
7878 const_rtx tocrel_offset = const0_rtx;
7880 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
7882 tocrel_base = XEXP (op, 0);
7883 tocrel_offset = XEXP (op, 1);
7886 if (tocrel_base_ret)
7887 *tocrel_base_ret = tocrel_base;
7888 if (tocrel_offset_ret)
7889 *tocrel_offset_ret = tocrel_offset;
7891 return (GET_CODE (tocrel_base) == UNSPEC
7892 && XINT (tocrel_base, 1) == UNSPEC_TOCREL
7893 && REG_P (XVECEXP (tocrel_base, 0, 1))
7894 && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER);
7897 /* Return true if X is a constant pool address, and also for cmodel=medium
7898 if X is a toc-relative address known to be offsettable within MODE. */
7901 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
7904 const_rtx tocrel_base, tocrel_offset;
7905 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
7906 && (TARGET_CMODEL != CMODEL_MEDIUM
7907 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
7909 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
7910 INTVAL (tocrel_offset), mode)));
7914 legitimate_small_data_p (machine_mode mode, rtx x)
7916 return (DEFAULT_ABI == ABI_V4
7917 && !flag_pic && !TARGET_TOC
7918 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
7919 && small_data_operand (x, mode));
7923 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
7924 bool strict, bool worst_case)
7926 unsigned HOST_WIDE_INT offset;
7929 if (GET_CODE (x) != PLUS)
7931 if (!REG_P (XEXP (x, 0)))
7933 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
7935 if (mode_supports_dq_form (mode))
7936 return quad_address_p (x, mode, strict);
7937 if (!reg_offset_addressing_ok_p (mode))
7938 return virtual_stack_registers_memory_p (x);
7939 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
7941 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
7944 offset = INTVAL (XEXP (x, 1));
7951 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7953 if (VECTOR_MEM_VSX_P (mode))
7958 if (!TARGET_POWERPC64)
7960 else if (offset & 3)
7973 if (!TARGET_POWERPC64)
7975 else if (offset & 3)
7984 return offset < 0x10000 - extra;
7988 legitimate_indexed_address_p (rtx x, int strict)
7992 if (GET_CODE (x) != PLUS)
7998 return (REG_P (op0) && REG_P (op1)
7999 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8000 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8001 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8002 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8006 avoiding_indexed_address_p (machine_mode mode)
8008 /* Avoid indexed addressing for modes that have non-indexed
8009 load/store instruction forms. */
8010 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8014 legitimate_indirect_address_p (rtx x, int strict)
8016 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8020 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8022 if (!TARGET_MACHO || !flag_pic
8023 || mode != SImode || GET_CODE (x) != MEM)
8027 if (GET_CODE (x) != LO_SUM)
8029 if (GET_CODE (XEXP (x, 0)) != REG)
8031 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8035 return CONSTANT_P (x);
8039 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8041 if (GET_CODE (x) != LO_SUM)
8043 if (GET_CODE (XEXP (x, 0)) != REG)
8045 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8047 /* quad word addresses are restricted, and we can't use LO_SUM. */
8048 if (mode_supports_dq_form (mode))
8052 if (TARGET_ELF || TARGET_MACHO)
8056 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8058 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8059 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8060 recognizes some LO_SUM addresses as valid although this
8061 function says opposite. In most cases, LRA through different
8062 transformations can generate correct code for address reloads.
8063 It can not manage only some LO_SUM cases. So we need to add
8064 code analogous to one in rs6000_legitimize_reload_address for
8065 LOW_SUM here saying that some addresses are still valid. */
8066 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8067 && small_toc_ref (x, VOIDmode));
8068 if (TARGET_TOC && ! large_toc_ok)
8070 if (GET_MODE_NUNITS (mode) != 1)
8072 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8073 && !(/* ??? Assume floating point reg based on mode? */
8074 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8077 return CONSTANT_P (x) || large_toc_ok;
8084 /* Try machine-dependent ways of modifying an illegitimate address
8085 to be legitimate. If we find one, return the new, valid address.
8086 This is used from only one place: `memory_address' in explow.c.
8088 OLDX is the address as it was before break_out_memory_refs was
8089 called. In some cases it is useful to look at this to decide what
8092 It is always safe for this function to do nothing. It exists to
8093 recognize opportunities to optimize the output.
8095 On RS/6000, first check for the sum of a register with a constant
8096 integer that is out of range. If so, generate code to add the
8097 constant with the low-order 16 bits masked to the register and force
8098 this result into another register (this can be done with `cau').
8099 Then generate an address of REG+(CONST&0xffff), allowing for the
8100 possibility of bit 16 being a one.
8102 Then check for the sum of a register and something not constant, try to
8103 load the other things into a register and return the sum. */
8106 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8111 if (!reg_offset_addressing_ok_p (mode)
8112 || mode_supports_dq_form (mode))
8114 if (virtual_stack_registers_memory_p (x))
8117 /* In theory we should not be seeing addresses of the form reg+0,
8118 but just in case it is generated, optimize it away. */
8119 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8120 return force_reg (Pmode, XEXP (x, 0));
8122 /* For TImode with load/store quad, restrict addresses to just a single
8123 pointer, so it works with both GPRs and VSX registers. */
8124 /* Make sure both operands are registers. */
8125 else if (GET_CODE (x) == PLUS
8126 && (mode != TImode || !TARGET_VSX))
8127 return gen_rtx_PLUS (Pmode,
8128 force_reg (Pmode, XEXP (x, 0)),
8129 force_reg (Pmode, XEXP (x, 1)));
8131 return force_reg (Pmode, x);
8133 if (GET_CODE (x) == SYMBOL_REF)
8135 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8137 return rs6000_legitimize_tls_address (x, model);
8149 /* As in legitimate_offset_address_p we do not assume
8150 worst-case. The mode here is just a hint as to the registers
8151 used. A TImode is usually in gprs, but may actually be in
8152 fprs. Leave worst-case scenario for reload to handle via
8153 insn constraints. PTImode is only GPRs. */
8160 if (GET_CODE (x) == PLUS
8161 && GET_CODE (XEXP (x, 0)) == REG
8162 && GET_CODE (XEXP (x, 1)) == CONST_INT
8163 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8164 >= 0x10000 - extra))
8166 HOST_WIDE_INT high_int, low_int;
8168 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8169 if (low_int >= 0x8000 - extra)
8171 high_int = INTVAL (XEXP (x, 1)) - low_int;
8172 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8173 GEN_INT (high_int)), 0);
8174 return plus_constant (Pmode, sum, low_int);
8176 else if (GET_CODE (x) == PLUS
8177 && GET_CODE (XEXP (x, 0)) == REG
8178 && GET_CODE (XEXP (x, 1)) != CONST_INT
8179 && GET_MODE_NUNITS (mode) == 1
8180 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8181 || (/* ??? Assume floating point reg based on mode? */
8182 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8183 && !avoiding_indexed_address_p (mode))
8185 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8186 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8188 else if ((TARGET_ELF
8190 || !MACHO_DYNAMIC_NO_PIC_P
8196 && GET_CODE (x) != CONST_INT
8197 && GET_CODE (x) != CONST_WIDE_INT
8198 && GET_CODE (x) != CONST_DOUBLE
8200 && GET_MODE_NUNITS (mode) == 1
8201 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8202 || (/* ??? Assume floating point reg based on mode? */
8203 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8205 rtx reg = gen_reg_rtx (Pmode);
8207 emit_insn (gen_elf_high (reg, x));
8209 emit_insn (gen_macho_high (reg, x));
8210 return gen_rtx_LO_SUM (Pmode, reg, x);
8213 && GET_CODE (x) == SYMBOL_REF
8214 && constant_pool_expr_p (x)
8215 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8216 return create_TOC_reference (x, NULL_RTX);
8221 /* Debug version of rs6000_legitimize_address. */
8223 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8229 ret = rs6000_legitimize_address (x, oldx, mode);
8230 insns = get_insns ();
8236 "\nrs6000_legitimize_address: mode %s, old code %s, "
8237 "new code %s, modified\n",
8238 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8239 GET_RTX_NAME (GET_CODE (ret)));
8241 fprintf (stderr, "Original address:\n");
8244 fprintf (stderr, "oldx:\n");
8247 fprintf (stderr, "New address:\n");
8252 fprintf (stderr, "Insns added:\n");
8253 debug_rtx_list (insns, 20);
8259 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8260 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8271 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8272 We need to emit DTP-relative relocations. */
8274 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8276 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8281 fputs ("\t.long\t", file);
8284 fputs (DOUBLE_INT_ASM_OP, file);
8289 output_addr_const (file, x);
8291 fputs ("@dtprel+0x8000", file);
8292 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8294 switch (SYMBOL_REF_TLS_MODEL (x))
8298 case TLS_MODEL_LOCAL_EXEC:
8299 fputs ("@le", file);
8301 case TLS_MODEL_INITIAL_EXEC:
8302 fputs ("@ie", file);
8304 case TLS_MODEL_GLOBAL_DYNAMIC:
8305 case TLS_MODEL_LOCAL_DYNAMIC:
8314 /* Return true if X is a symbol that refers to real (rather than emulated)
8318 rs6000_real_tls_symbol_ref_p (rtx x)
8320 return (GET_CODE (x) == SYMBOL_REF
8321 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8324 /* In the name of slightly smaller debug output, and to cater to
8325 general assembler lossage, recognize various UNSPEC sequences
8326 and turn them back into a direct symbol reference. */
8329 rs6000_delegitimize_address (rtx orig_x)
8333 orig_x = delegitimize_mem_from_attrs (orig_x);
8339 if (TARGET_CMODEL != CMODEL_SMALL
8340 && GET_CODE (y) == LO_SUM)
8344 if (GET_CODE (y) == PLUS
8345 && GET_MODE (y) == Pmode
8346 && CONST_INT_P (XEXP (y, 1)))
8348 offset = XEXP (y, 1);
8352 if (GET_CODE (y) == UNSPEC
8353 && XINT (y, 1) == UNSPEC_TOCREL)
8355 y = XVECEXP (y, 0, 0);
8358 /* Do not associate thread-local symbols with the original
8359 constant pool symbol. */
8361 && GET_CODE (y) == SYMBOL_REF
8362 && CONSTANT_POOL_ADDRESS_P (y)
8363 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8367 if (offset != NULL_RTX)
8368 y = gen_rtx_PLUS (Pmode, y, offset);
8369 if (!MEM_P (orig_x))
8372 return replace_equiv_address_nv (orig_x, y);
8376 && GET_CODE (orig_x) == LO_SUM
8377 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8379 y = XEXP (XEXP (orig_x, 1), 0);
8380 if (GET_CODE (y) == UNSPEC
8381 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8382 return XVECEXP (y, 0, 0);
8388 /* Return true if X shouldn't be emitted into the debug info.
8389 The linker doesn't like .toc section references from
8390 .debug_* sections, so reject .toc section symbols. */
8393 rs6000_const_not_ok_for_debug_p (rtx x)
8395 if (GET_CODE (x) == UNSPEC)
8397 if (GET_CODE (x) == SYMBOL_REF
8398 && CONSTANT_POOL_ADDRESS_P (x))
8400 rtx c = get_pool_constant (x);
8401 machine_mode cmode = get_pool_mode (x);
8402 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8409 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8412 rs6000_legitimate_combined_insn (rtx_insn *insn)
8414 int icode = INSN_CODE (insn);
8416 /* Reject creating doloop insns. Combine should not be allowed
8417 to create these for a number of reasons:
8418 1) In a nested loop, if combine creates one of these in an
8419 outer loop and the register allocator happens to allocate ctr
8420 to the outer loop insn, then the inner loop can't use ctr.
8421 Inner loops ought to be more highly optimized.
8422 2) Combine often wants to create one of these from what was
8423 originally a three insn sequence, first combining the three
8424 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8425 allocated ctr, the splitter takes use back to the three insn
8426 sequence. It's better to stop combine at the two insn
8428 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8429 insns, the register allocator sometimes uses floating point
8430 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8431 jump insn and output reloads are not implemented for jumps,
8432 the ctrsi/ctrdi splitters need to handle all possible cases.
8433 That's a pain, and it gets to be seriously difficult when a
8434 splitter that runs after reload needs memory to transfer from
8435 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8436 for the difficult case. It's better to not create problems
8437 in the first place. */
8438 if (icode != CODE_FOR_nothing
8439 && (icode == CODE_FOR_bdz_si
8440 || icode == CODE_FOR_bdz_di
8441 || icode == CODE_FOR_bdnz_si
8442 || icode == CODE_FOR_bdnz_di
8443 || icode == CODE_FOR_bdztf_si
8444 || icode == CODE_FOR_bdztf_di
8445 || icode == CODE_FOR_bdnztf_si
8446 || icode == CODE_FOR_bdnztf_di))
8452 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8454 static GTY(()) rtx rs6000_tls_symbol;
8456 rs6000_tls_get_addr (void)
8458 if (!rs6000_tls_symbol)
8459 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8461 return rs6000_tls_symbol;
8464 /* Construct the SYMBOL_REF for TLS GOT references. */
8466 static GTY(()) rtx rs6000_got_symbol;
8468 rs6000_got_sym (void)
8470 if (!rs6000_got_symbol)
8472 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8473 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8474 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8477 return rs6000_got_symbol;
8480 /* AIX Thread-Local Address support. */
8483 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8485 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8489 name = XSTR (addr, 0);
8490 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8491 or the symbol will be in TLS private data section. */
8492 if (name[strlen (name) - 1] != ']'
8493 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8494 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8496 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8497 strcpy (tlsname, name);
8499 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8500 tlsaddr = copy_rtx (addr);
8501 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8506 /* Place addr into TOC constant pool. */
8507 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8509 /* Output the TOC entry and create the MEM referencing the value. */
8510 if (constant_pool_expr_p (XEXP (sym, 0))
8511 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8513 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8514 mem = gen_const_mem (Pmode, tocref);
8515 set_mem_alias_set (mem, get_TOC_alias_set ());
8520 /* Use global-dynamic for local-dynamic. */
8521 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8522 || model == TLS_MODEL_LOCAL_DYNAMIC)
8524 /* Create new TOC reference for @m symbol. */
8525 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8526 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8527 strcpy (tlsname, "*LCM");
8528 strcat (tlsname, name + 3);
8529 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8530 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8531 tocref = create_TOC_reference (modaddr, NULL_RTX);
8532 rtx modmem = gen_const_mem (Pmode, tocref);
8533 set_mem_alias_set (modmem, get_TOC_alias_set ());
8535 rtx modreg = gen_reg_rtx (Pmode);
8536 emit_insn (gen_rtx_SET (modreg, modmem));
8538 tmpreg = gen_reg_rtx (Pmode);
8539 emit_insn (gen_rtx_SET (tmpreg, mem));
8541 dest = gen_reg_rtx (Pmode);
8543 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8545 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8548 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8549 else if (TARGET_32BIT)
8551 tlsreg = gen_reg_rtx (SImode);
8552 emit_insn (gen_tls_get_tpointer (tlsreg));
8555 tlsreg = gen_rtx_REG (DImode, 13);
8557 /* Load the TOC value into temporary register. */
8558 tmpreg = gen_reg_rtx (Pmode);
8559 emit_insn (gen_rtx_SET (tmpreg, mem));
8560 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8561 gen_rtx_MINUS (Pmode, addr, tlsreg));
8563 /* Add TOC symbol value to TLS pointer. */
8564 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8569 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8570 this (thread-local) address. */
8573 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8578 return rs6000_legitimize_tls_address_aix (addr, model);
8580 dest = gen_reg_rtx (Pmode);
8581 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8587 tlsreg = gen_rtx_REG (Pmode, 13);
8588 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8592 tlsreg = gen_rtx_REG (Pmode, 2);
8593 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8597 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8601 tmp = gen_reg_rtx (Pmode);
8604 tlsreg = gen_rtx_REG (Pmode, 13);
8605 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8609 tlsreg = gen_rtx_REG (Pmode, 2);
8610 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8614 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8616 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8621 rtx r3, got, tga, tmp1, tmp2, call_insn;
8623 /* We currently use relocations like @got@tlsgd for tls, which
8624 means the linker will handle allocation of tls entries, placing
8625 them in the .got section. So use a pointer to the .got section,
8626 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8627 or to secondary GOT sections used by 32-bit -fPIC. */
8629 got = gen_rtx_REG (Pmode, 2);
8633 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8636 rtx gsym = rs6000_got_sym ();
8637 got = gen_reg_rtx (Pmode);
8639 rs6000_emit_move (got, gsym, Pmode);
8644 tmp1 = gen_reg_rtx (Pmode);
8645 tmp2 = gen_reg_rtx (Pmode);
8646 mem = gen_const_mem (Pmode, tmp1);
8647 lab = gen_label_rtx ();
8648 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
8649 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
8650 if (TARGET_LINK_STACK)
8651 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
8652 emit_move_insn (tmp2, mem);
8653 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
8654 set_unique_reg_note (last, REG_EQUAL, gsym);
8659 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
8661 tga = rs6000_tls_get_addr ();
8662 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
8665 r3 = gen_rtx_REG (Pmode, 3);
8666 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
8669 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
8671 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
8673 else if (DEFAULT_ABI == ABI_V4)
8674 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
8677 call_insn = last_call_insn ();
8678 PATTERN (call_insn) = insn;
8679 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
8680 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
8681 pic_offset_table_rtx);
8683 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
8685 tga = rs6000_tls_get_addr ();
8686 tmp1 = gen_reg_rtx (Pmode);
8687 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
8690 r3 = gen_rtx_REG (Pmode, 3);
8691 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
8694 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
8696 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
8698 else if (DEFAULT_ABI == ABI_V4)
8699 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
8702 call_insn = last_call_insn ();
8703 PATTERN (call_insn) = insn;
8704 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
8705 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
8706 pic_offset_table_rtx);
8708 if (rs6000_tls_size == 16)
8711 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
8713 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
8715 else if (rs6000_tls_size == 32)
8717 tmp2 = gen_reg_rtx (Pmode);
8719 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
8721 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
8724 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
8726 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
8730 tmp2 = gen_reg_rtx (Pmode);
8732 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
8734 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
8736 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
8742 /* IE, or 64-bit offset LE. */
8743 tmp2 = gen_reg_rtx (Pmode);
8745 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
8747 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
8750 insn = gen_tls_tls_64 (dest, tmp2, addr);
8752 insn = gen_tls_tls_32 (dest, tmp2, addr);
8760 /* Only create the global variable for the stack protect guard if we are using
8761 the global flavor of that guard. */
8763 rs6000_init_stack_protect_guard (void)
8765 if (rs6000_stack_protector_guard == SSP_GLOBAL)
8766 return default_stack_protect_guard ();
8771 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8774 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
8776 if (GET_CODE (x) == HIGH
8777 && GET_CODE (XEXP (x, 0)) == UNSPEC)
8780 /* A TLS symbol in the TOC cannot contain a sum. */
8781 if (GET_CODE (x) == CONST
8782 && GET_CODE (XEXP (x, 0)) == PLUS
8783 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8784 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
8787 /* Do not place an ELF TLS symbol in the constant pool. */
8788 return TARGET_ELF && tls_referenced_p (x);
8791 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8792 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8793 can be addressed relative to the toc pointer. */
8796 use_toc_relative_ref (rtx sym, machine_mode mode)
8798 return ((constant_pool_expr_p (sym)
8799 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
8800 get_pool_mode (sym)))
8801 || (TARGET_CMODEL == CMODEL_MEDIUM
8802 && SYMBOL_REF_LOCAL_P (sym)
8803 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
8806 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
8807 replace the input X, or the original X if no replacement is called for.
8808 The output parameter *WIN is 1 if the calling macro should goto WIN,
8811 For RS/6000, we wish to handle large displacements off a base
8812 register by splitting the addend across an addiu/addis and the mem insn.
8813 This cuts number of extra insns needed from 3 to 1.
8815 On Darwin, we use this to generate code for floating point constants.
8816 A movsf_low is generated so we wind up with 2 instructions rather than 3.
8817 The Darwin code is inside #if TARGET_MACHO because only then are the
8818 machopic_* functions defined. */
8820 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
8821 int opnum, int type,
8822 int ind_levels ATTRIBUTE_UNUSED, int *win)
8824 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
8825 bool quad_offset_p = mode_supports_dq_form (mode);
8827 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
8828 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
8831 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
8832 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
8833 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
8834 && TARGET_P9_VECTOR)
8835 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
8836 && TARGET_P9_VECTOR)))
8837 reg_offset_p = false;
8839 /* We must recognize output that we have already generated ourselves. */
8840 if (GET_CODE (x) == PLUS
8841 && GET_CODE (XEXP (x, 0)) == PLUS
8842 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
8843 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
8844 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8846 if (TARGET_DEBUG_ADDR)
8848 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
8851 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
8852 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
8853 opnum, (enum reload_type) type);
8858 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
8859 if (GET_CODE (x) == LO_SUM
8860 && GET_CODE (XEXP (x, 0)) == HIGH)
8862 if (TARGET_DEBUG_ADDR)
8864 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
8867 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
8868 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
8869 opnum, (enum reload_type) type);
8875 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
8876 && GET_CODE (x) == LO_SUM
8877 && GET_CODE (XEXP (x, 0)) == PLUS
8878 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
8879 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
8880 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
8881 && machopic_operand_p (XEXP (x, 1)))
8883 /* Result of previous invocation of this function on Darwin
8884 floating point constant. */
8885 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
8886 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
8887 opnum, (enum reload_type) type);
8893 if (TARGET_CMODEL != CMODEL_SMALL
8896 && small_toc_ref (x, VOIDmode))
8898 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
8899 x = gen_rtx_LO_SUM (Pmode, hi, x);
8900 if (TARGET_DEBUG_ADDR)
8902 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
8905 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
8906 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
8907 opnum, (enum reload_type) type);
8912 if (GET_CODE (x) == PLUS
8913 && REG_P (XEXP (x, 0))
8914 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
8915 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
8916 && CONST_INT_P (XEXP (x, 1))
8918 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
8920 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
8921 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
8923 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8925 /* Check for 32-bit overflow or quad addresses with one of the
8926 four least significant bits set. */
8927 if (high + low != val
8928 || (quad_offset_p && (low & 0xf)))
8934 /* Reload the high part into a base reg; leave the low part
8935 in the mem directly. */
8937 x = gen_rtx_PLUS (GET_MODE (x),
8938 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
8942 if (TARGET_DEBUG_ADDR)
8944 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
8947 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
8948 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
8949 opnum, (enum reload_type) type);
8954 if (GET_CODE (x) == SYMBOL_REF
8957 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
8959 && DEFAULT_ABI == ABI_DARWIN
8960 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
8961 && machopic_symbol_defined_p (x)
8963 && DEFAULT_ABI == ABI_V4
8966 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
8967 The same goes for DImode without 64-bit gprs and DFmode and DDmode
8969 ??? Assume floating point reg based on mode? This assumption is
8970 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
8971 where reload ends up doing a DFmode load of a constant from
8972 mem using two gprs. Unfortunately, at this point reload
8973 hasn't yet selected regs so poking around in reload data
8974 won't help and even if we could figure out the regs reliably,
8975 we'd still want to allow this transformation when the mem is
8976 naturally aligned. Since we say the address is good here, we
8977 can't disable offsets from LO_SUMs in mem_operand_gpr.
8978 FIXME: Allow offset from lo_sum for other modes too, when
8979 mem is sufficiently aligned.
8981 Also disallow this if the type can go in VMX/Altivec registers, since
8982 those registers do not have d-form (reg+offset) address modes. */
8983 && !reg_addr[mode].scalar_in_vmx_p
8988 && (mode != TImode || !TARGET_VSX)
8990 && (mode != DImode || TARGET_POWERPC64)
8991 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
8992 || TARGET_HARD_FLOAT))
8997 rtx offset = machopic_gen_offset (x);
8998 x = gen_rtx_LO_SUM (GET_MODE (x),
8999 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9000 gen_rtx_HIGH (Pmode, offset)), offset);
9004 x = gen_rtx_LO_SUM (GET_MODE (x),
9005 gen_rtx_HIGH (Pmode, x), x);
9007 if (TARGET_DEBUG_ADDR)
9009 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9012 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9013 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9014 opnum, (enum reload_type) type);
9019 /* Reload an offset address wrapped by an AND that represents the
9020 masking of the lower bits. Strip the outer AND and let reload
9021 convert the offset address into an indirect address. For VSX,
9022 force reload to create the address with an AND in a separate
9023 register, because we can't guarantee an altivec register will
9025 if (VECTOR_MEM_ALTIVEC_P (mode)
9026 && GET_CODE (x) == AND
9027 && GET_CODE (XEXP (x, 0)) == PLUS
9028 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9029 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9030 && GET_CODE (XEXP (x, 1)) == CONST_INT
9031 && INTVAL (XEXP (x, 1)) == -16)
9041 && GET_CODE (x) == SYMBOL_REF
9042 && use_toc_relative_ref (x, mode))
9044 x = create_TOC_reference (x, NULL_RTX);
9045 if (TARGET_CMODEL != CMODEL_SMALL)
9047 if (TARGET_DEBUG_ADDR)
9049 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9052 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9053 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9054 opnum, (enum reload_type) type);
9063 /* Debug version of rs6000_legitimize_reload_address. */
9065 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9066 int opnum, int type,
9067 int ind_levels, int *win)
9069 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9072 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9073 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9074 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9078 fprintf (stderr, "Same address returned\n");
9080 fprintf (stderr, "NULL returned\n");
9083 fprintf (stderr, "New address:\n");
9090 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9091 that is a valid memory address for an instruction.
9092 The MODE argument is the machine mode for the MEM expression
9093 that wants to use this address.
9095 On the RS/6000, there are four valid address: a SYMBOL_REF that
9096 refers to a constant pool entry of an address (or the sum of it
9097 plus a constant), a short (16-bit signed) constant plus a register,
9098 the sum of two registers, or a register indirect, possibly with an
9099 auto-increment. For DFmode, DDmode and DImode with a constant plus
9100 register, we must ensure that both words are addressable or PowerPC64
9101 with offset word aligned.
9103 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9104 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9105 because adjacent memory cells are accessed by adding word-sized offsets
9106 during assembly output. */
9108 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9110 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9111 bool quad_offset_p = mode_supports_dq_form (mode);
9113 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9114 if (VECTOR_MEM_ALTIVEC_P (mode)
9115 && GET_CODE (x) == AND
9116 && GET_CODE (XEXP (x, 1)) == CONST_INT
9117 && INTVAL (XEXP (x, 1)) == -16)
9120 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9122 if (legitimate_indirect_address_p (x, reg_ok_strict))
9125 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9126 && mode_supports_pre_incdec_p (mode)
9127 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9129 /* Handle restricted vector d-form offsets in ISA 3.0. */
9132 if (quad_address_p (x, mode, reg_ok_strict))
9135 else if (virtual_stack_registers_memory_p (x))
9138 else if (reg_offset_p)
9140 if (legitimate_small_data_p (mode, x))
9142 if (legitimate_constant_pool_address_p (x, mode,
9143 reg_ok_strict || lra_in_progress))
9147 /* For TImode, if we have TImode in VSX registers, only allow register
9148 indirect addresses. This will allow the values to go in either GPRs
9149 or VSX registers without reloading. The vector types would tend to
9150 go into VSX registers, so we allow REG+REG, while TImode seems
9151 somewhat split, in that some uses are GPR based, and some VSX based. */
9152 /* FIXME: We could loosen this by changing the following to
9153 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9154 but currently we cannot allow REG+REG addressing for TImode. See
9155 PR72827 for complete details on how this ends up hoodwinking DSE. */
9156 if (mode == TImode && TARGET_VSX)
9158 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9161 && GET_CODE (x) == PLUS
9162 && GET_CODE (XEXP (x, 0)) == REG
9163 && (XEXP (x, 0) == virtual_stack_vars_rtx
9164 || XEXP (x, 0) == arg_pointer_rtx)
9165 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9167 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9169 if (!FLOAT128_2REG_P (mode)
9170 && (TARGET_HARD_FLOAT
9172 || (mode != DFmode && mode != DDmode))
9173 && (TARGET_POWERPC64 || mode != DImode)
9174 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9176 && !avoiding_indexed_address_p (mode)
9177 && legitimate_indexed_address_p (x, reg_ok_strict))
9179 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9180 && mode_supports_pre_modify_p (mode)
9181 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9182 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9183 reg_ok_strict, false)
9184 || (!avoiding_indexed_address_p (mode)
9185 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9186 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9188 if (reg_offset_p && !quad_offset_p
9189 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9194 /* Debug version of rs6000_legitimate_address_p. */
9196 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9199 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9201 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9202 "strict = %d, reload = %s, code = %s\n",
9203 ret ? "true" : "false",
9204 GET_MODE_NAME (mode),
9206 (reload_completed ? "after" : "before"),
9207 GET_RTX_NAME (GET_CODE (x)));
9213 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9216 rs6000_mode_dependent_address_p (const_rtx addr,
9217 addr_space_t as ATTRIBUTE_UNUSED)
9219 return rs6000_mode_dependent_address_ptr (addr);
9222 /* Go to LABEL if ADDR (a legitimate address expression)
9223 has an effect that depends on the machine mode it is used for.
9225 On the RS/6000 this is true of all integral offsets (since AltiVec
9226 and VSX modes don't allow them) or is a pre-increment or decrement.
9228 ??? Except that due to conceptual problems in offsettable_address_p
9229 we can't really report the problems of integral offsets. So leave
9230 this assuming that the adjustable offset must be valid for the
9231 sub-words of a TFmode operand, which is what we had before. */
9234 rs6000_mode_dependent_address (const_rtx addr)
9236 switch (GET_CODE (addr))
9239 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9240 is considered a legitimate address before reload, so there
9241 are no offset restrictions in that case. Note that this
9242 condition is safe in strict mode because any address involving
9243 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9244 been rejected as illegitimate. */
9245 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9246 && XEXP (addr, 0) != arg_pointer_rtx
9247 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9249 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9250 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9255 /* Anything in the constant pool is sufficiently aligned that
9256 all bytes have the same high part address. */
9257 return !legitimate_constant_pool_address_p (addr, QImode, false);
9259 /* Auto-increment cases are now treated generically in recog.c. */
9261 return TARGET_UPDATE;
9263 /* AND is only allowed in Altivec loads. */
9274 /* Debug version of rs6000_mode_dependent_address. */
9276 rs6000_debug_mode_dependent_address (const_rtx addr)
9278 bool ret = rs6000_mode_dependent_address (addr);
9280 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9281 ret ? "true" : "false");
9287 /* Implement FIND_BASE_TERM. */
9290 rs6000_find_base_term (rtx op)
9295 if (GET_CODE (base) == CONST)
9296 base = XEXP (base, 0);
9297 if (GET_CODE (base) == PLUS)
9298 base = XEXP (base, 0);
9299 if (GET_CODE (base) == UNSPEC)
9300 switch (XINT (base, 1))
9303 case UNSPEC_MACHOPIC_OFFSET:
9304 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9305 for aliasing purposes. */
9306 return XVECEXP (base, 0, 0);
9312 /* More elaborate version of recog's offsettable_memref_p predicate
9313 that works around the ??? note of rs6000_mode_dependent_address.
9314 In particular it accepts
9316 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9318 in 32-bit mode, that the recog predicate rejects. */
9321 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9328 /* First mimic offsettable_memref_p. */
9329 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9332 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9333 the latter predicate knows nothing about the mode of the memory
9334 reference and, therefore, assumes that it is the largest supported
9335 mode (TFmode). As a consequence, legitimate offsettable memory
9336 references are rejected. rs6000_legitimate_offset_address_p contains
9337 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9338 at least with a little bit of help here given that we know the
9339 actual registers used. */
9340 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9341 || GET_MODE_SIZE (reg_mode) == 4);
9342 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9343 strict, worst_case);
9346 /* Determine the reassociation width to be used in reassociate_bb.
9347 This takes into account how many parallel operations we
9348 can actually do of a given type, and also the latency.
9352 vect add/sub/mul 2/cycle
9353 fp add/sub/mul 2/cycle
9358 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9361 switch (rs6000_tune)
9363 case PROCESSOR_POWER8:
9364 case PROCESSOR_POWER9:
9365 if (DECIMAL_FLOAT_MODE_P (mode))
9367 if (VECTOR_MODE_P (mode))
9369 if (INTEGRAL_MODE_P (mode))
9371 if (FLOAT_MODE_P (mode))
9380 /* Change register usage conditional on target flags. */
9382 rs6000_conditional_register_usage (void)
9386 if (TARGET_DEBUG_TARGET)
9387 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9389 /* Set MQ register fixed (already call_used) so that it will not be
9393 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9395 fixed_regs[13] = call_used_regs[13]
9396 = call_really_used_regs[13] = 1;
9398 /* Conditionally disable FPRs. */
9399 if (TARGET_SOFT_FLOAT)
9400 for (i = 32; i < 64; i++)
9401 fixed_regs[i] = call_used_regs[i]
9402 = call_really_used_regs[i] = 1;
9404 /* The TOC register is not killed across calls in a way that is
9405 visible to the compiler. */
9406 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9407 call_really_used_regs[2] = 0;
9409 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9410 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9412 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9413 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9414 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9415 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9417 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9418 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9419 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9420 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9422 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9423 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9424 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9426 if (!TARGET_ALTIVEC && !TARGET_VSX)
9428 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9429 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9430 call_really_used_regs[VRSAVE_REGNO] = 1;
9433 if (TARGET_ALTIVEC || TARGET_VSX)
9434 global_regs[VSCR_REGNO] = 1;
9436 if (TARGET_ALTIVEC_ABI)
9438 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9439 call_used_regs[i] = call_really_used_regs[i] = 1;
9441 /* AIX reserves VR20:31 in non-extended ABI mode. */
9443 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9444 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9449 /* Output insns to set DEST equal to the constant SOURCE as a series of
9450 lis, ori and shl instructions and return TRUE. */
9453 rs6000_emit_set_const (rtx dest, rtx source)
9455 machine_mode mode = GET_MODE (dest);
9460 gcc_checking_assert (CONST_INT_P (source));
9461 c = INTVAL (source);
9466 emit_insn (gen_rtx_SET (dest, source));
9470 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9472 emit_insn (gen_rtx_SET (copy_rtx (temp),
9473 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9474 emit_insn (gen_rtx_SET (dest,
9475 gen_rtx_IOR (SImode, copy_rtx (temp),
9476 GEN_INT (c & 0xffff))));
9480 if (!TARGET_POWERPC64)
9484 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9486 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9488 emit_move_insn (hi, GEN_INT (c >> 32));
9489 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9490 emit_move_insn (lo, GEN_INT (c));
9493 rs6000_emit_set_long_const (dest, c);
9500 insn = get_last_insn ();
9501 set = single_set (insn);
9502 if (! CONSTANT_P (SET_SRC (set)))
9503 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9508 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9509 Output insns to set DEST equal to the constant C as a series of
9510 lis, ori and shl instructions. */
9513 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9516 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9526 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9527 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9528 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9530 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9531 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9533 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9535 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9536 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9538 emit_move_insn (dest,
9539 gen_rtx_IOR (DImode, copy_rtx (temp),
9542 else if (ud3 == 0 && ud4 == 0)
9544 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9546 gcc_assert (ud2 & 0x8000);
9547 emit_move_insn (copy_rtx (temp),
9548 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9550 emit_move_insn (copy_rtx (temp),
9551 gen_rtx_IOR (DImode, copy_rtx (temp),
9553 emit_move_insn (dest,
9554 gen_rtx_ZERO_EXTEND (DImode,
9555 gen_lowpart (SImode,
9558 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9559 || (ud4 == 0 && ! (ud3 & 0x8000)))
9561 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9563 emit_move_insn (copy_rtx (temp),
9564 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9566 emit_move_insn (copy_rtx (temp),
9567 gen_rtx_IOR (DImode, copy_rtx (temp),
9569 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9570 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9573 emit_move_insn (dest,
9574 gen_rtx_IOR (DImode, copy_rtx (temp),
9579 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9581 emit_move_insn (copy_rtx (temp),
9582 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9584 emit_move_insn (copy_rtx (temp),
9585 gen_rtx_IOR (DImode, copy_rtx (temp),
9588 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9589 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9592 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9593 gen_rtx_IOR (DImode, copy_rtx (temp),
9594 GEN_INT (ud2 << 16)));
9596 emit_move_insn (dest,
9597 gen_rtx_IOR (DImode, copy_rtx (temp),
9602 /* Helper for the following. Get rid of [r+r] memory refs
9603 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9606 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9608 if (GET_CODE (operands[0]) == MEM
9609 && GET_CODE (XEXP (operands[0], 0)) != REG
9610 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9611 GET_MODE (operands[0]), false))
9613 = replace_equiv_address (operands[0],
9614 copy_addr_to_reg (XEXP (operands[0], 0)));
9616 if (GET_CODE (operands[1]) == MEM
9617 && GET_CODE (XEXP (operands[1], 0)) != REG
9618 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
9619 GET_MODE (operands[1]), false))
9621 = replace_equiv_address (operands[1],
9622 copy_addr_to_reg (XEXP (operands[1], 0)));
9625 /* Generate a vector of constants to permute MODE for a little-endian
9626 storage operation by swapping the two halves of a vector. */
9628 rs6000_const_vec (machine_mode mode)
9656 v = rtvec_alloc (subparts);
9658 for (i = 0; i < subparts / 2; ++i)
9659 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
9660 for (i = subparts / 2; i < subparts; ++i)
9661 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
9666 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9669 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
9671 /* Scalar permutations are easier to express in integer modes rather than
9672 floating-point modes, so cast them here. We use V1TImode instead
9673 of TImode to ensure that the values don't go through GPRs. */
9674 if (FLOAT128_VECTOR_P (mode))
9676 dest = gen_lowpart (V1TImode, dest);
9677 source = gen_lowpart (V1TImode, source);
9681 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9683 if (mode == TImode || mode == V1TImode)
9684 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
9688 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
9689 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
9693 /* Emit a little-endian load from vector memory location SOURCE to VSX
9694 register DEST in mode MODE. The load is done with two permuting
9695 insn's that represent an lxvd2x and xxpermdi. */
9697 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
9699 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9701 if (mode == TImode || mode == V1TImode)
9704 dest = gen_lowpart (V2DImode, dest);
9705 source = adjust_address (source, V2DImode, 0);
9708 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
9709 rs6000_emit_le_vsx_permute (tmp, source, mode);
9710 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9713 /* Emit a little-endian store to vector memory location DEST from VSX
9714 register SOURCE in mode MODE. The store is done with two permuting
9715 insn's that represent an xxpermdi and an stxvd2x. */
9717 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
9719 /* This should never be called during or after LRA, because it does
9720 not re-permute the source register. It is intended only for use
9722 gcc_assert (!lra_in_progress && !reload_completed);
9724 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9726 if (mode == TImode || mode == V1TImode)
9729 dest = adjust_address (dest, V2DImode, 0);
9730 source = gen_lowpart (V2DImode, source);
9733 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
9734 rs6000_emit_le_vsx_permute (tmp, source, mode);
9735 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9738 /* Emit a sequence representing a little-endian VSX load or store,
9739 moving data from SOURCE to DEST in mode MODE. This is done
9740 separately from rs6000_emit_move to ensure it is called only
9741 during expand. LE VSX loads and stores introduced later are
9742 handled with a split. The expand-time RTL generation allows
9743 us to optimize away redundant pairs of register-permutes. */
9745 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
9747 gcc_assert (!BYTES_BIG_ENDIAN
9748 && VECTOR_MEM_VSX_P (mode)
9749 && !TARGET_P9_VECTOR
9750 && !gpr_or_gpr_p (dest, source)
9751 && (MEM_P (source) ^ MEM_P (dest)));
9755 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
9756 rs6000_emit_le_vsx_load (dest, source, mode);
9760 if (!REG_P (source))
9761 source = force_reg (mode, source);
9762 rs6000_emit_le_vsx_store (dest, source, mode);
9766 /* Return whether a SFmode or SImode move can be done without converting one
9767 mode to another. This arrises when we have:
9769 (SUBREG:SF (REG:SI ...))
9770 (SUBREG:SI (REG:SF ...))
9772 and one of the values is in a floating point/vector register, where SFmode
9773 scalars are stored in DFmode format. */
9776 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
9778 if (TARGET_ALLOW_SF_SUBREG)
9781 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
9784 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
9787 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9788 if (SUBREG_P (dest))
9790 rtx dest_subreg = SUBREG_REG (dest);
9791 rtx src_subreg = SUBREG_REG (src);
9792 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
9799 /* Helper function to change moves with:
9801 (SUBREG:SF (REG:SI)) and
9802 (SUBREG:SI (REG:SF))
9804 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9805 values are stored as DFmode values in the VSX registers. We need to convert
9806 the bits before we can use a direct move or operate on the bits in the
9807 vector register as an integer type.
9809 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9812 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
9814 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
9815 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
9816 && SUBREG_P (source) && sf_subreg_operand (source, mode))
9818 rtx inner_source = SUBREG_REG (source);
9819 machine_mode inner_mode = GET_MODE (inner_source);
9821 if (mode == SImode && inner_mode == SFmode)
9823 emit_insn (gen_movsi_from_sf (dest, inner_source));
9827 if (mode == SFmode && inner_mode == SImode)
9829 emit_insn (gen_movsf_from_si (dest, inner_source));
9837 /* Emit a move from SOURCE to DEST in mode MODE. */
9839 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
9843 operands[1] = source;
9845 if (TARGET_DEBUG_ADDR)
9848 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9849 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9850 GET_MODE_NAME (mode),
9853 can_create_pseudo_p ());
9855 fprintf (stderr, "source:\n");
9859 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
9860 if (CONST_WIDE_INT_P (operands[1])
9861 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9863 /* This should be fixed with the introduction of CONST_WIDE_INT. */
9867 #ifdef HAVE_AS_GNU_ATTRIBUTE
9868 /* If we use a long double type, set the flags in .gnu_attribute that say
9869 what the long double type is. This is to allow the linker's warning
9870 message for the wrong long double to be useful, even if the function does
9871 not do a call (for example, doing a 128-bit add on power9 if the long
9872 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9873 used if they aren't the default long dobule type. */
9874 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
9876 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
9877 rs6000_passes_float = rs6000_passes_long_double = true;
9879 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
9880 rs6000_passes_float = rs6000_passes_long_double = true;
9884 /* See if we need to special case SImode/SFmode SUBREG moves. */
9885 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
9886 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
9889 /* Check if GCC is setting up a block move that will end up using FP
9890 registers as temporaries. We must make sure this is acceptable. */
9891 if (GET_CODE (operands[0]) == MEM
9892 && GET_CODE (operands[1]) == MEM
9894 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
9895 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
9896 && ! (rs6000_slow_unaligned_access (SImode,
9897 (MEM_ALIGN (operands[0]) > 32
9898 ? 32 : MEM_ALIGN (operands[0])))
9899 || rs6000_slow_unaligned_access (SImode,
9900 (MEM_ALIGN (operands[1]) > 32
9901 ? 32 : MEM_ALIGN (operands[1]))))
9902 && ! MEM_VOLATILE_P (operands [0])
9903 && ! MEM_VOLATILE_P (operands [1]))
9905 emit_move_insn (adjust_address (operands[0], SImode, 0),
9906 adjust_address (operands[1], SImode, 0));
9907 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
9908 adjust_address (copy_rtx (operands[1]), SImode, 4));
9912 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
9913 && !gpc_reg_operand (operands[1], mode))
9914 operands[1] = force_reg (mode, operands[1]);
9916 /* Recognize the case where operand[1] is a reference to thread-local
9917 data and load its address to a register. */
9918 if (tls_referenced_p (operands[1]))
9920 enum tls_model model;
9921 rtx tmp = operands[1];
9924 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
9926 addend = XEXP (XEXP (tmp, 0), 1);
9927 tmp = XEXP (XEXP (tmp, 0), 0);
9930 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
9931 model = SYMBOL_REF_TLS_MODEL (tmp);
9932 gcc_assert (model != 0);
9934 tmp = rs6000_legitimize_tls_address (tmp, model);
9937 tmp = gen_rtx_PLUS (mode, tmp, addend);
9938 tmp = force_operand (tmp, operands[0]);
9943 /* 128-bit constant floating-point values on Darwin should really be loaded
9944 as two parts. However, this premature splitting is a problem when DFmode
9945 values can go into Altivec registers. */
9946 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
9947 && GET_CODE (operands[1]) == CONST_DOUBLE)
9949 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
9950 simplify_gen_subreg (DFmode, operands[1], mode, 0),
9952 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
9953 GET_MODE_SIZE (DFmode)),
9954 simplify_gen_subreg (DFmode, operands[1], mode,
9955 GET_MODE_SIZE (DFmode)),
9960 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9961 p1:SD) if p1 is not of floating point class and p0 is spilled as
9962 we can have no analogous movsd_store for this. */
9963 if (lra_in_progress && mode == DDmode
9964 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
9965 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9966 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
9967 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
9970 int regno = REGNO (SUBREG_REG (operands[1]));
9972 if (regno >= FIRST_PSEUDO_REGISTER)
9974 cl = reg_preferred_class (regno);
9975 regno = reg_renumber[regno];
9977 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
9979 if (regno >= 0 && ! FP_REGNO_P (regno))
9982 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
9983 operands[1] = SUBREG_REG (operands[1]);
9988 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
9989 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9990 && (REG_P (operands[1])
9991 || (GET_CODE (operands[1]) == SUBREG
9992 && REG_P (SUBREG_REG (operands[1])))))
9994 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
9995 ? SUBREG_REG (operands[1]) : operands[1]);
9998 if (regno >= FIRST_PSEUDO_REGISTER)
10000 cl = reg_preferred_class (regno);
10001 gcc_assert (cl != NO_REGS);
10002 regno = reg_renumber[regno];
10004 regno = ira_class_hard_regs[cl][0];
10006 if (FP_REGNO_P (regno))
10008 if (GET_MODE (operands[0]) != DDmode)
10009 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10010 emit_insn (gen_movsd_store (operands[0], operands[1]));
10012 else if (INT_REGNO_P (regno))
10013 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10018 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10019 p:DD)) if p0 is not of floating point class and p1 is spilled as
10020 we can have no analogous movsd_load for this. */
10021 if (lra_in_progress && mode == DDmode
10022 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10023 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10024 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10025 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10028 int regno = REGNO (SUBREG_REG (operands[0]));
10030 if (regno >= FIRST_PSEUDO_REGISTER)
10032 cl = reg_preferred_class (regno);
10033 regno = reg_renumber[regno];
10035 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10037 if (regno >= 0 && ! FP_REGNO_P (regno))
10040 operands[0] = SUBREG_REG (operands[0]);
10041 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10044 if (lra_in_progress
10046 && (REG_P (operands[0])
10047 || (GET_CODE (operands[0]) == SUBREG
10048 && REG_P (SUBREG_REG (operands[0]))))
10049 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10050 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10052 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10053 ? SUBREG_REG (operands[0]) : operands[0]);
10056 if (regno >= FIRST_PSEUDO_REGISTER)
10058 cl = reg_preferred_class (regno);
10059 gcc_assert (cl != NO_REGS);
10060 regno = reg_renumber[regno];
10062 regno = ira_class_hard_regs[cl][0];
10064 if (FP_REGNO_P (regno))
10066 if (GET_MODE (operands[1]) != DDmode)
10067 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10068 emit_insn (gen_movsd_load (operands[0], operands[1]));
10070 else if (INT_REGNO_P (regno))
10071 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10077 /* FIXME: In the long term, this switch statement should go away
10078 and be replaced by a sequence of tests based on things like
10084 if (CONSTANT_P (operands[1])
10085 && GET_CODE (operands[1]) != CONST_INT)
10086 operands[1] = force_const_mem (mode, operands[1]);
10093 if (FLOAT128_2REG_P (mode))
10094 rs6000_eliminate_indexed_memrefs (operands);
10101 if (CONSTANT_P (operands[1])
10102 && ! easy_fp_constant (operands[1], mode))
10103 operands[1] = force_const_mem (mode, operands[1]);
10113 if (CONSTANT_P (operands[1])
10114 && !easy_vector_constant (operands[1], mode))
10115 operands[1] = force_const_mem (mode, operands[1]);
10120 /* Use default pattern for address of ELF small data */
10123 && DEFAULT_ABI == ABI_V4
10124 && (GET_CODE (operands[1]) == SYMBOL_REF
10125 || GET_CODE (operands[1]) == CONST)
10126 && small_data_operand (operands[1], mode))
10128 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10132 if (DEFAULT_ABI == ABI_V4
10133 && mode == Pmode && mode == SImode
10134 && flag_pic == 1 && got_operand (operands[1], mode))
10136 emit_insn (gen_movsi_got (operands[0], operands[1]));
10140 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10144 && CONSTANT_P (operands[1])
10145 && GET_CODE (operands[1]) != HIGH
10146 && GET_CODE (operands[1]) != CONST_INT)
10148 rtx target = (!can_create_pseudo_p ()
10150 : gen_reg_rtx (mode));
10152 /* If this is a function address on -mcall-aixdesc,
10153 convert it to the address of the descriptor. */
10154 if (DEFAULT_ABI == ABI_AIX
10155 && GET_CODE (operands[1]) == SYMBOL_REF
10156 && XSTR (operands[1], 0)[0] == '.')
10158 const char *name = XSTR (operands[1], 0);
10160 while (*name == '.')
10162 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10163 CONSTANT_POOL_ADDRESS_P (new_ref)
10164 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10165 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10166 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10167 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10168 operands[1] = new_ref;
10171 if (DEFAULT_ABI == ABI_DARWIN)
10174 if (MACHO_DYNAMIC_NO_PIC_P)
10176 /* Take care of any required data indirection. */
10177 operands[1] = rs6000_machopic_legitimize_pic_address (
10178 operands[1], mode, operands[0]);
10179 if (operands[0] != operands[1])
10180 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10184 emit_insn (gen_macho_high (target, operands[1]));
10185 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10189 emit_insn (gen_elf_high (target, operands[1]));
10190 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10194 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10195 and we have put it in the TOC, we just need to make a TOC-relative
10196 reference to it. */
10198 && GET_CODE (operands[1]) == SYMBOL_REF
10199 && use_toc_relative_ref (operands[1], mode))
10200 operands[1] = create_TOC_reference (operands[1], operands[0]);
10201 else if (mode == Pmode
10202 && CONSTANT_P (operands[1])
10203 && GET_CODE (operands[1]) != HIGH
10204 && ((GET_CODE (operands[1]) != CONST_INT
10205 && ! easy_fp_constant (operands[1], mode))
10206 || (GET_CODE (operands[1]) == CONST_INT
10207 && (num_insns_constant (operands[1], mode)
10208 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10209 || (GET_CODE (operands[0]) == REG
10210 && FP_REGNO_P (REGNO (operands[0]))))
10211 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10212 && (TARGET_CMODEL == CMODEL_SMALL
10213 || can_create_pseudo_p ()
10214 || (REG_P (operands[0])
10215 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10219 /* Darwin uses a special PIC legitimizer. */
10220 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10223 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10225 if (operands[0] != operands[1])
10226 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10231 /* If we are to limit the number of things we put in the TOC and
10232 this is a symbol plus a constant we can add in one insn,
10233 just put the symbol in the TOC and add the constant. */
10234 if (GET_CODE (operands[1]) == CONST
10235 && TARGET_NO_SUM_IN_TOC
10236 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10237 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10238 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10239 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10240 && ! side_effects_p (operands[0]))
10243 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10244 rtx other = XEXP (XEXP (operands[1], 0), 1);
10246 sym = force_reg (mode, sym);
10247 emit_insn (gen_add3_insn (operands[0], sym, other));
10251 operands[1] = force_const_mem (mode, operands[1]);
10254 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10255 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10257 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10259 operands[1] = gen_const_mem (mode, tocref);
10260 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10266 if (!VECTOR_MEM_VSX_P (TImode))
10267 rs6000_eliminate_indexed_memrefs (operands);
10271 rs6000_eliminate_indexed_memrefs (operands);
10275 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10278 /* Above, we may have called force_const_mem which may have returned
10279 an invalid address. If we can, fix this up; otherwise, reload will
10280 have to deal with it. */
10281 if (GET_CODE (operands[1]) == MEM)
10282 operands[1] = validize_mem (operands[1]);
10284 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10287 /* Nonzero if we can use a floating-point register to pass this arg. */
10288 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10289 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10290 && (CUM)->fregno <= FP_ARG_MAX_REG \
10291 && TARGET_HARD_FLOAT)
10293 /* Nonzero if we can use an AltiVec register to pass this arg. */
10294 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10295 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10296 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10297 && TARGET_ALTIVEC_ABI \
10300 /* Walk down the type tree of TYPE counting consecutive base elements.
10301 If *MODEP is VOIDmode, then set it to the first valid floating point
10302 or vector type. If a non-floating point or vector type is found, or
10303 if a floating point or vector type that doesn't match a non-VOIDmode
10304 *MODEP is found, then return -1, otherwise return the count in the
10308 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10311 HOST_WIDE_INT size;
10313 switch (TREE_CODE (type))
10316 mode = TYPE_MODE (type);
10317 if (!SCALAR_FLOAT_MODE_P (mode))
10320 if (*modep == VOIDmode)
10323 if (*modep == mode)
10329 mode = TYPE_MODE (TREE_TYPE (type));
10330 if (!SCALAR_FLOAT_MODE_P (mode))
10333 if (*modep == VOIDmode)
10336 if (*modep == mode)
10342 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10345 /* Use V4SImode as representative of all 128-bit vector types. */
10346 size = int_size_in_bytes (type);
10356 if (*modep == VOIDmode)
10359 /* Vector modes are considered to be opaque: two vectors are
10360 equivalent for the purposes of being homogeneous aggregates
10361 if they are the same size. */
10362 if (*modep == mode)
10370 tree index = TYPE_DOMAIN (type);
10372 /* Can't handle incomplete types nor sizes that are not
10374 if (!COMPLETE_TYPE_P (type)
10375 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10378 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10381 || !TYPE_MAX_VALUE (index)
10382 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10383 || !TYPE_MIN_VALUE (index)
10384 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10388 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10389 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10391 /* There must be no padding. */
10392 if (wi::to_wide (TYPE_SIZE (type))
10393 != count * GET_MODE_BITSIZE (*modep))
10405 /* Can't handle incomplete types nor sizes that are not
10407 if (!COMPLETE_TYPE_P (type)
10408 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10411 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10413 if (TREE_CODE (field) != FIELD_DECL)
10416 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10419 count += sub_count;
10422 /* There must be no padding. */
10423 if (wi::to_wide (TYPE_SIZE (type))
10424 != count * GET_MODE_BITSIZE (*modep))
10431 case QUAL_UNION_TYPE:
10433 /* These aren't very interesting except in a degenerate case. */
10438 /* Can't handle incomplete types nor sizes that are not
10440 if (!COMPLETE_TYPE_P (type)
10441 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10444 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10446 if (TREE_CODE (field) != FIELD_DECL)
10449 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10452 count = count > sub_count ? count : sub_count;
10455 /* There must be no padding. */
10456 if (wi::to_wide (TYPE_SIZE (type))
10457 != count * GET_MODE_BITSIZE (*modep))
10470 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10471 float or vector aggregate that shall be passed in FP/vector registers
10472 according to the ELFv2 ABI, return the homogeneous element mode in
10473 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10475 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10478 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10479 machine_mode *elt_mode,
10482 /* Note that we do not accept complex types at the top level as
10483 homogeneous aggregates; these types are handled via the
10484 targetm.calls.split_complex_arg mechanism. Complex types
10485 can be elements of homogeneous aggregates, however. */
10486 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10487 && AGGREGATE_TYPE_P (type))
10489 machine_mode field_mode = VOIDmode;
10490 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10492 if (field_count > 0)
10494 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
10495 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
10497 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10498 up to AGGR_ARG_NUM_REG registers. */
10499 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
10502 *elt_mode = field_mode;
10504 *n_elts = field_count;
10517 /* Return a nonzero value to say to return the function value in
10518 memory, just as large structures are always returned. TYPE will be
10519 the data type of the value, and FNTYPE will be the type of the
10520 function doing the returning, or @code{NULL} for libcalls.
10522 The AIX ABI for the RS/6000 specifies that all structures are
10523 returned in memory. The Darwin ABI does the same.
10525 For the Darwin 64 Bit ABI, a function result can be returned in
10526 registers or in memory, depending on the size of the return data
10527 type. If it is returned in registers, the value occupies the same
10528 registers as it would if it were the first and only function
10529 argument. Otherwise, the function places its result in memory at
10530 the location pointed to by GPR3.
10532 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10533 but a draft put them in memory, and GCC used to implement the draft
10534 instead of the final standard. Therefore, aix_struct_return
10535 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10536 compatibility can change DRAFT_V4_STRUCT_RET to override the
10537 default, and -m switches get the final word. See
10538 rs6000_option_override_internal for more details.
10540 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10541 long double support is enabled. These values are returned in memory.
10543 int_size_in_bytes returns -1 for variable size objects, which go in
10544 memory always. The cast to unsigned makes -1 > 8. */
10547 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10549 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10551 && rs6000_darwin64_abi
10552 && TREE_CODE (type) == RECORD_TYPE
10553 && int_size_in_bytes (type) > 0)
10555 CUMULATIVE_ARGS valcum;
10559 valcum.fregno = FP_ARG_MIN_REG;
10560 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10561 /* Do a trial code generation as if this were going to be passed
10562 as an argument; if any part goes in memory, we return NULL. */
10563 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10566 /* Otherwise fall through to more conventional ABI rules. */
10569 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10570 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10574 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10575 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10576 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10579 if (AGGREGATE_TYPE_P (type)
10580 && (aix_struct_return
10581 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10584 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10585 modes only exist for GCC vector types if -maltivec. */
10586 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10587 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10590 /* Return synthetic vectors in memory. */
10591 if (TREE_CODE (type) == VECTOR_TYPE
10592 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10594 static bool warned_for_return_big_vectors = false;
10595 if (!warned_for_return_big_vectors)
10597 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10598 "non-standard ABI extension with no compatibility "
10600 warned_for_return_big_vectors = true;
10605 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10606 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10612 /* Specify whether values returned in registers should be at the most
10613 significant end of a register. We want aggregates returned by
10614 value to match the way aggregates are passed to functions. */
10617 rs6000_return_in_msb (const_tree valtype)
10619 return (DEFAULT_ABI == ABI_ELFv2
10620 && BYTES_BIG_ENDIAN
10621 && AGGREGATE_TYPE_P (valtype)
10622 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
10626 #ifdef HAVE_AS_GNU_ATTRIBUTE
10627 /* Return TRUE if a call to function FNDECL may be one that
10628 potentially affects the function calling ABI of the object file. */
10631 call_ABI_of_interest (tree fndecl)
10633 if (rs6000_gnu_attr && symtab->state == EXPANSION)
10635 struct cgraph_node *c_node;
10637 /* Libcalls are always interesting. */
10638 if (fndecl == NULL_TREE)
10641 /* Any call to an external function is interesting. */
10642 if (DECL_EXTERNAL (fndecl))
10645 /* Interesting functions that we are emitting in this object file. */
10646 c_node = cgraph_node::get (fndecl);
10647 c_node = c_node->ultimate_alias_target ();
10648 return !c_node->only_called_directly_p ();
10654 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10655 for a call to a function whose data type is FNTYPE.
10656 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10658 For incoming args we set the number of arguments in the prototype large
10659 so we never return a PARALLEL. */
10662 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
10663 rtx libname ATTRIBUTE_UNUSED, int incoming,
10664 int libcall, int n_named_args,
10665 tree fndecl ATTRIBUTE_UNUSED,
10666 machine_mode return_mode ATTRIBUTE_UNUSED)
10668 static CUMULATIVE_ARGS zero_cumulative;
10670 *cum = zero_cumulative;
10672 cum->fregno = FP_ARG_MIN_REG;
10673 cum->vregno = ALTIVEC_ARG_MIN_REG;
10674 cum->prototype = (fntype && prototype_p (fntype));
10675 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
10676 ? CALL_LIBCALL : CALL_NORMAL);
10677 cum->sysv_gregno = GP_ARG_MIN_REG;
10678 cum->stdarg = stdarg_p (fntype);
10679 cum->libcall = libcall;
10681 cum->nargs_prototype = 0;
10682 if (incoming || cum->prototype)
10683 cum->nargs_prototype = n_named_args;
10685 /* Check for a longcall attribute. */
10686 if ((!fntype && rs6000_default_long_calls)
10688 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
10689 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
10690 cum->call_cookie |= CALL_LONG;
10692 if (TARGET_DEBUG_ARG)
10694 fprintf (stderr, "\ninit_cumulative_args:");
10697 tree ret_type = TREE_TYPE (fntype);
10698 fprintf (stderr, " ret code = %s,",
10699 get_tree_code_name (TREE_CODE (ret_type)));
10702 if (cum->call_cookie & CALL_LONG)
10703 fprintf (stderr, " longcall,");
10705 fprintf (stderr, " proto = %d, nargs = %d\n",
10706 cum->prototype, cum->nargs_prototype);
10709 #ifdef HAVE_AS_GNU_ATTRIBUTE
10710 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
10712 cum->escapes = call_ABI_of_interest (fndecl);
10719 return_type = TREE_TYPE (fntype);
10720 return_mode = TYPE_MODE (return_type);
10723 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
10725 if (return_type != NULL)
10727 if (TREE_CODE (return_type) == RECORD_TYPE
10728 && TYPE_TRANSPARENT_AGGR (return_type))
10730 return_type = TREE_TYPE (first_field (return_type));
10731 return_mode = TYPE_MODE (return_type);
10733 if (AGGREGATE_TYPE_P (return_type)
10734 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
10736 rs6000_returns_struct = true;
10738 if (SCALAR_FLOAT_MODE_P (return_mode))
10740 rs6000_passes_float = true;
10741 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10742 && (FLOAT128_IBM_P (return_mode)
10743 || FLOAT128_IEEE_P (return_mode)
10744 || (return_type != NULL
10745 && (TYPE_MAIN_VARIANT (return_type)
10746 == long_double_type_node))))
10747 rs6000_passes_long_double = true;
10749 /* Note if we passed or return a IEEE 128-bit type. We changed
10750 the mangling for these types, and we may need to make an alias
10751 with the old mangling. */
10752 if (FLOAT128_IEEE_P (return_mode))
10753 rs6000_passes_ieee128 = true;
10755 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
10756 rs6000_passes_vector = true;
10763 && TARGET_ALTIVEC_ABI
10764 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
10766 error ("cannot return value in vector register because"
10767 " altivec instructions are disabled, use %qs"
10768 " to enable them", "-maltivec");
10772 /* The mode the ABI uses for a word. This is not the same as word_mode
10773 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10775 static scalar_int_mode
10776 rs6000_abi_word_mode (void)
10778 return TARGET_32BIT ? SImode : DImode;
10781 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10783 rs6000_offload_options (void)
10786 return xstrdup ("-foffload-abi=lp64");
10788 return xstrdup ("-foffload-abi=ilp32");
10791 /* On rs6000, function arguments are promoted, as are function return
10794 static machine_mode
10795 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
10797 int *punsignedp ATTRIBUTE_UNUSED,
10800 PROMOTE_MODE (mode, *punsignedp, type);
10805 /* Return true if TYPE must be passed on the stack and not in registers. */
10808 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
10810 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
10811 return must_pass_in_stack_var_size (mode, type);
10813 return must_pass_in_stack_var_size_or_pad (mode, type);
10817 is_complex_IBM_long_double (machine_mode mode)
10819 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
10822 /* Whether ABI_V4 passes MODE args to a function in floating point
10826 abi_v4_pass_in_fpr (machine_mode mode, bool named)
10828 if (!TARGET_HARD_FLOAT)
10830 if (mode == DFmode)
10832 if (mode == SFmode && named)
10834 /* ABI_V4 passes complex IBM long double in 8 gprs.
10835 Stupid, but we can't change the ABI now. */
10836 if (is_complex_IBM_long_double (mode))
10838 if (FLOAT128_2REG_P (mode))
10840 if (DECIMAL_FLOAT_MODE_P (mode))
10845 /* Implement TARGET_FUNCTION_ARG_PADDING.
10847 For the AIX ABI structs are always stored left shifted in their
10850 static pad_direction
10851 rs6000_function_arg_padding (machine_mode mode, const_tree type)
10853 #ifndef AGGREGATE_PADDING_FIXED
10854 #define AGGREGATE_PADDING_FIXED 0
10856 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10857 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10860 if (!AGGREGATE_PADDING_FIXED)
10862 /* GCC used to pass structures of the same size as integer types as
10863 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10864 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10865 passed padded downward, except that -mstrict-align further
10866 muddied the water in that multi-component structures of 2 and 4
10867 bytes in size were passed padded upward.
10869 The following arranges for best compatibility with previous
10870 versions of gcc, but removes the -mstrict-align dependency. */
10871 if (BYTES_BIG_ENDIAN)
10873 HOST_WIDE_INT size = 0;
10875 if (mode == BLKmode)
10877 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
10878 size = int_size_in_bytes (type);
10881 size = GET_MODE_SIZE (mode);
10883 if (size == 1 || size == 2 || size == 4)
10884 return PAD_DOWNWARD;
10889 if (AGGREGATES_PAD_UPWARD_ALWAYS)
10891 if (type != 0 && AGGREGATE_TYPE_P (type))
10895 /* Fall back to the default. */
10896 return default_function_arg_padding (mode, type);
10899 /* If defined, a C expression that gives the alignment boundary, in bits,
10900 of an argument with the specified mode and type. If it is not defined,
10901 PARM_BOUNDARY is used for all arguments.
10903 V.4 wants long longs and doubles to be double word aligned. Just
10904 testing the mode size is a boneheaded way to do this as it means
10905 that other types such as complex int are also double word aligned.
10906 However, we're stuck with this because changing the ABI might break
10907 existing library interfaces.
10909 Quadword align Altivec/VSX vectors.
10910 Quadword align large synthetic vector types. */
10912 static unsigned int
10913 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
10915 machine_mode elt_mode;
10918 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10920 if (DEFAULT_ABI == ABI_V4
10921 && (GET_MODE_SIZE (mode) == 8
10922 || (TARGET_HARD_FLOAT
10923 && !is_complex_IBM_long_double (mode)
10924 && FLOAT128_2REG_P (mode))))
10926 else if (FLOAT128_VECTOR_P (mode))
10928 else if (type && TREE_CODE (type) == VECTOR_TYPE
10929 && int_size_in_bytes (type) >= 8
10930 && int_size_in_bytes (type) < 16)
10932 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10933 || (type && TREE_CODE (type) == VECTOR_TYPE
10934 && int_size_in_bytes (type) >= 16))
10937 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10938 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10939 -mcompat-align-parm is used. */
10940 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
10941 || DEFAULT_ABI == ABI_ELFv2)
10942 && type && TYPE_ALIGN (type) > 64)
10944 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10945 or homogeneous float/vector aggregates here. We already handled
10946 vector aggregates above, but still need to check for float here. */
10947 bool aggregate_p = (AGGREGATE_TYPE_P (type)
10948 && !SCALAR_FLOAT_MODE_P (elt_mode));
10950 /* We used to check for BLKmode instead of the above aggregate type
10951 check. Warn when this results in any difference to the ABI. */
10952 if (aggregate_p != (mode == BLKmode))
10954 static bool warned;
10955 if (!warned && warn_psabi)
10958 inform (input_location,
10959 "the ABI of passing aggregates with %d-byte alignment"
10960 " has changed in GCC 5",
10961 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
10969 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10970 implement the "aggregate type" check as a BLKmode check here; this
10971 means certain aggregate types are in fact not aligned. */
10972 if (TARGET_MACHO && rs6000_darwin64_abi
10974 && type && TYPE_ALIGN (type) > 64)
10977 return PARM_BOUNDARY;
10980 /* The offset in words to the start of the parameter save area. */
10982 static unsigned int
10983 rs6000_parm_offset (void)
10985 return (DEFAULT_ABI == ABI_V4 ? 2
10986 : DEFAULT_ABI == ABI_ELFv2 ? 4
10990 /* For a function parm of MODE and TYPE, return the starting word in
10991 the parameter area. NWORDS of the parameter area are already used. */
10993 static unsigned int
10994 rs6000_parm_start (machine_mode mode, const_tree type,
10995 unsigned int nwords)
10997 unsigned int align;
10999 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11000 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11003 /* Compute the size (in words) of a function argument. */
11005 static unsigned long
11006 rs6000_arg_size (machine_mode mode, const_tree type)
11008 unsigned long size;
11010 if (mode != BLKmode)
11011 size = GET_MODE_SIZE (mode);
11013 size = int_size_in_bytes (type);
11016 return (size + 3) >> 2;
11018 return (size + 7) >> 3;
11021 /* Use this to flush pending int fields. */
11024 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11025 HOST_WIDE_INT bitpos, int final)
11027 unsigned int startbit, endbit;
11028 int intregs, intoffset;
11030 /* Handle the situations where a float is taking up the first half
11031 of the GPR, and the other half is empty (typically due to
11032 alignment restrictions). We can detect this by a 8-byte-aligned
11033 int field, or by seeing that this is the final flush for this
11034 argument. Count the word and continue on. */
11035 if (cum->floats_in_gpr == 1
11036 && (cum->intoffset % 64 == 0
11037 || (cum->intoffset == -1 && final)))
11040 cum->floats_in_gpr = 0;
11043 if (cum->intoffset == -1)
11046 intoffset = cum->intoffset;
11047 cum->intoffset = -1;
11048 cum->floats_in_gpr = 0;
11050 if (intoffset % BITS_PER_WORD != 0)
11052 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11053 if (!int_mode_for_size (bits, 0).exists ())
11055 /* We couldn't find an appropriate mode, which happens,
11056 e.g., in packed structs when there are 3 bytes to load.
11057 Back intoffset back to the beginning of the word in this
11059 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11063 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11064 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11065 intregs = (endbit - startbit) / BITS_PER_WORD;
11066 cum->words += intregs;
11067 /* words should be unsigned. */
11068 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11070 int pad = (endbit/BITS_PER_WORD) - cum->words;
11075 /* The darwin64 ABI calls for us to recurse down through structs,
11076 looking for elements passed in registers. Unfortunately, we have
11077 to track int register count here also because of misalignments
11078 in powerpc alignment mode. */
11081 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11083 HOST_WIDE_INT startbitpos)
11087 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11088 if (TREE_CODE (f) == FIELD_DECL)
11090 HOST_WIDE_INT bitpos = startbitpos;
11091 tree ftype = TREE_TYPE (f);
11093 if (ftype == error_mark_node)
11095 mode = TYPE_MODE (ftype);
11097 if (DECL_SIZE (f) != 0
11098 && tree_fits_uhwi_p (bit_position (f)))
11099 bitpos += int_bit_position (f);
11101 /* ??? FIXME: else assume zero offset. */
11103 if (TREE_CODE (ftype) == RECORD_TYPE)
11104 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11105 else if (USE_FP_FOR_ARG_P (cum, mode))
11107 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11108 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11109 cum->fregno += n_fpregs;
11110 /* Single-precision floats present a special problem for
11111 us, because they are smaller than an 8-byte GPR, and so
11112 the structure-packing rules combined with the standard
11113 varargs behavior mean that we want to pack float/float
11114 and float/int combinations into a single register's
11115 space. This is complicated by the arg advance flushing,
11116 which works on arbitrarily large groups of int-type
11118 if (mode == SFmode)
11120 if (cum->floats_in_gpr == 1)
11122 /* Two floats in a word; count the word and reset
11123 the float count. */
11125 cum->floats_in_gpr = 0;
11127 else if (bitpos % 64 == 0)
11129 /* A float at the beginning of an 8-byte word;
11130 count it and put off adjusting cum->words until
11131 we see if a arg advance flush is going to do it
11133 cum->floats_in_gpr++;
11137 /* The float is at the end of a word, preceded
11138 by integer fields, so the arg advance flush
11139 just above has already set cum->words and
11140 everything is taken care of. */
11144 cum->words += n_fpregs;
11146 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11148 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11152 else if (cum->intoffset == -1)
11153 cum->intoffset = bitpos;
11157 /* Check for an item that needs to be considered specially under the darwin 64
11158 bit ABI. These are record types where the mode is BLK or the structure is
11159 8 bytes in size. */
11161 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11163 return rs6000_darwin64_abi
11164 && ((mode == BLKmode
11165 && TREE_CODE (type) == RECORD_TYPE
11166 && int_size_in_bytes (type) > 0)
11167 || (type && TREE_CODE (type) == RECORD_TYPE
11168 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11171 /* Update the data in CUM to advance over an argument
11172 of mode MODE and data type TYPE.
11173 (TYPE is null for libcalls where that information may not be available.)
11175 Note that for args passed by reference, function_arg will be called
11176 with MODE and TYPE set to that of the pointer to the arg, not the arg
11180 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11181 const_tree type, bool named, int depth)
11183 machine_mode elt_mode;
11186 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11188 /* Only tick off an argument if we're not recursing. */
11190 cum->nargs_prototype--;
11192 #ifdef HAVE_AS_GNU_ATTRIBUTE
11193 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11196 if (SCALAR_FLOAT_MODE_P (mode))
11198 rs6000_passes_float = true;
11199 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11200 && (FLOAT128_IBM_P (mode)
11201 || FLOAT128_IEEE_P (mode)
11203 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11204 rs6000_passes_long_double = true;
11206 /* Note if we passed or return a IEEE 128-bit type. We changed the
11207 mangling for these types, and we may need to make an alias with
11208 the old mangling. */
11209 if (FLOAT128_IEEE_P (mode))
11210 rs6000_passes_ieee128 = true;
11212 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11213 rs6000_passes_vector = true;
11217 if (TARGET_ALTIVEC_ABI
11218 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11219 || (type && TREE_CODE (type) == VECTOR_TYPE
11220 && int_size_in_bytes (type) == 16)))
11222 bool stack = false;
11224 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11226 cum->vregno += n_elts;
11228 if (!TARGET_ALTIVEC)
11229 error ("cannot pass argument in vector register because"
11230 " altivec instructions are disabled, use %qs"
11231 " to enable them", "-maltivec");
11233 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11234 even if it is going to be passed in a vector register.
11235 Darwin does the same for variable-argument functions. */
11236 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11238 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11248 /* Vector parameters must be 16-byte aligned. In 32-bit
11249 mode this means we need to take into account the offset
11250 to the parameter save area. In 64-bit mode, they just
11251 have to start on an even word, since the parameter save
11252 area is 16-byte aligned. */
11254 align = -(rs6000_parm_offset () + cum->words) & 3;
11256 align = cum->words & 1;
11257 cum->words += align + rs6000_arg_size (mode, type);
11259 if (TARGET_DEBUG_ARG)
11261 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11262 cum->words, align);
11263 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11264 cum->nargs_prototype, cum->prototype,
11265 GET_MODE_NAME (mode));
11269 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11271 int size = int_size_in_bytes (type);
11272 /* Variable sized types have size == -1 and are
11273 treated as if consisting entirely of ints.
11274 Pad to 16 byte boundary if needed. */
11275 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11276 && (cum->words % 2) != 0)
11278 /* For varargs, we can just go up by the size of the struct. */
11280 cum->words += (size + 7) / 8;
11283 /* It is tempting to say int register count just goes up by
11284 sizeof(type)/8, but this is wrong in a case such as
11285 { int; double; int; } [powerpc alignment]. We have to
11286 grovel through the fields for these too. */
11287 cum->intoffset = 0;
11288 cum->floats_in_gpr = 0;
11289 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11290 rs6000_darwin64_record_arg_advance_flush (cum,
11291 size * BITS_PER_UNIT, 1);
11293 if (TARGET_DEBUG_ARG)
11295 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11296 cum->words, TYPE_ALIGN (type), size);
11298 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11299 cum->nargs_prototype, cum->prototype,
11300 GET_MODE_NAME (mode));
11303 else if (DEFAULT_ABI == ABI_V4)
11305 if (abi_v4_pass_in_fpr (mode, named))
11307 /* _Decimal128 must use an even/odd register pair. This assumes
11308 that the register number is odd when fregno is odd. */
11309 if (mode == TDmode && (cum->fregno % 2) == 1)
11312 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11313 <= FP_ARG_V4_MAX_REG)
11314 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11317 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11318 if (mode == DFmode || FLOAT128_IBM_P (mode)
11319 || mode == DDmode || mode == TDmode)
11320 cum->words += cum->words & 1;
11321 cum->words += rs6000_arg_size (mode, type);
11326 int n_words = rs6000_arg_size (mode, type);
11327 int gregno = cum->sysv_gregno;
11329 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11330 As does any other 2 word item such as complex int due to a
11331 historical mistake. */
11333 gregno += (1 - gregno) & 1;
11335 /* Multi-reg args are not split between registers and stack. */
11336 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11338 /* Long long is aligned on the stack. So are other 2 word
11339 items such as complex int due to a historical mistake. */
11341 cum->words += cum->words & 1;
11342 cum->words += n_words;
11345 /* Note: continuing to accumulate gregno past when we've started
11346 spilling to the stack indicates the fact that we've started
11347 spilling to the stack to expand_builtin_saveregs. */
11348 cum->sysv_gregno = gregno + n_words;
11351 if (TARGET_DEBUG_ARG)
11353 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11354 cum->words, cum->fregno);
11355 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11356 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11357 fprintf (stderr, "mode = %4s, named = %d\n",
11358 GET_MODE_NAME (mode), named);
11363 int n_words = rs6000_arg_size (mode, type);
11364 int start_words = cum->words;
11365 int align_words = rs6000_parm_start (mode, type, start_words);
11367 cum->words = align_words + n_words;
11369 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11371 /* _Decimal128 must be passed in an even/odd float register pair.
11372 This assumes that the register number is odd when fregno is
11374 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11376 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11379 if (TARGET_DEBUG_ARG)
11381 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11382 cum->words, cum->fregno);
11383 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11384 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11385 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11386 named, align_words - start_words, depth);
11392 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11393 const_tree type, bool named)
11395 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11399 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11400 structure between cum->intoffset and bitpos to integer registers. */
11403 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11404 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11407 unsigned int regno;
11408 unsigned int startbit, endbit;
11409 int this_regno, intregs, intoffset;
11412 if (cum->intoffset == -1)
11415 intoffset = cum->intoffset;
11416 cum->intoffset = -1;
11418 /* If this is the trailing part of a word, try to only load that
11419 much into the register. Otherwise load the whole register. Note
11420 that in the latter case we may pick up unwanted bits. It's not a
11421 problem at the moment but may wish to revisit. */
11423 if (intoffset % BITS_PER_WORD != 0)
11425 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11426 if (!int_mode_for_size (bits, 0).exists (&mode))
11428 /* We couldn't find an appropriate mode, which happens,
11429 e.g., in packed structs when there are 3 bytes to load.
11430 Back intoffset back to the beginning of the word in this
11432 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11439 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11440 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11441 intregs = (endbit - startbit) / BITS_PER_WORD;
11442 this_regno = cum->words + intoffset / BITS_PER_WORD;
11444 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11445 cum->use_stack = 1;
11447 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11451 intoffset /= BITS_PER_UNIT;
11454 regno = GP_ARG_MIN_REG + this_regno;
11455 reg = gen_rtx_REG (mode, regno);
11457 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11460 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11464 while (intregs > 0);
11467 /* Recursive workhorse for the following. */
11470 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11471 HOST_WIDE_INT startbitpos, rtx rvec[],
11476 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11477 if (TREE_CODE (f) == FIELD_DECL)
11479 HOST_WIDE_INT bitpos = startbitpos;
11480 tree ftype = TREE_TYPE (f);
11482 if (ftype == error_mark_node)
11484 mode = TYPE_MODE (ftype);
11486 if (DECL_SIZE (f) != 0
11487 && tree_fits_uhwi_p (bit_position (f)))
11488 bitpos += int_bit_position (f);
11490 /* ??? FIXME: else assume zero offset. */
11492 if (TREE_CODE (ftype) == RECORD_TYPE)
11493 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11494 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11496 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11500 case E_SCmode: mode = SFmode; break;
11501 case E_DCmode: mode = DFmode; break;
11502 case E_TCmode: mode = TFmode; break;
11506 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11507 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11509 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11510 && (mode == TFmode || mode == TDmode));
11511 /* Long double or _Decimal128 split over regs and memory. */
11512 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11516 = gen_rtx_EXPR_LIST (VOIDmode,
11517 gen_rtx_REG (mode, cum->fregno++),
11518 GEN_INT (bitpos / BITS_PER_UNIT));
11519 if (FLOAT128_2REG_P (mode))
11522 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11524 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11526 = gen_rtx_EXPR_LIST (VOIDmode,
11527 gen_rtx_REG (mode, cum->vregno++),
11528 GEN_INT (bitpos / BITS_PER_UNIT));
11530 else if (cum->intoffset == -1)
11531 cum->intoffset = bitpos;
11535 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11536 the register(s) to be used for each field and subfield of a struct
11537 being passed by value, along with the offset of where the
11538 register's value may be found in the block. FP fields go in FP
11539 register, vector fields go in vector registers, and everything
11540 else goes in int registers, packed as in memory.
11542 This code is also used for function return values. RETVAL indicates
11543 whether this is the case.
11545 Much of this is taken from the SPARC V9 port, which has a similar
11546 calling convention. */
11549 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11550 bool named, bool retval)
11552 rtx rvec[FIRST_PSEUDO_REGISTER];
11553 int k = 1, kbase = 1;
11554 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11555 /* This is a copy; modifications are not visible to our caller. */
11556 CUMULATIVE_ARGS copy_cum = *orig_cum;
11557 CUMULATIVE_ARGS *cum = ©_cum;
11559 /* Pad to 16 byte boundary if needed. */
11560 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11561 && (cum->words % 2) != 0)
11564 cum->intoffset = 0;
11565 cum->use_stack = 0;
11566 cum->named = named;
11568 /* Put entries into rvec[] for individual FP and vector fields, and
11569 for the chunks of memory that go in int regs. Note we start at
11570 element 1; 0 is reserved for an indication of using memory, and
11571 may or may not be filled in below. */
11572 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11573 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11575 /* If any part of the struct went on the stack put all of it there.
11576 This hack is because the generic code for
11577 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11578 parts of the struct are not at the beginning. */
11579 if (cum->use_stack)
11582 return NULL_RTX; /* doesn't go in registers at all */
11584 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11586 if (k > 1 || cum->use_stack)
11587 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11592 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11595 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11600 rtx rvec[GP_ARG_NUM_REG + 1];
11602 if (align_words >= GP_ARG_NUM_REG)
11605 n_units = rs6000_arg_size (mode, type);
11607 /* Optimize the simple case where the arg fits in one gpr, except in
11608 the case of BLKmode due to assign_parms assuming that registers are
11609 BITS_PER_WORD wide. */
11611 || (n_units == 1 && mode != BLKmode))
11612 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11615 if (align_words + n_units > GP_ARG_NUM_REG)
11616 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11617 using a magic NULL_RTX component.
11618 This is not strictly correct. Only some of the arg belongs in
11619 memory, not all of it. However, the normal scheme using
11620 function_arg_partial_nregs can result in unusual subregs, eg.
11621 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11622 store the whole arg to memory is often more efficient than code
11623 to store pieces, and we know that space is available in the right
11624 place for the whole arg. */
11625 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11630 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
11631 rtx off = GEN_INT (i++ * 4);
11632 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11634 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
11636 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11639 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11640 but must also be copied into the parameter save area starting at
11641 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11642 to the GPRs and/or memory. Return the number of elements used. */
11645 rs6000_psave_function_arg (machine_mode mode, const_tree type,
11646 int align_words, rtx *rvec)
11650 if (align_words < GP_ARG_NUM_REG)
11652 int n_words = rs6000_arg_size (mode, type);
11654 if (align_words + n_words > GP_ARG_NUM_REG
11656 || (TARGET_32BIT && TARGET_POWERPC64))
11658 /* If this is partially on the stack, then we only
11659 include the portion actually in registers here. */
11660 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11663 if (align_words + n_words > GP_ARG_NUM_REG)
11665 /* Not all of the arg fits in gprs. Say that it goes in memory
11666 too, using a magic NULL_RTX component. Also see comment in
11667 rs6000_mixed_function_arg for why the normal
11668 function_arg_partial_nregs scheme doesn't work in this case. */
11669 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11674 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11675 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
11676 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11678 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11682 /* The whole arg fits in gprs. */
11683 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11684 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
11689 /* It's entirely in memory. */
11690 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11696 /* RVEC is a vector of K components of an argument of mode MODE.
11697 Construct the final function_arg return value from it. */
11700 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
11702 gcc_assert (k >= 1);
11704 /* Avoid returning a PARALLEL in the trivial cases. */
11707 if (XEXP (rvec[0], 0) == NULL_RTX)
11710 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
11711 return XEXP (rvec[0], 0);
11714 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11717 /* Determine where to put an argument to a function.
11718 Value is zero to push the argument on the stack,
11719 or a hard register in which to store the argument.
11721 MODE is the argument's machine mode.
11722 TYPE is the data type of the argument (as a tree).
11723 This is null for libcalls where that information may
11725 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11726 the preceding args and about the function being called. It is
11727 not modified in this routine.
11728 NAMED is nonzero if this argument is a named parameter
11729 (otherwise it is an extra parameter matching an ellipsis).
11731 On RS/6000 the first eight words of non-FP are normally in registers
11732 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11733 Under V.4, the first 8 FP args are in registers.
11735 If this is floating-point and no prototype is specified, we use
11736 both an FP and integer register (or possibly FP reg and stack). Library
11737 functions (when CALL_LIBCALL is set) always have the proper types for args,
11738 so we can pass the FP value just in one register. emit_library_function
11739 doesn't support PARALLEL anyway.
11741 Note that for args passed by reference, function_arg will be called
11742 with MODE and TYPE set to that of the pointer to the arg, not the arg
11746 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
11747 const_tree type, bool named)
11749 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11750 enum rs6000_abi abi = DEFAULT_ABI;
11751 machine_mode elt_mode;
11754 /* Return a marker to indicate whether CR1 needs to set or clear the
11755 bit that V.4 uses to say fp args were passed in registers.
11756 Assume that we don't need the marker for software floating point,
11757 or compiler generated library calls. */
11758 if (mode == VOIDmode)
11761 && (cum->call_cookie & CALL_LIBCALL) == 0
11763 || (cum->nargs_prototype < 0
11764 && (cum->prototype || TARGET_NO_PROTOTYPE)))
11765 && TARGET_HARD_FLOAT)
11766 return GEN_INT (cum->call_cookie
11767 | ((cum->fregno == FP_ARG_MIN_REG)
11768 ? CALL_V4_SET_FP_ARGS
11769 : CALL_V4_CLEAR_FP_ARGS));
11771 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
11774 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11776 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11778 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
11779 if (rslt != NULL_RTX)
11781 /* Else fall through to usual handling. */
11784 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11786 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11790 /* Do we also need to pass this argument in the parameter save area?
11791 Library support functions for IEEE 128-bit are assumed to not need the
11792 value passed both in GPRs and in vector registers. */
11793 if (TARGET_64BIT && !cum->prototype
11794 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11796 int align_words = ROUND_UP (cum->words, 2);
11797 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11800 /* Describe where this argument goes in the vector registers. */
11801 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
11803 r = gen_rtx_REG (elt_mode, cum->vregno + i);
11804 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11805 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11808 return rs6000_finish_function_arg (mode, rvec, k);
11810 else if (TARGET_ALTIVEC_ABI
11811 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
11812 || (type && TREE_CODE (type) == VECTOR_TYPE
11813 && int_size_in_bytes (type) == 16)))
11815 if (named || abi == ABI_V4)
11819 /* Vector parameters to varargs functions under AIX or Darwin
11820 get passed in memory and possibly also in GPRs. */
11821 int align, align_words, n_words;
11822 machine_mode part_mode;
11824 /* Vector parameters must be 16-byte aligned. In 32-bit
11825 mode this means we need to take into account the offset
11826 to the parameter save area. In 64-bit mode, they just
11827 have to start on an even word, since the parameter save
11828 area is 16-byte aligned. */
11830 align = -(rs6000_parm_offset () + cum->words) & 3;
11832 align = cum->words & 1;
11833 align_words = cum->words + align;
11835 /* Out of registers? Memory, then. */
11836 if (align_words >= GP_ARG_NUM_REG)
11839 if (TARGET_32BIT && TARGET_POWERPC64)
11840 return rs6000_mixed_function_arg (mode, type, align_words);
11842 /* The vector value goes in GPRs. Only the part of the
11843 value in GPRs is reported here. */
11845 n_words = rs6000_arg_size (mode, type);
11846 if (align_words + n_words > GP_ARG_NUM_REG)
11847 /* Fortunately, there are only two possibilities, the value
11848 is either wholly in GPRs or half in GPRs and half not. */
11849 part_mode = DImode;
11851 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
11855 else if (abi == ABI_V4)
11857 if (abi_v4_pass_in_fpr (mode, named))
11859 /* _Decimal128 must use an even/odd register pair. This assumes
11860 that the register number is odd when fregno is odd. */
11861 if (mode == TDmode && (cum->fregno % 2) == 1)
11864 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11865 <= FP_ARG_V4_MAX_REG)
11866 return gen_rtx_REG (mode, cum->fregno);
11872 int n_words = rs6000_arg_size (mode, type);
11873 int gregno = cum->sysv_gregno;
11875 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11876 As does any other 2 word item such as complex int due to a
11877 historical mistake. */
11879 gregno += (1 - gregno) & 1;
11881 /* Multi-reg args are not split between registers and stack. */
11882 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11885 if (TARGET_32BIT && TARGET_POWERPC64)
11886 return rs6000_mixed_function_arg (mode, type,
11887 gregno - GP_ARG_MIN_REG);
11888 return gen_rtx_REG (mode, gregno);
11893 int align_words = rs6000_parm_start (mode, type, cum->words);
11895 /* _Decimal128 must be passed in an even/odd float register pair.
11896 This assumes that the register number is odd when fregno is odd. */
11897 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11900 if (USE_FP_FOR_ARG_P (cum, elt_mode))
11902 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11905 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11908 /* Do we also need to pass this argument in the parameter
11910 if (type && (cum->nargs_prototype <= 0
11911 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11912 && TARGET_XL_COMPAT
11913 && align_words >= GP_ARG_NUM_REG)))
11914 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11916 /* Describe where this argument goes in the fprs. */
11917 for (i = 0; i < n_elts
11918 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
11920 /* Check if the argument is split over registers and memory.
11921 This can only ever happen for long double or _Decimal128;
11922 complex types are handled via split_complex_arg. */
11923 machine_mode fmode = elt_mode;
11924 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
11926 gcc_assert (FLOAT128_2REG_P (fmode));
11927 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
11930 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
11931 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11932 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11935 /* If there were not enough FPRs to hold the argument, the rest
11936 usually goes into memory. However, if the current position
11937 is still within the register parameter area, a portion may
11938 actually have to go into GPRs.
11940 Note that it may happen that the portion of the argument
11941 passed in the first "half" of the first GPR was already
11942 passed in the last FPR as well.
11944 For unnamed arguments, we already set up GPRs to cover the
11945 whole argument in rs6000_psave_function_arg, so there is
11946 nothing further to do at this point. */
11947 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
11948 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
11949 && cum->nargs_prototype > 0)
11951 static bool warned;
11953 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11954 int n_words = rs6000_arg_size (mode, type);
11956 align_words += fpr_words;
11957 n_words -= fpr_words;
11961 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11962 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
11963 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11965 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11967 if (!warned && warn_psabi)
11970 inform (input_location,
11971 "the ABI of passing homogeneous float aggregates"
11972 " has changed in GCC 5");
11976 return rs6000_finish_function_arg (mode, rvec, k);
11978 else if (align_words < GP_ARG_NUM_REG)
11980 if (TARGET_32BIT && TARGET_POWERPC64)
11981 return rs6000_mixed_function_arg (mode, type, align_words);
11983 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11990 /* For an arg passed partly in registers and partly in memory, this is
11991 the number of bytes passed in registers. For args passed entirely in
11992 registers or entirely in memory, zero. When an arg is described by a
11993 PARALLEL, perhaps using more than one register type, this function
11994 returns the number of bytes used by the first element of the PARALLEL. */
11997 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
11998 tree type, bool named)
12000 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12001 bool passed_in_gprs = true;
12004 machine_mode elt_mode;
12007 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12009 if (DEFAULT_ABI == ABI_V4)
12012 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12014 /* If we are passing this arg in the fixed parameter save area (gprs or
12015 memory) as well as VRs, we do not use the partial bytes mechanism;
12016 instead, rs6000_function_arg will return a PARALLEL including a memory
12017 element as necessary. Library support functions for IEEE 128-bit are
12018 assumed to not need the value passed both in GPRs and in vector
12020 if (TARGET_64BIT && !cum->prototype
12021 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12024 /* Otherwise, we pass in VRs only. Check for partial copies. */
12025 passed_in_gprs = false;
12026 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12027 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12030 /* In this complicated case we just disable the partial_nregs code. */
12031 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12034 align_words = rs6000_parm_start (mode, type, cum->words);
12036 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12038 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12040 /* If we are passing this arg in the fixed parameter save area
12041 (gprs or memory) as well as FPRs, we do not use the partial
12042 bytes mechanism; instead, rs6000_function_arg will return a
12043 PARALLEL including a memory element as necessary. */
12045 && (cum->nargs_prototype <= 0
12046 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12047 && TARGET_XL_COMPAT
12048 && align_words >= GP_ARG_NUM_REG)))
12051 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12052 passed_in_gprs = false;
12053 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12055 /* Compute number of bytes / words passed in FPRs. If there
12056 is still space available in the register parameter area
12057 *after* that amount, a part of the argument will be passed
12058 in GPRs. In that case, the total amount passed in any
12059 registers is equal to the amount that would have been passed
12060 in GPRs if everything were passed there, so we fall back to
12061 the GPR code below to compute the appropriate value. */
12062 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12063 * MIN (8, GET_MODE_SIZE (elt_mode)));
12064 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12066 if (align_words + fpr_words < GP_ARG_NUM_REG)
12067 passed_in_gprs = true;
12074 && align_words < GP_ARG_NUM_REG
12075 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12076 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12078 if (ret != 0 && TARGET_DEBUG_ARG)
12079 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12084 /* A C expression that indicates when an argument must be passed by
12085 reference. If nonzero for an argument, a copy of that argument is
12086 made in memory and a pointer to the argument is passed instead of
12087 the argument itself. The pointer is passed in whatever way is
12088 appropriate for passing a pointer to that type.
12090 Under V.4, aggregates and long double are passed by reference.
12092 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12093 reference unless the AltiVec vector extension ABI is in force.
12095 As an extension to all ABIs, variable sized types are passed by
12099 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12100 machine_mode mode, const_tree type,
12101 bool named ATTRIBUTE_UNUSED)
12106 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12107 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12109 if (TARGET_DEBUG_ARG)
12110 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12114 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12116 if (TARGET_DEBUG_ARG)
12117 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12121 if (int_size_in_bytes (type) < 0)
12123 if (TARGET_DEBUG_ARG)
12124 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12128 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12129 modes only exist for GCC vector types if -maltivec. */
12130 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12132 if (TARGET_DEBUG_ARG)
12133 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12137 /* Pass synthetic vectors in memory. */
12138 if (TREE_CODE (type) == VECTOR_TYPE
12139 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12141 static bool warned_for_pass_big_vectors = false;
12142 if (TARGET_DEBUG_ARG)
12143 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12144 if (!warned_for_pass_big_vectors)
12146 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12147 "non-standard ABI extension with no compatibility "
12149 warned_for_pass_big_vectors = true;
12157 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12158 already processes. Return true if the parameter must be passed
12159 (fully or partially) on the stack. */
12162 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12168 /* Catch errors. */
12169 if (type == NULL || type == error_mark_node)
12172 /* Handle types with no storage requirement. */
12173 if (TYPE_MODE (type) == VOIDmode)
12176 /* Handle complex types. */
12177 if (TREE_CODE (type) == COMPLEX_TYPE)
12178 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12179 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12181 /* Handle transparent aggregates. */
12182 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12183 && TYPE_TRANSPARENT_AGGR (type))
12184 type = TREE_TYPE (first_field (type));
12186 /* See if this arg was passed by invisible reference. */
12187 if (pass_by_reference (get_cumulative_args (args_so_far),
12188 TYPE_MODE (type), type, true))
12189 type = build_pointer_type (type);
12191 /* Find mode as it is passed by the ABI. */
12192 unsignedp = TYPE_UNSIGNED (type);
12193 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12195 /* If we must pass in stack, we need a stack. */
12196 if (rs6000_must_pass_in_stack (mode, type))
12199 /* If there is no incoming register, we need a stack. */
12200 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12201 if (entry_parm == NULL)
12204 /* Likewise if we need to pass both in registers and on the stack. */
12205 if (GET_CODE (entry_parm) == PARALLEL
12206 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12209 /* Also true if we're partially in registers and partially not. */
12210 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12213 /* Update info on where next arg arrives in registers. */
12214 rs6000_function_arg_advance (args_so_far, mode, type, true);
12218 /* Return true if FUN has no prototype, has a variable argument
12219 list, or passes any parameter in memory. */
12222 rs6000_function_parms_need_stack (tree fun, bool incoming)
12224 tree fntype, result;
12225 CUMULATIVE_ARGS args_so_far_v;
12226 cumulative_args_t args_so_far;
12229 /* Must be a libcall, all of which only use reg parms. */
12234 fntype = TREE_TYPE (fun);
12236 /* Varargs functions need the parameter save area. */
12237 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12240 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12241 args_so_far = pack_cumulative_args (&args_so_far_v);
12243 /* When incoming, we will have been passed the function decl.
12244 It is necessary to use the decl to handle K&R style functions,
12245 where TYPE_ARG_TYPES may not be available. */
12248 gcc_assert (DECL_P (fun));
12249 result = DECL_RESULT (fun);
12252 result = TREE_TYPE (fntype);
12254 if (result && aggregate_value_p (result, fntype))
12256 if (!TYPE_P (result))
12257 result = TREE_TYPE (result);
12258 result = build_pointer_type (result);
12259 rs6000_parm_needs_stack (args_so_far, result);
12266 for (parm = DECL_ARGUMENTS (fun);
12267 parm && parm != void_list_node;
12268 parm = TREE_CHAIN (parm))
12269 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12274 function_args_iterator args_iter;
12277 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12278 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12285 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12286 usually a constant depending on the ABI. However, in the ELFv2 ABI
12287 the register parameter area is optional when calling a function that
12288 has a prototype is scope, has no variable argument list, and passes
12289 all parameters in registers. */
12292 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12294 int reg_parm_stack_space;
12296 switch (DEFAULT_ABI)
12299 reg_parm_stack_space = 0;
12304 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12308 /* ??? Recomputing this every time is a bit expensive. Is there
12309 a place to cache this information? */
12310 if (rs6000_function_parms_need_stack (fun, incoming))
12311 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12313 reg_parm_stack_space = 0;
12317 return reg_parm_stack_space;
12321 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12324 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12329 for (i = 0; i < nregs; i++)
12331 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12332 if (reload_completed)
12334 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12337 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12338 i * GET_MODE_SIZE (reg_mode));
12341 tem = replace_equiv_address (tem, XEXP (tem, 0));
12345 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12349 /* Perform any needed actions needed for a function that is receiving a
12350 variable number of arguments.
12354 MODE and TYPE are the mode and type of the current parameter.
12356 PRETEND_SIZE is a variable that should be set to the amount of stack
12357 that must be pushed by the prolog to pretend that our caller pushed
12360 Normally, this macro will push all remaining incoming registers on the
12361 stack and set PRETEND_SIZE to the length of the registers pushed. */
12364 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12365 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12368 CUMULATIVE_ARGS next_cum;
12369 int reg_size = TARGET_32BIT ? 4 : 8;
12370 rtx save_area = NULL_RTX, mem;
12371 int first_reg_offset;
12372 alias_set_type set;
12374 /* Skip the last named argument. */
12375 next_cum = *get_cumulative_args (cum);
12376 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12378 if (DEFAULT_ABI == ABI_V4)
12380 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12384 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12385 HOST_WIDE_INT offset = 0;
12387 /* Try to optimize the size of the varargs save area.
12388 The ABI requires that ap.reg_save_area is doubleword
12389 aligned, but we don't need to allocate space for all
12390 the bytes, only those to which we actually will save
12392 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12393 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12394 if (TARGET_HARD_FLOAT
12395 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12396 && cfun->va_list_fpr_size)
12399 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12400 * UNITS_PER_FP_WORD;
12401 if (cfun->va_list_fpr_size
12402 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12403 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12405 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12406 * UNITS_PER_FP_WORD;
12410 offset = -((first_reg_offset * reg_size) & ~7);
12411 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12413 gpr_reg_num = cfun->va_list_gpr_size;
12414 if (reg_size == 4 && (first_reg_offset & 1))
12417 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12420 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12421 * UNITS_PER_FP_WORD
12422 - (int) (GP_ARG_NUM_REG * reg_size);
12424 if (gpr_size + fpr_size)
12427 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12428 gcc_assert (GET_CODE (reg_save_area) == MEM);
12429 reg_save_area = XEXP (reg_save_area, 0);
12430 if (GET_CODE (reg_save_area) == PLUS)
12432 gcc_assert (XEXP (reg_save_area, 0)
12433 == virtual_stack_vars_rtx);
12434 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
12435 offset += INTVAL (XEXP (reg_save_area, 1));
12438 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12441 cfun->machine->varargs_save_offset = offset;
12442 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12447 first_reg_offset = next_cum.words;
12448 save_area = crtl->args.internal_arg_pointer;
12450 if (targetm.calls.must_pass_in_stack (mode, type))
12451 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12454 set = get_varargs_alias_set ();
12455 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12456 && cfun->va_list_gpr_size)
12458 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12460 if (va_list_gpr_counter_field)
12461 /* V4 va_list_gpr_size counts number of registers needed. */
12462 n_gpr = cfun->va_list_gpr_size;
12464 /* char * va_list instead counts number of bytes needed. */
12465 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12470 mem = gen_rtx_MEM (BLKmode,
12471 plus_constant (Pmode, save_area,
12472 first_reg_offset * reg_size));
12473 MEM_NOTRAP_P (mem) = 1;
12474 set_mem_alias_set (mem, set);
12475 set_mem_align (mem, BITS_PER_WORD);
12477 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12481 /* Save FP registers if needed. */
12482 if (DEFAULT_ABI == ABI_V4
12483 && TARGET_HARD_FLOAT
12485 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12486 && cfun->va_list_fpr_size)
12488 int fregno = next_cum.fregno, nregs;
12489 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12490 rtx lab = gen_label_rtx ();
12491 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12492 * UNITS_PER_FP_WORD);
12495 (gen_rtx_SET (pc_rtx,
12496 gen_rtx_IF_THEN_ELSE (VOIDmode,
12497 gen_rtx_NE (VOIDmode, cr1,
12499 gen_rtx_LABEL_REF (VOIDmode, lab),
12503 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12504 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12506 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12507 plus_constant (Pmode, save_area, off));
12508 MEM_NOTRAP_P (mem) = 1;
12509 set_mem_alias_set (mem, set);
12510 set_mem_align (mem, GET_MODE_ALIGNMENT (
12511 TARGET_HARD_FLOAT ? DFmode : SFmode));
12512 emit_move_insn (mem, gen_rtx_REG (
12513 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12520 /* Create the va_list data type. */
12523 rs6000_build_builtin_va_list (void)
12525 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12527 /* For AIX, prefer 'char *' because that's what the system
12528 header files like. */
12529 if (DEFAULT_ABI != ABI_V4)
12530 return build_pointer_type (char_type_node);
12532 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12533 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12534 get_identifier ("__va_list_tag"), record);
12536 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12537 unsigned_char_type_node);
12538 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12539 unsigned_char_type_node);
12540 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12541 every user file. */
12542 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12543 get_identifier ("reserved"), short_unsigned_type_node);
12544 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12545 get_identifier ("overflow_arg_area"),
12547 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12548 get_identifier ("reg_save_area"),
12551 va_list_gpr_counter_field = f_gpr;
12552 va_list_fpr_counter_field = f_fpr;
12554 DECL_FIELD_CONTEXT (f_gpr) = record;
12555 DECL_FIELD_CONTEXT (f_fpr) = record;
12556 DECL_FIELD_CONTEXT (f_res) = record;
12557 DECL_FIELD_CONTEXT (f_ovf) = record;
12558 DECL_FIELD_CONTEXT (f_sav) = record;
12560 TYPE_STUB_DECL (record) = type_decl;
12561 TYPE_NAME (record) = type_decl;
12562 TYPE_FIELDS (record) = f_gpr;
12563 DECL_CHAIN (f_gpr) = f_fpr;
12564 DECL_CHAIN (f_fpr) = f_res;
12565 DECL_CHAIN (f_res) = f_ovf;
12566 DECL_CHAIN (f_ovf) = f_sav;
12568 layout_type (record);
12570 /* The correct type is an array type of one element. */
12571 return build_array_type (record, build_index_type (size_zero_node));
12574 /* Implement va_start. */
12577 rs6000_va_start (tree valist, rtx nextarg)
12579 HOST_WIDE_INT words, n_gpr, n_fpr;
12580 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12581 tree gpr, fpr, ovf, sav, t;
12583 /* Only SVR4 needs something special. */
12584 if (DEFAULT_ABI != ABI_V4)
12586 std_expand_builtin_va_start (valist, nextarg);
12590 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12591 f_fpr = DECL_CHAIN (f_gpr);
12592 f_res = DECL_CHAIN (f_fpr);
12593 f_ovf = DECL_CHAIN (f_res);
12594 f_sav = DECL_CHAIN (f_ovf);
12596 valist = build_simple_mem_ref (valist);
12597 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12598 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12600 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12602 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12605 /* Count number of gp and fp argument registers used. */
12606 words = crtl->args.info.words;
12607 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12609 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12612 if (TARGET_DEBUG_ARG)
12613 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12614 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12615 words, n_gpr, n_fpr);
12617 if (cfun->va_list_gpr_size)
12619 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
12620 build_int_cst (NULL_TREE, n_gpr));
12621 TREE_SIDE_EFFECTS (t) = 1;
12622 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12625 if (cfun->va_list_fpr_size)
12627 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
12628 build_int_cst (NULL_TREE, n_fpr));
12629 TREE_SIDE_EFFECTS (t) = 1;
12630 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12632 #ifdef HAVE_AS_GNU_ATTRIBUTE
12633 if (call_ABI_of_interest (cfun->decl))
12634 rs6000_passes_float = true;
12638 /* Find the overflow area. */
12639 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
12641 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
12642 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
12643 TREE_SIDE_EFFECTS (t) = 1;
12644 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12646 /* If there were no va_arg invocations, don't set up the register
12648 if (!cfun->va_list_gpr_size
12649 && !cfun->va_list_fpr_size
12650 && n_gpr < GP_ARG_NUM_REG
12651 && n_fpr < FP_ARG_V4_MAX_REG)
12654 /* Find the register save area. */
12655 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
12656 if (cfun->machine->varargs_save_offset)
12657 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
12658 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
12659 TREE_SIDE_EFFECTS (t) = 1;
12660 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12663 /* Implement va_arg. */
12666 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
12667 gimple_seq *post_p)
12669 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12670 tree gpr, fpr, ovf, sav, reg, t, u;
12671 int size, rsize, n_reg, sav_ofs, sav_scale;
12672 tree lab_false, lab_over, addr;
12674 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
12678 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
12680 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
12681 return build_va_arg_indirect_ref (t);
12684 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12685 earlier version of gcc, with the property that it always applied alignment
12686 adjustments to the va-args (even for zero-sized types). The cheapest way
12687 to deal with this is to replicate the effect of the part of
12688 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12690 We don't need to check for pass-by-reference because of the test above.
12691 We can return a simplifed answer, since we know there's no offset to add. */
12694 && rs6000_darwin64_abi)
12695 || DEFAULT_ABI == ABI_ELFv2
12696 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
12697 && integer_zerop (TYPE_SIZE (type)))
12699 unsigned HOST_WIDE_INT align, boundary;
12700 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
12701 align = PARM_BOUNDARY / BITS_PER_UNIT;
12702 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
12703 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
12704 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
12705 boundary /= BITS_PER_UNIT;
12706 if (boundary > align)
12709 /* This updates arg ptr by the amount that would be necessary
12710 to align the zero-sized (but not zero-alignment) item. */
12711 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12712 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
12713 gimplify_and_add (t, pre_p);
12715 t = fold_convert (sizetype, valist_tmp);
12716 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12717 fold_convert (TREE_TYPE (valist),
12718 fold_build2 (BIT_AND_EXPR, sizetype, t,
12719 size_int (-boundary))));
12720 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
12721 gimplify_and_add (t, pre_p);
12723 /* Since it is zero-sized there's no increment for the item itself. */
12724 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
12725 return build_va_arg_indirect_ref (valist_tmp);
12728 if (DEFAULT_ABI != ABI_V4)
12730 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
12732 tree elem_type = TREE_TYPE (type);
12733 machine_mode elem_mode = TYPE_MODE (elem_type);
12734 int elem_size = GET_MODE_SIZE (elem_mode);
12736 if (elem_size < UNITS_PER_WORD)
12738 tree real_part, imag_part;
12739 gimple_seq post = NULL;
12741 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12743 /* Copy the value into a temporary, lest the formal temporary
12744 be reused out from under us. */
12745 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
12746 gimple_seq_add_seq (pre_p, post);
12748 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12751 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
12755 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
12758 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12759 f_fpr = DECL_CHAIN (f_gpr);
12760 f_res = DECL_CHAIN (f_fpr);
12761 f_ovf = DECL_CHAIN (f_res);
12762 f_sav = DECL_CHAIN (f_ovf);
12764 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12765 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12767 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12769 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12772 size = int_size_in_bytes (type);
12773 rsize = (size + 3) / 4;
12774 int pad = 4 * rsize - size;
12777 machine_mode mode = TYPE_MODE (type);
12778 if (abi_v4_pass_in_fpr (mode, false))
12780 /* FP args go in FP registers, if present. */
12782 n_reg = (size + 7) / 8;
12783 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
12784 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
12785 if (mode != SFmode && mode != SDmode)
12790 /* Otherwise into GP registers. */
12799 /* Pull the value out of the saved registers.... */
12802 addr = create_tmp_var (ptr_type_node, "addr");
12804 /* AltiVec vectors never go in registers when -mabi=altivec. */
12805 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12809 lab_false = create_artificial_label (input_location);
12810 lab_over = create_artificial_label (input_location);
12812 /* Long long is aligned in the registers. As are any other 2 gpr
12813 item such as complex int due to a historical mistake. */
12815 if (n_reg == 2 && reg == gpr)
12818 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12819 build_int_cst (TREE_TYPE (reg), n_reg - 1));
12820 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
12821 unshare_expr (reg), u);
12823 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12824 reg number is 0 for f1, so we want to make it odd. */
12825 else if (reg == fpr && mode == TDmode)
12827 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12828 build_int_cst (TREE_TYPE (reg), 1));
12829 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
12832 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
12833 t = build2 (GE_EXPR, boolean_type_node, u, t);
12834 u = build1 (GOTO_EXPR, void_type_node, lab_false);
12835 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
12836 gimplify_and_add (t, pre_p);
12840 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
12842 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12843 build_int_cst (TREE_TYPE (reg), n_reg));
12844 u = fold_convert (sizetype, u);
12845 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
12846 t = fold_build_pointer_plus (t, u);
12848 /* _Decimal32 varargs are located in the second word of the 64-bit
12849 FP register for 32-bit binaries. */
12850 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
12851 t = fold_build_pointer_plus_hwi (t, size);
12853 /* Args are passed right-aligned. */
12854 if (BYTES_BIG_ENDIAN)
12855 t = fold_build_pointer_plus_hwi (t, pad);
12857 gimplify_assign (addr, t, pre_p);
12859 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
12861 stmt = gimple_build_label (lab_false);
12862 gimple_seq_add_stmt (pre_p, stmt);
12864 if ((n_reg == 2 && !regalign) || n_reg > 2)
12866 /* Ensure that we don't find any more args in regs.
12867 Alignment has taken care of for special cases. */
12868 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
12872 /* ... otherwise out of the overflow area. */
12874 /* Care for on-stack alignment if needed. */
12878 t = fold_build_pointer_plus_hwi (t, align - 1);
12879 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
12880 build_int_cst (TREE_TYPE (t), -align));
12883 /* Args are passed right-aligned. */
12884 if (BYTES_BIG_ENDIAN)
12885 t = fold_build_pointer_plus_hwi (t, pad);
12887 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
12889 gimplify_assign (unshare_expr (addr), t, pre_p);
12891 t = fold_build_pointer_plus_hwi (t, size);
12892 gimplify_assign (unshare_expr (ovf), t, pre_p);
12896 stmt = gimple_build_label (lab_over);
12897 gimple_seq_add_stmt (pre_p, stmt);
12900 if (STRICT_ALIGNMENT
12901 && (TYPE_ALIGN (type)
12902 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
12904 /* The value (of type complex double, for example) may not be
12905 aligned in memory in the saved registers, so copy via a
12906 temporary. (This is the same code as used for SPARC.) */
12907 tree tmp = create_tmp_var (type, "va_arg_tmp");
12908 tree dest_addr = build_fold_addr_expr (tmp);
12910 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
12911 3, dest_addr, addr, size_int (rsize * 4));
12912 TREE_ADDRESSABLE (tmp) = 1;
12914 gimplify_and_add (copy, pre_p);
12918 addr = fold_convert (ptrtype, addr);
12919 return build_va_arg_indirect_ref (addr);
12925 def_builtin (const char *name, tree type, enum rs6000_builtins code)
12928 unsigned classify = rs6000_builtin_info[(int)code].attr;
12929 const char *attr_string = "";
12931 gcc_assert (name != NULL);
12932 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
12934 if (rs6000_builtin_decls[(int)code])
12935 fatal_error (input_location,
12936 "internal error: builtin function %qs already processed",
12939 rs6000_builtin_decls[(int)code] = t =
12940 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
12942 /* Set any special attributes. */
12943 if ((classify & RS6000_BTC_CONST) != 0)
12945 /* const function, function only depends on the inputs. */
12946 TREE_READONLY (t) = 1;
12947 TREE_NOTHROW (t) = 1;
12948 attr_string = ", const";
12950 else if ((classify & RS6000_BTC_PURE) != 0)
12952 /* pure function, function can read global memory, but does not set any
12954 DECL_PURE_P (t) = 1;
12955 TREE_NOTHROW (t) = 1;
12956 attr_string = ", pure";
12958 else if ((classify & RS6000_BTC_FP) != 0)
12960 /* Function is a math function. If rounding mode is on, then treat the
12961 function as not reading global memory, but it can have arbitrary side
12962 effects. If it is off, then assume the function is a const function.
12963 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12964 builtin-attribute.def that is used for the math functions. */
12965 TREE_NOTHROW (t) = 1;
12966 if (flag_rounding_math)
12968 DECL_PURE_P (t) = 1;
12969 DECL_IS_NOVOPS (t) = 1;
12970 attr_string = ", fp, pure";
12974 TREE_READONLY (t) = 1;
12975 attr_string = ", fp, const";
12978 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
12979 gcc_unreachable ();
12981 if (TARGET_DEBUG_BUILTIN)
12982 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
12983 (int)code, name, attr_string);
12986 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
12988 #undef RS6000_BUILTIN_0
12989 #undef RS6000_BUILTIN_1
12990 #undef RS6000_BUILTIN_2
12991 #undef RS6000_BUILTIN_3
12992 #undef RS6000_BUILTIN_A
12993 #undef RS6000_BUILTIN_D
12994 #undef RS6000_BUILTIN_H
12995 #undef RS6000_BUILTIN_P
12996 #undef RS6000_BUILTIN_X
12998 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12999 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13000 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13001 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13002 { MASK, ICODE, NAME, ENUM },
13004 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13005 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13006 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13007 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13008 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13010 static const struct builtin_description bdesc_3arg[] =
13012 #include "rs6000-builtin.def"
13015 /* DST operations: void foo (void *, const int, const char). */
13017 #undef RS6000_BUILTIN_0
13018 #undef RS6000_BUILTIN_1
13019 #undef RS6000_BUILTIN_2
13020 #undef RS6000_BUILTIN_3
13021 #undef RS6000_BUILTIN_A
13022 #undef RS6000_BUILTIN_D
13023 #undef RS6000_BUILTIN_H
13024 #undef RS6000_BUILTIN_P
13025 #undef RS6000_BUILTIN_X
13027 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13028 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13029 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13030 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13031 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13032 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13033 { MASK, ICODE, NAME, ENUM },
13035 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13036 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13037 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13039 static const struct builtin_description bdesc_dst[] =
13041 #include "rs6000-builtin.def"
13044 /* Simple binary operations: VECc = foo (VECa, VECb). */
13046 #undef RS6000_BUILTIN_0
13047 #undef RS6000_BUILTIN_1
13048 #undef RS6000_BUILTIN_2
13049 #undef RS6000_BUILTIN_3
13050 #undef RS6000_BUILTIN_A
13051 #undef RS6000_BUILTIN_D
13052 #undef RS6000_BUILTIN_H
13053 #undef RS6000_BUILTIN_P
13054 #undef RS6000_BUILTIN_X
13056 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13057 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13058 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13059 { MASK, ICODE, NAME, ENUM },
13061 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13062 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13063 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13064 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13065 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13066 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13068 static const struct builtin_description bdesc_2arg[] =
13070 #include "rs6000-builtin.def"
13073 #undef RS6000_BUILTIN_0
13074 #undef RS6000_BUILTIN_1
13075 #undef RS6000_BUILTIN_2
13076 #undef RS6000_BUILTIN_3
13077 #undef RS6000_BUILTIN_A
13078 #undef RS6000_BUILTIN_D
13079 #undef RS6000_BUILTIN_H
13080 #undef RS6000_BUILTIN_P
13081 #undef RS6000_BUILTIN_X
13083 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13084 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13085 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13086 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13087 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13088 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13089 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13090 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13091 { MASK, ICODE, NAME, ENUM },
13093 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13095 /* AltiVec predicates. */
13097 static const struct builtin_description bdesc_altivec_preds[] =
13099 #include "rs6000-builtin.def"
13102 /* ABS* operations. */
13104 #undef RS6000_BUILTIN_0
13105 #undef RS6000_BUILTIN_1
13106 #undef RS6000_BUILTIN_2
13107 #undef RS6000_BUILTIN_3
13108 #undef RS6000_BUILTIN_A
13109 #undef RS6000_BUILTIN_D
13110 #undef RS6000_BUILTIN_H
13111 #undef RS6000_BUILTIN_P
13112 #undef RS6000_BUILTIN_X
13114 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13115 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13116 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13117 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13118 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13119 { MASK, ICODE, NAME, ENUM },
13121 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13122 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13123 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13124 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13126 static const struct builtin_description bdesc_abs[] =
13128 #include "rs6000-builtin.def"
13131 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13134 #undef RS6000_BUILTIN_0
13135 #undef RS6000_BUILTIN_1
13136 #undef RS6000_BUILTIN_2
13137 #undef RS6000_BUILTIN_3
13138 #undef RS6000_BUILTIN_A
13139 #undef RS6000_BUILTIN_D
13140 #undef RS6000_BUILTIN_H
13141 #undef RS6000_BUILTIN_P
13142 #undef RS6000_BUILTIN_X
13144 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13145 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13146 { MASK, ICODE, NAME, ENUM },
13148 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13149 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13150 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13151 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13152 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13153 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13154 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13156 static const struct builtin_description bdesc_1arg[] =
13158 #include "rs6000-builtin.def"
13161 /* Simple no-argument operations: result = __builtin_darn_32 () */
13163 #undef RS6000_BUILTIN_0
13164 #undef RS6000_BUILTIN_1
13165 #undef RS6000_BUILTIN_2
13166 #undef RS6000_BUILTIN_3
13167 #undef RS6000_BUILTIN_A
13168 #undef RS6000_BUILTIN_D
13169 #undef RS6000_BUILTIN_H
13170 #undef RS6000_BUILTIN_P
13171 #undef RS6000_BUILTIN_X
13173 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13174 { MASK, ICODE, NAME, ENUM },
13176 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13177 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13178 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13179 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13180 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13181 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13182 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13183 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13185 static const struct builtin_description bdesc_0arg[] =
13187 #include "rs6000-builtin.def"
13190 /* HTM builtins. */
13191 #undef RS6000_BUILTIN_0
13192 #undef RS6000_BUILTIN_1
13193 #undef RS6000_BUILTIN_2
13194 #undef RS6000_BUILTIN_3
13195 #undef RS6000_BUILTIN_A
13196 #undef RS6000_BUILTIN_D
13197 #undef RS6000_BUILTIN_H
13198 #undef RS6000_BUILTIN_P
13199 #undef RS6000_BUILTIN_X
13201 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13202 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13203 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13204 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13205 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13206 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13207 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13208 { MASK, ICODE, NAME, ENUM },
13210 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13211 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13213 static const struct builtin_description bdesc_htm[] =
13215 #include "rs6000-builtin.def"
13218 #undef RS6000_BUILTIN_0
13219 #undef RS6000_BUILTIN_1
13220 #undef RS6000_BUILTIN_2
13221 #undef RS6000_BUILTIN_3
13222 #undef RS6000_BUILTIN_A
13223 #undef RS6000_BUILTIN_D
13224 #undef RS6000_BUILTIN_H
13225 #undef RS6000_BUILTIN_P
13227 /* Return true if a builtin function is overloaded. */
13229 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13231 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13235 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13237 return rs6000_builtin_info[(int)fncode].name;
13240 /* Expand an expression EXP that calls a builtin without arguments. */
13242 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13245 machine_mode tmode = insn_data[icode].operand[0].mode;
13247 if (icode == CODE_FOR_nothing)
13248 /* Builtin not supported on this processor. */
13251 if (icode == CODE_FOR_rs6000_mffsl
13252 && rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
13254 error ("__builtin_mffsl() not supported with -msoft-float");
13259 || GET_MODE (target) != tmode
13260 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13261 target = gen_reg_rtx (tmode);
13263 pat = GEN_FCN (icode) (target);
13273 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13276 tree arg0 = CALL_EXPR_ARG (exp, 0);
13277 tree arg1 = CALL_EXPR_ARG (exp, 1);
13278 rtx op0 = expand_normal (arg0);
13279 rtx op1 = expand_normal (arg1);
13280 machine_mode mode0 = insn_data[icode].operand[0].mode;
13281 machine_mode mode1 = insn_data[icode].operand[1].mode;
13283 if (icode == CODE_FOR_nothing)
13284 /* Builtin not supported on this processor. */
13287 /* If we got invalid arguments bail out before generating bad rtl. */
13288 if (arg0 == error_mark_node || arg1 == error_mark_node)
13291 if (GET_CODE (op0) != CONST_INT
13292 || INTVAL (op0) > 255
13293 || INTVAL (op0) < 0)
13295 error ("argument 1 must be an 8-bit field value");
13299 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13300 op0 = copy_to_mode_reg (mode0, op0);
13302 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13303 op1 = copy_to_mode_reg (mode1, op1);
13305 pat = GEN_FCN (icode) (op0, op1);
13314 rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
13317 tree arg0 = CALL_EXPR_ARG (exp, 0);
13318 rtx op0 = expand_normal (arg0);
13320 if (icode == CODE_FOR_nothing)
13321 /* Builtin not supported on this processor. */
13324 if (rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
13326 error ("__builtin_mtfsb0 and __builtin_mtfsb1 not supported with -msoft-float");
13330 /* If we got invalid arguments bail out before generating bad rtl. */
13331 if (arg0 == error_mark_node)
13334 /* Only allow bit numbers 0 to 31. */
13335 if (!u5bit_cint_operand (op0, VOIDmode))
13337 error ("Argument must be a constant between 0 and 31.");
13341 pat = GEN_FCN (icode) (op0);
13350 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
13353 tree arg0 = CALL_EXPR_ARG (exp, 0);
13354 rtx op0 = expand_normal (arg0);
13355 machine_mode mode0 = insn_data[icode].operand[0].mode;
13357 if (icode == CODE_FOR_nothing)
13358 /* Builtin not supported on this processor. */
13361 if (rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
13363 error ("__builtin_set_fpscr_rn not supported with -msoft-float");
13367 /* If we got invalid arguments bail out before generating bad rtl. */
13368 if (arg0 == error_mark_node)
13371 /* If the argument is a constant, check the range. Argument can only be a
13372 2-bit value. Unfortunately, can't check the range of the value at
13373 compile time if the argument is a variable. The least significant two
13374 bits of the argument, regardless of type, are used to set the rounding
13375 mode. All other bits are ignored. */
13376 if (GET_CODE (op0) == CONST_INT && !const_0_to_3_operand(op0, VOIDmode))
13378 error ("Argument must be a value between 0 and 3.");
13382 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13383 op0 = copy_to_mode_reg (mode0, op0);
13385 pat = GEN_FCN (icode) (op0);
13393 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
13396 tree arg0 = CALL_EXPR_ARG (exp, 0);
13397 rtx op0 = expand_normal (arg0);
13398 machine_mode mode0 = insn_data[icode].operand[0].mode;
13401 /* Builtin not supported in 32-bit mode. */
13402 fatal_error (input_location,
13403 "__builtin_set_fpscr_drn is not supported in 32-bit mode.");
13405 if (rs6000_isa_flags_explicit & OPTION_MASK_SOFT_FLOAT)
13407 error ("__builtin_set_fpscr_drn not supported with -msoft-float");
13411 if (icode == CODE_FOR_nothing)
13412 /* Builtin not supported on this processor. */
13415 /* If we got invalid arguments bail out before generating bad rtl. */
13416 if (arg0 == error_mark_node)
13419 /* If the argument is a constant, check the range. Agrument can only be a
13420 3-bit value. Unfortunately, can't check the range of the value at
13421 compile time if the argument is a variable. The least significant two
13422 bits of the argument, regardless of type, are used to set the rounding
13423 mode. All other bits are ignored. */
13424 if (GET_CODE (op0) == CONST_INT && !const_0_to_7_operand(op0, VOIDmode))
13426 error ("Argument must be a value between 0 and 7.");
13430 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13431 op0 = copy_to_mode_reg (mode0, op0);
13433 pat = GEN_FCN (icode) (op0);
13442 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13445 tree arg0 = CALL_EXPR_ARG (exp, 0);
13446 rtx op0 = expand_normal (arg0);
13447 machine_mode tmode = insn_data[icode].operand[0].mode;
13448 machine_mode mode0 = insn_data[icode].operand[1].mode;
13450 if (icode == CODE_FOR_nothing)
13451 /* Builtin not supported on this processor. */
13454 /* If we got invalid arguments bail out before generating bad rtl. */
13455 if (arg0 == error_mark_node)
13458 if (icode == CODE_FOR_altivec_vspltisb
13459 || icode == CODE_FOR_altivec_vspltish
13460 || icode == CODE_FOR_altivec_vspltisw)
13462 /* Only allow 5-bit *signed* literals. */
13463 if (GET_CODE (op0) != CONST_INT
13464 || INTVAL (op0) > 15
13465 || INTVAL (op0) < -16)
13467 error ("argument 1 must be a 5-bit signed literal");
13468 return CONST0_RTX (tmode);
13473 || GET_MODE (target) != tmode
13474 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13475 target = gen_reg_rtx (tmode);
13477 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13478 op0 = copy_to_mode_reg (mode0, op0);
13480 pat = GEN_FCN (icode) (target, op0);
13489 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13491 rtx pat, scratch1, scratch2;
13492 tree arg0 = CALL_EXPR_ARG (exp, 0);
13493 rtx op0 = expand_normal (arg0);
13494 machine_mode tmode = insn_data[icode].operand[0].mode;
13495 machine_mode mode0 = insn_data[icode].operand[1].mode;
13497 /* If we have invalid arguments, bail out before generating bad rtl. */
13498 if (arg0 == error_mark_node)
13502 || GET_MODE (target) != tmode
13503 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13504 target = gen_reg_rtx (tmode);
13506 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13507 op0 = copy_to_mode_reg (mode0, op0);
13509 scratch1 = gen_reg_rtx (mode0);
13510 scratch2 = gen_reg_rtx (mode0);
13512 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13521 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13524 tree arg0 = CALL_EXPR_ARG (exp, 0);
13525 tree arg1 = CALL_EXPR_ARG (exp, 1);
13526 rtx op0 = expand_normal (arg0);
13527 rtx op1 = expand_normal (arg1);
13528 machine_mode tmode = insn_data[icode].operand[0].mode;
13529 machine_mode mode0 = insn_data[icode].operand[1].mode;
13530 machine_mode mode1 = insn_data[icode].operand[2].mode;
13532 if (icode == CODE_FOR_nothing)
13533 /* Builtin not supported on this processor. */
13536 /* If we got invalid arguments bail out before generating bad rtl. */
13537 if (arg0 == error_mark_node || arg1 == error_mark_node)
13540 if (icode == CODE_FOR_unpackv1ti
13541 || icode == CODE_FOR_unpackkf
13542 || icode == CODE_FOR_unpacktf
13543 || icode == CODE_FOR_unpackif
13544 || icode == CODE_FOR_unpacktd)
13546 /* Only allow 1-bit unsigned literals. */
13548 if (TREE_CODE (arg1) != INTEGER_CST
13549 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13551 error ("argument 2 must be a 1-bit unsigned literal");
13552 return CONST0_RTX (tmode);
13555 else if (icode == CODE_FOR_altivec_vspltw)
13557 /* Only allow 2-bit unsigned literals. */
13559 if (TREE_CODE (arg1) != INTEGER_CST
13560 || TREE_INT_CST_LOW (arg1) & ~3)
13562 error ("argument 2 must be a 2-bit unsigned literal");
13563 return CONST0_RTX (tmode);
13566 else if (icode == CODE_FOR_altivec_vsplth)
13568 /* Only allow 3-bit unsigned literals. */
13570 if (TREE_CODE (arg1) != INTEGER_CST
13571 || TREE_INT_CST_LOW (arg1) & ~7)
13573 error ("argument 2 must be a 3-bit unsigned literal");
13574 return CONST0_RTX (tmode);
13577 else if (icode == CODE_FOR_altivec_vspltb)
13579 /* Only allow 4-bit unsigned literals. */
13581 if (TREE_CODE (arg1) != INTEGER_CST
13582 || TREE_INT_CST_LOW (arg1) & ~15)
13584 error ("argument 2 must be a 4-bit unsigned literal");
13585 return CONST0_RTX (tmode);
13588 else if (icode == CODE_FOR_altivec_vcfux
13589 || icode == CODE_FOR_altivec_vcfsx
13590 || icode == CODE_FOR_altivec_vctsxs
13591 || icode == CODE_FOR_altivec_vctuxs)
13593 /* Only allow 5-bit unsigned literals. */
13595 if (TREE_CODE (arg1) != INTEGER_CST
13596 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13598 error ("argument 2 must be a 5-bit unsigned literal");
13599 return CONST0_RTX (tmode);
13602 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13603 || icode == CODE_FOR_dfptstsfi_lt_dd
13604 || icode == CODE_FOR_dfptstsfi_gt_dd
13605 || icode == CODE_FOR_dfptstsfi_unordered_dd
13606 || icode == CODE_FOR_dfptstsfi_eq_td
13607 || icode == CODE_FOR_dfptstsfi_lt_td
13608 || icode == CODE_FOR_dfptstsfi_gt_td
13609 || icode == CODE_FOR_dfptstsfi_unordered_td)
13611 /* Only allow 6-bit unsigned literals. */
13613 if (TREE_CODE (arg0) != INTEGER_CST
13614 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13616 error ("argument 1 must be a 6-bit unsigned literal");
13617 return CONST0_RTX (tmode);
13620 else if (icode == CODE_FOR_xststdcqp_kf
13621 || icode == CODE_FOR_xststdcqp_tf
13622 || icode == CODE_FOR_xststdcdp
13623 || icode == CODE_FOR_xststdcsp
13624 || icode == CODE_FOR_xvtstdcdp
13625 || icode == CODE_FOR_xvtstdcsp)
13627 /* Only allow 7-bit unsigned literals. */
13629 if (TREE_CODE (arg1) != INTEGER_CST
13630 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13632 error ("argument 2 must be a 7-bit unsigned literal");
13633 return CONST0_RTX (tmode);
13638 || GET_MODE (target) != tmode
13639 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13640 target = gen_reg_rtx (tmode);
13642 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13643 op0 = copy_to_mode_reg (mode0, op0);
13644 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13645 op1 = copy_to_mode_reg (mode1, op1);
13647 pat = GEN_FCN (icode) (target, op0, op1);
13656 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13659 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13660 tree arg0 = CALL_EXPR_ARG (exp, 1);
13661 tree arg1 = CALL_EXPR_ARG (exp, 2);
13662 rtx op0 = expand_normal (arg0);
13663 rtx op1 = expand_normal (arg1);
13664 machine_mode tmode = SImode;
13665 machine_mode mode0 = insn_data[icode].operand[1].mode;
13666 machine_mode mode1 = insn_data[icode].operand[2].mode;
13669 if (TREE_CODE (cr6_form) != INTEGER_CST)
13671 error ("argument 1 of %qs must be a constant",
13672 "__builtin_altivec_predicate");
13676 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13678 gcc_assert (mode0 == mode1);
13680 /* If we have invalid arguments, bail out before generating bad rtl. */
13681 if (arg0 == error_mark_node || arg1 == error_mark_node)
13685 || GET_MODE (target) != tmode
13686 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13687 target = gen_reg_rtx (tmode);
13689 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13690 op0 = copy_to_mode_reg (mode0, op0);
13691 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13692 op1 = copy_to_mode_reg (mode1, op1);
13694 /* Note that for many of the relevant operations (e.g. cmpne or
13695 cmpeq) with float or double operands, it makes more sense for the
13696 mode of the allocated scratch register to select a vector of
13697 integer. But the choice to copy the mode of operand 0 was made
13698 long ago and there are no plans to change it. */
13699 scratch = gen_reg_rtx (mode0);
13701 pat = GEN_FCN (icode) (scratch, op0, op1);
13706 /* The vec_any* and vec_all* predicates use the same opcodes for two
13707 different operations, but the bits in CR6 will be different
13708 depending on what information we want. So we have to play tricks
13709 with CR6 to get the right bits out.
13711 If you think this is disgusting, look at the specs for the
13712 AltiVec predicates. */
13714 switch (cr6_form_int)
13717 emit_insn (gen_cr6_test_for_zero (target));
13720 emit_insn (gen_cr6_test_for_zero_reverse (target));
13723 emit_insn (gen_cr6_test_for_lt (target));
13726 emit_insn (gen_cr6_test_for_lt_reverse (target));
13729 error ("argument 1 of %qs is out of range",
13730 "__builtin_altivec_predicate");
13738 swap_endian_selector_for_mode (machine_mode mode)
13740 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13741 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13742 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13743 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13745 unsigned int *swaparray, i;
13765 gcc_unreachable ();
13768 for (i = 0; i < 16; ++i)
13769 perm[i] = GEN_INT (swaparray[i]);
13771 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13772 gen_rtvec_v (16, perm)));
13776 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13779 tree arg0 = CALL_EXPR_ARG (exp, 0);
13780 tree arg1 = CALL_EXPR_ARG (exp, 1);
13781 machine_mode tmode = insn_data[icode].operand[0].mode;
13782 machine_mode mode0 = Pmode;
13783 machine_mode mode1 = Pmode;
13784 rtx op0 = expand_normal (arg0);
13785 rtx op1 = expand_normal (arg1);
13787 if (icode == CODE_FOR_nothing)
13788 /* Builtin not supported on this processor. */
13791 /* If we got invalid arguments bail out before generating bad rtl. */
13792 if (arg0 == error_mark_node || arg1 == error_mark_node)
13796 || GET_MODE (target) != tmode
13797 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13798 target = gen_reg_rtx (tmode);
13800 op1 = copy_to_mode_reg (mode1, op1);
13802 /* For LVX, express the RTL accurately by ANDing the address with -16.
13803 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13804 so the raw address is fine. */
13805 if (icode == CODE_FOR_altivec_lvx_v1ti
13806 || icode == CODE_FOR_altivec_lvx_v2df
13807 || icode == CODE_FOR_altivec_lvx_v2di
13808 || icode == CODE_FOR_altivec_lvx_v4sf
13809 || icode == CODE_FOR_altivec_lvx_v4si
13810 || icode == CODE_FOR_altivec_lvx_v8hi
13811 || icode == CODE_FOR_altivec_lvx_v16qi)
13814 if (op0 == const0_rtx)
13818 op0 = copy_to_mode_reg (mode0, op0);
13819 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
13821 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13822 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
13824 emit_insn (gen_rtx_SET (target, addr));
13828 if (op0 == const0_rtx)
13829 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
13832 op0 = copy_to_mode_reg (mode0, op0);
13833 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
13834 gen_rtx_PLUS (Pmode, op1, op0));
13837 pat = GEN_FCN (icode) (target, addr);
13847 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
13850 tree arg0 = CALL_EXPR_ARG (exp, 0);
13851 tree arg1 = CALL_EXPR_ARG (exp, 1);
13852 tree arg2 = CALL_EXPR_ARG (exp, 2);
13853 rtx op0 = expand_normal (arg0);
13854 rtx op1 = expand_normal (arg1);
13855 rtx op2 = expand_normal (arg2);
13856 machine_mode mode0 = insn_data[icode].operand[0].mode;
13857 machine_mode mode1 = insn_data[icode].operand[1].mode;
13858 machine_mode mode2 = insn_data[icode].operand[2].mode;
13860 if (icode == CODE_FOR_nothing)
13861 /* Builtin not supported on this processor. */
13864 /* If we got invalid arguments bail out before generating bad rtl. */
13865 if (arg0 == error_mark_node
13866 || arg1 == error_mark_node
13867 || arg2 == error_mark_node)
13870 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13871 op0 = copy_to_mode_reg (mode0, op0);
13872 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13873 op1 = copy_to_mode_reg (mode1, op1);
13874 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13875 op2 = copy_to_mode_reg (mode2, op2);
13877 pat = GEN_FCN (icode) (op0, op1, op2);
13885 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
13887 tree arg0 = CALL_EXPR_ARG (exp, 0);
13888 tree arg1 = CALL_EXPR_ARG (exp, 1);
13889 tree arg2 = CALL_EXPR_ARG (exp, 2);
13890 rtx op0 = expand_normal (arg0);
13891 rtx op1 = expand_normal (arg1);
13892 rtx op2 = expand_normal (arg2);
13893 rtx pat, addr, rawaddr;
13894 machine_mode tmode = insn_data[icode].operand[0].mode;
13895 machine_mode smode = insn_data[icode].operand[1].mode;
13896 machine_mode mode1 = Pmode;
13897 machine_mode mode2 = Pmode;
13899 /* Invalid arguments. Bail before doing anything stoopid! */
13900 if (arg0 == error_mark_node
13901 || arg1 == error_mark_node
13902 || arg2 == error_mark_node)
13905 op2 = copy_to_mode_reg (mode2, op2);
13907 /* For STVX, express the RTL accurately by ANDing the address with -16.
13908 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13909 so the raw address is fine. */
13910 if (icode == CODE_FOR_altivec_stvx_v2df
13911 || icode == CODE_FOR_altivec_stvx_v2di
13912 || icode == CODE_FOR_altivec_stvx_v4sf
13913 || icode == CODE_FOR_altivec_stvx_v4si
13914 || icode == CODE_FOR_altivec_stvx_v8hi
13915 || icode == CODE_FOR_altivec_stvx_v16qi)
13917 if (op1 == const0_rtx)
13921 op1 = copy_to_mode_reg (mode1, op1);
13922 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
13925 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13926 addr = gen_rtx_MEM (tmode, addr);
13928 op0 = copy_to_mode_reg (tmode, op0);
13930 emit_insn (gen_rtx_SET (addr, op0));
13934 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
13935 op0 = copy_to_mode_reg (smode, op0);
13937 if (op1 == const0_rtx)
13938 addr = gen_rtx_MEM (tmode, op2);
13941 op1 = copy_to_mode_reg (mode1, op1);
13942 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
13945 pat = GEN_FCN (icode) (addr, op0);
13953 /* Return the appropriate SPR number associated with the given builtin. */
13954 static inline HOST_WIDE_INT
13955 htm_spr_num (enum rs6000_builtins code)
13957 if (code == HTM_BUILTIN_GET_TFHAR
13958 || code == HTM_BUILTIN_SET_TFHAR)
13960 else if (code == HTM_BUILTIN_GET_TFIAR
13961 || code == HTM_BUILTIN_SET_TFIAR)
13963 else if (code == HTM_BUILTIN_GET_TEXASR
13964 || code == HTM_BUILTIN_SET_TEXASR)
13966 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
13967 || code == HTM_BUILTIN_SET_TEXASRU);
13968 return TEXASRU_SPR;
13971 /* Return the appropriate SPR regno associated with the given builtin. */
13972 static inline HOST_WIDE_INT
13973 htm_spr_regno (enum rs6000_builtins code)
13975 if (code == HTM_BUILTIN_GET_TFHAR
13976 || code == HTM_BUILTIN_SET_TFHAR)
13977 return TFHAR_REGNO;
13978 else if (code == HTM_BUILTIN_GET_TFIAR
13979 || code == HTM_BUILTIN_SET_TFIAR)
13980 return TFIAR_REGNO;
13981 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
13982 || code == HTM_BUILTIN_SET_TEXASR
13983 || code == HTM_BUILTIN_GET_TEXASRU
13984 || code == HTM_BUILTIN_SET_TEXASRU);
13985 return TEXASR_REGNO;
13988 /* Return the correct ICODE value depending on whether we are
13989 setting or reading the HTM SPRs. */
13990 static inline enum insn_code
13991 rs6000_htm_spr_icode (bool nonvoid)
13994 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
13996 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
13999 /* Expand the HTM builtin in EXP and store the result in TARGET.
14000 Store true in *EXPANDEDP if we found a builtin to expand. */
14002 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14004 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14005 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14006 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14007 const struct builtin_description *d;
14012 if (!TARGET_POWERPC64
14013 && (fcode == HTM_BUILTIN_TABORTDC
14014 || fcode == HTM_BUILTIN_TABORTDCI))
14016 size_t uns_fcode = (size_t)fcode;
14017 const char *name = rs6000_builtin_info[uns_fcode].name;
14018 error ("builtin %qs is only valid in 64-bit mode", name);
14022 /* Expand the HTM builtins. */
14024 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14025 if (d->code == fcode)
14027 rtx op[MAX_HTM_OPERANDS], pat;
14030 call_expr_arg_iterator iter;
14031 unsigned attr = rs6000_builtin_info[fcode].attr;
14032 enum insn_code icode = d->icode;
14033 const struct insn_operand_data *insn_op;
14034 bool uses_spr = (attr & RS6000_BTC_SPR);
14038 icode = rs6000_htm_spr_icode (nonvoid);
14039 insn_op = &insn_data[icode].operand[0];
14043 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14045 || GET_MODE (target) != tmode
14046 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14047 target = gen_reg_rtx (tmode);
14049 op[nopnds++] = target;
14052 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14054 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14057 insn_op = &insn_data[icode].operand[nopnds];
14059 op[nopnds] = expand_normal (arg);
14061 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14063 if (!strcmp (insn_op->constraint, "n"))
14065 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14066 if (!CONST_INT_P (op[nopnds]))
14067 error ("argument %d must be an unsigned literal", arg_num);
14069 error ("argument %d is an unsigned literal that is "
14070 "out of range", arg_num);
14073 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14079 /* Handle the builtins for extended mnemonics. These accept
14080 no arguments, but map to builtins that take arguments. */
14083 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14084 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14085 op[nopnds++] = GEN_INT (1);
14087 attr |= RS6000_BTC_UNARY;
14089 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14090 op[nopnds++] = GEN_INT (0);
14092 attr |= RS6000_BTC_UNARY;
14098 /* If this builtin accesses SPRs, then pass in the appropriate
14099 SPR number and SPR regno as the last two operands. */
14102 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14103 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14104 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14106 /* If this builtin accesses a CR, then pass in a scratch
14107 CR as the last operand. */
14108 else if (attr & RS6000_BTC_CR)
14109 { cr = gen_reg_rtx (CCmode);
14115 int expected_nopnds = 0;
14116 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14117 expected_nopnds = 1;
14118 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14119 expected_nopnds = 2;
14120 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14121 expected_nopnds = 3;
14122 if (!(attr & RS6000_BTC_VOID))
14123 expected_nopnds += 1;
14125 expected_nopnds += 2;
14127 gcc_assert (nopnds == expected_nopnds
14128 && nopnds <= MAX_HTM_OPERANDS);
14134 pat = GEN_FCN (icode) (op[0]);
14137 pat = GEN_FCN (icode) (op[0], op[1]);
14140 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14143 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14146 gcc_unreachable ();
14152 if (attr & RS6000_BTC_CR)
14154 if (fcode == HTM_BUILTIN_TBEGIN)
14156 /* Emit code to set TARGET to true or false depending on
14157 whether the tbegin. instruction successfully or failed
14158 to start a transaction. We do this by placing the 1's
14159 complement of CR's EQ bit into TARGET. */
14160 rtx scratch = gen_reg_rtx (SImode);
14161 emit_insn (gen_rtx_SET (scratch,
14162 gen_rtx_EQ (SImode, cr,
14164 emit_insn (gen_rtx_SET (target,
14165 gen_rtx_XOR (SImode, scratch,
14170 /* Emit code to copy the 4-bit condition register field
14171 CR into the least significant end of register TARGET. */
14172 rtx scratch1 = gen_reg_rtx (SImode);
14173 rtx scratch2 = gen_reg_rtx (SImode);
14174 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14175 emit_insn (gen_movcc (subreg, cr));
14176 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14177 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14186 *expandedp = false;
14190 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14193 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14196 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14197 if (fcode == RS6000_BUILTIN_CPU_INIT)
14200 if (target == 0 || GET_MODE (target) != SImode)
14201 target = gen_reg_rtx (SImode);
14203 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14204 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14205 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14206 to a STRING_CST. */
14207 if (TREE_CODE (arg) == ARRAY_REF
14208 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14209 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14210 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14211 arg = TREE_OPERAND (arg, 0);
14213 if (TREE_CODE (arg) != STRING_CST)
14215 error ("builtin %qs only accepts a string argument",
14216 rs6000_builtin_info[(size_t) fcode].name);
14220 if (fcode == RS6000_BUILTIN_CPU_IS)
14222 const char *cpu = TREE_STRING_POINTER (arg);
14223 rtx cpuid = NULL_RTX;
14224 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14225 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14227 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14228 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
14231 if (cpuid == NULL_RTX)
14233 /* Invalid CPU argument. */
14234 error ("cpu %qs is an invalid argument to builtin %qs",
14235 cpu, rs6000_builtin_info[(size_t) fcode].name);
14239 rtx platform = gen_reg_rtx (SImode);
14240 rtx tcbmem = gen_const_mem (SImode,
14241 gen_rtx_PLUS (Pmode,
14242 gen_rtx_REG (Pmode, TLS_REGNUM),
14243 GEN_INT (TCB_PLATFORM_OFFSET)));
14244 emit_move_insn (platform, tcbmem);
14245 emit_insn (gen_eqsi3 (target, platform, cpuid));
14247 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14249 const char *hwcap = TREE_STRING_POINTER (arg);
14250 rtx mask = NULL_RTX;
14252 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14253 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14255 mask = GEN_INT (cpu_supports_info[i].mask);
14256 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14259 if (mask == NULL_RTX)
14261 /* Invalid HWCAP argument. */
14262 error ("%s %qs is an invalid argument to builtin %qs",
14263 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14267 rtx tcb_hwcap = gen_reg_rtx (SImode);
14268 rtx tcbmem = gen_const_mem (SImode,
14269 gen_rtx_PLUS (Pmode,
14270 gen_rtx_REG (Pmode, TLS_REGNUM),
14271 GEN_INT (hwcap_offset)));
14272 emit_move_insn (tcb_hwcap, tcbmem);
14273 rtx scratch1 = gen_reg_rtx (SImode);
14274 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14275 rtx scratch2 = gen_reg_rtx (SImode);
14276 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14277 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14280 gcc_unreachable ();
14282 /* Record that we have expanded a CPU builtin, so that we can later
14283 emit a reference to the special symbol exported by LIBC to ensure we
14284 do not link against an old LIBC that doesn't support this feature. */
14285 cpu_builtin_p = true;
14288 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14289 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14291 /* For old LIBCs, always return FALSE. */
14292 emit_move_insn (target, GEN_INT (0));
14293 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14299 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14302 tree arg0 = CALL_EXPR_ARG (exp, 0);
14303 tree arg1 = CALL_EXPR_ARG (exp, 1);
14304 tree arg2 = CALL_EXPR_ARG (exp, 2);
14305 rtx op0 = expand_normal (arg0);
14306 rtx op1 = expand_normal (arg1);
14307 rtx op2 = expand_normal (arg2);
14308 machine_mode tmode = insn_data[icode].operand[0].mode;
14309 machine_mode mode0 = insn_data[icode].operand[1].mode;
14310 machine_mode mode1 = insn_data[icode].operand[2].mode;
14311 machine_mode mode2 = insn_data[icode].operand[3].mode;
14313 if (icode == CODE_FOR_nothing)
14314 /* Builtin not supported on this processor. */
14317 /* If we got invalid arguments bail out before generating bad rtl. */
14318 if (arg0 == error_mark_node
14319 || arg1 == error_mark_node
14320 || arg2 == error_mark_node)
14323 /* Check and prepare argument depending on the instruction code.
14325 Note that a switch statement instead of the sequence of tests
14326 would be incorrect as many of the CODE_FOR values could be
14327 CODE_FOR_nothing and that would yield multiple alternatives
14328 with identical values. We'd never reach here at runtime in
14330 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14331 || icode == CODE_FOR_altivec_vsldoi_v2df
14332 || icode == CODE_FOR_altivec_vsldoi_v4si
14333 || icode == CODE_FOR_altivec_vsldoi_v8hi
14334 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14336 /* Only allow 4-bit unsigned literals. */
14338 if (TREE_CODE (arg2) != INTEGER_CST
14339 || TREE_INT_CST_LOW (arg2) & ~0xf)
14341 error ("argument 3 must be a 4-bit unsigned literal");
14342 return CONST0_RTX (tmode);
14345 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14346 || icode == CODE_FOR_vsx_xxpermdi_v2di
14347 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14348 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14349 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14350 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14351 || icode == CODE_FOR_vsx_xxpermdi_v4si
14352 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14353 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14354 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14355 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14356 || icode == CODE_FOR_vsx_xxsldwi_v4si
14357 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14358 || icode == CODE_FOR_vsx_xxsldwi_v2di
14359 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14361 /* Only allow 2-bit unsigned literals. */
14363 if (TREE_CODE (arg2) != INTEGER_CST
14364 || TREE_INT_CST_LOW (arg2) & ~0x3)
14366 error ("argument 3 must be a 2-bit unsigned literal");
14367 return CONST0_RTX (tmode);
14370 else if (icode == CODE_FOR_vsx_set_v2df
14371 || icode == CODE_FOR_vsx_set_v2di
14372 || icode == CODE_FOR_bcdadd
14373 || icode == CODE_FOR_bcdadd_lt
14374 || icode == CODE_FOR_bcdadd_eq
14375 || icode == CODE_FOR_bcdadd_gt
14376 || icode == CODE_FOR_bcdsub
14377 || icode == CODE_FOR_bcdsub_lt
14378 || icode == CODE_FOR_bcdsub_eq
14379 || icode == CODE_FOR_bcdsub_gt)
14381 /* Only allow 1-bit unsigned literals. */
14383 if (TREE_CODE (arg2) != INTEGER_CST
14384 || TREE_INT_CST_LOW (arg2) & ~0x1)
14386 error ("argument 3 must be a 1-bit unsigned literal");
14387 return CONST0_RTX (tmode);
14390 else if (icode == CODE_FOR_dfp_ddedpd_dd
14391 || icode == CODE_FOR_dfp_ddedpd_td)
14393 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14395 if (TREE_CODE (arg0) != INTEGER_CST
14396 || TREE_INT_CST_LOW (arg2) & ~0x3)
14398 error ("argument 1 must be 0 or 2");
14399 return CONST0_RTX (tmode);
14402 else if (icode == CODE_FOR_dfp_denbcd_dd
14403 || icode == CODE_FOR_dfp_denbcd_td)
14405 /* Only allow 1-bit unsigned literals. */
14407 if (TREE_CODE (arg0) != INTEGER_CST
14408 || TREE_INT_CST_LOW (arg0) & ~0x1)
14410 error ("argument 1 must be a 1-bit unsigned literal");
14411 return CONST0_RTX (tmode);
14414 else if (icode == CODE_FOR_dfp_dscli_dd
14415 || icode == CODE_FOR_dfp_dscli_td
14416 || icode == CODE_FOR_dfp_dscri_dd
14417 || icode == CODE_FOR_dfp_dscri_td)
14419 /* Only allow 6-bit unsigned literals. */
14421 if (TREE_CODE (arg1) != INTEGER_CST
14422 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14424 error ("argument 2 must be a 6-bit unsigned literal");
14425 return CONST0_RTX (tmode);
14428 else if (icode == CODE_FOR_crypto_vshasigmaw
14429 || icode == CODE_FOR_crypto_vshasigmad)
14431 /* Check whether the 2nd and 3rd arguments are integer constants and in
14432 range and prepare arguments. */
14434 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14436 error ("argument 2 must be 0 or 1");
14437 return CONST0_RTX (tmode);
14441 if (TREE_CODE (arg2) != INTEGER_CST
14442 || wi::geu_p (wi::to_wide (arg2), 16))
14444 error ("argument 3 must be in the range 0..15");
14445 return CONST0_RTX (tmode);
14450 || GET_MODE (target) != tmode
14451 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14452 target = gen_reg_rtx (tmode);
14454 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14455 op0 = copy_to_mode_reg (mode0, op0);
14456 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14457 op1 = copy_to_mode_reg (mode1, op1);
14458 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14459 op2 = copy_to_mode_reg (mode2, op2);
14461 pat = GEN_FCN (icode) (target, op0, op1, op2);
14470 /* Expand the dst builtins. */
14472 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14475 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14476 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14477 tree arg0, arg1, arg2;
14478 machine_mode mode0, mode1;
14479 rtx pat, op0, op1, op2;
14480 const struct builtin_description *d;
14483 *expandedp = false;
14485 /* Handle DST variants. */
14487 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14488 if (d->code == fcode)
14490 arg0 = CALL_EXPR_ARG (exp, 0);
14491 arg1 = CALL_EXPR_ARG (exp, 1);
14492 arg2 = CALL_EXPR_ARG (exp, 2);
14493 op0 = expand_normal (arg0);
14494 op1 = expand_normal (arg1);
14495 op2 = expand_normal (arg2);
14496 mode0 = insn_data[d->icode].operand[0].mode;
14497 mode1 = insn_data[d->icode].operand[1].mode;
14499 /* Invalid arguments, bail out before generating bad rtl. */
14500 if (arg0 == error_mark_node
14501 || arg1 == error_mark_node
14502 || arg2 == error_mark_node)
14507 if (TREE_CODE (arg2) != INTEGER_CST
14508 || TREE_INT_CST_LOW (arg2) & ~0x3)
14510 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14514 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14515 op0 = copy_to_mode_reg (Pmode, op0);
14516 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14517 op1 = copy_to_mode_reg (mode1, op1);
14519 pat = GEN_FCN (d->icode) (op0, op1, op2);
14529 /* Expand vec_init builtin. */
14531 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14533 machine_mode tmode = TYPE_MODE (type);
14534 machine_mode inner_mode = GET_MODE_INNER (tmode);
14535 int i, n_elt = GET_MODE_NUNITS (tmode);
14537 gcc_assert (VECTOR_MODE_P (tmode));
14538 gcc_assert (n_elt == call_expr_nargs (exp));
14540 if (!target || !register_operand (target, tmode))
14541 target = gen_reg_rtx (tmode);
14543 /* If we have a vector compromised of a single element, such as V1TImode, do
14544 the initialization directly. */
14545 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14547 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14548 emit_move_insn (target, gen_lowpart (tmode, x));
14552 rtvec v = rtvec_alloc (n_elt);
14554 for (i = 0; i < n_elt; ++i)
14556 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14557 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14560 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14566 /* Return the integer constant in ARG. Constrain it to be in the range
14567 of the subparts of VEC_TYPE; issue an error if not. */
14570 get_element_number (tree vec_type, tree arg)
14572 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14574 if (!tree_fits_uhwi_p (arg)
14575 || (elt = tree_to_uhwi (arg), elt > max))
14577 error ("selector must be an integer constant in the range 0..%wi", max);
14584 /* Expand vec_set builtin. */
14586 altivec_expand_vec_set_builtin (tree exp)
14588 machine_mode tmode, mode1;
14589 tree arg0, arg1, arg2;
14593 arg0 = CALL_EXPR_ARG (exp, 0);
14594 arg1 = CALL_EXPR_ARG (exp, 1);
14595 arg2 = CALL_EXPR_ARG (exp, 2);
14597 tmode = TYPE_MODE (TREE_TYPE (arg0));
14598 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14599 gcc_assert (VECTOR_MODE_P (tmode));
14601 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14602 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14603 elt = get_element_number (TREE_TYPE (arg0), arg2);
14605 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14606 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14608 op0 = force_reg (tmode, op0);
14609 op1 = force_reg (mode1, op1);
14611 rs6000_expand_vector_set (op0, op1, elt);
14616 /* Expand vec_ext builtin. */
14618 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14620 machine_mode tmode, mode0;
14625 arg0 = CALL_EXPR_ARG (exp, 0);
14626 arg1 = CALL_EXPR_ARG (exp, 1);
14628 op0 = expand_normal (arg0);
14629 op1 = expand_normal (arg1);
14631 /* Call get_element_number to validate arg1 if it is a constant. */
14632 if (TREE_CODE (arg1) == INTEGER_CST)
14633 (void) get_element_number (TREE_TYPE (arg0), arg1);
14635 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14636 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14637 gcc_assert (VECTOR_MODE_P (mode0));
14639 op0 = force_reg (mode0, op0);
14641 if (optimize || !target || !register_operand (target, tmode))
14642 target = gen_reg_rtx (tmode);
14644 rs6000_expand_vector_extract (target, op0, op1);
14649 /* Expand the builtin in EXP and store the result in TARGET. Store
14650 true in *EXPANDEDP if we found a builtin to expand. */
14652 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14654 const struct builtin_description *d;
14656 enum insn_code icode;
14657 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14658 tree arg0, arg1, arg2;
14660 machine_mode tmode, mode0;
14661 enum rs6000_builtins fcode
14662 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14664 if (rs6000_overloaded_builtin_p (fcode))
14667 error ("unresolved overload for Altivec builtin %qF", fndecl);
14669 /* Given it is invalid, just generate a normal call. */
14670 return expand_call (exp, target, false);
14673 target = altivec_expand_dst_builtin (exp, target, expandedp);
14681 case ALTIVEC_BUILTIN_STVX_V2DF:
14682 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14683 case ALTIVEC_BUILTIN_STVX_V2DI:
14684 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14685 case ALTIVEC_BUILTIN_STVX_V4SF:
14686 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14687 case ALTIVEC_BUILTIN_STVX:
14688 case ALTIVEC_BUILTIN_STVX_V4SI:
14689 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14690 case ALTIVEC_BUILTIN_STVX_V8HI:
14691 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14692 case ALTIVEC_BUILTIN_STVX_V16QI:
14693 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14694 case ALTIVEC_BUILTIN_STVEBX:
14695 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14696 case ALTIVEC_BUILTIN_STVEHX:
14697 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14698 case ALTIVEC_BUILTIN_STVEWX:
14699 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14700 case ALTIVEC_BUILTIN_STVXL_V2DF:
14701 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14702 case ALTIVEC_BUILTIN_STVXL_V2DI:
14703 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14704 case ALTIVEC_BUILTIN_STVXL_V4SF:
14705 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14706 case ALTIVEC_BUILTIN_STVXL:
14707 case ALTIVEC_BUILTIN_STVXL_V4SI:
14708 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14709 case ALTIVEC_BUILTIN_STVXL_V8HI:
14710 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14711 case ALTIVEC_BUILTIN_STVXL_V16QI:
14712 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14714 case ALTIVEC_BUILTIN_STVLX:
14715 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14716 case ALTIVEC_BUILTIN_STVLXL:
14717 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14718 case ALTIVEC_BUILTIN_STVRX:
14719 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14720 case ALTIVEC_BUILTIN_STVRXL:
14721 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14723 case P9V_BUILTIN_STXVL:
14724 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14726 case P9V_BUILTIN_XST_LEN_R:
14727 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14729 case VSX_BUILTIN_STXVD2X_V1TI:
14730 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14731 case VSX_BUILTIN_STXVD2X_V2DF:
14732 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14733 case VSX_BUILTIN_STXVD2X_V2DI:
14734 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14735 case VSX_BUILTIN_STXVW4X_V4SF:
14736 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14737 case VSX_BUILTIN_STXVW4X_V4SI:
14738 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14739 case VSX_BUILTIN_STXVW4X_V8HI:
14740 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14741 case VSX_BUILTIN_STXVW4X_V16QI:
14742 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14744 /* For the following on big endian, it's ok to use any appropriate
14745 unaligned-supporting store, so use a generic expander. For
14746 little-endian, the exact element-reversing instruction must
14748 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14750 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14751 : CODE_FOR_vsx_st_elemrev_v1ti);
14752 return altivec_expand_stv_builtin (code, exp);
14754 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14756 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14757 : CODE_FOR_vsx_st_elemrev_v2df);
14758 return altivec_expand_stv_builtin (code, exp);
14760 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14762 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14763 : CODE_FOR_vsx_st_elemrev_v2di);
14764 return altivec_expand_stv_builtin (code, exp);
14766 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14768 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14769 : CODE_FOR_vsx_st_elemrev_v4sf);
14770 return altivec_expand_stv_builtin (code, exp);
14772 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14774 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14775 : CODE_FOR_vsx_st_elemrev_v4si);
14776 return altivec_expand_stv_builtin (code, exp);
14778 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14780 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14781 : CODE_FOR_vsx_st_elemrev_v8hi);
14782 return altivec_expand_stv_builtin (code, exp);
14784 case VSX_BUILTIN_ST_ELEMREV_V16QI:
14786 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
14787 : CODE_FOR_vsx_st_elemrev_v16qi);
14788 return altivec_expand_stv_builtin (code, exp);
14791 case ALTIVEC_BUILTIN_MFVSCR:
14792 icode = CODE_FOR_altivec_mfvscr;
14793 tmode = insn_data[icode].operand[0].mode;
14796 || GET_MODE (target) != tmode
14797 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14798 target = gen_reg_rtx (tmode);
14800 pat = GEN_FCN (icode) (target);
14806 case ALTIVEC_BUILTIN_MTVSCR:
14807 icode = CODE_FOR_altivec_mtvscr;
14808 arg0 = CALL_EXPR_ARG (exp, 0);
14809 op0 = expand_normal (arg0);
14810 mode0 = insn_data[icode].operand[0].mode;
14812 /* If we got invalid arguments bail out before generating bad rtl. */
14813 if (arg0 == error_mark_node)
14816 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14817 op0 = copy_to_mode_reg (mode0, op0);
14819 pat = GEN_FCN (icode) (op0);
14824 case ALTIVEC_BUILTIN_DSSALL:
14825 emit_insn (gen_altivec_dssall ());
14828 case ALTIVEC_BUILTIN_DSS:
14829 icode = CODE_FOR_altivec_dss;
14830 arg0 = CALL_EXPR_ARG (exp, 0);
14832 op0 = expand_normal (arg0);
14833 mode0 = insn_data[icode].operand[0].mode;
14835 /* If we got invalid arguments bail out before generating bad rtl. */
14836 if (arg0 == error_mark_node)
14839 if (TREE_CODE (arg0) != INTEGER_CST
14840 || TREE_INT_CST_LOW (arg0) & ~0x3)
14842 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14846 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14847 op0 = copy_to_mode_reg (mode0, op0);
14849 emit_insn (gen_altivec_dss (op0));
14852 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
14853 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
14854 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
14855 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
14856 case VSX_BUILTIN_VEC_INIT_V2DF:
14857 case VSX_BUILTIN_VEC_INIT_V2DI:
14858 case VSX_BUILTIN_VEC_INIT_V1TI:
14859 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
14861 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
14862 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
14863 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
14864 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
14865 case VSX_BUILTIN_VEC_SET_V2DF:
14866 case VSX_BUILTIN_VEC_SET_V2DI:
14867 case VSX_BUILTIN_VEC_SET_V1TI:
14868 return altivec_expand_vec_set_builtin (exp);
14870 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
14871 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
14872 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
14873 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
14874 case VSX_BUILTIN_VEC_EXT_V2DF:
14875 case VSX_BUILTIN_VEC_EXT_V2DI:
14876 case VSX_BUILTIN_VEC_EXT_V1TI:
14877 return altivec_expand_vec_ext_builtin (exp, target);
14879 case P9V_BUILTIN_VEC_EXTRACT4B:
14880 arg1 = CALL_EXPR_ARG (exp, 1);
14883 /* Generate a normal call if it is invalid. */
14884 if (arg1 == error_mark_node)
14885 return expand_call (exp, target, false);
14887 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
14889 error ("second argument to %qs must be 0..12", "vec_vextract4b");
14890 return expand_call (exp, target, false);
14894 case P9V_BUILTIN_VEC_INSERT4B:
14895 arg2 = CALL_EXPR_ARG (exp, 2);
14898 /* Generate a normal call if it is invalid. */
14899 if (arg2 == error_mark_node)
14900 return expand_call (exp, target, false);
14902 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
14904 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
14905 return expand_call (exp, target, false);
14911 /* Fall through. */
14914 /* Expand abs* operations. */
14916 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14917 if (d->code == fcode)
14918 return altivec_expand_abs_builtin (d->icode, exp, target);
14920 /* Expand the AltiVec predicates. */
14921 d = bdesc_altivec_preds;
14922 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14923 if (d->code == fcode)
14924 return altivec_expand_predicate_builtin (d->icode, exp, target);
14926 /* LV* are funky. We initialized them differently. */
14929 case ALTIVEC_BUILTIN_LVSL:
14930 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
14931 exp, target, false);
14932 case ALTIVEC_BUILTIN_LVSR:
14933 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
14934 exp, target, false);
14935 case ALTIVEC_BUILTIN_LVEBX:
14936 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
14937 exp, target, false);
14938 case ALTIVEC_BUILTIN_LVEHX:
14939 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
14940 exp, target, false);
14941 case ALTIVEC_BUILTIN_LVEWX:
14942 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
14943 exp, target, false);
14944 case ALTIVEC_BUILTIN_LVXL_V2DF:
14945 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
14946 exp, target, false);
14947 case ALTIVEC_BUILTIN_LVXL_V2DI:
14948 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
14949 exp, target, false);
14950 case ALTIVEC_BUILTIN_LVXL_V4SF:
14951 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
14952 exp, target, false);
14953 case ALTIVEC_BUILTIN_LVXL:
14954 case ALTIVEC_BUILTIN_LVXL_V4SI:
14955 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
14956 exp, target, false);
14957 case ALTIVEC_BUILTIN_LVXL_V8HI:
14958 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
14959 exp, target, false);
14960 case ALTIVEC_BUILTIN_LVXL_V16QI:
14961 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
14962 exp, target, false);
14963 case ALTIVEC_BUILTIN_LVX_V1TI:
14964 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
14965 exp, target, false);
14966 case ALTIVEC_BUILTIN_LVX_V2DF:
14967 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
14968 exp, target, false);
14969 case ALTIVEC_BUILTIN_LVX_V2DI:
14970 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
14971 exp, target, false);
14972 case ALTIVEC_BUILTIN_LVX_V4SF:
14973 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
14974 exp, target, false);
14975 case ALTIVEC_BUILTIN_LVX:
14976 case ALTIVEC_BUILTIN_LVX_V4SI:
14977 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
14978 exp, target, false);
14979 case ALTIVEC_BUILTIN_LVX_V8HI:
14980 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
14981 exp, target, false);
14982 case ALTIVEC_BUILTIN_LVX_V16QI:
14983 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
14984 exp, target, false);
14985 case ALTIVEC_BUILTIN_LVLX:
14986 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
14987 exp, target, true);
14988 case ALTIVEC_BUILTIN_LVLXL:
14989 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
14990 exp, target, true);
14991 case ALTIVEC_BUILTIN_LVRX:
14992 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
14993 exp, target, true);
14994 case ALTIVEC_BUILTIN_LVRXL:
14995 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
14996 exp, target, true);
14997 case VSX_BUILTIN_LXVD2X_V1TI:
14998 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
14999 exp, target, false);
15000 case VSX_BUILTIN_LXVD2X_V2DF:
15001 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15002 exp, target, false);
15003 case VSX_BUILTIN_LXVD2X_V2DI:
15004 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15005 exp, target, false);
15006 case VSX_BUILTIN_LXVW4X_V4SF:
15007 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15008 exp, target, false);
15009 case VSX_BUILTIN_LXVW4X_V4SI:
15010 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15011 exp, target, false);
15012 case VSX_BUILTIN_LXVW4X_V8HI:
15013 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15014 exp, target, false);
15015 case VSX_BUILTIN_LXVW4X_V16QI:
15016 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15017 exp, target, false);
15018 /* For the following on big endian, it's ok to use any appropriate
15019 unaligned-supporting load, so use a generic expander. For
15020 little-endian, the exact element-reversing instruction must
15022 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15024 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15025 : CODE_FOR_vsx_ld_elemrev_v2df);
15026 return altivec_expand_lv_builtin (code, exp, target, false);
15028 case VSX_BUILTIN_LD_ELEMREV_V1TI:
15030 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
15031 : CODE_FOR_vsx_ld_elemrev_v1ti);
15032 return altivec_expand_lv_builtin (code, exp, target, false);
15034 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15036 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15037 : CODE_FOR_vsx_ld_elemrev_v2di);
15038 return altivec_expand_lv_builtin (code, exp, target, false);
15040 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15042 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15043 : CODE_FOR_vsx_ld_elemrev_v4sf);
15044 return altivec_expand_lv_builtin (code, exp, target, false);
15046 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15048 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15049 : CODE_FOR_vsx_ld_elemrev_v4si);
15050 return altivec_expand_lv_builtin (code, exp, target, false);
15052 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15054 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15055 : CODE_FOR_vsx_ld_elemrev_v8hi);
15056 return altivec_expand_lv_builtin (code, exp, target, false);
15058 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15060 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15061 : CODE_FOR_vsx_ld_elemrev_v16qi);
15062 return altivec_expand_lv_builtin (code, exp, target, false);
15067 /* Fall through. */
15070 *expandedp = false;
15074 /* Check whether a builtin function is supported in this target
15077 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
15079 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
15080 if ((fnmask & rs6000_builtin_mask) != fnmask)
15086 /* Raise an error message for a builtin function that is called without the
15087 appropriate target options being set. */
15090 rs6000_invalid_builtin (enum rs6000_builtins fncode)
15092 size_t uns_fncode = (size_t) fncode;
15093 const char *name = rs6000_builtin_info[uns_fncode].name;
15094 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
15096 gcc_assert (name != NULL);
15097 if ((fnmask & RS6000_BTM_CELL) != 0)
15098 error ("builtin function %qs is only valid for the cell processor", name);
15099 else if ((fnmask & RS6000_BTM_VSX) != 0)
15100 error ("builtin function %qs requires the %qs option", name, "-mvsx");
15101 else if ((fnmask & RS6000_BTM_HTM) != 0)
15102 error ("builtin function %qs requires the %qs option", name, "-mhtm");
15103 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
15104 error ("builtin function %qs requires the %qs option", name, "-maltivec");
15105 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
15106 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
15107 error ("builtin function %qs requires the %qs and %qs options",
15108 name, "-mhard-dfp", "-mpower8-vector");
15109 else if ((fnmask & RS6000_BTM_DFP) != 0)
15110 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
15111 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
15112 error ("builtin function %qs requires the %qs option", name,
15113 "-mpower8-vector");
15114 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
15115 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
15116 error ("builtin function %qs requires the %qs and %qs options",
15117 name, "-mcpu=power9", "-m64");
15118 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
15119 error ("builtin function %qs requires the %qs option", name,
15121 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
15122 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
15123 error ("builtin function %qs requires the %qs and %qs options",
15124 name, "-mcpu=power9", "-m64");
15125 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
15126 error ("builtin function %qs requires the %qs option", name,
15128 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
15130 if (!TARGET_HARD_FLOAT)
15131 error ("builtin function %qs requires the %qs option", name,
15134 error ("builtin function %qs requires the %qs option", name,
15135 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
15137 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
15138 error ("builtin function %qs requires the %qs option", name,
15140 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
15141 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
15143 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
15144 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
15145 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
15146 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
15147 error ("builtin function %qs requires the %qs (or newer), and "
15148 "%qs or %qs options",
15149 name, "-mcpu=power7", "-m64", "-mpowerpc64");
15151 error ("builtin function %qs is not supported with the current options",
15155 /* Target hook for early folding of built-ins, shamelessly stolen
15159 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
15160 int n_args ATTRIBUTE_UNUSED,
15161 tree *args ATTRIBUTE_UNUSED,
15162 bool ignore ATTRIBUTE_UNUSED)
15164 #ifdef SUBTARGET_FOLD_BUILTIN
15165 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
15171 /* Helper function to sort out which built-ins may be valid without having
15174 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
15178 case ALTIVEC_BUILTIN_STVX_V16QI:
15179 case ALTIVEC_BUILTIN_STVX_V8HI:
15180 case ALTIVEC_BUILTIN_STVX_V4SI:
15181 case ALTIVEC_BUILTIN_STVX_V4SF:
15182 case ALTIVEC_BUILTIN_STVX_V2DI:
15183 case ALTIVEC_BUILTIN_STVX_V2DF:
15184 case VSX_BUILTIN_STXVW4X_V16QI:
15185 case VSX_BUILTIN_STXVW4X_V8HI:
15186 case VSX_BUILTIN_STXVW4X_V4SF:
15187 case VSX_BUILTIN_STXVW4X_V4SI:
15188 case VSX_BUILTIN_STXVD2X_V2DF:
15189 case VSX_BUILTIN_STXVD2X_V2DI:
15196 /* Helper function to handle the gimple folding of a vector compare
15197 operation. This sets up true/false vectors, and uses the
15198 VEC_COND_EXPR operation.
15199 CODE indicates which comparison is to be made. (EQ, GT, ...).
15200 TYPE indicates the type of the result. */
15202 fold_build_vec_cmp (tree_code code, tree type,
15203 tree arg0, tree arg1)
15205 tree cmp_type = build_same_sized_truth_vector_type (type);
15206 tree zero_vec = build_zero_cst (type);
15207 tree minus_one_vec = build_minus_one_cst (type);
15208 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
15209 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
15212 /* Helper function to handle the in-between steps for the
15213 vector compare built-ins. */
15215 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
15217 tree arg0 = gimple_call_arg (stmt, 0);
15218 tree arg1 = gimple_call_arg (stmt, 1);
15219 tree lhs = gimple_call_lhs (stmt);
15220 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
15221 gimple *g = gimple_build_assign (lhs, cmp);
15222 gimple_set_location (g, gimple_location (stmt));
15223 gsi_replace (gsi, g, true);
15226 /* Helper function to map V2DF and V4SF types to their
15227 integral equivalents (V2DI and V4SI). */
15228 tree map_to_integral_tree_type (tree input_tree_type)
15230 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
15231 return input_tree_type;
15234 if (types_compatible_p (TREE_TYPE (input_tree_type),
15235 TREE_TYPE (V2DF_type_node)))
15236 return V2DI_type_node;
15237 else if (types_compatible_p (TREE_TYPE (input_tree_type),
15238 TREE_TYPE (V4SF_type_node)))
15239 return V4SI_type_node;
15241 gcc_unreachable ();
15245 /* Helper function to handle the vector merge[hl] built-ins. The
15246 implementation difference between h and l versions for this code are in
15247 the values used when building of the permute vector for high word versus
15248 low word merge. The variance is keyed off the use_high parameter. */
15250 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
15252 tree arg0 = gimple_call_arg (stmt, 0);
15253 tree arg1 = gimple_call_arg (stmt, 1);
15254 tree lhs = gimple_call_lhs (stmt);
15255 tree lhs_type = TREE_TYPE (lhs);
15256 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15257 int midpoint = n_elts / 2;
15263 /* The permute_type will match the lhs for integral types. For double and
15264 float types, the permute type needs to map to the V2 or V4 type that
15267 permute_type = map_to_integral_tree_type (lhs_type);
15268 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15270 for (int i = 0; i < midpoint; i++)
15272 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15274 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15275 offset + n_elts + i));
15278 tree permute = elts.build ();
15280 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15281 gimple_set_location (g, gimple_location (stmt));
15282 gsi_replace (gsi, g, true);
15285 /* Helper function to handle the vector merge[eo] built-ins. */
15287 fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
15289 tree arg0 = gimple_call_arg (stmt, 0);
15290 tree arg1 = gimple_call_arg (stmt, 1);
15291 tree lhs = gimple_call_lhs (stmt);
15292 tree lhs_type = TREE_TYPE (lhs);
15293 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15295 /* The permute_type will match the lhs for integral types. For double and
15296 float types, the permute type needs to map to the V2 or V4 type that
15299 permute_type = map_to_integral_tree_type (lhs_type);
15301 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15303 /* Build the permute vector. */
15304 for (int i = 0; i < n_elts / 2; i++)
15306 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15308 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15309 2*i + use_odd + n_elts));
15312 tree permute = elts.build ();
15314 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15315 gimple_set_location (g, gimple_location (stmt));
15316 gsi_replace (gsi, g, true);
15319 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15320 a constant, use rs6000_fold_builtin.) */
15323 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15325 gimple *stmt = gsi_stmt (*gsi);
15326 tree fndecl = gimple_call_fndecl (stmt);
15327 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15328 enum rs6000_builtins fn_code
15329 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15330 tree arg0, arg1, lhs, temp;
15333 size_t uns_fncode = (size_t) fn_code;
15334 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15335 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15336 const char *fn_name2 = (icode != CODE_FOR_nothing)
15337 ? get_insn_name ((int) icode)
15340 if (TARGET_DEBUG_BUILTIN)
15341 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15342 fn_code, fn_name1, fn_name2);
15344 if (!rs6000_fold_gimple)
15347 /* Prevent gimple folding for code that does not have a LHS, unless it is
15348 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15349 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15352 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15353 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15354 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15360 /* Flavors of vec_add. We deliberately don't expand
15361 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15362 TImode, resulting in much poorer code generation. */
15363 case ALTIVEC_BUILTIN_VADDUBM:
15364 case ALTIVEC_BUILTIN_VADDUHM:
15365 case ALTIVEC_BUILTIN_VADDUWM:
15366 case P8V_BUILTIN_VADDUDM:
15367 case ALTIVEC_BUILTIN_VADDFP:
15368 case VSX_BUILTIN_XVADDDP:
15369 arg0 = gimple_call_arg (stmt, 0);
15370 arg1 = gimple_call_arg (stmt, 1);
15371 lhs = gimple_call_lhs (stmt);
15372 g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
15373 gimple_set_location (g, gimple_location (stmt));
15374 gsi_replace (gsi, g, true);
15376 /* Flavors of vec_sub. We deliberately don't expand
15377 P8V_BUILTIN_VSUBUQM. */
15378 case ALTIVEC_BUILTIN_VSUBUBM:
15379 case ALTIVEC_BUILTIN_VSUBUHM:
15380 case ALTIVEC_BUILTIN_VSUBUWM:
15381 case P8V_BUILTIN_VSUBUDM:
15382 case ALTIVEC_BUILTIN_VSUBFP:
15383 case VSX_BUILTIN_XVSUBDP:
15384 arg0 = gimple_call_arg (stmt, 0);
15385 arg1 = gimple_call_arg (stmt, 1);
15386 lhs = gimple_call_lhs (stmt);
15387 g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
15388 gimple_set_location (g, gimple_location (stmt));
15389 gsi_replace (gsi, g, true);
15391 case VSX_BUILTIN_XVMULSP:
15392 case VSX_BUILTIN_XVMULDP:
15393 arg0 = gimple_call_arg (stmt, 0);
15394 arg1 = gimple_call_arg (stmt, 1);
15395 lhs = gimple_call_lhs (stmt);
15396 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15397 gimple_set_location (g, gimple_location (stmt));
15398 gsi_replace (gsi, g, true);
15400 /* Even element flavors of vec_mul (signed). */
15401 case ALTIVEC_BUILTIN_VMULESB:
15402 case ALTIVEC_BUILTIN_VMULESH:
15403 case P8V_BUILTIN_VMULESW:
15404 /* Even element flavors of vec_mul (unsigned). */
15405 case ALTIVEC_BUILTIN_VMULEUB:
15406 case ALTIVEC_BUILTIN_VMULEUH:
15407 case P8V_BUILTIN_VMULEUW:
15408 arg0 = gimple_call_arg (stmt, 0);
15409 arg1 = gimple_call_arg (stmt, 1);
15410 lhs = gimple_call_lhs (stmt);
15411 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15412 gimple_set_location (g, gimple_location (stmt));
15413 gsi_replace (gsi, g, true);
15415 /* Odd element flavors of vec_mul (signed). */
15416 case ALTIVEC_BUILTIN_VMULOSB:
15417 case ALTIVEC_BUILTIN_VMULOSH:
15418 case P8V_BUILTIN_VMULOSW:
15419 /* Odd element flavors of vec_mul (unsigned). */
15420 case ALTIVEC_BUILTIN_VMULOUB:
15421 case ALTIVEC_BUILTIN_VMULOUH:
15422 case P8V_BUILTIN_VMULOUW:
15423 arg0 = gimple_call_arg (stmt, 0);
15424 arg1 = gimple_call_arg (stmt, 1);
15425 lhs = gimple_call_lhs (stmt);
15426 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15427 gimple_set_location (g, gimple_location (stmt));
15428 gsi_replace (gsi, g, true);
15430 /* Flavors of vec_div (Integer). */
15431 case VSX_BUILTIN_DIV_V2DI:
15432 case VSX_BUILTIN_UDIV_V2DI:
15433 arg0 = gimple_call_arg (stmt, 0);
15434 arg1 = gimple_call_arg (stmt, 1);
15435 lhs = gimple_call_lhs (stmt);
15436 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15437 gimple_set_location (g, gimple_location (stmt));
15438 gsi_replace (gsi, g, true);
15440 /* Flavors of vec_div (Float). */
15441 case VSX_BUILTIN_XVDIVSP:
15442 case VSX_BUILTIN_XVDIVDP:
15443 arg0 = gimple_call_arg (stmt, 0);
15444 arg1 = gimple_call_arg (stmt, 1);
15445 lhs = gimple_call_lhs (stmt);
15446 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15447 gimple_set_location (g, gimple_location (stmt));
15448 gsi_replace (gsi, g, true);
15450 /* Flavors of vec_and. */
15451 case ALTIVEC_BUILTIN_VAND:
15452 arg0 = gimple_call_arg (stmt, 0);
15453 arg1 = gimple_call_arg (stmt, 1);
15454 lhs = gimple_call_lhs (stmt);
15455 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15456 gimple_set_location (g, gimple_location (stmt));
15457 gsi_replace (gsi, g, true);
15459 /* Flavors of vec_andc. */
15460 case ALTIVEC_BUILTIN_VANDC:
15461 arg0 = gimple_call_arg (stmt, 0);
15462 arg1 = gimple_call_arg (stmt, 1);
15463 lhs = gimple_call_lhs (stmt);
15464 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15465 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15466 gimple_set_location (g, gimple_location (stmt));
15467 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15468 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15469 gimple_set_location (g, gimple_location (stmt));
15470 gsi_replace (gsi, g, true);
15472 /* Flavors of vec_nand. */
15473 case P8V_BUILTIN_VEC_NAND:
15474 case P8V_BUILTIN_NAND_V16QI:
15475 case P8V_BUILTIN_NAND_V8HI:
15476 case P8V_BUILTIN_NAND_V4SI:
15477 case P8V_BUILTIN_NAND_V4SF:
15478 case P8V_BUILTIN_NAND_V2DF:
15479 case P8V_BUILTIN_NAND_V2DI:
15480 arg0 = gimple_call_arg (stmt, 0);
15481 arg1 = gimple_call_arg (stmt, 1);
15482 lhs = gimple_call_lhs (stmt);
15483 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15484 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15485 gimple_set_location (g, gimple_location (stmt));
15486 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15487 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15488 gimple_set_location (g, gimple_location (stmt));
15489 gsi_replace (gsi, g, true);
15491 /* Flavors of vec_or. */
15492 case ALTIVEC_BUILTIN_VOR:
15493 arg0 = gimple_call_arg (stmt, 0);
15494 arg1 = gimple_call_arg (stmt, 1);
15495 lhs = gimple_call_lhs (stmt);
15496 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15497 gimple_set_location (g, gimple_location (stmt));
15498 gsi_replace (gsi, g, true);
15500 /* flavors of vec_orc. */
15501 case P8V_BUILTIN_ORC_V16QI:
15502 case P8V_BUILTIN_ORC_V8HI:
15503 case P8V_BUILTIN_ORC_V4SI:
15504 case P8V_BUILTIN_ORC_V4SF:
15505 case P8V_BUILTIN_ORC_V2DF:
15506 case P8V_BUILTIN_ORC_V2DI:
15507 arg0 = gimple_call_arg (stmt, 0);
15508 arg1 = gimple_call_arg (stmt, 1);
15509 lhs = gimple_call_lhs (stmt);
15510 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15511 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15512 gimple_set_location (g, gimple_location (stmt));
15513 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15514 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15515 gimple_set_location (g, gimple_location (stmt));
15516 gsi_replace (gsi, g, true);
15518 /* Flavors of vec_xor. */
15519 case ALTIVEC_BUILTIN_VXOR:
15520 arg0 = gimple_call_arg (stmt, 0);
15521 arg1 = gimple_call_arg (stmt, 1);
15522 lhs = gimple_call_lhs (stmt);
15523 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15524 gimple_set_location (g, gimple_location (stmt));
15525 gsi_replace (gsi, g, true);
15527 /* Flavors of vec_nor. */
15528 case ALTIVEC_BUILTIN_VNOR:
15529 arg0 = gimple_call_arg (stmt, 0);
15530 arg1 = gimple_call_arg (stmt, 1);
15531 lhs = gimple_call_lhs (stmt);
15532 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15533 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15534 gimple_set_location (g, gimple_location (stmt));
15535 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15536 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15537 gimple_set_location (g, gimple_location (stmt));
15538 gsi_replace (gsi, g, true);
15540 /* flavors of vec_abs. */
15541 case ALTIVEC_BUILTIN_ABS_V16QI:
15542 case ALTIVEC_BUILTIN_ABS_V8HI:
15543 case ALTIVEC_BUILTIN_ABS_V4SI:
15544 case ALTIVEC_BUILTIN_ABS_V4SF:
15545 case P8V_BUILTIN_ABS_V2DI:
15546 case VSX_BUILTIN_XVABSDP:
15547 arg0 = gimple_call_arg (stmt, 0);
15548 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15549 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15551 lhs = gimple_call_lhs (stmt);
15552 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15553 gimple_set_location (g, gimple_location (stmt));
15554 gsi_replace (gsi, g, true);
15556 /* flavors of vec_min. */
15557 case VSX_BUILTIN_XVMINDP:
15558 case P8V_BUILTIN_VMINSD:
15559 case P8V_BUILTIN_VMINUD:
15560 case ALTIVEC_BUILTIN_VMINSB:
15561 case ALTIVEC_BUILTIN_VMINSH:
15562 case ALTIVEC_BUILTIN_VMINSW:
15563 case ALTIVEC_BUILTIN_VMINUB:
15564 case ALTIVEC_BUILTIN_VMINUH:
15565 case ALTIVEC_BUILTIN_VMINUW:
15566 case ALTIVEC_BUILTIN_VMINFP:
15567 arg0 = gimple_call_arg (stmt, 0);
15568 arg1 = gimple_call_arg (stmt, 1);
15569 lhs = gimple_call_lhs (stmt);
15570 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15571 gimple_set_location (g, gimple_location (stmt));
15572 gsi_replace (gsi, g, true);
15574 /* flavors of vec_max. */
15575 case VSX_BUILTIN_XVMAXDP:
15576 case P8V_BUILTIN_VMAXSD:
15577 case P8V_BUILTIN_VMAXUD:
15578 case ALTIVEC_BUILTIN_VMAXSB:
15579 case ALTIVEC_BUILTIN_VMAXSH:
15580 case ALTIVEC_BUILTIN_VMAXSW:
15581 case ALTIVEC_BUILTIN_VMAXUB:
15582 case ALTIVEC_BUILTIN_VMAXUH:
15583 case ALTIVEC_BUILTIN_VMAXUW:
15584 case ALTIVEC_BUILTIN_VMAXFP:
15585 arg0 = gimple_call_arg (stmt, 0);
15586 arg1 = gimple_call_arg (stmt, 1);
15587 lhs = gimple_call_lhs (stmt);
15588 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15589 gimple_set_location (g, gimple_location (stmt));
15590 gsi_replace (gsi, g, true);
15592 /* Flavors of vec_eqv. */
15593 case P8V_BUILTIN_EQV_V16QI:
15594 case P8V_BUILTIN_EQV_V8HI:
15595 case P8V_BUILTIN_EQV_V4SI:
15596 case P8V_BUILTIN_EQV_V4SF:
15597 case P8V_BUILTIN_EQV_V2DF:
15598 case P8V_BUILTIN_EQV_V2DI:
15599 arg0 = gimple_call_arg (stmt, 0);
15600 arg1 = gimple_call_arg (stmt, 1);
15601 lhs = gimple_call_lhs (stmt);
15602 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15603 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15604 gimple_set_location (g, gimple_location (stmt));
15605 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15606 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15607 gimple_set_location (g, gimple_location (stmt));
15608 gsi_replace (gsi, g, true);
15610 /* Flavors of vec_rotate_left. */
15611 case ALTIVEC_BUILTIN_VRLB:
15612 case ALTIVEC_BUILTIN_VRLH:
15613 case ALTIVEC_BUILTIN_VRLW:
15614 case P8V_BUILTIN_VRLD:
15615 arg0 = gimple_call_arg (stmt, 0);
15616 arg1 = gimple_call_arg (stmt, 1);
15617 lhs = gimple_call_lhs (stmt);
15618 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15619 gimple_set_location (g, gimple_location (stmt));
15620 gsi_replace (gsi, g, true);
15622 /* Flavors of vector shift right algebraic.
15623 vec_sra{b,h,w} -> vsra{b,h,w}. */
15624 case ALTIVEC_BUILTIN_VSRAB:
15625 case ALTIVEC_BUILTIN_VSRAH:
15626 case ALTIVEC_BUILTIN_VSRAW:
15627 case P8V_BUILTIN_VSRAD:
15628 arg0 = gimple_call_arg (stmt, 0);
15629 arg1 = gimple_call_arg (stmt, 1);
15630 lhs = gimple_call_lhs (stmt);
15631 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
15632 gimple_set_location (g, gimple_location (stmt));
15633 gsi_replace (gsi, g, true);
15635 /* Flavors of vector shift left.
15636 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15637 case ALTIVEC_BUILTIN_VSLB:
15638 case ALTIVEC_BUILTIN_VSLH:
15639 case ALTIVEC_BUILTIN_VSLW:
15640 case P8V_BUILTIN_VSLD:
15643 gimple_seq stmts = NULL;
15644 arg0 = gimple_call_arg (stmt, 0);
15645 tree arg0_type = TREE_TYPE (arg0);
15646 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
15647 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
15649 arg1 = gimple_call_arg (stmt, 1);
15650 tree arg1_type = TREE_TYPE (arg1);
15651 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15652 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15653 loc = gimple_location (stmt);
15654 lhs = gimple_call_lhs (stmt);
15655 /* Force arg1 into the range valid matching the arg0 type. */
15656 /* Build a vector consisting of the max valid bit-size values. */
15657 int n_elts = VECTOR_CST_NELTS (arg1);
15658 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
15660 tree element_size = build_int_cst (unsigned_element_type,
15661 tree_size_in_bits / n_elts);
15662 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
15663 for (int i = 0; i < n_elts; i++)
15664 elts.safe_push (element_size);
15665 tree modulo_tree = elts.build ();
15666 /* Modulo the provided shift value against that vector. */
15667 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15668 unsigned_arg1_type, arg1);
15669 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15670 unsigned_arg1_type, unsigned_arg1,
15672 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15673 /* And finally, do the shift. */
15674 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
15675 gimple_set_location (g, gimple_location (stmt));
15676 gsi_replace (gsi, g, true);
15679 /* Flavors of vector shift right. */
15680 case ALTIVEC_BUILTIN_VSRB:
15681 case ALTIVEC_BUILTIN_VSRH:
15682 case ALTIVEC_BUILTIN_VSRW:
15683 case P8V_BUILTIN_VSRD:
15685 arg0 = gimple_call_arg (stmt, 0);
15686 arg1 = gimple_call_arg (stmt, 1);
15687 lhs = gimple_call_lhs (stmt);
15688 gimple_seq stmts = NULL;
15689 /* Convert arg0 to unsigned. */
15691 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15692 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15694 = gimple_build (&stmts, RSHIFT_EXPR,
15695 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
15696 /* Convert result back to the lhs type. */
15697 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15698 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15699 update_call_from_tree (gsi, res);
15702 /* Vector loads. */
15703 case ALTIVEC_BUILTIN_LVX_V16QI:
15704 case ALTIVEC_BUILTIN_LVX_V8HI:
15705 case ALTIVEC_BUILTIN_LVX_V4SI:
15706 case ALTIVEC_BUILTIN_LVX_V4SF:
15707 case ALTIVEC_BUILTIN_LVX_V2DI:
15708 case ALTIVEC_BUILTIN_LVX_V2DF:
15709 case ALTIVEC_BUILTIN_LVX_V1TI:
15711 arg0 = gimple_call_arg (stmt, 0); // offset
15712 arg1 = gimple_call_arg (stmt, 1); // address
15713 lhs = gimple_call_lhs (stmt);
15714 location_t loc = gimple_location (stmt);
15715 /* Since arg1 may be cast to a different type, just use ptr_type_node
15716 here instead of trying to enforce TBAA on pointer types. */
15717 tree arg1_type = ptr_type_node;
15718 tree lhs_type = TREE_TYPE (lhs);
15719 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15720 the tree using the value from arg0. The resulting type will match
15721 the type of arg1. */
15722 gimple_seq stmts = NULL;
15723 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15724 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15725 arg1_type, arg1, temp_offset);
15726 /* Mask off any lower bits from the address. */
15727 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15728 arg1_type, temp_addr,
15729 build_int_cst (arg1_type, -16));
15730 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15731 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15732 take an offset, but since we've already incorporated the offset
15733 above, here we just pass in a zero. */
15735 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15736 build_int_cst (arg1_type, 0)));
15737 gimple_set_location (g, loc);
15738 gsi_replace (gsi, g, true);
15741 /* Vector stores. */
15742 case ALTIVEC_BUILTIN_STVX_V16QI:
15743 case ALTIVEC_BUILTIN_STVX_V8HI:
15744 case ALTIVEC_BUILTIN_STVX_V4SI:
15745 case ALTIVEC_BUILTIN_STVX_V4SF:
15746 case ALTIVEC_BUILTIN_STVX_V2DI:
15747 case ALTIVEC_BUILTIN_STVX_V2DF:
15749 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15750 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15751 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15752 location_t loc = gimple_location (stmt);
15753 tree arg0_type = TREE_TYPE (arg0);
15754 /* Use ptr_type_node (no TBAA) for the arg2_type.
15755 FIXME: (Richard) "A proper fix would be to transition this type as
15756 seen from the frontend to GIMPLE, for example in a similar way we
15757 do for MEM_REFs by piggy-backing that on an extra argument, a
15758 constant zero pointer of the alias pointer type to use (which would
15759 also serve as a type indicator of the store itself). I'd use a
15760 target specific internal function for this (not sure if we can have
15761 those target specific, but I guess if it's folded away then that's
15762 fine) and get away with the overload set." */
15763 tree arg2_type = ptr_type_node;
15764 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15765 the tree using the value from arg0. The resulting type will match
15766 the type of arg2. */
15767 gimple_seq stmts = NULL;
15768 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15769 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15770 arg2_type, arg2, temp_offset);
15771 /* Mask off any lower bits from the address. */
15772 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15773 arg2_type, temp_addr,
15774 build_int_cst (arg2_type, -16));
15775 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15776 /* The desired gimple result should be similar to:
15777 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15779 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15780 build_int_cst (arg2_type, 0)), arg0);
15781 gimple_set_location (g, loc);
15782 gsi_replace (gsi, g, true);
15786 /* unaligned Vector loads. */
15787 case VSX_BUILTIN_LXVW4X_V16QI:
15788 case VSX_BUILTIN_LXVW4X_V8HI:
15789 case VSX_BUILTIN_LXVW4X_V4SF:
15790 case VSX_BUILTIN_LXVW4X_V4SI:
15791 case VSX_BUILTIN_LXVD2X_V2DF:
15792 case VSX_BUILTIN_LXVD2X_V2DI:
15794 arg0 = gimple_call_arg (stmt, 0); // offset
15795 arg1 = gimple_call_arg (stmt, 1); // address
15796 lhs = gimple_call_lhs (stmt);
15797 location_t loc = gimple_location (stmt);
15798 /* Since arg1 may be cast to a different type, just use ptr_type_node
15799 here instead of trying to enforce TBAA on pointer types. */
15800 tree arg1_type = ptr_type_node;
15801 tree lhs_type = TREE_TYPE (lhs);
15802 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15803 required alignment (power) is 4 bytes regardless of data type. */
15804 tree align_ltype = build_aligned_type (lhs_type, 4);
15805 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15806 the tree using the value from arg0. The resulting type will match
15807 the type of arg1. */
15808 gimple_seq stmts = NULL;
15809 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15810 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15811 arg1_type, arg1, temp_offset);
15812 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15813 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15814 take an offset, but since we've already incorporated the offset
15815 above, here we just pass in a zero. */
15817 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
15818 build_int_cst (arg1_type, 0)));
15819 gimple_set_location (g, loc);
15820 gsi_replace (gsi, g, true);
15824 /* unaligned Vector stores. */
15825 case VSX_BUILTIN_STXVW4X_V16QI:
15826 case VSX_BUILTIN_STXVW4X_V8HI:
15827 case VSX_BUILTIN_STXVW4X_V4SF:
15828 case VSX_BUILTIN_STXVW4X_V4SI:
15829 case VSX_BUILTIN_STXVD2X_V2DF:
15830 case VSX_BUILTIN_STXVD2X_V2DI:
15832 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15833 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15834 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15835 location_t loc = gimple_location (stmt);
15836 tree arg0_type = TREE_TYPE (arg0);
15837 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15838 tree arg2_type = ptr_type_node;
15839 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15840 required alignment (power) is 4 bytes regardless of data type. */
15841 tree align_stype = build_aligned_type (arg0_type, 4);
15842 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15843 the tree using the value from arg1. */
15844 gimple_seq stmts = NULL;
15845 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15846 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15847 arg2_type, arg2, temp_offset);
15848 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15850 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
15851 build_int_cst (arg2_type, 0)), arg0);
15852 gimple_set_location (g, loc);
15853 gsi_replace (gsi, g, true);
15857 /* Vector Fused multiply-add (fma). */
15858 case ALTIVEC_BUILTIN_VMADDFP:
15859 case VSX_BUILTIN_XVMADDDP:
15860 case ALTIVEC_BUILTIN_VMLADDUHM:
15862 arg0 = gimple_call_arg (stmt, 0);
15863 arg1 = gimple_call_arg (stmt, 1);
15864 tree arg2 = gimple_call_arg (stmt, 2);
15865 lhs = gimple_call_lhs (stmt);
15866 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15867 gimple_call_set_lhs (g, lhs);
15868 gimple_call_set_nothrow (g, true);
15869 gimple_set_location (g, gimple_location (stmt));
15870 gsi_replace (gsi, g, true);
15874 /* Vector compares; EQ, NE, GE, GT, LE. */
15875 case ALTIVEC_BUILTIN_VCMPEQUB:
15876 case ALTIVEC_BUILTIN_VCMPEQUH:
15877 case ALTIVEC_BUILTIN_VCMPEQUW:
15878 case P8V_BUILTIN_VCMPEQUD:
15879 fold_compare_helper (gsi, EQ_EXPR, stmt);
15882 case P9V_BUILTIN_CMPNEB:
15883 case P9V_BUILTIN_CMPNEH:
15884 case P9V_BUILTIN_CMPNEW:
15885 fold_compare_helper (gsi, NE_EXPR, stmt);
15888 case VSX_BUILTIN_CMPGE_16QI:
15889 case VSX_BUILTIN_CMPGE_U16QI:
15890 case VSX_BUILTIN_CMPGE_8HI:
15891 case VSX_BUILTIN_CMPGE_U8HI:
15892 case VSX_BUILTIN_CMPGE_4SI:
15893 case VSX_BUILTIN_CMPGE_U4SI:
15894 case VSX_BUILTIN_CMPGE_2DI:
15895 case VSX_BUILTIN_CMPGE_U2DI:
15896 fold_compare_helper (gsi, GE_EXPR, stmt);
15899 case ALTIVEC_BUILTIN_VCMPGTSB:
15900 case ALTIVEC_BUILTIN_VCMPGTUB:
15901 case ALTIVEC_BUILTIN_VCMPGTSH:
15902 case ALTIVEC_BUILTIN_VCMPGTUH:
15903 case ALTIVEC_BUILTIN_VCMPGTSW:
15904 case ALTIVEC_BUILTIN_VCMPGTUW:
15905 case P8V_BUILTIN_VCMPGTUD:
15906 case P8V_BUILTIN_VCMPGTSD:
15907 fold_compare_helper (gsi, GT_EXPR, stmt);
15910 case VSX_BUILTIN_CMPLE_16QI:
15911 case VSX_BUILTIN_CMPLE_U16QI:
15912 case VSX_BUILTIN_CMPLE_8HI:
15913 case VSX_BUILTIN_CMPLE_U8HI:
15914 case VSX_BUILTIN_CMPLE_4SI:
15915 case VSX_BUILTIN_CMPLE_U4SI:
15916 case VSX_BUILTIN_CMPLE_2DI:
15917 case VSX_BUILTIN_CMPLE_U2DI:
15918 fold_compare_helper (gsi, LE_EXPR, stmt);
15921 /* flavors of vec_splat_[us]{8,16,32}. */
15922 case ALTIVEC_BUILTIN_VSPLTISB:
15923 case ALTIVEC_BUILTIN_VSPLTISH:
15924 case ALTIVEC_BUILTIN_VSPLTISW:
15927 if (fn_code == ALTIVEC_BUILTIN_VSPLTISB)
15929 else if (fn_code == ALTIVEC_BUILTIN_VSPLTISH)
15934 arg0 = gimple_call_arg (stmt, 0);
15935 lhs = gimple_call_lhs (stmt);
15937 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15938 5-bit signed constant in range -16 to +15. */
15939 if (TREE_CODE (arg0) != INTEGER_CST
15940 || !IN_RANGE (sext_hwi (TREE_INT_CST_LOW (arg0), size),
15943 gimple_seq stmts = NULL;
15944 location_t loc = gimple_location (stmt);
15945 tree splat_value = gimple_convert (&stmts, loc,
15946 TREE_TYPE (TREE_TYPE (lhs)), arg0);
15947 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15948 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
15949 g = gimple_build_assign (lhs, splat_tree);
15950 gimple_set_location (g, gimple_location (stmt));
15951 gsi_replace (gsi, g, true);
15955 /* Flavors of vec_splat. */
15956 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
15957 case ALTIVEC_BUILTIN_VSPLTB:
15958 case ALTIVEC_BUILTIN_VSPLTH:
15959 case ALTIVEC_BUILTIN_VSPLTW:
15960 case VSX_BUILTIN_XXSPLTD_V2DI:
15961 case VSX_BUILTIN_XXSPLTD_V2DF:
15963 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
15964 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
15965 /* Only fold the vec_splat_*() if arg1 is both a constant value and
15966 is a valid index into the arg0 vector. */
15967 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
15968 if (TREE_CODE (arg1) != INTEGER_CST
15969 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
15971 lhs = gimple_call_lhs (stmt);
15972 tree lhs_type = TREE_TYPE (lhs);
15973 tree arg0_type = TREE_TYPE (arg0);
15975 if (TREE_CODE (arg0) == VECTOR_CST)
15976 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
15979 /* Determine (in bits) the length and start location of the
15980 splat value for a call to the tree_vec_extract helper. */
15981 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
15982 * BITS_PER_UNIT / n_elts;
15983 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
15984 tree len = build_int_cst (bitsizetype, splat_elem_size);
15985 tree start = build_int_cst (bitsizetype, splat_start_bit);
15986 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
15989 /* And finally, build the new vector. */
15990 tree splat_tree = build_vector_from_val (lhs_type, splat);
15991 g = gimple_build_assign (lhs, splat_tree);
15992 gimple_set_location (g, gimple_location (stmt));
15993 gsi_replace (gsi, g, true);
15997 /* vec_mergel (integrals). */
15998 case ALTIVEC_BUILTIN_VMRGLH:
15999 case ALTIVEC_BUILTIN_VMRGLW:
16000 case VSX_BUILTIN_XXMRGLW_4SI:
16001 case ALTIVEC_BUILTIN_VMRGLB:
16002 case VSX_BUILTIN_VEC_MERGEL_V2DI:
16003 case VSX_BUILTIN_XXMRGLW_4SF:
16004 case VSX_BUILTIN_VEC_MERGEL_V2DF:
16005 fold_mergehl_helper (gsi, stmt, 1);
16007 /* vec_mergeh (integrals). */
16008 case ALTIVEC_BUILTIN_VMRGHH:
16009 case ALTIVEC_BUILTIN_VMRGHW:
16010 case VSX_BUILTIN_XXMRGHW_4SI:
16011 case ALTIVEC_BUILTIN_VMRGHB:
16012 case VSX_BUILTIN_VEC_MERGEH_V2DI:
16013 case VSX_BUILTIN_XXMRGHW_4SF:
16014 case VSX_BUILTIN_VEC_MERGEH_V2DF:
16015 fold_mergehl_helper (gsi, stmt, 0);
16018 /* Flavors of vec_mergee. */
16019 case P8V_BUILTIN_VMRGEW_V4SI:
16020 case P8V_BUILTIN_VMRGEW_V2DI:
16021 case P8V_BUILTIN_VMRGEW_V4SF:
16022 case P8V_BUILTIN_VMRGEW_V2DF:
16023 fold_mergeeo_helper (gsi, stmt, 0);
16025 /* Flavors of vec_mergeo. */
16026 case P8V_BUILTIN_VMRGOW_V4SI:
16027 case P8V_BUILTIN_VMRGOW_V2DI:
16028 case P8V_BUILTIN_VMRGOW_V4SF:
16029 case P8V_BUILTIN_VMRGOW_V2DF:
16030 fold_mergeeo_helper (gsi, stmt, 1);
16033 /* d = vec_pack (a, b) */
16034 case P8V_BUILTIN_VPKUDUM:
16035 case ALTIVEC_BUILTIN_VPKUHUM:
16036 case ALTIVEC_BUILTIN_VPKUWUM:
16038 arg0 = gimple_call_arg (stmt, 0);
16039 arg1 = gimple_call_arg (stmt, 1);
16040 lhs = gimple_call_lhs (stmt);
16041 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
16042 gimple_set_location (g, gimple_location (stmt));
16043 gsi_replace (gsi, g, true);
16047 /* d = vec_unpackh (a) */
16048 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
16049 in this code is sensitive to endian-ness, and needs to be inverted to
16050 handle both LE and BE targets. */
16051 case ALTIVEC_BUILTIN_VUPKHSB:
16052 case ALTIVEC_BUILTIN_VUPKHSH:
16053 case P8V_BUILTIN_VUPKHSW:
16055 arg0 = gimple_call_arg (stmt, 0);
16056 lhs = gimple_call_lhs (stmt);
16057 if (BYTES_BIG_ENDIAN)
16058 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
16060 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
16061 gimple_set_location (g, gimple_location (stmt));
16062 gsi_replace (gsi, g, true);
16065 /* d = vec_unpackl (a) */
16066 case ALTIVEC_BUILTIN_VUPKLSB:
16067 case ALTIVEC_BUILTIN_VUPKLSH:
16068 case P8V_BUILTIN_VUPKLSW:
16070 arg0 = gimple_call_arg (stmt, 0);
16071 lhs = gimple_call_lhs (stmt);
16072 if (BYTES_BIG_ENDIAN)
16073 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
16075 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
16076 gimple_set_location (g, gimple_location (stmt));
16077 gsi_replace (gsi, g, true);
16080 /* There is no gimple type corresponding with pixel, so just return. */
16081 case ALTIVEC_BUILTIN_VUPKHPX:
16082 case ALTIVEC_BUILTIN_VUPKLPX:
16086 case ALTIVEC_BUILTIN_VPERM_16QI:
16087 case ALTIVEC_BUILTIN_VPERM_8HI:
16088 case ALTIVEC_BUILTIN_VPERM_4SI:
16089 case ALTIVEC_BUILTIN_VPERM_2DI:
16090 case ALTIVEC_BUILTIN_VPERM_4SF:
16091 case ALTIVEC_BUILTIN_VPERM_2DF:
16093 arg0 = gimple_call_arg (stmt, 0);
16094 arg1 = gimple_call_arg (stmt, 1);
16095 tree permute = gimple_call_arg (stmt, 2);
16096 lhs = gimple_call_lhs (stmt);
16097 location_t loc = gimple_location (stmt);
16098 gimple_seq stmts = NULL;
16099 // convert arg0 and arg1 to match the type of the permute
16100 // for the VEC_PERM_EXPR operation.
16101 tree permute_type = (TREE_TYPE (permute));
16102 tree arg0_ptype = gimple_convert (&stmts, loc, permute_type, arg0);
16103 tree arg1_ptype = gimple_convert (&stmts, loc, permute_type, arg1);
16104 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
16105 permute_type, arg0_ptype, arg1_ptype,
16107 // Convert the result back to the desired lhs type upon completion.
16108 tree temp = gimple_convert (&stmts, loc, TREE_TYPE (lhs), lhs_ptype);
16109 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16110 g = gimple_build_assign (lhs, temp);
16111 gimple_set_location (g, loc);
16112 gsi_replace (gsi, g, true);
16117 if (TARGET_DEBUG_BUILTIN)
16118 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16119 fn_code, fn_name1, fn_name2);
16126 /* Expand an expression EXP that calls a built-in function,
16127 with result going to TARGET if that's convenient
16128 (and in mode MODE if that's convenient).
16129 SUBTARGET may be used as the target for computing one of EXP's operands.
16130 IGNORE is nonzero if the value is to be ignored. */
16133 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16134 machine_mode mode ATTRIBUTE_UNUSED,
16135 int ignore ATTRIBUTE_UNUSED)
16137 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16138 enum rs6000_builtins fcode
16139 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16140 size_t uns_fcode = (size_t)fcode;
16141 const struct builtin_description *d;
16145 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16146 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16147 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16149 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16150 floating point type, depending on whether long double is the IBM extended
16151 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16152 we only define one variant of the built-in function, and switch the code
16153 when defining it, rather than defining two built-ins and using the
16154 overload table in rs6000-c.c to switch between the two. If we don't have
16155 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16156 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16157 if (FLOAT128_IEEE_P (TFmode))
16163 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16164 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16165 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16166 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16167 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16168 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16169 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16170 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16171 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16172 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16173 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16174 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16175 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16178 if (TARGET_DEBUG_BUILTIN)
16180 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16181 const char *name2 = (icode != CODE_FOR_nothing)
16182 ? get_insn_name ((int) icode)
16186 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16188 default: name3 = "unknown"; break;
16189 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16190 case RS6000_BTC_UNARY: name3 = "unary"; break;
16191 case RS6000_BTC_BINARY: name3 = "binary"; break;
16192 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16193 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16194 case RS6000_BTC_ABS: name3 = "abs"; break;
16195 case RS6000_BTC_DST: name3 = "dst"; break;
16200 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16201 (name1) ? name1 : "---", fcode,
16202 (name2) ? name2 : "---", (int) icode,
16204 func_valid_p ? "" : ", not valid");
16209 rs6000_invalid_builtin (fcode);
16211 /* Given it is invalid, just generate a normal call. */
16212 return expand_call (exp, target, ignore);
16217 case RS6000_BUILTIN_RECIP:
16218 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16220 case RS6000_BUILTIN_RECIPF:
16221 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16223 case RS6000_BUILTIN_RSQRTF:
16224 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16226 case RS6000_BUILTIN_RSQRT:
16227 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16229 case POWER7_BUILTIN_BPERMD:
16230 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16231 ? CODE_FOR_bpermd_di
16232 : CODE_FOR_bpermd_si), exp, target);
16234 case RS6000_BUILTIN_GET_TB:
16235 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16238 case RS6000_BUILTIN_MFTB:
16239 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16240 ? CODE_FOR_rs6000_mftb_di
16241 : CODE_FOR_rs6000_mftb_si),
16244 case RS6000_BUILTIN_MFFS:
16245 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16247 case RS6000_BUILTIN_MTFSB0:
16248 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
16250 case RS6000_BUILTIN_MTFSB1:
16251 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
16253 case RS6000_BUILTIN_SET_FPSCR_RN:
16254 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
16257 case RS6000_BUILTIN_SET_FPSCR_DRN:
16259 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
16262 case RS6000_BUILTIN_MFFSL:
16263 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
16265 case RS6000_BUILTIN_MTFSF:
16266 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16268 case RS6000_BUILTIN_CPU_INIT:
16269 case RS6000_BUILTIN_CPU_IS:
16270 case RS6000_BUILTIN_CPU_SUPPORTS:
16271 return cpu_expand_builtin (fcode, exp, target);
16273 case MISC_BUILTIN_SPEC_BARRIER:
16275 emit_insn (gen_speculation_barrier ());
16279 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16280 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16282 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16283 : (int) CODE_FOR_altivec_lvsl_direct);
16284 machine_mode tmode = insn_data[icode2].operand[0].mode;
16285 machine_mode mode = insn_data[icode2].operand[1].mode;
16289 gcc_assert (TARGET_ALTIVEC);
16291 arg = CALL_EXPR_ARG (exp, 0);
16292 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16293 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16294 addr = memory_address (mode, op);
16295 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16299 /* For the load case need to negate the address. */
16300 op = gen_reg_rtx (GET_MODE (addr));
16301 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16303 op = gen_rtx_MEM (mode, op);
16306 || GET_MODE (target) != tmode
16307 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16308 target = gen_reg_rtx (tmode);
16310 pat = GEN_FCN (icode2) (target, op);
16318 case ALTIVEC_BUILTIN_VCFUX:
16319 case ALTIVEC_BUILTIN_VCFSX:
16320 case ALTIVEC_BUILTIN_VCTUXS:
16321 case ALTIVEC_BUILTIN_VCTSXS:
16322 /* FIXME: There's got to be a nicer way to handle this case than
16323 constructing a new CALL_EXPR. */
16324 if (call_expr_nargs (exp) == 1)
16326 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16327 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16331 /* For the pack and unpack int128 routines, fix up the builtin so it
16332 uses the correct IBM128 type. */
16333 case MISC_BUILTIN_PACK_IF:
16334 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16336 icode = CODE_FOR_packtf;
16337 fcode = MISC_BUILTIN_PACK_TF;
16338 uns_fcode = (size_t)fcode;
16342 case MISC_BUILTIN_UNPACK_IF:
16343 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16345 icode = CODE_FOR_unpacktf;
16346 fcode = MISC_BUILTIN_UNPACK_TF;
16347 uns_fcode = (size_t)fcode;
16355 if (TARGET_ALTIVEC)
16357 ret = altivec_expand_builtin (exp, target, &success);
16364 ret = htm_expand_builtin (exp, target, &success);
16370 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16371 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16372 gcc_assert (attr == RS6000_BTC_UNARY
16373 || attr == RS6000_BTC_BINARY
16374 || attr == RS6000_BTC_TERNARY
16375 || attr == RS6000_BTC_SPECIAL);
16377 /* Handle simple unary operations. */
16379 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16380 if (d->code == fcode)
16381 return rs6000_expand_unop_builtin (icode, exp, target);
16383 /* Handle simple binary operations. */
16385 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16386 if (d->code == fcode)
16387 return rs6000_expand_binop_builtin (icode, exp, target);
16389 /* Handle simple ternary operations. */
16391 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16392 if (d->code == fcode)
16393 return rs6000_expand_ternop_builtin (icode, exp, target);
16395 /* Handle simple no-argument operations. */
16397 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16398 if (d->code == fcode)
16399 return rs6000_expand_zeroop_builtin (icode, target);
16401 gcc_unreachable ();
16404 /* Create a builtin vector type with a name. Taking care not to give
16405 the canonical type a name. */
16408 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16410 tree result = build_vector_type (elt_type, num_elts);
16412 /* Copy so we don't give the canonical type a name. */
16413 result = build_variant_type_copy (result);
16415 add_builtin_type (name, result);
16421 rs6000_init_builtins (void)
16427 if (TARGET_DEBUG_BUILTIN)
16428 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16429 (TARGET_ALTIVEC) ? ", altivec" : "",
16430 (TARGET_VSX) ? ", vsx" : "");
16432 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16433 : "__vector long long",
16434 intDI_type_node, 2);
16435 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16436 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16437 intSI_type_node, 4);
16438 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16439 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16440 intHI_type_node, 8);
16441 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16442 intQI_type_node, 16);
16444 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16445 unsigned_intQI_type_node, 16);
16446 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16447 unsigned_intHI_type_node, 8);
16448 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16449 unsigned_intSI_type_node, 4);
16450 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16451 ? "__vector unsigned long"
16452 : "__vector unsigned long long",
16453 unsigned_intDI_type_node, 2);
16455 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16457 const_str_type_node
16458 = build_pointer_type (build_qualified_type (char_type_node,
16461 /* We use V1TI mode as a special container to hold __int128_t items that
16462 must live in VSX registers. */
16463 if (intTI_type_node)
16465 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16466 intTI_type_node, 1);
16467 unsigned_V1TI_type_node
16468 = rs6000_vector_type ("__vector unsigned __int128",
16469 unsigned_intTI_type_node, 1);
16472 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16473 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16474 'vector unsigned short'. */
16476 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16477 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16478 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16479 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16480 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16482 long_integer_type_internal_node = long_integer_type_node;
16483 long_unsigned_type_internal_node = long_unsigned_type_node;
16484 long_long_integer_type_internal_node = long_long_integer_type_node;
16485 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16486 intQI_type_internal_node = intQI_type_node;
16487 uintQI_type_internal_node = unsigned_intQI_type_node;
16488 intHI_type_internal_node = intHI_type_node;
16489 uintHI_type_internal_node = unsigned_intHI_type_node;
16490 intSI_type_internal_node = intSI_type_node;
16491 uintSI_type_internal_node = unsigned_intSI_type_node;
16492 intDI_type_internal_node = intDI_type_node;
16493 uintDI_type_internal_node = unsigned_intDI_type_node;
16494 intTI_type_internal_node = intTI_type_node;
16495 uintTI_type_internal_node = unsigned_intTI_type_node;
16496 float_type_internal_node = float_type_node;
16497 double_type_internal_node = double_type_node;
16498 long_double_type_internal_node = long_double_type_node;
16499 dfloat64_type_internal_node = dfloat64_type_node;
16500 dfloat128_type_internal_node = dfloat128_type_node;
16501 void_type_internal_node = void_type_node;
16503 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16504 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16505 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16506 format that uses a pair of doubles, depending on the switches and
16509 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16510 floating point, we need make sure the type is non-zero or else self-test
16511 fails during bootstrap.
16513 Always create __ibm128 as a separate type, even if the current long double
16514 format is IBM extended double.
16516 For IEEE 128-bit floating point, always create the type __ieee128. If the
16517 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16519 if (TARGET_FLOAT128_TYPE)
16521 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16522 ibm128_float_type_node = long_double_type_node;
16525 ibm128_float_type_node = make_node (REAL_TYPE);
16526 TYPE_PRECISION (ibm128_float_type_node) = 128;
16527 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16528 layout_type (ibm128_float_type_node);
16531 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16534 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16535 ieee128_float_type_node = long_double_type_node;
16537 ieee128_float_type_node = float128_type_node;
16539 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16544 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16546 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16548 builtin_mode_to_type[QImode][0] = integer_type_node;
16549 builtin_mode_to_type[HImode][0] = integer_type_node;
16550 builtin_mode_to_type[SImode][0] = intSI_type_node;
16551 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16552 builtin_mode_to_type[DImode][0] = intDI_type_node;
16553 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16554 builtin_mode_to_type[TImode][0] = intTI_type_node;
16555 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16556 builtin_mode_to_type[SFmode][0] = float_type_node;
16557 builtin_mode_to_type[DFmode][0] = double_type_node;
16558 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16559 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16560 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16561 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16562 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16563 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16564 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16565 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16566 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16567 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16568 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16569 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16570 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16571 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16572 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16573 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16574 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16576 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16577 TYPE_NAME (bool_char_type_node) = tdecl;
16579 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16580 TYPE_NAME (bool_short_type_node) = tdecl;
16582 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16583 TYPE_NAME (bool_int_type_node) = tdecl;
16585 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16586 TYPE_NAME (pixel_type_node) = tdecl;
16588 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16589 bool_char_type_node, 16);
16590 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16591 bool_short_type_node, 8);
16592 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16593 bool_int_type_node, 4);
16594 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16595 ? "__vector __bool long"
16596 : "__vector __bool long long",
16597 bool_long_long_type_node, 2);
16598 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16599 pixel_type_node, 8);
16601 /* Create Altivec and VSX builtins on machines with at least the
16602 general purpose extensions (970 and newer) to allow the use of
16603 the target attribute. */
16604 if (TARGET_EXTRA_BUILTINS)
16605 altivec_init_builtins ();
16607 htm_init_builtins ();
16609 if (TARGET_EXTRA_BUILTINS)
16610 rs6000_common_init_builtins ();
16612 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16613 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16614 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16616 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16617 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16618 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16620 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16621 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16622 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16624 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16625 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16626 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16628 mode = (TARGET_64BIT) ? DImode : SImode;
16629 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16630 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16631 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16633 ftype = build_function_type_list (unsigned_intDI_type_node,
16635 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16638 ftype = build_function_type_list (unsigned_intDI_type_node,
16641 ftype = build_function_type_list (unsigned_intSI_type_node,
16643 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16645 ftype = build_function_type_list (double_type_node, NULL_TREE);
16646 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16648 ftype = build_function_type_list (double_type_node, NULL_TREE);
16649 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
16651 ftype = build_function_type_list (void_type_node,
16654 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
16656 ftype = build_function_type_list (void_type_node,
16659 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
16661 ftype = build_function_type_list (void_type_node,
16664 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
16666 ftype = build_function_type_list (void_type_node,
16669 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
16671 ftype = build_function_type_list (void_type_node,
16672 intSI_type_node, double_type_node,
16674 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16676 ftype = build_function_type_list (void_type_node, NULL_TREE);
16677 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16678 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16679 MISC_BUILTIN_SPEC_BARRIER);
16681 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16683 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16684 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16686 /* AIX libm provides clog as __clog. */
16687 if (TARGET_XCOFF &&
16688 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16689 set_user_assembler_name (tdecl, "__clog");
16691 #ifdef SUBTARGET_INIT_BUILTINS
16692 SUBTARGET_INIT_BUILTINS;
16696 /* Returns the rs6000 builtin decl for CODE. */
16699 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16701 HOST_WIDE_INT fnmask;
16703 if (code >= RS6000_BUILTIN_COUNT)
16704 return error_mark_node;
16706 fnmask = rs6000_builtin_info[code].mask;
16707 if ((fnmask & rs6000_builtin_mask) != fnmask)
16709 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16710 return error_mark_node;
16713 return rs6000_builtin_decls[code];
16717 altivec_init_builtins (void)
16719 const struct builtin_description *d;
16723 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16725 tree pvoid_type_node = build_pointer_type (void_type_node);
16727 tree pcvoid_type_node
16728 = build_pointer_type (build_qualified_type (void_type_node,
16731 tree int_ftype_opaque
16732 = build_function_type_list (integer_type_node,
16733 opaque_V4SI_type_node, NULL_TREE);
16734 tree opaque_ftype_opaque
16735 = build_function_type_list (integer_type_node, NULL_TREE);
16736 tree opaque_ftype_opaque_int
16737 = build_function_type_list (opaque_V4SI_type_node,
16738 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16739 tree opaque_ftype_opaque_opaque_int
16740 = build_function_type_list (opaque_V4SI_type_node,
16741 opaque_V4SI_type_node, opaque_V4SI_type_node,
16742 integer_type_node, NULL_TREE);
16743 tree opaque_ftype_opaque_opaque_opaque
16744 = build_function_type_list (opaque_V4SI_type_node,
16745 opaque_V4SI_type_node, opaque_V4SI_type_node,
16746 opaque_V4SI_type_node, NULL_TREE);
16747 tree opaque_ftype_opaque_opaque
16748 = build_function_type_list (opaque_V4SI_type_node,
16749 opaque_V4SI_type_node, opaque_V4SI_type_node,
16751 tree int_ftype_int_opaque_opaque
16752 = build_function_type_list (integer_type_node,
16753 integer_type_node, opaque_V4SI_type_node,
16754 opaque_V4SI_type_node, NULL_TREE);
16755 tree int_ftype_int_v4si_v4si
16756 = build_function_type_list (integer_type_node,
16757 integer_type_node, V4SI_type_node,
16758 V4SI_type_node, NULL_TREE);
16759 tree int_ftype_int_v2di_v2di
16760 = build_function_type_list (integer_type_node,
16761 integer_type_node, V2DI_type_node,
16762 V2DI_type_node, NULL_TREE);
16763 tree void_ftype_v4si
16764 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16765 tree v8hi_ftype_void
16766 = build_function_type_list (V8HI_type_node, NULL_TREE);
16767 tree void_ftype_void
16768 = build_function_type_list (void_type_node, NULL_TREE);
16769 tree void_ftype_int
16770 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16772 tree opaque_ftype_long_pcvoid
16773 = build_function_type_list (opaque_V4SI_type_node,
16774 long_integer_type_node, pcvoid_type_node,
16776 tree v16qi_ftype_long_pcvoid
16777 = build_function_type_list (V16QI_type_node,
16778 long_integer_type_node, pcvoid_type_node,
16780 tree v8hi_ftype_long_pcvoid
16781 = build_function_type_list (V8HI_type_node,
16782 long_integer_type_node, pcvoid_type_node,
16784 tree v4si_ftype_long_pcvoid
16785 = build_function_type_list (V4SI_type_node,
16786 long_integer_type_node, pcvoid_type_node,
16788 tree v4sf_ftype_long_pcvoid
16789 = build_function_type_list (V4SF_type_node,
16790 long_integer_type_node, pcvoid_type_node,
16792 tree v2df_ftype_long_pcvoid
16793 = build_function_type_list (V2DF_type_node,
16794 long_integer_type_node, pcvoid_type_node,
16796 tree v2di_ftype_long_pcvoid
16797 = build_function_type_list (V2DI_type_node,
16798 long_integer_type_node, pcvoid_type_node,
16800 tree v1ti_ftype_long_pcvoid
16801 = build_function_type_list (V1TI_type_node,
16802 long_integer_type_node, pcvoid_type_node,
16805 tree void_ftype_opaque_long_pvoid
16806 = build_function_type_list (void_type_node,
16807 opaque_V4SI_type_node, long_integer_type_node,
16808 pvoid_type_node, NULL_TREE);
16809 tree void_ftype_v4si_long_pvoid
16810 = build_function_type_list (void_type_node,
16811 V4SI_type_node, long_integer_type_node,
16812 pvoid_type_node, NULL_TREE);
16813 tree void_ftype_v16qi_long_pvoid
16814 = build_function_type_list (void_type_node,
16815 V16QI_type_node, long_integer_type_node,
16816 pvoid_type_node, NULL_TREE);
16818 tree void_ftype_v16qi_pvoid_long
16819 = build_function_type_list (void_type_node,
16820 V16QI_type_node, pvoid_type_node,
16821 long_integer_type_node, NULL_TREE);
16823 tree void_ftype_v8hi_long_pvoid
16824 = build_function_type_list (void_type_node,
16825 V8HI_type_node, long_integer_type_node,
16826 pvoid_type_node, NULL_TREE);
16827 tree void_ftype_v4sf_long_pvoid
16828 = build_function_type_list (void_type_node,
16829 V4SF_type_node, long_integer_type_node,
16830 pvoid_type_node, NULL_TREE);
16831 tree void_ftype_v2df_long_pvoid
16832 = build_function_type_list (void_type_node,
16833 V2DF_type_node, long_integer_type_node,
16834 pvoid_type_node, NULL_TREE);
16835 tree void_ftype_v1ti_long_pvoid
16836 = build_function_type_list (void_type_node,
16837 V1TI_type_node, long_integer_type_node,
16838 pvoid_type_node, NULL_TREE);
16839 tree void_ftype_v2di_long_pvoid
16840 = build_function_type_list (void_type_node,
16841 V2DI_type_node, long_integer_type_node,
16842 pvoid_type_node, NULL_TREE);
16843 tree int_ftype_int_v8hi_v8hi
16844 = build_function_type_list (integer_type_node,
16845 integer_type_node, V8HI_type_node,
16846 V8HI_type_node, NULL_TREE);
16847 tree int_ftype_int_v16qi_v16qi
16848 = build_function_type_list (integer_type_node,
16849 integer_type_node, V16QI_type_node,
16850 V16QI_type_node, NULL_TREE);
16851 tree int_ftype_int_v4sf_v4sf
16852 = build_function_type_list (integer_type_node,
16853 integer_type_node, V4SF_type_node,
16854 V4SF_type_node, NULL_TREE);
16855 tree int_ftype_int_v2df_v2df
16856 = build_function_type_list (integer_type_node,
16857 integer_type_node, V2DF_type_node,
16858 V2DF_type_node, NULL_TREE);
16859 tree v2di_ftype_v2di
16860 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16861 tree v4si_ftype_v4si
16862 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16863 tree v8hi_ftype_v8hi
16864 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16865 tree v16qi_ftype_v16qi
16866 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16867 tree v4sf_ftype_v4sf
16868 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16869 tree v2df_ftype_v2df
16870 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16871 tree void_ftype_pcvoid_int_int
16872 = build_function_type_list (void_type_node,
16873 pcvoid_type_node, integer_type_node,
16874 integer_type_node, NULL_TREE);
16876 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16877 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16878 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16879 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16880 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16881 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16882 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16883 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16884 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16885 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16886 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16887 ALTIVEC_BUILTIN_LVXL_V2DF);
16888 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16889 ALTIVEC_BUILTIN_LVXL_V2DI);
16890 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16891 ALTIVEC_BUILTIN_LVXL_V4SF);
16892 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16893 ALTIVEC_BUILTIN_LVXL_V4SI);
16894 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16895 ALTIVEC_BUILTIN_LVXL_V8HI);
16896 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16897 ALTIVEC_BUILTIN_LVXL_V16QI);
16898 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16899 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16900 ALTIVEC_BUILTIN_LVX_V1TI);
16901 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16902 ALTIVEC_BUILTIN_LVX_V2DF);
16903 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16904 ALTIVEC_BUILTIN_LVX_V2DI);
16905 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16906 ALTIVEC_BUILTIN_LVX_V4SF);
16907 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16908 ALTIVEC_BUILTIN_LVX_V4SI);
16909 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16910 ALTIVEC_BUILTIN_LVX_V8HI);
16911 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16912 ALTIVEC_BUILTIN_LVX_V16QI);
16913 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16914 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16915 ALTIVEC_BUILTIN_STVX_V2DF);
16916 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16917 ALTIVEC_BUILTIN_STVX_V2DI);
16918 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16919 ALTIVEC_BUILTIN_STVX_V4SF);
16920 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16921 ALTIVEC_BUILTIN_STVX_V4SI);
16922 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16923 ALTIVEC_BUILTIN_STVX_V8HI);
16924 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16925 ALTIVEC_BUILTIN_STVX_V16QI);
16926 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16927 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16928 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16929 ALTIVEC_BUILTIN_STVXL_V2DF);
16930 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16931 ALTIVEC_BUILTIN_STVXL_V2DI);
16932 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16933 ALTIVEC_BUILTIN_STVXL_V4SF);
16934 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16935 ALTIVEC_BUILTIN_STVXL_V4SI);
16936 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16937 ALTIVEC_BUILTIN_STVXL_V8HI);
16938 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16939 ALTIVEC_BUILTIN_STVXL_V16QI);
16940 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16941 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16942 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16943 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16944 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16945 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16946 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16947 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16948 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16949 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16950 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16951 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16952 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16953 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16954 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16955 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16957 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16958 VSX_BUILTIN_LXVD2X_V2DF);
16959 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16960 VSX_BUILTIN_LXVD2X_V2DI);
16961 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16962 VSX_BUILTIN_LXVW4X_V4SF);
16963 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16964 VSX_BUILTIN_LXVW4X_V4SI);
16965 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16966 VSX_BUILTIN_LXVW4X_V8HI);
16967 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16968 VSX_BUILTIN_LXVW4X_V16QI);
16969 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16970 VSX_BUILTIN_STXVD2X_V2DF);
16971 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16972 VSX_BUILTIN_STXVD2X_V2DI);
16973 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16974 VSX_BUILTIN_STXVW4X_V4SF);
16975 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16976 VSX_BUILTIN_STXVW4X_V4SI);
16977 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16978 VSX_BUILTIN_STXVW4X_V8HI);
16979 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16980 VSX_BUILTIN_STXVW4X_V16QI);
16982 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16983 VSX_BUILTIN_LD_ELEMREV_V2DF);
16984 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16985 VSX_BUILTIN_LD_ELEMREV_V2DI);
16986 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16987 VSX_BUILTIN_LD_ELEMREV_V4SF);
16988 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16989 VSX_BUILTIN_LD_ELEMREV_V4SI);
16990 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16991 VSX_BUILTIN_LD_ELEMREV_V8HI);
16992 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16993 VSX_BUILTIN_LD_ELEMREV_V16QI);
16994 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16995 VSX_BUILTIN_ST_ELEMREV_V2DF);
16996 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16997 VSX_BUILTIN_ST_ELEMREV_V1TI);
16998 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16999 VSX_BUILTIN_ST_ELEMREV_V2DI);
17000 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
17001 VSX_BUILTIN_ST_ELEMREV_V4SF);
17002 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
17003 VSX_BUILTIN_ST_ELEMREV_V4SI);
17004 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
17005 VSX_BUILTIN_ST_ELEMREV_V8HI);
17006 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
17007 VSX_BUILTIN_ST_ELEMREV_V16QI);
17009 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
17010 VSX_BUILTIN_VEC_LD);
17011 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
17012 VSX_BUILTIN_VEC_ST);
17013 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
17014 VSX_BUILTIN_VEC_XL);
17015 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
17016 VSX_BUILTIN_VEC_XL_BE);
17017 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
17018 VSX_BUILTIN_VEC_XST);
17019 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
17020 VSX_BUILTIN_VEC_XST_BE);
17022 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
17023 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
17024 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
17026 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
17027 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
17028 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
17029 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
17030 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
17031 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
17032 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
17033 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
17034 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
17035 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
17036 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
17037 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
17039 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
17040 ALTIVEC_BUILTIN_VEC_ADDE);
17041 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
17042 ALTIVEC_BUILTIN_VEC_ADDEC);
17043 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
17044 ALTIVEC_BUILTIN_VEC_CMPNE);
17045 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
17046 ALTIVEC_BUILTIN_VEC_MUL);
17047 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
17048 ALTIVEC_BUILTIN_VEC_SUBE);
17049 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
17050 ALTIVEC_BUILTIN_VEC_SUBEC);
17052 /* Cell builtins. */
17053 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
17054 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
17055 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
17056 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
17058 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
17059 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
17060 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
17061 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
17063 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
17064 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
17065 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
17066 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
17068 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
17069 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
17070 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
17071 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
17073 if (TARGET_P9_VECTOR)
17075 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
17076 P9V_BUILTIN_STXVL);
17077 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
17078 P9V_BUILTIN_XST_LEN_R);
17081 /* Add the DST variants. */
17083 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
17085 HOST_WIDE_INT mask = d->mask;
17087 /* It is expected that these dst built-in functions may have
17088 d->icode equal to CODE_FOR_nothing. */
17089 if ((mask & builtin_mask) != mask)
17091 if (TARGET_DEBUG_BUILTIN)
17092 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
17096 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
17099 /* Initialize the predicates. */
17100 d = bdesc_altivec_preds;
17101 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
17103 machine_mode mode1;
17105 HOST_WIDE_INT mask = d->mask;
17107 if ((mask & builtin_mask) != mask)
17109 if (TARGET_DEBUG_BUILTIN)
17110 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
17115 if (rs6000_overloaded_builtin_p (d->code))
17119 /* Cannot define builtin if the instruction is disabled. */
17120 gcc_assert (d->icode != CODE_FOR_nothing);
17121 mode1 = insn_data[d->icode].operand[1].mode;
17127 type = int_ftype_int_opaque_opaque;
17130 type = int_ftype_int_v2di_v2di;
17133 type = int_ftype_int_v4si_v4si;
17136 type = int_ftype_int_v8hi_v8hi;
17139 type = int_ftype_int_v16qi_v16qi;
17142 type = int_ftype_int_v4sf_v4sf;
17145 type = int_ftype_int_v2df_v2df;
17148 gcc_unreachable ();
17151 def_builtin (d->name, type, d->code);
17154 /* Initialize the abs* operators. */
17156 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17158 machine_mode mode0;
17160 HOST_WIDE_INT mask = d->mask;
17162 if ((mask & builtin_mask) != mask)
17164 if (TARGET_DEBUG_BUILTIN)
17165 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17170 /* Cannot define builtin if the instruction is disabled. */
17171 gcc_assert (d->icode != CODE_FOR_nothing);
17172 mode0 = insn_data[d->icode].operand[0].mode;
17177 type = v2di_ftype_v2di;
17180 type = v4si_ftype_v4si;
17183 type = v8hi_ftype_v8hi;
17186 type = v16qi_ftype_v16qi;
17189 type = v4sf_ftype_v4sf;
17192 type = v2df_ftype_v2df;
17195 gcc_unreachable ();
17198 def_builtin (d->name, type, d->code);
17201 /* Initialize target builtin that implements
17202 targetm.vectorize.builtin_mask_for_load. */
17204 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17205 v16qi_ftype_long_pcvoid,
17206 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17207 BUILT_IN_MD, NULL, NULL_TREE);
17208 TREE_READONLY (decl) = 1;
17209 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17210 altivec_builtin_mask_for_load = decl;
17212 /* Access to the vec_init patterns. */
17213 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17214 integer_type_node, integer_type_node,
17215 integer_type_node, NULL_TREE);
17216 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17218 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17219 short_integer_type_node,
17220 short_integer_type_node,
17221 short_integer_type_node,
17222 short_integer_type_node,
17223 short_integer_type_node,
17224 short_integer_type_node,
17225 short_integer_type_node, NULL_TREE);
17226 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17228 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17229 char_type_node, char_type_node,
17230 char_type_node, char_type_node,
17231 char_type_node, char_type_node,
17232 char_type_node, char_type_node,
17233 char_type_node, char_type_node,
17234 char_type_node, char_type_node,
17235 char_type_node, char_type_node,
17236 char_type_node, NULL_TREE);
17237 def_builtin ("__builtin_vec_init_v16qi", ftype,
17238 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17240 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17241 float_type_node, float_type_node,
17242 float_type_node, NULL_TREE);
17243 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17245 /* VSX builtins. */
17246 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17247 double_type_node, NULL_TREE);
17248 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17250 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17251 intDI_type_node, NULL_TREE);
17252 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17254 /* Access to the vec_set patterns. */
17255 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17257 integer_type_node, NULL_TREE);
17258 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17260 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17262 integer_type_node, NULL_TREE);
17263 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17265 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17267 integer_type_node, NULL_TREE);
17268 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17270 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17272 integer_type_node, NULL_TREE);
17273 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17275 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17277 integer_type_node, NULL_TREE);
17278 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17280 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17282 integer_type_node, NULL_TREE);
17283 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17285 /* Access to the vec_extract patterns. */
17286 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17287 integer_type_node, NULL_TREE);
17288 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17290 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17291 integer_type_node, NULL_TREE);
17292 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17294 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17295 integer_type_node, NULL_TREE);
17296 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17298 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17299 integer_type_node, NULL_TREE);
17300 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17302 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17303 integer_type_node, NULL_TREE);
17304 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17306 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17307 integer_type_node, NULL_TREE);
17308 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17311 if (V1TI_type_node)
17313 tree v1ti_ftype_long_pcvoid
17314 = build_function_type_list (V1TI_type_node,
17315 long_integer_type_node, pcvoid_type_node,
17317 tree void_ftype_v1ti_long_pvoid
17318 = build_function_type_list (void_type_node,
17319 V1TI_type_node, long_integer_type_node,
17320 pvoid_type_node, NULL_TREE);
17321 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17322 VSX_BUILTIN_LD_ELEMREV_V1TI);
17323 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17324 VSX_BUILTIN_LXVD2X_V1TI);
17325 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17326 VSX_BUILTIN_STXVD2X_V1TI);
17327 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17328 NULL_TREE, NULL_TREE);
17329 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17330 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17332 integer_type_node, NULL_TREE);
17333 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17334 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17335 integer_type_node, NULL_TREE);
17336 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17342 htm_init_builtins (void)
17344 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17345 const struct builtin_description *d;
17349 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17351 tree op[MAX_HTM_OPERANDS], type;
17352 HOST_WIDE_INT mask = d->mask;
17353 unsigned attr = rs6000_builtin_info[d->code].attr;
17354 bool void_func = (attr & RS6000_BTC_VOID);
17355 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17357 tree gpr_type_node;
17361 /* It is expected that these htm built-in functions may have
17362 d->icode equal to CODE_FOR_nothing. */
17364 if (TARGET_32BIT && TARGET_POWERPC64)
17365 gpr_type_node = long_long_unsigned_type_node;
17367 gpr_type_node = long_unsigned_type_node;
17369 if (attr & RS6000_BTC_SPR)
17371 rettype = gpr_type_node;
17372 argtype = gpr_type_node;
17374 else if (d->code == HTM_BUILTIN_TABORTDC
17375 || d->code == HTM_BUILTIN_TABORTDCI)
17377 rettype = unsigned_type_node;
17378 argtype = gpr_type_node;
17382 rettype = unsigned_type_node;
17383 argtype = unsigned_type_node;
17386 if ((mask & builtin_mask) != mask)
17388 if (TARGET_DEBUG_BUILTIN)
17389 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17395 if (TARGET_DEBUG_BUILTIN)
17396 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17397 (long unsigned) i);
17401 op[nopnds++] = (void_func) ? void_type_node : rettype;
17403 if (attr_args == RS6000_BTC_UNARY)
17404 op[nopnds++] = argtype;
17405 else if (attr_args == RS6000_BTC_BINARY)
17407 op[nopnds++] = argtype;
17408 op[nopnds++] = argtype;
17410 else if (attr_args == RS6000_BTC_TERNARY)
17412 op[nopnds++] = argtype;
17413 op[nopnds++] = argtype;
17414 op[nopnds++] = argtype;
17420 type = build_function_type_list (op[0], NULL_TREE);
17423 type = build_function_type_list (op[0], op[1], NULL_TREE);
17426 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17429 type = build_function_type_list (op[0], op[1], op[2], op[3],
17433 gcc_unreachable ();
17436 def_builtin (d->name, type, d->code);
17440 /* Hash function for builtin functions with up to 3 arguments and a return
17443 builtin_hasher::hash (builtin_hash_struct *bh)
17448 for (i = 0; i < 4; i++)
17450 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17451 ret = (ret * 2) + bh->uns_p[i];
17457 /* Compare builtin hash entries H1 and H2 for equivalence. */
17459 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17461 return ((p1->mode[0] == p2->mode[0])
17462 && (p1->mode[1] == p2->mode[1])
17463 && (p1->mode[2] == p2->mode[2])
17464 && (p1->mode[3] == p2->mode[3])
17465 && (p1->uns_p[0] == p2->uns_p[0])
17466 && (p1->uns_p[1] == p2->uns_p[1])
17467 && (p1->uns_p[2] == p2->uns_p[2])
17468 && (p1->uns_p[3] == p2->uns_p[3]));
17471 /* Map types for builtin functions with an explicit return type and up to 3
17472 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17473 of the argument. */
17475 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17476 machine_mode mode_arg1, machine_mode mode_arg2,
17477 enum rs6000_builtins builtin, const char *name)
17479 struct builtin_hash_struct h;
17480 struct builtin_hash_struct *h2;
17483 tree ret_type = NULL_TREE;
17484 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17486 /* Create builtin_hash_table. */
17487 if (builtin_hash_table == NULL)
17488 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17490 h.type = NULL_TREE;
17491 h.mode[0] = mode_ret;
17492 h.mode[1] = mode_arg0;
17493 h.mode[2] = mode_arg1;
17494 h.mode[3] = mode_arg2;
17500 /* If the builtin is a type that produces unsigned results or takes unsigned
17501 arguments, and it is returned as a decl for the vectorizer (such as
17502 widening multiplies, permute), make sure the arguments and return value
17503 are type correct. */
17506 /* unsigned 1 argument functions. */
17507 case CRYPTO_BUILTIN_VSBOX:
17508 case P8V_BUILTIN_VGBBD:
17509 case MISC_BUILTIN_CDTBCD:
17510 case MISC_BUILTIN_CBCDTD:
17515 /* unsigned 2 argument functions. */
17516 case ALTIVEC_BUILTIN_VMULEUB:
17517 case ALTIVEC_BUILTIN_VMULEUH:
17518 case P8V_BUILTIN_VMULEUW:
17519 case ALTIVEC_BUILTIN_VMULOUB:
17520 case ALTIVEC_BUILTIN_VMULOUH:
17521 case P8V_BUILTIN_VMULOUW:
17522 case CRYPTO_BUILTIN_VCIPHER:
17523 case CRYPTO_BUILTIN_VCIPHERLAST:
17524 case CRYPTO_BUILTIN_VNCIPHER:
17525 case CRYPTO_BUILTIN_VNCIPHERLAST:
17526 case CRYPTO_BUILTIN_VPMSUMB:
17527 case CRYPTO_BUILTIN_VPMSUMH:
17528 case CRYPTO_BUILTIN_VPMSUMW:
17529 case CRYPTO_BUILTIN_VPMSUMD:
17530 case CRYPTO_BUILTIN_VPMSUM:
17531 case MISC_BUILTIN_ADDG6S:
17532 case MISC_BUILTIN_DIVWEU:
17533 case MISC_BUILTIN_DIVDEU:
17534 case VSX_BUILTIN_UDIV_V2DI:
17535 case ALTIVEC_BUILTIN_VMAXUB:
17536 case ALTIVEC_BUILTIN_VMINUB:
17537 case ALTIVEC_BUILTIN_VMAXUH:
17538 case ALTIVEC_BUILTIN_VMINUH:
17539 case ALTIVEC_BUILTIN_VMAXUW:
17540 case ALTIVEC_BUILTIN_VMINUW:
17541 case P8V_BUILTIN_VMAXUD:
17542 case P8V_BUILTIN_VMINUD:
17548 /* unsigned 3 argument functions. */
17549 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17550 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17551 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17552 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17553 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17554 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17555 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17556 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17557 case VSX_BUILTIN_VPERM_16QI_UNS:
17558 case VSX_BUILTIN_VPERM_8HI_UNS:
17559 case VSX_BUILTIN_VPERM_4SI_UNS:
17560 case VSX_BUILTIN_VPERM_2DI_UNS:
17561 case VSX_BUILTIN_XXSEL_16QI_UNS:
17562 case VSX_BUILTIN_XXSEL_8HI_UNS:
17563 case VSX_BUILTIN_XXSEL_4SI_UNS:
17564 case VSX_BUILTIN_XXSEL_2DI_UNS:
17565 case CRYPTO_BUILTIN_VPERMXOR:
17566 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17567 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17568 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17569 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17570 case CRYPTO_BUILTIN_VSHASIGMAW:
17571 case CRYPTO_BUILTIN_VSHASIGMAD:
17572 case CRYPTO_BUILTIN_VSHASIGMA:
17579 /* signed permute functions with unsigned char mask. */
17580 case ALTIVEC_BUILTIN_VPERM_16QI:
17581 case ALTIVEC_BUILTIN_VPERM_8HI:
17582 case ALTIVEC_BUILTIN_VPERM_4SI:
17583 case ALTIVEC_BUILTIN_VPERM_4SF:
17584 case ALTIVEC_BUILTIN_VPERM_2DI:
17585 case ALTIVEC_BUILTIN_VPERM_2DF:
17586 case VSX_BUILTIN_VPERM_16QI:
17587 case VSX_BUILTIN_VPERM_8HI:
17588 case VSX_BUILTIN_VPERM_4SI:
17589 case VSX_BUILTIN_VPERM_4SF:
17590 case VSX_BUILTIN_VPERM_2DI:
17591 case VSX_BUILTIN_VPERM_2DF:
17595 /* unsigned args, signed return. */
17596 case VSX_BUILTIN_XVCVUXDSP:
17597 case VSX_BUILTIN_XVCVUXDDP_UNS:
17598 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17602 /* signed args, unsigned return. */
17603 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17604 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17605 case MISC_BUILTIN_UNPACK_TD:
17606 case MISC_BUILTIN_UNPACK_V1TI:
17610 /* unsigned arguments, bool return (compares). */
17611 case ALTIVEC_BUILTIN_VCMPEQUB:
17612 case ALTIVEC_BUILTIN_VCMPEQUH:
17613 case ALTIVEC_BUILTIN_VCMPEQUW:
17614 case P8V_BUILTIN_VCMPEQUD:
17615 case VSX_BUILTIN_CMPGE_U16QI:
17616 case VSX_BUILTIN_CMPGE_U8HI:
17617 case VSX_BUILTIN_CMPGE_U4SI:
17618 case VSX_BUILTIN_CMPGE_U2DI:
17619 case ALTIVEC_BUILTIN_VCMPGTUB:
17620 case ALTIVEC_BUILTIN_VCMPGTUH:
17621 case ALTIVEC_BUILTIN_VCMPGTUW:
17622 case P8V_BUILTIN_VCMPGTUD:
17627 /* unsigned arguments for 128-bit pack instructions. */
17628 case MISC_BUILTIN_PACK_TD:
17629 case MISC_BUILTIN_PACK_V1TI:
17634 /* unsigned second arguments (vector shift right). */
17635 case ALTIVEC_BUILTIN_VSRB:
17636 case ALTIVEC_BUILTIN_VSRH:
17637 case ALTIVEC_BUILTIN_VSRW:
17638 case P8V_BUILTIN_VSRD:
17646 /* Figure out how many args are present. */
17647 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17650 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17651 if (!ret_type && h.uns_p[0])
17652 ret_type = builtin_mode_to_type[h.mode[0]][0];
17655 fatal_error (input_location,
17656 "internal error: builtin function %qs had an unexpected "
17657 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17659 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17660 arg_type[i] = NULL_TREE;
17662 for (i = 0; i < num_args; i++)
17664 int m = (int) h.mode[i+1];
17665 int uns_p = h.uns_p[i+1];
17667 arg_type[i] = builtin_mode_to_type[m][uns_p];
17668 if (!arg_type[i] && uns_p)
17669 arg_type[i] = builtin_mode_to_type[m][0];
17672 fatal_error (input_location,
17673 "internal error: builtin function %qs, argument %d "
17674 "had unexpected argument type %qs", name, i,
17675 GET_MODE_NAME (m));
17678 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17679 if (*found == NULL)
17681 h2 = ggc_alloc<builtin_hash_struct> ();
17685 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17686 arg_type[2], NULL_TREE);
17689 return (*found)->type;
17693 rs6000_common_init_builtins (void)
17695 const struct builtin_description *d;
17698 tree opaque_ftype_opaque = NULL_TREE;
17699 tree opaque_ftype_opaque_opaque = NULL_TREE;
17700 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17701 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17703 /* Create Altivec and VSX builtins on machines with at least the
17704 general purpose extensions (970 and newer) to allow the use of
17705 the target attribute. */
17707 if (TARGET_EXTRA_BUILTINS)
17708 builtin_mask |= RS6000_BTM_COMMON;
17710 /* Add the ternary operators. */
17712 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17715 HOST_WIDE_INT mask = d->mask;
17717 if ((mask & builtin_mask) != mask)
17719 if (TARGET_DEBUG_BUILTIN)
17720 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17724 if (rs6000_overloaded_builtin_p (d->code))
17726 if (! (type = opaque_ftype_opaque_opaque_opaque))
17727 type = opaque_ftype_opaque_opaque_opaque
17728 = build_function_type_list (opaque_V4SI_type_node,
17729 opaque_V4SI_type_node,
17730 opaque_V4SI_type_node,
17731 opaque_V4SI_type_node,
17736 enum insn_code icode = d->icode;
17739 if (TARGET_DEBUG_BUILTIN)
17740 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17746 if (icode == CODE_FOR_nothing)
17748 if (TARGET_DEBUG_BUILTIN)
17749 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17755 type = builtin_function_type (insn_data[icode].operand[0].mode,
17756 insn_data[icode].operand[1].mode,
17757 insn_data[icode].operand[2].mode,
17758 insn_data[icode].operand[3].mode,
17762 def_builtin (d->name, type, d->code);
17765 /* Add the binary operators. */
17767 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17769 machine_mode mode0, mode1, mode2;
17771 HOST_WIDE_INT mask = d->mask;
17773 if ((mask & builtin_mask) != mask)
17775 if (TARGET_DEBUG_BUILTIN)
17776 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17780 if (rs6000_overloaded_builtin_p (d->code))
17782 if (! (type = opaque_ftype_opaque_opaque))
17783 type = opaque_ftype_opaque_opaque
17784 = build_function_type_list (opaque_V4SI_type_node,
17785 opaque_V4SI_type_node,
17786 opaque_V4SI_type_node,
17791 enum insn_code icode = d->icode;
17794 if (TARGET_DEBUG_BUILTIN)
17795 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17801 if (icode == CODE_FOR_nothing)
17803 if (TARGET_DEBUG_BUILTIN)
17804 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17810 mode0 = insn_data[icode].operand[0].mode;
17811 mode1 = insn_data[icode].operand[1].mode;
17812 mode2 = insn_data[icode].operand[2].mode;
17814 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17818 def_builtin (d->name, type, d->code);
17821 /* Add the simple unary operators. */
17823 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17825 machine_mode mode0, mode1;
17827 HOST_WIDE_INT mask = d->mask;
17829 if ((mask & builtin_mask) != mask)
17831 if (TARGET_DEBUG_BUILTIN)
17832 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17836 if (rs6000_overloaded_builtin_p (d->code))
17838 if (! (type = opaque_ftype_opaque))
17839 type = opaque_ftype_opaque
17840 = build_function_type_list (opaque_V4SI_type_node,
17841 opaque_V4SI_type_node,
17846 enum insn_code icode = d->icode;
17849 if (TARGET_DEBUG_BUILTIN)
17850 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17856 if (icode == CODE_FOR_nothing)
17858 if (TARGET_DEBUG_BUILTIN)
17859 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17865 mode0 = insn_data[icode].operand[0].mode;
17866 mode1 = insn_data[icode].operand[1].mode;
17868 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17872 def_builtin (d->name, type, d->code);
17875 /* Add the simple no-argument operators. */
17877 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17879 machine_mode mode0;
17881 HOST_WIDE_INT mask = d->mask;
17883 if ((mask & builtin_mask) != mask)
17885 if (TARGET_DEBUG_BUILTIN)
17886 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17889 if (rs6000_overloaded_builtin_p (d->code))
17891 if (!opaque_ftype_opaque)
17892 opaque_ftype_opaque
17893 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17894 type = opaque_ftype_opaque;
17898 enum insn_code icode = d->icode;
17901 if (TARGET_DEBUG_BUILTIN)
17902 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17903 (long unsigned) i);
17906 if (icode == CODE_FOR_nothing)
17908 if (TARGET_DEBUG_BUILTIN)
17910 "rs6000_builtin, skip no-argument %s (no code)\n",
17914 mode0 = insn_data[icode].operand[0].mode;
17915 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17918 def_builtin (d->name, type, d->code);
17922 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17924 init_float128_ibm (machine_mode mode)
17926 if (!TARGET_XL_COMPAT)
17928 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17929 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17930 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17931 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17933 if (!TARGET_HARD_FLOAT)
17935 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17936 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17937 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17938 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17939 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17940 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17941 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17942 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17944 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17945 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17946 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17947 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17948 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17949 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17950 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17951 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17956 set_optab_libfunc (add_optab, mode, "_xlqadd");
17957 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17958 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17959 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17962 /* Add various conversions for IFmode to use the traditional TFmode
17964 if (mode == IFmode)
17966 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf");
17967 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf");
17968 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdtf");
17969 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd");
17970 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd");
17971 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtftd");
17973 if (TARGET_POWERPC64)
17975 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17976 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17977 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17978 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17983 /* Create a decl for either complex long double multiply or complex long double
17984 divide when long double is IEEE 128-bit floating point. We can't use
17985 __multc3 and __divtc3 because the original long double using IBM extended
17986 double used those names. The complex multiply/divide functions are encoded
17987 as builtin functions with a complex result and 4 scalar inputs. */
17990 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17992 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17995 set_builtin_decl (fncode, fndecl, true);
17997 if (TARGET_DEBUG_BUILTIN)
17998 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
18003 /* Set up IEEE 128-bit floating point routines. Use different names if the
18004 arguments can be passed in a vector register. The historical PowerPC
18005 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18006 continue to use that if we aren't using vector registers to pass IEEE
18007 128-bit floating point. */
18010 init_float128_ieee (machine_mode mode)
18012 if (FLOAT128_VECTOR_P (mode))
18014 static bool complex_muldiv_init_p = false;
18016 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
18017 we have clone or target attributes, this will be called a second
18018 time. We want to create the built-in function only once. */
18019 if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
18021 complex_muldiv_init_p = true;
18022 built_in_function fncode_mul =
18023 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
18024 - MIN_MODE_COMPLEX_FLOAT);
18025 built_in_function fncode_div =
18026 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
18027 - MIN_MODE_COMPLEX_FLOAT);
18029 tree fntype = build_function_type_list (complex_long_double_type_node,
18030 long_double_type_node,
18031 long_double_type_node,
18032 long_double_type_node,
18033 long_double_type_node,
18036 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
18037 create_complex_muldiv ("__divkc3", fncode_div, fntype);
18040 set_optab_libfunc (add_optab, mode, "__addkf3");
18041 set_optab_libfunc (sub_optab, mode, "__subkf3");
18042 set_optab_libfunc (neg_optab, mode, "__negkf2");
18043 set_optab_libfunc (smul_optab, mode, "__mulkf3");
18044 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
18045 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
18046 set_optab_libfunc (abs_optab, mode, "__abskf2");
18047 set_optab_libfunc (powi_optab, mode, "__powikf2");
18049 set_optab_libfunc (eq_optab, mode, "__eqkf2");
18050 set_optab_libfunc (ne_optab, mode, "__nekf2");
18051 set_optab_libfunc (gt_optab, mode, "__gtkf2");
18052 set_optab_libfunc (ge_optab, mode, "__gekf2");
18053 set_optab_libfunc (lt_optab, mode, "__ltkf2");
18054 set_optab_libfunc (le_optab, mode, "__lekf2");
18055 set_optab_libfunc (unord_optab, mode, "__unordkf2");
18057 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
18058 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
18059 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
18060 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
18062 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
18063 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18064 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
18066 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
18067 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18068 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
18070 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf");
18071 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf");
18072 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdkf");
18073 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd");
18074 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd");
18075 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendkftd");
18077 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
18078 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
18079 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
18080 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
18082 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
18083 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
18084 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
18085 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
18087 if (TARGET_POWERPC64)
18089 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
18090 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
18091 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
18092 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
18098 set_optab_libfunc (add_optab, mode, "_q_add");
18099 set_optab_libfunc (sub_optab, mode, "_q_sub");
18100 set_optab_libfunc (neg_optab, mode, "_q_neg");
18101 set_optab_libfunc (smul_optab, mode, "_q_mul");
18102 set_optab_libfunc (sdiv_optab, mode, "_q_div");
18103 if (TARGET_PPC_GPOPT)
18104 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
18106 set_optab_libfunc (eq_optab, mode, "_q_feq");
18107 set_optab_libfunc (ne_optab, mode, "_q_fne");
18108 set_optab_libfunc (gt_optab, mode, "_q_fgt");
18109 set_optab_libfunc (ge_optab, mode, "_q_fge");
18110 set_optab_libfunc (lt_optab, mode, "_q_flt");
18111 set_optab_libfunc (le_optab, mode, "_q_fle");
18113 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
18114 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
18115 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
18116 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
18117 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
18118 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
18119 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
18120 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
18125 rs6000_init_libfuncs (void)
18127 /* __float128 support. */
18128 if (TARGET_FLOAT128_TYPE)
18130 init_float128_ibm (IFmode);
18131 init_float128_ieee (KFmode);
18134 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18135 if (TARGET_LONG_DOUBLE_128)
18137 if (!TARGET_IEEEQUAD)
18138 init_float128_ibm (TFmode);
18140 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18142 init_float128_ieee (TFmode);
18146 /* Emit a potentially record-form instruction, setting DST from SRC.
18147 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18148 signed comparison of DST with zero. If DOT is 1, the generated RTL
18149 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18150 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18151 a separate COMPARE. */
18154 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18158 emit_move_insn (dst, src);
18162 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18164 emit_move_insn (dst, src);
18165 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18169 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18172 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18173 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18177 rtx set = gen_rtx_SET (dst, src);
18178 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18183 /* A validation routine: say whether CODE, a condition code, and MODE
18184 match. The other alternatives either don't make sense or should
18185 never be generated. */
18188 validate_condition_mode (enum rtx_code code, machine_mode mode)
18190 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18191 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18192 && GET_MODE_CLASS (mode) == MODE_CC);
18194 /* These don't make sense. */
18195 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18196 || mode != CCUNSmode);
18198 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18199 || mode == CCUNSmode);
18201 gcc_assert (mode == CCFPmode
18202 || (code != ORDERED && code != UNORDERED
18203 && code != UNEQ && code != LTGT
18204 && code != UNGT && code != UNLT
18205 && code != UNGE && code != UNLE));
18207 /* These should never be generated except for
18208 flag_finite_math_only. */
18209 gcc_assert (mode != CCFPmode
18210 || flag_finite_math_only
18211 || (code != LE && code != GE
18212 && code != UNEQ && code != LTGT
18213 && code != UNGT && code != UNLT));
18215 /* These are invalid; the information is not there. */
18216 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18220 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18221 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18222 not zero, store there the bit offset (counted from the right) where
18223 the single stretch of 1 bits begins; and similarly for B, the bit
18224 offset where it ends. */
18227 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18229 unsigned HOST_WIDE_INT val = INTVAL (mask);
18230 unsigned HOST_WIDE_INT bit;
18232 int n = GET_MODE_PRECISION (mode);
18234 if (mode != DImode && mode != SImode)
18237 if (INTVAL (mask) >= 0)
18240 ne = exact_log2 (bit);
18241 nb = exact_log2 (val + bit);
18243 else if (val + 1 == 0)
18252 nb = exact_log2 (bit);
18253 ne = exact_log2 (val + bit);
18258 ne = exact_log2 (bit);
18259 if (val + bit == 0)
18267 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18278 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18279 or rldicr instruction, to implement an AND with it in mode MODE. */
18282 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18286 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18289 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18291 if (mode == DImode)
18292 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18294 /* For SImode, rlwinm can do everything. */
18295 if (mode == SImode)
18296 return (nb < 32 && ne < 32);
18301 /* Return the instruction template for an AND with mask in mode MODE, with
18302 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18305 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18309 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18310 gcc_unreachable ();
18312 if (mode == DImode && ne == 0)
18314 operands[3] = GEN_INT (63 - nb);
18316 return "rldicl. %0,%1,0,%3";
18317 return "rldicl %0,%1,0,%3";
18320 if (mode == DImode && nb == 63)
18322 operands[3] = GEN_INT (63 - ne);
18324 return "rldicr. %0,%1,0,%3";
18325 return "rldicr %0,%1,0,%3";
18328 if (nb < 32 && ne < 32)
18330 operands[3] = GEN_INT (31 - nb);
18331 operands[4] = GEN_INT (31 - ne);
18333 return "rlwinm. %0,%1,0,%3,%4";
18334 return "rlwinm %0,%1,0,%3,%4";
18337 gcc_unreachable ();
18340 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18341 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18342 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18345 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18349 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18352 int n = GET_MODE_PRECISION (mode);
18355 if (CONST_INT_P (XEXP (shift, 1)))
18357 sh = INTVAL (XEXP (shift, 1));
18358 if (sh < 0 || sh >= n)
18362 rtx_code code = GET_CODE (shift);
18364 /* Convert any shift by 0 to a rotate, to simplify below code. */
18368 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18369 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18371 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18377 /* DImode rotates need rld*. */
18378 if (mode == DImode && code == ROTATE)
18379 return (nb == 63 || ne == 0 || ne == sh);
18381 /* SImode rotates need rlw*. */
18382 if (mode == SImode && code == ROTATE)
18383 return (nb < 32 && ne < 32 && sh < 32);
18385 /* Wrap-around masks are only okay for rotates. */
18389 /* Variable shifts are only okay for rotates. */
18393 /* Don't allow ASHIFT if the mask is wrong for that. */
18394 if (code == ASHIFT && ne < sh)
18397 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18398 if the mask is wrong for that. */
18399 if (nb < 32 && ne < 32 && sh < 32
18400 && !(code == LSHIFTRT && nb >= 32 - sh))
18403 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18404 if the mask is wrong for that. */
18405 if (code == LSHIFTRT)
18407 if (nb == 63 || ne == 0 || ne == sh)
18408 return !(code == LSHIFTRT && nb >= sh);
18413 /* Return the instruction template for a shift with mask in mode MODE, with
18414 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18417 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18421 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18422 gcc_unreachable ();
18424 if (mode == DImode && ne == 0)
18426 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18427 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18428 operands[3] = GEN_INT (63 - nb);
18430 return "rld%I2cl. %0,%1,%2,%3";
18431 return "rld%I2cl %0,%1,%2,%3";
18434 if (mode == DImode && nb == 63)
18436 operands[3] = GEN_INT (63 - ne);
18438 return "rld%I2cr. %0,%1,%2,%3";
18439 return "rld%I2cr %0,%1,%2,%3";
18443 && GET_CODE (operands[4]) != LSHIFTRT
18444 && CONST_INT_P (operands[2])
18445 && ne == INTVAL (operands[2]))
18447 operands[3] = GEN_INT (63 - nb);
18449 return "rld%I2c. %0,%1,%2,%3";
18450 return "rld%I2c %0,%1,%2,%3";
18453 if (nb < 32 && ne < 32)
18455 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18456 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18457 operands[3] = GEN_INT (31 - nb);
18458 operands[4] = GEN_INT (31 - ne);
18459 /* This insn can also be a 64-bit rotate with mask that really makes
18460 it just a shift right (with mask); the %h below are to adjust for
18461 that situation (shift count is >= 32 in that case). */
18463 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18464 return "rlw%I2nm %0,%1,%h2,%3,%4";
18467 gcc_unreachable ();
18470 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18471 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18472 ASHIFT, or LSHIFTRT) in mode MODE. */
18475 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18479 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18482 int n = GET_MODE_PRECISION (mode);
18484 int sh = INTVAL (XEXP (shift, 1));
18485 if (sh < 0 || sh >= n)
18488 rtx_code code = GET_CODE (shift);
18490 /* Convert any shift by 0 to a rotate, to simplify below code. */
18494 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18495 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18497 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18503 /* DImode rotates need rldimi. */
18504 if (mode == DImode && code == ROTATE)
18507 /* SImode rotates need rlwimi. */
18508 if (mode == SImode && code == ROTATE)
18509 return (nb < 32 && ne < 32 && sh < 32);
18511 /* Wrap-around masks are only okay for rotates. */
18515 /* Don't allow ASHIFT if the mask is wrong for that. */
18516 if (code == ASHIFT && ne < sh)
18519 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18520 if the mask is wrong for that. */
18521 if (nb < 32 && ne < 32 && sh < 32
18522 && !(code == LSHIFTRT && nb >= 32 - sh))
18525 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18526 if the mask is wrong for that. */
18527 if (code == LSHIFTRT)
18530 return !(code == LSHIFTRT && nb >= sh);
18535 /* Return the instruction template for an insert with mask in mode MODE, with
18536 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18539 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18543 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18544 gcc_unreachable ();
18546 /* Prefer rldimi because rlwimi is cracked. */
18547 if (TARGET_POWERPC64
18548 && (!dot || mode == DImode)
18549 && GET_CODE (operands[4]) != LSHIFTRT
18550 && ne == INTVAL (operands[2]))
18552 operands[3] = GEN_INT (63 - nb);
18554 return "rldimi. %0,%1,%2,%3";
18555 return "rldimi %0,%1,%2,%3";
18558 if (nb < 32 && ne < 32)
18560 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18561 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18562 operands[3] = GEN_INT (31 - nb);
18563 operands[4] = GEN_INT (31 - ne);
18565 return "rlwimi. %0,%1,%2,%3,%4";
18566 return "rlwimi %0,%1,%2,%3,%4";
18569 gcc_unreachable ();
18572 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18573 using two machine instructions. */
18576 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18578 /* There are two kinds of AND we can handle with two insns:
18579 1) those we can do with two rl* insn;
18582 We do not handle that last case yet. */
18584 /* If there is just one stretch of ones, we can do it. */
18585 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18588 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18589 one insn, we can do the whole thing with two. */
18590 unsigned HOST_WIDE_INT val = INTVAL (c);
18591 unsigned HOST_WIDE_INT bit1 = val & -val;
18592 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18593 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18594 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18595 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18598 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18599 If EXPAND is true, split rotate-and-mask instructions we generate to
18600 their constituent parts as well (this is used during expand); if DOT
18601 is 1, make the last insn a record-form instruction clobbering the
18602 destination GPR and setting the CC reg (from operands[3]); if 2, set
18603 that GPR as well as the CC reg. */
18606 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18608 gcc_assert (!(expand && dot));
18610 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18612 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18613 shift right. This generates better code than doing the masks without
18614 shifts, or shifting first right and then left. */
18616 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18618 gcc_assert (mode == DImode);
18620 int shift = 63 - nb;
18623 rtx tmp1 = gen_reg_rtx (DImode);
18624 rtx tmp2 = gen_reg_rtx (DImode);
18625 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18626 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18627 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18631 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18632 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18633 emit_move_insn (operands[0], tmp);
18634 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18635 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18640 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18641 that does the rest. */
18642 unsigned HOST_WIDE_INT bit1 = val & -val;
18643 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18644 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18645 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18647 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18648 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18650 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18652 /* Two "no-rotate"-and-mask instructions, for SImode. */
18653 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18655 gcc_assert (mode == SImode);
18657 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18658 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18659 emit_move_insn (reg, tmp);
18660 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18661 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18665 gcc_assert (mode == DImode);
18667 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18668 insns; we have to do the first in SImode, because it wraps. */
18669 if (mask2 <= 0xffffffff
18670 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18672 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18673 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18675 rtx reg_low = gen_lowpart (SImode, reg);
18676 emit_move_insn (reg_low, tmp);
18677 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18678 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18682 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18683 at the top end), rotate back and clear the other hole. */
18684 int right = exact_log2 (bit3);
18685 int left = 64 - right;
18687 /* Rotate the mask too. */
18688 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18692 rtx tmp1 = gen_reg_rtx (DImode);
18693 rtx tmp2 = gen_reg_rtx (DImode);
18694 rtx tmp3 = gen_reg_rtx (DImode);
18695 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18696 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18697 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18698 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18702 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18703 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18704 emit_move_insn (operands[0], tmp);
18705 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18706 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18707 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18711 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18712 for lfq and stfq insns iff the registers are hard registers. */
18715 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18717 /* We might have been passed a SUBREG. */
18718 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
18721 /* We might have been passed non floating point registers. */
18722 if (!FP_REGNO_P (REGNO (reg1))
18723 || !FP_REGNO_P (REGNO (reg2)))
18726 return (REGNO (reg1) == REGNO (reg2) - 1);
18729 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18730 addr1 and addr2 must be in consecutive memory locations
18731 (addr2 == addr1 + 8). */
18734 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18737 unsigned int reg1, reg2;
18738 int offset1, offset2;
18740 /* The mems cannot be volatile. */
18741 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18744 addr1 = XEXP (mem1, 0);
18745 addr2 = XEXP (mem2, 0);
18747 /* Extract an offset (if used) from the first addr. */
18748 if (GET_CODE (addr1) == PLUS)
18750 /* If not a REG, return zero. */
18751 if (GET_CODE (XEXP (addr1, 0)) != REG)
18755 reg1 = REGNO (XEXP (addr1, 0));
18756 /* The offset must be constant! */
18757 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
18759 offset1 = INTVAL (XEXP (addr1, 1));
18762 else if (GET_CODE (addr1) != REG)
18766 reg1 = REGNO (addr1);
18767 /* This was a simple (mem (reg)) expression. Offset is 0. */
18771 /* And now for the second addr. */
18772 if (GET_CODE (addr2) == PLUS)
18774 /* If not a REG, return zero. */
18775 if (GET_CODE (XEXP (addr2, 0)) != REG)
18779 reg2 = REGNO (XEXP (addr2, 0));
18780 /* The offset must be constant. */
18781 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
18783 offset2 = INTVAL (XEXP (addr2, 1));
18786 else if (GET_CODE (addr2) != REG)
18790 reg2 = REGNO (addr2);
18791 /* This was a simple (mem (reg)) expression. Offset is 0. */
18795 /* Both of these must have the same base register. */
18799 /* The offset for the second addr must be 8 more than the first addr. */
18800 if (offset2 != offset1 + 8)
18803 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18808 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18809 need to use DDmode, in all other cases we can use the same mode. */
18810 static machine_mode
18811 rs6000_secondary_memory_needed_mode (machine_mode mode)
18813 if (lra_in_progress && mode == SDmode)
18818 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18819 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18820 only work on the traditional altivec registers, note if an altivec register
18823 static enum rs6000_reg_type
18824 register_to_reg_type (rtx reg, bool *is_altivec)
18826 HOST_WIDE_INT regno;
18827 enum reg_class rclass;
18829 if (GET_CODE (reg) == SUBREG)
18830 reg = SUBREG_REG (reg);
18833 return NO_REG_TYPE;
18835 regno = REGNO (reg);
18836 if (regno >= FIRST_PSEUDO_REGISTER)
18838 if (!lra_in_progress && !reload_completed)
18839 return PSEUDO_REG_TYPE;
18841 regno = true_regnum (reg);
18842 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
18843 return PSEUDO_REG_TYPE;
18846 gcc_assert (regno >= 0);
18848 if (is_altivec && ALTIVEC_REGNO_P (regno))
18849 *is_altivec = true;
18851 rclass = rs6000_regno_regclass[regno];
18852 return reg_class_to_reg_type[(int)rclass];
18855 /* Helper function to return the cost of adding a TOC entry address. */
18858 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18862 if (TARGET_CMODEL != CMODEL_SMALL)
18863 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18866 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18871 /* Helper function for rs6000_secondary_reload to determine whether the memory
18872 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18873 needs reloading. Return negative if the memory is not handled by the memory
18874 helper functions and to try a different reload method, 0 if no additional
18875 instructions are need, and positive to give the extra cost for the
18879 rs6000_secondary_reload_memory (rtx addr,
18880 enum reg_class rclass,
18883 int extra_cost = 0;
18884 rtx reg, and_arg, plus_arg0, plus_arg1;
18885 addr_mask_type addr_mask;
18886 const char *type = NULL;
18887 const char *fail_msg = NULL;
18889 if (GPR_REG_CLASS_P (rclass))
18890 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18892 else if (rclass == FLOAT_REGS)
18893 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18895 else if (rclass == ALTIVEC_REGS)
18896 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18898 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18899 else if (rclass == VSX_REGS)
18900 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18901 & ~RELOAD_REG_AND_M16);
18903 /* If the register allocator hasn't made up its mind yet on the register
18904 class to use, settle on defaults to use. */
18905 else if (rclass == NO_REGS)
18907 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18908 & ~RELOAD_REG_AND_M16);
18910 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18911 addr_mask &= ~(RELOAD_REG_INDEXED
18912 | RELOAD_REG_PRE_INCDEC
18913 | RELOAD_REG_PRE_MODIFY);
18919 /* If the register isn't valid in this register class, just return now. */
18920 if ((addr_mask & RELOAD_REG_VALID) == 0)
18922 if (TARGET_DEBUG_ADDR)
18925 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18926 "not valid in class\n",
18927 GET_MODE_NAME (mode), reg_class_names[rclass]);
18934 switch (GET_CODE (addr))
18936 /* Does the register class supports auto update forms for this mode? We
18937 don't need a scratch register, since the powerpc only supports
18938 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18941 reg = XEXP (addr, 0);
18942 if (!base_reg_operand (addr, GET_MODE (reg)))
18944 fail_msg = "no base register #1";
18948 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18956 reg = XEXP (addr, 0);
18957 plus_arg1 = XEXP (addr, 1);
18958 if (!base_reg_operand (reg, GET_MODE (reg))
18959 || GET_CODE (plus_arg1) != PLUS
18960 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18962 fail_msg = "bad PRE_MODIFY";
18966 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18973 /* Do we need to simulate AND -16 to clear the bottom address bits used
18974 in VMX load/stores? Only allow the AND for vector sizes. */
18976 and_arg = XEXP (addr, 0);
18977 if (GET_MODE_SIZE (mode) != 16
18978 || GET_CODE (XEXP (addr, 1)) != CONST_INT
18979 || INTVAL (XEXP (addr, 1)) != -16)
18981 fail_msg = "bad Altivec AND #1";
18985 if (rclass != ALTIVEC_REGS)
18987 if (legitimate_indirect_address_p (and_arg, false))
18990 else if (legitimate_indexed_address_p (and_arg, false))
18995 fail_msg = "bad Altivec AND #2";
19003 /* If this is an indirect address, make sure it is a base register. */
19006 if (!legitimate_indirect_address_p (addr, false))
19013 /* If this is an indexed address, make sure the register class can handle
19014 indexed addresses for this mode. */
19016 plus_arg0 = XEXP (addr, 0);
19017 plus_arg1 = XEXP (addr, 1);
19019 /* (plus (plus (reg) (constant)) (constant)) is generated during
19020 push_reload processing, so handle it now. */
19021 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
19023 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19030 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19031 push_reload processing, so handle it now. */
19032 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
19034 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19037 type = "indexed #2";
19041 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
19043 fail_msg = "no base register #2";
19047 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
19049 if ((addr_mask & RELOAD_REG_INDEXED) == 0
19050 || !legitimate_indexed_address_p (addr, false))
19057 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
19058 && CONST_INT_P (plus_arg1))
19060 if (!quad_address_offset_p (INTVAL (plus_arg1)))
19063 type = "vector d-form offset";
19067 /* Make sure the register class can handle offset addresses. */
19068 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19070 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19073 type = "offset #2";
19079 fail_msg = "bad PLUS";
19086 /* Quad offsets are restricted and can't handle normal addresses. */
19087 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19090 type = "vector d-form lo_sum";
19093 else if (!legitimate_lo_sum_address_p (mode, addr, false))
19095 fail_msg = "bad LO_SUM";
19099 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19106 /* Static addresses need to create a TOC entry. */
19110 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19113 type = "vector d-form lo_sum #2";
19119 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
19123 /* TOC references look like offsetable memory. */
19125 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
19127 fail_msg = "bad UNSPEC";
19131 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19134 type = "vector d-form lo_sum #3";
19137 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19140 type = "toc reference";
19146 fail_msg = "bad address";
19151 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19153 if (extra_cost < 0)
19155 "rs6000_secondary_reload_memory error: mode = %s, "
19156 "class = %s, addr_mask = '%s', %s\n",
19157 GET_MODE_NAME (mode),
19158 reg_class_names[rclass],
19159 rs6000_debug_addr_mask (addr_mask, false),
19160 (fail_msg != NULL) ? fail_msg : "<bad address>");
19164 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19165 "addr_mask = '%s', extra cost = %d, %s\n",
19166 GET_MODE_NAME (mode),
19167 reg_class_names[rclass],
19168 rs6000_debug_addr_mask (addr_mask, false),
19170 (type) ? type : "<none>");
19178 /* Helper function for rs6000_secondary_reload to return true if a move to a
19179 different register classe is really a simple move. */
19182 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19183 enum rs6000_reg_type from_type,
19186 int size = GET_MODE_SIZE (mode);
19188 /* Add support for various direct moves available. In this function, we only
19189 look at cases where we don't need any extra registers, and one or more
19190 simple move insns are issued. Originally small integers are not allowed
19191 in FPR/VSX registers. Single precision binary floating is not a simple
19192 move because we need to convert to the single precision memory layout.
19193 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19194 need special direct move handling, which we do not support yet. */
19195 if (TARGET_DIRECT_MOVE
19196 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19197 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19199 if (TARGET_POWERPC64)
19201 /* ISA 2.07: MTVSRD or MVFVSRD. */
19205 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19206 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19210 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19211 if (TARGET_P8_VECTOR)
19213 if (mode == SImode)
19216 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19220 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19221 if (mode == SDmode)
19225 /* Power6+: MFTGPR or MFFGPR. */
19226 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19227 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19228 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19231 /* Move to/from SPR. */
19232 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19233 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19234 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19240 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19241 special direct moves that involve allocating an extra register, return the
19242 insn code of the helper function if there is such a function or
19243 CODE_FOR_nothing if not. */
19246 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19247 enum rs6000_reg_type from_type,
19249 secondary_reload_info *sri,
19253 enum insn_code icode = CODE_FOR_nothing;
19255 int size = GET_MODE_SIZE (mode);
19257 if (TARGET_POWERPC64 && size == 16)
19259 /* Handle moving 128-bit values from GPRs to VSX point registers on
19260 ISA 2.07 (power8, power9) when running in 64-bit mode using
19261 XXPERMDI to glue the two 64-bit values back together. */
19262 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19264 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19265 icode = reg_addr[mode].reload_vsx_gpr;
19268 /* Handle moving 128-bit values from VSX point registers to GPRs on
19269 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19270 bottom 64-bit value. */
19271 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19273 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19274 icode = reg_addr[mode].reload_gpr_vsx;
19278 else if (TARGET_POWERPC64 && mode == SFmode)
19280 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19282 cost = 3; /* xscvdpspn, mfvsrd, and. */
19283 icode = reg_addr[mode].reload_gpr_vsx;
19286 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19288 cost = 2; /* mtvsrz, xscvspdpn. */
19289 icode = reg_addr[mode].reload_vsx_gpr;
19293 else if (!TARGET_POWERPC64 && size == 8)
19295 /* Handle moving 64-bit values from GPRs to floating point registers on
19296 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19297 32-bit values back together. Altivec register classes must be handled
19298 specially since a different instruction is used, and the secondary
19299 reload support requires a single instruction class in the scratch
19300 register constraint. However, right now TFmode is not allowed in
19301 Altivec registers, so the pattern will never match. */
19302 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19304 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19305 icode = reg_addr[mode].reload_fpr_gpr;
19309 if (icode != CODE_FOR_nothing)
19314 sri->icode = icode;
19315 sri->extra_cost = cost;
19322 /* Return whether a move between two register classes can be done either
19323 directly (simple move) or via a pattern that uses a single extra temporary
19324 (using ISA 2.07's direct move in this case. */
19327 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19328 enum rs6000_reg_type from_type,
19330 secondary_reload_info *sri,
19333 /* Fall back to load/store reloads if either type is not a register. */
19334 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19337 /* If we haven't allocated registers yet, assume the move can be done for the
19338 standard register types. */
19339 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19340 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19341 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19344 /* Moves to the same set of registers is a simple move for non-specialized
19346 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19349 /* Check whether a simple move can be done directly. */
19350 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19354 sri->icode = CODE_FOR_nothing;
19355 sri->extra_cost = 0;
19360 /* Now check if we can do it in a few steps. */
19361 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19365 /* Inform reload about cases where moving X with a mode MODE to a register in
19366 RCLASS requires an extra scratch or immediate register. Return the class
19367 needed for the immediate register.
19369 For VSX and Altivec, we may need a register to convert sp+offset into
19372 For misaligned 64-bit gpr loads and stores we need a register to
19373 convert an offset address to indirect. */
19376 rs6000_secondary_reload (bool in_p,
19378 reg_class_t rclass_i,
19380 secondary_reload_info *sri)
19382 enum reg_class rclass = (enum reg_class) rclass_i;
19383 reg_class_t ret = ALL_REGS;
19384 enum insn_code icode;
19385 bool default_p = false;
19386 bool done_p = false;
19388 /* Allow subreg of memory before/during reload. */
19389 bool memory_p = (MEM_P (x)
19390 || (!reload_completed && GET_CODE (x) == SUBREG
19391 && MEM_P (SUBREG_REG (x))));
19393 sri->icode = CODE_FOR_nothing;
19394 sri->t_icode = CODE_FOR_nothing;
19395 sri->extra_cost = 0;
19397 ? reg_addr[mode].reload_load
19398 : reg_addr[mode].reload_store);
19400 if (REG_P (x) || register_operand (x, mode))
19402 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19403 bool altivec_p = (rclass == ALTIVEC_REGS);
19404 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19407 std::swap (to_type, from_type);
19409 /* Can we do a direct move of some sort? */
19410 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19413 icode = (enum insn_code)sri->icode;
19420 /* Make sure 0.0 is not reloaded or forced into memory. */
19421 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19428 /* If this is a scalar floating point value and we want to load it into the
19429 traditional Altivec registers, do it via a move via a traditional floating
19430 point register, unless we have D-form addressing. Also make sure that
19431 non-zero constants use a FPR. */
19432 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19433 && !mode_supports_vmx_dform (mode)
19434 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19435 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
19442 /* Handle reload of load/stores if we have reload helper functions. */
19443 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19445 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19448 if (extra_cost >= 0)
19452 if (extra_cost > 0)
19454 sri->extra_cost = extra_cost;
19455 sri->icode = icode;
19460 /* Handle unaligned loads and stores of integer registers. */
19461 if (!done_p && TARGET_POWERPC64
19462 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19464 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19466 rtx addr = XEXP (x, 0);
19467 rtx off = address_offset (addr);
19469 if (off != NULL_RTX)
19471 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19472 unsigned HOST_WIDE_INT offset = INTVAL (off);
19474 /* We need a secondary reload when our legitimate_address_p
19475 says the address is good (as otherwise the entire address
19476 will be reloaded), and the offset is not a multiple of
19477 four or we have an address wrap. Address wrap will only
19478 occur for LO_SUMs since legitimate_offset_address_p
19479 rejects addresses for 16-byte mems that will wrap. */
19480 if (GET_CODE (addr) == LO_SUM
19481 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19482 && ((offset & 3) != 0
19483 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19484 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19485 && (offset & 3) != 0))
19487 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19489 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19490 : CODE_FOR_reload_di_load);
19492 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19493 : CODE_FOR_reload_di_store);
19494 sri->extra_cost = 2;
19505 if (!done_p && !TARGET_POWERPC64
19506 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19508 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19510 rtx addr = XEXP (x, 0);
19511 rtx off = address_offset (addr);
19513 if (off != NULL_RTX)
19515 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19516 unsigned HOST_WIDE_INT offset = INTVAL (off);
19518 /* We need a secondary reload when our legitimate_address_p
19519 says the address is good (as otherwise the entire address
19520 will be reloaded), and we have a wrap.
19522 legitimate_lo_sum_address_p allows LO_SUM addresses to
19523 have any offset so test for wrap in the low 16 bits.
19525 legitimate_offset_address_p checks for the range
19526 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19527 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19528 [0x7ff4,0x7fff] respectively, so test for the
19529 intersection of these ranges, [0x7ffc,0x7fff] and
19530 [0x7ff4,0x7ff7] respectively.
19532 Note that the address we see here may have been
19533 manipulated by legitimize_reload_address. */
19534 if (GET_CODE (addr) == LO_SUM
19535 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19536 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19539 sri->icode = CODE_FOR_reload_si_load;
19541 sri->icode = CODE_FOR_reload_si_store;
19542 sri->extra_cost = 2;
19557 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19559 gcc_assert (ret != ALL_REGS);
19561 if (TARGET_DEBUG_ADDR)
19564 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19566 reg_class_names[ret],
19567 in_p ? "true" : "false",
19568 reg_class_names[rclass],
19569 GET_MODE_NAME (mode));
19571 if (reload_completed)
19572 fputs (", after reload", stderr);
19575 fputs (", done_p not set", stderr);
19578 fputs (", default secondary reload", stderr);
19580 if (sri->icode != CODE_FOR_nothing)
19581 fprintf (stderr, ", reload func = %s, extra cost = %d",
19582 insn_data[sri->icode].name, sri->extra_cost);
19584 else if (sri->extra_cost > 0)
19585 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19587 fputs ("\n", stderr);
19594 /* Better tracing for rs6000_secondary_reload_inner. */
19597 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19602 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19604 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19605 store_p ? "store" : "load");
19608 set = gen_rtx_SET (mem, reg);
19610 set = gen_rtx_SET (reg, mem);
19612 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19613 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19616 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19617 ATTRIBUTE_NORETURN;
19620 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19623 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19624 gcc_unreachable ();
19627 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19628 reload helper functions. These were identified in
19629 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19630 reload, it calls the insns:
19631 reload_<RELOAD:mode>_<P:mptrsize>_store
19632 reload_<RELOAD:mode>_<P:mptrsize>_load
19634 which in turn calls this function, to do whatever is necessary to create
19635 valid addresses. */
19638 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19640 int regno = true_regnum (reg);
19641 machine_mode mode = GET_MODE (reg);
19642 addr_mask_type addr_mask;
19645 rtx op_reg, op0, op1;
19650 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
19651 || !base_reg_operand (scratch, GET_MODE (scratch)))
19652 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19654 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19655 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19657 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19658 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19660 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19661 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19664 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19666 /* Make sure the mode is valid in this register class. */
19667 if ((addr_mask & RELOAD_REG_VALID) == 0)
19668 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19670 if (TARGET_DEBUG_ADDR)
19671 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19673 new_addr = addr = XEXP (mem, 0);
19674 switch (GET_CODE (addr))
19676 /* Does the register class support auto update forms for this mode? If
19677 not, do the update now. We don't need a scratch register, since the
19678 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19681 op_reg = XEXP (addr, 0);
19682 if (!base_reg_operand (op_reg, Pmode))
19683 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19685 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19687 int delta = GET_MODE_SIZE (mode);
19688 if (GET_CODE (addr) == PRE_DEC)
19690 emit_insn (gen_add2_insn (op_reg, GEN_INT (delta)));
19696 op0 = XEXP (addr, 0);
19697 op1 = XEXP (addr, 1);
19698 if (!base_reg_operand (op0, Pmode)
19699 || GET_CODE (op1) != PLUS
19700 || !rtx_equal_p (op0, XEXP (op1, 0)))
19701 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19703 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19705 emit_insn (gen_rtx_SET (op0, op1));
19710 /* Do we need to simulate AND -16 to clear the bottom address bits used
19711 in VMX load/stores? */
19713 op0 = XEXP (addr, 0);
19714 op1 = XEXP (addr, 1);
19715 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19717 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
19720 else if (GET_CODE (op1) == PLUS)
19722 emit_insn (gen_rtx_SET (scratch, op1));
19727 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19729 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19730 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19731 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19732 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19733 new_addr = scratch;
19737 /* If this is an indirect address, make sure it is a base register. */
19740 if (!base_reg_operand (addr, GET_MODE (addr)))
19742 emit_insn (gen_rtx_SET (scratch, addr));
19743 new_addr = scratch;
19747 /* If this is an indexed address, make sure the register class can handle
19748 indexed addresses for this mode. */
19750 op0 = XEXP (addr, 0);
19751 op1 = XEXP (addr, 1);
19752 if (!base_reg_operand (op0, Pmode))
19753 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19755 else if (int_reg_operand (op1, Pmode))
19757 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19759 emit_insn (gen_rtx_SET (scratch, addr));
19760 new_addr = scratch;
19764 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19766 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19767 || !quad_address_p (addr, mode, false))
19769 emit_insn (gen_rtx_SET (scratch, addr));
19770 new_addr = scratch;
19774 /* Make sure the register class can handle offset addresses. */
19775 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19777 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19779 emit_insn (gen_rtx_SET (scratch, addr));
19780 new_addr = scratch;
19785 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19790 op0 = XEXP (addr, 0);
19791 op1 = XEXP (addr, 1);
19792 if (!base_reg_operand (op0, Pmode))
19793 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19795 else if (int_reg_operand (op1, Pmode))
19797 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19799 emit_insn (gen_rtx_SET (scratch, addr));
19800 new_addr = scratch;
19804 /* Quad offsets are restricted and can't handle normal addresses. */
19805 else if (mode_supports_dq_form (mode))
19807 emit_insn (gen_rtx_SET (scratch, addr));
19808 new_addr = scratch;
19811 /* Make sure the register class can handle offset addresses. */
19812 else if (legitimate_lo_sum_address_p (mode, addr, false))
19814 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19816 emit_insn (gen_rtx_SET (scratch, addr));
19817 new_addr = scratch;
19822 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19829 rs6000_emit_move (scratch, addr, Pmode);
19830 new_addr = scratch;
19834 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19837 /* Adjust the address if it changed. */
19838 if (addr != new_addr)
19840 mem = replace_equiv_address_nv (mem, new_addr);
19841 if (TARGET_DEBUG_ADDR)
19842 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19845 /* Now create the move. */
19847 emit_insn (gen_rtx_SET (mem, reg));
19849 emit_insn (gen_rtx_SET (reg, mem));
19854 /* Convert reloads involving 64-bit gprs and misaligned offset
19855 addressing, or multiple 32-bit gprs and offsets that are too large,
19856 to use indirect addressing. */
19859 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19861 int regno = true_regnum (reg);
19862 enum reg_class rclass;
19864 rtx scratch_or_premodify = scratch;
19866 if (TARGET_DEBUG_ADDR)
19868 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19869 store_p ? "store" : "load");
19870 fprintf (stderr, "reg:\n");
19872 fprintf (stderr, "mem:\n");
19874 fprintf (stderr, "scratch:\n");
19875 debug_rtx (scratch);
19878 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
19879 gcc_assert (GET_CODE (mem) == MEM);
19880 rclass = REGNO_REG_CLASS (regno);
19881 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19882 addr = XEXP (mem, 0);
19884 if (GET_CODE (addr) == PRE_MODIFY)
19886 gcc_assert (REG_P (XEXP (addr, 0))
19887 && GET_CODE (XEXP (addr, 1)) == PLUS
19888 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19889 scratch_or_premodify = XEXP (addr, 0);
19890 addr = XEXP (addr, 1);
19892 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19894 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19896 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19898 /* Now create the move. */
19900 emit_insn (gen_rtx_SET (mem, reg));
19902 emit_insn (gen_rtx_SET (reg, mem));
19907 /* Given an rtx X being reloaded into a reg required to be
19908 in class CLASS, return the class of reg to actually use.
19909 In general this is just CLASS; but on some machines
19910 in some cases it is preferable to use a more restrictive class.
19912 On the RS/6000, we have to return NO_REGS when we want to reload a
19913 floating-point CONST_DOUBLE to force it to be copied to memory.
19915 We also don't want to reload integer values into floating-point
19916 registers if we can at all help it. In fact, this can
19917 cause reload to die, if it tries to generate a reload of CTR
19918 into a FP register and discovers it doesn't have the memory location
19921 ??? Would it be a good idea to have reload do the converse, that is
19922 try to reload floating modes into FP registers if possible?
19925 static enum reg_class
19926 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19928 machine_mode mode = GET_MODE (x);
19929 bool is_constant = CONSTANT_P (x);
19931 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19932 reload class for it. */
19933 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19934 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19937 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19938 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19941 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19942 the reloading of address expressions using PLUS into floating point
19944 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19948 /* Zero is always allowed in all VSX registers. */
19949 if (x == CONST0_RTX (mode))
19952 /* If this is a vector constant that can be formed with a few Altivec
19953 instructions, we want altivec registers. */
19954 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19955 return ALTIVEC_REGS;
19957 /* If this is an integer constant that can easily be loaded into
19958 vector registers, allow it. */
19959 if (CONST_INT_P (x))
19961 HOST_WIDE_INT value = INTVAL (x);
19963 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19964 2.06 can generate it in the Altivec registers with
19968 if (TARGET_P8_VECTOR)
19970 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19971 return ALTIVEC_REGS;
19976 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19977 a sign extend in the Altivec registers. */
19978 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19979 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19980 return ALTIVEC_REGS;
19983 /* Force constant to memory. */
19987 /* D-form addressing can easily reload the value. */
19988 if (mode_supports_vmx_dform (mode)
19989 || mode_supports_dq_form (mode))
19992 /* If this is a scalar floating point value and we don't have D-form
19993 addressing, prefer the traditional floating point registers so that we
19994 can use D-form (register+offset) addressing. */
19995 if (rclass == VSX_REGS
19996 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19999 /* Prefer the Altivec registers if Altivec is handling the vector
20000 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20002 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
20003 || mode == V1TImode)
20004 return ALTIVEC_REGS;
20009 if (is_constant || GET_CODE (x) == PLUS)
20011 if (reg_class_subset_p (GENERAL_REGS, rclass))
20012 return GENERAL_REGS;
20013 if (reg_class_subset_p (BASE_REGS, rclass))
20018 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
20019 return GENERAL_REGS;
20024 /* Debug version of rs6000_preferred_reload_class. */
20025 static enum reg_class
20026 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
20028 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
20031 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20033 reg_class_names[ret], reg_class_names[rclass],
20034 GET_MODE_NAME (GET_MODE (x)));
20040 /* If we are copying between FP or AltiVec registers and anything else, we need
20041 a memory location. The exception is when we are targeting ppc64 and the
20042 move to/from fpr to gpr instructions are available. Also, under VSX, you
20043 can copy vector registers from the FP register set to the Altivec register
20044 set and vice versa. */
20047 rs6000_secondary_memory_needed (machine_mode mode,
20048 reg_class_t from_class,
20049 reg_class_t to_class)
20051 enum rs6000_reg_type from_type, to_type;
20052 bool altivec_p = ((from_class == ALTIVEC_REGS)
20053 || (to_class == ALTIVEC_REGS));
20055 /* If a simple/direct move is available, we don't need secondary memory */
20056 from_type = reg_class_to_reg_type[(int)from_class];
20057 to_type = reg_class_to_reg_type[(int)to_class];
20059 if (rs6000_secondary_reload_move (to_type, from_type, mode,
20060 (secondary_reload_info *)0, altivec_p))
20063 /* If we have a floating point or vector register class, we need to use
20064 memory to transfer the data. */
20065 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
20071 /* Debug version of rs6000_secondary_memory_needed. */
20073 rs6000_debug_secondary_memory_needed (machine_mode mode,
20074 reg_class_t from_class,
20075 reg_class_t to_class)
20077 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
20080 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20081 "to_class = %s, mode = %s\n",
20082 ret ? "true" : "false",
20083 reg_class_names[from_class],
20084 reg_class_names[to_class],
20085 GET_MODE_NAME (mode));
20090 /* Return the register class of a scratch register needed to copy IN into
20091 or out of a register in RCLASS in MODE. If it can be done directly,
20092 NO_REGS is returned. */
20094 static enum reg_class
20095 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
20100 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
20102 && MACHOPIC_INDIRECT
20106 /* We cannot copy a symbolic operand directly into anything
20107 other than BASE_REGS for TARGET_ELF. So indicate that a
20108 register from BASE_REGS is needed as an intermediate
20111 On Darwin, pic addresses require a load from memory, which
20112 needs a base register. */
20113 if (rclass != BASE_REGS
20114 && (GET_CODE (in) == SYMBOL_REF
20115 || GET_CODE (in) == HIGH
20116 || GET_CODE (in) == LABEL_REF
20117 || GET_CODE (in) == CONST))
20121 if (GET_CODE (in) == REG)
20123 regno = REGNO (in);
20124 if (regno >= FIRST_PSEUDO_REGISTER)
20126 regno = true_regnum (in);
20127 if (regno >= FIRST_PSEUDO_REGISTER)
20131 else if (GET_CODE (in) == SUBREG)
20133 regno = true_regnum (in);
20134 if (regno >= FIRST_PSEUDO_REGISTER)
20140 /* If we have VSX register moves, prefer moving scalar values between
20141 Altivec registers and GPR by going via an FPR (and then via memory)
20142 instead of reloading the secondary memory address for Altivec moves. */
20144 && GET_MODE_SIZE (mode) < 16
20145 && !mode_supports_vmx_dform (mode)
20146 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20147 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20148 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20149 && (regno >= 0 && INT_REGNO_P (regno)))))
20152 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20154 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20155 || (regno >= 0 && INT_REGNO_P (regno)))
20158 /* Constants, memory, and VSX registers can go into VSX registers (both the
20159 traditional floating point and the altivec registers). */
20160 if (rclass == VSX_REGS
20161 && (regno == -1 || VSX_REGNO_P (regno)))
20164 /* Constants, memory, and FP registers can go into FP registers. */
20165 if ((regno == -1 || FP_REGNO_P (regno))
20166 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20167 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20169 /* Memory, and AltiVec registers can go into AltiVec registers. */
20170 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20171 && rclass == ALTIVEC_REGS)
20174 /* We can copy among the CR registers. */
20175 if ((rclass == CR_REGS || rclass == CR0_REGS)
20176 && regno >= 0 && CR_REGNO_P (regno))
20179 /* Otherwise, we need GENERAL_REGS. */
20180 return GENERAL_REGS;
20183 /* Debug version of rs6000_secondary_reload_class. */
20184 static enum reg_class
20185 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20186 machine_mode mode, rtx in)
20188 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20190 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20191 "mode = %s, input rtx:\n",
20192 reg_class_names[ret], reg_class_names[rclass],
20193 GET_MODE_NAME (mode));
20199 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20202 rs6000_can_change_mode_class (machine_mode from,
20204 reg_class_t rclass)
20206 unsigned from_size = GET_MODE_SIZE (from);
20207 unsigned to_size = GET_MODE_SIZE (to);
20209 if (from_size != to_size)
20211 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20213 if (reg_classes_intersect_p (xclass, rclass))
20215 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20216 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20217 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20218 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20220 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20221 single register under VSX because the scalar part of the register
20222 is in the upper 64-bits, and not the lower 64-bits. Types like
20223 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20224 IEEE floating point can't overlap, and neither can small
20227 if (to_float128_vector_p && from_float128_vector_p)
20230 else if (to_float128_vector_p || from_float128_vector_p)
20233 /* TDmode in floating-mode registers must always go into a register
20234 pair with the most significant word in the even-numbered register
20235 to match ISA requirements. In little-endian mode, this does not
20236 match subreg numbering, so we cannot allow subregs. */
20237 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20240 if (from_size < 8 || to_size < 8)
20243 if (from_size == 8 && (8 * to_nregs) != to_size)
20246 if (to_size == 8 && (8 * from_nregs) != from_size)
20255 /* Since the VSX register set includes traditional floating point registers
20256 and altivec registers, just check for the size being different instead of
20257 trying to check whether the modes are vector modes. Otherwise it won't
20258 allow say DF and DI to change classes. For types like TFmode and TDmode
20259 that take 2 64-bit registers, rather than a single 128-bit register, don't
20260 allow subregs of those types to other 128 bit types. */
20261 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20263 unsigned num_regs = (from_size + 15) / 16;
20264 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20265 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20268 return (from_size == 8 || from_size == 16);
20271 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20272 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20278 /* Debug version of rs6000_can_change_mode_class. */
20280 rs6000_debug_can_change_mode_class (machine_mode from,
20282 reg_class_t rclass)
20284 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20287 "rs6000_can_change_mode_class, return %s, from = %s, "
20288 "to = %s, rclass = %s\n",
20289 ret ? "true" : "false",
20290 GET_MODE_NAME (from), GET_MODE_NAME (to),
20291 reg_class_names[rclass]);
20296 /* Return a string to do a move operation of 128 bits of data. */
20299 rs6000_output_move_128bit (rtx operands[])
20301 rtx dest = operands[0];
20302 rtx src = operands[1];
20303 machine_mode mode = GET_MODE (dest);
20306 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20307 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20311 dest_regno = REGNO (dest);
20312 dest_gpr_p = INT_REGNO_P (dest_regno);
20313 dest_fp_p = FP_REGNO_P (dest_regno);
20314 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20315 dest_vsx_p = dest_fp_p | dest_vmx_p;
20320 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20325 src_regno = REGNO (src);
20326 src_gpr_p = INT_REGNO_P (src_regno);
20327 src_fp_p = FP_REGNO_P (src_regno);
20328 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20329 src_vsx_p = src_fp_p | src_vmx_p;
20334 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20337 /* Register moves. */
20338 if (dest_regno >= 0 && src_regno >= 0)
20345 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20346 return (WORDS_BIG_ENDIAN
20347 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20348 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20350 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20354 else if (TARGET_VSX && dest_vsx_p)
20357 return "xxlor %x0,%x1,%x1";
20359 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20360 return (WORDS_BIG_ENDIAN
20361 ? "mtvsrdd %x0,%1,%L1"
20362 : "mtvsrdd %x0,%L1,%1");
20364 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20368 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20369 return "vor %0,%1,%1";
20371 else if (dest_fp_p && src_fp_p)
20376 else if (dest_regno >= 0 && MEM_P (src))
20380 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20386 else if (TARGET_ALTIVEC && dest_vmx_p
20387 && altivec_indexed_or_indirect_operand (src, mode))
20388 return "lvx %0,%y1";
20390 else if (TARGET_VSX && dest_vsx_p)
20392 if (mode_supports_dq_form (mode)
20393 && quad_address_p (XEXP (src, 0), mode, true))
20394 return "lxv %x0,%1";
20396 else if (TARGET_P9_VECTOR)
20397 return "lxvx %x0,%y1";
20399 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20400 return "lxvw4x %x0,%y1";
20403 return "lxvd2x %x0,%y1";
20406 else if (TARGET_ALTIVEC && dest_vmx_p)
20407 return "lvx %0,%y1";
20409 else if (dest_fp_p)
20414 else if (src_regno >= 0 && MEM_P (dest))
20418 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20419 return "stq %1,%0";
20424 else if (TARGET_ALTIVEC && src_vmx_p
20425 && altivec_indexed_or_indirect_operand (dest, mode))
20426 return "stvx %1,%y0";
20428 else if (TARGET_VSX && src_vsx_p)
20430 if (mode_supports_dq_form (mode)
20431 && quad_address_p (XEXP (dest, 0), mode, true))
20432 return "stxv %x1,%0";
20434 else if (TARGET_P9_VECTOR)
20435 return "stxvx %x1,%y0";
20437 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20438 return "stxvw4x %x1,%y0";
20441 return "stxvd2x %x1,%y0";
20444 else if (TARGET_ALTIVEC && src_vmx_p)
20445 return "stvx %1,%y0";
20452 else if (dest_regno >= 0
20453 && (GET_CODE (src) == CONST_INT
20454 || GET_CODE (src) == CONST_WIDE_INT
20455 || GET_CODE (src) == CONST_DOUBLE
20456 || GET_CODE (src) == CONST_VECTOR))
20461 else if ((dest_vmx_p && TARGET_ALTIVEC)
20462 || (dest_vsx_p && TARGET_VSX))
20463 return output_vec_const_move (operands);
20466 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20469 /* Validate a 128-bit move. */
20471 rs6000_move_128bit_ok_p (rtx operands[])
20473 machine_mode mode = GET_MODE (operands[0]);
20474 return (gpc_reg_operand (operands[0], mode)
20475 || gpc_reg_operand (operands[1], mode));
20478 /* Return true if a 128-bit move needs to be split. */
20480 rs6000_split_128bit_ok_p (rtx operands[])
20482 if (!reload_completed)
20485 if (!gpr_or_gpr_p (operands[0], operands[1]))
20488 if (quad_load_store_p (operands[0], operands[1]))
20495 /* Given a comparison operation, return the bit number in CCR to test. We
20496 know this is a valid comparison.
20498 SCC_P is 1 if this is for an scc. That means that %D will have been
20499 used instead of %C, so the bits will be in different places.
20501 Return -1 if OP isn't a valid comparison for some reason. */
20504 ccr_bit (rtx op, int scc_p)
20506 enum rtx_code code = GET_CODE (op);
20507 machine_mode cc_mode;
20512 if (!COMPARISON_P (op))
20515 reg = XEXP (op, 0);
20517 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
20519 cc_mode = GET_MODE (reg);
20520 cc_regnum = REGNO (reg);
20521 base_bit = 4 * (cc_regnum - CR0_REGNO);
20523 validate_condition_mode (code, cc_mode);
20525 /* When generating a sCOND operation, only positive conditions are
20528 || code == EQ || code == GT || code == LT || code == UNORDERED
20529 || code == GTU || code == LTU);
20534 return scc_p ? base_bit + 3 : base_bit + 2;
20536 return base_bit + 2;
20537 case GT: case GTU: case UNLE:
20538 return base_bit + 1;
20539 case LT: case LTU: case UNGE:
20541 case ORDERED: case UNORDERED:
20542 return base_bit + 3;
20545 /* If scc, we will have done a cror to put the bit in the
20546 unordered position. So test that bit. For integer, this is ! LT
20547 unless this is an scc insn. */
20548 return scc_p ? base_bit + 3 : base_bit;
20551 return scc_p ? base_bit + 3 : base_bit + 1;
20554 gcc_unreachable ();
20558 /* Return the GOT register. */
20561 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20563 /* The second flow pass currently (June 1999) can't update
20564 regs_ever_live without disturbing other parts of the compiler, so
20565 update it here to make the prolog/epilogue code happy. */
20566 if (!can_create_pseudo_p ()
20567 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20568 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20570 crtl->uses_pic_offset_table = 1;
20572 return pic_offset_table_rtx;
20575 static rs6000_stack_t stack_info;
20577 /* Function to init struct machine_function.
20578 This will be called, via a pointer variable,
20579 from push_function_context. */
20581 static struct machine_function *
20582 rs6000_init_machine_status (void)
20584 stack_info.reload_completed = 0;
20585 return ggc_cleared_alloc<machine_function> ();
20588 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
20590 /* Write out a function code label. */
20593 rs6000_output_function_entry (FILE *file, const char *fname)
20595 if (fname[0] != '.')
20597 switch (DEFAULT_ABI)
20600 gcc_unreachable ();
20606 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20616 RS6000_OUTPUT_BASENAME (file, fname);
20619 /* Print an operand. Recognize special options, documented below. */
20622 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20623 only introduced by the linker, when applying the sda21
20625 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20626 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20628 #define SMALL_DATA_RELOC "sda21"
20629 #define SMALL_DATA_REG 0
20633 print_operand (FILE *file, rtx x, int code)
20636 unsigned HOST_WIDE_INT uval;
20640 /* %a is output_address. */
20642 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20646 /* Like 'J' but get to the GT bit only. */
20649 output_operand_lossage ("invalid %%D value");
20653 /* Bit 1 is GT bit. */
20654 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20656 /* Add one for shift count in rlinm for scc. */
20657 fprintf (file, "%d", i + 1);
20661 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20664 output_operand_lossage ("invalid %%e value");
20669 if ((uval & 0xffff) == 0 && uval != 0)
20674 /* X is a CR register. Print the number of the EQ bit of the CR */
20675 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20676 output_operand_lossage ("invalid %%E value");
20678 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20682 /* X is a CR register. Print the shift count needed to move it
20683 to the high-order four bits. */
20684 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20685 output_operand_lossage ("invalid %%f value");
20687 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20691 /* Similar, but print the count for the rotate in the opposite
20693 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20694 output_operand_lossage ("invalid %%F value");
20696 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20700 /* X is a constant integer. If it is negative, print "m",
20701 otherwise print "z". This is to make an aze or ame insn. */
20702 if (GET_CODE (x) != CONST_INT)
20703 output_operand_lossage ("invalid %%G value");
20704 else if (INTVAL (x) >= 0)
20711 /* If constant, output low-order five bits. Otherwise, write
20714 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20716 print_operand (file, x, 0);
20720 /* If constant, output low-order six bits. Otherwise, write
20723 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20725 print_operand (file, x, 0);
20729 /* Print `i' if this is a constant, else nothing. */
20735 /* Write the bit number in CCR for jump. */
20736 i = ccr_bit (x, 0);
20738 output_operand_lossage ("invalid %%j code");
20740 fprintf (file, "%d", i);
20744 /* Similar, but add one for shift count in rlinm for scc and pass
20745 scc flag to `ccr_bit'. */
20746 i = ccr_bit (x, 1);
20748 output_operand_lossage ("invalid %%J code");
20750 /* If we want bit 31, write a shift count of zero, not 32. */
20751 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20755 /* X must be a constant. Write the 1's complement of the
20758 output_operand_lossage ("invalid %%k value");
20760 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20764 /* X must be a symbolic constant on ELF. Write an
20765 expression suitable for an 'addi' that adds in the low 16
20766 bits of the MEM. */
20767 if (GET_CODE (x) == CONST)
20769 if (GET_CODE (XEXP (x, 0)) != PLUS
20770 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
20771 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20772 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
20773 output_operand_lossage ("invalid %%K value");
20775 print_operand_address (file, x);
20776 fputs ("@l", file);
20779 /* %l is output_asm_label. */
20782 /* Write second word of DImode or DFmode reference. Works on register
20783 or non-indexed memory only. */
20785 fputs (reg_names[REGNO (x) + 1], file);
20786 else if (MEM_P (x))
20788 machine_mode mode = GET_MODE (x);
20789 /* Handle possible auto-increment. Since it is pre-increment and
20790 we have already done it, we can just use an offset of word. */
20791 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20792 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20793 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20795 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20796 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20799 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20803 if (small_data_operand (x, GET_MODE (x)))
20804 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20805 reg_names[SMALL_DATA_REG]);
20809 case 'N': /* Unused */
20810 /* Write the number of elements in the vector times 4. */
20811 if (GET_CODE (x) != PARALLEL)
20812 output_operand_lossage ("invalid %%N value");
20814 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20817 case 'O': /* Unused */
20818 /* Similar, but subtract 1 first. */
20819 if (GET_CODE (x) != PARALLEL)
20820 output_operand_lossage ("invalid %%O value");
20822 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20826 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20829 || (i = exact_log2 (INTVAL (x))) < 0)
20830 output_operand_lossage ("invalid %%p value");
20832 fprintf (file, "%d", i);
20836 /* The operand must be an indirect memory reference. The result
20837 is the register name. */
20838 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
20839 || REGNO (XEXP (x, 0)) >= 32)
20840 output_operand_lossage ("invalid %%P value");
20842 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20846 /* This outputs the logical code corresponding to a boolean
20847 expression. The expression may have one or both operands
20848 negated (if one, only the first one). For condition register
20849 logical operations, it will also treat the negated
20850 CR codes as NOTs, but not handle NOTs of them. */
20852 const char *const *t = 0;
20854 enum rtx_code code = GET_CODE (x);
20855 static const char * const tbl[3][3] = {
20856 { "and", "andc", "nor" },
20857 { "or", "orc", "nand" },
20858 { "xor", "eqv", "xor" } };
20862 else if (code == IOR)
20864 else if (code == XOR)
20867 output_operand_lossage ("invalid %%q value");
20869 if (GET_CODE (XEXP (x, 0)) != NOT)
20873 if (GET_CODE (XEXP (x, 1)) == NOT)
20884 if (! TARGET_MFCRF)
20890 /* X is a CR register. Print the mask for `mtcrf'. */
20891 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
20892 output_operand_lossage ("invalid %%R value");
20894 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20898 /* Low 5 bits of 32 - value */
20900 output_operand_lossage ("invalid %%s value");
20902 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20906 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20907 if (!REG_P (x) || GET_MODE (x) != CCmode)
20909 output_operand_lossage ("invalid %%t value");
20913 /* Bit 3 is OV bit. */
20914 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20916 /* If we want bit 31, write a shift count of zero, not 32. */
20917 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20921 /* Print the symbolic name of a branch target register. */
20922 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
20923 && REGNO (x) != CTR_REGNO))
20924 output_operand_lossage ("invalid %%T value");
20925 else if (REGNO (x) == LR_REGNO)
20926 fputs ("lr", file);
20928 fputs ("ctr", file);
20932 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20933 for use in unsigned operand. */
20936 output_operand_lossage ("invalid %%u value");
20941 if ((uval & 0xffff) == 0)
20944 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20948 /* High-order 16 bits of constant for use in signed operand. */
20950 output_operand_lossage ("invalid %%v value");
20952 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20953 (INTVAL (x) >> 16) & 0xffff);
20957 /* Print `u' if this has an auto-increment or auto-decrement. */
20959 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20960 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20961 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20966 /* Print the trap code for this operand. */
20967 switch (GET_CODE (x))
20970 fputs ("eq", file); /* 4 */
20973 fputs ("ne", file); /* 24 */
20976 fputs ("lt", file); /* 16 */
20979 fputs ("le", file); /* 20 */
20982 fputs ("gt", file); /* 8 */
20985 fputs ("ge", file); /* 12 */
20988 fputs ("llt", file); /* 2 */
20991 fputs ("lle", file); /* 6 */
20994 fputs ("lgt", file); /* 1 */
20997 fputs ("lge", file); /* 5 */
21000 output_operand_lossage ("invalid %%V value");
21005 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21008 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
21009 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
21011 print_operand (file, x, 0);
21015 /* X is a FPR or Altivec register used in a VSX context. */
21016 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
21017 output_operand_lossage ("invalid %%x value");
21020 int reg = REGNO (x);
21021 int vsx_reg = (FP_REGNO_P (reg)
21023 : reg - FIRST_ALTIVEC_REGNO + 32);
21025 #ifdef TARGET_REGNAMES
21026 if (TARGET_REGNAMES)
21027 fprintf (file, "%%vs%d", vsx_reg);
21030 fprintf (file, "%d", vsx_reg);
21036 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
21037 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
21038 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
21043 /* Like 'L', for third word of TImode/PTImode */
21045 fputs (reg_names[REGNO (x) + 2], file);
21046 else if (MEM_P (x))
21048 machine_mode mode = GET_MODE (x);
21049 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21050 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21051 output_address (mode, plus_constant (Pmode,
21052 XEXP (XEXP (x, 0), 0), 8));
21053 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21054 output_address (mode, plus_constant (Pmode,
21055 XEXP (XEXP (x, 0), 0), 8));
21057 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
21058 if (small_data_operand (x, GET_MODE (x)))
21059 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21060 reg_names[SMALL_DATA_REG]);
21065 /* X is a SYMBOL_REF. Write out the name preceded by a
21066 period and without any trailing data in brackets. Used for function
21067 names. If we are configured for System V (or the embedded ABI) on
21068 the PowerPC, do not emit the period, since those systems do not use
21069 TOCs and the like. */
21070 if (!SYMBOL_REF_P (x))
21072 output_operand_lossage ("invalid %%z value");
21076 /* For macho, check to see if we need a stub. */
21079 const char *name = XSTR (x, 0);
21081 if (darwin_emit_branch_islands
21082 && MACHOPIC_INDIRECT
21083 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
21084 name = machopic_indirection_name (x, /*stub_p=*/true);
21086 assemble_name (file, name);
21088 else if (!DOT_SYMBOLS)
21089 assemble_name (file, XSTR (x, 0));
21091 rs6000_output_function_entry (file, XSTR (x, 0));
21095 /* Like 'L', for last word of TImode/PTImode. */
21097 fputs (reg_names[REGNO (x) + 3], file);
21098 else if (MEM_P (x))
21100 machine_mode mode = GET_MODE (x);
21101 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21102 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21103 output_address (mode, plus_constant (Pmode,
21104 XEXP (XEXP (x, 0), 0), 12));
21105 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21106 output_address (mode, plus_constant (Pmode,
21107 XEXP (XEXP (x, 0), 0), 12));
21109 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
21110 if (small_data_operand (x, GET_MODE (x)))
21111 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21112 reg_names[SMALL_DATA_REG]);
21116 /* Print AltiVec memory operand. */
21121 gcc_assert (MEM_P (x));
21125 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
21126 && GET_CODE (tmp) == AND
21127 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
21128 && INTVAL (XEXP (tmp, 1)) == -16)
21129 tmp = XEXP (tmp, 0);
21130 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
21131 && GET_CODE (tmp) == PRE_MODIFY)
21132 tmp = XEXP (tmp, 1);
21134 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21137 if (GET_CODE (tmp) != PLUS
21138 || !REG_P (XEXP (tmp, 0))
21139 || !REG_P (XEXP (tmp, 1)))
21141 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21145 if (REGNO (XEXP (tmp, 0)) == 0)
21146 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21147 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21149 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21150 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21157 fprintf (file, "%s", reg_names[REGNO (x)]);
21158 else if (MEM_P (x))
21160 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21161 know the width from the mode. */
21162 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21163 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21164 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21165 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21166 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21167 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21168 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21169 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21171 output_address (GET_MODE (x), XEXP (x, 0));
21175 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21176 /* This hack along with a corresponding hack in
21177 rs6000_output_addr_const_extra arranges to output addends
21178 where the assembler expects to find them. eg.
21179 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21180 without this hack would be output as "x@toc+4". We
21182 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21184 output_addr_const (file, x);
21189 if (const char *name = get_some_local_dynamic_name ())
21190 assemble_name (file, name);
21192 output_operand_lossage ("'%%&' used without any "
21193 "local dynamic TLS references");
21197 output_operand_lossage ("invalid %%xn code");
21201 /* Print the address of an operand. */
21204 print_operand_address (FILE *file, rtx x)
21207 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21208 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21209 || GET_CODE (x) == LABEL_REF)
21211 output_addr_const (file, x);
21212 if (small_data_operand (x, GET_MODE (x)))
21213 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21214 reg_names[SMALL_DATA_REG]);
21216 gcc_assert (!TARGET_TOC);
21218 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21219 && REG_P (XEXP (x, 1)))
21221 if (REGNO (XEXP (x, 0)) == 0)
21222 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21223 reg_names[ REGNO (XEXP (x, 0)) ]);
21225 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21226 reg_names[ REGNO (XEXP (x, 1)) ]);
21228 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21229 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21230 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21231 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21233 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21234 && CONSTANT_P (XEXP (x, 1)))
21236 fprintf (file, "lo16(");
21237 output_addr_const (file, XEXP (x, 1));
21238 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21242 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21243 && CONSTANT_P (XEXP (x, 1)))
21245 output_addr_const (file, XEXP (x, 1));
21246 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21249 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21251 /* This hack along with a corresponding hack in
21252 rs6000_output_addr_const_extra arranges to output addends
21253 where the assembler expects to find them. eg.
21255 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21256 without this hack would be output as "x@toc+8@l(9)". We
21257 want "x+8@toc@l(9)". */
21258 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21259 if (GET_CODE (x) == LO_SUM)
21260 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21262 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21265 output_addr_const (file, x);
21268 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21271 rs6000_output_addr_const_extra (FILE *file, rtx x)
21273 if (GET_CODE (x) == UNSPEC)
21274 switch (XINT (x, 1))
21276 case UNSPEC_TOCREL:
21277 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21278 && REG_P (XVECEXP (x, 0, 1))
21279 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21280 output_addr_const (file, XVECEXP (x, 0, 0));
21281 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21283 if (INTVAL (tocrel_offset_oac) >= 0)
21284 fprintf (file, "+");
21285 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21287 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21290 assemble_name (file, toc_label_name);
21293 else if (TARGET_ELF)
21294 fputs ("@toc", file);
21298 case UNSPEC_MACHOPIC_OFFSET:
21299 output_addr_const (file, XVECEXP (x, 0, 0));
21301 machopic_output_function_base_name (file);
21308 /* Target hook for assembling integer objects. The PowerPC version has
21309 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21310 is defined. It also needs to handle DI-mode objects on 64-bit
21314 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21316 #ifdef RELOCATABLE_NEEDS_FIXUP
21317 /* Special handling for SI values. */
21318 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21320 static int recurse = 0;
21322 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21323 the .fixup section. Since the TOC section is already relocated, we
21324 don't need to mark it here. We used to skip the text section, but it
21325 should never be valid for relocated addresses to be placed in the text
21327 if (DEFAULT_ABI == ABI_V4
21328 && (TARGET_RELOCATABLE || flag_pic > 1)
21329 && in_section != toc_section
21331 && !CONST_SCALAR_INT_P (x)
21337 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21339 ASM_OUTPUT_LABEL (asm_out_file, buf);
21340 fprintf (asm_out_file, "\t.long\t(");
21341 output_addr_const (asm_out_file, x);
21342 fprintf (asm_out_file, ")@fixup\n");
21343 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21344 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21345 fprintf (asm_out_file, "\t.long\t");
21346 assemble_name (asm_out_file, buf);
21347 fprintf (asm_out_file, "\n\t.previous\n");
21351 /* Remove initial .'s to turn a -mcall-aixdesc function
21352 address into the address of the descriptor, not the function
21354 else if (GET_CODE (x) == SYMBOL_REF
21355 && XSTR (x, 0)[0] == '.'
21356 && DEFAULT_ABI == ABI_AIX)
21358 const char *name = XSTR (x, 0);
21359 while (*name == '.')
21362 fprintf (asm_out_file, "\t.long\t%s\n", name);
21366 #endif /* RELOCATABLE_NEEDS_FIXUP */
21367 return default_assemble_integer (x, size, aligned_p);
21370 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21371 /* Emit an assembler directive to set symbol visibility for DECL to
21372 VISIBILITY_TYPE. */
21375 rs6000_assemble_visibility (tree decl, int vis)
21380 /* Functions need to have their entry point symbol visibility set as
21381 well as their descriptor symbol visibility. */
21382 if (DEFAULT_ABI == ABI_AIX
21384 && TREE_CODE (decl) == FUNCTION_DECL)
21386 static const char * const visibility_types[] = {
21387 NULL, "protected", "hidden", "internal"
21390 const char *name, *type;
21392 name = ((* targetm.strip_name_encoding)
21393 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21394 type = visibility_types[vis];
21396 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21397 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21400 default_assemble_visibility (decl, vis);
21405 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21407 /* Reversal of FP compares takes care -- an ordered compare
21408 becomes an unordered compare and vice versa. */
21409 if (mode == CCFPmode
21410 && (!flag_finite_math_only
21411 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21412 || code == UNEQ || code == LTGT))
21413 return reverse_condition_maybe_unordered (code);
21415 return reverse_condition (code);
21418 /* Generate a compare for CODE. Return a brand-new rtx that
21419 represents the result of the compare. */
21422 rs6000_generate_compare (rtx cmp, machine_mode mode)
21424 machine_mode comp_mode;
21425 rtx compare_result;
21426 enum rtx_code code = GET_CODE (cmp);
21427 rtx op0 = XEXP (cmp, 0);
21428 rtx op1 = XEXP (cmp, 1);
21430 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21431 comp_mode = CCmode;
21432 else if (FLOAT_MODE_P (mode))
21433 comp_mode = CCFPmode;
21434 else if (code == GTU || code == LTU
21435 || code == GEU || code == LEU)
21436 comp_mode = CCUNSmode;
21437 else if ((code == EQ || code == NE)
21438 && unsigned_reg_p (op0)
21439 && (unsigned_reg_p (op1)
21440 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21441 /* These are unsigned values, perhaps there will be a later
21442 ordering compare that can be shared with this one. */
21443 comp_mode = CCUNSmode;
21445 comp_mode = CCmode;
21447 /* If we have an unsigned compare, make sure we don't have a signed value as
21449 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
21450 && INTVAL (op1) < 0)
21452 op0 = copy_rtx_if_shared (op0);
21453 op1 = force_reg (GET_MODE (op0), op1);
21454 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21457 /* First, the compare. */
21458 compare_result = gen_reg_rtx (comp_mode);
21460 /* IEEE 128-bit support in VSX registers when we do not have hardware
21462 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21464 rtx libfunc = NULL_RTX;
21465 bool check_nan = false;
21472 libfunc = optab_libfunc (eq_optab, mode);
21477 libfunc = optab_libfunc (ge_optab, mode);
21482 libfunc = optab_libfunc (le_optab, mode);
21487 libfunc = optab_libfunc (unord_optab, mode);
21488 code = (code == UNORDERED) ? NE : EQ;
21494 libfunc = optab_libfunc (ge_optab, mode);
21495 code = (code == UNGE) ? GE : GT;
21501 libfunc = optab_libfunc (le_optab, mode);
21502 code = (code == UNLE) ? LE : LT;
21508 libfunc = optab_libfunc (eq_optab, mode);
21509 code = (code = UNEQ) ? EQ : NE;
21513 gcc_unreachable ();
21516 gcc_assert (libfunc);
21519 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21520 SImode, op0, mode, op1, mode);
21522 /* The library signals an exception for signalling NaNs, so we need to
21523 handle isgreater, etc. by first checking isordered. */
21526 rtx ne_rtx, normal_dest, unord_dest;
21527 rtx unord_func = optab_libfunc (unord_optab, mode);
21528 rtx join_label = gen_label_rtx ();
21529 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21530 rtx unord_cmp = gen_reg_rtx (comp_mode);
21533 /* Test for either value being a NaN. */
21534 gcc_assert (unord_func);
21535 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21536 SImode, op0, mode, op1, mode);
21538 /* Set value (0) if either value is a NaN, and jump to the join
21540 dest = gen_reg_rtx (SImode);
21541 emit_move_insn (dest, const1_rtx);
21542 emit_insn (gen_rtx_SET (unord_cmp,
21543 gen_rtx_COMPARE (comp_mode, unord_dest,
21546 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21547 emit_jump_insn (gen_rtx_SET (pc_rtx,
21548 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21552 /* Do the normal comparison, knowing that the values are not
21554 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21555 SImode, op0, mode, op1, mode);
21557 emit_insn (gen_cstoresi4 (dest,
21558 gen_rtx_fmt_ee (code, SImode, normal_dest,
21560 normal_dest, const0_rtx));
21562 /* Join NaN and non-Nan paths. Compare dest against 0. */
21563 emit_label (join_label);
21567 emit_insn (gen_rtx_SET (compare_result,
21568 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21573 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21574 CLOBBERs to match cmptf_internal2 pattern. */
21575 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21576 && FLOAT128_IBM_P (GET_MODE (op0))
21577 && TARGET_HARD_FLOAT)
21578 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21580 gen_rtx_SET (compare_result,
21581 gen_rtx_COMPARE (comp_mode, op0, op1)),
21582 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21583 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21584 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21585 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21586 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21587 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21588 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21589 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21590 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21591 else if (GET_CODE (op1) == UNSPEC
21592 && XINT (op1, 1) == UNSPEC_SP_TEST)
21594 rtx op1b = XVECEXP (op1, 0, 0);
21595 comp_mode = CCEQmode;
21596 compare_result = gen_reg_rtx (CCEQmode);
21598 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21600 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21603 emit_insn (gen_rtx_SET (compare_result,
21604 gen_rtx_COMPARE (comp_mode, op0, op1)));
21607 /* Some kinds of FP comparisons need an OR operation;
21608 under flag_finite_math_only we don't bother. */
21609 if (FLOAT_MODE_P (mode)
21610 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21611 && !flag_finite_math_only
21612 && (code == LE || code == GE
21613 || code == UNEQ || code == LTGT
21614 || code == UNGT || code == UNLT))
21616 enum rtx_code or1, or2;
21617 rtx or1_rtx, or2_rtx, compare2_rtx;
21618 rtx or_result = gen_reg_rtx (CCEQmode);
21622 case LE: or1 = LT; or2 = EQ; break;
21623 case GE: or1 = GT; or2 = EQ; break;
21624 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21625 case LTGT: or1 = LT; or2 = GT; break;
21626 case UNGT: or1 = UNORDERED; or2 = GT; break;
21627 case UNLT: or1 = UNORDERED; or2 = LT; break;
21628 default: gcc_unreachable ();
21630 validate_condition_mode (or1, comp_mode);
21631 validate_condition_mode (or2, comp_mode);
21632 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21633 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21634 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21635 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21637 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21639 compare_result = or_result;
21643 validate_condition_mode (code, GET_MODE (compare_result));
21645 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21649 /* Return the diagnostic message string if the binary operation OP is
21650 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21653 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21657 machine_mode mode1 = TYPE_MODE (type1);
21658 machine_mode mode2 = TYPE_MODE (type2);
21660 /* For complex modes, use the inner type. */
21661 if (COMPLEX_MODE_P (mode1))
21662 mode1 = GET_MODE_INNER (mode1);
21664 if (COMPLEX_MODE_P (mode2))
21665 mode2 = GET_MODE_INNER (mode2);
21667 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21668 double to intermix unless -mfloat128-convert. */
21669 if (mode1 == mode2)
21672 if (!TARGET_FLOAT128_CVT)
21674 if ((mode1 == KFmode && mode2 == IFmode)
21675 || (mode1 == IFmode && mode2 == KFmode))
21676 return N_("__float128 and __ibm128 cannot be used in the same "
21679 if (TARGET_IEEEQUAD
21680 && ((mode1 == IFmode && mode2 == TFmode)
21681 || (mode1 == TFmode && mode2 == IFmode)))
21682 return N_("__ibm128 and long double cannot be used in the same "
21685 if (!TARGET_IEEEQUAD
21686 && ((mode1 == KFmode && mode2 == TFmode)
21687 || (mode1 == TFmode && mode2 == KFmode)))
21688 return N_("__float128 and long double cannot be used in the same "
21696 /* Expand floating point conversion to/from __float128 and __ibm128. */
21699 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21701 machine_mode dest_mode = GET_MODE (dest);
21702 machine_mode src_mode = GET_MODE (src);
21703 convert_optab cvt = unknown_optab;
21704 bool do_move = false;
21705 rtx libfunc = NULL_RTX;
21707 typedef rtx (*rtx_2func_t) (rtx, rtx);
21708 rtx_2func_t hw_convert = (rtx_2func_t)0;
21712 rtx_2func_t from_df;
21713 rtx_2func_t from_sf;
21714 rtx_2func_t from_si_sign;
21715 rtx_2func_t from_si_uns;
21716 rtx_2func_t from_di_sign;
21717 rtx_2func_t from_di_uns;
21720 rtx_2func_t to_si_sign;
21721 rtx_2func_t to_si_uns;
21722 rtx_2func_t to_di_sign;
21723 rtx_2func_t to_di_uns;
21724 } hw_conversions[2] = {
21725 /* convertions to/from KFmode */
21727 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21728 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21729 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21730 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21731 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21732 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21733 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21734 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21735 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21736 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21737 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21738 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21741 /* convertions to/from TFmode */
21743 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21744 gen_extendsftf2_hw, /* TFmode <- SFmode. */
21745 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
21746 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
21747 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
21748 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
21749 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
21750 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
21751 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
21752 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
21753 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
21754 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
21758 if (dest_mode == src_mode)
21759 gcc_unreachable ();
21761 /* Eliminate memory operations. */
21763 src = force_reg (src_mode, src);
21767 rtx tmp = gen_reg_rtx (dest_mode);
21768 rs6000_expand_float128_convert (tmp, src, unsigned_p);
21769 rs6000_emit_move (dest, tmp, dest_mode);
21773 /* Convert to IEEE 128-bit floating point. */
21774 if (FLOAT128_IEEE_P (dest_mode))
21776 if (dest_mode == KFmode)
21778 else if (dest_mode == TFmode)
21781 gcc_unreachable ();
21787 hw_convert = hw_conversions[kf_or_tf].from_df;
21792 hw_convert = hw_conversions[kf_or_tf].from_sf;
21798 if (FLOAT128_IBM_P (src_mode))
21807 cvt = ufloat_optab;
21808 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
21812 cvt = sfloat_optab;
21813 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
21820 cvt = ufloat_optab;
21821 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
21825 cvt = sfloat_optab;
21826 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
21831 gcc_unreachable ();
21835 /* Convert from IEEE 128-bit floating point. */
21836 else if (FLOAT128_IEEE_P (src_mode))
21838 if (src_mode == KFmode)
21840 else if (src_mode == TFmode)
21843 gcc_unreachable ();
21849 hw_convert = hw_conversions[kf_or_tf].to_df;
21854 hw_convert = hw_conversions[kf_or_tf].to_sf;
21860 if (FLOAT128_IBM_P (dest_mode))
21870 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
21875 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
21883 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
21888 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
21893 gcc_unreachable ();
21897 /* Both IBM format. */
21898 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
21902 gcc_unreachable ();
21904 /* Handle conversion between TFmode/KFmode/IFmode. */
21906 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
21908 /* Handle conversion if we have hardware support. */
21909 else if (TARGET_FLOAT128_HW && hw_convert)
21910 emit_insn ((hw_convert) (dest, src));
21912 /* Call an external function to do the conversion. */
21913 else if (cvt != unknown_optab)
21915 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
21916 gcc_assert (libfunc != NULL_RTX);
21918 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
21921 gcc_assert (dest2 != NULL_RTX);
21922 if (!rtx_equal_p (dest, dest2))
21923 emit_move_insn (dest, dest2);
21927 gcc_unreachable ();
21933 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
21934 can be used as that dest register. Return the dest register. */
21937 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
21939 if (op2 == const0_rtx)
21942 if (GET_CODE (scratch) == SCRATCH)
21943 scratch = gen_reg_rtx (mode);
21945 if (logical_operand (op2, mode))
21946 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
21948 emit_insn (gen_rtx_SET (scratch,
21949 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
21955 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
21958 machine_mode op_mode;
21959 enum rtx_code cond_code;
21960 rtx result = operands[0];
21962 condition_rtx = rs6000_generate_compare (operands[1], mode);
21963 cond_code = GET_CODE (condition_rtx);
21965 if (cond_code == NE
21966 || cond_code == GE || cond_code == LE
21967 || cond_code == GEU || cond_code == LEU
21968 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
21970 rtx not_result = gen_reg_rtx (CCEQmode);
21971 rtx not_op, rev_cond_rtx;
21972 machine_mode cc_mode;
21974 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
21976 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
21977 SImode, XEXP (condition_rtx, 0), const0_rtx);
21978 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
21979 emit_insn (gen_rtx_SET (not_result, not_op));
21980 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
21983 op_mode = GET_MODE (XEXP (operands[1], 0));
21984 if (op_mode == VOIDmode)
21985 op_mode = GET_MODE (XEXP (operands[1], 1));
21987 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
21989 PUT_MODE (condition_rtx, DImode);
21990 convert_move (result, condition_rtx, 0);
21994 PUT_MODE (condition_rtx, SImode);
21995 emit_insn (gen_rtx_SET (result, condition_rtx));
21999 /* Emit a branch of kind CODE to location LOC. */
22002 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22004 rtx condition_rtx, loc_ref;
22006 condition_rtx = rs6000_generate_compare (operands[0], mode);
22007 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22008 emit_jump_insn (gen_rtx_SET (pc_rtx,
22009 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22010 loc_ref, pc_rtx)));
22013 /* Return the string to output a conditional branch to LABEL, which is
22014 the operand template of the label, or NULL if the branch is really a
22015 conditional return.
22017 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22018 condition code register and its mode specifies what kind of
22019 comparison we made.
22021 REVERSED is nonzero if we should reverse the sense of the comparison.
22023 INSN is the insn. */
22026 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22028 static char string[64];
22029 enum rtx_code code = GET_CODE (op);
22030 rtx cc_reg = XEXP (op, 0);
22031 machine_mode mode = GET_MODE (cc_reg);
22032 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22033 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22034 int really_reversed = reversed ^ need_longbranch;
22040 validate_condition_mode (code, mode);
22042 /* Work out which way this really branches. We could use
22043 reverse_condition_maybe_unordered here always but this
22044 makes the resulting assembler clearer. */
22045 if (really_reversed)
22047 /* Reversal of FP compares takes care -- an ordered compare
22048 becomes an unordered compare and vice versa. */
22049 if (mode == CCFPmode)
22050 code = reverse_condition_maybe_unordered (code);
22052 code = reverse_condition (code);
22057 /* Not all of these are actually distinct opcodes, but
22058 we distinguish them for clarity of the resulting assembler. */
22059 case NE: case LTGT:
22060 ccode = "ne"; break;
22061 case EQ: case UNEQ:
22062 ccode = "eq"; break;
22064 ccode = "ge"; break;
22065 case GT: case GTU: case UNGT:
22066 ccode = "gt"; break;
22068 ccode = "le"; break;
22069 case LT: case LTU: case UNLT:
22070 ccode = "lt"; break;
22071 case UNORDERED: ccode = "un"; break;
22072 case ORDERED: ccode = "nu"; break;
22073 case UNGE: ccode = "nl"; break;
22074 case UNLE: ccode = "ng"; break;
22076 gcc_unreachable ();
22079 /* Maybe we have a guess as to how likely the branch is. */
22081 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22082 if (note != NULL_RTX)
22084 /* PROB is the difference from 50%. */
22085 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22086 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22088 /* Only hint for highly probable/improbable branches on newer cpus when
22089 we have real profile data, as static prediction overrides processor
22090 dynamic prediction. For older cpus we may as well always hint, but
22091 assume not taken for branches that are very close to 50% as a
22092 mispredicted taken branch is more expensive than a
22093 mispredicted not-taken branch. */
22094 if (rs6000_always_hint
22095 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22096 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22097 && br_prob_note_reliable_p (note)))
22099 if (abs (prob) > REG_BR_PROB_BASE / 20
22100 && ((prob > 0) ^ need_longbranch))
22108 s += sprintf (s, "b%slr%s ", ccode, pred);
22110 s += sprintf (s, "b%s%s ", ccode, pred);
22112 /* We need to escape any '%' characters in the reg_names string.
22113 Assume they'd only be the first character.... */
22114 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22116 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22120 /* If the branch distance was too far, we may have to use an
22121 unconditional branch to go the distance. */
22122 if (need_longbranch)
22123 s += sprintf (s, ",$+8\n\tb %s", label);
22125 s += sprintf (s, ",%s", label);
22131 /* Return insn for VSX or Altivec comparisons. */
22134 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22137 machine_mode mode = GET_MODE (op0);
22145 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22156 mask = gen_reg_rtx (mode);
22157 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22164 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22165 DMODE is expected destination mode. This is a recursive function. */
22168 rs6000_emit_vector_compare (enum rtx_code rcode,
22170 machine_mode dmode)
22173 bool swap_operands = false;
22174 bool try_again = false;
22176 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22177 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22179 /* See if the comparison works as is. */
22180 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22188 swap_operands = true;
22193 swap_operands = true;
22201 /* Invert condition and try again.
22202 e.g., A != B becomes ~(A==B). */
22204 enum rtx_code rev_code;
22205 enum insn_code nor_code;
22208 rev_code = reverse_condition_maybe_unordered (rcode);
22209 if (rev_code == UNKNOWN)
22212 nor_code = optab_handler (one_cmpl_optab, dmode);
22213 if (nor_code == CODE_FOR_nothing)
22216 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22220 mask = gen_reg_rtx (dmode);
22221 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22229 /* Try GT/GTU/LT/LTU OR EQ */
22232 enum insn_code ior_code;
22233 enum rtx_code new_code;
22254 gcc_unreachable ();
22257 ior_code = optab_handler (ior_optab, dmode);
22258 if (ior_code == CODE_FOR_nothing)
22261 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22265 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22269 mask = gen_reg_rtx (dmode);
22270 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22281 std::swap (op0, op1);
22283 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22288 /* You only get two chances. */
22292 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22293 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22294 operands for the relation operation COND. */
22297 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22298 rtx cond, rtx cc_op0, rtx cc_op1)
22300 machine_mode dest_mode = GET_MODE (dest);
22301 machine_mode mask_mode = GET_MODE (cc_op0);
22302 enum rtx_code rcode = GET_CODE (cond);
22303 machine_mode cc_mode = CCmode;
22306 bool invert_move = false;
22308 if (VECTOR_UNIT_NONE_P (dest_mode))
22311 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22312 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22316 /* Swap operands if we can, and fall back to doing the operation as
22317 specified, and doing a NOR to invert the test. */
22323 /* Invert condition and try again.
22324 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22325 invert_move = true;
22326 rcode = reverse_condition_maybe_unordered (rcode);
22327 if (rcode == UNKNOWN)
22333 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22335 /* Invert condition to avoid compound test. */
22336 invert_move = true;
22337 rcode = reverse_condition (rcode);
22345 /* Mark unsigned tests with CCUNSmode. */
22346 cc_mode = CCUNSmode;
22348 /* Invert condition to avoid compound test if necessary. */
22349 if (rcode == GEU || rcode == LEU)
22351 invert_move = true;
22352 rcode = reverse_condition (rcode);
22360 /* Get the vector mask for the given relational operations. */
22361 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22367 std::swap (op_true, op_false);
22369 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22370 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22371 && (GET_CODE (op_true) == CONST_VECTOR
22372 || GET_CODE (op_false) == CONST_VECTOR))
22374 rtx constant_0 = CONST0_RTX (dest_mode);
22375 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22377 if (op_true == constant_m1 && op_false == constant_0)
22379 emit_move_insn (dest, mask);
22383 else if (op_true == constant_0 && op_false == constant_m1)
22385 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22389 /* If we can't use the vector comparison directly, perhaps we can use
22390 the mask for the true or false fields, instead of loading up a
22392 if (op_true == constant_m1)
22395 if (op_false == constant_0)
22399 if (!REG_P (op_true) && !SUBREG_P (op_true))
22400 op_true = force_reg (dest_mode, op_true);
22402 if (!REG_P (op_false) && !SUBREG_P (op_false))
22403 op_false = force_reg (dest_mode, op_false);
22405 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22406 CONST0_RTX (dest_mode));
22407 emit_insn (gen_rtx_SET (dest,
22408 gen_rtx_IF_THEN_ELSE (dest_mode,
22415 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22416 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22417 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22418 hardware has no such operation. */
22421 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22423 enum rtx_code code = GET_CODE (op);
22424 rtx op0 = XEXP (op, 0);
22425 rtx op1 = XEXP (op, 1);
22426 machine_mode compare_mode = GET_MODE (op0);
22427 machine_mode result_mode = GET_MODE (dest);
22428 bool max_p = false;
22430 if (result_mode != compare_mode)
22433 if (code == GE || code == GT)
22435 else if (code == LE || code == LT)
22440 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22443 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22449 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22453 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22454 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22455 operands of the last comparison is nonzero/true, FALSE_COND if it is
22456 zero/false. Return 0 if the hardware has no such operation. */
22459 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22461 enum rtx_code code = GET_CODE (op);
22462 rtx op0 = XEXP (op, 0);
22463 rtx op1 = XEXP (op, 1);
22464 machine_mode result_mode = GET_MODE (dest);
22469 if (!can_create_pseudo_p ())
22482 code = swap_condition (code);
22483 std::swap (op0, op1);
22490 /* Generate: [(parallel [(set (dest)
22491 (if_then_else (op (cmp1) (cmp2))
22494 (clobber (scratch))])]. */
22496 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22497 cmove_rtx = gen_rtx_SET (dest,
22498 gen_rtx_IF_THEN_ELSE (result_mode,
22503 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22504 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22505 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22510 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22511 operands of the last comparison is nonzero/true, FALSE_COND if it
22512 is zero/false. Return 0 if the hardware has no such operation. */
22515 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22517 enum rtx_code code = GET_CODE (op);
22518 rtx op0 = XEXP (op, 0);
22519 rtx op1 = XEXP (op, 1);
22520 machine_mode compare_mode = GET_MODE (op0);
22521 machine_mode result_mode = GET_MODE (dest);
22523 bool is_against_zero;
22525 /* These modes should always match. */
22526 if (GET_MODE (op1) != compare_mode
22527 /* In the isel case however, we can use a compare immediate, so
22528 op1 may be a small constant. */
22529 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22531 if (GET_MODE (true_cond) != result_mode)
22533 if (GET_MODE (false_cond) != result_mode)
22536 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22537 if (TARGET_P9_MINMAX
22538 && (compare_mode == SFmode || compare_mode == DFmode)
22539 && (result_mode == SFmode || result_mode == DFmode))
22541 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22544 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22548 /* Don't allow using floating point comparisons for integer results for
22550 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22553 /* First, work out if the hardware can do this at all, or
22554 if it's too slow.... */
22555 if (!FLOAT_MODE_P (compare_mode))
22558 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22562 is_against_zero = op1 == CONST0_RTX (compare_mode);
22564 /* A floating-point subtract might overflow, underflow, or produce
22565 an inexact result, thus changing the floating-point flags, so it
22566 can't be generated if we care about that. It's safe if one side
22567 of the construct is zero, since then no subtract will be
22569 if (SCALAR_FLOAT_MODE_P (compare_mode)
22570 && flag_trapping_math && ! is_against_zero)
22573 /* Eliminate half of the comparisons by switching operands, this
22574 makes the remaining code simpler. */
22575 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22576 || code == LTGT || code == LT || code == UNLE)
22578 code = reverse_condition_maybe_unordered (code);
22580 true_cond = false_cond;
22584 /* UNEQ and LTGT take four instructions for a comparison with zero,
22585 it'll probably be faster to use a branch here too. */
22586 if (code == UNEQ && HONOR_NANS (compare_mode))
22589 /* We're going to try to implement comparisons by performing
22590 a subtract, then comparing against zero. Unfortunately,
22591 Inf - Inf is NaN which is not zero, and so if we don't
22592 know that the operand is finite and the comparison
22593 would treat EQ different to UNORDERED, we can't do it. */
22594 if (HONOR_INFINITIES (compare_mode)
22595 && code != GT && code != UNGE
22596 && (GET_CODE (op1) != CONST_DOUBLE
22597 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22598 /* Constructs of the form (a OP b ? a : b) are safe. */
22599 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22600 || (! rtx_equal_p (op0, true_cond)
22601 && ! rtx_equal_p (op1, true_cond))))
22604 /* At this point we know we can use fsel. */
22606 /* Reduce the comparison to a comparison against zero. */
22607 if (! is_against_zero)
22609 temp = gen_reg_rtx (compare_mode);
22610 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22612 op1 = CONST0_RTX (compare_mode);
22615 /* If we don't care about NaNs we can reduce some of the comparisons
22616 down to faster ones. */
22617 if (! HONOR_NANS (compare_mode))
22623 true_cond = false_cond;
22636 /* Now, reduce everything down to a GE. */
22643 temp = gen_reg_rtx (compare_mode);
22644 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22649 temp = gen_reg_rtx (compare_mode);
22650 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22655 temp = gen_reg_rtx (compare_mode);
22656 emit_insn (gen_rtx_SET (temp,
22657 gen_rtx_NEG (compare_mode,
22658 gen_rtx_ABS (compare_mode, op0))));
22663 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22664 temp = gen_reg_rtx (result_mode);
22665 emit_insn (gen_rtx_SET (temp,
22666 gen_rtx_IF_THEN_ELSE (result_mode,
22667 gen_rtx_GE (VOIDmode,
22669 true_cond, false_cond)));
22670 false_cond = true_cond;
22673 temp = gen_reg_rtx (compare_mode);
22674 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22679 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22680 temp = gen_reg_rtx (result_mode);
22681 emit_insn (gen_rtx_SET (temp,
22682 gen_rtx_IF_THEN_ELSE (result_mode,
22683 gen_rtx_GE (VOIDmode,
22685 true_cond, false_cond)));
22686 true_cond = false_cond;
22689 temp = gen_reg_rtx (compare_mode);
22690 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22695 gcc_unreachable ();
22698 emit_insn (gen_rtx_SET (dest,
22699 gen_rtx_IF_THEN_ELSE (result_mode,
22700 gen_rtx_GE (VOIDmode,
22702 true_cond, false_cond)));
22706 /* Same as above, but for ints (isel). */
22709 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22711 rtx condition_rtx, cr;
22712 machine_mode mode = GET_MODE (dest);
22713 enum rtx_code cond_code;
22714 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22717 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22720 /* We still have to do the compare, because isel doesn't do a
22721 compare, it just looks at the CRx bits set by a previous compare
22723 condition_rtx = rs6000_generate_compare (op, mode);
22724 cond_code = GET_CODE (condition_rtx);
22725 cr = XEXP (condition_rtx, 0);
22726 signedp = GET_MODE (cr) == CCmode;
22728 isel_func = (mode == SImode
22729 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22730 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22734 case LT: case GT: case LTU: case GTU: case EQ:
22735 /* isel handles these directly. */
22739 /* We need to swap the sense of the comparison. */
22741 std::swap (false_cond, true_cond);
22742 PUT_CODE (condition_rtx, reverse_condition (cond_code));
22747 false_cond = force_reg (mode, false_cond);
22748 if (true_cond != const0_rtx)
22749 true_cond = force_reg (mode, true_cond);
22751 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
22757 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
22759 machine_mode mode = GET_MODE (op0);
22763 /* VSX/altivec have direct min/max insns. */
22764 if ((code == SMAX || code == SMIN)
22765 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
22766 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
22768 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
22772 if (code == SMAX || code == SMIN)
22777 if (code == SMAX || code == UMAX)
22778 target = emit_conditional_move (dest, c, op0, op1, mode,
22779 op0, op1, mode, 0);
22781 target = emit_conditional_move (dest, c, op0, op1, mode,
22782 op1, op0, mode, 0);
22783 gcc_assert (target);
22784 if (target != dest)
22785 emit_move_insn (dest, target);
22788 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22789 COND is true. Mark the jump as unlikely to be taken. */
22792 emit_unlikely_jump (rtx cond, rtx label)
22794 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
22795 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
22796 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
22799 /* A subroutine of the atomic operation splitters. Emit a load-locked
22800 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22801 the zero_extend operation. */
22804 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
22806 rtx (*fn) (rtx, rtx) = NULL;
22811 fn = gen_load_lockedqi;
22814 fn = gen_load_lockedhi;
22817 if (GET_MODE (mem) == QImode)
22818 fn = gen_load_lockedqi_si;
22819 else if (GET_MODE (mem) == HImode)
22820 fn = gen_load_lockedhi_si;
22822 fn = gen_load_lockedsi;
22825 fn = gen_load_lockeddi;
22828 fn = gen_load_lockedti;
22831 gcc_unreachable ();
22833 emit_insn (fn (reg, mem));
22836 /* A subroutine of the atomic operation splitters. Emit a store-conditional
22837 instruction in MODE. */
22840 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
22842 rtx (*fn) (rtx, rtx, rtx) = NULL;
22847 fn = gen_store_conditionalqi;
22850 fn = gen_store_conditionalhi;
22853 fn = gen_store_conditionalsi;
22856 fn = gen_store_conditionaldi;
22859 fn = gen_store_conditionalti;
22862 gcc_unreachable ();
22865 /* Emit sync before stwcx. to address PPC405 Erratum. */
22866 if (PPC405_ERRATUM77)
22867 emit_insn (gen_hwsync ());
22869 emit_insn (fn (res, mem, val));
22872 /* Expand barriers before and after a load_locked/store_cond sequence. */
22875 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
22877 rtx addr = XEXP (mem, 0);
22879 if (!legitimate_indirect_address_p (addr, reload_completed)
22880 && !legitimate_indexed_address_p (addr, reload_completed))
22882 addr = force_reg (Pmode, addr);
22883 mem = replace_equiv_address_nv (mem, addr);
22888 case MEMMODEL_RELAXED:
22889 case MEMMODEL_CONSUME:
22890 case MEMMODEL_ACQUIRE:
22892 case MEMMODEL_RELEASE:
22893 case MEMMODEL_ACQ_REL:
22894 emit_insn (gen_lwsync ());
22896 case MEMMODEL_SEQ_CST:
22897 emit_insn (gen_hwsync ());
22900 gcc_unreachable ();
22906 rs6000_post_atomic_barrier (enum memmodel model)
22910 case MEMMODEL_RELAXED:
22911 case MEMMODEL_CONSUME:
22912 case MEMMODEL_RELEASE:
22914 case MEMMODEL_ACQUIRE:
22915 case MEMMODEL_ACQ_REL:
22916 case MEMMODEL_SEQ_CST:
22917 emit_insn (gen_isync ());
22920 gcc_unreachable ();
22924 /* A subroutine of the various atomic expanders. For sub-word operations,
22925 we must adjust things to operate on SImode. Given the original MEM,
22926 return a new aligned memory. Also build and return the quantities by
22927 which to shift and mask. */
22930 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
22932 rtx addr, align, shift, mask, mem;
22933 HOST_WIDE_INT shift_mask;
22934 machine_mode mode = GET_MODE (orig_mem);
22936 /* For smaller modes, we have to implement this via SImode. */
22937 shift_mask = (mode == QImode ? 0x18 : 0x10);
22939 addr = XEXP (orig_mem, 0);
22940 addr = force_reg (GET_MODE (addr), addr);
22942 /* Aligned memory containing subword. Generate a new memory. We
22943 do not want any of the existing MEM_ATTR data, as we're now
22944 accessing memory outside the original object. */
22945 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
22946 NULL_RTX, 1, OPTAB_LIB_WIDEN);
22947 mem = gen_rtx_MEM (SImode, align);
22948 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
22949 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
22950 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
22952 /* Shift amount for subword relative to aligned word. */
22953 shift = gen_reg_rtx (SImode);
22954 addr = gen_lowpart (SImode, addr);
22955 rtx tmp = gen_reg_rtx (SImode);
22956 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
22957 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
22958 if (BYTES_BIG_ENDIAN)
22959 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
22960 shift, 1, OPTAB_LIB_WIDEN);
22963 /* Mask for insertion. */
22964 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
22965 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
22971 /* A subroutine of the various atomic expanders. For sub-word operands,
22972 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
22975 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
22979 x = gen_reg_rtx (SImode);
22980 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
22981 gen_rtx_NOT (SImode, mask),
22984 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
22989 /* A subroutine of the various atomic expanders. For sub-word operands,
22990 extract WIDE to NARROW via SHIFT. */
22993 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
22995 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
22996 wide, 1, OPTAB_LIB_WIDEN);
22997 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23000 /* Expand an atomic compare and swap operation. */
23003 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23005 rtx boolval, retval, mem, oldval, newval, cond;
23006 rtx label1, label2, x, mask, shift;
23007 machine_mode mode, orig_mode;
23008 enum memmodel mod_s, mod_f;
23011 boolval = operands[0];
23012 retval = operands[1];
23014 oldval = operands[3];
23015 newval = operands[4];
23016 is_weak = (INTVAL (operands[5]) != 0);
23017 mod_s = memmodel_base (INTVAL (operands[6]));
23018 mod_f = memmodel_base (INTVAL (operands[7]));
23019 orig_mode = mode = GET_MODE (mem);
23021 mask = shift = NULL_RTX;
23022 if (mode == QImode || mode == HImode)
23024 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23025 lwarx and shift/mask operations. With power8, we need to do the
23026 comparison in SImode, but the store is still done in QI/HImode. */
23027 oldval = convert_modes (SImode, mode, oldval, 1);
23029 if (!TARGET_SYNC_HI_QI)
23031 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23033 /* Shift and mask OLDVAL into position with the word. */
23034 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23035 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23037 /* Shift and mask NEWVAL into position within the word. */
23038 newval = convert_modes (SImode, mode, newval, 1);
23039 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23040 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23043 /* Prepare to adjust the return value. */
23044 retval = gen_reg_rtx (SImode);
23047 else if (reg_overlap_mentioned_p (retval, oldval))
23048 oldval = copy_to_reg (oldval);
23050 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23051 oldval = copy_to_mode_reg (mode, oldval);
23053 if (reg_overlap_mentioned_p (retval, newval))
23054 newval = copy_to_reg (newval);
23056 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23061 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23062 emit_label (XEXP (label1, 0));
23064 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23066 emit_load_locked (mode, retval, mem);
23070 x = expand_simple_binop (SImode, AND, retval, mask,
23071 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23073 cond = gen_reg_rtx (CCmode);
23074 /* If we have TImode, synthesize a comparison. */
23075 if (mode != TImode)
23076 x = gen_rtx_COMPARE (CCmode, x, oldval);
23079 rtx xor1_result = gen_reg_rtx (DImode);
23080 rtx xor2_result = gen_reg_rtx (DImode);
23081 rtx or_result = gen_reg_rtx (DImode);
23082 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23083 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23084 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23085 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23087 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23088 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23089 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23090 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23093 emit_insn (gen_rtx_SET (cond, x));
23095 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23096 emit_unlikely_jump (x, label2);
23100 x = rs6000_mask_atomic_subword (retval, newval, mask);
23102 emit_store_conditional (orig_mode, cond, mem, x);
23106 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23107 emit_unlikely_jump (x, label1);
23110 if (!is_mm_relaxed (mod_f))
23111 emit_label (XEXP (label2, 0));
23113 rs6000_post_atomic_barrier (mod_s);
23115 if (is_mm_relaxed (mod_f))
23116 emit_label (XEXP (label2, 0));
23119 rs6000_finish_atomic_subword (operands[1], retval, shift);
23120 else if (mode != GET_MODE (operands[1]))
23121 convert_move (operands[1], retval, 1);
23123 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23124 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23125 emit_insn (gen_rtx_SET (boolval, x));
23128 /* Expand an atomic exchange operation. */
23131 rs6000_expand_atomic_exchange (rtx operands[])
23133 rtx retval, mem, val, cond;
23135 enum memmodel model;
23136 rtx label, x, mask, shift;
23138 retval = operands[0];
23141 model = memmodel_base (INTVAL (operands[3]));
23142 mode = GET_MODE (mem);
23144 mask = shift = NULL_RTX;
23145 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23147 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23149 /* Shift and mask VAL into position with the word. */
23150 val = convert_modes (SImode, mode, val, 1);
23151 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23152 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23154 /* Prepare to adjust the return value. */
23155 retval = gen_reg_rtx (SImode);
23159 mem = rs6000_pre_atomic_barrier (mem, model);
23161 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23162 emit_label (XEXP (label, 0));
23164 emit_load_locked (mode, retval, mem);
23168 x = rs6000_mask_atomic_subword (retval, val, mask);
23170 cond = gen_reg_rtx (CCmode);
23171 emit_store_conditional (mode, cond, mem, x);
23173 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23174 emit_unlikely_jump (x, label);
23176 rs6000_post_atomic_barrier (model);
23179 rs6000_finish_atomic_subword (operands[0], retval, shift);
23182 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23183 to perform. MEM is the memory on which to operate. VAL is the second
23184 operand of the binary operator. BEFORE and AFTER are optional locations to
23185 return the value of MEM either before of after the operation. MODEL_RTX
23186 is a CONST_INT containing the memory model to use. */
23189 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23190 rtx orig_before, rtx orig_after, rtx model_rtx)
23192 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23193 machine_mode mode = GET_MODE (mem);
23194 machine_mode store_mode = mode;
23195 rtx label, x, cond, mask, shift;
23196 rtx before = orig_before, after = orig_after;
23198 mask = shift = NULL_RTX;
23199 /* On power8, we want to use SImode for the operation. On previous systems,
23200 use the operation in a subword and shift/mask to get the proper byte or
23202 if (mode == QImode || mode == HImode)
23204 if (TARGET_SYNC_HI_QI)
23206 val = convert_modes (SImode, mode, val, 1);
23208 /* Prepare to adjust the return value. */
23209 before = gen_reg_rtx (SImode);
23211 after = gen_reg_rtx (SImode);
23216 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23218 /* Shift and mask VAL into position with the word. */
23219 val = convert_modes (SImode, mode, val, 1);
23220 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23221 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23227 /* We've already zero-extended VAL. That is sufficient to
23228 make certain that it does not affect other bits. */
23233 /* If we make certain that all of the other bits in VAL are
23234 set, that will be sufficient to not affect other bits. */
23235 x = gen_rtx_NOT (SImode, mask);
23236 x = gen_rtx_IOR (SImode, x, val);
23237 emit_insn (gen_rtx_SET (val, x));
23244 /* These will all affect bits outside the field and need
23245 adjustment via MASK within the loop. */
23249 gcc_unreachable ();
23252 /* Prepare to adjust the return value. */
23253 before = gen_reg_rtx (SImode);
23255 after = gen_reg_rtx (SImode);
23256 store_mode = mode = SImode;
23260 mem = rs6000_pre_atomic_barrier (mem, model);
23262 label = gen_label_rtx ();
23263 emit_label (label);
23264 label = gen_rtx_LABEL_REF (VOIDmode, label);
23266 if (before == NULL_RTX)
23267 before = gen_reg_rtx (mode);
23269 emit_load_locked (mode, before, mem);
23273 x = expand_simple_binop (mode, AND, before, val,
23274 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23275 after = expand_simple_unop (mode, NOT, x, after, 1);
23279 after = expand_simple_binop (mode, code, before, val,
23280 after, 1, OPTAB_LIB_WIDEN);
23286 x = expand_simple_binop (SImode, AND, after, mask,
23287 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23288 x = rs6000_mask_atomic_subword (before, x, mask);
23290 else if (store_mode != mode)
23291 x = convert_modes (store_mode, mode, x, 1);
23293 cond = gen_reg_rtx (CCmode);
23294 emit_store_conditional (store_mode, cond, mem, x);
23296 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23297 emit_unlikely_jump (x, label);
23299 rs6000_post_atomic_barrier (model);
23303 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23304 then do the calcuations in a SImode register. */
23306 rs6000_finish_atomic_subword (orig_before, before, shift);
23308 rs6000_finish_atomic_subword (orig_after, after, shift);
23310 else if (store_mode != mode)
23312 /* QImode/HImode on machines with lbarx/lharx where we do the native
23313 operation and then do the calcuations in a SImode register. */
23315 convert_move (orig_before, before, 1);
23317 convert_move (orig_after, after, 1);
23319 else if (orig_after && after != orig_after)
23320 emit_move_insn (orig_after, after);
23323 /* Emit instructions to move SRC to DST. Called by splitters for
23324 multi-register moves. It will emit at most one instruction for
23325 each register that is accessed; that is, it won't emit li/lis pairs
23326 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23330 rs6000_split_multireg_move (rtx dst, rtx src)
23332 /* The register number of the first register being moved. */
23334 /* The mode that is to be moved. */
23336 /* The mode that the move is being done in, and its size. */
23337 machine_mode reg_mode;
23339 /* The number of registers that will be moved. */
23342 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23343 mode = GET_MODE (dst);
23344 nregs = hard_regno_nregs (reg, mode);
23345 if (FP_REGNO_P (reg))
23346 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23347 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23348 else if (ALTIVEC_REGNO_P (reg))
23349 reg_mode = V16QImode;
23351 reg_mode = word_mode;
23352 reg_mode_size = GET_MODE_SIZE (reg_mode);
23354 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23356 /* TDmode residing in FP registers is special, since the ISA requires that
23357 the lower-numbered word of a register pair is always the most significant
23358 word, even in little-endian mode. This does not match the usual subreg
23359 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23360 the appropriate constituent registers "by hand" in little-endian mode.
23362 Note we do not need to check for destructive overlap here since TDmode
23363 can only reside in even/odd register pairs. */
23364 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23369 for (i = 0; i < nregs; i++)
23371 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23372 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23374 p_src = simplify_gen_subreg (reg_mode, src, mode,
23375 i * reg_mode_size);
23377 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23378 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23380 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23381 i * reg_mode_size);
23383 emit_insn (gen_rtx_SET (p_dst, p_src));
23389 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23391 /* Move register range backwards, if we might have destructive
23394 for (i = nregs - 1; i >= 0; i--)
23395 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23396 i * reg_mode_size),
23397 simplify_gen_subreg (reg_mode, src, mode,
23398 i * reg_mode_size)));
23404 bool used_update = false;
23405 rtx restore_basereg = NULL_RTX;
23407 if (MEM_P (src) && INT_REGNO_P (reg))
23411 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23412 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23415 breg = XEXP (XEXP (src, 0), 0);
23416 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23417 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23418 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23419 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23420 src = replace_equiv_address (src, breg);
23422 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23424 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23426 rtx basereg = XEXP (XEXP (src, 0), 0);
23429 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23430 emit_insn (gen_rtx_SET (ndst,
23431 gen_rtx_MEM (reg_mode,
23433 used_update = true;
23436 emit_insn (gen_rtx_SET (basereg,
23437 XEXP (XEXP (src, 0), 1)));
23438 src = replace_equiv_address (src, basereg);
23442 rtx basereg = gen_rtx_REG (Pmode, reg);
23443 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23444 src = replace_equiv_address (src, basereg);
23448 breg = XEXP (src, 0);
23449 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23450 breg = XEXP (breg, 0);
23452 /* If the base register we are using to address memory is
23453 also a destination reg, then change that register last. */
23455 && REGNO (breg) >= REGNO (dst)
23456 && REGNO (breg) < REGNO (dst) + nregs)
23457 j = REGNO (breg) - REGNO (dst);
23459 else if (MEM_P (dst) && INT_REGNO_P (reg))
23463 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23464 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23467 breg = XEXP (XEXP (dst, 0), 0);
23468 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23469 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23470 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23472 /* We have to update the breg before doing the store.
23473 Use store with update, if available. */
23477 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23478 emit_insn (TARGET_32BIT
23479 ? (TARGET_POWERPC64
23480 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23481 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
23482 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23483 used_update = true;
23486 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23487 dst = replace_equiv_address (dst, breg);
23489 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23490 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23492 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23494 rtx basereg = XEXP (XEXP (dst, 0), 0);
23497 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23498 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23501 used_update = true;
23504 emit_insn (gen_rtx_SET (basereg,
23505 XEXP (XEXP (dst, 0), 1)));
23506 dst = replace_equiv_address (dst, basereg);
23510 rtx basereg = XEXP (XEXP (dst, 0), 0);
23511 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23512 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23514 && REG_P (offsetreg)
23515 && REGNO (basereg) != REGNO (offsetreg));
23516 if (REGNO (basereg) == 0)
23518 rtx tmp = offsetreg;
23519 offsetreg = basereg;
23522 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23523 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23524 dst = replace_equiv_address (dst, basereg);
23527 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23528 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23531 for (i = 0; i < nregs; i++)
23533 /* Calculate index to next subword. */
23538 /* If compiler already emitted move of first word by
23539 store with update, no need to do anything. */
23540 if (j == 0 && used_update)
23543 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23544 j * reg_mode_size),
23545 simplify_gen_subreg (reg_mode, src, mode,
23546 j * reg_mode_size)));
23548 if (restore_basereg != NULL_RTX)
23549 emit_insn (restore_basereg);
23554 /* This page contains routines that are used to determine what the
23555 function prologue and epilogue code will do and write them out. */
23557 /* Determine whether the REG is really used. */
23560 save_reg_p (int reg)
23562 /* We need to mark the PIC offset register live for the same conditions
23563 as it is set up, or otherwise it won't be saved before we clobber it. */
23565 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23567 /* When calling eh_return, we must return true for all the cases
23568 where conditional_register_usage marks the PIC offset reg
23570 if (TARGET_TOC && TARGET_MINIMAL_TOC
23571 && (crtl->calls_eh_return
23572 || df_regs_ever_live_p (reg)
23573 || !constant_pool_empty_p ()))
23576 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
23581 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23584 /* Return the first fixed-point register that is required to be
23585 saved. 32 if none. */
23588 first_reg_to_save (void)
23592 /* Find lowest numbered live register. */
23593 for (first_reg = 13; first_reg <= 31; first_reg++)
23594 if (save_reg_p (first_reg))
23599 && crtl->uses_pic_offset_table
23600 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
23601 return RS6000_PIC_OFFSET_TABLE_REGNUM;
23607 /* Similar, for FP regs. */
23610 first_fp_reg_to_save (void)
23614 /* Find lowest numbered live register. */
23615 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23616 if (save_reg_p (first_reg))
23622 /* Similar, for AltiVec regs. */
23625 first_altivec_reg_to_save (void)
23629 /* Stack frame remains as is unless we are in AltiVec ABI. */
23630 if (! TARGET_ALTIVEC_ABI)
23631 return LAST_ALTIVEC_REGNO + 1;
23633 /* On Darwin, the unwind routines are compiled without
23634 TARGET_ALTIVEC, and use save_world to save/restore the
23635 altivec registers when necessary. */
23636 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23637 && ! TARGET_ALTIVEC)
23638 return FIRST_ALTIVEC_REGNO + 20;
23640 /* Find lowest numbered live register. */
23641 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23642 if (save_reg_p (i))
23648 /* Return a 32-bit mask of the AltiVec registers we need to set in
23649 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23650 the 32-bit word is 0. */
23652 static unsigned int
23653 compute_vrsave_mask (void)
23655 unsigned int i, mask = 0;
23657 /* On Darwin, the unwind routines are compiled without
23658 TARGET_ALTIVEC, and use save_world to save/restore the
23659 call-saved altivec registers when necessary. */
23660 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23661 && ! TARGET_ALTIVEC)
23664 /* First, find out if we use _any_ altivec registers. */
23665 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23666 if (df_regs_ever_live_p (i))
23667 mask |= ALTIVEC_REG_BIT (i);
23672 /* Next, remove the argument registers from the set. These must
23673 be in the VRSAVE mask set by the caller, so we don't need to add
23674 them in again. More importantly, the mask we compute here is
23675 used to generate CLOBBERs in the set_vrsave insn, and we do not
23676 wish the argument registers to die. */
23677 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23678 mask &= ~ALTIVEC_REG_BIT (i);
23680 /* Similarly, remove the return value from the set. */
23683 diddle_return_value (is_altivec_return_reg, &yes);
23685 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23691 /* For a very restricted set of circumstances, we can cut down the
23692 size of prologues/epilogues by calling our own save/restore-the-world
23696 compute_save_world_info (rs6000_stack_t *info)
23698 info->world_save_p = 1;
23700 = (WORLD_SAVE_P (info)
23701 && DEFAULT_ABI == ABI_DARWIN
23702 && !cfun->has_nonlocal_label
23703 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23704 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23705 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23706 && info->cr_save_p);
23708 /* This will not work in conjunction with sibcalls. Make sure there
23709 are none. (This check is expensive, but seldom executed.) */
23710 if (WORLD_SAVE_P (info))
23713 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23714 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23716 info->world_save_p = 0;
23721 if (WORLD_SAVE_P (info))
23723 /* Even if we're not touching VRsave, make sure there's room on the
23724 stack for it, if it looks like we're calling SAVE_WORLD, which
23725 will attempt to save it. */
23726 info->vrsave_size = 4;
23728 /* If we are going to save the world, we need to save the link register too. */
23729 info->lr_save_p = 1;
23731 /* "Save" the VRsave register too if we're saving the world. */
23732 if (info->vrsave_mask == 0)
23733 info->vrsave_mask = compute_vrsave_mask ();
23735 /* Because the Darwin register save/restore routines only handle
23736 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23738 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23739 && (info->first_altivec_reg_save
23740 >= FIRST_SAVED_ALTIVEC_REGNO));
23748 is_altivec_return_reg (rtx reg, void *xyes)
23750 bool *yes = (bool *) xyes;
23751 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
23756 /* Return whether REG is a global user reg or has been specifed by
23757 -ffixed-REG. We should not restore these, and so cannot use
23758 lmw or out-of-line restore functions if there are any. We also
23759 can't save them (well, emit frame notes for them), because frame
23760 unwinding during exception handling will restore saved registers. */
23763 fixed_reg_p (int reg)
23765 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23766 backend sets it, overriding anything the user might have given. */
23767 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23768 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23769 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23770 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23773 return fixed_regs[reg];
23776 /* Determine the strategy for savings/restoring registers. */
23779 SAVE_MULTIPLE = 0x1,
23780 SAVE_INLINE_GPRS = 0x2,
23781 SAVE_INLINE_FPRS = 0x4,
23782 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
23783 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
23784 SAVE_INLINE_VRS = 0x20,
23785 REST_MULTIPLE = 0x100,
23786 REST_INLINE_GPRS = 0x200,
23787 REST_INLINE_FPRS = 0x400,
23788 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
23789 REST_INLINE_VRS = 0x1000
23793 rs6000_savres_strategy (rs6000_stack_t *info,
23794 bool using_static_chain_p)
23798 /* Select between in-line and out-of-line save and restore of regs.
23799 First, all the obvious cases where we don't use out-of-line. */
23800 if (crtl->calls_eh_return
23801 || cfun->machine->ra_need_lr)
23802 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
23803 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
23804 | SAVE_INLINE_VRS | REST_INLINE_VRS);
23806 if (info->first_gp_reg_save == 32)
23807 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23809 if (info->first_fp_reg_save == 64)
23810 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23812 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
23813 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23815 /* Define cutoff for using out-of-line functions to save registers. */
23816 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
23818 if (!optimize_size)
23820 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23821 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23822 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23826 /* Prefer out-of-line restore if it will exit. */
23827 if (info->first_fp_reg_save > 61)
23828 strategy |= SAVE_INLINE_FPRS;
23829 if (info->first_gp_reg_save > 29)
23831 if (info->first_fp_reg_save == 64)
23832 strategy |= SAVE_INLINE_GPRS;
23834 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23836 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
23837 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23840 else if (DEFAULT_ABI == ABI_DARWIN)
23842 if (info->first_fp_reg_save > 60)
23843 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23844 if (info->first_gp_reg_save > 29)
23845 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23846 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23850 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
23851 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
23852 || info->first_fp_reg_save > 61)
23853 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23854 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23855 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23858 /* Don't bother to try to save things out-of-line if r11 is occupied
23859 by the static chain. It would require too much fiddling and the
23860 static chain is rarely used anyway. FPRs are saved w.r.t the stack
23861 pointer on Darwin, and AIX uses r1 or r12. */
23862 if (using_static_chain_p
23863 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
23864 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
23866 | SAVE_INLINE_VRS);
23868 /* Don't ever restore fixed regs. That means we can't use the
23869 out-of-line register restore functions if a fixed reg is in the
23870 range of regs restored. */
23871 if (!(strategy & REST_INLINE_FPRS))
23872 for (int i = info->first_fp_reg_save; i < 64; i++)
23875 strategy |= REST_INLINE_FPRS;
23879 /* We can only use the out-of-line routines to restore fprs if we've
23880 saved all the registers from first_fp_reg_save in the prologue.
23881 Otherwise, we risk loading garbage. Of course, if we have saved
23882 out-of-line then we know we haven't skipped any fprs. */
23883 if ((strategy & SAVE_INLINE_FPRS)
23884 && !(strategy & REST_INLINE_FPRS))
23885 for (int i = info->first_fp_reg_save; i < 64; i++)
23886 if (!save_reg_p (i))
23888 strategy |= REST_INLINE_FPRS;
23892 /* Similarly, for altivec regs. */
23893 if (!(strategy & REST_INLINE_VRS))
23894 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
23897 strategy |= REST_INLINE_VRS;
23901 if ((strategy & SAVE_INLINE_VRS)
23902 && !(strategy & REST_INLINE_VRS))
23903 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
23904 if (!save_reg_p (i))
23906 strategy |= REST_INLINE_VRS;
23910 /* info->lr_save_p isn't yet set if the only reason lr needs to be
23911 saved is an out-of-line save or restore. Set up the value for
23912 the next test (excluding out-of-line gprs). */
23913 bool lr_save_p = (info->lr_save_p
23914 || !(strategy & SAVE_INLINE_FPRS)
23915 || !(strategy & SAVE_INLINE_VRS)
23916 || !(strategy & REST_INLINE_FPRS)
23917 || !(strategy & REST_INLINE_VRS));
23919 if (TARGET_MULTIPLE
23920 && !TARGET_POWERPC64
23921 && info->first_gp_reg_save < 31
23922 && !(flag_shrink_wrap
23923 && flag_shrink_wrap_separate
23924 && optimize_function_for_speed_p (cfun)))
23927 for (int i = info->first_gp_reg_save; i < 32; i++)
23928 if (save_reg_p (i))
23932 /* Don't use store multiple if only one reg needs to be
23933 saved. This can occur for example when the ABI_V4 pic reg
23934 (r30) needs to be saved to make calls, but r31 is not
23936 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23939 /* Prefer store multiple for saves over out-of-line
23940 routines, since the store-multiple instruction will
23941 always be smaller. */
23942 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
23944 /* The situation is more complicated with load multiple.
23945 We'd prefer to use the out-of-line routines for restores,
23946 since the "exit" out-of-line routines can handle the
23947 restore of LR and the frame teardown. However if doesn't
23948 make sense to use the out-of-line routine if that is the
23949 only reason we'd need to save LR, and we can't use the
23950 "exit" out-of-line gpr restore if we have saved some
23951 fprs; In those cases it is advantageous to use load
23952 multiple when available. */
23953 if (info->first_fp_reg_save != 64 || !lr_save_p)
23954 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
23958 /* Using the "exit" out-of-line routine does not improve code size
23959 if using it would require lr to be saved and if only saving one
23961 else if (!lr_save_p && info->first_gp_reg_save > 29)
23962 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23964 /* Don't ever restore fixed regs. */
23965 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
23966 for (int i = info->first_gp_reg_save; i < 32; i++)
23967 if (fixed_reg_p (i))
23969 strategy |= REST_INLINE_GPRS;
23970 strategy &= ~REST_MULTIPLE;
23974 /* We can only use load multiple or the out-of-line routines to
23975 restore gprs if we've saved all the registers from
23976 first_gp_reg_save. Otherwise, we risk loading garbage.
23977 Of course, if we have saved out-of-line or used stmw then we know
23978 we haven't skipped any gprs. */
23979 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
23980 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
23981 for (int i = info->first_gp_reg_save; i < 32; i++)
23982 if (!save_reg_p (i))
23984 strategy |= REST_INLINE_GPRS;
23985 strategy &= ~REST_MULTIPLE;
23989 if (TARGET_ELF && TARGET_64BIT)
23991 if (!(strategy & SAVE_INLINE_FPRS))
23992 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
23993 else if (!(strategy & SAVE_INLINE_GPRS)
23994 && info->first_fp_reg_save == 64)
23995 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
23997 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
23998 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24000 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24001 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24006 /* Calculate the stack information for the current function. This is
24007 complicated by having two separate calling sequences, the AIX calling
24008 sequence and the V.4 calling sequence.
24010 AIX (and Darwin/Mac OS X) stack frames look like:
24012 SP----> +---------------------------------------+
24013 | back chain to caller | 0 0
24014 +---------------------------------------+
24015 | saved CR | 4 8 (8-11)
24016 +---------------------------------------+
24018 +---------------------------------------+
24019 | reserved for compilers | 12 24
24020 +---------------------------------------+
24021 | reserved for binders | 16 32
24022 +---------------------------------------+
24023 | saved TOC pointer | 20 40
24024 +---------------------------------------+
24025 | Parameter save area (+padding*) (P) | 24 48
24026 +---------------------------------------+
24027 | Alloca space (A) | 24+P etc.
24028 +---------------------------------------+
24029 | Local variable space (L) | 24+P+A
24030 +---------------------------------------+
24031 | Float/int conversion temporary (X) | 24+P+A+L
24032 +---------------------------------------+
24033 | Save area for AltiVec registers (W) | 24+P+A+L+X
24034 +---------------------------------------+
24035 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24036 +---------------------------------------+
24037 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24038 +---------------------------------------+
24039 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24040 +---------------------------------------+
24041 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24042 +---------------------------------------+
24043 old SP->| back chain to caller's caller |
24044 +---------------------------------------+
24046 * If the alloca area is present, the parameter save area is
24047 padded so that the former starts 16-byte aligned.
24049 The required alignment for AIX configurations is two words (i.e., 8
24052 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24054 SP----> +---------------------------------------+
24055 | Back chain to caller | 0
24056 +---------------------------------------+
24057 | Save area for CR | 8
24058 +---------------------------------------+
24060 +---------------------------------------+
24061 | Saved TOC pointer | 24
24062 +---------------------------------------+
24063 | Parameter save area (+padding*) (P) | 32
24064 +---------------------------------------+
24065 | Alloca space (A) | 32+P
24066 +---------------------------------------+
24067 | Local variable space (L) | 32+P+A
24068 +---------------------------------------+
24069 | Save area for AltiVec registers (W) | 32+P+A+L
24070 +---------------------------------------+
24071 | AltiVec alignment padding (Y) | 32+P+A+L+W
24072 +---------------------------------------+
24073 | Save area for GP registers (G) | 32+P+A+L+W+Y
24074 +---------------------------------------+
24075 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24076 +---------------------------------------+
24077 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24078 +---------------------------------------+
24080 * If the alloca area is present, the parameter save area is
24081 padded so that the former starts 16-byte aligned.
24083 V.4 stack frames look like:
24085 SP----> +---------------------------------------+
24086 | back chain to caller | 0
24087 +---------------------------------------+
24088 | caller's saved LR | 4
24089 +---------------------------------------+
24090 | Parameter save area (+padding*) (P) | 8
24091 +---------------------------------------+
24092 | Alloca space (A) | 8+P
24093 +---------------------------------------+
24094 | Varargs save area (V) | 8+P+A
24095 +---------------------------------------+
24096 | Local variable space (L) | 8+P+A+V
24097 +---------------------------------------+
24098 | Float/int conversion temporary (X) | 8+P+A+V+L
24099 +---------------------------------------+
24100 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24101 +---------------------------------------+
24102 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24103 +---------------------------------------+
24104 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24105 +---------------------------------------+
24106 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24107 +---------------------------------------+
24108 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24109 +---------------------------------------+
24110 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24111 +---------------------------------------+
24112 old SP->| back chain to caller's caller |
24113 +---------------------------------------+
24115 * If the alloca area is present and the required alignment is
24116 16 bytes, the parameter save area is padded so that the
24117 alloca area starts 16-byte aligned.
24119 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24120 given. (But note below and in sysv4.h that we require only 8 and
24121 may round up the size of our stack frame anyways. The historical
24122 reason is early versions of powerpc-linux which didn't properly
24123 align the stack at program startup. A happy side-effect is that
24124 -mno-eabi libraries can be used with -meabi programs.)
24126 The EABI configuration defaults to the V.4 layout. However,
24127 the stack alignment requirements may differ. If -mno-eabi is not
24128 given, the required stack alignment is 8 bytes; if -mno-eabi is
24129 given, the required alignment is 16 bytes. (But see V.4 comment
24132 #ifndef ABI_STACK_BOUNDARY
24133 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24136 static rs6000_stack_t *
24137 rs6000_stack_info (void)
24139 /* We should never be called for thunks, we are not set up for that. */
24140 gcc_assert (!cfun->is_thunk);
24142 rs6000_stack_t *info = &stack_info;
24143 int reg_size = TARGET_32BIT ? 4 : 8;
24148 HOST_WIDE_INT non_fixed_size;
24149 bool using_static_chain_p;
24151 if (reload_completed && info->reload_completed)
24154 memset (info, 0, sizeof (*info));
24155 info->reload_completed = reload_completed;
24157 /* Select which calling sequence. */
24158 info->abi = DEFAULT_ABI;
24160 /* Calculate which registers need to be saved & save area size. */
24161 info->first_gp_reg_save = first_reg_to_save ();
24162 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24163 even if it currently looks like we won't. Reload may need it to
24164 get at a constant; if so, it will have already created a constant
24165 pool entry for it. */
24166 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24167 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24168 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24169 && crtl->uses_const_pool
24170 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24171 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24173 first_gp = info->first_gp_reg_save;
24175 info->gp_size = reg_size * (32 - first_gp);
24177 info->first_fp_reg_save = first_fp_reg_to_save ();
24178 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24180 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24181 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24182 - info->first_altivec_reg_save);
24184 /* Does this function call anything? */
24185 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24187 /* Determine if we need to save the condition code registers. */
24188 if (save_reg_p (CR2_REGNO)
24189 || save_reg_p (CR3_REGNO)
24190 || save_reg_p (CR4_REGNO))
24192 info->cr_save_p = 1;
24193 if (DEFAULT_ABI == ABI_V4)
24194 info->cr_size = reg_size;
24197 /* If the current function calls __builtin_eh_return, then we need
24198 to allocate stack space for registers that will hold data for
24199 the exception handler. */
24200 if (crtl->calls_eh_return)
24203 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24206 ehrd_size = i * UNITS_PER_WORD;
24211 /* In the ELFv2 ABI, we also need to allocate space for separate
24212 CR field save areas if the function calls __builtin_eh_return. */
24213 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24215 /* This hard-codes that we have three call-saved CR fields. */
24216 ehcr_size = 3 * reg_size;
24217 /* We do *not* use the regular CR save mechanism. */
24218 info->cr_save_p = 0;
24223 /* Determine various sizes. */
24224 info->reg_size = reg_size;
24225 info->fixed_size = RS6000_SAVE_AREA;
24226 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24227 if (cfun->calls_alloca)
24229 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24230 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24232 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24233 TARGET_ALTIVEC ? 16 : 8);
24234 if (FRAME_GROWS_DOWNWARD)
24236 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24237 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24238 - (info->fixed_size + info->vars_size + info->parm_size);
24240 if (TARGET_ALTIVEC_ABI)
24241 info->vrsave_mask = compute_vrsave_mask ();
24243 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24244 info->vrsave_size = 4;
24246 compute_save_world_info (info);
24248 /* Calculate the offsets. */
24249 switch (DEFAULT_ABI)
24253 gcc_unreachable ();
24258 info->fp_save_offset = -info->fp_size;
24259 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24261 if (TARGET_ALTIVEC_ABI)
24263 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24265 /* Align stack so vector save area is on a quadword boundary.
24266 The padding goes above the vectors. */
24267 if (info->altivec_size != 0)
24268 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24270 info->altivec_save_offset = info->vrsave_save_offset
24271 - info->altivec_padding_size
24272 - info->altivec_size;
24273 gcc_assert (info->altivec_size == 0
24274 || info->altivec_save_offset % 16 == 0);
24276 /* Adjust for AltiVec case. */
24277 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24280 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24282 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24283 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24284 info->lr_save_offset = 2*reg_size;
24288 info->fp_save_offset = -info->fp_size;
24289 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24290 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24292 if (TARGET_ALTIVEC_ABI)
24294 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24296 /* Align stack so vector save area is on a quadword boundary. */
24297 if (info->altivec_size != 0)
24298 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24300 info->altivec_save_offset = info->vrsave_save_offset
24301 - info->altivec_padding_size
24302 - info->altivec_size;
24304 /* Adjust for AltiVec case. */
24305 info->ehrd_offset = info->altivec_save_offset;
24308 info->ehrd_offset = info->cr_save_offset;
24310 info->ehrd_offset -= ehrd_size;
24311 info->lr_save_offset = reg_size;
24314 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24315 info->save_size = RS6000_ALIGN (info->fp_size
24317 + info->altivec_size
24318 + info->altivec_padding_size
24322 + info->vrsave_size,
24325 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24327 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24328 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24330 /* Determine if we need to save the link register. */
24332 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24334 && !TARGET_PROFILE_KERNEL)
24335 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24336 #ifdef TARGET_RELOCATABLE
24337 || (DEFAULT_ABI == ABI_V4
24338 && (TARGET_RELOCATABLE || flag_pic > 1)
24339 && !constant_pool_empty_p ())
24341 || rs6000_ra_ever_killed ())
24342 info->lr_save_p = 1;
24344 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24345 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24346 && call_used_regs[STATIC_CHAIN_REGNUM]);
24347 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24349 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24350 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24351 || !(info->savres_strategy & SAVE_INLINE_VRS)
24352 || !(info->savres_strategy & REST_INLINE_GPRS)
24353 || !(info->savres_strategy & REST_INLINE_FPRS)
24354 || !(info->savres_strategy & REST_INLINE_VRS))
24355 info->lr_save_p = 1;
24357 if (info->lr_save_p)
24358 df_set_regs_ever_live (LR_REGNO, true);
24360 /* Determine if we need to allocate any stack frame:
24362 For AIX we need to push the stack if a frame pointer is needed
24363 (because the stack might be dynamically adjusted), if we are
24364 debugging, if we make calls, or if the sum of fp_save, gp_save,
24365 and local variables are more than the space needed to save all
24366 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24367 + 18*8 = 288 (GPR13 reserved).
24369 For V.4 we don't have the stack cushion that AIX uses, but assume
24370 that the debugger can handle stackless frames. */
24375 else if (DEFAULT_ABI == ABI_V4)
24376 info->push_p = non_fixed_size != 0;
24378 else if (frame_pointer_needed)
24381 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24385 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24391 debug_stack_info (rs6000_stack_t *info)
24393 const char *abi_string;
24396 info = rs6000_stack_info ();
24398 fprintf (stderr, "\nStack information for function %s:\n",
24399 ((current_function_decl && DECL_NAME (current_function_decl))
24400 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24405 default: abi_string = "Unknown"; break;
24406 case ABI_NONE: abi_string = "NONE"; break;
24407 case ABI_AIX: abi_string = "AIX"; break;
24408 case ABI_ELFv2: abi_string = "ELFv2"; break;
24409 case ABI_DARWIN: abi_string = "Darwin"; break;
24410 case ABI_V4: abi_string = "V.4"; break;
24413 fprintf (stderr, "\tABI = %5s\n", abi_string);
24415 if (TARGET_ALTIVEC_ABI)
24416 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24418 if (info->first_gp_reg_save != 32)
24419 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24421 if (info->first_fp_reg_save != 64)
24422 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24424 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24425 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24426 info->first_altivec_reg_save);
24428 if (info->lr_save_p)
24429 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24431 if (info->cr_save_p)
24432 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24434 if (info->vrsave_mask)
24435 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24438 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24441 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24444 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24447 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24449 if (info->altivec_size)
24450 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24451 info->altivec_save_offset);
24453 if (info->vrsave_size)
24454 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24455 info->vrsave_save_offset);
24457 if (info->lr_save_p)
24458 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24460 if (info->cr_save_p)
24461 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24463 if (info->varargs_save_offset)
24464 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24466 if (info->total_size)
24467 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24470 if (info->vars_size)
24471 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24474 if (info->parm_size)
24475 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24477 if (info->fixed_size)
24478 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24481 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24484 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24486 if (info->altivec_size)
24487 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24489 if (info->vrsave_size)
24490 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24492 if (info->altivec_padding_size)
24493 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24494 info->altivec_padding_size);
24497 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24499 if (info->save_size)
24500 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24502 if (info->reg_size != 4)
24503 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24505 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24507 fprintf (stderr, "\n");
24511 rs6000_return_addr (int count, rtx frame)
24513 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24514 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24516 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24518 cfun->machine->ra_needs_full_frame = 1;
24521 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24522 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24523 frame = stack_pointer_rtx;
24524 rtx prev_frame_addr = memory_address (Pmode, frame);
24525 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24526 rtx lr_save_off = plus_constant (Pmode,
24527 prev_frame, RETURN_ADDRESS_OFFSET);
24528 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24529 return gen_rtx_MEM (Pmode, lr_save_addr);
24532 cfun->machine->ra_need_lr = 1;
24533 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24536 /* Say whether a function is a candidate for sibcall handling or not. */
24539 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24543 /* The sibcall epilogue may clobber the static chain register.
24544 ??? We could work harder and avoid that, but it's probably
24545 not worth the hassle in practice. */
24546 if (CALL_EXPR_STATIC_CHAIN (exp))
24550 fntype = TREE_TYPE (decl);
24552 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24554 /* We can't do it if the called function has more vector parameters
24555 than the current function; there's nowhere to put the VRsave code. */
24556 if (TARGET_ALTIVEC_ABI
24557 && TARGET_ALTIVEC_VRSAVE
24558 && !(decl && decl == current_function_decl))
24560 function_args_iterator args_iter;
24564 /* Functions with vector parameters are required to have a
24565 prototype, so the argument type info must be available
24567 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24568 if (TREE_CODE (type) == VECTOR_TYPE
24569 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24572 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24573 if (TREE_CODE (type) == VECTOR_TYPE
24574 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24581 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24582 functions, because the callee may have a different TOC pointer to
24583 the caller and there's no way to ensure we restore the TOC when
24584 we return. With the secure-plt SYSV ABI we can't make non-local
24585 calls when -fpic/PIC because the plt call stubs use r30. */
24586 if (DEFAULT_ABI == ABI_DARWIN
24587 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24589 && !DECL_EXTERNAL (decl)
24590 && !DECL_WEAK (decl)
24591 && (*targetm.binds_local_p) (decl))
24592 || (DEFAULT_ABI == ABI_V4
24593 && (!TARGET_SECURE_PLT
24596 && (*targetm.binds_local_p) (decl)))))
24598 tree attr_list = TYPE_ATTRIBUTES (fntype);
24600 if (!lookup_attribute ("longcall", attr_list)
24601 || lookup_attribute ("shortcall", attr_list))
24609 rs6000_ra_ever_killed (void)
24615 if (cfun->is_thunk)
24618 if (cfun->machine->lr_save_state)
24619 return cfun->machine->lr_save_state - 1;
24621 /* regs_ever_live has LR marked as used if any sibcalls are present,
24622 but this should not force saving and restoring in the
24623 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24624 clobbers LR, so that is inappropriate. */
24626 /* Also, the prologue can generate a store into LR that
24627 doesn't really count, like this:
24630 bcl to set PIC register
24634 When we're called from the epilogue, we need to avoid counting
24635 this as a store. */
24637 push_topmost_sequence ();
24638 top = get_insns ();
24639 pop_topmost_sequence ();
24640 reg = gen_rtx_REG (Pmode, LR_REGNO);
24642 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24648 if (!SIBLING_CALL_P (insn))
24651 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24653 else if (set_of (reg, insn) != NULL_RTX
24654 && !prologue_epilogue_contains (insn))
24661 /* Emit instructions needed to load the TOC register.
24662 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24663 a constant pool; or for SVR4 -fpic. */
24666 rs6000_emit_load_toc_table (int fromprolog)
24669 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24671 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24674 rtx lab, tmp1, tmp2, got;
24676 lab = gen_label_rtx ();
24677 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24678 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24681 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24685 got = rs6000_got_sym ();
24686 tmp1 = tmp2 = dest;
24689 tmp1 = gen_reg_rtx (Pmode);
24690 tmp2 = gen_reg_rtx (Pmode);
24692 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24693 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24694 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24695 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24697 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24699 emit_insn (gen_load_toc_v4_pic_si ());
24700 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24702 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24705 rtx temp0 = (fromprolog
24706 ? gen_rtx_REG (Pmode, 0)
24707 : gen_reg_rtx (Pmode));
24713 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24714 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24716 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
24717 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24719 emit_insn (gen_load_toc_v4_PIC_1 (symF));
24720 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24721 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
24727 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24729 lab = gen_label_rtx ();
24730 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
24731 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24732 if (TARGET_LINK_STACK)
24733 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
24734 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
24736 emit_insn (gen_addsi3 (dest, temp0, dest));
24738 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
24740 /* This is for AIX code running in non-PIC ELF32. */
24741 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24744 emit_insn (gen_elf_high (dest, realsym));
24745 emit_insn (gen_elf_low (dest, dest, realsym));
24749 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24752 emit_insn (gen_load_toc_aix_si (dest));
24754 emit_insn (gen_load_toc_aix_di (dest));
24758 /* Emit instructions to restore the link register after determining where
24759 its value has been stored. */
24762 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
24764 rs6000_stack_t *info = rs6000_stack_info ();
24767 operands[0] = source;
24768 operands[1] = scratch;
24770 if (info->lr_save_p)
24772 rtx frame_rtx = stack_pointer_rtx;
24773 HOST_WIDE_INT sp_offset = 0;
24776 if (frame_pointer_needed
24777 || cfun->calls_alloca
24778 || info->total_size > 32767)
24780 tmp = gen_frame_mem (Pmode, frame_rtx);
24781 emit_move_insn (operands[1], tmp);
24782 frame_rtx = operands[1];
24784 else if (info->push_p)
24785 sp_offset = info->total_size;
24787 tmp = plus_constant (Pmode, frame_rtx,
24788 info->lr_save_offset + sp_offset);
24789 tmp = gen_frame_mem (Pmode, tmp);
24790 emit_move_insn (tmp, operands[0]);
24793 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
24795 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24796 state of lr_save_p so any change from here on would be a bug. In
24797 particular, stop rs6000_ra_ever_killed from considering the SET
24798 of lr we may have added just above. */
24799 cfun->machine->lr_save_state = info->lr_save_p + 1;
24802 static GTY(()) alias_set_type set = -1;
24805 get_TOC_alias_set (void)
24808 set = new_alias_set ();
24812 /* This returns nonzero if the current function uses the TOC. This is
24813 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24814 is generated by the ABI_V4 load_toc_* patterns.
24815 Return 2 instead of 1 if the load_toc_* pattern is in the function
24816 partition that doesn't start the function. */
24824 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24828 rtx pat = PATTERN (insn);
24831 if (GET_CODE (pat) == PARALLEL)
24832 for (i = 0; i < XVECLEN (pat, 0); i++)
24834 rtx sub = XVECEXP (pat, 0, i);
24835 if (GET_CODE (sub) == USE)
24837 sub = XEXP (sub, 0);
24838 if (GET_CODE (sub) == UNSPEC
24839 && XINT (sub, 1) == UNSPEC_TOC)
24844 else if (crtl->has_bb_partition
24846 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
24854 create_TOC_reference (rtx symbol, rtx largetoc_reg)
24856 rtx tocrel, tocreg, hi;
24858 if (TARGET_DEBUG_ADDR)
24860 if (GET_CODE (symbol) == SYMBOL_REF)
24861 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
24865 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
24866 GET_RTX_NAME (GET_CODE (symbol)));
24867 debug_rtx (symbol);
24871 if (!can_create_pseudo_p ())
24872 df_set_regs_ever_live (TOC_REGISTER, true);
24874 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
24875 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
24876 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
24879 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
24880 if (largetoc_reg != NULL)
24882 emit_move_insn (largetoc_reg, hi);
24885 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
24888 /* Issue assembly directives that create a reference to the given DWARF
24889 FRAME_TABLE_LABEL from the current function section. */
24891 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
24893 fprintf (asm_out_file, "\t.ref %s\n",
24894 (* targetm.strip_name_encoding) (frame_table_label));
24897 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
24898 and the change to the stack pointer. */
24901 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
24908 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
24909 if (hard_frame_needed)
24910 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
24911 if (!(REGNO (fp) == STACK_POINTER_REGNUM
24912 || (hard_frame_needed
24913 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
24916 p = rtvec_alloc (i);
24919 rtx mem = gen_frame_mem (BLKmode, regs[i]);
24920 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
24923 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
24926 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
24927 and set the appropriate attributes for the generated insn. Return the
24928 first insn which adjusts the stack pointer or the last insn before
24929 the stack adjustment loop.
24931 SIZE_INT is used to create the CFI note for the allocation.
24933 SIZE_RTX is an rtx containing the size of the adjustment. Note that
24934 since stacks grow to lower addresses its runtime value is -SIZE_INT.
24936 ORIG_SP contains the backchain value that must be stored at *sp. */
24939 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
24943 rtx size_rtx = GEN_INT (-size_int);
24944 if (size_int > 32767)
24946 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
24947 /* Need a note here so that try_split doesn't get confused. */
24948 if (get_last_insn () == NULL_RTX)
24949 emit_note (NOTE_INSN_DELETED);
24950 insn = emit_move_insn (tmp_reg, size_rtx);
24951 try_split (PATTERN (insn), insn, 0);
24952 size_rtx = tmp_reg;
24955 if (Pmode == SImode)
24956 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
24961 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
24965 rtx par = PATTERN (insn);
24966 gcc_assert (GET_CODE (par) == PARALLEL);
24967 rtx set = XVECEXP (par, 0, 0);
24968 gcc_assert (GET_CODE (set) == SET);
24969 rtx mem = SET_DEST (set);
24970 gcc_assert (MEM_P (mem));
24971 MEM_NOTRAP_P (mem) = 1;
24972 set_mem_alias_set (mem, get_frame_alias_set ());
24974 RTX_FRAME_RELATED_P (insn) = 1;
24975 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
24976 gen_rtx_SET (stack_pointer_rtx,
24977 gen_rtx_PLUS (Pmode,
24979 GEN_INT (-size_int))));
24981 /* Emit a blockage to ensure the allocation/probing insns are
24982 not optimized, combined, removed, etc. Add REG_STACK_CHECK
24983 note for similar reasons. */
24984 if (flag_stack_clash_protection)
24986 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
24987 emit_insn (gen_blockage ());
24993 static HOST_WIDE_INT
24994 get_stack_clash_protection_probe_interval (void)
24996 return (HOST_WIDE_INT_1U
24997 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25000 static HOST_WIDE_INT
25001 get_stack_clash_protection_guard_size (void)
25003 return (HOST_WIDE_INT_1U
25004 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25007 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25008 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25010 COPY_REG, if non-null, should contain a copy of the original
25011 stack pointer at exit from this function.
25013 This is subtly different than the Ada probing in that it tries hard to
25014 prevent attacks that jump the stack guard. Thus it is never allowed to
25015 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25016 space without a suitable probe. */
25018 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25021 rtx orig_sp = copy_reg;
25023 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25025 /* Round the size down to a multiple of PROBE_INTERVAL. */
25026 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25028 /* If explicitly requested,
25029 or the rounded size is not the same as the original size
25030 or the the rounded size is greater than a page,
25031 then we will need a copy of the original stack pointer. */
25032 if (rounded_size != orig_size
25033 || rounded_size > probe_interval
25036 /* If the caller did not request a copy of the incoming stack
25037 pointer, then we use r0 to hold the copy. */
25039 orig_sp = gen_rtx_REG (Pmode, 0);
25040 emit_move_insn (orig_sp, stack_pointer_rtx);
25043 /* There's three cases here.
25045 One is a single probe which is the most common and most efficiently
25046 implemented as it does not have to have a copy of the original
25047 stack pointer if there are no residuals.
25049 Second is unrolled allocation/probes which we use if there's just
25050 a few of them. It needs to save the original stack pointer into a
25051 temporary for use as a source register in the allocation/probe.
25053 Last is a loop. This is the most uncommon case and least efficient. */
25054 rtx_insn *retval = NULL;
25055 if (rounded_size == probe_interval)
25057 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25059 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25061 else if (rounded_size <= 8 * probe_interval)
25063 /* The ABI requires using the store with update insns to allocate
25064 space and store the backchain into the stack
25066 So we save the current stack pointer into a temporary, then
25067 emit the store-with-update insns to store the saved stack pointer
25068 into the right location in each new page. */
25069 for (int i = 0; i < rounded_size; i += probe_interval)
25072 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25074 /* Save the first stack adjustment in RETVAL. */
25079 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25083 /* Compute the ending address. */
25085 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25086 rtx rs = GEN_INT (-rounded_size);
25088 if (add_operand (rs, Pmode))
25089 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25092 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25093 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25094 stack_pointer_rtx));
25095 /* Describe the effect of INSN to the CFI engine. */
25096 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25097 gen_rtx_SET (end_addr,
25098 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25101 RTX_FRAME_RELATED_P (insn) = 1;
25103 /* Emit the loop. */
25105 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25106 stack_pointer_rtx, orig_sp,
25109 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25110 stack_pointer_rtx, orig_sp,
25112 RTX_FRAME_RELATED_P (retval) = 1;
25113 /* Describe the effect of INSN to the CFI engine. */
25114 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25115 gen_rtx_SET (stack_pointer_rtx, end_addr));
25117 /* Emit a blockage to ensure the allocation/probing insns are
25118 not optimized, combined, removed, etc. Other cases handle this
25119 within their call to rs6000_emit_allocate_stack_1. */
25120 emit_insn (gen_blockage ());
25122 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25125 if (orig_size != rounded_size)
25127 /* Allocate (and implicitly probe) any residual space. */
25128 HOST_WIDE_INT residual = orig_size - rounded_size;
25130 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25132 /* If the residual was the only allocation, then we can return the
25133 allocating insn. */
25141 /* Emit the correct code for allocating stack space, as insns.
25142 If COPY_REG, make sure a copy of the old frame is left there.
25143 The generated code may use hard register 0 as a temporary. */
25146 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25149 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25150 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25151 rtx todec = gen_int_mode (-size, Pmode);
25153 if (INTVAL (todec) != -size)
25155 warning (0, "stack frame too large");
25156 emit_insn (gen_trap ());
25160 if (crtl->limit_stack)
25162 if (REG_P (stack_limit_rtx)
25163 && REGNO (stack_limit_rtx) > 1
25164 && REGNO (stack_limit_rtx) <= 31)
25167 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25170 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25172 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25174 && DEFAULT_ABI == ABI_V4
25177 rtx toload = gen_rtx_CONST (VOIDmode,
25178 gen_rtx_PLUS (Pmode,
25182 emit_insn (gen_elf_high (tmp_reg, toload));
25183 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25184 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25188 warning (0, "stack limit expression is not supported");
25191 if (flag_stack_clash_protection)
25193 if (size < get_stack_clash_protection_guard_size ())
25194 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25197 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25200 /* If we asked for a copy with an offset, then we still need add in
25202 if (copy_reg && copy_off)
25203 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25211 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25213 emit_move_insn (copy_reg, stack_reg);
25216 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25217 it now and set the alias set/attributes. The above gen_*_update
25218 calls will generate a PARALLEL with the MEM set being the first
25220 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25224 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25226 #if PROBE_INTERVAL > 32768
25227 #error Cannot use indexed addressing mode for stack probing
25230 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25231 inclusive. These are offsets from the current stack pointer. */
25234 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25236 /* See if we have a constant small number of probes to generate. If so,
25237 that's the easy case. */
25238 if (first + size <= 32768)
25242 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25243 it exceeds SIZE. If only one probe is needed, this will not
25244 generate any code. Then probe at FIRST + SIZE. */
25245 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25246 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25249 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25253 /* Otherwise, do the same as above, but in a loop. Note that we must be
25254 extra careful with variables wrapping around because we might be at
25255 the very top (or the very bottom) of the address space and we have
25256 to be able to handle this case properly; in particular, we use an
25257 equality test for the loop condition. */
25260 HOST_WIDE_INT rounded_size;
25261 rtx r12 = gen_rtx_REG (Pmode, 12);
25262 rtx r0 = gen_rtx_REG (Pmode, 0);
25264 /* Sanity check for the addressing mode we're going to use. */
25265 gcc_assert (first <= 32768);
25267 /* Step 1: round SIZE to the previous multiple of the interval. */
25269 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25272 /* Step 2: compute initial and final value of the loop counter. */
25274 /* TEST_ADDR = SP + FIRST. */
25275 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25278 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25279 if (rounded_size > 32768)
25281 emit_move_insn (r0, GEN_INT (-rounded_size));
25282 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25285 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25289 /* Step 3: the loop
25293 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25296 while (TEST_ADDR != LAST_ADDR)
25298 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25299 until it is equal to ROUNDED_SIZE. */
25302 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25304 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25307 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25308 that SIZE is equal to ROUNDED_SIZE. */
25310 if (size != rounded_size)
25311 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25315 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25316 addresses, not offsets. */
25318 static const char *
25319 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25321 static int labelno = 0;
25325 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25328 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25330 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25332 xops[1] = GEN_INT (-PROBE_INTERVAL);
25333 output_asm_insn ("addi %0,%0,%1", xops);
25335 /* Probe at TEST_ADDR. */
25336 xops[1] = gen_rtx_REG (Pmode, 0);
25337 output_asm_insn ("stw %1,0(%0)", xops);
25339 /* Test if TEST_ADDR == LAST_ADDR. */
25342 output_asm_insn ("cmpd 0,%0,%1", xops);
25344 output_asm_insn ("cmpw 0,%0,%1", xops);
25347 fputs ("\tbne 0,", asm_out_file);
25348 assemble_name_raw (asm_out_file, loop_lab);
25349 fputc ('\n', asm_out_file);
25354 /* This function is called when rs6000_frame_related is processing
25355 SETs within a PARALLEL, and returns whether the REGNO save ought to
25356 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25357 for out-of-line register save functions, store multiple, and the
25358 Darwin world_save. They may contain registers that don't really
25362 interesting_frame_related_regno (unsigned int regno)
25364 /* Saves apparently of r0 are actually saving LR. It doesn't make
25365 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25366 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25367 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25368 as frame related. */
25371 /* If we see CR2 then we are here on a Darwin world save. Saves of
25372 CR2 signify the whole CR is being saved. This is a long-standing
25373 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25374 that CR needs to be saved. */
25375 if (regno == CR2_REGNO)
25377 /* Omit frame info for any user-defined global regs. If frame info
25378 is supplied for them, frame unwinding will restore a user reg.
25379 Also omit frame info for any reg we don't need to save, as that
25380 bloats frame info and can cause problems with shrink wrapping.
25381 Since global regs won't be seen as needing to be saved, both of
25382 these conditions are covered by save_reg_p. */
25383 return save_reg_p (regno);
25386 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25387 addresses, not offsets.
25389 REG2 contains the backchain that must be stored into *sp at each allocation.
25391 This is subtly different than the Ada probing above in that it tries hard
25392 to prevent attacks that jump the stack guard. Thus, it is never allowed
25393 to allocate more than PROBE_INTERVAL bytes of stack space without a
25396 static const char *
25397 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25399 static int labelno = 0;
25403 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25405 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25407 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25409 /* This allocates and probes. */
25412 xops[2] = GEN_INT (-probe_interval);
25414 output_asm_insn ("stdu %1,%2(%0)", xops);
25416 output_asm_insn ("stwu %1,%2(%0)", xops);
25418 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25422 output_asm_insn ("cmpd 0,%0,%1", xops);
25424 output_asm_insn ("cmpw 0,%0,%1", xops);
25426 fputs ("\tbne 0,", asm_out_file);
25427 assemble_name_raw (asm_out_file, loop_lab);
25428 fputc ('\n', asm_out_file);
25433 /* Wrapper around the output_probe_stack_range routines. */
25435 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25437 if (flag_stack_clash_protection)
25438 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25440 return output_probe_stack_range_1 (reg1, reg3);
25443 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25444 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25445 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25446 deduce these equivalences by itself so it wasn't necessary to hold
25447 its hand so much. Don't be tempted to always supply d2_f_d_e with
25448 the actual cfa register, ie. r31 when we are using a hard frame
25449 pointer. That fails when saving regs off r1, and sched moves the
25450 r31 setup past the reg saves. */
25453 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25454 rtx reg2, rtx repl2)
25458 if (REGNO (reg) == STACK_POINTER_REGNUM)
25460 gcc_checking_assert (val == 0);
25464 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25467 rtx pat = PATTERN (insn);
25468 if (!repl && !reg2)
25470 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25471 if (GET_CODE (pat) == PARALLEL)
25472 for (int i = 0; i < XVECLEN (pat, 0); i++)
25473 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25475 rtx set = XVECEXP (pat, 0, i);
25477 if (!REG_P (SET_SRC (set))
25478 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25479 RTX_FRAME_RELATED_P (set) = 1;
25481 RTX_FRAME_RELATED_P (insn) = 1;
25485 /* We expect that 'pat' is either a SET or a PARALLEL containing
25486 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25487 are important so they all have to be marked RTX_FRAME_RELATED_P.
25488 Call simplify_replace_rtx on the SETs rather than the whole insn
25489 so as to leave the other stuff alone (for example USE of r12). */
25491 set_used_flags (pat);
25492 if (GET_CODE (pat) == SET)
25495 pat = simplify_replace_rtx (pat, reg, repl);
25497 pat = simplify_replace_rtx (pat, reg2, repl2);
25499 else if (GET_CODE (pat) == PARALLEL)
25501 pat = shallow_copy_rtx (pat);
25502 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25504 for (int i = 0; i < XVECLEN (pat, 0); i++)
25505 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25507 rtx set = XVECEXP (pat, 0, i);
25510 set = simplify_replace_rtx (set, reg, repl);
25512 set = simplify_replace_rtx (set, reg2, repl2);
25513 XVECEXP (pat, 0, i) = set;
25515 if (!REG_P (SET_SRC (set))
25516 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25517 RTX_FRAME_RELATED_P (set) = 1;
25521 gcc_unreachable ();
25523 RTX_FRAME_RELATED_P (insn) = 1;
25524 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25529 /* Returns an insn that has a vrsave set operation with the
25530 appropriate CLOBBERs. */
25533 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25536 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25537 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25540 = gen_rtx_SET (vrsave,
25541 gen_rtx_UNSPEC_VOLATILE (SImode,
25542 gen_rtvec (2, reg, vrsave),
25543 UNSPECV_SET_VRSAVE));
25547 /* We need to clobber the registers in the mask so the scheduler
25548 does not move sets to VRSAVE before sets of AltiVec registers.
25550 However, if the function receives nonlocal gotos, reload will set
25551 all call saved registers live. We will end up with:
25553 (set (reg 999) (mem))
25554 (parallel [ (set (reg vrsave) (unspec blah))
25555 (clobber (reg 999))])
25557 The clobber will cause the store into reg 999 to be dead, and
25558 flow will attempt to delete an epilogue insn. In this case, we
25559 need an unspec use/set of the register. */
25561 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25562 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25564 if (!epiloguep || call_used_regs [i])
25565 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
25566 gen_rtx_REG (V4SImode, i));
25569 rtx reg = gen_rtx_REG (V4SImode, i);
25572 = gen_rtx_SET (reg,
25573 gen_rtx_UNSPEC (V4SImode,
25574 gen_rtvec (1, reg), 27));
25578 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25580 for (i = 0; i < nclobs; ++i)
25581 XVECEXP (insn, 0, i) = clobs[i];
25587 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25591 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25592 mem = gen_frame_mem (GET_MODE (reg), addr);
25593 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25597 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25599 return gen_frame_set (reg, frame_reg, offset, false);
25603 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25605 return gen_frame_set (reg, frame_reg, offset, true);
25608 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25609 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25612 emit_frame_save (rtx frame_reg, machine_mode mode,
25613 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25617 /* Some cases that need register indexed addressing. */
25618 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25619 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25621 reg = gen_rtx_REG (mode, regno);
25622 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25623 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25624 NULL_RTX, NULL_RTX);
25627 /* Emit an offset memory reference suitable for a frame store, while
25628 converting to a valid addressing mode. */
25631 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25633 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25636 #ifndef TARGET_FIX_AND_CONTINUE
25637 #define TARGET_FIX_AND_CONTINUE 0
25640 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25641 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25642 #define LAST_SAVRES_REGISTER 31
25643 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25654 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25656 /* Temporary holding space for an out-of-line register save/restore
25658 static char savres_routine_name[30];
25660 /* Return the name for an out-of-line register save/restore routine.
25661 We are saving/restoring GPRs if GPR is true. */
25664 rs6000_savres_routine_name (int regno, int sel)
25666 const char *prefix = "";
25667 const char *suffix = "";
25669 /* Different targets are supposed to define
25670 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25671 routine name could be defined with:
25673 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25675 This is a nice idea in practice, but in reality, things are
25676 complicated in several ways:
25678 - ELF targets have save/restore routines for GPRs.
25680 - PPC64 ELF targets have routines for save/restore of GPRs that
25681 differ in what they do with the link register, so having a set
25682 prefix doesn't work. (We only use one of the save routines at
25683 the moment, though.)
25685 - PPC32 elf targets have "exit" versions of the restore routines
25686 that restore the link register and can save some extra space.
25687 These require an extra suffix. (There are also "tail" versions
25688 of the restore routines and "GOT" versions of the save routines,
25689 but we don't generate those at present. Same problems apply,
25692 We deal with all this by synthesizing our own prefix/suffix and
25693 using that for the simple sprintf call shown above. */
25694 if (DEFAULT_ABI == ABI_V4)
25699 if ((sel & SAVRES_REG) == SAVRES_GPR)
25700 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25701 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25702 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25703 else if ((sel & SAVRES_REG) == SAVRES_VR)
25704 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25708 if ((sel & SAVRES_LR))
25711 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25713 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25714 /* No out-of-line save/restore routines for GPRs on AIX. */
25715 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
25719 if ((sel & SAVRES_REG) == SAVRES_GPR)
25720 prefix = ((sel & SAVRES_SAVE)
25721 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
25722 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
25723 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25725 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25726 if ((sel & SAVRES_LR))
25727 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
25731 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
25732 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
25735 else if ((sel & SAVRES_REG) == SAVRES_VR)
25736 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25741 if (DEFAULT_ABI == ABI_DARWIN)
25743 /* The Darwin approach is (slightly) different, in order to be
25744 compatible with code generated by the system toolchain. There is a
25745 single symbol for the start of save sequence, and the code here
25746 embeds an offset into that code on the basis of the first register
25748 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
25749 if ((sel & SAVRES_REG) == SAVRES_GPR)
25750 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
25751 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
25752 (regno - 13) * 4, prefix, regno);
25753 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25754 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
25755 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
25756 else if ((sel & SAVRES_REG) == SAVRES_VR)
25757 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
25758 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
25763 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
25765 return savres_routine_name;
25768 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25769 We are saving/restoring GPRs if GPR is true. */
25772 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
25774 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
25775 ? info->first_gp_reg_save
25776 : (sel & SAVRES_REG) == SAVRES_FPR
25777 ? info->first_fp_reg_save - 32
25778 : (sel & SAVRES_REG) == SAVRES_VR
25779 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
25784 /* Don't generate bogus routine names. */
25785 gcc_assert (FIRST_SAVRES_REGISTER <= regno
25786 && regno <= LAST_SAVRES_REGISTER
25787 && select >= 0 && select <= 12);
25789 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
25795 name = rs6000_savres_routine_name (regno, sel);
25797 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
25798 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
25799 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
25805 /* Emit a sequence of insns, including a stack tie if needed, for
25806 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25807 reset the stack pointer, but move the base of the frame into
25808 reg UPDT_REGNO for use by out-of-line register restore routines. */
25811 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
25812 unsigned updt_regno)
25814 /* If there is nothing to do, don't do anything. */
25815 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
25818 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
25820 /* This blockage is needed so that sched doesn't decide to move
25821 the sp change before the register restores. */
25822 if (DEFAULT_ABI == ABI_V4)
25823 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
25824 GEN_INT (frame_off)));
25826 /* If we are restoring registers out-of-line, we will be using the
25827 "exit" variants of the restore routines, which will reset the
25828 stack for us. But we do need to point updt_reg into the
25829 right place for those routines. */
25830 if (frame_off != 0)
25831 return emit_insn (gen_add3_insn (updt_reg_rtx,
25832 frame_reg_rtx, GEN_INT (frame_off)));
25834 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
25839 /* Return the register number used as a pointer by out-of-line
25840 save/restore functions. */
25842 static inline unsigned
25843 ptr_regno_for_savres (int sel)
25845 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25846 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
25847 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
25850 /* Construct a parallel rtx describing the effect of a call to an
25851 out-of-line register save/restore routine, and emit the insn
25852 or jump_insn as appropriate. */
25855 rs6000_emit_savres_rtx (rs6000_stack_t *info,
25856 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
25857 machine_mode reg_mode, int sel)
25860 int offset, start_reg, end_reg, n_regs, use_reg;
25861 int reg_size = GET_MODE_SIZE (reg_mode);
25868 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
25869 ? info->first_gp_reg_save
25870 : (sel & SAVRES_REG) == SAVRES_FPR
25871 ? info->first_fp_reg_save
25872 : (sel & SAVRES_REG) == SAVRES_VR
25873 ? info->first_altivec_reg_save
25875 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
25877 : (sel & SAVRES_REG) == SAVRES_FPR
25879 : (sel & SAVRES_REG) == SAVRES_VR
25880 ? LAST_ALTIVEC_REGNO + 1
25882 n_regs = end_reg - start_reg;
25883 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
25884 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
25887 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25888 RTVEC_ELT (p, offset++) = ret_rtx;
25890 RTVEC_ELT (p, offset++)
25891 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
25893 sym = rs6000_savres_routine_sym (info, sel);
25894 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
25896 use_reg = ptr_regno_for_savres (sel);
25897 if ((sel & SAVRES_REG) == SAVRES_VR)
25899 /* Vector regs are saved/restored using [reg+reg] addressing. */
25900 RTVEC_ELT (p, offset++)
25901 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
25902 RTVEC_ELT (p, offset++)
25903 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
25906 RTVEC_ELT (p, offset++)
25907 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
25909 for (i = 0; i < end_reg - start_reg; i++)
25910 RTVEC_ELT (p, i + offset)
25911 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
25912 frame_reg_rtx, save_area_offset + reg_size * i,
25913 (sel & SAVRES_SAVE) != 0);
25915 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25916 RTVEC_ELT (p, i + offset)
25917 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
25919 par = gen_rtx_PARALLEL (VOIDmode, p);
25921 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
25923 insn = emit_jump_insn (par);
25924 JUMP_LABEL (insn) = ret_rtx;
25927 insn = emit_insn (par);
25931 /* Emit prologue code to store CR fields that need to be saved into REG. This
25932 function should only be called when moving the non-volatile CRs to REG, it
25933 is not a general purpose routine to move the entire set of CRs to REG.
25934 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
25938 rs6000_emit_prologue_move_from_cr (rtx reg)
25940 /* Only the ELFv2 ABI allows storing only selected fields. */
25941 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
25943 int i, cr_reg[8], count = 0;
25945 /* Collect CR fields that must be saved. */
25946 for (i = 0; i < 8; i++)
25947 if (save_reg_p (CR0_REGNO + i))
25948 cr_reg[count++] = i;
25950 /* If it's just a single one, use mfcrf. */
25953 rtvec p = rtvec_alloc (1);
25954 rtvec r = rtvec_alloc (2);
25955 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
25956 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
25958 = gen_rtx_SET (reg,
25959 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
25961 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
25965 /* ??? It might be better to handle count == 2 / 3 cases here
25966 as well, using logical operations to combine the values. */
25969 emit_insn (gen_prologue_movesi_from_cr (reg));
25972 /* Return whether the split-stack arg pointer (r12) is used. */
25975 split_stack_arg_pointer_used_p (void)
25977 /* If the pseudo holding the arg pointer is no longer a pseudo,
25978 then the arg pointer is used. */
25979 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
25980 && (!REG_P (cfun->machine->split_stack_arg_pointer)
25981 || (REGNO (cfun->machine->split_stack_arg_pointer)
25982 < FIRST_PSEUDO_REGISTER)))
25985 /* Unfortunately we also need to do some code scanning, since
25986 r12 may have been substituted for the pseudo. */
25988 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
25989 FOR_BB_INSNS (bb, insn)
25990 if (NONDEBUG_INSN_P (insn))
25992 /* A call destroys r12. */
25997 FOR_EACH_INSN_USE (use, insn)
25999 rtx x = DF_REF_REG (use);
26000 if (REG_P (x) && REGNO (x) == 12)
26004 FOR_EACH_INSN_DEF (def, insn)
26006 rtx x = DF_REF_REG (def);
26007 if (REG_P (x) && REGNO (x) == 12)
26011 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26014 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26017 rs6000_global_entry_point_needed_p (void)
26019 /* Only needed for the ELFv2 ABI. */
26020 if (DEFAULT_ABI != ABI_ELFv2)
26023 /* With -msingle-pic-base, we assume the whole program shares the same
26024 TOC, so no global entry point prologues are needed anywhere. */
26025 if (TARGET_SINGLE_PIC_BASE)
26028 /* Ensure we have a global entry point for thunks. ??? We could
26029 avoid that if the target routine doesn't need a global entry point,
26030 but we do not know whether this is the case at this point. */
26031 if (cfun->is_thunk)
26034 /* For regular functions, rs6000_emit_prologue sets this flag if the
26035 routine ever uses the TOC pointer. */
26036 return cfun->machine->r2_setup_needed;
26039 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26041 rs6000_get_separate_components (void)
26043 rs6000_stack_t *info = rs6000_stack_info ();
26045 if (WORLD_SAVE_P (info))
26048 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26049 && !(info->savres_strategy & REST_MULTIPLE));
26051 /* Component 0 is the save/restore of LR (done via GPR0).
26052 Component 2 is the save of the TOC (GPR2).
26053 Components 13..31 are the save/restore of GPR13..GPR31.
26054 Components 46..63 are the save/restore of FPR14..FPR31. */
26056 cfun->machine->n_components = 64;
26058 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26059 bitmap_clear (components);
26061 int reg_size = TARGET_32BIT ? 4 : 8;
26062 int fp_reg_size = 8;
26064 /* The GPRs we need saved to the frame. */
26065 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26066 && (info->savres_strategy & REST_INLINE_GPRS))
26068 int offset = info->gp_save_offset;
26070 offset += info->total_size;
26072 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26074 if (IN_RANGE (offset, -0x8000, 0x7fff)
26075 && save_reg_p (regno))
26076 bitmap_set_bit (components, regno);
26078 offset += reg_size;
26082 /* Don't mess with the hard frame pointer. */
26083 if (frame_pointer_needed)
26084 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26086 /* Don't mess with the fixed TOC register. */
26087 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26088 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26089 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26090 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26092 /* The FPRs we need saved to the frame. */
26093 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26094 && (info->savres_strategy & REST_INLINE_FPRS))
26096 int offset = info->fp_save_offset;
26098 offset += info->total_size;
26100 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26102 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26103 bitmap_set_bit (components, regno);
26105 offset += fp_reg_size;
26109 /* Optimize LR save and restore if we can. This is component 0. Any
26110 out-of-line register save/restore routines need LR. */
26111 if (info->lr_save_p
26112 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26113 && (info->savres_strategy & SAVE_INLINE_GPRS)
26114 && (info->savres_strategy & REST_INLINE_GPRS)
26115 && (info->savres_strategy & SAVE_INLINE_FPRS)
26116 && (info->savres_strategy & REST_INLINE_FPRS)
26117 && (info->savres_strategy & SAVE_INLINE_VRS)
26118 && (info->savres_strategy & REST_INLINE_VRS))
26120 int offset = info->lr_save_offset;
26122 offset += info->total_size;
26123 if (IN_RANGE (offset, -0x8000, 0x7fff))
26124 bitmap_set_bit (components, 0);
26127 /* Optimize saving the TOC. This is component 2. */
26128 if (cfun->machine->save_toc_in_prologue)
26129 bitmap_set_bit (components, 2);
26134 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26136 rs6000_components_for_bb (basic_block bb)
26138 rs6000_stack_t *info = rs6000_stack_info ();
26140 bitmap in = DF_LIVE_IN (bb);
26141 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26142 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26144 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26145 bitmap_clear (components);
26147 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26150 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26151 if (bitmap_bit_p (in, regno)
26152 || bitmap_bit_p (gen, regno)
26153 || bitmap_bit_p (kill, regno))
26154 bitmap_set_bit (components, regno);
26157 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26158 if (bitmap_bit_p (in, regno)
26159 || bitmap_bit_p (gen, regno)
26160 || bitmap_bit_p (kill, regno))
26161 bitmap_set_bit (components, regno);
26163 /* The link register. */
26164 if (bitmap_bit_p (in, LR_REGNO)
26165 || bitmap_bit_p (gen, LR_REGNO)
26166 || bitmap_bit_p (kill, LR_REGNO))
26167 bitmap_set_bit (components, 0);
26169 /* The TOC save. */
26170 if (bitmap_bit_p (in, TOC_REGNUM)
26171 || bitmap_bit_p (gen, TOC_REGNUM)
26172 || bitmap_bit_p (kill, TOC_REGNUM))
26173 bitmap_set_bit (components, 2);
26178 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26180 rs6000_disqualify_components (sbitmap components, edge e,
26181 sbitmap edge_components, bool /*is_prologue*/)
26183 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26184 live where we want to place that code. */
26185 if (bitmap_bit_p (edge_components, 0)
26186 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26189 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26190 "on entry to bb %d\n", e->dest->index);
26191 bitmap_clear_bit (components, 0);
26195 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26197 rs6000_emit_prologue_components (sbitmap components)
26199 rs6000_stack_t *info = rs6000_stack_info ();
26200 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26201 ? HARD_FRAME_POINTER_REGNUM
26202 : STACK_POINTER_REGNUM);
26204 machine_mode reg_mode = Pmode;
26205 int reg_size = TARGET_32BIT ? 4 : 8;
26206 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26207 int fp_reg_size = 8;
26209 /* Prologue for LR. */
26210 if (bitmap_bit_p (components, 0))
26212 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26213 rtx reg = gen_rtx_REG (reg_mode, 0);
26214 rtx_insn *insn = emit_move_insn (reg, lr);
26215 RTX_FRAME_RELATED_P (insn) = 1;
26216 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26218 int offset = info->lr_save_offset;
26220 offset += info->total_size;
26222 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26223 RTX_FRAME_RELATED_P (insn) = 1;
26224 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26225 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26228 /* Prologue for TOC. */
26229 if (bitmap_bit_p (components, 2))
26231 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26232 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26233 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26236 /* Prologue for the GPRs. */
26237 int offset = info->gp_save_offset;
26239 offset += info->total_size;
26241 for (int i = info->first_gp_reg_save; i < 32; i++)
26243 if (bitmap_bit_p (components, i))
26245 rtx reg = gen_rtx_REG (reg_mode, i);
26246 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26247 RTX_FRAME_RELATED_P (insn) = 1;
26248 rtx set = copy_rtx (single_set (insn));
26249 add_reg_note (insn, REG_CFA_OFFSET, set);
26252 offset += reg_size;
26255 /* Prologue for the FPRs. */
26256 offset = info->fp_save_offset;
26258 offset += info->total_size;
26260 for (int i = info->first_fp_reg_save; i < 64; i++)
26262 if (bitmap_bit_p (components, i))
26264 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26265 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26266 RTX_FRAME_RELATED_P (insn) = 1;
26267 rtx set = copy_rtx (single_set (insn));
26268 add_reg_note (insn, REG_CFA_OFFSET, set);
26271 offset += fp_reg_size;
26275 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26277 rs6000_emit_epilogue_components (sbitmap components)
26279 rs6000_stack_t *info = rs6000_stack_info ();
26280 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26281 ? HARD_FRAME_POINTER_REGNUM
26282 : STACK_POINTER_REGNUM);
26284 machine_mode reg_mode = Pmode;
26285 int reg_size = TARGET_32BIT ? 4 : 8;
26287 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26288 int fp_reg_size = 8;
26290 /* Epilogue for the FPRs. */
26291 int offset = info->fp_save_offset;
26293 offset += info->total_size;
26295 for (int i = info->first_fp_reg_save; i < 64; i++)
26297 if (bitmap_bit_p (components, i))
26299 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26300 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26301 RTX_FRAME_RELATED_P (insn) = 1;
26302 add_reg_note (insn, REG_CFA_RESTORE, reg);
26305 offset += fp_reg_size;
26308 /* Epilogue for the GPRs. */
26309 offset = info->gp_save_offset;
26311 offset += info->total_size;
26313 for (int i = info->first_gp_reg_save; i < 32; i++)
26315 if (bitmap_bit_p (components, i))
26317 rtx reg = gen_rtx_REG (reg_mode, i);
26318 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26319 RTX_FRAME_RELATED_P (insn) = 1;
26320 add_reg_note (insn, REG_CFA_RESTORE, reg);
26323 offset += reg_size;
26326 /* Epilogue for LR. */
26327 if (bitmap_bit_p (components, 0))
26329 int offset = info->lr_save_offset;
26331 offset += info->total_size;
26333 rtx reg = gen_rtx_REG (reg_mode, 0);
26334 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26336 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26337 insn = emit_move_insn (lr, reg);
26338 RTX_FRAME_RELATED_P (insn) = 1;
26339 add_reg_note (insn, REG_CFA_RESTORE, lr);
26343 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26345 rs6000_set_handled_components (sbitmap components)
26347 rs6000_stack_t *info = rs6000_stack_info ();
26349 for (int i = info->first_gp_reg_save; i < 32; i++)
26350 if (bitmap_bit_p (components, i))
26351 cfun->machine->gpr_is_wrapped_separately[i] = true;
26353 for (int i = info->first_fp_reg_save; i < 64; i++)
26354 if (bitmap_bit_p (components, i))
26355 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26357 if (bitmap_bit_p (components, 0))
26358 cfun->machine->lr_is_wrapped_separately = true;
26360 if (bitmap_bit_p (components, 2))
26361 cfun->machine->toc_is_wrapped_separately = true;
26364 /* VRSAVE is a bit vector representing which AltiVec registers
26365 are used. The OS uses this to determine which vector
26366 registers to save on a context switch. We need to save
26367 VRSAVE on the stack frame, add whatever AltiVec registers we
26368 used in this function, and do the corresponding magic in the
26371 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26372 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26374 /* Get VRSAVE into a GPR. */
26375 rtx reg = gen_rtx_REG (SImode, save_regno);
26376 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26378 emit_insn (gen_get_vrsave_internal (reg));
26380 emit_insn (gen_rtx_SET (reg, vrsave));
26383 int offset = info->vrsave_save_offset + frame_off;
26384 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26386 /* Include the registers in the mask. */
26387 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26389 emit_insn (generate_set_vrsave (reg, info, 0));
26392 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26393 called, it left the arg pointer to the old stack in r29. Otherwise, the
26394 arg pointer is the top of the current frame. */
26396 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26397 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26399 cfun->machine->split_stack_argp_used = true;
26403 rtx r12 = gen_rtx_REG (Pmode, 12);
26404 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26405 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26406 emit_insn_before (set_r12, sp_adjust);
26408 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26410 rtx r12 = gen_rtx_REG (Pmode, 12);
26411 if (frame_off == 0)
26412 emit_move_insn (r12, frame_reg_rtx);
26414 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26419 rtx r12 = gen_rtx_REG (Pmode, 12);
26420 rtx r29 = gen_rtx_REG (Pmode, 29);
26421 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26422 rtx not_more = gen_label_rtx ();
26425 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26426 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26427 gen_rtx_LABEL_REF (VOIDmode, not_more),
26429 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26430 JUMP_LABEL (jump) = not_more;
26431 LABEL_NUSES (not_more) += 1;
26432 emit_move_insn (r12, r29);
26433 emit_label (not_more);
26437 /* Emit function prologue as insns. */
26440 rs6000_emit_prologue (void)
26442 rs6000_stack_t *info = rs6000_stack_info ();
26443 machine_mode reg_mode = Pmode;
26444 int reg_size = TARGET_32BIT ? 4 : 8;
26445 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26446 int fp_reg_size = 8;
26447 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26448 rtx frame_reg_rtx = sp_reg_rtx;
26449 unsigned int cr_save_regno;
26450 rtx cr_save_rtx = NULL_RTX;
26453 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26454 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26455 && call_used_regs[STATIC_CHAIN_REGNUM]);
26456 int using_split_stack = (flag_split_stack
26457 && (lookup_attribute ("no_split_stack",
26458 DECL_ATTRIBUTES (cfun->decl))
26461 /* Offset to top of frame for frame_reg and sp respectively. */
26462 HOST_WIDE_INT frame_off = 0;
26463 HOST_WIDE_INT sp_off = 0;
26464 /* sp_adjust is the stack adjusting instruction, tracked so that the
26465 insn setting up the split-stack arg pointer can be emitted just
26466 prior to it, when r12 is not used here for other purposes. */
26467 rtx_insn *sp_adjust = 0;
26470 /* Track and check usage of r0, r11, r12. */
26471 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26472 #define START_USE(R) do \
26474 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26475 reg_inuse |= 1 << (R); \
26477 #define END_USE(R) do \
26479 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26480 reg_inuse &= ~(1 << (R)); \
26482 #define NOT_INUSE(R) do \
26484 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26487 #define START_USE(R) do {} while (0)
26488 #define END_USE(R) do {} while (0)
26489 #define NOT_INUSE(R) do {} while (0)
26492 if (DEFAULT_ABI == ABI_ELFv2
26493 && !TARGET_SINGLE_PIC_BASE)
26495 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26497 /* With -mminimal-toc we may generate an extra use of r2 below. */
26498 if (TARGET_TOC && TARGET_MINIMAL_TOC
26499 && !constant_pool_empty_p ())
26500 cfun->machine->r2_setup_needed = true;
26504 if (flag_stack_usage_info)
26505 current_function_static_stack_size = info->total_size;
26507 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26509 HOST_WIDE_INT size = info->total_size;
26511 if (crtl->is_leaf && !cfun->calls_alloca)
26513 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26514 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26515 size - get_stack_check_protect ());
26518 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26521 if (TARGET_FIX_AND_CONTINUE)
26523 /* gdb on darwin arranges to forward a function from the old
26524 address by modifying the first 5 instructions of the function
26525 to branch to the overriding function. This is necessary to
26526 permit function pointers that point to the old function to
26527 actually forward to the new function. */
26528 emit_insn (gen_nop ());
26529 emit_insn (gen_nop ());
26530 emit_insn (gen_nop ());
26531 emit_insn (gen_nop ());
26532 emit_insn (gen_nop ());
26535 /* Handle world saves specially here. */
26536 if (WORLD_SAVE_P (info))
26543 /* save_world expects lr in r0. */
26544 reg0 = gen_rtx_REG (Pmode, 0);
26545 if (info->lr_save_p)
26547 insn = emit_move_insn (reg0,
26548 gen_rtx_REG (Pmode, LR_REGNO));
26549 RTX_FRAME_RELATED_P (insn) = 1;
26552 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26553 assumptions about the offsets of various bits of the stack
26555 gcc_assert (info->gp_save_offset == -220
26556 && info->fp_save_offset == -144
26557 && info->lr_save_offset == 8
26558 && info->cr_save_offset == 4
26561 && (!crtl->calls_eh_return
26562 || info->ehrd_offset == -432)
26563 && info->vrsave_save_offset == -224
26564 && info->altivec_save_offset == -416);
26566 treg = gen_rtx_REG (SImode, 11);
26567 emit_move_insn (treg, GEN_INT (-info->total_size));
26569 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26570 in R11. It also clobbers R12, so beware! */
26572 /* Preserve CR2 for save_world prologues */
26574 sz += 32 - info->first_gp_reg_save;
26575 sz += 64 - info->first_fp_reg_save;
26576 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26577 p = rtvec_alloc (sz);
26579 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
26580 gen_rtx_REG (SImode,
26582 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26583 gen_rtx_SYMBOL_REF (Pmode,
26585 /* We do floats first so that the instruction pattern matches
26587 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26589 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26590 info->first_fp_reg_save + i),
26592 info->fp_save_offset + frame_off + 8 * i);
26593 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26595 = gen_frame_store (gen_rtx_REG (V4SImode,
26596 info->first_altivec_reg_save + i),
26598 info->altivec_save_offset + frame_off + 16 * i);
26599 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26601 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26603 info->gp_save_offset + frame_off + reg_size * i);
26605 /* CR register traditionally saved as CR2. */
26607 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26608 frame_reg_rtx, info->cr_save_offset + frame_off);
26609 /* Explain about use of R0. */
26610 if (info->lr_save_p)
26612 = gen_frame_store (reg0,
26613 frame_reg_rtx, info->lr_save_offset + frame_off);
26614 /* Explain what happens to the stack pointer. */
26616 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26617 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26620 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26621 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26622 treg, GEN_INT (-info->total_size));
26623 sp_off = frame_off = info->total_size;
26626 strategy = info->savres_strategy;
26628 /* For V.4, update stack before we do any saving and set back pointer. */
26629 if (! WORLD_SAVE_P (info)
26631 && (DEFAULT_ABI == ABI_V4
26632 || crtl->calls_eh_return))
26634 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26635 || !(strategy & SAVE_INLINE_GPRS)
26636 || !(strategy & SAVE_INLINE_VRS));
26637 int ptr_regno = -1;
26638 rtx ptr_reg = NULL_RTX;
26641 if (info->total_size < 32767)
26642 frame_off = info->total_size;
26645 else if (info->cr_save_p
26647 || info->first_fp_reg_save < 64
26648 || info->first_gp_reg_save < 32
26649 || info->altivec_size != 0
26650 || info->vrsave_size != 0
26651 || crtl->calls_eh_return)
26655 /* The prologue won't be saving any regs so there is no need
26656 to set up a frame register to access any frame save area.
26657 We also won't be using frame_off anywhere below, but set
26658 the correct value anyway to protect against future
26659 changes to this function. */
26660 frame_off = info->total_size;
26662 if (ptr_regno != -1)
26664 /* Set up the frame offset to that needed by the first
26665 out-of-line save function. */
26666 START_USE (ptr_regno);
26667 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26668 frame_reg_rtx = ptr_reg;
26669 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26670 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26671 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26672 ptr_off = info->gp_save_offset + info->gp_size;
26673 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26674 ptr_off = info->altivec_save_offset + info->altivec_size;
26675 frame_off = -ptr_off;
26677 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26679 if (REGNO (frame_reg_rtx) == 12)
26681 sp_off = info->total_size;
26682 if (frame_reg_rtx != sp_reg_rtx)
26683 rs6000_emit_stack_tie (frame_reg_rtx, false);
26686 /* If we use the link register, get it into r0. */
26687 if (!WORLD_SAVE_P (info) && info->lr_save_p
26688 && !cfun->machine->lr_is_wrapped_separately)
26690 rtx addr, reg, mem;
26692 reg = gen_rtx_REG (Pmode, 0);
26694 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26695 RTX_FRAME_RELATED_P (insn) = 1;
26697 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26698 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26700 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26701 GEN_INT (info->lr_save_offset + frame_off));
26702 mem = gen_rtx_MEM (Pmode, addr);
26703 /* This should not be of rs6000_sr_alias_set, because of
26704 __builtin_return_address. */
26706 insn = emit_move_insn (mem, reg);
26707 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26708 NULL_RTX, NULL_RTX);
26713 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26714 r12 will be needed by out-of-line gpr save. */
26715 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26716 && !(strategy & (SAVE_INLINE_GPRS
26717 | SAVE_NOINLINE_GPRS_SAVES_LR))
26719 if (!WORLD_SAVE_P (info)
26721 && REGNO (frame_reg_rtx) != cr_save_regno
26722 && !(using_static_chain_p && cr_save_regno == 11)
26723 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
26725 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
26726 START_USE (cr_save_regno);
26727 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26730 /* Do any required saving of fpr's. If only one or two to save, do
26731 it ourselves. Otherwise, call function. */
26732 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
26734 int offset = info->fp_save_offset + frame_off;
26735 for (int i = info->first_fp_reg_save; i < 64; i++)
26738 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
26739 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
26740 sp_off - frame_off);
26742 offset += fp_reg_size;
26745 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
26747 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
26748 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
26749 unsigned ptr_regno = ptr_regno_for_savres (sel);
26750 rtx ptr_reg = frame_reg_rtx;
26752 if (REGNO (frame_reg_rtx) == ptr_regno)
26753 gcc_checking_assert (frame_off == 0);
26756 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26757 NOT_INUSE (ptr_regno);
26758 emit_insn (gen_add3_insn (ptr_reg,
26759 frame_reg_rtx, GEN_INT (frame_off)));
26761 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26762 info->fp_save_offset,
26763 info->lr_save_offset,
26765 rs6000_frame_related (insn, ptr_reg, sp_off,
26766 NULL_RTX, NULL_RTX);
26771 /* Save GPRs. This is done as a PARALLEL if we are using
26772 the store-multiple instructions. */
26773 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
26775 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
26776 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
26777 unsigned ptr_regno = ptr_regno_for_savres (sel);
26778 rtx ptr_reg = frame_reg_rtx;
26779 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
26780 int end_save = info->gp_save_offset + info->gp_size;
26783 if (ptr_regno == 12)
26786 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26788 /* Need to adjust r11 (r12) if we saved any FPRs. */
26789 if (end_save + frame_off != 0)
26791 rtx offset = GEN_INT (end_save + frame_off);
26794 frame_off = -end_save;
26796 NOT_INUSE (ptr_regno);
26797 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
26799 else if (!ptr_set_up)
26801 NOT_INUSE (ptr_regno);
26802 emit_move_insn (ptr_reg, frame_reg_rtx);
26804 ptr_off = -end_save;
26805 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26806 info->gp_save_offset + ptr_off,
26807 info->lr_save_offset + ptr_off,
26809 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
26810 NULL_RTX, NULL_RTX);
26814 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
26818 p = rtvec_alloc (32 - info->first_gp_reg_save);
26819 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26821 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26823 info->gp_save_offset + frame_off + reg_size * i);
26824 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26825 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26826 NULL_RTX, NULL_RTX);
26828 else if (!WORLD_SAVE_P (info))
26830 int offset = info->gp_save_offset + frame_off;
26831 for (int i = info->first_gp_reg_save; i < 32; i++)
26834 && !cfun->machine->gpr_is_wrapped_separately[i])
26835 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
26836 sp_off - frame_off);
26838 offset += reg_size;
26842 if (crtl->calls_eh_return)
26849 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26850 if (regno == INVALID_REGNUM)
26854 p = rtvec_alloc (i);
26858 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26859 if (regno == INVALID_REGNUM)
26863 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
26865 info->ehrd_offset + sp_off + reg_size * (int) i);
26866 RTVEC_ELT (p, i) = set;
26867 RTX_FRAME_RELATED_P (set) = 1;
26870 insn = emit_insn (gen_blockage ());
26871 RTX_FRAME_RELATED_P (insn) = 1;
26872 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
26875 /* In AIX ABI we need to make sure r2 is really saved. */
26876 if (TARGET_AIX && crtl->calls_eh_return)
26878 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
26879 rtx join_insn, note;
26880 rtx_insn *save_insn;
26881 long toc_restore_insn;
26883 tmp_reg = gen_rtx_REG (Pmode, 11);
26884 tmp_reg_si = gen_rtx_REG (SImode, 11);
26885 if (using_static_chain_p)
26888 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
26892 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
26893 /* Peek at instruction to which this function returns. If it's
26894 restoring r2, then we know we've already saved r2. We can't
26895 unconditionally save r2 because the value we have will already
26896 be updated if we arrived at this function via a plt call or
26897 toc adjusting stub. */
26898 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
26899 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
26900 + RS6000_TOC_SAVE_SLOT);
26901 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
26902 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
26903 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
26904 validate_condition_mode (EQ, CCUNSmode);
26905 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
26906 emit_insn (gen_rtx_SET (compare_result,
26907 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
26908 toc_save_done = gen_label_rtx ();
26909 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26910 gen_rtx_EQ (VOIDmode, compare_result,
26912 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
26914 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26915 JUMP_LABEL (jump) = toc_save_done;
26916 LABEL_NUSES (toc_save_done) += 1;
26918 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
26919 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
26920 sp_off - frame_off);
26922 emit_label (toc_save_done);
26924 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
26925 have a CFG that has different saves along different paths.
26926 Move the note to a dummy blockage insn, which describes that
26927 R2 is unconditionally saved after the label. */
26928 /* ??? An alternate representation might be a special insn pattern
26929 containing both the branch and the store. That might let the
26930 code that minimizes the number of DW_CFA_advance opcodes better
26931 freedom in placing the annotations. */
26932 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
26934 remove_note (save_insn, note);
26936 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
26937 copy_rtx (PATTERN (save_insn)), NULL_RTX);
26938 RTX_FRAME_RELATED_P (save_insn) = 0;
26940 join_insn = emit_insn (gen_blockage ());
26941 REG_NOTES (join_insn) = note;
26942 RTX_FRAME_RELATED_P (join_insn) = 1;
26944 if (using_static_chain_p)
26946 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
26953 /* Save CR if we use any that must be preserved. */
26954 if (!WORLD_SAVE_P (info) && info->cr_save_p)
26956 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26957 GEN_INT (info->cr_save_offset + frame_off));
26958 rtx mem = gen_frame_mem (SImode, addr);
26960 /* If we didn't copy cr before, do so now using r0. */
26961 if (cr_save_rtx == NULL_RTX)
26964 cr_save_rtx = gen_rtx_REG (SImode, 0);
26965 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26968 /* Saving CR requires a two-instruction sequence: one instruction
26969 to move the CR to a general-purpose register, and a second
26970 instruction that stores the GPR to memory.
26972 We do not emit any DWARF CFI records for the first of these,
26973 because we cannot properly represent the fact that CR is saved in
26974 a register. One reason is that we cannot express that multiple
26975 CR fields are saved; another reason is that on 64-bit, the size
26976 of the CR register in DWARF (4 bytes) differs from the size of
26977 a general-purpose register.
26979 This means if any intervening instruction were to clobber one of
26980 the call-saved CR fields, we'd have incorrect CFI. To prevent
26981 this from happening, we mark the store to memory as a use of
26982 those CR fields, which prevents any such instruction from being
26983 scheduled in between the two instructions. */
26988 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
26989 for (i = 0; i < 8; i++)
26990 if (save_reg_p (CR0_REGNO + i))
26991 crsave_v[n_crsave++]
26992 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
26994 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
26995 gen_rtvec_v (n_crsave, crsave_v)));
26996 END_USE (REGNO (cr_save_rtx));
26998 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
26999 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27000 so we need to construct a frame expression manually. */
27001 RTX_FRAME_RELATED_P (insn) = 1;
27003 /* Update address to be stack-pointer relative, like
27004 rs6000_frame_related would do. */
27005 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27006 GEN_INT (info->cr_save_offset + sp_off));
27007 mem = gen_frame_mem (SImode, addr);
27009 if (DEFAULT_ABI == ABI_ELFv2)
27011 /* In the ELFv2 ABI we generate separate CFI records for each
27012 CR field that was actually saved. They all point to the
27013 same 32-bit stack slot. */
27017 for (i = 0; i < 8; i++)
27018 if (save_reg_p (CR0_REGNO + i))
27021 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27023 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27027 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27028 gen_rtx_PARALLEL (VOIDmode,
27029 gen_rtvec_v (n_crframe, crframe)));
27033 /* In other ABIs, by convention, we use a single CR regnum to
27034 represent the fact that all call-saved CR fields are saved.
27035 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27036 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27037 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27041 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27042 *separate* slots if the routine calls __builtin_eh_return, so
27043 that they can be independently restored by the unwinder. */
27044 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27046 int i, cr_off = info->ehcr_offset;
27049 /* ??? We might get better performance by using multiple mfocrf
27051 crsave = gen_rtx_REG (SImode, 0);
27052 emit_insn (gen_prologue_movesi_from_cr (crsave));
27054 for (i = 0; i < 8; i++)
27055 if (!call_used_regs[CR0_REGNO + i])
27057 rtvec p = rtvec_alloc (2);
27059 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27061 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27063 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27065 RTX_FRAME_RELATED_P (insn) = 1;
27066 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27067 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27068 sp_reg_rtx, cr_off + sp_off));
27070 cr_off += reg_size;
27074 /* If we are emitting stack probes, but allocate no stack, then
27075 just note that in the dump file. */
27076 if (flag_stack_clash_protection
27079 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27081 /* Update stack and set back pointer unless this is V.4,
27082 for which it was done previously. */
27083 if (!WORLD_SAVE_P (info) && info->push_p
27084 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27086 rtx ptr_reg = NULL;
27089 /* If saving altivec regs we need to be able to address all save
27090 locations using a 16-bit offset. */
27091 if ((strategy & SAVE_INLINE_VRS) == 0
27092 || (info->altivec_size != 0
27093 && (info->altivec_save_offset + info->altivec_size - 16
27094 + info->total_size - frame_off) > 32767)
27095 || (info->vrsave_size != 0
27096 && (info->vrsave_save_offset
27097 + info->total_size - frame_off) > 32767))
27099 int sel = SAVRES_SAVE | SAVRES_VR;
27100 unsigned ptr_regno = ptr_regno_for_savres (sel);
27102 if (using_static_chain_p
27103 && ptr_regno == STATIC_CHAIN_REGNUM)
27105 if (REGNO (frame_reg_rtx) != ptr_regno)
27106 START_USE (ptr_regno);
27107 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27108 frame_reg_rtx = ptr_reg;
27109 ptr_off = info->altivec_save_offset + info->altivec_size;
27110 frame_off = -ptr_off;
27112 else if (REGNO (frame_reg_rtx) == 1)
27113 frame_off = info->total_size;
27114 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27116 if (REGNO (frame_reg_rtx) == 12)
27118 sp_off = info->total_size;
27119 if (frame_reg_rtx != sp_reg_rtx)
27120 rs6000_emit_stack_tie (frame_reg_rtx, false);
27123 /* Set frame pointer, if needed. */
27124 if (frame_pointer_needed)
27126 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27128 RTX_FRAME_RELATED_P (insn) = 1;
27131 /* Save AltiVec registers if needed. Save here because the red zone does
27132 not always include AltiVec registers. */
27133 if (!WORLD_SAVE_P (info)
27134 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27136 int end_save = info->altivec_save_offset + info->altivec_size;
27138 /* Oddly, the vector save/restore functions point r0 at the end
27139 of the save area, then use r11 or r12 to load offsets for
27140 [reg+reg] addressing. */
27141 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27142 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27143 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27145 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27147 if (scratch_regno == 12)
27149 if (end_save + frame_off != 0)
27151 rtx offset = GEN_INT (end_save + frame_off);
27153 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27156 emit_move_insn (ptr_reg, frame_reg_rtx);
27158 ptr_off = -end_save;
27159 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27160 info->altivec_save_offset + ptr_off,
27161 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27162 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27163 NULL_RTX, NULL_RTX);
27164 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27166 /* The oddity mentioned above clobbered our frame reg. */
27167 emit_move_insn (frame_reg_rtx, ptr_reg);
27168 frame_off = ptr_off;
27171 else if (!WORLD_SAVE_P (info)
27172 && info->altivec_size != 0)
27176 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27177 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27179 rtx areg, savereg, mem;
27180 HOST_WIDE_INT offset;
27182 offset = (info->altivec_save_offset + frame_off
27183 + 16 * (i - info->first_altivec_reg_save));
27185 savereg = gen_rtx_REG (V4SImode, i);
27187 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27189 mem = gen_frame_mem (V4SImode,
27190 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27191 GEN_INT (offset)));
27192 insn = emit_insn (gen_rtx_SET (mem, savereg));
27198 areg = gen_rtx_REG (Pmode, 0);
27199 emit_move_insn (areg, GEN_INT (offset));
27201 /* AltiVec addressing mode is [reg+reg]. */
27202 mem = gen_frame_mem (V4SImode,
27203 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27205 /* Rather than emitting a generic move, force use of the stvx
27206 instruction, which we always want on ISA 2.07 (power8) systems.
27207 In particular we don't want xxpermdi/stxvd2x for little
27209 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27212 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27213 areg, GEN_INT (offset));
27217 /* VRSAVE is a bit vector representing which AltiVec registers
27218 are used. The OS uses this to determine which vector
27219 registers to save on a context switch. We need to save
27220 VRSAVE on the stack frame, add whatever AltiVec registers we
27221 used in this function, and do the corresponding magic in the
27224 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27226 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27227 be using r12 as frame_reg_rtx and r11 as the static chain
27228 pointer for nested functions. */
27229 int save_regno = 12;
27230 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27231 && !using_static_chain_p)
27233 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27236 if (using_static_chain_p)
27239 NOT_INUSE (save_regno);
27241 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27244 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27245 if (!TARGET_SINGLE_PIC_BASE
27246 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27247 && !constant_pool_empty_p ())
27248 || (DEFAULT_ABI == ABI_V4
27249 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27250 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27252 /* If emit_load_toc_table will use the link register, we need to save
27253 it. We use R12 for this purpose because emit_load_toc_table
27254 can use register 0. This allows us to use a plain 'blr' to return
27255 from the procedure more often. */
27256 int save_LR_around_toc_setup = (TARGET_ELF
27257 && DEFAULT_ABI == ABI_V4
27259 && ! info->lr_save_p
27260 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27261 if (save_LR_around_toc_setup)
27263 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27264 rtx tmp = gen_rtx_REG (Pmode, 12);
27267 insn = emit_move_insn (tmp, lr);
27268 RTX_FRAME_RELATED_P (insn) = 1;
27270 rs6000_emit_load_toc_table (TRUE);
27272 insn = emit_move_insn (lr, tmp);
27273 add_reg_note (insn, REG_CFA_RESTORE, lr);
27274 RTX_FRAME_RELATED_P (insn) = 1;
27277 rs6000_emit_load_toc_table (TRUE);
27281 if (!TARGET_SINGLE_PIC_BASE
27282 && DEFAULT_ABI == ABI_DARWIN
27283 && flag_pic && crtl->uses_pic_offset_table)
27285 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27286 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27288 /* Save and restore LR locally around this call (in R0). */
27289 if (!info->lr_save_p)
27290 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27292 emit_insn (gen_load_macho_picbase (src));
27294 emit_move_insn (gen_rtx_REG (Pmode,
27295 RS6000_PIC_OFFSET_TABLE_REGNUM),
27298 if (!info->lr_save_p)
27299 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27303 /* If we need to, save the TOC register after doing the stack setup.
27304 Do not emit eh frame info for this save. The unwinder wants info,
27305 conceptually attached to instructions in this function, about
27306 register values in the caller of this function. This R2 may have
27307 already been changed from the value in the caller.
27308 We don't attempt to write accurate DWARF EH frame info for R2
27309 because code emitted by gcc for a (non-pointer) function call
27310 doesn't save and restore R2. Instead, R2 is managed out-of-line
27311 by a linker generated plt call stub when the function resides in
27312 a shared library. This behavior is costly to describe in DWARF,
27313 both in terms of the size of DWARF info and the time taken in the
27314 unwinder to interpret it. R2 changes, apart from the
27315 calls_eh_return case earlier in this function, are handled by
27316 linux-unwind.h frob_update_context. */
27317 if (rs6000_save_toc_in_prologue_p ()
27318 && !cfun->machine->toc_is_wrapped_separately)
27320 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27321 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27324 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27325 if (using_split_stack && split_stack_arg_pointer_used_p ())
27326 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27329 /* Output .extern statements for the save/restore routines we use. */
27332 rs6000_output_savres_externs (FILE *file)
27334 rs6000_stack_t *info = rs6000_stack_info ();
27336 if (TARGET_DEBUG_STACK)
27337 debug_stack_info (info);
27339 /* Write .extern for any function we will call to save and restore
27341 if (info->first_fp_reg_save < 64
27346 int regno = info->first_fp_reg_save - 32;
27348 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27350 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27351 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27352 name = rs6000_savres_routine_name (regno, sel);
27353 fprintf (file, "\t.extern %s\n", name);
27355 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27357 bool lr = (info->savres_strategy
27358 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27359 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27360 name = rs6000_savres_routine_name (regno, sel);
27361 fprintf (file, "\t.extern %s\n", name);
27366 /* Write function prologue. */
27369 rs6000_output_function_prologue (FILE *file)
27371 if (!cfun->is_thunk)
27372 rs6000_output_savres_externs (file);
27374 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27375 immediately after the global entry point label. */
27376 if (rs6000_global_entry_point_needed_p ())
27378 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27380 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27382 if (TARGET_CMODEL != CMODEL_LARGE)
27384 /* In the small and medium code models, we assume the TOC is less
27385 2 GB away from the text section, so it can be computed via the
27386 following two-instruction sequence. */
27389 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27390 fprintf (file, "0:\taddis 2,12,.TOC.-");
27391 assemble_name (file, buf);
27392 fprintf (file, "@ha\n");
27393 fprintf (file, "\taddi 2,2,.TOC.-");
27394 assemble_name (file, buf);
27395 fprintf (file, "@l\n");
27399 /* In the large code model, we allow arbitrary offsets between the
27400 TOC and the text section, so we have to load the offset from
27401 memory. The data field is emitted directly before the global
27402 entry point in rs6000_elf_declare_function_name. */
27405 #ifdef HAVE_AS_ENTRY_MARKERS
27406 /* If supported by the linker, emit a marker relocation. If the
27407 total code size of the final executable or shared library
27408 happens to fit into 2 GB after all, the linker will replace
27409 this code sequence with the sequence for the small or medium
27411 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27413 fprintf (file, "\tld 2,");
27414 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27415 assemble_name (file, buf);
27416 fprintf (file, "-");
27417 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27418 assemble_name (file, buf);
27419 fprintf (file, "(12)\n");
27420 fprintf (file, "\tadd 2,2,12\n");
27423 fputs ("\t.localentry\t", file);
27424 assemble_name (file, name);
27425 fputs (",.-", file);
27426 assemble_name (file, name);
27427 fputs ("\n", file);
27430 /* Output -mprofile-kernel code. This needs to be done here instead of
27431 in output_function_profile since it must go after the ELFv2 ABI
27432 local entry point. */
27433 if (TARGET_PROFILE_KERNEL && crtl->profile)
27435 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27436 gcc_assert (!TARGET_32BIT);
27438 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27440 /* In the ELFv2 ABI we have no compiler stack word. It must be
27441 the resposibility of _mcount to preserve the static chain
27442 register if required. */
27443 if (DEFAULT_ABI != ABI_ELFv2
27444 && cfun->static_chain_decl != NULL)
27446 asm_fprintf (file, "\tstd %s,24(%s)\n",
27447 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27448 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27449 asm_fprintf (file, "\tld %s,24(%s)\n",
27450 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27453 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27456 rs6000_pic_labelno++;
27459 /* -mprofile-kernel code calls mcount before the function prolog,
27460 so a profiled leaf function should stay a leaf function. */
27462 rs6000_keep_leaf_when_profiled ()
27464 return TARGET_PROFILE_KERNEL;
27467 /* Non-zero if vmx regs are restored before the frame pop, zero if
27468 we restore after the pop when possible. */
27469 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27471 /* Restoring cr is a two step process: loading a reg from the frame
27472 save, then moving the reg to cr. For ABI_V4 we must let the
27473 unwinder know that the stack location is no longer valid at or
27474 before the stack deallocation, but we can't emit a cfa_restore for
27475 cr at the stack deallocation like we do for other registers.
27476 The trouble is that it is possible for the move to cr to be
27477 scheduled after the stack deallocation. So say exactly where cr
27478 is located on each of the two insns. */
27481 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27483 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27484 rtx reg = gen_rtx_REG (SImode, regno);
27485 rtx_insn *insn = emit_move_insn (reg, mem);
27487 if (!exit_func && DEFAULT_ABI == ABI_V4)
27489 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27490 rtx set = gen_rtx_SET (reg, cr);
27492 add_reg_note (insn, REG_CFA_REGISTER, set);
27493 RTX_FRAME_RELATED_P (insn) = 1;
27498 /* Reload CR from REG. */
27501 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
27506 if (using_mfcr_multiple)
27508 for (i = 0; i < 8; i++)
27509 if (save_reg_p (CR0_REGNO + i))
27511 gcc_assert (count);
27514 if (using_mfcr_multiple && count > 1)
27520 p = rtvec_alloc (count);
27523 for (i = 0; i < 8; i++)
27524 if (save_reg_p (CR0_REGNO + i))
27526 rtvec r = rtvec_alloc (2);
27527 RTVEC_ELT (r, 0) = reg;
27528 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27529 RTVEC_ELT (p, ndx) =
27530 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27531 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27534 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27535 gcc_assert (ndx == count);
27537 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27538 CR field separately. */
27539 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27541 for (i = 0; i < 8; i++)
27542 if (save_reg_p (CR0_REGNO + i))
27543 add_reg_note (insn, REG_CFA_RESTORE,
27544 gen_rtx_REG (SImode, CR0_REGNO + i));
27546 RTX_FRAME_RELATED_P (insn) = 1;
27550 for (i = 0; i < 8; i++)
27551 if (save_reg_p (CR0_REGNO + i))
27553 rtx insn = emit_insn (gen_movsi_to_cr_one
27554 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27556 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27557 CR field separately, attached to the insn that in fact
27558 restores this particular CR field. */
27559 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27561 add_reg_note (insn, REG_CFA_RESTORE,
27562 gen_rtx_REG (SImode, CR0_REGNO + i));
27564 RTX_FRAME_RELATED_P (insn) = 1;
27568 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27569 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27570 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27572 rtx_insn *insn = get_last_insn ();
27573 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27575 add_reg_note (insn, REG_CFA_RESTORE, cr);
27576 RTX_FRAME_RELATED_P (insn) = 1;
27580 /* Like cr, the move to lr instruction can be scheduled after the
27581 stack deallocation, but unlike cr, its stack frame save is still
27582 valid. So we only need to emit the cfa_restore on the correct
27586 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27588 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27589 rtx reg = gen_rtx_REG (Pmode, regno);
27591 emit_move_insn (reg, mem);
27595 restore_saved_lr (int regno, bool exit_func)
27597 rtx reg = gen_rtx_REG (Pmode, regno);
27598 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27599 rtx_insn *insn = emit_move_insn (lr, reg);
27601 if (!exit_func && flag_shrink_wrap)
27603 add_reg_note (insn, REG_CFA_RESTORE, lr);
27604 RTX_FRAME_RELATED_P (insn) = 1;
27609 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27611 if (DEFAULT_ABI == ABI_ELFv2)
27614 for (i = 0; i < 8; i++)
27615 if (save_reg_p (CR0_REGNO + i))
27617 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27618 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27622 else if (info->cr_save_p)
27623 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27624 gen_rtx_REG (SImode, CR2_REGNO),
27627 if (info->lr_save_p)
27628 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27629 gen_rtx_REG (Pmode, LR_REGNO),
27631 return cfa_restores;
27634 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27635 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27636 below stack pointer not cloberred by signals. */
27639 offset_below_red_zone_p (HOST_WIDE_INT offset)
27641 return offset < (DEFAULT_ABI == ABI_V4
27643 : TARGET_32BIT ? -220 : -288);
27646 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27649 emit_cfa_restores (rtx cfa_restores)
27651 rtx_insn *insn = get_last_insn ();
27652 rtx *loc = ®_NOTES (insn);
27655 loc = &XEXP (*loc, 1);
27656 *loc = cfa_restores;
27657 RTX_FRAME_RELATED_P (insn) = 1;
27660 /* Emit function epilogue as insns. */
27663 rs6000_emit_epilogue (int sibcall)
27665 rs6000_stack_t *info;
27666 int restoring_GPRs_inline;
27667 int restoring_FPRs_inline;
27668 int using_load_multiple;
27669 int using_mtcr_multiple;
27670 int use_backchain_to_restore_sp;
27673 HOST_WIDE_INT frame_off = 0;
27674 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27675 rtx frame_reg_rtx = sp_reg_rtx;
27676 rtx cfa_restores = NULL_RTX;
27678 rtx cr_save_reg = NULL_RTX;
27679 machine_mode reg_mode = Pmode;
27680 int reg_size = TARGET_32BIT ? 4 : 8;
27681 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27682 int fp_reg_size = 8;
27685 unsigned ptr_regno;
27687 info = rs6000_stack_info ();
27689 strategy = info->savres_strategy;
27690 using_load_multiple = strategy & REST_MULTIPLE;
27691 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
27692 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
27693 using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
27694 || rs6000_tune == PROCESSOR_PPC603
27695 || rs6000_tune == PROCESSOR_PPC750
27697 /* Restore via the backchain when we have a large frame, since this
27698 is more efficient than an addis, addi pair. The second condition
27699 here will not trigger at the moment; We don't actually need a
27700 frame pointer for alloca, but the generic parts of the compiler
27701 give us one anyway. */
27702 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
27703 ? info->lr_save_offset
27705 || (cfun->calls_alloca
27706 && !frame_pointer_needed));
27707 restore_lr = (info->lr_save_p
27708 && (restoring_FPRs_inline
27709 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
27710 && (restoring_GPRs_inline
27711 || info->first_fp_reg_save < 64)
27712 && !cfun->machine->lr_is_wrapped_separately);
27715 if (WORLD_SAVE_P (info))
27719 const char *alloc_rname;
27722 /* eh_rest_world_r10 will return to the location saved in the LR
27723 stack slot (which is not likely to be our caller.)
27724 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27725 rest_world is similar, except any R10 parameter is ignored.
27726 The exception-handling stuff that was here in 2.95 is no
27727 longer necessary. */
27730 + 32 - info->first_gp_reg_save
27731 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
27732 + 63 + 1 - info->first_fp_reg_save);
27734 strcpy (rname, ((crtl->calls_eh_return) ?
27735 "*eh_rest_world_r10" : "*rest_world"));
27736 alloc_rname = ggc_strdup (rname);
27739 RTVEC_ELT (p, j++) = ret_rtx;
27741 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
27742 /* The instruction pattern requires a clobber here;
27743 it is shared with the restVEC helper. */
27745 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
27748 /* CR register traditionally saved as CR2. */
27749 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
27751 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
27752 if (flag_shrink_wrap)
27754 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27755 gen_rtx_REG (Pmode, LR_REGNO),
27757 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27761 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27763 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
27765 = gen_frame_load (reg,
27766 frame_reg_rtx, info->gp_save_offset + reg_size * i);
27767 if (flag_shrink_wrap
27768 && save_reg_p (info->first_gp_reg_save + i))
27769 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27771 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27773 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
27775 = gen_frame_load (reg,
27776 frame_reg_rtx, info->altivec_save_offset + 16 * i);
27777 if (flag_shrink_wrap
27778 && save_reg_p (info->first_altivec_reg_save + i))
27779 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27781 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
27783 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
27784 info->first_fp_reg_save + i);
27786 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
27787 if (flag_shrink_wrap
27788 && save_reg_p (info->first_fp_reg_save + i))
27789 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27792 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
27794 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
27796 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
27798 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
27800 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
27801 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
27803 if (flag_shrink_wrap)
27805 REG_NOTES (insn) = cfa_restores;
27806 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27807 RTX_FRAME_RELATED_P (insn) = 1;
27812 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
27814 frame_off = info->total_size;
27816 /* Restore AltiVec registers if we must do so before adjusting the
27818 if (info->altivec_size != 0
27819 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27820 || (DEFAULT_ABI != ABI_V4
27821 && offset_below_red_zone_p (info->altivec_save_offset))))
27824 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27826 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27827 if (use_backchain_to_restore_sp)
27829 int frame_regno = 11;
27831 if ((strategy & REST_INLINE_VRS) == 0)
27833 /* Of r11 and r12, select the one not clobbered by an
27834 out-of-line restore function for the frame register. */
27835 frame_regno = 11 + 12 - scratch_regno;
27837 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
27838 emit_move_insn (frame_reg_rtx,
27839 gen_rtx_MEM (Pmode, sp_reg_rtx));
27842 else if (frame_pointer_needed)
27843 frame_reg_rtx = hard_frame_pointer_rtx;
27845 if ((strategy & REST_INLINE_VRS) == 0)
27847 int end_save = info->altivec_save_offset + info->altivec_size;
27849 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27850 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27852 if (end_save + frame_off != 0)
27854 rtx offset = GEN_INT (end_save + frame_off);
27856 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27859 emit_move_insn (ptr_reg, frame_reg_rtx);
27861 ptr_off = -end_save;
27862 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27863 info->altivec_save_offset + ptr_off,
27864 0, V4SImode, SAVRES_VR);
27868 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27869 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27871 rtx addr, areg, mem, insn;
27872 rtx reg = gen_rtx_REG (V4SImode, i);
27873 HOST_WIDE_INT offset
27874 = (info->altivec_save_offset + frame_off
27875 + 16 * (i - info->first_altivec_reg_save));
27877 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27879 mem = gen_frame_mem (V4SImode,
27880 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27881 GEN_INT (offset)));
27882 insn = gen_rtx_SET (reg, mem);
27886 areg = gen_rtx_REG (Pmode, 0);
27887 emit_move_insn (areg, GEN_INT (offset));
27889 /* AltiVec addressing mode is [reg+reg]. */
27890 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
27891 mem = gen_frame_mem (V4SImode, addr);
27893 /* Rather than emitting a generic move, force use of the
27894 lvx instruction, which we always want. In particular we
27895 don't want lxvd2x/xxpermdi for little endian. */
27896 insn = gen_altivec_lvx_v4si_internal (reg, mem);
27899 (void) emit_insn (insn);
27903 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27904 if (((strategy & REST_INLINE_VRS) == 0
27905 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
27906 && (flag_shrink_wrap
27907 || (offset_below_red_zone_p
27908 (info->altivec_save_offset
27909 + 16 * (i - info->first_altivec_reg_save))))
27912 rtx reg = gen_rtx_REG (V4SImode, i);
27913 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27917 /* Restore VRSAVE if we must do so before adjusting the stack. */
27918 if (info->vrsave_size != 0
27919 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27920 || (DEFAULT_ABI != ABI_V4
27921 && offset_below_red_zone_p (info->vrsave_save_offset))))
27925 if (frame_reg_rtx == sp_reg_rtx)
27927 if (use_backchain_to_restore_sp)
27929 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27930 emit_move_insn (frame_reg_rtx,
27931 gen_rtx_MEM (Pmode, sp_reg_rtx));
27934 else if (frame_pointer_needed)
27935 frame_reg_rtx = hard_frame_pointer_rtx;
27938 reg = gen_rtx_REG (SImode, 12);
27939 emit_insn (gen_frame_load (reg, frame_reg_rtx,
27940 info->vrsave_save_offset + frame_off));
27942 emit_insn (generate_set_vrsave (reg, info, 1));
27946 /* If we have a large stack frame, restore the old stack pointer
27947 using the backchain. */
27948 if (use_backchain_to_restore_sp)
27950 if (frame_reg_rtx == sp_reg_rtx)
27952 /* Under V.4, don't reset the stack pointer until after we're done
27953 loading the saved registers. */
27954 if (DEFAULT_ABI == ABI_V4)
27955 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27957 insn = emit_move_insn (frame_reg_rtx,
27958 gen_rtx_MEM (Pmode, sp_reg_rtx));
27961 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27962 && DEFAULT_ABI == ABI_V4)
27963 /* frame_reg_rtx has been set up by the altivec restore. */
27967 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
27968 frame_reg_rtx = sp_reg_rtx;
27971 /* If we have a frame pointer, we can restore the old stack pointer
27973 else if (frame_pointer_needed)
27975 frame_reg_rtx = sp_reg_rtx;
27976 if (DEFAULT_ABI == ABI_V4)
27977 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
27978 /* Prevent reordering memory accesses against stack pointer restore. */
27979 else if (cfun->calls_alloca
27980 || offset_below_red_zone_p (-info->total_size))
27981 rs6000_emit_stack_tie (frame_reg_rtx, true);
27983 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
27984 GEN_INT (info->total_size)));
27987 else if (info->push_p
27988 && DEFAULT_ABI != ABI_V4
27989 && !crtl->calls_eh_return)
27991 /* Prevent reordering memory accesses against stack pointer restore. */
27992 if (cfun->calls_alloca
27993 || offset_below_red_zone_p (-info->total_size))
27994 rs6000_emit_stack_tie (frame_reg_rtx, false);
27995 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
27996 GEN_INT (info->total_size)));
27999 if (insn && frame_reg_rtx == sp_reg_rtx)
28003 REG_NOTES (insn) = cfa_restores;
28004 cfa_restores = NULL_RTX;
28006 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28007 RTX_FRAME_RELATED_P (insn) = 1;
28010 /* Restore AltiVec registers if we have not done so already. */
28011 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28012 && info->altivec_size != 0
28013 && (DEFAULT_ABI == ABI_V4
28014 || !offset_below_red_zone_p (info->altivec_save_offset)))
28018 if ((strategy & REST_INLINE_VRS) == 0)
28020 int end_save = info->altivec_save_offset + info->altivec_size;
28022 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28023 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28024 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28026 if (end_save + frame_off != 0)
28028 rtx offset = GEN_INT (end_save + frame_off);
28030 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28033 emit_move_insn (ptr_reg, frame_reg_rtx);
28035 ptr_off = -end_save;
28036 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28037 info->altivec_save_offset + ptr_off,
28038 0, V4SImode, SAVRES_VR);
28039 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28041 /* Frame reg was clobbered by out-of-line save. Restore it
28042 from ptr_reg, and if we are calling out-of-line gpr or
28043 fpr restore set up the correct pointer and offset. */
28044 unsigned newptr_regno = 1;
28045 if (!restoring_GPRs_inline)
28047 bool lr = info->gp_save_offset + info->gp_size == 0;
28048 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28049 newptr_regno = ptr_regno_for_savres (sel);
28050 end_save = info->gp_save_offset + info->gp_size;
28052 else if (!restoring_FPRs_inline)
28054 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28055 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28056 newptr_regno = ptr_regno_for_savres (sel);
28057 end_save = info->fp_save_offset + info->fp_size;
28060 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28061 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28063 if (end_save + ptr_off != 0)
28065 rtx offset = GEN_INT (end_save + ptr_off);
28067 frame_off = -end_save;
28069 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28072 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28077 frame_off = ptr_off;
28078 emit_move_insn (frame_reg_rtx, ptr_reg);
28084 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28085 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28087 rtx addr, areg, mem, insn;
28088 rtx reg = gen_rtx_REG (V4SImode, i);
28089 HOST_WIDE_INT offset
28090 = (info->altivec_save_offset + frame_off
28091 + 16 * (i - info->first_altivec_reg_save));
28093 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28095 mem = gen_frame_mem (V4SImode,
28096 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28097 GEN_INT (offset)));
28098 insn = gen_rtx_SET (reg, mem);
28102 areg = gen_rtx_REG (Pmode, 0);
28103 emit_move_insn (areg, GEN_INT (offset));
28105 /* AltiVec addressing mode is [reg+reg]. */
28106 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28107 mem = gen_frame_mem (V4SImode, addr);
28109 /* Rather than emitting a generic move, force use of the
28110 lvx instruction, which we always want. In particular we
28111 don't want lxvd2x/xxpermdi for little endian. */
28112 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28115 (void) emit_insn (insn);
28119 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28120 if (((strategy & REST_INLINE_VRS) == 0
28121 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28122 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28125 rtx reg = gen_rtx_REG (V4SImode, i);
28126 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28130 /* Restore VRSAVE if we have not done so already. */
28131 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28132 && info->vrsave_size != 0
28133 && (DEFAULT_ABI == ABI_V4
28134 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28138 reg = gen_rtx_REG (SImode, 12);
28139 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28140 info->vrsave_save_offset + frame_off));
28142 emit_insn (generate_set_vrsave (reg, info, 1));
28145 /* If we exit by an out-of-line restore function on ABI_V4 then that
28146 function will deallocate the stack, so we don't need to worry
28147 about the unwinder restoring cr from an invalid stack frame
28149 exit_func = (!restoring_FPRs_inline
28150 || (!restoring_GPRs_inline
28151 && info->first_fp_reg_save == 64));
28153 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28154 *separate* slots if the routine calls __builtin_eh_return, so
28155 that they can be independently restored by the unwinder. */
28156 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28158 int i, cr_off = info->ehcr_offset;
28160 for (i = 0; i < 8; i++)
28161 if (!call_used_regs[CR0_REGNO + i])
28163 rtx reg = gen_rtx_REG (SImode, 0);
28164 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28165 cr_off + frame_off));
28167 insn = emit_insn (gen_movsi_to_cr_one
28168 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28170 if (!exit_func && flag_shrink_wrap)
28172 add_reg_note (insn, REG_CFA_RESTORE,
28173 gen_rtx_REG (SImode, CR0_REGNO + i));
28175 RTX_FRAME_RELATED_P (insn) = 1;
28178 cr_off += reg_size;
28182 /* Get the old lr if we saved it. If we are restoring registers
28183 out-of-line, then the out-of-line routines can do this for us. */
28184 if (restore_lr && restoring_GPRs_inline)
28185 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28187 /* Get the old cr if we saved it. */
28188 if (info->cr_save_p)
28190 unsigned cr_save_regno = 12;
28192 if (!restoring_GPRs_inline)
28194 /* Ensure we don't use the register used by the out-of-line
28195 gpr register restore below. */
28196 bool lr = info->gp_save_offset + info->gp_size == 0;
28197 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28198 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28200 if (gpr_ptr_regno == 12)
28201 cr_save_regno = 11;
28202 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28204 else if (REGNO (frame_reg_rtx) == 12)
28205 cr_save_regno = 11;
28207 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28208 info->cr_save_offset + frame_off,
28212 /* Set LR here to try to overlap restores below. */
28213 if (restore_lr && restoring_GPRs_inline)
28214 restore_saved_lr (0, exit_func);
28216 /* Load exception handler data registers, if needed. */
28217 if (crtl->calls_eh_return)
28219 unsigned int i, regno;
28223 rtx reg = gen_rtx_REG (reg_mode, 2);
28224 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28225 frame_off + RS6000_TOC_SAVE_SLOT));
28232 regno = EH_RETURN_DATA_REGNO (i);
28233 if (regno == INVALID_REGNUM)
28236 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28237 info->ehrd_offset + frame_off
28238 + reg_size * (int) i);
28240 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28244 /* Restore GPRs. This is done as a PARALLEL if we are using
28245 the load-multiple instructions. */
28246 if (!restoring_GPRs_inline)
28248 /* We are jumping to an out-of-line function. */
28250 int end_save = info->gp_save_offset + info->gp_size;
28251 bool can_use_exit = end_save == 0;
28252 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28255 /* Emit stack reset code if we need it. */
28256 ptr_regno = ptr_regno_for_savres (sel);
28257 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28259 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28260 else if (end_save + frame_off != 0)
28261 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28262 GEN_INT (end_save + frame_off)));
28263 else if (REGNO (frame_reg_rtx) != ptr_regno)
28264 emit_move_insn (ptr_reg, frame_reg_rtx);
28265 if (REGNO (frame_reg_rtx) == ptr_regno)
28266 frame_off = -end_save;
28268 if (can_use_exit && info->cr_save_p)
28269 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28271 ptr_off = -end_save;
28272 rs6000_emit_savres_rtx (info, ptr_reg,
28273 info->gp_save_offset + ptr_off,
28274 info->lr_save_offset + ptr_off,
28277 else if (using_load_multiple)
28280 p = rtvec_alloc (32 - info->first_gp_reg_save);
28281 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28283 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28285 info->gp_save_offset + frame_off + reg_size * i);
28286 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28290 int offset = info->gp_save_offset + frame_off;
28291 for (i = info->first_gp_reg_save; i < 32; i++)
28294 && !cfun->machine->gpr_is_wrapped_separately[i])
28296 rtx reg = gen_rtx_REG (reg_mode, i);
28297 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28300 offset += reg_size;
28304 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28306 /* If the frame pointer was used then we can't delay emitting
28307 a REG_CFA_DEF_CFA note. This must happen on the insn that
28308 restores the frame pointer, r31. We may have already emitted
28309 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28310 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28311 be harmless if emitted. */
28312 if (frame_pointer_needed)
28314 insn = get_last_insn ();
28315 add_reg_note (insn, REG_CFA_DEF_CFA,
28316 plus_constant (Pmode, frame_reg_rtx, frame_off));
28317 RTX_FRAME_RELATED_P (insn) = 1;
28320 /* Set up cfa_restores. We always need these when
28321 shrink-wrapping. If not shrink-wrapping then we only need
28322 the cfa_restore when the stack location is no longer valid.
28323 The cfa_restores must be emitted on or before the insn that
28324 invalidates the stack, and of course must not be emitted
28325 before the insn that actually does the restore. The latter
28326 is why it is a bad idea to emit the cfa_restores as a group
28327 on the last instruction here that actually does a restore:
28328 That insn may be reordered with respect to others doing
28330 if (flag_shrink_wrap
28331 && !restoring_GPRs_inline
28332 && info->first_fp_reg_save == 64)
28333 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28335 for (i = info->first_gp_reg_save; i < 32; i++)
28337 && !cfun->machine->gpr_is_wrapped_separately[i])
28339 rtx reg = gen_rtx_REG (reg_mode, i);
28340 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28344 if (!restoring_GPRs_inline
28345 && info->first_fp_reg_save == 64)
28347 /* We are jumping to an out-of-line function. */
28349 emit_cfa_restores (cfa_restores);
28353 if (restore_lr && !restoring_GPRs_inline)
28355 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28356 restore_saved_lr (0, exit_func);
28359 /* Restore fpr's if we need to do it without calling a function. */
28360 if (restoring_FPRs_inline)
28362 int offset = info->fp_save_offset + frame_off;
28363 for (i = info->first_fp_reg_save; i < 64; i++)
28366 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28368 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28369 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28370 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28371 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28375 offset += fp_reg_size;
28379 /* If we saved cr, restore it here. Just those that were used. */
28380 if (info->cr_save_p)
28381 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28383 /* If this is V.4, unwind the stack pointer after all of the loads
28384 have been done, or set up r11 if we are restoring fp out of line. */
28386 if (!restoring_FPRs_inline)
28388 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28389 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28390 ptr_regno = ptr_regno_for_savres (sel);
28393 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28394 if (REGNO (frame_reg_rtx) == ptr_regno)
28397 if (insn && restoring_FPRs_inline)
28401 REG_NOTES (insn) = cfa_restores;
28402 cfa_restores = NULL_RTX;
28404 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28405 RTX_FRAME_RELATED_P (insn) = 1;
28408 if (crtl->calls_eh_return)
28410 rtx sa = EH_RETURN_STACKADJ_RTX;
28411 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28414 if (!sibcall && restoring_FPRs_inline)
28418 /* We can't hang the cfa_restores off a simple return,
28419 since the shrink-wrap code sometimes uses an existing
28420 return. This means there might be a path from
28421 pre-prologue code to this return, and dwarf2cfi code
28422 wants the eh_frame unwinder state to be the same on
28423 all paths to any point. So we need to emit the
28424 cfa_restores before the return. For -m64 we really
28425 don't need epilogue cfa_restores at all, except for
28426 this irritating dwarf2cfi with shrink-wrap
28427 requirement; The stack red-zone means eh_frame info
28428 from the prologue telling the unwinder to restore
28429 from the stack is perfectly good right to the end of
28431 emit_insn (gen_blockage ());
28432 emit_cfa_restores (cfa_restores);
28433 cfa_restores = NULL_RTX;
28436 emit_jump_insn (targetm.gen_simple_return ());
28439 if (!sibcall && !restoring_FPRs_inline)
28441 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28442 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28444 RTVEC_ELT (p, elt++) = ret_rtx;
28446 RTVEC_ELT (p, elt++)
28447 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
28449 /* We have to restore more than two FP registers, so branch to the
28450 restore function. It will return to our caller. */
28455 if (flag_shrink_wrap)
28456 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28458 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28459 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28460 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28461 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28463 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28465 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28467 RTVEC_ELT (p, elt++)
28468 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28469 if (flag_shrink_wrap
28470 && save_reg_p (info->first_fp_reg_save + i))
28471 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28474 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28480 /* Ensure the cfa_restores are hung off an insn that won't
28481 be reordered above other restores. */
28482 emit_insn (gen_blockage ());
28484 emit_cfa_restores (cfa_restores);
28488 /* Write function epilogue. */
28491 rs6000_output_function_epilogue (FILE *file)
28494 macho_branch_islands ();
28497 rtx_insn *insn = get_last_insn ();
28498 rtx_insn *deleted_debug_label = NULL;
28500 /* Mach-O doesn't support labels at the end of objects, so if
28501 it looks like we might want one, take special action.
28503 First, collect any sequence of deleted debug labels. */
28506 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28508 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28509 notes only, instead set their CODE_LABEL_NUMBER to -1,
28510 otherwise there would be code generation differences
28511 in between -g and -g0. */
28512 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28513 deleted_debug_label = insn;
28514 insn = PREV_INSN (insn);
28517 /* Second, if we have:
28520 then this needs to be detected, so skip past the barrier. */
28522 if (insn && BARRIER_P (insn))
28523 insn = PREV_INSN (insn);
28525 /* Up to now we've only seen notes or barriers. */
28530 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28531 /* Trailing label: <barrier>. */
28532 fputs ("\tnop\n", file);
28535 /* Lastly, see if we have a completely empty function body. */
28536 while (insn && ! INSN_P (insn))
28537 insn = PREV_INSN (insn);
28538 /* If we don't find any insns, we've got an empty function body;
28539 I.e. completely empty - without a return or branch. This is
28540 taken as the case where a function body has been removed
28541 because it contains an inline __builtin_unreachable(). GCC
28542 states that reaching __builtin_unreachable() means UB so we're
28543 not obliged to do anything special; however, we want
28544 non-zero-sized function bodies. To meet this, and help the
28545 user out, let's trap the case. */
28547 fputs ("\ttrap\n", file);
28550 else if (deleted_debug_label)
28551 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28552 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28553 CODE_LABEL_NUMBER (insn) = -1;
28557 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28560 We don't output a traceback table if -finhibit-size-directive was
28561 used. The documentation for -finhibit-size-directive reads
28562 ``don't output a @code{.size} assembler directive, or anything
28563 else that would cause trouble if the function is split in the
28564 middle, and the two halves are placed at locations far apart in
28565 memory.'' The traceback table has this property, since it
28566 includes the offset from the start of the function to the
28567 traceback table itself.
28569 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28570 different traceback table. */
28571 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28572 && ! flag_inhibit_size_directive
28573 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28575 const char *fname = NULL;
28576 const char *language_string = lang_hooks.name;
28577 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28579 int optional_tbtab;
28580 rs6000_stack_t *info = rs6000_stack_info ();
28582 if (rs6000_traceback == traceback_full)
28583 optional_tbtab = 1;
28584 else if (rs6000_traceback == traceback_part)
28585 optional_tbtab = 0;
28587 optional_tbtab = !optimize_size && !TARGET_ELF;
28589 if (optional_tbtab)
28591 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28592 while (*fname == '.') /* V.4 encodes . in the name */
28595 /* Need label immediately before tbtab, so we can compute
28596 its offset from the function start. */
28597 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28598 ASM_OUTPUT_LABEL (file, fname);
28601 /* The .tbtab pseudo-op can only be used for the first eight
28602 expressions, since it can't handle the possibly variable
28603 length fields that follow. However, if you omit the optional
28604 fields, the assembler outputs zeros for all optional fields
28605 anyways, giving each variable length field is minimum length
28606 (as defined in sys/debug.h). Thus we can not use the .tbtab
28607 pseudo-op at all. */
28609 /* An all-zero word flags the start of the tbtab, for debuggers
28610 that have to find it by searching forward from the entry
28611 point or from the current pc. */
28612 fputs ("\t.long 0\n", file);
28614 /* Tbtab format type. Use format type 0. */
28615 fputs ("\t.byte 0,", file);
28617 /* Language type. Unfortunately, there does not seem to be any
28618 official way to discover the language being compiled, so we
28619 use language_string.
28620 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28621 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28622 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28623 numbers either, so for now use 0. */
28625 || ! strcmp (language_string, "GNU GIMPLE")
28626 || ! strcmp (language_string, "GNU Go")
28627 || ! strcmp (language_string, "GNU D")
28628 || ! strcmp (language_string, "libgccjit"))
28630 else if (! strcmp (language_string, "GNU F77")
28631 || lang_GNU_Fortran ())
28633 else if (! strcmp (language_string, "GNU Ada"))
28635 else if (lang_GNU_CXX ()
28636 || ! strcmp (language_string, "GNU Objective-C++"))
28638 else if (! strcmp (language_string, "GNU Java"))
28640 else if (! strcmp (language_string, "GNU Objective-C"))
28643 gcc_unreachable ();
28644 fprintf (file, "%d,", i);
28646 /* 8 single bit fields: global linkage (not set for C extern linkage,
28647 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28648 from start of procedure stored in tbtab, internal function, function
28649 has controlled storage, function has no toc, function uses fp,
28650 function logs/aborts fp operations. */
28651 /* Assume that fp operations are used if any fp reg must be saved. */
28652 fprintf (file, "%d,",
28653 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28655 /* 6 bitfields: function is interrupt handler, name present in
28656 proc table, function calls alloca, on condition directives
28657 (controls stack walks, 3 bits), saves condition reg, saves
28659 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28660 set up as a frame pointer, even when there is no alloca call. */
28661 fprintf (file, "%d,",
28662 ((optional_tbtab << 6)
28663 | ((optional_tbtab & frame_pointer_needed) << 5)
28664 | (info->cr_save_p << 1)
28665 | (info->lr_save_p)));
28667 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28669 fprintf (file, "%d,",
28670 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28672 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28673 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28675 if (optional_tbtab)
28677 /* Compute the parameter info from the function decl argument
28680 int next_parm_info_bit = 31;
28682 for (decl = DECL_ARGUMENTS (current_function_decl);
28683 decl; decl = DECL_CHAIN (decl))
28685 rtx parameter = DECL_INCOMING_RTL (decl);
28686 machine_mode mode = GET_MODE (parameter);
28688 if (GET_CODE (parameter) == REG)
28690 if (SCALAR_FLOAT_MODE_P (mode))
28713 gcc_unreachable ();
28716 /* If only one bit will fit, don't or in this entry. */
28717 if (next_parm_info_bit > 0)
28718 parm_info |= (bits << (next_parm_info_bit - 1));
28719 next_parm_info_bit -= 2;
28723 fixed_parms += ((GET_MODE_SIZE (mode)
28724 + (UNITS_PER_WORD - 1))
28726 next_parm_info_bit -= 1;
28732 /* Number of fixed point parameters. */
28733 /* This is actually the number of words of fixed point parameters; thus
28734 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28735 fprintf (file, "%d,", fixed_parms);
28737 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28739 /* This is actually the number of fp registers that hold parameters;
28740 and thus the maximum value is 13. */
28741 /* Set parameters on stack bit if parameters are not in their original
28742 registers, regardless of whether they are on the stack? Xlc
28743 seems to set the bit when not optimizing. */
28744 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
28746 if (optional_tbtab)
28748 /* Optional fields follow. Some are variable length. */
28750 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28751 float, 11 double float. */
28752 /* There is an entry for each parameter in a register, in the order
28753 that they occur in the parameter list. Any intervening arguments
28754 on the stack are ignored. If the list overflows a long (max
28755 possible length 34 bits) then completely leave off all elements
28757 /* Only emit this long if there was at least one parameter. */
28758 if (fixed_parms || float_parms)
28759 fprintf (file, "\t.long %d\n", parm_info);
28761 /* Offset from start of code to tb table. */
28762 fputs ("\t.long ", file);
28763 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28764 RS6000_OUTPUT_BASENAME (file, fname);
28766 rs6000_output_function_entry (file, fname);
28769 /* Interrupt handler mask. */
28770 /* Omit this long, since we never set the interrupt handler bit
28773 /* Number of CTL (controlled storage) anchors. */
28774 /* Omit this long, since the has_ctl bit is never set above. */
28776 /* Displacement into stack of each CTL anchor. */
28777 /* Omit this list of longs, because there are no CTL anchors. */
28779 /* Length of function name. */
28782 fprintf (file, "\t.short %d\n", (int) strlen (fname));
28784 /* Function name. */
28785 assemble_string (fname, strlen (fname));
28787 /* Register for alloca automatic storage; this is always reg 31.
28788 Only emit this if the alloca bit was set above. */
28789 if (frame_pointer_needed)
28790 fputs ("\t.byte 31\n", file);
28792 fputs ("\t.align 2\n", file);
28796 /* Arrange to define .LCTOC1 label, if not already done. */
28800 if (!toc_initialized)
28802 switch_to_section (toc_section);
28803 switch_to_section (current_function_section ());
28808 /* -fsplit-stack support. */
28810 /* A SYMBOL_REF for __morestack. */
28811 static GTY(()) rtx morestack_ref;
28814 gen_add3_const (rtx rt, rtx ra, long c)
28817 return gen_adddi3 (rt, ra, GEN_INT (c));
28819 return gen_addsi3 (rt, ra, GEN_INT (c));
28822 /* Emit -fsplit-stack prologue, which goes before the regular function
28823 prologue (at local entry point in the case of ELFv2). */
28826 rs6000_expand_split_stack_prologue (void)
28828 rs6000_stack_t *info = rs6000_stack_info ();
28829 unsigned HOST_WIDE_INT allocate;
28830 long alloc_hi, alloc_lo;
28831 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
28834 gcc_assert (flag_split_stack && reload_completed);
28839 if (global_regs[29])
28841 error ("%qs uses register r29", "-fsplit-stack");
28842 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
28843 "conflicts with %qD", global_regs_decl[29]);
28846 allocate = info->total_size;
28847 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
28849 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
28852 if (morestack_ref == NULL_RTX)
28854 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
28855 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
28856 | SYMBOL_FLAG_FUNCTION);
28859 r0 = gen_rtx_REG (Pmode, 0);
28860 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28861 r12 = gen_rtx_REG (Pmode, 12);
28862 emit_insn (gen_load_split_stack_limit (r0));
28863 /* Always emit two insns here to calculate the requested stack,
28864 so that the linker can edit them when adjusting size for calling
28865 non-split-stack code. */
28866 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
28867 alloc_lo = -allocate - alloc_hi;
28870 emit_insn (gen_add3_const (r12, r1, alloc_hi));
28872 emit_insn (gen_add3_const (r12, r12, alloc_lo));
28874 emit_insn (gen_nop ());
28878 emit_insn (gen_add3_const (r12, r1, alloc_lo));
28879 emit_insn (gen_nop ());
28882 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
28883 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
28884 ok_label = gen_label_rtx ();
28885 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
28886 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
28887 gen_rtx_LABEL_REF (VOIDmode, ok_label),
28889 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
28890 JUMP_LABEL (insn) = ok_label;
28891 /* Mark the jump as very likely to be taken. */
28892 add_reg_br_prob_note (insn, profile_probability::very_likely ());
28894 lr = gen_rtx_REG (Pmode, LR_REGNO);
28895 insn = emit_move_insn (r0, lr);
28896 RTX_FRAME_RELATED_P (insn) = 1;
28897 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
28898 RTX_FRAME_RELATED_P (insn) = 1;
28900 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
28901 const0_rtx, const0_rtx));
28902 call_fusage = NULL_RTX;
28903 use_reg (&call_fusage, r12);
28904 /* Say the call uses r0, even though it doesn't, to stop regrename
28905 from twiddling with the insns saving lr, trashing args for cfun.
28906 The insns restoring lr are similarly protected by making
28907 split_stack_return use r0. */
28908 use_reg (&call_fusage, r0);
28909 add_function_usage_to (insn, call_fusage);
28910 /* Indicate that this function can't jump to non-local gotos. */
28911 make_reg_eh_region_note_nothrow_nononlocal (insn);
28912 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
28913 insn = emit_move_insn (lr, r0);
28914 add_reg_note (insn, REG_CFA_RESTORE, lr);
28915 RTX_FRAME_RELATED_P (insn) = 1;
28916 emit_insn (gen_split_stack_return ());
28918 emit_label (ok_label);
28919 LABEL_NUSES (ok_label) = 1;
28922 /* Return the internal arg pointer used for function incoming
28923 arguments. When -fsplit-stack, the arg pointer is r12 so we need
28924 to copy it to a pseudo in order for it to be preserved over calls
28925 and suchlike. We'd really like to use a pseudo here for the
28926 internal arg pointer but data-flow analysis is not prepared to
28927 accept pseudos as live at the beginning of a function. */
28930 rs6000_internal_arg_pointer (void)
28932 if (flag_split_stack
28933 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
28937 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
28941 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
28942 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
28944 /* Put the pseudo initialization right after the note at the
28945 beginning of the function. */
28946 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
28947 gen_rtx_REG (Pmode, 12));
28948 push_topmost_sequence ();
28949 emit_insn_after (pat, get_insns ());
28950 pop_topmost_sequence ();
28952 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
28953 FIRST_PARM_OFFSET (current_function_decl));
28954 return copy_to_reg (ret);
28956 return virtual_incoming_args_rtx;
28959 /* We may have to tell the dataflow pass that the split stack prologue
28960 is initializing a register. */
28963 rs6000_live_on_entry (bitmap regs)
28965 if (flag_split_stack)
28966 bitmap_set_bit (regs, 12);
28969 /* Emit -fsplit-stack dynamic stack allocation space check. */
28972 rs6000_split_stack_space_check (rtx size, rtx label)
28974 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28975 rtx limit = gen_reg_rtx (Pmode);
28976 rtx requested = gen_reg_rtx (Pmode);
28977 rtx cmp = gen_reg_rtx (CCUNSmode);
28980 emit_insn (gen_load_split_stack_limit (limit));
28981 if (CONST_INT_P (size))
28982 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
28985 size = force_reg (Pmode, size);
28986 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
28988 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
28989 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
28990 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
28991 gen_rtx_LABEL_REF (VOIDmode, label),
28993 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
28994 JUMP_LABEL (jump) = label;
28997 /* A C compound statement that outputs the assembler code for a thunk
28998 function, used to implement C++ virtual function calls with
28999 multiple inheritance. The thunk acts as a wrapper around a virtual
29000 function, adjusting the implicit object parameter before handing
29001 control off to the real function.
29003 First, emit code to add the integer DELTA to the location that
29004 contains the incoming first argument. Assume that this argument
29005 contains a pointer, and is the one used to pass the `this' pointer
29006 in C++. This is the incoming argument *before* the function
29007 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29008 values of all other incoming arguments.
29010 After the addition, emit code to jump to FUNCTION, which is a
29011 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29012 not touch the return address. Hence returning from FUNCTION will
29013 return to whoever called the current `thunk'.
29015 The effect must be as if FUNCTION had been called directly with the
29016 adjusted first argument. This macro is responsible for emitting
29017 all of the code for a thunk function; output_function_prologue()
29018 and output_function_epilogue() are not invoked.
29020 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29021 been extracted from it.) It might possibly be useful on some
29022 targets, but probably not.
29024 If you do not define this macro, the target-independent code in the
29025 C++ frontend will generate a less efficient heavyweight thunk that
29026 calls FUNCTION instead of jumping to it. The generic approach does
29027 not support varargs. */
29030 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29031 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29034 rtx this_rtx, funexp;
29037 reload_completed = 1;
29038 epilogue_completed = 1;
29040 /* Mark the end of the (empty) prologue. */
29041 emit_note (NOTE_INSN_PROLOGUE_END);
29043 /* Find the "this" pointer. If the function returns a structure,
29044 the structure return pointer is in r3. */
29045 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29046 this_rtx = gen_rtx_REG (Pmode, 4);
29048 this_rtx = gen_rtx_REG (Pmode, 3);
29050 /* Apply the constant offset, if required. */
29052 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29054 /* Apply the offset from the vtable, if required. */
29057 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29058 rtx tmp = gen_rtx_REG (Pmode, 12);
29060 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29061 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29063 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29064 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29068 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29070 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29072 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29075 /* Generate a tail call to the target function. */
29076 if (!TREE_USED (function))
29078 assemble_external (function);
29079 TREE_USED (function) = 1;
29081 funexp = XEXP (DECL_RTL (function), 0);
29082 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29085 if (MACHOPIC_INDIRECT)
29086 funexp = machopic_indirect_call_target (funexp);
29089 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29090 generate sibcall RTL explicitly. */
29091 insn = emit_call_insn (
29092 gen_rtx_PARALLEL (VOIDmode,
29094 gen_rtx_CALL (VOIDmode,
29095 funexp, const0_rtx),
29096 gen_rtx_USE (VOIDmode, const0_rtx),
29097 simple_return_rtx)));
29098 SIBLING_CALL_P (insn) = 1;
29101 /* Run just enough of rest_of_compilation to get the insns emitted.
29102 There's not really enough bulk here to make other passes such as
29103 instruction scheduling worth while. Note that use_thunk calls
29104 assemble_start_function and assemble_end_function. */
29105 insn = get_insns ();
29106 shorten_branches (insn);
29107 final_start_function (insn, file, 1);
29108 final (insn, file, 1);
29109 final_end_function ();
29111 reload_completed = 0;
29112 epilogue_completed = 0;
29115 /* A quick summary of the various types of 'constant-pool tables'
29118 Target Flags Name One table per
29119 AIX (none) AIX TOC object file
29120 AIX -mfull-toc AIX TOC object file
29121 AIX -mminimal-toc AIX minimal TOC translation unit
29122 SVR4/EABI (none) SVR4 SDATA object file
29123 SVR4/EABI -fpic SVR4 pic object file
29124 SVR4/EABI -fPIC SVR4 PIC translation unit
29125 SVR4/EABI -mrelocatable EABI TOC function
29126 SVR4/EABI -maix AIX TOC object file
29127 SVR4/EABI -maix -mminimal-toc
29128 AIX minimal TOC translation unit
29130 Name Reg. Set by entries contains:
29131 made by addrs? fp? sum?
29133 AIX TOC 2 crt0 as Y option option
29134 AIX minimal TOC 30 prolog gcc Y Y option
29135 SVR4 SDATA 13 crt0 gcc N Y N
29136 SVR4 pic 30 prolog ld Y not yet N
29137 SVR4 PIC 30 prolog gcc Y option option
29138 EABI TOC 30 prolog gcc Y option option
29142 /* Hash functions for the hash table. */
29145 rs6000_hash_constant (rtx k)
29147 enum rtx_code code = GET_CODE (k);
29148 machine_mode mode = GET_MODE (k);
29149 unsigned result = (code << 3) ^ mode;
29150 const char *format;
29153 format = GET_RTX_FORMAT (code);
29154 flen = strlen (format);
29160 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29162 case CONST_WIDE_INT:
29165 flen = CONST_WIDE_INT_NUNITS (k);
29166 for (i = 0; i < flen; i++)
29167 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29172 if (mode != VOIDmode)
29173 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29185 for (; fidx < flen; fidx++)
29186 switch (format[fidx])
29191 const char *str = XSTR (k, fidx);
29192 len = strlen (str);
29193 result = result * 613 + len;
29194 for (i = 0; i < len; i++)
29195 result = result * 613 + (unsigned) str[i];
29200 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29204 result = result * 613 + (unsigned) XINT (k, fidx);
29207 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29208 result = result * 613 + (unsigned) XWINT (k, fidx);
29212 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29213 result = result * 613 + (unsigned) (XWINT (k, fidx)
29220 gcc_unreachable ();
29227 toc_hasher::hash (toc_hash_struct *thc)
29229 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29232 /* Compare H1 and H2 for equivalence. */
29235 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29240 if (h1->key_mode != h2->key_mode)
29243 return rtx_equal_p (r1, r2);
29246 /* These are the names given by the C++ front-end to vtables, and
29247 vtable-like objects. Ideally, this logic should not be here;
29248 instead, there should be some programmatic way of inquiring as
29249 to whether or not an object is a vtable. */
29251 #define VTABLE_NAME_P(NAME) \
29252 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29253 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29254 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29255 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29256 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29258 #ifdef NO_DOLLAR_IN_LABEL
29259 /* Return a GGC-allocated character string translating dollar signs in
29260 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29263 rs6000_xcoff_strip_dollar (const char *name)
29269 q = (const char *) strchr (name, '$');
29271 if (q == 0 || q == name)
29274 len = strlen (name);
29275 strip = XALLOCAVEC (char, len + 1);
29276 strcpy (strip, name);
29277 p = strip + (q - name);
29281 p = strchr (p + 1, '$');
29284 return ggc_alloc_string (strip, len);
29289 rs6000_output_symbol_ref (FILE *file, rtx x)
29291 const char *name = XSTR (x, 0);
29293 /* Currently C++ toc references to vtables can be emitted before it
29294 is decided whether the vtable is public or private. If this is
29295 the case, then the linker will eventually complain that there is
29296 a reference to an unknown section. Thus, for vtables only,
29297 we emit the TOC reference to reference the identifier and not the
29299 if (VTABLE_NAME_P (name))
29301 RS6000_OUTPUT_BASENAME (file, name);
29304 assemble_name (file, name);
29307 /* Output a TOC entry. We derive the entry name from what is being
29311 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29314 const char *name = buf;
29316 HOST_WIDE_INT offset = 0;
29318 gcc_assert (!TARGET_NO_TOC);
29320 /* When the linker won't eliminate them, don't output duplicate
29321 TOC entries (this happens on AIX if there is any kind of TOC,
29322 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29324 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29326 struct toc_hash_struct *h;
29328 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29329 time because GGC is not initialized at that point. */
29330 if (toc_hash_table == NULL)
29331 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29333 h = ggc_alloc<toc_hash_struct> ();
29335 h->key_mode = mode;
29336 h->labelno = labelno;
29338 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29339 if (*found == NULL)
29341 else /* This is indeed a duplicate.
29342 Set this label equal to that label. */
29344 fputs ("\t.set ", file);
29345 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29346 fprintf (file, "%d,", labelno);
29347 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29348 fprintf (file, "%d\n", ((*found)->labelno));
29351 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
29352 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29353 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29355 fputs ("\t.set ", file);
29356 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29357 fprintf (file, "%d,", labelno);
29358 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29359 fprintf (file, "%d\n", ((*found)->labelno));
29366 /* If we're going to put a double constant in the TOC, make sure it's
29367 aligned properly when strict alignment is on. */
29368 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29369 && STRICT_ALIGNMENT
29370 && GET_MODE_BITSIZE (mode) >= 64
29371 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29372 ASM_OUTPUT_ALIGN (file, 3);
29375 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29377 /* Handle FP constants specially. Note that if we have a minimal
29378 TOC, things we put here aren't actually in the TOC, so we can allow
29380 if (GET_CODE (x) == CONST_DOUBLE &&
29381 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29382 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29386 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29387 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29389 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29393 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29394 fputs (DOUBLE_INT_ASM_OP, file);
29396 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29397 k[0] & 0xffffffff, k[1] & 0xffffffff,
29398 k[2] & 0xffffffff, k[3] & 0xffffffff);
29399 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29400 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29401 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29402 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29403 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29408 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29409 fputs ("\t.long ", file);
29411 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29412 k[0] & 0xffffffff, k[1] & 0xffffffff,
29413 k[2] & 0xffffffff, k[3] & 0xffffffff);
29414 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29415 k[0] & 0xffffffff, k[1] & 0xffffffff,
29416 k[2] & 0xffffffff, k[3] & 0xffffffff);
29420 else if (GET_CODE (x) == CONST_DOUBLE &&
29421 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29425 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29426 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29428 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29432 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29433 fputs (DOUBLE_INT_ASM_OP, file);
29435 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29436 k[0] & 0xffffffff, k[1] & 0xffffffff);
29437 fprintf (file, "0x%lx%08lx\n",
29438 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29439 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29444 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29445 fputs ("\t.long ", file);
29447 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29448 k[0] & 0xffffffff, k[1] & 0xffffffff);
29449 fprintf (file, "0x%lx,0x%lx\n",
29450 k[0] & 0xffffffff, k[1] & 0xffffffff);
29454 else if (GET_CODE (x) == CONST_DOUBLE &&
29455 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29459 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29460 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29462 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29466 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29467 fputs (DOUBLE_INT_ASM_OP, file);
29469 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29470 if (WORDS_BIG_ENDIAN)
29471 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29473 fprintf (file, "0x%lx\n", l & 0xffffffff);
29478 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29479 fputs ("\t.long ", file);
29481 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29482 fprintf (file, "0x%lx\n", l & 0xffffffff);
29486 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
29488 unsigned HOST_WIDE_INT low;
29489 HOST_WIDE_INT high;
29491 low = INTVAL (x) & 0xffffffff;
29492 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29494 /* TOC entries are always Pmode-sized, so when big-endian
29495 smaller integer constants in the TOC need to be padded.
29496 (This is still a win over putting the constants in
29497 a separate constant pool, because then we'd have
29498 to have both a TOC entry _and_ the actual constant.)
29500 For a 32-bit target, CONST_INT values are loaded and shifted
29501 entirely within `low' and can be stored in one TOC entry. */
29503 /* It would be easy to make this work, but it doesn't now. */
29504 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29506 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29509 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29510 high = (HOST_WIDE_INT) low >> 32;
29516 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29517 fputs (DOUBLE_INT_ASM_OP, file);
29519 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29520 (long) high & 0xffffffff, (long) low & 0xffffffff);
29521 fprintf (file, "0x%lx%08lx\n",
29522 (long) high & 0xffffffff, (long) low & 0xffffffff);
29527 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29529 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29530 fputs ("\t.long ", file);
29532 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29533 (long) high & 0xffffffff, (long) low & 0xffffffff);
29534 fprintf (file, "0x%lx,0x%lx\n",
29535 (long) high & 0xffffffff, (long) low & 0xffffffff);
29539 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29540 fputs ("\t.long ", file);
29542 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29543 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29549 if (GET_CODE (x) == CONST)
29551 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29552 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
29554 base = XEXP (XEXP (x, 0), 0);
29555 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29558 switch (GET_CODE (base))
29561 name = XSTR (base, 0);
29565 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29566 CODE_LABEL_NUMBER (XEXP (base, 0)));
29570 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29574 gcc_unreachable ();
29577 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29578 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29581 fputs ("\t.tc ", file);
29582 RS6000_OUTPUT_BASENAME (file, name);
29585 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29587 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29589 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29590 after other TOC symbols, reducing overflow of small TOC access
29591 to [TC] symbols. */
29592 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29593 ? "[TE]," : "[TC],", file);
29596 /* Currently C++ toc references to vtables can be emitted before it
29597 is decided whether the vtable is public or private. If this is
29598 the case, then the linker will eventually complain that there is
29599 a TOC reference to an unknown section. Thus, for vtables only,
29600 we emit the TOC reference to reference the symbol and not the
29602 if (VTABLE_NAME_P (name))
29604 RS6000_OUTPUT_BASENAME (file, name);
29606 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29607 else if (offset > 0)
29608 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29611 output_addr_const (file, x);
29614 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
29616 switch (SYMBOL_REF_TLS_MODEL (base))
29620 case TLS_MODEL_LOCAL_EXEC:
29621 fputs ("@le", file);
29623 case TLS_MODEL_INITIAL_EXEC:
29624 fputs ("@ie", file);
29626 /* Use global-dynamic for local-dynamic. */
29627 case TLS_MODEL_GLOBAL_DYNAMIC:
29628 case TLS_MODEL_LOCAL_DYNAMIC:
29630 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29631 fputs ("\t.tc .", file);
29632 RS6000_OUTPUT_BASENAME (file, name);
29633 fputs ("[TC],", file);
29634 output_addr_const (file, x);
29635 fputs ("@m", file);
29638 gcc_unreachable ();
29646 /* Output an assembler pseudo-op to write an ASCII string of N characters
29647 starting at P to FILE.
29649 On the RS/6000, we have to do this using the .byte operation and
29650 write out special characters outside the quoted string.
29651 Also, the assembler is broken; very long strings are truncated,
29652 so we must artificially break them up early. */
29655 output_ascii (FILE *file, const char *p, int n)
29658 int i, count_string;
29659 const char *for_string = "\t.byte \"";
29660 const char *for_decimal = "\t.byte ";
29661 const char *to_close = NULL;
29664 for (i = 0; i < n; i++)
29667 if (c >= ' ' && c < 0177)
29670 fputs (for_string, file);
29673 /* Write two quotes to get one. */
29681 for_decimal = "\"\n\t.byte ";
29685 if (count_string >= 512)
29687 fputs (to_close, file);
29689 for_string = "\t.byte \"";
29690 for_decimal = "\t.byte ";
29698 fputs (for_decimal, file);
29699 fprintf (file, "%d", c);
29701 for_string = "\n\t.byte \"";
29702 for_decimal = ", ";
29708 /* Now close the string if we have written one. Then end the line. */
29710 fputs (to_close, file);
29713 /* Generate a unique section name for FILENAME for a section type
29714 represented by SECTION_DESC. Output goes into BUF.
29716 SECTION_DESC can be any string, as long as it is different for each
29717 possible section type.
29719 We name the section in the same manner as xlc. The name begins with an
29720 underscore followed by the filename (after stripping any leading directory
29721 names) with the last period replaced by the string SECTION_DESC. If
29722 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29726 rs6000_gen_section_name (char **buf, const char *filename,
29727 const char *section_desc)
29729 const char *q, *after_last_slash, *last_period = 0;
29733 after_last_slash = filename;
29734 for (q = filename; *q; q++)
29737 after_last_slash = q + 1;
29738 else if (*q == '.')
29742 len = strlen (after_last_slash) + strlen (section_desc) + 2;
29743 *buf = (char *) xmalloc (len);
29748 for (q = after_last_slash; *q; q++)
29750 if (q == last_period)
29752 strcpy (p, section_desc);
29753 p += strlen (section_desc);
29757 else if (ISALNUM (*q))
29761 if (last_period == 0)
29762 strcpy (p, section_desc);
29767 /* Emit profile function. */
29770 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
29772 /* Non-standard profiling for kernels, which just saves LR then calls
29773 _mcount without worrying about arg saves. The idea is to change
29774 the function prologue as little as possible as it isn't easy to
29775 account for arg save/restore code added just for _mcount. */
29776 if (TARGET_PROFILE_KERNEL)
29779 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29781 #ifndef NO_PROFILE_COUNTERS
29782 # define NO_PROFILE_COUNTERS 0
29784 if (NO_PROFILE_COUNTERS)
29785 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29786 LCT_NORMAL, VOIDmode);
29790 const char *label_name;
29793 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29794 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
29795 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
29797 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29798 LCT_NORMAL, VOIDmode, fun, Pmode);
29801 else if (DEFAULT_ABI == ABI_DARWIN)
29803 const char *mcount_name = RS6000_MCOUNT;
29804 int caller_addr_regno = LR_REGNO;
29806 /* Be conservative and always set this, at least for now. */
29807 crtl->uses_pic_offset_table = 1;
29810 /* For PIC code, set up a stub and collect the caller's address
29811 from r0, which is where the prologue puts it. */
29812 if (MACHOPIC_INDIRECT
29813 && crtl->uses_pic_offset_table)
29814 caller_addr_regno = 0;
29816 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
29817 LCT_NORMAL, VOIDmode,
29818 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
29822 /* Write function profiler code. */
29825 output_function_profiler (FILE *file, int labelno)
29829 switch (DEFAULT_ABI)
29832 gcc_unreachable ();
29837 warning (0, "no profiling of 64-bit code for this ABI");
29840 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29841 fprintf (file, "\tmflr %s\n", reg_names[0]);
29842 if (NO_PROFILE_COUNTERS)
29844 asm_fprintf (file, "\tstw %s,4(%s)\n",
29845 reg_names[0], reg_names[1]);
29847 else if (TARGET_SECURE_PLT && flag_pic)
29849 if (TARGET_LINK_STACK)
29852 get_ppc476_thunk_name (name);
29853 asm_fprintf (file, "\tbl %s\n", name);
29856 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
29857 asm_fprintf (file, "\tstw %s,4(%s)\n",
29858 reg_names[0], reg_names[1]);
29859 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
29860 asm_fprintf (file, "\taddis %s,%s,",
29861 reg_names[12], reg_names[12]);
29862 assemble_name (file, buf);
29863 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
29864 assemble_name (file, buf);
29865 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
29867 else if (flag_pic == 1)
29869 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
29870 asm_fprintf (file, "\tstw %s,4(%s)\n",
29871 reg_names[0], reg_names[1]);
29872 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
29873 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
29874 assemble_name (file, buf);
29875 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
29877 else if (flag_pic > 1)
29879 asm_fprintf (file, "\tstw %s,4(%s)\n",
29880 reg_names[0], reg_names[1]);
29881 /* Now, we need to get the address of the label. */
29882 if (TARGET_LINK_STACK)
29885 get_ppc476_thunk_name (name);
29886 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
29887 assemble_name (file, buf);
29888 fputs ("-.\n1:", file);
29889 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
29890 asm_fprintf (file, "\taddi %s,%s,4\n",
29891 reg_names[11], reg_names[11]);
29895 fputs ("\tbcl 20,31,1f\n\t.long ", file);
29896 assemble_name (file, buf);
29897 fputs ("-.\n1:", file);
29898 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
29900 asm_fprintf (file, "\tlwz %s,0(%s)\n",
29901 reg_names[0], reg_names[11]);
29902 asm_fprintf (file, "\tadd %s,%s,%s\n",
29903 reg_names[0], reg_names[0], reg_names[11]);
29907 asm_fprintf (file, "\tlis %s,", reg_names[12]);
29908 assemble_name (file, buf);
29909 fputs ("@ha\n", file);
29910 asm_fprintf (file, "\tstw %s,4(%s)\n",
29911 reg_names[0], reg_names[1]);
29912 asm_fprintf (file, "\tla %s,", reg_names[0]);
29913 assemble_name (file, buf);
29914 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
29917 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
29918 fprintf (file, "\tbl %s%s\n",
29919 RS6000_MCOUNT, flag_pic ? "@plt" : "");
29925 /* Don't do anything, done in output_profile_hook (). */
29932 /* The following variable value is the last issued insn. */
29934 static rtx_insn *last_scheduled_insn;
29936 /* The following variable helps to balance issuing of load and
29937 store instructions */
29939 static int load_store_pendulum;
29941 /* The following variable helps pair divide insns during scheduling. */
29942 static int divide_cnt;
29943 /* The following variable helps pair and alternate vector and vector load
29944 insns during scheduling. */
29945 static int vec_pairing;
29948 /* Power4 load update and store update instructions are cracked into a
29949 load or store and an integer insn which are executed in the same cycle.
29950 Branches have their own dispatch slot which does not count against the
29951 GCC issue rate, but it changes the program flow so there are no other
29952 instructions to issue in this cycle. */
29955 rs6000_variable_issue_1 (rtx_insn *insn, int more)
29957 last_scheduled_insn = insn;
29958 if (GET_CODE (PATTERN (insn)) == USE
29959 || GET_CODE (PATTERN (insn)) == CLOBBER)
29961 cached_can_issue_more = more;
29962 return cached_can_issue_more;
29965 if (insn_terminates_group_p (insn, current_group))
29967 cached_can_issue_more = 0;
29968 return cached_can_issue_more;
29971 /* If no reservation, but reach here */
29972 if (recog_memoized (insn) < 0)
29975 if (rs6000_sched_groups)
29977 if (is_microcoded_insn (insn))
29978 cached_can_issue_more = 0;
29979 else if (is_cracked_insn (insn))
29980 cached_can_issue_more = more > 2 ? more - 2 : 0;
29982 cached_can_issue_more = more - 1;
29984 return cached_can_issue_more;
29987 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
29990 cached_can_issue_more = more - 1;
29991 return cached_can_issue_more;
29995 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
29997 int r = rs6000_variable_issue_1 (insn, more);
29999 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30003 /* Adjust the cost of a scheduling dependency. Return the new cost of
30004 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30007 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30010 enum attr_type attr_type;
30012 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30019 /* Data dependency; DEP_INSN writes a register that INSN reads
30020 some cycles later. */
30022 /* Separate a load from a narrower, dependent store. */
30023 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30024 && GET_CODE (PATTERN (insn)) == SET
30025 && GET_CODE (PATTERN (dep_insn)) == SET
30026 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
30027 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
30028 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30029 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30032 attr_type = get_attr_type (insn);
30037 /* Tell the first scheduling pass about the latency between
30038 a mtctr and bctr (and mtlr and br/blr). The first
30039 scheduling pass will not know about this latency since
30040 the mtctr instruction, which has the latency associated
30041 to it, will be generated by reload. */
30044 /* Leave some extra cycles between a compare and its
30045 dependent branch, to inhibit expensive mispredicts. */
30046 if ((rs6000_tune == PROCESSOR_PPC603
30047 || rs6000_tune == PROCESSOR_PPC604
30048 || rs6000_tune == PROCESSOR_PPC604e
30049 || rs6000_tune == PROCESSOR_PPC620
30050 || rs6000_tune == PROCESSOR_PPC630
30051 || rs6000_tune == PROCESSOR_PPC750
30052 || rs6000_tune == PROCESSOR_PPC7400
30053 || rs6000_tune == PROCESSOR_PPC7450
30054 || rs6000_tune == PROCESSOR_PPCE5500
30055 || rs6000_tune == PROCESSOR_PPCE6500
30056 || rs6000_tune == PROCESSOR_POWER4
30057 || rs6000_tune == PROCESSOR_POWER5
30058 || rs6000_tune == PROCESSOR_POWER7
30059 || rs6000_tune == PROCESSOR_POWER8
30060 || rs6000_tune == PROCESSOR_POWER9
30061 || rs6000_tune == PROCESSOR_CELL)
30062 && recog_memoized (dep_insn)
30063 && (INSN_CODE (dep_insn) >= 0))
30065 switch (get_attr_type (dep_insn))
30068 case TYPE_FPCOMPARE:
30069 case TYPE_CR_LOGICAL:
30073 if (get_attr_dot (dep_insn) == DOT_YES)
30078 if (get_attr_dot (dep_insn) == DOT_YES
30079 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30090 if ((rs6000_tune == PROCESSOR_POWER6)
30091 && recog_memoized (dep_insn)
30092 && (INSN_CODE (dep_insn) >= 0))
30095 if (GET_CODE (PATTERN (insn)) != SET)
30096 /* If this happens, we have to extend this to schedule
30097 optimally. Return default for now. */
30100 /* Adjust the cost for the case where the value written
30101 by a fixed point operation is used as the address
30102 gen value on a store. */
30103 switch (get_attr_type (dep_insn))
30108 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30109 return get_attr_sign_extend (dep_insn)
30110 == SIGN_EXTEND_YES ? 6 : 4;
30115 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30116 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30126 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30134 if (get_attr_update (dep_insn) == UPDATE_YES
30135 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30141 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30147 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30148 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30158 if ((rs6000_tune == PROCESSOR_POWER6)
30159 && recog_memoized (dep_insn)
30160 && (INSN_CODE (dep_insn) >= 0))
30163 /* Adjust the cost for the case where the value written
30164 by a fixed point instruction is used within the address
30165 gen portion of a subsequent load(u)(x) */
30166 switch (get_attr_type (dep_insn))
30171 if (set_to_load_agen (dep_insn, insn))
30172 return get_attr_sign_extend (dep_insn)
30173 == SIGN_EXTEND_YES ? 6 : 4;
30178 if (set_to_load_agen (dep_insn, insn))
30179 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30189 if (set_to_load_agen (dep_insn, insn))
30197 if (get_attr_update (dep_insn) == UPDATE_YES
30198 && set_to_load_agen (dep_insn, insn))
30204 if (set_to_load_agen (dep_insn, insn))
30210 if (set_to_load_agen (dep_insn, insn))
30211 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30221 if ((rs6000_tune == PROCESSOR_POWER6)
30222 && get_attr_update (insn) == UPDATE_NO
30223 && recog_memoized (dep_insn)
30224 && (INSN_CODE (dep_insn) >= 0)
30225 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30232 /* Fall out to return default cost. */
30236 case REG_DEP_OUTPUT:
30237 /* Output dependency; DEP_INSN writes a register that INSN writes some
30239 if ((rs6000_tune == PROCESSOR_POWER6)
30240 && recog_memoized (dep_insn)
30241 && (INSN_CODE (dep_insn) >= 0))
30243 attr_type = get_attr_type (insn);
30248 case TYPE_FPSIMPLE:
30249 if (get_attr_type (dep_insn) == TYPE_FP
30250 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30254 if (get_attr_update (insn) == UPDATE_NO
30255 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30262 /* Fall through, no cost for output dependency. */
30266 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30271 gcc_unreachable ();
30277 /* Debug version of rs6000_adjust_cost. */
30280 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30281 int cost, unsigned int dw)
30283 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30291 default: dep = "unknown depencency"; break;
30292 case REG_DEP_TRUE: dep = "data dependency"; break;
30293 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30294 case REG_DEP_ANTI: dep = "anti depencency"; break;
30298 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30299 "%s, insn:\n", ret, cost, dep);
30307 /* The function returns a true if INSN is microcoded.
30308 Return false otherwise. */
30311 is_microcoded_insn (rtx_insn *insn)
30313 if (!insn || !NONDEBUG_INSN_P (insn)
30314 || GET_CODE (PATTERN (insn)) == USE
30315 || GET_CODE (PATTERN (insn)) == CLOBBER)
30318 if (rs6000_tune == PROCESSOR_CELL)
30319 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30321 if (rs6000_sched_groups
30322 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30324 enum attr_type type = get_attr_type (insn);
30325 if ((type == TYPE_LOAD
30326 && get_attr_update (insn) == UPDATE_YES
30327 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30328 || ((type == TYPE_LOAD || type == TYPE_STORE)
30329 && get_attr_update (insn) == UPDATE_YES
30330 && get_attr_indexed (insn) == INDEXED_YES)
30331 || type == TYPE_MFCR)
30338 /* The function returns true if INSN is cracked into 2 instructions
30339 by the processor (and therefore occupies 2 issue slots). */
30342 is_cracked_insn (rtx_insn *insn)
30344 if (!insn || !NONDEBUG_INSN_P (insn)
30345 || GET_CODE (PATTERN (insn)) == USE
30346 || GET_CODE (PATTERN (insn)) == CLOBBER)
30349 if (rs6000_sched_groups
30350 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30352 enum attr_type type = get_attr_type (insn);
30353 if ((type == TYPE_LOAD
30354 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30355 && get_attr_update (insn) == UPDATE_NO)
30356 || (type == TYPE_LOAD
30357 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30358 && get_attr_update (insn) == UPDATE_YES
30359 && get_attr_indexed (insn) == INDEXED_NO)
30360 || (type == TYPE_STORE
30361 && get_attr_update (insn) == UPDATE_YES
30362 && get_attr_indexed (insn) == INDEXED_NO)
30363 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30364 && get_attr_update (insn) == UPDATE_YES)
30365 || (type == TYPE_CR_LOGICAL
30366 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30367 || (type == TYPE_EXTS
30368 && get_attr_dot (insn) == DOT_YES)
30369 || (type == TYPE_SHIFT
30370 && get_attr_dot (insn) == DOT_YES
30371 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30372 || (type == TYPE_MUL
30373 && get_attr_dot (insn) == DOT_YES)
30374 || type == TYPE_DIV
30375 || (type == TYPE_INSERT
30376 && get_attr_size (insn) == SIZE_32))
30383 /* The function returns true if INSN can be issued only from
30384 the branch slot. */
30387 is_branch_slot_insn (rtx_insn *insn)
30389 if (!insn || !NONDEBUG_INSN_P (insn)
30390 || GET_CODE (PATTERN (insn)) == USE
30391 || GET_CODE (PATTERN (insn)) == CLOBBER)
30394 if (rs6000_sched_groups)
30396 enum attr_type type = get_attr_type (insn);
30397 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30405 /* The function returns true if out_inst sets a value that is
30406 used in the address generation computation of in_insn */
30408 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30410 rtx out_set, in_set;
30412 /* For performance reasons, only handle the simple case where
30413 both loads are a single_set. */
30414 out_set = single_set (out_insn);
30417 in_set = single_set (in_insn);
30419 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30425 /* Try to determine base/offset/size parts of the given MEM.
30426 Return true if successful, false if all the values couldn't
30429 This function only looks for REG or REG+CONST address forms.
30430 REG+REG address form will return false. */
30433 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30434 HOST_WIDE_INT *size)
30437 if MEM_SIZE_KNOWN_P (mem)
30438 *size = MEM_SIZE (mem);
30442 addr_rtx = (XEXP (mem, 0));
30443 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30444 addr_rtx = XEXP (addr_rtx, 1);
30447 while (GET_CODE (addr_rtx) == PLUS
30448 && CONST_INT_P (XEXP (addr_rtx, 1)))
30450 *offset += INTVAL (XEXP (addr_rtx, 1));
30451 addr_rtx = XEXP (addr_rtx, 0);
30453 if (!REG_P (addr_rtx))
30460 /* The function returns true if the target storage location of
30461 mem1 is adjacent to the target storage location of mem2 */
30462 /* Return 1 if memory locations are adjacent. */
30465 adjacent_mem_locations (rtx mem1, rtx mem2)
30468 HOST_WIDE_INT off1, size1, off2, size2;
30470 if (get_memref_parts (mem1, ®1, &off1, &size1)
30471 && get_memref_parts (mem2, ®2, &off2, &size2))
30472 return ((REGNO (reg1) == REGNO (reg2))
30473 && ((off1 + size1 == off2)
30474 || (off2 + size2 == off1)));
30479 /* This function returns true if it can be determined that the two MEM
30480 locations overlap by at least 1 byte based on base reg/offset/size. */
30483 mem_locations_overlap (rtx mem1, rtx mem2)
30486 HOST_WIDE_INT off1, size1, off2, size2;
30488 if (get_memref_parts (mem1, ®1, &off1, &size1)
30489 && get_memref_parts (mem2, ®2, &off2, &size2))
30490 return ((REGNO (reg1) == REGNO (reg2))
30491 && (((off1 <= off2) && (off1 + size1 > off2))
30492 || ((off2 <= off1) && (off2 + size2 > off1))));
30497 /* A C statement (sans semicolon) to update the integer scheduling
30498 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30499 INSN earlier, reduce the priority to execute INSN later. Do not
30500 define this macro if you do not need to adjust the scheduling
30501 priorities of insns. */
30504 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30506 rtx load_mem, str_mem;
30507 /* On machines (like the 750) which have asymmetric integer units,
30508 where one integer unit can do multiply and divides and the other
30509 can't, reduce the priority of multiply/divide so it is scheduled
30510 before other integer operations. */
30513 if (! INSN_P (insn))
30516 if (GET_CODE (PATTERN (insn)) == USE)
30519 switch (rs6000_tune) {
30520 case PROCESSOR_PPC750:
30521 switch (get_attr_type (insn))
30528 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30529 priority, priority);
30530 if (priority >= 0 && priority < 0x01000000)
30537 if (insn_must_be_first_in_group (insn)
30538 && reload_completed
30539 && current_sched_info->sched_max_insns_priority
30540 && rs6000_sched_restricted_insns_priority)
30543 /* Prioritize insns that can be dispatched only in the first
30545 if (rs6000_sched_restricted_insns_priority == 1)
30546 /* Attach highest priority to insn. This means that in
30547 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30548 precede 'priority' (critical path) considerations. */
30549 return current_sched_info->sched_max_insns_priority;
30550 else if (rs6000_sched_restricted_insns_priority == 2)
30551 /* Increase priority of insn by a minimal amount. This means that in
30552 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30553 considerations precede dispatch-slot restriction considerations. */
30554 return (priority + 1);
30557 if (rs6000_tune == PROCESSOR_POWER6
30558 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30559 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30560 /* Attach highest priority to insn if the scheduler has just issued two
30561 stores and this instruction is a load, or two loads and this instruction
30562 is a store. Power6 wants loads and stores scheduled alternately
30564 return current_sched_info->sched_max_insns_priority;
30569 /* Return true if the instruction is nonpipelined on the Cell. */
30571 is_nonpipeline_insn (rtx_insn *insn)
30573 enum attr_type type;
30574 if (!insn || !NONDEBUG_INSN_P (insn)
30575 || GET_CODE (PATTERN (insn)) == USE
30576 || GET_CODE (PATTERN (insn)) == CLOBBER)
30579 type = get_attr_type (insn);
30580 if (type == TYPE_MUL
30581 || type == TYPE_DIV
30582 || type == TYPE_SDIV
30583 || type == TYPE_DDIV
30584 || type == TYPE_SSQRT
30585 || type == TYPE_DSQRT
30586 || type == TYPE_MFCR
30587 || type == TYPE_MFCRF
30588 || type == TYPE_MFJMPR)
30596 /* Return how many instructions the machine can issue per cycle. */
30599 rs6000_issue_rate (void)
30601 /* Unless scheduling for register pressure, use issue rate of 1 for
30602 first scheduling pass to decrease degradation. */
30603 if (!reload_completed && !flag_sched_pressure)
30606 switch (rs6000_tune) {
30607 case PROCESSOR_RS64A:
30608 case PROCESSOR_PPC601: /* ? */
30609 case PROCESSOR_PPC7450:
30611 case PROCESSOR_PPC440:
30612 case PROCESSOR_PPC603:
30613 case PROCESSOR_PPC750:
30614 case PROCESSOR_PPC7400:
30615 case PROCESSOR_PPC8540:
30616 case PROCESSOR_PPC8548:
30617 case PROCESSOR_CELL:
30618 case PROCESSOR_PPCE300C2:
30619 case PROCESSOR_PPCE300C3:
30620 case PROCESSOR_PPCE500MC:
30621 case PROCESSOR_PPCE500MC64:
30622 case PROCESSOR_PPCE5500:
30623 case PROCESSOR_PPCE6500:
30624 case PROCESSOR_TITAN:
30626 case PROCESSOR_PPC476:
30627 case PROCESSOR_PPC604:
30628 case PROCESSOR_PPC604e:
30629 case PROCESSOR_PPC620:
30630 case PROCESSOR_PPC630:
30632 case PROCESSOR_POWER4:
30633 case PROCESSOR_POWER5:
30634 case PROCESSOR_POWER6:
30635 case PROCESSOR_POWER7:
30637 case PROCESSOR_POWER8:
30639 case PROCESSOR_POWER9:
30646 /* Return how many instructions to look ahead for better insn
30650 rs6000_use_sched_lookahead (void)
30652 switch (rs6000_tune)
30654 case PROCESSOR_PPC8540:
30655 case PROCESSOR_PPC8548:
30658 case PROCESSOR_CELL:
30659 return (reload_completed ? 8 : 0);
30666 /* We are choosing insn from the ready queue. Return zero if INSN can be
30669 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30671 if (ready_index == 0)
30674 if (rs6000_tune != PROCESSOR_CELL)
30677 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30679 if (!reload_completed
30680 || is_nonpipeline_insn (insn)
30681 || is_microcoded_insn (insn))
30687 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30688 and return true. */
30691 find_mem_ref (rtx pat, rtx *mem_ref)
30696 /* stack_tie does not produce any real memory traffic. */
30697 if (tie_operand (pat, VOIDmode))
30700 if (GET_CODE (pat) == MEM)
30706 /* Recursively process the pattern. */
30707 fmt = GET_RTX_FORMAT (GET_CODE (pat));
30709 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
30713 if (find_mem_ref (XEXP (pat, i), mem_ref))
30716 else if (fmt[i] == 'E')
30717 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
30719 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
30727 /* Determine if PAT is a PATTERN of a load insn. */
30730 is_load_insn1 (rtx pat, rtx *load_mem)
30732 if (!pat || pat == NULL_RTX)
30735 if (GET_CODE (pat) == SET)
30736 return find_mem_ref (SET_SRC (pat), load_mem);
30738 if (GET_CODE (pat) == PARALLEL)
30742 for (i = 0; i < XVECLEN (pat, 0); i++)
30743 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
30750 /* Determine if INSN loads from memory. */
30753 is_load_insn (rtx insn, rtx *load_mem)
30755 if (!insn || !INSN_P (insn))
30761 return is_load_insn1 (PATTERN (insn), load_mem);
30764 /* Determine if PAT is a PATTERN of a store insn. */
30767 is_store_insn1 (rtx pat, rtx *str_mem)
30769 if (!pat || pat == NULL_RTX)
30772 if (GET_CODE (pat) == SET)
30773 return find_mem_ref (SET_DEST (pat), str_mem);
30775 if (GET_CODE (pat) == PARALLEL)
30779 for (i = 0; i < XVECLEN (pat, 0); i++)
30780 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
30787 /* Determine if INSN stores to memory. */
30790 is_store_insn (rtx insn, rtx *str_mem)
30792 if (!insn || !INSN_P (insn))
30795 return is_store_insn1 (PATTERN (insn), str_mem);
30798 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30801 is_power9_pairable_vec_type (enum attr_type type)
30805 case TYPE_VECSIMPLE:
30806 case TYPE_VECCOMPLEX:
30810 case TYPE_VECFLOAT:
30812 case TYPE_VECDOUBLE:
30820 /* Returns whether the dependence between INSN and NEXT is considered
30821 costly by the given target. */
30824 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
30828 rtx load_mem, str_mem;
30830 /* If the flag is not enabled - no dependence is considered costly;
30831 allow all dependent insns in the same group.
30832 This is the most aggressive option. */
30833 if (rs6000_sched_costly_dep == no_dep_costly)
30836 /* If the flag is set to 1 - a dependence is always considered costly;
30837 do not allow dependent instructions in the same group.
30838 This is the most conservative option. */
30839 if (rs6000_sched_costly_dep == all_deps_costly)
30842 insn = DEP_PRO (dep);
30843 next = DEP_CON (dep);
30845 if (rs6000_sched_costly_dep == store_to_load_dep_costly
30846 && is_load_insn (next, &load_mem)
30847 && is_store_insn (insn, &str_mem))
30848 /* Prevent load after store in the same group. */
30851 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
30852 && is_load_insn (next, &load_mem)
30853 && is_store_insn (insn, &str_mem)
30854 && DEP_TYPE (dep) == REG_DEP_TRUE
30855 && mem_locations_overlap(str_mem, load_mem))
30856 /* Prevent load after store in the same group if it is a true
30860 /* The flag is set to X; dependences with latency >= X are considered costly,
30861 and will not be scheduled in the same group. */
30862 if (rs6000_sched_costly_dep <= max_dep_latency
30863 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
30869 /* Return the next insn after INSN that is found before TAIL is reached,
30870 skipping any "non-active" insns - insns that will not actually occupy
30871 an issue slot. Return NULL_RTX if such an insn is not found. */
30874 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
30876 if (insn == NULL_RTX || insn == tail)
30881 insn = NEXT_INSN (insn);
30882 if (insn == NULL_RTX || insn == tail)
30886 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
30887 || (NONJUMP_INSN_P (insn)
30888 && GET_CODE (PATTERN (insn)) != USE
30889 && GET_CODE (PATTERN (insn)) != CLOBBER
30890 && INSN_CODE (insn) != CODE_FOR_stack_tie))
30896 /* Do Power9 specific sched_reorder2 reordering of ready list. */
30899 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
30904 enum attr_type type, type2;
30906 type = get_attr_type (last_scheduled_insn);
30908 /* Try to issue fixed point divides back-to-back in pairs so they will be
30909 routed to separate execution units and execute in parallel. */
30910 if (type == TYPE_DIV && divide_cnt == 0)
30912 /* First divide has been scheduled. */
30915 /* Scan the ready list looking for another divide, if found move it
30916 to the end of the list so it is chosen next. */
30920 if (recog_memoized (ready[pos]) >= 0
30921 && get_attr_type (ready[pos]) == TYPE_DIV)
30924 for (i = pos; i < lastpos; i++)
30925 ready[i] = ready[i + 1];
30926 ready[lastpos] = tmp;
30934 /* Last insn was the 2nd divide or not a divide, reset the counter. */
30937 /* The best dispatch throughput for vector and vector load insns can be
30938 achieved by interleaving a vector and vector load such that they'll
30939 dispatch to the same superslice. If this pairing cannot be achieved
30940 then it is best to pair vector insns together and vector load insns
30943 To aid in this pairing, vec_pairing maintains the current state with
30944 the following values:
30946 0 : Initial state, no vecload/vector pairing has been started.
30948 1 : A vecload or vector insn has been issued and a candidate for
30949 pairing has been found and moved to the end of the ready
30951 if (type == TYPE_VECLOAD)
30953 /* Issued a vecload. */
30954 if (vec_pairing == 0)
30956 int vecload_pos = -1;
30957 /* We issued a single vecload, look for a vector insn to pair it
30958 with. If one isn't found, try to pair another vecload. */
30962 if (recog_memoized (ready[pos]) >= 0)
30964 type2 = get_attr_type (ready[pos]);
30965 if (is_power9_pairable_vec_type (type2))
30967 /* Found a vector insn to pair with, move it to the
30968 end of the ready list so it is scheduled next. */
30970 for (i = pos; i < lastpos; i++)
30971 ready[i] = ready[i + 1];
30972 ready[lastpos] = tmp;
30974 return cached_can_issue_more;
30976 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
30977 /* Remember position of first vecload seen. */
30982 if (vecload_pos >= 0)
30984 /* Didn't find a vector to pair with but did find a vecload,
30985 move it to the end of the ready list. */
30986 tmp = ready[vecload_pos];
30987 for (i = vecload_pos; i < lastpos; i++)
30988 ready[i] = ready[i + 1];
30989 ready[lastpos] = tmp;
30991 return cached_can_issue_more;
30995 else if (is_power9_pairable_vec_type (type))
30997 /* Issued a vector operation. */
30998 if (vec_pairing == 0)
31001 /* We issued a single vector insn, look for a vecload to pair it
31002 with. If one isn't found, try to pair another vector. */
31006 if (recog_memoized (ready[pos]) >= 0)
31008 type2 = get_attr_type (ready[pos]);
31009 if (type2 == TYPE_VECLOAD)
31011 /* Found a vecload insn to pair with, move it to the
31012 end of the ready list so it is scheduled next. */
31014 for (i = pos; i < lastpos; i++)
31015 ready[i] = ready[i + 1];
31016 ready[lastpos] = tmp;
31018 return cached_can_issue_more;
31020 else if (is_power9_pairable_vec_type (type2)
31022 /* Remember position of first vector insn seen. */
31029 /* Didn't find a vecload to pair with but did find a vector
31030 insn, move it to the end of the ready list. */
31031 tmp = ready[vec_pos];
31032 for (i = vec_pos; i < lastpos; i++)
31033 ready[i] = ready[i + 1];
31034 ready[lastpos] = tmp;
31036 return cached_can_issue_more;
31041 /* We've either finished a vec/vecload pair, couldn't find an insn to
31042 continue the current pair, or the last insn had nothing to do with
31043 with pairing. In any case, reset the state. */
31047 return cached_can_issue_more;
31050 /* We are about to begin issuing insns for this clock cycle. */
31053 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31054 rtx_insn **ready ATTRIBUTE_UNUSED,
31055 int *pn_ready ATTRIBUTE_UNUSED,
31056 int clock_var ATTRIBUTE_UNUSED)
31058 int n_ready = *pn_ready;
31061 fprintf (dump, "// rs6000_sched_reorder :\n");
31063 /* Reorder the ready list, if the second to last ready insn
31064 is a nonepipeline insn. */
31065 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31067 if (is_nonpipeline_insn (ready[n_ready - 1])
31068 && (recog_memoized (ready[n_ready - 2]) > 0))
31069 /* Simply swap first two insns. */
31070 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31073 if (rs6000_tune == PROCESSOR_POWER6)
31074 load_store_pendulum = 0;
31076 return rs6000_issue_rate ();
31079 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31082 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31083 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31086 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31088 /* For Power6, we need to handle some special cases to try and keep the
31089 store queue from overflowing and triggering expensive flushes.
31091 This code monitors how load and store instructions are being issued
31092 and skews the ready list one way or the other to increase the likelihood
31093 that a desired instruction is issued at the proper time.
31095 A couple of things are done. First, we maintain a "load_store_pendulum"
31096 to track the current state of load/store issue.
31098 - If the pendulum is at zero, then no loads or stores have been
31099 issued in the current cycle so we do nothing.
31101 - If the pendulum is 1, then a single load has been issued in this
31102 cycle and we attempt to locate another load in the ready list to
31105 - If the pendulum is -2, then two stores have already been
31106 issued in this cycle, so we increase the priority of the first load
31107 in the ready list to increase it's likelihood of being chosen first
31110 - If the pendulum is -1, then a single store has been issued in this
31111 cycle and we attempt to locate another store in the ready list to
31112 issue with it, preferring a store to an adjacent memory location to
31113 facilitate store pairing in the store queue.
31115 - If the pendulum is 2, then two loads have already been
31116 issued in this cycle, so we increase the priority of the first store
31117 in the ready list to increase it's likelihood of being chosen first
31120 - If the pendulum < -2 or > 2, then do nothing.
31122 Note: This code covers the most common scenarios. There exist non
31123 load/store instructions which make use of the LSU and which
31124 would need to be accounted for to strictly model the behavior
31125 of the machine. Those instructions are currently unaccounted
31126 for to help minimize compile time overhead of this code.
31128 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31133 rtx load_mem, str_mem;
31135 if (is_store_insn (last_scheduled_insn, &str_mem))
31136 /* Issuing a store, swing the load_store_pendulum to the left */
31137 load_store_pendulum--;
31138 else if (is_load_insn (last_scheduled_insn, &load_mem))
31139 /* Issuing a load, swing the load_store_pendulum to the right */
31140 load_store_pendulum++;
31142 return cached_can_issue_more;
31144 /* If the pendulum is balanced, or there is only one instruction on
31145 the ready list, then all is well, so return. */
31146 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31147 return cached_can_issue_more;
31149 if (load_store_pendulum == 1)
31151 /* A load has been issued in this cycle. Scan the ready list
31152 for another load to issue with it */
31157 if (is_load_insn (ready[pos], &load_mem))
31159 /* Found a load. Move it to the head of the ready list,
31160 and adjust it's priority so that it is more likely to
31163 for (i=pos; i<*pn_ready-1; i++)
31164 ready[i] = ready[i + 1];
31165 ready[*pn_ready-1] = tmp;
31167 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31168 INSN_PRIORITY (tmp)++;
31174 else if (load_store_pendulum == -2)
31176 /* Two stores have been issued in this cycle. Increase the
31177 priority of the first load in the ready list to favor it for
31178 issuing in the next cycle. */
31183 if (is_load_insn (ready[pos], &load_mem)
31185 && INSN_PRIORITY_KNOWN (ready[pos]))
31187 INSN_PRIORITY (ready[pos])++;
31189 /* Adjust the pendulum to account for the fact that a load
31190 was found and increased in priority. This is to prevent
31191 increasing the priority of multiple loads */
31192 load_store_pendulum--;
31199 else if (load_store_pendulum == -1)
31201 /* A store has been issued in this cycle. Scan the ready list for
31202 another store to issue with it, preferring a store to an adjacent
31204 int first_store_pos = -1;
31210 if (is_store_insn (ready[pos], &str_mem))
31213 /* Maintain the index of the first store found on the
31215 if (first_store_pos == -1)
31216 first_store_pos = pos;
31218 if (is_store_insn (last_scheduled_insn, &str_mem2)
31219 && adjacent_mem_locations (str_mem, str_mem2))
31221 /* Found an adjacent store. Move it to the head of the
31222 ready list, and adjust it's priority so that it is
31223 more likely to stay there */
31225 for (i=pos; i<*pn_ready-1; i++)
31226 ready[i] = ready[i + 1];
31227 ready[*pn_ready-1] = tmp;
31229 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31230 INSN_PRIORITY (tmp)++;
31232 first_store_pos = -1;
31240 if (first_store_pos >= 0)
31242 /* An adjacent store wasn't found, but a non-adjacent store was,
31243 so move the non-adjacent store to the front of the ready
31244 list, and adjust its priority so that it is more likely to
31246 tmp = ready[first_store_pos];
31247 for (i=first_store_pos; i<*pn_ready-1; i++)
31248 ready[i] = ready[i + 1];
31249 ready[*pn_ready-1] = tmp;
31250 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31251 INSN_PRIORITY (tmp)++;
31254 else if (load_store_pendulum == 2)
31256 /* Two loads have been issued in this cycle. Increase the priority
31257 of the first store in the ready list to favor it for issuing in
31263 if (is_store_insn (ready[pos], &str_mem)
31265 && INSN_PRIORITY_KNOWN (ready[pos]))
31267 INSN_PRIORITY (ready[pos])++;
31269 /* Adjust the pendulum to account for the fact that a store
31270 was found and increased in priority. This is to prevent
31271 increasing the priority of multiple stores */
31272 load_store_pendulum++;
31281 /* Do Power9 dependent reordering if necessary. */
31282 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31283 && recog_memoized (last_scheduled_insn) >= 0)
31284 return power9_sched_reorder2 (ready, *pn_ready - 1);
31286 return cached_can_issue_more;
31289 /* Return whether the presence of INSN causes a dispatch group termination
31290 of group WHICH_GROUP.
31292 If WHICH_GROUP == current_group, this function will return true if INSN
31293 causes the termination of the current group (i.e, the dispatch group to
31294 which INSN belongs). This means that INSN will be the last insn in the
31295 group it belongs to.
31297 If WHICH_GROUP == previous_group, this function will return true if INSN
31298 causes the termination of the previous group (i.e, the dispatch group that
31299 precedes the group to which INSN belongs). This means that INSN will be
31300 the first insn in the group it belongs to). */
31303 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31310 first = insn_must_be_first_in_group (insn);
31311 last = insn_must_be_last_in_group (insn);
31316 if (which_group == current_group)
31318 else if (which_group == previous_group)
31326 insn_must_be_first_in_group (rtx_insn *insn)
31328 enum attr_type type;
31332 || DEBUG_INSN_P (insn)
31333 || GET_CODE (PATTERN (insn)) == USE
31334 || GET_CODE (PATTERN (insn)) == CLOBBER)
31337 switch (rs6000_tune)
31339 case PROCESSOR_POWER5:
31340 if (is_cracked_insn (insn))
31343 case PROCESSOR_POWER4:
31344 if (is_microcoded_insn (insn))
31347 if (!rs6000_sched_groups)
31350 type = get_attr_type (insn);
31357 case TYPE_CR_LOGICAL:
31370 case PROCESSOR_POWER6:
31371 type = get_attr_type (insn);
31380 case TYPE_FPCOMPARE:
31391 if (get_attr_dot (insn) == DOT_NO
31392 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31397 if (get_attr_size (insn) == SIZE_32)
31405 if (get_attr_update (insn) == UPDATE_YES)
31413 case PROCESSOR_POWER7:
31414 type = get_attr_type (insn);
31418 case TYPE_CR_LOGICAL:
31432 if (get_attr_dot (insn) == DOT_YES)
31437 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31438 || get_attr_update (insn) == UPDATE_YES)
31445 if (get_attr_update (insn) == UPDATE_YES)
31453 case PROCESSOR_POWER8:
31454 type = get_attr_type (insn);
31458 case TYPE_CR_LOGICAL:
31466 case TYPE_VECSTORE:
31473 if (get_attr_dot (insn) == DOT_YES)
31478 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31479 || get_attr_update (insn) == UPDATE_YES)
31484 if (get_attr_update (insn) == UPDATE_YES
31485 && get_attr_indexed (insn) == INDEXED_YES)
31501 insn_must_be_last_in_group (rtx_insn *insn)
31503 enum attr_type type;
31507 || DEBUG_INSN_P (insn)
31508 || GET_CODE (PATTERN (insn)) == USE
31509 || GET_CODE (PATTERN (insn)) == CLOBBER)
31512 switch (rs6000_tune) {
31513 case PROCESSOR_POWER4:
31514 case PROCESSOR_POWER5:
31515 if (is_microcoded_insn (insn))
31518 if (is_branch_slot_insn (insn))
31522 case PROCESSOR_POWER6:
31523 type = get_attr_type (insn);
31531 case TYPE_FPCOMPARE:
31542 if (get_attr_dot (insn) == DOT_NO
31543 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31548 if (get_attr_size (insn) == SIZE_32)
31556 case PROCESSOR_POWER7:
31557 type = get_attr_type (insn);
31567 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31568 && get_attr_update (insn) == UPDATE_YES)
31573 if (get_attr_update (insn) == UPDATE_YES
31574 && get_attr_indexed (insn) == INDEXED_YES)
31582 case PROCESSOR_POWER8:
31583 type = get_attr_type (insn);
31595 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31596 && get_attr_update (insn) == UPDATE_YES)
31601 if (get_attr_update (insn) == UPDATE_YES
31602 && get_attr_indexed (insn) == INDEXED_YES)
31617 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31618 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31621 is_costly_group (rtx *group_insns, rtx next_insn)
31624 int issue_rate = rs6000_issue_rate ();
31626 for (i = 0; i < issue_rate; i++)
31628 sd_iterator_def sd_it;
31630 rtx insn = group_insns[i];
31635 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31637 rtx next = DEP_CON (dep);
31639 if (next == next_insn
31640 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31648 /* Utility of the function redefine_groups.
31649 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31650 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31651 to keep it "far" (in a separate group) from GROUP_INSNS, following
31652 one of the following schemes, depending on the value of the flag
31653 -minsert_sched_nops = X:
31654 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31655 in order to force NEXT_INSN into a separate group.
31656 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31657 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31658 insertion (has a group just ended, how many vacant issue slots remain in the
31659 last group, and how many dispatch groups were encountered so far). */
31662 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31663 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31668 int issue_rate = rs6000_issue_rate ();
31669 bool end = *group_end;
31672 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31673 return can_issue_more;
31675 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31676 return can_issue_more;
31678 force = is_costly_group (group_insns, next_insn);
31680 return can_issue_more;
31682 if (sched_verbose > 6)
31683 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
31684 *group_count ,can_issue_more);
31686 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
31689 can_issue_more = 0;
31691 /* Since only a branch can be issued in the last issue_slot, it is
31692 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31693 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31694 in this case the last nop will start a new group and the branch
31695 will be forced to the new group. */
31696 if (can_issue_more && !is_branch_slot_insn (next_insn))
31699 /* Do we have a special group ending nop? */
31700 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
31701 || rs6000_tune == PROCESSOR_POWER8)
31703 nop = gen_group_ending_nop ();
31704 emit_insn_before (nop, next_insn);
31705 can_issue_more = 0;
31708 while (can_issue_more > 0)
31711 emit_insn_before (nop, next_insn);
31719 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
31721 int n_nops = rs6000_sched_insert_nops;
31723 /* Nops can't be issued from the branch slot, so the effective
31724 issue_rate for nops is 'issue_rate - 1'. */
31725 if (can_issue_more == 0)
31726 can_issue_more = issue_rate;
31728 if (can_issue_more == 0)
31730 can_issue_more = issue_rate - 1;
31733 for (i = 0; i < issue_rate; i++)
31735 group_insns[i] = 0;
31742 emit_insn_before (nop, next_insn);
31743 if (can_issue_more == issue_rate - 1) /* new group begins */
31746 if (can_issue_more == 0)
31748 can_issue_more = issue_rate - 1;
31751 for (i = 0; i < issue_rate; i++)
31753 group_insns[i] = 0;
31759 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31762 /* Is next_insn going to start a new group? */
31765 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31766 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31767 || (can_issue_more < issue_rate &&
31768 insn_terminates_group_p (next_insn, previous_group)));
31769 if (*group_end && end)
31772 if (sched_verbose > 6)
31773 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
31774 *group_count, can_issue_more);
31775 return can_issue_more;
31778 return can_issue_more;
31781 /* This function tries to synch the dispatch groups that the compiler "sees"
31782 with the dispatch groups that the processor dispatcher is expected to
31783 form in practice. It tries to achieve this synchronization by forcing the
31784 estimated processor grouping on the compiler (as opposed to the function
31785 'pad_goups' which tries to force the scheduler's grouping on the processor).
31787 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31788 examines the (estimated) dispatch groups that will be formed by the processor
31789 dispatcher. It marks these group boundaries to reflect the estimated
31790 processor grouping, overriding the grouping that the scheduler had marked.
31791 Depending on the value of the flag '-minsert-sched-nops' this function can
31792 force certain insns into separate groups or force a certain distance between
31793 them by inserting nops, for example, if there exists a "costly dependence"
31796 The function estimates the group boundaries that the processor will form as
31797 follows: It keeps track of how many vacant issue slots are available after
31798 each insn. A subsequent insn will start a new group if one of the following
31800 - no more vacant issue slots remain in the current dispatch group.
31801 - only the last issue slot, which is the branch slot, is vacant, but the next
31802 insn is not a branch.
31803 - only the last 2 or less issue slots, including the branch slot, are vacant,
31804 which means that a cracked insn (which occupies two issue slots) can't be
31805 issued in this group.
31806 - less than 'issue_rate' slots are vacant, and the next insn always needs to
31807 start a new group. */
31810 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31813 rtx_insn *insn, *next_insn;
31815 int can_issue_more;
31818 int group_count = 0;
31822 issue_rate = rs6000_issue_rate ();
31823 group_insns = XALLOCAVEC (rtx, issue_rate);
31824 for (i = 0; i < issue_rate; i++)
31826 group_insns[i] = 0;
31828 can_issue_more = issue_rate;
31830 insn = get_next_active_insn (prev_head_insn, tail);
31833 while (insn != NULL_RTX)
31835 slot = (issue_rate - can_issue_more);
31836 group_insns[slot] = insn;
31838 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
31839 if (insn_terminates_group_p (insn, current_group))
31840 can_issue_more = 0;
31842 next_insn = get_next_active_insn (insn, tail);
31843 if (next_insn == NULL_RTX)
31844 return group_count + 1;
31846 /* Is next_insn going to start a new group? */
31848 = (can_issue_more == 0
31849 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31850 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31851 || (can_issue_more < issue_rate &&
31852 insn_terminates_group_p (next_insn, previous_group)));
31854 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
31855 next_insn, &group_end, can_issue_more,
31861 can_issue_more = 0;
31862 for (i = 0; i < issue_rate; i++)
31864 group_insns[i] = 0;
31868 if (GET_MODE (next_insn) == TImode && can_issue_more)
31869 PUT_MODE (next_insn, VOIDmode);
31870 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
31871 PUT_MODE (next_insn, TImode);
31874 if (can_issue_more == 0)
31875 can_issue_more = issue_rate;
31878 return group_count;
31881 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
31882 dispatch group boundaries that the scheduler had marked. Pad with nops
31883 any dispatch groups which have vacant issue slots, in order to force the
31884 scheduler's grouping on the processor dispatcher. The function
31885 returns the number of dispatch groups found. */
31888 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31891 rtx_insn *insn, *next_insn;
31894 int can_issue_more;
31896 int group_count = 0;
31898 /* Initialize issue_rate. */
31899 issue_rate = rs6000_issue_rate ();
31900 can_issue_more = issue_rate;
31902 insn = get_next_active_insn (prev_head_insn, tail);
31903 next_insn = get_next_active_insn (insn, tail);
31905 while (insn != NULL_RTX)
31908 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
31910 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
31912 if (next_insn == NULL_RTX)
31917 /* If the scheduler had marked group termination at this location
31918 (between insn and next_insn), and neither insn nor next_insn will
31919 force group termination, pad the group with nops to force group
31922 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
31923 && !insn_terminates_group_p (insn, current_group)
31924 && !insn_terminates_group_p (next_insn, previous_group))
31926 if (!is_branch_slot_insn (next_insn))
31929 while (can_issue_more)
31932 emit_insn_before (nop, next_insn);
31937 can_issue_more = issue_rate;
31942 next_insn = get_next_active_insn (insn, tail);
31945 return group_count;
31948 /* We're beginning a new block. Initialize data structures as necessary. */
31951 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
31952 int sched_verbose ATTRIBUTE_UNUSED,
31953 int max_ready ATTRIBUTE_UNUSED)
31955 last_scheduled_insn = NULL;
31956 load_store_pendulum = 0;
31961 /* The following function is called at the end of scheduling BB.
31962 After reload, it inserts nops at insn group bundling. */
31965 rs6000_sched_finish (FILE *dump, int sched_verbose)
31970 fprintf (dump, "=== Finishing schedule.\n");
31972 if (reload_completed && rs6000_sched_groups)
31974 /* Do not run sched_finish hook when selective scheduling enabled. */
31975 if (sel_sched_p ())
31978 if (rs6000_sched_insert_nops == sched_finish_none)
31981 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
31982 n_groups = pad_groups (dump, sched_verbose,
31983 current_sched_info->prev_head,
31984 current_sched_info->next_tail);
31986 n_groups = redefine_groups (dump, sched_verbose,
31987 current_sched_info->prev_head,
31988 current_sched_info->next_tail);
31990 if (sched_verbose >= 6)
31992 fprintf (dump, "ngroups = %d\n", n_groups);
31993 print_rtl (dump, current_sched_info->prev_head);
31994 fprintf (dump, "Done finish_sched\n");
31999 struct rs6000_sched_context
32001 short cached_can_issue_more;
32002 rtx_insn *last_scheduled_insn;
32003 int load_store_pendulum;
32008 typedef struct rs6000_sched_context rs6000_sched_context_def;
32009 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32011 /* Allocate store for new scheduling context. */
32013 rs6000_alloc_sched_context (void)
32015 return xmalloc (sizeof (rs6000_sched_context_def));
32018 /* If CLEAN_P is true then initializes _SC with clean data,
32019 and from the global context otherwise. */
32021 rs6000_init_sched_context (void *_sc, bool clean_p)
32023 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32027 sc->cached_can_issue_more = 0;
32028 sc->last_scheduled_insn = NULL;
32029 sc->load_store_pendulum = 0;
32030 sc->divide_cnt = 0;
32031 sc->vec_pairing = 0;
32035 sc->cached_can_issue_more = cached_can_issue_more;
32036 sc->last_scheduled_insn = last_scheduled_insn;
32037 sc->load_store_pendulum = load_store_pendulum;
32038 sc->divide_cnt = divide_cnt;
32039 sc->vec_pairing = vec_pairing;
32043 /* Sets the global scheduling context to the one pointed to by _SC. */
32045 rs6000_set_sched_context (void *_sc)
32047 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32049 gcc_assert (sc != NULL);
32051 cached_can_issue_more = sc->cached_can_issue_more;
32052 last_scheduled_insn = sc->last_scheduled_insn;
32053 load_store_pendulum = sc->load_store_pendulum;
32054 divide_cnt = sc->divide_cnt;
32055 vec_pairing = sc->vec_pairing;
32060 rs6000_free_sched_context (void *_sc)
32062 gcc_assert (_sc != NULL);
32068 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32070 switch (get_attr_type (insn))
32085 /* Length in units of the trampoline for entering a nested function. */
32088 rs6000_trampoline_size (void)
32092 switch (DEFAULT_ABI)
32095 gcc_unreachable ();
32098 ret = (TARGET_32BIT) ? 12 : 24;
32102 gcc_assert (!TARGET_32BIT);
32108 ret = (TARGET_32BIT) ? 40 : 48;
32115 /* Emit RTL insns to initialize the variable parts of a trampoline.
32116 FNADDR is an RTX for the address of the function's pure code.
32117 CXT is an RTX for the static chain value for the function. */
32120 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32122 int regsize = (TARGET_32BIT) ? 4 : 8;
32123 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32124 rtx ctx_reg = force_reg (Pmode, cxt);
32125 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32127 switch (DEFAULT_ABI)
32130 gcc_unreachable ();
32132 /* Under AIX, just build the 3 word function descriptor */
32135 rtx fnmem, fn_reg, toc_reg;
32137 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32138 error ("you cannot take the address of a nested function if you use "
32139 "the %qs option", "-mno-pointers-to-nested-functions");
32141 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32142 fn_reg = gen_reg_rtx (Pmode);
32143 toc_reg = gen_reg_rtx (Pmode);
32145 /* Macro to shorten the code expansions below. */
32146 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32148 m_tramp = replace_equiv_address (m_tramp, addr);
32150 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32151 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32152 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32153 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32154 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32160 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32164 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32165 LCT_NORMAL, VOIDmode,
32167 GEN_INT (rs6000_trampoline_size ()), SImode,
32175 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32176 identifier as an argument, so the front end shouldn't look it up. */
32179 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32181 return is_attribute_p ("altivec", attr_id);
32184 /* Handle the "altivec" attribute. The attribute may have
32185 arguments as follows:
32187 __attribute__((altivec(vector__)))
32188 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32189 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32191 and may appear more than once (e.g., 'vector bool char') in a
32192 given declaration. */
32195 rs6000_handle_altivec_attribute (tree *node,
32196 tree name ATTRIBUTE_UNUSED,
32198 int flags ATTRIBUTE_UNUSED,
32199 bool *no_add_attrs)
32201 tree type = *node, result = NULL_TREE;
32205 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32206 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32207 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32210 while (POINTER_TYPE_P (type)
32211 || TREE_CODE (type) == FUNCTION_TYPE
32212 || TREE_CODE (type) == METHOD_TYPE
32213 || TREE_CODE (type) == ARRAY_TYPE)
32214 type = TREE_TYPE (type);
32216 mode = TYPE_MODE (type);
32218 /* Check for invalid AltiVec type qualifiers. */
32219 if (type == long_double_type_node)
32220 error ("use of %<long double%> in AltiVec types is invalid");
32221 else if (type == boolean_type_node)
32222 error ("use of boolean types in AltiVec types is invalid");
32223 else if (TREE_CODE (type) == COMPLEX_TYPE)
32224 error ("use of %<complex%> in AltiVec types is invalid");
32225 else if (DECIMAL_FLOAT_MODE_P (mode))
32226 error ("use of decimal floating point types in AltiVec types is invalid");
32227 else if (!TARGET_VSX)
32229 if (type == long_unsigned_type_node || type == long_integer_type_node)
32232 error ("use of %<long%> in AltiVec types is invalid for "
32233 "64-bit code without %qs", "-mvsx");
32234 else if (rs6000_warn_altivec_long)
32235 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32238 else if (type == long_long_unsigned_type_node
32239 || type == long_long_integer_type_node)
32240 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32242 else if (type == double_type_node)
32243 error ("use of %<double%> in AltiVec types is invalid without %qs",
32247 switch (altivec_type)
32250 unsigned_p = TYPE_UNSIGNED (type);
32254 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32257 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32260 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32263 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32266 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32268 case E_SFmode: result = V4SF_type_node; break;
32269 case E_DFmode: result = V2DF_type_node; break;
32270 /* If the user says 'vector int bool', we may be handed the 'bool'
32271 attribute _before_ the 'vector' attribute, and so select the
32272 proper type in the 'b' case below. */
32273 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32274 case E_V2DImode: case E_V2DFmode:
32282 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32283 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32284 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32285 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32292 case E_V8HImode: result = pixel_V8HI_type_node;
32298 /* Propagate qualifiers attached to the element type
32299 onto the vector type. */
32300 if (result && result != type && TYPE_QUALS (type))
32301 result = build_qualified_type (result, TYPE_QUALS (type));
32303 *no_add_attrs = true; /* No need to hang on to the attribute. */
32306 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32311 /* AltiVec defines five built-in scalar types that serve as vector
32312 elements; we must teach the compiler how to mangle them. The 128-bit
32313 floating point mangling is target-specific as well. */
32315 static const char *
32316 rs6000_mangle_type (const_tree type)
32318 type = TYPE_MAIN_VARIANT (type);
32320 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32321 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32324 if (type == bool_char_type_node) return "U6__boolc";
32325 if (type == bool_short_type_node) return "U6__bools";
32326 if (type == pixel_type_node) return "u7__pixel";
32327 if (type == bool_int_type_node) return "U6__booli";
32328 if (type == bool_long_long_type_node) return "U6__boolx";
32330 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32332 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32333 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32335 /* For all other types, use the default mangling. */
32339 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32340 struct attribute_spec.handler. */
32343 rs6000_handle_longcall_attribute (tree *node, tree name,
32344 tree args ATTRIBUTE_UNUSED,
32345 int flags ATTRIBUTE_UNUSED,
32346 bool *no_add_attrs)
32348 if (TREE_CODE (*node) != FUNCTION_TYPE
32349 && TREE_CODE (*node) != FIELD_DECL
32350 && TREE_CODE (*node) != TYPE_DECL)
32352 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32354 *no_add_attrs = true;
32360 /* Set longcall attributes on all functions declared when
32361 rs6000_default_long_calls is true. */
32363 rs6000_set_default_type_attributes (tree type)
32365 if (rs6000_default_long_calls
32366 && (TREE_CODE (type) == FUNCTION_TYPE
32367 || TREE_CODE (type) == METHOD_TYPE))
32368 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32370 TYPE_ATTRIBUTES (type));
32373 darwin_set_default_type_attributes (type);
32377 /* Return a reference suitable for calling a function with the
32378 longcall attribute. */
32381 rs6000_longcall_ref (rtx call_ref)
32383 const char *call_name;
32386 if (GET_CODE (call_ref) != SYMBOL_REF)
32389 /* System V adds '.' to the internal name, so skip them. */
32390 call_name = XSTR (call_ref, 0);
32391 if (*call_name == '.')
32393 while (*call_name == '.')
32396 node = get_identifier (call_name);
32397 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32400 return force_reg (Pmode, call_ref);
32403 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32404 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32407 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32408 struct attribute_spec.handler. */
32410 rs6000_handle_struct_attribute (tree *node, tree name,
32411 tree args ATTRIBUTE_UNUSED,
32412 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32415 if (DECL_P (*node))
32417 if (TREE_CODE (*node) == TYPE_DECL)
32418 type = &TREE_TYPE (*node);
32423 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32424 || TREE_CODE (*type) == UNION_TYPE)))
32426 warning (OPT_Wattributes, "%qE attribute ignored", name);
32427 *no_add_attrs = true;
32430 else if ((is_attribute_p ("ms_struct", name)
32431 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32432 || ((is_attribute_p ("gcc_struct", name)
32433 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32435 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32437 *no_add_attrs = true;
32444 rs6000_ms_bitfield_layout_p (const_tree record_type)
32446 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32447 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32448 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32451 #ifdef USING_ELFOS_H
32453 /* A get_unnamed_section callback, used for switching to toc_section. */
32456 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32458 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32459 && TARGET_MINIMAL_TOC)
32461 if (!toc_initialized)
32463 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32464 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32465 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32466 fprintf (asm_out_file, "\t.tc ");
32467 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32468 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32469 fprintf (asm_out_file, "\n");
32471 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32472 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32473 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32474 fprintf (asm_out_file, " = .+32768\n");
32475 toc_initialized = 1;
32478 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32480 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32482 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32483 if (!toc_initialized)
32485 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32486 toc_initialized = 1;
32491 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32492 if (!toc_initialized)
32494 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32495 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32496 fprintf (asm_out_file, " = .+32768\n");
32497 toc_initialized = 1;
32502 /* Implement TARGET_ASM_INIT_SECTIONS. */
32505 rs6000_elf_asm_init_sections (void)
32508 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32511 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32512 SDATA2_SECTION_ASM_OP);
32515 /* Implement TARGET_SELECT_RTX_SECTION. */
32518 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32519 unsigned HOST_WIDE_INT align)
32521 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32522 return toc_section;
32524 return default_elf_select_rtx_section (mode, x, align);
32527 /* For a SYMBOL_REF, set generic flags and then perform some
32528 target-specific processing.
32530 When the AIX ABI is requested on a non-AIX system, replace the
32531 function name with the real name (with a leading .) rather than the
32532 function descriptor name. This saves a lot of overriding code to
32533 read the prefixes. */
32535 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32537 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32539 default_encode_section_info (decl, rtl, first);
32542 && TREE_CODE (decl) == FUNCTION_DECL
32544 && DEFAULT_ABI == ABI_AIX)
32546 rtx sym_ref = XEXP (rtl, 0);
32547 size_t len = strlen (XSTR (sym_ref, 0));
32548 char *str = XALLOCAVEC (char, len + 2);
32550 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32551 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32556 compare_section_name (const char *section, const char *templ)
32560 len = strlen (templ);
32561 return (strncmp (section, templ, len) == 0
32562 && (section[len] == 0 || section[len] == '.'));
32566 rs6000_elf_in_small_data_p (const_tree decl)
32568 if (rs6000_sdata == SDATA_NONE)
32571 /* We want to merge strings, so we never consider them small data. */
32572 if (TREE_CODE (decl) == STRING_CST)
32575 /* Functions are never in the small data area. */
32576 if (TREE_CODE (decl) == FUNCTION_DECL)
32579 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32581 const char *section = DECL_SECTION_NAME (decl);
32582 if (compare_section_name (section, ".sdata")
32583 || compare_section_name (section, ".sdata2")
32584 || compare_section_name (section, ".gnu.linkonce.s")
32585 || compare_section_name (section, ".sbss")
32586 || compare_section_name (section, ".sbss2")
32587 || compare_section_name (section, ".gnu.linkonce.sb")
32588 || strcmp (section, ".PPC.EMB.sdata0") == 0
32589 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32594 /* If we are told not to put readonly data in sdata, then don't. */
32595 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32596 && !rs6000_readonly_in_sdata)
32599 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32602 && size <= g_switch_value
32603 /* If it's not public, and we're not going to reference it there,
32604 there's no need to put it in the small data section. */
32605 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32612 #endif /* USING_ELFOS_H */
32614 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32617 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32619 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32622 /* Do not place thread-local symbols refs in the object blocks. */
32625 rs6000_use_blocks_for_decl_p (const_tree decl)
32627 return !DECL_THREAD_LOCAL_P (decl);
32630 /* Return a REG that occurs in ADDR with coefficient 1.
32631 ADDR can be effectively incremented by incrementing REG.
32633 r0 is special and we must not select it as an address
32634 register by this routine since our caller will try to
32635 increment the returned register via an "la" instruction. */
32638 find_addr_reg (rtx addr)
32640 while (GET_CODE (addr) == PLUS)
32642 if (GET_CODE (XEXP (addr, 0)) == REG
32643 && REGNO (XEXP (addr, 0)) != 0)
32644 addr = XEXP (addr, 0);
32645 else if (GET_CODE (XEXP (addr, 1)) == REG
32646 && REGNO (XEXP (addr, 1)) != 0)
32647 addr = XEXP (addr, 1);
32648 else if (CONSTANT_P (XEXP (addr, 0)))
32649 addr = XEXP (addr, 1);
32650 else if (CONSTANT_P (XEXP (addr, 1)))
32651 addr = XEXP (addr, 0);
32653 gcc_unreachable ();
32655 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
32660 rs6000_fatal_bad_address (rtx op)
32662 fatal_insn ("bad address", op);
32667 typedef struct branch_island_d {
32668 tree function_name;
32674 static vec<branch_island, va_gc> *branch_islands;
32676 /* Remember to generate a branch island for far calls to the given
32680 add_compiler_branch_island (tree label_name, tree function_name,
32683 branch_island bi = {function_name, label_name, line_number};
32684 vec_safe_push (branch_islands, bi);
32687 /* Generate far-jump branch islands for everything recorded in
32688 branch_islands. Invoked immediately after the last instruction of
32689 the epilogue has been emitted; the branch islands must be appended
32690 to, and contiguous with, the function body. Mach-O stubs are
32691 generated in machopic_output_stub(). */
32694 macho_branch_islands (void)
32698 while (!vec_safe_is_empty (branch_islands))
32700 branch_island *bi = &branch_islands->last ();
32701 const char *label = IDENTIFIER_POINTER (bi->label_name);
32702 const char *name = IDENTIFIER_POINTER (bi->function_name);
32703 char name_buf[512];
32704 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32705 if (name[0] == '*' || name[0] == '&')
32706 strcpy (name_buf, name+1);
32710 strcpy (name_buf+1, name);
32712 strcpy (tmp_buf, "\n");
32713 strcat (tmp_buf, label);
32714 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32715 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32716 dbxout_stabd (N_SLINE, bi->line_number);
32717 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32720 if (TARGET_LINK_STACK)
32723 get_ppc476_thunk_name (name);
32724 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
32725 strcat (tmp_buf, name);
32726 strcat (tmp_buf, "\n");
32727 strcat (tmp_buf, label);
32728 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32732 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
32733 strcat (tmp_buf, label);
32734 strcat (tmp_buf, "_pic\n");
32735 strcat (tmp_buf, label);
32736 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32739 strcat (tmp_buf, "\taddis r11,r11,ha16(");
32740 strcat (tmp_buf, name_buf);
32741 strcat (tmp_buf, " - ");
32742 strcat (tmp_buf, label);
32743 strcat (tmp_buf, "_pic)\n");
32745 strcat (tmp_buf, "\tmtlr r0\n");
32747 strcat (tmp_buf, "\taddi r12,r11,lo16(");
32748 strcat (tmp_buf, name_buf);
32749 strcat (tmp_buf, " - ");
32750 strcat (tmp_buf, label);
32751 strcat (tmp_buf, "_pic)\n");
32753 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
32757 strcat (tmp_buf, ":\nlis r12,hi16(");
32758 strcat (tmp_buf, name_buf);
32759 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
32760 strcat (tmp_buf, name_buf);
32761 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
32763 output_asm_insn (tmp_buf, 0);
32764 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32765 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32766 dbxout_stabd (N_SLINE, bi->line_number);
32767 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32768 branch_islands->pop ();
32772 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32773 already there or not. */
32776 no_previous_def (tree function_name)
32781 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32782 if (function_name == bi->function_name)
32787 /* GET_PREV_LABEL gets the label name from the previous definition of
32791 get_prev_label (tree function_name)
32796 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32797 if (function_name == bi->function_name)
32798 return bi->label_name;
32802 /* INSN is either a function call or a millicode call. It may have an
32803 unconditional jump in its delay slot.
32805 CALL_DEST is the routine we are calling. */
32808 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
32809 int cookie_operand_number)
32811 static char buf[256];
32812 if (darwin_emit_branch_islands
32813 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
32814 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
32817 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
32819 if (no_previous_def (funname))
32821 rtx label_rtx = gen_label_rtx ();
32822 char *label_buf, temp_buf[256];
32823 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
32824 CODE_LABEL_NUMBER (label_rtx));
32825 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
32826 labelname = get_identifier (label_buf);
32827 add_compiler_branch_island (labelname, funname, insn_line (insn));
32830 labelname = get_prev_label (funname);
32832 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
32833 instruction will reach 'foo', otherwise link as 'bl L42'".
32834 "L42" should be a 'branch island', that will do a far jump to
32835 'foo'. Branch islands are generated in
32836 macho_branch_islands(). */
32837 sprintf (buf, "jbsr %%z%d,%.246s",
32838 dest_operand_number, IDENTIFIER_POINTER (labelname));
32841 sprintf (buf, "bl %%z%d", dest_operand_number);
32845 /* Generate PIC and indirect symbol stubs. */
32848 machopic_output_stub (FILE *file, const char *symb, const char *stub)
32850 unsigned int length;
32851 char *symbol_name, *lazy_ptr_name;
32852 char *local_label_0;
32853 static int label = 0;
32855 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
32856 symb = (*targetm.strip_name_encoding) (symb);
32859 length = strlen (symb);
32860 symbol_name = XALLOCAVEC (char, length + 32);
32861 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
32863 lazy_ptr_name = XALLOCAVEC (char, length + 32);
32864 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
32867 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
32869 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
32873 fprintf (file, "\t.align 5\n");
32875 fprintf (file, "%s:\n", stub);
32876 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32879 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
32880 sprintf (local_label_0, "\"L%011d$spb\"", label);
32882 fprintf (file, "\tmflr r0\n");
32883 if (TARGET_LINK_STACK)
32886 get_ppc476_thunk_name (name);
32887 fprintf (file, "\tbl %s\n", name);
32888 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
32892 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
32893 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
32895 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
32896 lazy_ptr_name, local_label_0);
32897 fprintf (file, "\tmtlr r0\n");
32898 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
32899 (TARGET_64BIT ? "ldu" : "lwzu"),
32900 lazy_ptr_name, local_label_0);
32901 fprintf (file, "\tmtctr r12\n");
32902 fprintf (file, "\tbctr\n");
32906 fprintf (file, "\t.align 4\n");
32908 fprintf (file, "%s:\n", stub);
32909 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32911 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
32912 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
32913 (TARGET_64BIT ? "ldu" : "lwzu"),
32915 fprintf (file, "\tmtctr r12\n");
32916 fprintf (file, "\tbctr\n");
32919 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
32920 fprintf (file, "%s:\n", lazy_ptr_name);
32921 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
32922 fprintf (file, "%sdyld_stub_binding_helper\n",
32923 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
32926 /* Legitimize PIC addresses. If the address is already
32927 position-independent, we return ORIG. Newly generated
32928 position-independent addresses go into a reg. This is REG if non
32929 zero, otherwise we allocate register(s) as necessary. */
32931 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
32934 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
32939 if (reg == NULL && !reload_completed)
32940 reg = gen_reg_rtx (Pmode);
32942 if (GET_CODE (orig) == CONST)
32946 if (GET_CODE (XEXP (orig, 0)) == PLUS
32947 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
32950 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
32952 /* Use a different reg for the intermediate value, as
32953 it will be marked UNCHANGING. */
32954 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
32955 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
32958 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
32961 if (GET_CODE (offset) == CONST_INT)
32963 if (SMALL_INT (offset))
32964 return plus_constant (Pmode, base, INTVAL (offset));
32965 else if (!reload_completed)
32966 offset = force_reg (Pmode, offset);
32969 rtx mem = force_const_mem (Pmode, orig);
32970 return machopic_legitimize_pic_address (mem, Pmode, reg);
32973 return gen_rtx_PLUS (Pmode, base, offset);
32976 /* Fall back on generic machopic code. */
32977 return machopic_legitimize_pic_address (orig, mode, reg);
32980 /* Output a .machine directive for the Darwin assembler, and call
32981 the generic start_file routine. */
32984 rs6000_darwin_file_start (void)
32986 static const struct
32990 HOST_WIDE_INT if_set;
32992 { "ppc64", "ppc64", MASK_64BIT },
32993 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
32994 { "power4", "ppc970", 0 },
32995 { "G5", "ppc970", 0 },
32996 { "7450", "ppc7450", 0 },
32997 { "7400", "ppc7400", MASK_ALTIVEC },
32998 { "G4", "ppc7400", 0 },
32999 { "750", "ppc750", 0 },
33000 { "740", "ppc750", 0 },
33001 { "G3", "ppc750", 0 },
33002 { "604e", "ppc604e", 0 },
33003 { "604", "ppc604", 0 },
33004 { "603e", "ppc603", 0 },
33005 { "603", "ppc603", 0 },
33006 { "601", "ppc601", 0 },
33007 { NULL, "ppc", 0 } };
33008 const char *cpu_id = "";
33011 rs6000_file_start ();
33012 darwin_file_start ();
33014 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33016 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33017 cpu_id = rs6000_default_cpu;
33019 if (global_options_set.x_rs6000_cpu_index)
33020 cpu_id = processor_target_table[rs6000_cpu_index].name;
33022 /* Look through the mapping array. Pick the first name that either
33023 matches the argument, has a bit set in IF_SET that is also set
33024 in the target flags, or has a NULL name. */
33027 while (mapping[i].arg != NULL
33028 && strcmp (mapping[i].arg, cpu_id) != 0
33029 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33032 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33035 #endif /* TARGET_MACHO */
33039 rs6000_elf_reloc_rw_mask (void)
33043 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33049 /* Record an element in the table of global constructors. SYMBOL is
33050 a SYMBOL_REF of the function to be called; PRIORITY is a number
33051 between 0 and MAX_INIT_PRIORITY.
33053 This differs from default_named_section_asm_out_constructor in
33054 that we have special handling for -mrelocatable. */
33056 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33058 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33060 const char *section = ".ctors";
33063 if (priority != DEFAULT_INIT_PRIORITY)
33065 sprintf (buf, ".ctors.%.5u",
33066 /* Invert the numbering so the linker puts us in the proper
33067 order; constructors are run from right to left, and the
33068 linker sorts in increasing order. */
33069 MAX_INIT_PRIORITY - priority);
33073 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33074 assemble_align (POINTER_SIZE);
33076 if (DEFAULT_ABI == ABI_V4
33077 && (TARGET_RELOCATABLE || flag_pic > 1))
33079 fputs ("\t.long (", asm_out_file);
33080 output_addr_const (asm_out_file, symbol);
33081 fputs (")@fixup\n", asm_out_file);
33084 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33087 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33089 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33091 const char *section = ".dtors";
33094 if (priority != DEFAULT_INIT_PRIORITY)
33096 sprintf (buf, ".dtors.%.5u",
33097 /* Invert the numbering so the linker puts us in the proper
33098 order; constructors are run from right to left, and the
33099 linker sorts in increasing order. */
33100 MAX_INIT_PRIORITY - priority);
33104 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33105 assemble_align (POINTER_SIZE);
33107 if (DEFAULT_ABI == ABI_V4
33108 && (TARGET_RELOCATABLE || flag_pic > 1))
33110 fputs ("\t.long (", asm_out_file);
33111 output_addr_const (asm_out_file, symbol);
33112 fputs (")@fixup\n", asm_out_file);
33115 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33119 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33121 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33123 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33124 ASM_OUTPUT_LABEL (file, name);
33125 fputs (DOUBLE_INT_ASM_OP, file);
33126 rs6000_output_function_entry (file, name);
33127 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33130 fputs ("\t.size\t", file);
33131 assemble_name (file, name);
33132 fputs (",24\n\t.type\t.", file);
33133 assemble_name (file, name);
33134 fputs (",@function\n", file);
33135 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33137 fputs ("\t.globl\t.", file);
33138 assemble_name (file, name);
33143 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33144 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33145 rs6000_output_function_entry (file, name);
33146 fputs (":\n", file);
33151 if (DEFAULT_ABI == ABI_V4
33152 && (TARGET_RELOCATABLE || flag_pic > 1)
33153 && !TARGET_SECURE_PLT
33154 && (!constant_pool_empty_p () || crtl->profile)
33155 && (uses_toc = uses_TOC ()))
33160 switch_to_other_text_partition ();
33161 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33163 fprintf (file, "\t.long ");
33164 assemble_name (file, toc_label_name);
33167 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33168 assemble_name (file, buf);
33171 switch_to_other_text_partition ();
33174 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33175 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33177 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33181 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33183 fprintf (file, "\t.quad .TOC.-");
33184 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33185 assemble_name (file, buf);
33189 if (DEFAULT_ABI == ABI_AIX)
33191 const char *desc_name, *orig_name;
33193 orig_name = (*targetm.strip_name_encoding) (name);
33194 desc_name = orig_name;
33195 while (*desc_name == '.')
33198 if (TREE_PUBLIC (decl))
33199 fprintf (file, "\t.globl %s\n", desc_name);
33201 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33202 fprintf (file, "%s:\n", desc_name);
33203 fprintf (file, "\t.long %s\n", orig_name);
33204 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33205 fputs ("\t.long 0\n", file);
33206 fprintf (file, "\t.previous\n");
33208 ASM_OUTPUT_LABEL (file, name);
33211 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33213 rs6000_elf_file_end (void)
33215 #ifdef HAVE_AS_GNU_ATTRIBUTE
33216 /* ??? The value emitted depends on options active at file end.
33217 Assume anyone using #pragma or attributes that might change
33218 options knows what they are doing. */
33219 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33220 && rs6000_passes_float)
33224 if (TARGET_HARD_FLOAT)
33228 if (rs6000_passes_long_double)
33230 if (!TARGET_LONG_DOUBLE_128)
33232 else if (TARGET_IEEEQUAD)
33237 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33239 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33241 if (rs6000_passes_vector)
33242 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33243 (TARGET_ALTIVEC_ABI ? 2 : 1));
33244 if (rs6000_returns_struct)
33245 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33246 aix_struct_return ? 2 : 1);
33249 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33250 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33251 file_end_indicate_exec_stack ();
33254 if (flag_split_stack)
33255 file_end_indicate_split_stack ();
33259 /* We have expanded a CPU builtin, so we need to emit a reference to
33260 the special symbol that LIBC uses to declare it supports the
33261 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33262 switch_to_section (data_section);
33263 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33264 fprintf (asm_out_file, "\t%s %s\n",
33265 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33272 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33273 #define HAVE_XCOFF_DWARF_EXTRAS 0
33276 static enum unwind_info_type
33277 rs6000_xcoff_debug_unwind_info (void)
33283 rs6000_xcoff_asm_output_anchor (rtx symbol)
33287 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33288 SYMBOL_REF_BLOCK_OFFSET (symbol));
33289 fprintf (asm_out_file, "%s", SET_ASM_OP);
33290 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33291 fprintf (asm_out_file, ",");
33292 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33293 fprintf (asm_out_file, "\n");
33297 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33299 fputs (GLOBAL_ASM_OP, stream);
33300 RS6000_OUTPUT_BASENAME (stream, name);
33301 putc ('\n', stream);
33304 /* A get_unnamed_decl callback, used for read-only sections. PTR
33305 points to the section string variable. */
33308 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33310 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33311 *(const char *const *) directive,
33312 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33315 /* Likewise for read-write sections. */
33318 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33320 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33321 *(const char *const *) directive,
33322 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33326 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33328 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33329 *(const char *const *) directive,
33330 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33333 /* A get_unnamed_section callback, used for switching to toc_section. */
33336 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33338 if (TARGET_MINIMAL_TOC)
33340 /* toc_section is always selected at least once from
33341 rs6000_xcoff_file_start, so this is guaranteed to
33342 always be defined once and only once in each file. */
33343 if (!toc_initialized)
33345 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33346 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33347 toc_initialized = 1;
33349 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33350 (TARGET_32BIT ? "" : ",3"));
33353 fputs ("\t.toc\n", asm_out_file);
33356 /* Implement TARGET_ASM_INIT_SECTIONS. */
33359 rs6000_xcoff_asm_init_sections (void)
33361 read_only_data_section
33362 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33363 &xcoff_read_only_section_name);
33365 private_data_section
33366 = get_unnamed_section (SECTION_WRITE,
33367 rs6000_xcoff_output_readwrite_section_asm_op,
33368 &xcoff_private_data_section_name);
33371 = get_unnamed_section (SECTION_TLS,
33372 rs6000_xcoff_output_tls_section_asm_op,
33373 &xcoff_tls_data_section_name);
33375 tls_private_data_section
33376 = get_unnamed_section (SECTION_TLS,
33377 rs6000_xcoff_output_tls_section_asm_op,
33378 &xcoff_private_data_section_name);
33380 read_only_private_data_section
33381 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33382 &xcoff_private_data_section_name);
33385 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33387 readonly_data_section = read_only_data_section;
33391 rs6000_xcoff_reloc_rw_mask (void)
33397 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33398 tree decl ATTRIBUTE_UNUSED)
33401 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33403 if (flags & SECTION_EXCLUDE)
33405 else if (flags & SECTION_DEBUG)
33407 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33410 else if (flags & SECTION_CODE)
33412 else if (flags & SECTION_TLS)
33414 else if (flags & SECTION_WRITE)
33419 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33420 (flags & SECTION_CODE) ? "." : "",
33421 name, suffix[smclass], flags & SECTION_ENTSIZE);
33424 #define IN_NAMED_SECTION(DECL) \
33425 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33426 && DECL_SECTION_NAME (DECL) != NULL)
33429 rs6000_xcoff_select_section (tree decl, int reloc,
33430 unsigned HOST_WIDE_INT align)
33432 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33434 if (align > BIGGEST_ALIGNMENT)
33436 resolve_unique_section (decl, reloc, true);
33437 if (IN_NAMED_SECTION (decl))
33438 return get_named_section (decl, NULL, reloc);
33441 if (decl_readonly_section (decl, reloc))
33443 if (TREE_PUBLIC (decl))
33444 return read_only_data_section;
33446 return read_only_private_data_section;
33451 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33453 if (TREE_PUBLIC (decl))
33454 return tls_data_section;
33455 else if (bss_initializer_p (decl))
33457 /* Convert to COMMON to emit in BSS. */
33458 DECL_COMMON (decl) = 1;
33459 return tls_comm_section;
33462 return tls_private_data_section;
33466 if (TREE_PUBLIC (decl))
33467 return data_section;
33469 return private_data_section;
33474 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33478 /* Use select_section for private data and uninitialized data with
33479 alignment <= BIGGEST_ALIGNMENT. */
33480 if (!TREE_PUBLIC (decl)
33481 || DECL_COMMON (decl)
33482 || (DECL_INITIAL (decl) == NULL_TREE
33483 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33484 || DECL_INITIAL (decl) == error_mark_node
33485 || (flag_zero_initialized_in_bss
33486 && initializer_zerop (DECL_INITIAL (decl))))
33489 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33490 name = (*targetm.strip_name_encoding) (name);
33491 set_decl_section_name (decl, name);
33494 /* Select section for constant in constant pool.
33496 On RS/6000, all constants are in the private read-only data area.
33497 However, if this is being placed in the TOC it must be output as a
33501 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33502 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33504 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33505 return toc_section;
33507 return read_only_private_data_section;
33510 /* Remove any trailing [DS] or the like from the symbol name. */
33512 static const char *
33513 rs6000_xcoff_strip_name_encoding (const char *name)
33518 len = strlen (name);
33519 if (name[len - 1] == ']')
33520 return ggc_alloc_string (name, len - 4);
33525 /* Section attributes. AIX is always PIC. */
33527 static unsigned int
33528 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33530 unsigned int align;
33531 unsigned int flags = default_section_type_flags (decl, name, reloc);
33533 /* Align to at least UNIT size. */
33534 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33535 align = MIN_UNITS_PER_WORD;
33537 /* Increase alignment of large objects if not already stricter. */
33538 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33539 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33540 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33542 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33545 /* Output at beginning of assembler file.
33547 Initialize the section names for the RS/6000 at this point.
33549 Specify filename, including full path, to assembler.
33551 We want to go into the TOC section so at least one .toc will be emitted.
33552 Also, in order to output proper .bs/.es pairs, we need at least one static
33553 [RW] section emitted.
33555 Finally, declare mcount when profiling to make the assembler happy. */
33558 rs6000_xcoff_file_start (void)
33560 rs6000_gen_section_name (&xcoff_bss_section_name,
33561 main_input_filename, ".bss_");
33562 rs6000_gen_section_name (&xcoff_private_data_section_name,
33563 main_input_filename, ".rw_");
33564 rs6000_gen_section_name (&xcoff_read_only_section_name,
33565 main_input_filename, ".ro_");
33566 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33567 main_input_filename, ".tls_");
33568 rs6000_gen_section_name (&xcoff_tbss_section_name,
33569 main_input_filename, ".tbss_[UL]");
33571 fputs ("\t.file\t", asm_out_file);
33572 output_quoted_string (asm_out_file, main_input_filename);
33573 fputc ('\n', asm_out_file);
33574 if (write_symbols != NO_DEBUG)
33575 switch_to_section (private_data_section);
33576 switch_to_section (toc_section);
33577 switch_to_section (text_section);
33579 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33580 rs6000_file_start ();
33583 /* Output at end of assembler file.
33584 On the RS/6000, referencing data should automatically pull in text. */
33587 rs6000_xcoff_file_end (void)
33589 switch_to_section (text_section);
33590 fputs ("_section_.text:\n", asm_out_file);
33591 switch_to_section (data_section);
33592 fputs (TARGET_32BIT
33593 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33597 struct declare_alias_data
33600 bool function_descriptor;
33603 /* Declare alias N. A helper function for for_node_and_aliases. */
33606 rs6000_declare_alias (struct symtab_node *n, void *d)
33608 struct declare_alias_data *data = (struct declare_alias_data *)d;
33609 /* Main symbol is output specially, because varasm machinery does part of
33610 the job for us - we do not need to declare .globl/lglobs and such. */
33611 if (!n->alias || n->weakref)
33614 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33617 /* Prevent assemble_alias from trying to use .set pseudo operation
33618 that does not behave as expected by the middle-end. */
33619 TREE_ASM_WRITTEN (n->decl) = true;
33621 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33622 char *buffer = (char *) alloca (strlen (name) + 2);
33624 int dollar_inside = 0;
33626 strcpy (buffer, name);
33627 p = strchr (buffer, '$');
33631 p = strchr (p + 1, '$');
33633 if (TREE_PUBLIC (n->decl))
33635 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33637 if (dollar_inside) {
33638 if (data->function_descriptor)
33639 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33640 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33642 if (data->function_descriptor)
33644 fputs ("\t.globl .", data->file);
33645 RS6000_OUTPUT_BASENAME (data->file, buffer);
33646 putc ('\n', data->file);
33648 fputs ("\t.globl ", data->file);
33649 RS6000_OUTPUT_BASENAME (data->file, buffer);
33650 putc ('\n', data->file);
33652 #ifdef ASM_WEAKEN_DECL
33653 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33654 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33661 if (data->function_descriptor)
33662 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33663 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33665 if (data->function_descriptor)
33667 fputs ("\t.lglobl .", data->file);
33668 RS6000_OUTPUT_BASENAME (data->file, buffer);
33669 putc ('\n', data->file);
33671 fputs ("\t.lglobl ", data->file);
33672 RS6000_OUTPUT_BASENAME (data->file, buffer);
33673 putc ('\n', data->file);
33675 if (data->function_descriptor)
33676 fputs (".", data->file);
33677 RS6000_OUTPUT_BASENAME (data->file, buffer);
33678 fputs (":\n", data->file);
33683 #ifdef HAVE_GAS_HIDDEN
33684 /* Helper function to calculate visibility of a DECL
33685 and return the value as a const string. */
33687 static const char *
33688 rs6000_xcoff_visibility (tree decl)
33690 static const char * const visibility_types[] = {
33691 "", ",protected", ",hidden", ",internal"
33694 enum symbol_visibility vis = DECL_VISIBILITY (decl);
33695 return visibility_types[vis];
33700 /* This macro produces the initial definition of a function name.
33701 On the RS/6000, we need to place an extra '.' in the function name and
33702 output the function descriptor.
33703 Dollar signs are converted to underscores.
33705 The csect for the function will have already been created when
33706 text_section was selected. We do have to go back to that csect, however.
33708 The third and fourth parameters to the .function pseudo-op (16 and 044)
33709 are placeholders which no longer have any use.
33711 Because AIX assembler's .set command has unexpected semantics, we output
33712 all aliases as alternative labels in front of the definition. */
33715 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
33717 char *buffer = (char *) alloca (strlen (name) + 1);
33719 int dollar_inside = 0;
33720 struct declare_alias_data data = {file, false};
33722 strcpy (buffer, name);
33723 p = strchr (buffer, '$');
33727 p = strchr (p + 1, '$');
33729 if (TREE_PUBLIC (decl))
33731 if (!RS6000_WEAK || !DECL_WEAK (decl))
33733 if (dollar_inside) {
33734 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33735 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33737 fputs ("\t.globl .", file);
33738 RS6000_OUTPUT_BASENAME (file, buffer);
33739 #ifdef HAVE_GAS_HIDDEN
33740 fputs (rs6000_xcoff_visibility (decl), file);
33747 if (dollar_inside) {
33748 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33749 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33751 fputs ("\t.lglobl .", file);
33752 RS6000_OUTPUT_BASENAME (file, buffer);
33755 fputs ("\t.csect ", file);
33756 RS6000_OUTPUT_BASENAME (file, buffer);
33757 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
33758 RS6000_OUTPUT_BASENAME (file, buffer);
33759 fputs (":\n", file);
33760 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33762 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
33763 RS6000_OUTPUT_BASENAME (file, buffer);
33764 fputs (", TOC[tc0], 0\n", file);
33766 switch_to_section (function_section (decl));
33768 RS6000_OUTPUT_BASENAME (file, buffer);
33769 fputs (":\n", file);
33770 data.function_descriptor = true;
33771 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33773 if (!DECL_IGNORED_P (decl))
33775 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33776 xcoffout_declare_function (file, decl, buffer);
33777 else if (write_symbols == DWARF2_DEBUG)
33779 name = (*targetm.strip_name_encoding) (name);
33780 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
33787 /* Output assembly language to globalize a symbol from a DECL,
33788 possibly with visibility. */
33791 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
33793 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
33794 fputs (GLOBAL_ASM_OP, stream);
33795 RS6000_OUTPUT_BASENAME (stream, name);
33796 #ifdef HAVE_GAS_HIDDEN
33797 fputs (rs6000_xcoff_visibility (decl), stream);
33799 putc ('\n', stream);
33802 /* Output assembly language to define a symbol as COMMON from a DECL,
33803 possibly with visibility. */
33806 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
33807 tree decl ATTRIBUTE_UNUSED,
33809 unsigned HOST_WIDE_INT size,
33810 unsigned HOST_WIDE_INT align)
33812 unsigned HOST_WIDE_INT align2 = 2;
33815 align2 = floor_log2 (align / BITS_PER_UNIT);
33819 fputs (COMMON_ASM_OP, stream);
33820 RS6000_OUTPUT_BASENAME (stream, name);
33823 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
33826 #ifdef HAVE_GAS_HIDDEN
33828 fputs (rs6000_xcoff_visibility (decl), stream);
33830 putc ('\n', stream);
33833 /* This macro produces the initial definition of a object (variable) name.
33834 Because AIX assembler's .set command has unexpected semantics, we output
33835 all aliases as alternative labels in front of the definition. */
33838 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
33840 struct declare_alias_data data = {file, false};
33841 RS6000_OUTPUT_BASENAME (file, name);
33842 fputs (":\n", file);
33843 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33847 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
33850 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
33852 fputs (integer_asm_op (size, FALSE), file);
33853 assemble_name (file, label);
33854 fputs ("-$", file);
33857 /* Output a symbol offset relative to the dbase for the current object.
33858 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
33861 __gcc_unwind_dbase is embedded in all executables/libraries through
33862 libgcc/config/rs6000/crtdbase.S. */
33865 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
33867 fputs (integer_asm_op (size, FALSE), file);
33868 assemble_name (file, label);
33869 fputs("-__gcc_unwind_dbase", file);
33874 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
33878 const char *symname;
33880 default_encode_section_info (decl, rtl, first);
33882 /* Careful not to prod global register variables. */
33885 symbol = XEXP (rtl, 0);
33886 if (GET_CODE (symbol) != SYMBOL_REF)
33889 flags = SYMBOL_REF_FLAGS (symbol);
33891 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33892 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
33894 SYMBOL_REF_FLAGS (symbol) = flags;
33896 /* Append mapping class to extern decls. */
33897 symname = XSTR (symbol, 0);
33898 if (decl /* sync condition with assemble_external () */
33899 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
33900 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
33901 || TREE_CODE (decl) == FUNCTION_DECL)
33902 && symname[strlen (symname) - 1] != ']')
33904 char *newname = (char *) alloca (strlen (symname) + 5);
33905 strcpy (newname, symname);
33906 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
33907 ? "[DS]" : "[UA]"));
33908 XSTR (symbol, 0) = ggc_strdup (newname);
33911 #endif /* HAVE_AS_TLS */
33912 #endif /* TARGET_XCOFF */
33915 rs6000_asm_weaken_decl (FILE *stream, tree decl,
33916 const char *name, const char *val)
33918 fputs ("\t.weak\t", stream);
33919 RS6000_OUTPUT_BASENAME (stream, name);
33920 if (decl && TREE_CODE (decl) == FUNCTION_DECL
33921 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
33924 fputs ("[DS]", stream);
33925 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33927 fputs (rs6000_xcoff_visibility (decl), stream);
33929 fputs ("\n\t.weak\t.", stream);
33930 RS6000_OUTPUT_BASENAME (stream, name);
33932 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33934 fputs (rs6000_xcoff_visibility (decl), stream);
33936 fputc ('\n', stream);
33939 #ifdef ASM_OUTPUT_DEF
33940 ASM_OUTPUT_DEF (stream, name, val);
33942 if (decl && TREE_CODE (decl) == FUNCTION_DECL
33943 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
33945 fputs ("\t.set\t.", stream);
33946 RS6000_OUTPUT_BASENAME (stream, name);
33947 fputs (",.", stream);
33948 RS6000_OUTPUT_BASENAME (stream, val);
33949 fputc ('\n', stream);
33955 /* Return true if INSN should not be copied. */
33958 rs6000_cannot_copy_insn_p (rtx_insn *insn)
33960 return recog_memoized (insn) >= 0
33961 && get_attr_cannot_copy (insn);
33964 /* Compute a (partial) cost for rtx X. Return true if the complete
33965 cost has been computed, and false if subexpressions should be
33966 scanned. In either case, *TOTAL contains the cost result. */
33969 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
33970 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
33972 int code = GET_CODE (x);
33976 /* On the RS/6000, if it is valid in the insn, it is free. */
33978 if (((outer_code == SET
33979 || outer_code == PLUS
33980 || outer_code == MINUS)
33981 && (satisfies_constraint_I (x)
33982 || satisfies_constraint_L (x)))
33983 || (outer_code == AND
33984 && (satisfies_constraint_K (x)
33986 ? satisfies_constraint_L (x)
33987 : satisfies_constraint_J (x))))
33988 || ((outer_code == IOR || outer_code == XOR)
33989 && (satisfies_constraint_K (x)
33991 ? satisfies_constraint_L (x)
33992 : satisfies_constraint_J (x))))
33993 || outer_code == ASHIFT
33994 || outer_code == ASHIFTRT
33995 || outer_code == LSHIFTRT
33996 || outer_code == ROTATE
33997 || outer_code == ROTATERT
33998 || outer_code == ZERO_EXTRACT
33999 || (outer_code == MULT
34000 && satisfies_constraint_I (x))
34001 || ((outer_code == DIV || outer_code == UDIV
34002 || outer_code == MOD || outer_code == UMOD)
34003 && exact_log2 (INTVAL (x)) >= 0)
34004 || (outer_code == COMPARE
34005 && (satisfies_constraint_I (x)
34006 || satisfies_constraint_K (x)))
34007 || ((outer_code == EQ || outer_code == NE)
34008 && (satisfies_constraint_I (x)
34009 || satisfies_constraint_K (x)
34011 ? satisfies_constraint_L (x)
34012 : satisfies_constraint_J (x))))
34013 || (outer_code == GTU
34014 && satisfies_constraint_I (x))
34015 || (outer_code == LTU
34016 && satisfies_constraint_P (x)))
34021 else if ((outer_code == PLUS
34022 && reg_or_add_cint_operand (x, VOIDmode))
34023 || (outer_code == MINUS
34024 && reg_or_sub_cint_operand (x, VOIDmode))
34025 || ((outer_code == SET
34026 || outer_code == IOR
34027 || outer_code == XOR)
34029 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34031 *total = COSTS_N_INSNS (1);
34037 case CONST_WIDE_INT:
34041 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34045 /* When optimizing for size, MEM should be slightly more expensive
34046 than generating address, e.g., (plus (reg) (const)).
34047 L1 cache latency is about two instructions. */
34048 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34049 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34050 *total += COSTS_N_INSNS (100);
34059 if (FLOAT_MODE_P (mode))
34060 *total = rs6000_cost->fp;
34062 *total = COSTS_N_INSNS (1);
34066 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34067 && satisfies_constraint_I (XEXP (x, 1)))
34069 if (INTVAL (XEXP (x, 1)) >= -256
34070 && INTVAL (XEXP (x, 1)) <= 255)
34071 *total = rs6000_cost->mulsi_const9;
34073 *total = rs6000_cost->mulsi_const;
34075 else if (mode == SFmode)
34076 *total = rs6000_cost->fp;
34077 else if (FLOAT_MODE_P (mode))
34078 *total = rs6000_cost->dmul;
34079 else if (mode == DImode)
34080 *total = rs6000_cost->muldi;
34082 *total = rs6000_cost->mulsi;
34086 if (mode == SFmode)
34087 *total = rs6000_cost->fp;
34089 *total = rs6000_cost->dmul;
34094 if (FLOAT_MODE_P (mode))
34096 *total = mode == DFmode ? rs6000_cost->ddiv
34097 : rs6000_cost->sdiv;
34104 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34105 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34107 if (code == DIV || code == MOD)
34109 *total = COSTS_N_INSNS (2);
34112 *total = COSTS_N_INSNS (1);
34116 if (GET_MODE (XEXP (x, 1)) == DImode)
34117 *total = rs6000_cost->divdi;
34119 *total = rs6000_cost->divsi;
34121 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34122 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34123 *total += COSTS_N_INSNS (2);
34127 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34131 *total = COSTS_N_INSNS (4);
34135 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34139 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34143 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34146 *total = COSTS_N_INSNS (1);
34150 if (CONST_INT_P (XEXP (x, 1)))
34152 rtx left = XEXP (x, 0);
34153 rtx_code left_code = GET_CODE (left);
34155 /* rotate-and-mask: 1 insn. */
34156 if ((left_code == ROTATE
34157 || left_code == ASHIFT
34158 || left_code == LSHIFTRT)
34159 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34161 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34162 if (!CONST_INT_P (XEXP (left, 1)))
34163 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34164 *total += COSTS_N_INSNS (1);
34168 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34169 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34170 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34171 || (val & 0xffff) == val
34172 || (val & 0xffff0000) == val
34173 || ((val & 0xffff) == 0 && mode == SImode))
34175 *total = rtx_cost (left, mode, AND, 0, speed);
34176 *total += COSTS_N_INSNS (1);
34181 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34183 *total = rtx_cost (left, mode, AND, 0, speed);
34184 *total += COSTS_N_INSNS (2);
34189 *total = COSTS_N_INSNS (1);
34194 *total = COSTS_N_INSNS (1);
34200 *total = COSTS_N_INSNS (1);
34204 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34205 the sign extend and shift separately within the insn. */
34206 if (TARGET_EXTSWSLI && mode == DImode
34207 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34208 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34219 /* Handle mul_highpart. */
34220 if (outer_code == TRUNCATE
34221 && GET_CODE (XEXP (x, 0)) == MULT)
34223 if (mode == DImode)
34224 *total = rs6000_cost->muldi;
34226 *total = rs6000_cost->mulsi;
34229 else if (outer_code == AND)
34232 *total = COSTS_N_INSNS (1);
34237 if (GET_CODE (XEXP (x, 0)) == MEM)
34240 *total = COSTS_N_INSNS (1);
34246 if (!FLOAT_MODE_P (mode))
34248 *total = COSTS_N_INSNS (1);
34254 case UNSIGNED_FLOAT:
34257 case FLOAT_TRUNCATE:
34258 *total = rs6000_cost->fp;
34262 if (mode == DFmode)
34263 *total = rs6000_cost->sfdf_convert;
34265 *total = rs6000_cost->fp;
34269 switch (XINT (x, 1))
34272 *total = rs6000_cost->fp;
34284 *total = COSTS_N_INSNS (1);
34287 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34289 *total = rs6000_cost->fp;
34298 /* Carry bit requires mode == Pmode.
34299 NEG or PLUS already counted so only add one. */
34301 && (outer_code == NEG || outer_code == PLUS))
34303 *total = COSTS_N_INSNS (1);
34311 if (outer_code == SET)
34313 if (XEXP (x, 1) == const0_rtx)
34315 *total = COSTS_N_INSNS (2);
34320 *total = COSTS_N_INSNS (3);
34325 if (outer_code == COMPARE)
34339 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34342 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34343 int opno, int *total, bool speed)
34345 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34348 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34349 "opno = %d, total = %d, speed = %s, x:\n",
34350 ret ? "complete" : "scan inner",
34351 GET_MODE_NAME (mode),
34352 GET_RTX_NAME (outer_code),
34355 speed ? "true" : "false");
34363 rs6000_insn_cost (rtx_insn *insn, bool speed)
34365 if (recog_memoized (insn) < 0)
34369 return get_attr_length (insn);
34371 int cost = get_attr_cost (insn);
34375 int n = get_attr_length (insn) / 4;
34376 enum attr_type type = get_attr_type (insn);
34383 cost = COSTS_N_INSNS (n + 1);
34387 switch (get_attr_size (insn))
34390 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34393 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34396 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34399 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34402 gcc_unreachable ();
34406 switch (get_attr_size (insn))
34409 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34412 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34415 gcc_unreachable ();
34420 cost = n * rs6000_cost->fp;
34423 cost = n * rs6000_cost->dmul;
34426 cost = n * rs6000_cost->sdiv;
34429 cost = n * rs6000_cost->ddiv;
34436 cost = COSTS_N_INSNS (n + 2);
34440 cost = COSTS_N_INSNS (n);
34446 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34449 rs6000_debug_address_cost (rtx x, machine_mode mode,
34450 addr_space_t as, bool speed)
34452 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34454 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34455 ret, speed ? "true" : "false");
34462 /* A C expression returning the cost of moving data from a register of class
34463 CLASS1 to one of CLASS2. */
34466 rs6000_register_move_cost (machine_mode mode,
34467 reg_class_t from, reg_class_t to)
34471 if (TARGET_DEBUG_COST)
34474 /* Moves from/to GENERAL_REGS. */
34475 if (reg_classes_intersect_p (to, GENERAL_REGS)
34476 || reg_classes_intersect_p (from, GENERAL_REGS))
34478 reg_class_t rclass = from;
34480 if (! reg_classes_intersect_p (to, GENERAL_REGS))
34483 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34484 ret = (rs6000_memory_move_cost (mode, rclass, false)
34485 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34487 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34489 else if (rclass == CR_REGS)
34492 /* For those processors that have slow LR/CTR moves, make them more
34493 expensive than memory in order to bias spills to memory .*/
34494 else if ((rs6000_tune == PROCESSOR_POWER6
34495 || rs6000_tune == PROCESSOR_POWER7
34496 || rs6000_tune == PROCESSOR_POWER8
34497 || rs6000_tune == PROCESSOR_POWER9)
34498 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
34499 ret = 6 * hard_regno_nregs (0, mode);
34502 /* A move will cost one instruction per GPR moved. */
34503 ret = 2 * hard_regno_nregs (0, mode);
34506 /* If we have VSX, we can easily move between FPR or Altivec registers. */
34507 else if (VECTOR_MEM_VSX_P (mode)
34508 && reg_classes_intersect_p (to, VSX_REGS)
34509 && reg_classes_intersect_p (from, VSX_REGS))
34510 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
34512 /* Moving between two similar registers is just one instruction. */
34513 else if (reg_classes_intersect_p (to, from))
34514 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
34516 /* Everything else has to go through GENERAL_REGS. */
34518 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34519 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34521 if (TARGET_DEBUG_COST)
34523 if (dbg_cost_ctrl == 1)
34525 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
34526 ret, GET_MODE_NAME (mode), reg_class_names[from],
34527 reg_class_names[to]);
34534 /* A C expressions returning the cost of moving data of MODE from a register to
34538 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34539 bool in ATTRIBUTE_UNUSED)
34543 if (TARGET_DEBUG_COST)
34546 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34547 ret = 4 * hard_regno_nregs (0, mode);
34548 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34549 || reg_classes_intersect_p (rclass, VSX_REGS)))
34550 ret = 4 * hard_regno_nregs (32, mode);
34551 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34552 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34554 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34556 if (TARGET_DEBUG_COST)
34558 if (dbg_cost_ctrl == 1)
34560 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34561 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34568 /* Returns a code for a target-specific builtin that implements
34569 reciprocal of the function, or NULL_TREE if not available. */
34572 rs6000_builtin_reciprocal (tree fndecl)
34574 switch (DECL_FUNCTION_CODE (fndecl))
34576 case VSX_BUILTIN_XVSQRTDP:
34577 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34580 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34582 case VSX_BUILTIN_XVSQRTSP:
34583 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34586 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34593 /* Load up a constant. If the mode is a vector mode, splat the value across
34594 all of the vector elements. */
34597 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34601 if (mode == SFmode || mode == DFmode)
34603 rtx d = const_double_from_real_value (dconst, mode);
34604 reg = force_reg (mode, d);
34606 else if (mode == V4SFmode)
34608 rtx d = const_double_from_real_value (dconst, SFmode);
34609 rtvec v = gen_rtvec (4, d, d, d, d);
34610 reg = gen_reg_rtx (mode);
34611 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34613 else if (mode == V2DFmode)
34615 rtx d = const_double_from_real_value (dconst, DFmode);
34616 rtvec v = gen_rtvec (2, d, d);
34617 reg = gen_reg_rtx (mode);
34618 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34621 gcc_unreachable ();
34626 /* Generate an FMA instruction. */
34629 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
34631 machine_mode mode = GET_MODE (target);
34634 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
34635 gcc_assert (dst != NULL);
34638 emit_move_insn (target, dst);
34641 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34644 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
34646 machine_mode mode = GET_MODE (dst);
34649 /* This is a tad more complicated, since the fnma_optab is for
34650 a different expression: fma(-m1, m2, a), which is the same
34651 thing except in the case of signed zeros.
34653 Fortunately we know that if FMA is supported that FNMSUB is
34654 also supported in the ISA. Just expand it directly. */
34656 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
34658 r = gen_rtx_NEG (mode, a);
34659 r = gen_rtx_FMA (mode, m1, m2, r);
34660 r = gen_rtx_NEG (mode, r);
34661 emit_insn (gen_rtx_SET (dst, r));
34664 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34665 add a reg_note saying that this was a division. Support both scalar and
34666 vector divide. Assumes no trapping math and finite arguments. */
34669 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
34671 machine_mode mode = GET_MODE (dst);
34672 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
34675 /* Low precision estimates guarantee 5 bits of accuracy. High
34676 precision estimates guarantee 14 bits of accuracy. SFmode
34677 requires 23 bits of accuracy. DFmode requires 52 bits of
34678 accuracy. Each pass at least doubles the accuracy, leading
34679 to the following. */
34680 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34681 if (mode == DFmode || mode == V2DFmode)
34684 enum insn_code code = optab_handler (smul_optab, mode);
34685 insn_gen_fn gen_mul = GEN_FCN (code);
34687 gcc_assert (code != CODE_FOR_nothing);
34689 one = rs6000_load_constant_and_splat (mode, dconst1);
34691 /* x0 = 1./d estimate */
34692 x0 = gen_reg_rtx (mode);
34693 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
34696 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34699 /* e0 = 1. - d * x0 */
34700 e0 = gen_reg_rtx (mode);
34701 rs6000_emit_nmsub (e0, d, x0, one);
34703 /* x1 = x0 + e0 * x0 */
34704 x1 = gen_reg_rtx (mode);
34705 rs6000_emit_madd (x1, e0, x0, x0);
34707 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
34708 ++i, xprev = xnext, eprev = enext) {
34710 /* enext = eprev * eprev */
34711 enext = gen_reg_rtx (mode);
34712 emit_insn (gen_mul (enext, eprev, eprev));
34714 /* xnext = xprev + enext * xprev */
34715 xnext = gen_reg_rtx (mode);
34716 rs6000_emit_madd (xnext, enext, xprev, xprev);
34722 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34724 /* u = n * xprev */
34725 u = gen_reg_rtx (mode);
34726 emit_insn (gen_mul (u, n, xprev));
34728 /* v = n - (d * u) */
34729 v = gen_reg_rtx (mode);
34730 rs6000_emit_nmsub (v, d, u, n);
34732 /* dst = (v * xprev) + u */
34733 rs6000_emit_madd (dst, v, xprev, u);
34736 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
34739 /* Goldschmidt's Algorithm for single/double-precision floating point
34740 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34743 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
34745 machine_mode mode = GET_MODE (src);
34746 rtx e = gen_reg_rtx (mode);
34747 rtx g = gen_reg_rtx (mode);
34748 rtx h = gen_reg_rtx (mode);
34750 /* Low precision estimates guarantee 5 bits of accuracy. High
34751 precision estimates guarantee 14 bits of accuracy. SFmode
34752 requires 23 bits of accuracy. DFmode requires 52 bits of
34753 accuracy. Each pass at least doubles the accuracy, leading
34754 to the following. */
34755 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34756 if (mode == DFmode || mode == V2DFmode)
34761 enum insn_code code = optab_handler (smul_optab, mode);
34762 insn_gen_fn gen_mul = GEN_FCN (code);
34764 gcc_assert (code != CODE_FOR_nothing);
34766 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
34768 /* e = rsqrt estimate */
34769 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
34772 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
34775 rtx zero = force_reg (mode, CONST0_RTX (mode));
34777 if (mode == SFmode)
34779 rtx target = emit_conditional_move (e, GT, src, zero, mode,
34782 emit_move_insn (e, target);
34786 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
34787 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
34791 /* g = sqrt estimate. */
34792 emit_insn (gen_mul (g, e, src));
34793 /* h = 1/(2*sqrt) estimate. */
34794 emit_insn (gen_mul (h, e, mhalf));
34800 rtx t = gen_reg_rtx (mode);
34801 rs6000_emit_nmsub (t, g, h, mhalf);
34802 /* Apply correction directly to 1/rsqrt estimate. */
34803 rs6000_emit_madd (dst, e, t, e);
34807 for (i = 0; i < passes; i++)
34809 rtx t1 = gen_reg_rtx (mode);
34810 rtx g1 = gen_reg_rtx (mode);
34811 rtx h1 = gen_reg_rtx (mode);
34813 rs6000_emit_nmsub (t1, g, h, mhalf);
34814 rs6000_emit_madd (g1, g, t1, g);
34815 rs6000_emit_madd (h1, h, t1, h);
34820 /* Multiply by 2 for 1/rsqrt. */
34821 emit_insn (gen_add3_insn (dst, h, h));
34826 rtx t = gen_reg_rtx (mode);
34827 rs6000_emit_nmsub (t, g, h, mhalf);
34828 rs6000_emit_madd (dst, g, t, g);
34834 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
34835 (Power7) targets. DST is the target, and SRC is the argument operand. */
34838 rs6000_emit_popcount (rtx dst, rtx src)
34840 machine_mode mode = GET_MODE (dst);
34843 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
34844 if (TARGET_POPCNTD)
34846 if (mode == SImode)
34847 emit_insn (gen_popcntdsi2 (dst, src));
34849 emit_insn (gen_popcntddi2 (dst, src));
34853 tmp1 = gen_reg_rtx (mode);
34855 if (mode == SImode)
34857 emit_insn (gen_popcntbsi2 (tmp1, src));
34858 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
34860 tmp2 = force_reg (SImode, tmp2);
34861 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
34865 emit_insn (gen_popcntbdi2 (tmp1, src));
34866 tmp2 = expand_mult (DImode, tmp1,
34867 GEN_INT ((HOST_WIDE_INT)
34868 0x01010101 << 32 | 0x01010101),
34870 tmp2 = force_reg (DImode, tmp2);
34871 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
34876 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
34877 target, and SRC is the argument operand. */
34880 rs6000_emit_parity (rtx dst, rtx src)
34882 machine_mode mode = GET_MODE (dst);
34885 tmp = gen_reg_rtx (mode);
34887 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
34890 if (mode == SImode)
34892 emit_insn (gen_popcntbsi2 (tmp, src));
34893 emit_insn (gen_paritysi2_cmpb (dst, tmp));
34897 emit_insn (gen_popcntbdi2 (tmp, src));
34898 emit_insn (gen_paritydi2_cmpb (dst, tmp));
34903 if (mode == SImode)
34905 /* Is mult+shift >= shift+xor+shift+xor? */
34906 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
34908 rtx tmp1, tmp2, tmp3, tmp4;
34910 tmp1 = gen_reg_rtx (SImode);
34911 emit_insn (gen_popcntbsi2 (tmp1, src));
34913 tmp2 = gen_reg_rtx (SImode);
34914 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
34915 tmp3 = gen_reg_rtx (SImode);
34916 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
34918 tmp4 = gen_reg_rtx (SImode);
34919 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
34920 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
34923 rs6000_emit_popcount (tmp, src);
34924 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
34928 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
34929 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
34931 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
34933 tmp1 = gen_reg_rtx (DImode);
34934 emit_insn (gen_popcntbdi2 (tmp1, src));
34936 tmp2 = gen_reg_rtx (DImode);
34937 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
34938 tmp3 = gen_reg_rtx (DImode);
34939 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
34941 tmp4 = gen_reg_rtx (DImode);
34942 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
34943 tmp5 = gen_reg_rtx (DImode);
34944 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
34946 tmp6 = gen_reg_rtx (DImode);
34947 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
34948 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
34951 rs6000_emit_popcount (tmp, src);
34952 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
34956 /* Expand an Altivec constant permutation for little endian mode.
34957 OP0 and OP1 are the input vectors and TARGET is the output vector.
34958 SEL specifies the constant permutation vector.
34960 There are two issues: First, the two input operands must be
34961 swapped so that together they form a double-wide array in LE
34962 order. Second, the vperm instruction has surprising behavior
34963 in LE mode: it interprets the elements of the source vectors
34964 in BE mode ("left to right") and interprets the elements of
34965 the destination vector in LE mode ("right to left"). To
34966 correct for this, we must subtract each element of the permute
34967 control vector from 31.
34969 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
34970 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
34971 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
34972 serve as the permute control vector. Then, in BE mode,
34976 places the desired result in vr9. However, in LE mode the
34977 vector contents will be
34979 vr10 = 00000003 00000002 00000001 00000000
34980 vr11 = 00000007 00000006 00000005 00000004
34982 The result of the vperm using the same permute control vector is
34984 vr9 = 05000000 07000000 01000000 03000000
34986 That is, the leftmost 4 bytes of vr10 are interpreted as the
34987 source for the rightmost 4 bytes of vr9, and so on.
34989 If we change the permute control vector to
34991 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
34999 vr9 = 00000006 00000004 00000002 00000000. */
35002 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35003 const vec_perm_indices &sel)
35007 rtx constv, unspec;
35009 /* Unpack and adjust the constant selector. */
35010 for (i = 0; i < 16; ++i)
35012 unsigned int elt = 31 - (sel[i] & 31);
35013 perm[i] = GEN_INT (elt);
35016 /* Expand to a permute, swapping the inputs and using the
35017 adjusted selector. */
35019 op0 = force_reg (V16QImode, op0);
35021 op1 = force_reg (V16QImode, op1);
35023 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35024 constv = force_reg (V16QImode, constv);
35025 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35027 if (!REG_P (target))
35029 rtx tmp = gen_reg_rtx (V16QImode);
35030 emit_move_insn (tmp, unspec);
35034 emit_move_insn (target, unspec);
35037 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35038 permute control vector. But here it's not a constant, so we must
35039 generate a vector NAND or NOR to do the adjustment. */
35042 altivec_expand_vec_perm_le (rtx operands[4])
35044 rtx notx, iorx, unspec;
35045 rtx target = operands[0];
35046 rtx op0 = operands[1];
35047 rtx op1 = operands[2];
35048 rtx sel = operands[3];
35050 rtx norreg = gen_reg_rtx (V16QImode);
35051 machine_mode mode = GET_MODE (target);
35053 /* Get everything in regs so the pattern matches. */
35055 op0 = force_reg (mode, op0);
35057 op1 = force_reg (mode, op1);
35059 sel = force_reg (V16QImode, sel);
35060 if (!REG_P (target))
35061 tmp = gen_reg_rtx (mode);
35063 if (TARGET_P9_VECTOR)
35065 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35070 /* Invert the selector with a VNAND if available, else a VNOR.
35071 The VNAND is preferred for future fusion opportunities. */
35072 notx = gen_rtx_NOT (V16QImode, sel);
35073 iorx = (TARGET_P8_VECTOR
35074 ? gen_rtx_IOR (V16QImode, notx, notx)
35075 : gen_rtx_AND (V16QImode, notx, notx));
35076 emit_insn (gen_rtx_SET (norreg, iorx));
35078 /* Permute with operands reversed and adjusted selector. */
35079 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35083 /* Copy into target, possibly by way of a register. */
35084 if (!REG_P (target))
35086 emit_move_insn (tmp, unspec);
35090 emit_move_insn (target, unspec);
35093 /* Expand an Altivec constant permutation. Return true if we match
35094 an efficient implementation; false to fall back to VPERM.
35096 OP0 and OP1 are the input vectors and TARGET is the output vector.
35097 SEL specifies the constant permutation vector. */
35100 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35101 const vec_perm_indices &sel)
35103 struct altivec_perm_insn {
35104 HOST_WIDE_INT mask;
35105 enum insn_code impl;
35106 unsigned char perm[16];
35108 static const struct altivec_perm_insn patterns[] = {
35109 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35110 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35111 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35112 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35113 { OPTION_MASK_ALTIVEC,
35114 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35115 : CODE_FOR_altivec_vmrglb_direct),
35116 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35117 { OPTION_MASK_ALTIVEC,
35118 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35119 : CODE_FOR_altivec_vmrglh_direct),
35120 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35121 { OPTION_MASK_ALTIVEC,
35122 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35123 : CODE_FOR_altivec_vmrglw_direct),
35124 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35125 { OPTION_MASK_ALTIVEC,
35126 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35127 : CODE_FOR_altivec_vmrghb_direct),
35128 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35129 { OPTION_MASK_ALTIVEC,
35130 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35131 : CODE_FOR_altivec_vmrghh_direct),
35132 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35133 { OPTION_MASK_ALTIVEC,
35134 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35135 : CODE_FOR_altivec_vmrghw_direct),
35136 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35137 { OPTION_MASK_P8_VECTOR,
35138 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35139 : CODE_FOR_p8_vmrgow_v4sf_direct),
35140 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35141 { OPTION_MASK_P8_VECTOR,
35142 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35143 : CODE_FOR_p8_vmrgew_v4sf_direct),
35144 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35147 unsigned int i, j, elt, which;
35148 unsigned char perm[16];
35152 /* Unpack the constant selector. */
35153 for (i = which = 0; i < 16; ++i)
35156 which |= (elt < 16 ? 1 : 2);
35160 /* Simplify the constant selector based on operands. */
35164 gcc_unreachable ();
35168 if (!rtx_equal_p (op0, op1))
35173 for (i = 0; i < 16; ++i)
35185 /* Look for splat patterns. */
35190 for (i = 0; i < 16; ++i)
35191 if (perm[i] != elt)
35195 if (!BYTES_BIG_ENDIAN)
35197 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35203 for (i = 0; i < 16; i += 2)
35204 if (perm[i] != elt || perm[i + 1] != elt + 1)
35208 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35209 x = gen_reg_rtx (V8HImode);
35210 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35212 emit_move_insn (target, gen_lowpart (V16QImode, x));
35219 for (i = 0; i < 16; i += 4)
35221 || perm[i + 1] != elt + 1
35222 || perm[i + 2] != elt + 2
35223 || perm[i + 3] != elt + 3)
35227 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35228 x = gen_reg_rtx (V4SImode);
35229 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35231 emit_move_insn (target, gen_lowpart (V16QImode, x));
35237 /* Look for merge and pack patterns. */
35238 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35242 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35245 elt = patterns[j].perm[0];
35246 if (perm[0] == elt)
35248 else if (perm[0] == elt + 16)
35252 for (i = 1; i < 16; ++i)
35254 elt = patterns[j].perm[i];
35256 elt = (elt >= 16 ? elt - 16 : elt + 16);
35257 else if (one_vec && elt >= 16)
35259 if (perm[i] != elt)
35264 enum insn_code icode = patterns[j].impl;
35265 machine_mode omode = insn_data[icode].operand[0].mode;
35266 machine_mode imode = insn_data[icode].operand[1].mode;
35268 /* For little-endian, don't use vpkuwum and vpkuhum if the
35269 underlying vector type is not V4SI and V8HI, respectively.
35270 For example, using vpkuwum with a V8HI picks up the even
35271 halfwords (BE numbering) when the even halfwords (LE
35272 numbering) are what we need. */
35273 if (!BYTES_BIG_ENDIAN
35274 && icode == CODE_FOR_altivec_vpkuwum_direct
35275 && ((GET_CODE (op0) == REG
35276 && GET_MODE (op0) != V4SImode)
35277 || (GET_CODE (op0) == SUBREG
35278 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35280 if (!BYTES_BIG_ENDIAN
35281 && icode == CODE_FOR_altivec_vpkuhum_direct
35282 && ((GET_CODE (op0) == REG
35283 && GET_MODE (op0) != V8HImode)
35284 || (GET_CODE (op0) == SUBREG
35285 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35288 /* For little-endian, the two input operands must be swapped
35289 (or swapped back) to ensure proper right-to-left numbering
35291 if (swapped ^ !BYTES_BIG_ENDIAN)
35292 std::swap (op0, op1);
35293 if (imode != V16QImode)
35295 op0 = gen_lowpart (imode, op0);
35296 op1 = gen_lowpart (imode, op1);
35298 if (omode == V16QImode)
35301 x = gen_reg_rtx (omode);
35302 emit_insn (GEN_FCN (icode) (x, op0, op1));
35303 if (omode != V16QImode)
35304 emit_move_insn (target, gen_lowpart (V16QImode, x));
35309 if (!BYTES_BIG_ENDIAN)
35311 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35318 /* Expand a VSX Permute Doubleword constant permutation.
35319 Return true if we match an efficient implementation. */
35322 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35323 unsigned char perm0, unsigned char perm1)
35327 /* If both selectors come from the same operand, fold to single op. */
35328 if ((perm0 & 2) == (perm1 & 2))
35335 /* If both operands are equal, fold to simpler permutation. */
35336 if (rtx_equal_p (op0, op1))
35339 perm1 = (perm1 & 1) + 2;
35341 /* If the first selector comes from the second operand, swap. */
35342 else if (perm0 & 2)
35348 std::swap (op0, op1);
35350 /* If the second selector does not come from the second operand, fail. */
35351 else if ((perm1 & 2) == 0)
35355 if (target != NULL)
35357 machine_mode vmode, dmode;
35360 vmode = GET_MODE (target);
35361 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35362 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35363 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35364 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35365 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35366 emit_insn (gen_rtx_SET (target, x));
35371 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35374 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35375 rtx op1, const vec_perm_indices &sel)
35377 bool testing_p = !target;
35379 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35380 if (TARGET_ALTIVEC && testing_p)
35383 /* Check for ps_merge* or xxpermdi insns. */
35384 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35388 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35389 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35391 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35395 if (TARGET_ALTIVEC)
35397 /* Force the target-independent code to lower to V16QImode. */
35398 if (vmode != V16QImode)
35400 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35407 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35408 OP0 and OP1 are the input vectors and TARGET is the output vector.
35409 PERM specifies the constant permutation vector. */
35412 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35413 machine_mode vmode, const vec_perm_builder &perm)
35415 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35417 emit_move_insn (target, x);
35420 /* Expand an extract even operation. */
35423 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35425 machine_mode vmode = GET_MODE (target);
35426 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35427 vec_perm_builder perm (nelt, nelt, 1);
35429 for (i = 0; i < nelt; i++)
35430 perm.quick_push (i * 2);
35432 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35435 /* Expand a vector interleave operation. */
35438 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35440 machine_mode vmode = GET_MODE (target);
35441 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35442 vec_perm_builder perm (nelt, nelt, 1);
35444 high = (highp ? 0 : nelt / 2);
35445 for (i = 0; i < nelt / 2; i++)
35447 perm.quick_push (i + high);
35448 perm.quick_push (i + nelt + high);
35451 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35454 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35456 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35458 HOST_WIDE_INT hwi_scale (scale);
35459 REAL_VALUE_TYPE r_pow;
35460 rtvec v = rtvec_alloc (2);
35462 rtx scale_vec = gen_reg_rtx (V2DFmode);
35463 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35464 elt = const_double_from_real_value (r_pow, DFmode);
35465 RTVEC_ELT (v, 0) = elt;
35466 RTVEC_ELT (v, 1) = elt;
35467 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35468 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35471 /* Return an RTX representing where to find the function value of a
35472 function returning MODE. */
35474 rs6000_complex_function_value (machine_mode mode)
35476 unsigned int regno;
35478 machine_mode inner = GET_MODE_INNER (mode);
35479 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35481 if (TARGET_FLOAT128_TYPE
35483 || (mode == TCmode && TARGET_IEEEQUAD)))
35484 regno = ALTIVEC_ARG_RETURN;
35486 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35487 regno = FP_ARG_RETURN;
35491 regno = GP_ARG_RETURN;
35493 /* 32-bit is OK since it'll go in r3/r4. */
35494 if (TARGET_32BIT && inner_bytes >= 4)
35495 return gen_rtx_REG (mode, regno);
35498 if (inner_bytes >= 8)
35499 return gen_rtx_REG (mode, regno);
35501 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35503 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35504 GEN_INT (inner_bytes));
35505 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35508 /* Return an rtx describing a return value of MODE as a PARALLEL
35509 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35510 stride REG_STRIDE. */
35513 rs6000_parallel_return (machine_mode mode,
35514 int n_elts, machine_mode elt_mode,
35515 unsigned int regno, unsigned int reg_stride)
35517 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35520 for (i = 0; i < n_elts; i++)
35522 rtx r = gen_rtx_REG (elt_mode, regno);
35523 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35524 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35525 regno += reg_stride;
35531 /* Target hook for TARGET_FUNCTION_VALUE.
35533 An integer value is in r3 and a floating-point value is in fp1,
35534 unless -msoft-float. */
35537 rs6000_function_value (const_tree valtype,
35538 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35539 bool outgoing ATTRIBUTE_UNUSED)
35542 unsigned int regno;
35543 machine_mode elt_mode;
35546 /* Special handling for structs in darwin64. */
35548 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35550 CUMULATIVE_ARGS valcum;
35554 valcum.fregno = FP_ARG_MIN_REG;
35555 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35556 /* Do a trial code generation as if this were going to be passed as
35557 an argument; if any part goes in memory, we return NULL. */
35558 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35561 /* Otherwise fall through to standard ABI rules. */
35564 mode = TYPE_MODE (valtype);
35566 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35567 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35569 int first_reg, n_regs;
35571 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35573 /* _Decimal128 must use even/odd register pairs. */
35574 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35575 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35579 first_reg = ALTIVEC_ARG_RETURN;
35583 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35586 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35587 if (TARGET_32BIT && TARGET_POWERPC64)
35596 int count = GET_MODE_SIZE (mode) / 4;
35597 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35600 if ((INTEGRAL_TYPE_P (valtype)
35601 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35602 || POINTER_TYPE_P (valtype))
35603 mode = TARGET_32BIT ? SImode : DImode;
35605 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35606 /* _Decimal128 must use an even/odd register pair. */
35607 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35608 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
35609 && !FLOAT128_VECTOR_P (mode))
35610 regno = FP_ARG_RETURN;
35611 else if (TREE_CODE (valtype) == COMPLEX_TYPE
35612 && targetm.calls.split_complex_arg)
35613 return rs6000_complex_function_value (mode);
35614 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35615 return register is used in both cases, and we won't see V2DImode/V2DFmode
35616 for pure altivec, combine the two cases. */
35617 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
35618 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
35619 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
35620 regno = ALTIVEC_ARG_RETURN;
35622 regno = GP_ARG_RETURN;
35624 return gen_rtx_REG (mode, regno);
35627 /* Define how to find the value returned by a library function
35628 assuming the value has mode MODE. */
35630 rs6000_libcall_value (machine_mode mode)
35632 unsigned int regno;
35634 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35635 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
35636 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
35638 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35639 /* _Decimal128 must use an even/odd register pair. */
35640 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35641 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
35642 regno = FP_ARG_RETURN;
35643 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35644 return register is used in both cases, and we won't see V2DImode/V2DFmode
35645 for pure altivec, combine the two cases. */
35646 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
35647 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
35648 regno = ALTIVEC_ARG_RETURN;
35649 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
35650 return rs6000_complex_function_value (mode);
35652 regno = GP_ARG_RETURN;
35654 return gen_rtx_REG (mode, regno);
35657 /* Compute register pressure classes. We implement the target hook to avoid
35658 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
35659 lead to incorrect estimates of number of available registers and therefor
35660 increased register pressure/spill. */
35662 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
35667 pressure_classes[n++] = GENERAL_REGS;
35669 pressure_classes[n++] = VSX_REGS;
35672 if (TARGET_ALTIVEC)
35673 pressure_classes[n++] = ALTIVEC_REGS;
35674 if (TARGET_HARD_FLOAT)
35675 pressure_classes[n++] = FLOAT_REGS;
35677 pressure_classes[n++] = CR_REGS;
35678 pressure_classes[n++] = SPECIAL_REGS;
35683 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35684 Frame pointer elimination is automatically handled.
35686 For the RS/6000, if frame pointer elimination is being done, we would like
35687 to convert ap into fp, not sp.
35689 We need r30 if -mminimal-toc was specified, and there are constant pool
35693 rs6000_can_eliminate (const int from, const int to)
35695 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
35696 ? ! frame_pointer_needed
35697 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
35698 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
35699 || constant_pool_empty_p ()
35703 /* Define the offset between two registers, FROM to be eliminated and its
35704 replacement TO, at the start of a routine. */
35706 rs6000_initial_elimination_offset (int from, int to)
35708 rs6000_stack_t *info = rs6000_stack_info ();
35709 HOST_WIDE_INT offset;
35711 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35712 offset = info->push_p ? 0 : -info->total_size;
35713 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35715 offset = info->push_p ? 0 : -info->total_size;
35716 if (FRAME_GROWS_DOWNWARD)
35717 offset += info->fixed_size + info->vars_size + info->parm_size;
35719 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35720 offset = FRAME_GROWS_DOWNWARD
35721 ? info->fixed_size + info->vars_size + info->parm_size
35723 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35724 offset = info->total_size;
35725 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35726 offset = info->push_p ? info->total_size : 0;
35727 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
35730 gcc_unreachable ();
35735 /* Fill in sizes of registers used by unwinder. */
35738 rs6000_init_dwarf_reg_sizes_extra (tree address)
35740 if (TARGET_MACHO && ! TARGET_ALTIVEC)
35743 machine_mode mode = TYPE_MODE (char_type_node);
35744 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
35745 rtx mem = gen_rtx_MEM (BLKmode, addr);
35746 rtx value = gen_int_mode (16, mode);
35748 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35749 The unwinder still needs to know the size of Altivec registers. */
35751 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
35753 int column = DWARF_REG_TO_UNWIND_COLUMN
35754 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
35755 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
35757 emit_move_insn (adjust_address (mem, mode, offset), value);
35762 /* Map internal gcc register numbers to debug format register numbers.
35763 FORMAT specifies the type of debug register number to use:
35764 0 -- debug information, except for frame-related sections
35765 1 -- DWARF .debug_frame section
35766 2 -- DWARF .eh_frame section */
35769 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
35771 /* Except for the above, we use the internal number for non-DWARF
35772 debug information, and also for .eh_frame. */
35773 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
35776 /* On some platforms, we use the standard DWARF register
35777 numbering for .debug_info and .debug_frame. */
35778 #ifdef RS6000_USE_DWARF_NUMBERING
35781 if (regno == LR_REGNO)
35783 if (regno == CTR_REGNO)
35785 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
35786 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
35787 The actual code emitted saves the whole of CR, so we map CR2_REGNO
35788 to the DWARF reg for CR. */
35789 if (format == 1 && regno == CR2_REGNO)
35791 if (CR_REGNO_P (regno))
35792 return regno - CR0_REGNO + 86;
35793 if (regno == CA_REGNO)
35794 return 101; /* XER */
35795 if (ALTIVEC_REGNO_P (regno))
35796 return regno - FIRST_ALTIVEC_REGNO + 1124;
35797 if (regno == VRSAVE_REGNO)
35799 if (regno == VSCR_REGNO)
35805 /* target hook eh_return_filter_mode */
35806 static scalar_int_mode
35807 rs6000_eh_return_filter_mode (void)
35809 return TARGET_32BIT ? SImode : word_mode;
35812 /* Target hook for translate_mode_attribute. */
35813 static machine_mode
35814 rs6000_translate_mode_attribute (machine_mode mode)
35816 if ((FLOAT128_IEEE_P (mode)
35817 && ieee128_float_type_node == long_double_type_node)
35818 || (FLOAT128_IBM_P (mode)
35819 && ibm128_float_type_node == long_double_type_node))
35820 return COMPLEX_MODE_P (mode) ? E_TCmode : E_TFmode;
35824 /* Target hook for scalar_mode_supported_p. */
35826 rs6000_scalar_mode_supported_p (scalar_mode mode)
35828 /* -m32 does not support TImode. This is the default, from
35829 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
35830 same ABI as for -m32. But default_scalar_mode_supported_p allows
35831 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
35832 for -mpowerpc64. */
35833 if (TARGET_32BIT && mode == TImode)
35836 if (DECIMAL_FLOAT_MODE_P (mode))
35837 return default_decimal_float_supported_p ();
35838 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
35841 return default_scalar_mode_supported_p (mode);
35844 /* Target hook for vector_mode_supported_p. */
35846 rs6000_vector_mode_supported_p (machine_mode mode)
35848 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
35849 128-bit, the compiler might try to widen IEEE 128-bit to IBM
35851 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
35858 /* Target hook for floatn_mode. */
35859 static opt_scalar_float_mode
35860 rs6000_floatn_mode (int n, bool extended)
35870 if (TARGET_FLOAT128_TYPE)
35871 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35873 return opt_scalar_float_mode ();
35876 return opt_scalar_float_mode ();
35879 /* Those are the only valid _FloatNx types. */
35880 gcc_unreachable ();
35894 if (TARGET_FLOAT128_TYPE)
35895 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35897 return opt_scalar_float_mode ();
35900 return opt_scalar_float_mode ();
35906 /* Target hook for c_mode_for_suffix. */
35907 static machine_mode
35908 rs6000_c_mode_for_suffix (char suffix)
35910 if (TARGET_FLOAT128_TYPE)
35912 if (suffix == 'q' || suffix == 'Q')
35913 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
35915 /* At the moment, we are not defining a suffix for IBM extended double.
35916 If/when the default for -mabi=ieeelongdouble is changed, and we want
35917 to support __ibm128 constants in legacy library code, we may need to
35918 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
35919 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
35920 __float80 constants. */
35926 /* Target hook for invalid_arg_for_unprototyped_fn. */
35927 static const char *
35928 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
35930 return (!rs6000_darwin64_abi
35932 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
35933 && (funcdecl == NULL_TREE
35934 || (TREE_CODE (funcdecl) == FUNCTION_DECL
35935 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
35936 ? N_("AltiVec argument passed to unprototyped function")
35940 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
35941 setup by using __stack_chk_fail_local hidden function instead of
35942 calling __stack_chk_fail directly. Otherwise it is better to call
35943 __stack_chk_fail directly. */
35945 static tree ATTRIBUTE_UNUSED
35946 rs6000_stack_protect_fail (void)
35948 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
35949 ? default_hidden_stack_protect_fail ()
35950 : default_external_stack_protect_fail ();
35953 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
35956 static unsigned HOST_WIDE_INT
35957 rs6000_asan_shadow_offset (void)
35959 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
35963 /* Mask options that we want to support inside of attribute((target)) and
35964 #pragma GCC target operations. Note, we do not include things like
35965 64/32-bit, endianness, hard/soft floating point, etc. that would have
35966 different calling sequences. */
35968 struct rs6000_opt_mask {
35969 const char *name; /* option name */
35970 HOST_WIDE_INT mask; /* mask to set */
35971 bool invert; /* invert sense of mask */
35972 bool valid_target; /* option is a target option */
35975 static struct rs6000_opt_mask const rs6000_opt_masks[] =
35977 { "altivec", OPTION_MASK_ALTIVEC, false, true },
35978 { "cmpb", OPTION_MASK_CMPB, false, true },
35979 { "crypto", OPTION_MASK_CRYPTO, false, true },
35980 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
35981 { "dlmzb", OPTION_MASK_DLMZB, false, true },
35982 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
35984 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
35985 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
35986 { "fprnd", OPTION_MASK_FPRND, false, true },
35987 { "hard-dfp", OPTION_MASK_DFP, false, true },
35988 { "htm", OPTION_MASK_HTM, false, true },
35989 { "isel", OPTION_MASK_ISEL, false, true },
35990 { "mfcrf", OPTION_MASK_MFCRF, false, true },
35991 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
35992 { "modulo", OPTION_MASK_MODULO, false, true },
35993 { "mulhw", OPTION_MASK_MULHW, false, true },
35994 { "multiple", OPTION_MASK_MULTIPLE, false, true },
35995 { "popcntb", OPTION_MASK_POPCNTB, false, true },
35996 { "popcntd", OPTION_MASK_POPCNTD, false, true },
35997 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
35998 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
35999 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36000 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36001 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36002 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36003 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36004 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36005 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36006 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36007 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36008 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36009 { "string", 0, false, true },
36010 { "update", OPTION_MASK_NO_UPDATE, true , true },
36011 { "vsx", OPTION_MASK_VSX, false, true },
36012 #ifdef OPTION_MASK_64BIT
36014 { "aix64", OPTION_MASK_64BIT, false, false },
36015 { "aix32", OPTION_MASK_64BIT, true, false },
36017 { "64", OPTION_MASK_64BIT, false, false },
36018 { "32", OPTION_MASK_64BIT, true, false },
36021 #ifdef OPTION_MASK_EABI
36022 { "eabi", OPTION_MASK_EABI, false, false },
36024 #ifdef OPTION_MASK_LITTLE_ENDIAN
36025 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36026 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36028 #ifdef OPTION_MASK_RELOCATABLE
36029 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36031 #ifdef OPTION_MASK_STRICT_ALIGN
36032 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36034 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36035 { "string", 0, false, false },
36038 /* Builtin mask mapping for printing the flags. */
36039 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36041 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36042 { "vsx", RS6000_BTM_VSX, false, false },
36043 { "fre", RS6000_BTM_FRE, false, false },
36044 { "fres", RS6000_BTM_FRES, false, false },
36045 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36046 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36047 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36048 { "cell", RS6000_BTM_CELL, false, false },
36049 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36050 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36051 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36052 { "crypto", RS6000_BTM_CRYPTO, false, false },
36053 { "htm", RS6000_BTM_HTM, false, false },
36054 { "hard-dfp", RS6000_BTM_DFP, false, false },
36055 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36056 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36057 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
36058 { "float128", RS6000_BTM_FLOAT128, false, false },
36059 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36062 /* Option variables that we want to support inside attribute((target)) and
36063 #pragma GCC target operations. */
36065 struct rs6000_opt_var {
36066 const char *name; /* option name */
36067 size_t global_offset; /* offset of the option in global_options. */
36068 size_t target_offset; /* offset of the option in target options. */
36071 static struct rs6000_opt_var const rs6000_opt_vars[] =
36074 offsetof (struct gcc_options, x_TARGET_FRIZ),
36075 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36076 { "avoid-indexed-addresses",
36077 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36078 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36080 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36081 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36082 { "optimize-swaps",
36083 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36084 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36085 { "allow-movmisalign",
36086 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36087 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36089 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36090 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36092 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36093 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36094 { "align-branch-targets",
36095 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36096 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36098 offsetof (struct gcc_options, x_tls_markers),
36099 offsetof (struct cl_target_option, x_tls_markers), },
36101 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36102 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36104 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36105 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36106 { "speculate-indirect-jumps",
36107 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36108 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36111 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36112 parsing. Return true if there were no errors. */
36115 rs6000_inner_target_options (tree args, bool attr_p)
36119 if (args == NULL_TREE)
36122 else if (TREE_CODE (args) == STRING_CST)
36124 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36127 while ((q = strtok (p, ",")) != NULL)
36129 bool error_p = false;
36130 bool not_valid_p = false;
36131 const char *cpu_opt = NULL;
36134 if (strncmp (q, "cpu=", 4) == 0)
36136 int cpu_index = rs6000_cpu_name_lookup (q+4);
36137 if (cpu_index >= 0)
36138 rs6000_cpu_index = cpu_index;
36145 else if (strncmp (q, "tune=", 5) == 0)
36147 int tune_index = rs6000_cpu_name_lookup (q+5);
36148 if (tune_index >= 0)
36149 rs6000_tune_index = tune_index;
36159 bool invert = false;
36163 if (strncmp (r, "no-", 3) == 0)
36169 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36170 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36172 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36174 if (!rs6000_opt_masks[i].valid_target)
36175 not_valid_p = true;
36179 rs6000_isa_flags_explicit |= mask;
36181 /* VSX needs altivec, so -mvsx automagically sets
36182 altivec and disables -mavoid-indexed-addresses. */
36185 if (mask == OPTION_MASK_VSX)
36187 mask |= OPTION_MASK_ALTIVEC;
36188 TARGET_AVOID_XFORM = 0;
36192 if (rs6000_opt_masks[i].invert)
36196 rs6000_isa_flags &= ~mask;
36198 rs6000_isa_flags |= mask;
36203 if (error_p && !not_valid_p)
36205 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36206 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36208 size_t j = rs6000_opt_vars[i].global_offset;
36209 *((int *) ((char *)&global_options + j)) = !invert;
36211 not_valid_p = false;
36219 const char *eprefix, *esuffix;
36224 eprefix = "__attribute__((__target__(";
36229 eprefix = "#pragma GCC target ";
36234 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36236 else if (not_valid_p)
36237 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36239 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36244 else if (TREE_CODE (args) == TREE_LIST)
36248 tree value = TREE_VALUE (args);
36251 bool ret2 = rs6000_inner_target_options (value, attr_p);
36255 args = TREE_CHAIN (args);
36257 while (args != NULL_TREE);
36262 error ("attribute %<target%> argument not a string");
36269 /* Print out the target options as a list for -mdebug=target. */
36272 rs6000_debug_target_options (tree args, const char *prefix)
36274 if (args == NULL_TREE)
36275 fprintf (stderr, "%s<NULL>", prefix);
36277 else if (TREE_CODE (args) == STRING_CST)
36279 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36282 while ((q = strtok (p, ",")) != NULL)
36285 fprintf (stderr, "%s\"%s\"", prefix, q);
36290 else if (TREE_CODE (args) == TREE_LIST)
36294 tree value = TREE_VALUE (args);
36297 rs6000_debug_target_options (value, prefix);
36300 args = TREE_CHAIN (args);
36302 while (args != NULL_TREE);
36306 gcc_unreachable ();
36312 /* Hook to validate attribute((target("..."))). */
36315 rs6000_valid_attribute_p (tree fndecl,
36316 tree ARG_UNUSED (name),
36320 struct cl_target_option cur_target;
36323 tree new_target, new_optimize;
36324 tree func_optimize;
36326 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36328 if (TARGET_DEBUG_TARGET)
36330 tree tname = DECL_NAME (fndecl);
36331 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36333 fprintf (stderr, "function: %.*s\n",
36334 (int) IDENTIFIER_LENGTH (tname),
36335 IDENTIFIER_POINTER (tname));
36337 fprintf (stderr, "function: unknown\n");
36339 fprintf (stderr, "args:");
36340 rs6000_debug_target_options (args, " ");
36341 fprintf (stderr, "\n");
36344 fprintf (stderr, "flags: 0x%x\n", flags);
36346 fprintf (stderr, "--------------------\n");
36349 /* attribute((target("default"))) does nothing, beyond
36350 affecting multi-versioning. */
36351 if (TREE_VALUE (args)
36352 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36353 && TREE_CHAIN (args) == NULL_TREE
36354 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36357 old_optimize = build_optimization_node (&global_options);
36358 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36360 /* If the function changed the optimization levels as well as setting target
36361 options, start with the optimizations specified. */
36362 if (func_optimize && func_optimize != old_optimize)
36363 cl_optimization_restore (&global_options,
36364 TREE_OPTIMIZATION (func_optimize));
36366 /* The target attributes may also change some optimization flags, so update
36367 the optimization options if necessary. */
36368 cl_target_option_save (&cur_target, &global_options);
36369 rs6000_cpu_index = rs6000_tune_index = -1;
36370 ret = rs6000_inner_target_options (args, true);
36372 /* Set up any additional state. */
36375 ret = rs6000_option_override_internal (false);
36376 new_target = build_target_option_node (&global_options);
36381 new_optimize = build_optimization_node (&global_options);
36388 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36390 if (old_optimize != new_optimize)
36391 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36394 cl_target_option_restore (&global_options, &cur_target);
36396 if (old_optimize != new_optimize)
36397 cl_optimization_restore (&global_options,
36398 TREE_OPTIMIZATION (old_optimize));
36404 /* Hook to validate the current #pragma GCC target and set the state, and
36405 update the macros based on what was changed. If ARGS is NULL, then
36406 POP_TARGET is used to reset the options. */
36409 rs6000_pragma_target_parse (tree args, tree pop_target)
36411 tree prev_tree = build_target_option_node (&global_options);
36413 struct cl_target_option *prev_opt, *cur_opt;
36414 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36415 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36417 if (TARGET_DEBUG_TARGET)
36419 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36420 fprintf (stderr, "args:");
36421 rs6000_debug_target_options (args, " ");
36422 fprintf (stderr, "\n");
36426 fprintf (stderr, "pop_target:\n");
36427 debug_tree (pop_target);
36430 fprintf (stderr, "pop_target: <NULL>\n");
36432 fprintf (stderr, "--------------------\n");
36437 cur_tree = ((pop_target)
36439 : target_option_default_node);
36440 cl_target_option_restore (&global_options,
36441 TREE_TARGET_OPTION (cur_tree));
36445 rs6000_cpu_index = rs6000_tune_index = -1;
36446 if (!rs6000_inner_target_options (args, false)
36447 || !rs6000_option_override_internal (false)
36448 || (cur_tree = build_target_option_node (&global_options))
36451 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36452 fprintf (stderr, "invalid pragma\n");
36458 target_option_current_node = cur_tree;
36459 rs6000_activate_target_options (target_option_current_node);
36461 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36462 change the macros that are defined. */
36463 if (rs6000_target_modify_macros_ptr)
36465 prev_opt = TREE_TARGET_OPTION (prev_tree);
36466 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36467 prev_flags = prev_opt->x_rs6000_isa_flags;
36469 cur_opt = TREE_TARGET_OPTION (cur_tree);
36470 cur_flags = cur_opt->x_rs6000_isa_flags;
36471 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36473 diff_bumask = (prev_bumask ^ cur_bumask);
36474 diff_flags = (prev_flags ^ cur_flags);
36476 if ((diff_flags != 0) || (diff_bumask != 0))
36478 /* Delete old macros. */
36479 rs6000_target_modify_macros_ptr (false,
36480 prev_flags & diff_flags,
36481 prev_bumask & diff_bumask);
36483 /* Define new macros. */
36484 rs6000_target_modify_macros_ptr (true,
36485 cur_flags & diff_flags,
36486 cur_bumask & diff_bumask);
36494 /* Remember the last target of rs6000_set_current_function. */
36495 static GTY(()) tree rs6000_previous_fndecl;
36497 /* Restore target's globals from NEW_TREE and invalidate the
36498 rs6000_previous_fndecl cache. */
36501 rs6000_activate_target_options (tree new_tree)
36503 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36504 if (TREE_TARGET_GLOBALS (new_tree))
36505 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36506 else if (new_tree == target_option_default_node)
36507 restore_target_globals (&default_target_globals);
36509 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36510 rs6000_previous_fndecl = NULL_TREE;
36513 /* Establish appropriate back-end context for processing the function
36514 FNDECL. The argument might be NULL to indicate processing at top
36515 level, outside of any function scope. */
36517 rs6000_set_current_function (tree fndecl)
36519 if (TARGET_DEBUG_TARGET)
36521 fprintf (stderr, "\n==================== rs6000_set_current_function");
36524 fprintf (stderr, ", fndecl %s (%p)",
36525 (DECL_NAME (fndecl)
36526 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36527 : "<unknown>"), (void *)fndecl);
36529 if (rs6000_previous_fndecl)
36530 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36532 fprintf (stderr, "\n");
36535 /* Only change the context if the function changes. This hook is called
36536 several times in the course of compiling a function, and we don't want to
36537 slow things down too much or call target_reinit when it isn't safe. */
36538 if (fndecl == rs6000_previous_fndecl)
36542 if (rs6000_previous_fndecl == NULL_TREE)
36543 old_tree = target_option_current_node;
36544 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36545 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36547 old_tree = target_option_default_node;
36550 if (fndecl == NULL_TREE)
36552 if (old_tree != target_option_current_node)
36553 new_tree = target_option_current_node;
36555 new_tree = NULL_TREE;
36559 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36560 if (new_tree == NULL_TREE)
36561 new_tree = target_option_default_node;
36564 if (TARGET_DEBUG_TARGET)
36568 fprintf (stderr, "\nnew fndecl target specific options:\n");
36569 debug_tree (new_tree);
36574 fprintf (stderr, "\nold fndecl target specific options:\n");
36575 debug_tree (old_tree);
36578 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
36579 fprintf (stderr, "--------------------\n");
36582 if (new_tree && old_tree != new_tree)
36583 rs6000_activate_target_options (new_tree);
36586 rs6000_previous_fndecl = fndecl;
36590 /* Save the current options */
36593 rs6000_function_specific_save (struct cl_target_option *ptr,
36594 struct gcc_options *opts)
36596 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
36597 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
36600 /* Restore the current options */
36603 rs6000_function_specific_restore (struct gcc_options *opts,
36604 struct cl_target_option *ptr)
36607 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
36608 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
36609 (void) rs6000_option_override_internal (false);
36612 /* Print the current options */
36615 rs6000_function_specific_print (FILE *file, int indent,
36616 struct cl_target_option *ptr)
36618 rs6000_print_isa_options (file, indent, "Isa options set",
36619 ptr->x_rs6000_isa_flags);
36621 rs6000_print_isa_options (file, indent, "Isa options explicit",
36622 ptr->x_rs6000_isa_flags_explicit);
36625 /* Helper function to print the current isa or misc options on a line. */
36628 rs6000_print_options_internal (FILE *file,
36630 const char *string,
36631 HOST_WIDE_INT flags,
36632 const char *prefix,
36633 const struct rs6000_opt_mask *opts,
36634 size_t num_elements)
36637 size_t start_column = 0;
36639 size_t max_column = 120;
36640 size_t prefix_len = strlen (prefix);
36641 size_t comma_len = 0;
36642 const char *comma = "";
36645 start_column += fprintf (file, "%*s", indent, "");
36649 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
36653 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
36655 /* Print the various mask options. */
36656 cur_column = start_column;
36657 for (i = 0; i < num_elements; i++)
36659 bool invert = opts[i].invert;
36660 const char *name = opts[i].name;
36661 const char *no_str = "";
36662 HOST_WIDE_INT mask = opts[i].mask;
36663 size_t len = comma_len + prefix_len + strlen (name);
36667 if ((flags & mask) == 0)
36670 len += sizeof ("no-") - 1;
36678 if ((flags & mask) != 0)
36681 len += sizeof ("no-") - 1;
36688 if (cur_column > max_column)
36690 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
36691 cur_column = start_column + len;
36695 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
36697 comma_len = sizeof (", ") - 1;
36700 fputs ("\n", file);
36703 /* Helper function to print the current isa options on a line. */
36706 rs6000_print_isa_options (FILE *file, int indent, const char *string,
36707 HOST_WIDE_INT flags)
36709 rs6000_print_options_internal (file, indent, string, flags, "-m",
36710 &rs6000_opt_masks[0],
36711 ARRAY_SIZE (rs6000_opt_masks));
36715 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
36716 HOST_WIDE_INT flags)
36718 rs6000_print_options_internal (file, indent, string, flags, "",
36719 &rs6000_builtin_mask_names[0],
36720 ARRAY_SIZE (rs6000_builtin_mask_names));
36723 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36724 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36725 -mupper-regs-df, etc.).
36727 If the user used -mno-power8-vector, we need to turn off all of the implicit
36728 ISA 2.07 and 3.0 options that relate to the vector unit.
36730 If the user used -mno-power9-vector, we need to turn off all of the implicit
36731 ISA 3.0 options that relate to the vector unit.
36733 This function does not handle explicit options such as the user specifying
36734 -mdirect-move. These are handled in rs6000_option_override_internal, and
36735 the appropriate error is given if needed.
36737 We return a mask of all of the implicit options that should not be enabled
36740 static HOST_WIDE_INT
36741 rs6000_disable_incompatible_switches (void)
36743 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
36746 static const struct {
36747 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
36748 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
36749 const char *const name; /* name of the switch. */
36751 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
36752 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
36753 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
36756 for (i = 0; i < ARRAY_SIZE (flags); i++)
36758 HOST_WIDE_INT no_flag = flags[i].no_flag;
36760 if ((rs6000_isa_flags & no_flag) == 0
36761 && (rs6000_isa_flags_explicit & no_flag) != 0)
36763 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
36764 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
36770 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
36771 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
36773 set_flags &= ~rs6000_opt_masks[j].mask;
36774 error ("%<-mno-%s%> turns off %<-m%s%>",
36776 rs6000_opt_masks[j].name);
36779 gcc_assert (!set_flags);
36782 rs6000_isa_flags &= ~dep_flags;
36783 ignore_masks |= no_flag | dep_flags;
36787 return ignore_masks;
36791 /* Helper function for printing the function name when debugging. */
36793 static const char *
36794 get_decl_name (tree fn)
36801 name = DECL_NAME (fn);
36803 return "<no-name>";
36805 return IDENTIFIER_POINTER (name);
36808 /* Return the clone id of the target we are compiling code for in a target
36809 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
36810 the priority list for the target clones (ordered from lowest to
36814 rs6000_clone_priority (tree fndecl)
36816 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36817 HOST_WIDE_INT isa_masks;
36818 int ret = CLONE_DEFAULT;
36819 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
36820 const char *attrs_str = NULL;
36822 attrs = TREE_VALUE (TREE_VALUE (attrs));
36823 attrs_str = TREE_STRING_POINTER (attrs);
36825 /* Return priority zero for default function. Return the ISA needed for the
36826 function if it is not the default. */
36827 if (strcmp (attrs_str, "default") != 0)
36829 if (fn_opts == NULL_TREE)
36830 fn_opts = target_option_default_node;
36832 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
36833 isa_masks = rs6000_isa_flags;
36835 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
36837 for (ret = CLONE_MAX - 1; ret != 0; ret--)
36838 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
36842 if (TARGET_DEBUG_TARGET)
36843 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
36844 get_decl_name (fndecl), ret);
36849 /* This compares the priority of target features in function DECL1 and DECL2.
36850 It returns positive value if DECL1 is higher priority, negative value if
36851 DECL2 is higher priority and 0 if they are the same. Note, priorities are
36852 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
36855 rs6000_compare_version_priority (tree decl1, tree decl2)
36857 int priority1 = rs6000_clone_priority (decl1);
36858 int priority2 = rs6000_clone_priority (decl2);
36859 int ret = priority1 - priority2;
36861 if (TARGET_DEBUG_TARGET)
36862 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
36863 get_decl_name (decl1), get_decl_name (decl2), ret);
36868 /* Make a dispatcher declaration for the multi-versioned function DECL.
36869 Calls to DECL function will be replaced with calls to the dispatcher
36870 by the front-end. Returns the decl of the dispatcher function. */
36873 rs6000_get_function_versions_dispatcher (void *decl)
36875 tree fn = (tree) decl;
36876 struct cgraph_node *node = NULL;
36877 struct cgraph_node *default_node = NULL;
36878 struct cgraph_function_version_info *node_v = NULL;
36879 struct cgraph_function_version_info *first_v = NULL;
36881 tree dispatch_decl = NULL;
36883 struct cgraph_function_version_info *default_version_info = NULL;
36884 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
36886 if (TARGET_DEBUG_TARGET)
36887 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
36888 get_decl_name (fn));
36890 node = cgraph_node::get (fn);
36891 gcc_assert (node != NULL);
36893 node_v = node->function_version ();
36894 gcc_assert (node_v != NULL);
36896 if (node_v->dispatcher_resolver != NULL)
36897 return node_v->dispatcher_resolver;
36899 /* Find the default version and make it the first node. */
36901 /* Go to the beginning of the chain. */
36902 while (first_v->prev != NULL)
36903 first_v = first_v->prev;
36905 default_version_info = first_v;
36906 while (default_version_info != NULL)
36908 const tree decl2 = default_version_info->this_node->decl;
36909 if (is_function_default_version (decl2))
36911 default_version_info = default_version_info->next;
36914 /* If there is no default node, just return NULL. */
36915 if (default_version_info == NULL)
36918 /* Make default info the first node. */
36919 if (first_v != default_version_info)
36921 default_version_info->prev->next = default_version_info->next;
36922 if (default_version_info->next)
36923 default_version_info->next->prev = default_version_info->prev;
36924 first_v->prev = default_version_info;
36925 default_version_info->next = first_v;
36926 default_version_info->prev = NULL;
36929 default_node = default_version_info->this_node;
36931 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
36932 error_at (DECL_SOURCE_LOCATION (default_node->decl),
36933 "target_clones attribute needs GLIBC (2.23 and newer) that "
36934 "exports hardware capability bits");
36937 if (targetm.has_ifunc_p ())
36939 struct cgraph_function_version_info *it_v = NULL;
36940 struct cgraph_node *dispatcher_node = NULL;
36941 struct cgraph_function_version_info *dispatcher_version_info = NULL;
36943 /* Right now, the dispatching is done via ifunc. */
36944 dispatch_decl = make_dispatcher_decl (default_node->decl);
36946 dispatcher_node = cgraph_node::get_create (dispatch_decl);
36947 gcc_assert (dispatcher_node != NULL);
36948 dispatcher_node->dispatcher_function = 1;
36949 dispatcher_version_info
36950 = dispatcher_node->insert_new_function_version ();
36951 dispatcher_version_info->next = default_version_info;
36952 dispatcher_node->definition = 1;
36954 /* Set the dispatcher for all the versions. */
36955 it_v = default_version_info;
36956 while (it_v != NULL)
36958 it_v->dispatcher_resolver = dispatch_decl;
36964 error_at (DECL_SOURCE_LOCATION (default_node->decl),
36965 "multiversioning needs ifunc which is not supported "
36970 return dispatch_decl;
36973 /* Make the resolver function decl to dispatch the versions of a multi-
36974 versioned function, DEFAULT_DECL. Create an empty basic block in the
36975 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
36979 make_resolver_func (const tree default_decl,
36980 const tree dispatch_decl,
36981 basic_block *empty_bb)
36983 /* Make the resolver function static. The resolver function returns
36985 tree decl_name = clone_function_name_numbered (default_decl, "resolver");
36986 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
36987 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
36988 tree decl = build_fn_decl (resolver_name, type);
36989 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
36991 DECL_NAME (decl) = decl_name;
36992 TREE_USED (decl) = 1;
36993 DECL_ARTIFICIAL (decl) = 1;
36994 DECL_IGNORED_P (decl) = 0;
36995 TREE_PUBLIC (decl) = 0;
36996 DECL_UNINLINABLE (decl) = 1;
36998 /* Resolver is not external, body is generated. */
36999 DECL_EXTERNAL (decl) = 0;
37000 DECL_EXTERNAL (dispatch_decl) = 0;
37002 DECL_CONTEXT (decl) = NULL_TREE;
37003 DECL_INITIAL (decl) = make_node (BLOCK);
37004 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37006 /* Build result decl and add to function_decl. */
37007 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37008 DECL_ARTIFICIAL (t) = 1;
37009 DECL_IGNORED_P (t) = 1;
37010 DECL_RESULT (decl) = t;
37012 gimplify_function_tree (decl);
37013 push_cfun (DECL_STRUCT_FUNCTION (decl));
37014 *empty_bb = init_lowered_empty_function (decl, false,
37015 profile_count::uninitialized ());
37017 cgraph_node::add_new_function (decl, true);
37018 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37022 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37023 DECL_ATTRIBUTES (dispatch_decl)
37024 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37026 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37031 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37032 return a pointer to VERSION_DECL if we are running on a machine that
37033 supports the index CLONE_ISA hardware architecture bits. This function will
37034 be called during version dispatch to decide which function version to
37035 execute. It returns the basic block at the end, to which more conditions
37039 add_condition_to_bb (tree function_decl, tree version_decl,
37040 int clone_isa, basic_block new_bb)
37042 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37044 gcc_assert (new_bb != NULL);
37045 gimple_seq gseq = bb_seq (new_bb);
37048 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37049 build_fold_addr_expr (version_decl));
37050 tree result_var = create_tmp_var (ptr_type_node);
37051 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37052 gimple *return_stmt = gimple_build_return (result_var);
37054 if (clone_isa == CLONE_DEFAULT)
37056 gimple_seq_add_stmt (&gseq, convert_stmt);
37057 gimple_seq_add_stmt (&gseq, return_stmt);
37058 set_bb_seq (new_bb, gseq);
37059 gimple_set_bb (convert_stmt, new_bb);
37060 gimple_set_bb (return_stmt, new_bb);
37065 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37066 tree cond_var = create_tmp_var (bool_int_type_node);
37067 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37068 const char *arg_str = rs6000_clone_map[clone_isa].name;
37069 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37070 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37071 gimple_call_set_lhs (call_cond_stmt, cond_var);
37073 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37074 gimple_set_bb (call_cond_stmt, new_bb);
37075 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37077 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37078 NULL_TREE, NULL_TREE);
37079 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37080 gimple_set_bb (if_else_stmt, new_bb);
37081 gimple_seq_add_stmt (&gseq, if_else_stmt);
37083 gimple_seq_add_stmt (&gseq, convert_stmt);
37084 gimple_seq_add_stmt (&gseq, return_stmt);
37085 set_bb_seq (new_bb, gseq);
37087 basic_block bb1 = new_bb;
37088 edge e12 = split_block (bb1, if_else_stmt);
37089 basic_block bb2 = e12->dest;
37090 e12->flags &= ~EDGE_FALLTHRU;
37091 e12->flags |= EDGE_TRUE_VALUE;
37093 edge e23 = split_block (bb2, return_stmt);
37094 gimple_set_bb (convert_stmt, bb2);
37095 gimple_set_bb (return_stmt, bb2);
37097 basic_block bb3 = e23->dest;
37098 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37101 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37107 /* This function generates the dispatch function for multi-versioned functions.
37108 DISPATCH_DECL is the function which will contain the dispatch logic.
37109 FNDECLS are the function choices for dispatch, and is a tree chain.
37110 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37111 code is generated. */
37114 dispatch_function_versions (tree dispatch_decl,
37116 basic_block *empty_bb)
37120 vec<tree> *fndecls;
37121 tree clones[CLONE_MAX];
37123 if (TARGET_DEBUG_TARGET)
37124 fputs ("dispatch_function_versions, top\n", stderr);
37126 gcc_assert (dispatch_decl != NULL
37127 && fndecls_p != NULL
37128 && empty_bb != NULL);
37130 /* fndecls_p is actually a vector. */
37131 fndecls = static_cast<vec<tree> *> (fndecls_p);
37133 /* At least one more version other than the default. */
37134 gcc_assert (fndecls->length () >= 2);
37136 /* The first version in the vector is the default decl. */
37137 memset ((void *) clones, '\0', sizeof (clones));
37138 clones[CLONE_DEFAULT] = (*fndecls)[0];
37140 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37141 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37142 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37143 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37144 to insert the code here to do the call. */
37146 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37148 int priority = rs6000_clone_priority (ele);
37149 if (!clones[priority])
37150 clones[priority] = ele;
37153 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37156 if (TARGET_DEBUG_TARGET)
37157 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37158 ix, get_decl_name (clones[ix]));
37160 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37167 /* Generate the dispatching code body to dispatch multi-versioned function
37168 DECL. The target hook is called to process the "target" attributes and
37169 provide the code to dispatch the right function at run-time. NODE points
37170 to the dispatcher decl whose body will be created. */
37173 rs6000_generate_version_dispatcher_body (void *node_p)
37176 basic_block empty_bb;
37177 struct cgraph_node *node = (cgraph_node *) node_p;
37178 struct cgraph_function_version_info *ninfo = node->function_version ();
37180 if (ninfo->dispatcher_resolver)
37181 return ninfo->dispatcher_resolver;
37183 /* node is going to be an alias, so remove the finalized bit. */
37184 node->definition = false;
37186 /* The first version in the chain corresponds to the default version. */
37187 ninfo->dispatcher_resolver = resolver
37188 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37190 if (TARGET_DEBUG_TARGET)
37191 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37192 get_decl_name (resolver));
37194 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37195 auto_vec<tree, 2> fn_ver_vec;
37197 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37199 vinfo = vinfo->next)
37201 struct cgraph_node *version = vinfo->this_node;
37202 /* Check for virtual functions here again, as by this time it should
37203 have been determined if this function needs a vtable index or
37204 not. This happens for methods in derived classes that override
37205 virtual methods in base classes but are not explicitly marked as
37207 if (DECL_VINDEX (version->decl))
37208 sorry ("Virtual function multiversioning not supported");
37210 fn_ver_vec.safe_push (version->decl);
37213 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37214 cgraph_edge::rebuild_edges ();
37220 /* Hook to determine if one function can safely inline another. */
37223 rs6000_can_inline_p (tree caller, tree callee)
37226 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37227 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37229 /* If callee has no option attributes, then it is ok to inline. */
37233 /* If caller has no option attributes, but callee does then it is not ok to
37235 else if (!caller_tree)
37240 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37241 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37243 /* Callee's options should a subset of the caller's, i.e. a vsx function
37244 can inline an altivec function but a non-vsx function can't inline a
37246 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37247 == callee_opts->x_rs6000_isa_flags)
37251 if (TARGET_DEBUG_TARGET)
37252 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37253 get_decl_name (caller), get_decl_name (callee),
37254 (ret ? "can" : "cannot"));
37259 /* Allocate a stack temp and fixup the address so it meets the particular
37260 memory requirements (either offetable or REG+REG addressing). */
37263 rs6000_allocate_stack_temp (machine_mode mode,
37264 bool offsettable_p,
37267 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37268 rtx addr = XEXP (stack, 0);
37269 int strict_p = reload_completed;
37271 if (!legitimate_indirect_address_p (addr, strict_p))
37274 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37275 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37277 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37278 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37284 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37285 convert to such a form to deal with memory reference instructions
37286 like STFIWX and LDBRX that only take reg+reg addressing. */
37289 rs6000_force_indexed_or_indirect_mem (rtx x)
37291 machine_mode mode = GET_MODE (x);
37293 gcc_assert (MEM_P (x));
37294 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x, mode))
37296 rtx addr = XEXP (x, 0);
37297 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37299 rtx reg = XEXP (addr, 0);
37300 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37301 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37302 gcc_assert (REG_P (reg));
37303 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37306 else if (GET_CODE (addr) == PRE_MODIFY)
37308 rtx reg = XEXP (addr, 0);
37309 rtx expr = XEXP (addr, 1);
37310 gcc_assert (REG_P (reg));
37311 gcc_assert (GET_CODE (expr) == PLUS);
37312 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37316 x = replace_equiv_address (x, force_reg (Pmode, addr));
37322 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37324 On the RS/6000, all integer constants are acceptable, most won't be valid
37325 for particular insns, though. Only easy FP constants are acceptable. */
37328 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37330 if (TARGET_ELF && tls_referenced_p (x))
37333 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
37334 || GET_MODE (x) == VOIDmode
37335 || (TARGET_POWERPC64 && mode == DImode)
37336 || easy_fp_constant (x, mode)
37337 || easy_vector_constant (x, mode));
37341 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37344 chain_already_loaded (rtx_insn *last)
37346 for (; last != NULL; last = PREV_INSN (last))
37348 if (NONJUMP_INSN_P (last))
37350 rtx patt = PATTERN (last);
37352 if (GET_CODE (patt) == SET)
37354 rtx lhs = XEXP (patt, 0);
37356 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37364 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37367 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
37369 const bool direct_call_p
37370 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
37371 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37372 rtx toc_load = NULL_RTX;
37373 rtx toc_restore = NULL_RTX;
37375 rtx abi_reg = NULL_RTX;
37380 /* Handle longcall attributes. */
37381 if (INTVAL (cookie) & CALL_LONG)
37382 func_desc = rs6000_longcall_ref (func_desc);
37384 /* Handle indirect calls. */
37385 if (GET_CODE (func_desc) != SYMBOL_REF
37386 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
37388 /* Save the TOC into its reserved slot before the call,
37389 and prepare to restore it after the call. */
37390 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37391 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37392 rtx stack_toc_mem = gen_frame_mem (Pmode,
37393 gen_rtx_PLUS (Pmode, stack_ptr,
37394 stack_toc_offset));
37395 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37396 gen_rtvec (1, stack_toc_offset),
37398 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37400 /* Can we optimize saving the TOC in the prologue or
37401 do we need to do it at every call? */
37402 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37403 cfun->machine->save_toc_in_prologue = true;
37406 MEM_VOLATILE_P (stack_toc_mem) = 1;
37407 emit_move_insn (stack_toc_mem, toc_reg);
37410 if (DEFAULT_ABI == ABI_ELFv2)
37412 /* A function pointer in the ELFv2 ABI is just a plain address, but
37413 the ABI requires it to be loaded into r12 before the call. */
37414 func_addr = gen_rtx_REG (Pmode, 12);
37415 emit_move_insn (func_addr, func_desc);
37416 abi_reg = func_addr;
37420 /* A function pointer under AIX is a pointer to a data area whose
37421 first word contains the actual address of the function, whose
37422 second word contains a pointer to its TOC, and whose third word
37423 contains a value to place in the static chain register (r11).
37424 Note that if we load the static chain, our "trampoline" need
37425 not have any executable code. */
37427 /* Load up address of the actual function. */
37428 func_desc = force_reg (Pmode, func_desc);
37429 func_addr = gen_reg_rtx (Pmode);
37430 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
37432 /* Prepare to load the TOC of the called function. Note that the
37433 TOC load must happen immediately before the actual call so
37434 that unwinding the TOC registers works correctly. See the
37435 comment in frob_update_context. */
37436 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37437 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37438 gen_rtx_PLUS (Pmode, func_desc,
37440 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37442 /* If we have a static chain, load it up. But, if the call was
37443 originally direct, the 3rd word has not been written since no
37444 trampoline has been built, so we ought not to load it, lest we
37445 override a static chain value. */
37447 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37448 && !chain_already_loaded (get_current_sequence ()->next->last))
37450 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37451 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37452 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37453 gen_rtx_PLUS (Pmode, func_desc,
37455 emit_move_insn (sc_reg, func_sc_mem);
37462 /* Direct calls use the TOC: for local calls, the callee will
37463 assume the TOC register is set; for non-local calls, the
37464 PLT stub needs the TOC register. */
37466 func_addr = func_desc;
37469 /* Create the call. */
37470 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
37471 if (value != NULL_RTX)
37472 call[0] = gen_rtx_SET (value, call[0]);
37476 call[n_call++] = toc_load;
37478 call[n_call++] = toc_restore;
37480 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
37482 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37483 insn = emit_call_insn (insn);
37485 /* Mention all registers defined by the ABI to hold information
37486 as uses in CALL_INSN_FUNCTION_USAGE. */
37488 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37491 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37494 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
37499 gcc_assert (INTVAL (cookie) == 0);
37501 /* Create the call. */
37502 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
37503 if (value != NULL_RTX)
37504 call[0] = gen_rtx_SET (value, call[0]);
37506 call[1] = simple_return_rtx;
37508 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37509 insn = emit_call_insn (insn);
37511 /* Note use of the TOC register. */
37512 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
37515 /* Return whether we need to always update the saved TOC pointer when we update
37516 the stack pointer. */
37519 rs6000_save_toc_in_prologue_p (void)
37521 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
37524 #ifdef HAVE_GAS_HIDDEN
37525 # define USE_HIDDEN_LINKONCE 1
37527 # define USE_HIDDEN_LINKONCE 0
37530 /* Fills in the label name that should be used for a 476 link stack thunk. */
37533 get_ppc476_thunk_name (char name[32])
37535 gcc_assert (TARGET_LINK_STACK);
37537 if (USE_HIDDEN_LINKONCE)
37538 sprintf (name, "__ppc476.get_thunk");
37540 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
37543 /* This function emits the simple thunk routine that is used to preserve
37544 the link stack on the 476 cpu. */
37546 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
37548 rs6000_code_end (void)
37553 if (!TARGET_LINK_STACK)
37556 get_ppc476_thunk_name (name);
37558 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
37559 build_function_type_list (void_type_node, NULL_TREE));
37560 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
37561 NULL_TREE, void_type_node);
37562 TREE_PUBLIC (decl) = 1;
37563 TREE_STATIC (decl) = 1;
37566 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
37568 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
37569 targetm.asm_out.unique_section (decl, 0);
37570 switch_to_section (get_named_section (decl, NULL, 0));
37571 DECL_WEAK (decl) = 1;
37572 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
37573 targetm.asm_out.globalize_label (asm_out_file, name);
37574 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
37575 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
37580 switch_to_section (text_section);
37581 ASM_OUTPUT_LABEL (asm_out_file, name);
37584 DECL_INITIAL (decl) = make_node (BLOCK);
37585 current_function_decl = decl;
37586 allocate_struct_function (decl, false);
37587 init_function_start (decl);
37588 first_function_block_is_cold = false;
37589 /* Make sure unwind info is emitted for the thunk if needed. */
37590 final_start_function (emit_barrier (), asm_out_file, 1);
37592 fputs ("\tblr\n", asm_out_file);
37594 final_end_function ();
37595 init_insn_lengths ();
37596 free_after_compilation (cfun);
37598 current_function_decl = NULL;
37601 /* Add r30 to hard reg set if the prologue sets it up and it is not
37602 pic_offset_table_rtx. */
37605 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
37607 if (!TARGET_SINGLE_PIC_BASE
37609 && TARGET_MINIMAL_TOC
37610 && !constant_pool_empty_p ())
37611 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
37612 if (cfun->machine->split_stack_argp_used)
37613 add_to_hard_reg_set (&set->set, Pmode, 12);
37615 /* Make sure the hard reg set doesn't include r2, which was possibly added
37616 via PIC_OFFSET_TABLE_REGNUM. */
37618 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
37622 /* Helper function for rs6000_split_logical to emit a logical instruction after
37623 spliting the operation to single GPR registers.
37625 DEST is the destination register.
37626 OP1 and OP2 are the input source registers.
37627 CODE is the base operation (AND, IOR, XOR, NOT).
37628 MODE is the machine mode.
37629 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37630 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37631 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37634 rs6000_split_logical_inner (rtx dest,
37637 enum rtx_code code,
37639 bool complement_final_p,
37640 bool complement_op1_p,
37641 bool complement_op2_p)
37645 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
37646 if (op2 && GET_CODE (op2) == CONST_INT
37647 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
37648 && !complement_final_p && !complement_op1_p && !complement_op2_p)
37650 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
37651 HOST_WIDE_INT value = INTVAL (op2) & mask;
37653 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
37658 emit_insn (gen_rtx_SET (dest, const0_rtx));
37662 else if (value == mask)
37664 if (!rtx_equal_p (dest, op1))
37665 emit_insn (gen_rtx_SET (dest, op1));
37670 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
37671 into separate ORI/ORIS or XORI/XORIS instrucitons. */
37672 else if (code == IOR || code == XOR)
37676 if (!rtx_equal_p (dest, op1))
37677 emit_insn (gen_rtx_SET (dest, op1));
37683 if (code == AND && mode == SImode
37684 && !complement_final_p && !complement_op1_p && !complement_op2_p)
37686 emit_insn (gen_andsi3 (dest, op1, op2));
37690 if (complement_op1_p)
37691 op1 = gen_rtx_NOT (mode, op1);
37693 if (complement_op2_p)
37694 op2 = gen_rtx_NOT (mode, op2);
37696 /* For canonical RTL, if only one arm is inverted it is the first. */
37697 if (!complement_op1_p && complement_op2_p)
37698 std::swap (op1, op2);
37700 bool_rtx = ((code == NOT)
37701 ? gen_rtx_NOT (mode, op1)
37702 : gen_rtx_fmt_ee (code, mode, op1, op2));
37704 if (complement_final_p)
37705 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
37707 emit_insn (gen_rtx_SET (dest, bool_rtx));
37710 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
37711 operations are split immediately during RTL generation to allow for more
37712 optimizations of the AND/IOR/XOR.
37714 OPERANDS is an array containing the destination and two input operands.
37715 CODE is the base operation (AND, IOR, XOR, NOT).
37716 MODE is the machine mode.
37717 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37718 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37719 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
37720 CLOBBER_REG is either NULL or a scratch register of type CC to allow
37721 formation of the AND instructions. */
37724 rs6000_split_logical_di (rtx operands[3],
37725 enum rtx_code code,
37726 bool complement_final_p,
37727 bool complement_op1_p,
37728 bool complement_op2_p)
37730 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
37731 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
37732 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
37733 enum hi_lo { hi = 0, lo = 1 };
37734 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
37737 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
37738 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
37739 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
37740 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
37743 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
37746 if (GET_CODE (operands[2]) != CONST_INT)
37748 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
37749 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
37753 HOST_WIDE_INT value = INTVAL (operands[2]);
37754 HOST_WIDE_INT value_hi_lo[2];
37756 gcc_assert (!complement_final_p);
37757 gcc_assert (!complement_op1_p);
37758 gcc_assert (!complement_op2_p);
37760 value_hi_lo[hi] = value >> 32;
37761 value_hi_lo[lo] = value & lower_32bits;
37763 for (i = 0; i < 2; i++)
37765 HOST_WIDE_INT sub_value = value_hi_lo[i];
37767 if (sub_value & sign_bit)
37768 sub_value |= upper_32bits;
37770 op2_hi_lo[i] = GEN_INT (sub_value);
37772 /* If this is an AND instruction, check to see if we need to load
37773 the value in a register. */
37774 if (code == AND && sub_value != -1 && sub_value != 0
37775 && !and_operand (op2_hi_lo[i], SImode))
37776 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
37781 for (i = 0; i < 2; i++)
37783 /* Split large IOR/XOR operations. */
37784 if ((code == IOR || code == XOR)
37785 && GET_CODE (op2_hi_lo[i]) == CONST_INT
37786 && !complement_final_p
37787 && !complement_op1_p
37788 && !complement_op2_p
37789 && !logical_const_operand (op2_hi_lo[i], SImode))
37791 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
37792 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
37793 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
37794 rtx tmp = gen_reg_rtx (SImode);
37796 /* Make sure the constant is sign extended. */
37797 if ((hi_16bits & sign_bit) != 0)
37798 hi_16bits |= upper_32bits;
37800 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
37801 code, SImode, false, false, false);
37803 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
37804 code, SImode, false, false, false);
37807 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
37808 code, SImode, complement_final_p,
37809 complement_op1_p, complement_op2_p);
37815 /* Split the insns that make up boolean operations operating on multiple GPR
37816 registers. The boolean MD patterns ensure that the inputs either are
37817 exactly the same as the output registers, or there is no overlap.
37819 OPERANDS is an array containing the destination and two input operands.
37820 CODE is the base operation (AND, IOR, XOR, NOT).
37821 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37822 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37823 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37826 rs6000_split_logical (rtx operands[3],
37827 enum rtx_code code,
37828 bool complement_final_p,
37829 bool complement_op1_p,
37830 bool complement_op2_p)
37832 machine_mode mode = GET_MODE (operands[0]);
37833 machine_mode sub_mode;
37835 int sub_size, regno0, regno1, nregs, i;
37837 /* If this is DImode, use the specialized version that can run before
37838 register allocation. */
37839 if (mode == DImode && !TARGET_POWERPC64)
37841 rs6000_split_logical_di (operands, code, complement_final_p,
37842 complement_op1_p, complement_op2_p);
37848 op2 = (code == NOT) ? NULL_RTX : operands[2];
37849 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
37850 sub_size = GET_MODE_SIZE (sub_mode);
37851 regno0 = REGNO (op0);
37852 regno1 = REGNO (op1);
37854 gcc_assert (reload_completed);
37855 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
37856 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
37858 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
37859 gcc_assert (nregs > 1);
37861 if (op2 && REG_P (op2))
37862 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
37864 for (i = 0; i < nregs; i++)
37866 int offset = i * sub_size;
37867 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
37868 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
37869 rtx sub_op2 = ((code == NOT)
37871 : simplify_subreg (sub_mode, op2, mode, offset));
37873 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
37874 complement_final_p, complement_op1_p,
37882 /* Return true if the peephole2 can combine a load involving a combination of
37883 an addis instruction and a load with an offset that can be fused together on
37887 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
37888 rtx addis_value, /* addis value. */
37889 rtx target, /* target register that is loaded. */
37890 rtx mem) /* bottom part of the memory addr. */
37895 /* Validate arguments. */
37896 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
37899 if (!base_reg_operand (target, GET_MODE (target)))
37902 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
37905 /* Allow sign/zero extension. */
37906 if (GET_CODE (mem) == ZERO_EXTEND
37907 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
37908 mem = XEXP (mem, 0);
37913 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
37916 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
37917 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
37920 /* Validate that the register used to load the high value is either the
37921 register being loaded, or we can safely replace its use.
37923 This function is only called from the peephole2 pass and we assume that
37924 there are 2 instructions in the peephole (addis and load), so we want to
37925 check if the target register was not used in the memory address and the
37926 register to hold the addis result is dead after the peephole. */
37927 if (REGNO (addis_reg) != REGNO (target))
37929 if (reg_mentioned_p (target, mem))
37932 if (!peep2_reg_dead_p (2, addis_reg))
37935 /* If the target register being loaded is the stack pointer, we must
37936 avoid loading any other value into it, even temporarily. */
37937 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
37941 base_reg = XEXP (addr, 0);
37942 return REGNO (addis_reg) == REGNO (base_reg);
37945 /* During the peephole2 pass, adjust and expand the insns for a load fusion
37946 sequence. We adjust the addis register to use the target register. If the
37947 load sign extends, we adjust the code to do the zero extending load, and an
37948 explicit sign extension later since the fusion only covers zero extending
37952 operands[0] register set with addis (to be replaced with target)
37953 operands[1] value set via addis
37954 operands[2] target register being loaded
37955 operands[3] D-form memory reference using operands[0]. */
37958 expand_fusion_gpr_load (rtx *operands)
37960 rtx addis_value = operands[1];
37961 rtx target = operands[2];
37962 rtx orig_mem = operands[3];
37963 rtx new_addr, new_mem, orig_addr, offset;
37964 enum rtx_code plus_or_lo_sum;
37965 machine_mode target_mode = GET_MODE (target);
37966 machine_mode extend_mode = target_mode;
37967 machine_mode ptr_mode = Pmode;
37968 enum rtx_code extend = UNKNOWN;
37970 if (GET_CODE (orig_mem) == ZERO_EXTEND
37971 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
37973 extend = GET_CODE (orig_mem);
37974 orig_mem = XEXP (orig_mem, 0);
37975 target_mode = GET_MODE (orig_mem);
37978 gcc_assert (MEM_P (orig_mem));
37980 orig_addr = XEXP (orig_mem, 0);
37981 plus_or_lo_sum = GET_CODE (orig_addr);
37982 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
37984 offset = XEXP (orig_addr, 1);
37985 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
37986 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
37988 if (extend != UNKNOWN)
37989 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
37991 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
37992 UNSPEC_FUSION_GPR);
37993 emit_insn (gen_rtx_SET (target, new_mem));
37995 if (extend == SIGN_EXTEND)
37997 int sub_off = ((BYTES_BIG_ENDIAN)
37998 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38001 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38003 emit_insn (gen_rtx_SET (target,
38004 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38010 /* Emit the addis instruction that will be part of a fused instruction
38014 emit_fusion_addis (rtx target, rtx addis_value)
38017 const char *addis_str = NULL;
38019 /* Emit the addis instruction. */
38020 fuse_ops[0] = target;
38021 if (satisfies_constraint_L (addis_value))
38023 fuse_ops[1] = addis_value;
38024 addis_str = "lis %0,%v1";
38027 else if (GET_CODE (addis_value) == PLUS)
38029 rtx op0 = XEXP (addis_value, 0);
38030 rtx op1 = XEXP (addis_value, 1);
38032 if (REG_P (op0) && CONST_INT_P (op1)
38033 && satisfies_constraint_L (op1))
38037 addis_str = "addis %0,%1,%v2";
38041 else if (GET_CODE (addis_value) == HIGH)
38043 rtx value = XEXP (addis_value, 0);
38044 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38046 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38047 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38049 addis_str = "addis %0,%2,%1@toc@ha";
38051 else if (TARGET_XCOFF)
38052 addis_str = "addis %0,%1@u(%2)";
38055 gcc_unreachable ();
38058 else if (GET_CODE (value) == PLUS)
38060 rtx op0 = XEXP (value, 0);
38061 rtx op1 = XEXP (value, 1);
38063 if (GET_CODE (op0) == UNSPEC
38064 && XINT (op0, 1) == UNSPEC_TOCREL
38065 && CONST_INT_P (op1))
38067 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38068 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38071 addis_str = "addis %0,%2,%1+%3@toc@ha";
38073 else if (TARGET_XCOFF)
38074 addis_str = "addis %0,%1+%3@u(%2)";
38077 gcc_unreachable ();
38081 else if (satisfies_constraint_L (value))
38083 fuse_ops[1] = value;
38084 addis_str = "lis %0,%v1";
38087 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38089 fuse_ops[1] = value;
38090 addis_str = "lis %0,%1@ha";
38095 fatal_insn ("Could not generate addis value for fusion", addis_value);
38097 output_asm_insn (addis_str, fuse_ops);
38100 /* Emit a D-form load or store instruction that is the second instruction
38101 of a fusion sequence. */
38104 emit_fusion_load (rtx load_reg, rtx addis_reg, rtx offset, const char *insn_str)
38107 char insn_template[80];
38109 fuse_ops[0] = load_reg;
38110 fuse_ops[1] = addis_reg;
38112 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38114 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38115 fuse_ops[2] = offset;
38116 output_asm_insn (insn_template, fuse_ops);
38119 else if (GET_CODE (offset) == UNSPEC
38120 && XINT (offset, 1) == UNSPEC_TOCREL)
38123 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38125 else if (TARGET_XCOFF)
38126 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38129 gcc_unreachable ();
38131 fuse_ops[2] = XVECEXP (offset, 0, 0);
38132 output_asm_insn (insn_template, fuse_ops);
38135 else if (GET_CODE (offset) == PLUS
38136 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38137 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38138 && CONST_INT_P (XEXP (offset, 1)))
38140 rtx tocrel_unspec = XEXP (offset, 0);
38142 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38144 else if (TARGET_XCOFF)
38145 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38148 gcc_unreachable ();
38150 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38151 fuse_ops[3] = XEXP (offset, 1);
38152 output_asm_insn (insn_template, fuse_ops);
38155 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38157 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38159 fuse_ops[2] = offset;
38160 output_asm_insn (insn_template, fuse_ops);
38164 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38169 /* Given an address, convert it into the addis and load offset parts. Addresses
38170 created during the peephole2 process look like:
38171 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38172 (unspec [(...)] UNSPEC_TOCREL)) */
38175 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38179 if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38181 hi = XEXP (addr, 0);
38182 lo = XEXP (addr, 1);
38185 gcc_unreachable ();
38191 /* Return a string to fuse an addis instruction with a gpr load to the same
38192 register that we loaded up the addis instruction. The address that is used
38193 is the logical address that was formed during peephole2:
38194 (lo_sum (high) (low-part))
38196 The code is complicated, so we call output_asm_insn directly, and just
38200 emit_fusion_gpr_load (rtx target, rtx mem)
38205 const char *load_str = NULL;
38208 if (GET_CODE (mem) == ZERO_EXTEND)
38209 mem = XEXP (mem, 0);
38211 gcc_assert (REG_P (target) && MEM_P (mem));
38213 addr = XEXP (mem, 0);
38214 fusion_split_address (addr, &addis_value, &load_offset);
38216 /* Now emit the load instruction to the same register. */
38217 mode = GET_MODE (mem);
38235 gcc_assert (TARGET_POWERPC64);
38240 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38243 /* Emit the addis instruction. */
38244 emit_fusion_addis (target, addis_value);
38246 /* Emit the D-form load instruction. */
38247 emit_fusion_load (target, target, load_offset, load_str);
38253 #ifdef RS6000_GLIBC_ATOMIC_FENV
38254 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38255 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
38258 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38261 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
38263 if (!TARGET_HARD_FLOAT)
38265 #ifdef RS6000_GLIBC_ATOMIC_FENV
38266 if (atomic_hold_decl == NULL_TREE)
38269 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38270 get_identifier ("__atomic_feholdexcept"),
38271 build_function_type_list (void_type_node,
38272 double_ptr_type_node,
38274 TREE_PUBLIC (atomic_hold_decl) = 1;
38275 DECL_EXTERNAL (atomic_hold_decl) = 1;
38278 if (atomic_clear_decl == NULL_TREE)
38281 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38282 get_identifier ("__atomic_feclearexcept"),
38283 build_function_type_list (void_type_node,
38285 TREE_PUBLIC (atomic_clear_decl) = 1;
38286 DECL_EXTERNAL (atomic_clear_decl) = 1;
38289 tree const_double = build_qualified_type (double_type_node,
38291 tree const_double_ptr = build_pointer_type (const_double);
38292 if (atomic_update_decl == NULL_TREE)
38295 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38296 get_identifier ("__atomic_feupdateenv"),
38297 build_function_type_list (void_type_node,
38300 TREE_PUBLIC (atomic_update_decl) = 1;
38301 DECL_EXTERNAL (atomic_update_decl) = 1;
38304 tree fenv_var = create_tmp_var_raw (double_type_node);
38305 TREE_ADDRESSABLE (fenv_var) = 1;
38306 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
38308 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
38309 *clear = build_call_expr (atomic_clear_decl, 0);
38310 *update = build_call_expr (atomic_update_decl, 1,
38311 fold_convert (const_double_ptr, fenv_addr));
38316 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
38317 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
38318 tree call_mffs = build_call_expr (mffs, 0);
38320 /* Generates the equivalent of feholdexcept (&fenv_var)
38322 *fenv_var = __builtin_mffs ();
38324 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38325 __builtin_mtfsf (0xff, fenv_hold); */
38327 /* Mask to clear everything except for the rounding modes and non-IEEE
38328 arithmetic flag. */
38329 const unsigned HOST_WIDE_INT hold_exception_mask =
38330 HOST_WIDE_INT_C (0xffffffff00000007);
38332 tree fenv_var = create_tmp_var_raw (double_type_node);
38334 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
38336 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
38337 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38338 build_int_cst (uint64_type_node,
38339 hold_exception_mask));
38341 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38344 tree hold_mtfsf = build_call_expr (mtfsf, 2,
38345 build_int_cst (unsigned_type_node, 0xff),
38348 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
38350 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38352 double fenv_clear = __builtin_mffs ();
38353 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38354 __builtin_mtfsf (0xff, fenv_clear); */
38356 /* Mask to clear everything except for the rounding modes and non-IEEE
38357 arithmetic flag. */
38358 const unsigned HOST_WIDE_INT clear_exception_mask =
38359 HOST_WIDE_INT_C (0xffffffff00000000);
38361 tree fenv_clear = create_tmp_var_raw (double_type_node);
38363 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
38365 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
38366 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
38368 build_int_cst (uint64_type_node,
38369 clear_exception_mask));
38371 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38372 fenv_clear_llu_and);
38374 tree clear_mtfsf = build_call_expr (mtfsf, 2,
38375 build_int_cst (unsigned_type_node, 0xff),
38378 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
38380 /* Generates the equivalent of feupdateenv (&fenv_var)
38382 double old_fenv = __builtin_mffs ();
38383 double fenv_update;
38384 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38385 (*(uint64_t*)fenv_var 0x1ff80fff);
38386 __builtin_mtfsf (0xff, fenv_update); */
38388 const unsigned HOST_WIDE_INT update_exception_mask =
38389 HOST_WIDE_INT_C (0xffffffff1fffff00);
38390 const unsigned HOST_WIDE_INT new_exception_mask =
38391 HOST_WIDE_INT_C (0x1ff80fff);
38393 tree old_fenv = create_tmp_var_raw (double_type_node);
38394 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
38396 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
38397 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
38398 build_int_cst (uint64_type_node,
38399 update_exception_mask));
38401 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38402 build_int_cst (uint64_type_node,
38403 new_exception_mask));
38405 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
38406 old_llu_and, new_llu_and);
38408 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38411 tree update_mtfsf = build_call_expr (mtfsf, 2,
38412 build_int_cst (unsigned_type_node, 0xff),
38413 fenv_update_mtfsf);
38415 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
38419 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
38421 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38423 rtx_tmp0 = gen_reg_rtx (V2DFmode);
38424 rtx_tmp1 = gen_reg_rtx (V2DFmode);
38426 /* The destination of the vmrgew instruction layout is:
38427 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38428 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38429 vmrgew instruction will be correct. */
38430 if (BYTES_BIG_ENDIAN)
38432 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
38434 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
38439 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
38440 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
38443 rtx_tmp2 = gen_reg_rtx (V4SFmode);
38444 rtx_tmp3 = gen_reg_rtx (V4SFmode);
38446 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
38447 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
38449 if (BYTES_BIG_ENDIAN)
38450 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
38452 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
38456 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
38458 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38460 rtx_tmp0 = gen_reg_rtx (V2DImode);
38461 rtx_tmp1 = gen_reg_rtx (V2DImode);
38463 /* The destination of the vmrgew instruction layout is:
38464 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38465 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38466 vmrgew instruction will be correct. */
38467 if (BYTES_BIG_ENDIAN)
38469 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
38470 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
38474 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
38475 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
38478 rtx_tmp2 = gen_reg_rtx (V4SFmode);
38479 rtx_tmp3 = gen_reg_rtx (V4SFmode);
38481 if (signed_convert)
38483 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
38484 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
38488 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
38489 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
38492 if (BYTES_BIG_ENDIAN)
38493 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
38495 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
38499 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
38502 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
38504 rtx_tmp0 = gen_reg_rtx (V2DFmode);
38505 rtx_tmp1 = gen_reg_rtx (V2DFmode);
38507 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
38508 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
38510 rtx_tmp2 = gen_reg_rtx (V4SImode);
38511 rtx_tmp3 = gen_reg_rtx (V4SImode);
38513 if (signed_convert)
38515 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
38516 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
38520 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
38521 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
38524 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
38527 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
38530 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
38531 optimization_type opt_type)
38536 return (opt_type == OPTIMIZE_FOR_SPEED
38537 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
38544 /* Implement TARGET_CONSTANT_ALIGNMENT. */
38546 static HOST_WIDE_INT
38547 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
38549 if (TREE_CODE (exp) == STRING_CST
38550 && (STRICT_ALIGNMENT || !optimize_size))
38551 return MAX (align, BITS_PER_WORD);
38555 /* Implement TARGET_STARTING_FRAME_OFFSET. */
38557 static HOST_WIDE_INT
38558 rs6000_starting_frame_offset (void)
38560 if (FRAME_GROWS_DOWNWARD)
38562 return RS6000_STARTING_FRAME_OFFSET;
38566 /* Create an alias for a mangled name where we have changed the mangling (in
38567 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
38568 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
38570 #if TARGET_ELF && RS6000_WEAK
38572 rs6000_globalize_decl_name (FILE * stream, tree decl)
38574 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
38576 targetm.asm_out.globalize_label (stream, name);
38578 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
38580 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
38581 const char *old_name;
38583 ieee128_mangling_gcc_8_1 = true;
38584 lang_hooks.set_decl_assembler_name (decl);
38585 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
38586 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
38587 ieee128_mangling_gcc_8_1 = false;
38589 if (strcmp (name, old_name) != 0)
38591 fprintf (stream, "\t.weak %s\n", old_name);
38592 fprintf (stream, "\t.set %s,%s\n", old_name, name);
38599 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
38600 function names from <foo>l to <foo>f128 if the default long double type is
38601 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
38602 include file switches the names on systems that support long double as IEEE
38603 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
38604 In the future, glibc will export names like __ieee128_sinf128 and we can
38605 switch to using those instead of using sinf128, which pollutes the user's
38608 This will switch the names for Fortran math functions as well (which doesn't
38609 use math.h). However, Fortran needs other changes to the compiler and
38610 library before you can switch the real*16 type at compile time.
38612 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
38613 only do this if the default is that long double is IBM extended double, and
38614 the user asked for IEEE 128-bit. */
38617 rs6000_mangle_decl_assembler_name (tree decl, tree id)
38619 if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
38620 && TREE_CODE (decl) == FUNCTION_DECL && DECL_IS_BUILTIN (decl) )
38622 size_t len = IDENTIFIER_LENGTH (id);
38623 const char *name = IDENTIFIER_POINTER (id);
38625 if (name[len - 1] == 'l')
38627 bool uses_ieee128_p = false;
38628 tree type = TREE_TYPE (decl);
38629 machine_mode ret_mode = TYPE_MODE (type);
38631 /* See if the function returns a IEEE 128-bit floating point type or
38633 if (ret_mode == TFmode || ret_mode == TCmode)
38634 uses_ieee128_p = true;
38637 function_args_iterator args_iter;
38640 /* See if the function passes a IEEE 128-bit floating point type
38641 or complex type. */
38642 FOREACH_FUNCTION_ARGS (type, arg, args_iter)
38644 machine_mode arg_mode = TYPE_MODE (arg);
38645 if (arg_mode == TFmode || arg_mode == TCmode)
38647 uses_ieee128_p = true;
38653 /* If we passed or returned an IEEE 128-bit floating point type,
38654 change the name. */
38655 if (uses_ieee128_p)
38657 char *name2 = (char *) alloca (len + 4);
38658 memcpy (name2, name, len - 1);
38659 strcpy (name2 + len - 1, "f128");
38660 id = get_identifier (name2);
38669 struct gcc_target targetm = TARGET_INITIALIZER;
38671 #include "gt-rs6000.h"