1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2017 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
72 #include "tree-pass.h"
75 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
78 #include "gstab.h" /* for N_SLINE */
80 #include "case-cfn-macros.h"
82 #include "tree-ssa-propagate.h"
84 /* This file should be included last. */
85 #include "target-def.h"
87 #ifndef TARGET_NO_PROTOTYPE
88 #define TARGET_NO_PROTOTYPE 0
91 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
92 systems will also set long double to be IEEE 128-bit. AIX and Darwin
93 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
94 those systems will not pick up this default. This needs to be after all
95 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
97 #ifndef TARGET_IEEEQUAD_DEFAULT
98 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
99 #define TARGET_IEEEQUAD_DEFAULT 1
101 #define TARGET_IEEEQUAD_DEFAULT 0
105 #define min(A,B) ((A) < (B) ? (A) : (B))
106 #define max(A,B) ((A) > (B) ? (A) : (B))
108 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack {
112 int reload_completed; /* stack info won't change from here on */
113 int first_gp_reg_save; /* first callee saved GP register used */
114 int first_fp_reg_save; /* first callee saved FP register used */
115 int first_altivec_reg_save; /* first callee saved AltiVec register used */
116 int lr_save_p; /* true if the link reg needs to be saved */
117 int cr_save_p; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask; /* mask of vec registers to save */
119 int push_p; /* true if we need to allocate stack space */
120 int calls_p; /* true if the function makes any calls */
121 int world_save_p; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi; /* which ABI to use */
124 int gp_save_offset; /* offset to save GP regs from initial SP */
125 int fp_save_offset; /* offset to save FP regs from initial SP */
126 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset; /* offset to save LR from initial SP */
128 int cr_save_offset; /* offset to save CR from initial SP */
129 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset; /* offset to save the varargs registers */
131 int ehrd_offset; /* offset to EH return data */
132 int ehcr_offset; /* offset to EH CR field data */
133 int reg_size; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size; /* variable save area size */
135 int parm_size; /* outgoing parameter size */
136 int save_size; /* save area size */
137 int fixed_size; /* fixed size of stack frame */
138 int gp_size; /* size of saved GP registers */
139 int fp_size; /* size of saved FP registers */
140 int altivec_size; /* size of saved AltiVec registers */
141 int cr_size; /* size to hold CR if not in fixed area */
142 int vrsave_size; /* size to hold VRSAVE */
143 int altivec_padding_size; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer;
166 bool split_stack_argp_used;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately[32];
174 bool fpr_is_wrapped_separately[32];
175 bool lr_is_wrapped_separately;
176 bool toc_is_wrapped_separately;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno = 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode;
202 /* Width in bits of a pointer. */
203 unsigned rs6000_pointer_size;
205 #ifdef HAVE_AS_GNU_ATTRIBUTE
206 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
207 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
209 /* Flag whether floating point values have been passed/returned.
210 Note that this doesn't say whether fprs are used, since the
211 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
212 should be set for soft-float values passed in gprs and ieee128
213 values passed in vsx registers. */
214 static bool rs6000_passes_float;
215 static bool rs6000_passes_long_double;
216 /* Flag whether vector values have been passed/returned. */
217 static bool rs6000_passes_vector;
218 /* Flag whether small (<= 8 byte) structures have been returned. */
219 static bool rs6000_returns_struct;
222 /* Value is TRUE if register/mode pair is acceptable. */
223 static bool rs6000_hard_regno_mode_ok_p
224 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Maximum number of registers needed for a given register class and mode. */
227 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
229 /* How many registers are needed for a given register and mode. */
230 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
232 /* Map register number to register class. */
233 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
235 static int dbg_cost_ctrl;
237 /* Built in types. */
238 tree rs6000_builtin_types[RS6000_BTI_MAX];
239 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
241 /* Flag to say the TOC is initialized */
242 int toc_initialized, need_toc_init;
243 char toc_label_name[10];
245 /* Cached value of rs6000_variable_issue. This is cached in
246 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
247 static short cached_can_issue_more;
249 static GTY(()) section *read_only_data_section;
250 static GTY(()) section *private_data_section;
251 static GTY(()) section *tls_data_section;
252 static GTY(()) section *tls_private_data_section;
253 static GTY(()) section *read_only_private_data_section;
254 static GTY(()) section *sdata2_section;
255 static GTY(()) section *toc_section;
257 struct builtin_description
259 const HOST_WIDE_INT mask;
260 const enum insn_code icode;
261 const char *const name;
262 const enum rs6000_builtins code;
265 /* Describe the vector unit used for modes. */
266 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
267 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
269 /* Register classes for various constraints that are based on the target
271 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
273 /* Describe the alignment of a vector. */
274 int rs6000_vector_align[NUM_MACHINE_MODES];
276 /* Map selected modes to types for builtins. */
277 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
279 /* What modes to automatically generate reciprocal divide estimate (fre) and
280 reciprocal sqrt (frsqrte) for. */
281 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
283 /* Masks to determine which reciprocal esitmate instructions to generate
285 enum rs6000_recip_mask {
286 RECIP_SF_DIV = 0x001, /* Use divide estimate */
287 RECIP_DF_DIV = 0x002,
288 RECIP_V4SF_DIV = 0x004,
289 RECIP_V2DF_DIV = 0x008,
291 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
292 RECIP_DF_RSQRT = 0x020,
293 RECIP_V4SF_RSQRT = 0x040,
294 RECIP_V2DF_RSQRT = 0x080,
296 /* Various combination of flags for -mrecip=xxx. */
298 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
299 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
300 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
302 RECIP_HIGH_PRECISION = RECIP_ALL,
304 /* On low precision machines like the power5, don't enable double precision
305 reciprocal square root estimate, since it isn't accurate enough. */
306 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
309 /* -mrecip options. */
312 const char *string; /* option name */
313 unsigned int mask; /* mask bits to set */
314 } recip_options[] = {
315 { "all", RECIP_ALL },
316 { "none", RECIP_NONE },
317 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
319 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
320 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
321 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
322 | RECIP_V2DF_RSQRT) },
323 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
324 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
327 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
333 { "power9", PPC_PLATFORM_POWER9 },
334 { "power8", PPC_PLATFORM_POWER8 },
335 { "power7", PPC_PLATFORM_POWER7 },
336 { "power6x", PPC_PLATFORM_POWER6X },
337 { "power6", PPC_PLATFORM_POWER6 },
338 { "power5+", PPC_PLATFORM_POWER5_PLUS },
339 { "power5", PPC_PLATFORM_POWER5 },
340 { "ppc970", PPC_PLATFORM_PPC970 },
341 { "power4", PPC_PLATFORM_POWER4 },
342 { "ppca2", PPC_PLATFORM_PPCA2 },
343 { "ppc476", PPC_PLATFORM_PPC476 },
344 { "ppc464", PPC_PLATFORM_PPC464 },
345 { "ppc440", PPC_PLATFORM_PPC440 },
346 { "ppc405", PPC_PLATFORM_PPC405 },
347 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
350 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
356 } cpu_supports_info[] = {
357 /* AT_HWCAP masks. */
358 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
359 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
360 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
361 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
362 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
363 { "booke", PPC_FEATURE_BOOKE, 0 },
364 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
365 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
366 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
367 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
368 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
369 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
370 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
371 { "notb", PPC_FEATURE_NO_TB, 0 },
372 { "pa6t", PPC_FEATURE_PA6T, 0 },
373 { "power4", PPC_FEATURE_POWER4, 0 },
374 { "power5", PPC_FEATURE_POWER5, 0 },
375 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
376 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
377 { "ppc32", PPC_FEATURE_32, 0 },
378 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
379 { "ppc64", PPC_FEATURE_64, 0 },
380 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
381 { "smt", PPC_FEATURE_SMT, 0 },
382 { "spe", PPC_FEATURE_HAS_SPE, 0 },
383 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
384 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
385 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
387 /* AT_HWCAP2 masks. */
388 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
389 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
390 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
391 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
392 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
393 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
394 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
395 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
396 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
397 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
398 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
399 { "darn", PPC_FEATURE2_DARN, 1 },
400 { "scv", PPC_FEATURE2_SCV, 1 }
403 /* On PowerPC, we have a limited number of target clones that we care about
404 which means we can use an array to hold the options, rather than having more
405 elaborate data structures to identify each possible variation. Order the
406 clones from the default to the highest ISA. */
408 CLONE_DEFAULT = 0, /* default clone. */
409 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
410 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
411 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
412 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
416 /* Map compiler ISA bits into HWCAP names. */
418 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
419 const char *name; /* name to use in __builtin_cpu_supports. */
422 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
423 { 0, "" }, /* Default options. */
424 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
425 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
426 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
427 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
431 /* Newer LIBCs explicitly export this symbol to declare that they provide
432 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
433 reference to this symbol whenever we expand a CPU builtin, so that
434 we never link against an old LIBC. */
435 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
437 /* True if we have expanded a CPU builtin. */
440 /* Pointer to function (in rs6000-c.c) that can define or undefine target
441 macros that have changed. Languages that don't support the preprocessor
442 don't link in rs6000-c.c, so we can't call it directly. */
443 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
445 /* Simplfy register classes into simpler classifications. We assume
446 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
447 check for standard register classes (gpr/floating/altivec/vsx) and
448 floating/vector classes (float/altivec/vsx). */
450 enum rs6000_reg_type {
461 /* Map register class to register type. */
462 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
464 /* First/last register type for the 'normal' register types (i.e. general
465 purpose, floating point, altivec, and VSX registers). */
466 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
468 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
471 /* Register classes we care about in secondary reload or go if legitimate
472 address. We only need to worry about GPR, FPR, and Altivec registers here,
473 along an ANY field that is the OR of the 3 register classes. */
475 enum rs6000_reload_reg_type {
476 RELOAD_REG_GPR, /* General purpose registers. */
477 RELOAD_REG_FPR, /* Traditional floating point regs. */
478 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
479 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
483 /* For setting up register classes, loop through the 3 register classes mapping
484 into real registers, and skip the ANY class, which is just an OR of the
486 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
487 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
489 /* Map reload register type to a register in the register class. */
490 struct reload_reg_map_type {
491 const char *name; /* Register class name. */
492 int reg; /* Register in the register class. */
495 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
496 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
497 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
498 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
499 { "Any", -1 }, /* RELOAD_REG_ANY. */
502 /* Mask bits for each register class, indexed per mode. Historically the
503 compiler has been more restrictive which types can do PRE_MODIFY instead of
504 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
505 typedef unsigned char addr_mask_type;
507 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
508 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
509 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
510 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
511 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
512 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
513 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
514 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
516 /* Register type masks based on the type, of valid addressing modes. */
517 struct rs6000_reg_addr {
518 enum insn_code reload_load; /* INSN to reload for loading. */
519 enum insn_code reload_store; /* INSN to reload for storing. */
520 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
521 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
522 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
523 enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */
524 /* INSNs for fusing addi with loads
525 or stores for each reg. class. */
526 enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
527 enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
528 /* INSNs for fusing addis with loads
529 or stores for each reg. class. */
530 enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
531 enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
532 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
533 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
534 bool fused_toc; /* Mode supports TOC fusion. */
537 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
539 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
541 mode_supports_pre_incdec_p (machine_mode mode)
543 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
547 /* Helper function to say whether a mode supports PRE_MODIFY. */
549 mode_supports_pre_modify_p (machine_mode mode)
551 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
555 /* Given that there exists at least one variable that is set (produced)
556 by OUT_INSN and read (consumed) by IN_INSN, return true iff
557 IN_INSN represents one or more memory store operations and none of
558 the variables set by OUT_INSN is used by IN_INSN as the address of a
559 store operation. If either IN_INSN or OUT_INSN does not represent
560 a "single" RTL SET expression (as loosely defined by the
561 implementation of the single_set function) or a PARALLEL with only
562 SETs, CLOBBERs, and USEs inside, this function returns false.
564 This rs6000-specific version of store_data_bypass_p checks for
565 certain conditions that result in assertion failures (and internal
566 compiler errors) in the generic store_data_bypass_p function and
567 returns false rather than calling store_data_bypass_p if one of the
568 problematic conditions is detected. */
571 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
578 in_set = single_set (in_insn);
581 if (MEM_P (SET_DEST (in_set)))
583 out_set = single_set (out_insn);
586 out_pat = PATTERN (out_insn);
587 if (GET_CODE (out_pat) == PARALLEL)
589 for (i = 0; i < XVECLEN (out_pat, 0); i++)
591 out_exp = XVECEXP (out_pat, 0, i);
592 if ((GET_CODE (out_exp) == CLOBBER)
593 || (GET_CODE (out_exp) == USE))
595 else if (GET_CODE (out_exp) != SET)
604 in_pat = PATTERN (in_insn);
605 if (GET_CODE (in_pat) != PARALLEL)
608 for (i = 0; i < XVECLEN (in_pat, 0); i++)
610 in_exp = XVECEXP (in_pat, 0, i);
611 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
613 else if (GET_CODE (in_exp) != SET)
616 if (MEM_P (SET_DEST (in_exp)))
618 out_set = single_set (out_insn);
621 out_pat = PATTERN (out_insn);
622 if (GET_CODE (out_pat) != PARALLEL)
624 for (j = 0; j < XVECLEN (out_pat, 0); j++)
626 out_exp = XVECEXP (out_pat, 0, j);
627 if ((GET_CODE (out_exp) == CLOBBER)
628 || (GET_CODE (out_exp) == USE))
630 else if (GET_CODE (out_exp) != SET)
637 return store_data_bypass_p (out_insn, in_insn);
640 /* Return true if we have D-form addressing in altivec registers. */
642 mode_supports_vmx_dform (machine_mode mode)
644 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
647 /* Return true if we have D-form addressing in VSX registers. This addressing
648 is more limited than normal d-form addressing in that the offset must be
649 aligned on a 16-byte boundary. */
651 mode_supports_vsx_dform_quad (machine_mode mode)
653 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
658 /* Processor costs (relative to an add) */
660 const struct processor_costs *rs6000_cost;
662 /* Instruction size costs on 32bit processors. */
664 struct processor_costs size32_cost = {
665 COSTS_N_INSNS (1), /* mulsi */
666 COSTS_N_INSNS (1), /* mulsi_const */
667 COSTS_N_INSNS (1), /* mulsi_const9 */
668 COSTS_N_INSNS (1), /* muldi */
669 COSTS_N_INSNS (1), /* divsi */
670 COSTS_N_INSNS (1), /* divdi */
671 COSTS_N_INSNS (1), /* fp */
672 COSTS_N_INSNS (1), /* dmul */
673 COSTS_N_INSNS (1), /* sdiv */
674 COSTS_N_INSNS (1), /* ddiv */
675 32, /* cache line size */
679 0, /* SF->DF convert */
682 /* Instruction size costs on 64bit processors. */
684 struct processor_costs size64_cost = {
685 COSTS_N_INSNS (1), /* mulsi */
686 COSTS_N_INSNS (1), /* mulsi_const */
687 COSTS_N_INSNS (1), /* mulsi_const9 */
688 COSTS_N_INSNS (1), /* muldi */
689 COSTS_N_INSNS (1), /* divsi */
690 COSTS_N_INSNS (1), /* divdi */
691 COSTS_N_INSNS (1), /* fp */
692 COSTS_N_INSNS (1), /* dmul */
693 COSTS_N_INSNS (1), /* sdiv */
694 COSTS_N_INSNS (1), /* ddiv */
695 128, /* cache line size */
699 0, /* SF->DF convert */
702 /* Instruction costs on RS64A processors. */
704 struct processor_costs rs64a_cost = {
705 COSTS_N_INSNS (20), /* mulsi */
706 COSTS_N_INSNS (12), /* mulsi_const */
707 COSTS_N_INSNS (8), /* mulsi_const9 */
708 COSTS_N_INSNS (34), /* muldi */
709 COSTS_N_INSNS (65), /* divsi */
710 COSTS_N_INSNS (67), /* divdi */
711 COSTS_N_INSNS (4), /* fp */
712 COSTS_N_INSNS (4), /* dmul */
713 COSTS_N_INSNS (31), /* sdiv */
714 COSTS_N_INSNS (31), /* ddiv */
715 128, /* cache line size */
719 0, /* SF->DF convert */
722 /* Instruction costs on MPCCORE processors. */
724 struct processor_costs mpccore_cost = {
725 COSTS_N_INSNS (2), /* mulsi */
726 COSTS_N_INSNS (2), /* mulsi_const */
727 COSTS_N_INSNS (2), /* mulsi_const9 */
728 COSTS_N_INSNS (2), /* muldi */
729 COSTS_N_INSNS (6), /* divsi */
730 COSTS_N_INSNS (6), /* divdi */
731 COSTS_N_INSNS (4), /* fp */
732 COSTS_N_INSNS (5), /* dmul */
733 COSTS_N_INSNS (10), /* sdiv */
734 COSTS_N_INSNS (17), /* ddiv */
735 32, /* cache line size */
739 0, /* SF->DF convert */
742 /* Instruction costs on PPC403 processors. */
744 struct processor_costs ppc403_cost = {
745 COSTS_N_INSNS (4), /* mulsi */
746 COSTS_N_INSNS (4), /* mulsi_const */
747 COSTS_N_INSNS (4), /* mulsi_const9 */
748 COSTS_N_INSNS (4), /* muldi */
749 COSTS_N_INSNS (33), /* divsi */
750 COSTS_N_INSNS (33), /* divdi */
751 COSTS_N_INSNS (11), /* fp */
752 COSTS_N_INSNS (11), /* dmul */
753 COSTS_N_INSNS (11), /* sdiv */
754 COSTS_N_INSNS (11), /* ddiv */
755 32, /* cache line size */
759 0, /* SF->DF convert */
762 /* Instruction costs on PPC405 processors. */
764 struct processor_costs ppc405_cost = {
765 COSTS_N_INSNS (5), /* mulsi */
766 COSTS_N_INSNS (4), /* mulsi_const */
767 COSTS_N_INSNS (3), /* mulsi_const9 */
768 COSTS_N_INSNS (5), /* muldi */
769 COSTS_N_INSNS (35), /* divsi */
770 COSTS_N_INSNS (35), /* divdi */
771 COSTS_N_INSNS (11), /* fp */
772 COSTS_N_INSNS (11), /* dmul */
773 COSTS_N_INSNS (11), /* sdiv */
774 COSTS_N_INSNS (11), /* ddiv */
775 32, /* cache line size */
779 0, /* SF->DF convert */
782 /* Instruction costs on PPC440 processors. */
784 struct processor_costs ppc440_cost = {
785 COSTS_N_INSNS (3), /* mulsi */
786 COSTS_N_INSNS (2), /* mulsi_const */
787 COSTS_N_INSNS (2), /* mulsi_const9 */
788 COSTS_N_INSNS (3), /* muldi */
789 COSTS_N_INSNS (34), /* divsi */
790 COSTS_N_INSNS (34), /* divdi */
791 COSTS_N_INSNS (5), /* fp */
792 COSTS_N_INSNS (5), /* dmul */
793 COSTS_N_INSNS (19), /* sdiv */
794 COSTS_N_INSNS (33), /* ddiv */
795 32, /* cache line size */
799 0, /* SF->DF convert */
802 /* Instruction costs on PPC476 processors. */
804 struct processor_costs ppc476_cost = {
805 COSTS_N_INSNS (4), /* mulsi */
806 COSTS_N_INSNS (4), /* mulsi_const */
807 COSTS_N_INSNS (4), /* mulsi_const9 */
808 COSTS_N_INSNS (4), /* muldi */
809 COSTS_N_INSNS (11), /* divsi */
810 COSTS_N_INSNS (11), /* divdi */
811 COSTS_N_INSNS (6), /* fp */
812 COSTS_N_INSNS (6), /* dmul */
813 COSTS_N_INSNS (19), /* sdiv */
814 COSTS_N_INSNS (33), /* ddiv */
815 32, /* l1 cache line size */
819 0, /* SF->DF convert */
822 /* Instruction costs on PPC601 processors. */
824 struct processor_costs ppc601_cost = {
825 COSTS_N_INSNS (5), /* mulsi */
826 COSTS_N_INSNS (5), /* mulsi_const */
827 COSTS_N_INSNS (5), /* mulsi_const9 */
828 COSTS_N_INSNS (5), /* muldi */
829 COSTS_N_INSNS (36), /* divsi */
830 COSTS_N_INSNS (36), /* divdi */
831 COSTS_N_INSNS (4), /* fp */
832 COSTS_N_INSNS (5), /* dmul */
833 COSTS_N_INSNS (17), /* sdiv */
834 COSTS_N_INSNS (31), /* ddiv */
835 32, /* cache line size */
839 0, /* SF->DF convert */
842 /* Instruction costs on PPC603 processors. */
844 struct processor_costs ppc603_cost = {
845 COSTS_N_INSNS (5), /* mulsi */
846 COSTS_N_INSNS (3), /* mulsi_const */
847 COSTS_N_INSNS (2), /* mulsi_const9 */
848 COSTS_N_INSNS (5), /* muldi */
849 COSTS_N_INSNS (37), /* divsi */
850 COSTS_N_INSNS (37), /* divdi */
851 COSTS_N_INSNS (3), /* fp */
852 COSTS_N_INSNS (4), /* dmul */
853 COSTS_N_INSNS (18), /* sdiv */
854 COSTS_N_INSNS (33), /* ddiv */
855 32, /* cache line size */
859 0, /* SF->DF convert */
862 /* Instruction costs on PPC604 processors. */
864 struct processor_costs ppc604_cost = {
865 COSTS_N_INSNS (4), /* mulsi */
866 COSTS_N_INSNS (4), /* mulsi_const */
867 COSTS_N_INSNS (4), /* mulsi_const9 */
868 COSTS_N_INSNS (4), /* muldi */
869 COSTS_N_INSNS (20), /* divsi */
870 COSTS_N_INSNS (20), /* divdi */
871 COSTS_N_INSNS (3), /* fp */
872 COSTS_N_INSNS (3), /* dmul */
873 COSTS_N_INSNS (18), /* sdiv */
874 COSTS_N_INSNS (32), /* ddiv */
875 32, /* cache line size */
879 0, /* SF->DF convert */
882 /* Instruction costs on PPC604e processors. */
884 struct processor_costs ppc604e_cost = {
885 COSTS_N_INSNS (2), /* mulsi */
886 COSTS_N_INSNS (2), /* mulsi_const */
887 COSTS_N_INSNS (2), /* mulsi_const9 */
888 COSTS_N_INSNS (2), /* muldi */
889 COSTS_N_INSNS (20), /* divsi */
890 COSTS_N_INSNS (20), /* divdi */
891 COSTS_N_INSNS (3), /* fp */
892 COSTS_N_INSNS (3), /* dmul */
893 COSTS_N_INSNS (18), /* sdiv */
894 COSTS_N_INSNS (32), /* ddiv */
895 32, /* cache line size */
899 0, /* SF->DF convert */
902 /* Instruction costs on PPC620 processors. */
904 struct processor_costs ppc620_cost = {
905 COSTS_N_INSNS (5), /* mulsi */
906 COSTS_N_INSNS (4), /* mulsi_const */
907 COSTS_N_INSNS (3), /* mulsi_const9 */
908 COSTS_N_INSNS (7), /* muldi */
909 COSTS_N_INSNS (21), /* divsi */
910 COSTS_N_INSNS (37), /* divdi */
911 COSTS_N_INSNS (3), /* fp */
912 COSTS_N_INSNS (3), /* dmul */
913 COSTS_N_INSNS (18), /* sdiv */
914 COSTS_N_INSNS (32), /* ddiv */
915 128, /* cache line size */
919 0, /* SF->DF convert */
922 /* Instruction costs on PPC630 processors. */
924 struct processor_costs ppc630_cost = {
925 COSTS_N_INSNS (5), /* mulsi */
926 COSTS_N_INSNS (4), /* mulsi_const */
927 COSTS_N_INSNS (3), /* mulsi_const9 */
928 COSTS_N_INSNS (7), /* muldi */
929 COSTS_N_INSNS (21), /* divsi */
930 COSTS_N_INSNS (37), /* divdi */
931 COSTS_N_INSNS (3), /* fp */
932 COSTS_N_INSNS (3), /* dmul */
933 COSTS_N_INSNS (17), /* sdiv */
934 COSTS_N_INSNS (21), /* ddiv */
935 128, /* cache line size */
939 0, /* SF->DF convert */
942 /* Instruction costs on Cell processor. */
943 /* COSTS_N_INSNS (1) ~ one add. */
945 struct processor_costs ppccell_cost = {
946 COSTS_N_INSNS (9/2)+2, /* mulsi */
947 COSTS_N_INSNS (6/2), /* mulsi_const */
948 COSTS_N_INSNS (6/2), /* mulsi_const9 */
949 COSTS_N_INSNS (15/2)+2, /* muldi */
950 COSTS_N_INSNS (38/2), /* divsi */
951 COSTS_N_INSNS (70/2), /* divdi */
952 COSTS_N_INSNS (10/2), /* fp */
953 COSTS_N_INSNS (10/2), /* dmul */
954 COSTS_N_INSNS (74/2), /* sdiv */
955 COSTS_N_INSNS (74/2), /* ddiv */
956 128, /* cache line size */
960 0, /* SF->DF convert */
963 /* Instruction costs on PPC750 and PPC7400 processors. */
965 struct processor_costs ppc750_cost = {
966 COSTS_N_INSNS (5), /* mulsi */
967 COSTS_N_INSNS (3), /* mulsi_const */
968 COSTS_N_INSNS (2), /* mulsi_const9 */
969 COSTS_N_INSNS (5), /* muldi */
970 COSTS_N_INSNS (17), /* divsi */
971 COSTS_N_INSNS (17), /* divdi */
972 COSTS_N_INSNS (3), /* fp */
973 COSTS_N_INSNS (3), /* dmul */
974 COSTS_N_INSNS (17), /* sdiv */
975 COSTS_N_INSNS (31), /* ddiv */
976 32, /* cache line size */
980 0, /* SF->DF convert */
983 /* Instruction costs on PPC7450 processors. */
985 struct processor_costs ppc7450_cost = {
986 COSTS_N_INSNS (4), /* mulsi */
987 COSTS_N_INSNS (3), /* mulsi_const */
988 COSTS_N_INSNS (3), /* mulsi_const9 */
989 COSTS_N_INSNS (4), /* muldi */
990 COSTS_N_INSNS (23), /* divsi */
991 COSTS_N_INSNS (23), /* divdi */
992 COSTS_N_INSNS (5), /* fp */
993 COSTS_N_INSNS (5), /* dmul */
994 COSTS_N_INSNS (21), /* sdiv */
995 COSTS_N_INSNS (35), /* ddiv */
996 32, /* cache line size */
1000 0, /* SF->DF convert */
1003 /* Instruction costs on PPC8540 processors. */
1005 struct processor_costs ppc8540_cost = {
1006 COSTS_N_INSNS (4), /* mulsi */
1007 COSTS_N_INSNS (4), /* mulsi_const */
1008 COSTS_N_INSNS (4), /* mulsi_const9 */
1009 COSTS_N_INSNS (4), /* muldi */
1010 COSTS_N_INSNS (19), /* divsi */
1011 COSTS_N_INSNS (19), /* divdi */
1012 COSTS_N_INSNS (4), /* fp */
1013 COSTS_N_INSNS (4), /* dmul */
1014 COSTS_N_INSNS (29), /* sdiv */
1015 COSTS_N_INSNS (29), /* ddiv */
1016 32, /* cache line size */
1019 1, /* prefetch streams /*/
1020 0, /* SF->DF convert */
1023 /* Instruction costs on E300C2 and E300C3 cores. */
1025 struct processor_costs ppce300c2c3_cost = {
1026 COSTS_N_INSNS (4), /* mulsi */
1027 COSTS_N_INSNS (4), /* mulsi_const */
1028 COSTS_N_INSNS (4), /* mulsi_const9 */
1029 COSTS_N_INSNS (4), /* muldi */
1030 COSTS_N_INSNS (19), /* divsi */
1031 COSTS_N_INSNS (19), /* divdi */
1032 COSTS_N_INSNS (3), /* fp */
1033 COSTS_N_INSNS (4), /* dmul */
1034 COSTS_N_INSNS (18), /* sdiv */
1035 COSTS_N_INSNS (33), /* ddiv */
1039 1, /* prefetch streams /*/
1040 0, /* SF->DF convert */
1043 /* Instruction costs on PPCE500MC processors. */
1045 struct processor_costs ppce500mc_cost = {
1046 COSTS_N_INSNS (4), /* mulsi */
1047 COSTS_N_INSNS (4), /* mulsi_const */
1048 COSTS_N_INSNS (4), /* mulsi_const9 */
1049 COSTS_N_INSNS (4), /* muldi */
1050 COSTS_N_INSNS (14), /* divsi */
1051 COSTS_N_INSNS (14), /* divdi */
1052 COSTS_N_INSNS (8), /* fp */
1053 COSTS_N_INSNS (10), /* dmul */
1054 COSTS_N_INSNS (36), /* sdiv */
1055 COSTS_N_INSNS (66), /* ddiv */
1056 64, /* cache line size */
1059 1, /* prefetch streams /*/
1060 0, /* SF->DF convert */
1063 /* Instruction costs on PPCE500MC64 processors. */
1065 struct processor_costs ppce500mc64_cost = {
1066 COSTS_N_INSNS (4), /* mulsi */
1067 COSTS_N_INSNS (4), /* mulsi_const */
1068 COSTS_N_INSNS (4), /* mulsi_const9 */
1069 COSTS_N_INSNS (4), /* muldi */
1070 COSTS_N_INSNS (14), /* divsi */
1071 COSTS_N_INSNS (14), /* divdi */
1072 COSTS_N_INSNS (4), /* fp */
1073 COSTS_N_INSNS (10), /* dmul */
1074 COSTS_N_INSNS (36), /* sdiv */
1075 COSTS_N_INSNS (66), /* ddiv */
1076 64, /* cache line size */
1079 1, /* prefetch streams /*/
1080 0, /* SF->DF convert */
1083 /* Instruction costs on PPCE5500 processors. */
1085 struct processor_costs ppce5500_cost = {
1086 COSTS_N_INSNS (5), /* mulsi */
1087 COSTS_N_INSNS (5), /* mulsi_const */
1088 COSTS_N_INSNS (4), /* mulsi_const9 */
1089 COSTS_N_INSNS (5), /* muldi */
1090 COSTS_N_INSNS (14), /* divsi */
1091 COSTS_N_INSNS (14), /* divdi */
1092 COSTS_N_INSNS (7), /* fp */
1093 COSTS_N_INSNS (10), /* dmul */
1094 COSTS_N_INSNS (36), /* sdiv */
1095 COSTS_N_INSNS (66), /* ddiv */
1096 64, /* cache line size */
1099 1, /* prefetch streams /*/
1100 0, /* SF->DF convert */
1103 /* Instruction costs on PPCE6500 processors. */
1105 struct processor_costs ppce6500_cost = {
1106 COSTS_N_INSNS (5), /* mulsi */
1107 COSTS_N_INSNS (5), /* mulsi_const */
1108 COSTS_N_INSNS (4), /* mulsi_const9 */
1109 COSTS_N_INSNS (5), /* muldi */
1110 COSTS_N_INSNS (14), /* divsi */
1111 COSTS_N_INSNS (14), /* divdi */
1112 COSTS_N_INSNS (7), /* fp */
1113 COSTS_N_INSNS (10), /* dmul */
1114 COSTS_N_INSNS (36), /* sdiv */
1115 COSTS_N_INSNS (66), /* ddiv */
1116 64, /* cache line size */
1119 1, /* prefetch streams /*/
1120 0, /* SF->DF convert */
1123 /* Instruction costs on AppliedMicro Titan processors. */
1125 struct processor_costs titan_cost = {
1126 COSTS_N_INSNS (5), /* mulsi */
1127 COSTS_N_INSNS (5), /* mulsi_const */
1128 COSTS_N_INSNS (5), /* mulsi_const9 */
1129 COSTS_N_INSNS (5), /* muldi */
1130 COSTS_N_INSNS (18), /* divsi */
1131 COSTS_N_INSNS (18), /* divdi */
1132 COSTS_N_INSNS (10), /* fp */
1133 COSTS_N_INSNS (10), /* dmul */
1134 COSTS_N_INSNS (46), /* sdiv */
1135 COSTS_N_INSNS (72), /* ddiv */
1136 32, /* cache line size */
1139 1, /* prefetch streams /*/
1140 0, /* SF->DF convert */
1143 /* Instruction costs on POWER4 and POWER5 processors. */
1145 struct processor_costs power4_cost = {
1146 COSTS_N_INSNS (3), /* mulsi */
1147 COSTS_N_INSNS (2), /* mulsi_const */
1148 COSTS_N_INSNS (2), /* mulsi_const9 */
1149 COSTS_N_INSNS (4), /* muldi */
1150 COSTS_N_INSNS (18), /* divsi */
1151 COSTS_N_INSNS (34), /* divdi */
1152 COSTS_N_INSNS (3), /* fp */
1153 COSTS_N_INSNS (3), /* dmul */
1154 COSTS_N_INSNS (17), /* sdiv */
1155 COSTS_N_INSNS (17), /* ddiv */
1156 128, /* cache line size */
1158 1024, /* l2 cache */
1159 8, /* prefetch streams /*/
1160 0, /* SF->DF convert */
1163 /* Instruction costs on POWER6 processors. */
1165 struct processor_costs power6_cost = {
1166 COSTS_N_INSNS (8), /* mulsi */
1167 COSTS_N_INSNS (8), /* mulsi_const */
1168 COSTS_N_INSNS (8), /* mulsi_const9 */
1169 COSTS_N_INSNS (8), /* muldi */
1170 COSTS_N_INSNS (22), /* divsi */
1171 COSTS_N_INSNS (28), /* divdi */
1172 COSTS_N_INSNS (3), /* fp */
1173 COSTS_N_INSNS (3), /* dmul */
1174 COSTS_N_INSNS (13), /* sdiv */
1175 COSTS_N_INSNS (16), /* ddiv */
1176 128, /* cache line size */
1178 2048, /* l2 cache */
1179 16, /* prefetch streams */
1180 0, /* SF->DF convert */
1183 /* Instruction costs on POWER7 processors. */
1185 struct processor_costs power7_cost = {
1186 COSTS_N_INSNS (2), /* mulsi */
1187 COSTS_N_INSNS (2), /* mulsi_const */
1188 COSTS_N_INSNS (2), /* mulsi_const9 */
1189 COSTS_N_INSNS (2), /* muldi */
1190 COSTS_N_INSNS (18), /* divsi */
1191 COSTS_N_INSNS (34), /* divdi */
1192 COSTS_N_INSNS (3), /* fp */
1193 COSTS_N_INSNS (3), /* dmul */
1194 COSTS_N_INSNS (13), /* sdiv */
1195 COSTS_N_INSNS (16), /* ddiv */
1196 128, /* cache line size */
1199 12, /* prefetch streams */
1200 COSTS_N_INSNS (3), /* SF->DF convert */
1203 /* Instruction costs on POWER8 processors. */
1205 struct processor_costs power8_cost = {
1206 COSTS_N_INSNS (3), /* mulsi */
1207 COSTS_N_INSNS (3), /* mulsi_const */
1208 COSTS_N_INSNS (3), /* mulsi_const9 */
1209 COSTS_N_INSNS (3), /* muldi */
1210 COSTS_N_INSNS (19), /* divsi */
1211 COSTS_N_INSNS (35), /* divdi */
1212 COSTS_N_INSNS (3), /* fp */
1213 COSTS_N_INSNS (3), /* dmul */
1214 COSTS_N_INSNS (14), /* sdiv */
1215 COSTS_N_INSNS (17), /* ddiv */
1216 128, /* cache line size */
1219 12, /* prefetch streams */
1220 COSTS_N_INSNS (3), /* SF->DF convert */
1223 /* Instruction costs on POWER9 processors. */
1225 struct processor_costs power9_cost = {
1226 COSTS_N_INSNS (3), /* mulsi */
1227 COSTS_N_INSNS (3), /* mulsi_const */
1228 COSTS_N_INSNS (3), /* mulsi_const9 */
1229 COSTS_N_INSNS (3), /* muldi */
1230 COSTS_N_INSNS (8), /* divsi */
1231 COSTS_N_INSNS (12), /* divdi */
1232 COSTS_N_INSNS (3), /* fp */
1233 COSTS_N_INSNS (3), /* dmul */
1234 COSTS_N_INSNS (13), /* sdiv */
1235 COSTS_N_INSNS (18), /* ddiv */
1236 128, /* cache line size */
1239 8, /* prefetch streams */
1240 COSTS_N_INSNS (3), /* SF->DF convert */
1243 /* Instruction costs on POWER A2 processors. */
1245 struct processor_costs ppca2_cost = {
1246 COSTS_N_INSNS (16), /* mulsi */
1247 COSTS_N_INSNS (16), /* mulsi_const */
1248 COSTS_N_INSNS (16), /* mulsi_const9 */
1249 COSTS_N_INSNS (16), /* muldi */
1250 COSTS_N_INSNS (22), /* divsi */
1251 COSTS_N_INSNS (28), /* divdi */
1252 COSTS_N_INSNS (3), /* fp */
1253 COSTS_N_INSNS (3), /* dmul */
1254 COSTS_N_INSNS (59), /* sdiv */
1255 COSTS_N_INSNS (72), /* ddiv */
1258 2048, /* l2 cache */
1259 16, /* prefetch streams */
1260 0, /* SF->DF convert */
1264 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1265 #undef RS6000_BUILTIN_0
1266 #undef RS6000_BUILTIN_1
1267 #undef RS6000_BUILTIN_2
1268 #undef RS6000_BUILTIN_3
1269 #undef RS6000_BUILTIN_A
1270 #undef RS6000_BUILTIN_D
1271 #undef RS6000_BUILTIN_H
1272 #undef RS6000_BUILTIN_P
1273 #undef RS6000_BUILTIN_Q
1274 #undef RS6000_BUILTIN_X
1276 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1277 { NAME, ICODE, MASK, ATTR },
1279 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1280 { NAME, ICODE, MASK, ATTR },
1282 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1283 { NAME, ICODE, MASK, ATTR },
1285 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1286 { NAME, ICODE, MASK, ATTR },
1288 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1289 { NAME, ICODE, MASK, ATTR },
1291 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1292 { NAME, ICODE, MASK, ATTR },
1294 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1295 { NAME, ICODE, MASK, ATTR },
1297 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1298 { NAME, ICODE, MASK, ATTR },
1300 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1301 { NAME, ICODE, MASK, ATTR },
1303 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1304 { NAME, ICODE, MASK, ATTR },
1306 struct rs6000_builtin_info_type {
1308 const enum insn_code icode;
1309 const HOST_WIDE_INT mask;
1310 const unsigned attr;
1313 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1315 #include "rs6000-builtin.def"
1318 #undef RS6000_BUILTIN_0
1319 #undef RS6000_BUILTIN_1
1320 #undef RS6000_BUILTIN_2
1321 #undef RS6000_BUILTIN_3
1322 #undef RS6000_BUILTIN_A
1323 #undef RS6000_BUILTIN_D
1324 #undef RS6000_BUILTIN_H
1325 #undef RS6000_BUILTIN_P
1326 #undef RS6000_BUILTIN_Q
1327 #undef RS6000_BUILTIN_X
1329 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1330 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1333 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1334 static struct machine_function * rs6000_init_machine_status (void);
1335 static int rs6000_ra_ever_killed (void);
1336 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1337 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1338 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1339 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1340 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1341 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1342 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1343 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1345 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1347 static bool is_microcoded_insn (rtx_insn *);
1348 static bool is_nonpipeline_insn (rtx_insn *);
1349 static bool is_cracked_insn (rtx_insn *);
1350 static bool is_load_insn (rtx, rtx *);
1351 static bool is_store_insn (rtx, rtx *);
1352 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1353 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1354 static bool insn_must_be_first_in_group (rtx_insn *);
1355 static bool insn_must_be_last_in_group (rtx_insn *);
1356 static void altivec_init_builtins (void);
1357 static tree builtin_function_type (machine_mode, machine_mode,
1358 machine_mode, machine_mode,
1359 enum rs6000_builtins, const char *name);
1360 static void rs6000_common_init_builtins (void);
1361 static void paired_init_builtins (void);
1362 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1363 static void htm_init_builtins (void);
1364 static rs6000_stack_t *rs6000_stack_info (void);
1365 static void is_altivec_return_reg (rtx, void *);
1366 int easy_vector_constant (rtx, machine_mode);
1367 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1368 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1369 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1372 static void macho_branch_islands (void);
1374 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1376 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1378 static bool rs6000_mode_dependent_address (const_rtx);
1379 static bool rs6000_debug_mode_dependent_address (const_rtx);
1380 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1382 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1385 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1386 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1388 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1391 static bool rs6000_debug_can_change_mode_class (machine_mode,
1394 static bool rs6000_save_toc_in_prologue_p (void);
1395 static rtx rs6000_internal_arg_pointer (void);
1397 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1399 = rs6000_legitimize_reload_address;
1401 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1402 = rs6000_mode_dependent_address;
1404 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1406 = rs6000_secondary_reload_class;
1408 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1409 = rs6000_preferred_reload_class;
1411 const int INSN_NOT_AVAILABLE = -1;
1413 static void rs6000_print_isa_options (FILE *, int, const char *,
1415 static void rs6000_print_builtin_options (FILE *, int, const char *,
1417 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1419 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1420 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1421 enum rs6000_reg_type,
1423 secondary_reload_info *,
1425 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1426 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1427 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1429 /* Hash table stuff for keeping track of TOC entries. */
1431 struct GTY((for_user)) toc_hash_struct
1433 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1434 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1436 machine_mode key_mode;
1440 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1442 static hashval_t hash (toc_hash_struct *);
1443 static bool equal (toc_hash_struct *, toc_hash_struct *);
1446 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1448 /* Hash table to keep track of the argument types for builtin functions. */
1450 struct GTY((for_user)) builtin_hash_struct
1453 machine_mode mode[4]; /* return value + 3 arguments. */
1454 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1457 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1459 static hashval_t hash (builtin_hash_struct *);
1460 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1463 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1466 /* Default register names. */
1467 char rs6000_reg_names[][8] =
1469 "0", "1", "2", "3", "4", "5", "6", "7",
1470 "8", "9", "10", "11", "12", "13", "14", "15",
1471 "16", "17", "18", "19", "20", "21", "22", "23",
1472 "24", "25", "26", "27", "28", "29", "30", "31",
1473 "0", "1", "2", "3", "4", "5", "6", "7",
1474 "8", "9", "10", "11", "12", "13", "14", "15",
1475 "16", "17", "18", "19", "20", "21", "22", "23",
1476 "24", "25", "26", "27", "28", "29", "30", "31",
1477 "mq", "lr", "ctr","ap",
1478 "0", "1", "2", "3", "4", "5", "6", "7",
1480 /* AltiVec registers. */
1481 "0", "1", "2", "3", "4", "5", "6", "7",
1482 "8", "9", "10", "11", "12", "13", "14", "15",
1483 "16", "17", "18", "19", "20", "21", "22", "23",
1484 "24", "25", "26", "27", "28", "29", "30", "31",
1486 /* Soft frame pointer. */
1488 /* HTM SPR registers. */
1489 "tfhar", "tfiar", "texasr"
1492 #ifdef TARGET_REGNAMES
1493 static const char alt_reg_names[][8] =
1495 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1496 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1497 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1498 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1499 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1500 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1501 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1502 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1503 "mq", "lr", "ctr", "ap",
1504 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1506 /* AltiVec registers. */
1507 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1508 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1509 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1510 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1512 /* Soft frame pointer. */
1514 /* HTM SPR registers. */
1515 "tfhar", "tfiar", "texasr"
1519 /* Table of valid machine attributes. */
1521 static const struct attribute_spec rs6000_attribute_table[] =
1523 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1524 affects_type_identity, handler, exclude } */
1525 { "altivec", 1, 1, false, true, false, false,
1526 rs6000_handle_altivec_attribute, NULL },
1527 { "longcall", 0, 0, false, true, true, false,
1528 rs6000_handle_longcall_attribute, NULL },
1529 { "shortcall", 0, 0, false, true, true, false,
1530 rs6000_handle_longcall_attribute, NULL },
1531 { "ms_struct", 0, 0, false, false, false, false,
1532 rs6000_handle_struct_attribute, NULL },
1533 { "gcc_struct", 0, 0, false, false, false, false,
1534 rs6000_handle_struct_attribute, NULL },
1535 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1536 SUBTARGET_ATTRIBUTE_TABLE,
1538 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1541 #ifndef TARGET_PROFILE_KERNEL
1542 #define TARGET_PROFILE_KERNEL 0
1545 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1546 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1548 /* Initialize the GCC target structure. */
1549 #undef TARGET_ATTRIBUTE_TABLE
1550 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1551 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1552 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1553 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1554 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1556 #undef TARGET_ASM_ALIGNED_DI_OP
1557 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1559 /* Default unaligned ops are only provided for ELF. Find the ops needed
1560 for non-ELF systems. */
1561 #ifndef OBJECT_FORMAT_ELF
1563 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1565 #undef TARGET_ASM_UNALIGNED_HI_OP
1566 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1567 #undef TARGET_ASM_UNALIGNED_SI_OP
1568 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1569 #undef TARGET_ASM_UNALIGNED_DI_OP
1570 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1573 #undef TARGET_ASM_UNALIGNED_HI_OP
1574 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1575 #undef TARGET_ASM_UNALIGNED_SI_OP
1576 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1577 #undef TARGET_ASM_UNALIGNED_DI_OP
1578 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1579 #undef TARGET_ASM_ALIGNED_DI_OP
1580 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1584 /* This hook deals with fixups for relocatable code and DI-mode objects
1586 #undef TARGET_ASM_INTEGER
1587 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1589 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1590 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1591 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1594 #undef TARGET_SET_UP_BY_PROLOGUE
1595 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1597 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1598 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1599 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1600 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1601 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1602 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1603 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1604 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1605 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1606 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1607 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1608 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1610 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1611 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1613 #undef TARGET_INTERNAL_ARG_POINTER
1614 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1616 #undef TARGET_HAVE_TLS
1617 #define TARGET_HAVE_TLS HAVE_AS_TLS
1619 #undef TARGET_CANNOT_FORCE_CONST_MEM
1620 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1622 #undef TARGET_DELEGITIMIZE_ADDRESS
1623 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1625 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1626 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1628 #undef TARGET_LEGITIMATE_COMBINED_INSN
1629 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1631 #undef TARGET_ASM_FUNCTION_PROLOGUE
1632 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1633 #undef TARGET_ASM_FUNCTION_EPILOGUE
1634 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1636 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1637 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1639 #undef TARGET_LEGITIMIZE_ADDRESS
1640 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1642 #undef TARGET_SCHED_VARIABLE_ISSUE
1643 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1645 #undef TARGET_SCHED_ISSUE_RATE
1646 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1647 #undef TARGET_SCHED_ADJUST_COST
1648 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1649 #undef TARGET_SCHED_ADJUST_PRIORITY
1650 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1651 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1652 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1653 #undef TARGET_SCHED_INIT
1654 #define TARGET_SCHED_INIT rs6000_sched_init
1655 #undef TARGET_SCHED_FINISH
1656 #define TARGET_SCHED_FINISH rs6000_sched_finish
1657 #undef TARGET_SCHED_REORDER
1658 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1659 #undef TARGET_SCHED_REORDER2
1660 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1662 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1663 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1665 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1666 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1668 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1669 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1670 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1671 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1672 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1673 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1674 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1675 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1677 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1678 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1680 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1681 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1682 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1683 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1684 rs6000_builtin_support_vector_misalignment
1685 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1686 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1687 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1688 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1689 rs6000_builtin_vectorization_cost
1690 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1691 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1692 rs6000_preferred_simd_mode
1693 #undef TARGET_VECTORIZE_INIT_COST
1694 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1695 #undef TARGET_VECTORIZE_ADD_STMT_COST
1696 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1697 #undef TARGET_VECTORIZE_FINISH_COST
1698 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1699 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1700 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1702 #undef TARGET_INIT_BUILTINS
1703 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1704 #undef TARGET_BUILTIN_DECL
1705 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1707 #undef TARGET_FOLD_BUILTIN
1708 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1709 #undef TARGET_GIMPLE_FOLD_BUILTIN
1710 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1712 #undef TARGET_EXPAND_BUILTIN
1713 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1715 #undef TARGET_MANGLE_TYPE
1716 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1718 #undef TARGET_INIT_LIBFUNCS
1719 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1722 #undef TARGET_BINDS_LOCAL_P
1723 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1726 #undef TARGET_MS_BITFIELD_LAYOUT_P
1727 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1729 #undef TARGET_ASM_OUTPUT_MI_THUNK
1730 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1732 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1733 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1735 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1736 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1738 #undef TARGET_REGISTER_MOVE_COST
1739 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1740 #undef TARGET_MEMORY_MOVE_COST
1741 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1742 #undef TARGET_CANNOT_COPY_INSN_P
1743 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1744 #undef TARGET_RTX_COSTS
1745 #define TARGET_RTX_COSTS rs6000_rtx_costs
1746 #undef TARGET_ADDRESS_COST
1747 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1748 #undef TARGET_INSN_COST
1749 #define TARGET_INSN_COST rs6000_insn_cost
1751 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1752 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1754 #undef TARGET_PROMOTE_FUNCTION_MODE
1755 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1757 #undef TARGET_RETURN_IN_MEMORY
1758 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1760 #undef TARGET_RETURN_IN_MSB
1761 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1763 #undef TARGET_SETUP_INCOMING_VARARGS
1764 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1766 /* Always strict argument naming on rs6000. */
1767 #undef TARGET_STRICT_ARGUMENT_NAMING
1768 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1769 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1770 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1771 #undef TARGET_SPLIT_COMPLEX_ARG
1772 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1773 #undef TARGET_MUST_PASS_IN_STACK
1774 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1775 #undef TARGET_PASS_BY_REFERENCE
1776 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1777 #undef TARGET_ARG_PARTIAL_BYTES
1778 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1779 #undef TARGET_FUNCTION_ARG_ADVANCE
1780 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1781 #undef TARGET_FUNCTION_ARG
1782 #define TARGET_FUNCTION_ARG rs6000_function_arg
1783 #undef TARGET_FUNCTION_ARG_PADDING
1784 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1785 #undef TARGET_FUNCTION_ARG_BOUNDARY
1786 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1788 #undef TARGET_BUILD_BUILTIN_VA_LIST
1789 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1791 #undef TARGET_EXPAND_BUILTIN_VA_START
1792 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1794 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1795 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1797 #undef TARGET_EH_RETURN_FILTER_MODE
1798 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1800 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1801 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1803 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1804 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1806 #undef TARGET_FLOATN_MODE
1807 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1809 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1810 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1812 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1813 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1815 #undef TARGET_MD_ASM_ADJUST
1816 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1818 #undef TARGET_OPTION_OVERRIDE
1819 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1821 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1822 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1823 rs6000_builtin_vectorized_function
1825 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1826 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1827 rs6000_builtin_md_vectorized_function
1829 #undef TARGET_STACK_PROTECT_GUARD
1830 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1833 #undef TARGET_STACK_PROTECT_FAIL
1834 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1838 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1839 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1842 /* Use a 32-bit anchor range. This leads to sequences like:
1844 addis tmp,anchor,high
1847 where tmp itself acts as an anchor, and can be shared between
1848 accesses to the same 64k page. */
1849 #undef TARGET_MIN_ANCHOR_OFFSET
1850 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1851 #undef TARGET_MAX_ANCHOR_OFFSET
1852 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1853 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1854 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1855 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1856 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1858 #undef TARGET_BUILTIN_RECIPROCAL
1859 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1861 #undef TARGET_SECONDARY_RELOAD
1862 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1863 #undef TARGET_SECONDARY_MEMORY_NEEDED
1864 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1865 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1866 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1868 #undef TARGET_LEGITIMATE_ADDRESS_P
1869 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1871 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1872 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1874 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1875 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1877 #undef TARGET_CAN_ELIMINATE
1878 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1880 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1881 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1883 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1884 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1886 #undef TARGET_TRAMPOLINE_INIT
1887 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1889 #undef TARGET_FUNCTION_VALUE
1890 #define TARGET_FUNCTION_VALUE rs6000_function_value
1892 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1893 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1895 #undef TARGET_OPTION_SAVE
1896 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1898 #undef TARGET_OPTION_RESTORE
1899 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1901 #undef TARGET_OPTION_PRINT
1902 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1904 #undef TARGET_CAN_INLINE_P
1905 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1907 #undef TARGET_SET_CURRENT_FUNCTION
1908 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1910 #undef TARGET_LEGITIMATE_CONSTANT_P
1911 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1913 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1914 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1916 #undef TARGET_CAN_USE_DOLOOP_P
1917 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1919 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1920 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1922 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1923 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1924 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1925 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1926 #undef TARGET_UNWIND_WORD_MODE
1927 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1929 #undef TARGET_OFFLOAD_OPTIONS
1930 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1932 #undef TARGET_C_MODE_FOR_SUFFIX
1933 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1935 #undef TARGET_INVALID_BINARY_OP
1936 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1938 #undef TARGET_OPTAB_SUPPORTED_P
1939 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1941 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1942 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1944 #undef TARGET_COMPARE_VERSION_PRIORITY
1945 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1947 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1948 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1949 rs6000_generate_version_dispatcher_body
1951 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1952 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1953 rs6000_get_function_versions_dispatcher
1955 #undef TARGET_OPTION_FUNCTION_VERSIONS
1956 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1958 #undef TARGET_HARD_REGNO_NREGS
1959 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1960 #undef TARGET_HARD_REGNO_MODE_OK
1961 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1963 #undef TARGET_MODES_TIEABLE_P
1964 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1966 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1967 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1968 rs6000_hard_regno_call_part_clobbered
1970 #undef TARGET_SLOW_UNALIGNED_ACCESS
1971 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1973 #undef TARGET_CAN_CHANGE_MODE_CLASS
1974 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1976 #undef TARGET_CONSTANT_ALIGNMENT
1977 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1979 #undef TARGET_STARTING_FRAME_OFFSET
1980 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1983 /* Processor table. */
1986 const char *const name; /* Canonical processor name. */
1987 const enum processor_type processor; /* Processor type enum value. */
1988 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1991 static struct rs6000_ptt const processor_target_table[] =
1993 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1994 #include "rs6000-cpus.def"
1998 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2002 rs6000_cpu_name_lookup (const char *name)
2008 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2009 if (! strcmp (name, processor_target_table[i].name))
2017 /* Return number of consecutive hard regs needed starting at reg REGNO
2018 to hold something of mode MODE.
2019 This is ordinarily the length in words of a value of mode MODE
2020 but can be less for certain modes in special long registers.
2022 POWER and PowerPC GPRs hold 32 bits worth;
2023 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2026 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2028 unsigned HOST_WIDE_INT reg_size;
2030 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2031 128-bit floating point that can go in vector registers, which has VSX
2032 memory addressing. */
2033 if (FP_REGNO_P (regno))
2034 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2035 ? UNITS_PER_VSX_WORD
2036 : UNITS_PER_FP_WORD);
2038 else if (ALTIVEC_REGNO_P (regno))
2039 reg_size = UNITS_PER_ALTIVEC_WORD;
2042 reg_size = UNITS_PER_WORD;
2044 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2047 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2050 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2052 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2054 if (COMPLEX_MODE_P (mode))
2055 mode = GET_MODE_INNER (mode);
2057 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2058 register combinations, and use PTImode where we need to deal with quad
2059 word memory operations. Don't allow quad words in the argument or frame
2060 pointer registers, just registers 0..31. */
2061 if (mode == PTImode)
2062 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2063 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2064 && ((regno & 1) == 0));
2066 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2067 implementations. Don't allow an item to be split between a FP register
2068 and an Altivec register. Allow TImode in all VSX registers if the user
2070 if (TARGET_VSX && VSX_REGNO_P (regno)
2071 && (VECTOR_MEM_VSX_P (mode)
2072 || FLOAT128_VECTOR_P (mode)
2073 || reg_addr[mode].scalar_in_vmx_p
2075 || (TARGET_VADDUQM && mode == V1TImode)))
2077 if (FP_REGNO_P (regno))
2078 return FP_REGNO_P (last_regno);
2080 if (ALTIVEC_REGNO_P (regno))
2082 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2085 return ALTIVEC_REGNO_P (last_regno);
2089 /* The GPRs can hold any mode, but values bigger than one register
2090 cannot go past R31. */
2091 if (INT_REGNO_P (regno))
2092 return INT_REGNO_P (last_regno);
2094 /* The float registers (except for VSX vector modes) can only hold floating
2095 modes and DImode. */
2096 if (FP_REGNO_P (regno))
2098 if (FLOAT128_VECTOR_P (mode))
2101 if (SCALAR_FLOAT_MODE_P (mode)
2102 && (mode != TDmode || (regno % 2) == 0)
2103 && FP_REGNO_P (last_regno))
2106 if (GET_MODE_CLASS (mode) == MODE_INT)
2108 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2111 if (TARGET_P8_VECTOR && (mode == SImode))
2114 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2118 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
2119 && PAIRED_VECTOR_MODE (mode))
2125 /* The CR register can only hold CC modes. */
2126 if (CR_REGNO_P (regno))
2127 return GET_MODE_CLASS (mode) == MODE_CC;
2129 if (CA_REGNO_P (regno))
2130 return mode == Pmode || mode == SImode;
2132 /* AltiVec only in AldyVec registers. */
2133 if (ALTIVEC_REGNO_P (regno))
2134 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2135 || mode == V1TImode);
2137 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2138 and it must be able to fit within the register set. */
2140 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2143 /* Implement TARGET_HARD_REGNO_NREGS. */
2146 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2148 return rs6000_hard_regno_nregs[mode][regno];
2151 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2154 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2156 return rs6000_hard_regno_mode_ok_p[mode][regno];
2159 /* Implement TARGET_MODES_TIEABLE_P.
2161 PTImode cannot tie with other modes because PTImode is restricted to even
2162 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2165 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2166 128-bit floating point on VSX systems ties with other vectors. */
2169 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2171 if (mode1 == PTImode)
2172 return mode2 == PTImode;
2173 if (mode2 == PTImode)
2176 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2177 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2181 if (SCALAR_FLOAT_MODE_P (mode1))
2182 return SCALAR_FLOAT_MODE_P (mode2);
2183 if (SCALAR_FLOAT_MODE_P (mode2))
2186 if (GET_MODE_CLASS (mode1) == MODE_CC)
2187 return GET_MODE_CLASS (mode2) == MODE_CC;
2188 if (GET_MODE_CLASS (mode2) == MODE_CC)
2191 if (PAIRED_VECTOR_MODE (mode1))
2192 return PAIRED_VECTOR_MODE (mode2);
2193 if (PAIRED_VECTOR_MODE (mode2))
2199 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2202 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2206 && GET_MODE_SIZE (mode) > 4
2207 && INT_REGNO_P (regno))
2211 && FP_REGNO_P (regno)
2212 && GET_MODE_SIZE (mode) > 8
2213 && !FLOAT128_2REG_P (mode))
2219 /* Print interesting facts about registers. */
2221 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2225 for (r = first_regno; r <= last_regno; ++r)
2227 const char *comma = "";
2230 if (first_regno == last_regno)
2231 fprintf (stderr, "%s:\t", reg_name);
2233 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2236 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2237 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2241 fprintf (stderr, ",\n\t");
2246 if (rs6000_hard_regno_nregs[m][r] > 1)
2247 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2248 rs6000_hard_regno_nregs[m][r]);
2250 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2255 if (call_used_regs[r])
2259 fprintf (stderr, ",\n\t");
2264 len += fprintf (stderr, "%s%s", comma, "call-used");
2272 fprintf (stderr, ",\n\t");
2277 len += fprintf (stderr, "%s%s", comma, "fixed");
2283 fprintf (stderr, ",\n\t");
2287 len += fprintf (stderr, "%sreg-class = %s", comma,
2288 reg_class_names[(int)rs6000_regno_regclass[r]]);
2293 fprintf (stderr, ",\n\t");
2297 fprintf (stderr, "%sregno = %d\n", comma, r);
2302 rs6000_debug_vector_unit (enum rs6000_vector v)
2308 case VECTOR_NONE: ret = "none"; break;
2309 case VECTOR_ALTIVEC: ret = "altivec"; break;
2310 case VECTOR_VSX: ret = "vsx"; break;
2311 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2312 case VECTOR_PAIRED: ret = "paired"; break;
2313 case VECTOR_OTHER: ret = "other"; break;
2314 default: ret = "unknown"; break;
2320 /* Inner function printing just the address mask for a particular reload
2322 DEBUG_FUNCTION char *
2323 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2328 if ((mask & RELOAD_REG_VALID) != 0)
2330 else if (keep_spaces)
2333 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2335 else if (keep_spaces)
2338 if ((mask & RELOAD_REG_INDEXED) != 0)
2340 else if (keep_spaces)
2343 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2345 else if ((mask & RELOAD_REG_OFFSET) != 0)
2347 else if (keep_spaces)
2350 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2352 else if (keep_spaces)
2355 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2357 else if (keep_spaces)
2360 if ((mask & RELOAD_REG_AND_M16) != 0)
2362 else if (keep_spaces)
2370 /* Print the address masks in a human readble fashion. */
2372 rs6000_debug_print_mode (ssize_t m)
2378 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2379 for (rc = 0; rc < N_RELOAD_REG; rc++)
2380 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2381 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2383 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2384 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2385 fprintf (stderr, " Reload=%c%c",
2386 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2387 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2389 spaces += sizeof (" Reload=sl") - 1;
2391 if (reg_addr[m].scalar_in_vmx_p)
2393 fprintf (stderr, "%*s Upper=y", spaces, "");
2397 spaces += sizeof (" Upper=y") - 1;
2399 fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2400 || reg_addr[m].fused_toc);
2403 for (rc = 0; rc < N_RELOAD_REG; rc++)
2405 if (rc != RELOAD_REG_ANY)
2407 if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2408 || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2409 || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing
2410 || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
2411 || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2413 fuse_extra_p = true;
2422 fprintf (stderr, "%*s Fuse:", spaces, "");
2425 for (rc = 0; rc < N_RELOAD_REG; rc++)
2427 if (rc != RELOAD_REG_ANY)
2431 if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
2433 else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
2438 if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2440 else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
2445 if (load == '-' && store == '-')
2449 fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
2450 reload_reg_map[rc].name[0], load, store);
2456 if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2458 fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
2462 spaces += sizeof (" P8gpr") - 1;
2464 if (reg_addr[m].fused_toc)
2466 fprintf (stderr, "%*sToc", (spaces + 1), "");
2470 spaces += sizeof (" Toc") - 1;
2473 spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2475 if (rs6000_vector_unit[m] != VECTOR_NONE
2476 || rs6000_vector_mem[m] != VECTOR_NONE)
2478 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2480 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2481 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2484 fputs ("\n", stderr);
2487 #define DEBUG_FMT_ID "%-32s= "
2488 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2489 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2490 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2492 /* Print various interesting information with -mdebug=reg. */
2494 rs6000_debug_reg_global (void)
2496 static const char *const tf[2] = { "false", "true" };
2497 const char *nl = (const char *)0;
2500 char costly_num[20];
2502 char flags_buffer[40];
2503 const char *costly_str;
2504 const char *nop_str;
2505 const char *trace_str;
2506 const char *abi_str;
2507 const char *cmodel_str;
2508 struct cl_target_option cl_opts;
2510 /* Modes we want tieable information on. */
2511 static const machine_mode print_tieable_modes[] = {
2547 /* Virtual regs we are interested in. */
2548 const static struct {
2549 int regno; /* register number. */
2550 const char *name; /* register name. */
2551 } virtual_regs[] = {
2552 { STACK_POINTER_REGNUM, "stack pointer:" },
2553 { TOC_REGNUM, "toc: " },
2554 { STATIC_CHAIN_REGNUM, "static chain: " },
2555 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2556 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2557 { ARG_POINTER_REGNUM, "arg pointer: " },
2558 { FRAME_POINTER_REGNUM, "frame pointer:" },
2559 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2560 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2561 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2562 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2563 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2564 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2565 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2566 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2567 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2570 fputs ("\nHard register information:\n", stderr);
2571 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2572 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2573 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2576 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2577 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2578 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2579 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2580 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2581 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2583 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2584 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2585 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2589 "d reg_class = %s\n"
2590 "f reg_class = %s\n"
2591 "v reg_class = %s\n"
2592 "wa reg_class = %s\n"
2593 "wb reg_class = %s\n"
2594 "wd reg_class = %s\n"
2595 "we reg_class = %s\n"
2596 "wf reg_class = %s\n"
2597 "wg reg_class = %s\n"
2598 "wh reg_class = %s\n"
2599 "wi reg_class = %s\n"
2600 "wj reg_class = %s\n"
2601 "wk reg_class = %s\n"
2602 "wl reg_class = %s\n"
2603 "wm reg_class = %s\n"
2604 "wo reg_class = %s\n"
2605 "wp reg_class = %s\n"
2606 "wq reg_class = %s\n"
2607 "wr reg_class = %s\n"
2608 "ws reg_class = %s\n"
2609 "wt reg_class = %s\n"
2610 "wu reg_class = %s\n"
2611 "wv reg_class = %s\n"
2612 "ww reg_class = %s\n"
2613 "wx reg_class = %s\n"
2614 "wy reg_class = %s\n"
2615 "wz reg_class = %s\n"
2616 "wA reg_class = %s\n"
2617 "wH reg_class = %s\n"
2618 "wI reg_class = %s\n"
2619 "wJ reg_class = %s\n"
2620 "wK reg_class = %s\n"
2622 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2623 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2624 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2625 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2626 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2627 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2628 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2629 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2630 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2631 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2632 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2633 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2634 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2635 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2636 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2637 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2638 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2639 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2640 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2641 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2642 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2643 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2644 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2645 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2646 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2647 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2648 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2649 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2650 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2651 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2652 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2653 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2656 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2657 rs6000_debug_print_mode (m);
2659 fputs ("\n", stderr);
2661 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2663 machine_mode mode1 = print_tieable_modes[m1];
2664 bool first_time = true;
2666 nl = (const char *)0;
2667 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2669 machine_mode mode2 = print_tieable_modes[m2];
2670 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2674 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2679 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2684 fputs ("\n", stderr);
2690 if (rs6000_recip_control)
2692 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2694 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2695 if (rs6000_recip_bits[m])
2698 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2700 (RS6000_RECIP_AUTO_RE_P (m)
2702 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2703 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2705 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2708 fputs ("\n", stderr);
2711 if (rs6000_cpu_index >= 0)
2713 const char *name = processor_target_table[rs6000_cpu_index].name;
2715 = processor_target_table[rs6000_cpu_index].target_enable;
2717 sprintf (flags_buffer, "-mcpu=%s flags", name);
2718 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2721 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2723 if (rs6000_tune_index >= 0)
2725 const char *name = processor_target_table[rs6000_tune_index].name;
2727 = processor_target_table[rs6000_tune_index].target_enable;
2729 sprintf (flags_buffer, "-mtune=%s flags", name);
2730 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2733 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2735 cl_target_option_save (&cl_opts, &global_options);
2736 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2739 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2740 rs6000_isa_flags_explicit);
2742 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2743 rs6000_builtin_mask);
2745 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2747 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2748 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2750 switch (rs6000_sched_costly_dep)
2752 case max_dep_latency:
2753 costly_str = "max_dep_latency";
2757 costly_str = "no_dep_costly";
2760 case all_deps_costly:
2761 costly_str = "all_deps_costly";
2764 case true_store_to_load_dep_costly:
2765 costly_str = "true_store_to_load_dep_costly";
2768 case store_to_load_dep_costly:
2769 costly_str = "store_to_load_dep_costly";
2773 costly_str = costly_num;
2774 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2778 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2780 switch (rs6000_sched_insert_nops)
2782 case sched_finish_regroup_exact:
2783 nop_str = "sched_finish_regroup_exact";
2786 case sched_finish_pad_groups:
2787 nop_str = "sched_finish_pad_groups";
2790 case sched_finish_none:
2791 nop_str = "sched_finish_none";
2796 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2800 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2802 switch (rs6000_sdata)
2809 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2813 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2817 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2822 switch (rs6000_traceback)
2824 case traceback_default: trace_str = "default"; break;
2825 case traceback_none: trace_str = "none"; break;
2826 case traceback_part: trace_str = "part"; break;
2827 case traceback_full: trace_str = "full"; break;
2828 default: trace_str = "unknown"; break;
2831 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2833 switch (rs6000_current_cmodel)
2835 case CMODEL_SMALL: cmodel_str = "small"; break;
2836 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2837 case CMODEL_LARGE: cmodel_str = "large"; break;
2838 default: cmodel_str = "unknown"; break;
2841 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2843 switch (rs6000_current_abi)
2845 case ABI_NONE: abi_str = "none"; break;
2846 case ABI_AIX: abi_str = "aix"; break;
2847 case ABI_ELFv2: abi_str = "ELFv2"; break;
2848 case ABI_V4: abi_str = "V4"; break;
2849 case ABI_DARWIN: abi_str = "darwin"; break;
2850 default: abi_str = "unknown"; break;
2853 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2855 if (rs6000_altivec_abi)
2856 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2858 if (rs6000_darwin64_abi)
2859 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2861 fprintf (stderr, DEBUG_FMT_S, "single_float",
2862 (TARGET_SINGLE_FLOAT ? "true" : "false"));
2864 fprintf (stderr, DEBUG_FMT_S, "double_float",
2865 (TARGET_DOUBLE_FLOAT ? "true" : "false"));
2867 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2868 (TARGET_SOFT_FLOAT ? "true" : "false"));
2870 if (TARGET_LINK_STACK)
2871 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2873 if (TARGET_P8_FUSION)
2877 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
2878 if (TARGET_TOC_FUSION)
2879 strcat (options, ", toc");
2881 if (TARGET_P8_FUSION_SIGN)
2882 strcat (options, ", sign");
2884 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2887 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2888 TARGET_SECURE_PLT ? "secure" : "bss");
2889 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2890 aix_struct_return ? "aix" : "sysv");
2891 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2892 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2893 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2894 tf[!!rs6000_align_branch_targets]);
2895 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2896 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2897 rs6000_long_double_type_size);
2898 if (rs6000_long_double_type_size == 128)
2900 fprintf (stderr, DEBUG_FMT_S, "long double type",
2901 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2902 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2903 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2905 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2906 (int)rs6000_sched_restricted_insns_priority);
2907 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2909 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2910 (int)RS6000_BUILTIN_COUNT);
2912 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2913 (int)TARGET_FLOAT128_ENABLE_TYPE);
2916 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2917 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2919 if (TARGET_DIRECT_MOVE_128)
2920 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2921 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2925 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2926 legitimate address support to figure out the appropriate addressing to
2930 rs6000_setup_reg_addr_masks (void)
2932 ssize_t rc, reg, m, nregs;
2933 addr_mask_type any_addr_mask, addr_mask;
2935 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2937 machine_mode m2 = (machine_mode) m;
2938 bool complex_p = false;
2939 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2942 if (COMPLEX_MODE_P (m2))
2945 m2 = GET_MODE_INNER (m2);
2948 msize = GET_MODE_SIZE (m2);
2950 /* SDmode is special in that we want to access it only via REG+REG
2951 addressing on power7 and above, since we want to use the LFIWZX and
2952 STFIWZX instructions to load it. */
2953 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2956 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2959 reg = reload_reg_map[rc].reg;
2961 /* Can mode values go in the GPR/FPR/Altivec registers? */
2962 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2964 bool small_int_vsx_p = (small_int_p
2965 && (rc == RELOAD_REG_FPR
2966 || rc == RELOAD_REG_VMX));
2968 nregs = rs6000_hard_regno_nregs[m][reg];
2969 addr_mask |= RELOAD_REG_VALID;
2971 /* Indicate if the mode takes more than 1 physical register. If
2972 it takes a single register, indicate it can do REG+REG
2973 addressing. Small integers in VSX registers can only do
2974 REG+REG addressing. */
2975 if (small_int_vsx_p)
2976 addr_mask |= RELOAD_REG_INDEXED;
2977 else if (nregs > 1 || m == BLKmode || complex_p)
2978 addr_mask |= RELOAD_REG_MULTIPLE;
2980 addr_mask |= RELOAD_REG_INDEXED;
2982 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2983 addressing. If we allow scalars into Altivec registers,
2984 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */
2987 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2989 && !VECTOR_MODE_P (m2)
2990 && !FLOAT128_VECTOR_P (m2)
2992 && !small_int_vsx_p)
2994 addr_mask |= RELOAD_REG_PRE_INCDEC;
2996 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2997 we don't allow PRE_MODIFY for some multi-register
3002 addr_mask |= RELOAD_REG_PRE_MODIFY;
3006 if (TARGET_POWERPC64)
3007 addr_mask |= RELOAD_REG_PRE_MODIFY;
3013 addr_mask |= RELOAD_REG_PRE_MODIFY;
3019 /* GPR and FPR registers can do REG+OFFSET addressing, except
3020 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
3021 for 64-bit scalars and 32-bit SFmode to altivec registers. */
3022 if ((addr_mask != 0) && !indexed_only_p
3024 && (rc == RELOAD_REG_GPR
3025 || ((msize == 8 || m2 == SFmode)
3026 && (rc == RELOAD_REG_FPR
3027 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
3028 addr_mask |= RELOAD_REG_OFFSET;
3030 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
3031 instructions are enabled. The offset for 128-bit VSX registers is
3032 only 12-bits. While GPRs can handle the full offset range, VSX
3033 registers can only handle the restricted range. */
3034 else if ((addr_mask != 0) && !indexed_only_p
3035 && msize == 16 && TARGET_P9_VECTOR
3036 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
3037 || (m2 == TImode && TARGET_VSX)))
3039 addr_mask |= RELOAD_REG_OFFSET;
3040 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
3041 addr_mask |= RELOAD_REG_QUAD_OFFSET;
3044 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
3045 addressing on 128-bit types. */
3046 if (rc == RELOAD_REG_VMX && msize == 16
3047 && (addr_mask & RELOAD_REG_VALID) != 0)
3048 addr_mask |= RELOAD_REG_AND_M16;
3050 reg_addr[m].addr_mask[rc] = addr_mask;
3051 any_addr_mask |= addr_mask;
3054 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
3059 /* Initialize the various global tables that are based on register size. */
3061 rs6000_init_hard_regno_mode_ok (bool global_init_p)
3067 /* Precalculate REGNO_REG_CLASS. */
3068 rs6000_regno_regclass[0] = GENERAL_REGS;
3069 for (r = 1; r < 32; ++r)
3070 rs6000_regno_regclass[r] = BASE_REGS;
3072 for (r = 32; r < 64; ++r)
3073 rs6000_regno_regclass[r] = FLOAT_REGS;
3075 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
3076 rs6000_regno_regclass[r] = NO_REGS;
3078 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
3079 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3081 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3082 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3083 rs6000_regno_regclass[r] = CR_REGS;
3085 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3086 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3087 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3088 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3089 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3090 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3091 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3092 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3093 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3094 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3096 /* Precalculate register class to simpler reload register class. We don't
3097 need all of the register classes that are combinations of different
3098 classes, just the simple ones that have constraint letters. */
3099 for (c = 0; c < N_REG_CLASSES; c++)
3100 reg_class_to_reg_type[c] = NO_REG_TYPE;
3102 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3103 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3104 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3105 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3106 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3107 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3108 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3109 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3110 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3111 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3115 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3116 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3120 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3121 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3124 /* Precalculate the valid memory formats as well as the vector information,
3125 this must be set up before the rs6000_hard_regno_nregs_internal calls
3127 gcc_assert ((int)VECTOR_NONE == 0);
3128 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3129 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3131 gcc_assert ((int)CODE_FOR_nothing == 0);
3132 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3134 gcc_assert ((int)NO_REGS == 0);
3135 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3137 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3138 believes it can use native alignment or still uses 128-bit alignment. */
3139 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3150 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3151 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3152 if (TARGET_FLOAT128_TYPE)
3154 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3155 rs6000_vector_align[KFmode] = 128;
3157 if (FLOAT128_IEEE_P (TFmode))
3159 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3160 rs6000_vector_align[TFmode] = 128;
3164 /* V2DF mode, VSX only. */
3167 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3168 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3169 rs6000_vector_align[V2DFmode] = align64;
3172 /* V4SF mode, either VSX or Altivec. */
3175 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3176 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3177 rs6000_vector_align[V4SFmode] = align32;
3179 else if (TARGET_ALTIVEC)
3181 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3182 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3183 rs6000_vector_align[V4SFmode] = align32;
3186 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3190 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3191 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3192 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3193 rs6000_vector_align[V4SImode] = align32;
3194 rs6000_vector_align[V8HImode] = align32;
3195 rs6000_vector_align[V16QImode] = align32;
3199 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3200 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3201 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3205 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3206 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3207 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3211 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3212 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3215 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3216 rs6000_vector_unit[V2DImode]
3217 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3218 rs6000_vector_align[V2DImode] = align64;
3220 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3221 rs6000_vector_unit[V1TImode]
3222 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3223 rs6000_vector_align[V1TImode] = 128;
3226 /* DFmode, see if we want to use the VSX unit. Memory is handled
3227 differently, so don't set rs6000_vector_mem. */
3230 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3231 rs6000_vector_align[DFmode] = 64;
3234 /* SFmode, see if we want to use the VSX unit. */
3235 if (TARGET_P8_VECTOR)
3237 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3238 rs6000_vector_align[SFmode] = 32;
3241 /* Allow TImode in VSX register and set the VSX memory macros. */
3244 rs6000_vector_mem[TImode] = VECTOR_VSX;
3245 rs6000_vector_align[TImode] = align64;
3248 /* TODO add paired floating point vector support. */
3250 /* Register class constraints for the constraints that depend on compile
3251 switches. When the VSX code was added, different constraints were added
3252 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3253 of the VSX registers are used. The register classes for scalar floating
3254 point types is set, based on whether we allow that type into the upper
3255 (Altivec) registers. GCC has register classes to target the Altivec
3256 registers for load/store operations, to select using a VSX memory
3257 operation instead of the traditional floating point operation. The
3260 d - Register class to use with traditional DFmode instructions.
3261 f - Register class to use with traditional SFmode instructions.
3262 v - Altivec register.
3263 wa - Any VSX register.
3264 wc - Reserved to represent individual CR bits (used in LLVM).
3265 wd - Preferred register class for V2DFmode.
3266 wf - Preferred register class for V4SFmode.
3267 wg - Float register for power6x move insns.
3268 wh - FP register for direct move instructions.
3269 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3270 wj - FP or VSX register to hold 64-bit integers for direct moves.
3271 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3272 wl - Float register if we can do 32-bit signed int loads.
3273 wm - VSX register for ISA 2.07 direct move operations.
3274 wn - always NO_REGS.
3275 wr - GPR if 64-bit mode is permitted.
3276 ws - Register class to do ISA 2.06 DF operations.
3277 wt - VSX register for TImode in VSX registers.
3278 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3279 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3280 ww - Register class to do SF conversions in with VSX operations.
3281 wx - Float register if we can do 32-bit int stores.
3282 wy - Register class to do ISA 2.07 SF operations.
3283 wz - Float register if we can do 32-bit unsigned int loads.
3284 wH - Altivec register if SImode is allowed in VSX registers.
3285 wI - VSX register if SImode is allowed in VSX registers.
3286 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3287 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3289 if (TARGET_HARD_FLOAT)
3290 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3292 if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
3293 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3297 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3298 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3299 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3300 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3301 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3302 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3303 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3306 /* Add conditional constraints based on various options, to allow us to
3307 collapse multiple insn patterns. */
3309 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3311 if (TARGET_MFPGPR) /* DFmode */
3312 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3315 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3317 if (TARGET_DIRECT_MOVE)
3319 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3320 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3321 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3322 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3323 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3324 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3327 if (TARGET_POWERPC64)
3329 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3330 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3333 if (TARGET_P8_VECTOR) /* SFmode */
3335 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3336 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3337 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3339 else if (TARGET_VSX)
3340 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3343 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3346 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3348 if (TARGET_FLOAT128_TYPE)
3350 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3351 if (FLOAT128_IEEE_P (TFmode))
3352 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3355 if (TARGET_P9_VECTOR)
3357 /* Support for new D-form instructions. */
3358 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3360 /* Support for ISA 3.0 (power9) vectors. */
3361 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3364 /* Support for new direct moves (ISA 3.0 + 64bit). */
3365 if (TARGET_DIRECT_MOVE_128)
3366 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3368 /* Support small integers in VSX registers. */
3369 if (TARGET_P8_VECTOR)
3371 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3372 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3373 if (TARGET_P9_VECTOR)
3375 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3376 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3380 /* Set up the reload helper and direct move functions. */
3381 if (TARGET_VSX || TARGET_ALTIVEC)
3385 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3386 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3387 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3388 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3389 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3390 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3391 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3392 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3393 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3394 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3395 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3396 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3397 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3398 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3399 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3400 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3401 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3402 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3403 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3404 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3406 if (FLOAT128_VECTOR_P (KFmode))
3408 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3409 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3412 if (FLOAT128_VECTOR_P (TFmode))
3414 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3415 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3418 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3420 if (TARGET_NO_SDMODE_STACK)
3422 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3423 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3428 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3429 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3432 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3434 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3435 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3436 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3437 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3438 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3439 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3440 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3441 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3442 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3444 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3445 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3446 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3447 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3448 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3449 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3450 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3451 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3452 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3454 if (FLOAT128_VECTOR_P (KFmode))
3456 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3457 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3460 if (FLOAT128_VECTOR_P (TFmode))
3462 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3463 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3469 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3470 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3471 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3472 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3473 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3474 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3475 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3476 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3477 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3478 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3479 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3480 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3481 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3482 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3483 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3484 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3485 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3486 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3487 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3488 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3490 if (FLOAT128_VECTOR_P (KFmode))
3492 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3493 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3496 if (FLOAT128_IEEE_P (TFmode))
3498 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3499 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3502 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3504 if (TARGET_NO_SDMODE_STACK)
3506 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3507 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3512 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3513 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3516 if (TARGET_DIRECT_MOVE)
3518 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3519 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3520 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3524 reg_addr[DFmode].scalar_in_vmx_p = true;
3525 reg_addr[DImode].scalar_in_vmx_p = true;
3527 if (TARGET_P8_VECTOR)
3529 reg_addr[SFmode].scalar_in_vmx_p = true;
3530 reg_addr[SImode].scalar_in_vmx_p = true;
3532 if (TARGET_P9_VECTOR)
3534 reg_addr[HImode].scalar_in_vmx_p = true;
3535 reg_addr[QImode].scalar_in_vmx_p = true;
3540 /* Setup the fusion operations. */
3541 if (TARGET_P8_FUSION)
3543 reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
3544 reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
3545 reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
3547 reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
3550 if (TARGET_P9_FUSION)
3553 enum machine_mode mode; /* mode of the fused type. */
3554 enum machine_mode pmode; /* pointer mode. */
3555 enum rs6000_reload_reg_type rtype; /* register type. */
3556 enum insn_code load; /* load insn. */
3557 enum insn_code store; /* store insn. */
3560 static const struct fuse_insns addis_insns[] = {
3561 { E_SFmode, E_DImode, RELOAD_REG_FPR,
3562 CODE_FOR_fusion_vsx_di_sf_load,
3563 CODE_FOR_fusion_vsx_di_sf_store },
3565 { E_SFmode, E_SImode, RELOAD_REG_FPR,
3566 CODE_FOR_fusion_vsx_si_sf_load,
3567 CODE_FOR_fusion_vsx_si_sf_store },
3569 { E_DFmode, E_DImode, RELOAD_REG_FPR,
3570 CODE_FOR_fusion_vsx_di_df_load,
3571 CODE_FOR_fusion_vsx_di_df_store },
3573 { E_DFmode, E_SImode, RELOAD_REG_FPR,
3574 CODE_FOR_fusion_vsx_si_df_load,
3575 CODE_FOR_fusion_vsx_si_df_store },
3577 { E_DImode, E_DImode, RELOAD_REG_FPR,
3578 CODE_FOR_fusion_vsx_di_di_load,
3579 CODE_FOR_fusion_vsx_di_di_store },
3581 { E_DImode, E_SImode, RELOAD_REG_FPR,
3582 CODE_FOR_fusion_vsx_si_di_load,
3583 CODE_FOR_fusion_vsx_si_di_store },
3585 { E_QImode, E_DImode, RELOAD_REG_GPR,
3586 CODE_FOR_fusion_gpr_di_qi_load,
3587 CODE_FOR_fusion_gpr_di_qi_store },
3589 { E_QImode, E_SImode, RELOAD_REG_GPR,
3590 CODE_FOR_fusion_gpr_si_qi_load,
3591 CODE_FOR_fusion_gpr_si_qi_store },
3593 { E_HImode, E_DImode, RELOAD_REG_GPR,
3594 CODE_FOR_fusion_gpr_di_hi_load,
3595 CODE_FOR_fusion_gpr_di_hi_store },
3597 { E_HImode, E_SImode, RELOAD_REG_GPR,
3598 CODE_FOR_fusion_gpr_si_hi_load,
3599 CODE_FOR_fusion_gpr_si_hi_store },
3601 { E_SImode, E_DImode, RELOAD_REG_GPR,
3602 CODE_FOR_fusion_gpr_di_si_load,
3603 CODE_FOR_fusion_gpr_di_si_store },
3605 { E_SImode, E_SImode, RELOAD_REG_GPR,
3606 CODE_FOR_fusion_gpr_si_si_load,
3607 CODE_FOR_fusion_gpr_si_si_store },
3609 { E_SFmode, E_DImode, RELOAD_REG_GPR,
3610 CODE_FOR_fusion_gpr_di_sf_load,
3611 CODE_FOR_fusion_gpr_di_sf_store },
3613 { E_SFmode, E_SImode, RELOAD_REG_GPR,
3614 CODE_FOR_fusion_gpr_si_sf_load,
3615 CODE_FOR_fusion_gpr_si_sf_store },
3617 { E_DImode, E_DImode, RELOAD_REG_GPR,
3618 CODE_FOR_fusion_gpr_di_di_load,
3619 CODE_FOR_fusion_gpr_di_di_store },
3621 { E_DFmode, E_DImode, RELOAD_REG_GPR,
3622 CODE_FOR_fusion_gpr_di_df_load,
3623 CODE_FOR_fusion_gpr_di_df_store },
3626 machine_mode cur_pmode = Pmode;
3629 for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
3631 machine_mode xmode = addis_insns[i].mode;
3632 enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
3634 if (addis_insns[i].pmode != cur_pmode)
3637 if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
3640 reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
3641 reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
3643 if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
3645 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
3646 = addis_insns[i].load;
3647 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
3648 = addis_insns[i].store;
3653 /* Note which types we support fusing TOC setup plus memory insn. We only do
3654 fused TOCs for medium/large code models. */
3655 if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
3656 && (TARGET_CMODEL != CMODEL_SMALL))
3658 reg_addr[QImode].fused_toc = true;
3659 reg_addr[HImode].fused_toc = true;
3660 reg_addr[SImode].fused_toc = true;
3661 reg_addr[DImode].fused_toc = true;
3662 if (TARGET_HARD_FLOAT)
3664 if (TARGET_SINGLE_FLOAT)
3665 reg_addr[SFmode].fused_toc = true;
3666 if (TARGET_DOUBLE_FLOAT)
3667 reg_addr[DFmode].fused_toc = true;
3671 /* Precalculate HARD_REGNO_NREGS. */
3672 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3673 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3674 rs6000_hard_regno_nregs[m][r]
3675 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3677 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3678 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3679 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3680 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3681 rs6000_hard_regno_mode_ok_p[m][r] = true;
3683 /* Precalculate CLASS_MAX_NREGS sizes. */
3684 for (c = 0; c < LIM_REG_CLASSES; ++c)
3688 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3689 reg_size = UNITS_PER_VSX_WORD;
3691 else if (c == ALTIVEC_REGS)
3692 reg_size = UNITS_PER_ALTIVEC_WORD;
3694 else if (c == FLOAT_REGS)
3695 reg_size = UNITS_PER_FP_WORD;
3698 reg_size = UNITS_PER_WORD;
3700 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3702 machine_mode m2 = (machine_mode)m;
3703 int reg_size2 = reg_size;
3705 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3707 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3708 reg_size2 = UNITS_PER_FP_WORD;
3710 rs6000_class_max_nregs[m][c]
3711 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3715 /* Calculate which modes to automatically generate code to use a the
3716 reciprocal divide and square root instructions. In the future, possibly
3717 automatically generate the instructions even if the user did not specify
3718 -mrecip. The older machines double precision reciprocal sqrt estimate is
3719 not accurate enough. */
3720 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3722 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3724 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3725 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3726 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3727 if (VECTOR_UNIT_VSX_P (V2DFmode))
3728 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3730 if (TARGET_FRSQRTES)
3731 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3733 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3734 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3735 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3736 if (VECTOR_UNIT_VSX_P (V2DFmode))
3737 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3739 if (rs6000_recip_control)
3741 if (!flag_finite_math_only)
3742 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3744 if (flag_trapping_math)
3745 warning (0, "%qs requires %qs or %qs", "-mrecip",
3746 "-fno-trapping-math", "-ffast-math");
3747 if (!flag_reciprocal_math)
3748 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3750 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3752 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3753 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3754 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3756 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3757 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3758 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3760 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3761 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3762 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3764 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3765 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3766 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3768 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3769 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3770 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3772 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3773 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3774 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3776 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3777 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3778 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3780 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3781 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3782 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3786 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3787 legitimate address support to figure out the appropriate addressing to
3789 rs6000_setup_reg_addr_masks ();
3791 if (global_init_p || TARGET_DEBUG_TARGET)
3793 if (TARGET_DEBUG_REG)
3794 rs6000_debug_reg_global ();
3796 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3798 "SImode variable mult cost = %d\n"
3799 "SImode constant mult cost = %d\n"
3800 "SImode short constant mult cost = %d\n"
3801 "DImode multipliciation cost = %d\n"
3802 "SImode division cost = %d\n"
3803 "DImode division cost = %d\n"
3804 "Simple fp operation cost = %d\n"
3805 "DFmode multiplication cost = %d\n"
3806 "SFmode division cost = %d\n"
3807 "DFmode division cost = %d\n"
3808 "cache line size = %d\n"
3809 "l1 cache size = %d\n"
3810 "l2 cache size = %d\n"
3811 "simultaneous prefetches = %d\n"
3814 rs6000_cost->mulsi_const,
3815 rs6000_cost->mulsi_const9,
3823 rs6000_cost->cache_line_size,
3824 rs6000_cost->l1_cache_size,
3825 rs6000_cost->l2_cache_size,
3826 rs6000_cost->simultaneous_prefetches);
3831 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3834 darwin_rs6000_override_options (void)
3836 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3838 rs6000_altivec_abi = 1;
3839 TARGET_ALTIVEC_VRSAVE = 1;
3840 rs6000_current_abi = ABI_DARWIN;
3842 if (DEFAULT_ABI == ABI_DARWIN
3844 darwin_one_byte_bool = 1;
3846 if (TARGET_64BIT && ! TARGET_POWERPC64)
3848 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3849 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3853 rs6000_default_long_calls = 1;
3854 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3857 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3859 if (!flag_mkernel && !flag_apple_kext
3861 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3862 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3864 /* Unless the user (not the configurer) has explicitly overridden
3865 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3866 G4 unless targeting the kernel. */
3869 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3870 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3871 && ! global_options_set.x_rs6000_cpu_index)
3873 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3878 /* If not otherwise specified by a target, make 'long double' equivalent to
3881 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3882 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3885 /* Return the builtin mask of the various options used that could affect which
3886 builtins were used. In the past we used target_flags, but we've run out of
3887 bits, and some options like PAIRED are no longer in target_flags. */
3890 rs6000_builtin_mask_calculate (void)
3892 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3893 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3894 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3895 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
3896 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3897 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3898 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3899 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3900 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3901 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3902 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3903 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3904 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3905 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3906 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3907 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3908 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3909 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3910 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3911 | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)
3912 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3913 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3916 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3917 to clobber the XER[CA] bit because clobbering that bit without telling
3918 the compiler worked just fine with versions of GCC before GCC 5, and
3919 breaking a lot of older code in ways that are hard to track down is
3920 not such a great idea. */
3923 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3924 vec<const char *> &/*constraints*/,
3925 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3927 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3928 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3932 /* Override command line options.
3934 Combine build-specific configuration information with options
3935 specified on the command line to set various state variables which
3936 influence code generation, optimization, and expansion of built-in
3937 functions. Assure that command-line configuration preferences are
3938 compatible with each other and with the build configuration; issue
3939 warnings while adjusting configuration or error messages while
3940 rejecting configuration.
3942 Upon entry to this function:
3944 This function is called once at the beginning of
3945 compilation, and then again at the start and end of compiling
3946 each section of code that has a different configuration, as
3947 indicated, for example, by adding the
3949 __attribute__((__target__("cpu=power9")))
3951 qualifier to a function definition or, for example, by bracketing
3954 #pragma GCC target("altivec")
3958 #pragma GCC reset_options
3960 directives. Parameter global_init_p is true for the initial
3961 invocation, which initializes global variables, and false for all
3962 subsequent invocations.
3965 Various global state information is assumed to be valid. This
3966 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3967 default CPU specified at build configure time, TARGET_DEFAULT,
3968 representing the default set of option flags for the default
3969 target, and global_options_set.x_rs6000_isa_flags, representing
3970 which options were requested on the command line.
3972 Upon return from this function:
3974 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3975 was set by name on the command line. Additionally, if certain
3976 attributes are automatically enabled or disabled by this function
3977 in order to assure compatibility between options and
3978 configuration, the flags associated with those attributes are
3979 also set. By setting these "explicit bits", we avoid the risk
3980 that other code might accidentally overwrite these particular
3981 attributes with "default values".
3983 The various bits of rs6000_isa_flags are set to indicate the
3984 target options that have been selected for the most current
3985 compilation efforts. This has the effect of also turning on the
3986 associated TARGET_XXX values since these are macros which are
3987 generally defined to test the corresponding bit of the
3988 rs6000_isa_flags variable.
3990 The variable rs6000_builtin_mask is set to represent the target
3991 options for the most current compilation efforts, consistent with
3992 the current contents of rs6000_isa_flags. This variable controls
3993 expansion of built-in functions.
3995 Various other global variables and fields of global structures
3996 (over 50 in all) are initialized to reflect the desired options
3997 for the most current compilation efforts. */
4000 rs6000_option_override_internal (bool global_init_p)
4004 HOST_WIDE_INT set_masks;
4005 HOST_WIDE_INT ignore_masks;
4008 struct cl_target_option *main_target_opt
4009 = ((global_init_p || target_option_default_node == NULL)
4010 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
4012 /* Print defaults. */
4013 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
4014 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
4016 /* Remember the explicit arguments. */
4018 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
4020 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
4021 library functions, so warn about it. The flag may be useful for
4022 performance studies from time to time though, so don't disable it
4024 if (global_options_set.x_rs6000_alignment_flags
4025 && rs6000_alignment_flags == MASK_ALIGN_POWER
4026 && DEFAULT_ABI == ABI_DARWIN
4028 warning (0, "%qs is not supported for 64-bit Darwin;"
4029 " it is incompatible with the installed C and C++ libraries",
4032 /* Numerous experiment shows that IRA based loop pressure
4033 calculation works better for RTL loop invariant motion on targets
4034 with enough (>= 32) registers. It is an expensive optimization.
4035 So it is on only for peak performance. */
4036 if (optimize >= 3 && global_init_p
4037 && !global_options_set.x_flag_ira_loop_pressure)
4038 flag_ira_loop_pressure = 1;
4040 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
4041 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
4042 options were already specified. */
4043 if (flag_sanitize & SANITIZE_USER_ADDRESS
4044 && !global_options_set.x_flag_asynchronous_unwind_tables)
4045 flag_asynchronous_unwind_tables = 1;
4047 /* Set the pointer size. */
4050 rs6000_pmode = DImode;
4051 rs6000_pointer_size = 64;
4055 rs6000_pmode = SImode;
4056 rs6000_pointer_size = 32;
4059 /* Some OSs don't support saving the high part of 64-bit registers on context
4060 switch. Other OSs don't support saving Altivec registers. On those OSs,
4061 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
4062 if the user wants either, the user must explicitly specify them and we
4063 won't interfere with the user's specification. */
4065 set_masks = POWERPC_MASKS;
4066 #ifdef OS_MISSING_POWERPC64
4067 if (OS_MISSING_POWERPC64)
4068 set_masks &= ~OPTION_MASK_POWERPC64;
4070 #ifdef OS_MISSING_ALTIVEC
4071 if (OS_MISSING_ALTIVEC)
4072 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
4073 | OTHER_VSX_VECTOR_MASKS);
4076 /* Don't override by the processor default if given explicitly. */
4077 set_masks &= ~rs6000_isa_flags_explicit;
4079 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
4080 the cpu in a target attribute or pragma, but did not specify a tuning
4081 option, use the cpu for the tuning option rather than the option specified
4082 with -mtune on the command line. Process a '--with-cpu' configuration
4083 request as an implicit --cpu. */
4084 if (rs6000_cpu_index >= 0)
4085 cpu_index = rs6000_cpu_index;
4086 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
4087 cpu_index = main_target_opt->x_rs6000_cpu_index;
4088 else if (OPTION_TARGET_CPU_DEFAULT)
4089 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
4093 const char *unavailable_cpu = NULL;
4094 switch (processor_target_table[cpu_index].processor)
4096 #ifndef HAVE_AS_POWER9
4097 case PROCESSOR_POWER9:
4098 unavailable_cpu = "power9";
4101 #ifndef HAVE_AS_POWER8
4102 case PROCESSOR_POWER8:
4103 unavailable_cpu = "power8";
4106 #ifndef HAVE_AS_POPCNTD
4107 case PROCESSOR_POWER7:
4108 unavailable_cpu = "power7";
4112 case PROCESSOR_POWER6:
4113 unavailable_cpu = "power6";
4116 #ifndef HAVE_AS_POPCNTB
4117 case PROCESSOR_POWER5:
4118 unavailable_cpu = "power5";
4124 if (unavailable_cpu)
4127 warning (0, "will not generate %qs instructions because "
4128 "assembler lacks %qs support", unavailable_cpu,
4133 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4134 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4135 with those from the cpu, except for options that were explicitly set. If
4136 we don't have a cpu, do not override the target bits set in
4140 rs6000_cpu_index = cpu_index;
4141 rs6000_isa_flags &= ~set_masks;
4142 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
4147 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4148 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4149 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4150 to using rs6000_isa_flags, we need to do the initialization here.
4152 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4153 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4154 HOST_WIDE_INT flags;
4156 flags = TARGET_DEFAULT;
4159 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4160 const char *default_cpu = (!TARGET_POWERPC64
4165 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
4166 flags = processor_target_table[default_cpu_index].target_enable;
4168 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
4171 if (rs6000_tune_index >= 0)
4172 tune_index = rs6000_tune_index;
4173 else if (cpu_index >= 0)
4174 rs6000_tune_index = tune_index = cpu_index;
4178 enum processor_type tune_proc
4179 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
4182 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
4183 if (processor_target_table[i].processor == tune_proc)
4191 rs6000_cpu = processor_target_table[cpu_index].processor;
4193 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
4195 gcc_assert (tune_index >= 0);
4196 rs6000_tune = processor_target_table[tune_index].processor;
4198 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
4199 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
4200 || rs6000_cpu == PROCESSOR_PPCE5500)
4203 error ("AltiVec not supported in this target");
4206 /* If we are optimizing big endian systems for space, use the load/store
4207 multiple and string instructions. */
4208 if (BYTES_BIG_ENDIAN && optimize_size)
4209 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
4210 | OPTION_MASK_STRING);
4212 /* Don't allow -mmultiple or -mstring on little endian systems
4213 unless the cpu is a 750, because the hardware doesn't support the
4214 instructions used in little endian mode, and causes an alignment
4215 trap. The 750 does not cause an alignment trap (except when the
4216 target is unaligned). */
4218 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
4220 if (TARGET_MULTIPLE)
4222 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
4223 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
4224 warning (0, "%qs is not supported on little endian systems",
4230 rs6000_isa_flags &= ~OPTION_MASK_STRING;
4231 if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
4232 warning (0, "%qs is not supported on little endian systems",
4237 /* If little-endian, default to -mstrict-align on older processors.
4238 Testing for htm matches power8 and later. */
4239 if (!BYTES_BIG_ENDIAN
4240 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
4241 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
4243 /* -maltivec={le,be} implies -maltivec. */
4244 if (rs6000_altivec_element_order != 0)
4245 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
4247 /* Disallow -maltivec=le in big endian mode for now. This is not
4248 known to be useful for anyone. */
4249 if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
4251 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
4252 rs6000_altivec_element_order = 0;
4255 if (!rs6000_fold_gimple)
4257 "gimple folding of rs6000 builtins has been disabled.\n");
4259 /* Add some warnings for VSX. */
4262 const char *msg = NULL;
4263 if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
4265 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4266 msg = N_("-mvsx requires hardware floating point");
4269 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4270 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4273 else if (TARGET_PAIRED_FLOAT)
4274 msg = N_("-mvsx and -mpaired are incompatible");
4275 else if (TARGET_AVOID_XFORM > 0)
4276 msg = N_("-mvsx needs indexed addressing");
4277 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
4278 & OPTION_MASK_ALTIVEC))
4280 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4281 msg = N_("-mvsx and -mno-altivec are incompatible");
4283 msg = N_("-mno-altivec disables vsx");
4289 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4290 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4294 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4295 the -mcpu setting to enable options that conflict. */
4296 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4297 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4298 | OPTION_MASK_ALTIVEC
4299 | OPTION_MASK_VSX)) != 0)
4300 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4301 | OPTION_MASK_DIRECT_MOVE)
4302 & ~rs6000_isa_flags_explicit);
4304 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4305 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4307 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4308 off all of the options that depend on those flags. */
4309 ignore_masks = rs6000_disable_incompatible_switches ();
4311 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4312 unless the user explicitly used the -mno-<option> to disable the code. */
4313 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4314 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4315 else if (TARGET_P9_MINMAX)
4319 if (cpu_index == PROCESSOR_POWER9)
4321 /* legacy behavior: allow -mcpu=power9 with certain
4322 capabilities explicitly disabled. */
4323 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4326 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4327 "for <xxx> less than power9", "-mcpu");
4329 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4330 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4331 & rs6000_isa_flags_explicit))
4332 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4333 were explicitly cleared. */
4334 error ("%qs incompatible with explicitly disabled options",
4337 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4339 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4340 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4341 else if (TARGET_VSX)
4342 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4343 else if (TARGET_POPCNTD)
4344 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4345 else if (TARGET_DFP)
4346 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4347 else if (TARGET_CMPB)
4348 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4349 else if (TARGET_FPRND)
4350 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4351 else if (TARGET_POPCNTB)
4352 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4353 else if (TARGET_ALTIVEC)
4354 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4356 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4358 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4359 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4360 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4363 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4365 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4366 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4367 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4370 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4372 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4373 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4374 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4377 if (TARGET_P8_VECTOR && !TARGET_VSX)
4379 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4380 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4381 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4382 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4384 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4385 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4386 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4390 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4392 rs6000_isa_flags |= OPTION_MASK_VSX;
4393 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4397 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4399 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4400 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4401 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4404 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4405 silently turn off quad memory mode. */
4406 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4408 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4409 warning (0, N_("-mquad-memory requires 64-bit mode"));
4411 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4412 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4414 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4415 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4418 /* Non-atomic quad memory load/store are disabled for little endian, since
4419 the words are reversed, but atomic operations can still be done by
4420 swapping the words. */
4421 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4423 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4424 warning (0, N_("-mquad-memory is not available in little endian "
4427 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4430 /* Assume if the user asked for normal quad memory instructions, they want
4431 the atomic versions as well, unless they explicity told us not to use quad
4432 word atomic instructions. */
4433 if (TARGET_QUAD_MEMORY
4434 && !TARGET_QUAD_MEMORY_ATOMIC
4435 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4436 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4438 /* If we can shrink-wrap the TOC register save separately, then use
4439 -msave-toc-indirect unless explicitly disabled. */
4440 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4441 && flag_shrink_wrap_separate
4442 && optimize_function_for_speed_p (cfun))
4443 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4445 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4446 generating power8 instructions. */
4447 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4448 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4449 & OPTION_MASK_P8_FUSION);
4451 /* Setting additional fusion flags turns on base fusion. */
4452 if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
4454 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4456 if (TARGET_P8_FUSION_SIGN)
4457 error ("%qs requires %qs", "-mpower8-fusion-sign",
4460 if (TARGET_TOC_FUSION)
4461 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4463 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4466 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4469 /* Power9 fusion is a superset over power8 fusion. */
4470 if (TARGET_P9_FUSION && !TARGET_P8_FUSION)
4472 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4474 /* We prefer to not mention undocumented options in
4475 error messages. However, if users have managed to select
4476 power9-fusion without selecting power8-fusion, they
4477 already know about undocumented flags. */
4478 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4479 rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
4482 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4485 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4486 generating power9 instructions. */
4487 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_FUSION))
4488 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4489 & OPTION_MASK_P9_FUSION);
4491 /* Power8 does not fuse sign extended loads with the addis. If we are
4492 optimizing at high levels for speed, convert a sign extended load into a
4493 zero extending load, and an explicit sign extension. */
4494 if (TARGET_P8_FUSION
4495 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4496 && optimize_function_for_speed_p (cfun)
4498 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4500 /* TOC fusion requires 64-bit and medium/large code model. */
4501 if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
4503 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4504 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4505 warning (0, N_("-mtoc-fusion requires 64-bit"));
4508 if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
4510 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4511 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4512 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4515 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4517 if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
4518 && (TARGET_CMODEL != CMODEL_SMALL)
4519 && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
4520 rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
4522 /* ISA 3.0 vector instructions include ISA 2.07. */
4523 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4525 /* We prefer to not mention undocumented options in
4526 error messages. However, if users have managed to select
4527 power9-vector without selecting power8-vector, they
4528 already know about undocumented flags. */
4529 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4530 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4531 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4532 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4534 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4535 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4536 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4540 /* OPTION_MASK_P9_VECTOR is explicit and
4541 OPTION_MASK_P8_VECTOR is not explicit. */
4542 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4543 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4547 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4548 support. If we only have ISA 2.06 support, and the user did not specify
4549 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4550 but we don't enable the full vectorization support */
4551 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4552 TARGET_ALLOW_MOVMISALIGN = 1;
4554 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4556 if (TARGET_ALLOW_MOVMISALIGN > 0
4557 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4558 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4560 TARGET_ALLOW_MOVMISALIGN = 0;
4563 /* Determine when unaligned vector accesses are permitted, and when
4564 they are preferred over masked Altivec loads. Note that if
4565 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4566 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4568 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4572 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4573 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4575 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4578 else if (!TARGET_ALLOW_MOVMISALIGN)
4580 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4581 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4582 "-mallow-movmisalign");
4584 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4588 /* Set long double size before the IEEE 128-bit tests. */
4589 if (!global_options_set.x_rs6000_long_double_type_size)
4591 if (main_target_opt != NULL
4592 && (main_target_opt->x_rs6000_long_double_type_size
4593 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
4594 error ("target attribute or pragma changes long double size");
4596 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
4599 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4600 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4601 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4602 those systems will not pick up this default. Warn if the user changes the
4603 default unless -Wno-psabi. */
4604 if (!global_options_set.x_rs6000_ieeequad)
4605 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4607 else if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4609 static bool warned_change_long_double;
4610 if (!warned_change_long_double)
4612 warned_change_long_double = true;
4613 if (TARGET_IEEEQUAD)
4614 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4616 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4620 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4621 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4622 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4623 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4624 the keyword as well as the type. */
4625 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4627 /* IEEE 128-bit floating point requires VSX support. */
4628 if (TARGET_FLOAT128_KEYWORD)
4632 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4633 error ("%qs requires VSX support", "-mfloat128");
4635 TARGET_FLOAT128_TYPE = 0;
4636 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4637 | OPTION_MASK_FLOAT128_HW);
4639 else if (!TARGET_FLOAT128_TYPE)
4641 TARGET_FLOAT128_TYPE = 1;
4642 warning (0, "The -mfloat128 option may not be fully supported");
4646 /* Enable the __float128 keyword under Linux by default. */
4647 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4648 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4649 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4651 /* If we have are supporting the float128 type and full ISA 3.0 support,
4652 enable -mfloat128-hardware by default. However, don't enable the
4653 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4654 because sometimes the compiler wants to put things in an integer
4655 container, and if we don't have __int128 support, it is impossible. */
4656 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4657 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4658 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4659 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4661 if (TARGET_FLOAT128_HW
4662 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4664 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4665 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4667 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4670 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4672 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4673 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4675 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4678 /* Print the options after updating the defaults. */
4679 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4680 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4682 /* E500mc does "better" if we inline more aggressively. Respect the
4683 user's opinion, though. */
4684 if (rs6000_block_move_inline_limit == 0
4685 && (rs6000_tune == PROCESSOR_PPCE500MC
4686 || rs6000_tune == PROCESSOR_PPCE500MC64
4687 || rs6000_tune == PROCESSOR_PPCE5500
4688 || rs6000_tune == PROCESSOR_PPCE6500))
4689 rs6000_block_move_inline_limit = 128;
4691 /* store_one_arg depends on expand_block_move to handle at least the
4692 size of reg_parm_stack_space. */
4693 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4694 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4698 /* If the appropriate debug option is enabled, replace the target hooks
4699 with debug versions that call the real version and then prints
4700 debugging information. */
4701 if (TARGET_DEBUG_COST)
4703 targetm.rtx_costs = rs6000_debug_rtx_costs;
4704 targetm.address_cost = rs6000_debug_address_cost;
4705 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4708 if (TARGET_DEBUG_ADDR)
4710 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4711 targetm.legitimize_address = rs6000_debug_legitimize_address;
4712 rs6000_secondary_reload_class_ptr
4713 = rs6000_debug_secondary_reload_class;
4714 targetm.secondary_memory_needed
4715 = rs6000_debug_secondary_memory_needed;
4716 targetm.can_change_mode_class
4717 = rs6000_debug_can_change_mode_class;
4718 rs6000_preferred_reload_class_ptr
4719 = rs6000_debug_preferred_reload_class;
4720 rs6000_legitimize_reload_address_ptr
4721 = rs6000_debug_legitimize_reload_address;
4722 rs6000_mode_dependent_address_ptr
4723 = rs6000_debug_mode_dependent_address;
4726 if (rs6000_veclibabi_name)
4728 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4729 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4732 error ("unknown vectorization library ABI type (%qs) for "
4733 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4739 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4740 target attribute or pragma which automatically enables both options,
4741 unless the altivec ABI was set. This is set by default for 64-bit, but
4743 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4745 TARGET_FLOAT128_TYPE = 0;
4746 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4747 | OPTION_MASK_FLOAT128_KEYWORD)
4748 & ~rs6000_isa_flags_explicit);
4751 /* Enable Altivec ABI for AIX -maltivec. */
4752 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4754 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4755 error ("target attribute or pragma changes AltiVec ABI");
4757 rs6000_altivec_abi = 1;
4760 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4761 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4762 be explicitly overridden in either case. */
4765 if (!global_options_set.x_rs6000_altivec_abi
4766 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4768 if (main_target_opt != NULL &&
4769 !main_target_opt->x_rs6000_altivec_abi)
4770 error ("target attribute or pragma changes AltiVec ABI");
4772 rs6000_altivec_abi = 1;
4776 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4777 So far, the only darwin64 targets are also MACH-O. */
4779 && DEFAULT_ABI == ABI_DARWIN
4782 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4783 error ("target attribute or pragma changes darwin64 ABI");
4786 rs6000_darwin64_abi = 1;
4787 /* Default to natural alignment, for better performance. */
4788 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4792 /* Place FP constants in the constant pool instead of TOC
4793 if section anchors enabled. */
4794 if (flag_section_anchors
4795 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4796 TARGET_NO_FP_IN_TOC = 1;
4798 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4799 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4801 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4802 SUBTARGET_OVERRIDE_OPTIONS;
4804 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4805 SUBSUBTARGET_OVERRIDE_OPTIONS;
4807 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4808 SUB3TARGET_OVERRIDE_OPTIONS;
4811 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4812 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4814 /* For the E500 family of cores, reset the single/double FP flags to let us
4815 check that they remain constant across attributes or pragmas. Also,
4816 clear a possible request for string instructions, not supported and which
4817 we might have silently queried above for -Os. */
4821 case PROCESSOR_PPC8540:
4822 case PROCESSOR_PPC8548:
4823 case PROCESSOR_PPCE500MC:
4824 case PROCESSOR_PPCE500MC64:
4825 case PROCESSOR_PPCE5500:
4826 case PROCESSOR_PPCE6500:
4827 rs6000_single_float = 0;
4828 rs6000_double_float = 0;
4829 rs6000_isa_flags &= ~OPTION_MASK_STRING;
4836 if (main_target_opt)
4838 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
4839 error ("target attribute or pragma changes single precision floating "
4841 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
4842 error ("target attribute or pragma changes double precision floating "
4846 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4847 && rs6000_tune != PROCESSOR_POWER5
4848 && rs6000_tune != PROCESSOR_POWER6
4849 && rs6000_tune != PROCESSOR_POWER7
4850 && rs6000_tune != PROCESSOR_POWER8
4851 && rs6000_tune != PROCESSOR_POWER9
4852 && rs6000_tune != PROCESSOR_PPCA2
4853 && rs6000_tune != PROCESSOR_CELL
4854 && rs6000_tune != PROCESSOR_PPC476);
4855 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4856 || rs6000_tune == PROCESSOR_POWER5
4857 || rs6000_tune == PROCESSOR_POWER7
4858 || rs6000_tune == PROCESSOR_POWER8);
4859 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4860 || rs6000_tune == PROCESSOR_POWER5
4861 || rs6000_tune == PROCESSOR_POWER6
4862 || rs6000_tune == PROCESSOR_POWER7
4863 || rs6000_tune == PROCESSOR_POWER8
4864 || rs6000_tune == PROCESSOR_POWER9
4865 || rs6000_tune == PROCESSOR_PPCE500MC
4866 || rs6000_tune == PROCESSOR_PPCE500MC64
4867 || rs6000_tune == PROCESSOR_PPCE5500
4868 || rs6000_tune == PROCESSOR_PPCE6500);
4870 /* Allow debug switches to override the above settings. These are set to -1
4871 in rs6000.opt to indicate the user hasn't directly set the switch. */
4872 if (TARGET_ALWAYS_HINT >= 0)
4873 rs6000_always_hint = TARGET_ALWAYS_HINT;
4875 if (TARGET_SCHED_GROUPS >= 0)
4876 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4878 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4879 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4881 rs6000_sched_restricted_insns_priority
4882 = (rs6000_sched_groups ? 1 : 0);
4884 /* Handle -msched-costly-dep option. */
4885 rs6000_sched_costly_dep
4886 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4888 if (rs6000_sched_costly_dep_str)
4890 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4891 rs6000_sched_costly_dep = no_dep_costly;
4892 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4893 rs6000_sched_costly_dep = all_deps_costly;
4894 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4895 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4896 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4897 rs6000_sched_costly_dep = store_to_load_dep_costly;
4899 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4900 atoi (rs6000_sched_costly_dep_str));
4903 /* Handle -minsert-sched-nops option. */
4904 rs6000_sched_insert_nops
4905 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4907 if (rs6000_sched_insert_nops_str)
4909 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4910 rs6000_sched_insert_nops = sched_finish_none;
4911 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4912 rs6000_sched_insert_nops = sched_finish_pad_groups;
4913 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4914 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4916 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4917 atoi (rs6000_sched_insert_nops_str));
4920 /* Handle stack protector */
4921 if (!global_options_set.x_rs6000_stack_protector_guard)
4922 #ifdef TARGET_THREAD_SSP_OFFSET
4923 rs6000_stack_protector_guard = SSP_TLS;
4925 rs6000_stack_protector_guard = SSP_GLOBAL;
4928 #ifdef TARGET_THREAD_SSP_OFFSET
4929 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4930 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4933 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4936 const char *str = rs6000_stack_protector_guard_offset_str;
4939 long offset = strtol (str, &endp, 0);
4940 if (!*str || *endp || errno)
4941 error ("%qs is not a valid number in %qs", str,
4942 "-mstack-protector-guard-offset=");
4944 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4945 || (TARGET_64BIT && (offset & 3)))
4946 error ("%qs is not a valid offset in %qs", str,
4947 "-mstack-protector-guard-offset=");
4949 rs6000_stack_protector_guard_offset = offset;
4952 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4954 const char *str = rs6000_stack_protector_guard_reg_str;
4955 int reg = decode_reg_name (str);
4957 if (!IN_RANGE (reg, 1, 31))
4958 error ("%qs is not a valid base register in %qs", str,
4959 "-mstack-protector-guard-reg=");
4961 rs6000_stack_protector_guard_reg = reg;
4964 if (rs6000_stack_protector_guard == SSP_TLS
4965 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4966 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4970 #ifdef TARGET_REGNAMES
4971 /* If the user desires alternate register names, copy in the
4972 alternate names now. */
4973 if (TARGET_REGNAMES)
4974 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4977 /* Set aix_struct_return last, after the ABI is determined.
4978 If -maix-struct-return or -msvr4-struct-return was explicitly
4979 used, don't override with the ABI default. */
4980 if (!global_options_set.x_aix_struct_return)
4981 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4984 /* IBM XL compiler defaults to unsigned bitfields. */
4985 if (TARGET_XL_COMPAT)
4986 flag_signed_bitfields = 0;
4989 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4990 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4992 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4994 /* We can only guarantee the availability of DI pseudo-ops when
4995 assembling for 64-bit targets. */
4998 targetm.asm_out.aligned_op.di = NULL;
4999 targetm.asm_out.unaligned_op.di = NULL;
5003 /* Set branch target alignment, if not optimizing for size. */
5006 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
5007 aligned 8byte to avoid misprediction by the branch predictor. */
5008 if (rs6000_tune == PROCESSOR_TITAN
5009 || rs6000_tune == PROCESSOR_CELL)
5011 if (align_functions <= 0)
5012 align_functions = 8;
5013 if (align_jumps <= 0)
5015 if (align_loops <= 0)
5018 if (rs6000_align_branch_targets)
5020 if (align_functions <= 0)
5021 align_functions = 16;
5022 if (align_jumps <= 0)
5024 if (align_loops <= 0)
5026 can_override_loop_align = 1;
5030 if (align_jumps_max_skip <= 0)
5031 align_jumps_max_skip = 15;
5032 if (align_loops_max_skip <= 0)
5033 align_loops_max_skip = 15;
5036 /* Arrange to save and restore machine status around nested functions. */
5037 init_machine_status = rs6000_init_machine_status;
5039 /* We should always be splitting complex arguments, but we can't break
5040 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
5041 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
5042 targetm.calls.split_complex_arg = NULL;
5044 /* The AIX and ELFv1 ABIs define standard function descriptors. */
5045 if (DEFAULT_ABI == ABI_AIX)
5046 targetm.calls.custom_function_descriptors = 0;
5049 /* Initialize rs6000_cost with the appropriate target costs. */
5051 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
5053 switch (rs6000_tune)
5055 case PROCESSOR_RS64A:
5056 rs6000_cost = &rs64a_cost;
5059 case PROCESSOR_MPCCORE:
5060 rs6000_cost = &mpccore_cost;
5063 case PROCESSOR_PPC403:
5064 rs6000_cost = &ppc403_cost;
5067 case PROCESSOR_PPC405:
5068 rs6000_cost = &ppc405_cost;
5071 case PROCESSOR_PPC440:
5072 rs6000_cost = &ppc440_cost;
5075 case PROCESSOR_PPC476:
5076 rs6000_cost = &ppc476_cost;
5079 case PROCESSOR_PPC601:
5080 rs6000_cost = &ppc601_cost;
5083 case PROCESSOR_PPC603:
5084 rs6000_cost = &ppc603_cost;
5087 case PROCESSOR_PPC604:
5088 rs6000_cost = &ppc604_cost;
5091 case PROCESSOR_PPC604e:
5092 rs6000_cost = &ppc604e_cost;
5095 case PROCESSOR_PPC620:
5096 rs6000_cost = &ppc620_cost;
5099 case PROCESSOR_PPC630:
5100 rs6000_cost = &ppc630_cost;
5103 case PROCESSOR_CELL:
5104 rs6000_cost = &ppccell_cost;
5107 case PROCESSOR_PPC750:
5108 case PROCESSOR_PPC7400:
5109 rs6000_cost = &ppc750_cost;
5112 case PROCESSOR_PPC7450:
5113 rs6000_cost = &ppc7450_cost;
5116 case PROCESSOR_PPC8540:
5117 case PROCESSOR_PPC8548:
5118 rs6000_cost = &ppc8540_cost;
5121 case PROCESSOR_PPCE300C2:
5122 case PROCESSOR_PPCE300C3:
5123 rs6000_cost = &ppce300c2c3_cost;
5126 case PROCESSOR_PPCE500MC:
5127 rs6000_cost = &ppce500mc_cost;
5130 case PROCESSOR_PPCE500MC64:
5131 rs6000_cost = &ppce500mc64_cost;
5134 case PROCESSOR_PPCE5500:
5135 rs6000_cost = &ppce5500_cost;
5138 case PROCESSOR_PPCE6500:
5139 rs6000_cost = &ppce6500_cost;
5142 case PROCESSOR_TITAN:
5143 rs6000_cost = &titan_cost;
5146 case PROCESSOR_POWER4:
5147 case PROCESSOR_POWER5:
5148 rs6000_cost = &power4_cost;
5151 case PROCESSOR_POWER6:
5152 rs6000_cost = &power6_cost;
5155 case PROCESSOR_POWER7:
5156 rs6000_cost = &power7_cost;
5159 case PROCESSOR_POWER8:
5160 rs6000_cost = &power8_cost;
5163 case PROCESSOR_POWER9:
5164 rs6000_cost = &power9_cost;
5167 case PROCESSOR_PPCA2:
5168 rs6000_cost = &ppca2_cost;
5177 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
5178 rs6000_cost->simultaneous_prefetches,
5179 global_options.x_param_values,
5180 global_options_set.x_param_values);
5181 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
5182 global_options.x_param_values,
5183 global_options_set.x_param_values);
5184 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
5185 rs6000_cost->cache_line_size,
5186 global_options.x_param_values,
5187 global_options_set.x_param_values);
5188 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
5189 global_options.x_param_values,
5190 global_options_set.x_param_values);
5192 /* Increase loop peeling limits based on performance analysis. */
5193 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
5194 global_options.x_param_values,
5195 global_options_set.x_param_values);
5196 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
5197 global_options.x_param_values,
5198 global_options_set.x_param_values);
5200 /* Use the 'model' -fsched-pressure algorithm by default. */
5201 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
5202 SCHED_PRESSURE_MODEL,
5203 global_options.x_param_values,
5204 global_options_set.x_param_values);
5206 /* If using typedef char *va_list, signal that
5207 __builtin_va_start (&ap, 0) can be optimized to
5208 ap = __builtin_next_arg (0). */
5209 if (DEFAULT_ABI != ABI_V4)
5210 targetm.expand_builtin_va_start = NULL;
5213 /* Set up single/double float flags.
5214 If TARGET_HARD_FLOAT is set, but neither single or double is set,
5215 then set both flags. */
5216 if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
5217 rs6000_single_float = rs6000_double_float = 1;
5219 /* If not explicitly specified via option, decide whether to generate indexed
5220 load/store instructions. A value of -1 indicates that the
5221 initial value of this variable has not been overwritten. During
5222 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5223 if (TARGET_AVOID_XFORM == -1)
5224 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5225 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5226 need indexed accesses and the type used is the scalar type of the element
5227 being loaded or stored. */
5228 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
5229 && !TARGET_ALTIVEC);
5231 /* Set the -mrecip options. */
5232 if (rs6000_recip_name)
5234 char *p = ASTRDUP (rs6000_recip_name);
5236 unsigned int mask, i;
5239 while ((q = strtok (p, ",")) != NULL)
5250 if (!strcmp (q, "default"))
5251 mask = ((TARGET_RECIP_PRECISION)
5252 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
5255 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
5256 if (!strcmp (q, recip_options[i].string))
5258 mask = recip_options[i].mask;
5262 if (i == ARRAY_SIZE (recip_options))
5264 error ("unknown option for %<%s=%s%>", "-mrecip", q);
5272 rs6000_recip_control &= ~mask;
5274 rs6000_recip_control |= mask;
5278 /* Set the builtin mask of the various options used that could affect which
5279 builtins were used. In the past we used target_flags, but we've run out
5280 of bits, and some options like PAIRED are no longer in target_flags. */
5281 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
5282 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
5283 rs6000_print_builtin_options (stderr, 0, "builtin mask",
5284 rs6000_builtin_mask);
5286 /* Initialize all of the registers. */
5287 rs6000_init_hard_regno_mode_ok (global_init_p);
5289 /* Save the initial options in case the user does function specific options */
5291 target_option_default_node = target_option_current_node
5292 = build_target_option_node (&global_options);
5294 /* If not explicitly specified via option, decide whether to generate the
5295 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5296 if (TARGET_LINK_STACK == -1)
5297 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
5302 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5303 define the target cpu type. */
5306 rs6000_option_override (void)
5308 (void) rs6000_option_override_internal (true);
5312 /* Implement targetm.vectorize.builtin_mask_for_load. */
5314 rs6000_builtin_mask_for_load (void)
5316 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5317 if ((TARGET_ALTIVEC && !TARGET_VSX)
5318 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
5319 return altivec_builtin_mask_for_load;
5324 /* Implement LOOP_ALIGN. */
5326 rs6000_loop_align (rtx label)
5331 /* Don't override loop alignment if -falign-loops was specified. */
5332 if (!can_override_loop_align)
5333 return align_loops_log;
5335 bb = BLOCK_FOR_INSN (label);
5336 ninsns = num_loop_insns(bb->loop_father);
5338 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5339 if (ninsns > 4 && ninsns <= 8
5340 && (rs6000_tune == PROCESSOR_POWER4
5341 || rs6000_tune == PROCESSOR_POWER5
5342 || rs6000_tune == PROCESSOR_POWER6
5343 || rs6000_tune == PROCESSOR_POWER7
5344 || rs6000_tune == PROCESSOR_POWER8
5345 || rs6000_tune == PROCESSOR_POWER9))
5348 return align_loops_log;
5351 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5353 rs6000_loop_align_max_skip (rtx_insn *label)
5355 return (1 << rs6000_loop_align (label)) - 1;
5358 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5359 after applying N number of iterations. This routine does not determine
5360 how may iterations are required to reach desired alignment. */
5363 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5370 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5373 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5383 /* Assuming that all other types are naturally aligned. CHECKME! */
5388 /* Return true if the vector misalignment factor is supported by the
5391 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5398 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5401 /* Return if movmisalign pattern is not supported for this mode. */
5402 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5405 if (misalignment == -1)
5407 /* Misalignment factor is unknown at compile time but we know
5408 it's word aligned. */
5409 if (rs6000_vector_alignment_reachable (type, is_packed))
5411 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5413 if (element_size == 64 || element_size == 32)
5420 /* VSX supports word-aligned vector. */
5421 if (misalignment % 4 == 0)
5427 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5429 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5430 tree vectype, int misalign)
5435 switch (type_of_cost)
5445 case cond_branch_not_taken:
5454 case vec_promote_demote:
5460 case cond_branch_taken:
5463 case unaligned_load:
5464 case vector_gather_load:
5465 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5468 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5470 elements = TYPE_VECTOR_SUBPARTS (vectype);
5472 /* Double word aligned. */
5480 /* Double word aligned. */
5484 /* Unknown misalignment. */
5497 /* Misaligned loads are not supported. */
5502 case unaligned_store:
5503 case vector_scatter_store:
5504 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5507 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5509 elements = TYPE_VECTOR_SUBPARTS (vectype);
5511 /* Double word aligned. */
5519 /* Double word aligned. */
5523 /* Unknown misalignment. */
5536 /* Misaligned stores are not supported. */
5542 /* This is a rough approximation assuming non-constant elements
5543 constructed into a vector via element insertion. FIXME:
5544 vec_construct is not granular enough for uniformly good
5545 decisions. If the initialization is a splat, this is
5546 cheaper than we estimate. Improve this someday. */
5547 elem_type = TREE_TYPE (vectype);
5548 /* 32-bit vectors loaded into registers are stored as double
5549 precision, so we need 2 permutes, 2 converts, and 1 merge
5550 to construct a vector of short floats from them. */
5551 if (SCALAR_FLOAT_TYPE_P (elem_type)
5552 && TYPE_PRECISION (elem_type) == 32)
5554 /* On POWER9, integer vector types are built up in GPRs and then
5555 use a direct move (2 cycles). For POWER8 this is even worse,
5556 as we need two direct moves and a merge, and the direct moves
5558 else if (INTEGRAL_TYPE_P (elem_type))
5560 if (TARGET_P9_VECTOR)
5561 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5563 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5566 /* V2DFmode doesn't need a direct move. */
5574 /* Implement targetm.vectorize.preferred_simd_mode. */
5577 rs6000_preferred_simd_mode (scalar_mode mode)
5586 if (TARGET_ALTIVEC || TARGET_VSX)
5603 if (TARGET_PAIRED_FLOAT
5609 typedef struct _rs6000_cost_data
5611 struct loop *loop_info;
5615 /* Test for likely overcommitment of vector hardware resources. If a
5616 loop iteration is relatively large, and too large a percentage of
5617 instructions in the loop are vectorized, the cost model may not
5618 adequately reflect delays from unavailable vector resources.
5619 Penalize the loop body cost for this case. */
5622 rs6000_density_test (rs6000_cost_data *data)
5624 const int DENSITY_PCT_THRESHOLD = 85;
5625 const int DENSITY_SIZE_THRESHOLD = 70;
5626 const int DENSITY_PENALTY = 10;
5627 struct loop *loop = data->loop_info;
5628 basic_block *bbs = get_loop_body (loop);
5629 int nbbs = loop->num_nodes;
5630 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5633 for (i = 0; i < nbbs; i++)
5635 basic_block bb = bbs[i];
5636 gimple_stmt_iterator gsi;
5638 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5640 gimple *stmt = gsi_stmt (gsi);
5641 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
5643 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5644 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5650 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5652 if (density_pct > DENSITY_PCT_THRESHOLD
5653 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5655 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5656 if (dump_enabled_p ())
5657 dump_printf_loc (MSG_NOTE, vect_location,
5658 "density %d%%, cost %d exceeds threshold, penalizing "
5659 "loop body cost by %d%%", density_pct,
5660 vec_cost + not_vec_cost, DENSITY_PENALTY);
5664 /* Implement targetm.vectorize.init_cost. */
5666 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5667 instruction is needed by the vectorization. */
5668 static bool rs6000_vect_nonmem;
5671 rs6000_init_cost (struct loop *loop_info)
5673 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5674 data->loop_info = loop_info;
5675 data->cost[vect_prologue] = 0;
5676 data->cost[vect_body] = 0;
5677 data->cost[vect_epilogue] = 0;
5678 rs6000_vect_nonmem = false;
5682 /* Implement targetm.vectorize.add_stmt_cost. */
5685 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5686 struct _stmt_vec_info *stmt_info, int misalign,
5687 enum vect_cost_model_location where)
5689 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5690 unsigned retval = 0;
5692 if (flag_vect_cost_model)
5694 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5695 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5697 /* Statements in an inner loop relative to the loop being
5698 vectorized are weighted more heavily. The value here is
5699 arbitrary and could potentially be improved with analysis. */
5700 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5701 count *= 50; /* FIXME. */
5703 retval = (unsigned) (count * stmt_cost);
5704 cost_data->cost[where] += retval;
5706 /* Check whether we're doing something other than just a copy loop.
5707 Not all such loops may be profitably vectorized; see
5708 rs6000_finish_cost. */
5709 if ((kind == vec_to_scalar || kind == vec_perm
5710 || kind == vec_promote_demote || kind == vec_construct
5711 || kind == scalar_to_vec)
5712 || (where == vect_body && kind == vector_stmt))
5713 rs6000_vect_nonmem = true;
5719 /* Implement targetm.vectorize.finish_cost. */
5722 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5723 unsigned *body_cost, unsigned *epilogue_cost)
5725 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5727 if (cost_data->loop_info)
5728 rs6000_density_test (cost_data);
5730 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5731 that require versioning for any reason. The vectorization is at
5732 best a wash inside the loop, and the versioning checks make
5733 profitability highly unlikely and potentially quite harmful. */
5734 if (cost_data->loop_info)
5736 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5737 if (!rs6000_vect_nonmem
5738 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5739 && LOOP_REQUIRES_VERSIONING (vec_info))
5740 cost_data->cost[vect_body] += 10000;
5743 *prologue_cost = cost_data->cost[vect_prologue];
5744 *body_cost = cost_data->cost[vect_body];
5745 *epilogue_cost = cost_data->cost[vect_epilogue];
5748 /* Implement targetm.vectorize.destroy_cost_data. */
5751 rs6000_destroy_cost_data (void *data)
5756 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5757 library with vectorized intrinsics. */
5760 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5764 const char *suffix = NULL;
5765 tree fntype, new_fndecl, bdecl = NULL_TREE;
5768 machine_mode el_mode, in_mode;
5771 /* Libmass is suitable for unsafe math only as it does not correctly support
5772 parts of IEEE with the required precision such as denormals. Only support
5773 it if we have VSX to use the simd d2 or f4 functions.
5774 XXX: Add variable length support. */
5775 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5778 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5779 n = TYPE_VECTOR_SUBPARTS (type_out);
5780 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5781 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5782 if (el_mode != in_mode
5818 if (el_mode == DFmode && n == 2)
5820 bdecl = mathfn_built_in (double_type_node, fn);
5821 suffix = "d2"; /* pow -> powd2 */
5823 else if (el_mode == SFmode && n == 4)
5825 bdecl = mathfn_built_in (float_type_node, fn);
5826 suffix = "4"; /* powf -> powf4 */
5838 gcc_assert (suffix != NULL);
5839 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5843 strcpy (name, bname + sizeof ("__builtin_") - 1);
5844 strcat (name, suffix);
5847 fntype = build_function_type_list (type_out, type_in, NULL);
5848 else if (n_args == 2)
5849 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5853 /* Build a function declaration for the vectorized function. */
5854 new_fndecl = build_decl (BUILTINS_LOCATION,
5855 FUNCTION_DECL, get_identifier (name), fntype);
5856 TREE_PUBLIC (new_fndecl) = 1;
5857 DECL_EXTERNAL (new_fndecl) = 1;
5858 DECL_IS_NOVOPS (new_fndecl) = 1;
5859 TREE_READONLY (new_fndecl) = 1;
5864 /* Returns a function decl for a vectorized version of the builtin function
5865 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5866 if it is not available. */
5869 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5872 machine_mode in_mode, out_mode;
5875 if (TARGET_DEBUG_BUILTIN)
5876 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5877 combined_fn_name (combined_fn (fn)),
5878 GET_MODE_NAME (TYPE_MODE (type_out)),
5879 GET_MODE_NAME (TYPE_MODE (type_in)));
5881 if (TREE_CODE (type_out) != VECTOR_TYPE
5882 || TREE_CODE (type_in) != VECTOR_TYPE)
5885 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5886 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5887 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5888 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5893 if (VECTOR_UNIT_VSX_P (V2DFmode)
5894 && out_mode == DFmode && out_n == 2
5895 && in_mode == DFmode && in_n == 2)
5896 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5897 if (VECTOR_UNIT_VSX_P (V4SFmode)
5898 && out_mode == SFmode && out_n == 4
5899 && in_mode == SFmode && in_n == 4)
5900 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5901 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5902 && out_mode == SFmode && out_n == 4
5903 && in_mode == SFmode && in_n == 4)
5904 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5907 if (VECTOR_UNIT_VSX_P (V2DFmode)
5908 && out_mode == DFmode && out_n == 2
5909 && in_mode == DFmode && in_n == 2)
5910 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5911 if (VECTOR_UNIT_VSX_P (V4SFmode)
5912 && out_mode == SFmode && out_n == 4
5913 && in_mode == SFmode && in_n == 4)
5914 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5915 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5916 && out_mode == SFmode && out_n == 4
5917 && in_mode == SFmode && in_n == 4)
5918 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5921 if (VECTOR_UNIT_VSX_P (V2DFmode)
5922 && out_mode == DFmode && out_n == 2
5923 && in_mode == DFmode && in_n == 2)
5924 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5925 if (VECTOR_UNIT_VSX_P (V4SFmode)
5926 && out_mode == SFmode && out_n == 4
5927 && in_mode == SFmode && in_n == 4)
5928 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5929 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5930 && out_mode == SFmode && out_n == 4
5931 && in_mode == SFmode && in_n == 4)
5932 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5935 if (VECTOR_UNIT_VSX_P (V2DFmode)
5936 && out_mode == DFmode && out_n == 2
5937 && in_mode == DFmode && in_n == 2)
5938 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5939 if (VECTOR_UNIT_VSX_P (V4SFmode)
5940 && out_mode == SFmode && out_n == 4
5941 && in_mode == SFmode && in_n == 4)
5942 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5943 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5944 && out_mode == SFmode && out_n == 4
5945 && in_mode == SFmode && in_n == 4)
5946 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5949 if (VECTOR_UNIT_VSX_P (V2DFmode)
5950 && out_mode == DFmode && out_n == 2
5951 && in_mode == DFmode && in_n == 2)
5952 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5953 if (VECTOR_UNIT_VSX_P (V4SFmode)
5954 && out_mode == SFmode && out_n == 4
5955 && in_mode == SFmode && in_n == 4)
5956 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5957 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5958 && out_mode == SFmode && out_n == 4
5959 && in_mode == SFmode && in_n == 4)
5960 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5963 if (VECTOR_UNIT_VSX_P (V2DFmode)
5964 && flag_unsafe_math_optimizations
5965 && out_mode == DFmode && out_n == 2
5966 && in_mode == DFmode && in_n == 2)
5967 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5968 if (VECTOR_UNIT_VSX_P (V4SFmode)
5969 && flag_unsafe_math_optimizations
5970 && out_mode == SFmode && out_n == 4
5971 && in_mode == SFmode && in_n == 4)
5972 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5975 if (VECTOR_UNIT_VSX_P (V2DFmode)
5976 && !flag_trapping_math
5977 && out_mode == DFmode && out_n == 2
5978 && in_mode == DFmode && in_n == 2)
5979 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5980 if (VECTOR_UNIT_VSX_P (V4SFmode)
5981 && !flag_trapping_math
5982 && out_mode == SFmode && out_n == 4
5983 && in_mode == SFmode && in_n == 4)
5984 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5990 /* Generate calls to libmass if appropriate. */
5991 if (rs6000_veclib_handler)
5992 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5997 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
6000 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
6003 machine_mode in_mode, out_mode;
6006 if (TARGET_DEBUG_BUILTIN)
6007 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
6008 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
6009 GET_MODE_NAME (TYPE_MODE (type_out)),
6010 GET_MODE_NAME (TYPE_MODE (type_in)));
6012 if (TREE_CODE (type_out) != VECTOR_TYPE
6013 || TREE_CODE (type_in) != VECTOR_TYPE)
6016 out_mode = TYPE_MODE (TREE_TYPE (type_out));
6017 out_n = TYPE_VECTOR_SUBPARTS (type_out);
6018 in_mode = TYPE_MODE (TREE_TYPE (type_in));
6019 in_n = TYPE_VECTOR_SUBPARTS (type_in);
6021 enum rs6000_builtins fn
6022 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
6025 case RS6000_BUILTIN_RSQRTF:
6026 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6027 && out_mode == SFmode && out_n == 4
6028 && in_mode == SFmode && in_n == 4)
6029 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
6031 case RS6000_BUILTIN_RSQRT:
6032 if (VECTOR_UNIT_VSX_P (V2DFmode)
6033 && out_mode == DFmode && out_n == 2
6034 && in_mode == DFmode && in_n == 2)
6035 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
6037 case RS6000_BUILTIN_RECIPF:
6038 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6039 && out_mode == SFmode && out_n == 4
6040 && in_mode == SFmode && in_n == 4)
6041 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
6043 case RS6000_BUILTIN_RECIP:
6044 if (VECTOR_UNIT_VSX_P (V2DFmode)
6045 && out_mode == DFmode && out_n == 2
6046 && in_mode == DFmode && in_n == 2)
6047 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
6055 /* Default CPU string for rs6000*_file_start functions. */
6056 static const char *rs6000_default_cpu;
6058 /* Do anything needed at the start of the asm file. */
6061 rs6000_file_start (void)
6064 const char *start = buffer;
6065 FILE *file = asm_out_file;
6067 rs6000_default_cpu = TARGET_CPU_DEFAULT;
6069 default_file_start ();
6071 if (flag_verbose_asm)
6073 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
6075 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
6077 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
6081 if (global_options_set.x_rs6000_cpu_index)
6083 fprintf (file, "%s -mcpu=%s", start,
6084 processor_target_table[rs6000_cpu_index].name);
6088 if (global_options_set.x_rs6000_tune_index)
6090 fprintf (file, "%s -mtune=%s", start,
6091 processor_target_table[rs6000_tune_index].name);
6095 if (PPC405_ERRATUM77)
6097 fprintf (file, "%s PPC405CR_ERRATUM77", start);
6101 #ifdef USING_ELFOS_H
6102 switch (rs6000_sdata)
6104 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
6105 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
6106 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
6107 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
6110 if (rs6000_sdata && g_switch_value)
6112 fprintf (file, "%s -G %d", start,
6122 #ifdef USING_ELFOS_H
6123 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
6124 && !global_options_set.x_rs6000_cpu_index)
6126 fputs ("\t.machine ", asm_out_file);
6127 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
6128 fputs ("power9\n", asm_out_file);
6129 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
6130 fputs ("power8\n", asm_out_file);
6131 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
6132 fputs ("power7\n", asm_out_file);
6133 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
6134 fputs ("power6\n", asm_out_file);
6135 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
6136 fputs ("power5\n", asm_out_file);
6137 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
6138 fputs ("power4\n", asm_out_file);
6139 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
6140 fputs ("ppc64\n", asm_out_file);
6142 fputs ("ppc\n", asm_out_file);
6146 if (DEFAULT_ABI == ABI_ELFv2)
6147 fprintf (file, "\t.abiversion 2\n");
6151 /* Return nonzero if this function is known to have a null epilogue. */
6154 direct_return (void)
6156 if (reload_completed)
6158 rs6000_stack_t *info = rs6000_stack_info ();
6160 if (info->first_gp_reg_save == 32
6161 && info->first_fp_reg_save == 64
6162 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
6163 && ! info->lr_save_p
6164 && ! info->cr_save_p
6165 && info->vrsave_size == 0
6173 /* Return the number of instructions it takes to form a constant in an
6174 integer register. */
6177 num_insns_constant_wide (HOST_WIDE_INT value)
6179 /* signed constant loadable with addi */
6180 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
6183 /* constant loadable with addis */
6184 else if ((value & 0xffff) == 0
6185 && (value >> 31 == -1 || value >> 31 == 0))
6188 else if (TARGET_POWERPC64)
6190 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
6191 HOST_WIDE_INT high = value >> 31;
6193 if (high == 0 || high == -1)
6199 return num_insns_constant_wide (high) + 1;
6201 return num_insns_constant_wide (low) + 1;
6203 return (num_insns_constant_wide (high)
6204 + num_insns_constant_wide (low) + 1);
6212 num_insns_constant (rtx op, machine_mode mode)
6214 HOST_WIDE_INT low, high;
6216 switch (GET_CODE (op))
6219 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
6220 && rs6000_is_valid_and_mask (op, mode))
6223 return num_insns_constant_wide (INTVAL (op));
6225 case CONST_WIDE_INT:
6228 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
6229 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
6230 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
6235 if (mode == SFmode || mode == SDmode)
6239 if (DECIMAL_FLOAT_MODE_P (mode))
6240 REAL_VALUE_TO_TARGET_DECIMAL32
6241 (*CONST_DOUBLE_REAL_VALUE (op), l);
6243 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6244 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6248 if (DECIMAL_FLOAT_MODE_P (mode))
6249 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
6251 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6252 high = l[WORDS_BIG_ENDIAN == 0];
6253 low = l[WORDS_BIG_ENDIAN != 0];
6256 return (num_insns_constant_wide (low)
6257 + num_insns_constant_wide (high));
6260 if ((high == 0 && low >= 0)
6261 || (high == -1 && low < 0))
6262 return num_insns_constant_wide (low);
6264 else if (rs6000_is_valid_and_mask (op, mode))
6268 return num_insns_constant_wide (high) + 1;
6271 return (num_insns_constant_wide (high)
6272 + num_insns_constant_wide (low) + 1);
6280 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6281 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6282 corresponding element of the vector, but for V4SFmode and V2SFmode,
6283 the corresponding "float" is interpreted as an SImode integer. */
6286 const_vector_elt_as_int (rtx op, unsigned int elt)
6290 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6291 gcc_assert (GET_MODE (op) != V2DImode
6292 && GET_MODE (op) != V2DFmode);
6294 tmp = CONST_VECTOR_ELT (op, elt);
6295 if (GET_MODE (op) == V4SFmode
6296 || GET_MODE (op) == V2SFmode)
6297 tmp = gen_lowpart (SImode, tmp);
6298 return INTVAL (tmp);
6301 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6302 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6303 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6304 all items are set to the same value and contain COPIES replicas of the
6305 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6306 operand and the others are set to the value of the operand's msb. */
6309 vspltis_constant (rtx op, unsigned step, unsigned copies)
6311 machine_mode mode = GET_MODE (op);
6312 machine_mode inner = GET_MODE_INNER (mode);
6320 HOST_WIDE_INT splat_val;
6321 HOST_WIDE_INT msb_val;
6323 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
6326 nunits = GET_MODE_NUNITS (mode);
6327 bitsize = GET_MODE_BITSIZE (inner);
6328 mask = GET_MODE_MASK (inner);
6330 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6332 msb_val = val >= 0 ? 0 : -1;
6334 /* Construct the value to be splatted, if possible. If not, return 0. */
6335 for (i = 2; i <= copies; i *= 2)
6337 HOST_WIDE_INT small_val;
6339 small_val = splat_val >> bitsize;
6341 if (splat_val != ((HOST_WIDE_INT)
6342 ((unsigned HOST_WIDE_INT) small_val << bitsize)
6343 | (small_val & mask)))
6345 splat_val = small_val;
6348 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6349 if (EASY_VECTOR_15 (splat_val))
6352 /* Also check if we can splat, and then add the result to itself. Do so if
6353 the value is positive, of if the splat instruction is using OP's mode;
6354 for splat_val < 0, the splat and the add should use the same mode. */
6355 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6356 && (splat_val >= 0 || (step == 1 && copies == 1)))
6359 /* Also check if are loading up the most significant bit which can be done by
6360 loading up -1 and shifting the value left by -1. */
6361 else if (EASY_VECTOR_MSB (splat_val, inner))
6367 /* Check if VAL is present in every STEP-th element, and the
6368 other elements are filled with its most significant bit. */
6369 for (i = 1; i < nunits; ++i)
6371 HOST_WIDE_INT desired_val;
6372 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6373 if ((i & (step - 1)) == 0)
6376 desired_val = msb_val;
6378 if (desired_val != const_vector_elt_as_int (op, elt))
6385 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6386 instruction, filling in the bottom elements with 0 or -1.
6388 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6389 for the number of zeroes to shift in, or negative for the number of 0xff
6392 OP is a CONST_VECTOR. */
6395 vspltis_shifted (rtx op)
6397 machine_mode mode = GET_MODE (op);
6398 machine_mode inner = GET_MODE_INNER (mode);
6406 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6409 /* We need to create pseudo registers to do the shift, so don't recognize
6410 shift vector constants after reload. */
6411 if (!can_create_pseudo_p ())
6414 nunits = GET_MODE_NUNITS (mode);
6415 mask = GET_MODE_MASK (inner);
6417 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6419 /* Check if the value can really be the operand of a vspltis[bhw]. */
6420 if (EASY_VECTOR_15 (val))
6423 /* Also check if we are loading up the most significant bit which can be done
6424 by loading up -1 and shifting the value left by -1. */
6425 else if (EASY_VECTOR_MSB (val, inner))
6431 /* Check if VAL is present in every STEP-th element until we find elements
6432 that are 0 or all 1 bits. */
6433 for (i = 1; i < nunits; ++i)
6435 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6436 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6438 /* If the value isn't the splat value, check for the remaining elements
6444 for (j = i+1; j < nunits; ++j)
6446 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6447 if (const_vector_elt_as_int (op, elt2) != 0)
6451 return (nunits - i) * GET_MODE_SIZE (inner);
6454 else if ((elt_val & mask) == mask)
6456 for (j = i+1; j < nunits; ++j)
6458 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6459 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6463 return -((nunits - i) * GET_MODE_SIZE (inner));
6471 /* If all elements are equal, we don't need to do VLSDOI. */
6476 /* Return true if OP is of the given MODE and can be synthesized
6477 with a vspltisb, vspltish or vspltisw. */
6480 easy_altivec_constant (rtx op, machine_mode mode)
6482 unsigned step, copies;
6484 if (mode == VOIDmode)
6485 mode = GET_MODE (op);
6486 else if (mode != GET_MODE (op))
6489 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6491 if (mode == V2DFmode)
6492 return zero_constant (op, mode);
6494 else if (mode == V2DImode)
6496 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6497 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6500 if (zero_constant (op, mode))
6503 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6504 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6510 /* V1TImode is a special container for TImode. Ignore for now. */
6511 else if (mode == V1TImode)
6514 /* Start with a vspltisw. */
6515 step = GET_MODE_NUNITS (mode) / 4;
6518 if (vspltis_constant (op, step, copies))
6521 /* Then try with a vspltish. */
6527 if (vspltis_constant (op, step, copies))
6530 /* And finally a vspltisb. */
6536 if (vspltis_constant (op, step, copies))
6539 if (vspltis_shifted (op) != 0)
6545 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6546 result is OP. Abort if it is not possible. */
6549 gen_easy_altivec_constant (rtx op)
6551 machine_mode mode = GET_MODE (op);
6552 int nunits = GET_MODE_NUNITS (mode);
6553 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6554 unsigned step = nunits / 4;
6555 unsigned copies = 1;
6557 /* Start with a vspltisw. */
6558 if (vspltis_constant (op, step, copies))
6559 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6561 /* Then try with a vspltish. */
6567 if (vspltis_constant (op, step, copies))
6568 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6570 /* And finally a vspltisb. */
6576 if (vspltis_constant (op, step, copies))
6577 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6582 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6583 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6585 Return the number of instructions needed (1 or 2) into the address pointed
6588 Return the constant that is being split via CONSTANT_PTR. */
6591 xxspltib_constant_p (rtx op,
6596 size_t nunits = GET_MODE_NUNITS (mode);
6598 HOST_WIDE_INT value;
6601 /* Set the returned values to out of bound values. */
6602 *num_insns_ptr = -1;
6603 *constant_ptr = 256;
6605 if (!TARGET_P9_VECTOR)
6608 if (mode == VOIDmode)
6609 mode = GET_MODE (op);
6611 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6614 /* Handle (vec_duplicate <constant>). */
6615 if (GET_CODE (op) == VEC_DUPLICATE)
6617 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6618 && mode != V2DImode)
6621 element = XEXP (op, 0);
6622 if (!CONST_INT_P (element))
6625 value = INTVAL (element);
6626 if (!IN_RANGE (value, -128, 127))
6630 /* Handle (const_vector [...]). */
6631 else if (GET_CODE (op) == CONST_VECTOR)
6633 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6634 && mode != V2DImode)
6637 element = CONST_VECTOR_ELT (op, 0);
6638 if (!CONST_INT_P (element))
6641 value = INTVAL (element);
6642 if (!IN_RANGE (value, -128, 127))
6645 for (i = 1; i < nunits; i++)
6647 element = CONST_VECTOR_ELT (op, i);
6648 if (!CONST_INT_P (element))
6651 if (value != INTVAL (element))
6656 /* Handle integer constants being loaded into the upper part of the VSX
6657 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6658 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6659 else if (CONST_INT_P (op))
6661 if (!SCALAR_INT_MODE_P (mode))
6664 value = INTVAL (op);
6665 if (!IN_RANGE (value, -128, 127))
6668 if (!IN_RANGE (value, -1, 0))
6670 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6673 if (EASY_VECTOR_15 (value))
6681 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6682 sign extend. Special case 0/-1 to allow getting any VSX register instead
6683 of an Altivec register. */
6684 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6685 && EASY_VECTOR_15 (value))
6688 /* Return # of instructions and the constant byte for XXSPLTIB. */
6689 if (mode == V16QImode)
6692 else if (IN_RANGE (value, -1, 0))
6698 *constant_ptr = (int) value;
6703 output_vec_const_move (rtx *operands)
6711 mode = GET_MODE (dest);
6715 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6716 int xxspltib_value = 256;
6719 if (zero_constant (vec, mode))
6721 if (TARGET_P9_VECTOR)
6722 return "xxspltib %x0,0";
6724 else if (dest_vmx_p)
6725 return "vspltisw %0,0";
6728 return "xxlxor %x0,%x0,%x0";
6731 if (all_ones_constant (vec, mode))
6733 if (TARGET_P9_VECTOR)
6734 return "xxspltib %x0,255";
6736 else if (dest_vmx_p)
6737 return "vspltisw %0,-1";
6739 else if (TARGET_P8_VECTOR)
6740 return "xxlorc %x0,%x0,%x0";
6746 if (TARGET_P9_VECTOR
6747 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6751 operands[2] = GEN_INT (xxspltib_value & 0xff);
6752 return "xxspltib %x0,%2";
6763 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6764 if (zero_constant (vec, mode))
6765 return "vspltisw %0,0";
6767 if (all_ones_constant (vec, mode))
6768 return "vspltisw %0,-1";
6770 /* Do we need to construct a value using VSLDOI? */
6771 shift = vspltis_shifted (vec);
6775 splat_vec = gen_easy_altivec_constant (vec);
6776 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6777 operands[1] = XEXP (splat_vec, 0);
6778 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6781 switch (GET_MODE (splat_vec))
6784 return "vspltisw %0,%1";
6787 return "vspltish %0,%1";
6790 return "vspltisb %0,%1";
6800 /* Initialize TARGET of vector PAIRED to VALS. */
6803 paired_expand_vector_init (rtx target, rtx vals)
6805 machine_mode mode = GET_MODE (target);
6806 int n_elts = GET_MODE_NUNITS (mode);
6808 rtx x, new_rtx, tmp, constant_op, op1, op2;
6811 for (i = 0; i < n_elts; ++i)
6813 x = XVECEXP (vals, 0, i);
6814 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6819 /* Load from constant pool. */
6820 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
6826 /* The vector is initialized only with non-constants. */
6827 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
6828 XVECEXP (vals, 0, 1));
6830 emit_move_insn (target, new_rtx);
6834 /* One field is non-constant and the other one is a constant. Load the
6835 constant from the constant pool and use ps_merge instruction to
6836 construct the whole vector. */
6837 op1 = XVECEXP (vals, 0, 0);
6838 op2 = XVECEXP (vals, 0, 1);
6840 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
6842 tmp = gen_reg_rtx (GET_MODE (constant_op));
6843 emit_move_insn (tmp, constant_op);
6845 if (CONSTANT_P (op1))
6846 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
6848 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
6850 emit_move_insn (target, new_rtx);
6854 paired_expand_vector_move (rtx operands[])
6856 rtx op0 = operands[0], op1 = operands[1];
6858 emit_move_insn (op0, op1);
6861 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6862 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6863 operands for the relation operation COND. This is a recursive
6867 paired_emit_vector_compare (enum rtx_code rcode,
6868 rtx dest, rtx op0, rtx op1,
6869 rtx cc_op0, rtx cc_op1)
6871 rtx tmp = gen_reg_rtx (V2SFmode);
6874 gcc_assert (TARGET_PAIRED_FLOAT);
6875 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
6881 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6885 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6886 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
6890 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
6893 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6896 tmp1 = gen_reg_rtx (V2SFmode);
6897 max = gen_reg_rtx (V2SFmode);
6898 min = gen_reg_rtx (V2SFmode);
6899 gen_reg_rtx (V2SFmode);
6901 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6902 emit_insn (gen_selv2sf4
6903 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6904 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
6905 emit_insn (gen_selv2sf4
6906 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6907 emit_insn (gen_subv2sf3 (tmp1, min, max));
6908 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
6911 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
6914 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6917 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
6920 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6923 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
6932 /* Emit vector conditional expression.
6933 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6934 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6937 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
6938 rtx cond, rtx cc_op0, rtx cc_op1)
6940 enum rtx_code rcode = GET_CODE (cond);
6942 if (!TARGET_PAIRED_FLOAT)
6945 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
6950 /* Initialize vector TARGET to VALS. */
6953 rs6000_expand_vector_init (rtx target, rtx vals)
6955 machine_mode mode = GET_MODE (target);
6956 machine_mode inner_mode = GET_MODE_INNER (mode);
6957 int n_elts = GET_MODE_NUNITS (mode);
6958 int n_var = 0, one_var = -1;
6959 bool all_same = true, all_const_zero = true;
6963 for (i = 0; i < n_elts; ++i)
6965 x = XVECEXP (vals, 0, i);
6966 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6967 ++n_var, one_var = i;
6968 else if (x != CONST0_RTX (inner_mode))
6969 all_const_zero = false;
6971 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6977 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6978 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6979 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6981 /* Zero register. */
6982 emit_move_insn (target, CONST0_RTX (mode));
6985 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6987 /* Splat immediate. */
6988 emit_insn (gen_rtx_SET (target, const_vec));
6993 /* Load from constant pool. */
6994 emit_move_insn (target, const_vec);
6999 /* Double word values on VSX can use xxpermdi or lxvdsx. */
7000 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
7004 size_t num_elements = all_same ? 1 : 2;
7005 for (i = 0; i < num_elements; i++)
7007 op[i] = XVECEXP (vals, 0, i);
7008 /* Just in case there is a SUBREG with a smaller mode, do a
7010 if (GET_MODE (op[i]) != inner_mode)
7012 rtx tmp = gen_reg_rtx (inner_mode);
7013 convert_move (tmp, op[i], 0);
7016 /* Allow load with splat double word. */
7017 else if (MEM_P (op[i]))
7020 op[i] = force_reg (inner_mode, op[i]);
7022 else if (!REG_P (op[i]))
7023 op[i] = force_reg (inner_mode, op[i]);
7028 if (mode == V2DFmode)
7029 emit_insn (gen_vsx_splat_v2df (target, op[0]));
7031 emit_insn (gen_vsx_splat_v2di (target, op[0]));
7035 if (mode == V2DFmode)
7036 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
7038 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
7043 /* Special case initializing vector int if we are on 64-bit systems with
7044 direct move or we have the ISA 3.0 instructions. */
7045 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
7046 && TARGET_DIRECT_MOVE_64BIT)
7050 rtx element0 = XVECEXP (vals, 0, 0);
7051 if (MEM_P (element0))
7052 element0 = rs6000_address_for_fpconvert (element0);
7054 element0 = force_reg (SImode, element0);
7056 if (TARGET_P9_VECTOR)
7057 emit_insn (gen_vsx_splat_v4si (target, element0));
7060 rtx tmp = gen_reg_rtx (DImode);
7061 emit_insn (gen_zero_extendsidi2 (tmp, element0));
7062 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
7071 for (i = 0; i < 4; i++)
7073 elements[i] = XVECEXP (vals, 0, i);
7074 if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
7075 elements[i] = copy_to_mode_reg (SImode, elements[i]);
7078 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
7079 elements[2], elements[3]));
7084 /* With single precision floating point on VSX, know that internally single
7085 precision is actually represented as a double, and either make 2 V2DF
7086 vectors, and convert these vectors to single precision, or do one
7087 conversion, and splat the result to the other elements. */
7088 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
7092 rtx element0 = XVECEXP (vals, 0, 0);
7094 if (TARGET_P9_VECTOR)
7096 if (MEM_P (element0))
7097 element0 = rs6000_address_for_fpconvert (element0);
7099 emit_insn (gen_vsx_splat_v4sf (target, element0));
7104 rtx freg = gen_reg_rtx (V4SFmode);
7105 rtx sreg = force_reg (SFmode, element0);
7106 rtx cvt = (TARGET_XSCVDPSPN
7107 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
7108 : gen_vsx_xscvdpsp_scalar (freg, sreg));
7111 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
7117 rtx dbl_even = gen_reg_rtx (V2DFmode);
7118 rtx dbl_odd = gen_reg_rtx (V2DFmode);
7119 rtx flt_even = gen_reg_rtx (V4SFmode);
7120 rtx flt_odd = gen_reg_rtx (V4SFmode);
7121 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
7122 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
7123 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
7124 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
7126 /* Use VMRGEW if we can instead of doing a permute. */
7127 if (TARGET_P8_VECTOR)
7129 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
7130 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
7131 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7132 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7133 if (BYTES_BIG_ENDIAN)
7134 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
7136 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
7140 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
7141 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
7142 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7143 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7144 rs6000_expand_extract_even (target, flt_even, flt_odd);
7150 /* Special case initializing vector short/char that are splats if we are on
7151 64-bit systems with direct move. */
7152 if (all_same && TARGET_DIRECT_MOVE_64BIT
7153 && (mode == V16QImode || mode == V8HImode))
7155 rtx op0 = XVECEXP (vals, 0, 0);
7156 rtx di_tmp = gen_reg_rtx (DImode);
7159 op0 = force_reg (GET_MODE_INNER (mode), op0);
7161 if (mode == V16QImode)
7163 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
7164 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
7168 if (mode == V8HImode)
7170 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
7171 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
7176 /* Store value to stack temp. Load vector element. Splat. However, splat
7177 of 64-bit items is not supported on Altivec. */
7178 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
7180 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7181 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
7182 XVECEXP (vals, 0, 0));
7183 x = gen_rtx_UNSPEC (VOIDmode,
7184 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7185 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7187 gen_rtx_SET (target, mem),
7189 x = gen_rtx_VEC_SELECT (inner_mode, target,
7190 gen_rtx_PARALLEL (VOIDmode,
7191 gen_rtvec (1, const0_rtx)));
7192 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
7196 /* One field is non-constant. Load constant then overwrite
7200 rtx copy = copy_rtx (vals);
7202 /* Load constant part of vector, substitute neighboring value for
7204 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
7205 rs6000_expand_vector_init (target, copy);
7207 /* Insert variable. */
7208 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
7212 /* Construct the vector in memory one field at a time
7213 and load the whole vector. */
7214 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7215 for (i = 0; i < n_elts; i++)
7216 emit_move_insn (adjust_address_nv (mem, inner_mode,
7217 i * GET_MODE_SIZE (inner_mode)),
7218 XVECEXP (vals, 0, i));
7219 emit_move_insn (target, mem);
7222 /* Set field ELT of TARGET to VAL. */
7225 rs6000_expand_vector_set (rtx target, rtx val, int elt)
7227 machine_mode mode = GET_MODE (target);
7228 machine_mode inner_mode = GET_MODE_INNER (mode);
7229 rtx reg = gen_reg_rtx (mode);
7231 int width = GET_MODE_SIZE (inner_mode);
7234 val = force_reg (GET_MODE (val), val);
7236 if (VECTOR_MEM_VSX_P (mode))
7238 rtx insn = NULL_RTX;
7239 rtx elt_rtx = GEN_INT (elt);
7241 if (mode == V2DFmode)
7242 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
7244 else if (mode == V2DImode)
7245 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
7247 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
7249 if (mode == V4SImode)
7250 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
7251 else if (mode == V8HImode)
7252 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
7253 else if (mode == V16QImode)
7254 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
7255 else if (mode == V4SFmode)
7256 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
7266 /* Simplify setting single element vectors like V1TImode. */
7267 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
7269 emit_move_insn (target, gen_lowpart (mode, val));
7273 /* Load single variable value. */
7274 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7275 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
7276 x = gen_rtx_UNSPEC (VOIDmode,
7277 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7278 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7280 gen_rtx_SET (reg, mem),
7283 /* Linear sequence. */
7284 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
7285 for (i = 0; i < 16; ++i)
7286 XVECEXP (mask, 0, i) = GEN_INT (i);
7288 /* Set permute mask to insert element into target. */
7289 for (i = 0; i < width; ++i)
7290 XVECEXP (mask, 0, elt*width + i)
7291 = GEN_INT (i + 0x10);
7292 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
7294 if (BYTES_BIG_ENDIAN)
7295 x = gen_rtx_UNSPEC (mode,
7296 gen_rtvec (3, target, reg,
7297 force_reg (V16QImode, x)),
7301 if (TARGET_P9_VECTOR)
7302 x = gen_rtx_UNSPEC (mode,
7303 gen_rtvec (3, target, reg,
7304 force_reg (V16QImode, x)),
7308 /* Invert selector. We prefer to generate VNAND on P8 so
7309 that future fusion opportunities can kick in, but must
7310 generate VNOR elsewhere. */
7311 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
7312 rtx iorx = (TARGET_P8_VECTOR
7313 ? gen_rtx_IOR (V16QImode, notx, notx)
7314 : gen_rtx_AND (V16QImode, notx, notx));
7315 rtx tmp = gen_reg_rtx (V16QImode);
7316 emit_insn (gen_rtx_SET (tmp, iorx));
7318 /* Permute with operands reversed and adjusted selector. */
7319 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
7324 emit_insn (gen_rtx_SET (target, x));
7327 /* Extract field ELT from VEC into TARGET. */
7330 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
7332 machine_mode mode = GET_MODE (vec);
7333 machine_mode inner_mode = GET_MODE_INNER (mode);
7336 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
7343 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
7344 emit_move_insn (target, gen_lowpart (TImode, vec));
7347 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
7350 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
7353 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
7356 if (TARGET_DIRECT_MOVE_64BIT)
7358 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
7364 if (TARGET_DIRECT_MOVE_64BIT)
7366 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
7372 if (TARGET_DIRECT_MOVE_64BIT)
7374 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
7380 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
7381 && TARGET_DIRECT_MOVE_64BIT)
7383 if (GET_MODE (elt) != DImode)
7385 rtx tmp = gen_reg_rtx (DImode);
7386 convert_move (tmp, elt, 0);
7389 else if (!REG_P (elt))
7390 elt = force_reg (DImode, elt);
7395 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
7399 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
7403 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
7407 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
7411 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
7415 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
7423 gcc_assert (CONST_INT_P (elt));
7425 /* Allocate mode-sized buffer. */
7426 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7428 emit_move_insn (mem, vec);
7430 /* Add offset to field within buffer matching vector element. */
7431 mem = adjust_address_nv (mem, inner_mode,
7432 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
7434 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
7437 /* Helper function to return the register number of a RTX. */
7439 regno_or_subregno (rtx op)
7443 else if (SUBREG_P (op))
7444 return subreg_regno (op);
7449 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7450 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7451 temporary (BASE_TMP) to fixup the address. Return the new memory address
7452 that is valid for reads or writes to a given register (SCALAR_REG). */
7455 rs6000_adjust_vec_address (rtx scalar_reg,
7459 machine_mode scalar_mode)
7461 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7462 rtx addr = XEXP (mem, 0);
7467 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7468 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
7470 /* Calculate what we need to add to the address to get the element
7472 if (CONST_INT_P (element))
7473 element_offset = GEN_INT (INTVAL (element) * scalar_size);
7476 int byte_shift = exact_log2 (scalar_size);
7477 gcc_assert (byte_shift >= 0);
7479 if (byte_shift == 0)
7480 element_offset = element;
7484 if (TARGET_POWERPC64)
7485 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
7487 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
7489 element_offset = base_tmp;
7493 /* Create the new address pointing to the element within the vector. If we
7494 are adding 0, we don't have to change the address. */
7495 if (element_offset == const0_rtx)
7498 /* A simple indirect address can be converted into a reg + offset
7500 else if (REG_P (addr) || SUBREG_P (addr))
7501 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7503 /* Optimize D-FORM addresses with constant offset with a constant element, to
7504 include the element offset in the address directly. */
7505 else if (GET_CODE (addr) == PLUS)
7507 rtx op0 = XEXP (addr, 0);
7508 rtx op1 = XEXP (addr, 1);
7511 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7512 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7514 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7515 rtx offset_rtx = GEN_INT (offset);
7517 if (IN_RANGE (offset, -32768, 32767)
7518 && (scalar_size < 8 || (offset & 0x3) == 0))
7519 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7522 emit_move_insn (base_tmp, offset_rtx);
7523 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7528 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7529 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7531 /* Note, ADDI requires the register being added to be a base
7532 register. If the register was R0, load it up into the temporary
7535 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7537 insn = gen_add3_insn (base_tmp, op1, element_offset);
7538 gcc_assert (insn != NULL_RTX);
7543 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7545 insn = gen_add3_insn (base_tmp, element_offset, op1);
7546 gcc_assert (insn != NULL_RTX);
7552 emit_move_insn (base_tmp, op1);
7553 emit_insn (gen_add2_insn (base_tmp, element_offset));
7556 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7562 emit_move_insn (base_tmp, addr);
7563 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7566 /* If we have a PLUS, we need to see whether the particular register class
7567 allows for D-FORM or X-FORM addressing. */
7568 if (GET_CODE (new_addr) == PLUS)
7570 rtx op1 = XEXP (new_addr, 1);
7571 addr_mask_type addr_mask;
7572 int scalar_regno = regno_or_subregno (scalar_reg);
7574 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7575 if (INT_REGNO_P (scalar_regno))
7576 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7578 else if (FP_REGNO_P (scalar_regno))
7579 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7581 else if (ALTIVEC_REGNO_P (scalar_regno))
7582 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7587 if (REG_P (op1) || SUBREG_P (op1))
7588 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7590 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7593 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7594 valid_addr_p = true;
7597 valid_addr_p = false;
7601 emit_move_insn (base_tmp, new_addr);
7602 new_addr = base_tmp;
7605 return change_address (mem, scalar_mode, new_addr);
7608 /* Split a variable vec_extract operation into the component instructions. */
7611 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7614 machine_mode mode = GET_MODE (src);
7615 machine_mode scalar_mode = GET_MODE (dest);
7616 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7617 int byte_shift = exact_log2 (scalar_size);
7619 gcc_assert (byte_shift >= 0);
7621 /* If we are given a memory address, optimize to load just the element. We
7622 don't have to adjust the vector element number on little endian
7626 gcc_assert (REG_P (tmp_gpr));
7627 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7628 tmp_gpr, scalar_mode));
7632 else if (REG_P (src) || SUBREG_P (src))
7634 int bit_shift = byte_shift + 3;
7636 int dest_regno = regno_or_subregno (dest);
7637 int src_regno = regno_or_subregno (src);
7638 int element_regno = regno_or_subregno (element);
7640 gcc_assert (REG_P (tmp_gpr));
7642 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7643 a general purpose register. */
7644 if (TARGET_P9_VECTOR
7645 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7646 && INT_REGNO_P (dest_regno)
7647 && ALTIVEC_REGNO_P (src_regno)
7648 && INT_REGNO_P (element_regno))
7650 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7651 rtx element_si = gen_rtx_REG (SImode, element_regno);
7653 if (mode == V16QImode)
7654 emit_insn (VECTOR_ELT_ORDER_BIG
7655 ? gen_vextublx (dest_si, element_si, src)
7656 : gen_vextubrx (dest_si, element_si, src));
7658 else if (mode == V8HImode)
7660 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7661 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7662 emit_insn (VECTOR_ELT_ORDER_BIG
7663 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7664 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7670 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7671 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7672 emit_insn (VECTOR_ELT_ORDER_BIG
7673 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7674 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7681 gcc_assert (REG_P (tmp_altivec));
7683 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7684 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7685 will shift the element into the upper position (adding 3 to convert a
7686 byte shift into a bit shift). */
7687 if (scalar_size == 8)
7689 if (!VECTOR_ELT_ORDER_BIG)
7691 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7697 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7699 emit_insn (gen_rtx_SET (tmp_gpr,
7700 gen_rtx_AND (DImode,
7701 gen_rtx_ASHIFT (DImode,
7708 if (!VECTOR_ELT_ORDER_BIG)
7710 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7712 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7713 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7719 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7722 /* Get the value into the lower byte of the Altivec register where VSLO
7724 if (TARGET_P9_VECTOR)
7725 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7726 else if (can_create_pseudo_p ())
7727 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7730 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7731 emit_move_insn (tmp_di, tmp_gpr);
7732 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7735 /* Do the VSLO to get the value into the final location. */
7739 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7743 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7748 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7749 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7750 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7751 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7754 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7762 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7763 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7764 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7765 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7767 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7768 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7769 GEN_INT (64 - (8 * scalar_size))));
7783 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7784 two SImode values. */
7787 rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
7789 const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
7791 if (CONST_INT_P (si1) && CONST_INT_P (si2))
7793 unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
7794 unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
7796 emit_move_insn (dest, GEN_INT (const1 | const2));
7800 /* Put si1 into upper 32-bits of dest. */
7801 if (CONST_INT_P (si1))
7802 emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
7805 /* Generate RLDIC. */
7806 rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
7807 rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
7808 rtx mask_rtx = GEN_INT (mask_32bit << 32);
7809 rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
7810 gcc_assert (!reg_overlap_mentioned_p (dest, si1));
7811 emit_insn (gen_rtx_SET (dest, and_rtx));
7814 /* Put si2 into the temporary. */
7815 gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
7816 if (CONST_INT_P (si2))
7817 emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
7819 emit_insn (gen_zero_extendsidi2 (tmp, si2));
7821 /* Combine the two parts. */
7822 emit_insn (gen_iordi3 (dest, dest, tmp));
7826 /* Split a V4SI initialization. */
7829 rs6000_split_v4si_init (rtx operands[])
7831 rtx dest = operands[0];
7833 /* Destination is a GPR, build up the two DImode parts in place. */
7834 if (REG_P (dest) || SUBREG_P (dest))
7836 int d_regno = regno_or_subregno (dest);
7837 rtx scalar1 = operands[1];
7838 rtx scalar2 = operands[2];
7839 rtx scalar3 = operands[3];
7840 rtx scalar4 = operands[4];
7841 rtx tmp1 = operands[5];
7842 rtx tmp2 = operands[6];
7844 /* Even though we only need one temporary (plus the destination, which
7845 has an early clobber constraint, try to use two temporaries, one for
7846 each double word created. That way the 2nd insn scheduling pass can
7847 rearrange things so the two parts are done in parallel. */
7848 if (BYTES_BIG_ENDIAN)
7850 rtx di_lo = gen_rtx_REG (DImode, d_regno);
7851 rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
7852 rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
7853 rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
7857 rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
7858 rtx di_hi = gen_rtx_REG (DImode, d_regno);
7859 gcc_assert (!VECTOR_ELT_ORDER_BIG);
7860 rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
7861 rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
7870 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7871 selects whether the alignment is abi mandated, optional, or
7872 both abi and optional alignment. */
7875 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7877 if (how != align_opt)
7879 if (TREE_CODE (type) == VECTOR_TYPE)
7881 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
7886 else if (align < 128)
7891 if (how != align_abi)
7893 if (TREE_CODE (type) == ARRAY_TYPE
7894 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7896 if (align < BITS_PER_WORD)
7897 align = BITS_PER_WORD;
7904 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7905 instructions simply ignore the low bits; VSX memory instructions
7906 are aligned to 4 or 8 bytes. */
7909 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7911 return (STRICT_ALIGNMENT
7912 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7913 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7914 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7915 && (int) align < VECTOR_ALIGN (mode)))));
7918 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7921 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7923 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7925 if (computed != 128)
7928 if (!warned && warn_psabi)
7931 inform (input_location,
7932 "the layout of aggregates containing vectors with"
7933 " %d-byte alignment has changed in GCC 5",
7934 computed / BITS_PER_UNIT);
7937 /* In current GCC there is no special case. */
7944 /* AIX increases natural record alignment to doubleword if the first
7945 field is an FP double while the FP fields remain word aligned. */
7948 rs6000_special_round_type_align (tree type, unsigned int computed,
7949 unsigned int specified)
7951 unsigned int align = MAX (computed, specified);
7952 tree field = TYPE_FIELDS (type);
7954 /* Skip all non field decls */
7955 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7956 field = DECL_CHAIN (field);
7958 if (field != NULL && field != type)
7960 type = TREE_TYPE (field);
7961 while (TREE_CODE (type) == ARRAY_TYPE)
7962 type = TREE_TYPE (type);
7964 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7965 align = MAX (align, 64);
7971 /* Darwin increases record alignment to the natural alignment of
7975 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7976 unsigned int specified)
7978 unsigned int align = MAX (computed, specified);
7980 if (TYPE_PACKED (type))
7983 /* Find the first field, looking down into aggregates. */
7985 tree field = TYPE_FIELDS (type);
7986 /* Skip all non field decls */
7987 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7988 field = DECL_CHAIN (field);
7991 /* A packed field does not contribute any extra alignment. */
7992 if (DECL_PACKED (field))
7994 type = TREE_TYPE (field);
7995 while (TREE_CODE (type) == ARRAY_TYPE)
7996 type = TREE_TYPE (type);
7997 } while (AGGREGATE_TYPE_P (type));
7999 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
8000 align = MAX (align, TYPE_ALIGN (type));
8005 /* Return 1 for an operand in small memory on V.4/eabi. */
8008 small_data_operand (rtx op ATTRIBUTE_UNUSED,
8009 machine_mode mode ATTRIBUTE_UNUSED)
8014 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
8017 if (DEFAULT_ABI != ABI_V4)
8020 if (GET_CODE (op) == SYMBOL_REF)
8023 else if (GET_CODE (op) != CONST
8024 || GET_CODE (XEXP (op, 0)) != PLUS
8025 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
8026 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
8031 rtx sum = XEXP (op, 0);
8032 HOST_WIDE_INT summand;
8034 /* We have to be careful here, because it is the referenced address
8035 that must be 32k from _SDA_BASE_, not just the symbol. */
8036 summand = INTVAL (XEXP (sum, 1));
8037 if (summand < 0 || summand > g_switch_value)
8040 sym_ref = XEXP (sum, 0);
8043 return SYMBOL_REF_SMALL_P (sym_ref);
8049 /* Return true if either operand is a general purpose register. */
8052 gpr_or_gpr_p (rtx op0, rtx op1)
8054 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
8055 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
8058 /* Return true if this is a move direct operation between GPR registers and
8059 floating point/VSX registers. */
8062 direct_move_p (rtx op0, rtx op1)
8066 if (!REG_P (op0) || !REG_P (op1))
8069 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
8072 regno0 = REGNO (op0);
8073 regno1 = REGNO (op1);
8074 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
8077 if (INT_REGNO_P (regno0))
8078 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
8080 else if (INT_REGNO_P (regno1))
8082 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
8085 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
8092 /* Return true if the OFFSET is valid for the quad address instructions that
8093 use d-form (register + offset) addressing. */
8096 quad_address_offset_p (HOST_WIDE_INT offset)
8098 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
8101 /* Return true if the ADDR is an acceptable address for a quad memory
8102 operation of mode MODE (either LQ/STQ for general purpose registers, or
8103 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
8104 is intended for LQ/STQ. If it is false, the address is intended for the ISA
8105 3.0 LXV/STXV instruction. */
8108 quad_address_p (rtx addr, machine_mode mode, bool strict)
8112 if (GET_MODE_SIZE (mode) != 16)
8115 if (legitimate_indirect_address_p (addr, strict))
8118 if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
8121 if (GET_CODE (addr) != PLUS)
8124 op0 = XEXP (addr, 0);
8125 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
8128 op1 = XEXP (addr, 1);
8129 if (!CONST_INT_P (op1))
8132 return quad_address_offset_p (INTVAL (op1));
8135 /* Return true if this is a load or store quad operation. This function does
8136 not handle the atomic quad memory instructions. */
8139 quad_load_store_p (rtx op0, rtx op1)
8143 if (!TARGET_QUAD_MEMORY)
8146 else if (REG_P (op0) && MEM_P (op1))
8147 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
8148 && quad_memory_operand (op1, GET_MODE (op1))
8149 && !reg_overlap_mentioned_p (op0, op1));
8151 else if (MEM_P (op0) && REG_P (op1))
8152 ret = (quad_memory_operand (op0, GET_MODE (op0))
8153 && quad_int_reg_operand (op1, GET_MODE (op1)));
8158 if (TARGET_DEBUG_ADDR)
8160 fprintf (stderr, "\n========== quad_load_store, return %s\n",
8161 ret ? "true" : "false");
8162 debug_rtx (gen_rtx_SET (op0, op1));
8168 /* Given an address, return a constant offset term if one exists. */
8171 address_offset (rtx op)
8173 if (GET_CODE (op) == PRE_INC
8174 || GET_CODE (op) == PRE_DEC)
8176 else if (GET_CODE (op) == PRE_MODIFY
8177 || GET_CODE (op) == LO_SUM)
8180 if (GET_CODE (op) == CONST)
8183 if (GET_CODE (op) == PLUS)
8186 if (CONST_INT_P (op))
8192 /* Return true if the MEM operand is a memory operand suitable for use
8193 with a (full width, possibly multiple) gpr load/store. On
8194 powerpc64 this means the offset must be divisible by 4.
8195 Implements 'Y' constraint.
8197 Accept direct, indexed, offset, lo_sum and tocref. Since this is
8198 a constraint function we know the operand has satisfied a suitable
8199 memory predicate. Also accept some odd rtl generated by reload
8200 (see rs6000_legitimize_reload_address for various forms). It is
8201 important that reload rtl be accepted by appropriate constraints
8202 but not by the operand predicate.
8204 Offsetting a lo_sum should not be allowed, except where we know by
8205 alignment that a 32k boundary is not crossed, but see the ???
8206 comment in rs6000_legitimize_reload_address. Note that by
8207 "offsetting" here we mean a further offset to access parts of the
8208 MEM. It's fine to have a lo_sum where the inner address is offset
8209 from a sym, since the same sym+offset will appear in the high part
8210 of the address calculation. */
8213 mem_operand_gpr (rtx op, machine_mode mode)
8215 unsigned HOST_WIDE_INT offset;
8217 rtx addr = XEXP (op, 0);
8219 op = address_offset (addr);
8223 offset = INTVAL (op);
8224 if (TARGET_POWERPC64 && (offset & 3) != 0)
8227 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8231 if (GET_CODE (addr) == LO_SUM)
8232 /* For lo_sum addresses, we must allow any offset except one that
8233 causes a wrap, so test only the low 16 bits. */
8234 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8236 return offset + 0x8000 < 0x10000u - extra;
8239 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8240 enforce an offset divisible by 4 even for 32-bit. */
8243 mem_operand_ds_form (rtx op, machine_mode mode)
8245 unsigned HOST_WIDE_INT offset;
8247 rtx addr = XEXP (op, 0);
8249 if (!offsettable_address_p (false, mode, addr))
8252 op = address_offset (addr);
8256 offset = INTVAL (op);
8257 if ((offset & 3) != 0)
8260 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8264 if (GET_CODE (addr) == LO_SUM)
8265 /* For lo_sum addresses, we must allow any offset except one that
8266 causes a wrap, so test only the low 16 bits. */
8267 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8269 return offset + 0x8000 < 0x10000u - extra;
8272 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8275 reg_offset_addressing_ok_p (machine_mode mode)
8289 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8290 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8291 a vector mode, if we want to use the VSX registers to move it around,
8292 we need to restrict ourselves to reg+reg addressing. Similarly for
8293 IEEE 128-bit floating point that is passed in a single vector
8295 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
8296 return mode_supports_vsx_dform_quad (mode);
8301 /* Paired vector modes. Only reg+reg addressing is valid. */
8302 if (TARGET_PAIRED_FLOAT)
8307 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8308 addressing for the LFIWZX and STFIWX instructions. */
8309 if (TARGET_NO_SDMODE_STACK)
8321 virtual_stack_registers_memory_p (rtx op)
8325 if (GET_CODE (op) == REG)
8326 regnum = REGNO (op);
8328 else if (GET_CODE (op) == PLUS
8329 && GET_CODE (XEXP (op, 0)) == REG
8330 && GET_CODE (XEXP (op, 1)) == CONST_INT)
8331 regnum = REGNO (XEXP (op, 0));
8336 return (regnum >= FIRST_VIRTUAL_REGISTER
8337 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
8340 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8341 is known to not straddle a 32k boundary. This function is used
8342 to determine whether -mcmodel=medium code can use TOC pointer
8343 relative addressing for OP. This means the alignment of the TOC
8344 pointer must also be taken into account, and unfortunately that is
8347 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8348 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8352 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
8356 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
8358 if (GET_CODE (op) != SYMBOL_REF)
8361 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8363 if (mode_supports_vsx_dform_quad (mode))
8366 dsize = GET_MODE_SIZE (mode);
8367 decl = SYMBOL_REF_DECL (op);
8373 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8374 replacing memory addresses with an anchor plus offset. We
8375 could find the decl by rummaging around in the block->objects
8376 VEC for the given offset but that seems like too much work. */
8377 dalign = BITS_PER_UNIT;
8378 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
8379 && SYMBOL_REF_ANCHOR_P (op)
8380 && SYMBOL_REF_BLOCK (op) != NULL)
8382 struct object_block *block = SYMBOL_REF_BLOCK (op);
8384 dalign = block->alignment;
8385 offset += SYMBOL_REF_BLOCK_OFFSET (op);
8387 else if (CONSTANT_POOL_ADDRESS_P (op))
8389 /* It would be nice to have get_pool_align().. */
8390 machine_mode cmode = get_pool_mode (op);
8392 dalign = GET_MODE_ALIGNMENT (cmode);
8395 else if (DECL_P (decl))
8397 dalign = DECL_ALIGN (decl);
8401 /* Allow BLKmode when the entire object is known to not
8402 cross a 32k boundary. */
8403 if (!DECL_SIZE_UNIT (decl))
8406 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
8409 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
8413 dalign /= BITS_PER_UNIT;
8414 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8415 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8416 return dalign >= dsize;
8422 /* Find how many bits of the alignment we know for this access. */
8423 dalign /= BITS_PER_UNIT;
8424 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8425 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8427 lsb = offset & -offset;
8431 return dalign >= dsize;
8435 constant_pool_expr_p (rtx op)
8439 split_const (op, &base, &offset);
8440 return (GET_CODE (base) == SYMBOL_REF
8441 && CONSTANT_POOL_ADDRESS_P (base)
8442 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
8445 /* These are only used to pass through from print_operand/print_operand_address
8446 to rs6000_output_addr_const_extra over the intervening function
8447 output_addr_const which is not target code. */
8448 static const_rtx tocrel_base_oac, tocrel_offset_oac;
8450 /* Return true if OP is a toc pointer relative address (the output
8451 of create_TOC_reference). If STRICT, do not match non-split
8452 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8453 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8454 TOCREL_OFFSET_RET respectively. */
8457 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
8458 const_rtx *tocrel_offset_ret)
8463 if (TARGET_CMODEL != CMODEL_SMALL)
8465 /* When strict ensure we have everything tidy. */
8467 && !(GET_CODE (op) == LO_SUM
8468 && REG_P (XEXP (op, 0))
8469 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
8472 /* When not strict, allow non-split TOC addresses and also allow
8473 (lo_sum (high ..)) TOC addresses created during reload. */
8474 if (GET_CODE (op) == LO_SUM)
8478 const_rtx tocrel_base = op;
8479 const_rtx tocrel_offset = const0_rtx;
8481 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
8483 tocrel_base = XEXP (op, 0);
8484 tocrel_offset = XEXP (op, 1);
8487 if (tocrel_base_ret)
8488 *tocrel_base_ret = tocrel_base;
8489 if (tocrel_offset_ret)
8490 *tocrel_offset_ret = tocrel_offset;
8492 return (GET_CODE (tocrel_base) == UNSPEC
8493 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
8496 /* Return true if X is a constant pool address, and also for cmodel=medium
8497 if X is a toc-relative address known to be offsettable within MODE. */
8500 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
8503 const_rtx tocrel_base, tocrel_offset;
8504 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
8505 && (TARGET_CMODEL != CMODEL_MEDIUM
8506 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
8508 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
8509 INTVAL (tocrel_offset), mode)));
8513 legitimate_small_data_p (machine_mode mode, rtx x)
8515 return (DEFAULT_ABI == ABI_V4
8516 && !flag_pic && !TARGET_TOC
8517 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
8518 && small_data_operand (x, mode));
8522 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
8523 bool strict, bool worst_case)
8525 unsigned HOST_WIDE_INT offset;
8528 if (GET_CODE (x) != PLUS)
8530 if (!REG_P (XEXP (x, 0)))
8532 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8534 if (mode_supports_vsx_dform_quad (mode))
8535 return quad_address_p (x, mode, strict);
8536 if (!reg_offset_addressing_ok_p (mode))
8537 return virtual_stack_registers_memory_p (x);
8538 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
8540 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8543 offset = INTVAL (XEXP (x, 1));
8549 /* Paired single modes: offset addressing isn't valid. */
8555 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8557 if (VECTOR_MEM_VSX_P (mode))
8562 if (!TARGET_POWERPC64)
8564 else if (offset & 3)
8577 if (!TARGET_POWERPC64)
8579 else if (offset & 3)
8588 return offset < 0x10000 - extra;
8592 legitimate_indexed_address_p (rtx x, int strict)
8596 if (GET_CODE (x) != PLUS)
8602 return (REG_P (op0) && REG_P (op1)
8603 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8604 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8605 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8606 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8610 avoiding_indexed_address_p (machine_mode mode)
8612 /* Avoid indexed addressing for modes that have non-indexed
8613 load/store instruction forms. */
8614 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8618 legitimate_indirect_address_p (rtx x, int strict)
8620 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8624 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8626 if (!TARGET_MACHO || !flag_pic
8627 || mode != SImode || GET_CODE (x) != MEM)
8631 if (GET_CODE (x) != LO_SUM)
8633 if (GET_CODE (XEXP (x, 0)) != REG)
8635 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8639 return CONSTANT_P (x);
8643 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8645 if (GET_CODE (x) != LO_SUM)
8647 if (GET_CODE (XEXP (x, 0)) != REG)
8649 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8651 /* quad word addresses are restricted, and we can't use LO_SUM. */
8652 if (mode_supports_vsx_dform_quad (mode))
8656 if (TARGET_ELF || TARGET_MACHO)
8660 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8662 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8663 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8664 recognizes some LO_SUM addresses as valid although this
8665 function says opposite. In most cases, LRA through different
8666 transformations can generate correct code for address reloads.
8667 It can not manage only some LO_SUM cases. So we need to add
8668 code analogous to one in rs6000_legitimize_reload_address for
8669 LOW_SUM here saying that some addresses are still valid. */
8670 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8671 && small_toc_ref (x, VOIDmode));
8672 if (TARGET_TOC && ! large_toc_ok)
8674 if (GET_MODE_NUNITS (mode) != 1)
8676 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8677 && !(/* ??? Assume floating point reg based on mode? */
8678 TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
8679 && (mode == DFmode || mode == DDmode)))
8682 return CONSTANT_P (x) || large_toc_ok;
8689 /* Try machine-dependent ways of modifying an illegitimate address
8690 to be legitimate. If we find one, return the new, valid address.
8691 This is used from only one place: `memory_address' in explow.c.
8693 OLDX is the address as it was before break_out_memory_refs was
8694 called. In some cases it is useful to look at this to decide what
8697 It is always safe for this function to do nothing. It exists to
8698 recognize opportunities to optimize the output.
8700 On RS/6000, first check for the sum of a register with a constant
8701 integer that is out of range. If so, generate code to add the
8702 constant with the low-order 16 bits masked to the register and force
8703 this result into another register (this can be done with `cau').
8704 Then generate an address of REG+(CONST&0xffff), allowing for the
8705 possibility of bit 16 being a one.
8707 Then check for the sum of a register and something not constant, try to
8708 load the other things into a register and return the sum. */
8711 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8716 if (!reg_offset_addressing_ok_p (mode)
8717 || mode_supports_vsx_dform_quad (mode))
8719 if (virtual_stack_registers_memory_p (x))
8722 /* In theory we should not be seeing addresses of the form reg+0,
8723 but just in case it is generated, optimize it away. */
8724 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8725 return force_reg (Pmode, XEXP (x, 0));
8727 /* For TImode with load/store quad, restrict addresses to just a single
8728 pointer, so it works with both GPRs and VSX registers. */
8729 /* Make sure both operands are registers. */
8730 else if (GET_CODE (x) == PLUS
8731 && (mode != TImode || !TARGET_VSX))
8732 return gen_rtx_PLUS (Pmode,
8733 force_reg (Pmode, XEXP (x, 0)),
8734 force_reg (Pmode, XEXP (x, 1)));
8736 return force_reg (Pmode, x);
8738 if (GET_CODE (x) == SYMBOL_REF)
8740 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8742 return rs6000_legitimize_tls_address (x, model);
8754 /* As in legitimate_offset_address_p we do not assume
8755 worst-case. The mode here is just a hint as to the registers
8756 used. A TImode is usually in gprs, but may actually be in
8757 fprs. Leave worst-case scenario for reload to handle via
8758 insn constraints. PTImode is only GPRs. */
8765 if (GET_CODE (x) == PLUS
8766 && GET_CODE (XEXP (x, 0)) == REG
8767 && GET_CODE (XEXP (x, 1)) == CONST_INT
8768 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8770 && !PAIRED_VECTOR_MODE (mode))
8772 HOST_WIDE_INT high_int, low_int;
8774 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8775 if (low_int >= 0x8000 - extra)
8777 high_int = INTVAL (XEXP (x, 1)) - low_int;
8778 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8779 GEN_INT (high_int)), 0);
8780 return plus_constant (Pmode, sum, low_int);
8782 else if (GET_CODE (x) == PLUS
8783 && GET_CODE (XEXP (x, 0)) == REG
8784 && GET_CODE (XEXP (x, 1)) != CONST_INT
8785 && GET_MODE_NUNITS (mode) == 1
8786 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8787 || (/* ??? Assume floating point reg based on mode? */
8788 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8789 && (mode == DFmode || mode == DDmode)))
8790 && !avoiding_indexed_address_p (mode))
8792 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8793 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8795 else if (PAIRED_VECTOR_MODE (mode))
8799 /* We accept [reg + reg]. */
8801 if (GET_CODE (x) == PLUS)
8803 rtx op1 = XEXP (x, 0);
8804 rtx op2 = XEXP (x, 1);
8807 op1 = force_reg (Pmode, op1);
8808 op2 = force_reg (Pmode, op2);
8810 /* We can't always do [reg + reg] for these, because [reg +
8811 reg + offset] is not a legitimate addressing mode. */
8812 y = gen_rtx_PLUS (Pmode, op1, op2);
8814 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
8815 return force_reg (Pmode, y);
8820 return force_reg (Pmode, x);
8822 else if ((TARGET_ELF
8824 || !MACHO_DYNAMIC_NO_PIC_P
8830 && GET_CODE (x) != CONST_INT
8831 && GET_CODE (x) != CONST_WIDE_INT
8832 && GET_CODE (x) != CONST_DOUBLE
8834 && GET_MODE_NUNITS (mode) == 1
8835 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8836 || (/* ??? Assume floating point reg based on mode? */
8837 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8838 && (mode == DFmode || mode == DDmode))))
8840 rtx reg = gen_reg_rtx (Pmode);
8842 emit_insn (gen_elf_high (reg, x));
8844 emit_insn (gen_macho_high (reg, x));
8845 return gen_rtx_LO_SUM (Pmode, reg, x);
8848 && GET_CODE (x) == SYMBOL_REF
8849 && constant_pool_expr_p (x)
8850 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8851 return create_TOC_reference (x, NULL_RTX);
8856 /* Debug version of rs6000_legitimize_address. */
8858 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8864 ret = rs6000_legitimize_address (x, oldx, mode);
8865 insns = get_insns ();
8871 "\nrs6000_legitimize_address: mode %s, old code %s, "
8872 "new code %s, modified\n",
8873 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8874 GET_RTX_NAME (GET_CODE (ret)));
8876 fprintf (stderr, "Original address:\n");
8879 fprintf (stderr, "oldx:\n");
8882 fprintf (stderr, "New address:\n");
8887 fprintf (stderr, "Insns added:\n");
8888 debug_rtx_list (insns, 20);
8894 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8895 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8906 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8907 We need to emit DTP-relative relocations. */
8909 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8911 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8916 fputs ("\t.long\t", file);
8919 fputs (DOUBLE_INT_ASM_OP, file);
8924 output_addr_const (file, x);
8926 fputs ("@dtprel+0x8000", file);
8927 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8929 switch (SYMBOL_REF_TLS_MODEL (x))
8933 case TLS_MODEL_LOCAL_EXEC:
8934 fputs ("@le", file);
8936 case TLS_MODEL_INITIAL_EXEC:
8937 fputs ("@ie", file);
8939 case TLS_MODEL_GLOBAL_DYNAMIC:
8940 case TLS_MODEL_LOCAL_DYNAMIC:
8949 /* Return true if X is a symbol that refers to real (rather than emulated)
8953 rs6000_real_tls_symbol_ref_p (rtx x)
8955 return (GET_CODE (x) == SYMBOL_REF
8956 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8959 /* In the name of slightly smaller debug output, and to cater to
8960 general assembler lossage, recognize various UNSPEC sequences
8961 and turn them back into a direct symbol reference. */
8964 rs6000_delegitimize_address (rtx orig_x)
8968 orig_x = delegitimize_mem_from_attrs (orig_x);
8974 if (TARGET_CMODEL != CMODEL_SMALL
8975 && GET_CODE (y) == LO_SUM)
8979 if (GET_CODE (y) == PLUS
8980 && GET_MODE (y) == Pmode
8981 && CONST_INT_P (XEXP (y, 1)))
8983 offset = XEXP (y, 1);
8987 if (GET_CODE (y) == UNSPEC
8988 && XINT (y, 1) == UNSPEC_TOCREL)
8990 y = XVECEXP (y, 0, 0);
8993 /* Do not associate thread-local symbols with the original
8994 constant pool symbol. */
8996 && GET_CODE (y) == SYMBOL_REF
8997 && CONSTANT_POOL_ADDRESS_P (y)
8998 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
9002 if (offset != NULL_RTX)
9003 y = gen_rtx_PLUS (Pmode, y, offset);
9004 if (!MEM_P (orig_x))
9007 return replace_equiv_address_nv (orig_x, y);
9011 && GET_CODE (orig_x) == LO_SUM
9012 && GET_CODE (XEXP (orig_x, 1)) == CONST)
9014 y = XEXP (XEXP (orig_x, 1), 0);
9015 if (GET_CODE (y) == UNSPEC
9016 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
9017 return XVECEXP (y, 0, 0);
9023 /* Return true if X shouldn't be emitted into the debug info.
9024 The linker doesn't like .toc section references from
9025 .debug_* sections, so reject .toc section symbols. */
9028 rs6000_const_not_ok_for_debug_p (rtx x)
9030 if (GET_CODE (x) == UNSPEC)
9032 if (GET_CODE (x) == SYMBOL_REF
9033 && CONSTANT_POOL_ADDRESS_P (x))
9035 rtx c = get_pool_constant (x);
9036 machine_mode cmode = get_pool_mode (x);
9037 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
9045 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
9048 rs6000_legitimate_combined_insn (rtx_insn *insn)
9050 int icode = INSN_CODE (insn);
9052 /* Reject creating doloop insns. Combine should not be allowed
9053 to create these for a number of reasons:
9054 1) In a nested loop, if combine creates one of these in an
9055 outer loop and the register allocator happens to allocate ctr
9056 to the outer loop insn, then the inner loop can't use ctr.
9057 Inner loops ought to be more highly optimized.
9058 2) Combine often wants to create one of these from what was
9059 originally a three insn sequence, first combining the three
9060 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
9061 allocated ctr, the splitter takes use back to the three insn
9062 sequence. It's better to stop combine at the two insn
9064 3) Faced with not being able to allocate ctr for ctrsi/crtdi
9065 insns, the register allocator sometimes uses floating point
9066 or vector registers for the pseudo. Since ctrsi/ctrdi is a
9067 jump insn and output reloads are not implemented for jumps,
9068 the ctrsi/ctrdi splitters need to handle all possible cases.
9069 That's a pain, and it gets to be seriously difficult when a
9070 splitter that runs after reload needs memory to transfer from
9071 a gpr to fpr. See PR70098 and PR71763 which are not fixed
9072 for the difficult case. It's better to not create problems
9073 in the first place. */
9074 if (icode != CODE_FOR_nothing
9075 && (icode == CODE_FOR_ctrsi_internal1
9076 || icode == CODE_FOR_ctrdi_internal1
9077 || icode == CODE_FOR_ctrsi_internal2
9078 || icode == CODE_FOR_ctrdi_internal2))
9084 /* Construct the SYMBOL_REF for the tls_get_addr function. */
9086 static GTY(()) rtx rs6000_tls_symbol;
9088 rs6000_tls_get_addr (void)
9090 if (!rs6000_tls_symbol)
9091 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
9093 return rs6000_tls_symbol;
9096 /* Construct the SYMBOL_REF for TLS GOT references. */
9098 static GTY(()) rtx rs6000_got_symbol;
9100 rs6000_got_sym (void)
9102 if (!rs6000_got_symbol)
9104 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9105 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
9106 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
9109 return rs6000_got_symbol;
9112 /* AIX Thread-Local Address support. */
9115 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
9117 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
9121 name = XSTR (addr, 0);
9122 /* Append TLS CSECT qualifier, unless the symbol already is qualified
9123 or the symbol will be in TLS private data section. */
9124 if (name[strlen (name) - 1] != ']'
9125 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
9126 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
9128 tlsname = XALLOCAVEC (char, strlen (name) + 4);
9129 strcpy (tlsname, name);
9131 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
9132 tlsaddr = copy_rtx (addr);
9133 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
9138 /* Place addr into TOC constant pool. */
9139 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
9141 /* Output the TOC entry and create the MEM referencing the value. */
9142 if (constant_pool_expr_p (XEXP (sym, 0))
9143 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
9145 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
9146 mem = gen_const_mem (Pmode, tocref);
9147 set_mem_alias_set (mem, get_TOC_alias_set ());
9152 /* Use global-dynamic for local-dynamic. */
9153 if (model == TLS_MODEL_GLOBAL_DYNAMIC
9154 || model == TLS_MODEL_LOCAL_DYNAMIC)
9156 /* Create new TOC reference for @m symbol. */
9157 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
9158 tlsname = XALLOCAVEC (char, strlen (name) + 1);
9159 strcpy (tlsname, "*LCM");
9160 strcat (tlsname, name + 3);
9161 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
9162 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
9163 tocref = create_TOC_reference (modaddr, NULL_RTX);
9164 rtx modmem = gen_const_mem (Pmode, tocref);
9165 set_mem_alias_set (modmem, get_TOC_alias_set ());
9167 rtx modreg = gen_reg_rtx (Pmode);
9168 emit_insn (gen_rtx_SET (modreg, modmem));
9170 tmpreg = gen_reg_rtx (Pmode);
9171 emit_insn (gen_rtx_SET (tmpreg, mem));
9173 dest = gen_reg_rtx (Pmode);
9175 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
9177 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
9180 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
9181 else if (TARGET_32BIT)
9183 tlsreg = gen_reg_rtx (SImode);
9184 emit_insn (gen_tls_get_tpointer (tlsreg));
9187 tlsreg = gen_rtx_REG (DImode, 13);
9189 /* Load the TOC value into temporary register. */
9190 tmpreg = gen_reg_rtx (Pmode);
9191 emit_insn (gen_rtx_SET (tmpreg, mem));
9192 set_unique_reg_note (get_last_insn (), REG_EQUAL,
9193 gen_rtx_MINUS (Pmode, addr, tlsreg));
9195 /* Add TOC symbol value to TLS pointer. */
9196 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
9201 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
9202 this (thread-local) address. */
9205 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
9210 return rs6000_legitimize_tls_address_aix (addr, model);
9212 dest = gen_reg_rtx (Pmode);
9213 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
9219 tlsreg = gen_rtx_REG (Pmode, 13);
9220 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
9224 tlsreg = gen_rtx_REG (Pmode, 2);
9225 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
9229 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
9233 tmp = gen_reg_rtx (Pmode);
9236 tlsreg = gen_rtx_REG (Pmode, 13);
9237 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
9241 tlsreg = gen_rtx_REG (Pmode, 2);
9242 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
9246 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
9248 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
9253 rtx r3, got, tga, tmp1, tmp2, call_insn;
9255 /* We currently use relocations like @got@tlsgd for tls, which
9256 means the linker will handle allocation of tls entries, placing
9257 them in the .got section. So use a pointer to the .got section,
9258 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9259 or to secondary GOT sections used by 32-bit -fPIC. */
9261 got = gen_rtx_REG (Pmode, 2);
9265 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9268 rtx gsym = rs6000_got_sym ();
9269 got = gen_reg_rtx (Pmode);
9271 rs6000_emit_move (got, gsym, Pmode);
9276 tmp1 = gen_reg_rtx (Pmode);
9277 tmp2 = gen_reg_rtx (Pmode);
9278 mem = gen_const_mem (Pmode, tmp1);
9279 lab = gen_label_rtx ();
9280 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
9281 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
9282 if (TARGET_LINK_STACK)
9283 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
9284 emit_move_insn (tmp2, mem);
9285 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
9286 set_unique_reg_note (last, REG_EQUAL, gsym);
9291 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
9293 tga = rs6000_tls_get_addr ();
9294 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
9297 r3 = gen_rtx_REG (Pmode, 3);
9298 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9301 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
9303 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
9305 else if (DEFAULT_ABI == ABI_V4)
9306 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
9309 call_insn = last_call_insn ();
9310 PATTERN (call_insn) = insn;
9311 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9312 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9313 pic_offset_table_rtx);
9315 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
9317 tga = rs6000_tls_get_addr ();
9318 tmp1 = gen_reg_rtx (Pmode);
9319 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
9322 r3 = gen_rtx_REG (Pmode, 3);
9323 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9326 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
9328 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
9330 else if (DEFAULT_ABI == ABI_V4)
9331 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
9334 call_insn = last_call_insn ();
9335 PATTERN (call_insn) = insn;
9336 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9337 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9338 pic_offset_table_rtx);
9340 if (rs6000_tls_size == 16)
9343 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
9345 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
9347 else if (rs6000_tls_size == 32)
9349 tmp2 = gen_reg_rtx (Pmode);
9351 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
9353 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
9356 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
9358 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
9362 tmp2 = gen_reg_rtx (Pmode);
9364 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
9366 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
9368 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
9374 /* IE, or 64-bit offset LE. */
9375 tmp2 = gen_reg_rtx (Pmode);
9377 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
9379 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
9382 insn = gen_tls_tls_64 (dest, tmp2, addr);
9384 insn = gen_tls_tls_32 (dest, tmp2, addr);
9392 /* Only create the global variable for the stack protect guard if we are using
9393 the global flavor of that guard. */
9395 rs6000_init_stack_protect_guard (void)
9397 if (rs6000_stack_protector_guard == SSP_GLOBAL)
9398 return default_stack_protect_guard ();
9403 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9406 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
9408 if (GET_CODE (x) == HIGH
9409 && GET_CODE (XEXP (x, 0)) == UNSPEC)
9412 /* A TLS symbol in the TOC cannot contain a sum. */
9413 if (GET_CODE (x) == CONST
9414 && GET_CODE (XEXP (x, 0)) == PLUS
9415 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9416 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
9419 /* Do not place an ELF TLS symbol in the constant pool. */
9420 return TARGET_ELF && tls_referenced_p (x);
9423 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9424 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9425 can be addressed relative to the toc pointer. */
9428 use_toc_relative_ref (rtx sym, machine_mode mode)
9430 return ((constant_pool_expr_p (sym)
9431 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
9432 get_pool_mode (sym)))
9433 || (TARGET_CMODEL == CMODEL_MEDIUM
9434 && SYMBOL_REF_LOCAL_P (sym)
9435 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
9438 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9439 replace the input X, or the original X if no replacement is called for.
9440 The output parameter *WIN is 1 if the calling macro should goto WIN,
9443 For RS/6000, we wish to handle large displacements off a base
9444 register by splitting the addend across an addiu/addis and the mem insn.
9445 This cuts number of extra insns needed from 3 to 1.
9447 On Darwin, we use this to generate code for floating point constants.
9448 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9449 The Darwin code is inside #if TARGET_MACHO because only then are the
9450 machopic_* functions defined. */
9452 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
9453 int opnum, int type,
9454 int ind_levels ATTRIBUTE_UNUSED, int *win)
9456 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9457 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9459 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9460 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9463 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
9464 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
9465 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
9466 && TARGET_P9_VECTOR)
9467 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
9468 && TARGET_P9_VECTOR)))
9469 reg_offset_p = false;
9471 /* We must recognize output that we have already generated ourselves. */
9472 if (GET_CODE (x) == PLUS
9473 && GET_CODE (XEXP (x, 0)) == PLUS
9474 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9475 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9476 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9478 if (TARGET_DEBUG_ADDR)
9480 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
9483 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9484 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9485 opnum, (enum reload_type) type);
9490 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9491 if (GET_CODE (x) == LO_SUM
9492 && GET_CODE (XEXP (x, 0)) == HIGH)
9494 if (TARGET_DEBUG_ADDR)
9496 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
9499 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9500 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9501 opnum, (enum reload_type) type);
9507 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
9508 && GET_CODE (x) == LO_SUM
9509 && GET_CODE (XEXP (x, 0)) == PLUS
9510 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
9511 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
9512 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
9513 && machopic_operand_p (XEXP (x, 1)))
9515 /* Result of previous invocation of this function on Darwin
9516 floating point constant. */
9517 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9518 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9519 opnum, (enum reload_type) type);
9525 if (TARGET_CMODEL != CMODEL_SMALL
9528 && small_toc_ref (x, VOIDmode))
9530 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
9531 x = gen_rtx_LO_SUM (Pmode, hi, x);
9532 if (TARGET_DEBUG_ADDR)
9534 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
9537 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9538 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9539 opnum, (enum reload_type) type);
9544 if (GET_CODE (x) == PLUS
9545 && REG_P (XEXP (x, 0))
9546 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
9547 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
9548 && CONST_INT_P (XEXP (x, 1))
9550 && !PAIRED_VECTOR_MODE (mode)
9551 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
9553 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
9554 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
9556 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9558 /* Check for 32-bit overflow or quad addresses with one of the
9559 four least significant bits set. */
9560 if (high + low != val
9561 || (quad_offset_p && (low & 0xf)))
9567 /* Reload the high part into a base reg; leave the low part
9568 in the mem directly. */
9570 x = gen_rtx_PLUS (GET_MODE (x),
9571 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
9575 if (TARGET_DEBUG_ADDR)
9577 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
9580 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9581 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9582 opnum, (enum reload_type) type);
9587 if (GET_CODE (x) == SYMBOL_REF
9590 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
9591 && !PAIRED_VECTOR_MODE (mode)
9593 && DEFAULT_ABI == ABI_DARWIN
9594 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
9595 && machopic_symbol_defined_p (x)
9597 && DEFAULT_ABI == ABI_V4
9600 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9601 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9603 ??? Assume floating point reg based on mode? This assumption is
9604 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9605 where reload ends up doing a DFmode load of a constant from
9606 mem using two gprs. Unfortunately, at this point reload
9607 hasn't yet selected regs so poking around in reload data
9608 won't help and even if we could figure out the regs reliably,
9609 we'd still want to allow this transformation when the mem is
9610 naturally aligned. Since we say the address is good here, we
9611 can't disable offsets from LO_SUMs in mem_operand_gpr.
9612 FIXME: Allow offset from lo_sum for other modes too, when
9613 mem is sufficiently aligned.
9615 Also disallow this if the type can go in VMX/Altivec registers, since
9616 those registers do not have d-form (reg+offset) address modes. */
9617 && !reg_addr[mode].scalar_in_vmx_p
9622 && (mode != TImode || !TARGET_VSX)
9624 && (mode != DImode || TARGET_POWERPC64)
9625 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
9626 || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
9631 rtx offset = machopic_gen_offset (x);
9632 x = gen_rtx_LO_SUM (GET_MODE (x),
9633 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9634 gen_rtx_HIGH (Pmode, offset)), offset);
9638 x = gen_rtx_LO_SUM (GET_MODE (x),
9639 gen_rtx_HIGH (Pmode, x), x);
9641 if (TARGET_DEBUG_ADDR)
9643 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9646 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9647 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9648 opnum, (enum reload_type) type);
9653 /* Reload an offset address wrapped by an AND that represents the
9654 masking of the lower bits. Strip the outer AND and let reload
9655 convert the offset address into an indirect address. For VSX,
9656 force reload to create the address with an AND in a separate
9657 register, because we can't guarantee an altivec register will
9659 if (VECTOR_MEM_ALTIVEC_P (mode)
9660 && GET_CODE (x) == AND
9661 && GET_CODE (XEXP (x, 0)) == PLUS
9662 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9663 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9664 && GET_CODE (XEXP (x, 1)) == CONST_INT
9665 && INTVAL (XEXP (x, 1)) == -16)
9675 && GET_CODE (x) == SYMBOL_REF
9676 && use_toc_relative_ref (x, mode))
9678 x = create_TOC_reference (x, NULL_RTX);
9679 if (TARGET_CMODEL != CMODEL_SMALL)
9681 if (TARGET_DEBUG_ADDR)
9683 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9686 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9687 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9688 opnum, (enum reload_type) type);
9697 /* Debug version of rs6000_legitimize_reload_address. */
9699 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9700 int opnum, int type,
9701 int ind_levels, int *win)
9703 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9706 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9707 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9708 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9712 fprintf (stderr, "Same address returned\n");
9714 fprintf (stderr, "NULL returned\n");
9717 fprintf (stderr, "New address:\n");
9724 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9725 that is a valid memory address for an instruction.
9726 The MODE argument is the machine mode for the MEM expression
9727 that wants to use this address.
9729 On the RS/6000, there are four valid address: a SYMBOL_REF that
9730 refers to a constant pool entry of an address (or the sum of it
9731 plus a constant), a short (16-bit signed) constant plus a register,
9732 the sum of two registers, or a register indirect, possibly with an
9733 auto-increment. For DFmode, DDmode and DImode with a constant plus
9734 register, we must ensure that both words are addressable or PowerPC64
9735 with offset word aligned.
9737 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9738 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9739 because adjacent memory cells are accessed by adding word-sized offsets
9740 during assembly output. */
9742 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9744 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9745 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9747 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9748 if (VECTOR_MEM_ALTIVEC_P (mode)
9749 && GET_CODE (x) == AND
9750 && GET_CODE (XEXP (x, 1)) == CONST_INT
9751 && INTVAL (XEXP (x, 1)) == -16)
9754 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9756 if (legitimate_indirect_address_p (x, reg_ok_strict))
9759 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9760 && mode_supports_pre_incdec_p (mode)
9761 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9763 /* Handle restricted vector d-form offsets in ISA 3.0. */
9766 if (quad_address_p (x, mode, reg_ok_strict))
9769 else if (virtual_stack_registers_memory_p (x))
9772 else if (reg_offset_p)
9774 if (legitimate_small_data_p (mode, x))
9776 if (legitimate_constant_pool_address_p (x, mode,
9777 reg_ok_strict || lra_in_progress))
9779 if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
9780 && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
9784 /* For TImode, if we have TImode in VSX registers, only allow register
9785 indirect addresses. This will allow the values to go in either GPRs
9786 or VSX registers without reloading. The vector types would tend to
9787 go into VSX registers, so we allow REG+REG, while TImode seems
9788 somewhat split, in that some uses are GPR based, and some VSX based. */
9789 /* FIXME: We could loosen this by changing the following to
9790 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9791 but currently we cannot allow REG+REG addressing for TImode. See
9792 PR72827 for complete details on how this ends up hoodwinking DSE. */
9793 if (mode == TImode && TARGET_VSX)
9795 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9798 && GET_CODE (x) == PLUS
9799 && GET_CODE (XEXP (x, 0)) == REG
9800 && (XEXP (x, 0) == virtual_stack_vars_rtx
9801 || XEXP (x, 0) == arg_pointer_rtx)
9802 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9804 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9806 if (!FLOAT128_2REG_P (mode)
9807 && ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9809 || (mode != DFmode && mode != DDmode))
9810 && (TARGET_POWERPC64 || mode != DImode)
9811 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9813 && !avoiding_indexed_address_p (mode)
9814 && legitimate_indexed_address_p (x, reg_ok_strict))
9816 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9817 && mode_supports_pre_modify_p (mode)
9818 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9819 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9820 reg_ok_strict, false)
9821 || (!avoiding_indexed_address_p (mode)
9822 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9823 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9825 if (reg_offset_p && !quad_offset_p
9826 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9831 /* Debug version of rs6000_legitimate_address_p. */
9833 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9836 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9838 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9839 "strict = %d, reload = %s, code = %s\n",
9840 ret ? "true" : "false",
9841 GET_MODE_NAME (mode),
9843 (reload_completed ? "after" : "before"),
9844 GET_RTX_NAME (GET_CODE (x)));
9850 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9853 rs6000_mode_dependent_address_p (const_rtx addr,
9854 addr_space_t as ATTRIBUTE_UNUSED)
9856 return rs6000_mode_dependent_address_ptr (addr);
9859 /* Go to LABEL if ADDR (a legitimate address expression)
9860 has an effect that depends on the machine mode it is used for.
9862 On the RS/6000 this is true of all integral offsets (since AltiVec
9863 and VSX modes don't allow them) or is a pre-increment or decrement.
9865 ??? Except that due to conceptual problems in offsettable_address_p
9866 we can't really report the problems of integral offsets. So leave
9867 this assuming that the adjustable offset must be valid for the
9868 sub-words of a TFmode operand, which is what we had before. */
9871 rs6000_mode_dependent_address (const_rtx addr)
9873 switch (GET_CODE (addr))
9876 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9877 is considered a legitimate address before reload, so there
9878 are no offset restrictions in that case. Note that this
9879 condition is safe in strict mode because any address involving
9880 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9881 been rejected as illegitimate. */
9882 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9883 && XEXP (addr, 0) != arg_pointer_rtx
9884 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9886 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9887 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9892 /* Anything in the constant pool is sufficiently aligned that
9893 all bytes have the same high part address. */
9894 return !legitimate_constant_pool_address_p (addr, QImode, false);
9896 /* Auto-increment cases are now treated generically in recog.c. */
9898 return TARGET_UPDATE;
9900 /* AND is only allowed in Altivec loads. */
9911 /* Debug version of rs6000_mode_dependent_address. */
9913 rs6000_debug_mode_dependent_address (const_rtx addr)
9915 bool ret = rs6000_mode_dependent_address (addr);
9917 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9918 ret ? "true" : "false");
9924 /* Implement FIND_BASE_TERM. */
9927 rs6000_find_base_term (rtx op)
9932 if (GET_CODE (base) == CONST)
9933 base = XEXP (base, 0);
9934 if (GET_CODE (base) == PLUS)
9935 base = XEXP (base, 0);
9936 if (GET_CODE (base) == UNSPEC)
9937 switch (XINT (base, 1))
9940 case UNSPEC_MACHOPIC_OFFSET:
9941 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9942 for aliasing purposes. */
9943 return XVECEXP (base, 0, 0);
9949 /* More elaborate version of recog's offsettable_memref_p predicate
9950 that works around the ??? note of rs6000_mode_dependent_address.
9951 In particular it accepts
9953 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9955 in 32-bit mode, that the recog predicate rejects. */
9958 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
9965 /* First mimic offsettable_memref_p. */
9966 if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
9969 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9970 the latter predicate knows nothing about the mode of the memory
9971 reference and, therefore, assumes that it is the largest supported
9972 mode (TFmode). As a consequence, legitimate offsettable memory
9973 references are rejected. rs6000_legitimate_offset_address_p contains
9974 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9975 at least with a little bit of help here given that we know the
9976 actual registers used. */
9977 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9978 || GET_MODE_SIZE (reg_mode) == 4);
9979 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9983 /* Determine the reassociation width to be used in reassociate_bb.
9984 This takes into account how many parallel operations we
9985 can actually do of a given type, and also the latency.
9989 vect add/sub/mul 2/cycle
9990 fp add/sub/mul 2/cycle
9995 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9998 switch (rs6000_tune)
10000 case PROCESSOR_POWER8:
10001 case PROCESSOR_POWER9:
10002 if (DECIMAL_FLOAT_MODE_P (mode))
10004 if (VECTOR_MODE_P (mode))
10006 if (INTEGRAL_MODE_P (mode))
10007 return opc == MULT_EXPR ? 4 : 6;
10008 if (FLOAT_MODE_P (mode))
10017 /* Change register usage conditional on target flags. */
10019 rs6000_conditional_register_usage (void)
10023 if (TARGET_DEBUG_TARGET)
10024 fprintf (stderr, "rs6000_conditional_register_usage called\n");
10026 /* Set MQ register fixed (already call_used) so that it will not be
10028 fixed_regs[64] = 1;
10030 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
10032 fixed_regs[13] = call_used_regs[13]
10033 = call_really_used_regs[13] = 1;
10035 /* Conditionally disable FPRs. */
10036 if (TARGET_SOFT_FLOAT)
10037 for (i = 32; i < 64; i++)
10038 fixed_regs[i] = call_used_regs[i]
10039 = call_really_used_regs[i] = 1;
10041 /* The TOC register is not killed across calls in a way that is
10042 visible to the compiler. */
10043 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10044 call_really_used_regs[2] = 0;
10046 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
10047 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10049 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10050 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10051 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10052 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10054 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
10055 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10056 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10057 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10059 if (TARGET_TOC && TARGET_MINIMAL_TOC)
10060 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10061 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10063 if (!TARGET_ALTIVEC && !TARGET_VSX)
10065 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10066 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10067 call_really_used_regs[VRSAVE_REGNO] = 1;
10070 if (TARGET_ALTIVEC || TARGET_VSX)
10071 global_regs[VSCR_REGNO] = 1;
10073 if (TARGET_ALTIVEC_ABI)
10075 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
10076 call_used_regs[i] = call_really_used_regs[i] = 1;
10078 /* AIX reserves VR20:31 in non-extended ABI mode. */
10080 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
10081 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10086 /* Output insns to set DEST equal to the constant SOURCE as a series of
10087 lis, ori and shl instructions and return TRUE. */
10090 rs6000_emit_set_const (rtx dest, rtx source)
10092 machine_mode mode = GET_MODE (dest);
10097 gcc_checking_assert (CONST_INT_P (source));
10098 c = INTVAL (source);
10103 emit_insn (gen_rtx_SET (dest, source));
10107 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
10109 emit_insn (gen_rtx_SET (copy_rtx (temp),
10110 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
10111 emit_insn (gen_rtx_SET (dest,
10112 gen_rtx_IOR (SImode, copy_rtx (temp),
10113 GEN_INT (c & 0xffff))));
10117 if (!TARGET_POWERPC64)
10121 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
10123 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
10125 emit_move_insn (hi, GEN_INT (c >> 32));
10126 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
10127 emit_move_insn (lo, GEN_INT (c));
10130 rs6000_emit_set_long_const (dest, c);
10134 gcc_unreachable ();
10137 insn = get_last_insn ();
10138 set = single_set (insn);
10139 if (! CONSTANT_P (SET_SRC (set)))
10140 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
10145 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
10146 Output insns to set DEST equal to the constant C as a series of
10147 lis, ori and shl instructions. */
10150 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
10153 HOST_WIDE_INT ud1, ud2, ud3, ud4;
10163 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
10164 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
10165 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
10167 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
10168 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
10170 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10172 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10173 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10175 emit_move_insn (dest,
10176 gen_rtx_IOR (DImode, copy_rtx (temp),
10179 else if (ud3 == 0 && ud4 == 0)
10181 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10183 gcc_assert (ud2 & 0x8000);
10184 emit_move_insn (copy_rtx (temp),
10185 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10187 emit_move_insn (copy_rtx (temp),
10188 gen_rtx_IOR (DImode, copy_rtx (temp),
10190 emit_move_insn (dest,
10191 gen_rtx_ZERO_EXTEND (DImode,
10192 gen_lowpart (SImode,
10193 copy_rtx (temp))));
10195 else if ((ud4 == 0xffff && (ud3 & 0x8000))
10196 || (ud4 == 0 && ! (ud3 & 0x8000)))
10198 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10200 emit_move_insn (copy_rtx (temp),
10201 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
10203 emit_move_insn (copy_rtx (temp),
10204 gen_rtx_IOR (DImode, copy_rtx (temp),
10206 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10207 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10210 emit_move_insn (dest,
10211 gen_rtx_IOR (DImode, copy_rtx (temp),
10216 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10218 emit_move_insn (copy_rtx (temp),
10219 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
10221 emit_move_insn (copy_rtx (temp),
10222 gen_rtx_IOR (DImode, copy_rtx (temp),
10225 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
10226 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10229 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10230 gen_rtx_IOR (DImode, copy_rtx (temp),
10231 GEN_INT (ud2 << 16)));
10233 emit_move_insn (dest,
10234 gen_rtx_IOR (DImode, copy_rtx (temp),
10239 /* Helper for the following. Get rid of [r+r] memory refs
10240 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
10243 rs6000_eliminate_indexed_memrefs (rtx operands[2])
10245 if (GET_CODE (operands[0]) == MEM
10246 && GET_CODE (XEXP (operands[0], 0)) != REG
10247 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
10248 GET_MODE (operands[0]), false))
10250 = replace_equiv_address (operands[0],
10251 copy_addr_to_reg (XEXP (operands[0], 0)));
10253 if (GET_CODE (operands[1]) == MEM
10254 && GET_CODE (XEXP (operands[1], 0)) != REG
10255 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
10256 GET_MODE (operands[1]), false))
10258 = replace_equiv_address (operands[1],
10259 copy_addr_to_reg (XEXP (operands[1], 0)));
10262 /* Generate a vector of constants to permute MODE for a little-endian
10263 storage operation by swapping the two halves of a vector. */
10265 rs6000_const_vec (machine_mode mode)
10293 v = rtvec_alloc (subparts);
10295 for (i = 0; i < subparts / 2; ++i)
10296 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
10297 for (i = subparts / 2; i < subparts; ++i)
10298 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
10303 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10304 store operation. */
10306 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
10308 /* Scalar permutations are easier to express in integer modes rather than
10309 floating-point modes, so cast them here. We use V1TImode instead
10310 of TImode to ensure that the values don't go through GPRs. */
10311 if (FLOAT128_VECTOR_P (mode))
10313 dest = gen_lowpart (V1TImode, dest);
10314 source = gen_lowpart (V1TImode, source);
10318 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10320 if (mode == TImode || mode == V1TImode)
10321 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
10325 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
10326 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
10330 /* Emit a little-endian load from vector memory location SOURCE to VSX
10331 register DEST in mode MODE. The load is done with two permuting
10332 insn's that represent an lxvd2x and xxpermdi. */
10334 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
10336 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10338 if (mode == TImode || mode == V1TImode)
10341 dest = gen_lowpart (V2DImode, dest);
10342 source = adjust_address (source, V2DImode, 0);
10345 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
10346 rs6000_emit_le_vsx_permute (tmp, source, mode);
10347 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10350 /* Emit a little-endian store to vector memory location DEST from VSX
10351 register SOURCE in mode MODE. The store is done with two permuting
10352 insn's that represent an xxpermdi and an stxvd2x. */
10354 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
10356 /* This should never be called during or after LRA, because it does
10357 not re-permute the source register. It is intended only for use
10359 gcc_assert (!lra_in_progress && !reload_completed);
10361 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10363 if (mode == TImode || mode == V1TImode)
10366 dest = adjust_address (dest, V2DImode, 0);
10367 source = gen_lowpart (V2DImode, source);
10370 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
10371 rs6000_emit_le_vsx_permute (tmp, source, mode);
10372 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10375 /* Emit a sequence representing a little-endian VSX load or store,
10376 moving data from SOURCE to DEST in mode MODE. This is done
10377 separately from rs6000_emit_move to ensure it is called only
10378 during expand. LE VSX loads and stores introduced later are
10379 handled with a split. The expand-time RTL generation allows
10380 us to optimize away redundant pairs of register-permutes. */
10382 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
10384 gcc_assert (!BYTES_BIG_ENDIAN
10385 && VECTOR_MEM_VSX_P (mode)
10386 && !TARGET_P9_VECTOR
10387 && !gpr_or_gpr_p (dest, source)
10388 && (MEM_P (source) ^ MEM_P (dest)));
10390 if (MEM_P (source))
10392 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
10393 rs6000_emit_le_vsx_load (dest, source, mode);
10397 if (!REG_P (source))
10398 source = force_reg (mode, source);
10399 rs6000_emit_le_vsx_store (dest, source, mode);
10403 /* Return whether a SFmode or SImode move can be done without converting one
10404 mode to another. This arrises when we have:
10406 (SUBREG:SF (REG:SI ...))
10407 (SUBREG:SI (REG:SF ...))
10409 and one of the values is in a floating point/vector register, where SFmode
10410 scalars are stored in DFmode format. */
10413 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
10415 if (TARGET_ALLOW_SF_SUBREG)
10418 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
10421 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
10424 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10425 if (SUBREG_P (dest))
10427 rtx dest_subreg = SUBREG_REG (dest);
10428 rtx src_subreg = SUBREG_REG (src);
10429 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
10436 /* Helper function to change moves with:
10438 (SUBREG:SF (REG:SI)) and
10439 (SUBREG:SI (REG:SF))
10441 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10442 values are stored as DFmode values in the VSX registers. We need to convert
10443 the bits before we can use a direct move or operate on the bits in the
10444 vector register as an integer type.
10446 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10449 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
10451 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
10452 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
10453 && SUBREG_P (source) && sf_subreg_operand (source, mode))
10455 rtx inner_source = SUBREG_REG (source);
10456 machine_mode inner_mode = GET_MODE (inner_source);
10458 if (mode == SImode && inner_mode == SFmode)
10460 emit_insn (gen_movsi_from_sf (dest, inner_source));
10464 if (mode == SFmode && inner_mode == SImode)
10466 emit_insn (gen_movsf_from_si (dest, inner_source));
10474 /* Emit a move from SOURCE to DEST in mode MODE. */
10476 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
10479 operands[0] = dest;
10480 operands[1] = source;
10482 if (TARGET_DEBUG_ADDR)
10485 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10486 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10487 GET_MODE_NAME (mode),
10490 can_create_pseudo_p ());
10492 fprintf (stderr, "source:\n");
10493 debug_rtx (source);
10496 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10497 if (CONST_WIDE_INT_P (operands[1])
10498 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10500 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10501 gcc_unreachable ();
10504 /* See if we need to special case SImode/SFmode SUBREG moves. */
10505 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
10506 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
10509 /* Check if GCC is setting up a block move that will end up using FP
10510 registers as temporaries. We must make sure this is acceptable. */
10511 if (GET_CODE (operands[0]) == MEM
10512 && GET_CODE (operands[1]) == MEM
10514 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
10515 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10516 && ! (rs6000_slow_unaligned_access (SImode,
10517 (MEM_ALIGN (operands[0]) > 32
10518 ? 32 : MEM_ALIGN (operands[0])))
10519 || rs6000_slow_unaligned_access (SImode,
10520 (MEM_ALIGN (operands[1]) > 32
10521 ? 32 : MEM_ALIGN (operands[1]))))
10522 && ! MEM_VOLATILE_P (operands [0])
10523 && ! MEM_VOLATILE_P (operands [1]))
10525 emit_move_insn (adjust_address (operands[0], SImode, 0),
10526 adjust_address (operands[1], SImode, 0));
10527 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
10528 adjust_address (copy_rtx (operands[1]), SImode, 4));
10532 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
10533 && !gpc_reg_operand (operands[1], mode))
10534 operands[1] = force_reg (mode, operands[1]);
10536 /* Recognize the case where operand[1] is a reference to thread-local
10537 data and load its address to a register. */
10538 if (tls_referenced_p (operands[1]))
10540 enum tls_model model;
10541 rtx tmp = operands[1];
10544 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
10546 addend = XEXP (XEXP (tmp, 0), 1);
10547 tmp = XEXP (XEXP (tmp, 0), 0);
10550 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
10551 model = SYMBOL_REF_TLS_MODEL (tmp);
10552 gcc_assert (model != 0);
10554 tmp = rs6000_legitimize_tls_address (tmp, model);
10557 tmp = gen_rtx_PLUS (mode, tmp, addend);
10558 tmp = force_operand (tmp, operands[0]);
10563 /* 128-bit constant floating-point values on Darwin should really be loaded
10564 as two parts. However, this premature splitting is a problem when DFmode
10565 values can go into Altivec registers. */
10566 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
10567 && GET_CODE (operands[1]) == CONST_DOUBLE)
10569 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
10570 simplify_gen_subreg (DFmode, operands[1], mode, 0),
10572 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
10573 GET_MODE_SIZE (DFmode)),
10574 simplify_gen_subreg (DFmode, operands[1], mode,
10575 GET_MODE_SIZE (DFmode)),
10580 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10581 p1:SD) if p1 is not of floating point class and p0 is spilled as
10582 we can have no analogous movsd_store for this. */
10583 if (lra_in_progress && mode == DDmode
10584 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10585 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10586 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
10587 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
10590 int regno = REGNO (SUBREG_REG (operands[1]));
10592 if (regno >= FIRST_PSEUDO_REGISTER)
10594 cl = reg_preferred_class (regno);
10595 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
10597 if (regno >= 0 && ! FP_REGNO_P (regno))
10600 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
10601 operands[1] = SUBREG_REG (operands[1]);
10604 if (lra_in_progress
10606 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10607 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10608 && (REG_P (operands[1])
10609 || (GET_CODE (operands[1]) == SUBREG
10610 && REG_P (SUBREG_REG (operands[1])))))
10612 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
10613 ? SUBREG_REG (operands[1]) : operands[1]);
10616 if (regno >= FIRST_PSEUDO_REGISTER)
10618 cl = reg_preferred_class (regno);
10619 gcc_assert (cl != NO_REGS);
10620 regno = ira_class_hard_regs[cl][0];
10622 if (FP_REGNO_P (regno))
10624 if (GET_MODE (operands[0]) != DDmode)
10625 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10626 emit_insn (gen_movsd_store (operands[0], operands[1]));
10628 else if (INT_REGNO_P (regno))
10629 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10634 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10635 p:DD)) if p0 is not of floating point class and p1 is spilled as
10636 we can have no analogous movsd_load for this. */
10637 if (lra_in_progress && mode == DDmode
10638 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10639 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10640 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10641 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10644 int regno = REGNO (SUBREG_REG (operands[0]));
10646 if (regno >= FIRST_PSEUDO_REGISTER)
10648 cl = reg_preferred_class (regno);
10649 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10651 if (regno >= 0 && ! FP_REGNO_P (regno))
10654 operands[0] = SUBREG_REG (operands[0]);
10655 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10658 if (lra_in_progress
10660 && (REG_P (operands[0])
10661 || (GET_CODE (operands[0]) == SUBREG
10662 && REG_P (SUBREG_REG (operands[0]))))
10663 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10664 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10666 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10667 ? SUBREG_REG (operands[0]) : operands[0]);
10670 if (regno >= FIRST_PSEUDO_REGISTER)
10672 cl = reg_preferred_class (regno);
10673 gcc_assert (cl != NO_REGS);
10674 regno = ira_class_hard_regs[cl][0];
10676 if (FP_REGNO_P (regno))
10678 if (GET_MODE (operands[1]) != DDmode)
10679 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10680 emit_insn (gen_movsd_load (operands[0], operands[1]));
10682 else if (INT_REGNO_P (regno))
10683 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10689 /* FIXME: In the long term, this switch statement should go away
10690 and be replaced by a sequence of tests based on things like
10696 if (CONSTANT_P (operands[1])
10697 && GET_CODE (operands[1]) != CONST_INT)
10698 operands[1] = force_const_mem (mode, operands[1]);
10705 if (FLOAT128_2REG_P (mode))
10706 rs6000_eliminate_indexed_memrefs (operands);
10713 if (CONSTANT_P (operands[1])
10714 && ! easy_fp_constant (operands[1], mode))
10715 operands[1] = force_const_mem (mode, operands[1]);
10727 if (CONSTANT_P (operands[1])
10728 && !easy_vector_constant (operands[1], mode))
10729 operands[1] = force_const_mem (mode, operands[1]);
10734 /* Use default pattern for address of ELF small data */
10737 && DEFAULT_ABI == ABI_V4
10738 && (GET_CODE (operands[1]) == SYMBOL_REF
10739 || GET_CODE (operands[1]) == CONST)
10740 && small_data_operand (operands[1], mode))
10742 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10746 if (DEFAULT_ABI == ABI_V4
10747 && mode == Pmode && mode == SImode
10748 && flag_pic == 1 && got_operand (operands[1], mode))
10750 emit_insn (gen_movsi_got (operands[0], operands[1]));
10754 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10758 && CONSTANT_P (operands[1])
10759 && GET_CODE (operands[1]) != HIGH
10760 && GET_CODE (operands[1]) != CONST_INT)
10762 rtx target = (!can_create_pseudo_p ()
10764 : gen_reg_rtx (mode));
10766 /* If this is a function address on -mcall-aixdesc,
10767 convert it to the address of the descriptor. */
10768 if (DEFAULT_ABI == ABI_AIX
10769 && GET_CODE (operands[1]) == SYMBOL_REF
10770 && XSTR (operands[1], 0)[0] == '.')
10772 const char *name = XSTR (operands[1], 0);
10774 while (*name == '.')
10776 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10777 CONSTANT_POOL_ADDRESS_P (new_ref)
10778 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10779 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10780 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10781 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10782 operands[1] = new_ref;
10785 if (DEFAULT_ABI == ABI_DARWIN)
10788 if (MACHO_DYNAMIC_NO_PIC_P)
10790 /* Take care of any required data indirection. */
10791 operands[1] = rs6000_machopic_legitimize_pic_address (
10792 operands[1], mode, operands[0]);
10793 if (operands[0] != operands[1])
10794 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10798 emit_insn (gen_macho_high (target, operands[1]));
10799 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10803 emit_insn (gen_elf_high (target, operands[1]));
10804 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10808 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10809 and we have put it in the TOC, we just need to make a TOC-relative
10810 reference to it. */
10812 && GET_CODE (operands[1]) == SYMBOL_REF
10813 && use_toc_relative_ref (operands[1], mode))
10814 operands[1] = create_TOC_reference (operands[1], operands[0]);
10815 else if (mode == Pmode
10816 && CONSTANT_P (operands[1])
10817 && GET_CODE (operands[1]) != HIGH
10818 && ((GET_CODE (operands[1]) != CONST_INT
10819 && ! easy_fp_constant (operands[1], mode))
10820 || (GET_CODE (operands[1]) == CONST_INT
10821 && (num_insns_constant (operands[1], mode)
10822 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10823 || (GET_CODE (operands[0]) == REG
10824 && FP_REGNO_P (REGNO (operands[0]))))
10825 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10826 && (TARGET_CMODEL == CMODEL_SMALL
10827 || can_create_pseudo_p ()
10828 || (REG_P (operands[0])
10829 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10833 /* Darwin uses a special PIC legitimizer. */
10834 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10837 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10839 if (operands[0] != operands[1])
10840 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10845 /* If we are to limit the number of things we put in the TOC and
10846 this is a symbol plus a constant we can add in one insn,
10847 just put the symbol in the TOC and add the constant. */
10848 if (GET_CODE (operands[1]) == CONST
10849 && TARGET_NO_SUM_IN_TOC
10850 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10851 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10852 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10853 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10854 && ! side_effects_p (operands[0]))
10857 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10858 rtx other = XEXP (XEXP (operands[1], 0), 1);
10860 sym = force_reg (mode, sym);
10861 emit_insn (gen_add3_insn (operands[0], sym, other));
10865 operands[1] = force_const_mem (mode, operands[1]);
10868 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10869 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10871 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10873 operands[1] = gen_const_mem (mode, tocref);
10874 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10880 if (!VECTOR_MEM_VSX_P (TImode))
10881 rs6000_eliminate_indexed_memrefs (operands);
10885 rs6000_eliminate_indexed_memrefs (operands);
10889 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10892 /* Above, we may have called force_const_mem which may have returned
10893 an invalid address. If we can, fix this up; otherwise, reload will
10894 have to deal with it. */
10895 if (GET_CODE (operands[1]) == MEM)
10896 operands[1] = validize_mem (operands[1]);
10898 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10901 /* Nonzero if we can use a floating-point register to pass this arg. */
10902 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10903 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10904 && (CUM)->fregno <= FP_ARG_MAX_REG \
10905 && TARGET_HARD_FLOAT)
10907 /* Nonzero if we can use an AltiVec register to pass this arg. */
10908 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10909 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10910 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10911 && TARGET_ALTIVEC_ABI \
10914 /* Walk down the type tree of TYPE counting consecutive base elements.
10915 If *MODEP is VOIDmode, then set it to the first valid floating point
10916 or vector type. If a non-floating point or vector type is found, or
10917 if a floating point or vector type that doesn't match a non-VOIDmode
10918 *MODEP is found, then return -1, otherwise return the count in the
10922 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10925 HOST_WIDE_INT size;
10927 switch (TREE_CODE (type))
10930 mode = TYPE_MODE (type);
10931 if (!SCALAR_FLOAT_MODE_P (mode))
10934 if (*modep == VOIDmode)
10937 if (*modep == mode)
10943 mode = TYPE_MODE (TREE_TYPE (type));
10944 if (!SCALAR_FLOAT_MODE_P (mode))
10947 if (*modep == VOIDmode)
10950 if (*modep == mode)
10956 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10959 /* Use V4SImode as representative of all 128-bit vector types. */
10960 size = int_size_in_bytes (type);
10970 if (*modep == VOIDmode)
10973 /* Vector modes are considered to be opaque: two vectors are
10974 equivalent for the purposes of being homogeneous aggregates
10975 if they are the same size. */
10976 if (*modep == mode)
10984 tree index = TYPE_DOMAIN (type);
10986 /* Can't handle incomplete types nor sizes that are not
10988 if (!COMPLETE_TYPE_P (type)
10989 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10992 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10995 || !TYPE_MAX_VALUE (index)
10996 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10997 || !TYPE_MIN_VALUE (index)
10998 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
11002 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
11003 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
11005 /* There must be no padding. */
11006 if (wi::to_wide (TYPE_SIZE (type))
11007 != count * GET_MODE_BITSIZE (*modep))
11019 /* Can't handle incomplete types nor sizes that are not
11021 if (!COMPLETE_TYPE_P (type)
11022 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11025 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11027 if (TREE_CODE (field) != FIELD_DECL)
11030 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11033 count += sub_count;
11036 /* There must be no padding. */
11037 if (wi::to_wide (TYPE_SIZE (type))
11038 != count * GET_MODE_BITSIZE (*modep))
11045 case QUAL_UNION_TYPE:
11047 /* These aren't very interesting except in a degenerate case. */
11052 /* Can't handle incomplete types nor sizes that are not
11054 if (!COMPLETE_TYPE_P (type)
11055 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11058 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11060 if (TREE_CODE (field) != FIELD_DECL)
11063 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11066 count = count > sub_count ? count : sub_count;
11069 /* There must be no padding. */
11070 if (wi::to_wide (TYPE_SIZE (type))
11071 != count * GET_MODE_BITSIZE (*modep))
11084 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
11085 float or vector aggregate that shall be passed in FP/vector registers
11086 according to the ELFv2 ABI, return the homogeneous element mode in
11087 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
11089 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
11092 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
11093 machine_mode *elt_mode,
11096 /* Note that we do not accept complex types at the top level as
11097 homogeneous aggregates; these types are handled via the
11098 targetm.calls.split_complex_arg mechanism. Complex types
11099 can be elements of homogeneous aggregates, however. */
11100 if (DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P (type))
11102 machine_mode field_mode = VOIDmode;
11103 int field_count = rs6000_aggregate_candidate (type, &field_mode);
11105 if (field_count > 0)
11107 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
11108 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
11110 /* The ELFv2 ABI allows homogeneous aggregates to occupy
11111 up to AGGR_ARG_NUM_REG registers. */
11112 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
11115 *elt_mode = field_mode;
11117 *n_elts = field_count;
11130 /* Return a nonzero value to say to return the function value in
11131 memory, just as large structures are always returned. TYPE will be
11132 the data type of the value, and FNTYPE will be the type of the
11133 function doing the returning, or @code{NULL} for libcalls.
11135 The AIX ABI for the RS/6000 specifies that all structures are
11136 returned in memory. The Darwin ABI does the same.
11138 For the Darwin 64 Bit ABI, a function result can be returned in
11139 registers or in memory, depending on the size of the return data
11140 type. If it is returned in registers, the value occupies the same
11141 registers as it would if it were the first and only function
11142 argument. Otherwise, the function places its result in memory at
11143 the location pointed to by GPR3.
11145 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
11146 but a draft put them in memory, and GCC used to implement the draft
11147 instead of the final standard. Therefore, aix_struct_return
11148 controls this instead of DEFAULT_ABI; V.4 targets needing backward
11149 compatibility can change DRAFT_V4_STRUCT_RET to override the
11150 default, and -m switches get the final word. See
11151 rs6000_option_override_internal for more details.
11153 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
11154 long double support is enabled. These values are returned in memory.
11156 int_size_in_bytes returns -1 for variable size objects, which go in
11157 memory always. The cast to unsigned makes -1 > 8. */
11160 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
11162 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
11164 && rs6000_darwin64_abi
11165 && TREE_CODE (type) == RECORD_TYPE
11166 && int_size_in_bytes (type) > 0)
11168 CUMULATIVE_ARGS valcum;
11172 valcum.fregno = FP_ARG_MIN_REG;
11173 valcum.vregno = ALTIVEC_ARG_MIN_REG;
11174 /* Do a trial code generation as if this were going to be passed
11175 as an argument; if any part goes in memory, we return NULL. */
11176 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
11179 /* Otherwise fall through to more conventional ABI rules. */
11182 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
11183 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
11187 /* The ELFv2 ABI returns aggregates up to 16B in registers */
11188 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
11189 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
11192 if (AGGREGATE_TYPE_P (type)
11193 && (aix_struct_return
11194 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
11197 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11198 modes only exist for GCC vector types if -maltivec. */
11199 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
11200 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
11203 /* Return synthetic vectors in memory. */
11204 if (TREE_CODE (type) == VECTOR_TYPE
11205 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11207 static bool warned_for_return_big_vectors = false;
11208 if (!warned_for_return_big_vectors)
11210 warning (OPT_Wpsabi, "GCC vector returned by reference: "
11211 "non-standard ABI extension with no compatibility "
11213 warned_for_return_big_vectors = true;
11218 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11219 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11225 /* Specify whether values returned in registers should be at the most
11226 significant end of a register. We want aggregates returned by
11227 value to match the way aggregates are passed to functions. */
11230 rs6000_return_in_msb (const_tree valtype)
11232 return (DEFAULT_ABI == ABI_ELFv2
11233 && BYTES_BIG_ENDIAN
11234 && AGGREGATE_TYPE_P (valtype)
11235 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
11239 #ifdef HAVE_AS_GNU_ATTRIBUTE
11240 /* Return TRUE if a call to function FNDECL may be one that
11241 potentially affects the function calling ABI of the object file. */
11244 call_ABI_of_interest (tree fndecl)
11246 if (rs6000_gnu_attr && symtab->state == EXPANSION)
11248 struct cgraph_node *c_node;
11250 /* Libcalls are always interesting. */
11251 if (fndecl == NULL_TREE)
11254 /* Any call to an external function is interesting. */
11255 if (DECL_EXTERNAL (fndecl))
11258 /* Interesting functions that we are emitting in this object file. */
11259 c_node = cgraph_node::get (fndecl);
11260 c_node = c_node->ultimate_alias_target ();
11261 return !c_node->only_called_directly_p ();
11267 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11268 for a call to a function whose data type is FNTYPE.
11269 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11271 For incoming args we set the number of arguments in the prototype large
11272 so we never return a PARALLEL. */
11275 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
11276 rtx libname ATTRIBUTE_UNUSED, int incoming,
11277 int libcall, int n_named_args,
11278 tree fndecl ATTRIBUTE_UNUSED,
11279 machine_mode return_mode ATTRIBUTE_UNUSED)
11281 static CUMULATIVE_ARGS zero_cumulative;
11283 *cum = zero_cumulative;
11285 cum->fregno = FP_ARG_MIN_REG;
11286 cum->vregno = ALTIVEC_ARG_MIN_REG;
11287 cum->prototype = (fntype && prototype_p (fntype));
11288 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
11289 ? CALL_LIBCALL : CALL_NORMAL);
11290 cum->sysv_gregno = GP_ARG_MIN_REG;
11291 cum->stdarg = stdarg_p (fntype);
11292 cum->libcall = libcall;
11294 cum->nargs_prototype = 0;
11295 if (incoming || cum->prototype)
11296 cum->nargs_prototype = n_named_args;
11298 /* Check for a longcall attribute. */
11299 if ((!fntype && rs6000_default_long_calls)
11301 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
11302 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
11303 cum->call_cookie |= CALL_LONG;
11305 if (TARGET_DEBUG_ARG)
11307 fprintf (stderr, "\ninit_cumulative_args:");
11310 tree ret_type = TREE_TYPE (fntype);
11311 fprintf (stderr, " ret code = %s,",
11312 get_tree_code_name (TREE_CODE (ret_type)));
11315 if (cum->call_cookie & CALL_LONG)
11316 fprintf (stderr, " longcall,");
11318 fprintf (stderr, " proto = %d, nargs = %d\n",
11319 cum->prototype, cum->nargs_prototype);
11322 #ifdef HAVE_AS_GNU_ATTRIBUTE
11323 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
11325 cum->escapes = call_ABI_of_interest (fndecl);
11332 return_type = TREE_TYPE (fntype);
11333 return_mode = TYPE_MODE (return_type);
11336 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
11338 if (return_type != NULL)
11340 if (TREE_CODE (return_type) == RECORD_TYPE
11341 && TYPE_TRANSPARENT_AGGR (return_type))
11343 return_type = TREE_TYPE (first_field (return_type));
11344 return_mode = TYPE_MODE (return_type);
11346 if (AGGREGATE_TYPE_P (return_type)
11347 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
11349 rs6000_returns_struct = true;
11351 if (SCALAR_FLOAT_MODE_P (return_mode))
11353 rs6000_passes_float = true;
11354 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11355 && (FLOAT128_IBM_P (return_mode)
11356 || FLOAT128_IEEE_P (return_mode)
11357 || (return_type != NULL
11358 && (TYPE_MAIN_VARIANT (return_type)
11359 == long_double_type_node))))
11360 rs6000_passes_long_double = true;
11362 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
11363 || PAIRED_VECTOR_MODE (return_mode))
11364 rs6000_passes_vector = true;
11371 && TARGET_ALTIVEC_ABI
11372 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
11374 error ("cannot return value in vector register because"
11375 " altivec instructions are disabled, use %qs"
11376 " to enable them", "-maltivec");
11380 /* The mode the ABI uses for a word. This is not the same as word_mode
11381 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11383 static scalar_int_mode
11384 rs6000_abi_word_mode (void)
11386 return TARGET_32BIT ? SImode : DImode;
11389 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11391 rs6000_offload_options (void)
11394 return xstrdup ("-foffload-abi=lp64");
11396 return xstrdup ("-foffload-abi=ilp32");
11399 /* On rs6000, function arguments are promoted, as are function return
11402 static machine_mode
11403 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
11405 int *punsignedp ATTRIBUTE_UNUSED,
11408 PROMOTE_MODE (mode, *punsignedp, type);
11413 /* Return true if TYPE must be passed on the stack and not in registers. */
11416 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
11418 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
11419 return must_pass_in_stack_var_size (mode, type);
11421 return must_pass_in_stack_var_size_or_pad (mode, type);
11425 is_complex_IBM_long_double (machine_mode mode)
11427 return mode == ICmode || (!TARGET_IEEEQUAD && mode == TCmode);
11430 /* Whether ABI_V4 passes MODE args to a function in floating point
11434 abi_v4_pass_in_fpr (machine_mode mode)
11436 if (!TARGET_HARD_FLOAT)
11438 if (TARGET_SINGLE_FLOAT && mode == SFmode)
11440 if (TARGET_DOUBLE_FLOAT && mode == DFmode)
11442 /* ABI_V4 passes complex IBM long double in 8 gprs.
11443 Stupid, but we can't change the ABI now. */
11444 if (is_complex_IBM_long_double (mode))
11446 if (FLOAT128_2REG_P (mode))
11448 if (DECIMAL_FLOAT_MODE_P (mode))
11453 /* Implement TARGET_FUNCTION_ARG_PADDING.
11455 For the AIX ABI structs are always stored left shifted in their
11458 static pad_direction
11459 rs6000_function_arg_padding (machine_mode mode, const_tree type)
11461 #ifndef AGGREGATE_PADDING_FIXED
11462 #define AGGREGATE_PADDING_FIXED 0
11464 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11465 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11468 if (!AGGREGATE_PADDING_FIXED)
11470 /* GCC used to pass structures of the same size as integer types as
11471 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
11472 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11473 passed padded downward, except that -mstrict-align further
11474 muddied the water in that multi-component structures of 2 and 4
11475 bytes in size were passed padded upward.
11477 The following arranges for best compatibility with previous
11478 versions of gcc, but removes the -mstrict-align dependency. */
11479 if (BYTES_BIG_ENDIAN)
11481 HOST_WIDE_INT size = 0;
11483 if (mode == BLKmode)
11485 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
11486 size = int_size_in_bytes (type);
11489 size = GET_MODE_SIZE (mode);
11491 if (size == 1 || size == 2 || size == 4)
11492 return PAD_DOWNWARD;
11497 if (AGGREGATES_PAD_UPWARD_ALWAYS)
11499 if (type != 0 && AGGREGATE_TYPE_P (type))
11503 /* Fall back to the default. */
11504 return default_function_arg_padding (mode, type);
11507 /* If defined, a C expression that gives the alignment boundary, in bits,
11508 of an argument with the specified mode and type. If it is not defined,
11509 PARM_BOUNDARY is used for all arguments.
11511 V.4 wants long longs and doubles to be double word aligned. Just
11512 testing the mode size is a boneheaded way to do this as it means
11513 that other types such as complex int are also double word aligned.
11514 However, we're stuck with this because changing the ABI might break
11515 existing library interfaces.
11517 Quadword align Altivec/VSX vectors.
11518 Quadword align large synthetic vector types. */
11520 static unsigned int
11521 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
11523 machine_mode elt_mode;
11526 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11528 if (DEFAULT_ABI == ABI_V4
11529 && (GET_MODE_SIZE (mode) == 8
11530 || (TARGET_HARD_FLOAT
11531 && !is_complex_IBM_long_double (mode)
11532 && FLOAT128_2REG_P (mode))))
11534 else if (FLOAT128_VECTOR_P (mode))
11536 else if (PAIRED_VECTOR_MODE (mode)
11537 || (type && TREE_CODE (type) == VECTOR_TYPE
11538 && int_size_in_bytes (type) >= 8
11539 && int_size_in_bytes (type) < 16))
11541 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11542 || (type && TREE_CODE (type) == VECTOR_TYPE
11543 && int_size_in_bytes (type) >= 16))
11546 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11547 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11548 -mcompat-align-parm is used. */
11549 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
11550 || DEFAULT_ABI == ABI_ELFv2)
11551 && type && TYPE_ALIGN (type) > 64)
11553 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11554 or homogeneous float/vector aggregates here. We already handled
11555 vector aggregates above, but still need to check for float here. */
11556 bool aggregate_p = (AGGREGATE_TYPE_P (type)
11557 && !SCALAR_FLOAT_MODE_P (elt_mode));
11559 /* We used to check for BLKmode instead of the above aggregate type
11560 check. Warn when this results in any difference to the ABI. */
11561 if (aggregate_p != (mode == BLKmode))
11563 static bool warned;
11564 if (!warned && warn_psabi)
11567 inform (input_location,
11568 "the ABI of passing aggregates with %d-byte alignment"
11569 " has changed in GCC 5",
11570 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
11578 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11579 implement the "aggregate type" check as a BLKmode check here; this
11580 means certain aggregate types are in fact not aligned. */
11581 if (TARGET_MACHO && rs6000_darwin64_abi
11583 && type && TYPE_ALIGN (type) > 64)
11586 return PARM_BOUNDARY;
11589 /* The offset in words to the start of the parameter save area. */
11591 static unsigned int
11592 rs6000_parm_offset (void)
11594 return (DEFAULT_ABI == ABI_V4 ? 2
11595 : DEFAULT_ABI == ABI_ELFv2 ? 4
11599 /* For a function parm of MODE and TYPE, return the starting word in
11600 the parameter area. NWORDS of the parameter area are already used. */
11602 static unsigned int
11603 rs6000_parm_start (machine_mode mode, const_tree type,
11604 unsigned int nwords)
11606 unsigned int align;
11608 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11609 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11612 /* Compute the size (in words) of a function argument. */
11614 static unsigned long
11615 rs6000_arg_size (machine_mode mode, const_tree type)
11617 unsigned long size;
11619 if (mode != BLKmode)
11620 size = GET_MODE_SIZE (mode);
11622 size = int_size_in_bytes (type);
11625 return (size + 3) >> 2;
11627 return (size + 7) >> 3;
11630 /* Use this to flush pending int fields. */
11633 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11634 HOST_WIDE_INT bitpos, int final)
11636 unsigned int startbit, endbit;
11637 int intregs, intoffset;
11639 /* Handle the situations where a float is taking up the first half
11640 of the GPR, and the other half is empty (typically due to
11641 alignment restrictions). We can detect this by a 8-byte-aligned
11642 int field, or by seeing that this is the final flush for this
11643 argument. Count the word and continue on. */
11644 if (cum->floats_in_gpr == 1
11645 && (cum->intoffset % 64 == 0
11646 || (cum->intoffset == -1 && final)))
11649 cum->floats_in_gpr = 0;
11652 if (cum->intoffset == -1)
11655 intoffset = cum->intoffset;
11656 cum->intoffset = -1;
11657 cum->floats_in_gpr = 0;
11659 if (intoffset % BITS_PER_WORD != 0)
11661 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11662 if (!int_mode_for_size (bits, 0).exists ())
11664 /* We couldn't find an appropriate mode, which happens,
11665 e.g., in packed structs when there are 3 bytes to load.
11666 Back intoffset back to the beginning of the word in this
11668 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11672 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11673 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11674 intregs = (endbit - startbit) / BITS_PER_WORD;
11675 cum->words += intregs;
11676 /* words should be unsigned. */
11677 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11679 int pad = (endbit/BITS_PER_WORD) - cum->words;
11684 /* The darwin64 ABI calls for us to recurse down through structs,
11685 looking for elements passed in registers. Unfortunately, we have
11686 to track int register count here also because of misalignments
11687 in powerpc alignment mode. */
11690 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11692 HOST_WIDE_INT startbitpos)
11696 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11697 if (TREE_CODE (f) == FIELD_DECL)
11699 HOST_WIDE_INT bitpos = startbitpos;
11700 tree ftype = TREE_TYPE (f);
11702 if (ftype == error_mark_node)
11704 mode = TYPE_MODE (ftype);
11706 if (DECL_SIZE (f) != 0
11707 && tree_fits_uhwi_p (bit_position (f)))
11708 bitpos += int_bit_position (f);
11710 /* ??? FIXME: else assume zero offset. */
11712 if (TREE_CODE (ftype) == RECORD_TYPE)
11713 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11714 else if (USE_FP_FOR_ARG_P (cum, mode))
11716 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11717 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11718 cum->fregno += n_fpregs;
11719 /* Single-precision floats present a special problem for
11720 us, because they are smaller than an 8-byte GPR, and so
11721 the structure-packing rules combined with the standard
11722 varargs behavior mean that we want to pack float/float
11723 and float/int combinations into a single register's
11724 space. This is complicated by the arg advance flushing,
11725 which works on arbitrarily large groups of int-type
11727 if (mode == SFmode)
11729 if (cum->floats_in_gpr == 1)
11731 /* Two floats in a word; count the word and reset
11732 the float count. */
11734 cum->floats_in_gpr = 0;
11736 else if (bitpos % 64 == 0)
11738 /* A float at the beginning of an 8-byte word;
11739 count it and put off adjusting cum->words until
11740 we see if a arg advance flush is going to do it
11742 cum->floats_in_gpr++;
11746 /* The float is at the end of a word, preceded
11747 by integer fields, so the arg advance flush
11748 just above has already set cum->words and
11749 everything is taken care of. */
11753 cum->words += n_fpregs;
11755 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11757 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11761 else if (cum->intoffset == -1)
11762 cum->intoffset = bitpos;
11766 /* Check for an item that needs to be considered specially under the darwin 64
11767 bit ABI. These are record types where the mode is BLK or the structure is
11768 8 bytes in size. */
11770 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11772 return rs6000_darwin64_abi
11773 && ((mode == BLKmode
11774 && TREE_CODE (type) == RECORD_TYPE
11775 && int_size_in_bytes (type) > 0)
11776 || (type && TREE_CODE (type) == RECORD_TYPE
11777 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11780 /* Update the data in CUM to advance over an argument
11781 of mode MODE and data type TYPE.
11782 (TYPE is null for libcalls where that information may not be available.)
11784 Note that for args passed by reference, function_arg will be called
11785 with MODE and TYPE set to that of the pointer to the arg, not the arg
11789 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11790 const_tree type, bool named, int depth)
11792 machine_mode elt_mode;
11795 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11797 /* Only tick off an argument if we're not recursing. */
11799 cum->nargs_prototype--;
11801 #ifdef HAVE_AS_GNU_ATTRIBUTE
11802 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11805 if (SCALAR_FLOAT_MODE_P (mode))
11807 rs6000_passes_float = true;
11808 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11809 && (FLOAT128_IBM_P (mode)
11810 || FLOAT128_IEEE_P (mode)
11812 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11813 rs6000_passes_long_double = true;
11815 if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11816 || (PAIRED_VECTOR_MODE (mode)
11818 && cum->sysv_gregno <= GP_ARG_MAX_REG))
11819 rs6000_passes_vector = true;
11823 if (TARGET_ALTIVEC_ABI
11824 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11825 || (type && TREE_CODE (type) == VECTOR_TYPE
11826 && int_size_in_bytes (type) == 16)))
11828 bool stack = false;
11830 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11832 cum->vregno += n_elts;
11834 if (!TARGET_ALTIVEC)
11835 error ("cannot pass argument in vector register because"
11836 " altivec instructions are disabled, use %qs"
11837 " to enable them", "-maltivec");
11839 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11840 even if it is going to be passed in a vector register.
11841 Darwin does the same for variable-argument functions. */
11842 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11844 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11854 /* Vector parameters must be 16-byte aligned. In 32-bit
11855 mode this means we need to take into account the offset
11856 to the parameter save area. In 64-bit mode, they just
11857 have to start on an even word, since the parameter save
11858 area is 16-byte aligned. */
11860 align = -(rs6000_parm_offset () + cum->words) & 3;
11862 align = cum->words & 1;
11863 cum->words += align + rs6000_arg_size (mode, type);
11865 if (TARGET_DEBUG_ARG)
11867 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11868 cum->words, align);
11869 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11870 cum->nargs_prototype, cum->prototype,
11871 GET_MODE_NAME (mode));
11875 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11877 int size = int_size_in_bytes (type);
11878 /* Variable sized types have size == -1 and are
11879 treated as if consisting entirely of ints.
11880 Pad to 16 byte boundary if needed. */
11881 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11882 && (cum->words % 2) != 0)
11884 /* For varargs, we can just go up by the size of the struct. */
11886 cum->words += (size + 7) / 8;
11889 /* It is tempting to say int register count just goes up by
11890 sizeof(type)/8, but this is wrong in a case such as
11891 { int; double; int; } [powerpc alignment]. We have to
11892 grovel through the fields for these too. */
11893 cum->intoffset = 0;
11894 cum->floats_in_gpr = 0;
11895 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11896 rs6000_darwin64_record_arg_advance_flush (cum,
11897 size * BITS_PER_UNIT, 1);
11899 if (TARGET_DEBUG_ARG)
11901 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11902 cum->words, TYPE_ALIGN (type), size);
11904 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11905 cum->nargs_prototype, cum->prototype,
11906 GET_MODE_NAME (mode));
11909 else if (DEFAULT_ABI == ABI_V4)
11911 if (abi_v4_pass_in_fpr (mode))
11913 /* _Decimal128 must use an even/odd register pair. This assumes
11914 that the register number is odd when fregno is odd. */
11915 if (mode == TDmode && (cum->fregno % 2) == 1)
11918 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11919 <= FP_ARG_V4_MAX_REG)
11920 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11923 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11924 if (mode == DFmode || FLOAT128_IBM_P (mode)
11925 || mode == DDmode || mode == TDmode)
11926 cum->words += cum->words & 1;
11927 cum->words += rs6000_arg_size (mode, type);
11932 int n_words = rs6000_arg_size (mode, type);
11933 int gregno = cum->sysv_gregno;
11935 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11936 As does any other 2 word item such as complex int due to a
11937 historical mistake. */
11939 gregno += (1 - gregno) & 1;
11941 /* Multi-reg args are not split between registers and stack. */
11942 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11944 /* Long long is aligned on the stack. So are other 2 word
11945 items such as complex int due to a historical mistake. */
11947 cum->words += cum->words & 1;
11948 cum->words += n_words;
11951 /* Note: continuing to accumulate gregno past when we've started
11952 spilling to the stack indicates the fact that we've started
11953 spilling to the stack to expand_builtin_saveregs. */
11954 cum->sysv_gregno = gregno + n_words;
11957 if (TARGET_DEBUG_ARG)
11959 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11960 cum->words, cum->fregno);
11961 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11962 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11963 fprintf (stderr, "mode = %4s, named = %d\n",
11964 GET_MODE_NAME (mode), named);
11969 int n_words = rs6000_arg_size (mode, type);
11970 int start_words = cum->words;
11971 int align_words = rs6000_parm_start (mode, type, start_words);
11973 cum->words = align_words + n_words;
11975 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11977 /* _Decimal128 must be passed in an even/odd float register pair.
11978 This assumes that the register number is odd when fregno is
11980 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11982 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11985 if (TARGET_DEBUG_ARG)
11987 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11988 cum->words, cum->fregno);
11989 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11990 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11991 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11992 named, align_words - start_words, depth);
11998 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11999 const_tree type, bool named)
12001 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
12005 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
12006 structure between cum->intoffset and bitpos to integer registers. */
12009 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
12010 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
12013 unsigned int regno;
12014 unsigned int startbit, endbit;
12015 int this_regno, intregs, intoffset;
12018 if (cum->intoffset == -1)
12021 intoffset = cum->intoffset;
12022 cum->intoffset = -1;
12024 /* If this is the trailing part of a word, try to only load that
12025 much into the register. Otherwise load the whole register. Note
12026 that in the latter case we may pick up unwanted bits. It's not a
12027 problem at the moment but may wish to revisit. */
12029 if (intoffset % BITS_PER_WORD != 0)
12031 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
12032 if (!int_mode_for_size (bits, 0).exists (&mode))
12034 /* We couldn't find an appropriate mode, which happens,
12035 e.g., in packed structs when there are 3 bytes to load.
12036 Back intoffset back to the beginning of the word in this
12038 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
12045 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
12046 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
12047 intregs = (endbit - startbit) / BITS_PER_WORD;
12048 this_regno = cum->words + intoffset / BITS_PER_WORD;
12050 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
12051 cum->use_stack = 1;
12053 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
12057 intoffset /= BITS_PER_UNIT;
12060 regno = GP_ARG_MIN_REG + this_regno;
12061 reg = gen_rtx_REG (mode, regno);
12063 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
12066 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
12070 while (intregs > 0);
12073 /* Recursive workhorse for the following. */
12076 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
12077 HOST_WIDE_INT startbitpos, rtx rvec[],
12082 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
12083 if (TREE_CODE (f) == FIELD_DECL)
12085 HOST_WIDE_INT bitpos = startbitpos;
12086 tree ftype = TREE_TYPE (f);
12088 if (ftype == error_mark_node)
12090 mode = TYPE_MODE (ftype);
12092 if (DECL_SIZE (f) != 0
12093 && tree_fits_uhwi_p (bit_position (f)))
12094 bitpos += int_bit_position (f);
12096 /* ??? FIXME: else assume zero offset. */
12098 if (TREE_CODE (ftype) == RECORD_TYPE)
12099 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
12100 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
12102 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
12106 case E_SCmode: mode = SFmode; break;
12107 case E_DCmode: mode = DFmode; break;
12108 case E_TCmode: mode = TFmode; break;
12112 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12113 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
12115 gcc_assert (cum->fregno == FP_ARG_MAX_REG
12116 && (mode == TFmode || mode == TDmode));
12117 /* Long double or _Decimal128 split over regs and memory. */
12118 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
12122 = gen_rtx_EXPR_LIST (VOIDmode,
12123 gen_rtx_REG (mode, cum->fregno++),
12124 GEN_INT (bitpos / BITS_PER_UNIT));
12125 if (FLOAT128_2REG_P (mode))
12128 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
12130 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12132 = gen_rtx_EXPR_LIST (VOIDmode,
12133 gen_rtx_REG (mode, cum->vregno++),
12134 GEN_INT (bitpos / BITS_PER_UNIT));
12136 else if (cum->intoffset == -1)
12137 cum->intoffset = bitpos;
12141 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
12142 the register(s) to be used for each field and subfield of a struct
12143 being passed by value, along with the offset of where the
12144 register's value may be found in the block. FP fields go in FP
12145 register, vector fields go in vector registers, and everything
12146 else goes in int registers, packed as in memory.
12148 This code is also used for function return values. RETVAL indicates
12149 whether this is the case.
12151 Much of this is taken from the SPARC V9 port, which has a similar
12152 calling convention. */
12155 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
12156 bool named, bool retval)
12158 rtx rvec[FIRST_PSEUDO_REGISTER];
12159 int k = 1, kbase = 1;
12160 HOST_WIDE_INT typesize = int_size_in_bytes (type);
12161 /* This is a copy; modifications are not visible to our caller. */
12162 CUMULATIVE_ARGS copy_cum = *orig_cum;
12163 CUMULATIVE_ARGS *cum = ©_cum;
12165 /* Pad to 16 byte boundary if needed. */
12166 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
12167 && (cum->words % 2) != 0)
12170 cum->intoffset = 0;
12171 cum->use_stack = 0;
12172 cum->named = named;
12174 /* Put entries into rvec[] for individual FP and vector fields, and
12175 for the chunks of memory that go in int regs. Note we start at
12176 element 1; 0 is reserved for an indication of using memory, and
12177 may or may not be filled in below. */
12178 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
12179 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
12181 /* If any part of the struct went on the stack put all of it there.
12182 This hack is because the generic code for
12183 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
12184 parts of the struct are not at the beginning. */
12185 if (cum->use_stack)
12188 return NULL_RTX; /* doesn't go in registers at all */
12190 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12192 if (k > 1 || cum->use_stack)
12193 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
12198 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
12201 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
12206 rtx rvec[GP_ARG_NUM_REG + 1];
12208 if (align_words >= GP_ARG_NUM_REG)
12211 n_units = rs6000_arg_size (mode, type);
12213 /* Optimize the simple case where the arg fits in one gpr, except in
12214 the case of BLKmode due to assign_parms assuming that registers are
12215 BITS_PER_WORD wide. */
12217 || (n_units == 1 && mode != BLKmode))
12218 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12221 if (align_words + n_units > GP_ARG_NUM_REG)
12222 /* Not all of the arg fits in gprs. Say that it goes in memory too,
12223 using a magic NULL_RTX component.
12224 This is not strictly correct. Only some of the arg belongs in
12225 memory, not all of it. However, the normal scheme using
12226 function_arg_partial_nregs can result in unusual subregs, eg.
12227 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12228 store the whole arg to memory is often more efficient than code
12229 to store pieces, and we know that space is available in the right
12230 place for the whole arg. */
12231 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12236 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
12237 rtx off = GEN_INT (i++ * 4);
12238 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12240 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
12242 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12245 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12246 but must also be copied into the parameter save area starting at
12247 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12248 to the GPRs and/or memory. Return the number of elements used. */
12251 rs6000_psave_function_arg (machine_mode mode, const_tree type,
12252 int align_words, rtx *rvec)
12256 if (align_words < GP_ARG_NUM_REG)
12258 int n_words = rs6000_arg_size (mode, type);
12260 if (align_words + n_words > GP_ARG_NUM_REG
12262 || (TARGET_32BIT && TARGET_POWERPC64))
12264 /* If this is partially on the stack, then we only
12265 include the portion actually in registers here. */
12266 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12269 if (align_words + n_words > GP_ARG_NUM_REG)
12271 /* Not all of the arg fits in gprs. Say that it goes in memory
12272 too, using a magic NULL_RTX component. Also see comment in
12273 rs6000_mixed_function_arg for why the normal
12274 function_arg_partial_nregs scheme doesn't work in this case. */
12275 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12280 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12281 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
12282 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12284 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12288 /* The whole arg fits in gprs. */
12289 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12290 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
12295 /* It's entirely in memory. */
12296 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12302 /* RVEC is a vector of K components of an argument of mode MODE.
12303 Construct the final function_arg return value from it. */
12306 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
12308 gcc_assert (k >= 1);
12310 /* Avoid returning a PARALLEL in the trivial cases. */
12313 if (XEXP (rvec[0], 0) == NULL_RTX)
12316 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
12317 return XEXP (rvec[0], 0);
12320 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12323 /* Determine where to put an argument to a function.
12324 Value is zero to push the argument on the stack,
12325 or a hard register in which to store the argument.
12327 MODE is the argument's machine mode.
12328 TYPE is the data type of the argument (as a tree).
12329 This is null for libcalls where that information may
12331 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12332 the preceding args and about the function being called. It is
12333 not modified in this routine.
12334 NAMED is nonzero if this argument is a named parameter
12335 (otherwise it is an extra parameter matching an ellipsis).
12337 On RS/6000 the first eight words of non-FP are normally in registers
12338 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12339 Under V.4, the first 8 FP args are in registers.
12341 If this is floating-point and no prototype is specified, we use
12342 both an FP and integer register (or possibly FP reg and stack). Library
12343 functions (when CALL_LIBCALL is set) always have the proper types for args,
12344 so we can pass the FP value just in one register. emit_library_function
12345 doesn't support PARALLEL anyway.
12347 Note that for args passed by reference, function_arg will be called
12348 with MODE and TYPE set to that of the pointer to the arg, not the arg
12352 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
12353 const_tree type, bool named)
12355 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12356 enum rs6000_abi abi = DEFAULT_ABI;
12357 machine_mode elt_mode;
12360 /* Return a marker to indicate whether CR1 needs to set or clear the
12361 bit that V.4 uses to say fp args were passed in registers.
12362 Assume that we don't need the marker for software floating point,
12363 or compiler generated library calls. */
12364 if (mode == VOIDmode)
12367 && (cum->call_cookie & CALL_LIBCALL) == 0
12369 || (cum->nargs_prototype < 0
12370 && (cum->prototype || TARGET_NO_PROTOTYPE)))
12371 && TARGET_HARD_FLOAT)
12372 return GEN_INT (cum->call_cookie
12373 | ((cum->fregno == FP_ARG_MIN_REG)
12374 ? CALL_V4_SET_FP_ARGS
12375 : CALL_V4_CLEAR_FP_ARGS));
12377 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
12380 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12382 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12384 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
12385 if (rslt != NULL_RTX)
12387 /* Else fall through to usual handling. */
12390 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12392 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12396 /* Do we also need to pass this argument in the parameter save area?
12397 Library support functions for IEEE 128-bit are assumed to not need the
12398 value passed both in GPRs and in vector registers. */
12399 if (TARGET_64BIT && !cum->prototype
12400 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12402 int align_words = ROUND_UP (cum->words, 2);
12403 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12406 /* Describe where this argument goes in the vector registers. */
12407 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
12409 r = gen_rtx_REG (elt_mode, cum->vregno + i);
12410 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12411 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12414 return rs6000_finish_function_arg (mode, rvec, k);
12416 else if (TARGET_ALTIVEC_ABI
12417 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
12418 || (type && TREE_CODE (type) == VECTOR_TYPE
12419 && int_size_in_bytes (type) == 16)))
12421 if (named || abi == ABI_V4)
12425 /* Vector parameters to varargs functions under AIX or Darwin
12426 get passed in memory and possibly also in GPRs. */
12427 int align, align_words, n_words;
12428 machine_mode part_mode;
12430 /* Vector parameters must be 16-byte aligned. In 32-bit
12431 mode this means we need to take into account the offset
12432 to the parameter save area. In 64-bit mode, they just
12433 have to start on an even word, since the parameter save
12434 area is 16-byte aligned. */
12436 align = -(rs6000_parm_offset () + cum->words) & 3;
12438 align = cum->words & 1;
12439 align_words = cum->words + align;
12441 /* Out of registers? Memory, then. */
12442 if (align_words >= GP_ARG_NUM_REG)
12445 if (TARGET_32BIT && TARGET_POWERPC64)
12446 return rs6000_mixed_function_arg (mode, type, align_words);
12448 /* The vector value goes in GPRs. Only the part of the
12449 value in GPRs is reported here. */
12451 n_words = rs6000_arg_size (mode, type);
12452 if (align_words + n_words > GP_ARG_NUM_REG)
12453 /* Fortunately, there are only two possibilities, the value
12454 is either wholly in GPRs or half in GPRs and half not. */
12455 part_mode = DImode;
12457 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
12461 else if (abi == ABI_V4)
12463 if (abi_v4_pass_in_fpr (mode))
12465 /* _Decimal128 must use an even/odd register pair. This assumes
12466 that the register number is odd when fregno is odd. */
12467 if (mode == TDmode && (cum->fregno % 2) == 1)
12470 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
12471 <= FP_ARG_V4_MAX_REG)
12472 return gen_rtx_REG (mode, cum->fregno);
12478 int n_words = rs6000_arg_size (mode, type);
12479 int gregno = cum->sysv_gregno;
12481 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12482 As does any other 2 word item such as complex int due to a
12483 historical mistake. */
12485 gregno += (1 - gregno) & 1;
12487 /* Multi-reg args are not split between registers and stack. */
12488 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
12491 if (TARGET_32BIT && TARGET_POWERPC64)
12492 return rs6000_mixed_function_arg (mode, type,
12493 gregno - GP_ARG_MIN_REG);
12494 return gen_rtx_REG (mode, gregno);
12499 int align_words = rs6000_parm_start (mode, type, cum->words);
12501 /* _Decimal128 must be passed in an even/odd float register pair.
12502 This assumes that the register number is odd when fregno is odd. */
12503 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12506 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12508 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12511 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12514 /* Do we also need to pass this argument in the parameter
12516 if (type && (cum->nargs_prototype <= 0
12517 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12518 && TARGET_XL_COMPAT
12519 && align_words >= GP_ARG_NUM_REG)))
12520 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12522 /* Describe where this argument goes in the fprs. */
12523 for (i = 0; i < n_elts
12524 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
12526 /* Check if the argument is split over registers and memory.
12527 This can only ever happen for long double or _Decimal128;
12528 complex types are handled via split_complex_arg. */
12529 machine_mode fmode = elt_mode;
12530 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
12532 gcc_assert (FLOAT128_2REG_P (fmode));
12533 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
12536 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
12537 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12538 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12541 /* If there were not enough FPRs to hold the argument, the rest
12542 usually goes into memory. However, if the current position
12543 is still within the register parameter area, a portion may
12544 actually have to go into GPRs.
12546 Note that it may happen that the portion of the argument
12547 passed in the first "half" of the first GPR was already
12548 passed in the last FPR as well.
12550 For unnamed arguments, we already set up GPRs to cover the
12551 whole argument in rs6000_psave_function_arg, so there is
12552 nothing further to do at this point. */
12553 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
12554 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
12555 && cum->nargs_prototype > 0)
12557 static bool warned;
12559 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12560 int n_words = rs6000_arg_size (mode, type);
12562 align_words += fpr_words;
12563 n_words -= fpr_words;
12567 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12568 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
12569 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12571 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12573 if (!warned && warn_psabi)
12576 inform (input_location,
12577 "the ABI of passing homogeneous float aggregates"
12578 " has changed in GCC 5");
12582 return rs6000_finish_function_arg (mode, rvec, k);
12584 else if (align_words < GP_ARG_NUM_REG)
12586 if (TARGET_32BIT && TARGET_POWERPC64)
12587 return rs6000_mixed_function_arg (mode, type, align_words);
12589 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12596 /* For an arg passed partly in registers and partly in memory, this is
12597 the number of bytes passed in registers. For args passed entirely in
12598 registers or entirely in memory, zero. When an arg is described by a
12599 PARALLEL, perhaps using more than one register type, this function
12600 returns the number of bytes used by the first element of the PARALLEL. */
12603 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
12604 tree type, bool named)
12606 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12607 bool passed_in_gprs = true;
12610 machine_mode elt_mode;
12613 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12615 if (DEFAULT_ABI == ABI_V4)
12618 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12620 /* If we are passing this arg in the fixed parameter save area (gprs or
12621 memory) as well as VRs, we do not use the partial bytes mechanism;
12622 instead, rs6000_function_arg will return a PARALLEL including a memory
12623 element as necessary. Library support functions for IEEE 128-bit are
12624 assumed to not need the value passed both in GPRs and in vector
12626 if (TARGET_64BIT && !cum->prototype
12627 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12630 /* Otherwise, we pass in VRs only. Check for partial copies. */
12631 passed_in_gprs = false;
12632 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12633 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12636 /* In this complicated case we just disable the partial_nregs code. */
12637 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12640 align_words = rs6000_parm_start (mode, type, cum->words);
12642 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12644 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12646 /* If we are passing this arg in the fixed parameter save area
12647 (gprs or memory) as well as FPRs, we do not use the partial
12648 bytes mechanism; instead, rs6000_function_arg will return a
12649 PARALLEL including a memory element as necessary. */
12651 && (cum->nargs_prototype <= 0
12652 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12653 && TARGET_XL_COMPAT
12654 && align_words >= GP_ARG_NUM_REG)))
12657 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12658 passed_in_gprs = false;
12659 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12661 /* Compute number of bytes / words passed in FPRs. If there
12662 is still space available in the register parameter area
12663 *after* that amount, a part of the argument will be passed
12664 in GPRs. In that case, the total amount passed in any
12665 registers is equal to the amount that would have been passed
12666 in GPRs if everything were passed there, so we fall back to
12667 the GPR code below to compute the appropriate value. */
12668 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12669 * MIN (8, GET_MODE_SIZE (elt_mode)));
12670 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12672 if (align_words + fpr_words < GP_ARG_NUM_REG)
12673 passed_in_gprs = true;
12680 && align_words < GP_ARG_NUM_REG
12681 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12682 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12684 if (ret != 0 && TARGET_DEBUG_ARG)
12685 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12690 /* A C expression that indicates when an argument must be passed by
12691 reference. If nonzero for an argument, a copy of that argument is
12692 made in memory and a pointer to the argument is passed instead of
12693 the argument itself. The pointer is passed in whatever way is
12694 appropriate for passing a pointer to that type.
12696 Under V.4, aggregates and long double are passed by reference.
12698 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12699 reference unless the AltiVec vector extension ABI is in force.
12701 As an extension to all ABIs, variable sized types are passed by
12705 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12706 machine_mode mode, const_tree type,
12707 bool named ATTRIBUTE_UNUSED)
12712 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12713 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12715 if (TARGET_DEBUG_ARG)
12716 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12720 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12722 if (TARGET_DEBUG_ARG)
12723 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12727 if (int_size_in_bytes (type) < 0)
12729 if (TARGET_DEBUG_ARG)
12730 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12734 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12735 modes only exist for GCC vector types if -maltivec. */
12736 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12738 if (TARGET_DEBUG_ARG)
12739 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12743 /* Pass synthetic vectors in memory. */
12744 if (TREE_CODE (type) == VECTOR_TYPE
12745 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12747 static bool warned_for_pass_big_vectors = false;
12748 if (TARGET_DEBUG_ARG)
12749 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12750 if (!warned_for_pass_big_vectors)
12752 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12753 "non-standard ABI extension with no compatibility "
12755 warned_for_pass_big_vectors = true;
12763 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12764 already processes. Return true if the parameter must be passed
12765 (fully or partially) on the stack. */
12768 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12774 /* Catch errors. */
12775 if (type == NULL || type == error_mark_node)
12778 /* Handle types with no storage requirement. */
12779 if (TYPE_MODE (type) == VOIDmode)
12782 /* Handle complex types. */
12783 if (TREE_CODE (type) == COMPLEX_TYPE)
12784 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12785 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12787 /* Handle transparent aggregates. */
12788 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12789 && TYPE_TRANSPARENT_AGGR (type))
12790 type = TREE_TYPE (first_field (type));
12792 /* See if this arg was passed by invisible reference. */
12793 if (pass_by_reference (get_cumulative_args (args_so_far),
12794 TYPE_MODE (type), type, true))
12795 type = build_pointer_type (type);
12797 /* Find mode as it is passed by the ABI. */
12798 unsignedp = TYPE_UNSIGNED (type);
12799 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12801 /* If we must pass in stack, we need a stack. */
12802 if (rs6000_must_pass_in_stack (mode, type))
12805 /* If there is no incoming register, we need a stack. */
12806 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12807 if (entry_parm == NULL)
12810 /* Likewise if we need to pass both in registers and on the stack. */
12811 if (GET_CODE (entry_parm) == PARALLEL
12812 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12815 /* Also true if we're partially in registers and partially not. */
12816 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12819 /* Update info on where next arg arrives in registers. */
12820 rs6000_function_arg_advance (args_so_far, mode, type, true);
12824 /* Return true if FUN has no prototype, has a variable argument
12825 list, or passes any parameter in memory. */
12828 rs6000_function_parms_need_stack (tree fun, bool incoming)
12830 tree fntype, result;
12831 CUMULATIVE_ARGS args_so_far_v;
12832 cumulative_args_t args_so_far;
12835 /* Must be a libcall, all of which only use reg parms. */
12840 fntype = TREE_TYPE (fun);
12842 /* Varargs functions need the parameter save area. */
12843 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12846 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12847 args_so_far = pack_cumulative_args (&args_so_far_v);
12849 /* When incoming, we will have been passed the function decl.
12850 It is necessary to use the decl to handle K&R style functions,
12851 where TYPE_ARG_TYPES may not be available. */
12854 gcc_assert (DECL_P (fun));
12855 result = DECL_RESULT (fun);
12858 result = TREE_TYPE (fntype);
12860 if (result && aggregate_value_p (result, fntype))
12862 if (!TYPE_P (result))
12863 result = TREE_TYPE (result);
12864 result = build_pointer_type (result);
12865 rs6000_parm_needs_stack (args_so_far, result);
12872 for (parm = DECL_ARGUMENTS (fun);
12873 parm && parm != void_list_node;
12874 parm = TREE_CHAIN (parm))
12875 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12880 function_args_iterator args_iter;
12883 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12884 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12891 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12892 usually a constant depending on the ABI. However, in the ELFv2 ABI
12893 the register parameter area is optional when calling a function that
12894 has a prototype is scope, has no variable argument list, and passes
12895 all parameters in registers. */
12898 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12900 int reg_parm_stack_space;
12902 switch (DEFAULT_ABI)
12905 reg_parm_stack_space = 0;
12910 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12914 /* ??? Recomputing this every time is a bit expensive. Is there
12915 a place to cache this information? */
12916 if (rs6000_function_parms_need_stack (fun, incoming))
12917 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12919 reg_parm_stack_space = 0;
12923 return reg_parm_stack_space;
12927 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12930 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12935 for (i = 0; i < nregs; i++)
12937 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12938 if (reload_completed)
12940 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12943 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12944 i * GET_MODE_SIZE (reg_mode));
12947 tem = replace_equiv_address (tem, XEXP (tem, 0));
12951 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12955 /* Perform any needed actions needed for a function that is receiving a
12956 variable number of arguments.
12960 MODE and TYPE are the mode and type of the current parameter.
12962 PRETEND_SIZE is a variable that should be set to the amount of stack
12963 that must be pushed by the prolog to pretend that our caller pushed
12966 Normally, this macro will push all remaining incoming registers on the
12967 stack and set PRETEND_SIZE to the length of the registers pushed. */
12970 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12971 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12974 CUMULATIVE_ARGS next_cum;
12975 int reg_size = TARGET_32BIT ? 4 : 8;
12976 rtx save_area = NULL_RTX, mem;
12977 int first_reg_offset;
12978 alias_set_type set;
12980 /* Skip the last named argument. */
12981 next_cum = *get_cumulative_args (cum);
12982 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12984 if (DEFAULT_ABI == ABI_V4)
12986 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12990 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12991 HOST_WIDE_INT offset = 0;
12993 /* Try to optimize the size of the varargs save area.
12994 The ABI requires that ap.reg_save_area is doubleword
12995 aligned, but we don't need to allocate space for all
12996 the bytes, only those to which we actually will save
12998 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12999 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
13000 if (TARGET_HARD_FLOAT
13001 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13002 && cfun->va_list_fpr_size)
13005 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
13006 * UNITS_PER_FP_WORD;
13007 if (cfun->va_list_fpr_size
13008 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13009 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
13011 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13012 * UNITS_PER_FP_WORD;
13016 offset = -((first_reg_offset * reg_size) & ~7);
13017 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
13019 gpr_reg_num = cfun->va_list_gpr_size;
13020 if (reg_size == 4 && (first_reg_offset & 1))
13023 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
13026 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
13027 * UNITS_PER_FP_WORD
13028 - (int) (GP_ARG_NUM_REG * reg_size);
13030 if (gpr_size + fpr_size)
13033 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
13034 gcc_assert (GET_CODE (reg_save_area) == MEM);
13035 reg_save_area = XEXP (reg_save_area, 0);
13036 if (GET_CODE (reg_save_area) == PLUS)
13038 gcc_assert (XEXP (reg_save_area, 0)
13039 == virtual_stack_vars_rtx);
13040 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
13041 offset += INTVAL (XEXP (reg_save_area, 1));
13044 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
13047 cfun->machine->varargs_save_offset = offset;
13048 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
13053 first_reg_offset = next_cum.words;
13054 save_area = crtl->args.internal_arg_pointer;
13056 if (targetm.calls.must_pass_in_stack (mode, type))
13057 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
13060 set = get_varargs_alias_set ();
13061 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
13062 && cfun->va_list_gpr_size)
13064 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
13066 if (va_list_gpr_counter_field)
13067 /* V4 va_list_gpr_size counts number of registers needed. */
13068 n_gpr = cfun->va_list_gpr_size;
13070 /* char * va_list instead counts number of bytes needed. */
13071 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
13076 mem = gen_rtx_MEM (BLKmode,
13077 plus_constant (Pmode, save_area,
13078 first_reg_offset * reg_size));
13079 MEM_NOTRAP_P (mem) = 1;
13080 set_mem_alias_set (mem, set);
13081 set_mem_align (mem, BITS_PER_WORD);
13083 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
13087 /* Save FP registers if needed. */
13088 if (DEFAULT_ABI == ABI_V4
13089 && TARGET_HARD_FLOAT
13091 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13092 && cfun->va_list_fpr_size)
13094 int fregno = next_cum.fregno, nregs;
13095 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
13096 rtx lab = gen_label_rtx ();
13097 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
13098 * UNITS_PER_FP_WORD);
13101 (gen_rtx_SET (pc_rtx,
13102 gen_rtx_IF_THEN_ELSE (VOIDmode,
13103 gen_rtx_NE (VOIDmode, cr1,
13105 gen_rtx_LABEL_REF (VOIDmode, lab),
13109 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
13110 fregno++, off += UNITS_PER_FP_WORD, nregs++)
13112 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13114 plus_constant (Pmode, save_area, off));
13115 MEM_NOTRAP_P (mem) = 1;
13116 set_mem_alias_set (mem, set);
13117 set_mem_align (mem, GET_MODE_ALIGNMENT (
13118 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13119 ? DFmode : SFmode));
13120 emit_move_insn (mem, gen_rtx_REG (
13121 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13122 ? DFmode : SFmode, fregno));
13129 /* Create the va_list data type. */
13132 rs6000_build_builtin_va_list (void)
13134 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
13136 /* For AIX, prefer 'char *' because that's what the system
13137 header files like. */
13138 if (DEFAULT_ABI != ABI_V4)
13139 return build_pointer_type (char_type_node);
13141 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
13142 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
13143 get_identifier ("__va_list_tag"), record);
13145 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
13146 unsigned_char_type_node);
13147 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
13148 unsigned_char_type_node);
13149 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
13150 every user file. */
13151 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13152 get_identifier ("reserved"), short_unsigned_type_node);
13153 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13154 get_identifier ("overflow_arg_area"),
13156 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13157 get_identifier ("reg_save_area"),
13160 va_list_gpr_counter_field = f_gpr;
13161 va_list_fpr_counter_field = f_fpr;
13163 DECL_FIELD_CONTEXT (f_gpr) = record;
13164 DECL_FIELD_CONTEXT (f_fpr) = record;
13165 DECL_FIELD_CONTEXT (f_res) = record;
13166 DECL_FIELD_CONTEXT (f_ovf) = record;
13167 DECL_FIELD_CONTEXT (f_sav) = record;
13169 TYPE_STUB_DECL (record) = type_decl;
13170 TYPE_NAME (record) = type_decl;
13171 TYPE_FIELDS (record) = f_gpr;
13172 DECL_CHAIN (f_gpr) = f_fpr;
13173 DECL_CHAIN (f_fpr) = f_res;
13174 DECL_CHAIN (f_res) = f_ovf;
13175 DECL_CHAIN (f_ovf) = f_sav;
13177 layout_type (record);
13179 /* The correct type is an array type of one element. */
13180 return build_array_type (record, build_index_type (size_zero_node));
13183 /* Implement va_start. */
13186 rs6000_va_start (tree valist, rtx nextarg)
13188 HOST_WIDE_INT words, n_gpr, n_fpr;
13189 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13190 tree gpr, fpr, ovf, sav, t;
13192 /* Only SVR4 needs something special. */
13193 if (DEFAULT_ABI != ABI_V4)
13195 std_expand_builtin_va_start (valist, nextarg);
13199 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13200 f_fpr = DECL_CHAIN (f_gpr);
13201 f_res = DECL_CHAIN (f_fpr);
13202 f_ovf = DECL_CHAIN (f_res);
13203 f_sav = DECL_CHAIN (f_ovf);
13205 valist = build_simple_mem_ref (valist);
13206 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13207 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13209 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13211 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13214 /* Count number of gp and fp argument registers used. */
13215 words = crtl->args.info.words;
13216 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
13218 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
13221 if (TARGET_DEBUG_ARG)
13222 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
13223 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
13224 words, n_gpr, n_fpr);
13226 if (cfun->va_list_gpr_size)
13228 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
13229 build_int_cst (NULL_TREE, n_gpr));
13230 TREE_SIDE_EFFECTS (t) = 1;
13231 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13234 if (cfun->va_list_fpr_size)
13236 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
13237 build_int_cst (NULL_TREE, n_fpr));
13238 TREE_SIDE_EFFECTS (t) = 1;
13239 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13241 #ifdef HAVE_AS_GNU_ATTRIBUTE
13242 if (call_ABI_of_interest (cfun->decl))
13243 rs6000_passes_float = true;
13247 /* Find the overflow area. */
13248 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
13250 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
13251 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
13252 TREE_SIDE_EFFECTS (t) = 1;
13253 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13255 /* If there were no va_arg invocations, don't set up the register
13257 if (!cfun->va_list_gpr_size
13258 && !cfun->va_list_fpr_size
13259 && n_gpr < GP_ARG_NUM_REG
13260 && n_fpr < FP_ARG_V4_MAX_REG)
13263 /* Find the register save area. */
13264 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
13265 if (cfun->machine->varargs_save_offset)
13266 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
13267 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
13268 TREE_SIDE_EFFECTS (t) = 1;
13269 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13272 /* Implement va_arg. */
13275 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
13276 gimple_seq *post_p)
13278 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13279 tree gpr, fpr, ovf, sav, reg, t, u;
13280 int size, rsize, n_reg, sav_ofs, sav_scale;
13281 tree lab_false, lab_over, addr;
13283 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
13287 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
13289 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
13290 return build_va_arg_indirect_ref (t);
13293 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13294 earlier version of gcc, with the property that it always applied alignment
13295 adjustments to the va-args (even for zero-sized types). The cheapest way
13296 to deal with this is to replicate the effect of the part of
13297 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13299 We don't need to check for pass-by-reference because of the test above.
13300 We can return a simplifed answer, since we know there's no offset to add. */
13303 && rs6000_darwin64_abi)
13304 || DEFAULT_ABI == ABI_ELFv2
13305 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
13306 && integer_zerop (TYPE_SIZE (type)))
13308 unsigned HOST_WIDE_INT align, boundary;
13309 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
13310 align = PARM_BOUNDARY / BITS_PER_UNIT;
13311 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
13312 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
13313 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
13314 boundary /= BITS_PER_UNIT;
13315 if (boundary > align)
13318 /* This updates arg ptr by the amount that would be necessary
13319 to align the zero-sized (but not zero-alignment) item. */
13320 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13321 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
13322 gimplify_and_add (t, pre_p);
13324 t = fold_convert (sizetype, valist_tmp);
13325 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13326 fold_convert (TREE_TYPE (valist),
13327 fold_build2 (BIT_AND_EXPR, sizetype, t,
13328 size_int (-boundary))));
13329 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
13330 gimplify_and_add (t, pre_p);
13332 /* Since it is zero-sized there's no increment for the item itself. */
13333 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
13334 return build_va_arg_indirect_ref (valist_tmp);
13337 if (DEFAULT_ABI != ABI_V4)
13339 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
13341 tree elem_type = TREE_TYPE (type);
13342 machine_mode elem_mode = TYPE_MODE (elem_type);
13343 int elem_size = GET_MODE_SIZE (elem_mode);
13345 if (elem_size < UNITS_PER_WORD)
13347 tree real_part, imag_part;
13348 gimple_seq post = NULL;
13350 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13352 /* Copy the value into a temporary, lest the formal temporary
13353 be reused out from under us. */
13354 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
13355 gimple_seq_add_seq (pre_p, post);
13357 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13360 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
13364 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
13367 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13368 f_fpr = DECL_CHAIN (f_gpr);
13369 f_res = DECL_CHAIN (f_fpr);
13370 f_ovf = DECL_CHAIN (f_res);
13371 f_sav = DECL_CHAIN (f_ovf);
13373 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13374 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13376 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13378 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13381 size = int_size_in_bytes (type);
13382 rsize = (size + 3) / 4;
13383 int pad = 4 * rsize - size;
13386 machine_mode mode = TYPE_MODE (type);
13387 if (abi_v4_pass_in_fpr (mode))
13389 /* FP args go in FP registers, if present. */
13391 n_reg = (size + 7) / 8;
13392 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
13393 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
13394 if (mode != SFmode && mode != SDmode)
13399 /* Otherwise into GP registers. */
13408 /* Pull the value out of the saved registers.... */
13411 addr = create_tmp_var (ptr_type_node, "addr");
13413 /* AltiVec vectors never go in registers when -mabi=altivec. */
13414 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13418 lab_false = create_artificial_label (input_location);
13419 lab_over = create_artificial_label (input_location);
13421 /* Long long is aligned in the registers. As are any other 2 gpr
13422 item such as complex int due to a historical mistake. */
13424 if (n_reg == 2 && reg == gpr)
13427 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13428 build_int_cst (TREE_TYPE (reg), n_reg - 1));
13429 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
13430 unshare_expr (reg), u);
13432 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13433 reg number is 0 for f1, so we want to make it odd. */
13434 else if (reg == fpr && mode == TDmode)
13436 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13437 build_int_cst (TREE_TYPE (reg), 1));
13438 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
13441 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
13442 t = build2 (GE_EXPR, boolean_type_node, u, t);
13443 u = build1 (GOTO_EXPR, void_type_node, lab_false);
13444 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
13445 gimplify_and_add (t, pre_p);
13449 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
13451 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13452 build_int_cst (TREE_TYPE (reg), n_reg));
13453 u = fold_convert (sizetype, u);
13454 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
13455 t = fold_build_pointer_plus (t, u);
13457 /* _Decimal32 varargs are located in the second word of the 64-bit
13458 FP register for 32-bit binaries. */
13459 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
13460 t = fold_build_pointer_plus_hwi (t, size);
13462 /* Args are passed right-aligned. */
13463 if (BYTES_BIG_ENDIAN)
13464 t = fold_build_pointer_plus_hwi (t, pad);
13466 gimplify_assign (addr, t, pre_p);
13468 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
13470 stmt = gimple_build_label (lab_false);
13471 gimple_seq_add_stmt (pre_p, stmt);
13473 if ((n_reg == 2 && !regalign) || n_reg > 2)
13475 /* Ensure that we don't find any more args in regs.
13476 Alignment has taken care of for special cases. */
13477 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
13481 /* ... otherwise out of the overflow area. */
13483 /* Care for on-stack alignment if needed. */
13487 t = fold_build_pointer_plus_hwi (t, align - 1);
13488 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
13489 build_int_cst (TREE_TYPE (t), -align));
13492 /* Args are passed right-aligned. */
13493 if (BYTES_BIG_ENDIAN)
13494 t = fold_build_pointer_plus_hwi (t, pad);
13496 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
13498 gimplify_assign (unshare_expr (addr), t, pre_p);
13500 t = fold_build_pointer_plus_hwi (t, size);
13501 gimplify_assign (unshare_expr (ovf), t, pre_p);
13505 stmt = gimple_build_label (lab_over);
13506 gimple_seq_add_stmt (pre_p, stmt);
13509 if (STRICT_ALIGNMENT
13510 && (TYPE_ALIGN (type)
13511 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
13513 /* The value (of type complex double, for example) may not be
13514 aligned in memory in the saved registers, so copy via a
13515 temporary. (This is the same code as used for SPARC.) */
13516 tree tmp = create_tmp_var (type, "va_arg_tmp");
13517 tree dest_addr = build_fold_addr_expr (tmp);
13519 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
13520 3, dest_addr, addr, size_int (rsize * 4));
13522 gimplify_and_add (copy, pre_p);
13526 addr = fold_convert (ptrtype, addr);
13527 return build_va_arg_indirect_ref (addr);
13533 def_builtin (const char *name, tree type, enum rs6000_builtins code)
13536 unsigned classify = rs6000_builtin_info[(int)code].attr;
13537 const char *attr_string = "";
13539 gcc_assert (name != NULL);
13540 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
13542 if (rs6000_builtin_decls[(int)code])
13543 fatal_error (input_location,
13544 "internal error: builtin function %qs already processed",
13547 rs6000_builtin_decls[(int)code] = t =
13548 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
13550 /* Set any special attributes. */
13551 if ((classify & RS6000_BTC_CONST) != 0)
13553 /* const function, function only depends on the inputs. */
13554 TREE_READONLY (t) = 1;
13555 TREE_NOTHROW (t) = 1;
13556 attr_string = ", const";
13558 else if ((classify & RS6000_BTC_PURE) != 0)
13560 /* pure function, function can read global memory, but does not set any
13562 DECL_PURE_P (t) = 1;
13563 TREE_NOTHROW (t) = 1;
13564 attr_string = ", pure";
13566 else if ((classify & RS6000_BTC_FP) != 0)
13568 /* Function is a math function. If rounding mode is on, then treat the
13569 function as not reading global memory, but it can have arbitrary side
13570 effects. If it is off, then assume the function is a const function.
13571 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13572 builtin-attribute.def that is used for the math functions. */
13573 TREE_NOTHROW (t) = 1;
13574 if (flag_rounding_math)
13576 DECL_PURE_P (t) = 1;
13577 DECL_IS_NOVOPS (t) = 1;
13578 attr_string = ", fp, pure";
13582 TREE_READONLY (t) = 1;
13583 attr_string = ", fp, const";
13586 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
13587 gcc_unreachable ();
13589 if (TARGET_DEBUG_BUILTIN)
13590 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
13591 (int)code, name, attr_string);
13594 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13596 #undef RS6000_BUILTIN_0
13597 #undef RS6000_BUILTIN_1
13598 #undef RS6000_BUILTIN_2
13599 #undef RS6000_BUILTIN_3
13600 #undef RS6000_BUILTIN_A
13601 #undef RS6000_BUILTIN_D
13602 #undef RS6000_BUILTIN_H
13603 #undef RS6000_BUILTIN_P
13604 #undef RS6000_BUILTIN_Q
13605 #undef RS6000_BUILTIN_X
13607 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13608 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13609 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13610 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13611 { MASK, ICODE, NAME, ENUM },
13613 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13614 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13615 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13616 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13617 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13618 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13620 static const struct builtin_description bdesc_3arg[] =
13622 #include "rs6000-builtin.def"
13625 /* DST operations: void foo (void *, const int, const char). */
13627 #undef RS6000_BUILTIN_0
13628 #undef RS6000_BUILTIN_1
13629 #undef RS6000_BUILTIN_2
13630 #undef RS6000_BUILTIN_3
13631 #undef RS6000_BUILTIN_A
13632 #undef RS6000_BUILTIN_D
13633 #undef RS6000_BUILTIN_H
13634 #undef RS6000_BUILTIN_P
13635 #undef RS6000_BUILTIN_Q
13636 #undef RS6000_BUILTIN_X
13638 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13639 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13640 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13641 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13642 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13643 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13644 { MASK, ICODE, NAME, ENUM },
13646 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13647 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13648 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13649 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13651 static const struct builtin_description bdesc_dst[] =
13653 #include "rs6000-builtin.def"
13656 /* Simple binary operations: VECc = foo (VECa, VECb). */
13658 #undef RS6000_BUILTIN_0
13659 #undef RS6000_BUILTIN_1
13660 #undef RS6000_BUILTIN_2
13661 #undef RS6000_BUILTIN_3
13662 #undef RS6000_BUILTIN_A
13663 #undef RS6000_BUILTIN_D
13664 #undef RS6000_BUILTIN_H
13665 #undef RS6000_BUILTIN_P
13666 #undef RS6000_BUILTIN_Q
13667 #undef RS6000_BUILTIN_X
13669 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13670 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13671 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13672 { MASK, ICODE, NAME, ENUM },
13674 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13675 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13676 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13677 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13678 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13679 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13680 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13682 static const struct builtin_description bdesc_2arg[] =
13684 #include "rs6000-builtin.def"
13687 #undef RS6000_BUILTIN_0
13688 #undef RS6000_BUILTIN_1
13689 #undef RS6000_BUILTIN_2
13690 #undef RS6000_BUILTIN_3
13691 #undef RS6000_BUILTIN_A
13692 #undef RS6000_BUILTIN_D
13693 #undef RS6000_BUILTIN_H
13694 #undef RS6000_BUILTIN_P
13695 #undef RS6000_BUILTIN_Q
13696 #undef RS6000_BUILTIN_X
13698 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13699 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13700 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13701 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13702 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13703 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13704 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13705 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13706 { MASK, ICODE, NAME, ENUM },
13708 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13709 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13711 /* AltiVec predicates. */
13713 static const struct builtin_description bdesc_altivec_preds[] =
13715 #include "rs6000-builtin.def"
13718 /* PAIRED predicates. */
13719 #undef RS6000_BUILTIN_0
13720 #undef RS6000_BUILTIN_1
13721 #undef RS6000_BUILTIN_2
13722 #undef RS6000_BUILTIN_3
13723 #undef RS6000_BUILTIN_A
13724 #undef RS6000_BUILTIN_D
13725 #undef RS6000_BUILTIN_H
13726 #undef RS6000_BUILTIN_P
13727 #undef RS6000_BUILTIN_Q
13728 #undef RS6000_BUILTIN_X
13730 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13731 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13732 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13733 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13734 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13735 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13736 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13737 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13738 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
13739 { MASK, ICODE, NAME, ENUM },
13741 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13743 static const struct builtin_description bdesc_paired_preds[] =
13745 #include "rs6000-builtin.def"
13748 /* ABS* operations. */
13750 #undef RS6000_BUILTIN_0
13751 #undef RS6000_BUILTIN_1
13752 #undef RS6000_BUILTIN_2
13753 #undef RS6000_BUILTIN_3
13754 #undef RS6000_BUILTIN_A
13755 #undef RS6000_BUILTIN_D
13756 #undef RS6000_BUILTIN_H
13757 #undef RS6000_BUILTIN_P
13758 #undef RS6000_BUILTIN_Q
13759 #undef RS6000_BUILTIN_X
13761 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13762 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13763 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13764 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13765 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13766 { MASK, ICODE, NAME, ENUM },
13768 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13769 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13770 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13771 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13772 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13774 static const struct builtin_description bdesc_abs[] =
13776 #include "rs6000-builtin.def"
13779 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13782 #undef RS6000_BUILTIN_0
13783 #undef RS6000_BUILTIN_1
13784 #undef RS6000_BUILTIN_2
13785 #undef RS6000_BUILTIN_3
13786 #undef RS6000_BUILTIN_A
13787 #undef RS6000_BUILTIN_D
13788 #undef RS6000_BUILTIN_H
13789 #undef RS6000_BUILTIN_P
13790 #undef RS6000_BUILTIN_Q
13791 #undef RS6000_BUILTIN_X
13793 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13794 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13795 { MASK, ICODE, NAME, ENUM },
13797 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13798 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13799 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13800 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13801 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13802 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13803 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13804 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13806 static const struct builtin_description bdesc_1arg[] =
13808 #include "rs6000-builtin.def"
13811 /* Simple no-argument operations: result = __builtin_darn_32 () */
13813 #undef RS6000_BUILTIN_0
13814 #undef RS6000_BUILTIN_1
13815 #undef RS6000_BUILTIN_2
13816 #undef RS6000_BUILTIN_3
13817 #undef RS6000_BUILTIN_A
13818 #undef RS6000_BUILTIN_D
13819 #undef RS6000_BUILTIN_H
13820 #undef RS6000_BUILTIN_P
13821 #undef RS6000_BUILTIN_Q
13822 #undef RS6000_BUILTIN_X
13824 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13825 { MASK, ICODE, NAME, ENUM },
13827 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13828 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13829 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13830 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13831 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13832 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13833 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13834 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13835 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13837 static const struct builtin_description bdesc_0arg[] =
13839 #include "rs6000-builtin.def"
13842 /* HTM builtins. */
13843 #undef RS6000_BUILTIN_0
13844 #undef RS6000_BUILTIN_1
13845 #undef RS6000_BUILTIN_2
13846 #undef RS6000_BUILTIN_3
13847 #undef RS6000_BUILTIN_A
13848 #undef RS6000_BUILTIN_D
13849 #undef RS6000_BUILTIN_H
13850 #undef RS6000_BUILTIN_P
13851 #undef RS6000_BUILTIN_Q
13852 #undef RS6000_BUILTIN_X
13854 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13855 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13856 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13857 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13858 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13859 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13860 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13861 { MASK, ICODE, NAME, ENUM },
13863 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13864 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13865 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13867 static const struct builtin_description bdesc_htm[] =
13869 #include "rs6000-builtin.def"
13872 #undef RS6000_BUILTIN_0
13873 #undef RS6000_BUILTIN_1
13874 #undef RS6000_BUILTIN_2
13875 #undef RS6000_BUILTIN_3
13876 #undef RS6000_BUILTIN_A
13877 #undef RS6000_BUILTIN_D
13878 #undef RS6000_BUILTIN_H
13879 #undef RS6000_BUILTIN_P
13880 #undef RS6000_BUILTIN_Q
13882 /* Return true if a builtin function is overloaded. */
13884 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13886 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13890 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13892 return rs6000_builtin_info[(int)fncode].name;
13895 /* Expand an expression EXP that calls a builtin without arguments. */
13897 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13900 machine_mode tmode = insn_data[icode].operand[0].mode;
13902 if (icode == CODE_FOR_nothing)
13903 /* Builtin not supported on this processor. */
13907 || GET_MODE (target) != tmode
13908 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13909 target = gen_reg_rtx (tmode);
13911 pat = GEN_FCN (icode) (target);
13921 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13924 tree arg0 = CALL_EXPR_ARG (exp, 0);
13925 tree arg1 = CALL_EXPR_ARG (exp, 1);
13926 rtx op0 = expand_normal (arg0);
13927 rtx op1 = expand_normal (arg1);
13928 machine_mode mode0 = insn_data[icode].operand[0].mode;
13929 machine_mode mode1 = insn_data[icode].operand[1].mode;
13931 if (icode == CODE_FOR_nothing)
13932 /* Builtin not supported on this processor. */
13935 /* If we got invalid arguments bail out before generating bad rtl. */
13936 if (arg0 == error_mark_node || arg1 == error_mark_node)
13939 if (GET_CODE (op0) != CONST_INT
13940 || INTVAL (op0) > 255
13941 || INTVAL (op0) < 0)
13943 error ("argument 1 must be an 8-bit field value");
13947 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13948 op0 = copy_to_mode_reg (mode0, op0);
13950 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13951 op1 = copy_to_mode_reg (mode1, op1);
13953 pat = GEN_FCN (icode) (op0, op1);
13962 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13965 tree arg0 = CALL_EXPR_ARG (exp, 0);
13966 rtx op0 = expand_normal (arg0);
13967 machine_mode tmode = insn_data[icode].operand[0].mode;
13968 machine_mode mode0 = insn_data[icode].operand[1].mode;
13970 if (icode == CODE_FOR_nothing)
13971 /* Builtin not supported on this processor. */
13974 /* If we got invalid arguments bail out before generating bad rtl. */
13975 if (arg0 == error_mark_node)
13978 if (icode == CODE_FOR_altivec_vspltisb
13979 || icode == CODE_FOR_altivec_vspltish
13980 || icode == CODE_FOR_altivec_vspltisw)
13982 /* Only allow 5-bit *signed* literals. */
13983 if (GET_CODE (op0) != CONST_INT
13984 || INTVAL (op0) > 15
13985 || INTVAL (op0) < -16)
13987 error ("argument 1 must be a 5-bit signed literal");
13988 return CONST0_RTX (tmode);
13993 || GET_MODE (target) != tmode
13994 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13995 target = gen_reg_rtx (tmode);
13997 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13998 op0 = copy_to_mode_reg (mode0, op0);
14000 pat = GEN_FCN (icode) (target, op0);
14009 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
14011 rtx pat, scratch1, scratch2;
14012 tree arg0 = CALL_EXPR_ARG (exp, 0);
14013 rtx op0 = expand_normal (arg0);
14014 machine_mode tmode = insn_data[icode].operand[0].mode;
14015 machine_mode mode0 = insn_data[icode].operand[1].mode;
14017 /* If we have invalid arguments, bail out before generating bad rtl. */
14018 if (arg0 == error_mark_node)
14022 || GET_MODE (target) != tmode
14023 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14024 target = gen_reg_rtx (tmode);
14026 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14027 op0 = copy_to_mode_reg (mode0, op0);
14029 scratch1 = gen_reg_rtx (mode0);
14030 scratch2 = gen_reg_rtx (mode0);
14032 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
14041 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
14044 tree arg0 = CALL_EXPR_ARG (exp, 0);
14045 tree arg1 = CALL_EXPR_ARG (exp, 1);
14046 rtx op0 = expand_normal (arg0);
14047 rtx op1 = expand_normal (arg1);
14048 machine_mode tmode = insn_data[icode].operand[0].mode;
14049 machine_mode mode0 = insn_data[icode].operand[1].mode;
14050 machine_mode mode1 = insn_data[icode].operand[2].mode;
14052 if (icode == CODE_FOR_nothing)
14053 /* Builtin not supported on this processor. */
14056 /* If we got invalid arguments bail out before generating bad rtl. */
14057 if (arg0 == error_mark_node || arg1 == error_mark_node)
14060 if (icode == CODE_FOR_altivec_vcfux
14061 || icode == CODE_FOR_altivec_vcfsx
14062 || icode == CODE_FOR_altivec_vctsxs
14063 || icode == CODE_FOR_altivec_vctuxs
14064 || icode == CODE_FOR_altivec_vspltb
14065 || icode == CODE_FOR_altivec_vsplth
14066 || icode == CODE_FOR_altivec_vspltw)
14068 /* Only allow 5-bit unsigned literals. */
14070 if (TREE_CODE (arg1) != INTEGER_CST
14071 || TREE_INT_CST_LOW (arg1) & ~0x1f)
14073 error ("argument 2 must be a 5-bit unsigned literal");
14074 return CONST0_RTX (tmode);
14077 else if (icode == CODE_FOR_dfptstsfi_eq_dd
14078 || icode == CODE_FOR_dfptstsfi_lt_dd
14079 || icode == CODE_FOR_dfptstsfi_gt_dd
14080 || icode == CODE_FOR_dfptstsfi_unordered_dd
14081 || icode == CODE_FOR_dfptstsfi_eq_td
14082 || icode == CODE_FOR_dfptstsfi_lt_td
14083 || icode == CODE_FOR_dfptstsfi_gt_td
14084 || icode == CODE_FOR_dfptstsfi_unordered_td)
14086 /* Only allow 6-bit unsigned literals. */
14088 if (TREE_CODE (arg0) != INTEGER_CST
14089 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
14091 error ("argument 1 must be a 6-bit unsigned literal");
14092 return CONST0_RTX (tmode);
14095 else if (icode == CODE_FOR_xststdcqp_kf
14096 || icode == CODE_FOR_xststdcqp_tf
14097 || icode == CODE_FOR_xststdcdp
14098 || icode == CODE_FOR_xststdcsp
14099 || icode == CODE_FOR_xvtstdcdp
14100 || icode == CODE_FOR_xvtstdcsp)
14102 /* Only allow 7-bit unsigned literals. */
14104 if (TREE_CODE (arg1) != INTEGER_CST
14105 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
14107 error ("argument 2 must be a 7-bit unsigned literal");
14108 return CONST0_RTX (tmode);
14111 else if (icode == CODE_FOR_unpackv1ti
14112 || icode == CODE_FOR_unpackkf
14113 || icode == CODE_FOR_unpacktf
14114 || icode == CODE_FOR_unpackif
14115 || icode == CODE_FOR_unpacktd)
14117 /* Only allow 1-bit unsigned literals. */
14119 if (TREE_CODE (arg1) != INTEGER_CST
14120 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
14122 error ("argument 2 must be a 1-bit unsigned literal");
14123 return CONST0_RTX (tmode);
14128 || GET_MODE (target) != tmode
14129 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14130 target = gen_reg_rtx (tmode);
14132 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14133 op0 = copy_to_mode_reg (mode0, op0);
14134 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14135 op1 = copy_to_mode_reg (mode1, op1);
14137 pat = GEN_FCN (icode) (target, op0, op1);
14146 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
14149 tree cr6_form = CALL_EXPR_ARG (exp, 0);
14150 tree arg0 = CALL_EXPR_ARG (exp, 1);
14151 tree arg1 = CALL_EXPR_ARG (exp, 2);
14152 rtx op0 = expand_normal (arg0);
14153 rtx op1 = expand_normal (arg1);
14154 machine_mode tmode = SImode;
14155 machine_mode mode0 = insn_data[icode].operand[1].mode;
14156 machine_mode mode1 = insn_data[icode].operand[2].mode;
14159 if (TREE_CODE (cr6_form) != INTEGER_CST)
14161 error ("argument 1 of %qs must be a constant",
14162 "__builtin_altivec_predicate");
14166 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
14168 gcc_assert (mode0 == mode1);
14170 /* If we have invalid arguments, bail out before generating bad rtl. */
14171 if (arg0 == error_mark_node || arg1 == error_mark_node)
14175 || GET_MODE (target) != tmode
14176 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14177 target = gen_reg_rtx (tmode);
14179 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14180 op0 = copy_to_mode_reg (mode0, op0);
14181 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14182 op1 = copy_to_mode_reg (mode1, op1);
14184 /* Note that for many of the relevant operations (e.g. cmpne or
14185 cmpeq) with float or double operands, it makes more sense for the
14186 mode of the allocated scratch register to select a vector of
14187 integer. But the choice to copy the mode of operand 0 was made
14188 long ago and there are no plans to change it. */
14189 scratch = gen_reg_rtx (mode0);
14191 pat = GEN_FCN (icode) (scratch, op0, op1);
14196 /* The vec_any* and vec_all* predicates use the same opcodes for two
14197 different operations, but the bits in CR6 will be different
14198 depending on what information we want. So we have to play tricks
14199 with CR6 to get the right bits out.
14201 If you think this is disgusting, look at the specs for the
14202 AltiVec predicates. */
14204 switch (cr6_form_int)
14207 emit_insn (gen_cr6_test_for_zero (target));
14210 emit_insn (gen_cr6_test_for_zero_reverse (target));
14213 emit_insn (gen_cr6_test_for_lt (target));
14216 emit_insn (gen_cr6_test_for_lt_reverse (target));
14219 error ("argument 1 of %qs is out of range",
14220 "__builtin_altivec_predicate");
14228 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
14231 tree arg0 = CALL_EXPR_ARG (exp, 0);
14232 tree arg1 = CALL_EXPR_ARG (exp, 1);
14233 machine_mode tmode = insn_data[icode].operand[0].mode;
14234 machine_mode mode0 = Pmode;
14235 machine_mode mode1 = Pmode;
14236 rtx op0 = expand_normal (arg0);
14237 rtx op1 = expand_normal (arg1);
14239 if (icode == CODE_FOR_nothing)
14240 /* Builtin not supported on this processor. */
14243 /* If we got invalid arguments bail out before generating bad rtl. */
14244 if (arg0 == error_mark_node || arg1 == error_mark_node)
14248 || GET_MODE (target) != tmode
14249 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14250 target = gen_reg_rtx (tmode);
14252 op1 = copy_to_mode_reg (mode1, op1);
14254 if (op0 == const0_rtx)
14256 addr = gen_rtx_MEM (tmode, op1);
14260 op0 = copy_to_mode_reg (mode0, op0);
14261 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
14264 pat = GEN_FCN (icode) (target, addr);
14273 /* Return a constant vector for use as a little-endian permute control vector
14274 to reverse the order of elements of the given vector mode. */
14276 swap_selector_for_mode (machine_mode mode)
14278 /* These are little endian vectors, so their elements are reversed
14279 from what you would normally expect for a permute control vector. */
14280 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14281 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14282 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14283 unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14284 unsigned int *swaparray, i;
14301 swaparray = swap16;
14304 gcc_unreachable ();
14307 for (i = 0; i < 16; ++i)
14308 perm[i] = GEN_INT (swaparray[i]);
14310 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
14314 swap_endian_selector_for_mode (machine_mode mode)
14316 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
14317 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14318 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14319 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14321 unsigned int *swaparray, i;
14341 gcc_unreachable ();
14344 for (i = 0; i < 16; ++i)
14345 perm[i] = GEN_INT (swaparray[i]);
14347 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
14348 gen_rtvec_v (16, perm)));
14351 /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
14352 with -maltivec=be specified. Issue the load followed by an element-
14353 reversing permute. */
14355 altivec_expand_lvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14357 rtx tmp = gen_reg_rtx (mode);
14358 rtx load = gen_rtx_SET (tmp, op1);
14359 rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14360 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
14361 rtx sel = swap_selector_for_mode (mode);
14362 rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
14364 gcc_assert (REG_P (op0));
14366 emit_insn (gen_rtx_SET (op0, vperm));
14369 /* Generate code for a "stvxl" built-in for a little endian target with
14370 -maltivec=be specified. Issue the store preceded by an element-reversing
14373 altivec_expand_stvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14375 rtx tmp = gen_reg_rtx (mode);
14376 rtx store = gen_rtx_SET (op0, tmp);
14377 rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14378 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
14379 rtx sel = swap_selector_for_mode (mode);
14382 gcc_assert (REG_P (op1));
14383 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14384 emit_insn (gen_rtx_SET (tmp, vperm));
14388 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
14389 specified. Issue the store preceded by an element-reversing permute. */
14391 altivec_expand_stvex_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14393 machine_mode inner_mode = GET_MODE_INNER (mode);
14394 rtx tmp = gen_reg_rtx (mode);
14395 rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
14396 rtx sel = swap_selector_for_mode (mode);
14399 gcc_assert (REG_P (op1));
14400 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14401 emit_insn (gen_rtx_SET (tmp, vperm));
14402 emit_insn (gen_rtx_SET (op0, stvx));
14406 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
14409 tree arg0 = CALL_EXPR_ARG (exp, 0);
14410 tree arg1 = CALL_EXPR_ARG (exp, 1);
14411 machine_mode tmode = insn_data[icode].operand[0].mode;
14412 machine_mode mode0 = Pmode;
14413 machine_mode mode1 = Pmode;
14414 rtx op0 = expand_normal (arg0);
14415 rtx op1 = expand_normal (arg1);
14417 if (icode == CODE_FOR_nothing)
14418 /* Builtin not supported on this processor. */
14421 /* If we got invalid arguments bail out before generating bad rtl. */
14422 if (arg0 == error_mark_node || arg1 == error_mark_node)
14426 || GET_MODE (target) != tmode
14427 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14428 target = gen_reg_rtx (tmode);
14430 op1 = copy_to_mode_reg (mode1, op1);
14432 /* For LVX, express the RTL accurately by ANDing the address with -16.
14433 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14434 so the raw address is fine. */
14435 if (icode == CODE_FOR_altivec_lvx_v2df_2op
14436 || icode == CODE_FOR_altivec_lvx_v2di_2op
14437 || icode == CODE_FOR_altivec_lvx_v4sf_2op
14438 || icode == CODE_FOR_altivec_lvx_v4si_2op
14439 || icode == CODE_FOR_altivec_lvx_v8hi_2op
14440 || icode == CODE_FOR_altivec_lvx_v16qi_2op)
14443 if (op0 == const0_rtx)
14447 op0 = copy_to_mode_reg (mode0, op0);
14448 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
14450 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14451 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
14453 /* For -maltivec=be, emit the load and follow it up with a
14454 permute to swap the elements. */
14455 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14457 rtx temp = gen_reg_rtx (tmode);
14458 emit_insn (gen_rtx_SET (temp, addr));
14460 rtx sel = swap_selector_for_mode (tmode);
14461 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, temp, temp, sel),
14463 emit_insn (gen_rtx_SET (target, vperm));
14466 emit_insn (gen_rtx_SET (target, addr));
14470 if (op0 == const0_rtx)
14471 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14474 op0 = copy_to_mode_reg (mode0, op0);
14475 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14476 gen_rtx_PLUS (Pmode, op1, op0));
14479 pat = GEN_FCN (icode) (target, addr);
14489 paired_expand_stv_builtin (enum insn_code icode, tree exp)
14491 tree arg0 = CALL_EXPR_ARG (exp, 0);
14492 tree arg1 = CALL_EXPR_ARG (exp, 1);
14493 tree arg2 = CALL_EXPR_ARG (exp, 2);
14494 rtx op0 = expand_normal (arg0);
14495 rtx op1 = expand_normal (arg1);
14496 rtx op2 = expand_normal (arg2);
14498 machine_mode tmode = insn_data[icode].operand[0].mode;
14499 machine_mode mode1 = Pmode;
14500 machine_mode mode2 = Pmode;
14502 /* Invalid arguments. Bail before doing anything stoopid! */
14503 if (arg0 == error_mark_node
14504 || arg1 == error_mark_node
14505 || arg2 == error_mark_node)
14508 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
14509 op0 = copy_to_mode_reg (tmode, op0);
14511 op2 = copy_to_mode_reg (mode2, op2);
14513 if (op1 == const0_rtx)
14515 addr = gen_rtx_MEM (tmode, op2);
14519 op1 = copy_to_mode_reg (mode1, op1);
14520 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
14523 pat = GEN_FCN (icode) (addr, op0);
14530 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
14533 tree arg0 = CALL_EXPR_ARG (exp, 0);
14534 tree arg1 = CALL_EXPR_ARG (exp, 1);
14535 tree arg2 = CALL_EXPR_ARG (exp, 2);
14536 rtx op0 = expand_normal (arg0);
14537 rtx op1 = expand_normal (arg1);
14538 rtx op2 = expand_normal (arg2);
14539 machine_mode mode0 = insn_data[icode].operand[0].mode;
14540 machine_mode mode1 = insn_data[icode].operand[1].mode;
14541 machine_mode mode2 = insn_data[icode].operand[2].mode;
14543 if (icode == CODE_FOR_nothing)
14544 /* Builtin not supported on this processor. */
14547 /* If we got invalid arguments bail out before generating bad rtl. */
14548 if (arg0 == error_mark_node
14549 || arg1 == error_mark_node
14550 || arg2 == error_mark_node)
14553 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14554 op0 = copy_to_mode_reg (mode0, op0);
14555 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14556 op1 = copy_to_mode_reg (mode1, op1);
14557 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14558 op2 = copy_to_mode_reg (mode2, op2);
14560 pat = GEN_FCN (icode) (op0, op1, op2);
14568 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
14570 tree arg0 = CALL_EXPR_ARG (exp, 0);
14571 tree arg1 = CALL_EXPR_ARG (exp, 1);
14572 tree arg2 = CALL_EXPR_ARG (exp, 2);
14573 rtx op0 = expand_normal (arg0);
14574 rtx op1 = expand_normal (arg1);
14575 rtx op2 = expand_normal (arg2);
14576 rtx pat, addr, rawaddr;
14577 machine_mode tmode = insn_data[icode].operand[0].mode;
14578 machine_mode smode = insn_data[icode].operand[1].mode;
14579 machine_mode mode1 = Pmode;
14580 machine_mode mode2 = Pmode;
14582 /* Invalid arguments. Bail before doing anything stoopid! */
14583 if (arg0 == error_mark_node
14584 || arg1 == error_mark_node
14585 || arg2 == error_mark_node)
14588 op2 = copy_to_mode_reg (mode2, op2);
14590 /* For STVX, express the RTL accurately by ANDing the address with -16.
14591 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14592 so the raw address is fine. */
14593 if (icode == CODE_FOR_altivec_stvx_v2df_2op
14594 || icode == CODE_FOR_altivec_stvx_v2di_2op
14595 || icode == CODE_FOR_altivec_stvx_v4sf_2op
14596 || icode == CODE_FOR_altivec_stvx_v4si_2op
14597 || icode == CODE_FOR_altivec_stvx_v8hi_2op
14598 || icode == CODE_FOR_altivec_stvx_v16qi_2op)
14600 if (op1 == const0_rtx)
14604 op1 = copy_to_mode_reg (mode1, op1);
14605 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
14608 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14609 addr = gen_rtx_MEM (tmode, addr);
14611 op0 = copy_to_mode_reg (tmode, op0);
14613 /* For -maltivec=be, emit a permute to swap the elements, followed
14615 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14617 rtx temp = gen_reg_rtx (tmode);
14618 rtx sel = swap_selector_for_mode (tmode);
14619 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, op0, op0, sel),
14621 emit_insn (gen_rtx_SET (temp, vperm));
14622 emit_insn (gen_rtx_SET (addr, temp));
14625 emit_insn (gen_rtx_SET (addr, op0));
14629 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
14630 op0 = copy_to_mode_reg (smode, op0);
14632 if (op1 == const0_rtx)
14633 addr = gen_rtx_MEM (tmode, op2);
14636 op1 = copy_to_mode_reg (mode1, op1);
14637 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
14640 pat = GEN_FCN (icode) (addr, op0);
14648 /* Return the appropriate SPR number associated with the given builtin. */
14649 static inline HOST_WIDE_INT
14650 htm_spr_num (enum rs6000_builtins code)
14652 if (code == HTM_BUILTIN_GET_TFHAR
14653 || code == HTM_BUILTIN_SET_TFHAR)
14655 else if (code == HTM_BUILTIN_GET_TFIAR
14656 || code == HTM_BUILTIN_SET_TFIAR)
14658 else if (code == HTM_BUILTIN_GET_TEXASR
14659 || code == HTM_BUILTIN_SET_TEXASR)
14661 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
14662 || code == HTM_BUILTIN_SET_TEXASRU);
14663 return TEXASRU_SPR;
14666 /* Return the appropriate SPR regno associated with the given builtin. */
14667 static inline HOST_WIDE_INT
14668 htm_spr_regno (enum rs6000_builtins code)
14670 if (code == HTM_BUILTIN_GET_TFHAR
14671 || code == HTM_BUILTIN_SET_TFHAR)
14672 return TFHAR_REGNO;
14673 else if (code == HTM_BUILTIN_GET_TFIAR
14674 || code == HTM_BUILTIN_SET_TFIAR)
14675 return TFIAR_REGNO;
14676 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
14677 || code == HTM_BUILTIN_SET_TEXASR
14678 || code == HTM_BUILTIN_GET_TEXASRU
14679 || code == HTM_BUILTIN_SET_TEXASRU);
14680 return TEXASR_REGNO;
14683 /* Return the correct ICODE value depending on whether we are
14684 setting or reading the HTM SPRs. */
14685 static inline enum insn_code
14686 rs6000_htm_spr_icode (bool nonvoid)
14689 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
14691 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
14694 /* Expand the HTM builtin in EXP and store the result in TARGET.
14695 Store true in *EXPANDEDP if we found a builtin to expand. */
14697 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14699 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14700 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14701 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14702 const struct builtin_description *d;
14707 if (!TARGET_POWERPC64
14708 && (fcode == HTM_BUILTIN_TABORTDC
14709 || fcode == HTM_BUILTIN_TABORTDCI))
14711 size_t uns_fcode = (size_t)fcode;
14712 const char *name = rs6000_builtin_info[uns_fcode].name;
14713 error ("builtin %qs is only valid in 64-bit mode", name);
14717 /* Expand the HTM builtins. */
14719 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14720 if (d->code == fcode)
14722 rtx op[MAX_HTM_OPERANDS], pat;
14725 call_expr_arg_iterator iter;
14726 unsigned attr = rs6000_builtin_info[fcode].attr;
14727 enum insn_code icode = d->icode;
14728 const struct insn_operand_data *insn_op;
14729 bool uses_spr = (attr & RS6000_BTC_SPR);
14733 icode = rs6000_htm_spr_icode (nonvoid);
14734 insn_op = &insn_data[icode].operand[0];
14738 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14740 || GET_MODE (target) != tmode
14741 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14742 target = gen_reg_rtx (tmode);
14744 op[nopnds++] = target;
14747 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14749 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14752 insn_op = &insn_data[icode].operand[nopnds];
14754 op[nopnds] = expand_normal (arg);
14756 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14758 if (!strcmp (insn_op->constraint, "n"))
14760 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14761 if (!CONST_INT_P (op[nopnds]))
14762 error ("argument %d must be an unsigned literal", arg_num);
14764 error ("argument %d is an unsigned literal that is "
14765 "out of range", arg_num);
14768 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14774 /* Handle the builtins for extended mnemonics. These accept
14775 no arguments, but map to builtins that take arguments. */
14778 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14779 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14780 op[nopnds++] = GEN_INT (1);
14782 attr |= RS6000_BTC_UNARY;
14784 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14785 op[nopnds++] = GEN_INT (0);
14787 attr |= RS6000_BTC_UNARY;
14793 /* If this builtin accesses SPRs, then pass in the appropriate
14794 SPR number and SPR regno as the last two operands. */
14797 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14798 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14799 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14801 /* If this builtin accesses a CR, then pass in a scratch
14802 CR as the last operand. */
14803 else if (attr & RS6000_BTC_CR)
14804 { cr = gen_reg_rtx (CCmode);
14810 int expected_nopnds = 0;
14811 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14812 expected_nopnds = 1;
14813 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14814 expected_nopnds = 2;
14815 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14816 expected_nopnds = 3;
14817 if (!(attr & RS6000_BTC_VOID))
14818 expected_nopnds += 1;
14820 expected_nopnds += 2;
14822 gcc_assert (nopnds == expected_nopnds
14823 && nopnds <= MAX_HTM_OPERANDS);
14829 pat = GEN_FCN (icode) (op[0]);
14832 pat = GEN_FCN (icode) (op[0], op[1]);
14835 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14838 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14841 gcc_unreachable ();
14847 if (attr & RS6000_BTC_CR)
14849 if (fcode == HTM_BUILTIN_TBEGIN)
14851 /* Emit code to set TARGET to true or false depending on
14852 whether the tbegin. instruction successfully or failed
14853 to start a transaction. We do this by placing the 1's
14854 complement of CR's EQ bit into TARGET. */
14855 rtx scratch = gen_reg_rtx (SImode);
14856 emit_insn (gen_rtx_SET (scratch,
14857 gen_rtx_EQ (SImode, cr,
14859 emit_insn (gen_rtx_SET (target,
14860 gen_rtx_XOR (SImode, scratch,
14865 /* Emit code to copy the 4-bit condition register field
14866 CR into the least significant end of register TARGET. */
14867 rtx scratch1 = gen_reg_rtx (SImode);
14868 rtx scratch2 = gen_reg_rtx (SImode);
14869 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14870 emit_insn (gen_movcc (subreg, cr));
14871 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14872 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14881 *expandedp = false;
14885 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14888 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14891 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14892 if (fcode == RS6000_BUILTIN_CPU_INIT)
14895 if (target == 0 || GET_MODE (target) != SImode)
14896 target = gen_reg_rtx (SImode);
14898 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14899 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14900 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14901 to a STRING_CST. */
14902 if (TREE_CODE (arg) == ARRAY_REF
14903 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14904 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14905 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14906 arg = TREE_OPERAND (arg, 0);
14908 if (TREE_CODE (arg) != STRING_CST)
14910 error ("builtin %qs only accepts a string argument",
14911 rs6000_builtin_info[(size_t) fcode].name);
14915 if (fcode == RS6000_BUILTIN_CPU_IS)
14917 const char *cpu = TREE_STRING_POINTER (arg);
14918 rtx cpuid = NULL_RTX;
14919 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14920 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14922 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14923 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
14926 if (cpuid == NULL_RTX)
14928 /* Invalid CPU argument. */
14929 error ("cpu %qs is an invalid argument to builtin %qs",
14930 cpu, rs6000_builtin_info[(size_t) fcode].name);
14934 rtx platform = gen_reg_rtx (SImode);
14935 rtx tcbmem = gen_const_mem (SImode,
14936 gen_rtx_PLUS (Pmode,
14937 gen_rtx_REG (Pmode, TLS_REGNUM),
14938 GEN_INT (TCB_PLATFORM_OFFSET)));
14939 emit_move_insn (platform, tcbmem);
14940 emit_insn (gen_eqsi3 (target, platform, cpuid));
14942 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14944 const char *hwcap = TREE_STRING_POINTER (arg);
14945 rtx mask = NULL_RTX;
14947 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14948 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14950 mask = GEN_INT (cpu_supports_info[i].mask);
14951 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14954 if (mask == NULL_RTX)
14956 /* Invalid HWCAP argument. */
14957 error ("%s %qs is an invalid argument to builtin %qs",
14958 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14962 rtx tcb_hwcap = gen_reg_rtx (SImode);
14963 rtx tcbmem = gen_const_mem (SImode,
14964 gen_rtx_PLUS (Pmode,
14965 gen_rtx_REG (Pmode, TLS_REGNUM),
14966 GEN_INT (hwcap_offset)));
14967 emit_move_insn (tcb_hwcap, tcbmem);
14968 rtx scratch1 = gen_reg_rtx (SImode);
14969 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14970 rtx scratch2 = gen_reg_rtx (SImode);
14971 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14972 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14975 gcc_unreachable ();
14977 /* Record that we have expanded a CPU builtin, so that we can later
14978 emit a reference to the special symbol exported by LIBC to ensure we
14979 do not link against an old LIBC that doesn't support this feature. */
14980 cpu_builtin_p = true;
14983 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14984 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14986 /* For old LIBCs, always return FALSE. */
14987 emit_move_insn (target, GEN_INT (0));
14988 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14994 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14997 tree arg0 = CALL_EXPR_ARG (exp, 0);
14998 tree arg1 = CALL_EXPR_ARG (exp, 1);
14999 tree arg2 = CALL_EXPR_ARG (exp, 2);
15000 rtx op0 = expand_normal (arg0);
15001 rtx op1 = expand_normal (arg1);
15002 rtx op2 = expand_normal (arg2);
15003 machine_mode tmode = insn_data[icode].operand[0].mode;
15004 machine_mode mode0 = insn_data[icode].operand[1].mode;
15005 machine_mode mode1 = insn_data[icode].operand[2].mode;
15006 machine_mode mode2 = insn_data[icode].operand[3].mode;
15008 if (icode == CODE_FOR_nothing)
15009 /* Builtin not supported on this processor. */
15012 /* If we got invalid arguments bail out before generating bad rtl. */
15013 if (arg0 == error_mark_node
15014 || arg1 == error_mark_node
15015 || arg2 == error_mark_node)
15018 /* Check and prepare argument depending on the instruction code.
15020 Note that a switch statement instead of the sequence of tests
15021 would be incorrect as many of the CODE_FOR values could be
15022 CODE_FOR_nothing and that would yield multiple alternatives
15023 with identical values. We'd never reach here at runtime in
15025 if (icode == CODE_FOR_altivec_vsldoi_v4sf
15026 || icode == CODE_FOR_altivec_vsldoi_v2df
15027 || icode == CODE_FOR_altivec_vsldoi_v4si
15028 || icode == CODE_FOR_altivec_vsldoi_v8hi
15029 || icode == CODE_FOR_altivec_vsldoi_v16qi)
15031 /* Only allow 4-bit unsigned literals. */
15033 if (TREE_CODE (arg2) != INTEGER_CST
15034 || TREE_INT_CST_LOW (arg2) & ~0xf)
15036 error ("argument 3 must be a 4-bit unsigned literal");
15037 return CONST0_RTX (tmode);
15040 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
15041 || icode == CODE_FOR_vsx_xxpermdi_v2di
15042 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
15043 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
15044 || icode == CODE_FOR_vsx_xxpermdi_v1ti
15045 || icode == CODE_FOR_vsx_xxpermdi_v4sf
15046 || icode == CODE_FOR_vsx_xxpermdi_v4si
15047 || icode == CODE_FOR_vsx_xxpermdi_v8hi
15048 || icode == CODE_FOR_vsx_xxpermdi_v16qi
15049 || icode == CODE_FOR_vsx_xxsldwi_v16qi
15050 || icode == CODE_FOR_vsx_xxsldwi_v8hi
15051 || icode == CODE_FOR_vsx_xxsldwi_v4si
15052 || icode == CODE_FOR_vsx_xxsldwi_v4sf
15053 || icode == CODE_FOR_vsx_xxsldwi_v2di
15054 || icode == CODE_FOR_vsx_xxsldwi_v2df)
15056 /* Only allow 2-bit unsigned literals. */
15058 if (TREE_CODE (arg2) != INTEGER_CST
15059 || TREE_INT_CST_LOW (arg2) & ~0x3)
15061 error ("argument 3 must be a 2-bit unsigned literal");
15062 return CONST0_RTX (tmode);
15065 else if (icode == CODE_FOR_vsx_set_v2df
15066 || icode == CODE_FOR_vsx_set_v2di
15067 || icode == CODE_FOR_bcdadd
15068 || icode == CODE_FOR_bcdadd_lt
15069 || icode == CODE_FOR_bcdadd_eq
15070 || icode == CODE_FOR_bcdadd_gt
15071 || icode == CODE_FOR_bcdsub
15072 || icode == CODE_FOR_bcdsub_lt
15073 || icode == CODE_FOR_bcdsub_eq
15074 || icode == CODE_FOR_bcdsub_gt)
15076 /* Only allow 1-bit unsigned literals. */
15078 if (TREE_CODE (arg2) != INTEGER_CST
15079 || TREE_INT_CST_LOW (arg2) & ~0x1)
15081 error ("argument 3 must be a 1-bit unsigned literal");
15082 return CONST0_RTX (tmode);
15085 else if (icode == CODE_FOR_dfp_ddedpd_dd
15086 || icode == CODE_FOR_dfp_ddedpd_td)
15088 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
15090 if (TREE_CODE (arg0) != INTEGER_CST
15091 || TREE_INT_CST_LOW (arg2) & ~0x3)
15093 error ("argument 1 must be 0 or 2");
15094 return CONST0_RTX (tmode);
15097 else if (icode == CODE_FOR_dfp_denbcd_dd
15098 || icode == CODE_FOR_dfp_denbcd_td)
15100 /* Only allow 1-bit unsigned literals. */
15102 if (TREE_CODE (arg0) != INTEGER_CST
15103 || TREE_INT_CST_LOW (arg0) & ~0x1)
15105 error ("argument 1 must be a 1-bit unsigned literal");
15106 return CONST0_RTX (tmode);
15109 else if (icode == CODE_FOR_dfp_dscli_dd
15110 || icode == CODE_FOR_dfp_dscli_td
15111 || icode == CODE_FOR_dfp_dscri_dd
15112 || icode == CODE_FOR_dfp_dscri_td)
15114 /* Only allow 6-bit unsigned literals. */
15116 if (TREE_CODE (arg1) != INTEGER_CST
15117 || TREE_INT_CST_LOW (arg1) & ~0x3f)
15119 error ("argument 2 must be a 6-bit unsigned literal");
15120 return CONST0_RTX (tmode);
15123 else if (icode == CODE_FOR_crypto_vshasigmaw
15124 || icode == CODE_FOR_crypto_vshasigmad)
15126 /* Check whether the 2nd and 3rd arguments are integer constants and in
15127 range and prepare arguments. */
15129 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
15131 error ("argument 2 must be 0 or 1");
15132 return CONST0_RTX (tmode);
15136 if (TREE_CODE (arg2) != INTEGER_CST
15137 || wi::geu_p (wi::to_wide (arg2), 16))
15139 error ("argument 3 must be in the range 0..15");
15140 return CONST0_RTX (tmode);
15145 || GET_MODE (target) != tmode
15146 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15147 target = gen_reg_rtx (tmode);
15149 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15150 op0 = copy_to_mode_reg (mode0, op0);
15151 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15152 op1 = copy_to_mode_reg (mode1, op1);
15153 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15154 op2 = copy_to_mode_reg (mode2, op2);
15156 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
15157 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
15159 pat = GEN_FCN (icode) (target, op0, op1, op2);
15167 /* Expand the lvx builtins. */
15169 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
15171 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15172 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15174 machine_mode tmode, mode0;
15176 enum insn_code icode;
15180 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
15181 icode = CODE_FOR_vector_altivec_load_v16qi;
15183 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
15184 icode = CODE_FOR_vector_altivec_load_v8hi;
15186 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
15187 icode = CODE_FOR_vector_altivec_load_v4si;
15189 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
15190 icode = CODE_FOR_vector_altivec_load_v4sf;
15192 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
15193 icode = CODE_FOR_vector_altivec_load_v2df;
15195 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
15196 icode = CODE_FOR_vector_altivec_load_v2di;
15198 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
15199 icode = CODE_FOR_vector_altivec_load_v1ti;
15202 *expandedp = false;
15208 arg0 = CALL_EXPR_ARG (exp, 0);
15209 op0 = expand_normal (arg0);
15210 tmode = insn_data[icode].operand[0].mode;
15211 mode0 = insn_data[icode].operand[1].mode;
15214 || GET_MODE (target) != tmode
15215 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15216 target = gen_reg_rtx (tmode);
15218 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15219 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15221 pat = GEN_FCN (icode) (target, op0);
15228 /* Expand the stvx builtins. */
15230 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15233 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15234 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15236 machine_mode mode0, mode1;
15238 enum insn_code icode;
15242 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
15243 icode = CODE_FOR_vector_altivec_store_v16qi;
15245 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
15246 icode = CODE_FOR_vector_altivec_store_v8hi;
15248 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
15249 icode = CODE_FOR_vector_altivec_store_v4si;
15251 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
15252 icode = CODE_FOR_vector_altivec_store_v4sf;
15254 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
15255 icode = CODE_FOR_vector_altivec_store_v2df;
15257 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
15258 icode = CODE_FOR_vector_altivec_store_v2di;
15260 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
15261 icode = CODE_FOR_vector_altivec_store_v1ti;
15264 *expandedp = false;
15268 arg0 = CALL_EXPR_ARG (exp, 0);
15269 arg1 = CALL_EXPR_ARG (exp, 1);
15270 op0 = expand_normal (arg0);
15271 op1 = expand_normal (arg1);
15272 mode0 = insn_data[icode].operand[0].mode;
15273 mode1 = insn_data[icode].operand[1].mode;
15275 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15276 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15277 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15278 op1 = copy_to_mode_reg (mode1, op1);
15280 pat = GEN_FCN (icode) (op0, op1);
15288 /* Expand the dst builtins. */
15290 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15293 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15294 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15295 tree arg0, arg1, arg2;
15296 machine_mode mode0, mode1;
15297 rtx pat, op0, op1, op2;
15298 const struct builtin_description *d;
15301 *expandedp = false;
15303 /* Handle DST variants. */
15305 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
15306 if (d->code == fcode)
15308 arg0 = CALL_EXPR_ARG (exp, 0);
15309 arg1 = CALL_EXPR_ARG (exp, 1);
15310 arg2 = CALL_EXPR_ARG (exp, 2);
15311 op0 = expand_normal (arg0);
15312 op1 = expand_normal (arg1);
15313 op2 = expand_normal (arg2);
15314 mode0 = insn_data[d->icode].operand[0].mode;
15315 mode1 = insn_data[d->icode].operand[1].mode;
15317 /* Invalid arguments, bail out before generating bad rtl. */
15318 if (arg0 == error_mark_node
15319 || arg1 == error_mark_node
15320 || arg2 == error_mark_node)
15325 if (TREE_CODE (arg2) != INTEGER_CST
15326 || TREE_INT_CST_LOW (arg2) & ~0x3)
15328 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
15332 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15333 op0 = copy_to_mode_reg (Pmode, op0);
15334 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15335 op1 = copy_to_mode_reg (mode1, op1);
15337 pat = GEN_FCN (d->icode) (op0, op1, op2);
15347 /* Expand vec_init builtin. */
15349 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
15351 machine_mode tmode = TYPE_MODE (type);
15352 machine_mode inner_mode = GET_MODE_INNER (tmode);
15353 int i, n_elt = GET_MODE_NUNITS (tmode);
15355 gcc_assert (VECTOR_MODE_P (tmode));
15356 gcc_assert (n_elt == call_expr_nargs (exp));
15358 if (!target || !register_operand (target, tmode))
15359 target = gen_reg_rtx (tmode);
15361 /* If we have a vector compromised of a single element, such as V1TImode, do
15362 the initialization directly. */
15363 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
15365 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
15366 emit_move_insn (target, gen_lowpart (tmode, x));
15370 rtvec v = rtvec_alloc (n_elt);
15372 for (i = 0; i < n_elt; ++i)
15374 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
15375 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15378 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
15384 /* Return the integer constant in ARG. Constrain it to be in the range
15385 of the subparts of VEC_TYPE; issue an error if not. */
15388 get_element_number (tree vec_type, tree arg)
15390 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15392 if (!tree_fits_uhwi_p (arg)
15393 || (elt = tree_to_uhwi (arg), elt > max))
15395 error ("selector must be an integer constant in the range 0..%wi", max);
15402 /* Expand vec_set builtin. */
15404 altivec_expand_vec_set_builtin (tree exp)
15406 machine_mode tmode, mode1;
15407 tree arg0, arg1, arg2;
15411 arg0 = CALL_EXPR_ARG (exp, 0);
15412 arg1 = CALL_EXPR_ARG (exp, 1);
15413 arg2 = CALL_EXPR_ARG (exp, 2);
15415 tmode = TYPE_MODE (TREE_TYPE (arg0));
15416 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15417 gcc_assert (VECTOR_MODE_P (tmode));
15419 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
15420 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
15421 elt = get_element_number (TREE_TYPE (arg0), arg2);
15423 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15424 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15426 op0 = force_reg (tmode, op0);
15427 op1 = force_reg (mode1, op1);
15429 rs6000_expand_vector_set (op0, op1, elt);
15434 /* Expand vec_ext builtin. */
15436 altivec_expand_vec_ext_builtin (tree exp, rtx target)
15438 machine_mode tmode, mode0;
15443 arg0 = CALL_EXPR_ARG (exp, 0);
15444 arg1 = CALL_EXPR_ARG (exp, 1);
15446 op0 = expand_normal (arg0);
15447 op1 = expand_normal (arg1);
15449 /* Call get_element_number to validate arg1 if it is a constant. */
15450 if (TREE_CODE (arg1) == INTEGER_CST)
15451 (void) get_element_number (TREE_TYPE (arg0), arg1);
15453 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15454 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15455 gcc_assert (VECTOR_MODE_P (mode0));
15457 op0 = force_reg (mode0, op0);
15459 if (optimize || !target || !register_operand (target, tmode))
15460 target = gen_reg_rtx (tmode);
15462 rs6000_expand_vector_extract (target, op0, op1);
15467 /* Expand the builtin in EXP and store the result in TARGET. Store
15468 true in *EXPANDEDP if we found a builtin to expand. */
15470 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
15472 const struct builtin_description *d;
15474 enum insn_code icode;
15475 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15476 tree arg0, arg1, arg2;
15478 machine_mode tmode, mode0;
15479 enum rs6000_builtins fcode
15480 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15482 if (rs6000_overloaded_builtin_p (fcode))
15485 error ("unresolved overload for Altivec builtin %qF", fndecl);
15487 /* Given it is invalid, just generate a normal call. */
15488 return expand_call (exp, target, false);
15491 target = altivec_expand_ld_builtin (exp, target, expandedp);
15495 target = altivec_expand_st_builtin (exp, target, expandedp);
15499 target = altivec_expand_dst_builtin (exp, target, expandedp);
15507 case ALTIVEC_BUILTIN_STVX_V2DF:
15508 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op, exp);
15509 case ALTIVEC_BUILTIN_STVX_V2DI:
15510 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op, exp);
15511 case ALTIVEC_BUILTIN_STVX_V4SF:
15512 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op, exp);
15513 case ALTIVEC_BUILTIN_STVX:
15514 case ALTIVEC_BUILTIN_STVX_V4SI:
15515 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op, exp);
15516 case ALTIVEC_BUILTIN_STVX_V8HI:
15517 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op, exp);
15518 case ALTIVEC_BUILTIN_STVX_V16QI:
15519 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op, exp);
15520 case ALTIVEC_BUILTIN_STVEBX:
15521 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
15522 case ALTIVEC_BUILTIN_STVEHX:
15523 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
15524 case ALTIVEC_BUILTIN_STVEWX:
15525 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
15526 case ALTIVEC_BUILTIN_STVXL_V2DF:
15527 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
15528 case ALTIVEC_BUILTIN_STVXL_V2DI:
15529 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
15530 case ALTIVEC_BUILTIN_STVXL_V4SF:
15531 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
15532 case ALTIVEC_BUILTIN_STVXL:
15533 case ALTIVEC_BUILTIN_STVXL_V4SI:
15534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
15535 case ALTIVEC_BUILTIN_STVXL_V8HI:
15536 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
15537 case ALTIVEC_BUILTIN_STVXL_V16QI:
15538 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
15540 case ALTIVEC_BUILTIN_STVLX:
15541 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
15542 case ALTIVEC_BUILTIN_STVLXL:
15543 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
15544 case ALTIVEC_BUILTIN_STVRX:
15545 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
15546 case ALTIVEC_BUILTIN_STVRXL:
15547 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
15549 case P9V_BUILTIN_STXVL:
15550 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
15552 case P9V_BUILTIN_XST_LEN_R:
15553 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
15555 case VSX_BUILTIN_STXVD2X_V1TI:
15556 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
15557 case VSX_BUILTIN_STXVD2X_V2DF:
15558 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
15559 case VSX_BUILTIN_STXVD2X_V2DI:
15560 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
15561 case VSX_BUILTIN_STXVW4X_V4SF:
15562 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
15563 case VSX_BUILTIN_STXVW4X_V4SI:
15564 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
15565 case VSX_BUILTIN_STXVW4X_V8HI:
15566 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
15567 case VSX_BUILTIN_STXVW4X_V16QI:
15568 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
15570 /* For the following on big endian, it's ok to use any appropriate
15571 unaligned-supporting store, so use a generic expander. For
15572 little-endian, the exact element-reversing instruction must
15574 case VSX_BUILTIN_ST_ELEMREV_V2DF:
15576 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
15577 : CODE_FOR_vsx_st_elemrev_v2df);
15578 return altivec_expand_stv_builtin (code, exp);
15580 case VSX_BUILTIN_ST_ELEMREV_V2DI:
15582 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
15583 : CODE_FOR_vsx_st_elemrev_v2di);
15584 return altivec_expand_stv_builtin (code, exp);
15586 case VSX_BUILTIN_ST_ELEMREV_V4SF:
15588 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
15589 : CODE_FOR_vsx_st_elemrev_v4sf);
15590 return altivec_expand_stv_builtin (code, exp);
15592 case VSX_BUILTIN_ST_ELEMREV_V4SI:
15594 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
15595 : CODE_FOR_vsx_st_elemrev_v4si);
15596 return altivec_expand_stv_builtin (code, exp);
15598 case VSX_BUILTIN_ST_ELEMREV_V8HI:
15600 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
15601 : CODE_FOR_vsx_st_elemrev_v8hi);
15602 return altivec_expand_stv_builtin (code, exp);
15604 case VSX_BUILTIN_ST_ELEMREV_V16QI:
15606 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
15607 : CODE_FOR_vsx_st_elemrev_v16qi);
15608 return altivec_expand_stv_builtin (code, exp);
15611 case ALTIVEC_BUILTIN_MFVSCR:
15612 icode = CODE_FOR_altivec_mfvscr;
15613 tmode = insn_data[icode].operand[0].mode;
15616 || GET_MODE (target) != tmode
15617 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15618 target = gen_reg_rtx (tmode);
15620 pat = GEN_FCN (icode) (target);
15626 case ALTIVEC_BUILTIN_MTVSCR:
15627 icode = CODE_FOR_altivec_mtvscr;
15628 arg0 = CALL_EXPR_ARG (exp, 0);
15629 op0 = expand_normal (arg0);
15630 mode0 = insn_data[icode].operand[0].mode;
15632 /* If we got invalid arguments bail out before generating bad rtl. */
15633 if (arg0 == error_mark_node)
15636 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15637 op0 = copy_to_mode_reg (mode0, op0);
15639 pat = GEN_FCN (icode) (op0);
15644 case ALTIVEC_BUILTIN_DSSALL:
15645 emit_insn (gen_altivec_dssall ());
15648 case ALTIVEC_BUILTIN_DSS:
15649 icode = CODE_FOR_altivec_dss;
15650 arg0 = CALL_EXPR_ARG (exp, 0);
15652 op0 = expand_normal (arg0);
15653 mode0 = insn_data[icode].operand[0].mode;
15655 /* If we got invalid arguments bail out before generating bad rtl. */
15656 if (arg0 == error_mark_node)
15659 if (TREE_CODE (arg0) != INTEGER_CST
15660 || TREE_INT_CST_LOW (arg0) & ~0x3)
15662 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15666 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15667 op0 = copy_to_mode_reg (mode0, op0);
15669 emit_insn (gen_altivec_dss (op0));
15672 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
15673 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
15674 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
15675 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
15676 case VSX_BUILTIN_VEC_INIT_V2DF:
15677 case VSX_BUILTIN_VEC_INIT_V2DI:
15678 case VSX_BUILTIN_VEC_INIT_V1TI:
15679 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
15681 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
15682 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
15683 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
15684 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
15685 case VSX_BUILTIN_VEC_SET_V2DF:
15686 case VSX_BUILTIN_VEC_SET_V2DI:
15687 case VSX_BUILTIN_VEC_SET_V1TI:
15688 return altivec_expand_vec_set_builtin (exp);
15690 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
15691 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
15692 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
15693 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
15694 case VSX_BUILTIN_VEC_EXT_V2DF:
15695 case VSX_BUILTIN_VEC_EXT_V2DI:
15696 case VSX_BUILTIN_VEC_EXT_V1TI:
15697 return altivec_expand_vec_ext_builtin (exp, target);
15699 case P9V_BUILTIN_VEXTRACT4B:
15700 case P9V_BUILTIN_VEC_VEXTRACT4B:
15701 arg1 = CALL_EXPR_ARG (exp, 1);
15704 /* Generate a normal call if it is invalid. */
15705 if (arg1 == error_mark_node)
15706 return expand_call (exp, target, false);
15708 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
15710 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15711 return expand_call (exp, target, false);
15715 case P9V_BUILTIN_VINSERT4B:
15716 case P9V_BUILTIN_VINSERT4B_DI:
15717 case P9V_BUILTIN_VEC_VINSERT4B:
15718 arg2 = CALL_EXPR_ARG (exp, 2);
15721 /* Generate a normal call if it is invalid. */
15722 if (arg2 == error_mark_node)
15723 return expand_call (exp, target, false);
15725 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
15727 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15728 return expand_call (exp, target, false);
15734 /* Fall through. */
15737 /* Expand abs* operations. */
15739 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
15740 if (d->code == fcode)
15741 return altivec_expand_abs_builtin (d->icode, exp, target);
15743 /* Expand the AltiVec predicates. */
15744 d = bdesc_altivec_preds;
15745 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
15746 if (d->code == fcode)
15747 return altivec_expand_predicate_builtin (d->icode, exp, target);
15749 /* LV* are funky. We initialized them differently. */
15752 case ALTIVEC_BUILTIN_LVSL:
15753 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
15754 exp, target, false);
15755 case ALTIVEC_BUILTIN_LVSR:
15756 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
15757 exp, target, false);
15758 case ALTIVEC_BUILTIN_LVEBX:
15759 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
15760 exp, target, false);
15761 case ALTIVEC_BUILTIN_LVEHX:
15762 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
15763 exp, target, false);
15764 case ALTIVEC_BUILTIN_LVEWX:
15765 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
15766 exp, target, false);
15767 case ALTIVEC_BUILTIN_LVXL_V2DF:
15768 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
15769 exp, target, false);
15770 case ALTIVEC_BUILTIN_LVXL_V2DI:
15771 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
15772 exp, target, false);
15773 case ALTIVEC_BUILTIN_LVXL_V4SF:
15774 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
15775 exp, target, false);
15776 case ALTIVEC_BUILTIN_LVXL:
15777 case ALTIVEC_BUILTIN_LVXL_V4SI:
15778 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
15779 exp, target, false);
15780 case ALTIVEC_BUILTIN_LVXL_V8HI:
15781 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
15782 exp, target, false);
15783 case ALTIVEC_BUILTIN_LVXL_V16QI:
15784 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
15785 exp, target, false);
15786 case ALTIVEC_BUILTIN_LVX_V2DF:
15787 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op,
15788 exp, target, false);
15789 case ALTIVEC_BUILTIN_LVX_V2DI:
15790 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op,
15791 exp, target, false);
15792 case ALTIVEC_BUILTIN_LVX_V4SF:
15793 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op,
15794 exp, target, false);
15795 case ALTIVEC_BUILTIN_LVX:
15796 case ALTIVEC_BUILTIN_LVX_V4SI:
15797 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op,
15798 exp, target, false);
15799 case ALTIVEC_BUILTIN_LVX_V8HI:
15800 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op,
15801 exp, target, false);
15802 case ALTIVEC_BUILTIN_LVX_V16QI:
15803 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op,
15804 exp, target, false);
15805 case ALTIVEC_BUILTIN_LVLX:
15806 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
15807 exp, target, true);
15808 case ALTIVEC_BUILTIN_LVLXL:
15809 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
15810 exp, target, true);
15811 case ALTIVEC_BUILTIN_LVRX:
15812 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
15813 exp, target, true);
15814 case ALTIVEC_BUILTIN_LVRXL:
15815 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
15816 exp, target, true);
15817 case VSX_BUILTIN_LXVD2X_V1TI:
15818 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
15819 exp, target, false);
15820 case VSX_BUILTIN_LXVD2X_V2DF:
15821 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15822 exp, target, false);
15823 case VSX_BUILTIN_LXVD2X_V2DI:
15824 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15825 exp, target, false);
15826 case VSX_BUILTIN_LXVW4X_V4SF:
15827 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15828 exp, target, false);
15829 case VSX_BUILTIN_LXVW4X_V4SI:
15830 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15831 exp, target, false);
15832 case VSX_BUILTIN_LXVW4X_V8HI:
15833 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15834 exp, target, false);
15835 case VSX_BUILTIN_LXVW4X_V16QI:
15836 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15837 exp, target, false);
15838 /* For the following on big endian, it's ok to use any appropriate
15839 unaligned-supporting load, so use a generic expander. For
15840 little-endian, the exact element-reversing instruction must
15842 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15844 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15845 : CODE_FOR_vsx_ld_elemrev_v2df);
15846 return altivec_expand_lv_builtin (code, exp, target, false);
15848 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15850 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15851 : CODE_FOR_vsx_ld_elemrev_v2di);
15852 return altivec_expand_lv_builtin (code, exp, target, false);
15854 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15856 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15857 : CODE_FOR_vsx_ld_elemrev_v4sf);
15858 return altivec_expand_lv_builtin (code, exp, target, false);
15860 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15862 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15863 : CODE_FOR_vsx_ld_elemrev_v4si);
15864 return altivec_expand_lv_builtin (code, exp, target, false);
15866 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15868 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15869 : CODE_FOR_vsx_ld_elemrev_v8hi);
15870 return altivec_expand_lv_builtin (code, exp, target, false);
15872 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15874 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15875 : CODE_FOR_vsx_ld_elemrev_v16qi);
15876 return altivec_expand_lv_builtin (code, exp, target, false);
15881 /* Fall through. */
15884 *expandedp = false;
15888 /* Expand the builtin in EXP and store the result in TARGET. Store
15889 true in *EXPANDEDP if we found a builtin to expand. */
15891 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
15893 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15894 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15895 const struct builtin_description *d;
15902 case PAIRED_BUILTIN_STX:
15903 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
15904 case PAIRED_BUILTIN_LX:
15905 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
15908 /* Fall through. */
15911 /* Expand the paired predicates. */
15912 d = bdesc_paired_preds;
15913 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
15914 if (d->code == fcode)
15915 return paired_expand_predicate_builtin (d->icode, exp, target);
15917 *expandedp = false;
15922 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
15924 rtx pat, scratch, tmp;
15925 tree form = CALL_EXPR_ARG (exp, 0);
15926 tree arg0 = CALL_EXPR_ARG (exp, 1);
15927 tree arg1 = CALL_EXPR_ARG (exp, 2);
15928 rtx op0 = expand_normal (arg0);
15929 rtx op1 = expand_normal (arg1);
15930 machine_mode mode0 = insn_data[icode].operand[1].mode;
15931 machine_mode mode1 = insn_data[icode].operand[2].mode;
15933 enum rtx_code code;
15935 if (TREE_CODE (form) != INTEGER_CST)
15937 error ("argument 1 of %s must be a constant",
15938 "__builtin_paired_predicate");
15942 form_int = TREE_INT_CST_LOW (form);
15944 gcc_assert (mode0 == mode1);
15946 if (arg0 == error_mark_node || arg1 == error_mark_node)
15950 || GET_MODE (target) != SImode
15951 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
15952 target = gen_reg_rtx (SImode);
15953 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
15954 op0 = copy_to_mode_reg (mode0, op0);
15955 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
15956 op1 = copy_to_mode_reg (mode1, op1);
15958 scratch = gen_reg_rtx (CCFPmode);
15960 pat = GEN_FCN (icode) (scratch, op0, op1);
15982 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
15985 error ("argument 1 of %qs is out of range",
15986 "__builtin_paired_predicate");
15990 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
15991 emit_move_insn (target, tmp);
15995 /* Raise an error message for a builtin function that is called without the
15996 appropriate target options being set. */
15999 rs6000_invalid_builtin (enum rs6000_builtins fncode)
16001 size_t uns_fncode = (size_t) fncode;
16002 const char *name = rs6000_builtin_info[uns_fncode].name;
16003 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
16005 gcc_assert (name != NULL);
16006 if ((fnmask & RS6000_BTM_CELL) != 0)
16007 error ("builtin function %qs is only valid for the cell processor", name);
16008 else if ((fnmask & RS6000_BTM_VSX) != 0)
16009 error ("builtin function %qs requires the %qs option", name, "-mvsx");
16010 else if ((fnmask & RS6000_BTM_HTM) != 0)
16011 error ("builtin function %qs requires the %qs option", name, "-mhtm");
16012 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
16013 error ("builtin function %qs requires the %qs option", name, "-maltivec");
16014 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
16015 error ("builtin function %qs requires the %qs option", name, "-mpaired");
16016 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16017 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16018 error ("builtin function %qs requires the %qs and %qs options",
16019 name, "-mhard-dfp", "-mpower8-vector");
16020 else if ((fnmask & RS6000_BTM_DFP) != 0)
16021 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
16022 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
16023 error ("builtin function %qs requires the %qs option", name,
16024 "-mpower8-vector");
16025 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16026 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16027 error ("builtin function %qs requires the %qs and %qs options",
16028 name, "-mcpu=power9", "-m64");
16029 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
16030 error ("builtin function %qs requires the %qs option", name,
16032 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16033 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16034 error ("builtin function %qs requires the %qs and %qs options",
16035 name, "-mcpu=power9", "-m64");
16036 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
16037 error ("builtin function %qs requires the %qs option", name,
16039 else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16040 == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16041 error ("builtin function %qs requires the %qs and %qs options",
16042 name, "-mhard-float", "-mlong-double-128");
16043 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
16044 error ("builtin function %qs requires the %qs option", name,
16046 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
16047 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
16049 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
16050 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
16052 error ("builtin function %qs is not supported with the current options",
16056 /* Target hook for early folding of built-ins, shamelessly stolen
16060 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
16061 int n_args ATTRIBUTE_UNUSED,
16062 tree *args ATTRIBUTE_UNUSED,
16063 bool ignore ATTRIBUTE_UNUSED)
16065 #ifdef SUBTARGET_FOLD_BUILTIN
16066 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
16072 /* Helper function to sort out which built-ins may be valid without having
16075 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
16079 case ALTIVEC_BUILTIN_STVX_V16QI:
16080 case ALTIVEC_BUILTIN_STVX_V8HI:
16081 case ALTIVEC_BUILTIN_STVX_V4SI:
16082 case ALTIVEC_BUILTIN_STVX_V4SF:
16083 case ALTIVEC_BUILTIN_STVX_V2DI:
16084 case ALTIVEC_BUILTIN_STVX_V2DF:
16091 /* Helper function to handle the gimple folding of a vector compare
16092 operation. This sets up true/false vectors, and uses the
16093 VEC_COND_EXPR operation.
16094 CODE indicates which comparison is to be made. (EQ, GT, ...).
16095 TYPE indicates the type of the result. */
16097 fold_build_vec_cmp (tree_code code, tree type,
16098 tree arg0, tree arg1)
16100 tree cmp_type = build_same_sized_truth_vector_type (type);
16101 tree zero_vec = build_zero_cst (type);
16102 tree minus_one_vec = build_minus_one_cst (type);
16103 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
16104 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
16107 /* Helper function to handle the in-between steps for the
16108 vector compare built-ins. */
16110 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
16112 tree arg0 = gimple_call_arg (stmt, 0);
16113 tree arg1 = gimple_call_arg (stmt, 1);
16114 tree lhs = gimple_call_lhs (stmt);
16115 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
16116 gimple *g = gimple_build_assign (lhs, cmp);
16117 gimple_set_location (g, gimple_location (stmt));
16118 gsi_replace (gsi, g, true);
16121 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
16122 a constant, use rs6000_fold_builtin.) */
16125 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
16127 gimple *stmt = gsi_stmt (*gsi);
16128 tree fndecl = gimple_call_fndecl (stmt);
16129 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
16130 enum rs6000_builtins fn_code
16131 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
16132 tree arg0, arg1, lhs, temp;
16135 size_t uns_fncode = (size_t) fn_code;
16136 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
16137 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
16138 const char *fn_name2 = (icode != CODE_FOR_nothing)
16139 ? get_insn_name ((int) icode)
16142 if (TARGET_DEBUG_BUILTIN)
16143 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
16144 fn_code, fn_name1, fn_name2);
16146 if (!rs6000_fold_gimple)
16149 /* Prevent gimple folding for code that does not have a LHS, unless it is
16150 allowed per the rs6000_builtin_valid_without_lhs helper function. */
16151 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
16154 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
16155 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
16156 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
16162 /* Flavors of vec_add. We deliberately don't expand
16163 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
16164 TImode, resulting in much poorer code generation. */
16165 case ALTIVEC_BUILTIN_VADDUBM:
16166 case ALTIVEC_BUILTIN_VADDUHM:
16167 case ALTIVEC_BUILTIN_VADDUWM:
16168 case P8V_BUILTIN_VADDUDM:
16169 case ALTIVEC_BUILTIN_VADDFP:
16170 case VSX_BUILTIN_XVADDDP:
16171 arg0 = gimple_call_arg (stmt, 0);
16172 arg1 = gimple_call_arg (stmt, 1);
16173 lhs = gimple_call_lhs (stmt);
16174 g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
16175 gimple_set_location (g, gimple_location (stmt));
16176 gsi_replace (gsi, g, true);
16178 /* Flavors of vec_sub. We deliberately don't expand
16179 P8V_BUILTIN_VSUBUQM. */
16180 case ALTIVEC_BUILTIN_VSUBUBM:
16181 case ALTIVEC_BUILTIN_VSUBUHM:
16182 case ALTIVEC_BUILTIN_VSUBUWM:
16183 case P8V_BUILTIN_VSUBUDM:
16184 case ALTIVEC_BUILTIN_VSUBFP:
16185 case VSX_BUILTIN_XVSUBDP:
16186 arg0 = gimple_call_arg (stmt, 0);
16187 arg1 = gimple_call_arg (stmt, 1);
16188 lhs = gimple_call_lhs (stmt);
16189 g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
16190 gimple_set_location (g, gimple_location (stmt));
16191 gsi_replace (gsi, g, true);
16193 case VSX_BUILTIN_XVMULSP:
16194 case VSX_BUILTIN_XVMULDP:
16195 arg0 = gimple_call_arg (stmt, 0);
16196 arg1 = gimple_call_arg (stmt, 1);
16197 lhs = gimple_call_lhs (stmt);
16198 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
16199 gimple_set_location (g, gimple_location (stmt));
16200 gsi_replace (gsi, g, true);
16202 /* Even element flavors of vec_mul (signed). */
16203 case ALTIVEC_BUILTIN_VMULESB:
16204 case ALTIVEC_BUILTIN_VMULESH:
16205 case ALTIVEC_BUILTIN_VMULESW:
16206 /* Even element flavors of vec_mul (unsigned). */
16207 case ALTIVEC_BUILTIN_VMULEUB:
16208 case ALTIVEC_BUILTIN_VMULEUH:
16209 case ALTIVEC_BUILTIN_VMULEUW:
16210 arg0 = gimple_call_arg (stmt, 0);
16211 arg1 = gimple_call_arg (stmt, 1);
16212 lhs = gimple_call_lhs (stmt);
16213 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
16214 gimple_set_location (g, gimple_location (stmt));
16215 gsi_replace (gsi, g, true);
16217 /* Odd element flavors of vec_mul (signed). */
16218 case ALTIVEC_BUILTIN_VMULOSB:
16219 case ALTIVEC_BUILTIN_VMULOSH:
16220 case ALTIVEC_BUILTIN_VMULOSW:
16221 /* Odd element flavors of vec_mul (unsigned). */
16222 case ALTIVEC_BUILTIN_VMULOUB:
16223 case ALTIVEC_BUILTIN_VMULOUH:
16224 case ALTIVEC_BUILTIN_VMULOUW:
16225 arg0 = gimple_call_arg (stmt, 0);
16226 arg1 = gimple_call_arg (stmt, 1);
16227 lhs = gimple_call_lhs (stmt);
16228 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
16229 gimple_set_location (g, gimple_location (stmt));
16230 gsi_replace (gsi, g, true);
16232 /* Flavors of vec_div (Integer). */
16233 case VSX_BUILTIN_DIV_V2DI:
16234 case VSX_BUILTIN_UDIV_V2DI:
16235 arg0 = gimple_call_arg (stmt, 0);
16236 arg1 = gimple_call_arg (stmt, 1);
16237 lhs = gimple_call_lhs (stmt);
16238 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
16239 gimple_set_location (g, gimple_location (stmt));
16240 gsi_replace (gsi, g, true);
16242 /* Flavors of vec_div (Float). */
16243 case VSX_BUILTIN_XVDIVSP:
16244 case VSX_BUILTIN_XVDIVDP:
16245 arg0 = gimple_call_arg (stmt, 0);
16246 arg1 = gimple_call_arg (stmt, 1);
16247 lhs = gimple_call_lhs (stmt);
16248 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
16249 gimple_set_location (g, gimple_location (stmt));
16250 gsi_replace (gsi, g, true);
16252 /* Flavors of vec_and. */
16253 case ALTIVEC_BUILTIN_VAND:
16254 arg0 = gimple_call_arg (stmt, 0);
16255 arg1 = gimple_call_arg (stmt, 1);
16256 lhs = gimple_call_lhs (stmt);
16257 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
16258 gimple_set_location (g, gimple_location (stmt));
16259 gsi_replace (gsi, g, true);
16261 /* Flavors of vec_andc. */
16262 case ALTIVEC_BUILTIN_VANDC:
16263 arg0 = gimple_call_arg (stmt, 0);
16264 arg1 = gimple_call_arg (stmt, 1);
16265 lhs = gimple_call_lhs (stmt);
16266 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16267 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16268 gimple_set_location (g, gimple_location (stmt));
16269 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16270 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
16271 gimple_set_location (g, gimple_location (stmt));
16272 gsi_replace (gsi, g, true);
16274 /* Flavors of vec_nand. */
16275 case P8V_BUILTIN_VEC_NAND:
16276 case P8V_BUILTIN_NAND_V16QI:
16277 case P8V_BUILTIN_NAND_V8HI:
16278 case P8V_BUILTIN_NAND_V4SI:
16279 case P8V_BUILTIN_NAND_V4SF:
16280 case P8V_BUILTIN_NAND_V2DF:
16281 case P8V_BUILTIN_NAND_V2DI:
16282 arg0 = gimple_call_arg (stmt, 0);
16283 arg1 = gimple_call_arg (stmt, 1);
16284 lhs = gimple_call_lhs (stmt);
16285 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16286 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
16287 gimple_set_location (g, gimple_location (stmt));
16288 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16289 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16290 gimple_set_location (g, gimple_location (stmt));
16291 gsi_replace (gsi, g, true);
16293 /* Flavors of vec_or. */
16294 case ALTIVEC_BUILTIN_VOR:
16295 arg0 = gimple_call_arg (stmt, 0);
16296 arg1 = gimple_call_arg (stmt, 1);
16297 lhs = gimple_call_lhs (stmt);
16298 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
16299 gimple_set_location (g, gimple_location (stmt));
16300 gsi_replace (gsi, g, true);
16302 /* flavors of vec_orc. */
16303 case P8V_BUILTIN_ORC_V16QI:
16304 case P8V_BUILTIN_ORC_V8HI:
16305 case P8V_BUILTIN_ORC_V4SI:
16306 case P8V_BUILTIN_ORC_V4SF:
16307 case P8V_BUILTIN_ORC_V2DF:
16308 case P8V_BUILTIN_ORC_V2DI:
16309 arg0 = gimple_call_arg (stmt, 0);
16310 arg1 = gimple_call_arg (stmt, 1);
16311 lhs = gimple_call_lhs (stmt);
16312 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16313 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16314 gimple_set_location (g, gimple_location (stmt));
16315 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16316 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
16317 gimple_set_location (g, gimple_location (stmt));
16318 gsi_replace (gsi, g, true);
16320 /* Flavors of vec_xor. */
16321 case ALTIVEC_BUILTIN_VXOR:
16322 arg0 = gimple_call_arg (stmt, 0);
16323 arg1 = gimple_call_arg (stmt, 1);
16324 lhs = gimple_call_lhs (stmt);
16325 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
16326 gimple_set_location (g, gimple_location (stmt));
16327 gsi_replace (gsi, g, true);
16329 /* Flavors of vec_nor. */
16330 case ALTIVEC_BUILTIN_VNOR:
16331 arg0 = gimple_call_arg (stmt, 0);
16332 arg1 = gimple_call_arg (stmt, 1);
16333 lhs = gimple_call_lhs (stmt);
16334 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16335 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
16336 gimple_set_location (g, gimple_location (stmt));
16337 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16338 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16339 gimple_set_location (g, gimple_location (stmt));
16340 gsi_replace (gsi, g, true);
16342 /* flavors of vec_abs. */
16343 case ALTIVEC_BUILTIN_ABS_V16QI:
16344 case ALTIVEC_BUILTIN_ABS_V8HI:
16345 case ALTIVEC_BUILTIN_ABS_V4SI:
16346 case ALTIVEC_BUILTIN_ABS_V4SF:
16347 case P8V_BUILTIN_ABS_V2DI:
16348 case VSX_BUILTIN_XVABSDP:
16349 arg0 = gimple_call_arg (stmt, 0);
16350 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16351 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16353 lhs = gimple_call_lhs (stmt);
16354 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
16355 gimple_set_location (g, gimple_location (stmt));
16356 gsi_replace (gsi, g, true);
16358 /* flavors of vec_min. */
16359 case VSX_BUILTIN_XVMINDP:
16360 case P8V_BUILTIN_VMINSD:
16361 case P8V_BUILTIN_VMINUD:
16362 case ALTIVEC_BUILTIN_VMINSB:
16363 case ALTIVEC_BUILTIN_VMINSH:
16364 case ALTIVEC_BUILTIN_VMINSW:
16365 case ALTIVEC_BUILTIN_VMINUB:
16366 case ALTIVEC_BUILTIN_VMINUH:
16367 case ALTIVEC_BUILTIN_VMINUW:
16368 case ALTIVEC_BUILTIN_VMINFP:
16369 arg0 = gimple_call_arg (stmt, 0);
16370 arg1 = gimple_call_arg (stmt, 1);
16371 lhs = gimple_call_lhs (stmt);
16372 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
16373 gimple_set_location (g, gimple_location (stmt));
16374 gsi_replace (gsi, g, true);
16376 /* flavors of vec_max. */
16377 case VSX_BUILTIN_XVMAXDP:
16378 case P8V_BUILTIN_VMAXSD:
16379 case P8V_BUILTIN_VMAXUD:
16380 case ALTIVEC_BUILTIN_VMAXSB:
16381 case ALTIVEC_BUILTIN_VMAXSH:
16382 case ALTIVEC_BUILTIN_VMAXSW:
16383 case ALTIVEC_BUILTIN_VMAXUB:
16384 case ALTIVEC_BUILTIN_VMAXUH:
16385 case ALTIVEC_BUILTIN_VMAXUW:
16386 case ALTIVEC_BUILTIN_VMAXFP:
16387 arg0 = gimple_call_arg (stmt, 0);
16388 arg1 = gimple_call_arg (stmt, 1);
16389 lhs = gimple_call_lhs (stmt);
16390 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
16391 gimple_set_location (g, gimple_location (stmt));
16392 gsi_replace (gsi, g, true);
16394 /* Flavors of vec_eqv. */
16395 case P8V_BUILTIN_EQV_V16QI:
16396 case P8V_BUILTIN_EQV_V8HI:
16397 case P8V_BUILTIN_EQV_V4SI:
16398 case P8V_BUILTIN_EQV_V4SF:
16399 case P8V_BUILTIN_EQV_V2DF:
16400 case P8V_BUILTIN_EQV_V2DI:
16401 arg0 = gimple_call_arg (stmt, 0);
16402 arg1 = gimple_call_arg (stmt, 1);
16403 lhs = gimple_call_lhs (stmt);
16404 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16405 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
16406 gimple_set_location (g, gimple_location (stmt));
16407 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16408 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16409 gimple_set_location (g, gimple_location (stmt));
16410 gsi_replace (gsi, g, true);
16412 /* Flavors of vec_rotate_left. */
16413 case ALTIVEC_BUILTIN_VRLB:
16414 case ALTIVEC_BUILTIN_VRLH:
16415 case ALTIVEC_BUILTIN_VRLW:
16416 case P8V_BUILTIN_VRLD:
16417 arg0 = gimple_call_arg (stmt, 0);
16418 arg1 = gimple_call_arg (stmt, 1);
16419 lhs = gimple_call_lhs (stmt);
16420 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
16421 gimple_set_location (g, gimple_location (stmt));
16422 gsi_replace (gsi, g, true);
16424 /* Flavors of vector shift right algebraic.
16425 vec_sra{b,h,w} -> vsra{b,h,w}. */
16426 case ALTIVEC_BUILTIN_VSRAB:
16427 case ALTIVEC_BUILTIN_VSRAH:
16428 case ALTIVEC_BUILTIN_VSRAW:
16429 case P8V_BUILTIN_VSRAD:
16430 arg0 = gimple_call_arg (stmt, 0);
16431 arg1 = gimple_call_arg (stmt, 1);
16432 lhs = gimple_call_lhs (stmt);
16433 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
16434 gimple_set_location (g, gimple_location (stmt));
16435 gsi_replace (gsi, g, true);
16437 /* Flavors of vector shift left.
16438 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
16439 case ALTIVEC_BUILTIN_VSLB:
16440 case ALTIVEC_BUILTIN_VSLH:
16441 case ALTIVEC_BUILTIN_VSLW:
16442 case P8V_BUILTIN_VSLD:
16443 arg0 = gimple_call_arg (stmt, 0);
16444 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16445 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16447 arg1 = gimple_call_arg (stmt, 1);
16448 lhs = gimple_call_lhs (stmt);
16449 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
16450 gimple_set_location (g, gimple_location (stmt));
16451 gsi_replace (gsi, g, true);
16453 /* Flavors of vector shift right. */
16454 case ALTIVEC_BUILTIN_VSRB:
16455 case ALTIVEC_BUILTIN_VSRH:
16456 case ALTIVEC_BUILTIN_VSRW:
16457 case P8V_BUILTIN_VSRD:
16459 arg0 = gimple_call_arg (stmt, 0);
16460 arg1 = gimple_call_arg (stmt, 1);
16461 lhs = gimple_call_lhs (stmt);
16462 gimple_seq stmts = NULL;
16463 /* Convert arg0 to unsigned. */
16465 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
16466 unsigned_type_for (TREE_TYPE (arg0)), arg0);
16468 = gimple_build (&stmts, RSHIFT_EXPR,
16469 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
16470 /* Convert result back to the lhs type. */
16471 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
16472 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16473 update_call_from_tree (gsi, res);
16476 /* Vector loads. */
16477 case ALTIVEC_BUILTIN_LVX_V16QI:
16478 case ALTIVEC_BUILTIN_LVX_V8HI:
16479 case ALTIVEC_BUILTIN_LVX_V4SI:
16480 case ALTIVEC_BUILTIN_LVX_V4SF:
16481 case ALTIVEC_BUILTIN_LVX_V2DI:
16482 case ALTIVEC_BUILTIN_LVX_V2DF:
16484 arg0 = gimple_call_arg (stmt, 0); // offset
16485 arg1 = gimple_call_arg (stmt, 1); // address
16486 /* Do not fold for -maltivec=be on LE targets. */
16487 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16489 lhs = gimple_call_lhs (stmt);
16490 location_t loc = gimple_location (stmt);
16491 /* Since arg1 may be cast to a different type, just use ptr_type_node
16492 here instead of trying to enforce TBAA on pointer types. */
16493 tree arg1_type = ptr_type_node;
16494 tree lhs_type = TREE_TYPE (lhs);
16495 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16496 the tree using the value from arg0. The resulting type will match
16497 the type of arg1. */
16498 gimple_seq stmts = NULL;
16499 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
16500 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16501 arg1_type, arg1, temp_offset);
16502 /* Mask off any lower bits from the address. */
16503 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16504 arg1_type, temp_addr,
16505 build_int_cst (arg1_type, -16));
16506 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16507 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
16508 take an offset, but since we've already incorporated the offset
16509 above, here we just pass in a zero. */
16511 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
16512 build_int_cst (arg1_type, 0)));
16513 gimple_set_location (g, loc);
16514 gsi_replace (gsi, g, true);
16517 /* Vector stores. */
16518 case ALTIVEC_BUILTIN_STVX_V16QI:
16519 case ALTIVEC_BUILTIN_STVX_V8HI:
16520 case ALTIVEC_BUILTIN_STVX_V4SI:
16521 case ALTIVEC_BUILTIN_STVX_V4SF:
16522 case ALTIVEC_BUILTIN_STVX_V2DI:
16523 case ALTIVEC_BUILTIN_STVX_V2DF:
16525 /* Do not fold for -maltivec=be on LE targets. */
16526 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16528 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
16529 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
16530 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
16531 location_t loc = gimple_location (stmt);
16532 tree arg0_type = TREE_TYPE (arg0);
16533 /* Use ptr_type_node (no TBAA) for the arg2_type.
16534 FIXME: (Richard) "A proper fix would be to transition this type as
16535 seen from the frontend to GIMPLE, for example in a similar way we
16536 do for MEM_REFs by piggy-backing that on an extra argument, a
16537 constant zero pointer of the alias pointer type to use (which would
16538 also serve as a type indicator of the store itself). I'd use a
16539 target specific internal function for this (not sure if we can have
16540 those target specific, but I guess if it's folded away then that's
16541 fine) and get away with the overload set." */
16542 tree arg2_type = ptr_type_node;
16543 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16544 the tree using the value from arg0. The resulting type will match
16545 the type of arg2. */
16546 gimple_seq stmts = NULL;
16547 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
16548 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16549 arg2_type, arg2, temp_offset);
16550 /* Mask off any lower bits from the address. */
16551 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16552 arg2_type, temp_addr,
16553 build_int_cst (arg2_type, -16));
16554 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16555 /* The desired gimple result should be similar to:
16556 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
16558 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
16559 build_int_cst (arg2_type, 0)), arg0);
16560 gimple_set_location (g, loc);
16561 gsi_replace (gsi, g, true);
16565 /* Vector Fused multiply-add (fma). */
16566 case ALTIVEC_BUILTIN_VMADDFP:
16567 case VSX_BUILTIN_XVMADDDP:
16568 case ALTIVEC_BUILTIN_VMLADDUHM:
16570 arg0 = gimple_call_arg (stmt, 0);
16571 arg1 = gimple_call_arg (stmt, 1);
16572 tree arg2 = gimple_call_arg (stmt, 2);
16573 lhs = gimple_call_lhs (stmt);
16574 gimple *g = gimple_build_assign (lhs, FMA_EXPR, arg0, arg1, arg2);
16575 gimple_set_location (g, gimple_location (stmt));
16576 gsi_replace (gsi, g, true);
16580 /* Vector compares; EQ, NE, GE, GT, LE. */
16581 case ALTIVEC_BUILTIN_VCMPEQUB:
16582 case ALTIVEC_BUILTIN_VCMPEQUH:
16583 case ALTIVEC_BUILTIN_VCMPEQUW:
16584 case P8V_BUILTIN_VCMPEQUD:
16585 fold_compare_helper (gsi, EQ_EXPR, stmt);
16588 case P9V_BUILTIN_CMPNEB:
16589 case P9V_BUILTIN_CMPNEH:
16590 case P9V_BUILTIN_CMPNEW:
16591 fold_compare_helper (gsi, NE_EXPR, stmt);
16594 case VSX_BUILTIN_CMPGE_16QI:
16595 case VSX_BUILTIN_CMPGE_U16QI:
16596 case VSX_BUILTIN_CMPGE_8HI:
16597 case VSX_BUILTIN_CMPGE_U8HI:
16598 case VSX_BUILTIN_CMPGE_4SI:
16599 case VSX_BUILTIN_CMPGE_U4SI:
16600 case VSX_BUILTIN_CMPGE_2DI:
16601 case VSX_BUILTIN_CMPGE_U2DI:
16602 fold_compare_helper (gsi, GE_EXPR, stmt);
16605 case ALTIVEC_BUILTIN_VCMPGTSB:
16606 case ALTIVEC_BUILTIN_VCMPGTUB:
16607 case ALTIVEC_BUILTIN_VCMPGTSH:
16608 case ALTIVEC_BUILTIN_VCMPGTUH:
16609 case ALTIVEC_BUILTIN_VCMPGTSW:
16610 case ALTIVEC_BUILTIN_VCMPGTUW:
16611 case P8V_BUILTIN_VCMPGTUD:
16612 case P8V_BUILTIN_VCMPGTSD:
16613 fold_compare_helper (gsi, GT_EXPR, stmt);
16616 case VSX_BUILTIN_CMPLE_16QI:
16617 case VSX_BUILTIN_CMPLE_U16QI:
16618 case VSX_BUILTIN_CMPLE_8HI:
16619 case VSX_BUILTIN_CMPLE_U8HI:
16620 case VSX_BUILTIN_CMPLE_4SI:
16621 case VSX_BUILTIN_CMPLE_U4SI:
16622 case VSX_BUILTIN_CMPLE_2DI:
16623 case VSX_BUILTIN_CMPLE_U2DI:
16624 fold_compare_helper (gsi, LE_EXPR, stmt);
16627 /* flavors of vec_splat_[us]{8,16,32}. */
16628 case ALTIVEC_BUILTIN_VSPLTISB:
16629 case ALTIVEC_BUILTIN_VSPLTISH:
16630 case ALTIVEC_BUILTIN_VSPLTISW:
16632 arg0 = gimple_call_arg (stmt, 0);
16633 lhs = gimple_call_lhs (stmt);
16634 /* Only fold the vec_splat_*() if arg0 is constant. */
16635 if (TREE_CODE (arg0) != INTEGER_CST)
16637 gimple_seq stmts = NULL;
16638 location_t loc = gimple_location (stmt);
16639 tree splat_value = gimple_convert (&stmts, loc,
16640 TREE_TYPE (TREE_TYPE (lhs)), arg0);
16641 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16642 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
16643 g = gimple_build_assign (lhs, splat_tree);
16644 gimple_set_location (g, gimple_location (stmt));
16645 gsi_replace (gsi, g, true);
16650 if (TARGET_DEBUG_BUILTIN)
16651 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16652 fn_code, fn_name1, fn_name2);
16659 /* Expand an expression EXP that calls a built-in function,
16660 with result going to TARGET if that's convenient
16661 (and in mode MODE if that's convenient).
16662 SUBTARGET may be used as the target for computing one of EXP's operands.
16663 IGNORE is nonzero if the value is to be ignored. */
16666 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16667 machine_mode mode ATTRIBUTE_UNUSED,
16668 int ignore ATTRIBUTE_UNUSED)
16670 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16671 enum rs6000_builtins fcode
16672 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16673 size_t uns_fcode = (size_t)fcode;
16674 const struct builtin_description *d;
16678 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16679 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16680 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16682 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16683 floating point type, depending on whether long double is the IBM extended
16684 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16685 we only define one variant of the built-in function, and switch the code
16686 when defining it, rather than defining two built-ins and using the
16687 overload table in rs6000-c.c to switch between the two. If we don't have
16688 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16689 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16690 #ifdef HAVE_AS_POWER9
16691 if (FLOAT128_IEEE_P (TFmode))
16697 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16698 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16699 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16700 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16701 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16702 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16703 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16704 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16705 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16706 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16707 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16708 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16709 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16713 if (TARGET_DEBUG_BUILTIN)
16715 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16716 const char *name2 = (icode != CODE_FOR_nothing)
16717 ? get_insn_name ((int) icode)
16721 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16723 default: name3 = "unknown"; break;
16724 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16725 case RS6000_BTC_UNARY: name3 = "unary"; break;
16726 case RS6000_BTC_BINARY: name3 = "binary"; break;
16727 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16728 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16729 case RS6000_BTC_ABS: name3 = "abs"; break;
16730 case RS6000_BTC_DST: name3 = "dst"; break;
16735 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16736 (name1) ? name1 : "---", fcode,
16737 (name2) ? name2 : "---", (int) icode,
16739 func_valid_p ? "" : ", not valid");
16744 rs6000_invalid_builtin (fcode);
16746 /* Given it is invalid, just generate a normal call. */
16747 return expand_call (exp, target, ignore);
16752 case RS6000_BUILTIN_RECIP:
16753 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16755 case RS6000_BUILTIN_RECIPF:
16756 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16758 case RS6000_BUILTIN_RSQRTF:
16759 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16761 case RS6000_BUILTIN_RSQRT:
16762 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16764 case POWER7_BUILTIN_BPERMD:
16765 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16766 ? CODE_FOR_bpermd_di
16767 : CODE_FOR_bpermd_si), exp, target);
16769 case RS6000_BUILTIN_GET_TB:
16770 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16773 case RS6000_BUILTIN_MFTB:
16774 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16775 ? CODE_FOR_rs6000_mftb_di
16776 : CODE_FOR_rs6000_mftb_si),
16779 case RS6000_BUILTIN_MFFS:
16780 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16782 case RS6000_BUILTIN_MTFSF:
16783 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16785 case RS6000_BUILTIN_CPU_INIT:
16786 case RS6000_BUILTIN_CPU_IS:
16787 case RS6000_BUILTIN_CPU_SUPPORTS:
16788 return cpu_expand_builtin (fcode, exp, target);
16790 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16791 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16793 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16794 : (int) CODE_FOR_altivec_lvsl_direct);
16795 machine_mode tmode = insn_data[icode2].operand[0].mode;
16796 machine_mode mode = insn_data[icode2].operand[1].mode;
16800 gcc_assert (TARGET_ALTIVEC);
16802 arg = CALL_EXPR_ARG (exp, 0);
16803 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16804 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16805 addr = memory_address (mode, op);
16806 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16810 /* For the load case need to negate the address. */
16811 op = gen_reg_rtx (GET_MODE (addr));
16812 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16814 op = gen_rtx_MEM (mode, op);
16817 || GET_MODE (target) != tmode
16818 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16819 target = gen_reg_rtx (tmode);
16821 pat = GEN_FCN (icode2) (target, op);
16829 case ALTIVEC_BUILTIN_VCFUX:
16830 case ALTIVEC_BUILTIN_VCFSX:
16831 case ALTIVEC_BUILTIN_VCTUXS:
16832 case ALTIVEC_BUILTIN_VCTSXS:
16833 /* FIXME: There's got to be a nicer way to handle this case than
16834 constructing a new CALL_EXPR. */
16835 if (call_expr_nargs (exp) == 1)
16837 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16838 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16846 if (TARGET_ALTIVEC)
16848 ret = altivec_expand_builtin (exp, target, &success);
16853 if (TARGET_PAIRED_FLOAT)
16855 ret = paired_expand_builtin (exp, target, &success);
16862 ret = htm_expand_builtin (exp, target, &success);
16868 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16869 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16870 gcc_assert (attr == RS6000_BTC_UNARY
16871 || attr == RS6000_BTC_BINARY
16872 || attr == RS6000_BTC_TERNARY
16873 || attr == RS6000_BTC_SPECIAL);
16875 /* Handle simple unary operations. */
16877 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16878 if (d->code == fcode)
16879 return rs6000_expand_unop_builtin (icode, exp, target);
16881 /* Handle simple binary operations. */
16883 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16884 if (d->code == fcode)
16885 return rs6000_expand_binop_builtin (icode, exp, target);
16887 /* Handle simple ternary operations. */
16889 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16890 if (d->code == fcode)
16891 return rs6000_expand_ternop_builtin (icode, exp, target);
16893 /* Handle simple no-argument operations. */
16895 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16896 if (d->code == fcode)
16897 return rs6000_expand_zeroop_builtin (icode, target);
16899 gcc_unreachable ();
16902 /* Create a builtin vector type with a name. Taking care not to give
16903 the canonical type a name. */
16906 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16908 tree result = build_vector_type (elt_type, num_elts);
16910 /* Copy so we don't give the canonical type a name. */
16911 result = build_variant_type_copy (result);
16913 add_builtin_type (name, result);
16919 rs6000_init_builtins (void)
16925 if (TARGET_DEBUG_BUILTIN)
16926 fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
16927 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
16928 (TARGET_ALTIVEC) ? ", altivec" : "",
16929 (TARGET_VSX) ? ", vsx" : "");
16931 V2SI_type_node = build_vector_type (intSI_type_node, 2);
16932 V2SF_type_node = build_vector_type (float_type_node, 2);
16933 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16934 : "__vector long long",
16935 intDI_type_node, 2);
16936 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16937 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16938 intSI_type_node, 4);
16939 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16940 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16941 intHI_type_node, 8);
16942 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16943 intQI_type_node, 16);
16945 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16946 unsigned_intQI_type_node, 16);
16947 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16948 unsigned_intHI_type_node, 8);
16949 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16950 unsigned_intSI_type_node, 4);
16951 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16952 ? "__vector unsigned long"
16953 : "__vector unsigned long long",
16954 unsigned_intDI_type_node, 2);
16956 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
16957 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
16958 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
16959 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16961 const_str_type_node
16962 = build_pointer_type (build_qualified_type (char_type_node,
16965 /* We use V1TI mode as a special container to hold __int128_t items that
16966 must live in VSX registers. */
16967 if (intTI_type_node)
16969 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16970 intTI_type_node, 1);
16971 unsigned_V1TI_type_node
16972 = rs6000_vector_type ("__vector unsigned __int128",
16973 unsigned_intTI_type_node, 1);
16976 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16977 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16978 'vector unsigned short'. */
16980 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16981 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16982 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16983 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16984 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16986 long_integer_type_internal_node = long_integer_type_node;
16987 long_unsigned_type_internal_node = long_unsigned_type_node;
16988 long_long_integer_type_internal_node = long_long_integer_type_node;
16989 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16990 intQI_type_internal_node = intQI_type_node;
16991 uintQI_type_internal_node = unsigned_intQI_type_node;
16992 intHI_type_internal_node = intHI_type_node;
16993 uintHI_type_internal_node = unsigned_intHI_type_node;
16994 intSI_type_internal_node = intSI_type_node;
16995 uintSI_type_internal_node = unsigned_intSI_type_node;
16996 intDI_type_internal_node = intDI_type_node;
16997 uintDI_type_internal_node = unsigned_intDI_type_node;
16998 intTI_type_internal_node = intTI_type_node;
16999 uintTI_type_internal_node = unsigned_intTI_type_node;
17000 float_type_internal_node = float_type_node;
17001 double_type_internal_node = double_type_node;
17002 long_double_type_internal_node = long_double_type_node;
17003 dfloat64_type_internal_node = dfloat64_type_node;
17004 dfloat128_type_internal_node = dfloat128_type_node;
17005 void_type_internal_node = void_type_node;
17007 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
17008 IFmode is the IBM extended 128-bit format that is a pair of doubles.
17009 TFmode will be either IEEE 128-bit floating point or the IBM double-double
17010 format that uses a pair of doubles, depending on the switches and
17013 If we don't support for either 128-bit IBM double double or IEEE 128-bit
17014 floating point, we need make sure the type is non-zero or else self-test
17015 fails during bootstrap.
17017 We don't register a built-in type for __ibm128 if the type is the same as
17018 long double. Instead we add a #define for __ibm128 in
17019 rs6000_cpu_cpp_builtins to long double.
17021 For IEEE 128-bit floating point, always create the type __ieee128. If the
17022 user used -mfloat128, rs6000-c.c will create a define from __float128 to
17024 if (TARGET_LONG_DOUBLE_128 && FLOAT128_IEEE_P (TFmode))
17026 ibm128_float_type_node = make_node (REAL_TYPE);
17027 TYPE_PRECISION (ibm128_float_type_node) = 128;
17028 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
17029 layout_type (ibm128_float_type_node);
17031 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
17035 ibm128_float_type_node = long_double_type_node;
17037 if (TARGET_FLOAT128_TYPE)
17039 ieee128_float_type_node = float128_type_node;
17040 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
17045 ieee128_float_type_node = long_double_type_node;
17047 /* Initialize the modes for builtin_function_type, mapping a machine mode to
17049 builtin_mode_to_type[QImode][0] = integer_type_node;
17050 builtin_mode_to_type[HImode][0] = integer_type_node;
17051 builtin_mode_to_type[SImode][0] = intSI_type_node;
17052 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
17053 builtin_mode_to_type[DImode][0] = intDI_type_node;
17054 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
17055 builtin_mode_to_type[TImode][0] = intTI_type_node;
17056 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
17057 builtin_mode_to_type[SFmode][0] = float_type_node;
17058 builtin_mode_to_type[DFmode][0] = double_type_node;
17059 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
17060 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
17061 builtin_mode_to_type[TFmode][0] = long_double_type_node;
17062 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
17063 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
17064 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
17065 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
17066 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
17067 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
17068 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
17069 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
17070 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
17071 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
17072 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
17073 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
17074 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
17075 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
17076 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
17077 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
17079 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
17080 TYPE_NAME (bool_char_type_node) = tdecl;
17082 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
17083 TYPE_NAME (bool_short_type_node) = tdecl;
17085 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
17086 TYPE_NAME (bool_int_type_node) = tdecl;
17088 tdecl = add_builtin_type ("__pixel", pixel_type_node);
17089 TYPE_NAME (pixel_type_node) = tdecl;
17091 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
17092 bool_char_type_node, 16);
17093 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
17094 bool_short_type_node, 8);
17095 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
17096 bool_int_type_node, 4);
17097 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17098 ? "__vector __bool long"
17099 : "__vector __bool long long",
17100 bool_long_type_node, 2);
17101 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
17102 pixel_type_node, 8);
17104 /* Paired builtins are only available if you build a compiler with the
17105 appropriate options, so only create those builtins with the appropriate
17106 compiler option. Create Altivec and VSX builtins on machines with at
17107 least the general purpose extensions (970 and newer) to allow the use of
17108 the target attribute. */
17109 if (TARGET_PAIRED_FLOAT)
17110 paired_init_builtins ();
17111 if (TARGET_EXTRA_BUILTINS)
17112 altivec_init_builtins ();
17114 htm_init_builtins ();
17116 if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
17117 rs6000_common_init_builtins ();
17119 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
17120 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
17121 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
17123 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
17124 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
17125 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
17127 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
17128 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
17129 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
17131 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
17132 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
17133 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
17135 mode = (TARGET_64BIT) ? DImode : SImode;
17136 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
17137 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
17138 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
17140 ftype = build_function_type_list (unsigned_intDI_type_node,
17142 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
17145 ftype = build_function_type_list (unsigned_intDI_type_node,
17148 ftype = build_function_type_list (unsigned_intSI_type_node,
17150 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
17152 ftype = build_function_type_list (double_type_node, NULL_TREE);
17153 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
17155 ftype = build_function_type_list (void_type_node,
17156 intSI_type_node, double_type_node,
17158 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
17160 ftype = build_function_type_list (void_type_node, NULL_TREE);
17161 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
17163 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
17165 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
17166 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
17168 /* AIX libm provides clog as __clog. */
17169 if (TARGET_XCOFF &&
17170 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
17171 set_user_assembler_name (tdecl, "__clog");
17173 #ifdef SUBTARGET_INIT_BUILTINS
17174 SUBTARGET_INIT_BUILTINS;
17178 /* Returns the rs6000 builtin decl for CODE. */
17181 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
17183 HOST_WIDE_INT fnmask;
17185 if (code >= RS6000_BUILTIN_COUNT)
17186 return error_mark_node;
17188 fnmask = rs6000_builtin_info[code].mask;
17189 if ((fnmask & rs6000_builtin_mask) != fnmask)
17191 rs6000_invalid_builtin ((enum rs6000_builtins)code);
17192 return error_mark_node;
17195 return rs6000_builtin_decls[code];
17199 paired_init_builtins (void)
17201 const struct builtin_description *d;
17203 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17205 tree int_ftype_int_v2sf_v2sf
17206 = build_function_type_list (integer_type_node,
17211 tree pcfloat_type_node =
17212 build_pointer_type (build_qualified_type
17213 (float_type_node, TYPE_QUAL_CONST));
17215 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
17216 long_integer_type_node,
17219 tree void_ftype_v2sf_long_pcfloat =
17220 build_function_type_list (void_type_node,
17222 long_integer_type_node,
17227 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
17228 PAIRED_BUILTIN_LX);
17231 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
17232 PAIRED_BUILTIN_STX);
17235 d = bdesc_paired_preds;
17236 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
17239 HOST_WIDE_INT mask = d->mask;
17241 if ((mask & builtin_mask) != mask)
17243 if (TARGET_DEBUG_BUILTIN)
17244 fprintf (stderr, "paired_init_builtins, skip predicate %s\n",
17249 /* Cannot define builtin if the instruction is disabled. */
17250 gcc_assert (d->icode != CODE_FOR_nothing);
17252 if (TARGET_DEBUG_BUILTIN)
17253 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
17254 (int)i, get_insn_name (d->icode), (int)d->icode,
17255 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
17257 switch (insn_data[d->icode].operand[1].mode)
17260 type = int_ftype_int_v2sf_v2sf;
17263 gcc_unreachable ();
17266 def_builtin (d->name, type, d->code);
17271 altivec_init_builtins (void)
17273 const struct builtin_description *d;
17277 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17279 tree pvoid_type_node = build_pointer_type (void_type_node);
17281 tree pcvoid_type_node
17282 = build_pointer_type (build_qualified_type (void_type_node,
17285 tree int_ftype_opaque
17286 = build_function_type_list (integer_type_node,
17287 opaque_V4SI_type_node, NULL_TREE);
17288 tree opaque_ftype_opaque
17289 = build_function_type_list (integer_type_node, NULL_TREE);
17290 tree opaque_ftype_opaque_int
17291 = build_function_type_list (opaque_V4SI_type_node,
17292 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
17293 tree opaque_ftype_opaque_opaque_int
17294 = build_function_type_list (opaque_V4SI_type_node,
17295 opaque_V4SI_type_node, opaque_V4SI_type_node,
17296 integer_type_node, NULL_TREE);
17297 tree opaque_ftype_opaque_opaque_opaque
17298 = build_function_type_list (opaque_V4SI_type_node,
17299 opaque_V4SI_type_node, opaque_V4SI_type_node,
17300 opaque_V4SI_type_node, NULL_TREE);
17301 tree opaque_ftype_opaque_opaque
17302 = build_function_type_list (opaque_V4SI_type_node,
17303 opaque_V4SI_type_node, opaque_V4SI_type_node,
17305 tree int_ftype_int_opaque_opaque
17306 = build_function_type_list (integer_type_node,
17307 integer_type_node, opaque_V4SI_type_node,
17308 opaque_V4SI_type_node, NULL_TREE);
17309 tree int_ftype_int_v4si_v4si
17310 = build_function_type_list (integer_type_node,
17311 integer_type_node, V4SI_type_node,
17312 V4SI_type_node, NULL_TREE);
17313 tree int_ftype_int_v2di_v2di
17314 = build_function_type_list (integer_type_node,
17315 integer_type_node, V2DI_type_node,
17316 V2DI_type_node, NULL_TREE);
17317 tree void_ftype_v4si
17318 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
17319 tree v8hi_ftype_void
17320 = build_function_type_list (V8HI_type_node, NULL_TREE);
17321 tree void_ftype_void
17322 = build_function_type_list (void_type_node, NULL_TREE);
17323 tree void_ftype_int
17324 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
17326 tree opaque_ftype_long_pcvoid
17327 = build_function_type_list (opaque_V4SI_type_node,
17328 long_integer_type_node, pcvoid_type_node,
17330 tree v16qi_ftype_long_pcvoid
17331 = build_function_type_list (V16QI_type_node,
17332 long_integer_type_node, pcvoid_type_node,
17334 tree v8hi_ftype_long_pcvoid
17335 = build_function_type_list (V8HI_type_node,
17336 long_integer_type_node, pcvoid_type_node,
17338 tree v4si_ftype_long_pcvoid
17339 = build_function_type_list (V4SI_type_node,
17340 long_integer_type_node, pcvoid_type_node,
17342 tree v4sf_ftype_long_pcvoid
17343 = build_function_type_list (V4SF_type_node,
17344 long_integer_type_node, pcvoid_type_node,
17346 tree v2df_ftype_long_pcvoid
17347 = build_function_type_list (V2DF_type_node,
17348 long_integer_type_node, pcvoid_type_node,
17350 tree v2di_ftype_long_pcvoid
17351 = build_function_type_list (V2DI_type_node,
17352 long_integer_type_node, pcvoid_type_node,
17355 tree void_ftype_opaque_long_pvoid
17356 = build_function_type_list (void_type_node,
17357 opaque_V4SI_type_node, long_integer_type_node,
17358 pvoid_type_node, NULL_TREE);
17359 tree void_ftype_v4si_long_pvoid
17360 = build_function_type_list (void_type_node,
17361 V4SI_type_node, long_integer_type_node,
17362 pvoid_type_node, NULL_TREE);
17363 tree void_ftype_v16qi_long_pvoid
17364 = build_function_type_list (void_type_node,
17365 V16QI_type_node, long_integer_type_node,
17366 pvoid_type_node, NULL_TREE);
17368 tree void_ftype_v16qi_pvoid_long
17369 = build_function_type_list (void_type_node,
17370 V16QI_type_node, pvoid_type_node,
17371 long_integer_type_node, NULL_TREE);
17373 tree void_ftype_v8hi_long_pvoid
17374 = build_function_type_list (void_type_node,
17375 V8HI_type_node, long_integer_type_node,
17376 pvoid_type_node, NULL_TREE);
17377 tree void_ftype_v4sf_long_pvoid
17378 = build_function_type_list (void_type_node,
17379 V4SF_type_node, long_integer_type_node,
17380 pvoid_type_node, NULL_TREE);
17381 tree void_ftype_v2df_long_pvoid
17382 = build_function_type_list (void_type_node,
17383 V2DF_type_node, long_integer_type_node,
17384 pvoid_type_node, NULL_TREE);
17385 tree void_ftype_v2di_long_pvoid
17386 = build_function_type_list (void_type_node,
17387 V2DI_type_node, long_integer_type_node,
17388 pvoid_type_node, NULL_TREE);
17389 tree int_ftype_int_v8hi_v8hi
17390 = build_function_type_list (integer_type_node,
17391 integer_type_node, V8HI_type_node,
17392 V8HI_type_node, NULL_TREE);
17393 tree int_ftype_int_v16qi_v16qi
17394 = build_function_type_list (integer_type_node,
17395 integer_type_node, V16QI_type_node,
17396 V16QI_type_node, NULL_TREE);
17397 tree int_ftype_int_v4sf_v4sf
17398 = build_function_type_list (integer_type_node,
17399 integer_type_node, V4SF_type_node,
17400 V4SF_type_node, NULL_TREE);
17401 tree int_ftype_int_v2df_v2df
17402 = build_function_type_list (integer_type_node,
17403 integer_type_node, V2DF_type_node,
17404 V2DF_type_node, NULL_TREE);
17405 tree v2di_ftype_v2di
17406 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
17407 tree v4si_ftype_v4si
17408 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
17409 tree v8hi_ftype_v8hi
17410 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
17411 tree v16qi_ftype_v16qi
17412 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
17413 tree v4sf_ftype_v4sf
17414 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
17415 tree v2df_ftype_v2df
17416 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
17417 tree void_ftype_pcvoid_int_int
17418 = build_function_type_list (void_type_node,
17419 pcvoid_type_node, integer_type_node,
17420 integer_type_node, NULL_TREE);
17422 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
17423 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
17424 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
17425 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
17426 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
17427 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
17428 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
17429 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
17430 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
17431 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
17432 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
17433 ALTIVEC_BUILTIN_LVXL_V2DF);
17434 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
17435 ALTIVEC_BUILTIN_LVXL_V2DI);
17436 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
17437 ALTIVEC_BUILTIN_LVXL_V4SF);
17438 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
17439 ALTIVEC_BUILTIN_LVXL_V4SI);
17440 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
17441 ALTIVEC_BUILTIN_LVXL_V8HI);
17442 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
17443 ALTIVEC_BUILTIN_LVXL_V16QI);
17444 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
17445 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
17446 ALTIVEC_BUILTIN_LVX_V2DF);
17447 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
17448 ALTIVEC_BUILTIN_LVX_V2DI);
17449 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
17450 ALTIVEC_BUILTIN_LVX_V4SF);
17451 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
17452 ALTIVEC_BUILTIN_LVX_V4SI);
17453 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
17454 ALTIVEC_BUILTIN_LVX_V8HI);
17455 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
17456 ALTIVEC_BUILTIN_LVX_V16QI);
17457 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
17458 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
17459 ALTIVEC_BUILTIN_STVX_V2DF);
17460 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
17461 ALTIVEC_BUILTIN_STVX_V2DI);
17462 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
17463 ALTIVEC_BUILTIN_STVX_V4SF);
17464 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
17465 ALTIVEC_BUILTIN_STVX_V4SI);
17466 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
17467 ALTIVEC_BUILTIN_STVX_V8HI);
17468 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
17469 ALTIVEC_BUILTIN_STVX_V16QI);
17470 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
17471 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
17472 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
17473 ALTIVEC_BUILTIN_STVXL_V2DF);
17474 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
17475 ALTIVEC_BUILTIN_STVXL_V2DI);
17476 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
17477 ALTIVEC_BUILTIN_STVXL_V4SF);
17478 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
17479 ALTIVEC_BUILTIN_STVXL_V4SI);
17480 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
17481 ALTIVEC_BUILTIN_STVXL_V8HI);
17482 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
17483 ALTIVEC_BUILTIN_STVXL_V16QI);
17484 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
17485 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
17486 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
17487 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
17488 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
17489 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
17490 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
17491 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
17492 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
17493 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
17494 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
17495 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
17496 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
17497 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
17498 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
17499 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
17501 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
17502 VSX_BUILTIN_LXVD2X_V2DF);
17503 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
17504 VSX_BUILTIN_LXVD2X_V2DI);
17505 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
17506 VSX_BUILTIN_LXVW4X_V4SF);
17507 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
17508 VSX_BUILTIN_LXVW4X_V4SI);
17509 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
17510 VSX_BUILTIN_LXVW4X_V8HI);
17511 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
17512 VSX_BUILTIN_LXVW4X_V16QI);
17513 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
17514 VSX_BUILTIN_STXVD2X_V2DF);
17515 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
17516 VSX_BUILTIN_STXVD2X_V2DI);
17517 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
17518 VSX_BUILTIN_STXVW4X_V4SF);
17519 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
17520 VSX_BUILTIN_STXVW4X_V4SI);
17521 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
17522 VSX_BUILTIN_STXVW4X_V8HI);
17523 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
17524 VSX_BUILTIN_STXVW4X_V16QI);
17526 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
17527 VSX_BUILTIN_LD_ELEMREV_V2DF);
17528 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
17529 VSX_BUILTIN_LD_ELEMREV_V2DI);
17530 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
17531 VSX_BUILTIN_LD_ELEMREV_V4SF);
17532 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
17533 VSX_BUILTIN_LD_ELEMREV_V4SI);
17534 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
17535 VSX_BUILTIN_LD_ELEMREV_V8HI);
17536 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
17537 VSX_BUILTIN_LD_ELEMREV_V16QI);
17538 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
17539 VSX_BUILTIN_ST_ELEMREV_V2DF);
17540 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
17541 VSX_BUILTIN_ST_ELEMREV_V2DI);
17542 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
17543 VSX_BUILTIN_ST_ELEMREV_V4SF);
17544 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
17545 VSX_BUILTIN_ST_ELEMREV_V4SI);
17546 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
17547 VSX_BUILTIN_ST_ELEMREV_V8HI);
17548 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
17549 VSX_BUILTIN_ST_ELEMREV_V16QI);
17551 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
17552 VSX_BUILTIN_VEC_LD);
17553 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
17554 VSX_BUILTIN_VEC_ST);
17555 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
17556 VSX_BUILTIN_VEC_XL);
17557 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
17558 VSX_BUILTIN_VEC_XL_BE);
17559 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
17560 VSX_BUILTIN_VEC_XST);
17561 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
17562 VSX_BUILTIN_VEC_XST_BE);
17564 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
17565 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
17566 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
17568 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
17569 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
17570 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
17571 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
17572 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
17573 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
17574 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
17575 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
17576 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
17577 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
17578 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
17579 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
17581 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
17582 ALTIVEC_BUILTIN_VEC_ADDE);
17583 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
17584 ALTIVEC_BUILTIN_VEC_ADDEC);
17585 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
17586 ALTIVEC_BUILTIN_VEC_CMPNE);
17587 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
17588 ALTIVEC_BUILTIN_VEC_MUL);
17589 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
17590 ALTIVEC_BUILTIN_VEC_SUBE);
17591 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
17592 ALTIVEC_BUILTIN_VEC_SUBEC);
17594 /* Cell builtins. */
17595 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
17596 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
17597 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
17598 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
17600 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
17601 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
17602 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
17603 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
17605 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
17606 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
17607 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
17608 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
17610 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
17611 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
17612 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
17613 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
17615 if (TARGET_P9_VECTOR)
17617 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
17618 P9V_BUILTIN_STXVL);
17619 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
17620 P9V_BUILTIN_XST_LEN_R);
17623 /* Add the DST variants. */
17625 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
17627 HOST_WIDE_INT mask = d->mask;
17629 /* It is expected that these dst built-in functions may have
17630 d->icode equal to CODE_FOR_nothing. */
17631 if ((mask & builtin_mask) != mask)
17633 if (TARGET_DEBUG_BUILTIN)
17634 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
17638 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
17641 /* Initialize the predicates. */
17642 d = bdesc_altivec_preds;
17643 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
17645 machine_mode mode1;
17647 HOST_WIDE_INT mask = d->mask;
17649 if ((mask & builtin_mask) != mask)
17651 if (TARGET_DEBUG_BUILTIN)
17652 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
17657 if (rs6000_overloaded_builtin_p (d->code))
17661 /* Cannot define builtin if the instruction is disabled. */
17662 gcc_assert (d->icode != CODE_FOR_nothing);
17663 mode1 = insn_data[d->icode].operand[1].mode;
17669 type = int_ftype_int_opaque_opaque;
17672 type = int_ftype_int_v2di_v2di;
17675 type = int_ftype_int_v4si_v4si;
17678 type = int_ftype_int_v8hi_v8hi;
17681 type = int_ftype_int_v16qi_v16qi;
17684 type = int_ftype_int_v4sf_v4sf;
17687 type = int_ftype_int_v2df_v2df;
17690 gcc_unreachable ();
17693 def_builtin (d->name, type, d->code);
17696 /* Initialize the abs* operators. */
17698 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17700 machine_mode mode0;
17702 HOST_WIDE_INT mask = d->mask;
17704 if ((mask & builtin_mask) != mask)
17706 if (TARGET_DEBUG_BUILTIN)
17707 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17712 /* Cannot define builtin if the instruction is disabled. */
17713 gcc_assert (d->icode != CODE_FOR_nothing);
17714 mode0 = insn_data[d->icode].operand[0].mode;
17719 type = v2di_ftype_v2di;
17722 type = v4si_ftype_v4si;
17725 type = v8hi_ftype_v8hi;
17728 type = v16qi_ftype_v16qi;
17731 type = v4sf_ftype_v4sf;
17734 type = v2df_ftype_v2df;
17737 gcc_unreachable ();
17740 def_builtin (d->name, type, d->code);
17743 /* Initialize target builtin that implements
17744 targetm.vectorize.builtin_mask_for_load. */
17746 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17747 v16qi_ftype_long_pcvoid,
17748 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17749 BUILT_IN_MD, NULL, NULL_TREE);
17750 TREE_READONLY (decl) = 1;
17751 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17752 altivec_builtin_mask_for_load = decl;
17754 /* Access to the vec_init patterns. */
17755 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17756 integer_type_node, integer_type_node,
17757 integer_type_node, NULL_TREE);
17758 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17760 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17761 short_integer_type_node,
17762 short_integer_type_node,
17763 short_integer_type_node,
17764 short_integer_type_node,
17765 short_integer_type_node,
17766 short_integer_type_node,
17767 short_integer_type_node, NULL_TREE);
17768 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17770 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17771 char_type_node, char_type_node,
17772 char_type_node, char_type_node,
17773 char_type_node, char_type_node,
17774 char_type_node, char_type_node,
17775 char_type_node, char_type_node,
17776 char_type_node, char_type_node,
17777 char_type_node, char_type_node,
17778 char_type_node, NULL_TREE);
17779 def_builtin ("__builtin_vec_init_v16qi", ftype,
17780 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17782 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17783 float_type_node, float_type_node,
17784 float_type_node, NULL_TREE);
17785 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17787 /* VSX builtins. */
17788 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17789 double_type_node, NULL_TREE);
17790 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17792 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17793 intDI_type_node, NULL_TREE);
17794 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17796 /* Access to the vec_set patterns. */
17797 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17799 integer_type_node, NULL_TREE);
17800 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17802 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17804 integer_type_node, NULL_TREE);
17805 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17807 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17809 integer_type_node, NULL_TREE);
17810 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17812 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17814 integer_type_node, NULL_TREE);
17815 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17817 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17819 integer_type_node, NULL_TREE);
17820 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17822 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17824 integer_type_node, NULL_TREE);
17825 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17827 /* Access to the vec_extract patterns. */
17828 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17829 integer_type_node, NULL_TREE);
17830 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17832 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17833 integer_type_node, NULL_TREE);
17834 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17836 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17837 integer_type_node, NULL_TREE);
17838 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17840 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17841 integer_type_node, NULL_TREE);
17842 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17844 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17845 integer_type_node, NULL_TREE);
17846 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17848 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17849 integer_type_node, NULL_TREE);
17850 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17853 if (V1TI_type_node)
17855 tree v1ti_ftype_long_pcvoid
17856 = build_function_type_list (V1TI_type_node,
17857 long_integer_type_node, pcvoid_type_node,
17859 tree void_ftype_v1ti_long_pvoid
17860 = build_function_type_list (void_type_node,
17861 V1TI_type_node, long_integer_type_node,
17862 pvoid_type_node, NULL_TREE);
17863 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17864 VSX_BUILTIN_LXVD2X_V1TI);
17865 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17866 VSX_BUILTIN_STXVD2X_V1TI);
17867 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17868 NULL_TREE, NULL_TREE);
17869 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17870 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17872 integer_type_node, NULL_TREE);
17873 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17874 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17875 integer_type_node, NULL_TREE);
17876 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17882 htm_init_builtins (void)
17884 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17885 const struct builtin_description *d;
17889 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17891 tree op[MAX_HTM_OPERANDS], type;
17892 HOST_WIDE_INT mask = d->mask;
17893 unsigned attr = rs6000_builtin_info[d->code].attr;
17894 bool void_func = (attr & RS6000_BTC_VOID);
17895 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17897 tree gpr_type_node;
17901 /* It is expected that these htm built-in functions may have
17902 d->icode equal to CODE_FOR_nothing. */
17904 if (TARGET_32BIT && TARGET_POWERPC64)
17905 gpr_type_node = long_long_unsigned_type_node;
17907 gpr_type_node = long_unsigned_type_node;
17909 if (attr & RS6000_BTC_SPR)
17911 rettype = gpr_type_node;
17912 argtype = gpr_type_node;
17914 else if (d->code == HTM_BUILTIN_TABORTDC
17915 || d->code == HTM_BUILTIN_TABORTDCI)
17917 rettype = unsigned_type_node;
17918 argtype = gpr_type_node;
17922 rettype = unsigned_type_node;
17923 argtype = unsigned_type_node;
17926 if ((mask & builtin_mask) != mask)
17928 if (TARGET_DEBUG_BUILTIN)
17929 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17935 if (TARGET_DEBUG_BUILTIN)
17936 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17937 (long unsigned) i);
17941 op[nopnds++] = (void_func) ? void_type_node : rettype;
17943 if (attr_args == RS6000_BTC_UNARY)
17944 op[nopnds++] = argtype;
17945 else if (attr_args == RS6000_BTC_BINARY)
17947 op[nopnds++] = argtype;
17948 op[nopnds++] = argtype;
17950 else if (attr_args == RS6000_BTC_TERNARY)
17952 op[nopnds++] = argtype;
17953 op[nopnds++] = argtype;
17954 op[nopnds++] = argtype;
17960 type = build_function_type_list (op[0], NULL_TREE);
17963 type = build_function_type_list (op[0], op[1], NULL_TREE);
17966 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17969 type = build_function_type_list (op[0], op[1], op[2], op[3],
17973 gcc_unreachable ();
17976 def_builtin (d->name, type, d->code);
17980 /* Hash function for builtin functions with up to 3 arguments and a return
17983 builtin_hasher::hash (builtin_hash_struct *bh)
17988 for (i = 0; i < 4; i++)
17990 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17991 ret = (ret * 2) + bh->uns_p[i];
17997 /* Compare builtin hash entries H1 and H2 for equivalence. */
17999 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
18001 return ((p1->mode[0] == p2->mode[0])
18002 && (p1->mode[1] == p2->mode[1])
18003 && (p1->mode[2] == p2->mode[2])
18004 && (p1->mode[3] == p2->mode[3])
18005 && (p1->uns_p[0] == p2->uns_p[0])
18006 && (p1->uns_p[1] == p2->uns_p[1])
18007 && (p1->uns_p[2] == p2->uns_p[2])
18008 && (p1->uns_p[3] == p2->uns_p[3]));
18011 /* Map types for builtin functions with an explicit return type and up to 3
18012 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
18013 of the argument. */
18015 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
18016 machine_mode mode_arg1, machine_mode mode_arg2,
18017 enum rs6000_builtins builtin, const char *name)
18019 struct builtin_hash_struct h;
18020 struct builtin_hash_struct *h2;
18023 tree ret_type = NULL_TREE;
18024 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
18026 /* Create builtin_hash_table. */
18027 if (builtin_hash_table == NULL)
18028 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
18030 h.type = NULL_TREE;
18031 h.mode[0] = mode_ret;
18032 h.mode[1] = mode_arg0;
18033 h.mode[2] = mode_arg1;
18034 h.mode[3] = mode_arg2;
18040 /* If the builtin is a type that produces unsigned results or takes unsigned
18041 arguments, and it is returned as a decl for the vectorizer (such as
18042 widening multiplies, permute), make sure the arguments and return value
18043 are type correct. */
18046 /* unsigned 1 argument functions. */
18047 case CRYPTO_BUILTIN_VSBOX:
18048 case P8V_BUILTIN_VGBBD:
18049 case MISC_BUILTIN_CDTBCD:
18050 case MISC_BUILTIN_CBCDTD:
18055 /* unsigned 2 argument functions. */
18056 case ALTIVEC_BUILTIN_VMULEUB:
18057 case ALTIVEC_BUILTIN_VMULEUH:
18058 case ALTIVEC_BUILTIN_VMULEUW:
18059 case ALTIVEC_BUILTIN_VMULOUB:
18060 case ALTIVEC_BUILTIN_VMULOUH:
18061 case ALTIVEC_BUILTIN_VMULOUW:
18062 case CRYPTO_BUILTIN_VCIPHER:
18063 case CRYPTO_BUILTIN_VCIPHERLAST:
18064 case CRYPTO_BUILTIN_VNCIPHER:
18065 case CRYPTO_BUILTIN_VNCIPHERLAST:
18066 case CRYPTO_BUILTIN_VPMSUMB:
18067 case CRYPTO_BUILTIN_VPMSUMH:
18068 case CRYPTO_BUILTIN_VPMSUMW:
18069 case CRYPTO_BUILTIN_VPMSUMD:
18070 case CRYPTO_BUILTIN_VPMSUM:
18071 case MISC_BUILTIN_ADDG6S:
18072 case MISC_BUILTIN_DIVWEU:
18073 case MISC_BUILTIN_DIVWEUO:
18074 case MISC_BUILTIN_DIVDEU:
18075 case MISC_BUILTIN_DIVDEUO:
18076 case VSX_BUILTIN_UDIV_V2DI:
18077 case ALTIVEC_BUILTIN_VMAXUB:
18078 case ALTIVEC_BUILTIN_VMINUB:
18079 case ALTIVEC_BUILTIN_VMAXUH:
18080 case ALTIVEC_BUILTIN_VMINUH:
18081 case ALTIVEC_BUILTIN_VMAXUW:
18082 case ALTIVEC_BUILTIN_VMINUW:
18083 case P8V_BUILTIN_VMAXUD:
18084 case P8V_BUILTIN_VMINUD:
18090 /* unsigned 3 argument functions. */
18091 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
18092 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
18093 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
18094 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
18095 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
18096 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
18097 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
18098 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
18099 case VSX_BUILTIN_VPERM_16QI_UNS:
18100 case VSX_BUILTIN_VPERM_8HI_UNS:
18101 case VSX_BUILTIN_VPERM_4SI_UNS:
18102 case VSX_BUILTIN_VPERM_2DI_UNS:
18103 case VSX_BUILTIN_XXSEL_16QI_UNS:
18104 case VSX_BUILTIN_XXSEL_8HI_UNS:
18105 case VSX_BUILTIN_XXSEL_4SI_UNS:
18106 case VSX_BUILTIN_XXSEL_2DI_UNS:
18107 case CRYPTO_BUILTIN_VPERMXOR:
18108 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
18109 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
18110 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
18111 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
18112 case CRYPTO_BUILTIN_VSHASIGMAW:
18113 case CRYPTO_BUILTIN_VSHASIGMAD:
18114 case CRYPTO_BUILTIN_VSHASIGMA:
18121 /* signed permute functions with unsigned char mask. */
18122 case ALTIVEC_BUILTIN_VPERM_16QI:
18123 case ALTIVEC_BUILTIN_VPERM_8HI:
18124 case ALTIVEC_BUILTIN_VPERM_4SI:
18125 case ALTIVEC_BUILTIN_VPERM_4SF:
18126 case ALTIVEC_BUILTIN_VPERM_2DI:
18127 case ALTIVEC_BUILTIN_VPERM_2DF:
18128 case VSX_BUILTIN_VPERM_16QI:
18129 case VSX_BUILTIN_VPERM_8HI:
18130 case VSX_BUILTIN_VPERM_4SI:
18131 case VSX_BUILTIN_VPERM_4SF:
18132 case VSX_BUILTIN_VPERM_2DI:
18133 case VSX_BUILTIN_VPERM_2DF:
18137 /* unsigned args, signed return. */
18138 case VSX_BUILTIN_XVCVUXDSP:
18139 case VSX_BUILTIN_XVCVUXDDP_UNS:
18140 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
18144 /* signed args, unsigned return. */
18145 case VSX_BUILTIN_XVCVDPUXDS_UNS:
18146 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
18147 case MISC_BUILTIN_UNPACK_TD:
18148 case MISC_BUILTIN_UNPACK_V1TI:
18152 /* unsigned arguments, bool return (compares). */
18153 case ALTIVEC_BUILTIN_VCMPEQUB:
18154 case ALTIVEC_BUILTIN_VCMPEQUH:
18155 case ALTIVEC_BUILTIN_VCMPEQUW:
18156 case P8V_BUILTIN_VCMPEQUD:
18157 case VSX_BUILTIN_CMPGE_U16QI:
18158 case VSX_BUILTIN_CMPGE_U8HI:
18159 case VSX_BUILTIN_CMPGE_U4SI:
18160 case VSX_BUILTIN_CMPGE_U2DI:
18161 case ALTIVEC_BUILTIN_VCMPGTUB:
18162 case ALTIVEC_BUILTIN_VCMPGTUH:
18163 case ALTIVEC_BUILTIN_VCMPGTUW:
18164 case P8V_BUILTIN_VCMPGTUD:
18169 /* unsigned arguments for 128-bit pack instructions. */
18170 case MISC_BUILTIN_PACK_TD:
18171 case MISC_BUILTIN_PACK_V1TI:
18176 /* unsigned second arguments (vector shift right). */
18177 case ALTIVEC_BUILTIN_VSRB:
18178 case ALTIVEC_BUILTIN_VSRH:
18179 case ALTIVEC_BUILTIN_VSRW:
18180 case P8V_BUILTIN_VSRD:
18188 /* Figure out how many args are present. */
18189 while (num_args > 0 && h.mode[num_args] == VOIDmode)
18192 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
18193 if (!ret_type && h.uns_p[0])
18194 ret_type = builtin_mode_to_type[h.mode[0]][0];
18197 fatal_error (input_location,
18198 "internal error: builtin function %qs had an unexpected "
18199 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
18201 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
18202 arg_type[i] = NULL_TREE;
18204 for (i = 0; i < num_args; i++)
18206 int m = (int) h.mode[i+1];
18207 int uns_p = h.uns_p[i+1];
18209 arg_type[i] = builtin_mode_to_type[m][uns_p];
18210 if (!arg_type[i] && uns_p)
18211 arg_type[i] = builtin_mode_to_type[m][0];
18214 fatal_error (input_location,
18215 "internal error: builtin function %qs, argument %d "
18216 "had unexpected argument type %qs", name, i,
18217 GET_MODE_NAME (m));
18220 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
18221 if (*found == NULL)
18223 h2 = ggc_alloc<builtin_hash_struct> ();
18227 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
18228 arg_type[2], NULL_TREE);
18231 return (*found)->type;
18235 rs6000_common_init_builtins (void)
18237 const struct builtin_description *d;
18240 tree opaque_ftype_opaque = NULL_TREE;
18241 tree opaque_ftype_opaque_opaque = NULL_TREE;
18242 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
18243 tree v2si_ftype = NULL_TREE;
18244 tree v2si_ftype_qi = NULL_TREE;
18245 tree v2si_ftype_v2si_qi = NULL_TREE;
18246 tree v2si_ftype_int_qi = NULL_TREE;
18247 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
18249 if (!TARGET_PAIRED_FLOAT)
18251 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
18252 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
18255 /* Paired builtins are only available if you build a compiler with the
18256 appropriate options, so only create those builtins with the appropriate
18257 compiler option. Create Altivec and VSX builtins on machines with at
18258 least the general purpose extensions (970 and newer) to allow the use of
18259 the target attribute.. */
18261 if (TARGET_EXTRA_BUILTINS)
18262 builtin_mask |= RS6000_BTM_COMMON;
18264 /* Add the ternary operators. */
18266 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
18269 HOST_WIDE_INT mask = d->mask;
18271 if ((mask & builtin_mask) != mask)
18273 if (TARGET_DEBUG_BUILTIN)
18274 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
18278 if (rs6000_overloaded_builtin_p (d->code))
18280 if (! (type = opaque_ftype_opaque_opaque_opaque))
18281 type = opaque_ftype_opaque_opaque_opaque
18282 = build_function_type_list (opaque_V4SI_type_node,
18283 opaque_V4SI_type_node,
18284 opaque_V4SI_type_node,
18285 opaque_V4SI_type_node,
18290 enum insn_code icode = d->icode;
18293 if (TARGET_DEBUG_BUILTIN)
18294 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
18300 if (icode == CODE_FOR_nothing)
18302 if (TARGET_DEBUG_BUILTIN)
18303 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
18309 type = builtin_function_type (insn_data[icode].operand[0].mode,
18310 insn_data[icode].operand[1].mode,
18311 insn_data[icode].operand[2].mode,
18312 insn_data[icode].operand[3].mode,
18316 def_builtin (d->name, type, d->code);
18319 /* Add the binary operators. */
18321 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
18323 machine_mode mode0, mode1, mode2;
18325 HOST_WIDE_INT mask = d->mask;
18327 if ((mask & builtin_mask) != mask)
18329 if (TARGET_DEBUG_BUILTIN)
18330 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
18334 if (rs6000_overloaded_builtin_p (d->code))
18336 if (! (type = opaque_ftype_opaque_opaque))
18337 type = opaque_ftype_opaque_opaque
18338 = build_function_type_list (opaque_V4SI_type_node,
18339 opaque_V4SI_type_node,
18340 opaque_V4SI_type_node,
18345 enum insn_code icode = d->icode;
18348 if (TARGET_DEBUG_BUILTIN)
18349 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18355 if (icode == CODE_FOR_nothing)
18357 if (TARGET_DEBUG_BUILTIN)
18358 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
18364 mode0 = insn_data[icode].operand[0].mode;
18365 mode1 = insn_data[icode].operand[1].mode;
18366 mode2 = insn_data[icode].operand[2].mode;
18368 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
18370 if (! (type = v2si_ftype_v2si_qi))
18371 type = v2si_ftype_v2si_qi
18372 = build_function_type_list (opaque_V2SI_type_node,
18373 opaque_V2SI_type_node,
18378 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
18379 && mode2 == QImode)
18381 if (! (type = v2si_ftype_int_qi))
18382 type = v2si_ftype_int_qi
18383 = build_function_type_list (opaque_V2SI_type_node,
18390 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
18394 def_builtin (d->name, type, d->code);
18397 /* Add the simple unary operators. */
18399 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
18401 machine_mode mode0, mode1;
18403 HOST_WIDE_INT mask = d->mask;
18405 if ((mask & builtin_mask) != mask)
18407 if (TARGET_DEBUG_BUILTIN)
18408 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
18412 if (rs6000_overloaded_builtin_p (d->code))
18414 if (! (type = opaque_ftype_opaque))
18415 type = opaque_ftype_opaque
18416 = build_function_type_list (opaque_V4SI_type_node,
18417 opaque_V4SI_type_node,
18422 enum insn_code icode = d->icode;
18425 if (TARGET_DEBUG_BUILTIN)
18426 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18432 if (icode == CODE_FOR_nothing)
18434 if (TARGET_DEBUG_BUILTIN)
18435 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
18441 mode0 = insn_data[icode].operand[0].mode;
18442 mode1 = insn_data[icode].operand[1].mode;
18444 if (mode0 == V2SImode && mode1 == QImode)
18446 if (! (type = v2si_ftype_qi))
18447 type = v2si_ftype_qi
18448 = build_function_type_list (opaque_V2SI_type_node,
18454 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
18458 def_builtin (d->name, type, d->code);
18461 /* Add the simple no-argument operators. */
18463 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
18465 machine_mode mode0;
18467 HOST_WIDE_INT mask = d->mask;
18469 if ((mask & builtin_mask) != mask)
18471 if (TARGET_DEBUG_BUILTIN)
18472 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
18475 if (rs6000_overloaded_builtin_p (d->code))
18477 if (!opaque_ftype_opaque)
18478 opaque_ftype_opaque
18479 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
18480 type = opaque_ftype_opaque;
18484 enum insn_code icode = d->icode;
18487 if (TARGET_DEBUG_BUILTIN)
18488 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18489 (long unsigned) i);
18492 if (icode == CODE_FOR_nothing)
18494 if (TARGET_DEBUG_BUILTIN)
18496 "rs6000_builtin, skip no-argument %s (no code)\n",
18500 mode0 = insn_data[icode].operand[0].mode;
18501 if (mode0 == V2SImode)
18503 /* code for paired single */
18504 if (! (type = v2si_ftype))
18507 = build_function_type_list (opaque_V2SI_type_node,
18513 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
18516 def_builtin (d->name, type, d->code);
18520 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18522 init_float128_ibm (machine_mode mode)
18524 if (!TARGET_XL_COMPAT)
18526 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
18527 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
18528 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
18529 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
18531 if (!TARGET_HARD_FLOAT)
18533 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
18534 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
18535 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
18536 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
18537 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
18538 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
18539 set_optab_libfunc (le_optab, mode, "__gcc_qle");
18540 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
18542 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
18543 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
18544 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
18545 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
18546 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
18547 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
18548 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
18549 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
18554 set_optab_libfunc (add_optab, mode, "_xlqadd");
18555 set_optab_libfunc (sub_optab, mode, "_xlqsub");
18556 set_optab_libfunc (smul_optab, mode, "_xlqmul");
18557 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
18560 /* Add various conversions for IFmode to use the traditional TFmode
18562 if (mode == IFmode)
18564 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
18565 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
18566 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
18567 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
18568 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
18569 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
18571 if (TARGET_POWERPC64)
18573 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
18574 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
18575 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
18576 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
18581 /* Set up IEEE 128-bit floating point routines. Use different names if the
18582 arguments can be passed in a vector register. The historical PowerPC
18583 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18584 continue to use that if we aren't using vector registers to pass IEEE
18585 128-bit floating point. */
18588 init_float128_ieee (machine_mode mode)
18590 if (FLOAT128_VECTOR_P (mode))
18592 set_optab_libfunc (add_optab, mode, "__addkf3");
18593 set_optab_libfunc (sub_optab, mode, "__subkf3");
18594 set_optab_libfunc (neg_optab, mode, "__negkf2");
18595 set_optab_libfunc (smul_optab, mode, "__mulkf3");
18596 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
18597 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
18598 set_optab_libfunc (abs_optab, mode, "__abstkf2");
18600 set_optab_libfunc (eq_optab, mode, "__eqkf2");
18601 set_optab_libfunc (ne_optab, mode, "__nekf2");
18602 set_optab_libfunc (gt_optab, mode, "__gtkf2");
18603 set_optab_libfunc (ge_optab, mode, "__gekf2");
18604 set_optab_libfunc (lt_optab, mode, "__ltkf2");
18605 set_optab_libfunc (le_optab, mode, "__lekf2");
18606 set_optab_libfunc (unord_optab, mode, "__unordkf2");
18608 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
18609 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
18610 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
18611 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
18613 set_conv_libfunc (sext_optab, mode, IFmode, "__extendtfkf2");
18614 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18615 set_conv_libfunc (sext_optab, mode, TFmode, "__extendtfkf2");
18617 set_conv_libfunc (trunc_optab, IFmode, mode, "__trunckftf2");
18618 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18619 set_conv_libfunc (trunc_optab, TFmode, mode, "__trunckftf2");
18621 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
18622 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
18623 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
18624 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
18625 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
18626 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
18628 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
18629 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
18630 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
18631 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
18633 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
18634 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
18635 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
18636 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
18638 if (TARGET_POWERPC64)
18640 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
18641 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
18642 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
18643 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
18649 set_optab_libfunc (add_optab, mode, "_q_add");
18650 set_optab_libfunc (sub_optab, mode, "_q_sub");
18651 set_optab_libfunc (neg_optab, mode, "_q_neg");
18652 set_optab_libfunc (smul_optab, mode, "_q_mul");
18653 set_optab_libfunc (sdiv_optab, mode, "_q_div");
18654 if (TARGET_PPC_GPOPT)
18655 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
18657 set_optab_libfunc (eq_optab, mode, "_q_feq");
18658 set_optab_libfunc (ne_optab, mode, "_q_fne");
18659 set_optab_libfunc (gt_optab, mode, "_q_fgt");
18660 set_optab_libfunc (ge_optab, mode, "_q_fge");
18661 set_optab_libfunc (lt_optab, mode, "_q_flt");
18662 set_optab_libfunc (le_optab, mode, "_q_fle");
18664 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
18665 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
18666 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
18667 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
18668 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
18669 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
18670 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
18671 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
18676 rs6000_init_libfuncs (void)
18678 /* __float128 support. */
18679 if (TARGET_FLOAT128_TYPE)
18681 init_float128_ibm (IFmode);
18682 init_float128_ieee (KFmode);
18685 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18686 if (TARGET_LONG_DOUBLE_128)
18688 if (!TARGET_IEEEQUAD)
18689 init_float128_ibm (TFmode);
18691 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18693 init_float128_ieee (TFmode);
18697 /* Emit a potentially record-form instruction, setting DST from SRC.
18698 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18699 signed comparison of DST with zero. If DOT is 1, the generated RTL
18700 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18701 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18702 a separate COMPARE. */
18705 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18709 emit_move_insn (dst, src);
18713 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18715 emit_move_insn (dst, src);
18716 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18720 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18723 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18724 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18728 rtx set = gen_rtx_SET (dst, src);
18729 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18734 /* A validation routine: say whether CODE, a condition code, and MODE
18735 match. The other alternatives either don't make sense or should
18736 never be generated. */
18739 validate_condition_mode (enum rtx_code code, machine_mode mode)
18741 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18742 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18743 && GET_MODE_CLASS (mode) == MODE_CC);
18745 /* These don't make sense. */
18746 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18747 || mode != CCUNSmode);
18749 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18750 || mode == CCUNSmode);
18752 gcc_assert (mode == CCFPmode
18753 || (code != ORDERED && code != UNORDERED
18754 && code != UNEQ && code != LTGT
18755 && code != UNGT && code != UNLT
18756 && code != UNGE && code != UNLE));
18758 /* These should never be generated except for
18759 flag_finite_math_only. */
18760 gcc_assert (mode != CCFPmode
18761 || flag_finite_math_only
18762 || (code != LE && code != GE
18763 && code != UNEQ && code != LTGT
18764 && code != UNGT && code != UNLT));
18766 /* These are invalid; the information is not there. */
18767 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18771 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18772 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18773 not zero, store there the bit offset (counted from the right) where
18774 the single stretch of 1 bits begins; and similarly for B, the bit
18775 offset where it ends. */
18778 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18780 unsigned HOST_WIDE_INT val = INTVAL (mask);
18781 unsigned HOST_WIDE_INT bit;
18783 int n = GET_MODE_PRECISION (mode);
18785 if (mode != DImode && mode != SImode)
18788 if (INTVAL (mask) >= 0)
18791 ne = exact_log2 (bit);
18792 nb = exact_log2 (val + bit);
18794 else if (val + 1 == 0)
18803 nb = exact_log2 (bit);
18804 ne = exact_log2 (val + bit);
18809 ne = exact_log2 (bit);
18810 if (val + bit == 0)
18818 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18829 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18830 or rldicr instruction, to implement an AND with it in mode MODE. */
18833 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18837 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18840 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18842 if (mode == DImode)
18843 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18845 /* For SImode, rlwinm can do everything. */
18846 if (mode == SImode)
18847 return (nb < 32 && ne < 32);
18852 /* Return the instruction template for an AND with mask in mode MODE, with
18853 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18856 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18860 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18861 gcc_unreachable ();
18863 if (mode == DImode && ne == 0)
18865 operands[3] = GEN_INT (63 - nb);
18867 return "rldicl. %0,%1,0,%3";
18868 return "rldicl %0,%1,0,%3";
18871 if (mode == DImode && nb == 63)
18873 operands[3] = GEN_INT (63 - ne);
18875 return "rldicr. %0,%1,0,%3";
18876 return "rldicr %0,%1,0,%3";
18879 if (nb < 32 && ne < 32)
18881 operands[3] = GEN_INT (31 - nb);
18882 operands[4] = GEN_INT (31 - ne);
18884 return "rlwinm. %0,%1,0,%3,%4";
18885 return "rlwinm %0,%1,0,%3,%4";
18888 gcc_unreachable ();
18891 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18892 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18893 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18896 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18900 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18903 int n = GET_MODE_PRECISION (mode);
18906 if (CONST_INT_P (XEXP (shift, 1)))
18908 sh = INTVAL (XEXP (shift, 1));
18909 if (sh < 0 || sh >= n)
18913 rtx_code code = GET_CODE (shift);
18915 /* Convert any shift by 0 to a rotate, to simplify below code. */
18919 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18920 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18922 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18928 /* DImode rotates need rld*. */
18929 if (mode == DImode && code == ROTATE)
18930 return (nb == 63 || ne == 0 || ne == sh);
18932 /* SImode rotates need rlw*. */
18933 if (mode == SImode && code == ROTATE)
18934 return (nb < 32 && ne < 32 && sh < 32);
18936 /* Wrap-around masks are only okay for rotates. */
18940 /* Variable shifts are only okay for rotates. */
18944 /* Don't allow ASHIFT if the mask is wrong for that. */
18945 if (code == ASHIFT && ne < sh)
18948 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18949 if the mask is wrong for that. */
18950 if (nb < 32 && ne < 32 && sh < 32
18951 && !(code == LSHIFTRT && nb >= 32 - sh))
18954 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18955 if the mask is wrong for that. */
18956 if (code == LSHIFTRT)
18958 if (nb == 63 || ne == 0 || ne == sh)
18959 return !(code == LSHIFTRT && nb >= sh);
18964 /* Return the instruction template for a shift with mask in mode MODE, with
18965 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18968 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18972 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18973 gcc_unreachable ();
18975 if (mode == DImode && ne == 0)
18977 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18978 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18979 operands[3] = GEN_INT (63 - nb);
18981 return "rld%I2cl. %0,%1,%2,%3";
18982 return "rld%I2cl %0,%1,%2,%3";
18985 if (mode == DImode && nb == 63)
18987 operands[3] = GEN_INT (63 - ne);
18989 return "rld%I2cr. %0,%1,%2,%3";
18990 return "rld%I2cr %0,%1,%2,%3";
18994 && GET_CODE (operands[4]) != LSHIFTRT
18995 && CONST_INT_P (operands[2])
18996 && ne == INTVAL (operands[2]))
18998 operands[3] = GEN_INT (63 - nb);
19000 return "rld%I2c. %0,%1,%2,%3";
19001 return "rld%I2c %0,%1,%2,%3";
19004 if (nb < 32 && ne < 32)
19006 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19007 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19008 operands[3] = GEN_INT (31 - nb);
19009 operands[4] = GEN_INT (31 - ne);
19010 /* This insn can also be a 64-bit rotate with mask that really makes
19011 it just a shift right (with mask); the %h below are to adjust for
19012 that situation (shift count is >= 32 in that case). */
19014 return "rlw%I2nm. %0,%1,%h2,%3,%4";
19015 return "rlw%I2nm %0,%1,%h2,%3,%4";
19018 gcc_unreachable ();
19021 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
19022 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
19023 ASHIFT, or LSHIFTRT) in mode MODE. */
19026 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
19030 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
19033 int n = GET_MODE_PRECISION (mode);
19035 int sh = INTVAL (XEXP (shift, 1));
19036 if (sh < 0 || sh >= n)
19039 rtx_code code = GET_CODE (shift);
19041 /* Convert any shift by 0 to a rotate, to simplify below code. */
19045 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19046 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19048 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19054 /* DImode rotates need rldimi. */
19055 if (mode == DImode && code == ROTATE)
19058 /* SImode rotates need rlwimi. */
19059 if (mode == SImode && code == ROTATE)
19060 return (nb < 32 && ne < 32 && sh < 32);
19062 /* Wrap-around masks are only okay for rotates. */
19066 /* Don't allow ASHIFT if the mask is wrong for that. */
19067 if (code == ASHIFT && ne < sh)
19070 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
19071 if the mask is wrong for that. */
19072 if (nb < 32 && ne < 32 && sh < 32
19073 && !(code == LSHIFTRT && nb >= 32 - sh))
19076 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
19077 if the mask is wrong for that. */
19078 if (code == LSHIFTRT)
19081 return !(code == LSHIFTRT && nb >= sh);
19086 /* Return the instruction template for an insert with mask in mode MODE, with
19087 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19090 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
19094 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19095 gcc_unreachable ();
19097 /* Prefer rldimi because rlwimi is cracked. */
19098 if (TARGET_POWERPC64
19099 && (!dot || mode == DImode)
19100 && GET_CODE (operands[4]) != LSHIFTRT
19101 && ne == INTVAL (operands[2]))
19103 operands[3] = GEN_INT (63 - nb);
19105 return "rldimi. %0,%1,%2,%3";
19106 return "rldimi %0,%1,%2,%3";
19109 if (nb < 32 && ne < 32)
19111 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19112 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19113 operands[3] = GEN_INT (31 - nb);
19114 operands[4] = GEN_INT (31 - ne);
19116 return "rlwimi. %0,%1,%2,%3,%4";
19117 return "rlwimi %0,%1,%2,%3,%4";
19120 gcc_unreachable ();
19123 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
19124 using two machine instructions. */
19127 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
19129 /* There are two kinds of AND we can handle with two insns:
19130 1) those we can do with two rl* insn;
19133 We do not handle that last case yet. */
19135 /* If there is just one stretch of ones, we can do it. */
19136 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
19139 /* Otherwise, fill in the lowest "hole"; if we can do the result with
19140 one insn, we can do the whole thing with two. */
19141 unsigned HOST_WIDE_INT val = INTVAL (c);
19142 unsigned HOST_WIDE_INT bit1 = val & -val;
19143 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19144 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19145 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19146 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
19149 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
19150 If EXPAND is true, split rotate-and-mask instructions we generate to
19151 their constituent parts as well (this is used during expand); if DOT
19152 is 1, make the last insn a record-form instruction clobbering the
19153 destination GPR and setting the CC reg (from operands[3]); if 2, set
19154 that GPR as well as the CC reg. */
19157 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
19159 gcc_assert (!(expand && dot));
19161 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
19163 /* If it is one stretch of ones, it is DImode; shift left, mask, then
19164 shift right. This generates better code than doing the masks without
19165 shifts, or shifting first right and then left. */
19167 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
19169 gcc_assert (mode == DImode);
19171 int shift = 63 - nb;
19174 rtx tmp1 = gen_reg_rtx (DImode);
19175 rtx tmp2 = gen_reg_rtx (DImode);
19176 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
19177 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
19178 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
19182 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
19183 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
19184 emit_move_insn (operands[0], tmp);
19185 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
19186 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19191 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
19192 that does the rest. */
19193 unsigned HOST_WIDE_INT bit1 = val & -val;
19194 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19195 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19196 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19198 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
19199 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
19201 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
19203 /* Two "no-rotate"-and-mask instructions, for SImode. */
19204 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
19206 gcc_assert (mode == SImode);
19208 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19209 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
19210 emit_move_insn (reg, tmp);
19211 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19212 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19216 gcc_assert (mode == DImode);
19218 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
19219 insns; we have to do the first in SImode, because it wraps. */
19220 if (mask2 <= 0xffffffff
19221 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
19223 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19224 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
19226 rtx reg_low = gen_lowpart (SImode, reg);
19227 emit_move_insn (reg_low, tmp);
19228 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19229 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19233 /* Two rld* insns: rotate, clear the hole in the middle (which now is
19234 at the top end), rotate back and clear the other hole. */
19235 int right = exact_log2 (bit3);
19236 int left = 64 - right;
19238 /* Rotate the mask too. */
19239 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
19243 rtx tmp1 = gen_reg_rtx (DImode);
19244 rtx tmp2 = gen_reg_rtx (DImode);
19245 rtx tmp3 = gen_reg_rtx (DImode);
19246 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
19247 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
19248 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
19249 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
19253 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
19254 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
19255 emit_move_insn (operands[0], tmp);
19256 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
19257 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
19258 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19262 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
19263 for lfq and stfq insns iff the registers are hard registers. */
19266 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
19268 /* We might have been passed a SUBREG. */
19269 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
19272 /* We might have been passed non floating point registers. */
19273 if (!FP_REGNO_P (REGNO (reg1))
19274 || !FP_REGNO_P (REGNO (reg2)))
19277 return (REGNO (reg1) == REGNO (reg2) - 1);
19280 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
19281 addr1 and addr2 must be in consecutive memory locations
19282 (addr2 == addr1 + 8). */
19285 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
19288 unsigned int reg1, reg2;
19289 int offset1, offset2;
19291 /* The mems cannot be volatile. */
19292 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
19295 addr1 = XEXP (mem1, 0);
19296 addr2 = XEXP (mem2, 0);
19298 /* Extract an offset (if used) from the first addr. */
19299 if (GET_CODE (addr1) == PLUS)
19301 /* If not a REG, return zero. */
19302 if (GET_CODE (XEXP (addr1, 0)) != REG)
19306 reg1 = REGNO (XEXP (addr1, 0));
19307 /* The offset must be constant! */
19308 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
19310 offset1 = INTVAL (XEXP (addr1, 1));
19313 else if (GET_CODE (addr1) != REG)
19317 reg1 = REGNO (addr1);
19318 /* This was a simple (mem (reg)) expression. Offset is 0. */
19322 /* And now for the second addr. */
19323 if (GET_CODE (addr2) == PLUS)
19325 /* If not a REG, return zero. */
19326 if (GET_CODE (XEXP (addr2, 0)) != REG)
19330 reg2 = REGNO (XEXP (addr2, 0));
19331 /* The offset must be constant. */
19332 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
19334 offset2 = INTVAL (XEXP (addr2, 1));
19337 else if (GET_CODE (addr2) != REG)
19341 reg2 = REGNO (addr2);
19342 /* This was a simple (mem (reg)) expression. Offset is 0. */
19346 /* Both of these must have the same base register. */
19350 /* The offset for the second addr must be 8 more than the first addr. */
19351 if (offset2 != offset1 + 8)
19354 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
19359 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
19360 need to use DDmode, in all other cases we can use the same mode. */
19361 static machine_mode
19362 rs6000_secondary_memory_needed_mode (machine_mode mode)
19364 if (lra_in_progress && mode == SDmode)
19369 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
19370 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
19371 only work on the traditional altivec registers, note if an altivec register
19374 static enum rs6000_reg_type
19375 register_to_reg_type (rtx reg, bool *is_altivec)
19377 HOST_WIDE_INT regno;
19378 enum reg_class rclass;
19380 if (GET_CODE (reg) == SUBREG)
19381 reg = SUBREG_REG (reg);
19384 return NO_REG_TYPE;
19386 regno = REGNO (reg);
19387 if (regno >= FIRST_PSEUDO_REGISTER)
19389 if (!lra_in_progress && !reload_completed)
19390 return PSEUDO_REG_TYPE;
19392 regno = true_regnum (reg);
19393 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
19394 return PSEUDO_REG_TYPE;
19397 gcc_assert (regno >= 0);
19399 if (is_altivec && ALTIVEC_REGNO_P (regno))
19400 *is_altivec = true;
19402 rclass = rs6000_regno_regclass[regno];
19403 return reg_class_to_reg_type[(int)rclass];
19406 /* Helper function to return the cost of adding a TOC entry address. */
19409 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
19413 if (TARGET_CMODEL != CMODEL_SMALL)
19414 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
19417 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
19422 /* Helper function for rs6000_secondary_reload to determine whether the memory
19423 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
19424 needs reloading. Return negative if the memory is not handled by the memory
19425 helper functions and to try a different reload method, 0 if no additional
19426 instructions are need, and positive to give the extra cost for the
19430 rs6000_secondary_reload_memory (rtx addr,
19431 enum reg_class rclass,
19434 int extra_cost = 0;
19435 rtx reg, and_arg, plus_arg0, plus_arg1;
19436 addr_mask_type addr_mask;
19437 const char *type = NULL;
19438 const char *fail_msg = NULL;
19440 if (GPR_REG_CLASS_P (rclass))
19441 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19443 else if (rclass == FLOAT_REGS)
19444 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19446 else if (rclass == ALTIVEC_REGS)
19447 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19449 /* For the combined VSX_REGS, turn off Altivec AND -16. */
19450 else if (rclass == VSX_REGS)
19451 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
19452 & ~RELOAD_REG_AND_M16);
19454 /* If the register allocator hasn't made up its mind yet on the register
19455 class to use, settle on defaults to use. */
19456 else if (rclass == NO_REGS)
19458 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
19459 & ~RELOAD_REG_AND_M16);
19461 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
19462 addr_mask &= ~(RELOAD_REG_INDEXED
19463 | RELOAD_REG_PRE_INCDEC
19464 | RELOAD_REG_PRE_MODIFY);
19470 /* If the register isn't valid in this register class, just return now. */
19471 if ((addr_mask & RELOAD_REG_VALID) == 0)
19473 if (TARGET_DEBUG_ADDR)
19476 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19477 "not valid in class\n",
19478 GET_MODE_NAME (mode), reg_class_names[rclass]);
19485 switch (GET_CODE (addr))
19487 /* Does the register class supports auto update forms for this mode? We
19488 don't need a scratch register, since the powerpc only supports
19489 PRE_INC, PRE_DEC, and PRE_MODIFY. */
19492 reg = XEXP (addr, 0);
19493 if (!base_reg_operand (addr, GET_MODE (reg)))
19495 fail_msg = "no base register #1";
19499 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19507 reg = XEXP (addr, 0);
19508 plus_arg1 = XEXP (addr, 1);
19509 if (!base_reg_operand (reg, GET_MODE (reg))
19510 || GET_CODE (plus_arg1) != PLUS
19511 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
19513 fail_msg = "bad PRE_MODIFY";
19517 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19524 /* Do we need to simulate AND -16 to clear the bottom address bits used
19525 in VMX load/stores? Only allow the AND for vector sizes. */
19527 and_arg = XEXP (addr, 0);
19528 if (GET_MODE_SIZE (mode) != 16
19529 || GET_CODE (XEXP (addr, 1)) != CONST_INT
19530 || INTVAL (XEXP (addr, 1)) != -16)
19532 fail_msg = "bad Altivec AND #1";
19536 if (rclass != ALTIVEC_REGS)
19538 if (legitimate_indirect_address_p (and_arg, false))
19541 else if (legitimate_indexed_address_p (and_arg, false))
19546 fail_msg = "bad Altivec AND #2";
19554 /* If this is an indirect address, make sure it is a base register. */
19557 if (!legitimate_indirect_address_p (addr, false))
19564 /* If this is an indexed address, make sure the register class can handle
19565 indexed addresses for this mode. */
19567 plus_arg0 = XEXP (addr, 0);
19568 plus_arg1 = XEXP (addr, 1);
19570 /* (plus (plus (reg) (constant)) (constant)) is generated during
19571 push_reload processing, so handle it now. */
19572 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
19574 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19581 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19582 push_reload processing, so handle it now. */
19583 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
19585 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19588 type = "indexed #2";
19592 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
19594 fail_msg = "no base register #2";
19598 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
19600 if ((addr_mask & RELOAD_REG_INDEXED) == 0
19601 || !legitimate_indexed_address_p (addr, false))
19608 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
19609 && CONST_INT_P (plus_arg1))
19611 if (!quad_address_offset_p (INTVAL (plus_arg1)))
19614 type = "vector d-form offset";
19618 /* Make sure the register class can handle offset addresses. */
19619 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19621 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19624 type = "offset #2";
19630 fail_msg = "bad PLUS";
19637 /* Quad offsets are restricted and can't handle normal addresses. */
19638 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19641 type = "vector d-form lo_sum";
19644 else if (!legitimate_lo_sum_address_p (mode, addr, false))
19646 fail_msg = "bad LO_SUM";
19650 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19657 /* Static addresses need to create a TOC entry. */
19661 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19664 type = "vector d-form lo_sum #2";
19670 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
19674 /* TOC references look like offsetable memory. */
19676 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
19678 fail_msg = "bad UNSPEC";
19682 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19685 type = "vector d-form lo_sum #3";
19688 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19691 type = "toc reference";
19697 fail_msg = "bad address";
19702 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19704 if (extra_cost < 0)
19706 "rs6000_secondary_reload_memory error: mode = %s, "
19707 "class = %s, addr_mask = '%s', %s\n",
19708 GET_MODE_NAME (mode),
19709 reg_class_names[rclass],
19710 rs6000_debug_addr_mask (addr_mask, false),
19711 (fail_msg != NULL) ? fail_msg : "<bad address>");
19715 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19716 "addr_mask = '%s', extra cost = %d, %s\n",
19717 GET_MODE_NAME (mode),
19718 reg_class_names[rclass],
19719 rs6000_debug_addr_mask (addr_mask, false),
19721 (type) ? type : "<none>");
19729 /* Helper function for rs6000_secondary_reload to return true if a move to a
19730 different register classe is really a simple move. */
19733 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19734 enum rs6000_reg_type from_type,
19737 int size = GET_MODE_SIZE (mode);
19739 /* Add support for various direct moves available. In this function, we only
19740 look at cases where we don't need any extra registers, and one or more
19741 simple move insns are issued. Originally small integers are not allowed
19742 in FPR/VSX registers. Single precision binary floating is not a simple
19743 move because we need to convert to the single precision memory layout.
19744 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19745 need special direct move handling, which we do not support yet. */
19746 if (TARGET_DIRECT_MOVE
19747 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19748 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19750 if (TARGET_POWERPC64)
19752 /* ISA 2.07: MTVSRD or MVFVSRD. */
19756 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19757 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19761 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19762 if (TARGET_P8_VECTOR)
19764 if (mode == SImode)
19767 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19771 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19772 if (mode == SDmode)
19776 /* Power6+: MFTGPR or MFFGPR. */
19777 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19778 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19779 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19782 /* Move to/from SPR. */
19783 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19784 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19785 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19791 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19792 special direct moves that involve allocating an extra register, return the
19793 insn code of the helper function if there is such a function or
19794 CODE_FOR_nothing if not. */
19797 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19798 enum rs6000_reg_type from_type,
19800 secondary_reload_info *sri,
19804 enum insn_code icode = CODE_FOR_nothing;
19806 int size = GET_MODE_SIZE (mode);
19808 if (TARGET_POWERPC64 && size == 16)
19810 /* Handle moving 128-bit values from GPRs to VSX point registers on
19811 ISA 2.07 (power8, power9) when running in 64-bit mode using
19812 XXPERMDI to glue the two 64-bit values back together. */
19813 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19815 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19816 icode = reg_addr[mode].reload_vsx_gpr;
19819 /* Handle moving 128-bit values from VSX point registers to GPRs on
19820 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19821 bottom 64-bit value. */
19822 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19824 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19825 icode = reg_addr[mode].reload_gpr_vsx;
19829 else if (TARGET_POWERPC64 && mode == SFmode)
19831 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19833 cost = 3; /* xscvdpspn, mfvsrd, and. */
19834 icode = reg_addr[mode].reload_gpr_vsx;
19837 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19839 cost = 2; /* mtvsrz, xscvspdpn. */
19840 icode = reg_addr[mode].reload_vsx_gpr;
19844 else if (!TARGET_POWERPC64 && size == 8)
19846 /* Handle moving 64-bit values from GPRs to floating point registers on
19847 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19848 32-bit values back together. Altivec register classes must be handled
19849 specially since a different instruction is used, and the secondary
19850 reload support requires a single instruction class in the scratch
19851 register constraint. However, right now TFmode is not allowed in
19852 Altivec registers, so the pattern will never match. */
19853 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19855 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19856 icode = reg_addr[mode].reload_fpr_gpr;
19860 if (icode != CODE_FOR_nothing)
19865 sri->icode = icode;
19866 sri->extra_cost = cost;
19873 /* Return whether a move between two register classes can be done either
19874 directly (simple move) or via a pattern that uses a single extra temporary
19875 (using ISA 2.07's direct move in this case. */
19878 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19879 enum rs6000_reg_type from_type,
19881 secondary_reload_info *sri,
19884 /* Fall back to load/store reloads if either type is not a register. */
19885 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19888 /* If we haven't allocated registers yet, assume the move can be done for the
19889 standard register types. */
19890 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19891 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19892 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19895 /* Moves to the same set of registers is a simple move for non-specialized
19897 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19900 /* Check whether a simple move can be done directly. */
19901 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19905 sri->icode = CODE_FOR_nothing;
19906 sri->extra_cost = 0;
19911 /* Now check if we can do it in a few steps. */
19912 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19916 /* Inform reload about cases where moving X with a mode MODE to a register in
19917 RCLASS requires an extra scratch or immediate register. Return the class
19918 needed for the immediate register.
19920 For VSX and Altivec, we may need a register to convert sp+offset into
19923 For misaligned 64-bit gpr loads and stores we need a register to
19924 convert an offset address to indirect. */
19927 rs6000_secondary_reload (bool in_p,
19929 reg_class_t rclass_i,
19931 secondary_reload_info *sri)
19933 enum reg_class rclass = (enum reg_class) rclass_i;
19934 reg_class_t ret = ALL_REGS;
19935 enum insn_code icode;
19936 bool default_p = false;
19937 bool done_p = false;
19939 /* Allow subreg of memory before/during reload. */
19940 bool memory_p = (MEM_P (x)
19941 || (!reload_completed && GET_CODE (x) == SUBREG
19942 && MEM_P (SUBREG_REG (x))));
19944 sri->icode = CODE_FOR_nothing;
19945 sri->t_icode = CODE_FOR_nothing;
19946 sri->extra_cost = 0;
19948 ? reg_addr[mode].reload_load
19949 : reg_addr[mode].reload_store);
19951 if (REG_P (x) || register_operand (x, mode))
19953 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19954 bool altivec_p = (rclass == ALTIVEC_REGS);
19955 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19958 std::swap (to_type, from_type);
19960 /* Can we do a direct move of some sort? */
19961 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19964 icode = (enum insn_code)sri->icode;
19971 /* Make sure 0.0 is not reloaded or forced into memory. */
19972 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19979 /* If this is a scalar floating point value and we want to load it into the
19980 traditional Altivec registers, do it via a move via a traditional floating
19981 point register, unless we have D-form addressing. Also make sure that
19982 non-zero constants use a FPR. */
19983 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19984 && !mode_supports_vmx_dform (mode)
19985 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19986 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
19993 /* Handle reload of load/stores if we have reload helper functions. */
19994 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19996 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19999 if (extra_cost >= 0)
20003 if (extra_cost > 0)
20005 sri->extra_cost = extra_cost;
20006 sri->icode = icode;
20011 /* Handle unaligned loads and stores of integer registers. */
20012 if (!done_p && TARGET_POWERPC64
20013 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20015 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
20017 rtx addr = XEXP (x, 0);
20018 rtx off = address_offset (addr);
20020 if (off != NULL_RTX)
20022 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20023 unsigned HOST_WIDE_INT offset = INTVAL (off);
20025 /* We need a secondary reload when our legitimate_address_p
20026 says the address is good (as otherwise the entire address
20027 will be reloaded), and the offset is not a multiple of
20028 four or we have an address wrap. Address wrap will only
20029 occur for LO_SUMs since legitimate_offset_address_p
20030 rejects addresses for 16-byte mems that will wrap. */
20031 if (GET_CODE (addr) == LO_SUM
20032 ? (1 /* legitimate_address_p allows any offset for lo_sum */
20033 && ((offset & 3) != 0
20034 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
20035 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
20036 && (offset & 3) != 0))
20038 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
20040 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
20041 : CODE_FOR_reload_di_load);
20043 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
20044 : CODE_FOR_reload_di_store);
20045 sri->extra_cost = 2;
20056 if (!done_p && !TARGET_POWERPC64
20057 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20059 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
20061 rtx addr = XEXP (x, 0);
20062 rtx off = address_offset (addr);
20064 if (off != NULL_RTX)
20066 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20067 unsigned HOST_WIDE_INT offset = INTVAL (off);
20069 /* We need a secondary reload when our legitimate_address_p
20070 says the address is good (as otherwise the entire address
20071 will be reloaded), and we have a wrap.
20073 legitimate_lo_sum_address_p allows LO_SUM addresses to
20074 have any offset so test for wrap in the low 16 bits.
20076 legitimate_offset_address_p checks for the range
20077 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
20078 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
20079 [0x7ff4,0x7fff] respectively, so test for the
20080 intersection of these ranges, [0x7ffc,0x7fff] and
20081 [0x7ff4,0x7ff7] respectively.
20083 Note that the address we see here may have been
20084 manipulated by legitimize_reload_address. */
20085 if (GET_CODE (addr) == LO_SUM
20086 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
20087 : offset - (0x8000 - extra) < UNITS_PER_WORD)
20090 sri->icode = CODE_FOR_reload_si_load;
20092 sri->icode = CODE_FOR_reload_si_store;
20093 sri->extra_cost = 2;
20108 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
20110 gcc_assert (ret != ALL_REGS);
20112 if (TARGET_DEBUG_ADDR)
20115 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
20117 reg_class_names[ret],
20118 in_p ? "true" : "false",
20119 reg_class_names[rclass],
20120 GET_MODE_NAME (mode));
20122 if (reload_completed)
20123 fputs (", after reload", stderr);
20126 fputs (", done_p not set", stderr);
20129 fputs (", default secondary reload", stderr);
20131 if (sri->icode != CODE_FOR_nothing)
20132 fprintf (stderr, ", reload func = %s, extra cost = %d",
20133 insn_data[sri->icode].name, sri->extra_cost);
20135 else if (sri->extra_cost > 0)
20136 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
20138 fputs ("\n", stderr);
20145 /* Better tracing for rs6000_secondary_reload_inner. */
20148 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
20153 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
20155 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
20156 store_p ? "store" : "load");
20159 set = gen_rtx_SET (mem, reg);
20161 set = gen_rtx_SET (reg, mem);
20163 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
20164 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
20167 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
20168 ATTRIBUTE_NORETURN;
20171 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
20174 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
20175 gcc_unreachable ();
20178 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
20179 reload helper functions. These were identified in
20180 rs6000_secondary_reload_memory, and if reload decided to use the secondary
20181 reload, it calls the insns:
20182 reload_<RELOAD:mode>_<P:mptrsize>_store
20183 reload_<RELOAD:mode>_<P:mptrsize>_load
20185 which in turn calls this function, to do whatever is necessary to create
20186 valid addresses. */
20189 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
20191 int regno = true_regnum (reg);
20192 machine_mode mode = GET_MODE (reg);
20193 addr_mask_type addr_mask;
20196 rtx op_reg, op0, op1;
20201 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
20202 || !base_reg_operand (scratch, GET_MODE (scratch)))
20203 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20205 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
20206 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
20208 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
20209 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
20211 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
20212 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
20215 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20217 /* Make sure the mode is valid in this register class. */
20218 if ((addr_mask & RELOAD_REG_VALID) == 0)
20219 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20221 if (TARGET_DEBUG_ADDR)
20222 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
20224 new_addr = addr = XEXP (mem, 0);
20225 switch (GET_CODE (addr))
20227 /* Does the register class support auto update forms for this mode? If
20228 not, do the update now. We don't need a scratch register, since the
20229 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
20232 op_reg = XEXP (addr, 0);
20233 if (!base_reg_operand (op_reg, Pmode))
20234 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20236 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
20238 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
20244 op0 = XEXP (addr, 0);
20245 op1 = XEXP (addr, 1);
20246 if (!base_reg_operand (op0, Pmode)
20247 || GET_CODE (op1) != PLUS
20248 || !rtx_equal_p (op0, XEXP (op1, 0)))
20249 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20251 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
20253 emit_insn (gen_rtx_SET (op0, op1));
20258 /* Do we need to simulate AND -16 to clear the bottom address bits used
20259 in VMX load/stores? */
20261 op0 = XEXP (addr, 0);
20262 op1 = XEXP (addr, 1);
20263 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
20265 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
20268 else if (GET_CODE (op1) == PLUS)
20270 emit_insn (gen_rtx_SET (scratch, op1));
20275 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20277 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
20278 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
20279 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
20280 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
20281 new_addr = scratch;
20285 /* If this is an indirect address, make sure it is a base register. */
20288 if (!base_reg_operand (addr, GET_MODE (addr)))
20290 emit_insn (gen_rtx_SET (scratch, addr));
20291 new_addr = scratch;
20295 /* If this is an indexed address, make sure the register class can handle
20296 indexed addresses for this mode. */
20298 op0 = XEXP (addr, 0);
20299 op1 = XEXP (addr, 1);
20300 if (!base_reg_operand (op0, Pmode))
20301 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20303 else if (int_reg_operand (op1, Pmode))
20305 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20307 emit_insn (gen_rtx_SET (scratch, addr));
20308 new_addr = scratch;
20312 else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
20314 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
20315 || !quad_address_p (addr, mode, false))
20317 emit_insn (gen_rtx_SET (scratch, addr));
20318 new_addr = scratch;
20322 /* Make sure the register class can handle offset addresses. */
20323 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
20325 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20327 emit_insn (gen_rtx_SET (scratch, addr));
20328 new_addr = scratch;
20333 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20338 op0 = XEXP (addr, 0);
20339 op1 = XEXP (addr, 1);
20340 if (!base_reg_operand (op0, Pmode))
20341 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20343 else if (int_reg_operand (op1, Pmode))
20345 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20347 emit_insn (gen_rtx_SET (scratch, addr));
20348 new_addr = scratch;
20352 /* Quad offsets are restricted and can't handle normal addresses. */
20353 else if (mode_supports_vsx_dform_quad (mode))
20355 emit_insn (gen_rtx_SET (scratch, addr));
20356 new_addr = scratch;
20359 /* Make sure the register class can handle offset addresses. */
20360 else if (legitimate_lo_sum_address_p (mode, addr, false))
20362 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20364 emit_insn (gen_rtx_SET (scratch, addr));
20365 new_addr = scratch;
20370 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20377 rs6000_emit_move (scratch, addr, Pmode);
20378 new_addr = scratch;
20382 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20385 /* Adjust the address if it changed. */
20386 if (addr != new_addr)
20388 mem = replace_equiv_address_nv (mem, new_addr);
20389 if (TARGET_DEBUG_ADDR)
20390 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
20393 /* Now create the move. */
20395 emit_insn (gen_rtx_SET (mem, reg));
20397 emit_insn (gen_rtx_SET (reg, mem));
20402 /* Convert reloads involving 64-bit gprs and misaligned offset
20403 addressing, or multiple 32-bit gprs and offsets that are too large,
20404 to use indirect addressing. */
20407 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
20409 int regno = true_regnum (reg);
20410 enum reg_class rclass;
20412 rtx scratch_or_premodify = scratch;
20414 if (TARGET_DEBUG_ADDR)
20416 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
20417 store_p ? "store" : "load");
20418 fprintf (stderr, "reg:\n");
20420 fprintf (stderr, "mem:\n");
20422 fprintf (stderr, "scratch:\n");
20423 debug_rtx (scratch);
20426 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
20427 gcc_assert (GET_CODE (mem) == MEM);
20428 rclass = REGNO_REG_CLASS (regno);
20429 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
20430 addr = XEXP (mem, 0);
20432 if (GET_CODE (addr) == PRE_MODIFY)
20434 gcc_assert (REG_P (XEXP (addr, 0))
20435 && GET_CODE (XEXP (addr, 1)) == PLUS
20436 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
20437 scratch_or_premodify = XEXP (addr, 0);
20438 if (!HARD_REGISTER_P (scratch_or_premodify))
20439 /* If we have a pseudo here then reload will have arranged
20440 to have it replaced, but only in the original insn.
20441 Use the replacement here too. */
20442 scratch_or_premodify = find_replacement (&XEXP (addr, 0));
20444 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
20445 expressions from the original insn, without unsharing them.
20446 Any RTL that points into the original insn will of course
20447 have register replacements applied. That is why we don't
20448 need to look for replacements under the PLUS. */
20449 addr = XEXP (addr, 1);
20451 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
20453 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
20455 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
20457 /* Now create the move. */
20459 emit_insn (gen_rtx_SET (mem, reg));
20461 emit_insn (gen_rtx_SET (reg, mem));
20466 /* Given an rtx X being reloaded into a reg required to be
20467 in class CLASS, return the class of reg to actually use.
20468 In general this is just CLASS; but on some machines
20469 in some cases it is preferable to use a more restrictive class.
20471 On the RS/6000, we have to return NO_REGS when we want to reload a
20472 floating-point CONST_DOUBLE to force it to be copied to memory.
20474 We also don't want to reload integer values into floating-point
20475 registers if we can at all help it. In fact, this can
20476 cause reload to die, if it tries to generate a reload of CTR
20477 into a FP register and discovers it doesn't have the memory location
20480 ??? Would it be a good idea to have reload do the converse, that is
20481 try to reload floating modes into FP registers if possible?
20484 static enum reg_class
20485 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
20487 machine_mode mode = GET_MODE (x);
20488 bool is_constant = CONSTANT_P (x);
20490 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
20491 reload class for it. */
20492 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20493 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
20496 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
20497 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
20500 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
20501 the reloading of address expressions using PLUS into floating point
20503 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
20507 /* Zero is always allowed in all VSX registers. */
20508 if (x == CONST0_RTX (mode))
20511 /* If this is a vector constant that can be formed with a few Altivec
20512 instructions, we want altivec registers. */
20513 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
20514 return ALTIVEC_REGS;
20516 /* If this is an integer constant that can easily be loaded into
20517 vector registers, allow it. */
20518 if (CONST_INT_P (x))
20520 HOST_WIDE_INT value = INTVAL (x);
20522 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20523 2.06 can generate it in the Altivec registers with
20527 if (TARGET_P8_VECTOR)
20529 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20530 return ALTIVEC_REGS;
20535 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20536 a sign extend in the Altivec registers. */
20537 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
20538 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
20539 return ALTIVEC_REGS;
20542 /* Force constant to memory. */
20546 /* D-form addressing can easily reload the value. */
20547 if (mode_supports_vmx_dform (mode)
20548 || mode_supports_vsx_dform_quad (mode))
20551 /* If this is a scalar floating point value and we don't have D-form
20552 addressing, prefer the traditional floating point registers so that we
20553 can use D-form (register+offset) addressing. */
20554 if (rclass == VSX_REGS
20555 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
20558 /* Prefer the Altivec registers if Altivec is handling the vector
20559 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20561 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
20562 || mode == V1TImode)
20563 return ALTIVEC_REGS;
20568 if (is_constant || GET_CODE (x) == PLUS)
20570 if (reg_class_subset_p (GENERAL_REGS, rclass))
20571 return GENERAL_REGS;
20572 if (reg_class_subset_p (BASE_REGS, rclass))
20577 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
20578 return GENERAL_REGS;
20583 /* Debug version of rs6000_preferred_reload_class. */
20584 static enum reg_class
20585 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
20587 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
20590 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20592 reg_class_names[ret], reg_class_names[rclass],
20593 GET_MODE_NAME (GET_MODE (x)));
20599 /* If we are copying between FP or AltiVec registers and anything else, we need
20600 a memory location. The exception is when we are targeting ppc64 and the
20601 move to/from fpr to gpr instructions are available. Also, under VSX, you
20602 can copy vector registers from the FP register set to the Altivec register
20603 set and vice versa. */
20606 rs6000_secondary_memory_needed (machine_mode mode,
20607 reg_class_t from_class,
20608 reg_class_t to_class)
20610 enum rs6000_reg_type from_type, to_type;
20611 bool altivec_p = ((from_class == ALTIVEC_REGS)
20612 || (to_class == ALTIVEC_REGS));
20614 /* If a simple/direct move is available, we don't need secondary memory */
20615 from_type = reg_class_to_reg_type[(int)from_class];
20616 to_type = reg_class_to_reg_type[(int)to_class];
20618 if (rs6000_secondary_reload_move (to_type, from_type, mode,
20619 (secondary_reload_info *)0, altivec_p))
20622 /* If we have a floating point or vector register class, we need to use
20623 memory to transfer the data. */
20624 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
20630 /* Debug version of rs6000_secondary_memory_needed. */
20632 rs6000_debug_secondary_memory_needed (machine_mode mode,
20633 reg_class_t from_class,
20634 reg_class_t to_class)
20636 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
20639 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20640 "to_class = %s, mode = %s\n",
20641 ret ? "true" : "false",
20642 reg_class_names[from_class],
20643 reg_class_names[to_class],
20644 GET_MODE_NAME (mode));
20649 /* Return the register class of a scratch register needed to copy IN into
20650 or out of a register in RCLASS in MODE. If it can be done directly,
20651 NO_REGS is returned. */
20653 static enum reg_class
20654 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
20659 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
20661 && MACHOPIC_INDIRECT
20665 /* We cannot copy a symbolic operand directly into anything
20666 other than BASE_REGS for TARGET_ELF. So indicate that a
20667 register from BASE_REGS is needed as an intermediate
20670 On Darwin, pic addresses require a load from memory, which
20671 needs a base register. */
20672 if (rclass != BASE_REGS
20673 && (GET_CODE (in) == SYMBOL_REF
20674 || GET_CODE (in) == HIGH
20675 || GET_CODE (in) == LABEL_REF
20676 || GET_CODE (in) == CONST))
20680 if (GET_CODE (in) == REG)
20682 regno = REGNO (in);
20683 if (regno >= FIRST_PSEUDO_REGISTER)
20685 regno = true_regnum (in);
20686 if (regno >= FIRST_PSEUDO_REGISTER)
20690 else if (GET_CODE (in) == SUBREG)
20692 regno = true_regnum (in);
20693 if (regno >= FIRST_PSEUDO_REGISTER)
20699 /* If we have VSX register moves, prefer moving scalar values between
20700 Altivec registers and GPR by going via an FPR (and then via memory)
20701 instead of reloading the secondary memory address for Altivec moves. */
20703 && GET_MODE_SIZE (mode) < 16
20704 && !mode_supports_vmx_dform (mode)
20705 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20706 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20707 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20708 && (regno >= 0 && INT_REGNO_P (regno)))))
20711 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20713 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20714 || (regno >= 0 && INT_REGNO_P (regno)))
20717 /* Constants, memory, and VSX registers can go into VSX registers (both the
20718 traditional floating point and the altivec registers). */
20719 if (rclass == VSX_REGS
20720 && (regno == -1 || VSX_REGNO_P (regno)))
20723 /* Constants, memory, and FP registers can go into FP registers. */
20724 if ((regno == -1 || FP_REGNO_P (regno))
20725 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20726 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20728 /* Memory, and AltiVec registers can go into AltiVec registers. */
20729 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20730 && rclass == ALTIVEC_REGS)
20733 /* We can copy among the CR registers. */
20734 if ((rclass == CR_REGS || rclass == CR0_REGS)
20735 && regno >= 0 && CR_REGNO_P (regno))
20738 /* Otherwise, we need GENERAL_REGS. */
20739 return GENERAL_REGS;
20742 /* Debug version of rs6000_secondary_reload_class. */
20743 static enum reg_class
20744 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20745 machine_mode mode, rtx in)
20747 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20749 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20750 "mode = %s, input rtx:\n",
20751 reg_class_names[ret], reg_class_names[rclass],
20752 GET_MODE_NAME (mode));
20758 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20761 rs6000_can_change_mode_class (machine_mode from,
20763 reg_class_t rclass)
20765 unsigned from_size = GET_MODE_SIZE (from);
20766 unsigned to_size = GET_MODE_SIZE (to);
20768 if (from_size != to_size)
20770 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20772 if (reg_classes_intersect_p (xclass, rclass))
20774 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20775 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20776 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20777 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20779 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20780 single register under VSX because the scalar part of the register
20781 is in the upper 64-bits, and not the lower 64-bits. Types like
20782 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20783 IEEE floating point can't overlap, and neither can small
20786 if (to_float128_vector_p && from_float128_vector_p)
20789 else if (to_float128_vector_p || from_float128_vector_p)
20792 /* TDmode in floating-mode registers must always go into a register
20793 pair with the most significant word in the even-numbered register
20794 to match ISA requirements. In little-endian mode, this does not
20795 match subreg numbering, so we cannot allow subregs. */
20796 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20799 if (from_size < 8 || to_size < 8)
20802 if (from_size == 8 && (8 * to_nregs) != to_size)
20805 if (to_size == 8 && (8 * from_nregs) != from_size)
20814 /* Since the VSX register set includes traditional floating point registers
20815 and altivec registers, just check for the size being different instead of
20816 trying to check whether the modes are vector modes. Otherwise it won't
20817 allow say DF and DI to change classes. For types like TFmode and TDmode
20818 that take 2 64-bit registers, rather than a single 128-bit register, don't
20819 allow subregs of those types to other 128 bit types. */
20820 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20822 unsigned num_regs = (from_size + 15) / 16;
20823 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20824 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20827 return (from_size == 8 || from_size == 16);
20830 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20831 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20837 /* Debug version of rs6000_can_change_mode_class. */
20839 rs6000_debug_can_change_mode_class (machine_mode from,
20841 reg_class_t rclass)
20843 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20846 "rs6000_can_change_mode_class, return %s, from = %s, "
20847 "to = %s, rclass = %s\n",
20848 ret ? "true" : "false",
20849 GET_MODE_NAME (from), GET_MODE_NAME (to),
20850 reg_class_names[rclass]);
20855 /* Return a string to do a move operation of 128 bits of data. */
20858 rs6000_output_move_128bit (rtx operands[])
20860 rtx dest = operands[0];
20861 rtx src = operands[1];
20862 machine_mode mode = GET_MODE (dest);
20865 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20866 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20870 dest_regno = REGNO (dest);
20871 dest_gpr_p = INT_REGNO_P (dest_regno);
20872 dest_fp_p = FP_REGNO_P (dest_regno);
20873 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20874 dest_vsx_p = dest_fp_p | dest_vmx_p;
20879 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20884 src_regno = REGNO (src);
20885 src_gpr_p = INT_REGNO_P (src_regno);
20886 src_fp_p = FP_REGNO_P (src_regno);
20887 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20888 src_vsx_p = src_fp_p | src_vmx_p;
20893 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20896 /* Register moves. */
20897 if (dest_regno >= 0 && src_regno >= 0)
20904 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20905 return (WORDS_BIG_ENDIAN
20906 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20907 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20909 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20913 else if (TARGET_VSX && dest_vsx_p)
20916 return "xxlor %x0,%x1,%x1";
20918 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20919 return (WORDS_BIG_ENDIAN
20920 ? "mtvsrdd %x0,%1,%L1"
20921 : "mtvsrdd %x0,%L1,%1");
20923 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20927 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20928 return "vor %0,%1,%1";
20930 else if (dest_fp_p && src_fp_p)
20935 else if (dest_regno >= 0 && MEM_P (src))
20939 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20945 else if (TARGET_ALTIVEC && dest_vmx_p
20946 && altivec_indexed_or_indirect_operand (src, mode))
20947 return "lvx %0,%y1";
20949 else if (TARGET_VSX && dest_vsx_p)
20951 if (mode_supports_vsx_dform_quad (mode)
20952 && quad_address_p (XEXP (src, 0), mode, true))
20953 return "lxv %x0,%1";
20955 else if (TARGET_P9_VECTOR)
20956 return "lxvx %x0,%y1";
20958 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20959 return "lxvw4x %x0,%y1";
20962 return "lxvd2x %x0,%y1";
20965 else if (TARGET_ALTIVEC && dest_vmx_p)
20966 return "lvx %0,%y1";
20968 else if (dest_fp_p)
20973 else if (src_regno >= 0 && MEM_P (dest))
20977 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20978 return "stq %1,%0";
20983 else if (TARGET_ALTIVEC && src_vmx_p
20984 && altivec_indexed_or_indirect_operand (src, mode))
20985 return "stvx %1,%y0";
20987 else if (TARGET_VSX && src_vsx_p)
20989 if (mode_supports_vsx_dform_quad (mode)
20990 && quad_address_p (XEXP (dest, 0), mode, true))
20991 return "stxv %x1,%0";
20993 else if (TARGET_P9_VECTOR)
20994 return "stxvx %x1,%y0";
20996 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20997 return "stxvw4x %x1,%y0";
21000 return "stxvd2x %x1,%y0";
21003 else if (TARGET_ALTIVEC && src_vmx_p)
21004 return "stvx %1,%y0";
21011 else if (dest_regno >= 0
21012 && (GET_CODE (src) == CONST_INT
21013 || GET_CODE (src) == CONST_WIDE_INT
21014 || GET_CODE (src) == CONST_DOUBLE
21015 || GET_CODE (src) == CONST_VECTOR))
21020 else if ((dest_vmx_p && TARGET_ALTIVEC)
21021 || (dest_vsx_p && TARGET_VSX))
21022 return output_vec_const_move (operands);
21025 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
21028 /* Validate a 128-bit move. */
21030 rs6000_move_128bit_ok_p (rtx operands[])
21032 machine_mode mode = GET_MODE (operands[0]);
21033 return (gpc_reg_operand (operands[0], mode)
21034 || gpc_reg_operand (operands[1], mode));
21037 /* Return true if a 128-bit move needs to be split. */
21039 rs6000_split_128bit_ok_p (rtx operands[])
21041 if (!reload_completed)
21044 if (!gpr_or_gpr_p (operands[0], operands[1]))
21047 if (quad_load_store_p (operands[0], operands[1]))
21054 /* Given a comparison operation, return the bit number in CCR to test. We
21055 know this is a valid comparison.
21057 SCC_P is 1 if this is for an scc. That means that %D will have been
21058 used instead of %C, so the bits will be in different places.
21060 Return -1 if OP isn't a valid comparison for some reason. */
21063 ccr_bit (rtx op, int scc_p)
21065 enum rtx_code code = GET_CODE (op);
21066 machine_mode cc_mode;
21071 if (!COMPARISON_P (op))
21074 reg = XEXP (op, 0);
21076 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
21078 cc_mode = GET_MODE (reg);
21079 cc_regnum = REGNO (reg);
21080 base_bit = 4 * (cc_regnum - CR0_REGNO);
21082 validate_condition_mode (code, cc_mode);
21084 /* When generating a sCOND operation, only positive conditions are
21087 || code == EQ || code == GT || code == LT || code == UNORDERED
21088 || code == GTU || code == LTU);
21093 return scc_p ? base_bit + 3 : base_bit + 2;
21095 return base_bit + 2;
21096 case GT: case GTU: case UNLE:
21097 return base_bit + 1;
21098 case LT: case LTU: case UNGE:
21100 case ORDERED: case UNORDERED:
21101 return base_bit + 3;
21104 /* If scc, we will have done a cror to put the bit in the
21105 unordered position. So test that bit. For integer, this is ! LT
21106 unless this is an scc insn. */
21107 return scc_p ? base_bit + 3 : base_bit;
21110 return scc_p ? base_bit + 3 : base_bit + 1;
21113 gcc_unreachable ();
21117 /* Return the GOT register. */
21120 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
21122 /* The second flow pass currently (June 1999) can't update
21123 regs_ever_live without disturbing other parts of the compiler, so
21124 update it here to make the prolog/epilogue code happy. */
21125 if (!can_create_pseudo_p ()
21126 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
21127 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
21129 crtl->uses_pic_offset_table = 1;
21131 return pic_offset_table_rtx;
21134 static rs6000_stack_t stack_info;
21136 /* Function to init struct machine_function.
21137 This will be called, via a pointer variable,
21138 from push_function_context. */
21140 static struct machine_function *
21141 rs6000_init_machine_status (void)
21143 stack_info.reload_completed = 0;
21144 return ggc_cleared_alloc<machine_function> ();
21147 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
21149 /* Write out a function code label. */
21152 rs6000_output_function_entry (FILE *file, const char *fname)
21154 if (fname[0] != '.')
21156 switch (DEFAULT_ABI)
21159 gcc_unreachable ();
21165 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
21175 RS6000_OUTPUT_BASENAME (file, fname);
21178 /* Print an operand. Recognize special options, documented below. */
21181 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
21182 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
21184 #define SMALL_DATA_RELOC "sda21"
21185 #define SMALL_DATA_REG 0
21189 print_operand (FILE *file, rtx x, int code)
21192 unsigned HOST_WIDE_INT uval;
21196 /* %a is output_address. */
21198 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
21202 /* Like 'J' but get to the GT bit only. */
21203 gcc_assert (REG_P (x));
21205 /* Bit 1 is GT bit. */
21206 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
21208 /* Add one for shift count in rlinm for scc. */
21209 fprintf (file, "%d", i + 1);
21213 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
21216 output_operand_lossage ("invalid %%e value");
21221 if ((uval & 0xffff) == 0 && uval != 0)
21226 /* X is a CR register. Print the number of the EQ bit of the CR */
21227 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21228 output_operand_lossage ("invalid %%E value");
21230 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
21234 /* X is a CR register. Print the shift count needed to move it
21235 to the high-order four bits. */
21236 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21237 output_operand_lossage ("invalid %%f value");
21239 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
21243 /* Similar, but print the count for the rotate in the opposite
21245 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21246 output_operand_lossage ("invalid %%F value");
21248 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
21252 /* X is a constant integer. If it is negative, print "m",
21253 otherwise print "z". This is to make an aze or ame insn. */
21254 if (GET_CODE (x) != CONST_INT)
21255 output_operand_lossage ("invalid %%G value");
21256 else if (INTVAL (x) >= 0)
21263 /* If constant, output low-order five bits. Otherwise, write
21266 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
21268 print_operand (file, x, 0);
21272 /* If constant, output low-order six bits. Otherwise, write
21275 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
21277 print_operand (file, x, 0);
21281 /* Print `i' if this is a constant, else nothing. */
21287 /* Write the bit number in CCR for jump. */
21288 i = ccr_bit (x, 0);
21290 output_operand_lossage ("invalid %%j code");
21292 fprintf (file, "%d", i);
21296 /* Similar, but add one for shift count in rlinm for scc and pass
21297 scc flag to `ccr_bit'. */
21298 i = ccr_bit (x, 1);
21300 output_operand_lossage ("invalid %%J code");
21302 /* If we want bit 31, write a shift count of zero, not 32. */
21303 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21307 /* X must be a constant. Write the 1's complement of the
21310 output_operand_lossage ("invalid %%k value");
21312 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
21316 /* X must be a symbolic constant on ELF. Write an
21317 expression suitable for an 'addi' that adds in the low 16
21318 bits of the MEM. */
21319 if (GET_CODE (x) == CONST)
21321 if (GET_CODE (XEXP (x, 0)) != PLUS
21322 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
21323 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
21324 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
21325 output_operand_lossage ("invalid %%K value");
21327 print_operand_address (file, x);
21328 fputs ("@l", file);
21331 /* %l is output_asm_label. */
21334 /* Write second word of DImode or DFmode reference. Works on register
21335 or non-indexed memory only. */
21337 fputs (reg_names[REGNO (x) + 1], file);
21338 else if (MEM_P (x))
21340 machine_mode mode = GET_MODE (x);
21341 /* Handle possible auto-increment. Since it is pre-increment and
21342 we have already done it, we can just use an offset of word. */
21343 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21344 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21345 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21347 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21348 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21351 output_address (mode, XEXP (adjust_address_nv (x, SImode,
21355 if (small_data_operand (x, GET_MODE (x)))
21356 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21357 reg_names[SMALL_DATA_REG]);
21362 /* Write the number of elements in the vector times 4. */
21363 if (GET_CODE (x) != PARALLEL)
21364 output_operand_lossage ("invalid %%N value");
21366 fprintf (file, "%d", XVECLEN (x, 0) * 4);
21370 /* Similar, but subtract 1 first. */
21371 if (GET_CODE (x) != PARALLEL)
21372 output_operand_lossage ("invalid %%O value");
21374 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
21378 /* X is a CONST_INT that is a power of two. Output the logarithm. */
21381 || (i = exact_log2 (INTVAL (x))) < 0)
21382 output_operand_lossage ("invalid %%p value");
21384 fprintf (file, "%d", i);
21388 /* The operand must be an indirect memory reference. The result
21389 is the register name. */
21390 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
21391 || REGNO (XEXP (x, 0)) >= 32)
21392 output_operand_lossage ("invalid %%P value");
21394 fputs (reg_names[REGNO (XEXP (x, 0))], file);
21398 /* This outputs the logical code corresponding to a boolean
21399 expression. The expression may have one or both operands
21400 negated (if one, only the first one). For condition register
21401 logical operations, it will also treat the negated
21402 CR codes as NOTs, but not handle NOTs of them. */
21404 const char *const *t = 0;
21406 enum rtx_code code = GET_CODE (x);
21407 static const char * const tbl[3][3] = {
21408 { "and", "andc", "nor" },
21409 { "or", "orc", "nand" },
21410 { "xor", "eqv", "xor" } };
21414 else if (code == IOR)
21416 else if (code == XOR)
21419 output_operand_lossage ("invalid %%q value");
21421 if (GET_CODE (XEXP (x, 0)) != NOT)
21425 if (GET_CODE (XEXP (x, 1)) == NOT)
21436 if (! TARGET_MFCRF)
21442 /* X is a CR register. Print the mask for `mtcrf'. */
21443 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21444 output_operand_lossage ("invalid %%R value");
21446 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
21450 /* Low 5 bits of 32 - value */
21452 output_operand_lossage ("invalid %%s value");
21454 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
21458 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
21459 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
21461 /* Bit 3 is OV bit. */
21462 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
21464 /* If we want bit 31, write a shift count of zero, not 32. */
21465 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21469 /* Print the symbolic name of a branch target register. */
21470 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
21471 && REGNO (x) != CTR_REGNO))
21472 output_operand_lossage ("invalid %%T value");
21473 else if (REGNO (x) == LR_REGNO)
21474 fputs ("lr", file);
21476 fputs ("ctr", file);
21480 /* High-order or low-order 16 bits of constant, whichever is non-zero,
21481 for use in unsigned operand. */
21484 output_operand_lossage ("invalid %%u value");
21489 if ((uval & 0xffff) == 0)
21492 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
21496 /* High-order 16 bits of constant for use in signed operand. */
21498 output_operand_lossage ("invalid %%v value");
21500 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
21501 (INTVAL (x) >> 16) & 0xffff);
21505 /* Print `u' if this has an auto-increment or auto-decrement. */
21507 && (GET_CODE (XEXP (x, 0)) == PRE_INC
21508 || GET_CODE (XEXP (x, 0)) == PRE_DEC
21509 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
21514 /* Print the trap code for this operand. */
21515 switch (GET_CODE (x))
21518 fputs ("eq", file); /* 4 */
21521 fputs ("ne", file); /* 24 */
21524 fputs ("lt", file); /* 16 */
21527 fputs ("le", file); /* 20 */
21530 fputs ("gt", file); /* 8 */
21533 fputs ("ge", file); /* 12 */
21536 fputs ("llt", file); /* 2 */
21539 fputs ("lle", file); /* 6 */
21542 fputs ("lgt", file); /* 1 */
21545 fputs ("lge", file); /* 5 */
21548 gcc_unreachable ();
21553 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21556 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
21557 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
21559 print_operand (file, x, 0);
21563 /* X is a FPR or Altivec register used in a VSX context. */
21564 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
21565 output_operand_lossage ("invalid %%x value");
21568 int reg = REGNO (x);
21569 int vsx_reg = (FP_REGNO_P (reg)
21571 : reg - FIRST_ALTIVEC_REGNO + 32);
21573 #ifdef TARGET_REGNAMES
21574 if (TARGET_REGNAMES)
21575 fprintf (file, "%%vs%d", vsx_reg);
21578 fprintf (file, "%d", vsx_reg);
21584 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
21585 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
21586 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
21591 /* Like 'L', for third word of TImode/PTImode */
21593 fputs (reg_names[REGNO (x) + 2], file);
21594 else if (MEM_P (x))
21596 machine_mode mode = GET_MODE (x);
21597 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21598 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21599 output_address (mode, plus_constant (Pmode,
21600 XEXP (XEXP (x, 0), 0), 8));
21601 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21602 output_address (mode, plus_constant (Pmode,
21603 XEXP (XEXP (x, 0), 0), 8));
21605 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
21606 if (small_data_operand (x, GET_MODE (x)))
21607 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21608 reg_names[SMALL_DATA_REG]);
21613 /* X is a SYMBOL_REF. Write out the name preceded by a
21614 period and without any trailing data in brackets. Used for function
21615 names. If we are configured for System V (or the embedded ABI) on
21616 the PowerPC, do not emit the period, since those systems do not use
21617 TOCs and the like. */
21618 gcc_assert (GET_CODE (x) == SYMBOL_REF);
21620 /* For macho, check to see if we need a stub. */
21623 const char *name = XSTR (x, 0);
21625 if (darwin_emit_branch_islands
21626 && MACHOPIC_INDIRECT
21627 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
21628 name = machopic_indirection_name (x, /*stub_p=*/true);
21630 assemble_name (file, name);
21632 else if (!DOT_SYMBOLS)
21633 assemble_name (file, XSTR (x, 0));
21635 rs6000_output_function_entry (file, XSTR (x, 0));
21639 /* Like 'L', for last word of TImode/PTImode. */
21641 fputs (reg_names[REGNO (x) + 3], file);
21642 else if (MEM_P (x))
21644 machine_mode mode = GET_MODE (x);
21645 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21646 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21647 output_address (mode, plus_constant (Pmode,
21648 XEXP (XEXP (x, 0), 0), 12));
21649 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21650 output_address (mode, plus_constant (Pmode,
21651 XEXP (XEXP (x, 0), 0), 12));
21653 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
21654 if (small_data_operand (x, GET_MODE (x)))
21655 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21656 reg_names[SMALL_DATA_REG]);
21660 /* Print AltiVec memory operand. */
21665 gcc_assert (MEM_P (x));
21669 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
21670 && GET_CODE (tmp) == AND
21671 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
21672 && INTVAL (XEXP (tmp, 1)) == -16)
21673 tmp = XEXP (tmp, 0);
21674 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
21675 && GET_CODE (tmp) == PRE_MODIFY)
21676 tmp = XEXP (tmp, 1);
21678 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21681 if (GET_CODE (tmp) != PLUS
21682 || !REG_P (XEXP (tmp, 0))
21683 || !REG_P (XEXP (tmp, 1)))
21685 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21689 if (REGNO (XEXP (tmp, 0)) == 0)
21690 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21691 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21693 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21694 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21701 fprintf (file, "%s", reg_names[REGNO (x)]);
21702 else if (MEM_P (x))
21704 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21705 know the width from the mode. */
21706 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21707 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21708 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21709 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21710 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21711 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21712 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21713 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21715 output_address (GET_MODE (x), XEXP (x, 0));
21719 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21720 /* This hack along with a corresponding hack in
21721 rs6000_output_addr_const_extra arranges to output addends
21722 where the assembler expects to find them. eg.
21723 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21724 without this hack would be output as "x@toc+4". We
21726 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21728 output_addr_const (file, x);
21733 if (const char *name = get_some_local_dynamic_name ())
21734 assemble_name (file, name);
21736 output_operand_lossage ("'%%&' used without any "
21737 "local dynamic TLS references");
21741 output_operand_lossage ("invalid %%xn code");
21745 /* Print the address of an operand. */
21748 print_operand_address (FILE *file, rtx x)
21751 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21752 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21753 || GET_CODE (x) == LABEL_REF)
21755 output_addr_const (file, x);
21756 if (small_data_operand (x, GET_MODE (x)))
21757 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21758 reg_names[SMALL_DATA_REG]);
21760 gcc_assert (!TARGET_TOC);
21762 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21763 && REG_P (XEXP (x, 1)))
21765 if (REGNO (XEXP (x, 0)) == 0)
21766 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21767 reg_names[ REGNO (XEXP (x, 0)) ]);
21769 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21770 reg_names[ REGNO (XEXP (x, 1)) ]);
21772 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21773 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21774 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21775 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21777 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21778 && CONSTANT_P (XEXP (x, 1)))
21780 fprintf (file, "lo16(");
21781 output_addr_const (file, XEXP (x, 1));
21782 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21786 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21787 && CONSTANT_P (XEXP (x, 1)))
21789 output_addr_const (file, XEXP (x, 1));
21790 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21793 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21795 /* This hack along with a corresponding hack in
21796 rs6000_output_addr_const_extra arranges to output addends
21797 where the assembler expects to find them. eg.
21799 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21800 without this hack would be output as "x@toc+8@l(9)". We
21801 want "x+8@toc@l(9)". */
21802 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21803 if (GET_CODE (x) == LO_SUM)
21804 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21806 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21809 gcc_unreachable ();
21812 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21815 rs6000_output_addr_const_extra (FILE *file, rtx x)
21817 if (GET_CODE (x) == UNSPEC)
21818 switch (XINT (x, 1))
21820 case UNSPEC_TOCREL:
21821 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21822 && REG_P (XVECEXP (x, 0, 1))
21823 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21824 output_addr_const (file, XVECEXP (x, 0, 0));
21825 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21827 if (INTVAL (tocrel_offset_oac) >= 0)
21828 fprintf (file, "+");
21829 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21831 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21834 assemble_name (file, toc_label_name);
21837 else if (TARGET_ELF)
21838 fputs ("@toc", file);
21842 case UNSPEC_MACHOPIC_OFFSET:
21843 output_addr_const (file, XVECEXP (x, 0, 0));
21845 machopic_output_function_base_name (file);
21852 /* Target hook for assembling integer objects. The PowerPC version has
21853 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21854 is defined. It also needs to handle DI-mode objects on 64-bit
21858 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21860 #ifdef RELOCATABLE_NEEDS_FIXUP
21861 /* Special handling for SI values. */
21862 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21864 static int recurse = 0;
21866 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21867 the .fixup section. Since the TOC section is already relocated, we
21868 don't need to mark it here. We used to skip the text section, but it
21869 should never be valid for relocated addresses to be placed in the text
21871 if (DEFAULT_ABI == ABI_V4
21872 && (TARGET_RELOCATABLE || flag_pic > 1)
21873 && in_section != toc_section
21875 && !CONST_SCALAR_INT_P (x)
21881 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21883 ASM_OUTPUT_LABEL (asm_out_file, buf);
21884 fprintf (asm_out_file, "\t.long\t(");
21885 output_addr_const (asm_out_file, x);
21886 fprintf (asm_out_file, ")@fixup\n");
21887 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21888 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21889 fprintf (asm_out_file, "\t.long\t");
21890 assemble_name (asm_out_file, buf);
21891 fprintf (asm_out_file, "\n\t.previous\n");
21895 /* Remove initial .'s to turn a -mcall-aixdesc function
21896 address into the address of the descriptor, not the function
21898 else if (GET_CODE (x) == SYMBOL_REF
21899 && XSTR (x, 0)[0] == '.'
21900 && DEFAULT_ABI == ABI_AIX)
21902 const char *name = XSTR (x, 0);
21903 while (*name == '.')
21906 fprintf (asm_out_file, "\t.long\t%s\n", name);
21910 #endif /* RELOCATABLE_NEEDS_FIXUP */
21911 return default_assemble_integer (x, size, aligned_p);
21914 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21915 /* Emit an assembler directive to set symbol visibility for DECL to
21916 VISIBILITY_TYPE. */
21919 rs6000_assemble_visibility (tree decl, int vis)
21924 /* Functions need to have their entry point symbol visibility set as
21925 well as their descriptor symbol visibility. */
21926 if (DEFAULT_ABI == ABI_AIX
21928 && TREE_CODE (decl) == FUNCTION_DECL)
21930 static const char * const visibility_types[] = {
21931 NULL, "protected", "hidden", "internal"
21934 const char *name, *type;
21936 name = ((* targetm.strip_name_encoding)
21937 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21938 type = visibility_types[vis];
21940 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21941 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21944 default_assemble_visibility (decl, vis);
21949 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21951 /* Reversal of FP compares takes care -- an ordered compare
21952 becomes an unordered compare and vice versa. */
21953 if (mode == CCFPmode
21954 && (!flag_finite_math_only
21955 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21956 || code == UNEQ || code == LTGT))
21957 return reverse_condition_maybe_unordered (code);
21959 return reverse_condition (code);
21962 /* Generate a compare for CODE. Return a brand-new rtx that
21963 represents the result of the compare. */
21966 rs6000_generate_compare (rtx cmp, machine_mode mode)
21968 machine_mode comp_mode;
21969 rtx compare_result;
21970 enum rtx_code code = GET_CODE (cmp);
21971 rtx op0 = XEXP (cmp, 0);
21972 rtx op1 = XEXP (cmp, 1);
21974 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21975 comp_mode = CCmode;
21976 else if (FLOAT_MODE_P (mode))
21977 comp_mode = CCFPmode;
21978 else if (code == GTU || code == LTU
21979 || code == GEU || code == LEU)
21980 comp_mode = CCUNSmode;
21981 else if ((code == EQ || code == NE)
21982 && unsigned_reg_p (op0)
21983 && (unsigned_reg_p (op1)
21984 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21985 /* These are unsigned values, perhaps there will be a later
21986 ordering compare that can be shared with this one. */
21987 comp_mode = CCUNSmode;
21989 comp_mode = CCmode;
21991 /* If we have an unsigned compare, make sure we don't have a signed value as
21993 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
21994 && INTVAL (op1) < 0)
21996 op0 = copy_rtx_if_shared (op0);
21997 op1 = force_reg (GET_MODE (op0), op1);
21998 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
22001 /* First, the compare. */
22002 compare_result = gen_reg_rtx (comp_mode);
22004 /* IEEE 128-bit support in VSX registers when we do not have hardware
22006 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22008 rtx libfunc = NULL_RTX;
22009 bool check_nan = false;
22016 libfunc = optab_libfunc (eq_optab, mode);
22021 libfunc = optab_libfunc (ge_optab, mode);
22026 libfunc = optab_libfunc (le_optab, mode);
22031 libfunc = optab_libfunc (unord_optab, mode);
22032 code = (code == UNORDERED) ? NE : EQ;
22038 libfunc = optab_libfunc (ge_optab, mode);
22039 code = (code == UNGE) ? GE : GT;
22045 libfunc = optab_libfunc (le_optab, mode);
22046 code = (code == UNLE) ? LE : LT;
22052 libfunc = optab_libfunc (eq_optab, mode);
22053 code = (code = UNEQ) ? EQ : NE;
22057 gcc_unreachable ();
22060 gcc_assert (libfunc);
22063 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22064 SImode, op0, mode, op1, mode);
22066 /* The library signals an exception for signalling NaNs, so we need to
22067 handle isgreater, etc. by first checking isordered. */
22070 rtx ne_rtx, normal_dest, unord_dest;
22071 rtx unord_func = optab_libfunc (unord_optab, mode);
22072 rtx join_label = gen_label_rtx ();
22073 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
22074 rtx unord_cmp = gen_reg_rtx (comp_mode);
22077 /* Test for either value being a NaN. */
22078 gcc_assert (unord_func);
22079 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
22080 SImode, op0, mode, op1, mode);
22082 /* Set value (0) if either value is a NaN, and jump to the join
22084 dest = gen_reg_rtx (SImode);
22085 emit_move_insn (dest, const1_rtx);
22086 emit_insn (gen_rtx_SET (unord_cmp,
22087 gen_rtx_COMPARE (comp_mode, unord_dest,
22090 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
22091 emit_jump_insn (gen_rtx_SET (pc_rtx,
22092 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
22096 /* Do the normal comparison, knowing that the values are not
22098 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22099 SImode, op0, mode, op1, mode);
22101 emit_insn (gen_cstoresi4 (dest,
22102 gen_rtx_fmt_ee (code, SImode, normal_dest,
22104 normal_dest, const0_rtx));
22106 /* Join NaN and non-Nan paths. Compare dest against 0. */
22107 emit_label (join_label);
22111 emit_insn (gen_rtx_SET (compare_result,
22112 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
22117 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
22118 CLOBBERs to match cmptf_internal2 pattern. */
22119 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
22120 && FLOAT128_IBM_P (GET_MODE (op0))
22121 && TARGET_HARD_FLOAT)
22122 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22124 gen_rtx_SET (compare_result,
22125 gen_rtx_COMPARE (comp_mode, op0, op1)),
22126 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22127 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22128 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22129 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22130 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22131 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22132 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22133 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22134 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
22135 else if (GET_CODE (op1) == UNSPEC
22136 && XINT (op1, 1) == UNSPEC_SP_TEST)
22138 rtx op1b = XVECEXP (op1, 0, 0);
22139 comp_mode = CCEQmode;
22140 compare_result = gen_reg_rtx (CCEQmode);
22142 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
22144 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
22147 emit_insn (gen_rtx_SET (compare_result,
22148 gen_rtx_COMPARE (comp_mode, op0, op1)));
22151 /* Some kinds of FP comparisons need an OR operation;
22152 under flag_finite_math_only we don't bother. */
22153 if (FLOAT_MODE_P (mode)
22154 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
22155 && !flag_finite_math_only
22156 && (code == LE || code == GE
22157 || code == UNEQ || code == LTGT
22158 || code == UNGT || code == UNLT))
22160 enum rtx_code or1, or2;
22161 rtx or1_rtx, or2_rtx, compare2_rtx;
22162 rtx or_result = gen_reg_rtx (CCEQmode);
22166 case LE: or1 = LT; or2 = EQ; break;
22167 case GE: or1 = GT; or2 = EQ; break;
22168 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
22169 case LTGT: or1 = LT; or2 = GT; break;
22170 case UNGT: or1 = UNORDERED; or2 = GT; break;
22171 case UNLT: or1 = UNORDERED; or2 = LT; break;
22172 default: gcc_unreachable ();
22174 validate_condition_mode (or1, comp_mode);
22175 validate_condition_mode (or2, comp_mode);
22176 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
22177 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
22178 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
22179 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
22181 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
22183 compare_result = or_result;
22187 validate_condition_mode (code, GET_MODE (compare_result));
22189 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
22193 /* Return the diagnostic message string if the binary operation OP is
22194 not permitted on TYPE1 and TYPE2, NULL otherwise. */
22197 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
22201 machine_mode mode1 = TYPE_MODE (type1);
22202 machine_mode mode2 = TYPE_MODE (type2);
22204 /* For complex modes, use the inner type. */
22205 if (COMPLEX_MODE_P (mode1))
22206 mode1 = GET_MODE_INNER (mode1);
22208 if (COMPLEX_MODE_P (mode2))
22209 mode2 = GET_MODE_INNER (mode2);
22211 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
22212 double to intermix unless -mfloat128-convert. */
22213 if (mode1 == mode2)
22216 if (!TARGET_FLOAT128_CVT)
22218 if ((mode1 == KFmode && mode2 == IFmode)
22219 || (mode1 == IFmode && mode2 == KFmode))
22220 return N_("__float128 and __ibm128 cannot be used in the same "
22223 if (TARGET_IEEEQUAD
22224 && ((mode1 == IFmode && mode2 == TFmode)
22225 || (mode1 == TFmode && mode2 == IFmode)))
22226 return N_("__ibm128 and long double cannot be used in the same "
22229 if (!TARGET_IEEEQUAD
22230 && ((mode1 == KFmode && mode2 == TFmode)
22231 || (mode1 == TFmode && mode2 == KFmode)))
22232 return N_("__float128 and long double cannot be used in the same "
22240 /* Expand floating point conversion to/from __float128 and __ibm128. */
22243 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
22245 machine_mode dest_mode = GET_MODE (dest);
22246 machine_mode src_mode = GET_MODE (src);
22247 convert_optab cvt = unknown_optab;
22248 bool do_move = false;
22249 rtx libfunc = NULL_RTX;
22251 typedef rtx (*rtx_2func_t) (rtx, rtx);
22252 rtx_2func_t hw_convert = (rtx_2func_t)0;
22256 rtx_2func_t from_df;
22257 rtx_2func_t from_sf;
22258 rtx_2func_t from_si_sign;
22259 rtx_2func_t from_si_uns;
22260 rtx_2func_t from_di_sign;
22261 rtx_2func_t from_di_uns;
22264 rtx_2func_t to_si_sign;
22265 rtx_2func_t to_si_uns;
22266 rtx_2func_t to_di_sign;
22267 rtx_2func_t to_di_uns;
22268 } hw_conversions[2] = {
22269 /* convertions to/from KFmode */
22271 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
22272 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
22273 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
22274 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
22275 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
22276 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
22277 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
22278 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
22279 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
22280 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
22281 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
22282 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
22285 /* convertions to/from TFmode */
22287 gen_extenddftf2_hw, /* TFmode <- DFmode. */
22288 gen_extendsftf2_hw, /* TFmode <- SFmode. */
22289 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
22290 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
22291 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
22292 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
22293 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
22294 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
22295 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
22296 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
22297 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
22298 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
22302 if (dest_mode == src_mode)
22303 gcc_unreachable ();
22305 /* Eliminate memory operations. */
22307 src = force_reg (src_mode, src);
22311 rtx tmp = gen_reg_rtx (dest_mode);
22312 rs6000_expand_float128_convert (tmp, src, unsigned_p);
22313 rs6000_emit_move (dest, tmp, dest_mode);
22317 /* Convert to IEEE 128-bit floating point. */
22318 if (FLOAT128_IEEE_P (dest_mode))
22320 if (dest_mode == KFmode)
22322 else if (dest_mode == TFmode)
22325 gcc_unreachable ();
22331 hw_convert = hw_conversions[kf_or_tf].from_df;
22336 hw_convert = hw_conversions[kf_or_tf].from_sf;
22342 if (FLOAT128_IBM_P (src_mode))
22351 cvt = ufloat_optab;
22352 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
22356 cvt = sfloat_optab;
22357 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
22364 cvt = ufloat_optab;
22365 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
22369 cvt = sfloat_optab;
22370 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
22375 gcc_unreachable ();
22379 /* Convert from IEEE 128-bit floating point. */
22380 else if (FLOAT128_IEEE_P (src_mode))
22382 if (src_mode == KFmode)
22384 else if (src_mode == TFmode)
22387 gcc_unreachable ();
22393 hw_convert = hw_conversions[kf_or_tf].to_df;
22398 hw_convert = hw_conversions[kf_or_tf].to_sf;
22404 if (FLOAT128_IBM_P (dest_mode))
22414 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22419 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22427 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22432 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22437 gcc_unreachable ();
22441 /* Both IBM format. */
22442 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22446 gcc_unreachable ();
22448 /* Handle conversion between TFmode/KFmode. */
22450 emit_move_insn (dest, gen_lowpart (dest_mode, src));
22452 /* Handle conversion if we have hardware support. */
22453 else if (TARGET_FLOAT128_HW && hw_convert)
22454 emit_insn ((hw_convert) (dest, src));
22456 /* Call an external function to do the conversion. */
22457 else if (cvt != unknown_optab)
22459 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22460 gcc_assert (libfunc != NULL_RTX);
22462 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22465 gcc_assert (dest2 != NULL_RTX);
22466 if (!rtx_equal_p (dest, dest2))
22467 emit_move_insn (dest, dest2);
22471 gcc_unreachable ();
22477 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22478 can be used as that dest register. Return the dest register. */
22481 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22483 if (op2 == const0_rtx)
22486 if (GET_CODE (scratch) == SCRATCH)
22487 scratch = gen_reg_rtx (mode);
22489 if (logical_operand (op2, mode))
22490 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22492 emit_insn (gen_rtx_SET (scratch,
22493 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22499 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22502 machine_mode op_mode;
22503 enum rtx_code cond_code;
22504 rtx result = operands[0];
22506 condition_rtx = rs6000_generate_compare (operands[1], mode);
22507 cond_code = GET_CODE (condition_rtx);
22509 if (cond_code == NE
22510 || cond_code == GE || cond_code == LE
22511 || cond_code == GEU || cond_code == LEU
22512 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22514 rtx not_result = gen_reg_rtx (CCEQmode);
22515 rtx not_op, rev_cond_rtx;
22516 machine_mode cc_mode;
22518 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22520 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22521 SImode, XEXP (condition_rtx, 0), const0_rtx);
22522 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22523 emit_insn (gen_rtx_SET (not_result, not_op));
22524 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22527 op_mode = GET_MODE (XEXP (operands[1], 0));
22528 if (op_mode == VOIDmode)
22529 op_mode = GET_MODE (XEXP (operands[1], 1));
22531 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22533 PUT_MODE (condition_rtx, DImode);
22534 convert_move (result, condition_rtx, 0);
22538 PUT_MODE (condition_rtx, SImode);
22539 emit_insn (gen_rtx_SET (result, condition_rtx));
22543 /* Emit a branch of kind CODE to location LOC. */
22546 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22548 rtx condition_rtx, loc_ref;
22550 condition_rtx = rs6000_generate_compare (operands[0], mode);
22551 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22552 emit_jump_insn (gen_rtx_SET (pc_rtx,
22553 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22554 loc_ref, pc_rtx)));
22557 /* Return the string to output a conditional branch to LABEL, which is
22558 the operand template of the label, or NULL if the branch is really a
22559 conditional return.
22561 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22562 condition code register and its mode specifies what kind of
22563 comparison we made.
22565 REVERSED is nonzero if we should reverse the sense of the comparison.
22567 INSN is the insn. */
22570 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22572 static char string[64];
22573 enum rtx_code code = GET_CODE (op);
22574 rtx cc_reg = XEXP (op, 0);
22575 machine_mode mode = GET_MODE (cc_reg);
22576 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22577 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22578 int really_reversed = reversed ^ need_longbranch;
22584 validate_condition_mode (code, mode);
22586 /* Work out which way this really branches. We could use
22587 reverse_condition_maybe_unordered here always but this
22588 makes the resulting assembler clearer. */
22589 if (really_reversed)
22591 /* Reversal of FP compares takes care -- an ordered compare
22592 becomes an unordered compare and vice versa. */
22593 if (mode == CCFPmode)
22594 code = reverse_condition_maybe_unordered (code);
22596 code = reverse_condition (code);
22601 /* Not all of these are actually distinct opcodes, but
22602 we distinguish them for clarity of the resulting assembler. */
22603 case NE: case LTGT:
22604 ccode = "ne"; break;
22605 case EQ: case UNEQ:
22606 ccode = "eq"; break;
22608 ccode = "ge"; break;
22609 case GT: case GTU: case UNGT:
22610 ccode = "gt"; break;
22612 ccode = "le"; break;
22613 case LT: case LTU: case UNLT:
22614 ccode = "lt"; break;
22615 case UNORDERED: ccode = "un"; break;
22616 case ORDERED: ccode = "nu"; break;
22617 case UNGE: ccode = "nl"; break;
22618 case UNLE: ccode = "ng"; break;
22620 gcc_unreachable ();
22623 /* Maybe we have a guess as to how likely the branch is. */
22625 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22626 if (note != NULL_RTX)
22628 /* PROB is the difference from 50%. */
22629 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22630 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22632 /* Only hint for highly probable/improbable branches on newer cpus when
22633 we have real profile data, as static prediction overrides processor
22634 dynamic prediction. For older cpus we may as well always hint, but
22635 assume not taken for branches that are very close to 50% as a
22636 mispredicted taken branch is more expensive than a
22637 mispredicted not-taken branch. */
22638 if (rs6000_always_hint
22639 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22640 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22641 && br_prob_note_reliable_p (note)))
22643 if (abs (prob) > REG_BR_PROB_BASE / 20
22644 && ((prob > 0) ^ need_longbranch))
22652 s += sprintf (s, "b%slr%s ", ccode, pred);
22654 s += sprintf (s, "b%s%s ", ccode, pred);
22656 /* We need to escape any '%' characters in the reg_names string.
22657 Assume they'd only be the first character.... */
22658 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22660 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22664 /* If the branch distance was too far, we may have to use an
22665 unconditional branch to go the distance. */
22666 if (need_longbranch)
22667 s += sprintf (s, ",$+8\n\tb %s", label);
22669 s += sprintf (s, ",%s", label);
22675 /* Return insn for VSX or Altivec comparisons. */
22678 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22681 machine_mode mode = GET_MODE (op0);
22689 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22700 mask = gen_reg_rtx (mode);
22701 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22708 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22709 DMODE is expected destination mode. This is a recursive function. */
22712 rs6000_emit_vector_compare (enum rtx_code rcode,
22714 machine_mode dmode)
22717 bool swap_operands = false;
22718 bool try_again = false;
22720 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22721 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22723 /* See if the comparison works as is. */
22724 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22732 swap_operands = true;
22737 swap_operands = true;
22745 /* Invert condition and try again.
22746 e.g., A != B becomes ~(A==B). */
22748 enum rtx_code rev_code;
22749 enum insn_code nor_code;
22752 rev_code = reverse_condition_maybe_unordered (rcode);
22753 if (rev_code == UNKNOWN)
22756 nor_code = optab_handler (one_cmpl_optab, dmode);
22757 if (nor_code == CODE_FOR_nothing)
22760 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22764 mask = gen_reg_rtx (dmode);
22765 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22773 /* Try GT/GTU/LT/LTU OR EQ */
22776 enum insn_code ior_code;
22777 enum rtx_code new_code;
22798 gcc_unreachable ();
22801 ior_code = optab_handler (ior_optab, dmode);
22802 if (ior_code == CODE_FOR_nothing)
22805 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22809 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22813 mask = gen_reg_rtx (dmode);
22814 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22825 std::swap (op0, op1);
22827 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22832 /* You only get two chances. */
22836 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22837 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22838 operands for the relation operation COND. */
22841 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22842 rtx cond, rtx cc_op0, rtx cc_op1)
22844 machine_mode dest_mode = GET_MODE (dest);
22845 machine_mode mask_mode = GET_MODE (cc_op0);
22846 enum rtx_code rcode = GET_CODE (cond);
22847 machine_mode cc_mode = CCmode;
22850 bool invert_move = false;
22852 if (VECTOR_UNIT_NONE_P (dest_mode))
22855 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22856 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22860 /* Swap operands if we can, and fall back to doing the operation as
22861 specified, and doing a NOR to invert the test. */
22867 /* Invert condition and try again.
22868 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22869 invert_move = true;
22870 rcode = reverse_condition_maybe_unordered (rcode);
22871 if (rcode == UNKNOWN)
22877 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22879 /* Invert condition to avoid compound test. */
22880 invert_move = true;
22881 rcode = reverse_condition (rcode);
22889 /* Mark unsigned tests with CCUNSmode. */
22890 cc_mode = CCUNSmode;
22892 /* Invert condition to avoid compound test if necessary. */
22893 if (rcode == GEU || rcode == LEU)
22895 invert_move = true;
22896 rcode = reverse_condition (rcode);
22904 /* Get the vector mask for the given relational operations. */
22905 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22911 std::swap (op_true, op_false);
22913 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22914 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22915 && (GET_CODE (op_true) == CONST_VECTOR
22916 || GET_CODE (op_false) == CONST_VECTOR))
22918 rtx constant_0 = CONST0_RTX (dest_mode);
22919 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22921 if (op_true == constant_m1 && op_false == constant_0)
22923 emit_move_insn (dest, mask);
22927 else if (op_true == constant_0 && op_false == constant_m1)
22929 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22933 /* If we can't use the vector comparison directly, perhaps we can use
22934 the mask for the true or false fields, instead of loading up a
22936 if (op_true == constant_m1)
22939 if (op_false == constant_0)
22943 if (!REG_P (op_true) && !SUBREG_P (op_true))
22944 op_true = force_reg (dest_mode, op_true);
22946 if (!REG_P (op_false) && !SUBREG_P (op_false))
22947 op_false = force_reg (dest_mode, op_false);
22949 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22950 CONST0_RTX (dest_mode));
22951 emit_insn (gen_rtx_SET (dest,
22952 gen_rtx_IF_THEN_ELSE (dest_mode,
22959 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22960 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22961 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22962 hardware has no such operation. */
22965 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22967 enum rtx_code code = GET_CODE (op);
22968 rtx op0 = XEXP (op, 0);
22969 rtx op1 = XEXP (op, 1);
22970 machine_mode compare_mode = GET_MODE (op0);
22971 machine_mode result_mode = GET_MODE (dest);
22972 bool max_p = false;
22974 if (result_mode != compare_mode)
22977 if (code == GE || code == GT)
22979 else if (code == LE || code == LT)
22984 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22987 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22993 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22997 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22998 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22999 operands of the last comparison is nonzero/true, FALSE_COND if it is
23000 zero/false. Return 0 if the hardware has no such operation. */
23003 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23005 enum rtx_code code = GET_CODE (op);
23006 rtx op0 = XEXP (op, 0);
23007 rtx op1 = XEXP (op, 1);
23008 machine_mode result_mode = GET_MODE (dest);
23013 if (!can_create_pseudo_p ())
23026 code = swap_condition (code);
23027 std::swap (op0, op1);
23034 /* Generate: [(parallel [(set (dest)
23035 (if_then_else (op (cmp1) (cmp2))
23038 (clobber (scratch))])]. */
23040 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
23041 cmove_rtx = gen_rtx_SET (dest,
23042 gen_rtx_IF_THEN_ELSE (result_mode,
23047 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
23048 emit_insn (gen_rtx_PARALLEL (VOIDmode,
23049 gen_rtvec (2, cmove_rtx, clobber_rtx)));
23054 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
23055 operands of the last comparison is nonzero/true, FALSE_COND if it
23056 is zero/false. Return 0 if the hardware has no such operation. */
23059 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23061 enum rtx_code code = GET_CODE (op);
23062 rtx op0 = XEXP (op, 0);
23063 rtx op1 = XEXP (op, 1);
23064 machine_mode compare_mode = GET_MODE (op0);
23065 machine_mode result_mode = GET_MODE (dest);
23067 bool is_against_zero;
23069 /* These modes should always match. */
23070 if (GET_MODE (op1) != compare_mode
23071 /* In the isel case however, we can use a compare immediate, so
23072 op1 may be a small constant. */
23073 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
23075 if (GET_MODE (true_cond) != result_mode)
23077 if (GET_MODE (false_cond) != result_mode)
23080 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
23081 if (TARGET_P9_MINMAX
23082 && (compare_mode == SFmode || compare_mode == DFmode)
23083 && (result_mode == SFmode || result_mode == DFmode))
23085 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
23088 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
23092 /* Don't allow using floating point comparisons for integer results for
23094 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
23097 /* First, work out if the hardware can do this at all, or
23098 if it's too slow.... */
23099 if (!FLOAT_MODE_P (compare_mode))
23102 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
23106 is_against_zero = op1 == CONST0_RTX (compare_mode);
23108 /* A floating-point subtract might overflow, underflow, or produce
23109 an inexact result, thus changing the floating-point flags, so it
23110 can't be generated if we care about that. It's safe if one side
23111 of the construct is zero, since then no subtract will be
23113 if (SCALAR_FLOAT_MODE_P (compare_mode)
23114 && flag_trapping_math && ! is_against_zero)
23117 /* Eliminate half of the comparisons by switching operands, this
23118 makes the remaining code simpler. */
23119 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
23120 || code == LTGT || code == LT || code == UNLE)
23122 code = reverse_condition_maybe_unordered (code);
23124 true_cond = false_cond;
23128 /* UNEQ and LTGT take four instructions for a comparison with zero,
23129 it'll probably be faster to use a branch here too. */
23130 if (code == UNEQ && HONOR_NANS (compare_mode))
23133 /* We're going to try to implement comparisons by performing
23134 a subtract, then comparing against zero. Unfortunately,
23135 Inf - Inf is NaN which is not zero, and so if we don't
23136 know that the operand is finite and the comparison
23137 would treat EQ different to UNORDERED, we can't do it. */
23138 if (HONOR_INFINITIES (compare_mode)
23139 && code != GT && code != UNGE
23140 && (GET_CODE (op1) != CONST_DOUBLE
23141 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
23142 /* Constructs of the form (a OP b ? a : b) are safe. */
23143 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
23144 || (! rtx_equal_p (op0, true_cond)
23145 && ! rtx_equal_p (op1, true_cond))))
23148 /* At this point we know we can use fsel. */
23150 /* Reduce the comparison to a comparison against zero. */
23151 if (! is_against_zero)
23153 temp = gen_reg_rtx (compare_mode);
23154 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
23156 op1 = CONST0_RTX (compare_mode);
23159 /* If we don't care about NaNs we can reduce some of the comparisons
23160 down to faster ones. */
23161 if (! HONOR_NANS (compare_mode))
23167 true_cond = false_cond;
23180 /* Now, reduce everything down to a GE. */
23187 temp = gen_reg_rtx (compare_mode);
23188 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23193 temp = gen_reg_rtx (compare_mode);
23194 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
23199 temp = gen_reg_rtx (compare_mode);
23200 emit_insn (gen_rtx_SET (temp,
23201 gen_rtx_NEG (compare_mode,
23202 gen_rtx_ABS (compare_mode, op0))));
23207 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
23208 temp = gen_reg_rtx (result_mode);
23209 emit_insn (gen_rtx_SET (temp,
23210 gen_rtx_IF_THEN_ELSE (result_mode,
23211 gen_rtx_GE (VOIDmode,
23213 true_cond, false_cond)));
23214 false_cond = true_cond;
23217 temp = gen_reg_rtx (compare_mode);
23218 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23223 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
23224 temp = gen_reg_rtx (result_mode);
23225 emit_insn (gen_rtx_SET (temp,
23226 gen_rtx_IF_THEN_ELSE (result_mode,
23227 gen_rtx_GE (VOIDmode,
23229 true_cond, false_cond)));
23230 true_cond = false_cond;
23233 temp = gen_reg_rtx (compare_mode);
23234 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23239 gcc_unreachable ();
23242 emit_insn (gen_rtx_SET (dest,
23243 gen_rtx_IF_THEN_ELSE (result_mode,
23244 gen_rtx_GE (VOIDmode,
23246 true_cond, false_cond)));
23250 /* Same as above, but for ints (isel). */
23253 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23255 rtx condition_rtx, cr;
23256 machine_mode mode = GET_MODE (dest);
23257 enum rtx_code cond_code;
23258 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
23261 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
23264 /* We still have to do the compare, because isel doesn't do a
23265 compare, it just looks at the CRx bits set by a previous compare
23267 condition_rtx = rs6000_generate_compare (op, mode);
23268 cond_code = GET_CODE (condition_rtx);
23269 cr = XEXP (condition_rtx, 0);
23270 signedp = GET_MODE (cr) == CCmode;
23272 isel_func = (mode == SImode
23273 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
23274 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
23278 case LT: case GT: case LTU: case GTU: case EQ:
23279 /* isel handles these directly. */
23283 /* We need to swap the sense of the comparison. */
23285 std::swap (false_cond, true_cond);
23286 PUT_CODE (condition_rtx, reverse_condition (cond_code));
23291 false_cond = force_reg (mode, false_cond);
23292 if (true_cond != const0_rtx)
23293 true_cond = force_reg (mode, true_cond);
23295 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
23301 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
23303 machine_mode mode = GET_MODE (op0);
23307 /* VSX/altivec have direct min/max insns. */
23308 if ((code == SMAX || code == SMIN)
23309 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
23310 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
23312 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
23316 if (code == SMAX || code == SMIN)
23321 if (code == SMAX || code == UMAX)
23322 target = emit_conditional_move (dest, c, op0, op1, mode,
23323 op0, op1, mode, 0);
23325 target = emit_conditional_move (dest, c, op0, op1, mode,
23326 op1, op0, mode, 0);
23327 gcc_assert (target);
23328 if (target != dest)
23329 emit_move_insn (dest, target);
23332 /* Split a signbit operation on 64-bit machines with direct move. Also allow
23333 for the value to come from memory or if it is already loaded into a GPR. */
23336 rs6000_split_signbit (rtx dest, rtx src)
23338 machine_mode d_mode = GET_MODE (dest);
23339 machine_mode s_mode = GET_MODE (src);
23340 rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest);
23341 rtx shift_reg = dest_di;
23343 gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64);
23347 rtx mem = (WORDS_BIG_ENDIAN
23348 ? adjust_address (src, DImode, 0)
23349 : adjust_address (src, DImode, 8));
23350 emit_insn (gen_rtx_SET (dest_di, mem));
23355 unsigned int r = reg_or_subregno (src);
23357 if (INT_REGNO_P (r))
23358 shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0));
23362 /* Generate the special mfvsrd instruction to get it in a GPR. */
23363 gcc_assert (VSX_REGNO_P (r));
23364 if (s_mode == KFmode)
23365 emit_insn (gen_signbitkf2_dm2 (dest_di, src));
23367 emit_insn (gen_signbittf2_dm2 (dest_di, src));
23371 emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
23375 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23376 COND is true. Mark the jump as unlikely to be taken. */
23379 emit_unlikely_jump (rtx cond, rtx label)
23381 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
23382 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
23383 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
23386 /* A subroutine of the atomic operation splitters. Emit a load-locked
23387 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23388 the zero_extend operation. */
23391 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
23393 rtx (*fn) (rtx, rtx) = NULL;
23398 fn = gen_load_lockedqi;
23401 fn = gen_load_lockedhi;
23404 if (GET_MODE (mem) == QImode)
23405 fn = gen_load_lockedqi_si;
23406 else if (GET_MODE (mem) == HImode)
23407 fn = gen_load_lockedhi_si;
23409 fn = gen_load_lockedsi;
23412 fn = gen_load_lockeddi;
23415 fn = gen_load_lockedti;
23418 gcc_unreachable ();
23420 emit_insn (fn (reg, mem));
23423 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23424 instruction in MODE. */
23427 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23429 rtx (*fn) (rtx, rtx, rtx) = NULL;
23434 fn = gen_store_conditionalqi;
23437 fn = gen_store_conditionalhi;
23440 fn = gen_store_conditionalsi;
23443 fn = gen_store_conditionaldi;
23446 fn = gen_store_conditionalti;
23449 gcc_unreachable ();
23452 /* Emit sync before stwcx. to address PPC405 Erratum. */
23453 if (PPC405_ERRATUM77)
23454 emit_insn (gen_hwsync ());
23456 emit_insn (fn (res, mem, val));
23459 /* Expand barriers before and after a load_locked/store_cond sequence. */
23462 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23464 rtx addr = XEXP (mem, 0);
23466 if (!legitimate_indirect_address_p (addr, reload_completed)
23467 && !legitimate_indexed_address_p (addr, reload_completed))
23469 addr = force_reg (Pmode, addr);
23470 mem = replace_equiv_address_nv (mem, addr);
23475 case MEMMODEL_RELAXED:
23476 case MEMMODEL_CONSUME:
23477 case MEMMODEL_ACQUIRE:
23479 case MEMMODEL_RELEASE:
23480 case MEMMODEL_ACQ_REL:
23481 emit_insn (gen_lwsync ());
23483 case MEMMODEL_SEQ_CST:
23484 emit_insn (gen_hwsync ());
23487 gcc_unreachable ();
23493 rs6000_post_atomic_barrier (enum memmodel model)
23497 case MEMMODEL_RELAXED:
23498 case MEMMODEL_CONSUME:
23499 case MEMMODEL_RELEASE:
23501 case MEMMODEL_ACQUIRE:
23502 case MEMMODEL_ACQ_REL:
23503 case MEMMODEL_SEQ_CST:
23504 emit_insn (gen_isync ());
23507 gcc_unreachable ();
23511 /* A subroutine of the various atomic expanders. For sub-word operations,
23512 we must adjust things to operate on SImode. Given the original MEM,
23513 return a new aligned memory. Also build and return the quantities by
23514 which to shift and mask. */
23517 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23519 rtx addr, align, shift, mask, mem;
23520 HOST_WIDE_INT shift_mask;
23521 machine_mode mode = GET_MODE (orig_mem);
23523 /* For smaller modes, we have to implement this via SImode. */
23524 shift_mask = (mode == QImode ? 0x18 : 0x10);
23526 addr = XEXP (orig_mem, 0);
23527 addr = force_reg (GET_MODE (addr), addr);
23529 /* Aligned memory containing subword. Generate a new memory. We
23530 do not want any of the existing MEM_ATTR data, as we're now
23531 accessing memory outside the original object. */
23532 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23533 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23534 mem = gen_rtx_MEM (SImode, align);
23535 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23536 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23537 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23539 /* Shift amount for subword relative to aligned word. */
23540 shift = gen_reg_rtx (SImode);
23541 addr = gen_lowpart (SImode, addr);
23542 rtx tmp = gen_reg_rtx (SImode);
23543 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23544 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23545 if (BYTES_BIG_ENDIAN)
23546 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23547 shift, 1, OPTAB_LIB_WIDEN);
23550 /* Mask for insertion. */
23551 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23552 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23558 /* A subroutine of the various atomic expanders. For sub-word operands,
23559 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23562 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23566 x = gen_reg_rtx (SImode);
23567 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23568 gen_rtx_NOT (SImode, mask),
23571 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23576 /* A subroutine of the various atomic expanders. For sub-word operands,
23577 extract WIDE to NARROW via SHIFT. */
23580 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23582 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23583 wide, 1, OPTAB_LIB_WIDEN);
23584 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23587 /* Expand an atomic compare and swap operation. */
23590 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23592 rtx boolval, retval, mem, oldval, newval, cond;
23593 rtx label1, label2, x, mask, shift;
23594 machine_mode mode, orig_mode;
23595 enum memmodel mod_s, mod_f;
23598 boolval = operands[0];
23599 retval = operands[1];
23601 oldval = operands[3];
23602 newval = operands[4];
23603 is_weak = (INTVAL (operands[5]) != 0);
23604 mod_s = memmodel_base (INTVAL (operands[6]));
23605 mod_f = memmodel_base (INTVAL (operands[7]));
23606 orig_mode = mode = GET_MODE (mem);
23608 mask = shift = NULL_RTX;
23609 if (mode == QImode || mode == HImode)
23611 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23612 lwarx and shift/mask operations. With power8, we need to do the
23613 comparison in SImode, but the store is still done in QI/HImode. */
23614 oldval = convert_modes (SImode, mode, oldval, 1);
23616 if (!TARGET_SYNC_HI_QI)
23618 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23620 /* Shift and mask OLDVAL into position with the word. */
23621 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23622 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23624 /* Shift and mask NEWVAL into position within the word. */
23625 newval = convert_modes (SImode, mode, newval, 1);
23626 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23627 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23630 /* Prepare to adjust the return value. */
23631 retval = gen_reg_rtx (SImode);
23634 else if (reg_overlap_mentioned_p (retval, oldval))
23635 oldval = copy_to_reg (oldval);
23637 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23638 oldval = copy_to_mode_reg (mode, oldval);
23640 if (reg_overlap_mentioned_p (retval, newval))
23641 newval = copy_to_reg (newval);
23643 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23648 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23649 emit_label (XEXP (label1, 0));
23651 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23653 emit_load_locked (mode, retval, mem);
23657 x = expand_simple_binop (SImode, AND, retval, mask,
23658 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23660 cond = gen_reg_rtx (CCmode);
23661 /* If we have TImode, synthesize a comparison. */
23662 if (mode != TImode)
23663 x = gen_rtx_COMPARE (CCmode, x, oldval);
23666 rtx xor1_result = gen_reg_rtx (DImode);
23667 rtx xor2_result = gen_reg_rtx (DImode);
23668 rtx or_result = gen_reg_rtx (DImode);
23669 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23670 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23671 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23672 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23674 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23675 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23676 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23677 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23680 emit_insn (gen_rtx_SET (cond, x));
23682 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23683 emit_unlikely_jump (x, label2);
23687 x = rs6000_mask_atomic_subword (retval, newval, mask);
23689 emit_store_conditional (orig_mode, cond, mem, x);
23693 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23694 emit_unlikely_jump (x, label1);
23697 if (!is_mm_relaxed (mod_f))
23698 emit_label (XEXP (label2, 0));
23700 rs6000_post_atomic_barrier (mod_s);
23702 if (is_mm_relaxed (mod_f))
23703 emit_label (XEXP (label2, 0));
23706 rs6000_finish_atomic_subword (operands[1], retval, shift);
23707 else if (mode != GET_MODE (operands[1]))
23708 convert_move (operands[1], retval, 1);
23710 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23711 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23712 emit_insn (gen_rtx_SET (boolval, x));
23715 /* Expand an atomic exchange operation. */
23718 rs6000_expand_atomic_exchange (rtx operands[])
23720 rtx retval, mem, val, cond;
23722 enum memmodel model;
23723 rtx label, x, mask, shift;
23725 retval = operands[0];
23728 model = memmodel_base (INTVAL (operands[3]));
23729 mode = GET_MODE (mem);
23731 mask = shift = NULL_RTX;
23732 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23734 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23736 /* Shift and mask VAL into position with the word. */
23737 val = convert_modes (SImode, mode, val, 1);
23738 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23739 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23741 /* Prepare to adjust the return value. */
23742 retval = gen_reg_rtx (SImode);
23746 mem = rs6000_pre_atomic_barrier (mem, model);
23748 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23749 emit_label (XEXP (label, 0));
23751 emit_load_locked (mode, retval, mem);
23755 x = rs6000_mask_atomic_subword (retval, val, mask);
23757 cond = gen_reg_rtx (CCmode);
23758 emit_store_conditional (mode, cond, mem, x);
23760 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23761 emit_unlikely_jump (x, label);
23763 rs6000_post_atomic_barrier (model);
23766 rs6000_finish_atomic_subword (operands[0], retval, shift);
23769 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23770 to perform. MEM is the memory on which to operate. VAL is the second
23771 operand of the binary operator. BEFORE and AFTER are optional locations to
23772 return the value of MEM either before of after the operation. MODEL_RTX
23773 is a CONST_INT containing the memory model to use. */
23776 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23777 rtx orig_before, rtx orig_after, rtx model_rtx)
23779 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23780 machine_mode mode = GET_MODE (mem);
23781 machine_mode store_mode = mode;
23782 rtx label, x, cond, mask, shift;
23783 rtx before = orig_before, after = orig_after;
23785 mask = shift = NULL_RTX;
23786 /* On power8, we want to use SImode for the operation. On previous systems,
23787 use the operation in a subword and shift/mask to get the proper byte or
23789 if (mode == QImode || mode == HImode)
23791 if (TARGET_SYNC_HI_QI)
23793 val = convert_modes (SImode, mode, val, 1);
23795 /* Prepare to adjust the return value. */
23796 before = gen_reg_rtx (SImode);
23798 after = gen_reg_rtx (SImode);
23803 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23805 /* Shift and mask VAL into position with the word. */
23806 val = convert_modes (SImode, mode, val, 1);
23807 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23808 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23814 /* We've already zero-extended VAL. That is sufficient to
23815 make certain that it does not affect other bits. */
23820 /* If we make certain that all of the other bits in VAL are
23821 set, that will be sufficient to not affect other bits. */
23822 x = gen_rtx_NOT (SImode, mask);
23823 x = gen_rtx_IOR (SImode, x, val);
23824 emit_insn (gen_rtx_SET (val, x));
23831 /* These will all affect bits outside the field and need
23832 adjustment via MASK within the loop. */
23836 gcc_unreachable ();
23839 /* Prepare to adjust the return value. */
23840 before = gen_reg_rtx (SImode);
23842 after = gen_reg_rtx (SImode);
23843 store_mode = mode = SImode;
23847 mem = rs6000_pre_atomic_barrier (mem, model);
23849 label = gen_label_rtx ();
23850 emit_label (label);
23851 label = gen_rtx_LABEL_REF (VOIDmode, label);
23853 if (before == NULL_RTX)
23854 before = gen_reg_rtx (mode);
23856 emit_load_locked (mode, before, mem);
23860 x = expand_simple_binop (mode, AND, before, val,
23861 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23862 after = expand_simple_unop (mode, NOT, x, after, 1);
23866 after = expand_simple_binop (mode, code, before, val,
23867 after, 1, OPTAB_LIB_WIDEN);
23873 x = expand_simple_binop (SImode, AND, after, mask,
23874 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23875 x = rs6000_mask_atomic_subword (before, x, mask);
23877 else if (store_mode != mode)
23878 x = convert_modes (store_mode, mode, x, 1);
23880 cond = gen_reg_rtx (CCmode);
23881 emit_store_conditional (store_mode, cond, mem, x);
23883 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23884 emit_unlikely_jump (x, label);
23886 rs6000_post_atomic_barrier (model);
23890 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23891 then do the calcuations in a SImode register. */
23893 rs6000_finish_atomic_subword (orig_before, before, shift);
23895 rs6000_finish_atomic_subword (orig_after, after, shift);
23897 else if (store_mode != mode)
23899 /* QImode/HImode on machines with lbarx/lharx where we do the native
23900 operation and then do the calcuations in a SImode register. */
23902 convert_move (orig_before, before, 1);
23904 convert_move (orig_after, after, 1);
23906 else if (orig_after && after != orig_after)
23907 emit_move_insn (orig_after, after);
23910 /* Emit instructions to move SRC to DST. Called by splitters for
23911 multi-register moves. It will emit at most one instruction for
23912 each register that is accessed; that is, it won't emit li/lis pairs
23913 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23917 rs6000_split_multireg_move (rtx dst, rtx src)
23919 /* The register number of the first register being moved. */
23921 /* The mode that is to be moved. */
23923 /* The mode that the move is being done in, and its size. */
23924 machine_mode reg_mode;
23926 /* The number of registers that will be moved. */
23929 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23930 mode = GET_MODE (dst);
23931 nregs = hard_regno_nregs (reg, mode);
23932 if (FP_REGNO_P (reg))
23933 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23934 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
23935 else if (ALTIVEC_REGNO_P (reg))
23936 reg_mode = V16QImode;
23938 reg_mode = word_mode;
23939 reg_mode_size = GET_MODE_SIZE (reg_mode);
23941 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23943 /* TDmode residing in FP registers is special, since the ISA requires that
23944 the lower-numbered word of a register pair is always the most significant
23945 word, even in little-endian mode. This does not match the usual subreg
23946 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23947 the appropriate constituent registers "by hand" in little-endian mode.
23949 Note we do not need to check for destructive overlap here since TDmode
23950 can only reside in even/odd register pairs. */
23951 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23956 for (i = 0; i < nregs; i++)
23958 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23959 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23961 p_src = simplify_gen_subreg (reg_mode, src, mode,
23962 i * reg_mode_size);
23964 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23965 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23967 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23968 i * reg_mode_size);
23970 emit_insn (gen_rtx_SET (p_dst, p_src));
23976 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23978 /* Move register range backwards, if we might have destructive
23981 for (i = nregs - 1; i >= 0; i--)
23982 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23983 i * reg_mode_size),
23984 simplify_gen_subreg (reg_mode, src, mode,
23985 i * reg_mode_size)));
23991 bool used_update = false;
23992 rtx restore_basereg = NULL_RTX;
23994 if (MEM_P (src) && INT_REGNO_P (reg))
23998 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23999 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
24002 breg = XEXP (XEXP (src, 0), 0);
24003 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
24004 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
24005 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
24006 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24007 src = replace_equiv_address (src, breg);
24009 else if (! rs6000_offsettable_memref_p (src, reg_mode))
24011 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
24013 rtx basereg = XEXP (XEXP (src, 0), 0);
24016 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
24017 emit_insn (gen_rtx_SET (ndst,
24018 gen_rtx_MEM (reg_mode,
24020 used_update = true;
24023 emit_insn (gen_rtx_SET (basereg,
24024 XEXP (XEXP (src, 0), 1)));
24025 src = replace_equiv_address (src, basereg);
24029 rtx basereg = gen_rtx_REG (Pmode, reg);
24030 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
24031 src = replace_equiv_address (src, basereg);
24035 breg = XEXP (src, 0);
24036 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
24037 breg = XEXP (breg, 0);
24039 /* If the base register we are using to address memory is
24040 also a destination reg, then change that register last. */
24042 && REGNO (breg) >= REGNO (dst)
24043 && REGNO (breg) < REGNO (dst) + nregs)
24044 j = REGNO (breg) - REGNO (dst);
24046 else if (MEM_P (dst) && INT_REGNO_P (reg))
24050 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
24051 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
24054 breg = XEXP (XEXP (dst, 0), 0);
24055 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
24056 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
24057 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
24059 /* We have to update the breg before doing the store.
24060 Use store with update, if available. */
24064 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24065 emit_insn (TARGET_32BIT
24066 ? (TARGET_POWERPC64
24067 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
24068 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
24069 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
24070 used_update = true;
24073 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24074 dst = replace_equiv_address (dst, breg);
24076 else if (!rs6000_offsettable_memref_p (dst, reg_mode)
24077 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
24079 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
24081 rtx basereg = XEXP (XEXP (dst, 0), 0);
24084 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24085 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
24088 used_update = true;
24091 emit_insn (gen_rtx_SET (basereg,
24092 XEXP (XEXP (dst, 0), 1)));
24093 dst = replace_equiv_address (dst, basereg);
24097 rtx basereg = XEXP (XEXP (dst, 0), 0);
24098 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
24099 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
24101 && REG_P (offsetreg)
24102 && REGNO (basereg) != REGNO (offsetreg));
24103 if (REGNO (basereg) == 0)
24105 rtx tmp = offsetreg;
24106 offsetreg = basereg;
24109 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
24110 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
24111 dst = replace_equiv_address (dst, basereg);
24114 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
24115 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
24118 for (i = 0; i < nregs; i++)
24120 /* Calculate index to next subword. */
24125 /* If compiler already emitted move of first word by
24126 store with update, no need to do anything. */
24127 if (j == 0 && used_update)
24130 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24131 j * reg_mode_size),
24132 simplify_gen_subreg (reg_mode, src, mode,
24133 j * reg_mode_size)));
24135 if (restore_basereg != NULL_RTX)
24136 emit_insn (restore_basereg);
24141 /* This page contains routines that are used to determine what the
24142 function prologue and epilogue code will do and write them out. */
24144 /* Determine whether the REG is really used. */
24147 save_reg_p (int reg)
24149 /* We need to mark the PIC offset register live for the same conditions
24150 as it is set up, or otherwise it won't be saved before we clobber it. */
24152 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
24154 /* When calling eh_return, we must return true for all the cases
24155 where conditional_register_usage marks the PIC offset reg
24157 if (TARGET_TOC && TARGET_MINIMAL_TOC
24158 && (crtl->calls_eh_return
24159 || df_regs_ever_live_p (reg)
24160 || !constant_pool_empty_p ()))
24163 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
24168 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
24171 /* Return the first fixed-point register that is required to be
24172 saved. 32 if none. */
24175 first_reg_to_save (void)
24179 /* Find lowest numbered live register. */
24180 for (first_reg = 13; first_reg <= 31; first_reg++)
24181 if (save_reg_p (first_reg))
24186 && crtl->uses_pic_offset_table
24187 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
24188 return RS6000_PIC_OFFSET_TABLE_REGNUM;
24194 /* Similar, for FP regs. */
24197 first_fp_reg_to_save (void)
24201 /* Find lowest numbered live register. */
24202 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
24203 if (save_reg_p (first_reg))
24209 /* Similar, for AltiVec regs. */
24212 first_altivec_reg_to_save (void)
24216 /* Stack frame remains as is unless we are in AltiVec ABI. */
24217 if (! TARGET_ALTIVEC_ABI)
24218 return LAST_ALTIVEC_REGNO + 1;
24220 /* On Darwin, the unwind routines are compiled without
24221 TARGET_ALTIVEC, and use save_world to save/restore the
24222 altivec registers when necessary. */
24223 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24224 && ! TARGET_ALTIVEC)
24225 return FIRST_ALTIVEC_REGNO + 20;
24227 /* Find lowest numbered live register. */
24228 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
24229 if (save_reg_p (i))
24235 /* Return a 32-bit mask of the AltiVec registers we need to set in
24236 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
24237 the 32-bit word is 0. */
24239 static unsigned int
24240 compute_vrsave_mask (void)
24242 unsigned int i, mask = 0;
24244 /* On Darwin, the unwind routines are compiled without
24245 TARGET_ALTIVEC, and use save_world to save/restore the
24246 call-saved altivec registers when necessary. */
24247 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24248 && ! TARGET_ALTIVEC)
24251 /* First, find out if we use _any_ altivec registers. */
24252 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
24253 if (df_regs_ever_live_p (i))
24254 mask |= ALTIVEC_REG_BIT (i);
24259 /* Next, remove the argument registers from the set. These must
24260 be in the VRSAVE mask set by the caller, so we don't need to add
24261 them in again. More importantly, the mask we compute here is
24262 used to generate CLOBBERs in the set_vrsave insn, and we do not
24263 wish the argument registers to die. */
24264 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
24265 mask &= ~ALTIVEC_REG_BIT (i);
24267 /* Similarly, remove the return value from the set. */
24270 diddle_return_value (is_altivec_return_reg, &yes);
24272 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
24278 /* For a very restricted set of circumstances, we can cut down the
24279 size of prologues/epilogues by calling our own save/restore-the-world
24283 compute_save_world_info (rs6000_stack_t *info)
24285 info->world_save_p = 1;
24287 = (WORLD_SAVE_P (info)
24288 && DEFAULT_ABI == ABI_DARWIN
24289 && !cfun->has_nonlocal_label
24290 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
24291 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
24292 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
24293 && info->cr_save_p);
24295 /* This will not work in conjunction with sibcalls. Make sure there
24296 are none. (This check is expensive, but seldom executed.) */
24297 if (WORLD_SAVE_P (info))
24300 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
24301 if (CALL_P (insn) && SIBLING_CALL_P (insn))
24303 info->world_save_p = 0;
24308 if (WORLD_SAVE_P (info))
24310 /* Even if we're not touching VRsave, make sure there's room on the
24311 stack for it, if it looks like we're calling SAVE_WORLD, which
24312 will attempt to save it. */
24313 info->vrsave_size = 4;
24315 /* If we are going to save the world, we need to save the link register too. */
24316 info->lr_save_p = 1;
24318 /* "Save" the VRsave register too if we're saving the world. */
24319 if (info->vrsave_mask == 0)
24320 info->vrsave_mask = compute_vrsave_mask ();
24322 /* Because the Darwin register save/restore routines only handle
24323 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24325 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
24326 && (info->first_altivec_reg_save
24327 >= FIRST_SAVED_ALTIVEC_REGNO));
24335 is_altivec_return_reg (rtx reg, void *xyes)
24337 bool *yes = (bool *) xyes;
24338 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
24343 /* Return whether REG is a global user reg or has been specifed by
24344 -ffixed-REG. We should not restore these, and so cannot use
24345 lmw or out-of-line restore functions if there are any. We also
24346 can't save them (well, emit frame notes for them), because frame
24347 unwinding during exception handling will restore saved registers. */
24350 fixed_reg_p (int reg)
24352 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24353 backend sets it, overriding anything the user might have given. */
24354 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
24355 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
24356 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
24357 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
24360 return fixed_regs[reg];
24363 /* Determine the strategy for savings/restoring registers. */
24366 SAVE_MULTIPLE = 0x1,
24367 SAVE_INLINE_GPRS = 0x2,
24368 SAVE_INLINE_FPRS = 0x4,
24369 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
24370 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
24371 SAVE_INLINE_VRS = 0x20,
24372 REST_MULTIPLE = 0x100,
24373 REST_INLINE_GPRS = 0x200,
24374 REST_INLINE_FPRS = 0x400,
24375 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
24376 REST_INLINE_VRS = 0x1000
24380 rs6000_savres_strategy (rs6000_stack_t *info,
24381 bool using_static_chain_p)
24385 /* Select between in-line and out-of-line save and restore of regs.
24386 First, all the obvious cases where we don't use out-of-line. */
24387 if (crtl->calls_eh_return
24388 || cfun->machine->ra_need_lr)
24389 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
24390 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
24391 | SAVE_INLINE_VRS | REST_INLINE_VRS);
24393 if (info->first_gp_reg_save == 32)
24394 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24396 if (info->first_fp_reg_save == 64
24397 /* The out-of-line FP routines use double-precision stores;
24398 we can't use those routines if we don't have such stores. */
24399 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
24400 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24402 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
24403 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24405 /* Define cutoff for using out-of-line functions to save registers. */
24406 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
24408 if (!optimize_size)
24410 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24411 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24412 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24416 /* Prefer out-of-line restore if it will exit. */
24417 if (info->first_fp_reg_save > 61)
24418 strategy |= SAVE_INLINE_FPRS;
24419 if (info->first_gp_reg_save > 29)
24421 if (info->first_fp_reg_save == 64)
24422 strategy |= SAVE_INLINE_GPRS;
24424 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24426 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24427 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24430 else if (DEFAULT_ABI == ABI_DARWIN)
24432 if (info->first_fp_reg_save > 60)
24433 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24434 if (info->first_gp_reg_save > 29)
24435 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24436 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24440 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24441 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24442 || info->first_fp_reg_save > 61)
24443 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24444 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24445 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24448 /* Don't bother to try to save things out-of-line if r11 is occupied
24449 by the static chain. It would require too much fiddling and the
24450 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24451 pointer on Darwin, and AIX uses r1 or r12. */
24452 if (using_static_chain_p
24453 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24454 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24456 | SAVE_INLINE_VRS);
24458 /* Don't ever restore fixed regs. That means we can't use the
24459 out-of-line register restore functions if a fixed reg is in the
24460 range of regs restored. */
24461 if (!(strategy & REST_INLINE_FPRS))
24462 for (int i = info->first_fp_reg_save; i < 64; i++)
24465 strategy |= REST_INLINE_FPRS;
24469 /* We can only use the out-of-line routines to restore fprs if we've
24470 saved all the registers from first_fp_reg_save in the prologue.
24471 Otherwise, we risk loading garbage. Of course, if we have saved
24472 out-of-line then we know we haven't skipped any fprs. */
24473 if ((strategy & SAVE_INLINE_FPRS)
24474 && !(strategy & REST_INLINE_FPRS))
24475 for (int i = info->first_fp_reg_save; i < 64; i++)
24476 if (!save_reg_p (i))
24478 strategy |= REST_INLINE_FPRS;
24482 /* Similarly, for altivec regs. */
24483 if (!(strategy & REST_INLINE_VRS))
24484 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24487 strategy |= REST_INLINE_VRS;
24491 if ((strategy & SAVE_INLINE_VRS)
24492 && !(strategy & REST_INLINE_VRS))
24493 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24494 if (!save_reg_p (i))
24496 strategy |= REST_INLINE_VRS;
24500 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24501 saved is an out-of-line save or restore. Set up the value for
24502 the next test (excluding out-of-line gprs). */
24503 bool lr_save_p = (info->lr_save_p
24504 || !(strategy & SAVE_INLINE_FPRS)
24505 || !(strategy & SAVE_INLINE_VRS)
24506 || !(strategy & REST_INLINE_FPRS)
24507 || !(strategy & REST_INLINE_VRS));
24509 if (TARGET_MULTIPLE
24510 && !TARGET_POWERPC64
24511 && info->first_gp_reg_save < 31
24512 && !(flag_shrink_wrap
24513 && flag_shrink_wrap_separate
24514 && optimize_function_for_speed_p (cfun)))
24517 for (int i = info->first_gp_reg_save; i < 32; i++)
24518 if (save_reg_p (i))
24522 /* Don't use store multiple if only one reg needs to be
24523 saved. This can occur for example when the ABI_V4 pic reg
24524 (r30) needs to be saved to make calls, but r31 is not
24526 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24529 /* Prefer store multiple for saves over out-of-line
24530 routines, since the store-multiple instruction will
24531 always be smaller. */
24532 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24534 /* The situation is more complicated with load multiple.
24535 We'd prefer to use the out-of-line routines for restores,
24536 since the "exit" out-of-line routines can handle the
24537 restore of LR and the frame teardown. However if doesn't
24538 make sense to use the out-of-line routine if that is the
24539 only reason we'd need to save LR, and we can't use the
24540 "exit" out-of-line gpr restore if we have saved some
24541 fprs; In those cases it is advantageous to use load
24542 multiple when available. */
24543 if (info->first_fp_reg_save != 64 || !lr_save_p)
24544 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24548 /* Using the "exit" out-of-line routine does not improve code size
24549 if using it would require lr to be saved and if only saving one
24551 else if (!lr_save_p && info->first_gp_reg_save > 29)
24552 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24554 /* Don't ever restore fixed regs. */
24555 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24556 for (int i = info->first_gp_reg_save; i < 32; i++)
24557 if (fixed_reg_p (i))
24559 strategy |= REST_INLINE_GPRS;
24560 strategy &= ~REST_MULTIPLE;
24564 /* We can only use load multiple or the out-of-line routines to
24565 restore gprs if we've saved all the registers from
24566 first_gp_reg_save. Otherwise, we risk loading garbage.
24567 Of course, if we have saved out-of-line or used stmw then we know
24568 we haven't skipped any gprs. */
24569 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24570 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24571 for (int i = info->first_gp_reg_save; i < 32; i++)
24572 if (!save_reg_p (i))
24574 strategy |= REST_INLINE_GPRS;
24575 strategy &= ~REST_MULTIPLE;
24579 if (TARGET_ELF && TARGET_64BIT)
24581 if (!(strategy & SAVE_INLINE_FPRS))
24582 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24583 else if (!(strategy & SAVE_INLINE_GPRS)
24584 && info->first_fp_reg_save == 64)
24585 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24587 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24588 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24590 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24591 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24596 /* Calculate the stack information for the current function. This is
24597 complicated by having two separate calling sequences, the AIX calling
24598 sequence and the V.4 calling sequence.
24600 AIX (and Darwin/Mac OS X) stack frames look like:
24602 SP----> +---------------------------------------+
24603 | back chain to caller | 0 0
24604 +---------------------------------------+
24605 | saved CR | 4 8 (8-11)
24606 +---------------------------------------+
24608 +---------------------------------------+
24609 | reserved for compilers | 12 24
24610 +---------------------------------------+
24611 | reserved for binders | 16 32
24612 +---------------------------------------+
24613 | saved TOC pointer | 20 40
24614 +---------------------------------------+
24615 | Parameter save area (+padding*) (P) | 24 48
24616 +---------------------------------------+
24617 | Alloca space (A) | 24+P etc.
24618 +---------------------------------------+
24619 | Local variable space (L) | 24+P+A
24620 +---------------------------------------+
24621 | Float/int conversion temporary (X) | 24+P+A+L
24622 +---------------------------------------+
24623 | Save area for AltiVec registers (W) | 24+P+A+L+X
24624 +---------------------------------------+
24625 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24626 +---------------------------------------+
24627 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24628 +---------------------------------------+
24629 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24630 +---------------------------------------+
24631 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24632 +---------------------------------------+
24633 old SP->| back chain to caller's caller |
24634 +---------------------------------------+
24636 * If the alloca area is present, the parameter save area is
24637 padded so that the former starts 16-byte aligned.
24639 The required alignment for AIX configurations is two words (i.e., 8
24642 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24644 SP----> +---------------------------------------+
24645 | Back chain to caller | 0
24646 +---------------------------------------+
24647 | Save area for CR | 8
24648 +---------------------------------------+
24650 +---------------------------------------+
24651 | Saved TOC pointer | 24
24652 +---------------------------------------+
24653 | Parameter save area (+padding*) (P) | 32
24654 +---------------------------------------+
24655 | Alloca space (A) | 32+P
24656 +---------------------------------------+
24657 | Local variable space (L) | 32+P+A
24658 +---------------------------------------+
24659 | Save area for AltiVec registers (W) | 32+P+A+L
24660 +---------------------------------------+
24661 | AltiVec alignment padding (Y) | 32+P+A+L+W
24662 +---------------------------------------+
24663 | Save area for GP registers (G) | 32+P+A+L+W+Y
24664 +---------------------------------------+
24665 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24666 +---------------------------------------+
24667 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24668 +---------------------------------------+
24670 * If the alloca area is present, the parameter save area is
24671 padded so that the former starts 16-byte aligned.
24673 V.4 stack frames look like:
24675 SP----> +---------------------------------------+
24676 | back chain to caller | 0
24677 +---------------------------------------+
24678 | caller's saved LR | 4
24679 +---------------------------------------+
24680 | Parameter save area (+padding*) (P) | 8
24681 +---------------------------------------+
24682 | Alloca space (A) | 8+P
24683 +---------------------------------------+
24684 | Varargs save area (V) | 8+P+A
24685 +---------------------------------------+
24686 | Local variable space (L) | 8+P+A+V
24687 +---------------------------------------+
24688 | Float/int conversion temporary (X) | 8+P+A+V+L
24689 +---------------------------------------+
24690 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24691 +---------------------------------------+
24692 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24693 +---------------------------------------+
24694 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24695 +---------------------------------------+
24696 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24697 +---------------------------------------+
24698 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24699 +---------------------------------------+
24700 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24701 +---------------------------------------+
24702 old SP->| back chain to caller's caller |
24703 +---------------------------------------+
24705 * If the alloca area is present and the required alignment is
24706 16 bytes, the parameter save area is padded so that the
24707 alloca area starts 16-byte aligned.
24709 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24710 given. (But note below and in sysv4.h that we require only 8 and
24711 may round up the size of our stack frame anyways. The historical
24712 reason is early versions of powerpc-linux which didn't properly
24713 align the stack at program startup. A happy side-effect is that
24714 -mno-eabi libraries can be used with -meabi programs.)
24716 The EABI configuration defaults to the V.4 layout. However,
24717 the stack alignment requirements may differ. If -mno-eabi is not
24718 given, the required stack alignment is 8 bytes; if -mno-eabi is
24719 given, the required alignment is 16 bytes. (But see V.4 comment
24722 #ifndef ABI_STACK_BOUNDARY
24723 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24726 static rs6000_stack_t *
24727 rs6000_stack_info (void)
24729 /* We should never be called for thunks, we are not set up for that. */
24730 gcc_assert (!cfun->is_thunk);
24732 rs6000_stack_t *info = &stack_info;
24733 int reg_size = TARGET_32BIT ? 4 : 8;
24738 HOST_WIDE_INT non_fixed_size;
24739 bool using_static_chain_p;
24741 if (reload_completed && info->reload_completed)
24744 memset (info, 0, sizeof (*info));
24745 info->reload_completed = reload_completed;
24747 /* Select which calling sequence. */
24748 info->abi = DEFAULT_ABI;
24750 /* Calculate which registers need to be saved & save area size. */
24751 info->first_gp_reg_save = first_reg_to_save ();
24752 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24753 even if it currently looks like we won't. Reload may need it to
24754 get at a constant; if so, it will have already created a constant
24755 pool entry for it. */
24756 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24757 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24758 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24759 && crtl->uses_const_pool
24760 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24761 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24763 first_gp = info->first_gp_reg_save;
24765 info->gp_size = reg_size * (32 - first_gp);
24767 info->first_fp_reg_save = first_fp_reg_to_save ();
24768 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24770 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24771 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24772 - info->first_altivec_reg_save);
24774 /* Does this function call anything? */
24775 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24777 /* Determine if we need to save the condition code registers. */
24778 if (save_reg_p (CR2_REGNO)
24779 || save_reg_p (CR3_REGNO)
24780 || save_reg_p (CR4_REGNO))
24782 info->cr_save_p = 1;
24783 if (DEFAULT_ABI == ABI_V4)
24784 info->cr_size = reg_size;
24787 /* If the current function calls __builtin_eh_return, then we need
24788 to allocate stack space for registers that will hold data for
24789 the exception handler. */
24790 if (crtl->calls_eh_return)
24793 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24796 ehrd_size = i * UNITS_PER_WORD;
24801 /* In the ELFv2 ABI, we also need to allocate space for separate
24802 CR field save areas if the function calls __builtin_eh_return. */
24803 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24805 /* This hard-codes that we have three call-saved CR fields. */
24806 ehcr_size = 3 * reg_size;
24807 /* We do *not* use the regular CR save mechanism. */
24808 info->cr_save_p = 0;
24813 /* Determine various sizes. */
24814 info->reg_size = reg_size;
24815 info->fixed_size = RS6000_SAVE_AREA;
24816 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24817 if (cfun->calls_alloca)
24819 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24820 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24822 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24823 TARGET_ALTIVEC ? 16 : 8);
24824 if (FRAME_GROWS_DOWNWARD)
24826 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24827 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24828 - (info->fixed_size + info->vars_size + info->parm_size);
24830 if (TARGET_ALTIVEC_ABI)
24831 info->vrsave_mask = compute_vrsave_mask ();
24833 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24834 info->vrsave_size = 4;
24836 compute_save_world_info (info);
24838 /* Calculate the offsets. */
24839 switch (DEFAULT_ABI)
24843 gcc_unreachable ();
24848 info->fp_save_offset = -info->fp_size;
24849 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24851 if (TARGET_ALTIVEC_ABI)
24853 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24855 /* Align stack so vector save area is on a quadword boundary.
24856 The padding goes above the vectors. */
24857 if (info->altivec_size != 0)
24858 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24860 info->altivec_save_offset = info->vrsave_save_offset
24861 - info->altivec_padding_size
24862 - info->altivec_size;
24863 gcc_assert (info->altivec_size == 0
24864 || info->altivec_save_offset % 16 == 0);
24866 /* Adjust for AltiVec case. */
24867 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24870 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24872 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24873 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24874 info->lr_save_offset = 2*reg_size;
24878 info->fp_save_offset = -info->fp_size;
24879 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24880 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24882 if (TARGET_ALTIVEC_ABI)
24884 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24886 /* Align stack so vector save area is on a quadword boundary. */
24887 if (info->altivec_size != 0)
24888 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24890 info->altivec_save_offset = info->vrsave_save_offset
24891 - info->altivec_padding_size
24892 - info->altivec_size;
24894 /* Adjust for AltiVec case. */
24895 info->ehrd_offset = info->altivec_save_offset;
24898 info->ehrd_offset = info->cr_save_offset;
24900 info->ehrd_offset -= ehrd_size;
24901 info->lr_save_offset = reg_size;
24904 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24905 info->save_size = RS6000_ALIGN (info->fp_size
24907 + info->altivec_size
24908 + info->altivec_padding_size
24912 + info->vrsave_size,
24915 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24917 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24918 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24920 /* Determine if we need to save the link register. */
24922 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24924 && !TARGET_PROFILE_KERNEL)
24925 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24926 #ifdef TARGET_RELOCATABLE
24927 || (DEFAULT_ABI == ABI_V4
24928 && (TARGET_RELOCATABLE || flag_pic > 1)
24929 && !constant_pool_empty_p ())
24931 || rs6000_ra_ever_killed ())
24932 info->lr_save_p = 1;
24934 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24935 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24936 && call_used_regs[STATIC_CHAIN_REGNUM]);
24937 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24939 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24940 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24941 || !(info->savres_strategy & SAVE_INLINE_VRS)
24942 || !(info->savres_strategy & REST_INLINE_GPRS)
24943 || !(info->savres_strategy & REST_INLINE_FPRS)
24944 || !(info->savres_strategy & REST_INLINE_VRS))
24945 info->lr_save_p = 1;
24947 if (info->lr_save_p)
24948 df_set_regs_ever_live (LR_REGNO, true);
24950 /* Determine if we need to allocate any stack frame:
24952 For AIX we need to push the stack if a frame pointer is needed
24953 (because the stack might be dynamically adjusted), if we are
24954 debugging, if we make calls, or if the sum of fp_save, gp_save,
24955 and local variables are more than the space needed to save all
24956 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24957 + 18*8 = 288 (GPR13 reserved).
24959 For V.4 we don't have the stack cushion that AIX uses, but assume
24960 that the debugger can handle stackless frames. */
24965 else if (DEFAULT_ABI == ABI_V4)
24966 info->push_p = non_fixed_size != 0;
24968 else if (frame_pointer_needed)
24971 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24975 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24981 debug_stack_info (rs6000_stack_t *info)
24983 const char *abi_string;
24986 info = rs6000_stack_info ();
24988 fprintf (stderr, "\nStack information for function %s:\n",
24989 ((current_function_decl && DECL_NAME (current_function_decl))
24990 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24995 default: abi_string = "Unknown"; break;
24996 case ABI_NONE: abi_string = "NONE"; break;
24997 case ABI_AIX: abi_string = "AIX"; break;
24998 case ABI_ELFv2: abi_string = "ELFv2"; break;
24999 case ABI_DARWIN: abi_string = "Darwin"; break;
25000 case ABI_V4: abi_string = "V.4"; break;
25003 fprintf (stderr, "\tABI = %5s\n", abi_string);
25005 if (TARGET_ALTIVEC_ABI)
25006 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
25008 if (info->first_gp_reg_save != 32)
25009 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
25011 if (info->first_fp_reg_save != 64)
25012 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
25014 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
25015 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
25016 info->first_altivec_reg_save);
25018 if (info->lr_save_p)
25019 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
25021 if (info->cr_save_p)
25022 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
25024 if (info->vrsave_mask)
25025 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
25028 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
25031 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
25034 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
25037 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
25039 if (info->altivec_size)
25040 fprintf (stderr, "\taltivec_save_offset = %5d\n",
25041 info->altivec_save_offset);
25043 if (info->vrsave_size)
25044 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
25045 info->vrsave_save_offset);
25047 if (info->lr_save_p)
25048 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
25050 if (info->cr_save_p)
25051 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
25053 if (info->varargs_save_offset)
25054 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
25056 if (info->total_size)
25057 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25060 if (info->vars_size)
25061 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25064 if (info->parm_size)
25065 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
25067 if (info->fixed_size)
25068 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
25071 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
25074 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
25076 if (info->altivec_size)
25077 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
25079 if (info->vrsave_size)
25080 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
25082 if (info->altivec_padding_size)
25083 fprintf (stderr, "\taltivec_padding_size= %5d\n",
25084 info->altivec_padding_size);
25087 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
25089 if (info->save_size)
25090 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
25092 if (info->reg_size != 4)
25093 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
25095 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
25097 fprintf (stderr, "\n");
25101 rs6000_return_addr (int count, rtx frame)
25103 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
25104 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
25106 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
25108 cfun->machine->ra_needs_full_frame = 1;
25111 /* FRAME is set to frame_pointer_rtx by the generic code, but that
25112 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
25113 frame = stack_pointer_rtx;
25114 rtx prev_frame_addr = memory_address (Pmode, frame);
25115 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
25116 rtx lr_save_off = plus_constant (Pmode,
25117 prev_frame, RETURN_ADDRESS_OFFSET);
25118 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
25119 return gen_rtx_MEM (Pmode, lr_save_addr);
25122 cfun->machine->ra_need_lr = 1;
25123 return get_hard_reg_initial_val (Pmode, LR_REGNO);
25126 /* Say whether a function is a candidate for sibcall handling or not. */
25129 rs6000_function_ok_for_sibcall (tree decl, tree exp)
25134 fntype = TREE_TYPE (decl);
25136 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
25138 /* We can't do it if the called function has more vector parameters
25139 than the current function; there's nowhere to put the VRsave code. */
25140 if (TARGET_ALTIVEC_ABI
25141 && TARGET_ALTIVEC_VRSAVE
25142 && !(decl && decl == current_function_decl))
25144 function_args_iterator args_iter;
25148 /* Functions with vector parameters are required to have a
25149 prototype, so the argument type info must be available
25151 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
25152 if (TREE_CODE (type) == VECTOR_TYPE
25153 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25156 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
25157 if (TREE_CODE (type) == VECTOR_TYPE
25158 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25165 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
25166 functions, because the callee may have a different TOC pointer to
25167 the caller and there's no way to ensure we restore the TOC when
25168 we return. With the secure-plt SYSV ABI we can't make non-local
25169 calls when -fpic/PIC because the plt call stubs use r30. */
25170 if (DEFAULT_ABI == ABI_DARWIN
25171 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25173 && !DECL_EXTERNAL (decl)
25174 && !DECL_WEAK (decl)
25175 && (*targetm.binds_local_p) (decl))
25176 || (DEFAULT_ABI == ABI_V4
25177 && (!TARGET_SECURE_PLT
25180 && (*targetm.binds_local_p) (decl)))))
25182 tree attr_list = TYPE_ATTRIBUTES (fntype);
25184 if (!lookup_attribute ("longcall", attr_list)
25185 || lookup_attribute ("shortcall", attr_list))
25193 rs6000_ra_ever_killed (void)
25199 if (cfun->is_thunk)
25202 if (cfun->machine->lr_save_state)
25203 return cfun->machine->lr_save_state - 1;
25205 /* regs_ever_live has LR marked as used if any sibcalls are present,
25206 but this should not force saving and restoring in the
25207 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
25208 clobbers LR, so that is inappropriate. */
25210 /* Also, the prologue can generate a store into LR that
25211 doesn't really count, like this:
25214 bcl to set PIC register
25218 When we're called from the epilogue, we need to avoid counting
25219 this as a store. */
25221 push_topmost_sequence ();
25222 top = get_insns ();
25223 pop_topmost_sequence ();
25224 reg = gen_rtx_REG (Pmode, LR_REGNO);
25226 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
25232 if (!SIBLING_CALL_P (insn))
25235 else if (find_regno_note (insn, REG_INC, LR_REGNO))
25237 else if (set_of (reg, insn) != NULL_RTX
25238 && !prologue_epilogue_contains (insn))
25245 /* Emit instructions needed to load the TOC register.
25246 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
25247 a constant pool; or for SVR4 -fpic. */
25250 rs6000_emit_load_toc_table (int fromprolog)
25253 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
25255 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
25258 rtx lab, tmp1, tmp2, got;
25260 lab = gen_label_rtx ();
25261 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
25262 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25265 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25269 got = rs6000_got_sym ();
25270 tmp1 = tmp2 = dest;
25273 tmp1 = gen_reg_rtx (Pmode);
25274 tmp2 = gen_reg_rtx (Pmode);
25276 emit_insn (gen_load_toc_v4_PIC_1 (lab));
25277 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
25278 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
25279 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
25281 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
25283 emit_insn (gen_load_toc_v4_pic_si ());
25284 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25286 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
25289 rtx temp0 = (fromprolog
25290 ? gen_rtx_REG (Pmode, 0)
25291 : gen_reg_rtx (Pmode));
25297 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25298 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25300 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
25301 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25303 emit_insn (gen_load_toc_v4_PIC_1 (symF));
25304 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25305 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
25311 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25313 lab = gen_label_rtx ();
25314 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
25315 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25316 if (TARGET_LINK_STACK)
25317 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
25318 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
25320 emit_insn (gen_addsi3 (dest, temp0, dest));
25322 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
25324 /* This is for AIX code running in non-PIC ELF32. */
25325 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25328 emit_insn (gen_elf_high (dest, realsym));
25329 emit_insn (gen_elf_low (dest, dest, realsym));
25333 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
25336 emit_insn (gen_load_toc_aix_si (dest));
25338 emit_insn (gen_load_toc_aix_di (dest));
25342 /* Emit instructions to restore the link register after determining where
25343 its value has been stored. */
25346 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
25348 rs6000_stack_t *info = rs6000_stack_info ();
25351 operands[0] = source;
25352 operands[1] = scratch;
25354 if (info->lr_save_p)
25356 rtx frame_rtx = stack_pointer_rtx;
25357 HOST_WIDE_INT sp_offset = 0;
25360 if (frame_pointer_needed
25361 || cfun->calls_alloca
25362 || info->total_size > 32767)
25364 tmp = gen_frame_mem (Pmode, frame_rtx);
25365 emit_move_insn (operands[1], tmp);
25366 frame_rtx = operands[1];
25368 else if (info->push_p)
25369 sp_offset = info->total_size;
25371 tmp = plus_constant (Pmode, frame_rtx,
25372 info->lr_save_offset + sp_offset);
25373 tmp = gen_frame_mem (Pmode, tmp);
25374 emit_move_insn (tmp, operands[0]);
25377 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
25379 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25380 state of lr_save_p so any change from here on would be a bug. In
25381 particular, stop rs6000_ra_ever_killed from considering the SET
25382 of lr we may have added just above. */
25383 cfun->machine->lr_save_state = info->lr_save_p + 1;
25386 static GTY(()) alias_set_type set = -1;
25389 get_TOC_alias_set (void)
25392 set = new_alias_set ();
25396 /* This returns nonzero if the current function uses the TOC. This is
25397 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25398 is generated by the ABI_V4 load_toc_* patterns.
25399 Return 2 instead of 1 if the load_toc_* pattern is in the function
25400 partition that doesn't start the function. */
25408 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
25412 rtx pat = PATTERN (insn);
25415 if (GET_CODE (pat) == PARALLEL)
25416 for (i = 0; i < XVECLEN (pat, 0); i++)
25418 rtx sub = XVECEXP (pat, 0, i);
25419 if (GET_CODE (sub) == USE)
25421 sub = XEXP (sub, 0);
25422 if (GET_CODE (sub) == UNSPEC
25423 && XINT (sub, 1) == UNSPEC_TOC)
25428 else if (crtl->has_bb_partition
25430 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25438 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25440 rtx tocrel, tocreg, hi;
25442 if (TARGET_DEBUG_ADDR)
25444 if (GET_CODE (symbol) == SYMBOL_REF)
25445 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25449 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25450 GET_RTX_NAME (GET_CODE (symbol)));
25451 debug_rtx (symbol);
25455 if (!can_create_pseudo_p ())
25456 df_set_regs_ever_live (TOC_REGISTER, true);
25458 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25459 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25460 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25463 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25464 if (largetoc_reg != NULL)
25466 emit_move_insn (largetoc_reg, hi);
25469 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25472 /* Issue assembly directives that create a reference to the given DWARF
25473 FRAME_TABLE_LABEL from the current function section. */
25475 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25477 fprintf (asm_out_file, "\t.ref %s\n",
25478 (* targetm.strip_name_encoding) (frame_table_label));
25481 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25482 and the change to the stack pointer. */
25485 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25492 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25493 if (hard_frame_needed)
25494 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25495 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25496 || (hard_frame_needed
25497 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25500 p = rtvec_alloc (i);
25503 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25504 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25507 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25510 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25511 and set the appropriate attributes for the generated insn. Return the
25512 first insn which adjusts the stack pointer or the last insn before
25513 the stack adjustment loop.
25515 SIZE_INT is used to create the CFI note for the allocation.
25517 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25518 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25520 ORIG_SP contains the backchain value that must be stored at *sp. */
25523 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25527 rtx size_rtx = GEN_INT (-size_int);
25528 if (size_int > 32767)
25530 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25531 /* Need a note here so that try_split doesn't get confused. */
25532 if (get_last_insn () == NULL_RTX)
25533 emit_note (NOTE_INSN_DELETED);
25534 insn = emit_move_insn (tmp_reg, size_rtx);
25535 try_split (PATTERN (insn), insn, 0);
25536 size_rtx = tmp_reg;
25539 if (Pmode == SImode)
25540 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25545 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
25549 rtx par = PATTERN (insn);
25550 gcc_assert (GET_CODE (par) == PARALLEL);
25551 rtx set = XVECEXP (par, 0, 0);
25552 gcc_assert (GET_CODE (set) == SET);
25553 rtx mem = SET_DEST (set);
25554 gcc_assert (MEM_P (mem));
25555 MEM_NOTRAP_P (mem) = 1;
25556 set_mem_alias_set (mem, get_frame_alias_set ());
25558 RTX_FRAME_RELATED_P (insn) = 1;
25559 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25560 gen_rtx_SET (stack_pointer_rtx,
25561 gen_rtx_PLUS (Pmode,
25563 GEN_INT (-size_int))));
25565 /* Emit a blockage to ensure the allocation/probing insns are
25566 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25567 note for similar reasons. */
25568 if (flag_stack_clash_protection)
25570 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25571 emit_insn (gen_blockage ());
25577 static HOST_WIDE_INT
25578 get_stack_clash_protection_probe_interval (void)
25580 return (HOST_WIDE_INT_1U
25581 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25584 static HOST_WIDE_INT
25585 get_stack_clash_protection_guard_size (void)
25587 return (HOST_WIDE_INT_1U
25588 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25591 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25592 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25594 COPY_REG, if non-null, should contain a copy of the original
25595 stack pointer at exit from this function.
25597 This is subtly different than the Ada probing in that it tries hard to
25598 prevent attacks that jump the stack guard. Thus it is never allowed to
25599 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25600 space without a suitable probe. */
25602 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25605 rtx orig_sp = copy_reg;
25607 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25609 /* Round the size down to a multiple of PROBE_INTERVAL. */
25610 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25612 /* If explicitly requested,
25613 or the rounded size is not the same as the original size
25614 or the the rounded size is greater than a page,
25615 then we will need a copy of the original stack pointer. */
25616 if (rounded_size != orig_size
25617 || rounded_size > probe_interval
25620 /* If the caller did not request a copy of the incoming stack
25621 pointer, then we use r0 to hold the copy. */
25623 orig_sp = gen_rtx_REG (Pmode, 0);
25624 emit_move_insn (orig_sp, stack_pointer_rtx);
25627 /* There's three cases here.
25629 One is a single probe which is the most common and most efficiently
25630 implemented as it does not have to have a copy of the original
25631 stack pointer if there are no residuals.
25633 Second is unrolled allocation/probes which we use if there's just
25634 a few of them. It needs to save the original stack pointer into a
25635 temporary for use as a source register in the allocation/probe.
25637 Last is a loop. This is the most uncommon case and least efficient. */
25638 rtx_insn *retval = NULL;
25639 if (rounded_size == probe_interval)
25641 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25643 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25645 else if (rounded_size <= 8 * probe_interval)
25647 /* The ABI requires using the store with update insns to allocate
25648 space and store the backchain into the stack
25650 So we save the current stack pointer into a temporary, then
25651 emit the store-with-update insns to store the saved stack pointer
25652 into the right location in each new page. */
25653 for (int i = 0; i < rounded_size; i += probe_interval)
25656 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25658 /* Save the first stack adjustment in RETVAL. */
25663 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25667 /* Compute the ending address. */
25669 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25670 rtx rs = GEN_INT (-rounded_size);
25672 if (add_operand (rs, Pmode))
25673 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25676 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25677 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25678 stack_pointer_rtx));
25679 /* Describe the effect of INSN to the CFI engine. */
25680 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25681 gen_rtx_SET (end_addr,
25682 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25685 RTX_FRAME_RELATED_P (insn) = 1;
25687 /* Emit the loop. */
25689 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25690 stack_pointer_rtx, orig_sp,
25693 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25694 stack_pointer_rtx, orig_sp,
25696 RTX_FRAME_RELATED_P (retval) = 1;
25697 /* Describe the effect of INSN to the CFI engine. */
25698 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25699 gen_rtx_SET (stack_pointer_rtx, end_addr));
25701 /* Emit a blockage to ensure the allocation/probing insns are
25702 not optimized, combined, removed, etc. Other cases handle this
25703 within their call to rs6000_emit_allocate_stack_1. */
25704 emit_insn (gen_blockage ());
25706 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25709 if (orig_size != rounded_size)
25711 /* Allocate (and implicitly probe) any residual space. */
25712 HOST_WIDE_INT residual = orig_size - rounded_size;
25714 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25716 /* If the residual was the only allocation, then we can return the
25717 allocating insn. */
25725 /* Emit the correct code for allocating stack space, as insns.
25726 If COPY_REG, make sure a copy of the old frame is left there.
25727 The generated code may use hard register 0 as a temporary. */
25730 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25733 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25734 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25735 rtx todec = gen_int_mode (-size, Pmode);
25737 if (INTVAL (todec) != -size)
25739 warning (0, "stack frame too large");
25740 emit_insn (gen_trap ());
25744 if (crtl->limit_stack)
25746 if (REG_P (stack_limit_rtx)
25747 && REGNO (stack_limit_rtx) > 1
25748 && REGNO (stack_limit_rtx) <= 31)
25751 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25754 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25756 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25758 && DEFAULT_ABI == ABI_V4
25761 rtx toload = gen_rtx_CONST (VOIDmode,
25762 gen_rtx_PLUS (Pmode,
25766 emit_insn (gen_elf_high (tmp_reg, toload));
25767 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25768 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25772 warning (0, "stack limit expression is not supported");
25775 if (flag_stack_clash_protection)
25777 if (size < get_stack_clash_protection_guard_size ())
25778 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25781 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25784 /* If we asked for a copy with an offset, then we still need add in
25786 if (copy_reg && copy_off)
25787 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25795 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25797 emit_move_insn (copy_reg, stack_reg);
25800 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25801 it now and set the alias set/attributes. The above gen_*_update
25802 calls will generate a PARALLEL with the MEM set being the first
25804 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25808 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25810 #if PROBE_INTERVAL > 32768
25811 #error Cannot use indexed addressing mode for stack probing
25814 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25815 inclusive. These are offsets from the current stack pointer. */
25818 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25820 /* See if we have a constant small number of probes to generate. If so,
25821 that's the easy case. */
25822 if (first + size <= 32768)
25826 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25827 it exceeds SIZE. If only one probe is needed, this will not
25828 generate any code. Then probe at FIRST + SIZE. */
25829 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25830 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25833 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25837 /* Otherwise, do the same as above, but in a loop. Note that we must be
25838 extra careful with variables wrapping around because we might be at
25839 the very top (or the very bottom) of the address space and we have
25840 to be able to handle this case properly; in particular, we use an
25841 equality test for the loop condition. */
25844 HOST_WIDE_INT rounded_size;
25845 rtx r12 = gen_rtx_REG (Pmode, 12);
25846 rtx r0 = gen_rtx_REG (Pmode, 0);
25848 /* Sanity check for the addressing mode we're going to use. */
25849 gcc_assert (first <= 32768);
25851 /* Step 1: round SIZE to the previous multiple of the interval. */
25853 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25856 /* Step 2: compute initial and final value of the loop counter. */
25858 /* TEST_ADDR = SP + FIRST. */
25859 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25862 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25863 if (rounded_size > 32768)
25865 emit_move_insn (r0, GEN_INT (-rounded_size));
25866 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25869 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25873 /* Step 3: the loop
25877 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25880 while (TEST_ADDR != LAST_ADDR)
25882 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25883 until it is equal to ROUNDED_SIZE. */
25886 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25888 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25891 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25892 that SIZE is equal to ROUNDED_SIZE. */
25894 if (size != rounded_size)
25895 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25899 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25900 addresses, not offsets. */
25902 static const char *
25903 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25905 static int labelno = 0;
25909 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25912 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25914 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25916 xops[1] = GEN_INT (-PROBE_INTERVAL);
25917 output_asm_insn ("addi %0,%0,%1", xops);
25919 /* Probe at TEST_ADDR. */
25920 xops[1] = gen_rtx_REG (Pmode, 0);
25921 output_asm_insn ("stw %1,0(%0)", xops);
25923 /* Test if TEST_ADDR == LAST_ADDR. */
25926 output_asm_insn ("cmpd 0,%0,%1", xops);
25928 output_asm_insn ("cmpw 0,%0,%1", xops);
25931 fputs ("\tbne 0,", asm_out_file);
25932 assemble_name_raw (asm_out_file, loop_lab);
25933 fputc ('\n', asm_out_file);
25938 /* This function is called when rs6000_frame_related is processing
25939 SETs within a PARALLEL, and returns whether the REGNO save ought to
25940 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25941 for out-of-line register save functions, store multiple, and the
25942 Darwin world_save. They may contain registers that don't really
25946 interesting_frame_related_regno (unsigned int regno)
25948 /* Saves apparently of r0 are actually saving LR. It doesn't make
25949 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25950 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25951 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25952 as frame related. */
25955 /* If we see CR2 then we are here on a Darwin world save. Saves of
25956 CR2 signify the whole CR is being saved. This is a long-standing
25957 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25958 that CR needs to be saved. */
25959 if (regno == CR2_REGNO)
25961 /* Omit frame info for any user-defined global regs. If frame info
25962 is supplied for them, frame unwinding will restore a user reg.
25963 Also omit frame info for any reg we don't need to save, as that
25964 bloats frame info and can cause problems with shrink wrapping.
25965 Since global regs won't be seen as needing to be saved, both of
25966 these conditions are covered by save_reg_p. */
25967 return save_reg_p (regno);
25970 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25971 addresses, not offsets.
25973 REG2 contains the backchain that must be stored into *sp at each allocation.
25975 This is subtly different than the Ada probing above in that it tries hard
25976 to prevent attacks that jump the stack guard. Thus, it is never allowed
25977 to allocate more than PROBE_INTERVAL bytes of stack space without a
25980 static const char *
25981 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25983 static int labelno = 0;
25987 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25989 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25991 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25993 /* This allocates and probes. */
25996 xops[2] = GEN_INT (-probe_interval);
25998 output_asm_insn ("stdu %1,%2(%0)", xops);
26000 output_asm_insn ("stwu %1,%2(%0)", xops);
26002 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
26006 output_asm_insn ("cmpd 0,%0,%1", xops);
26008 output_asm_insn ("cmpw 0,%0,%1", xops);
26010 fputs ("\tbne 0,", asm_out_file);
26011 assemble_name_raw (asm_out_file, loop_lab);
26012 fputc ('\n', asm_out_file);
26017 /* Wrapper around the output_probe_stack_range routines. */
26019 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
26021 if (flag_stack_clash_protection)
26022 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
26024 return output_probe_stack_range_1 (reg1, reg3);
26027 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
26028 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
26029 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
26030 deduce these equivalences by itself so it wasn't necessary to hold
26031 its hand so much. Don't be tempted to always supply d2_f_d_e with
26032 the actual cfa register, ie. r31 when we are using a hard frame
26033 pointer. That fails when saving regs off r1, and sched moves the
26034 r31 setup past the reg saves. */
26037 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
26038 rtx reg2, rtx repl2)
26042 if (REGNO (reg) == STACK_POINTER_REGNUM)
26044 gcc_checking_assert (val == 0);
26048 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
26051 rtx pat = PATTERN (insn);
26052 if (!repl && !reg2)
26054 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
26055 if (GET_CODE (pat) == PARALLEL)
26056 for (int i = 0; i < XVECLEN (pat, 0); i++)
26057 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26059 rtx set = XVECEXP (pat, 0, i);
26061 if (!REG_P (SET_SRC (set))
26062 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26063 RTX_FRAME_RELATED_P (set) = 1;
26065 RTX_FRAME_RELATED_P (insn) = 1;
26069 /* We expect that 'pat' is either a SET or a PARALLEL containing
26070 SETs (and possibly other stuff). In a PARALLEL, all the SETs
26071 are important so they all have to be marked RTX_FRAME_RELATED_P.
26072 Call simplify_replace_rtx on the SETs rather than the whole insn
26073 so as to leave the other stuff alone (for example USE of r12). */
26075 set_used_flags (pat);
26076 if (GET_CODE (pat) == SET)
26079 pat = simplify_replace_rtx (pat, reg, repl);
26081 pat = simplify_replace_rtx (pat, reg2, repl2);
26083 else if (GET_CODE (pat) == PARALLEL)
26085 pat = shallow_copy_rtx (pat);
26086 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
26088 for (int i = 0; i < XVECLEN (pat, 0); i++)
26089 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26091 rtx set = XVECEXP (pat, 0, i);
26094 set = simplify_replace_rtx (set, reg, repl);
26096 set = simplify_replace_rtx (set, reg2, repl2);
26097 XVECEXP (pat, 0, i) = set;
26099 if (!REG_P (SET_SRC (set))
26100 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26101 RTX_FRAME_RELATED_P (set) = 1;
26105 gcc_unreachable ();
26107 RTX_FRAME_RELATED_P (insn) = 1;
26108 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
26113 /* Returns an insn that has a vrsave set operation with the
26114 appropriate CLOBBERs. */
26117 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
26120 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
26121 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26124 = gen_rtx_SET (vrsave,
26125 gen_rtx_UNSPEC_VOLATILE (SImode,
26126 gen_rtvec (2, reg, vrsave),
26127 UNSPECV_SET_VRSAVE));
26131 /* We need to clobber the registers in the mask so the scheduler
26132 does not move sets to VRSAVE before sets of AltiVec registers.
26134 However, if the function receives nonlocal gotos, reload will set
26135 all call saved registers live. We will end up with:
26137 (set (reg 999) (mem))
26138 (parallel [ (set (reg vrsave) (unspec blah))
26139 (clobber (reg 999))])
26141 The clobber will cause the store into reg 999 to be dead, and
26142 flow will attempt to delete an epilogue insn. In this case, we
26143 need an unspec use/set of the register. */
26145 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
26146 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
26148 if (!epiloguep || call_used_regs [i])
26149 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
26150 gen_rtx_REG (V4SImode, i));
26153 rtx reg = gen_rtx_REG (V4SImode, i);
26156 = gen_rtx_SET (reg,
26157 gen_rtx_UNSPEC (V4SImode,
26158 gen_rtvec (1, reg), 27));
26162 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
26164 for (i = 0; i < nclobs; ++i)
26165 XVECEXP (insn, 0, i) = clobs[i];
26171 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
26175 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
26176 mem = gen_frame_mem (GET_MODE (reg), addr);
26177 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
26181 gen_frame_load (rtx reg, rtx frame_reg, int offset)
26183 return gen_frame_set (reg, frame_reg, offset, false);
26187 gen_frame_store (rtx reg, rtx frame_reg, int offset)
26189 return gen_frame_set (reg, frame_reg, offset, true);
26192 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
26193 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
26196 emit_frame_save (rtx frame_reg, machine_mode mode,
26197 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
26201 /* Some cases that need register indexed addressing. */
26202 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
26203 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
26205 reg = gen_rtx_REG (mode, regno);
26206 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
26207 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
26208 NULL_RTX, NULL_RTX);
26211 /* Emit an offset memory reference suitable for a frame store, while
26212 converting to a valid addressing mode. */
26215 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
26217 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
26220 #ifndef TARGET_FIX_AND_CONTINUE
26221 #define TARGET_FIX_AND_CONTINUE 0
26224 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
26225 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
26226 #define LAST_SAVRES_REGISTER 31
26227 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
26238 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
26240 /* Temporary holding space for an out-of-line register save/restore
26242 static char savres_routine_name[30];
26244 /* Return the name for an out-of-line register save/restore routine.
26245 We are saving/restoring GPRs if GPR is true. */
26248 rs6000_savres_routine_name (int regno, int sel)
26250 const char *prefix = "";
26251 const char *suffix = "";
26253 /* Different targets are supposed to define
26254 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
26255 routine name could be defined with:
26257 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
26259 This is a nice idea in practice, but in reality, things are
26260 complicated in several ways:
26262 - ELF targets have save/restore routines for GPRs.
26264 - PPC64 ELF targets have routines for save/restore of GPRs that
26265 differ in what they do with the link register, so having a set
26266 prefix doesn't work. (We only use one of the save routines at
26267 the moment, though.)
26269 - PPC32 elf targets have "exit" versions of the restore routines
26270 that restore the link register and can save some extra space.
26271 These require an extra suffix. (There are also "tail" versions
26272 of the restore routines and "GOT" versions of the save routines,
26273 but we don't generate those at present. Same problems apply,
26276 We deal with all this by synthesizing our own prefix/suffix and
26277 using that for the simple sprintf call shown above. */
26278 if (DEFAULT_ABI == ABI_V4)
26283 if ((sel & SAVRES_REG) == SAVRES_GPR)
26284 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
26285 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26286 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
26287 else if ((sel & SAVRES_REG) == SAVRES_VR)
26288 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26292 if ((sel & SAVRES_LR))
26295 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26297 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
26298 /* No out-of-line save/restore routines for GPRs on AIX. */
26299 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
26303 if ((sel & SAVRES_REG) == SAVRES_GPR)
26304 prefix = ((sel & SAVRES_SAVE)
26305 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
26306 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
26307 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26309 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26310 if ((sel & SAVRES_LR))
26311 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
26315 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
26316 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
26319 else if ((sel & SAVRES_REG) == SAVRES_VR)
26320 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26325 if (DEFAULT_ABI == ABI_DARWIN)
26327 /* The Darwin approach is (slightly) different, in order to be
26328 compatible with code generated by the system toolchain. There is a
26329 single symbol for the start of save sequence, and the code here
26330 embeds an offset into that code on the basis of the first register
26332 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
26333 if ((sel & SAVRES_REG) == SAVRES_GPR)
26334 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
26335 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
26336 (regno - 13) * 4, prefix, regno);
26337 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26338 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
26339 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
26340 else if ((sel & SAVRES_REG) == SAVRES_VR)
26341 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
26342 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
26347 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
26349 return savres_routine_name;
26352 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26353 We are saving/restoring GPRs if GPR is true. */
26356 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
26358 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
26359 ? info->first_gp_reg_save
26360 : (sel & SAVRES_REG) == SAVRES_FPR
26361 ? info->first_fp_reg_save - 32
26362 : (sel & SAVRES_REG) == SAVRES_VR
26363 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
26368 /* Don't generate bogus routine names. */
26369 gcc_assert (FIRST_SAVRES_REGISTER <= regno
26370 && regno <= LAST_SAVRES_REGISTER
26371 && select >= 0 && select <= 12);
26373 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
26379 name = rs6000_savres_routine_name (regno, sel);
26381 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
26382 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
26383 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
26389 /* Emit a sequence of insns, including a stack tie if needed, for
26390 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26391 reset the stack pointer, but move the base of the frame into
26392 reg UPDT_REGNO for use by out-of-line register restore routines. */
26395 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
26396 unsigned updt_regno)
26398 /* If there is nothing to do, don't do anything. */
26399 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
26402 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
26404 /* This blockage is needed so that sched doesn't decide to move
26405 the sp change before the register restores. */
26406 if (DEFAULT_ABI == ABI_V4)
26407 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
26408 GEN_INT (frame_off)));
26410 /* If we are restoring registers out-of-line, we will be using the
26411 "exit" variants of the restore routines, which will reset the
26412 stack for us. But we do need to point updt_reg into the
26413 right place for those routines. */
26414 if (frame_off != 0)
26415 return emit_insn (gen_add3_insn (updt_reg_rtx,
26416 frame_reg_rtx, GEN_INT (frame_off)));
26418 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26423 /* Return the register number used as a pointer by out-of-line
26424 save/restore functions. */
26426 static inline unsigned
26427 ptr_regno_for_savres (int sel)
26429 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26430 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26431 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26434 /* Construct a parallel rtx describing the effect of a call to an
26435 out-of-line register save/restore routine, and emit the insn
26436 or jump_insn as appropriate. */
26439 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26440 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26441 machine_mode reg_mode, int sel)
26444 int offset, start_reg, end_reg, n_regs, use_reg;
26445 int reg_size = GET_MODE_SIZE (reg_mode);
26452 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26453 ? info->first_gp_reg_save
26454 : (sel & SAVRES_REG) == SAVRES_FPR
26455 ? info->first_fp_reg_save
26456 : (sel & SAVRES_REG) == SAVRES_VR
26457 ? info->first_altivec_reg_save
26459 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26461 : (sel & SAVRES_REG) == SAVRES_FPR
26463 : (sel & SAVRES_REG) == SAVRES_VR
26464 ? LAST_ALTIVEC_REGNO + 1
26466 n_regs = end_reg - start_reg;
26467 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26468 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26471 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26472 RTVEC_ELT (p, offset++) = ret_rtx;
26474 RTVEC_ELT (p, offset++)
26475 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
26477 sym = rs6000_savres_routine_sym (info, sel);
26478 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26480 use_reg = ptr_regno_for_savres (sel);
26481 if ((sel & SAVRES_REG) == SAVRES_VR)
26483 /* Vector regs are saved/restored using [reg+reg] addressing. */
26484 RTVEC_ELT (p, offset++)
26485 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26486 RTVEC_ELT (p, offset++)
26487 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26490 RTVEC_ELT (p, offset++)
26491 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26493 for (i = 0; i < end_reg - start_reg; i++)
26494 RTVEC_ELT (p, i + offset)
26495 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26496 frame_reg_rtx, save_area_offset + reg_size * i,
26497 (sel & SAVRES_SAVE) != 0);
26499 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26500 RTVEC_ELT (p, i + offset)
26501 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26503 par = gen_rtx_PARALLEL (VOIDmode, p);
26505 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26507 insn = emit_jump_insn (par);
26508 JUMP_LABEL (insn) = ret_rtx;
26511 insn = emit_insn (par);
26515 /* Emit prologue code to store CR fields that need to be saved into REG. This
26516 function should only be called when moving the non-volatile CRs to REG, it
26517 is not a general purpose routine to move the entire set of CRs to REG.
26518 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26522 rs6000_emit_prologue_move_from_cr (rtx reg)
26524 /* Only the ELFv2 ABI allows storing only selected fields. */
26525 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26527 int i, cr_reg[8], count = 0;
26529 /* Collect CR fields that must be saved. */
26530 for (i = 0; i < 8; i++)
26531 if (save_reg_p (CR0_REGNO + i))
26532 cr_reg[count++] = i;
26534 /* If it's just a single one, use mfcrf. */
26537 rtvec p = rtvec_alloc (1);
26538 rtvec r = rtvec_alloc (2);
26539 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26540 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26542 = gen_rtx_SET (reg,
26543 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26545 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26549 /* ??? It might be better to handle count == 2 / 3 cases here
26550 as well, using logical operations to combine the values. */
26553 emit_insn (gen_prologue_movesi_from_cr (reg));
26556 /* Return whether the split-stack arg pointer (r12) is used. */
26559 split_stack_arg_pointer_used_p (void)
26561 /* If the pseudo holding the arg pointer is no longer a pseudo,
26562 then the arg pointer is used. */
26563 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26564 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26565 || (REGNO (cfun->machine->split_stack_arg_pointer)
26566 < FIRST_PSEUDO_REGISTER)))
26569 /* Unfortunately we also need to do some code scanning, since
26570 r12 may have been substituted for the pseudo. */
26572 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26573 FOR_BB_INSNS (bb, insn)
26574 if (NONDEBUG_INSN_P (insn))
26576 /* A call destroys r12. */
26581 FOR_EACH_INSN_USE (use, insn)
26583 rtx x = DF_REF_REG (use);
26584 if (REG_P (x) && REGNO (x) == 12)
26588 FOR_EACH_INSN_DEF (def, insn)
26590 rtx x = DF_REF_REG (def);
26591 if (REG_P (x) && REGNO (x) == 12)
26595 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26598 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26601 rs6000_global_entry_point_needed_p (void)
26603 /* Only needed for the ELFv2 ABI. */
26604 if (DEFAULT_ABI != ABI_ELFv2)
26607 /* With -msingle-pic-base, we assume the whole program shares the same
26608 TOC, so no global entry point prologues are needed anywhere. */
26609 if (TARGET_SINGLE_PIC_BASE)
26612 /* Ensure we have a global entry point for thunks. ??? We could
26613 avoid that if the target routine doesn't need a global entry point,
26614 but we do not know whether this is the case at this point. */
26615 if (cfun->is_thunk)
26618 /* For regular functions, rs6000_emit_prologue sets this flag if the
26619 routine ever uses the TOC pointer. */
26620 return cfun->machine->r2_setup_needed;
26623 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26625 rs6000_get_separate_components (void)
26627 rs6000_stack_t *info = rs6000_stack_info ();
26629 if (WORLD_SAVE_P (info))
26632 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26633 && !(info->savres_strategy & REST_MULTIPLE));
26635 /* Component 0 is the save/restore of LR (done via GPR0).
26636 Component 2 is the save of the TOC (GPR2).
26637 Components 13..31 are the save/restore of GPR13..GPR31.
26638 Components 46..63 are the save/restore of FPR14..FPR31. */
26640 cfun->machine->n_components = 64;
26642 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26643 bitmap_clear (components);
26645 int reg_size = TARGET_32BIT ? 4 : 8;
26646 int fp_reg_size = 8;
26648 /* The GPRs we need saved to the frame. */
26649 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26650 && (info->savres_strategy & REST_INLINE_GPRS))
26652 int offset = info->gp_save_offset;
26654 offset += info->total_size;
26656 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26658 if (IN_RANGE (offset, -0x8000, 0x7fff)
26659 && save_reg_p (regno))
26660 bitmap_set_bit (components, regno);
26662 offset += reg_size;
26666 /* Don't mess with the hard frame pointer. */
26667 if (frame_pointer_needed)
26668 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26670 /* Don't mess with the fixed TOC register. */
26671 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26672 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26673 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26674 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26676 /* The FPRs we need saved to the frame. */
26677 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26678 && (info->savres_strategy & REST_INLINE_FPRS))
26680 int offset = info->fp_save_offset;
26682 offset += info->total_size;
26684 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26686 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26687 bitmap_set_bit (components, regno);
26689 offset += fp_reg_size;
26693 /* Optimize LR save and restore if we can. This is component 0. Any
26694 out-of-line register save/restore routines need LR. */
26695 if (info->lr_save_p
26696 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26697 && (info->savres_strategy & SAVE_INLINE_GPRS)
26698 && (info->savres_strategy & REST_INLINE_GPRS)
26699 && (info->savres_strategy & SAVE_INLINE_FPRS)
26700 && (info->savres_strategy & REST_INLINE_FPRS)
26701 && (info->savres_strategy & SAVE_INLINE_VRS)
26702 && (info->savres_strategy & REST_INLINE_VRS))
26704 int offset = info->lr_save_offset;
26706 offset += info->total_size;
26707 if (IN_RANGE (offset, -0x8000, 0x7fff))
26708 bitmap_set_bit (components, 0);
26711 /* Optimize saving the TOC. This is component 2. */
26712 if (cfun->machine->save_toc_in_prologue)
26713 bitmap_set_bit (components, 2);
26718 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26720 rs6000_components_for_bb (basic_block bb)
26722 rs6000_stack_t *info = rs6000_stack_info ();
26724 bitmap in = DF_LIVE_IN (bb);
26725 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26726 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26728 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26729 bitmap_clear (components);
26731 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26734 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26735 if (bitmap_bit_p (in, regno)
26736 || bitmap_bit_p (gen, regno)
26737 || bitmap_bit_p (kill, regno))
26738 bitmap_set_bit (components, regno);
26741 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26742 if (bitmap_bit_p (in, regno)
26743 || bitmap_bit_p (gen, regno)
26744 || bitmap_bit_p (kill, regno))
26745 bitmap_set_bit (components, regno);
26747 /* The link register. */
26748 if (bitmap_bit_p (in, LR_REGNO)
26749 || bitmap_bit_p (gen, LR_REGNO)
26750 || bitmap_bit_p (kill, LR_REGNO))
26751 bitmap_set_bit (components, 0);
26753 /* The TOC save. */
26754 if (bitmap_bit_p (in, TOC_REGNUM)
26755 || bitmap_bit_p (gen, TOC_REGNUM)
26756 || bitmap_bit_p (kill, TOC_REGNUM))
26757 bitmap_set_bit (components, 2);
26762 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26764 rs6000_disqualify_components (sbitmap components, edge e,
26765 sbitmap edge_components, bool /*is_prologue*/)
26767 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26768 live where we want to place that code. */
26769 if (bitmap_bit_p (edge_components, 0)
26770 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26773 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26774 "on entry to bb %d\n", e->dest->index);
26775 bitmap_clear_bit (components, 0);
26779 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26781 rs6000_emit_prologue_components (sbitmap components)
26783 rs6000_stack_t *info = rs6000_stack_info ();
26784 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26785 ? HARD_FRAME_POINTER_REGNUM
26786 : STACK_POINTER_REGNUM);
26788 machine_mode reg_mode = Pmode;
26789 int reg_size = TARGET_32BIT ? 4 : 8;
26790 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26792 int fp_reg_size = 8;
26794 /* Prologue for LR. */
26795 if (bitmap_bit_p (components, 0))
26797 rtx reg = gen_rtx_REG (reg_mode, 0);
26798 rtx_insn *insn = emit_move_insn (reg, gen_rtx_REG (reg_mode, LR_REGNO));
26799 RTX_FRAME_RELATED_P (insn) = 1;
26800 add_reg_note (insn, REG_CFA_REGISTER, NULL);
26802 int offset = info->lr_save_offset;
26804 offset += info->total_size;
26806 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26807 RTX_FRAME_RELATED_P (insn) = 1;
26808 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26809 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26810 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26813 /* Prologue for TOC. */
26814 if (bitmap_bit_p (components, 2))
26816 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26817 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26818 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26821 /* Prologue for the GPRs. */
26822 int offset = info->gp_save_offset;
26824 offset += info->total_size;
26826 for (int i = info->first_gp_reg_save; i < 32; i++)
26828 if (bitmap_bit_p (components, i))
26830 rtx reg = gen_rtx_REG (reg_mode, i);
26831 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26832 RTX_FRAME_RELATED_P (insn) = 1;
26833 rtx set = copy_rtx (single_set (insn));
26834 add_reg_note (insn, REG_CFA_OFFSET, set);
26837 offset += reg_size;
26840 /* Prologue for the FPRs. */
26841 offset = info->fp_save_offset;
26843 offset += info->total_size;
26845 for (int i = info->first_fp_reg_save; i < 64; i++)
26847 if (bitmap_bit_p (components, i))
26849 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26850 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26851 RTX_FRAME_RELATED_P (insn) = 1;
26852 rtx set = copy_rtx (single_set (insn));
26853 add_reg_note (insn, REG_CFA_OFFSET, set);
26856 offset += fp_reg_size;
26860 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26862 rs6000_emit_epilogue_components (sbitmap components)
26864 rs6000_stack_t *info = rs6000_stack_info ();
26865 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26866 ? HARD_FRAME_POINTER_REGNUM
26867 : STACK_POINTER_REGNUM);
26869 machine_mode reg_mode = Pmode;
26870 int reg_size = TARGET_32BIT ? 4 : 8;
26872 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26874 int fp_reg_size = 8;
26876 /* Epilogue for the FPRs. */
26877 int offset = info->fp_save_offset;
26879 offset += info->total_size;
26881 for (int i = info->first_fp_reg_save; i < 64; i++)
26883 if (bitmap_bit_p (components, i))
26885 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26886 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26887 RTX_FRAME_RELATED_P (insn) = 1;
26888 add_reg_note (insn, REG_CFA_RESTORE, reg);
26891 offset += fp_reg_size;
26894 /* Epilogue for the GPRs. */
26895 offset = info->gp_save_offset;
26897 offset += info->total_size;
26899 for (int i = info->first_gp_reg_save; i < 32; i++)
26901 if (bitmap_bit_p (components, i))
26903 rtx reg = gen_rtx_REG (reg_mode, i);
26904 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26905 RTX_FRAME_RELATED_P (insn) = 1;
26906 add_reg_note (insn, REG_CFA_RESTORE, reg);
26909 offset += reg_size;
26912 /* Epilogue for LR. */
26913 if (bitmap_bit_p (components, 0))
26915 int offset = info->lr_save_offset;
26917 offset += info->total_size;
26919 rtx reg = gen_rtx_REG (reg_mode, 0);
26920 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26922 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26923 insn = emit_move_insn (lr, reg);
26924 RTX_FRAME_RELATED_P (insn) = 1;
26925 add_reg_note (insn, REG_CFA_RESTORE, lr);
26929 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26931 rs6000_set_handled_components (sbitmap components)
26933 rs6000_stack_t *info = rs6000_stack_info ();
26935 for (int i = info->first_gp_reg_save; i < 32; i++)
26936 if (bitmap_bit_p (components, i))
26937 cfun->machine->gpr_is_wrapped_separately[i] = true;
26939 for (int i = info->first_fp_reg_save; i < 64; i++)
26940 if (bitmap_bit_p (components, i))
26941 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26943 if (bitmap_bit_p (components, 0))
26944 cfun->machine->lr_is_wrapped_separately = true;
26946 if (bitmap_bit_p (components, 2))
26947 cfun->machine->toc_is_wrapped_separately = true;
26950 /* VRSAVE is a bit vector representing which AltiVec registers
26951 are used. The OS uses this to determine which vector
26952 registers to save on a context switch. We need to save
26953 VRSAVE on the stack frame, add whatever AltiVec registers we
26954 used in this function, and do the corresponding magic in the
26957 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26958 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26960 /* Get VRSAVE into a GPR. */
26961 rtx reg = gen_rtx_REG (SImode, save_regno);
26962 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26964 emit_insn (gen_get_vrsave_internal (reg));
26966 emit_insn (gen_rtx_SET (reg, vrsave));
26969 int offset = info->vrsave_save_offset + frame_off;
26970 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26972 /* Include the registers in the mask. */
26973 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26975 emit_insn (generate_set_vrsave (reg, info, 0));
26978 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26979 called, it left the arg pointer to the old stack in r29. Otherwise, the
26980 arg pointer is the top of the current frame. */
26982 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26983 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26985 cfun->machine->split_stack_argp_used = true;
26989 rtx r12 = gen_rtx_REG (Pmode, 12);
26990 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26991 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26992 emit_insn_before (set_r12, sp_adjust);
26994 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26996 rtx r12 = gen_rtx_REG (Pmode, 12);
26997 if (frame_off == 0)
26998 emit_move_insn (r12, frame_reg_rtx);
27000 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
27005 rtx r12 = gen_rtx_REG (Pmode, 12);
27006 rtx r29 = gen_rtx_REG (Pmode, 29);
27007 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
27008 rtx not_more = gen_label_rtx ();
27011 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27012 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
27013 gen_rtx_LABEL_REF (VOIDmode, not_more),
27015 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27016 JUMP_LABEL (jump) = not_more;
27017 LABEL_NUSES (not_more) += 1;
27018 emit_move_insn (r12, r29);
27019 emit_label (not_more);
27023 /* Emit function prologue as insns. */
27026 rs6000_emit_prologue (void)
27028 rs6000_stack_t *info = rs6000_stack_info ();
27029 machine_mode reg_mode = Pmode;
27030 int reg_size = TARGET_32BIT ? 4 : 8;
27031 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
27033 int fp_reg_size = 8;
27034 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27035 rtx frame_reg_rtx = sp_reg_rtx;
27036 unsigned int cr_save_regno;
27037 rtx cr_save_rtx = NULL_RTX;
27040 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
27041 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
27042 && call_used_regs[STATIC_CHAIN_REGNUM]);
27043 int using_split_stack = (flag_split_stack
27044 && (lookup_attribute ("no_split_stack",
27045 DECL_ATTRIBUTES (cfun->decl))
27048 /* Offset to top of frame for frame_reg and sp respectively. */
27049 HOST_WIDE_INT frame_off = 0;
27050 HOST_WIDE_INT sp_off = 0;
27051 /* sp_adjust is the stack adjusting instruction, tracked so that the
27052 insn setting up the split-stack arg pointer can be emitted just
27053 prior to it, when r12 is not used here for other purposes. */
27054 rtx_insn *sp_adjust = 0;
27057 /* Track and check usage of r0, r11, r12. */
27058 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
27059 #define START_USE(R) do \
27061 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27062 reg_inuse |= 1 << (R); \
27064 #define END_USE(R) do \
27066 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
27067 reg_inuse &= ~(1 << (R)); \
27069 #define NOT_INUSE(R) do \
27071 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27074 #define START_USE(R) do {} while (0)
27075 #define END_USE(R) do {} while (0)
27076 #define NOT_INUSE(R) do {} while (0)
27079 if (DEFAULT_ABI == ABI_ELFv2
27080 && !TARGET_SINGLE_PIC_BASE)
27082 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
27084 /* With -mminimal-toc we may generate an extra use of r2 below. */
27085 if (TARGET_TOC && TARGET_MINIMAL_TOC
27086 && !constant_pool_empty_p ())
27087 cfun->machine->r2_setup_needed = true;
27091 if (flag_stack_usage_info)
27092 current_function_static_stack_size = info->total_size;
27094 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
27096 HOST_WIDE_INT size = info->total_size;
27098 if (crtl->is_leaf && !cfun->calls_alloca)
27100 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
27101 rs6000_emit_probe_stack_range (get_stack_check_protect (),
27102 size - get_stack_check_protect ());
27105 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
27108 if (TARGET_FIX_AND_CONTINUE)
27110 /* gdb on darwin arranges to forward a function from the old
27111 address by modifying the first 5 instructions of the function
27112 to branch to the overriding function. This is necessary to
27113 permit function pointers that point to the old function to
27114 actually forward to the new function. */
27115 emit_insn (gen_nop ());
27116 emit_insn (gen_nop ());
27117 emit_insn (gen_nop ());
27118 emit_insn (gen_nop ());
27119 emit_insn (gen_nop ());
27122 /* Handle world saves specially here. */
27123 if (WORLD_SAVE_P (info))
27130 /* save_world expects lr in r0. */
27131 reg0 = gen_rtx_REG (Pmode, 0);
27132 if (info->lr_save_p)
27134 insn = emit_move_insn (reg0,
27135 gen_rtx_REG (Pmode, LR_REGNO));
27136 RTX_FRAME_RELATED_P (insn) = 1;
27139 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
27140 assumptions about the offsets of various bits of the stack
27142 gcc_assert (info->gp_save_offset == -220
27143 && info->fp_save_offset == -144
27144 && info->lr_save_offset == 8
27145 && info->cr_save_offset == 4
27148 && (!crtl->calls_eh_return
27149 || info->ehrd_offset == -432)
27150 && info->vrsave_save_offset == -224
27151 && info->altivec_save_offset == -416);
27153 treg = gen_rtx_REG (SImode, 11);
27154 emit_move_insn (treg, GEN_INT (-info->total_size));
27156 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
27157 in R11. It also clobbers R12, so beware! */
27159 /* Preserve CR2 for save_world prologues */
27161 sz += 32 - info->first_gp_reg_save;
27162 sz += 64 - info->first_fp_reg_save;
27163 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
27164 p = rtvec_alloc (sz);
27166 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
27167 gen_rtx_REG (SImode,
27169 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
27170 gen_rtx_SYMBOL_REF (Pmode,
27172 /* We do floats first so that the instruction pattern matches
27174 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
27176 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
27178 info->first_fp_reg_save + i),
27180 info->fp_save_offset + frame_off + 8 * i);
27181 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27183 = gen_frame_store (gen_rtx_REG (V4SImode,
27184 info->first_altivec_reg_save + i),
27186 info->altivec_save_offset + frame_off + 16 * i);
27187 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27189 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27191 info->gp_save_offset + frame_off + reg_size * i);
27193 /* CR register traditionally saved as CR2. */
27195 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
27196 frame_reg_rtx, info->cr_save_offset + frame_off);
27197 /* Explain about use of R0. */
27198 if (info->lr_save_p)
27200 = gen_frame_store (reg0,
27201 frame_reg_rtx, info->lr_save_offset + frame_off);
27202 /* Explain what happens to the stack pointer. */
27204 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
27205 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
27208 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27209 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27210 treg, GEN_INT (-info->total_size));
27211 sp_off = frame_off = info->total_size;
27214 strategy = info->savres_strategy;
27216 /* For V.4, update stack before we do any saving and set back pointer. */
27217 if (! WORLD_SAVE_P (info)
27219 && (DEFAULT_ABI == ABI_V4
27220 || crtl->calls_eh_return))
27222 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
27223 || !(strategy & SAVE_INLINE_GPRS)
27224 || !(strategy & SAVE_INLINE_VRS));
27225 int ptr_regno = -1;
27226 rtx ptr_reg = NULL_RTX;
27229 if (info->total_size < 32767)
27230 frame_off = info->total_size;
27233 else if (info->cr_save_p
27235 || info->first_fp_reg_save < 64
27236 || info->first_gp_reg_save < 32
27237 || info->altivec_size != 0
27238 || info->vrsave_size != 0
27239 || crtl->calls_eh_return)
27243 /* The prologue won't be saving any regs so there is no need
27244 to set up a frame register to access any frame save area.
27245 We also won't be using frame_off anywhere below, but set
27246 the correct value anyway to protect against future
27247 changes to this function. */
27248 frame_off = info->total_size;
27250 if (ptr_regno != -1)
27252 /* Set up the frame offset to that needed by the first
27253 out-of-line save function. */
27254 START_USE (ptr_regno);
27255 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27256 frame_reg_rtx = ptr_reg;
27257 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
27258 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
27259 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
27260 ptr_off = info->gp_save_offset + info->gp_size;
27261 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
27262 ptr_off = info->altivec_save_offset + info->altivec_size;
27263 frame_off = -ptr_off;
27265 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27267 if (REGNO (frame_reg_rtx) == 12)
27269 sp_off = info->total_size;
27270 if (frame_reg_rtx != sp_reg_rtx)
27271 rs6000_emit_stack_tie (frame_reg_rtx, false);
27274 /* If we use the link register, get it into r0. */
27275 if (!WORLD_SAVE_P (info) && info->lr_save_p
27276 && !cfun->machine->lr_is_wrapped_separately)
27278 rtx addr, reg, mem;
27280 reg = gen_rtx_REG (Pmode, 0);
27282 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
27283 RTX_FRAME_RELATED_P (insn) = 1;
27285 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
27286 | SAVE_NOINLINE_FPRS_SAVES_LR)))
27288 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27289 GEN_INT (info->lr_save_offset + frame_off));
27290 mem = gen_rtx_MEM (Pmode, addr);
27291 /* This should not be of rs6000_sr_alias_set, because of
27292 __builtin_return_address. */
27294 insn = emit_move_insn (mem, reg);
27295 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27296 NULL_RTX, NULL_RTX);
27301 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
27302 r12 will be needed by out-of-line gpr restore. */
27303 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27304 && !(strategy & (SAVE_INLINE_GPRS
27305 | SAVE_NOINLINE_GPRS_SAVES_LR))
27307 if (!WORLD_SAVE_P (info)
27309 && REGNO (frame_reg_rtx) != cr_save_regno
27310 && !(using_static_chain_p && cr_save_regno == 11)
27311 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
27313 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
27314 START_USE (cr_save_regno);
27315 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27318 /* Do any required saving of fpr's. If only one or two to save, do
27319 it ourselves. Otherwise, call function. */
27320 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
27322 int offset = info->fp_save_offset + frame_off;
27323 for (int i = info->first_fp_reg_save; i < 64; i++)
27326 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
27327 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
27328 sp_off - frame_off);
27330 offset += fp_reg_size;
27333 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
27335 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27336 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27337 unsigned ptr_regno = ptr_regno_for_savres (sel);
27338 rtx ptr_reg = frame_reg_rtx;
27340 if (REGNO (frame_reg_rtx) == ptr_regno)
27341 gcc_checking_assert (frame_off == 0);
27344 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27345 NOT_INUSE (ptr_regno);
27346 emit_insn (gen_add3_insn (ptr_reg,
27347 frame_reg_rtx, GEN_INT (frame_off)));
27349 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27350 info->fp_save_offset,
27351 info->lr_save_offset,
27353 rs6000_frame_related (insn, ptr_reg, sp_off,
27354 NULL_RTX, NULL_RTX);
27359 /* Save GPRs. This is done as a PARALLEL if we are using
27360 the store-multiple instructions. */
27361 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
27363 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
27364 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
27365 unsigned ptr_regno = ptr_regno_for_savres (sel);
27366 rtx ptr_reg = frame_reg_rtx;
27367 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
27368 int end_save = info->gp_save_offset + info->gp_size;
27371 if (ptr_regno == 12)
27374 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27376 /* Need to adjust r11 (r12) if we saved any FPRs. */
27377 if (end_save + frame_off != 0)
27379 rtx offset = GEN_INT (end_save + frame_off);
27382 frame_off = -end_save;
27384 NOT_INUSE (ptr_regno);
27385 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27387 else if (!ptr_set_up)
27389 NOT_INUSE (ptr_regno);
27390 emit_move_insn (ptr_reg, frame_reg_rtx);
27392 ptr_off = -end_save;
27393 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27394 info->gp_save_offset + ptr_off,
27395 info->lr_save_offset + ptr_off,
27397 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
27398 NULL_RTX, NULL_RTX);
27402 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
27406 p = rtvec_alloc (32 - info->first_gp_reg_save);
27407 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27409 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27411 info->gp_save_offset + frame_off + reg_size * i);
27412 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27413 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27414 NULL_RTX, NULL_RTX);
27416 else if (!WORLD_SAVE_P (info))
27418 int offset = info->gp_save_offset + frame_off;
27419 for (int i = info->first_gp_reg_save; i < 32; i++)
27422 && !cfun->machine->gpr_is_wrapped_separately[i])
27423 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
27424 sp_off - frame_off);
27426 offset += reg_size;
27430 if (crtl->calls_eh_return)
27437 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27438 if (regno == INVALID_REGNUM)
27442 p = rtvec_alloc (i);
27446 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27447 if (regno == INVALID_REGNUM)
27451 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27453 info->ehrd_offset + sp_off + reg_size * (int) i);
27454 RTVEC_ELT (p, i) = set;
27455 RTX_FRAME_RELATED_P (set) = 1;
27458 insn = emit_insn (gen_blockage ());
27459 RTX_FRAME_RELATED_P (insn) = 1;
27460 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27463 /* In AIX ABI we need to make sure r2 is really saved. */
27464 if (TARGET_AIX && crtl->calls_eh_return)
27466 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27467 rtx join_insn, note;
27468 rtx_insn *save_insn;
27469 long toc_restore_insn;
27471 tmp_reg = gen_rtx_REG (Pmode, 11);
27472 tmp_reg_si = gen_rtx_REG (SImode, 11);
27473 if (using_static_chain_p)
27476 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27480 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27481 /* Peek at instruction to which this function returns. If it's
27482 restoring r2, then we know we've already saved r2. We can't
27483 unconditionally save r2 because the value we have will already
27484 be updated if we arrived at this function via a plt call or
27485 toc adjusting stub. */
27486 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27487 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27488 + RS6000_TOC_SAVE_SLOT);
27489 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27490 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27491 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27492 validate_condition_mode (EQ, CCUNSmode);
27493 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27494 emit_insn (gen_rtx_SET (compare_result,
27495 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27496 toc_save_done = gen_label_rtx ();
27497 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27498 gen_rtx_EQ (VOIDmode, compare_result,
27500 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27502 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27503 JUMP_LABEL (jump) = toc_save_done;
27504 LABEL_NUSES (toc_save_done) += 1;
27506 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27507 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27508 sp_off - frame_off);
27510 emit_label (toc_save_done);
27512 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27513 have a CFG that has different saves along different paths.
27514 Move the note to a dummy blockage insn, which describes that
27515 R2 is unconditionally saved after the label. */
27516 /* ??? An alternate representation might be a special insn pattern
27517 containing both the branch and the store. That might let the
27518 code that minimizes the number of DW_CFA_advance opcodes better
27519 freedom in placing the annotations. */
27520 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27522 remove_note (save_insn, note);
27524 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27525 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27526 RTX_FRAME_RELATED_P (save_insn) = 0;
27528 join_insn = emit_insn (gen_blockage ());
27529 REG_NOTES (join_insn) = note;
27530 RTX_FRAME_RELATED_P (join_insn) = 1;
27532 if (using_static_chain_p)
27534 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27541 /* Save CR if we use any that must be preserved. */
27542 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27544 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27545 GEN_INT (info->cr_save_offset + frame_off));
27546 rtx mem = gen_frame_mem (SImode, addr);
27548 /* If we didn't copy cr before, do so now using r0. */
27549 if (cr_save_rtx == NULL_RTX)
27552 cr_save_rtx = gen_rtx_REG (SImode, 0);
27553 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27556 /* Saving CR requires a two-instruction sequence: one instruction
27557 to move the CR to a general-purpose register, and a second
27558 instruction that stores the GPR to memory.
27560 We do not emit any DWARF CFI records for the first of these,
27561 because we cannot properly represent the fact that CR is saved in
27562 a register. One reason is that we cannot express that multiple
27563 CR fields are saved; another reason is that on 64-bit, the size
27564 of the CR register in DWARF (4 bytes) differs from the size of
27565 a general-purpose register.
27567 This means if any intervening instruction were to clobber one of
27568 the call-saved CR fields, we'd have incorrect CFI. To prevent
27569 this from happening, we mark the store to memory as a use of
27570 those CR fields, which prevents any such instruction from being
27571 scheduled in between the two instructions. */
27576 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27577 for (i = 0; i < 8; i++)
27578 if (save_reg_p (CR0_REGNO + i))
27579 crsave_v[n_crsave++]
27580 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27582 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27583 gen_rtvec_v (n_crsave, crsave_v)));
27584 END_USE (REGNO (cr_save_rtx));
27586 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27587 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27588 so we need to construct a frame expression manually. */
27589 RTX_FRAME_RELATED_P (insn) = 1;
27591 /* Update address to be stack-pointer relative, like
27592 rs6000_frame_related would do. */
27593 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27594 GEN_INT (info->cr_save_offset + sp_off));
27595 mem = gen_frame_mem (SImode, addr);
27597 if (DEFAULT_ABI == ABI_ELFv2)
27599 /* In the ELFv2 ABI we generate separate CFI records for each
27600 CR field that was actually saved. They all point to the
27601 same 32-bit stack slot. */
27605 for (i = 0; i < 8; i++)
27606 if (save_reg_p (CR0_REGNO + i))
27609 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27611 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27615 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27616 gen_rtx_PARALLEL (VOIDmode,
27617 gen_rtvec_v (n_crframe, crframe)));
27621 /* In other ABIs, by convention, we use a single CR regnum to
27622 represent the fact that all call-saved CR fields are saved.
27623 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27624 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27625 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27629 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27630 *separate* slots if the routine calls __builtin_eh_return, so
27631 that they can be independently restored by the unwinder. */
27632 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27634 int i, cr_off = info->ehcr_offset;
27637 /* ??? We might get better performance by using multiple mfocrf
27639 crsave = gen_rtx_REG (SImode, 0);
27640 emit_insn (gen_prologue_movesi_from_cr (crsave));
27642 for (i = 0; i < 8; i++)
27643 if (!call_used_regs[CR0_REGNO + i])
27645 rtvec p = rtvec_alloc (2);
27647 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27649 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27651 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27653 RTX_FRAME_RELATED_P (insn) = 1;
27654 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27655 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27656 sp_reg_rtx, cr_off + sp_off));
27658 cr_off += reg_size;
27662 /* If we are emitting stack probes, but allocate no stack, then
27663 just note that in the dump file. */
27664 if (flag_stack_clash_protection
27667 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27669 /* Update stack and set back pointer unless this is V.4,
27670 for which it was done previously. */
27671 if (!WORLD_SAVE_P (info) && info->push_p
27672 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27674 rtx ptr_reg = NULL;
27677 /* If saving altivec regs we need to be able to address all save
27678 locations using a 16-bit offset. */
27679 if ((strategy & SAVE_INLINE_VRS) == 0
27680 || (info->altivec_size != 0
27681 && (info->altivec_save_offset + info->altivec_size - 16
27682 + info->total_size - frame_off) > 32767)
27683 || (info->vrsave_size != 0
27684 && (info->vrsave_save_offset
27685 + info->total_size - frame_off) > 32767))
27687 int sel = SAVRES_SAVE | SAVRES_VR;
27688 unsigned ptr_regno = ptr_regno_for_savres (sel);
27690 if (using_static_chain_p
27691 && ptr_regno == STATIC_CHAIN_REGNUM)
27693 if (REGNO (frame_reg_rtx) != ptr_regno)
27694 START_USE (ptr_regno);
27695 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27696 frame_reg_rtx = ptr_reg;
27697 ptr_off = info->altivec_save_offset + info->altivec_size;
27698 frame_off = -ptr_off;
27700 else if (REGNO (frame_reg_rtx) == 1)
27701 frame_off = info->total_size;
27702 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27704 if (REGNO (frame_reg_rtx) == 12)
27706 sp_off = info->total_size;
27707 if (frame_reg_rtx != sp_reg_rtx)
27708 rs6000_emit_stack_tie (frame_reg_rtx, false);
27711 /* Set frame pointer, if needed. */
27712 if (frame_pointer_needed)
27714 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27716 RTX_FRAME_RELATED_P (insn) = 1;
27719 /* Save AltiVec registers if needed. Save here because the red zone does
27720 not always include AltiVec registers. */
27721 if (!WORLD_SAVE_P (info)
27722 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27724 int end_save = info->altivec_save_offset + info->altivec_size;
27726 /* Oddly, the vector save/restore functions point r0 at the end
27727 of the save area, then use r11 or r12 to load offsets for
27728 [reg+reg] addressing. */
27729 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27730 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27731 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27733 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27735 if (scratch_regno == 12)
27737 if (end_save + frame_off != 0)
27739 rtx offset = GEN_INT (end_save + frame_off);
27741 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27744 emit_move_insn (ptr_reg, frame_reg_rtx);
27746 ptr_off = -end_save;
27747 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27748 info->altivec_save_offset + ptr_off,
27749 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27750 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27751 NULL_RTX, NULL_RTX);
27752 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27754 /* The oddity mentioned above clobbered our frame reg. */
27755 emit_move_insn (frame_reg_rtx, ptr_reg);
27756 frame_off = ptr_off;
27759 else if (!WORLD_SAVE_P (info)
27760 && info->altivec_size != 0)
27764 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27765 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27767 rtx areg, savereg, mem;
27768 HOST_WIDE_INT offset;
27770 offset = (info->altivec_save_offset + frame_off
27771 + 16 * (i - info->first_altivec_reg_save));
27773 savereg = gen_rtx_REG (V4SImode, i);
27775 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27777 mem = gen_frame_mem (V4SImode,
27778 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27779 GEN_INT (offset)));
27780 insn = emit_insn (gen_rtx_SET (mem, savereg));
27786 areg = gen_rtx_REG (Pmode, 0);
27787 emit_move_insn (areg, GEN_INT (offset));
27789 /* AltiVec addressing mode is [reg+reg]. */
27790 mem = gen_frame_mem (V4SImode,
27791 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27793 /* Rather than emitting a generic move, force use of the stvx
27794 instruction, which we always want on ISA 2.07 (power8) systems.
27795 In particular we don't want xxpermdi/stxvd2x for little
27797 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27800 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27801 areg, GEN_INT (offset));
27805 /* VRSAVE is a bit vector representing which AltiVec registers
27806 are used. The OS uses this to determine which vector
27807 registers to save on a context switch. We need to save
27808 VRSAVE on the stack frame, add whatever AltiVec registers we
27809 used in this function, and do the corresponding magic in the
27812 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27814 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27815 be using r12 as frame_reg_rtx and r11 as the static chain
27816 pointer for nested functions. */
27817 int save_regno = 12;
27818 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27819 && !using_static_chain_p)
27821 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27824 if (using_static_chain_p)
27827 NOT_INUSE (save_regno);
27829 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27832 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27833 if (!TARGET_SINGLE_PIC_BASE
27834 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27835 && !constant_pool_empty_p ())
27836 || (DEFAULT_ABI == ABI_V4
27837 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27838 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27840 /* If emit_load_toc_table will use the link register, we need to save
27841 it. We use R12 for this purpose because emit_load_toc_table
27842 can use register 0. This allows us to use a plain 'blr' to return
27843 from the procedure more often. */
27844 int save_LR_around_toc_setup = (TARGET_ELF
27845 && DEFAULT_ABI == ABI_V4
27847 && ! info->lr_save_p
27848 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27849 if (save_LR_around_toc_setup)
27851 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27852 rtx tmp = gen_rtx_REG (Pmode, 12);
27855 insn = emit_move_insn (tmp, lr);
27856 RTX_FRAME_RELATED_P (insn) = 1;
27858 rs6000_emit_load_toc_table (TRUE);
27860 insn = emit_move_insn (lr, tmp);
27861 add_reg_note (insn, REG_CFA_RESTORE, lr);
27862 RTX_FRAME_RELATED_P (insn) = 1;
27865 rs6000_emit_load_toc_table (TRUE);
27869 if (!TARGET_SINGLE_PIC_BASE
27870 && DEFAULT_ABI == ABI_DARWIN
27871 && flag_pic && crtl->uses_pic_offset_table)
27873 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27874 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27876 /* Save and restore LR locally around this call (in R0). */
27877 if (!info->lr_save_p)
27878 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27880 emit_insn (gen_load_macho_picbase (src));
27882 emit_move_insn (gen_rtx_REG (Pmode,
27883 RS6000_PIC_OFFSET_TABLE_REGNUM),
27886 if (!info->lr_save_p)
27887 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27891 /* If we need to, save the TOC register after doing the stack setup.
27892 Do not emit eh frame info for this save. The unwinder wants info,
27893 conceptually attached to instructions in this function, about
27894 register values in the caller of this function. This R2 may have
27895 already been changed from the value in the caller.
27896 We don't attempt to write accurate DWARF EH frame info for R2
27897 because code emitted by gcc for a (non-pointer) function call
27898 doesn't save and restore R2. Instead, R2 is managed out-of-line
27899 by a linker generated plt call stub when the function resides in
27900 a shared library. This behavior is costly to describe in DWARF,
27901 both in terms of the size of DWARF info and the time taken in the
27902 unwinder to interpret it. R2 changes, apart from the
27903 calls_eh_return case earlier in this function, are handled by
27904 linux-unwind.h frob_update_context. */
27905 if (rs6000_save_toc_in_prologue_p ()
27906 && !cfun->machine->toc_is_wrapped_separately)
27908 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27909 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27912 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27913 if (using_split_stack && split_stack_arg_pointer_used_p ())
27914 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27917 /* Output .extern statements for the save/restore routines we use. */
27920 rs6000_output_savres_externs (FILE *file)
27922 rs6000_stack_t *info = rs6000_stack_info ();
27924 if (TARGET_DEBUG_STACK)
27925 debug_stack_info (info);
27927 /* Write .extern for any function we will call to save and restore
27929 if (info->first_fp_reg_save < 64
27934 int regno = info->first_fp_reg_save - 32;
27936 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27938 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27939 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27940 name = rs6000_savres_routine_name (regno, sel);
27941 fprintf (file, "\t.extern %s\n", name);
27943 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27945 bool lr = (info->savres_strategy
27946 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27947 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27948 name = rs6000_savres_routine_name (regno, sel);
27949 fprintf (file, "\t.extern %s\n", name);
27954 /* Write function prologue. */
27957 rs6000_output_function_prologue (FILE *file)
27959 if (!cfun->is_thunk)
27960 rs6000_output_savres_externs (file);
27962 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27963 immediately after the global entry point label. */
27964 if (rs6000_global_entry_point_needed_p ())
27966 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27968 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27970 if (TARGET_CMODEL != CMODEL_LARGE)
27972 /* In the small and medium code models, we assume the TOC is less
27973 2 GB away from the text section, so it can be computed via the
27974 following two-instruction sequence. */
27977 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27978 fprintf (file, "0:\taddis 2,12,.TOC.-");
27979 assemble_name (file, buf);
27980 fprintf (file, "@ha\n");
27981 fprintf (file, "\taddi 2,2,.TOC.-");
27982 assemble_name (file, buf);
27983 fprintf (file, "@l\n");
27987 /* In the large code model, we allow arbitrary offsets between the
27988 TOC and the text section, so we have to load the offset from
27989 memory. The data field is emitted directly before the global
27990 entry point in rs6000_elf_declare_function_name. */
27993 #ifdef HAVE_AS_ENTRY_MARKERS
27994 /* If supported by the linker, emit a marker relocation. If the
27995 total code size of the final executable or shared library
27996 happens to fit into 2 GB after all, the linker will replace
27997 this code sequence with the sequence for the small or medium
27999 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
28001 fprintf (file, "\tld 2,");
28002 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
28003 assemble_name (file, buf);
28004 fprintf (file, "-");
28005 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28006 assemble_name (file, buf);
28007 fprintf (file, "(12)\n");
28008 fprintf (file, "\tadd 2,2,12\n");
28011 fputs ("\t.localentry\t", file);
28012 assemble_name (file, name);
28013 fputs (",.-", file);
28014 assemble_name (file, name);
28015 fputs ("\n", file);
28018 /* Output -mprofile-kernel code. This needs to be done here instead of
28019 in output_function_profile since it must go after the ELFv2 ABI
28020 local entry point. */
28021 if (TARGET_PROFILE_KERNEL && crtl->profile)
28023 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
28024 gcc_assert (!TARGET_32BIT);
28026 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
28028 /* In the ELFv2 ABI we have no compiler stack word. It must be
28029 the resposibility of _mcount to preserve the static chain
28030 register if required. */
28031 if (DEFAULT_ABI != ABI_ELFv2
28032 && cfun->static_chain_decl != NULL)
28034 asm_fprintf (file, "\tstd %s,24(%s)\n",
28035 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28036 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28037 asm_fprintf (file, "\tld %s,24(%s)\n",
28038 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28041 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28044 rs6000_pic_labelno++;
28047 /* -mprofile-kernel code calls mcount before the function prolog,
28048 so a profiled leaf function should stay a leaf function. */
28050 rs6000_keep_leaf_when_profiled ()
28052 return TARGET_PROFILE_KERNEL;
28055 /* Non-zero if vmx regs are restored before the frame pop, zero if
28056 we restore after the pop when possible. */
28057 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
28059 /* Restoring cr is a two step process: loading a reg from the frame
28060 save, then moving the reg to cr. For ABI_V4 we must let the
28061 unwinder know that the stack location is no longer valid at or
28062 before the stack deallocation, but we can't emit a cfa_restore for
28063 cr at the stack deallocation like we do for other registers.
28064 The trouble is that it is possible for the move to cr to be
28065 scheduled after the stack deallocation. So say exactly where cr
28066 is located on each of the two insns. */
28069 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
28071 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
28072 rtx reg = gen_rtx_REG (SImode, regno);
28073 rtx_insn *insn = emit_move_insn (reg, mem);
28075 if (!exit_func && DEFAULT_ABI == ABI_V4)
28077 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28078 rtx set = gen_rtx_SET (reg, cr);
28080 add_reg_note (insn, REG_CFA_REGISTER, set);
28081 RTX_FRAME_RELATED_P (insn) = 1;
28086 /* Reload CR from REG. */
28089 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
28094 if (using_mfcr_multiple)
28096 for (i = 0; i < 8; i++)
28097 if (save_reg_p (CR0_REGNO + i))
28099 gcc_assert (count);
28102 if (using_mfcr_multiple && count > 1)
28108 p = rtvec_alloc (count);
28111 for (i = 0; i < 8; i++)
28112 if (save_reg_p (CR0_REGNO + i))
28114 rtvec r = rtvec_alloc (2);
28115 RTVEC_ELT (r, 0) = reg;
28116 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
28117 RTVEC_ELT (p, ndx) =
28118 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
28119 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
28122 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28123 gcc_assert (ndx == count);
28125 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28126 CR field separately. */
28127 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28129 for (i = 0; i < 8; i++)
28130 if (save_reg_p (CR0_REGNO + i))
28131 add_reg_note (insn, REG_CFA_RESTORE,
28132 gen_rtx_REG (SImode, CR0_REGNO + i));
28134 RTX_FRAME_RELATED_P (insn) = 1;
28138 for (i = 0; i < 8; i++)
28139 if (save_reg_p (CR0_REGNO + i))
28141 rtx insn = emit_insn (gen_movsi_to_cr_one
28142 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28144 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28145 CR field separately, attached to the insn that in fact
28146 restores this particular CR field. */
28147 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28149 add_reg_note (insn, REG_CFA_RESTORE,
28150 gen_rtx_REG (SImode, CR0_REGNO + i));
28152 RTX_FRAME_RELATED_P (insn) = 1;
28156 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
28157 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
28158 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
28160 rtx_insn *insn = get_last_insn ();
28161 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28163 add_reg_note (insn, REG_CFA_RESTORE, cr);
28164 RTX_FRAME_RELATED_P (insn) = 1;
28168 /* Like cr, the move to lr instruction can be scheduled after the
28169 stack deallocation, but unlike cr, its stack frame save is still
28170 valid. So we only need to emit the cfa_restore on the correct
28174 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
28176 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
28177 rtx reg = gen_rtx_REG (Pmode, regno);
28179 emit_move_insn (reg, mem);
28183 restore_saved_lr (int regno, bool exit_func)
28185 rtx reg = gen_rtx_REG (Pmode, regno);
28186 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
28187 rtx_insn *insn = emit_move_insn (lr, reg);
28189 if (!exit_func && flag_shrink_wrap)
28191 add_reg_note (insn, REG_CFA_RESTORE, lr);
28192 RTX_FRAME_RELATED_P (insn) = 1;
28197 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
28199 if (DEFAULT_ABI == ABI_ELFv2)
28202 for (i = 0; i < 8; i++)
28203 if (save_reg_p (CR0_REGNO + i))
28205 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
28206 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
28210 else if (info->cr_save_p)
28211 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28212 gen_rtx_REG (SImode, CR2_REGNO),
28215 if (info->lr_save_p)
28216 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28217 gen_rtx_REG (Pmode, LR_REGNO),
28219 return cfa_restores;
28222 /* Return true if OFFSET from stack pointer can be clobbered by signals.
28223 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
28224 below stack pointer not cloberred by signals. */
28227 offset_below_red_zone_p (HOST_WIDE_INT offset)
28229 return offset < (DEFAULT_ABI == ABI_V4
28231 : TARGET_32BIT ? -220 : -288);
28234 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
28237 emit_cfa_restores (rtx cfa_restores)
28239 rtx_insn *insn = get_last_insn ();
28240 rtx *loc = ®_NOTES (insn);
28243 loc = &XEXP (*loc, 1);
28244 *loc = cfa_restores;
28245 RTX_FRAME_RELATED_P (insn) = 1;
28248 /* Emit function epilogue as insns. */
28251 rs6000_emit_epilogue (int sibcall)
28253 rs6000_stack_t *info;
28254 int restoring_GPRs_inline;
28255 int restoring_FPRs_inline;
28256 int using_load_multiple;
28257 int using_mtcr_multiple;
28258 int use_backchain_to_restore_sp;
28261 HOST_WIDE_INT frame_off = 0;
28262 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
28263 rtx frame_reg_rtx = sp_reg_rtx;
28264 rtx cfa_restores = NULL_RTX;
28266 rtx cr_save_reg = NULL_RTX;
28267 machine_mode reg_mode = Pmode;
28268 int reg_size = TARGET_32BIT ? 4 : 8;
28269 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
28271 int fp_reg_size = 8;
28274 unsigned ptr_regno;
28276 info = rs6000_stack_info ();
28278 strategy = info->savres_strategy;
28279 using_load_multiple = strategy & REST_MULTIPLE;
28280 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
28281 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
28282 using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
28283 || rs6000_tune == PROCESSOR_PPC603
28284 || rs6000_tune == PROCESSOR_PPC750
28286 /* Restore via the backchain when we have a large frame, since this
28287 is more efficient than an addis, addi pair. The second condition
28288 here will not trigger at the moment; We don't actually need a
28289 frame pointer for alloca, but the generic parts of the compiler
28290 give us one anyway. */
28291 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
28292 ? info->lr_save_offset
28294 || (cfun->calls_alloca
28295 && !frame_pointer_needed));
28296 restore_lr = (info->lr_save_p
28297 && (restoring_FPRs_inline
28298 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
28299 && (restoring_GPRs_inline
28300 || info->first_fp_reg_save < 64)
28301 && !cfun->machine->lr_is_wrapped_separately);
28304 if (WORLD_SAVE_P (info))
28308 const char *alloc_rname;
28311 /* eh_rest_world_r10 will return to the location saved in the LR
28312 stack slot (which is not likely to be our caller.)
28313 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28314 rest_world is similar, except any R10 parameter is ignored.
28315 The exception-handling stuff that was here in 2.95 is no
28316 longer necessary. */
28319 + 32 - info->first_gp_reg_save
28320 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
28321 + 63 + 1 - info->first_fp_reg_save);
28323 strcpy (rname, ((crtl->calls_eh_return) ?
28324 "*eh_rest_world_r10" : "*rest_world"));
28325 alloc_rname = ggc_strdup (rname);
28328 RTVEC_ELT (p, j++) = ret_rtx;
28330 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
28331 /* The instruction pattern requires a clobber here;
28332 it is shared with the restVEC helper. */
28334 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
28337 /* CR register traditionally saved as CR2. */
28338 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
28340 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
28341 if (flag_shrink_wrap)
28343 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28344 gen_rtx_REG (Pmode, LR_REGNO),
28346 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28350 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28352 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
28354 = gen_frame_load (reg,
28355 frame_reg_rtx, info->gp_save_offset + reg_size * i);
28356 if (flag_shrink_wrap
28357 && save_reg_p (info->first_gp_reg_save + i))
28358 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28360 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
28362 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
28364 = gen_frame_load (reg,
28365 frame_reg_rtx, info->altivec_save_offset + 16 * i);
28366 if (flag_shrink_wrap
28367 && save_reg_p (info->first_altivec_reg_save + i))
28368 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28370 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
28372 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
28373 ? DFmode : SFmode),
28374 info->first_fp_reg_save + i);
28376 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
28377 if (flag_shrink_wrap
28378 && save_reg_p (info->first_fp_reg_save + i))
28379 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28382 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
28384 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
28386 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
28388 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
28390 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
28391 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28393 if (flag_shrink_wrap)
28395 REG_NOTES (insn) = cfa_restores;
28396 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28397 RTX_FRAME_RELATED_P (insn) = 1;
28402 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28404 frame_off = info->total_size;
28406 /* Restore AltiVec registers if we must do so before adjusting the
28408 if (info->altivec_size != 0
28409 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28410 || (DEFAULT_ABI != ABI_V4
28411 && offset_below_red_zone_p (info->altivec_save_offset))))
28414 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28416 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
28417 if (use_backchain_to_restore_sp)
28419 int frame_regno = 11;
28421 if ((strategy & REST_INLINE_VRS) == 0)
28423 /* Of r11 and r12, select the one not clobbered by an
28424 out-of-line restore function for the frame register. */
28425 frame_regno = 11 + 12 - scratch_regno;
28427 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28428 emit_move_insn (frame_reg_rtx,
28429 gen_rtx_MEM (Pmode, sp_reg_rtx));
28432 else if (frame_pointer_needed)
28433 frame_reg_rtx = hard_frame_pointer_rtx;
28435 if ((strategy & REST_INLINE_VRS) == 0)
28437 int end_save = info->altivec_save_offset + info->altivec_size;
28439 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28440 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28442 if (end_save + frame_off != 0)
28444 rtx offset = GEN_INT (end_save + frame_off);
28446 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28449 emit_move_insn (ptr_reg, frame_reg_rtx);
28451 ptr_off = -end_save;
28452 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28453 info->altivec_save_offset + ptr_off,
28454 0, V4SImode, SAVRES_VR);
28458 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28459 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28461 rtx addr, areg, mem, insn;
28462 rtx reg = gen_rtx_REG (V4SImode, i);
28463 HOST_WIDE_INT offset
28464 = (info->altivec_save_offset + frame_off
28465 + 16 * (i - info->first_altivec_reg_save));
28467 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28469 mem = gen_frame_mem (V4SImode,
28470 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28471 GEN_INT (offset)));
28472 insn = gen_rtx_SET (reg, mem);
28476 areg = gen_rtx_REG (Pmode, 0);
28477 emit_move_insn (areg, GEN_INT (offset));
28479 /* AltiVec addressing mode is [reg+reg]. */
28480 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28481 mem = gen_frame_mem (V4SImode, addr);
28483 /* Rather than emitting a generic move, force use of the
28484 lvx instruction, which we always want. In particular we
28485 don't want lxvd2x/xxpermdi for little endian. */
28486 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28489 (void) emit_insn (insn);
28493 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28494 if (((strategy & REST_INLINE_VRS) == 0
28495 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28496 && (flag_shrink_wrap
28497 || (offset_below_red_zone_p
28498 (info->altivec_save_offset
28499 + 16 * (i - info->first_altivec_reg_save))))
28502 rtx reg = gen_rtx_REG (V4SImode, i);
28503 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28507 /* Restore VRSAVE if we must do so before adjusting the stack. */
28508 if (info->vrsave_size != 0
28509 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28510 || (DEFAULT_ABI != ABI_V4
28511 && offset_below_red_zone_p (info->vrsave_save_offset))))
28515 if (frame_reg_rtx == sp_reg_rtx)
28517 if (use_backchain_to_restore_sp)
28519 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28520 emit_move_insn (frame_reg_rtx,
28521 gen_rtx_MEM (Pmode, sp_reg_rtx));
28524 else if (frame_pointer_needed)
28525 frame_reg_rtx = hard_frame_pointer_rtx;
28528 reg = gen_rtx_REG (SImode, 12);
28529 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28530 info->vrsave_save_offset + frame_off));
28532 emit_insn (generate_set_vrsave (reg, info, 1));
28536 /* If we have a large stack frame, restore the old stack pointer
28537 using the backchain. */
28538 if (use_backchain_to_restore_sp)
28540 if (frame_reg_rtx == sp_reg_rtx)
28542 /* Under V.4, don't reset the stack pointer until after we're done
28543 loading the saved registers. */
28544 if (DEFAULT_ABI == ABI_V4)
28545 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28547 insn = emit_move_insn (frame_reg_rtx,
28548 gen_rtx_MEM (Pmode, sp_reg_rtx));
28551 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28552 && DEFAULT_ABI == ABI_V4)
28553 /* frame_reg_rtx has been set up by the altivec restore. */
28557 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28558 frame_reg_rtx = sp_reg_rtx;
28561 /* If we have a frame pointer, we can restore the old stack pointer
28563 else if (frame_pointer_needed)
28565 frame_reg_rtx = sp_reg_rtx;
28566 if (DEFAULT_ABI == ABI_V4)
28567 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28568 /* Prevent reordering memory accesses against stack pointer restore. */
28569 else if (cfun->calls_alloca
28570 || offset_below_red_zone_p (-info->total_size))
28571 rs6000_emit_stack_tie (frame_reg_rtx, true);
28573 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28574 GEN_INT (info->total_size)));
28577 else if (info->push_p
28578 && DEFAULT_ABI != ABI_V4
28579 && !crtl->calls_eh_return)
28581 /* Prevent reordering memory accesses against stack pointer restore. */
28582 if (cfun->calls_alloca
28583 || offset_below_red_zone_p (-info->total_size))
28584 rs6000_emit_stack_tie (frame_reg_rtx, false);
28585 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28586 GEN_INT (info->total_size)));
28589 if (insn && frame_reg_rtx == sp_reg_rtx)
28593 REG_NOTES (insn) = cfa_restores;
28594 cfa_restores = NULL_RTX;
28596 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28597 RTX_FRAME_RELATED_P (insn) = 1;
28600 /* Restore AltiVec registers if we have not done so already. */
28601 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28602 && info->altivec_size != 0
28603 && (DEFAULT_ABI == ABI_V4
28604 || !offset_below_red_zone_p (info->altivec_save_offset)))
28608 if ((strategy & REST_INLINE_VRS) == 0)
28610 int end_save = info->altivec_save_offset + info->altivec_size;
28612 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28613 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28614 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28616 if (end_save + frame_off != 0)
28618 rtx offset = GEN_INT (end_save + frame_off);
28620 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28623 emit_move_insn (ptr_reg, frame_reg_rtx);
28625 ptr_off = -end_save;
28626 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28627 info->altivec_save_offset + ptr_off,
28628 0, V4SImode, SAVRES_VR);
28629 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28631 /* Frame reg was clobbered by out-of-line save. Restore it
28632 from ptr_reg, and if we are calling out-of-line gpr or
28633 fpr restore set up the correct pointer and offset. */
28634 unsigned newptr_regno = 1;
28635 if (!restoring_GPRs_inline)
28637 bool lr = info->gp_save_offset + info->gp_size == 0;
28638 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28639 newptr_regno = ptr_regno_for_savres (sel);
28640 end_save = info->gp_save_offset + info->gp_size;
28642 else if (!restoring_FPRs_inline)
28644 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28645 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28646 newptr_regno = ptr_regno_for_savres (sel);
28647 end_save = info->fp_save_offset + info->fp_size;
28650 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28651 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28653 if (end_save + ptr_off != 0)
28655 rtx offset = GEN_INT (end_save + ptr_off);
28657 frame_off = -end_save;
28659 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28662 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28667 frame_off = ptr_off;
28668 emit_move_insn (frame_reg_rtx, ptr_reg);
28674 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28675 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28677 rtx addr, areg, mem, insn;
28678 rtx reg = gen_rtx_REG (V4SImode, i);
28679 HOST_WIDE_INT offset
28680 = (info->altivec_save_offset + frame_off
28681 + 16 * (i - info->first_altivec_reg_save));
28683 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28685 mem = gen_frame_mem (V4SImode,
28686 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28687 GEN_INT (offset)));
28688 insn = gen_rtx_SET (reg, mem);
28692 areg = gen_rtx_REG (Pmode, 0);
28693 emit_move_insn (areg, GEN_INT (offset));
28695 /* AltiVec addressing mode is [reg+reg]. */
28696 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28697 mem = gen_frame_mem (V4SImode, addr);
28699 /* Rather than emitting a generic move, force use of the
28700 lvx instruction, which we always want. In particular we
28701 don't want lxvd2x/xxpermdi for little endian. */
28702 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28705 (void) emit_insn (insn);
28709 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28710 if (((strategy & REST_INLINE_VRS) == 0
28711 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28712 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28715 rtx reg = gen_rtx_REG (V4SImode, i);
28716 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28720 /* Restore VRSAVE if we have not done so already. */
28721 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28722 && info->vrsave_size != 0
28723 && (DEFAULT_ABI == ABI_V4
28724 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28728 reg = gen_rtx_REG (SImode, 12);
28729 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28730 info->vrsave_save_offset + frame_off));
28732 emit_insn (generate_set_vrsave (reg, info, 1));
28735 /* If we exit by an out-of-line restore function on ABI_V4 then that
28736 function will deallocate the stack, so we don't need to worry
28737 about the unwinder restoring cr from an invalid stack frame
28739 exit_func = (!restoring_FPRs_inline
28740 || (!restoring_GPRs_inline
28741 && info->first_fp_reg_save == 64));
28743 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28744 *separate* slots if the routine calls __builtin_eh_return, so
28745 that they can be independently restored by the unwinder. */
28746 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28748 int i, cr_off = info->ehcr_offset;
28750 for (i = 0; i < 8; i++)
28751 if (!call_used_regs[CR0_REGNO + i])
28753 rtx reg = gen_rtx_REG (SImode, 0);
28754 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28755 cr_off + frame_off));
28757 insn = emit_insn (gen_movsi_to_cr_one
28758 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28760 if (!exit_func && flag_shrink_wrap)
28762 add_reg_note (insn, REG_CFA_RESTORE,
28763 gen_rtx_REG (SImode, CR0_REGNO + i));
28765 RTX_FRAME_RELATED_P (insn) = 1;
28768 cr_off += reg_size;
28772 /* Get the old lr if we saved it. If we are restoring registers
28773 out-of-line, then the out-of-line routines can do this for us. */
28774 if (restore_lr && restoring_GPRs_inline)
28775 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28777 /* Get the old cr if we saved it. */
28778 if (info->cr_save_p)
28780 unsigned cr_save_regno = 12;
28782 if (!restoring_GPRs_inline)
28784 /* Ensure we don't use the register used by the out-of-line
28785 gpr register restore below. */
28786 bool lr = info->gp_save_offset + info->gp_size == 0;
28787 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28788 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28790 if (gpr_ptr_regno == 12)
28791 cr_save_regno = 11;
28792 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28794 else if (REGNO (frame_reg_rtx) == 12)
28795 cr_save_regno = 11;
28797 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28798 info->cr_save_offset + frame_off,
28802 /* Set LR here to try to overlap restores below. */
28803 if (restore_lr && restoring_GPRs_inline)
28804 restore_saved_lr (0, exit_func);
28806 /* Load exception handler data registers, if needed. */
28807 if (crtl->calls_eh_return)
28809 unsigned int i, regno;
28813 rtx reg = gen_rtx_REG (reg_mode, 2);
28814 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28815 frame_off + RS6000_TOC_SAVE_SLOT));
28822 regno = EH_RETURN_DATA_REGNO (i);
28823 if (regno == INVALID_REGNUM)
28826 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28827 info->ehrd_offset + frame_off
28828 + reg_size * (int) i);
28830 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28834 /* Restore GPRs. This is done as a PARALLEL if we are using
28835 the load-multiple instructions. */
28836 if (!restoring_GPRs_inline)
28838 /* We are jumping to an out-of-line function. */
28840 int end_save = info->gp_save_offset + info->gp_size;
28841 bool can_use_exit = end_save == 0;
28842 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28845 /* Emit stack reset code if we need it. */
28846 ptr_regno = ptr_regno_for_savres (sel);
28847 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28849 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28850 else if (end_save + frame_off != 0)
28851 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28852 GEN_INT (end_save + frame_off)));
28853 else if (REGNO (frame_reg_rtx) != ptr_regno)
28854 emit_move_insn (ptr_reg, frame_reg_rtx);
28855 if (REGNO (frame_reg_rtx) == ptr_regno)
28856 frame_off = -end_save;
28858 if (can_use_exit && info->cr_save_p)
28859 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28861 ptr_off = -end_save;
28862 rs6000_emit_savres_rtx (info, ptr_reg,
28863 info->gp_save_offset + ptr_off,
28864 info->lr_save_offset + ptr_off,
28867 else if (using_load_multiple)
28870 p = rtvec_alloc (32 - info->first_gp_reg_save);
28871 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28873 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28875 info->gp_save_offset + frame_off + reg_size * i);
28876 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28880 int offset = info->gp_save_offset + frame_off;
28881 for (i = info->first_gp_reg_save; i < 32; i++)
28884 && !cfun->machine->gpr_is_wrapped_separately[i])
28886 rtx reg = gen_rtx_REG (reg_mode, i);
28887 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28890 offset += reg_size;
28894 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28896 /* If the frame pointer was used then we can't delay emitting
28897 a REG_CFA_DEF_CFA note. This must happen on the insn that
28898 restores the frame pointer, r31. We may have already emitted
28899 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28900 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28901 be harmless if emitted. */
28902 if (frame_pointer_needed)
28904 insn = get_last_insn ();
28905 add_reg_note (insn, REG_CFA_DEF_CFA,
28906 plus_constant (Pmode, frame_reg_rtx, frame_off));
28907 RTX_FRAME_RELATED_P (insn) = 1;
28910 /* Set up cfa_restores. We always need these when
28911 shrink-wrapping. If not shrink-wrapping then we only need
28912 the cfa_restore when the stack location is no longer valid.
28913 The cfa_restores must be emitted on or before the insn that
28914 invalidates the stack, and of course must not be emitted
28915 before the insn that actually does the restore. The latter
28916 is why it is a bad idea to emit the cfa_restores as a group
28917 on the last instruction here that actually does a restore:
28918 That insn may be reordered with respect to others doing
28920 if (flag_shrink_wrap
28921 && !restoring_GPRs_inline
28922 && info->first_fp_reg_save == 64)
28923 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28925 for (i = info->first_gp_reg_save; i < 32; i++)
28927 && !cfun->machine->gpr_is_wrapped_separately[i])
28929 rtx reg = gen_rtx_REG (reg_mode, i);
28930 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28934 if (!restoring_GPRs_inline
28935 && info->first_fp_reg_save == 64)
28937 /* We are jumping to an out-of-line function. */
28939 emit_cfa_restores (cfa_restores);
28943 if (restore_lr && !restoring_GPRs_inline)
28945 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28946 restore_saved_lr (0, exit_func);
28949 /* Restore fpr's if we need to do it without calling a function. */
28950 if (restoring_FPRs_inline)
28952 int offset = info->fp_save_offset + frame_off;
28953 for (i = info->first_fp_reg_save; i < 64; i++)
28956 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28958 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28959 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28960 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28961 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28965 offset += fp_reg_size;
28969 /* If we saved cr, restore it here. Just those that were used. */
28970 if (info->cr_save_p)
28971 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28973 /* If this is V.4, unwind the stack pointer after all of the loads
28974 have been done, or set up r11 if we are restoring fp out of line. */
28976 if (!restoring_FPRs_inline)
28978 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28979 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28980 ptr_regno = ptr_regno_for_savres (sel);
28983 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28984 if (REGNO (frame_reg_rtx) == ptr_regno)
28987 if (insn && restoring_FPRs_inline)
28991 REG_NOTES (insn) = cfa_restores;
28992 cfa_restores = NULL_RTX;
28994 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28995 RTX_FRAME_RELATED_P (insn) = 1;
28998 if (crtl->calls_eh_return)
29000 rtx sa = EH_RETURN_STACKADJ_RTX;
29001 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
29004 if (!sibcall && restoring_FPRs_inline)
29008 /* We can't hang the cfa_restores off a simple return,
29009 since the shrink-wrap code sometimes uses an existing
29010 return. This means there might be a path from
29011 pre-prologue code to this return, and dwarf2cfi code
29012 wants the eh_frame unwinder state to be the same on
29013 all paths to any point. So we need to emit the
29014 cfa_restores before the return. For -m64 we really
29015 don't need epilogue cfa_restores at all, except for
29016 this irritating dwarf2cfi with shrink-wrap
29017 requirement; The stack red-zone means eh_frame info
29018 from the prologue telling the unwinder to restore
29019 from the stack is perfectly good right to the end of
29021 emit_insn (gen_blockage ());
29022 emit_cfa_restores (cfa_restores);
29023 cfa_restores = NULL_RTX;
29026 emit_jump_insn (targetm.gen_simple_return ());
29029 if (!sibcall && !restoring_FPRs_inline)
29031 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29032 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
29034 RTVEC_ELT (p, elt++) = ret_rtx;
29036 RTVEC_ELT (p, elt++)
29037 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
29039 /* We have to restore more than two FP registers, so branch to the
29040 restore function. It will return to our caller. */
29045 if (flag_shrink_wrap)
29046 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
29048 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
29049 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
29050 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
29051 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
29053 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
29055 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
29057 RTVEC_ELT (p, elt++)
29058 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
29059 if (flag_shrink_wrap
29060 && save_reg_p (info->first_fp_reg_save + i))
29061 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29064 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
29070 /* Ensure the cfa_restores are hung off an insn that won't
29071 be reordered above other restores. */
29072 emit_insn (gen_blockage ());
29074 emit_cfa_restores (cfa_restores);
29078 /* Write function epilogue. */
29081 rs6000_output_function_epilogue (FILE *file)
29084 macho_branch_islands ();
29087 rtx_insn *insn = get_last_insn ();
29088 rtx_insn *deleted_debug_label = NULL;
29090 /* Mach-O doesn't support labels at the end of objects, so if
29091 it looks like we might want one, take special action.
29093 First, collect any sequence of deleted debug labels. */
29096 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
29098 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
29099 notes only, instead set their CODE_LABEL_NUMBER to -1,
29100 otherwise there would be code generation differences
29101 in between -g and -g0. */
29102 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29103 deleted_debug_label = insn;
29104 insn = PREV_INSN (insn);
29107 /* Second, if we have:
29110 then this needs to be detected, so skip past the barrier. */
29112 if (insn && BARRIER_P (insn))
29113 insn = PREV_INSN (insn);
29115 /* Up to now we've only seen notes or barriers. */
29120 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
29121 /* Trailing label: <barrier>. */
29122 fputs ("\tnop\n", file);
29125 /* Lastly, see if we have a completely empty function body. */
29126 while (insn && ! INSN_P (insn))
29127 insn = PREV_INSN (insn);
29128 /* If we don't find any insns, we've got an empty function body;
29129 I.e. completely empty - without a return or branch. This is
29130 taken as the case where a function body has been removed
29131 because it contains an inline __builtin_unreachable(). GCC
29132 states that reaching __builtin_unreachable() means UB so we're
29133 not obliged to do anything special; however, we want
29134 non-zero-sized function bodies. To meet this, and help the
29135 user out, let's trap the case. */
29137 fputs ("\ttrap\n", file);
29140 else if (deleted_debug_label)
29141 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
29142 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29143 CODE_LABEL_NUMBER (insn) = -1;
29147 /* Output a traceback table here. See /usr/include/sys/debug.h for info
29150 We don't output a traceback table if -finhibit-size-directive was
29151 used. The documentation for -finhibit-size-directive reads
29152 ``don't output a @code{.size} assembler directive, or anything
29153 else that would cause trouble if the function is split in the
29154 middle, and the two halves are placed at locations far apart in
29155 memory.'' The traceback table has this property, since it
29156 includes the offset from the start of the function to the
29157 traceback table itself.
29159 System V.4 Powerpc's (and the embedded ABI derived from it) use a
29160 different traceback table. */
29161 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29162 && ! flag_inhibit_size_directive
29163 && rs6000_traceback != traceback_none && !cfun->is_thunk)
29165 const char *fname = NULL;
29166 const char *language_string = lang_hooks.name;
29167 int fixed_parms = 0, float_parms = 0, parm_info = 0;
29169 int optional_tbtab;
29170 rs6000_stack_t *info = rs6000_stack_info ();
29172 if (rs6000_traceback == traceback_full)
29173 optional_tbtab = 1;
29174 else if (rs6000_traceback == traceback_part)
29175 optional_tbtab = 0;
29177 optional_tbtab = !optimize_size && !TARGET_ELF;
29179 if (optional_tbtab)
29181 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
29182 while (*fname == '.') /* V.4 encodes . in the name */
29185 /* Need label immediately before tbtab, so we can compute
29186 its offset from the function start. */
29187 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29188 ASM_OUTPUT_LABEL (file, fname);
29191 /* The .tbtab pseudo-op can only be used for the first eight
29192 expressions, since it can't handle the possibly variable
29193 length fields that follow. However, if you omit the optional
29194 fields, the assembler outputs zeros for all optional fields
29195 anyways, giving each variable length field is minimum length
29196 (as defined in sys/debug.h). Thus we can not use the .tbtab
29197 pseudo-op at all. */
29199 /* An all-zero word flags the start of the tbtab, for debuggers
29200 that have to find it by searching forward from the entry
29201 point or from the current pc. */
29202 fputs ("\t.long 0\n", file);
29204 /* Tbtab format type. Use format type 0. */
29205 fputs ("\t.byte 0,", file);
29207 /* Language type. Unfortunately, there does not seem to be any
29208 official way to discover the language being compiled, so we
29209 use language_string.
29210 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
29211 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
29212 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
29213 either, so for now use 0. */
29215 || ! strcmp (language_string, "GNU GIMPLE")
29216 || ! strcmp (language_string, "GNU Go")
29217 || ! strcmp (language_string, "libgccjit"))
29219 else if (! strcmp (language_string, "GNU F77")
29220 || lang_GNU_Fortran ())
29222 else if (! strcmp (language_string, "GNU Pascal"))
29224 else if (! strcmp (language_string, "GNU Ada"))
29226 else if (lang_GNU_CXX ()
29227 || ! strcmp (language_string, "GNU Objective-C++"))
29229 else if (! strcmp (language_string, "GNU Java"))
29231 else if (! strcmp (language_string, "GNU Objective-C"))
29234 gcc_unreachable ();
29235 fprintf (file, "%d,", i);
29237 /* 8 single bit fields: global linkage (not set for C extern linkage,
29238 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
29239 from start of procedure stored in tbtab, internal function, function
29240 has controlled storage, function has no toc, function uses fp,
29241 function logs/aborts fp operations. */
29242 /* Assume that fp operations are used if any fp reg must be saved. */
29243 fprintf (file, "%d,",
29244 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
29246 /* 6 bitfields: function is interrupt handler, name present in
29247 proc table, function calls alloca, on condition directives
29248 (controls stack walks, 3 bits), saves condition reg, saves
29250 /* The `function calls alloca' bit seems to be set whenever reg 31 is
29251 set up as a frame pointer, even when there is no alloca call. */
29252 fprintf (file, "%d,",
29253 ((optional_tbtab << 6)
29254 | ((optional_tbtab & frame_pointer_needed) << 5)
29255 | (info->cr_save_p << 1)
29256 | (info->lr_save_p)));
29258 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
29260 fprintf (file, "%d,",
29261 (info->push_p << 7) | (64 - info->first_fp_reg_save));
29263 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
29264 fprintf (file, "%d,", (32 - first_reg_to_save ()));
29266 if (optional_tbtab)
29268 /* Compute the parameter info from the function decl argument
29271 int next_parm_info_bit = 31;
29273 for (decl = DECL_ARGUMENTS (current_function_decl);
29274 decl; decl = DECL_CHAIN (decl))
29276 rtx parameter = DECL_INCOMING_RTL (decl);
29277 machine_mode mode = GET_MODE (parameter);
29279 if (GET_CODE (parameter) == REG)
29281 if (SCALAR_FLOAT_MODE_P (mode))
29304 gcc_unreachable ();
29307 /* If only one bit will fit, don't or in this entry. */
29308 if (next_parm_info_bit > 0)
29309 parm_info |= (bits << (next_parm_info_bit - 1));
29310 next_parm_info_bit -= 2;
29314 fixed_parms += ((GET_MODE_SIZE (mode)
29315 + (UNITS_PER_WORD - 1))
29317 next_parm_info_bit -= 1;
29323 /* Number of fixed point parameters. */
29324 /* This is actually the number of words of fixed point parameters; thus
29325 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29326 fprintf (file, "%d,", fixed_parms);
29328 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29330 /* This is actually the number of fp registers that hold parameters;
29331 and thus the maximum value is 13. */
29332 /* Set parameters on stack bit if parameters are not in their original
29333 registers, regardless of whether they are on the stack? Xlc
29334 seems to set the bit when not optimizing. */
29335 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
29337 if (optional_tbtab)
29339 /* Optional fields follow. Some are variable length. */
29341 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29342 float, 11 double float. */
29343 /* There is an entry for each parameter in a register, in the order
29344 that they occur in the parameter list. Any intervening arguments
29345 on the stack are ignored. If the list overflows a long (max
29346 possible length 34 bits) then completely leave off all elements
29348 /* Only emit this long if there was at least one parameter. */
29349 if (fixed_parms || float_parms)
29350 fprintf (file, "\t.long %d\n", parm_info);
29352 /* Offset from start of code to tb table. */
29353 fputs ("\t.long ", file);
29354 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29355 RS6000_OUTPUT_BASENAME (file, fname);
29357 rs6000_output_function_entry (file, fname);
29360 /* Interrupt handler mask. */
29361 /* Omit this long, since we never set the interrupt handler bit
29364 /* Number of CTL (controlled storage) anchors. */
29365 /* Omit this long, since the has_ctl bit is never set above. */
29367 /* Displacement into stack of each CTL anchor. */
29368 /* Omit this list of longs, because there are no CTL anchors. */
29370 /* Length of function name. */
29373 fprintf (file, "\t.short %d\n", (int) strlen (fname));
29375 /* Function name. */
29376 assemble_string (fname, strlen (fname));
29378 /* Register for alloca automatic storage; this is always reg 31.
29379 Only emit this if the alloca bit was set above. */
29380 if (frame_pointer_needed)
29381 fputs ("\t.byte 31\n", file);
29383 fputs ("\t.align 2\n", file);
29387 /* Arrange to define .LCTOC1 label, if not already done. */
29391 if (!toc_initialized)
29393 switch_to_section (toc_section);
29394 switch_to_section (current_function_section ());
29399 /* -fsplit-stack support. */
29401 /* A SYMBOL_REF for __morestack. */
29402 static GTY(()) rtx morestack_ref;
29405 gen_add3_const (rtx rt, rtx ra, long c)
29408 return gen_adddi3 (rt, ra, GEN_INT (c));
29410 return gen_addsi3 (rt, ra, GEN_INT (c));
29413 /* Emit -fsplit-stack prologue, which goes before the regular function
29414 prologue (at local entry point in the case of ELFv2). */
29417 rs6000_expand_split_stack_prologue (void)
29419 rs6000_stack_t *info = rs6000_stack_info ();
29420 unsigned HOST_WIDE_INT allocate;
29421 long alloc_hi, alloc_lo;
29422 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
29425 gcc_assert (flag_split_stack && reload_completed);
29430 if (global_regs[29])
29432 error ("%qs uses register r29", "-fsplit-stack");
29433 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29434 "conflicts with %qD", global_regs_decl[29]);
29437 allocate = info->total_size;
29438 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29440 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
29443 if (morestack_ref == NULL_RTX)
29445 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29446 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29447 | SYMBOL_FLAG_FUNCTION);
29450 r0 = gen_rtx_REG (Pmode, 0);
29451 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29452 r12 = gen_rtx_REG (Pmode, 12);
29453 emit_insn (gen_load_split_stack_limit (r0));
29454 /* Always emit two insns here to calculate the requested stack,
29455 so that the linker can edit them when adjusting size for calling
29456 non-split-stack code. */
29457 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29458 alloc_lo = -allocate - alloc_hi;
29461 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29463 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29465 emit_insn (gen_nop ());
29469 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29470 emit_insn (gen_nop ());
29473 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29474 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29475 ok_label = gen_label_rtx ();
29476 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29477 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29478 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29480 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29481 JUMP_LABEL (insn) = ok_label;
29482 /* Mark the jump as very likely to be taken. */
29483 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29485 lr = gen_rtx_REG (Pmode, LR_REGNO);
29486 insn = emit_move_insn (r0, lr);
29487 RTX_FRAME_RELATED_P (insn) = 1;
29488 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29489 RTX_FRAME_RELATED_P (insn) = 1;
29491 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29492 const0_rtx, const0_rtx));
29493 call_fusage = NULL_RTX;
29494 use_reg (&call_fusage, r12);
29495 /* Say the call uses r0, even though it doesn't, to stop regrename
29496 from twiddling with the insns saving lr, trashing args for cfun.
29497 The insns restoring lr are similarly protected by making
29498 split_stack_return use r0. */
29499 use_reg (&call_fusage, r0);
29500 add_function_usage_to (insn, call_fusage);
29501 /* Indicate that this function can't jump to non-local gotos. */
29502 make_reg_eh_region_note_nothrow_nononlocal (insn);
29503 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29504 insn = emit_move_insn (lr, r0);
29505 add_reg_note (insn, REG_CFA_RESTORE, lr);
29506 RTX_FRAME_RELATED_P (insn) = 1;
29507 emit_insn (gen_split_stack_return ());
29509 emit_label (ok_label);
29510 LABEL_NUSES (ok_label) = 1;
29513 /* Return the internal arg pointer used for function incoming
29514 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29515 to copy it to a pseudo in order for it to be preserved over calls
29516 and suchlike. We'd really like to use a pseudo here for the
29517 internal arg pointer but data-flow analysis is not prepared to
29518 accept pseudos as live at the beginning of a function. */
29521 rs6000_internal_arg_pointer (void)
29523 if (flag_split_stack
29524 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29528 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29532 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29533 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29535 /* Put the pseudo initialization right after the note at the
29536 beginning of the function. */
29537 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29538 gen_rtx_REG (Pmode, 12));
29539 push_topmost_sequence ();
29540 emit_insn_after (pat, get_insns ());
29541 pop_topmost_sequence ();
29543 return plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29544 FIRST_PARM_OFFSET (current_function_decl));
29546 return virtual_incoming_args_rtx;
29549 /* We may have to tell the dataflow pass that the split stack prologue
29550 is initializing a register. */
29553 rs6000_live_on_entry (bitmap regs)
29555 if (flag_split_stack)
29556 bitmap_set_bit (regs, 12);
29559 /* Emit -fsplit-stack dynamic stack allocation space check. */
29562 rs6000_split_stack_space_check (rtx size, rtx label)
29564 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29565 rtx limit = gen_reg_rtx (Pmode);
29566 rtx requested = gen_reg_rtx (Pmode);
29567 rtx cmp = gen_reg_rtx (CCUNSmode);
29570 emit_insn (gen_load_split_stack_limit (limit));
29571 if (CONST_INT_P (size))
29572 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29575 size = force_reg (Pmode, size);
29576 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29578 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29579 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29580 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29581 gen_rtx_LABEL_REF (VOIDmode, label),
29583 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29584 JUMP_LABEL (jump) = label;
29587 /* A C compound statement that outputs the assembler code for a thunk
29588 function, used to implement C++ virtual function calls with
29589 multiple inheritance. The thunk acts as a wrapper around a virtual
29590 function, adjusting the implicit object parameter before handing
29591 control off to the real function.
29593 First, emit code to add the integer DELTA to the location that
29594 contains the incoming first argument. Assume that this argument
29595 contains a pointer, and is the one used to pass the `this' pointer
29596 in C++. This is the incoming argument *before* the function
29597 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29598 values of all other incoming arguments.
29600 After the addition, emit code to jump to FUNCTION, which is a
29601 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29602 not touch the return address. Hence returning from FUNCTION will
29603 return to whoever called the current `thunk'.
29605 The effect must be as if FUNCTION had been called directly with the
29606 adjusted first argument. This macro is responsible for emitting
29607 all of the code for a thunk function; output_function_prologue()
29608 and output_function_epilogue() are not invoked.
29610 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29611 been extracted from it.) It might possibly be useful on some
29612 targets, but probably not.
29614 If you do not define this macro, the target-independent code in the
29615 C++ frontend will generate a less efficient heavyweight thunk that
29616 calls FUNCTION instead of jumping to it. The generic approach does
29617 not support varargs. */
29620 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29621 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29624 rtx this_rtx, funexp;
29627 reload_completed = 1;
29628 epilogue_completed = 1;
29630 /* Mark the end of the (empty) prologue. */
29631 emit_note (NOTE_INSN_PROLOGUE_END);
29633 /* Find the "this" pointer. If the function returns a structure,
29634 the structure return pointer is in r3. */
29635 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29636 this_rtx = gen_rtx_REG (Pmode, 4);
29638 this_rtx = gen_rtx_REG (Pmode, 3);
29640 /* Apply the constant offset, if required. */
29642 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29644 /* Apply the offset from the vtable, if required. */
29647 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29648 rtx tmp = gen_rtx_REG (Pmode, 12);
29650 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29651 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29653 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29654 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29658 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29660 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29662 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29665 /* Generate a tail call to the target function. */
29666 if (!TREE_USED (function))
29668 assemble_external (function);
29669 TREE_USED (function) = 1;
29671 funexp = XEXP (DECL_RTL (function), 0);
29672 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29675 if (MACHOPIC_INDIRECT)
29676 funexp = machopic_indirect_call_target (funexp);
29679 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29680 generate sibcall RTL explicitly. */
29681 insn = emit_call_insn (
29682 gen_rtx_PARALLEL (VOIDmode,
29684 gen_rtx_CALL (VOIDmode,
29685 funexp, const0_rtx),
29686 gen_rtx_USE (VOIDmode, const0_rtx),
29687 simple_return_rtx)));
29688 SIBLING_CALL_P (insn) = 1;
29691 /* Run just enough of rest_of_compilation to get the insns emitted.
29692 There's not really enough bulk here to make other passes such as
29693 instruction scheduling worth while. Note that use_thunk calls
29694 assemble_start_function and assemble_end_function. */
29695 insn = get_insns ();
29696 shorten_branches (insn);
29697 final_start_function (insn, file, 1);
29698 final (insn, file, 1);
29699 final_end_function ();
29701 reload_completed = 0;
29702 epilogue_completed = 0;
29705 /* A quick summary of the various types of 'constant-pool tables'
29708 Target Flags Name One table per
29709 AIX (none) AIX TOC object file
29710 AIX -mfull-toc AIX TOC object file
29711 AIX -mminimal-toc AIX minimal TOC translation unit
29712 SVR4/EABI (none) SVR4 SDATA object file
29713 SVR4/EABI -fpic SVR4 pic object file
29714 SVR4/EABI -fPIC SVR4 PIC translation unit
29715 SVR4/EABI -mrelocatable EABI TOC function
29716 SVR4/EABI -maix AIX TOC object file
29717 SVR4/EABI -maix -mminimal-toc
29718 AIX minimal TOC translation unit
29720 Name Reg. Set by entries contains:
29721 made by addrs? fp? sum?
29723 AIX TOC 2 crt0 as Y option option
29724 AIX minimal TOC 30 prolog gcc Y Y option
29725 SVR4 SDATA 13 crt0 gcc N Y N
29726 SVR4 pic 30 prolog ld Y not yet N
29727 SVR4 PIC 30 prolog gcc Y option option
29728 EABI TOC 30 prolog gcc Y option option
29732 /* Hash functions for the hash table. */
29735 rs6000_hash_constant (rtx k)
29737 enum rtx_code code = GET_CODE (k);
29738 machine_mode mode = GET_MODE (k);
29739 unsigned result = (code << 3) ^ mode;
29740 const char *format;
29743 format = GET_RTX_FORMAT (code);
29744 flen = strlen (format);
29750 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29752 case CONST_WIDE_INT:
29755 flen = CONST_WIDE_INT_NUNITS (k);
29756 for (i = 0; i < flen; i++)
29757 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29762 if (mode != VOIDmode)
29763 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29775 for (; fidx < flen; fidx++)
29776 switch (format[fidx])
29781 const char *str = XSTR (k, fidx);
29782 len = strlen (str);
29783 result = result * 613 + len;
29784 for (i = 0; i < len; i++)
29785 result = result * 613 + (unsigned) str[i];
29790 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29794 result = result * 613 + (unsigned) XINT (k, fidx);
29797 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29798 result = result * 613 + (unsigned) XWINT (k, fidx);
29802 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29803 result = result * 613 + (unsigned) (XWINT (k, fidx)
29810 gcc_unreachable ();
29817 toc_hasher::hash (toc_hash_struct *thc)
29819 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29822 /* Compare H1 and H2 for equivalence. */
29825 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29830 if (h1->key_mode != h2->key_mode)
29833 return rtx_equal_p (r1, r2);
29836 /* These are the names given by the C++ front-end to vtables, and
29837 vtable-like objects. Ideally, this logic should not be here;
29838 instead, there should be some programmatic way of inquiring as
29839 to whether or not an object is a vtable. */
29841 #define VTABLE_NAME_P(NAME) \
29842 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29843 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29844 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29845 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29846 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29848 #ifdef NO_DOLLAR_IN_LABEL
29849 /* Return a GGC-allocated character string translating dollar signs in
29850 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29853 rs6000_xcoff_strip_dollar (const char *name)
29859 q = (const char *) strchr (name, '$');
29861 if (q == 0 || q == name)
29864 len = strlen (name);
29865 strip = XALLOCAVEC (char, len + 1);
29866 strcpy (strip, name);
29867 p = strip + (q - name);
29871 p = strchr (p + 1, '$');
29874 return ggc_alloc_string (strip, len);
29879 rs6000_output_symbol_ref (FILE *file, rtx x)
29881 const char *name = XSTR (x, 0);
29883 /* Currently C++ toc references to vtables can be emitted before it
29884 is decided whether the vtable is public or private. If this is
29885 the case, then the linker will eventually complain that there is
29886 a reference to an unknown section. Thus, for vtables only,
29887 we emit the TOC reference to reference the identifier and not the
29889 if (VTABLE_NAME_P (name))
29891 RS6000_OUTPUT_BASENAME (file, name);
29894 assemble_name (file, name);
29897 /* Output a TOC entry. We derive the entry name from what is being
29901 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29904 const char *name = buf;
29906 HOST_WIDE_INT offset = 0;
29908 gcc_assert (!TARGET_NO_TOC);
29910 /* When the linker won't eliminate them, don't output duplicate
29911 TOC entries (this happens on AIX if there is any kind of TOC,
29912 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29914 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29916 struct toc_hash_struct *h;
29918 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29919 time because GGC is not initialized at that point. */
29920 if (toc_hash_table == NULL)
29921 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29923 h = ggc_alloc<toc_hash_struct> ();
29925 h->key_mode = mode;
29926 h->labelno = labelno;
29928 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29929 if (*found == NULL)
29931 else /* This is indeed a duplicate.
29932 Set this label equal to that label. */
29934 fputs ("\t.set ", file);
29935 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29936 fprintf (file, "%d,", labelno);
29937 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29938 fprintf (file, "%d\n", ((*found)->labelno));
29941 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
29942 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29943 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29945 fputs ("\t.set ", file);
29946 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29947 fprintf (file, "%d,", labelno);
29948 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29949 fprintf (file, "%d\n", ((*found)->labelno));
29956 /* If we're going to put a double constant in the TOC, make sure it's
29957 aligned properly when strict alignment is on. */
29958 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29959 && STRICT_ALIGNMENT
29960 && GET_MODE_BITSIZE (mode) >= 64
29961 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29962 ASM_OUTPUT_ALIGN (file, 3);
29965 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29967 /* Handle FP constants specially. Note that if we have a minimal
29968 TOC, things we put here aren't actually in the TOC, so we can allow
29970 if (GET_CODE (x) == CONST_DOUBLE &&
29971 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29972 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29976 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29977 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29979 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29983 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29984 fputs (DOUBLE_INT_ASM_OP, file);
29986 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29987 k[0] & 0xffffffff, k[1] & 0xffffffff,
29988 k[2] & 0xffffffff, k[3] & 0xffffffff);
29989 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29990 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29991 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29992 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29993 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29998 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29999 fputs ("\t.long ", file);
30001 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
30002 k[0] & 0xffffffff, k[1] & 0xffffffff,
30003 k[2] & 0xffffffff, k[3] & 0xffffffff);
30004 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
30005 k[0] & 0xffffffff, k[1] & 0xffffffff,
30006 k[2] & 0xffffffff, k[3] & 0xffffffff);
30010 else if (GET_CODE (x) == CONST_DOUBLE &&
30011 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
30015 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30016 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
30018 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30022 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30023 fputs (DOUBLE_INT_ASM_OP, file);
30025 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30026 k[0] & 0xffffffff, k[1] & 0xffffffff);
30027 fprintf (file, "0x%lx%08lx\n",
30028 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30029 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
30034 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30035 fputs ("\t.long ", file);
30037 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30038 k[0] & 0xffffffff, k[1] & 0xffffffff);
30039 fprintf (file, "0x%lx,0x%lx\n",
30040 k[0] & 0xffffffff, k[1] & 0xffffffff);
30044 else if (GET_CODE (x) == CONST_DOUBLE &&
30045 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
30049 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30050 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
30052 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
30056 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30057 fputs (DOUBLE_INT_ASM_OP, file);
30059 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30060 if (WORDS_BIG_ENDIAN)
30061 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
30063 fprintf (file, "0x%lx\n", l & 0xffffffff);
30068 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30069 fputs ("\t.long ", file);
30071 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30072 fprintf (file, "0x%lx\n", l & 0xffffffff);
30076 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
30078 unsigned HOST_WIDE_INT low;
30079 HOST_WIDE_INT high;
30081 low = INTVAL (x) & 0xffffffff;
30082 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
30084 /* TOC entries are always Pmode-sized, so when big-endian
30085 smaller integer constants in the TOC need to be padded.
30086 (This is still a win over putting the constants in
30087 a separate constant pool, because then we'd have
30088 to have both a TOC entry _and_ the actual constant.)
30090 For a 32-bit target, CONST_INT values are loaded and shifted
30091 entirely within `low' and can be stored in one TOC entry. */
30093 /* It would be easy to make this work, but it doesn't now. */
30094 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
30096 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
30099 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
30100 high = (HOST_WIDE_INT) low >> 32;
30106 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30107 fputs (DOUBLE_INT_ASM_OP, file);
30109 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30110 (long) high & 0xffffffff, (long) low & 0xffffffff);
30111 fprintf (file, "0x%lx%08lx\n",
30112 (long) high & 0xffffffff, (long) low & 0xffffffff);
30117 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
30119 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30120 fputs ("\t.long ", file);
30122 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30123 (long) high & 0xffffffff, (long) low & 0xffffffff);
30124 fprintf (file, "0x%lx,0x%lx\n",
30125 (long) high & 0xffffffff, (long) low & 0xffffffff);
30129 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30130 fputs ("\t.long ", file);
30132 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
30133 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
30139 if (GET_CODE (x) == CONST)
30141 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
30142 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
30144 base = XEXP (XEXP (x, 0), 0);
30145 offset = INTVAL (XEXP (XEXP (x, 0), 1));
30148 switch (GET_CODE (base))
30151 name = XSTR (base, 0);
30155 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
30156 CODE_LABEL_NUMBER (XEXP (base, 0)));
30160 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
30164 gcc_unreachable ();
30167 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30168 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
30171 fputs ("\t.tc ", file);
30172 RS6000_OUTPUT_BASENAME (file, name);
30175 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
30177 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
30179 /* Mark large TOC symbols on AIX with [TE] so they are mapped
30180 after other TOC symbols, reducing overflow of small TOC access
30181 to [TC] symbols. */
30182 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
30183 ? "[TE]," : "[TC],", file);
30186 /* Currently C++ toc references to vtables can be emitted before it
30187 is decided whether the vtable is public or private. If this is
30188 the case, then the linker will eventually complain that there is
30189 a TOC reference to an unknown section. Thus, for vtables only,
30190 we emit the TOC reference to reference the symbol and not the
30192 if (VTABLE_NAME_P (name))
30194 RS6000_OUTPUT_BASENAME (file, name);
30196 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
30197 else if (offset > 0)
30198 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
30201 output_addr_const (file, x);
30204 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
30206 switch (SYMBOL_REF_TLS_MODEL (base))
30210 case TLS_MODEL_LOCAL_EXEC:
30211 fputs ("@le", file);
30213 case TLS_MODEL_INITIAL_EXEC:
30214 fputs ("@ie", file);
30216 /* Use global-dynamic for local-dynamic. */
30217 case TLS_MODEL_GLOBAL_DYNAMIC:
30218 case TLS_MODEL_LOCAL_DYNAMIC:
30220 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
30221 fputs ("\t.tc .", file);
30222 RS6000_OUTPUT_BASENAME (file, name);
30223 fputs ("[TC],", file);
30224 output_addr_const (file, x);
30225 fputs ("@m", file);
30228 gcc_unreachable ();
30236 /* Output an assembler pseudo-op to write an ASCII string of N characters
30237 starting at P to FILE.
30239 On the RS/6000, we have to do this using the .byte operation and
30240 write out special characters outside the quoted string.
30241 Also, the assembler is broken; very long strings are truncated,
30242 so we must artificially break them up early. */
30245 output_ascii (FILE *file, const char *p, int n)
30248 int i, count_string;
30249 const char *for_string = "\t.byte \"";
30250 const char *for_decimal = "\t.byte ";
30251 const char *to_close = NULL;
30254 for (i = 0; i < n; i++)
30257 if (c >= ' ' && c < 0177)
30260 fputs (for_string, file);
30263 /* Write two quotes to get one. */
30271 for_decimal = "\"\n\t.byte ";
30275 if (count_string >= 512)
30277 fputs (to_close, file);
30279 for_string = "\t.byte \"";
30280 for_decimal = "\t.byte ";
30288 fputs (for_decimal, file);
30289 fprintf (file, "%d", c);
30291 for_string = "\n\t.byte \"";
30292 for_decimal = ", ";
30298 /* Now close the string if we have written one. Then end the line. */
30300 fputs (to_close, file);
30303 /* Generate a unique section name for FILENAME for a section type
30304 represented by SECTION_DESC. Output goes into BUF.
30306 SECTION_DESC can be any string, as long as it is different for each
30307 possible section type.
30309 We name the section in the same manner as xlc. The name begins with an
30310 underscore followed by the filename (after stripping any leading directory
30311 names) with the last period replaced by the string SECTION_DESC. If
30312 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30316 rs6000_gen_section_name (char **buf, const char *filename,
30317 const char *section_desc)
30319 const char *q, *after_last_slash, *last_period = 0;
30323 after_last_slash = filename;
30324 for (q = filename; *q; q++)
30327 after_last_slash = q + 1;
30328 else if (*q == '.')
30332 len = strlen (after_last_slash) + strlen (section_desc) + 2;
30333 *buf = (char *) xmalloc (len);
30338 for (q = after_last_slash; *q; q++)
30340 if (q == last_period)
30342 strcpy (p, section_desc);
30343 p += strlen (section_desc);
30347 else if (ISALNUM (*q))
30351 if (last_period == 0)
30352 strcpy (p, section_desc);
30357 /* Emit profile function. */
30360 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
30362 /* Non-standard profiling for kernels, which just saves LR then calls
30363 _mcount without worrying about arg saves. The idea is to change
30364 the function prologue as little as possible as it isn't easy to
30365 account for arg save/restore code added just for _mcount. */
30366 if (TARGET_PROFILE_KERNEL)
30369 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
30371 #ifndef NO_PROFILE_COUNTERS
30372 # define NO_PROFILE_COUNTERS 0
30374 if (NO_PROFILE_COUNTERS)
30375 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30376 LCT_NORMAL, VOIDmode);
30380 const char *label_name;
30383 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30384 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
30385 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
30387 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30388 LCT_NORMAL, VOIDmode, fun, Pmode);
30391 else if (DEFAULT_ABI == ABI_DARWIN)
30393 const char *mcount_name = RS6000_MCOUNT;
30394 int caller_addr_regno = LR_REGNO;
30396 /* Be conservative and always set this, at least for now. */
30397 crtl->uses_pic_offset_table = 1;
30400 /* For PIC code, set up a stub and collect the caller's address
30401 from r0, which is where the prologue puts it. */
30402 if (MACHOPIC_INDIRECT
30403 && crtl->uses_pic_offset_table)
30404 caller_addr_regno = 0;
30406 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
30407 LCT_NORMAL, VOIDmode,
30408 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
30412 /* Write function profiler code. */
30415 output_function_profiler (FILE *file, int labelno)
30419 switch (DEFAULT_ABI)
30422 gcc_unreachable ();
30427 warning (0, "no profiling of 64-bit code for this ABI");
30430 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30431 fprintf (file, "\tmflr %s\n", reg_names[0]);
30432 if (NO_PROFILE_COUNTERS)
30434 asm_fprintf (file, "\tstw %s,4(%s)\n",
30435 reg_names[0], reg_names[1]);
30437 else if (TARGET_SECURE_PLT && flag_pic)
30439 if (TARGET_LINK_STACK)
30442 get_ppc476_thunk_name (name);
30443 asm_fprintf (file, "\tbl %s\n", name);
30446 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30447 asm_fprintf (file, "\tstw %s,4(%s)\n",
30448 reg_names[0], reg_names[1]);
30449 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30450 asm_fprintf (file, "\taddis %s,%s,",
30451 reg_names[12], reg_names[12]);
30452 assemble_name (file, buf);
30453 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30454 assemble_name (file, buf);
30455 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30457 else if (flag_pic == 1)
30459 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30460 asm_fprintf (file, "\tstw %s,4(%s)\n",
30461 reg_names[0], reg_names[1]);
30462 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30463 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30464 assemble_name (file, buf);
30465 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30467 else if (flag_pic > 1)
30469 asm_fprintf (file, "\tstw %s,4(%s)\n",
30470 reg_names[0], reg_names[1]);
30471 /* Now, we need to get the address of the label. */
30472 if (TARGET_LINK_STACK)
30475 get_ppc476_thunk_name (name);
30476 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30477 assemble_name (file, buf);
30478 fputs ("-.\n1:", file);
30479 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30480 asm_fprintf (file, "\taddi %s,%s,4\n",
30481 reg_names[11], reg_names[11]);
30485 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30486 assemble_name (file, buf);
30487 fputs ("-.\n1:", file);
30488 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30490 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30491 reg_names[0], reg_names[11]);
30492 asm_fprintf (file, "\tadd %s,%s,%s\n",
30493 reg_names[0], reg_names[0], reg_names[11]);
30497 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30498 assemble_name (file, buf);
30499 fputs ("@ha\n", file);
30500 asm_fprintf (file, "\tstw %s,4(%s)\n",
30501 reg_names[0], reg_names[1]);
30502 asm_fprintf (file, "\tla %s,", reg_names[0]);
30503 assemble_name (file, buf);
30504 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30507 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30508 fprintf (file, "\tbl %s%s\n",
30509 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30515 /* Don't do anything, done in output_profile_hook (). */
30522 /* The following variable value is the last issued insn. */
30524 static rtx_insn *last_scheduled_insn;
30526 /* The following variable helps to balance issuing of load and
30527 store instructions */
30529 static int load_store_pendulum;
30531 /* The following variable helps pair divide insns during scheduling. */
30532 static int divide_cnt;
30533 /* The following variable helps pair and alternate vector and vector load
30534 insns during scheduling. */
30535 static int vec_pairing;
30538 /* Power4 load update and store update instructions are cracked into a
30539 load or store and an integer insn which are executed in the same cycle.
30540 Branches have their own dispatch slot which does not count against the
30541 GCC issue rate, but it changes the program flow so there are no other
30542 instructions to issue in this cycle. */
30545 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30547 last_scheduled_insn = insn;
30548 if (GET_CODE (PATTERN (insn)) == USE
30549 || GET_CODE (PATTERN (insn)) == CLOBBER)
30551 cached_can_issue_more = more;
30552 return cached_can_issue_more;
30555 if (insn_terminates_group_p (insn, current_group))
30557 cached_can_issue_more = 0;
30558 return cached_can_issue_more;
30561 /* If no reservation, but reach here */
30562 if (recog_memoized (insn) < 0)
30565 if (rs6000_sched_groups)
30567 if (is_microcoded_insn (insn))
30568 cached_can_issue_more = 0;
30569 else if (is_cracked_insn (insn))
30570 cached_can_issue_more = more > 2 ? more - 2 : 0;
30572 cached_can_issue_more = more - 1;
30574 return cached_can_issue_more;
30577 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30580 cached_can_issue_more = more - 1;
30581 return cached_can_issue_more;
30585 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30587 int r = rs6000_variable_issue_1 (insn, more);
30589 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30593 /* Adjust the cost of a scheduling dependency. Return the new cost of
30594 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30597 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30600 enum attr_type attr_type;
30602 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30609 /* Data dependency; DEP_INSN writes a register that INSN reads
30610 some cycles later. */
30612 /* Separate a load from a narrower, dependent store. */
30613 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30614 && GET_CODE (PATTERN (insn)) == SET
30615 && GET_CODE (PATTERN (dep_insn)) == SET
30616 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
30617 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
30618 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30619 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30622 attr_type = get_attr_type (insn);
30627 /* Tell the first scheduling pass about the latency between
30628 a mtctr and bctr (and mtlr and br/blr). The first
30629 scheduling pass will not know about this latency since
30630 the mtctr instruction, which has the latency associated
30631 to it, will be generated by reload. */
30634 /* Leave some extra cycles between a compare and its
30635 dependent branch, to inhibit expensive mispredicts. */
30636 if ((rs6000_tune == PROCESSOR_PPC603
30637 || rs6000_tune == PROCESSOR_PPC604
30638 || rs6000_tune == PROCESSOR_PPC604e
30639 || rs6000_tune == PROCESSOR_PPC620
30640 || rs6000_tune == PROCESSOR_PPC630
30641 || rs6000_tune == PROCESSOR_PPC750
30642 || rs6000_tune == PROCESSOR_PPC7400
30643 || rs6000_tune == PROCESSOR_PPC7450
30644 || rs6000_tune == PROCESSOR_PPCE5500
30645 || rs6000_tune == PROCESSOR_PPCE6500
30646 || rs6000_tune == PROCESSOR_POWER4
30647 || rs6000_tune == PROCESSOR_POWER5
30648 || rs6000_tune == PROCESSOR_POWER7
30649 || rs6000_tune == PROCESSOR_POWER8
30650 || rs6000_tune == PROCESSOR_POWER9
30651 || rs6000_tune == PROCESSOR_CELL)
30652 && recog_memoized (dep_insn)
30653 && (INSN_CODE (dep_insn) >= 0))
30655 switch (get_attr_type (dep_insn))
30658 case TYPE_FPCOMPARE:
30659 case TYPE_CR_LOGICAL:
30660 case TYPE_DELAYED_CR:
30664 if (get_attr_dot (dep_insn) == DOT_YES)
30669 if (get_attr_dot (dep_insn) == DOT_YES
30670 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30681 if ((rs6000_tune == PROCESSOR_POWER6)
30682 && recog_memoized (dep_insn)
30683 && (INSN_CODE (dep_insn) >= 0))
30686 if (GET_CODE (PATTERN (insn)) != SET)
30687 /* If this happens, we have to extend this to schedule
30688 optimally. Return default for now. */
30691 /* Adjust the cost for the case where the value written
30692 by a fixed point operation is used as the address
30693 gen value on a store. */
30694 switch (get_attr_type (dep_insn))
30699 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30700 return get_attr_sign_extend (dep_insn)
30701 == SIGN_EXTEND_YES ? 6 : 4;
30706 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30707 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30717 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30725 if (get_attr_update (dep_insn) == UPDATE_YES
30726 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30732 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30738 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30739 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30749 if ((rs6000_tune == PROCESSOR_POWER6)
30750 && recog_memoized (dep_insn)
30751 && (INSN_CODE (dep_insn) >= 0))
30754 /* Adjust the cost for the case where the value written
30755 by a fixed point instruction is used within the address
30756 gen portion of a subsequent load(u)(x) */
30757 switch (get_attr_type (dep_insn))
30762 if (set_to_load_agen (dep_insn, insn))
30763 return get_attr_sign_extend (dep_insn)
30764 == SIGN_EXTEND_YES ? 6 : 4;
30769 if (set_to_load_agen (dep_insn, insn))
30770 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30780 if (set_to_load_agen (dep_insn, insn))
30788 if (get_attr_update (dep_insn) == UPDATE_YES
30789 && set_to_load_agen (dep_insn, insn))
30795 if (set_to_load_agen (dep_insn, insn))
30801 if (set_to_load_agen (dep_insn, insn))
30802 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30812 if ((rs6000_tune == PROCESSOR_POWER6)
30813 && get_attr_update (insn) == UPDATE_NO
30814 && recog_memoized (dep_insn)
30815 && (INSN_CODE (dep_insn) >= 0)
30816 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30823 /* Fall out to return default cost. */
30827 case REG_DEP_OUTPUT:
30828 /* Output dependency; DEP_INSN writes a register that INSN writes some
30830 if ((rs6000_tune == PROCESSOR_POWER6)
30831 && recog_memoized (dep_insn)
30832 && (INSN_CODE (dep_insn) >= 0))
30834 attr_type = get_attr_type (insn);
30839 case TYPE_FPSIMPLE:
30840 if (get_attr_type (dep_insn) == TYPE_FP
30841 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30845 if (get_attr_update (insn) == UPDATE_NO
30846 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30853 /* Fall through, no cost for output dependency. */
30857 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30862 gcc_unreachable ();
30868 /* Debug version of rs6000_adjust_cost. */
30871 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30872 int cost, unsigned int dw)
30874 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30882 default: dep = "unknown depencency"; break;
30883 case REG_DEP_TRUE: dep = "data dependency"; break;
30884 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30885 case REG_DEP_ANTI: dep = "anti depencency"; break;
30889 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30890 "%s, insn:\n", ret, cost, dep);
30898 /* The function returns a true if INSN is microcoded.
30899 Return false otherwise. */
30902 is_microcoded_insn (rtx_insn *insn)
30904 if (!insn || !NONDEBUG_INSN_P (insn)
30905 || GET_CODE (PATTERN (insn)) == USE
30906 || GET_CODE (PATTERN (insn)) == CLOBBER)
30909 if (rs6000_tune == PROCESSOR_CELL)
30910 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30912 if (rs6000_sched_groups
30913 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30915 enum attr_type type = get_attr_type (insn);
30916 if ((type == TYPE_LOAD
30917 && get_attr_update (insn) == UPDATE_YES
30918 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30919 || ((type == TYPE_LOAD || type == TYPE_STORE)
30920 && get_attr_update (insn) == UPDATE_YES
30921 && get_attr_indexed (insn) == INDEXED_YES)
30922 || type == TYPE_MFCR)
30929 /* The function returns true if INSN is cracked into 2 instructions
30930 by the processor (and therefore occupies 2 issue slots). */
30933 is_cracked_insn (rtx_insn *insn)
30935 if (!insn || !NONDEBUG_INSN_P (insn)
30936 || GET_CODE (PATTERN (insn)) == USE
30937 || GET_CODE (PATTERN (insn)) == CLOBBER)
30940 if (rs6000_sched_groups
30941 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30943 enum attr_type type = get_attr_type (insn);
30944 if ((type == TYPE_LOAD
30945 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30946 && get_attr_update (insn) == UPDATE_NO)
30947 || (type == TYPE_LOAD
30948 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30949 && get_attr_update (insn) == UPDATE_YES
30950 && get_attr_indexed (insn) == INDEXED_NO)
30951 || (type == TYPE_STORE
30952 && get_attr_update (insn) == UPDATE_YES
30953 && get_attr_indexed (insn) == INDEXED_NO)
30954 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30955 && get_attr_update (insn) == UPDATE_YES)
30956 || type == TYPE_DELAYED_CR
30957 || (type == TYPE_EXTS
30958 && get_attr_dot (insn) == DOT_YES)
30959 || (type == TYPE_SHIFT
30960 && get_attr_dot (insn) == DOT_YES
30961 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30962 || (type == TYPE_MUL
30963 && get_attr_dot (insn) == DOT_YES)
30964 || type == TYPE_DIV
30965 || (type == TYPE_INSERT
30966 && get_attr_size (insn) == SIZE_32))
30973 /* The function returns true if INSN can be issued only from
30974 the branch slot. */
30977 is_branch_slot_insn (rtx_insn *insn)
30979 if (!insn || !NONDEBUG_INSN_P (insn)
30980 || GET_CODE (PATTERN (insn)) == USE
30981 || GET_CODE (PATTERN (insn)) == CLOBBER)
30984 if (rs6000_sched_groups)
30986 enum attr_type type = get_attr_type (insn);
30987 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30995 /* The function returns true if out_inst sets a value that is
30996 used in the address generation computation of in_insn */
30998 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
31000 rtx out_set, in_set;
31002 /* For performance reasons, only handle the simple case where
31003 both loads are a single_set. */
31004 out_set = single_set (out_insn);
31007 in_set = single_set (in_insn);
31009 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
31015 /* Try to determine base/offset/size parts of the given MEM.
31016 Return true if successful, false if all the values couldn't
31019 This function only looks for REG or REG+CONST address forms.
31020 REG+REG address form will return false. */
31023 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
31024 HOST_WIDE_INT *size)
31027 if MEM_SIZE_KNOWN_P (mem)
31028 *size = MEM_SIZE (mem);
31032 addr_rtx = (XEXP (mem, 0));
31033 if (GET_CODE (addr_rtx) == PRE_MODIFY)
31034 addr_rtx = XEXP (addr_rtx, 1);
31037 while (GET_CODE (addr_rtx) == PLUS
31038 && CONST_INT_P (XEXP (addr_rtx, 1)))
31040 *offset += INTVAL (XEXP (addr_rtx, 1));
31041 addr_rtx = XEXP (addr_rtx, 0);
31043 if (!REG_P (addr_rtx))
31050 /* The function returns true if the target storage location of
31051 mem1 is adjacent to the target storage location of mem2 */
31052 /* Return 1 if memory locations are adjacent. */
31055 adjacent_mem_locations (rtx mem1, rtx mem2)
31058 HOST_WIDE_INT off1, size1, off2, size2;
31060 if (get_memref_parts (mem1, ®1, &off1, &size1)
31061 && get_memref_parts (mem2, ®2, &off2, &size2))
31062 return ((REGNO (reg1) == REGNO (reg2))
31063 && ((off1 + size1 == off2)
31064 || (off2 + size2 == off1)));
31069 /* This function returns true if it can be determined that the two MEM
31070 locations overlap by at least 1 byte based on base reg/offset/size. */
31073 mem_locations_overlap (rtx mem1, rtx mem2)
31076 HOST_WIDE_INT off1, size1, off2, size2;
31078 if (get_memref_parts (mem1, ®1, &off1, &size1)
31079 && get_memref_parts (mem2, ®2, &off2, &size2))
31080 return ((REGNO (reg1) == REGNO (reg2))
31081 && (((off1 <= off2) && (off1 + size1 > off2))
31082 || ((off2 <= off1) && (off2 + size2 > off1))));
31087 /* A C statement (sans semicolon) to update the integer scheduling
31088 priority INSN_PRIORITY (INSN). Increase the priority to execute the
31089 INSN earlier, reduce the priority to execute INSN later. Do not
31090 define this macro if you do not need to adjust the scheduling
31091 priorities of insns. */
31094 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
31096 rtx load_mem, str_mem;
31097 /* On machines (like the 750) which have asymmetric integer units,
31098 where one integer unit can do multiply and divides and the other
31099 can't, reduce the priority of multiply/divide so it is scheduled
31100 before other integer operations. */
31103 if (! INSN_P (insn))
31106 if (GET_CODE (PATTERN (insn)) == USE)
31109 switch (rs6000_tune) {
31110 case PROCESSOR_PPC750:
31111 switch (get_attr_type (insn))
31118 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
31119 priority, priority);
31120 if (priority >= 0 && priority < 0x01000000)
31127 if (insn_must_be_first_in_group (insn)
31128 && reload_completed
31129 && current_sched_info->sched_max_insns_priority
31130 && rs6000_sched_restricted_insns_priority)
31133 /* Prioritize insns that can be dispatched only in the first
31135 if (rs6000_sched_restricted_insns_priority == 1)
31136 /* Attach highest priority to insn. This means that in
31137 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
31138 precede 'priority' (critical path) considerations. */
31139 return current_sched_info->sched_max_insns_priority;
31140 else if (rs6000_sched_restricted_insns_priority == 2)
31141 /* Increase priority of insn by a minimal amount. This means that in
31142 haifa-sched.c:ready_sort(), only 'priority' (critical path)
31143 considerations precede dispatch-slot restriction considerations. */
31144 return (priority + 1);
31147 if (rs6000_tune == PROCESSOR_POWER6
31148 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
31149 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
31150 /* Attach highest priority to insn if the scheduler has just issued two
31151 stores and this instruction is a load, or two loads and this instruction
31152 is a store. Power6 wants loads and stores scheduled alternately
31154 return current_sched_info->sched_max_insns_priority;
31159 /* Return true if the instruction is nonpipelined on the Cell. */
31161 is_nonpipeline_insn (rtx_insn *insn)
31163 enum attr_type type;
31164 if (!insn || !NONDEBUG_INSN_P (insn)
31165 || GET_CODE (PATTERN (insn)) == USE
31166 || GET_CODE (PATTERN (insn)) == CLOBBER)
31169 type = get_attr_type (insn);
31170 if (type == TYPE_MUL
31171 || type == TYPE_DIV
31172 || type == TYPE_SDIV
31173 || type == TYPE_DDIV
31174 || type == TYPE_SSQRT
31175 || type == TYPE_DSQRT
31176 || type == TYPE_MFCR
31177 || type == TYPE_MFCRF
31178 || type == TYPE_MFJMPR)
31186 /* Return how many instructions the machine can issue per cycle. */
31189 rs6000_issue_rate (void)
31191 /* Unless scheduling for register pressure, use issue rate of 1 for
31192 first scheduling pass to decrease degradation. */
31193 if (!reload_completed && !flag_sched_pressure)
31196 switch (rs6000_tune) {
31197 case PROCESSOR_RS64A:
31198 case PROCESSOR_PPC601: /* ? */
31199 case PROCESSOR_PPC7450:
31201 case PROCESSOR_PPC440:
31202 case PROCESSOR_PPC603:
31203 case PROCESSOR_PPC750:
31204 case PROCESSOR_PPC7400:
31205 case PROCESSOR_PPC8540:
31206 case PROCESSOR_PPC8548:
31207 case PROCESSOR_CELL:
31208 case PROCESSOR_PPCE300C2:
31209 case PROCESSOR_PPCE300C3:
31210 case PROCESSOR_PPCE500MC:
31211 case PROCESSOR_PPCE500MC64:
31212 case PROCESSOR_PPCE5500:
31213 case PROCESSOR_PPCE6500:
31214 case PROCESSOR_TITAN:
31216 case PROCESSOR_PPC476:
31217 case PROCESSOR_PPC604:
31218 case PROCESSOR_PPC604e:
31219 case PROCESSOR_PPC620:
31220 case PROCESSOR_PPC630:
31222 case PROCESSOR_POWER4:
31223 case PROCESSOR_POWER5:
31224 case PROCESSOR_POWER6:
31225 case PROCESSOR_POWER7:
31227 case PROCESSOR_POWER8:
31229 case PROCESSOR_POWER9:
31236 /* Return how many instructions to look ahead for better insn
31240 rs6000_use_sched_lookahead (void)
31242 switch (rs6000_tune)
31244 case PROCESSOR_PPC8540:
31245 case PROCESSOR_PPC8548:
31248 case PROCESSOR_CELL:
31249 return (reload_completed ? 8 : 0);
31256 /* We are choosing insn from the ready queue. Return zero if INSN can be
31259 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
31261 if (ready_index == 0)
31264 if (rs6000_tune != PROCESSOR_CELL)
31267 gcc_assert (insn != NULL_RTX && INSN_P (insn));
31269 if (!reload_completed
31270 || is_nonpipeline_insn (insn)
31271 || is_microcoded_insn (insn))
31277 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
31278 and return true. */
31281 find_mem_ref (rtx pat, rtx *mem_ref)
31286 /* stack_tie does not produce any real memory traffic. */
31287 if (tie_operand (pat, VOIDmode))
31290 if (GET_CODE (pat) == MEM)
31296 /* Recursively process the pattern. */
31297 fmt = GET_RTX_FORMAT (GET_CODE (pat));
31299 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
31303 if (find_mem_ref (XEXP (pat, i), mem_ref))
31306 else if (fmt[i] == 'E')
31307 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
31309 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
31317 /* Determine if PAT is a PATTERN of a load insn. */
31320 is_load_insn1 (rtx pat, rtx *load_mem)
31322 if (!pat || pat == NULL_RTX)
31325 if (GET_CODE (pat) == SET)
31326 return find_mem_ref (SET_SRC (pat), load_mem);
31328 if (GET_CODE (pat) == PARALLEL)
31332 for (i = 0; i < XVECLEN (pat, 0); i++)
31333 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
31340 /* Determine if INSN loads from memory. */
31343 is_load_insn (rtx insn, rtx *load_mem)
31345 if (!insn || !INSN_P (insn))
31351 return is_load_insn1 (PATTERN (insn), load_mem);
31354 /* Determine if PAT is a PATTERN of a store insn. */
31357 is_store_insn1 (rtx pat, rtx *str_mem)
31359 if (!pat || pat == NULL_RTX)
31362 if (GET_CODE (pat) == SET)
31363 return find_mem_ref (SET_DEST (pat), str_mem);
31365 if (GET_CODE (pat) == PARALLEL)
31369 for (i = 0; i < XVECLEN (pat, 0); i++)
31370 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
31377 /* Determine if INSN stores to memory. */
31380 is_store_insn (rtx insn, rtx *str_mem)
31382 if (!insn || !INSN_P (insn))
31385 return is_store_insn1 (PATTERN (insn), str_mem);
31388 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31391 is_power9_pairable_vec_type (enum attr_type type)
31395 case TYPE_VECSIMPLE:
31396 case TYPE_VECCOMPLEX:
31400 case TYPE_VECFLOAT:
31402 case TYPE_VECDOUBLE:
31410 /* Returns whether the dependence between INSN and NEXT is considered
31411 costly by the given target. */
31414 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
31418 rtx load_mem, str_mem;
31420 /* If the flag is not enabled - no dependence is considered costly;
31421 allow all dependent insns in the same group.
31422 This is the most aggressive option. */
31423 if (rs6000_sched_costly_dep == no_dep_costly)
31426 /* If the flag is set to 1 - a dependence is always considered costly;
31427 do not allow dependent instructions in the same group.
31428 This is the most conservative option. */
31429 if (rs6000_sched_costly_dep == all_deps_costly)
31432 insn = DEP_PRO (dep);
31433 next = DEP_CON (dep);
31435 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31436 && is_load_insn (next, &load_mem)
31437 && is_store_insn (insn, &str_mem))
31438 /* Prevent load after store in the same group. */
31441 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31442 && is_load_insn (next, &load_mem)
31443 && is_store_insn (insn, &str_mem)
31444 && DEP_TYPE (dep) == REG_DEP_TRUE
31445 && mem_locations_overlap(str_mem, load_mem))
31446 /* Prevent load after store in the same group if it is a true
31450 /* The flag is set to X; dependences with latency >= X are considered costly,
31451 and will not be scheduled in the same group. */
31452 if (rs6000_sched_costly_dep <= max_dep_latency
31453 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31459 /* Return the next insn after INSN that is found before TAIL is reached,
31460 skipping any "non-active" insns - insns that will not actually occupy
31461 an issue slot. Return NULL_RTX if such an insn is not found. */
31464 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31466 if (insn == NULL_RTX || insn == tail)
31471 insn = NEXT_INSN (insn);
31472 if (insn == NULL_RTX || insn == tail)
31476 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31477 || (NONJUMP_INSN_P (insn)
31478 && GET_CODE (PATTERN (insn)) != USE
31479 && GET_CODE (PATTERN (insn)) != CLOBBER
31480 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31486 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31489 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31494 enum attr_type type, type2;
31496 type = get_attr_type (last_scheduled_insn);
31498 /* Try to issue fixed point divides back-to-back in pairs so they will be
31499 routed to separate execution units and execute in parallel. */
31500 if (type == TYPE_DIV && divide_cnt == 0)
31502 /* First divide has been scheduled. */
31505 /* Scan the ready list looking for another divide, if found move it
31506 to the end of the list so it is chosen next. */
31510 if (recog_memoized (ready[pos]) >= 0
31511 && get_attr_type (ready[pos]) == TYPE_DIV)
31514 for (i = pos; i < lastpos; i++)
31515 ready[i] = ready[i + 1];
31516 ready[lastpos] = tmp;
31524 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31527 /* The best dispatch throughput for vector and vector load insns can be
31528 achieved by interleaving a vector and vector load such that they'll
31529 dispatch to the same superslice. If this pairing cannot be achieved
31530 then it is best to pair vector insns together and vector load insns
31533 To aid in this pairing, vec_pairing maintains the current state with
31534 the following values:
31536 0 : Initial state, no vecload/vector pairing has been started.
31538 1 : A vecload or vector insn has been issued and a candidate for
31539 pairing has been found and moved to the end of the ready
31541 if (type == TYPE_VECLOAD)
31543 /* Issued a vecload. */
31544 if (vec_pairing == 0)
31546 int vecload_pos = -1;
31547 /* We issued a single vecload, look for a vector insn to pair it
31548 with. If one isn't found, try to pair another vecload. */
31552 if (recog_memoized (ready[pos]) >= 0)
31554 type2 = get_attr_type (ready[pos]);
31555 if (is_power9_pairable_vec_type (type2))
31557 /* Found a vector insn to pair with, move it to the
31558 end of the ready list so it is scheduled next. */
31560 for (i = pos; i < lastpos; i++)
31561 ready[i] = ready[i + 1];
31562 ready[lastpos] = tmp;
31564 return cached_can_issue_more;
31566 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31567 /* Remember position of first vecload seen. */
31572 if (vecload_pos >= 0)
31574 /* Didn't find a vector to pair with but did find a vecload,
31575 move it to the end of the ready list. */
31576 tmp = ready[vecload_pos];
31577 for (i = vecload_pos; i < lastpos; i++)
31578 ready[i] = ready[i + 1];
31579 ready[lastpos] = tmp;
31581 return cached_can_issue_more;
31585 else if (is_power9_pairable_vec_type (type))
31587 /* Issued a vector operation. */
31588 if (vec_pairing == 0)
31591 /* We issued a single vector insn, look for a vecload to pair it
31592 with. If one isn't found, try to pair another vector. */
31596 if (recog_memoized (ready[pos]) >= 0)
31598 type2 = get_attr_type (ready[pos]);
31599 if (type2 == TYPE_VECLOAD)
31601 /* Found a vecload insn to pair with, move it to the
31602 end of the ready list so it is scheduled next. */
31604 for (i = pos; i < lastpos; i++)
31605 ready[i] = ready[i + 1];
31606 ready[lastpos] = tmp;
31608 return cached_can_issue_more;
31610 else if (is_power9_pairable_vec_type (type2)
31612 /* Remember position of first vector insn seen. */
31619 /* Didn't find a vecload to pair with but did find a vector
31620 insn, move it to the end of the ready list. */
31621 tmp = ready[vec_pos];
31622 for (i = vec_pos; i < lastpos; i++)
31623 ready[i] = ready[i + 1];
31624 ready[lastpos] = tmp;
31626 return cached_can_issue_more;
31631 /* We've either finished a vec/vecload pair, couldn't find an insn to
31632 continue the current pair, or the last insn had nothing to do with
31633 with pairing. In any case, reset the state. */
31637 return cached_can_issue_more;
31640 /* We are about to begin issuing insns for this clock cycle. */
31643 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31644 rtx_insn **ready ATTRIBUTE_UNUSED,
31645 int *pn_ready ATTRIBUTE_UNUSED,
31646 int clock_var ATTRIBUTE_UNUSED)
31648 int n_ready = *pn_ready;
31651 fprintf (dump, "// rs6000_sched_reorder :\n");
31653 /* Reorder the ready list, if the second to last ready insn
31654 is a nonepipeline insn. */
31655 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31657 if (is_nonpipeline_insn (ready[n_ready - 1])
31658 && (recog_memoized (ready[n_ready - 2]) > 0))
31659 /* Simply swap first two insns. */
31660 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31663 if (rs6000_tune == PROCESSOR_POWER6)
31664 load_store_pendulum = 0;
31666 return rs6000_issue_rate ();
31669 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31672 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31673 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31676 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31678 /* For Power6, we need to handle some special cases to try and keep the
31679 store queue from overflowing and triggering expensive flushes.
31681 This code monitors how load and store instructions are being issued
31682 and skews the ready list one way or the other to increase the likelihood
31683 that a desired instruction is issued at the proper time.
31685 A couple of things are done. First, we maintain a "load_store_pendulum"
31686 to track the current state of load/store issue.
31688 - If the pendulum is at zero, then no loads or stores have been
31689 issued in the current cycle so we do nothing.
31691 - If the pendulum is 1, then a single load has been issued in this
31692 cycle and we attempt to locate another load in the ready list to
31695 - If the pendulum is -2, then two stores have already been
31696 issued in this cycle, so we increase the priority of the first load
31697 in the ready list to increase it's likelihood of being chosen first
31700 - If the pendulum is -1, then a single store has been issued in this
31701 cycle and we attempt to locate another store in the ready list to
31702 issue with it, preferring a store to an adjacent memory location to
31703 facilitate store pairing in the store queue.
31705 - If the pendulum is 2, then two loads have already been
31706 issued in this cycle, so we increase the priority of the first store
31707 in the ready list to increase it's likelihood of being chosen first
31710 - If the pendulum < -2 or > 2, then do nothing.
31712 Note: This code covers the most common scenarios. There exist non
31713 load/store instructions which make use of the LSU and which
31714 would need to be accounted for to strictly model the behavior
31715 of the machine. Those instructions are currently unaccounted
31716 for to help minimize compile time overhead of this code.
31718 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31723 rtx load_mem, str_mem;
31725 if (is_store_insn (last_scheduled_insn, &str_mem))
31726 /* Issuing a store, swing the load_store_pendulum to the left */
31727 load_store_pendulum--;
31728 else if (is_load_insn (last_scheduled_insn, &load_mem))
31729 /* Issuing a load, swing the load_store_pendulum to the right */
31730 load_store_pendulum++;
31732 return cached_can_issue_more;
31734 /* If the pendulum is balanced, or there is only one instruction on
31735 the ready list, then all is well, so return. */
31736 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31737 return cached_can_issue_more;
31739 if (load_store_pendulum == 1)
31741 /* A load has been issued in this cycle. Scan the ready list
31742 for another load to issue with it */
31747 if (is_load_insn (ready[pos], &load_mem))
31749 /* Found a load. Move it to the head of the ready list,
31750 and adjust it's priority so that it is more likely to
31753 for (i=pos; i<*pn_ready-1; i++)
31754 ready[i] = ready[i + 1];
31755 ready[*pn_ready-1] = tmp;
31757 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31758 INSN_PRIORITY (tmp)++;
31764 else if (load_store_pendulum == -2)
31766 /* Two stores have been issued in this cycle. Increase the
31767 priority of the first load in the ready list to favor it for
31768 issuing in the next cycle. */
31773 if (is_load_insn (ready[pos], &load_mem)
31775 && INSN_PRIORITY_KNOWN (ready[pos]))
31777 INSN_PRIORITY (ready[pos])++;
31779 /* Adjust the pendulum to account for the fact that a load
31780 was found and increased in priority. This is to prevent
31781 increasing the priority of multiple loads */
31782 load_store_pendulum--;
31789 else if (load_store_pendulum == -1)
31791 /* A store has been issued in this cycle. Scan the ready list for
31792 another store to issue with it, preferring a store to an adjacent
31794 int first_store_pos = -1;
31800 if (is_store_insn (ready[pos], &str_mem))
31803 /* Maintain the index of the first store found on the
31805 if (first_store_pos == -1)
31806 first_store_pos = pos;
31808 if (is_store_insn (last_scheduled_insn, &str_mem2)
31809 && adjacent_mem_locations (str_mem, str_mem2))
31811 /* Found an adjacent store. Move it to the head of the
31812 ready list, and adjust it's priority so that it is
31813 more likely to stay there */
31815 for (i=pos; i<*pn_ready-1; i++)
31816 ready[i] = ready[i + 1];
31817 ready[*pn_ready-1] = tmp;
31819 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31820 INSN_PRIORITY (tmp)++;
31822 first_store_pos = -1;
31830 if (first_store_pos >= 0)
31832 /* An adjacent store wasn't found, but a non-adjacent store was,
31833 so move the non-adjacent store to the front of the ready
31834 list, and adjust its priority so that it is more likely to
31836 tmp = ready[first_store_pos];
31837 for (i=first_store_pos; i<*pn_ready-1; i++)
31838 ready[i] = ready[i + 1];
31839 ready[*pn_ready-1] = tmp;
31840 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31841 INSN_PRIORITY (tmp)++;
31844 else if (load_store_pendulum == 2)
31846 /* Two loads have been issued in this cycle. Increase the priority
31847 of the first store in the ready list to favor it for issuing in
31853 if (is_store_insn (ready[pos], &str_mem)
31855 && INSN_PRIORITY_KNOWN (ready[pos]))
31857 INSN_PRIORITY (ready[pos])++;
31859 /* Adjust the pendulum to account for the fact that a store
31860 was found and increased in priority. This is to prevent
31861 increasing the priority of multiple stores */
31862 load_store_pendulum++;
31871 /* Do Power9 dependent reordering if necessary. */
31872 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31873 && recog_memoized (last_scheduled_insn) >= 0)
31874 return power9_sched_reorder2 (ready, *pn_ready - 1);
31876 return cached_can_issue_more;
31879 /* Return whether the presence of INSN causes a dispatch group termination
31880 of group WHICH_GROUP.
31882 If WHICH_GROUP == current_group, this function will return true if INSN
31883 causes the termination of the current group (i.e, the dispatch group to
31884 which INSN belongs). This means that INSN will be the last insn in the
31885 group it belongs to.
31887 If WHICH_GROUP == previous_group, this function will return true if INSN
31888 causes the termination of the previous group (i.e, the dispatch group that
31889 precedes the group to which INSN belongs). This means that INSN will be
31890 the first insn in the group it belongs to). */
31893 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31900 first = insn_must_be_first_in_group (insn);
31901 last = insn_must_be_last_in_group (insn);
31906 if (which_group == current_group)
31908 else if (which_group == previous_group)
31916 insn_must_be_first_in_group (rtx_insn *insn)
31918 enum attr_type type;
31922 || DEBUG_INSN_P (insn)
31923 || GET_CODE (PATTERN (insn)) == USE
31924 || GET_CODE (PATTERN (insn)) == CLOBBER)
31927 switch (rs6000_tune)
31929 case PROCESSOR_POWER5:
31930 if (is_cracked_insn (insn))
31933 case PROCESSOR_POWER4:
31934 if (is_microcoded_insn (insn))
31937 if (!rs6000_sched_groups)
31940 type = get_attr_type (insn);
31947 case TYPE_DELAYED_CR:
31948 case TYPE_CR_LOGICAL:
31961 case PROCESSOR_POWER6:
31962 type = get_attr_type (insn);
31971 case TYPE_FPCOMPARE:
31982 if (get_attr_dot (insn) == DOT_NO
31983 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31988 if (get_attr_size (insn) == SIZE_32)
31996 if (get_attr_update (insn) == UPDATE_YES)
32004 case PROCESSOR_POWER7:
32005 type = get_attr_type (insn);
32009 case TYPE_CR_LOGICAL:
32023 if (get_attr_dot (insn) == DOT_YES)
32028 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32029 || get_attr_update (insn) == UPDATE_YES)
32036 if (get_attr_update (insn) == UPDATE_YES)
32044 case PROCESSOR_POWER8:
32045 type = get_attr_type (insn);
32049 case TYPE_CR_LOGICAL:
32050 case TYPE_DELAYED_CR:
32058 case TYPE_VECSTORE:
32065 if (get_attr_dot (insn) == DOT_YES)
32070 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32071 || get_attr_update (insn) == UPDATE_YES)
32076 if (get_attr_update (insn) == UPDATE_YES
32077 && get_attr_indexed (insn) == INDEXED_YES)
32093 insn_must_be_last_in_group (rtx_insn *insn)
32095 enum attr_type type;
32099 || DEBUG_INSN_P (insn)
32100 || GET_CODE (PATTERN (insn)) == USE
32101 || GET_CODE (PATTERN (insn)) == CLOBBER)
32104 switch (rs6000_tune) {
32105 case PROCESSOR_POWER4:
32106 case PROCESSOR_POWER5:
32107 if (is_microcoded_insn (insn))
32110 if (is_branch_slot_insn (insn))
32114 case PROCESSOR_POWER6:
32115 type = get_attr_type (insn);
32123 case TYPE_FPCOMPARE:
32134 if (get_attr_dot (insn) == DOT_NO
32135 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32140 if (get_attr_size (insn) == SIZE_32)
32148 case PROCESSOR_POWER7:
32149 type = get_attr_type (insn);
32159 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32160 && get_attr_update (insn) == UPDATE_YES)
32165 if (get_attr_update (insn) == UPDATE_YES
32166 && get_attr_indexed (insn) == INDEXED_YES)
32174 case PROCESSOR_POWER8:
32175 type = get_attr_type (insn);
32187 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32188 && get_attr_update (insn) == UPDATE_YES)
32193 if (get_attr_update (insn) == UPDATE_YES
32194 && get_attr_indexed (insn) == INDEXED_YES)
32209 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
32210 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
32213 is_costly_group (rtx *group_insns, rtx next_insn)
32216 int issue_rate = rs6000_issue_rate ();
32218 for (i = 0; i < issue_rate; i++)
32220 sd_iterator_def sd_it;
32222 rtx insn = group_insns[i];
32227 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
32229 rtx next = DEP_CON (dep);
32231 if (next == next_insn
32232 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
32240 /* Utility of the function redefine_groups.
32241 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
32242 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
32243 to keep it "far" (in a separate group) from GROUP_INSNS, following
32244 one of the following schemes, depending on the value of the flag
32245 -minsert_sched_nops = X:
32246 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
32247 in order to force NEXT_INSN into a separate group.
32248 (2) X < sched_finish_regroup_exact: insert exactly X nops.
32249 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
32250 insertion (has a group just ended, how many vacant issue slots remain in the
32251 last group, and how many dispatch groups were encountered so far). */
32254 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
32255 rtx_insn *next_insn, bool *group_end, int can_issue_more,
32260 int issue_rate = rs6000_issue_rate ();
32261 bool end = *group_end;
32264 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
32265 return can_issue_more;
32267 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
32268 return can_issue_more;
32270 force = is_costly_group (group_insns, next_insn);
32272 return can_issue_more;
32274 if (sched_verbose > 6)
32275 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
32276 *group_count ,can_issue_more);
32278 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
32281 can_issue_more = 0;
32283 /* Since only a branch can be issued in the last issue_slot, it is
32284 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
32285 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
32286 in this case the last nop will start a new group and the branch
32287 will be forced to the new group. */
32288 if (can_issue_more && !is_branch_slot_insn (next_insn))
32291 /* Do we have a special group ending nop? */
32292 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
32293 || rs6000_tune == PROCESSOR_POWER8)
32295 nop = gen_group_ending_nop ();
32296 emit_insn_before (nop, next_insn);
32297 can_issue_more = 0;
32300 while (can_issue_more > 0)
32303 emit_insn_before (nop, next_insn);
32311 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
32313 int n_nops = rs6000_sched_insert_nops;
32315 /* Nops can't be issued from the branch slot, so the effective
32316 issue_rate for nops is 'issue_rate - 1'. */
32317 if (can_issue_more == 0)
32318 can_issue_more = issue_rate;
32320 if (can_issue_more == 0)
32322 can_issue_more = issue_rate - 1;
32325 for (i = 0; i < issue_rate; i++)
32327 group_insns[i] = 0;
32334 emit_insn_before (nop, next_insn);
32335 if (can_issue_more == issue_rate - 1) /* new group begins */
32338 if (can_issue_more == 0)
32340 can_issue_more = issue_rate - 1;
32343 for (i = 0; i < issue_rate; i++)
32345 group_insns[i] = 0;
32351 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32354 /* Is next_insn going to start a new group? */
32357 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32358 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32359 || (can_issue_more < issue_rate &&
32360 insn_terminates_group_p (next_insn, previous_group)));
32361 if (*group_end && end)
32364 if (sched_verbose > 6)
32365 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
32366 *group_count, can_issue_more);
32367 return can_issue_more;
32370 return can_issue_more;
32373 /* This function tries to synch the dispatch groups that the compiler "sees"
32374 with the dispatch groups that the processor dispatcher is expected to
32375 form in practice. It tries to achieve this synchronization by forcing the
32376 estimated processor grouping on the compiler (as opposed to the function
32377 'pad_goups' which tries to force the scheduler's grouping on the processor).
32379 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32380 examines the (estimated) dispatch groups that will be formed by the processor
32381 dispatcher. It marks these group boundaries to reflect the estimated
32382 processor grouping, overriding the grouping that the scheduler had marked.
32383 Depending on the value of the flag '-minsert-sched-nops' this function can
32384 force certain insns into separate groups or force a certain distance between
32385 them by inserting nops, for example, if there exists a "costly dependence"
32388 The function estimates the group boundaries that the processor will form as
32389 follows: It keeps track of how many vacant issue slots are available after
32390 each insn. A subsequent insn will start a new group if one of the following
32392 - no more vacant issue slots remain in the current dispatch group.
32393 - only the last issue slot, which is the branch slot, is vacant, but the next
32394 insn is not a branch.
32395 - only the last 2 or less issue slots, including the branch slot, are vacant,
32396 which means that a cracked insn (which occupies two issue slots) can't be
32397 issued in this group.
32398 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32399 start a new group. */
32402 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32405 rtx_insn *insn, *next_insn;
32407 int can_issue_more;
32410 int group_count = 0;
32414 issue_rate = rs6000_issue_rate ();
32415 group_insns = XALLOCAVEC (rtx, issue_rate);
32416 for (i = 0; i < issue_rate; i++)
32418 group_insns[i] = 0;
32420 can_issue_more = issue_rate;
32422 insn = get_next_active_insn (prev_head_insn, tail);
32425 while (insn != NULL_RTX)
32427 slot = (issue_rate - can_issue_more);
32428 group_insns[slot] = insn;
32430 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32431 if (insn_terminates_group_p (insn, current_group))
32432 can_issue_more = 0;
32434 next_insn = get_next_active_insn (insn, tail);
32435 if (next_insn == NULL_RTX)
32436 return group_count + 1;
32438 /* Is next_insn going to start a new group? */
32440 = (can_issue_more == 0
32441 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32442 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32443 || (can_issue_more < issue_rate &&
32444 insn_terminates_group_p (next_insn, previous_group)));
32446 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32447 next_insn, &group_end, can_issue_more,
32453 can_issue_more = 0;
32454 for (i = 0; i < issue_rate; i++)
32456 group_insns[i] = 0;
32460 if (GET_MODE (next_insn) == TImode && can_issue_more)
32461 PUT_MODE (next_insn, VOIDmode);
32462 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32463 PUT_MODE (next_insn, TImode);
32466 if (can_issue_more == 0)
32467 can_issue_more = issue_rate;
32470 return group_count;
32473 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32474 dispatch group boundaries that the scheduler had marked. Pad with nops
32475 any dispatch groups which have vacant issue slots, in order to force the
32476 scheduler's grouping on the processor dispatcher. The function
32477 returns the number of dispatch groups found. */
32480 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32483 rtx_insn *insn, *next_insn;
32486 int can_issue_more;
32488 int group_count = 0;
32490 /* Initialize issue_rate. */
32491 issue_rate = rs6000_issue_rate ();
32492 can_issue_more = issue_rate;
32494 insn = get_next_active_insn (prev_head_insn, tail);
32495 next_insn = get_next_active_insn (insn, tail);
32497 while (insn != NULL_RTX)
32500 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32502 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32504 if (next_insn == NULL_RTX)
32509 /* If the scheduler had marked group termination at this location
32510 (between insn and next_insn), and neither insn nor next_insn will
32511 force group termination, pad the group with nops to force group
32514 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32515 && !insn_terminates_group_p (insn, current_group)
32516 && !insn_terminates_group_p (next_insn, previous_group))
32518 if (!is_branch_slot_insn (next_insn))
32521 while (can_issue_more)
32524 emit_insn_before (nop, next_insn);
32529 can_issue_more = issue_rate;
32534 next_insn = get_next_active_insn (insn, tail);
32537 return group_count;
32540 /* We're beginning a new block. Initialize data structures as necessary. */
32543 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32544 int sched_verbose ATTRIBUTE_UNUSED,
32545 int max_ready ATTRIBUTE_UNUSED)
32547 last_scheduled_insn = NULL;
32548 load_store_pendulum = 0;
32553 /* The following function is called at the end of scheduling BB.
32554 After reload, it inserts nops at insn group bundling. */
32557 rs6000_sched_finish (FILE *dump, int sched_verbose)
32562 fprintf (dump, "=== Finishing schedule.\n");
32564 if (reload_completed && rs6000_sched_groups)
32566 /* Do not run sched_finish hook when selective scheduling enabled. */
32567 if (sel_sched_p ())
32570 if (rs6000_sched_insert_nops == sched_finish_none)
32573 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32574 n_groups = pad_groups (dump, sched_verbose,
32575 current_sched_info->prev_head,
32576 current_sched_info->next_tail);
32578 n_groups = redefine_groups (dump, sched_verbose,
32579 current_sched_info->prev_head,
32580 current_sched_info->next_tail);
32582 if (sched_verbose >= 6)
32584 fprintf (dump, "ngroups = %d\n", n_groups);
32585 print_rtl (dump, current_sched_info->prev_head);
32586 fprintf (dump, "Done finish_sched\n");
32591 struct rs6000_sched_context
32593 short cached_can_issue_more;
32594 rtx_insn *last_scheduled_insn;
32595 int load_store_pendulum;
32600 typedef struct rs6000_sched_context rs6000_sched_context_def;
32601 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32603 /* Allocate store for new scheduling context. */
32605 rs6000_alloc_sched_context (void)
32607 return xmalloc (sizeof (rs6000_sched_context_def));
32610 /* If CLEAN_P is true then initializes _SC with clean data,
32611 and from the global context otherwise. */
32613 rs6000_init_sched_context (void *_sc, bool clean_p)
32615 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32619 sc->cached_can_issue_more = 0;
32620 sc->last_scheduled_insn = NULL;
32621 sc->load_store_pendulum = 0;
32622 sc->divide_cnt = 0;
32623 sc->vec_pairing = 0;
32627 sc->cached_can_issue_more = cached_can_issue_more;
32628 sc->last_scheduled_insn = last_scheduled_insn;
32629 sc->load_store_pendulum = load_store_pendulum;
32630 sc->divide_cnt = divide_cnt;
32631 sc->vec_pairing = vec_pairing;
32635 /* Sets the global scheduling context to the one pointed to by _SC. */
32637 rs6000_set_sched_context (void *_sc)
32639 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32641 gcc_assert (sc != NULL);
32643 cached_can_issue_more = sc->cached_can_issue_more;
32644 last_scheduled_insn = sc->last_scheduled_insn;
32645 load_store_pendulum = sc->load_store_pendulum;
32646 divide_cnt = sc->divide_cnt;
32647 vec_pairing = sc->vec_pairing;
32652 rs6000_free_sched_context (void *_sc)
32654 gcc_assert (_sc != NULL);
32660 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32662 switch (get_attr_type (insn))
32677 /* Length in units of the trampoline for entering a nested function. */
32680 rs6000_trampoline_size (void)
32684 switch (DEFAULT_ABI)
32687 gcc_unreachable ();
32690 ret = (TARGET_32BIT) ? 12 : 24;
32694 gcc_assert (!TARGET_32BIT);
32700 ret = (TARGET_32BIT) ? 40 : 48;
32707 /* Emit RTL insns to initialize the variable parts of a trampoline.
32708 FNADDR is an RTX for the address of the function's pure code.
32709 CXT is an RTX for the static chain value for the function. */
32712 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32714 int regsize = (TARGET_32BIT) ? 4 : 8;
32715 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32716 rtx ctx_reg = force_reg (Pmode, cxt);
32717 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32719 switch (DEFAULT_ABI)
32722 gcc_unreachable ();
32724 /* Under AIX, just build the 3 word function descriptor */
32727 rtx fnmem, fn_reg, toc_reg;
32729 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32730 error ("you cannot take the address of a nested function if you use "
32731 "the %qs option", "-mno-pointers-to-nested-functions");
32733 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32734 fn_reg = gen_reg_rtx (Pmode);
32735 toc_reg = gen_reg_rtx (Pmode);
32737 /* Macro to shorten the code expansions below. */
32738 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32740 m_tramp = replace_equiv_address (m_tramp, addr);
32742 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32743 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32744 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32745 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32746 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32752 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32756 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32757 LCT_NORMAL, VOIDmode,
32759 GEN_INT (rs6000_trampoline_size ()), SImode,
32767 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32768 identifier as an argument, so the front end shouldn't look it up. */
32771 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32773 return is_attribute_p ("altivec", attr_id);
32776 /* Handle the "altivec" attribute. The attribute may have
32777 arguments as follows:
32779 __attribute__((altivec(vector__)))
32780 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32781 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32783 and may appear more than once (e.g., 'vector bool char') in a
32784 given declaration. */
32787 rs6000_handle_altivec_attribute (tree *node,
32788 tree name ATTRIBUTE_UNUSED,
32790 int flags ATTRIBUTE_UNUSED,
32791 bool *no_add_attrs)
32793 tree type = *node, result = NULL_TREE;
32797 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32798 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32799 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32802 while (POINTER_TYPE_P (type)
32803 || TREE_CODE (type) == FUNCTION_TYPE
32804 || TREE_CODE (type) == METHOD_TYPE
32805 || TREE_CODE (type) == ARRAY_TYPE)
32806 type = TREE_TYPE (type);
32808 mode = TYPE_MODE (type);
32810 /* Check for invalid AltiVec type qualifiers. */
32811 if (type == long_double_type_node)
32812 error ("use of %<long double%> in AltiVec types is invalid");
32813 else if (type == boolean_type_node)
32814 error ("use of boolean types in AltiVec types is invalid");
32815 else if (TREE_CODE (type) == COMPLEX_TYPE)
32816 error ("use of %<complex%> in AltiVec types is invalid");
32817 else if (DECIMAL_FLOAT_MODE_P (mode))
32818 error ("use of decimal floating point types in AltiVec types is invalid");
32819 else if (!TARGET_VSX)
32821 if (type == long_unsigned_type_node || type == long_integer_type_node)
32824 error ("use of %<long%> in AltiVec types is invalid for "
32825 "64-bit code without %qs", "-mvsx");
32826 else if (rs6000_warn_altivec_long)
32827 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32830 else if (type == long_long_unsigned_type_node
32831 || type == long_long_integer_type_node)
32832 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32834 else if (type == double_type_node)
32835 error ("use of %<double%> in AltiVec types is invalid without %qs",
32839 switch (altivec_type)
32842 unsigned_p = TYPE_UNSIGNED (type);
32846 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32849 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32852 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32855 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32858 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32860 case E_SFmode: result = V4SF_type_node; break;
32861 case E_DFmode: result = V2DF_type_node; break;
32862 /* If the user says 'vector int bool', we may be handed the 'bool'
32863 attribute _before_ the 'vector' attribute, and so select the
32864 proper type in the 'b' case below. */
32865 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32866 case E_V2DImode: case E_V2DFmode:
32874 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32875 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32876 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32877 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32884 case E_V8HImode: result = pixel_V8HI_type_node;
32890 /* Propagate qualifiers attached to the element type
32891 onto the vector type. */
32892 if (result && result != type && TYPE_QUALS (type))
32893 result = build_qualified_type (result, TYPE_QUALS (type));
32895 *no_add_attrs = true; /* No need to hang on to the attribute. */
32898 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32903 /* AltiVec defines four built-in scalar types that serve as vector
32904 elements; we must teach the compiler how to mangle them. */
32906 static const char *
32907 rs6000_mangle_type (const_tree type)
32909 type = TYPE_MAIN_VARIANT (type);
32911 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32912 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32915 if (type == bool_char_type_node) return "U6__boolc";
32916 if (type == bool_short_type_node) return "U6__bools";
32917 if (type == pixel_type_node) return "u7__pixel";
32918 if (type == bool_int_type_node) return "U6__booli";
32919 if (type == bool_long_type_node) return "U6__booll";
32921 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
32922 "g" for IBM extended double, no matter whether it is long double (using
32923 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
32924 if (TARGET_FLOAT128_TYPE)
32926 if (type == ieee128_float_type_node)
32927 return "U10__float128";
32929 if (TARGET_LONG_DOUBLE_128)
32931 if (type == long_double_type_node)
32932 return (TARGET_IEEEQUAD) ? "U10__float128" : "g";
32934 if (type == ibm128_float_type_node)
32939 /* Mangle IBM extended float long double as `g' (__float128) on
32940 powerpc*-linux where long-double-64 previously was the default. */
32941 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
32943 && TARGET_LONG_DOUBLE_128
32944 && !TARGET_IEEEQUAD)
32947 /* For all other types, use normal C++ mangling. */
32951 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32952 struct attribute_spec.handler. */
32955 rs6000_handle_longcall_attribute (tree *node, tree name,
32956 tree args ATTRIBUTE_UNUSED,
32957 int flags ATTRIBUTE_UNUSED,
32958 bool *no_add_attrs)
32960 if (TREE_CODE (*node) != FUNCTION_TYPE
32961 && TREE_CODE (*node) != FIELD_DECL
32962 && TREE_CODE (*node) != TYPE_DECL)
32964 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32966 *no_add_attrs = true;
32972 /* Set longcall attributes on all functions declared when
32973 rs6000_default_long_calls is true. */
32975 rs6000_set_default_type_attributes (tree type)
32977 if (rs6000_default_long_calls
32978 && (TREE_CODE (type) == FUNCTION_TYPE
32979 || TREE_CODE (type) == METHOD_TYPE))
32980 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32982 TYPE_ATTRIBUTES (type));
32985 darwin_set_default_type_attributes (type);
32989 /* Return a reference suitable for calling a function with the
32990 longcall attribute. */
32993 rs6000_longcall_ref (rtx call_ref)
32995 const char *call_name;
32998 if (GET_CODE (call_ref) != SYMBOL_REF)
33001 /* System V adds '.' to the internal name, so skip them. */
33002 call_name = XSTR (call_ref, 0);
33003 if (*call_name == '.')
33005 while (*call_name == '.')
33008 node = get_identifier (call_name);
33009 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
33012 return force_reg (Pmode, call_ref);
33015 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
33016 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
33019 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
33020 struct attribute_spec.handler. */
33022 rs6000_handle_struct_attribute (tree *node, tree name,
33023 tree args ATTRIBUTE_UNUSED,
33024 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
33027 if (DECL_P (*node))
33029 if (TREE_CODE (*node) == TYPE_DECL)
33030 type = &TREE_TYPE (*node);
33035 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
33036 || TREE_CODE (*type) == UNION_TYPE)))
33038 warning (OPT_Wattributes, "%qE attribute ignored", name);
33039 *no_add_attrs = true;
33042 else if ((is_attribute_p ("ms_struct", name)
33043 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
33044 || ((is_attribute_p ("gcc_struct", name)
33045 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
33047 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
33049 *no_add_attrs = true;
33056 rs6000_ms_bitfield_layout_p (const_tree record_type)
33058 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
33059 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
33060 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
33063 #ifdef USING_ELFOS_H
33065 /* A get_unnamed_section callback, used for switching to toc_section. */
33068 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33070 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33071 && TARGET_MINIMAL_TOC)
33073 if (!toc_initialized)
33075 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33076 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33077 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
33078 fprintf (asm_out_file, "\t.tc ");
33079 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
33080 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33081 fprintf (asm_out_file, "\n");
33083 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33084 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33085 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33086 fprintf (asm_out_file, " = .+32768\n");
33087 toc_initialized = 1;
33090 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33092 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33094 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33095 if (!toc_initialized)
33097 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33098 toc_initialized = 1;
33103 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33104 if (!toc_initialized)
33106 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33107 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33108 fprintf (asm_out_file, " = .+32768\n");
33109 toc_initialized = 1;
33114 /* Implement TARGET_ASM_INIT_SECTIONS. */
33117 rs6000_elf_asm_init_sections (void)
33120 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
33123 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
33124 SDATA2_SECTION_ASM_OP);
33127 /* Implement TARGET_SELECT_RTX_SECTION. */
33130 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
33131 unsigned HOST_WIDE_INT align)
33133 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33134 return toc_section;
33136 return default_elf_select_rtx_section (mode, x, align);
33139 /* For a SYMBOL_REF, set generic flags and then perform some
33140 target-specific processing.
33142 When the AIX ABI is requested on a non-AIX system, replace the
33143 function name with the real name (with a leading .) rather than the
33144 function descriptor name. This saves a lot of overriding code to
33145 read the prefixes. */
33147 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
33149 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
33151 default_encode_section_info (decl, rtl, first);
33154 && TREE_CODE (decl) == FUNCTION_DECL
33156 && DEFAULT_ABI == ABI_AIX)
33158 rtx sym_ref = XEXP (rtl, 0);
33159 size_t len = strlen (XSTR (sym_ref, 0));
33160 char *str = XALLOCAVEC (char, len + 2);
33162 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
33163 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
33168 compare_section_name (const char *section, const char *templ)
33172 len = strlen (templ);
33173 return (strncmp (section, templ, len) == 0
33174 && (section[len] == 0 || section[len] == '.'));
33178 rs6000_elf_in_small_data_p (const_tree decl)
33180 if (rs6000_sdata == SDATA_NONE)
33183 /* We want to merge strings, so we never consider them small data. */
33184 if (TREE_CODE (decl) == STRING_CST)
33187 /* Functions are never in the small data area. */
33188 if (TREE_CODE (decl) == FUNCTION_DECL)
33191 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
33193 const char *section = DECL_SECTION_NAME (decl);
33194 if (compare_section_name (section, ".sdata")
33195 || compare_section_name (section, ".sdata2")
33196 || compare_section_name (section, ".gnu.linkonce.s")
33197 || compare_section_name (section, ".sbss")
33198 || compare_section_name (section, ".sbss2")
33199 || compare_section_name (section, ".gnu.linkonce.sb")
33200 || strcmp (section, ".PPC.EMB.sdata0") == 0
33201 || strcmp (section, ".PPC.EMB.sbss0") == 0)
33206 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
33209 && size <= g_switch_value
33210 /* If it's not public, and we're not going to reference it there,
33211 there's no need to put it in the small data section. */
33212 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
33219 #endif /* USING_ELFOS_H */
33221 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
33224 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
33226 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
33229 /* Do not place thread-local symbols refs in the object blocks. */
33232 rs6000_use_blocks_for_decl_p (const_tree decl)
33234 return !DECL_THREAD_LOCAL_P (decl);
33237 /* Return a REG that occurs in ADDR with coefficient 1.
33238 ADDR can be effectively incremented by incrementing REG.
33240 r0 is special and we must not select it as an address
33241 register by this routine since our caller will try to
33242 increment the returned register via an "la" instruction. */
33245 find_addr_reg (rtx addr)
33247 while (GET_CODE (addr) == PLUS)
33249 if (GET_CODE (XEXP (addr, 0)) == REG
33250 && REGNO (XEXP (addr, 0)) != 0)
33251 addr = XEXP (addr, 0);
33252 else if (GET_CODE (XEXP (addr, 1)) == REG
33253 && REGNO (XEXP (addr, 1)) != 0)
33254 addr = XEXP (addr, 1);
33255 else if (CONSTANT_P (XEXP (addr, 0)))
33256 addr = XEXP (addr, 1);
33257 else if (CONSTANT_P (XEXP (addr, 1)))
33258 addr = XEXP (addr, 0);
33260 gcc_unreachable ();
33262 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
33267 rs6000_fatal_bad_address (rtx op)
33269 fatal_insn ("bad address", op);
33274 typedef struct branch_island_d {
33275 tree function_name;
33281 static vec<branch_island, va_gc> *branch_islands;
33283 /* Remember to generate a branch island for far calls to the given
33287 add_compiler_branch_island (tree label_name, tree function_name,
33290 branch_island bi = {function_name, label_name, line_number};
33291 vec_safe_push (branch_islands, bi);
33294 /* Generate far-jump branch islands for everything recorded in
33295 branch_islands. Invoked immediately after the last instruction of
33296 the epilogue has been emitted; the branch islands must be appended
33297 to, and contiguous with, the function body. Mach-O stubs are
33298 generated in machopic_output_stub(). */
33301 macho_branch_islands (void)
33305 while (!vec_safe_is_empty (branch_islands))
33307 branch_island *bi = &branch_islands->last ();
33308 const char *label = IDENTIFIER_POINTER (bi->label_name);
33309 const char *name = IDENTIFIER_POINTER (bi->function_name);
33310 char name_buf[512];
33311 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33312 if (name[0] == '*' || name[0] == '&')
33313 strcpy (name_buf, name+1);
33317 strcpy (name_buf+1, name);
33319 strcpy (tmp_buf, "\n");
33320 strcat (tmp_buf, label);
33321 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33322 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33323 dbxout_stabd (N_SLINE, bi->line_number);
33324 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33327 if (TARGET_LINK_STACK)
33330 get_ppc476_thunk_name (name);
33331 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
33332 strcat (tmp_buf, name);
33333 strcat (tmp_buf, "\n");
33334 strcat (tmp_buf, label);
33335 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33339 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
33340 strcat (tmp_buf, label);
33341 strcat (tmp_buf, "_pic\n");
33342 strcat (tmp_buf, label);
33343 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33346 strcat (tmp_buf, "\taddis r11,r11,ha16(");
33347 strcat (tmp_buf, name_buf);
33348 strcat (tmp_buf, " - ");
33349 strcat (tmp_buf, label);
33350 strcat (tmp_buf, "_pic)\n");
33352 strcat (tmp_buf, "\tmtlr r0\n");
33354 strcat (tmp_buf, "\taddi r12,r11,lo16(");
33355 strcat (tmp_buf, name_buf);
33356 strcat (tmp_buf, " - ");
33357 strcat (tmp_buf, label);
33358 strcat (tmp_buf, "_pic)\n");
33360 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
33364 strcat (tmp_buf, ":\nlis r12,hi16(");
33365 strcat (tmp_buf, name_buf);
33366 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
33367 strcat (tmp_buf, name_buf);
33368 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
33370 output_asm_insn (tmp_buf, 0);
33371 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33372 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33373 dbxout_stabd (N_SLINE, bi->line_number);
33374 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33375 branch_islands->pop ();
33379 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33380 already there or not. */
33383 no_previous_def (tree function_name)
33388 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33389 if (function_name == bi->function_name)
33394 /* GET_PREV_LABEL gets the label name from the previous definition of
33398 get_prev_label (tree function_name)
33403 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33404 if (function_name == bi->function_name)
33405 return bi->label_name;
33409 /* INSN is either a function call or a millicode call. It may have an
33410 unconditional jump in its delay slot.
33412 CALL_DEST is the routine we are calling. */
33415 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
33416 int cookie_operand_number)
33418 static char buf[256];
33419 if (darwin_emit_branch_islands
33420 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
33421 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
33424 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
33426 if (no_previous_def (funname))
33428 rtx label_rtx = gen_label_rtx ();
33429 char *label_buf, temp_buf[256];
33430 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
33431 CODE_LABEL_NUMBER (label_rtx));
33432 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
33433 labelname = get_identifier (label_buf);
33434 add_compiler_branch_island (labelname, funname, insn_line (insn));
33437 labelname = get_prev_label (funname);
33439 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
33440 instruction will reach 'foo', otherwise link as 'bl L42'".
33441 "L42" should be a 'branch island', that will do a far jump to
33442 'foo'. Branch islands are generated in
33443 macho_branch_islands(). */
33444 sprintf (buf, "jbsr %%z%d,%.246s",
33445 dest_operand_number, IDENTIFIER_POINTER (labelname));
33448 sprintf (buf, "bl %%z%d", dest_operand_number);
33452 /* Generate PIC and indirect symbol stubs. */
33455 machopic_output_stub (FILE *file, const char *symb, const char *stub)
33457 unsigned int length;
33458 char *symbol_name, *lazy_ptr_name;
33459 char *local_label_0;
33460 static int label = 0;
33462 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33463 symb = (*targetm.strip_name_encoding) (symb);
33466 length = strlen (symb);
33467 symbol_name = XALLOCAVEC (char, length + 32);
33468 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33470 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33471 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33474 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33476 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33480 fprintf (file, "\t.align 5\n");
33482 fprintf (file, "%s:\n", stub);
33483 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33486 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33487 sprintf (local_label_0, "\"L%011d$spb\"", label);
33489 fprintf (file, "\tmflr r0\n");
33490 if (TARGET_LINK_STACK)
33493 get_ppc476_thunk_name (name);
33494 fprintf (file, "\tbl %s\n", name);
33495 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33499 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33500 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33502 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33503 lazy_ptr_name, local_label_0);
33504 fprintf (file, "\tmtlr r0\n");
33505 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33506 (TARGET_64BIT ? "ldu" : "lwzu"),
33507 lazy_ptr_name, local_label_0);
33508 fprintf (file, "\tmtctr r12\n");
33509 fprintf (file, "\tbctr\n");
33513 fprintf (file, "\t.align 4\n");
33515 fprintf (file, "%s:\n", stub);
33516 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33518 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33519 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33520 (TARGET_64BIT ? "ldu" : "lwzu"),
33522 fprintf (file, "\tmtctr r12\n");
33523 fprintf (file, "\tbctr\n");
33526 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33527 fprintf (file, "%s:\n", lazy_ptr_name);
33528 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33529 fprintf (file, "%sdyld_stub_binding_helper\n",
33530 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33533 /* Legitimize PIC addresses. If the address is already
33534 position-independent, we return ORIG. Newly generated
33535 position-independent addresses go into a reg. This is REG if non
33536 zero, otherwise we allocate register(s) as necessary. */
33538 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33541 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33546 if (reg == NULL && !reload_completed)
33547 reg = gen_reg_rtx (Pmode);
33549 if (GET_CODE (orig) == CONST)
33553 if (GET_CODE (XEXP (orig, 0)) == PLUS
33554 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33557 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33559 /* Use a different reg for the intermediate value, as
33560 it will be marked UNCHANGING. */
33561 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33562 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33565 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33568 if (GET_CODE (offset) == CONST_INT)
33570 if (SMALL_INT (offset))
33571 return plus_constant (Pmode, base, INTVAL (offset));
33572 else if (!reload_completed)
33573 offset = force_reg (Pmode, offset);
33576 rtx mem = force_const_mem (Pmode, orig);
33577 return machopic_legitimize_pic_address (mem, Pmode, reg);
33580 return gen_rtx_PLUS (Pmode, base, offset);
33583 /* Fall back on generic machopic code. */
33584 return machopic_legitimize_pic_address (orig, mode, reg);
33587 /* Output a .machine directive for the Darwin assembler, and call
33588 the generic start_file routine. */
33591 rs6000_darwin_file_start (void)
33593 static const struct
33597 HOST_WIDE_INT if_set;
33599 { "ppc64", "ppc64", MASK_64BIT },
33600 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33601 { "power4", "ppc970", 0 },
33602 { "G5", "ppc970", 0 },
33603 { "7450", "ppc7450", 0 },
33604 { "7400", "ppc7400", MASK_ALTIVEC },
33605 { "G4", "ppc7400", 0 },
33606 { "750", "ppc750", 0 },
33607 { "740", "ppc750", 0 },
33608 { "G3", "ppc750", 0 },
33609 { "604e", "ppc604e", 0 },
33610 { "604", "ppc604", 0 },
33611 { "603e", "ppc603", 0 },
33612 { "603", "ppc603", 0 },
33613 { "601", "ppc601", 0 },
33614 { NULL, "ppc", 0 } };
33615 const char *cpu_id = "";
33618 rs6000_file_start ();
33619 darwin_file_start ();
33621 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33623 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33624 cpu_id = rs6000_default_cpu;
33626 if (global_options_set.x_rs6000_cpu_index)
33627 cpu_id = processor_target_table[rs6000_cpu_index].name;
33629 /* Look through the mapping array. Pick the first name that either
33630 matches the argument, has a bit set in IF_SET that is also set
33631 in the target flags, or has a NULL name. */
33634 while (mapping[i].arg != NULL
33635 && strcmp (mapping[i].arg, cpu_id) != 0
33636 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33639 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33642 #endif /* TARGET_MACHO */
33646 rs6000_elf_reloc_rw_mask (void)
33650 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33656 /* Record an element in the table of global constructors. SYMBOL is
33657 a SYMBOL_REF of the function to be called; PRIORITY is a number
33658 between 0 and MAX_INIT_PRIORITY.
33660 This differs from default_named_section_asm_out_constructor in
33661 that we have special handling for -mrelocatable. */
33663 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33665 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33667 const char *section = ".ctors";
33670 if (priority != DEFAULT_INIT_PRIORITY)
33672 sprintf (buf, ".ctors.%.5u",
33673 /* Invert the numbering so the linker puts us in the proper
33674 order; constructors are run from right to left, and the
33675 linker sorts in increasing order. */
33676 MAX_INIT_PRIORITY - priority);
33680 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33681 assemble_align (POINTER_SIZE);
33683 if (DEFAULT_ABI == ABI_V4
33684 && (TARGET_RELOCATABLE || flag_pic > 1))
33686 fputs ("\t.long (", asm_out_file);
33687 output_addr_const (asm_out_file, symbol);
33688 fputs (")@fixup\n", asm_out_file);
33691 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33694 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33696 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33698 const char *section = ".dtors";
33701 if (priority != DEFAULT_INIT_PRIORITY)
33703 sprintf (buf, ".dtors.%.5u",
33704 /* Invert the numbering so the linker puts us in the proper
33705 order; constructors are run from right to left, and the
33706 linker sorts in increasing order. */
33707 MAX_INIT_PRIORITY - priority);
33711 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33712 assemble_align (POINTER_SIZE);
33714 if (DEFAULT_ABI == ABI_V4
33715 && (TARGET_RELOCATABLE || flag_pic > 1))
33717 fputs ("\t.long (", asm_out_file);
33718 output_addr_const (asm_out_file, symbol);
33719 fputs (")@fixup\n", asm_out_file);
33722 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33726 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33728 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33730 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33731 ASM_OUTPUT_LABEL (file, name);
33732 fputs (DOUBLE_INT_ASM_OP, file);
33733 rs6000_output_function_entry (file, name);
33734 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33737 fputs ("\t.size\t", file);
33738 assemble_name (file, name);
33739 fputs (",24\n\t.type\t.", file);
33740 assemble_name (file, name);
33741 fputs (",@function\n", file);
33742 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33744 fputs ("\t.globl\t.", file);
33745 assemble_name (file, name);
33750 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33751 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33752 rs6000_output_function_entry (file, name);
33753 fputs (":\n", file);
33758 if (DEFAULT_ABI == ABI_V4
33759 && (TARGET_RELOCATABLE || flag_pic > 1)
33760 && !TARGET_SECURE_PLT
33761 && (!constant_pool_empty_p () || crtl->profile)
33762 && (uses_toc = uses_TOC ()))
33767 switch_to_other_text_partition ();
33768 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33770 fprintf (file, "\t.long ");
33771 assemble_name (file, toc_label_name);
33774 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33775 assemble_name (file, buf);
33778 switch_to_other_text_partition ();
33781 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33782 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33784 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33788 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33790 fprintf (file, "\t.quad .TOC.-");
33791 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33792 assemble_name (file, buf);
33796 if (DEFAULT_ABI == ABI_AIX)
33798 const char *desc_name, *orig_name;
33800 orig_name = (*targetm.strip_name_encoding) (name);
33801 desc_name = orig_name;
33802 while (*desc_name == '.')
33805 if (TREE_PUBLIC (decl))
33806 fprintf (file, "\t.globl %s\n", desc_name);
33808 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33809 fprintf (file, "%s:\n", desc_name);
33810 fprintf (file, "\t.long %s\n", orig_name);
33811 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33812 fputs ("\t.long 0\n", file);
33813 fprintf (file, "\t.previous\n");
33815 ASM_OUTPUT_LABEL (file, name);
33818 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33820 rs6000_elf_file_end (void)
33822 #ifdef HAVE_AS_GNU_ATTRIBUTE
33823 /* ??? The value emitted depends on options active at file end.
33824 Assume anyone using #pragma or attributes that might change
33825 options knows what they are doing. */
33826 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33827 && rs6000_passes_float)
33833 else if (TARGET_SF_FPR)
33837 if (rs6000_passes_long_double)
33839 if (!TARGET_LONG_DOUBLE_128)
33841 else if (TARGET_IEEEQUAD)
33846 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33848 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33850 if (rs6000_passes_vector)
33851 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33852 (TARGET_ALTIVEC_ABI ? 2 : 1));
33853 if (rs6000_returns_struct)
33854 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33855 aix_struct_return ? 2 : 1);
33858 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33859 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33860 file_end_indicate_exec_stack ();
33863 if (flag_split_stack)
33864 file_end_indicate_split_stack ();
33868 /* We have expanded a CPU builtin, so we need to emit a reference to
33869 the special symbol that LIBC uses to declare it supports the
33870 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33871 switch_to_section (data_section);
33872 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33873 fprintf (asm_out_file, "\t%s %s\n",
33874 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33881 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33882 #define HAVE_XCOFF_DWARF_EXTRAS 0
33885 static enum unwind_info_type
33886 rs6000_xcoff_debug_unwind_info (void)
33892 rs6000_xcoff_asm_output_anchor (rtx symbol)
33896 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33897 SYMBOL_REF_BLOCK_OFFSET (symbol));
33898 fprintf (asm_out_file, "%s", SET_ASM_OP);
33899 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33900 fprintf (asm_out_file, ",");
33901 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33902 fprintf (asm_out_file, "\n");
33906 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33908 fputs (GLOBAL_ASM_OP, stream);
33909 RS6000_OUTPUT_BASENAME (stream, name);
33910 putc ('\n', stream);
33913 /* A get_unnamed_decl callback, used for read-only sections. PTR
33914 points to the section string variable. */
33917 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33919 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33920 *(const char *const *) directive,
33921 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33924 /* Likewise for read-write sections. */
33927 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33929 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33930 *(const char *const *) directive,
33931 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33935 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33937 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33938 *(const char *const *) directive,
33939 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33942 /* A get_unnamed_section callback, used for switching to toc_section. */
33945 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33947 if (TARGET_MINIMAL_TOC)
33949 /* toc_section is always selected at least once from
33950 rs6000_xcoff_file_start, so this is guaranteed to
33951 always be defined once and only once in each file. */
33952 if (!toc_initialized)
33954 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33955 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33956 toc_initialized = 1;
33958 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33959 (TARGET_32BIT ? "" : ",3"));
33962 fputs ("\t.toc\n", asm_out_file);
33965 /* Implement TARGET_ASM_INIT_SECTIONS. */
33968 rs6000_xcoff_asm_init_sections (void)
33970 read_only_data_section
33971 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33972 &xcoff_read_only_section_name);
33974 private_data_section
33975 = get_unnamed_section (SECTION_WRITE,
33976 rs6000_xcoff_output_readwrite_section_asm_op,
33977 &xcoff_private_data_section_name);
33980 = get_unnamed_section (SECTION_TLS,
33981 rs6000_xcoff_output_tls_section_asm_op,
33982 &xcoff_tls_data_section_name);
33984 tls_private_data_section
33985 = get_unnamed_section (SECTION_TLS,
33986 rs6000_xcoff_output_tls_section_asm_op,
33987 &xcoff_private_data_section_name);
33989 read_only_private_data_section
33990 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33991 &xcoff_private_data_section_name);
33994 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33996 readonly_data_section = read_only_data_section;
34000 rs6000_xcoff_reloc_rw_mask (void)
34006 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
34007 tree decl ATTRIBUTE_UNUSED)
34010 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
34012 if (flags & SECTION_EXCLUDE)
34014 else if (flags & SECTION_DEBUG)
34016 fprintf (asm_out_file, "\t.dwsect %s\n", name);
34019 else if (flags & SECTION_CODE)
34021 else if (flags & SECTION_TLS)
34023 else if (flags & SECTION_WRITE)
34028 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
34029 (flags & SECTION_CODE) ? "." : "",
34030 name, suffix[smclass], flags & SECTION_ENTSIZE);
34033 #define IN_NAMED_SECTION(DECL) \
34034 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
34035 && DECL_SECTION_NAME (DECL) != NULL)
34038 rs6000_xcoff_select_section (tree decl, int reloc,
34039 unsigned HOST_WIDE_INT align)
34041 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
34043 if (align > BIGGEST_ALIGNMENT)
34045 resolve_unique_section (decl, reloc, true);
34046 if (IN_NAMED_SECTION (decl))
34047 return get_named_section (decl, NULL, reloc);
34050 if (decl_readonly_section (decl, reloc))
34052 if (TREE_PUBLIC (decl))
34053 return read_only_data_section;
34055 return read_only_private_data_section;
34060 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34062 if (TREE_PUBLIC (decl))
34063 return tls_data_section;
34064 else if (bss_initializer_p (decl))
34066 /* Convert to COMMON to emit in BSS. */
34067 DECL_COMMON (decl) = 1;
34068 return tls_comm_section;
34071 return tls_private_data_section;
34075 if (TREE_PUBLIC (decl))
34076 return data_section;
34078 return private_data_section;
34083 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
34087 /* Use select_section for private data and uninitialized data with
34088 alignment <= BIGGEST_ALIGNMENT. */
34089 if (!TREE_PUBLIC (decl)
34090 || DECL_COMMON (decl)
34091 || (DECL_INITIAL (decl) == NULL_TREE
34092 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
34093 || DECL_INITIAL (decl) == error_mark_node
34094 || (flag_zero_initialized_in_bss
34095 && initializer_zerop (DECL_INITIAL (decl))))
34098 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
34099 name = (*targetm.strip_name_encoding) (name);
34100 set_decl_section_name (decl, name);
34103 /* Select section for constant in constant pool.
34105 On RS/6000, all constants are in the private read-only data area.
34106 However, if this is being placed in the TOC it must be output as a
34110 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
34111 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
34113 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
34114 return toc_section;
34116 return read_only_private_data_section;
34119 /* Remove any trailing [DS] or the like from the symbol name. */
34121 static const char *
34122 rs6000_xcoff_strip_name_encoding (const char *name)
34127 len = strlen (name);
34128 if (name[len - 1] == ']')
34129 return ggc_alloc_string (name, len - 4);
34134 /* Section attributes. AIX is always PIC. */
34136 static unsigned int
34137 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
34139 unsigned int align;
34140 unsigned int flags = default_section_type_flags (decl, name, reloc);
34142 /* Align to at least UNIT size. */
34143 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
34144 align = MIN_UNITS_PER_WORD;
34146 /* Increase alignment of large objects if not already stricter. */
34147 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
34148 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
34149 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
34151 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
34154 /* Output at beginning of assembler file.
34156 Initialize the section names for the RS/6000 at this point.
34158 Specify filename, including full path, to assembler.
34160 We want to go into the TOC section so at least one .toc will be emitted.
34161 Also, in order to output proper .bs/.es pairs, we need at least one static
34162 [RW] section emitted.
34164 Finally, declare mcount when profiling to make the assembler happy. */
34167 rs6000_xcoff_file_start (void)
34169 rs6000_gen_section_name (&xcoff_bss_section_name,
34170 main_input_filename, ".bss_");
34171 rs6000_gen_section_name (&xcoff_private_data_section_name,
34172 main_input_filename, ".rw_");
34173 rs6000_gen_section_name (&xcoff_read_only_section_name,
34174 main_input_filename, ".ro_");
34175 rs6000_gen_section_name (&xcoff_tls_data_section_name,
34176 main_input_filename, ".tls_");
34177 rs6000_gen_section_name (&xcoff_tbss_section_name,
34178 main_input_filename, ".tbss_[UL]");
34180 fputs ("\t.file\t", asm_out_file);
34181 output_quoted_string (asm_out_file, main_input_filename);
34182 fputc ('\n', asm_out_file);
34183 if (write_symbols != NO_DEBUG)
34184 switch_to_section (private_data_section);
34185 switch_to_section (toc_section);
34186 switch_to_section (text_section);
34188 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
34189 rs6000_file_start ();
34192 /* Output at end of assembler file.
34193 On the RS/6000, referencing data should automatically pull in text. */
34196 rs6000_xcoff_file_end (void)
34198 switch_to_section (text_section);
34199 fputs ("_section_.text:\n", asm_out_file);
34200 switch_to_section (data_section);
34201 fputs (TARGET_32BIT
34202 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
34206 struct declare_alias_data
34209 bool function_descriptor;
34212 /* Declare alias N. A helper function for for_node_and_aliases. */
34215 rs6000_declare_alias (struct symtab_node *n, void *d)
34217 struct declare_alias_data *data = (struct declare_alias_data *)d;
34218 /* Main symbol is output specially, because varasm machinery does part of
34219 the job for us - we do not need to declare .globl/lglobs and such. */
34220 if (!n->alias || n->weakref)
34223 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
34226 /* Prevent assemble_alias from trying to use .set pseudo operation
34227 that does not behave as expected by the middle-end. */
34228 TREE_ASM_WRITTEN (n->decl) = true;
34230 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
34231 char *buffer = (char *) alloca (strlen (name) + 2);
34233 int dollar_inside = 0;
34235 strcpy (buffer, name);
34236 p = strchr (buffer, '$');
34240 p = strchr (p + 1, '$');
34242 if (TREE_PUBLIC (n->decl))
34244 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
34246 if (dollar_inside) {
34247 if (data->function_descriptor)
34248 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34249 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34251 if (data->function_descriptor)
34253 fputs ("\t.globl .", data->file);
34254 RS6000_OUTPUT_BASENAME (data->file, buffer);
34255 putc ('\n', data->file);
34257 fputs ("\t.globl ", data->file);
34258 RS6000_OUTPUT_BASENAME (data->file, buffer);
34259 putc ('\n', data->file);
34261 #ifdef ASM_WEAKEN_DECL
34262 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
34263 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
34270 if (data->function_descriptor)
34271 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34272 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34274 if (data->function_descriptor)
34276 fputs ("\t.lglobl .", data->file);
34277 RS6000_OUTPUT_BASENAME (data->file, buffer);
34278 putc ('\n', data->file);
34280 fputs ("\t.lglobl ", data->file);
34281 RS6000_OUTPUT_BASENAME (data->file, buffer);
34282 putc ('\n', data->file);
34284 if (data->function_descriptor)
34285 fputs (".", data->file);
34286 RS6000_OUTPUT_BASENAME (data->file, buffer);
34287 fputs (":\n", data->file);
34292 #ifdef HAVE_GAS_HIDDEN
34293 /* Helper function to calculate visibility of a DECL
34294 and return the value as a const string. */
34296 static const char *
34297 rs6000_xcoff_visibility (tree decl)
34299 static const char * const visibility_types[] = {
34300 "", ",protected", ",hidden", ",internal"
34303 enum symbol_visibility vis = DECL_VISIBILITY (decl);
34305 if (TREE_CODE (decl) == FUNCTION_DECL
34306 && cgraph_node::get (decl)
34307 && cgraph_node::get (decl)->instrumentation_clone
34308 && cgraph_node::get (decl)->instrumented_version)
34309 vis = DECL_VISIBILITY (cgraph_node::get (decl)->instrumented_version->decl);
34311 return visibility_types[vis];
34316 /* This macro produces the initial definition of a function name.
34317 On the RS/6000, we need to place an extra '.' in the function name and
34318 output the function descriptor.
34319 Dollar signs are converted to underscores.
34321 The csect for the function will have already been created when
34322 text_section was selected. We do have to go back to that csect, however.
34324 The third and fourth parameters to the .function pseudo-op (16 and 044)
34325 are placeholders which no longer have any use.
34327 Because AIX assembler's .set command has unexpected semantics, we output
34328 all aliases as alternative labels in front of the definition. */
34331 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
34333 char *buffer = (char *) alloca (strlen (name) + 1);
34335 int dollar_inside = 0;
34336 struct declare_alias_data data = {file, false};
34338 strcpy (buffer, name);
34339 p = strchr (buffer, '$');
34343 p = strchr (p + 1, '$');
34345 if (TREE_PUBLIC (decl))
34347 if (!RS6000_WEAK || !DECL_WEAK (decl))
34349 if (dollar_inside) {
34350 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34351 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34353 fputs ("\t.globl .", file);
34354 RS6000_OUTPUT_BASENAME (file, buffer);
34355 #ifdef HAVE_GAS_HIDDEN
34356 fputs (rs6000_xcoff_visibility (decl), file);
34363 if (dollar_inside) {
34364 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34365 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34367 fputs ("\t.lglobl .", file);
34368 RS6000_OUTPUT_BASENAME (file, buffer);
34371 fputs ("\t.csect ", file);
34372 RS6000_OUTPUT_BASENAME (file, buffer);
34373 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
34374 RS6000_OUTPUT_BASENAME (file, buffer);
34375 fputs (":\n", file);
34376 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34378 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
34379 RS6000_OUTPUT_BASENAME (file, buffer);
34380 fputs (", TOC[tc0], 0\n", file);
34382 switch_to_section (function_section (decl));
34384 RS6000_OUTPUT_BASENAME (file, buffer);
34385 fputs (":\n", file);
34386 data.function_descriptor = true;
34387 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34389 if (!DECL_IGNORED_P (decl))
34391 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
34392 xcoffout_declare_function (file, decl, buffer);
34393 else if (write_symbols == DWARF2_DEBUG)
34395 name = (*targetm.strip_name_encoding) (name);
34396 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
34403 /* Output assembly language to globalize a symbol from a DECL,
34404 possibly with visibility. */
34407 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
34409 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
34410 fputs (GLOBAL_ASM_OP, stream);
34411 RS6000_OUTPUT_BASENAME (stream, name);
34412 #ifdef HAVE_GAS_HIDDEN
34413 fputs (rs6000_xcoff_visibility (decl), stream);
34415 putc ('\n', stream);
34418 /* Output assembly language to define a symbol as COMMON from a DECL,
34419 possibly with visibility. */
34422 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
34423 tree decl ATTRIBUTE_UNUSED,
34425 unsigned HOST_WIDE_INT size,
34426 unsigned HOST_WIDE_INT align)
34428 unsigned HOST_WIDE_INT align2 = 2;
34431 align2 = floor_log2 (align / BITS_PER_UNIT);
34435 fputs (COMMON_ASM_OP, stream);
34436 RS6000_OUTPUT_BASENAME (stream, name);
34439 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
34442 #ifdef HAVE_GAS_HIDDEN
34444 fputs (rs6000_xcoff_visibility (decl), stream);
34446 putc ('\n', stream);
34449 /* This macro produces the initial definition of a object (variable) name.
34450 Because AIX assembler's .set command has unexpected semantics, we output
34451 all aliases as alternative labels in front of the definition. */
34454 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
34456 struct declare_alias_data data = {file, false};
34457 RS6000_OUTPUT_BASENAME (file, name);
34458 fputs (":\n", file);
34459 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34463 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34466 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
34468 fputs (integer_asm_op (size, FALSE), file);
34469 assemble_name (file, label);
34470 fputs ("-$", file);
34473 /* Output a symbol offset relative to the dbase for the current object.
34474 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34477 __gcc_unwind_dbase is embedded in all executables/libraries through
34478 libgcc/config/rs6000/crtdbase.S. */
34481 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34483 fputs (integer_asm_op (size, FALSE), file);
34484 assemble_name (file, label);
34485 fputs("-__gcc_unwind_dbase", file);
34490 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34494 const char *symname;
34496 default_encode_section_info (decl, rtl, first);
34498 /* Careful not to prod global register variables. */
34501 symbol = XEXP (rtl, 0);
34502 if (GET_CODE (symbol) != SYMBOL_REF)
34505 flags = SYMBOL_REF_FLAGS (symbol);
34507 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34508 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34510 SYMBOL_REF_FLAGS (symbol) = flags;
34512 /* Append mapping class to extern decls. */
34513 symname = XSTR (symbol, 0);
34514 if (decl /* sync condition with assemble_external () */
34515 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34516 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34517 || TREE_CODE (decl) == FUNCTION_DECL)
34518 && symname[strlen (symname) - 1] != ']')
34520 char *newname = (char *) alloca (strlen (symname) + 5);
34521 strcpy (newname, symname);
34522 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34523 ? "[DS]" : "[UA]"));
34524 XSTR (symbol, 0) = ggc_strdup (newname);
34527 #endif /* HAVE_AS_TLS */
34528 #endif /* TARGET_XCOFF */
34531 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34532 const char *name, const char *val)
34534 fputs ("\t.weak\t", stream);
34535 RS6000_OUTPUT_BASENAME (stream, name);
34536 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34537 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34540 fputs ("[DS]", stream);
34541 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34543 fputs (rs6000_xcoff_visibility (decl), stream);
34545 fputs ("\n\t.weak\t.", stream);
34546 RS6000_OUTPUT_BASENAME (stream, name);
34548 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34550 fputs (rs6000_xcoff_visibility (decl), stream);
34552 fputc ('\n', stream);
34555 #ifdef ASM_OUTPUT_DEF
34556 ASM_OUTPUT_DEF (stream, name, val);
34558 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34559 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34561 fputs ("\t.set\t.", stream);
34562 RS6000_OUTPUT_BASENAME (stream, name);
34563 fputs (",.", stream);
34564 RS6000_OUTPUT_BASENAME (stream, val);
34565 fputc ('\n', stream);
34571 /* Return true if INSN should not be copied. */
34574 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34576 return recog_memoized (insn) >= 0
34577 && get_attr_cannot_copy (insn);
34580 /* Compute a (partial) cost for rtx X. Return true if the complete
34581 cost has been computed, and false if subexpressions should be
34582 scanned. In either case, *TOTAL contains the cost result. */
34585 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34586 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34588 int code = GET_CODE (x);
34592 /* On the RS/6000, if it is valid in the insn, it is free. */
34594 if (((outer_code == SET
34595 || outer_code == PLUS
34596 || outer_code == MINUS)
34597 && (satisfies_constraint_I (x)
34598 || satisfies_constraint_L (x)))
34599 || (outer_code == AND
34600 && (satisfies_constraint_K (x)
34602 ? satisfies_constraint_L (x)
34603 : satisfies_constraint_J (x))))
34604 || ((outer_code == IOR || outer_code == XOR)
34605 && (satisfies_constraint_K (x)
34607 ? satisfies_constraint_L (x)
34608 : satisfies_constraint_J (x))))
34609 || outer_code == ASHIFT
34610 || outer_code == ASHIFTRT
34611 || outer_code == LSHIFTRT
34612 || outer_code == ROTATE
34613 || outer_code == ROTATERT
34614 || outer_code == ZERO_EXTRACT
34615 || (outer_code == MULT
34616 && satisfies_constraint_I (x))
34617 || ((outer_code == DIV || outer_code == UDIV
34618 || outer_code == MOD || outer_code == UMOD)
34619 && exact_log2 (INTVAL (x)) >= 0)
34620 || (outer_code == COMPARE
34621 && (satisfies_constraint_I (x)
34622 || satisfies_constraint_K (x)))
34623 || ((outer_code == EQ || outer_code == NE)
34624 && (satisfies_constraint_I (x)
34625 || satisfies_constraint_K (x)
34627 ? satisfies_constraint_L (x)
34628 : satisfies_constraint_J (x))))
34629 || (outer_code == GTU
34630 && satisfies_constraint_I (x))
34631 || (outer_code == LTU
34632 && satisfies_constraint_P (x)))
34637 else if ((outer_code == PLUS
34638 && reg_or_add_cint_operand (x, VOIDmode))
34639 || (outer_code == MINUS
34640 && reg_or_sub_cint_operand (x, VOIDmode))
34641 || ((outer_code == SET
34642 || outer_code == IOR
34643 || outer_code == XOR)
34645 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34647 *total = COSTS_N_INSNS (1);
34653 case CONST_WIDE_INT:
34657 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34661 /* When optimizing for size, MEM should be slightly more expensive
34662 than generating address, e.g., (plus (reg) (const)).
34663 L1 cache latency is about two instructions. */
34664 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34665 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34666 *total += COSTS_N_INSNS (100);
34675 if (FLOAT_MODE_P (mode))
34676 *total = rs6000_cost->fp;
34678 *total = COSTS_N_INSNS (1);
34682 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34683 && satisfies_constraint_I (XEXP (x, 1)))
34685 if (INTVAL (XEXP (x, 1)) >= -256
34686 && INTVAL (XEXP (x, 1)) <= 255)
34687 *total = rs6000_cost->mulsi_const9;
34689 *total = rs6000_cost->mulsi_const;
34691 else if (mode == SFmode)
34692 *total = rs6000_cost->fp;
34693 else if (FLOAT_MODE_P (mode))
34694 *total = rs6000_cost->dmul;
34695 else if (mode == DImode)
34696 *total = rs6000_cost->muldi;
34698 *total = rs6000_cost->mulsi;
34702 if (mode == SFmode)
34703 *total = rs6000_cost->fp;
34705 *total = rs6000_cost->dmul;
34710 if (FLOAT_MODE_P (mode))
34712 *total = mode == DFmode ? rs6000_cost->ddiv
34713 : rs6000_cost->sdiv;
34720 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34721 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34723 if (code == DIV || code == MOD)
34725 *total = COSTS_N_INSNS (2);
34728 *total = COSTS_N_INSNS (1);
34732 if (GET_MODE (XEXP (x, 1)) == DImode)
34733 *total = rs6000_cost->divdi;
34735 *total = rs6000_cost->divsi;
34737 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34738 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34739 *total += COSTS_N_INSNS (2);
34743 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34747 *total = COSTS_N_INSNS (4);
34751 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34755 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34759 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34762 *total = COSTS_N_INSNS (1);
34766 if (CONST_INT_P (XEXP (x, 1)))
34768 rtx left = XEXP (x, 0);
34769 rtx_code left_code = GET_CODE (left);
34771 /* rotate-and-mask: 1 insn. */
34772 if ((left_code == ROTATE
34773 || left_code == ASHIFT
34774 || left_code == LSHIFTRT)
34775 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34777 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34778 if (!CONST_INT_P (XEXP (left, 1)))
34779 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34780 *total += COSTS_N_INSNS (1);
34784 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34785 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34786 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34787 || (val & 0xffff) == val
34788 || (val & 0xffff0000) == val
34789 || ((val & 0xffff) == 0 && mode == SImode))
34791 *total = rtx_cost (left, mode, AND, 0, speed);
34792 *total += COSTS_N_INSNS (1);
34797 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34799 *total = rtx_cost (left, mode, AND, 0, speed);
34800 *total += COSTS_N_INSNS (2);
34805 *total = COSTS_N_INSNS (1);
34810 *total = COSTS_N_INSNS (1);
34816 *total = COSTS_N_INSNS (1);
34820 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34821 the sign extend and shift separately within the insn. */
34822 if (TARGET_EXTSWSLI && mode == DImode
34823 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34824 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34835 /* Handle mul_highpart. */
34836 if (outer_code == TRUNCATE
34837 && GET_CODE (XEXP (x, 0)) == MULT)
34839 if (mode == DImode)
34840 *total = rs6000_cost->muldi;
34842 *total = rs6000_cost->mulsi;
34845 else if (outer_code == AND)
34848 *total = COSTS_N_INSNS (1);
34853 if (GET_CODE (XEXP (x, 0)) == MEM)
34856 *total = COSTS_N_INSNS (1);
34862 if (!FLOAT_MODE_P (mode))
34864 *total = COSTS_N_INSNS (1);
34870 case UNSIGNED_FLOAT:
34873 case FLOAT_TRUNCATE:
34874 *total = rs6000_cost->fp;
34878 if (mode == DFmode)
34879 *total = rs6000_cost->sfdf_convert;
34881 *total = rs6000_cost->fp;
34885 switch (XINT (x, 1))
34888 *total = rs6000_cost->fp;
34900 *total = COSTS_N_INSNS (1);
34903 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34905 *total = rs6000_cost->fp;
34914 /* Carry bit requires mode == Pmode.
34915 NEG or PLUS already counted so only add one. */
34917 && (outer_code == NEG || outer_code == PLUS))
34919 *total = COSTS_N_INSNS (1);
34927 if (outer_code == SET)
34929 if (XEXP (x, 1) == const0_rtx)
34931 *total = COSTS_N_INSNS (2);
34936 *total = COSTS_N_INSNS (3);
34941 if (outer_code == COMPARE)
34955 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34958 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34959 int opno, int *total, bool speed)
34961 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34964 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34965 "opno = %d, total = %d, speed = %s, x:\n",
34966 ret ? "complete" : "scan inner",
34967 GET_MODE_NAME (mode),
34968 GET_RTX_NAME (outer_code),
34971 speed ? "true" : "false");
34979 rs6000_insn_cost (rtx_insn *insn, bool speed)
34981 if (recog_memoized (insn) < 0)
34985 return get_attr_length (insn);
34987 int cost = get_attr_cost (insn);
34991 int n = get_attr_length (insn) / 4;
34992 enum attr_type type = get_attr_type (insn);
34999 cost = COSTS_N_INSNS (n + 1);
35003 switch (get_attr_size (insn))
35006 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
35009 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
35012 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
35015 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
35018 gcc_unreachable ();
35022 switch (get_attr_size (insn))
35025 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
35028 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
35031 gcc_unreachable ();
35036 cost = n * rs6000_cost->fp;
35039 cost = n * rs6000_cost->dmul;
35042 cost = n * rs6000_cost->sdiv;
35045 cost = n * rs6000_cost->ddiv;
35052 cost = COSTS_N_INSNS (n + 2);
35056 cost = COSTS_N_INSNS (n);
35062 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
35065 rs6000_debug_address_cost (rtx x, machine_mode mode,
35066 addr_space_t as, bool speed)
35068 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
35070 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
35071 ret, speed ? "true" : "false");
35078 /* A C expression returning the cost of moving data from a register of class
35079 CLASS1 to one of CLASS2. */
35082 rs6000_register_move_cost (machine_mode mode,
35083 reg_class_t from, reg_class_t to)
35087 if (TARGET_DEBUG_COST)
35090 /* Moves from/to GENERAL_REGS. */
35091 if (reg_classes_intersect_p (to, GENERAL_REGS)
35092 || reg_classes_intersect_p (from, GENERAL_REGS))
35094 reg_class_t rclass = from;
35096 if (! reg_classes_intersect_p (to, GENERAL_REGS))
35099 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
35100 ret = (rs6000_memory_move_cost (mode, rclass, false)
35101 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
35103 /* It's more expensive to move CR_REGS than CR0_REGS because of the
35105 else if (rclass == CR_REGS)
35108 /* For those processors that have slow LR/CTR moves, make them more
35109 expensive than memory in order to bias spills to memory .*/
35110 else if ((rs6000_tune == PROCESSOR_POWER6
35111 || rs6000_tune == PROCESSOR_POWER7
35112 || rs6000_tune == PROCESSOR_POWER8
35113 || rs6000_tune == PROCESSOR_POWER9)
35114 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
35115 ret = 6 * hard_regno_nregs (0, mode);
35118 /* A move will cost one instruction per GPR moved. */
35119 ret = 2 * hard_regno_nregs (0, mode);
35122 /* If we have VSX, we can easily move between FPR or Altivec registers. */
35123 else if (VECTOR_MEM_VSX_P (mode)
35124 && reg_classes_intersect_p (to, VSX_REGS)
35125 && reg_classes_intersect_p (from, VSX_REGS))
35126 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
35128 /* Moving between two similar registers is just one instruction. */
35129 else if (reg_classes_intersect_p (to, from))
35130 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
35132 /* Everything else has to go through GENERAL_REGS. */
35134 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
35135 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
35137 if (TARGET_DEBUG_COST)
35139 if (dbg_cost_ctrl == 1)
35141 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
35142 ret, GET_MODE_NAME (mode), reg_class_names[from],
35143 reg_class_names[to]);
35150 /* A C expressions returning the cost of moving data of MODE from a register to
35154 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
35155 bool in ATTRIBUTE_UNUSED)
35159 if (TARGET_DEBUG_COST)
35162 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
35163 ret = 4 * hard_regno_nregs (0, mode);
35164 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
35165 || reg_classes_intersect_p (rclass, VSX_REGS)))
35166 ret = 4 * hard_regno_nregs (32, mode);
35167 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
35168 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
35170 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
35172 if (TARGET_DEBUG_COST)
35174 if (dbg_cost_ctrl == 1)
35176 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
35177 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
35184 /* Returns a code for a target-specific builtin that implements
35185 reciprocal of the function, or NULL_TREE if not available. */
35188 rs6000_builtin_reciprocal (tree fndecl)
35190 switch (DECL_FUNCTION_CODE (fndecl))
35192 case VSX_BUILTIN_XVSQRTDP:
35193 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
35196 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
35198 case VSX_BUILTIN_XVSQRTSP:
35199 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
35202 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
35209 /* Load up a constant. If the mode is a vector mode, splat the value across
35210 all of the vector elements. */
35213 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
35217 if (mode == SFmode || mode == DFmode)
35219 rtx d = const_double_from_real_value (dconst, mode);
35220 reg = force_reg (mode, d);
35222 else if (mode == V4SFmode)
35224 rtx d = const_double_from_real_value (dconst, SFmode);
35225 rtvec v = gen_rtvec (4, d, d, d, d);
35226 reg = gen_reg_rtx (mode);
35227 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35229 else if (mode == V2DFmode)
35231 rtx d = const_double_from_real_value (dconst, DFmode);
35232 rtvec v = gen_rtvec (2, d, d);
35233 reg = gen_reg_rtx (mode);
35234 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35237 gcc_unreachable ();
35242 /* Generate an FMA instruction. */
35245 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
35247 machine_mode mode = GET_MODE (target);
35250 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
35251 gcc_assert (dst != NULL);
35254 emit_move_insn (target, dst);
35257 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
35260 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
35262 machine_mode mode = GET_MODE (dst);
35265 /* This is a tad more complicated, since the fnma_optab is for
35266 a different expression: fma(-m1, m2, a), which is the same
35267 thing except in the case of signed zeros.
35269 Fortunately we know that if FMA is supported that FNMSUB is
35270 also supported in the ISA. Just expand it directly. */
35272 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
35274 r = gen_rtx_NEG (mode, a);
35275 r = gen_rtx_FMA (mode, m1, m2, r);
35276 r = gen_rtx_NEG (mode, r);
35277 emit_insn (gen_rtx_SET (dst, r));
35280 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
35281 add a reg_note saying that this was a division. Support both scalar and
35282 vector divide. Assumes no trapping math and finite arguments. */
35285 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
35287 machine_mode mode = GET_MODE (dst);
35288 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
35291 /* Low precision estimates guarantee 5 bits of accuracy. High
35292 precision estimates guarantee 14 bits of accuracy. SFmode
35293 requires 23 bits of accuracy. DFmode requires 52 bits of
35294 accuracy. Each pass at least doubles the accuracy, leading
35295 to the following. */
35296 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35297 if (mode == DFmode || mode == V2DFmode)
35300 enum insn_code code = optab_handler (smul_optab, mode);
35301 insn_gen_fn gen_mul = GEN_FCN (code);
35303 gcc_assert (code != CODE_FOR_nothing);
35305 one = rs6000_load_constant_and_splat (mode, dconst1);
35307 /* x0 = 1./d estimate */
35308 x0 = gen_reg_rtx (mode);
35309 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
35312 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35315 /* e0 = 1. - d * x0 */
35316 e0 = gen_reg_rtx (mode);
35317 rs6000_emit_nmsub (e0, d, x0, one);
35319 /* x1 = x0 + e0 * x0 */
35320 x1 = gen_reg_rtx (mode);
35321 rs6000_emit_madd (x1, e0, x0, x0);
35323 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
35324 ++i, xprev = xnext, eprev = enext) {
35326 /* enext = eprev * eprev */
35327 enext = gen_reg_rtx (mode);
35328 emit_insn (gen_mul (enext, eprev, eprev));
35330 /* xnext = xprev + enext * xprev */
35331 xnext = gen_reg_rtx (mode);
35332 rs6000_emit_madd (xnext, enext, xprev, xprev);
35338 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35340 /* u = n * xprev */
35341 u = gen_reg_rtx (mode);
35342 emit_insn (gen_mul (u, n, xprev));
35344 /* v = n - (d * u) */
35345 v = gen_reg_rtx (mode);
35346 rs6000_emit_nmsub (v, d, u, n);
35348 /* dst = (v * xprev) + u */
35349 rs6000_emit_madd (dst, v, xprev, u);
35352 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
35355 /* Goldschmidt's Algorithm for single/double-precision floating point
35356 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35359 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
35361 machine_mode mode = GET_MODE (src);
35362 rtx e = gen_reg_rtx (mode);
35363 rtx g = gen_reg_rtx (mode);
35364 rtx h = gen_reg_rtx (mode);
35366 /* Low precision estimates guarantee 5 bits of accuracy. High
35367 precision estimates guarantee 14 bits of accuracy. SFmode
35368 requires 23 bits of accuracy. DFmode requires 52 bits of
35369 accuracy. Each pass at least doubles the accuracy, leading
35370 to the following. */
35371 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35372 if (mode == DFmode || mode == V2DFmode)
35377 enum insn_code code = optab_handler (smul_optab, mode);
35378 insn_gen_fn gen_mul = GEN_FCN (code);
35380 gcc_assert (code != CODE_FOR_nothing);
35382 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35384 /* e = rsqrt estimate */
35385 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35388 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35391 rtx zero = force_reg (mode, CONST0_RTX (mode));
35393 if (mode == SFmode)
35395 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35398 emit_move_insn (e, target);
35402 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35403 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35407 /* g = sqrt estimate. */
35408 emit_insn (gen_mul (g, e, src));
35409 /* h = 1/(2*sqrt) estimate. */
35410 emit_insn (gen_mul (h, e, mhalf));
35416 rtx t = gen_reg_rtx (mode);
35417 rs6000_emit_nmsub (t, g, h, mhalf);
35418 /* Apply correction directly to 1/rsqrt estimate. */
35419 rs6000_emit_madd (dst, e, t, e);
35423 for (i = 0; i < passes; i++)
35425 rtx t1 = gen_reg_rtx (mode);
35426 rtx g1 = gen_reg_rtx (mode);
35427 rtx h1 = gen_reg_rtx (mode);
35429 rs6000_emit_nmsub (t1, g, h, mhalf);
35430 rs6000_emit_madd (g1, g, t1, g);
35431 rs6000_emit_madd (h1, h, t1, h);
35436 /* Multiply by 2 for 1/rsqrt. */
35437 emit_insn (gen_add3_insn (dst, h, h));
35442 rtx t = gen_reg_rtx (mode);
35443 rs6000_emit_nmsub (t, g, h, mhalf);
35444 rs6000_emit_madd (dst, g, t, g);
35450 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35451 (Power7) targets. DST is the target, and SRC is the argument operand. */
35454 rs6000_emit_popcount (rtx dst, rtx src)
35456 machine_mode mode = GET_MODE (dst);
35459 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35460 if (TARGET_POPCNTD)
35462 if (mode == SImode)
35463 emit_insn (gen_popcntdsi2 (dst, src));
35465 emit_insn (gen_popcntddi2 (dst, src));
35469 tmp1 = gen_reg_rtx (mode);
35471 if (mode == SImode)
35473 emit_insn (gen_popcntbsi2 (tmp1, src));
35474 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35476 tmp2 = force_reg (SImode, tmp2);
35477 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35481 emit_insn (gen_popcntbdi2 (tmp1, src));
35482 tmp2 = expand_mult (DImode, tmp1,
35483 GEN_INT ((HOST_WIDE_INT)
35484 0x01010101 << 32 | 0x01010101),
35486 tmp2 = force_reg (DImode, tmp2);
35487 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35492 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35493 target, and SRC is the argument operand. */
35496 rs6000_emit_parity (rtx dst, rtx src)
35498 machine_mode mode = GET_MODE (dst);
35501 tmp = gen_reg_rtx (mode);
35503 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35506 if (mode == SImode)
35508 emit_insn (gen_popcntbsi2 (tmp, src));
35509 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35513 emit_insn (gen_popcntbdi2 (tmp, src));
35514 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35519 if (mode == SImode)
35521 /* Is mult+shift >= shift+xor+shift+xor? */
35522 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35524 rtx tmp1, tmp2, tmp3, tmp4;
35526 tmp1 = gen_reg_rtx (SImode);
35527 emit_insn (gen_popcntbsi2 (tmp1, src));
35529 tmp2 = gen_reg_rtx (SImode);
35530 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35531 tmp3 = gen_reg_rtx (SImode);
35532 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35534 tmp4 = gen_reg_rtx (SImode);
35535 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35536 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35539 rs6000_emit_popcount (tmp, src);
35540 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35544 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35545 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35547 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35549 tmp1 = gen_reg_rtx (DImode);
35550 emit_insn (gen_popcntbdi2 (tmp1, src));
35552 tmp2 = gen_reg_rtx (DImode);
35553 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35554 tmp3 = gen_reg_rtx (DImode);
35555 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35557 tmp4 = gen_reg_rtx (DImode);
35558 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35559 tmp5 = gen_reg_rtx (DImode);
35560 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35562 tmp6 = gen_reg_rtx (DImode);
35563 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35564 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35567 rs6000_emit_popcount (tmp, src);
35568 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35572 /* Expand an Altivec constant permutation for little endian mode.
35573 OP0 and OP1 are the input vectors and TARGET is the output vector.
35574 SEL specifies the constant permutation vector.
35576 There are two issues: First, the two input operands must be
35577 swapped so that together they form a double-wide array in LE
35578 order. Second, the vperm instruction has surprising behavior
35579 in LE mode: it interprets the elements of the source vectors
35580 in BE mode ("left to right") and interprets the elements of
35581 the destination vector in LE mode ("right to left"). To
35582 correct for this, we must subtract each element of the permute
35583 control vector from 31.
35585 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35586 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35587 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35588 serve as the permute control vector. Then, in BE mode,
35592 places the desired result in vr9. However, in LE mode the
35593 vector contents will be
35595 vr10 = 00000003 00000002 00000001 00000000
35596 vr11 = 00000007 00000006 00000005 00000004
35598 The result of the vperm using the same permute control vector is
35600 vr9 = 05000000 07000000 01000000 03000000
35602 That is, the leftmost 4 bytes of vr10 are interpreted as the
35603 source for the rightmost 4 bytes of vr9, and so on.
35605 If we change the permute control vector to
35607 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35615 vr9 = 00000006 00000004 00000002 00000000. */
35618 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35619 const vec_perm_indices &sel)
35623 rtx constv, unspec;
35625 /* Unpack and adjust the constant selector. */
35626 for (i = 0; i < 16; ++i)
35628 unsigned int elt = 31 - (sel[i] & 31);
35629 perm[i] = GEN_INT (elt);
35632 /* Expand to a permute, swapping the inputs and using the
35633 adjusted selector. */
35635 op0 = force_reg (V16QImode, op0);
35637 op1 = force_reg (V16QImode, op1);
35639 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35640 constv = force_reg (V16QImode, constv);
35641 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35643 if (!REG_P (target))
35645 rtx tmp = gen_reg_rtx (V16QImode);
35646 emit_move_insn (tmp, unspec);
35650 emit_move_insn (target, unspec);
35653 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35654 permute control vector. But here it's not a constant, so we must
35655 generate a vector NAND or NOR to do the adjustment. */
35658 altivec_expand_vec_perm_le (rtx operands[4])
35660 rtx notx, iorx, unspec;
35661 rtx target = operands[0];
35662 rtx op0 = operands[1];
35663 rtx op1 = operands[2];
35664 rtx sel = operands[3];
35666 rtx norreg = gen_reg_rtx (V16QImode);
35667 machine_mode mode = GET_MODE (target);
35669 /* Get everything in regs so the pattern matches. */
35671 op0 = force_reg (mode, op0);
35673 op1 = force_reg (mode, op1);
35675 sel = force_reg (V16QImode, sel);
35676 if (!REG_P (target))
35677 tmp = gen_reg_rtx (mode);
35679 if (TARGET_P9_VECTOR)
35681 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op0, op1, sel),
35686 /* Invert the selector with a VNAND if available, else a VNOR.
35687 The VNAND is preferred for future fusion opportunities. */
35688 notx = gen_rtx_NOT (V16QImode, sel);
35689 iorx = (TARGET_P8_VECTOR
35690 ? gen_rtx_IOR (V16QImode, notx, notx)
35691 : gen_rtx_AND (V16QImode, notx, notx));
35692 emit_insn (gen_rtx_SET (norreg, iorx));
35694 /* Permute with operands reversed and adjusted selector. */
35695 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35699 /* Copy into target, possibly by way of a register. */
35700 if (!REG_P (target))
35702 emit_move_insn (tmp, unspec);
35706 emit_move_insn (target, unspec);
35709 /* Expand an Altivec constant permutation. Return true if we match
35710 an efficient implementation; false to fall back to VPERM.
35712 OP0 and OP1 are the input vectors and TARGET is the output vector.
35713 SEL specifies the constant permutation vector. */
35716 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35717 const vec_perm_indices &sel)
35719 struct altivec_perm_insn {
35720 HOST_WIDE_INT mask;
35721 enum insn_code impl;
35722 unsigned char perm[16];
35724 static const struct altivec_perm_insn patterns[] = {
35725 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35726 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35727 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35728 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35729 { OPTION_MASK_ALTIVEC,
35730 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35731 : CODE_FOR_altivec_vmrglb_direct),
35732 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35733 { OPTION_MASK_ALTIVEC,
35734 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35735 : CODE_FOR_altivec_vmrglh_direct),
35736 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35737 { OPTION_MASK_ALTIVEC,
35738 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35739 : CODE_FOR_altivec_vmrglw_direct),
35740 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35741 { OPTION_MASK_ALTIVEC,
35742 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35743 : CODE_FOR_altivec_vmrghb_direct),
35744 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35745 { OPTION_MASK_ALTIVEC,
35746 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35747 : CODE_FOR_altivec_vmrghh_direct),
35748 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35749 { OPTION_MASK_ALTIVEC,
35750 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35751 : CODE_FOR_altivec_vmrghw_direct),
35752 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35753 { OPTION_MASK_P8_VECTOR,
35754 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35755 : CODE_FOR_p8_vmrgow_v4sf_direct),
35756 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35757 { OPTION_MASK_P8_VECTOR,
35758 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35759 : CODE_FOR_p8_vmrgew_v4sf_direct),
35760 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35763 unsigned int i, j, elt, which;
35764 unsigned char perm[16];
35768 /* Unpack the constant selector. */
35769 for (i = which = 0; i < 16; ++i)
35772 which |= (elt < 16 ? 1 : 2);
35776 /* Simplify the constant selector based on operands. */
35780 gcc_unreachable ();
35784 if (!rtx_equal_p (op0, op1))
35789 for (i = 0; i < 16; ++i)
35801 /* Look for splat patterns. */
35806 for (i = 0; i < 16; ++i)
35807 if (perm[i] != elt)
35811 if (!BYTES_BIG_ENDIAN)
35813 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35819 for (i = 0; i < 16; i += 2)
35820 if (perm[i] != elt || perm[i + 1] != elt + 1)
35824 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35825 x = gen_reg_rtx (V8HImode);
35826 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35828 emit_move_insn (target, gen_lowpart (V16QImode, x));
35835 for (i = 0; i < 16; i += 4)
35837 || perm[i + 1] != elt + 1
35838 || perm[i + 2] != elt + 2
35839 || perm[i + 3] != elt + 3)
35843 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35844 x = gen_reg_rtx (V4SImode);
35845 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35847 emit_move_insn (target, gen_lowpart (V16QImode, x));
35853 /* Look for merge and pack patterns. */
35854 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35858 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35861 elt = patterns[j].perm[0];
35862 if (perm[0] == elt)
35864 else if (perm[0] == elt + 16)
35868 for (i = 1; i < 16; ++i)
35870 elt = patterns[j].perm[i];
35872 elt = (elt >= 16 ? elt - 16 : elt + 16);
35873 else if (one_vec && elt >= 16)
35875 if (perm[i] != elt)
35880 enum insn_code icode = patterns[j].impl;
35881 machine_mode omode = insn_data[icode].operand[0].mode;
35882 machine_mode imode = insn_data[icode].operand[1].mode;
35884 /* For little-endian, don't use vpkuwum and vpkuhum if the
35885 underlying vector type is not V4SI and V8HI, respectively.
35886 For example, using vpkuwum with a V8HI picks up the even
35887 halfwords (BE numbering) when the even halfwords (LE
35888 numbering) are what we need. */
35889 if (!BYTES_BIG_ENDIAN
35890 && icode == CODE_FOR_altivec_vpkuwum_direct
35891 && ((GET_CODE (op0) == REG
35892 && GET_MODE (op0) != V4SImode)
35893 || (GET_CODE (op0) == SUBREG
35894 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35896 if (!BYTES_BIG_ENDIAN
35897 && icode == CODE_FOR_altivec_vpkuhum_direct
35898 && ((GET_CODE (op0) == REG
35899 && GET_MODE (op0) != V8HImode)
35900 || (GET_CODE (op0) == SUBREG
35901 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35904 /* For little-endian, the two input operands must be swapped
35905 (or swapped back) to ensure proper right-to-left numbering
35907 if (swapped ^ !BYTES_BIG_ENDIAN)
35908 std::swap (op0, op1);
35909 if (imode != V16QImode)
35911 op0 = gen_lowpart (imode, op0);
35912 op1 = gen_lowpart (imode, op1);
35914 if (omode == V16QImode)
35917 x = gen_reg_rtx (omode);
35918 emit_insn (GEN_FCN (icode) (x, op0, op1));
35919 if (omode != V16QImode)
35920 emit_move_insn (target, gen_lowpart (V16QImode, x));
35925 if (!BYTES_BIG_ENDIAN)
35927 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35934 /* Expand a Paired Single or VSX Permute Doubleword constant permutation.
35935 Return true if we match an efficient implementation. */
35938 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35939 unsigned char perm0, unsigned char perm1)
35943 /* If both selectors come from the same operand, fold to single op. */
35944 if ((perm0 & 2) == (perm1 & 2))
35951 /* If both operands are equal, fold to simpler permutation. */
35952 if (rtx_equal_p (op0, op1))
35955 perm1 = (perm1 & 1) + 2;
35957 /* If the first selector comes from the second operand, swap. */
35958 else if (perm0 & 2)
35964 std::swap (op0, op1);
35966 /* If the second selector does not come from the second operand, fail. */
35967 else if ((perm1 & 2) == 0)
35971 if (target != NULL)
35973 machine_mode vmode, dmode;
35976 vmode = GET_MODE (target);
35977 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35978 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35979 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35980 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35981 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35982 emit_insn (gen_rtx_SET (target, x));
35987 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35990 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35991 rtx op1, const vec_perm_indices &sel)
35993 bool testing_p = !target;
35995 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35996 if (TARGET_ALTIVEC && testing_p)
35999 /* Check for ps_merge* or xxpermdi insns. */
36000 if ((vmode == V2SFmode && TARGET_PAIRED_FLOAT)
36001 || ((vmode == V2DFmode || vmode == V2DImode)
36002 && VECTOR_MEM_VSX_P (vmode)))
36006 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
36007 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
36009 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
36013 if (TARGET_ALTIVEC)
36015 /* Force the target-independent code to lower to V16QImode. */
36016 if (vmode != V16QImode)
36018 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
36025 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
36026 OP0 and OP1 are the input vectors and TARGET is the output vector.
36027 PERM specifies the constant permutation vector. */
36030 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
36031 machine_mode vmode, const vec_perm_builder &perm)
36033 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
36035 emit_move_insn (target, x);
36038 /* Expand an extract even operation. */
36041 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
36043 machine_mode vmode = GET_MODE (target);
36044 unsigned i, nelt = GET_MODE_NUNITS (vmode);
36045 vec_perm_builder perm (nelt);
36047 for (i = 0; i < nelt; i++)
36048 perm.quick_push (i * 2);
36050 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36053 /* Expand a vector interleave operation. */
36056 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
36058 machine_mode vmode = GET_MODE (target);
36059 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
36060 vec_perm_builder perm (nelt);
36062 high = (highp ? 0 : nelt / 2);
36063 for (i = 0; i < nelt / 2; i++)
36065 perm.quick_push (i + high);
36066 perm.quick_push (i + nelt + high);
36069 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36072 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
36074 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
36076 HOST_WIDE_INT hwi_scale (scale);
36077 REAL_VALUE_TYPE r_pow;
36078 rtvec v = rtvec_alloc (2);
36080 rtx scale_vec = gen_reg_rtx (V2DFmode);
36081 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
36082 elt = const_double_from_real_value (r_pow, DFmode);
36083 RTVEC_ELT (v, 0) = elt;
36084 RTVEC_ELT (v, 1) = elt;
36085 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
36086 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
36089 /* Return an RTX representing where to find the function value of a
36090 function returning MODE. */
36092 rs6000_complex_function_value (machine_mode mode)
36094 unsigned int regno;
36096 machine_mode inner = GET_MODE_INNER (mode);
36097 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
36099 if (TARGET_FLOAT128_TYPE
36101 || (mode == TCmode && TARGET_IEEEQUAD)))
36102 regno = ALTIVEC_ARG_RETURN;
36104 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36105 regno = FP_ARG_RETURN;
36109 regno = GP_ARG_RETURN;
36111 /* 32-bit is OK since it'll go in r3/r4. */
36112 if (TARGET_32BIT && inner_bytes >= 4)
36113 return gen_rtx_REG (mode, regno);
36116 if (inner_bytes >= 8)
36117 return gen_rtx_REG (mode, regno);
36119 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
36121 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
36122 GEN_INT (inner_bytes));
36123 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
36126 /* Return an rtx describing a return value of MODE as a PARALLEL
36127 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
36128 stride REG_STRIDE. */
36131 rs6000_parallel_return (machine_mode mode,
36132 int n_elts, machine_mode elt_mode,
36133 unsigned int regno, unsigned int reg_stride)
36135 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
36138 for (i = 0; i < n_elts; i++)
36140 rtx r = gen_rtx_REG (elt_mode, regno);
36141 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
36142 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36143 regno += reg_stride;
36149 /* Target hook for TARGET_FUNCTION_VALUE.
36151 An integer value is in r3 and a floating-point value is in fp1,
36152 unless -msoft-float. */
36155 rs6000_function_value (const_tree valtype,
36156 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
36157 bool outgoing ATTRIBUTE_UNUSED)
36160 unsigned int regno;
36161 machine_mode elt_mode;
36164 /* Special handling for structs in darwin64. */
36166 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
36168 CUMULATIVE_ARGS valcum;
36172 valcum.fregno = FP_ARG_MIN_REG;
36173 valcum.vregno = ALTIVEC_ARG_MIN_REG;
36174 /* Do a trial code generation as if this were going to be passed as
36175 an argument; if any part goes in memory, we return NULL. */
36176 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
36179 /* Otherwise fall through to standard ABI rules. */
36182 mode = TYPE_MODE (valtype);
36184 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
36185 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
36187 int first_reg, n_regs;
36189 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
36191 /* _Decimal128 must use even/odd register pairs. */
36192 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36193 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
36197 first_reg = ALTIVEC_ARG_RETURN;
36201 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
36204 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
36205 if (TARGET_32BIT && TARGET_POWERPC64)
36214 int count = GET_MODE_SIZE (mode) / 4;
36215 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
36218 if ((INTEGRAL_TYPE_P (valtype)
36219 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
36220 || POINTER_TYPE_P (valtype))
36221 mode = TARGET_32BIT ? SImode : DImode;
36223 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36224 /* _Decimal128 must use an even/odd register pair. */
36225 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36226 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
36227 && !FLOAT128_VECTOR_P (mode)
36228 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
36229 regno = FP_ARG_RETURN;
36230 else if (TREE_CODE (valtype) == COMPLEX_TYPE
36231 && targetm.calls.split_complex_arg)
36232 return rs6000_complex_function_value (mode);
36233 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36234 return register is used in both cases, and we won't see V2DImode/V2DFmode
36235 for pure altivec, combine the two cases. */
36236 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
36237 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
36238 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
36239 regno = ALTIVEC_ARG_RETURN;
36241 regno = GP_ARG_RETURN;
36243 return gen_rtx_REG (mode, regno);
36246 /* Define how to find the value returned by a library function
36247 assuming the value has mode MODE. */
36249 rs6000_libcall_value (machine_mode mode)
36251 unsigned int regno;
36253 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
36254 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
36255 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
36257 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36258 /* _Decimal128 must use an even/odd register pair. */
36259 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36260 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
36261 && TARGET_HARD_FLOAT
36262 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
36263 regno = FP_ARG_RETURN;
36264 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36265 return register is used in both cases, and we won't see V2DImode/V2DFmode
36266 for pure altivec, combine the two cases. */
36267 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
36268 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
36269 regno = ALTIVEC_ARG_RETURN;
36270 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
36271 return rs6000_complex_function_value (mode);
36273 regno = GP_ARG_RETURN;
36275 return gen_rtx_REG (mode, regno);
36278 /* Compute register pressure classes. We implement the target hook to avoid
36279 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
36280 lead to incorrect estimates of number of available registers and therefor
36281 increased register pressure/spill. */
36283 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
36288 pressure_classes[n++] = GENERAL_REGS;
36290 pressure_classes[n++] = VSX_REGS;
36293 if (TARGET_ALTIVEC)
36294 pressure_classes[n++] = ALTIVEC_REGS;
36295 if (TARGET_HARD_FLOAT)
36296 pressure_classes[n++] = FLOAT_REGS;
36298 pressure_classes[n++] = CR_REGS;
36299 pressure_classes[n++] = SPECIAL_REGS;
36304 /* Given FROM and TO register numbers, say whether this elimination is allowed.
36305 Frame pointer elimination is automatically handled.
36307 For the RS/6000, if frame pointer elimination is being done, we would like
36308 to convert ap into fp, not sp.
36310 We need r30 if -mminimal-toc was specified, and there are constant pool
36314 rs6000_can_eliminate (const int from, const int to)
36316 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
36317 ? ! frame_pointer_needed
36318 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
36319 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
36320 || constant_pool_empty_p ()
36324 /* Define the offset between two registers, FROM to be eliminated and its
36325 replacement TO, at the start of a routine. */
36327 rs6000_initial_elimination_offset (int from, int to)
36329 rs6000_stack_t *info = rs6000_stack_info ();
36330 HOST_WIDE_INT offset;
36332 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36333 offset = info->push_p ? 0 : -info->total_size;
36334 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36336 offset = info->push_p ? 0 : -info->total_size;
36337 if (FRAME_GROWS_DOWNWARD)
36338 offset += info->fixed_size + info->vars_size + info->parm_size;
36340 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36341 offset = FRAME_GROWS_DOWNWARD
36342 ? info->fixed_size + info->vars_size + info->parm_size
36344 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36345 offset = info->total_size;
36346 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36347 offset = info->push_p ? info->total_size : 0;
36348 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
36351 gcc_unreachable ();
36356 /* Fill in sizes of registers used by unwinder. */
36359 rs6000_init_dwarf_reg_sizes_extra (tree address)
36361 if (TARGET_MACHO && ! TARGET_ALTIVEC)
36364 machine_mode mode = TYPE_MODE (char_type_node);
36365 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
36366 rtx mem = gen_rtx_MEM (BLKmode, addr);
36367 rtx value = gen_int_mode (16, mode);
36369 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36370 The unwinder still needs to know the size of Altivec registers. */
36372 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
36374 int column = DWARF_REG_TO_UNWIND_COLUMN
36375 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
36376 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
36378 emit_move_insn (adjust_address (mem, mode, offset), value);
36383 /* Map internal gcc register numbers to debug format register numbers.
36384 FORMAT specifies the type of debug register number to use:
36385 0 -- debug information, except for frame-related sections
36386 1 -- DWARF .debug_frame section
36387 2 -- DWARF .eh_frame section */
36390 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36392 /* Except for the above, we use the internal number for non-DWARF
36393 debug information, and also for .eh_frame. */
36394 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
36397 /* On some platforms, we use the standard DWARF register
36398 numbering for .debug_info and .debug_frame. */
36399 #ifdef RS6000_USE_DWARF_NUMBERING
36402 if (regno == LR_REGNO)
36404 if (regno == CTR_REGNO)
36406 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36407 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36408 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36409 to the DWARF reg for CR. */
36410 if (format == 1 && regno == CR2_REGNO)
36412 if (CR_REGNO_P (regno))
36413 return regno - CR0_REGNO + 86;
36414 if (regno == CA_REGNO)
36415 return 101; /* XER */
36416 if (ALTIVEC_REGNO_P (regno))
36417 return regno - FIRST_ALTIVEC_REGNO + 1124;
36418 if (regno == VRSAVE_REGNO)
36420 if (regno == VSCR_REGNO)
36426 /* target hook eh_return_filter_mode */
36427 static scalar_int_mode
36428 rs6000_eh_return_filter_mode (void)
36430 return TARGET_32BIT ? SImode : word_mode;
36433 /* Target hook for scalar_mode_supported_p. */
36435 rs6000_scalar_mode_supported_p (scalar_mode mode)
36437 /* -m32 does not support TImode. This is the default, from
36438 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36439 same ABI as for -m32. But default_scalar_mode_supported_p allows
36440 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36441 for -mpowerpc64. */
36442 if (TARGET_32BIT && mode == TImode)
36445 if (DECIMAL_FLOAT_MODE_P (mode))
36446 return default_decimal_float_supported_p ();
36447 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36450 return default_scalar_mode_supported_p (mode);
36453 /* Target hook for vector_mode_supported_p. */
36455 rs6000_vector_mode_supported_p (machine_mode mode)
36458 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
36461 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36462 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36464 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36471 /* Target hook for floatn_mode. */
36472 static opt_scalar_float_mode
36473 rs6000_floatn_mode (int n, bool extended)
36483 if (TARGET_FLOAT128_TYPE)
36484 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36486 return opt_scalar_float_mode ();
36489 return opt_scalar_float_mode ();
36492 /* Those are the only valid _FloatNx types. */
36493 gcc_unreachable ();
36507 if (TARGET_FLOAT128_TYPE)
36508 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36510 return opt_scalar_float_mode ();
36513 return opt_scalar_float_mode ();
36519 /* Target hook for c_mode_for_suffix. */
36520 static machine_mode
36521 rs6000_c_mode_for_suffix (char suffix)
36523 if (TARGET_FLOAT128_TYPE)
36525 if (suffix == 'q' || suffix == 'Q')
36526 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36528 /* At the moment, we are not defining a suffix for IBM extended double.
36529 If/when the default for -mabi=ieeelongdouble is changed, and we want
36530 to support __ibm128 constants in legacy library code, we may need to
36531 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36532 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36533 __float80 constants. */
36539 /* Target hook for invalid_arg_for_unprototyped_fn. */
36540 static const char *
36541 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36543 return (!rs6000_darwin64_abi
36545 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36546 && (funcdecl == NULL_TREE
36547 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36548 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36549 ? N_("AltiVec argument passed to unprototyped function")
36553 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36554 setup by using __stack_chk_fail_local hidden function instead of
36555 calling __stack_chk_fail directly. Otherwise it is better to call
36556 __stack_chk_fail directly. */
36558 static tree ATTRIBUTE_UNUSED
36559 rs6000_stack_protect_fail (void)
36561 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36562 ? default_hidden_stack_protect_fail ()
36563 : default_external_stack_protect_fail ();
36566 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36569 static unsigned HOST_WIDE_INT
36570 rs6000_asan_shadow_offset (void)
36572 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36576 /* Mask options that we want to support inside of attribute((target)) and
36577 #pragma GCC target operations. Note, we do not include things like
36578 64/32-bit, endianness, hard/soft floating point, etc. that would have
36579 different calling sequences. */
36581 struct rs6000_opt_mask {
36582 const char *name; /* option name */
36583 HOST_WIDE_INT mask; /* mask to set */
36584 bool invert; /* invert sense of mask */
36585 bool valid_target; /* option is a target option */
36588 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36590 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36591 { "cmpb", OPTION_MASK_CMPB, false, true },
36592 { "crypto", OPTION_MASK_CRYPTO, false, true },
36593 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36594 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36595 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36597 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36598 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36599 { "fprnd", OPTION_MASK_FPRND, false, true },
36600 { "hard-dfp", OPTION_MASK_DFP, false, true },
36601 { "htm", OPTION_MASK_HTM, false, true },
36602 { "isel", OPTION_MASK_ISEL, false, true },
36603 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36604 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36605 { "modulo", OPTION_MASK_MODULO, false, true },
36606 { "mulhw", OPTION_MASK_MULHW, false, true },
36607 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36608 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36609 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36610 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36611 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36612 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36613 { "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
36614 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36615 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36616 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36617 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36618 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36619 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36620 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36621 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36622 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36623 { "string", OPTION_MASK_STRING, false, true },
36624 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
36625 { "update", OPTION_MASK_NO_UPDATE, true , true },
36626 { "vsx", OPTION_MASK_VSX, false, true },
36627 #ifdef OPTION_MASK_64BIT
36629 { "aix64", OPTION_MASK_64BIT, false, false },
36630 { "aix32", OPTION_MASK_64BIT, true, false },
36632 { "64", OPTION_MASK_64BIT, false, false },
36633 { "32", OPTION_MASK_64BIT, true, false },
36636 #ifdef OPTION_MASK_EABI
36637 { "eabi", OPTION_MASK_EABI, false, false },
36639 #ifdef OPTION_MASK_LITTLE_ENDIAN
36640 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36641 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36643 #ifdef OPTION_MASK_RELOCATABLE
36644 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36646 #ifdef OPTION_MASK_STRICT_ALIGN
36647 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36649 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36650 { "string", OPTION_MASK_STRING, false, false },
36653 /* Builtin mask mapping for printing the flags. */
36654 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36656 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36657 { "vsx", RS6000_BTM_VSX, false, false },
36658 { "paired", RS6000_BTM_PAIRED, false, false },
36659 { "fre", RS6000_BTM_FRE, false, false },
36660 { "fres", RS6000_BTM_FRES, false, false },
36661 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36662 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36663 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36664 { "cell", RS6000_BTM_CELL, false, false },
36665 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36666 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36667 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36668 { "crypto", RS6000_BTM_CRYPTO, false, false },
36669 { "htm", RS6000_BTM_HTM, false, false },
36670 { "hard-dfp", RS6000_BTM_DFP, false, false },
36671 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36672 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36673 { "float128", RS6000_BTM_FLOAT128, false, false },
36674 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36677 /* Option variables that we want to support inside attribute((target)) and
36678 #pragma GCC target operations. */
36680 struct rs6000_opt_var {
36681 const char *name; /* option name */
36682 size_t global_offset; /* offset of the option in global_options. */
36683 size_t target_offset; /* offset of the option in target options. */
36686 static struct rs6000_opt_var const rs6000_opt_vars[] =
36689 offsetof (struct gcc_options, x_TARGET_FRIZ),
36690 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36691 { "avoid-indexed-addresses",
36692 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36693 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36695 offsetof (struct gcc_options, x_rs6000_paired_float),
36696 offsetof (struct cl_target_option, x_rs6000_paired_float), },
36698 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36699 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36700 { "optimize-swaps",
36701 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36702 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36703 { "allow-movmisalign",
36704 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36705 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36707 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36708 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36710 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36711 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36712 { "align-branch-targets",
36713 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36714 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36716 offsetof (struct gcc_options, x_tls_markers),
36717 offsetof (struct cl_target_option, x_tls_markers), },
36719 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36720 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36722 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36723 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36726 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36727 parsing. Return true if there were no errors. */
36730 rs6000_inner_target_options (tree args, bool attr_p)
36734 if (args == NULL_TREE)
36737 else if (TREE_CODE (args) == STRING_CST)
36739 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36742 while ((q = strtok (p, ",")) != NULL)
36744 bool error_p = false;
36745 bool not_valid_p = false;
36746 const char *cpu_opt = NULL;
36749 if (strncmp (q, "cpu=", 4) == 0)
36751 int cpu_index = rs6000_cpu_name_lookup (q+4);
36752 if (cpu_index >= 0)
36753 rs6000_cpu_index = cpu_index;
36760 else if (strncmp (q, "tune=", 5) == 0)
36762 int tune_index = rs6000_cpu_name_lookup (q+5);
36763 if (tune_index >= 0)
36764 rs6000_tune_index = tune_index;
36774 bool invert = false;
36778 if (strncmp (r, "no-", 3) == 0)
36784 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36785 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36787 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36789 if (!rs6000_opt_masks[i].valid_target)
36790 not_valid_p = true;
36794 rs6000_isa_flags_explicit |= mask;
36796 /* VSX needs altivec, so -mvsx automagically sets
36797 altivec and disables -mavoid-indexed-addresses. */
36800 if (mask == OPTION_MASK_VSX)
36802 mask |= OPTION_MASK_ALTIVEC;
36803 TARGET_AVOID_XFORM = 0;
36807 if (rs6000_opt_masks[i].invert)
36811 rs6000_isa_flags &= ~mask;
36813 rs6000_isa_flags |= mask;
36818 if (error_p && !not_valid_p)
36820 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36821 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36823 size_t j = rs6000_opt_vars[i].global_offset;
36824 *((int *) ((char *)&global_options + j)) = !invert;
36826 not_valid_p = false;
36834 const char *eprefix, *esuffix;
36839 eprefix = "__attribute__((__target__(";
36844 eprefix = "#pragma GCC target ";
36849 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36851 else if (not_valid_p)
36852 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36854 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36859 else if (TREE_CODE (args) == TREE_LIST)
36863 tree value = TREE_VALUE (args);
36866 bool ret2 = rs6000_inner_target_options (value, attr_p);
36870 args = TREE_CHAIN (args);
36872 while (args != NULL_TREE);
36877 error ("attribute %<target%> argument not a string");
36884 /* Print out the target options as a list for -mdebug=target. */
36887 rs6000_debug_target_options (tree args, const char *prefix)
36889 if (args == NULL_TREE)
36890 fprintf (stderr, "%s<NULL>", prefix);
36892 else if (TREE_CODE (args) == STRING_CST)
36894 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36897 while ((q = strtok (p, ",")) != NULL)
36900 fprintf (stderr, "%s\"%s\"", prefix, q);
36905 else if (TREE_CODE (args) == TREE_LIST)
36909 tree value = TREE_VALUE (args);
36912 rs6000_debug_target_options (value, prefix);
36915 args = TREE_CHAIN (args);
36917 while (args != NULL_TREE);
36921 gcc_unreachable ();
36927 /* Hook to validate attribute((target("..."))). */
36930 rs6000_valid_attribute_p (tree fndecl,
36931 tree ARG_UNUSED (name),
36935 struct cl_target_option cur_target;
36938 tree new_target, new_optimize;
36939 tree func_optimize;
36941 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36943 if (TARGET_DEBUG_TARGET)
36945 tree tname = DECL_NAME (fndecl);
36946 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36948 fprintf (stderr, "function: %.*s\n",
36949 (int) IDENTIFIER_LENGTH (tname),
36950 IDENTIFIER_POINTER (tname));
36952 fprintf (stderr, "function: unknown\n");
36954 fprintf (stderr, "args:");
36955 rs6000_debug_target_options (args, " ");
36956 fprintf (stderr, "\n");
36959 fprintf (stderr, "flags: 0x%x\n", flags);
36961 fprintf (stderr, "--------------------\n");
36964 /* attribute((target("default"))) does nothing, beyond
36965 affecting multi-versioning. */
36966 if (TREE_VALUE (args)
36967 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36968 && TREE_CHAIN (args) == NULL_TREE
36969 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36972 old_optimize = build_optimization_node (&global_options);
36973 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36975 /* If the function changed the optimization levels as well as setting target
36976 options, start with the optimizations specified. */
36977 if (func_optimize && func_optimize != old_optimize)
36978 cl_optimization_restore (&global_options,
36979 TREE_OPTIMIZATION (func_optimize));
36981 /* The target attributes may also change some optimization flags, so update
36982 the optimization options if necessary. */
36983 cl_target_option_save (&cur_target, &global_options);
36984 rs6000_cpu_index = rs6000_tune_index = -1;
36985 ret = rs6000_inner_target_options (args, true);
36987 /* Set up any additional state. */
36990 ret = rs6000_option_override_internal (false);
36991 new_target = build_target_option_node (&global_options);
36996 new_optimize = build_optimization_node (&global_options);
37003 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
37005 if (old_optimize != new_optimize)
37006 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
37009 cl_target_option_restore (&global_options, &cur_target);
37011 if (old_optimize != new_optimize)
37012 cl_optimization_restore (&global_options,
37013 TREE_OPTIMIZATION (old_optimize));
37019 /* Hook to validate the current #pragma GCC target and set the state, and
37020 update the macros based on what was changed. If ARGS is NULL, then
37021 POP_TARGET is used to reset the options. */
37024 rs6000_pragma_target_parse (tree args, tree pop_target)
37026 tree prev_tree = build_target_option_node (&global_options);
37028 struct cl_target_option *prev_opt, *cur_opt;
37029 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
37030 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
37032 if (TARGET_DEBUG_TARGET)
37034 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
37035 fprintf (stderr, "args:");
37036 rs6000_debug_target_options (args, " ");
37037 fprintf (stderr, "\n");
37041 fprintf (stderr, "pop_target:\n");
37042 debug_tree (pop_target);
37045 fprintf (stderr, "pop_target: <NULL>\n");
37047 fprintf (stderr, "--------------------\n");
37052 cur_tree = ((pop_target)
37054 : target_option_default_node);
37055 cl_target_option_restore (&global_options,
37056 TREE_TARGET_OPTION (cur_tree));
37060 rs6000_cpu_index = rs6000_tune_index = -1;
37061 if (!rs6000_inner_target_options (args, false)
37062 || !rs6000_option_override_internal (false)
37063 || (cur_tree = build_target_option_node (&global_options))
37066 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
37067 fprintf (stderr, "invalid pragma\n");
37073 target_option_current_node = cur_tree;
37074 rs6000_activate_target_options (target_option_current_node);
37076 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
37077 change the macros that are defined. */
37078 if (rs6000_target_modify_macros_ptr)
37080 prev_opt = TREE_TARGET_OPTION (prev_tree);
37081 prev_bumask = prev_opt->x_rs6000_builtin_mask;
37082 prev_flags = prev_opt->x_rs6000_isa_flags;
37084 cur_opt = TREE_TARGET_OPTION (cur_tree);
37085 cur_flags = cur_opt->x_rs6000_isa_flags;
37086 cur_bumask = cur_opt->x_rs6000_builtin_mask;
37088 diff_bumask = (prev_bumask ^ cur_bumask);
37089 diff_flags = (prev_flags ^ cur_flags);
37091 if ((diff_flags != 0) || (diff_bumask != 0))
37093 /* Delete old macros. */
37094 rs6000_target_modify_macros_ptr (false,
37095 prev_flags & diff_flags,
37096 prev_bumask & diff_bumask);
37098 /* Define new macros. */
37099 rs6000_target_modify_macros_ptr (true,
37100 cur_flags & diff_flags,
37101 cur_bumask & diff_bumask);
37109 /* Remember the last target of rs6000_set_current_function. */
37110 static GTY(()) tree rs6000_previous_fndecl;
37112 /* Restore target's globals from NEW_TREE and invalidate the
37113 rs6000_previous_fndecl cache. */
37116 rs6000_activate_target_options (tree new_tree)
37118 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
37119 if (TREE_TARGET_GLOBALS (new_tree))
37120 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
37121 else if (new_tree == target_option_default_node)
37122 restore_target_globals (&default_target_globals);
37124 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
37125 rs6000_previous_fndecl = NULL_TREE;
37128 /* Establish appropriate back-end context for processing the function
37129 FNDECL. The argument might be NULL to indicate processing at top
37130 level, outside of any function scope. */
37132 rs6000_set_current_function (tree fndecl)
37134 if (TARGET_DEBUG_TARGET)
37136 fprintf (stderr, "\n==================== rs6000_set_current_function");
37139 fprintf (stderr, ", fndecl %s (%p)",
37140 (DECL_NAME (fndecl)
37141 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
37142 : "<unknown>"), (void *)fndecl);
37144 if (rs6000_previous_fndecl)
37145 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
37147 fprintf (stderr, "\n");
37150 /* Only change the context if the function changes. This hook is called
37151 several times in the course of compiling a function, and we don't want to
37152 slow things down too much or call target_reinit when it isn't safe. */
37153 if (fndecl == rs6000_previous_fndecl)
37157 if (rs6000_previous_fndecl == NULL_TREE)
37158 old_tree = target_option_current_node;
37159 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
37160 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
37162 old_tree = target_option_default_node;
37165 if (fndecl == NULL_TREE)
37167 if (old_tree != target_option_current_node)
37168 new_tree = target_option_current_node;
37170 new_tree = NULL_TREE;
37174 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37175 if (new_tree == NULL_TREE)
37176 new_tree = target_option_default_node;
37179 if (TARGET_DEBUG_TARGET)
37183 fprintf (stderr, "\nnew fndecl target specific options:\n");
37184 debug_tree (new_tree);
37189 fprintf (stderr, "\nold fndecl target specific options:\n");
37190 debug_tree (old_tree);
37193 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
37194 fprintf (stderr, "--------------------\n");
37197 if (new_tree && old_tree != new_tree)
37198 rs6000_activate_target_options (new_tree);
37201 rs6000_previous_fndecl = fndecl;
37205 /* Save the current options */
37208 rs6000_function_specific_save (struct cl_target_option *ptr,
37209 struct gcc_options *opts)
37211 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
37212 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
37215 /* Restore the current options */
37218 rs6000_function_specific_restore (struct gcc_options *opts,
37219 struct cl_target_option *ptr)
37222 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
37223 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
37224 (void) rs6000_option_override_internal (false);
37227 /* Print the current options */
37230 rs6000_function_specific_print (FILE *file, int indent,
37231 struct cl_target_option *ptr)
37233 rs6000_print_isa_options (file, indent, "Isa options set",
37234 ptr->x_rs6000_isa_flags);
37236 rs6000_print_isa_options (file, indent, "Isa options explicit",
37237 ptr->x_rs6000_isa_flags_explicit);
37240 /* Helper function to print the current isa or misc options on a line. */
37243 rs6000_print_options_internal (FILE *file,
37245 const char *string,
37246 HOST_WIDE_INT flags,
37247 const char *prefix,
37248 const struct rs6000_opt_mask *opts,
37249 size_t num_elements)
37252 size_t start_column = 0;
37254 size_t max_column = 120;
37255 size_t prefix_len = strlen (prefix);
37256 size_t comma_len = 0;
37257 const char *comma = "";
37260 start_column += fprintf (file, "%*s", indent, "");
37264 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
37268 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
37270 /* Print the various mask options. */
37271 cur_column = start_column;
37272 for (i = 0; i < num_elements; i++)
37274 bool invert = opts[i].invert;
37275 const char *name = opts[i].name;
37276 const char *no_str = "";
37277 HOST_WIDE_INT mask = opts[i].mask;
37278 size_t len = comma_len + prefix_len + strlen (name);
37282 if ((flags & mask) == 0)
37285 len += sizeof ("no-") - 1;
37293 if ((flags & mask) != 0)
37296 len += sizeof ("no-") - 1;
37303 if (cur_column > max_column)
37305 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
37306 cur_column = start_column + len;
37310 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
37312 comma_len = sizeof (", ") - 1;
37315 fputs ("\n", file);
37318 /* Helper function to print the current isa options on a line. */
37321 rs6000_print_isa_options (FILE *file, int indent, const char *string,
37322 HOST_WIDE_INT flags)
37324 rs6000_print_options_internal (file, indent, string, flags, "-m",
37325 &rs6000_opt_masks[0],
37326 ARRAY_SIZE (rs6000_opt_masks));
37330 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
37331 HOST_WIDE_INT flags)
37333 rs6000_print_options_internal (file, indent, string, flags, "",
37334 &rs6000_builtin_mask_names[0],
37335 ARRAY_SIZE (rs6000_builtin_mask_names));
37338 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37339 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37340 -mupper-regs-df, etc.).
37342 If the user used -mno-power8-vector, we need to turn off all of the implicit
37343 ISA 2.07 and 3.0 options that relate to the vector unit.
37345 If the user used -mno-power9-vector, we need to turn off all of the implicit
37346 ISA 3.0 options that relate to the vector unit.
37348 This function does not handle explicit options such as the user specifying
37349 -mdirect-move. These are handled in rs6000_option_override_internal, and
37350 the appropriate error is given if needed.
37352 We return a mask of all of the implicit options that should not be enabled
37355 static HOST_WIDE_INT
37356 rs6000_disable_incompatible_switches (void)
37358 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37361 static const struct {
37362 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37363 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37364 const char *const name; /* name of the switch. */
37366 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37367 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37368 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37371 for (i = 0; i < ARRAY_SIZE (flags); i++)
37373 HOST_WIDE_INT no_flag = flags[i].no_flag;
37375 if ((rs6000_isa_flags & no_flag) == 0
37376 && (rs6000_isa_flags_explicit & no_flag) != 0)
37378 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37379 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37385 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37386 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37388 set_flags &= ~rs6000_opt_masks[j].mask;
37389 error ("%<-mno-%s%> turns off %<-m%s%>",
37391 rs6000_opt_masks[j].name);
37394 gcc_assert (!set_flags);
37397 rs6000_isa_flags &= ~dep_flags;
37398 ignore_masks |= no_flag | dep_flags;
37402 return ignore_masks;
37406 /* Helper function for printing the function name when debugging. */
37408 static const char *
37409 get_decl_name (tree fn)
37416 name = DECL_NAME (fn);
37418 return "<no-name>";
37420 return IDENTIFIER_POINTER (name);
37423 /* Return the clone id of the target we are compiling code for in a target
37424 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37425 the priority list for the target clones (ordered from lowest to
37429 rs6000_clone_priority (tree fndecl)
37431 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37432 HOST_WIDE_INT isa_masks;
37433 int ret = CLONE_DEFAULT;
37434 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37435 const char *attrs_str = NULL;
37437 attrs = TREE_VALUE (TREE_VALUE (attrs));
37438 attrs_str = TREE_STRING_POINTER (attrs);
37440 /* Return priority zero for default function. Return the ISA needed for the
37441 function if it is not the default. */
37442 if (strcmp (attrs_str, "default") != 0)
37444 if (fn_opts == NULL_TREE)
37445 fn_opts = target_option_default_node;
37447 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37448 isa_masks = rs6000_isa_flags;
37450 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37452 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37453 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37457 if (TARGET_DEBUG_TARGET)
37458 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37459 get_decl_name (fndecl), ret);
37464 /* This compares the priority of target features in function DECL1 and DECL2.
37465 It returns positive value if DECL1 is higher priority, negative value if
37466 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37467 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37470 rs6000_compare_version_priority (tree decl1, tree decl2)
37472 int priority1 = rs6000_clone_priority (decl1);
37473 int priority2 = rs6000_clone_priority (decl2);
37474 int ret = priority1 - priority2;
37476 if (TARGET_DEBUG_TARGET)
37477 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37478 get_decl_name (decl1), get_decl_name (decl2), ret);
37483 /* Make a dispatcher declaration for the multi-versioned function DECL.
37484 Calls to DECL function will be replaced with calls to the dispatcher
37485 by the front-end. Returns the decl of the dispatcher function. */
37488 rs6000_get_function_versions_dispatcher (void *decl)
37490 tree fn = (tree) decl;
37491 struct cgraph_node *node = NULL;
37492 struct cgraph_node *default_node = NULL;
37493 struct cgraph_function_version_info *node_v = NULL;
37494 struct cgraph_function_version_info *first_v = NULL;
37496 tree dispatch_decl = NULL;
37498 struct cgraph_function_version_info *default_version_info = NULL;
37499 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37501 if (TARGET_DEBUG_TARGET)
37502 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37503 get_decl_name (fn));
37505 node = cgraph_node::get (fn);
37506 gcc_assert (node != NULL);
37508 node_v = node->function_version ();
37509 gcc_assert (node_v != NULL);
37511 if (node_v->dispatcher_resolver != NULL)
37512 return node_v->dispatcher_resolver;
37514 /* Find the default version and make it the first node. */
37516 /* Go to the beginning of the chain. */
37517 while (first_v->prev != NULL)
37518 first_v = first_v->prev;
37520 default_version_info = first_v;
37521 while (default_version_info != NULL)
37523 const tree decl2 = default_version_info->this_node->decl;
37524 if (is_function_default_version (decl2))
37526 default_version_info = default_version_info->next;
37529 /* If there is no default node, just return NULL. */
37530 if (default_version_info == NULL)
37533 /* Make default info the first node. */
37534 if (first_v != default_version_info)
37536 default_version_info->prev->next = default_version_info->next;
37537 if (default_version_info->next)
37538 default_version_info->next->prev = default_version_info->prev;
37539 first_v->prev = default_version_info;
37540 default_version_info->next = first_v;
37541 default_version_info->prev = NULL;
37544 default_node = default_version_info->this_node;
37546 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37547 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37548 "target_clones attribute needs GLIBC (2.23 and newer) that "
37549 "exports hardware capability bits");
37552 if (targetm.has_ifunc_p ())
37554 struct cgraph_function_version_info *it_v = NULL;
37555 struct cgraph_node *dispatcher_node = NULL;
37556 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37558 /* Right now, the dispatching is done via ifunc. */
37559 dispatch_decl = make_dispatcher_decl (default_node->decl);
37561 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37562 gcc_assert (dispatcher_node != NULL);
37563 dispatcher_node->dispatcher_function = 1;
37564 dispatcher_version_info
37565 = dispatcher_node->insert_new_function_version ();
37566 dispatcher_version_info->next = default_version_info;
37567 dispatcher_node->definition = 1;
37569 /* Set the dispatcher for all the versions. */
37570 it_v = default_version_info;
37571 while (it_v != NULL)
37573 it_v->dispatcher_resolver = dispatch_decl;
37579 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37580 "multiversioning needs ifunc which is not supported "
37585 return dispatch_decl;
37588 /* Make the resolver function decl to dispatch the versions of a multi-
37589 versioned function, DEFAULT_DECL. Create an empty basic block in the
37590 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37594 make_resolver_func (const tree default_decl,
37595 const tree dispatch_decl,
37596 basic_block *empty_bb)
37598 /* Make the resolver function static. The resolver function returns
37600 tree decl_name = clone_function_name (default_decl, "resolver");
37601 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37602 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37603 tree decl = build_fn_decl (resolver_name, type);
37604 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37606 DECL_NAME (decl) = decl_name;
37607 TREE_USED (decl) = 1;
37608 DECL_ARTIFICIAL (decl) = 1;
37609 DECL_IGNORED_P (decl) = 0;
37610 TREE_PUBLIC (decl) = 0;
37611 DECL_UNINLINABLE (decl) = 1;
37613 /* Resolver is not external, body is generated. */
37614 DECL_EXTERNAL (decl) = 0;
37615 DECL_EXTERNAL (dispatch_decl) = 0;
37617 DECL_CONTEXT (decl) = NULL_TREE;
37618 DECL_INITIAL (decl) = make_node (BLOCK);
37619 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37621 /* Build result decl and add to function_decl. */
37622 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37623 DECL_ARTIFICIAL (t) = 1;
37624 DECL_IGNORED_P (t) = 1;
37625 DECL_RESULT (decl) = t;
37627 gimplify_function_tree (decl);
37628 push_cfun (DECL_STRUCT_FUNCTION (decl));
37629 *empty_bb = init_lowered_empty_function (decl, false,
37630 profile_count::uninitialized ());
37632 cgraph_node::add_new_function (decl, true);
37633 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37637 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37638 DECL_ATTRIBUTES (dispatch_decl)
37639 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37641 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37646 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37647 return a pointer to VERSION_DECL if we are running on a machine that
37648 supports the index CLONE_ISA hardware architecture bits. This function will
37649 be called during version dispatch to decide which function version to
37650 execute. It returns the basic block at the end, to which more conditions
37654 add_condition_to_bb (tree function_decl, tree version_decl,
37655 int clone_isa, basic_block new_bb)
37657 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37659 gcc_assert (new_bb != NULL);
37660 gimple_seq gseq = bb_seq (new_bb);
37663 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37664 build_fold_addr_expr (version_decl));
37665 tree result_var = create_tmp_var (ptr_type_node);
37666 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37667 gimple *return_stmt = gimple_build_return (result_var);
37669 if (clone_isa == CLONE_DEFAULT)
37671 gimple_seq_add_stmt (&gseq, convert_stmt);
37672 gimple_seq_add_stmt (&gseq, return_stmt);
37673 set_bb_seq (new_bb, gseq);
37674 gimple_set_bb (convert_stmt, new_bb);
37675 gimple_set_bb (return_stmt, new_bb);
37680 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37681 tree cond_var = create_tmp_var (bool_int_type_node);
37682 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37683 const char *arg_str = rs6000_clone_map[clone_isa].name;
37684 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37685 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37686 gimple_call_set_lhs (call_cond_stmt, cond_var);
37688 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37689 gimple_set_bb (call_cond_stmt, new_bb);
37690 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37692 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37693 NULL_TREE, NULL_TREE);
37694 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37695 gimple_set_bb (if_else_stmt, new_bb);
37696 gimple_seq_add_stmt (&gseq, if_else_stmt);
37698 gimple_seq_add_stmt (&gseq, convert_stmt);
37699 gimple_seq_add_stmt (&gseq, return_stmt);
37700 set_bb_seq (new_bb, gseq);
37702 basic_block bb1 = new_bb;
37703 edge e12 = split_block (bb1, if_else_stmt);
37704 basic_block bb2 = e12->dest;
37705 e12->flags &= ~EDGE_FALLTHRU;
37706 e12->flags |= EDGE_TRUE_VALUE;
37708 edge e23 = split_block (bb2, return_stmt);
37709 gimple_set_bb (convert_stmt, bb2);
37710 gimple_set_bb (return_stmt, bb2);
37712 basic_block bb3 = e23->dest;
37713 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37716 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37722 /* This function generates the dispatch function for multi-versioned functions.
37723 DISPATCH_DECL is the function which will contain the dispatch logic.
37724 FNDECLS are the function choices for dispatch, and is a tree chain.
37725 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37726 code is generated. */
37729 dispatch_function_versions (tree dispatch_decl,
37731 basic_block *empty_bb)
37735 vec<tree> *fndecls;
37736 tree clones[CLONE_MAX];
37738 if (TARGET_DEBUG_TARGET)
37739 fputs ("dispatch_function_versions, top\n", stderr);
37741 gcc_assert (dispatch_decl != NULL
37742 && fndecls_p != NULL
37743 && empty_bb != NULL);
37745 /* fndecls_p is actually a vector. */
37746 fndecls = static_cast<vec<tree> *> (fndecls_p);
37748 /* At least one more version other than the default. */
37749 gcc_assert (fndecls->length () >= 2);
37751 /* The first version in the vector is the default decl. */
37752 memset ((void *) clones, '\0', sizeof (clones));
37753 clones[CLONE_DEFAULT] = (*fndecls)[0];
37755 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37756 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37757 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37758 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37759 to insert the code here to do the call. */
37761 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37763 int priority = rs6000_clone_priority (ele);
37764 if (!clones[priority])
37765 clones[priority] = ele;
37768 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37771 if (TARGET_DEBUG_TARGET)
37772 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37773 ix, get_decl_name (clones[ix]));
37775 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37782 /* Generate the dispatching code body to dispatch multi-versioned function
37783 DECL. The target hook is called to process the "target" attributes and
37784 provide the code to dispatch the right function at run-time. NODE points
37785 to the dispatcher decl whose body will be created. */
37788 rs6000_generate_version_dispatcher_body (void *node_p)
37791 basic_block empty_bb;
37792 struct cgraph_node *node = (cgraph_node *) node_p;
37793 struct cgraph_function_version_info *ninfo = node->function_version ();
37795 if (ninfo->dispatcher_resolver)
37796 return ninfo->dispatcher_resolver;
37798 /* node is going to be an alias, so remove the finalized bit. */
37799 node->definition = false;
37801 /* The first version in the chain corresponds to the default version. */
37802 ninfo->dispatcher_resolver = resolver
37803 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37805 if (TARGET_DEBUG_TARGET)
37806 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37807 get_decl_name (resolver));
37809 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37810 auto_vec<tree, 2> fn_ver_vec;
37812 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37814 vinfo = vinfo->next)
37816 struct cgraph_node *version = vinfo->this_node;
37817 /* Check for virtual functions here again, as by this time it should
37818 have been determined if this function needs a vtable index or
37819 not. This happens for methods in derived classes that override
37820 virtual methods in base classes but are not explicitly marked as
37822 if (DECL_VINDEX (version->decl))
37823 sorry ("Virtual function multiversioning not supported");
37825 fn_ver_vec.safe_push (version->decl);
37828 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37829 cgraph_edge::rebuild_edges ();
37835 /* Hook to determine if one function can safely inline another. */
37838 rs6000_can_inline_p (tree caller, tree callee)
37841 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37842 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37844 /* If callee has no option attributes, then it is ok to inline. */
37848 /* If caller has no option attributes, but callee does then it is not ok to
37850 else if (!caller_tree)
37855 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37856 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37858 /* Callee's options should a subset of the caller's, i.e. a vsx function
37859 can inline an altivec function but a non-vsx function can't inline a
37861 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37862 == callee_opts->x_rs6000_isa_flags)
37866 if (TARGET_DEBUG_TARGET)
37867 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37868 get_decl_name (caller), get_decl_name (callee),
37869 (ret ? "can" : "cannot"));
37874 /* Allocate a stack temp and fixup the address so it meets the particular
37875 memory requirements (either offetable or REG+REG addressing). */
37878 rs6000_allocate_stack_temp (machine_mode mode,
37879 bool offsettable_p,
37882 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37883 rtx addr = XEXP (stack, 0);
37884 int strict_p = reload_completed;
37886 if (!legitimate_indirect_address_p (addr, strict_p))
37889 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37890 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37892 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37893 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37899 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
37900 to such a form to deal with memory reference instructions like STFIWX that
37901 only take reg+reg addressing. */
37904 rs6000_address_for_fpconvert (rtx x)
37908 gcc_assert (MEM_P (x));
37909 addr = XEXP (x, 0);
37910 if (can_create_pseudo_p ()
37911 && ! legitimate_indirect_address_p (addr, reload_completed)
37912 && ! legitimate_indexed_address_p (addr, reload_completed))
37914 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37916 rtx reg = XEXP (addr, 0);
37917 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37918 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37919 gcc_assert (REG_P (reg));
37920 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37923 else if (GET_CODE (addr) == PRE_MODIFY)
37925 rtx reg = XEXP (addr, 0);
37926 rtx expr = XEXP (addr, 1);
37927 gcc_assert (REG_P (reg));
37928 gcc_assert (GET_CODE (expr) == PLUS);
37929 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37933 x = replace_equiv_address (x, copy_addr_to_reg (addr));
37939 /* Given a memory reference, if it is not in the form for altivec memory
37940 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
37941 convert to the altivec format. */
37944 rs6000_address_for_altivec (rtx x)
37946 gcc_assert (MEM_P (x));
37947 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
37949 rtx addr = XEXP (x, 0);
37951 if (!legitimate_indexed_address_p (addr, reload_completed)
37952 && !legitimate_indirect_address_p (addr, reload_completed))
37953 addr = copy_to_mode_reg (Pmode, addr);
37955 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
37956 x = change_address (x, GET_MODE (x), addr);
37962 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37964 On the RS/6000, all integer constants are acceptable, most won't be valid
37965 for particular insns, though. Only easy FP constants are acceptable. */
37968 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37970 if (TARGET_ELF && tls_referenced_p (x))
37973 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
37974 || GET_MODE (x) == VOIDmode
37975 || (TARGET_POWERPC64 && mode == DImode)
37976 || easy_fp_constant (x, mode)
37977 || easy_vector_constant (x, mode));
37981 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37984 chain_already_loaded (rtx_insn *last)
37986 for (; last != NULL; last = PREV_INSN (last))
37988 if (NONJUMP_INSN_P (last))
37990 rtx patt = PATTERN (last);
37992 if (GET_CODE (patt) == SET)
37994 rtx lhs = XEXP (patt, 0);
37996 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
38004 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
38007 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38009 const bool direct_call_p
38010 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
38011 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
38012 rtx toc_load = NULL_RTX;
38013 rtx toc_restore = NULL_RTX;
38015 rtx abi_reg = NULL_RTX;
38020 /* Handle longcall attributes. */
38021 if (INTVAL (cookie) & CALL_LONG)
38022 func_desc = rs6000_longcall_ref (func_desc);
38024 /* Handle indirect calls. */
38025 if (GET_CODE (func_desc) != SYMBOL_REF
38026 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
38028 /* Save the TOC into its reserved slot before the call,
38029 and prepare to restore it after the call. */
38030 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
38031 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
38032 rtx stack_toc_mem = gen_frame_mem (Pmode,
38033 gen_rtx_PLUS (Pmode, stack_ptr,
38034 stack_toc_offset));
38035 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
38036 gen_rtvec (1, stack_toc_offset),
38038 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
38040 /* Can we optimize saving the TOC in the prologue or
38041 do we need to do it at every call? */
38042 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
38043 cfun->machine->save_toc_in_prologue = true;
38046 MEM_VOLATILE_P (stack_toc_mem) = 1;
38047 emit_move_insn (stack_toc_mem, toc_reg);
38050 if (DEFAULT_ABI == ABI_ELFv2)
38052 /* A function pointer in the ELFv2 ABI is just a plain address, but
38053 the ABI requires it to be loaded into r12 before the call. */
38054 func_addr = gen_rtx_REG (Pmode, 12);
38055 emit_move_insn (func_addr, func_desc);
38056 abi_reg = func_addr;
38060 /* A function pointer under AIX is a pointer to a data area whose
38061 first word contains the actual address of the function, whose
38062 second word contains a pointer to its TOC, and whose third word
38063 contains a value to place in the static chain register (r11).
38064 Note that if we load the static chain, our "trampoline" need
38065 not have any executable code. */
38067 /* Load up address of the actual function. */
38068 func_desc = force_reg (Pmode, func_desc);
38069 func_addr = gen_reg_rtx (Pmode);
38070 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
38072 /* Prepare to load the TOC of the called function. Note that the
38073 TOC load must happen immediately before the actual call so
38074 that unwinding the TOC registers works correctly. See the
38075 comment in frob_update_context. */
38076 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
38077 rtx func_toc_mem = gen_rtx_MEM (Pmode,
38078 gen_rtx_PLUS (Pmode, func_desc,
38080 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
38082 /* If we have a static chain, load it up. But, if the call was
38083 originally direct, the 3rd word has not been written since no
38084 trampoline has been built, so we ought not to load it, lest we
38085 override a static chain value. */
38087 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
38088 && !chain_already_loaded (get_current_sequence ()->next->last))
38090 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
38091 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
38092 rtx func_sc_mem = gen_rtx_MEM (Pmode,
38093 gen_rtx_PLUS (Pmode, func_desc,
38095 emit_move_insn (sc_reg, func_sc_mem);
38102 /* Direct calls use the TOC: for local calls, the callee will
38103 assume the TOC register is set; for non-local calls, the
38104 PLT stub needs the TOC register. */
38106 func_addr = func_desc;
38109 /* Create the call. */
38110 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
38111 if (value != NULL_RTX)
38112 call[0] = gen_rtx_SET (value, call[0]);
38116 call[n_call++] = toc_load;
38118 call[n_call++] = toc_restore;
38120 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
38122 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
38123 insn = emit_call_insn (insn);
38125 /* Mention all registers defined by the ABI to hold information
38126 as uses in CALL_INSN_FUNCTION_USAGE. */
38128 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38131 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
38134 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38139 gcc_assert (INTVAL (cookie) == 0);
38141 /* Create the call. */
38142 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
38143 if (value != NULL_RTX)
38144 call[0] = gen_rtx_SET (value, call[0]);
38146 call[1] = simple_return_rtx;
38148 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
38149 insn = emit_call_insn (insn);
38151 /* Note use of the TOC register. */
38152 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
38155 /* Return whether we need to always update the saved TOC pointer when we update
38156 the stack pointer. */
38159 rs6000_save_toc_in_prologue_p (void)
38161 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38164 #ifdef HAVE_GAS_HIDDEN
38165 # define USE_HIDDEN_LINKONCE 1
38167 # define USE_HIDDEN_LINKONCE 0
38170 /* Fills in the label name that should be used for a 476 link stack thunk. */
38173 get_ppc476_thunk_name (char name[32])
38175 gcc_assert (TARGET_LINK_STACK);
38177 if (USE_HIDDEN_LINKONCE)
38178 sprintf (name, "__ppc476.get_thunk");
38180 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38183 /* This function emits the simple thunk routine that is used to preserve
38184 the link stack on the 476 cpu. */
38186 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38188 rs6000_code_end (void)
38193 if (!TARGET_LINK_STACK)
38196 get_ppc476_thunk_name (name);
38198 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38199 build_function_type_list (void_type_node, NULL_TREE));
38200 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38201 NULL_TREE, void_type_node);
38202 TREE_PUBLIC (decl) = 1;
38203 TREE_STATIC (decl) = 1;
38206 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38208 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38209 targetm.asm_out.unique_section (decl, 0);
38210 switch_to_section (get_named_section (decl, NULL, 0));
38211 DECL_WEAK (decl) = 1;
38212 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38213 targetm.asm_out.globalize_label (asm_out_file, name);
38214 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38215 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38220 switch_to_section (text_section);
38221 ASM_OUTPUT_LABEL (asm_out_file, name);
38224 DECL_INITIAL (decl) = make_node (BLOCK);
38225 current_function_decl = decl;
38226 allocate_struct_function (decl, false);
38227 init_function_start (decl);
38228 first_function_block_is_cold = false;
38229 /* Make sure unwind info is emitted for the thunk if needed. */
38230 final_start_function (emit_barrier (), asm_out_file, 1);
38232 fputs ("\tblr\n", asm_out_file);
38234 final_end_function ();
38235 init_insn_lengths ();
38236 free_after_compilation (cfun);
38238 current_function_decl = NULL;
38241 /* Add r30 to hard reg set if the prologue sets it up and it is not
38242 pic_offset_table_rtx. */
38245 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38247 if (!TARGET_SINGLE_PIC_BASE
38249 && TARGET_MINIMAL_TOC
38250 && !constant_pool_empty_p ())
38251 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38252 if (cfun->machine->split_stack_argp_used)
38253 add_to_hard_reg_set (&set->set, Pmode, 12);
38255 /* Make sure the hard reg set doesn't include r2, which was possibly added
38256 via PIC_OFFSET_TABLE_REGNUM. */
38258 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38262 /* Helper function for rs6000_split_logical to emit a logical instruction after
38263 spliting the operation to single GPR registers.
38265 DEST is the destination register.
38266 OP1 and OP2 are the input source registers.
38267 CODE is the base operation (AND, IOR, XOR, NOT).
38268 MODE is the machine mode.
38269 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38270 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38271 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38274 rs6000_split_logical_inner (rtx dest,
38277 enum rtx_code code,
38279 bool complement_final_p,
38280 bool complement_op1_p,
38281 bool complement_op2_p)
38285 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38286 if (op2 && GET_CODE (op2) == CONST_INT
38287 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38288 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38290 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38291 HOST_WIDE_INT value = INTVAL (op2) & mask;
38293 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38298 emit_insn (gen_rtx_SET (dest, const0_rtx));
38302 else if (value == mask)
38304 if (!rtx_equal_p (dest, op1))
38305 emit_insn (gen_rtx_SET (dest, op1));
38310 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38311 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38312 else if (code == IOR || code == XOR)
38316 if (!rtx_equal_p (dest, op1))
38317 emit_insn (gen_rtx_SET (dest, op1));
38323 if (code == AND && mode == SImode
38324 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38326 emit_insn (gen_andsi3 (dest, op1, op2));
38330 if (complement_op1_p)
38331 op1 = gen_rtx_NOT (mode, op1);
38333 if (complement_op2_p)
38334 op2 = gen_rtx_NOT (mode, op2);
38336 /* For canonical RTL, if only one arm is inverted it is the first. */
38337 if (!complement_op1_p && complement_op2_p)
38338 std::swap (op1, op2);
38340 bool_rtx = ((code == NOT)
38341 ? gen_rtx_NOT (mode, op1)
38342 : gen_rtx_fmt_ee (code, mode, op1, op2));
38344 if (complement_final_p)
38345 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38347 emit_insn (gen_rtx_SET (dest, bool_rtx));
38350 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38351 operations are split immediately during RTL generation to allow for more
38352 optimizations of the AND/IOR/XOR.
38354 OPERANDS is an array containing the destination and two input operands.
38355 CODE is the base operation (AND, IOR, XOR, NOT).
38356 MODE is the machine mode.
38357 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38358 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38359 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38360 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38361 formation of the AND instructions. */
38364 rs6000_split_logical_di (rtx operands[3],
38365 enum rtx_code code,
38366 bool complement_final_p,
38367 bool complement_op1_p,
38368 bool complement_op2_p)
38370 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38371 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38372 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38373 enum hi_lo { hi = 0, lo = 1 };
38374 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38377 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38378 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38379 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38380 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38383 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38386 if (GET_CODE (operands[2]) != CONST_INT)
38388 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38389 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38393 HOST_WIDE_INT value = INTVAL (operands[2]);
38394 HOST_WIDE_INT value_hi_lo[2];
38396 gcc_assert (!complement_final_p);
38397 gcc_assert (!complement_op1_p);
38398 gcc_assert (!complement_op2_p);
38400 value_hi_lo[hi] = value >> 32;
38401 value_hi_lo[lo] = value & lower_32bits;
38403 for (i = 0; i < 2; i++)
38405 HOST_WIDE_INT sub_value = value_hi_lo[i];
38407 if (sub_value & sign_bit)
38408 sub_value |= upper_32bits;
38410 op2_hi_lo[i] = GEN_INT (sub_value);
38412 /* If this is an AND instruction, check to see if we need to load
38413 the value in a register. */
38414 if (code == AND && sub_value != -1 && sub_value != 0
38415 && !and_operand (op2_hi_lo[i], SImode))
38416 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38421 for (i = 0; i < 2; i++)
38423 /* Split large IOR/XOR operations. */
38424 if ((code == IOR || code == XOR)
38425 && GET_CODE (op2_hi_lo[i]) == CONST_INT
38426 && !complement_final_p
38427 && !complement_op1_p
38428 && !complement_op2_p
38429 && !logical_const_operand (op2_hi_lo[i], SImode))
38431 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38432 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38433 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38434 rtx tmp = gen_reg_rtx (SImode);
38436 /* Make sure the constant is sign extended. */
38437 if ((hi_16bits & sign_bit) != 0)
38438 hi_16bits |= upper_32bits;
38440 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38441 code, SImode, false, false, false);
38443 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38444 code, SImode, false, false, false);
38447 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38448 code, SImode, complement_final_p,
38449 complement_op1_p, complement_op2_p);
38455 /* Split the insns that make up boolean operations operating on multiple GPR
38456 registers. The boolean MD patterns ensure that the inputs either are
38457 exactly the same as the output registers, or there is no overlap.
38459 OPERANDS is an array containing the destination and two input operands.
38460 CODE is the base operation (AND, IOR, XOR, NOT).
38461 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38462 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38463 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38466 rs6000_split_logical (rtx operands[3],
38467 enum rtx_code code,
38468 bool complement_final_p,
38469 bool complement_op1_p,
38470 bool complement_op2_p)
38472 machine_mode mode = GET_MODE (operands[0]);
38473 machine_mode sub_mode;
38475 int sub_size, regno0, regno1, nregs, i;
38477 /* If this is DImode, use the specialized version that can run before
38478 register allocation. */
38479 if (mode == DImode && !TARGET_POWERPC64)
38481 rs6000_split_logical_di (operands, code, complement_final_p,
38482 complement_op1_p, complement_op2_p);
38488 op2 = (code == NOT) ? NULL_RTX : operands[2];
38489 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38490 sub_size = GET_MODE_SIZE (sub_mode);
38491 regno0 = REGNO (op0);
38492 regno1 = REGNO (op1);
38494 gcc_assert (reload_completed);
38495 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38496 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38498 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38499 gcc_assert (nregs > 1);
38501 if (op2 && REG_P (op2))
38502 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38504 for (i = 0; i < nregs; i++)
38506 int offset = i * sub_size;
38507 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38508 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38509 rtx sub_op2 = ((code == NOT)
38511 : simplify_subreg (sub_mode, op2, mode, offset));
38513 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38514 complement_final_p, complement_op1_p,
38522 /* Return true if the peephole2 can combine a load involving a combination of
38523 an addis instruction and a load with an offset that can be fused together on
38527 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38528 rtx addis_value, /* addis value. */
38529 rtx target, /* target register that is loaded. */
38530 rtx mem) /* bottom part of the memory addr. */
38535 /* Validate arguments. */
38536 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38539 if (!base_reg_operand (target, GET_MODE (target)))
38542 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38545 /* Allow sign/zero extension. */
38546 if (GET_CODE (mem) == ZERO_EXTEND
38547 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38548 mem = XEXP (mem, 0);
38553 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38556 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38557 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38560 /* Validate that the register used to load the high value is either the
38561 register being loaded, or we can safely replace its use.
38563 This function is only called from the peephole2 pass and we assume that
38564 there are 2 instructions in the peephole (addis and load), so we want to
38565 check if the target register was not used in the memory address and the
38566 register to hold the addis result is dead after the peephole. */
38567 if (REGNO (addis_reg) != REGNO (target))
38569 if (reg_mentioned_p (target, mem))
38572 if (!peep2_reg_dead_p (2, addis_reg))
38575 /* If the target register being loaded is the stack pointer, we must
38576 avoid loading any other value into it, even temporarily. */
38577 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38581 base_reg = XEXP (addr, 0);
38582 return REGNO (addis_reg) == REGNO (base_reg);
38585 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38586 sequence. We adjust the addis register to use the target register. If the
38587 load sign extends, we adjust the code to do the zero extending load, and an
38588 explicit sign extension later since the fusion only covers zero extending
38592 operands[0] register set with addis (to be replaced with target)
38593 operands[1] value set via addis
38594 operands[2] target register being loaded
38595 operands[3] D-form memory reference using operands[0]. */
38598 expand_fusion_gpr_load (rtx *operands)
38600 rtx addis_value = operands[1];
38601 rtx target = operands[2];
38602 rtx orig_mem = operands[3];
38603 rtx new_addr, new_mem, orig_addr, offset;
38604 enum rtx_code plus_or_lo_sum;
38605 machine_mode target_mode = GET_MODE (target);
38606 machine_mode extend_mode = target_mode;
38607 machine_mode ptr_mode = Pmode;
38608 enum rtx_code extend = UNKNOWN;
38610 if (GET_CODE (orig_mem) == ZERO_EXTEND
38611 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38613 extend = GET_CODE (orig_mem);
38614 orig_mem = XEXP (orig_mem, 0);
38615 target_mode = GET_MODE (orig_mem);
38618 gcc_assert (MEM_P (orig_mem));
38620 orig_addr = XEXP (orig_mem, 0);
38621 plus_or_lo_sum = GET_CODE (orig_addr);
38622 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38624 offset = XEXP (orig_addr, 1);
38625 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38626 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38628 if (extend != UNKNOWN)
38629 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38631 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38632 UNSPEC_FUSION_GPR);
38633 emit_insn (gen_rtx_SET (target, new_mem));
38635 if (extend == SIGN_EXTEND)
38637 int sub_off = ((BYTES_BIG_ENDIAN)
38638 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38641 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38643 emit_insn (gen_rtx_SET (target,
38644 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38650 /* Emit the addis instruction that will be part of a fused instruction
38654 emit_fusion_addis (rtx target, rtx addis_value)
38657 const char *addis_str = NULL;
38659 /* Emit the addis instruction. */
38660 fuse_ops[0] = target;
38661 if (satisfies_constraint_L (addis_value))
38663 fuse_ops[1] = addis_value;
38664 addis_str = "lis %0,%v1";
38667 else if (GET_CODE (addis_value) == PLUS)
38669 rtx op0 = XEXP (addis_value, 0);
38670 rtx op1 = XEXP (addis_value, 1);
38672 if (REG_P (op0) && CONST_INT_P (op1)
38673 && satisfies_constraint_L (op1))
38677 addis_str = "addis %0,%1,%v2";
38681 else if (GET_CODE (addis_value) == HIGH)
38683 rtx value = XEXP (addis_value, 0);
38684 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38686 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38687 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38689 addis_str = "addis %0,%2,%1@toc@ha";
38691 else if (TARGET_XCOFF)
38692 addis_str = "addis %0,%1@u(%2)";
38695 gcc_unreachable ();
38698 else if (GET_CODE (value) == PLUS)
38700 rtx op0 = XEXP (value, 0);
38701 rtx op1 = XEXP (value, 1);
38703 if (GET_CODE (op0) == UNSPEC
38704 && XINT (op0, 1) == UNSPEC_TOCREL
38705 && CONST_INT_P (op1))
38707 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38708 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38711 addis_str = "addis %0,%2,%1+%3@toc@ha";
38713 else if (TARGET_XCOFF)
38714 addis_str = "addis %0,%1+%3@u(%2)";
38717 gcc_unreachable ();
38721 else if (satisfies_constraint_L (value))
38723 fuse_ops[1] = value;
38724 addis_str = "lis %0,%v1";
38727 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38729 fuse_ops[1] = value;
38730 addis_str = "lis %0,%1@ha";
38735 fatal_insn ("Could not generate addis value for fusion", addis_value);
38737 output_asm_insn (addis_str, fuse_ops);
38740 /* Emit a D-form load or store instruction that is the second instruction
38741 of a fusion sequence. */
38744 emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset,
38745 const char *insn_str)
38748 char insn_template[80];
38750 fuse_ops[0] = load_store_reg;
38751 fuse_ops[1] = addis_reg;
38753 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38755 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38756 fuse_ops[2] = offset;
38757 output_asm_insn (insn_template, fuse_ops);
38760 else if (GET_CODE (offset) == UNSPEC
38761 && XINT (offset, 1) == UNSPEC_TOCREL)
38764 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38766 else if (TARGET_XCOFF)
38767 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38770 gcc_unreachable ();
38772 fuse_ops[2] = XVECEXP (offset, 0, 0);
38773 output_asm_insn (insn_template, fuse_ops);
38776 else if (GET_CODE (offset) == PLUS
38777 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38778 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38779 && CONST_INT_P (XEXP (offset, 1)))
38781 rtx tocrel_unspec = XEXP (offset, 0);
38783 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38785 else if (TARGET_XCOFF)
38786 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38789 gcc_unreachable ();
38791 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38792 fuse_ops[3] = XEXP (offset, 1);
38793 output_asm_insn (insn_template, fuse_ops);
38796 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38798 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38800 fuse_ops[2] = offset;
38801 output_asm_insn (insn_template, fuse_ops);
38805 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38810 /* Wrap a TOC address that can be fused to indicate that special fusion
38811 processing is needed. */
38814 fusion_wrap_memory_address (rtx old_mem)
38816 rtx old_addr = XEXP (old_mem, 0);
38817 rtvec v = gen_rtvec (1, old_addr);
38818 rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
38819 return replace_equiv_address_nv (old_mem, new_addr, false);
38822 /* Given an address, convert it into the addis and load offset parts. Addresses
38823 created during the peephole2 process look like:
38824 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38825 (unspec [(...)] UNSPEC_TOCREL))
38827 Addresses created via toc fusion look like:
38828 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38831 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38835 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
38837 lo = XVECEXP (addr, 0, 0);
38838 hi = gen_rtx_HIGH (Pmode, lo);
38840 else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38842 hi = XEXP (addr, 0);
38843 lo = XEXP (addr, 1);
38846 gcc_unreachable ();
38852 /* Return a string to fuse an addis instruction with a gpr load to the same
38853 register that we loaded up the addis instruction. The address that is used
38854 is the logical address that was formed during peephole2:
38855 (lo_sum (high) (low-part))
38857 Or the address is the TOC address that is wrapped before register allocation:
38858 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38860 The code is complicated, so we call output_asm_insn directly, and just
38864 emit_fusion_gpr_load (rtx target, rtx mem)
38869 const char *load_str = NULL;
38872 if (GET_CODE (mem) == ZERO_EXTEND)
38873 mem = XEXP (mem, 0);
38875 gcc_assert (REG_P (target) && MEM_P (mem));
38877 addr = XEXP (mem, 0);
38878 fusion_split_address (addr, &addis_value, &load_offset);
38880 /* Now emit the load instruction to the same register. */
38881 mode = GET_MODE (mem);
38899 gcc_assert (TARGET_POWERPC64);
38904 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38907 /* Emit the addis instruction. */
38908 emit_fusion_addis (target, addis_value);
38910 /* Emit the D-form load instruction. */
38911 emit_fusion_load_store (target, target, load_offset, load_str);
38917 /* Return true if the peephole2 can combine a load/store involving a
38918 combination of an addis instruction and the memory operation. This was
38919 added to the ISA 3.0 (power9) hardware. */
38922 fusion_p9_p (rtx addis_reg, /* register set via addis. */
38923 rtx addis_value, /* addis value. */
38924 rtx dest, /* destination (memory or register). */
38925 rtx src) /* source (register or memory). */
38927 rtx addr, mem, offset;
38928 machine_mode mode = GET_MODE (src);
38930 /* Validate arguments. */
38931 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38934 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38937 /* Ignore extend operations that are part of the load. */
38938 if (GET_CODE (src) == FLOAT_EXTEND || GET_CODE (src) == ZERO_EXTEND)
38939 src = XEXP (src, 0);
38941 /* Test for memory<-register or register<-memory. */
38942 if (fpr_reg_operand (src, mode) || int_reg_operand (src, mode))
38950 else if (MEM_P (src))
38952 if (!fpr_reg_operand (dest, mode) && !int_reg_operand (dest, mode))
38961 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38962 if (GET_CODE (addr) == PLUS)
38964 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38967 return satisfies_constraint_I (XEXP (addr, 1));
38970 else if (GET_CODE (addr) == LO_SUM)
38972 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
38975 offset = XEXP (addr, 1);
38976 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
38977 return small_toc_ref (offset, GET_MODE (offset));
38979 else if (TARGET_ELF && !TARGET_POWERPC64)
38980 return CONSTANT_P (offset);
38986 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38990 operands[0] register set with addis
38991 operands[1] value set via addis
38992 operands[2] target register being loaded
38993 operands[3] D-form memory reference using operands[0].
38995 This is similar to the fusion introduced with power8, except it scales to
38996 both loads/stores and does not require the result register to be the same as
38997 the base register. At the moment, we only do this if register set with addis
39001 expand_fusion_p9_load (rtx *operands)
39003 rtx tmp_reg = operands[0];
39004 rtx addis_value = operands[1];
39005 rtx target = operands[2];
39006 rtx orig_mem = operands[3];
39007 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn;
39008 enum rtx_code plus_or_lo_sum;
39009 machine_mode target_mode = GET_MODE (target);
39010 machine_mode extend_mode = target_mode;
39011 machine_mode ptr_mode = Pmode;
39012 enum rtx_code extend = UNKNOWN;
39014 if (GET_CODE (orig_mem) == FLOAT_EXTEND || GET_CODE (orig_mem) == ZERO_EXTEND)
39016 extend = GET_CODE (orig_mem);
39017 orig_mem = XEXP (orig_mem, 0);
39018 target_mode = GET_MODE (orig_mem);
39021 gcc_assert (MEM_P (orig_mem));
39023 orig_addr = XEXP (orig_mem, 0);
39024 plus_or_lo_sum = GET_CODE (orig_addr);
39025 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39027 offset = XEXP (orig_addr, 1);
39028 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39029 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39031 if (extend != UNKNOWN)
39032 new_mem = gen_rtx_fmt_e (extend, extend_mode, new_mem);
39034 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
39037 set = gen_rtx_SET (target, new_mem);
39038 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39039 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39045 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39049 operands[0] register set with addis
39050 operands[1] value set via addis
39051 operands[2] target D-form memory being stored to
39052 operands[3] register being stored
39054 This is similar to the fusion introduced with power8, except it scales to
39055 both loads/stores and does not require the result register to be the same as
39056 the base register. At the moment, we only do this if register set with addis
39060 expand_fusion_p9_store (rtx *operands)
39062 rtx tmp_reg = operands[0];
39063 rtx addis_value = operands[1];
39064 rtx orig_mem = operands[2];
39065 rtx src = operands[3];
39066 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn, new_src;
39067 enum rtx_code plus_or_lo_sum;
39068 machine_mode target_mode = GET_MODE (orig_mem);
39069 machine_mode ptr_mode = Pmode;
39071 gcc_assert (MEM_P (orig_mem));
39073 orig_addr = XEXP (orig_mem, 0);
39074 plus_or_lo_sum = GET_CODE (orig_addr);
39075 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39077 offset = XEXP (orig_addr, 1);
39078 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39079 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39081 new_src = gen_rtx_UNSPEC (target_mode, gen_rtvec (1, src),
39084 set = gen_rtx_SET (new_mem, new_src);
39085 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39086 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39092 /* Return a string to fuse an addis instruction with a load using extended
39093 fusion. The address that is used is the logical address that was formed
39094 during peephole2: (lo_sum (high) (low-part))
39096 The code is complicated, so we call output_asm_insn directly, and just
39100 emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
39102 machine_mode mode = GET_MODE (reg);
39106 const char *load_string;
39109 if (GET_CODE (mem) == FLOAT_EXTEND || GET_CODE (mem) == ZERO_EXTEND)
39111 mem = XEXP (mem, 0);
39112 mode = GET_MODE (mem);
39115 if (GET_CODE (reg) == SUBREG)
39117 gcc_assert (SUBREG_BYTE (reg) == 0);
39118 reg = SUBREG_REG (reg);
39122 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg);
39125 if (FP_REGNO_P (r))
39127 if (mode == SFmode)
39128 load_string = "lfs";
39129 else if (mode == DFmode || mode == DImode)
39130 load_string = "lfd";
39132 gcc_unreachable ();
39134 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39136 if (mode == SFmode)
39137 load_string = "lxssp";
39138 else if (mode == DFmode || mode == DImode)
39139 load_string = "lxsd";
39141 gcc_unreachable ();
39143 else if (INT_REGNO_P (r))
39148 load_string = "lbz";
39151 load_string = "lhz";
39155 load_string = "lwz";
39159 if (!TARGET_POWERPC64)
39160 gcc_unreachable ();
39161 load_string = "ld";
39164 gcc_unreachable ();
39168 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg);
39171 fatal_insn ("emit_fusion_p9_load not MEM", mem);
39173 addr = XEXP (mem, 0);
39174 fusion_split_address (addr, &hi, &lo);
39176 /* Emit the addis instruction. */
39177 emit_fusion_addis (tmp_reg, hi);
39179 /* Emit the D-form load instruction. */
39180 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
39185 /* Return a string to fuse an addis instruction with a store using extended
39186 fusion. The address that is used is the logical address that was formed
39187 during peephole2: (lo_sum (high) (low-part))
39189 The code is complicated, so we call output_asm_insn directly, and just
39193 emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
39195 machine_mode mode = GET_MODE (reg);
39199 const char *store_string;
39202 if (GET_CODE (reg) == SUBREG)
39204 gcc_assert (SUBREG_BYTE (reg) == 0);
39205 reg = SUBREG_REG (reg);
39209 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg);
39212 if (FP_REGNO_P (r))
39214 if (mode == SFmode)
39215 store_string = "stfs";
39216 else if (mode == DFmode)
39217 store_string = "stfd";
39219 gcc_unreachable ();
39221 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39223 if (mode == SFmode)
39224 store_string = "stxssp";
39225 else if (mode == DFmode || mode == DImode)
39226 store_string = "stxsd";
39228 gcc_unreachable ();
39230 else if (INT_REGNO_P (r))
39235 store_string = "stb";
39238 store_string = "sth";
39242 store_string = "stw";
39246 if (!TARGET_POWERPC64)
39247 gcc_unreachable ();
39248 store_string = "std";
39251 gcc_unreachable ();
39255 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg);
39258 fatal_insn ("emit_fusion_p9_store not MEM", mem);
39260 addr = XEXP (mem, 0);
39261 fusion_split_address (addr, &hi, &lo);
39263 /* Emit the addis instruction. */
39264 emit_fusion_addis (tmp_reg, hi);
39266 /* Emit the D-form load instruction. */
39267 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
39272 #ifdef RS6000_GLIBC_ATOMIC_FENV
39273 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
39274 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
39277 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
39280 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
39282 if (!TARGET_HARD_FLOAT)
39284 #ifdef RS6000_GLIBC_ATOMIC_FENV
39285 if (atomic_hold_decl == NULL_TREE)
39288 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39289 get_identifier ("__atomic_feholdexcept"),
39290 build_function_type_list (void_type_node,
39291 double_ptr_type_node,
39293 TREE_PUBLIC (atomic_hold_decl) = 1;
39294 DECL_EXTERNAL (atomic_hold_decl) = 1;
39297 if (atomic_clear_decl == NULL_TREE)
39300 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39301 get_identifier ("__atomic_feclearexcept"),
39302 build_function_type_list (void_type_node,
39304 TREE_PUBLIC (atomic_clear_decl) = 1;
39305 DECL_EXTERNAL (atomic_clear_decl) = 1;
39308 tree const_double = build_qualified_type (double_type_node,
39310 tree const_double_ptr = build_pointer_type (const_double);
39311 if (atomic_update_decl == NULL_TREE)
39314 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39315 get_identifier ("__atomic_feupdateenv"),
39316 build_function_type_list (void_type_node,
39319 TREE_PUBLIC (atomic_update_decl) = 1;
39320 DECL_EXTERNAL (atomic_update_decl) = 1;
39323 tree fenv_var = create_tmp_var_raw (double_type_node);
39324 TREE_ADDRESSABLE (fenv_var) = 1;
39325 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
39327 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
39328 *clear = build_call_expr (atomic_clear_decl, 0);
39329 *update = build_call_expr (atomic_update_decl, 1,
39330 fold_convert (const_double_ptr, fenv_addr));
39335 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
39336 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
39337 tree call_mffs = build_call_expr (mffs, 0);
39339 /* Generates the equivalent of feholdexcept (&fenv_var)
39341 *fenv_var = __builtin_mffs ();
39343 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
39344 __builtin_mtfsf (0xff, fenv_hold); */
39346 /* Mask to clear everything except for the rounding modes and non-IEEE
39347 arithmetic flag. */
39348 const unsigned HOST_WIDE_INT hold_exception_mask =
39349 HOST_WIDE_INT_C (0xffffffff00000007);
39351 tree fenv_var = create_tmp_var_raw (double_type_node);
39353 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
39355 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
39356 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39357 build_int_cst (uint64_type_node,
39358 hold_exception_mask));
39360 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39363 tree hold_mtfsf = build_call_expr (mtfsf, 2,
39364 build_int_cst (unsigned_type_node, 0xff),
39367 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
39369 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
39371 double fenv_clear = __builtin_mffs ();
39372 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39373 __builtin_mtfsf (0xff, fenv_clear); */
39375 /* Mask to clear everything except for the rounding modes and non-IEEE
39376 arithmetic flag. */
39377 const unsigned HOST_WIDE_INT clear_exception_mask =
39378 HOST_WIDE_INT_C (0xffffffff00000000);
39380 tree fenv_clear = create_tmp_var_raw (double_type_node);
39382 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
39384 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
39385 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
39387 build_int_cst (uint64_type_node,
39388 clear_exception_mask));
39390 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39391 fenv_clear_llu_and);
39393 tree clear_mtfsf = build_call_expr (mtfsf, 2,
39394 build_int_cst (unsigned_type_node, 0xff),
39397 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
39399 /* Generates the equivalent of feupdateenv (&fenv_var)
39401 double old_fenv = __builtin_mffs ();
39402 double fenv_update;
39403 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39404 (*(uint64_t*)fenv_var 0x1ff80fff);
39405 __builtin_mtfsf (0xff, fenv_update); */
39407 const unsigned HOST_WIDE_INT update_exception_mask =
39408 HOST_WIDE_INT_C (0xffffffff1fffff00);
39409 const unsigned HOST_WIDE_INT new_exception_mask =
39410 HOST_WIDE_INT_C (0x1ff80fff);
39412 tree old_fenv = create_tmp_var_raw (double_type_node);
39413 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
39415 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
39416 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
39417 build_int_cst (uint64_type_node,
39418 update_exception_mask));
39420 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39421 build_int_cst (uint64_type_node,
39422 new_exception_mask));
39424 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
39425 old_llu_and, new_llu_and);
39427 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39430 tree update_mtfsf = build_call_expr (mtfsf, 2,
39431 build_int_cst (unsigned_type_node, 0xff),
39432 fenv_update_mtfsf);
39434 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39438 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39440 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39442 rtx_tmp0 = gen_reg_rtx (V2DImode);
39443 rtx_tmp1 = gen_reg_rtx (V2DImode);
39445 /* The destination of the vmrgew instruction layout is:
39446 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39447 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39448 vmrgew instruction will be correct. */
39449 if (VECTOR_ELT_ORDER_BIG)
39451 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39452 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39456 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39457 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39460 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39461 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39463 if (signed_convert)
39465 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39466 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39470 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39471 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39474 if (VECTOR_ELT_ORDER_BIG)
39475 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39477 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39481 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39484 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39486 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39487 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39489 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39490 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39492 rtx_tmp2 = gen_reg_rtx (V4SImode);
39493 rtx_tmp3 = gen_reg_rtx (V4SImode);
39495 if (signed_convert)
39497 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39498 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39502 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39503 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39506 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39509 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39512 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39513 optimization_type opt_type)
39518 return (opt_type == OPTIMIZE_FOR_SPEED
39519 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39526 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39528 static HOST_WIDE_INT
39529 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39531 if (TREE_CODE (exp) == STRING_CST
39532 && (STRICT_ALIGNMENT || !optimize_size))
39533 return MAX (align, BITS_PER_WORD);
39537 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39539 static HOST_WIDE_INT
39540 rs6000_starting_frame_offset (void)
39542 if (FRAME_GROWS_DOWNWARD)
39544 return RS6000_STARTING_FRAME_OFFSET;
39547 struct gcc_target targetm = TARGET_INITIALIZER;
39549 #include "gt-rs6000.h"