1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 #include "tree-ssanames.h"
87 /* This file should be included last. */
88 #include "target-def.h"
90 #ifndef TARGET_NO_PROTOTYPE
91 #define TARGET_NO_PROTOTYPE 0
94 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
95 systems will also set long double to be IEEE 128-bit. AIX and Darwin
96 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
97 those systems will not pick up this default. This needs to be after all
98 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
100 #ifndef TARGET_IEEEQUAD_DEFAULT
101 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
102 #define TARGET_IEEEQUAD_DEFAULT 1
104 #define TARGET_IEEEQUAD_DEFAULT 0
108 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack {
112 int reload_completed; /* stack info won't change from here on */
113 int first_gp_reg_save; /* first callee saved GP register used */
114 int first_fp_reg_save; /* first callee saved FP register used */
115 int first_altivec_reg_save; /* first callee saved AltiVec register used */
116 int lr_save_p; /* true if the link reg needs to be saved */
117 int cr_save_p; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask; /* mask of vec registers to save */
119 int push_p; /* true if we need to allocate stack space */
120 int calls_p; /* true if the function makes any calls */
121 int world_save_p; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi; /* which ABI to use */
124 int gp_save_offset; /* offset to save GP regs from initial SP */
125 int fp_save_offset; /* offset to save FP regs from initial SP */
126 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset; /* offset to save LR from initial SP */
128 int cr_save_offset; /* offset to save CR from initial SP */
129 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset; /* offset to save the varargs registers */
131 int ehrd_offset; /* offset to EH return data */
132 int ehcr_offset; /* offset to EH CR field data */
133 int reg_size; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size; /* variable save area size */
135 int parm_size; /* outgoing parameter size */
136 int save_size; /* save area size */
137 int fixed_size; /* fixed size of stack frame */
138 int gp_size; /* size of saved GP registers */
139 int fp_size; /* size of saved FP registers */
140 int altivec_size; /* size of saved AltiVec registers */
141 int cr_size; /* size to hold CR if not in fixed area */
142 int vrsave_size; /* size to hold VRSAVE */
143 int altivec_padding_size; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer;
166 bool split_stack_argp_used;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately[32];
174 bool fpr_is_wrapped_separately[32];
175 bool lr_is_wrapped_separately;
176 bool toc_is_wrapped_separately;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno = 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode;
203 /* Note whether IEEE 128-bit floating point was passed or returned, either as
204 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
205 floating point. We changed the default C++ mangling for these types and we
206 may want to generate a weak alias of the old mangling (U10__float128) to the
207 new mangling (u9__ieee128). */
208 static bool rs6000_passes_ieee128;
211 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
212 name used in current releases (i.e. u9__ieee128). */
213 static bool ieee128_mangling_gcc_8_1;
215 /* Width in bits of a pointer. */
216 unsigned rs6000_pointer_size;
218 #ifdef HAVE_AS_GNU_ATTRIBUTE
219 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
220 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
222 /* Flag whether floating point values have been passed/returned.
223 Note that this doesn't say whether fprs are used, since the
224 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
225 should be set for soft-float values passed in gprs and ieee128
226 values passed in vsx registers. */
227 static bool rs6000_passes_float;
228 static bool rs6000_passes_long_double;
229 /* Flag whether vector values have been passed/returned. */
230 static bool rs6000_passes_vector;
231 /* Flag whether small (<= 8 byte) structures have been returned. */
232 static bool rs6000_returns_struct;
235 /* Value is TRUE if register/mode pair is acceptable. */
236 static bool rs6000_hard_regno_mode_ok_p
237 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
239 /* Maximum number of registers needed for a given register class and mode. */
240 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
242 /* How many registers are needed for a given register and mode. */
243 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
245 /* Map register number to register class. */
246 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
248 static int dbg_cost_ctrl;
250 /* Built in types. */
251 tree rs6000_builtin_types[RS6000_BTI_MAX];
252 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
254 /* Flag to say the TOC is initialized */
255 int toc_initialized, need_toc_init;
256 char toc_label_name[10];
258 /* Cached value of rs6000_variable_issue. This is cached in
259 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
260 static short cached_can_issue_more;
262 static GTY(()) section *read_only_data_section;
263 static GTY(()) section *private_data_section;
264 static GTY(()) section *tls_data_section;
265 static GTY(()) section *tls_private_data_section;
266 static GTY(()) section *read_only_private_data_section;
267 static GTY(()) section *sdata2_section;
268 static GTY(()) section *toc_section;
270 struct builtin_description
272 const HOST_WIDE_INT mask;
273 const enum insn_code icode;
274 const char *const name;
275 const enum rs6000_builtins code;
278 /* Describe the vector unit used for modes. */
279 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
280 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
282 /* Register classes for various constraints that are based on the target
284 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
286 /* Describe the alignment of a vector. */
287 int rs6000_vector_align[NUM_MACHINE_MODES];
289 /* Map selected modes to types for builtins. */
290 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
292 /* What modes to automatically generate reciprocal divide estimate (fre) and
293 reciprocal sqrt (frsqrte) for. */
294 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
296 /* Masks to determine which reciprocal esitmate instructions to generate
298 enum rs6000_recip_mask {
299 RECIP_SF_DIV = 0x001, /* Use divide estimate */
300 RECIP_DF_DIV = 0x002,
301 RECIP_V4SF_DIV = 0x004,
302 RECIP_V2DF_DIV = 0x008,
304 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
305 RECIP_DF_RSQRT = 0x020,
306 RECIP_V4SF_RSQRT = 0x040,
307 RECIP_V2DF_RSQRT = 0x080,
309 /* Various combination of flags for -mrecip=xxx. */
311 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
315 RECIP_HIGH_PRECISION = RECIP_ALL,
317 /* On low precision machines like the power5, don't enable double precision
318 reciprocal square root estimate, since it isn't accurate enough. */
319 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
322 /* -mrecip options. */
325 const char *string; /* option name */
326 unsigned int mask; /* mask bits to set */
327 } recip_options[] = {
328 { "all", RECIP_ALL },
329 { "none", RECIP_NONE },
330 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
332 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
334 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
335 | RECIP_V2DF_RSQRT) },
336 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
337 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
340 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
346 { "power9", PPC_PLATFORM_POWER9 },
347 { "power8", PPC_PLATFORM_POWER8 },
348 { "power7", PPC_PLATFORM_POWER7 },
349 { "power6x", PPC_PLATFORM_POWER6X },
350 { "power6", PPC_PLATFORM_POWER6 },
351 { "power5+", PPC_PLATFORM_POWER5_PLUS },
352 { "power5", PPC_PLATFORM_POWER5 },
353 { "ppc970", PPC_PLATFORM_PPC970 },
354 { "power4", PPC_PLATFORM_POWER4 },
355 { "ppca2", PPC_PLATFORM_PPCA2 },
356 { "ppc476", PPC_PLATFORM_PPC476 },
357 { "ppc464", PPC_PLATFORM_PPC464 },
358 { "ppc440", PPC_PLATFORM_PPC440 },
359 { "ppc405", PPC_PLATFORM_PPC405 },
360 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
363 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
369 } cpu_supports_info[] = {
370 /* AT_HWCAP masks. */
371 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
372 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
373 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
374 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
375 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
376 { "booke", PPC_FEATURE_BOOKE, 0 },
377 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
378 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
379 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
380 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
381 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
382 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
383 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
384 { "notb", PPC_FEATURE_NO_TB, 0 },
385 { "pa6t", PPC_FEATURE_PA6T, 0 },
386 { "power4", PPC_FEATURE_POWER4, 0 },
387 { "power5", PPC_FEATURE_POWER5, 0 },
388 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
389 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
390 { "ppc32", PPC_FEATURE_32, 0 },
391 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
392 { "ppc64", PPC_FEATURE_64, 0 },
393 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
394 { "smt", PPC_FEATURE_SMT, 0 },
395 { "spe", PPC_FEATURE_HAS_SPE, 0 },
396 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
397 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
398 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
400 /* AT_HWCAP2 masks. */
401 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
402 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
403 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
404 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
405 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
406 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
407 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
408 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
409 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
410 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
411 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
412 { "darn", PPC_FEATURE2_DARN, 1 },
413 { "scv", PPC_FEATURE2_SCV, 1 }
416 /* On PowerPC, we have a limited number of target clones that we care about
417 which means we can use an array to hold the options, rather than having more
418 elaborate data structures to identify each possible variation. Order the
419 clones from the default to the highest ISA. */
421 CLONE_DEFAULT = 0, /* default clone. */
422 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
423 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
424 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
425 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
429 /* Map compiler ISA bits into HWCAP names. */
431 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
432 const char *name; /* name to use in __builtin_cpu_supports. */
435 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
436 { 0, "" }, /* Default options. */
437 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
438 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
439 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
440 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
444 /* Newer LIBCs explicitly export this symbol to declare that they provide
445 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
446 reference to this symbol whenever we expand a CPU builtin, so that
447 we never link against an old LIBC. */
448 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
450 /* True if we have expanded a CPU builtin. */
453 /* Pointer to function (in rs6000-c.c) that can define or undefine target
454 macros that have changed. Languages that don't support the preprocessor
455 don't link in rs6000-c.c, so we can't call it directly. */
456 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
458 /* Simplfy register classes into simpler classifications. We assume
459 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
460 check for standard register classes (gpr/floating/altivec/vsx) and
461 floating/vector classes (float/altivec/vsx). */
463 enum rs6000_reg_type {
474 /* Map register class to register type. */
475 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
477 /* First/last register type for the 'normal' register types (i.e. general
478 purpose, floating point, altivec, and VSX registers). */
479 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
481 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
484 /* Register classes we care about in secondary reload or go if legitimate
485 address. We only need to worry about GPR, FPR, and Altivec registers here,
486 along an ANY field that is the OR of the 3 register classes. */
488 enum rs6000_reload_reg_type {
489 RELOAD_REG_GPR, /* General purpose registers. */
490 RELOAD_REG_FPR, /* Traditional floating point regs. */
491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
492 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
496 /* For setting up register classes, loop through the 3 register classes mapping
497 into real registers, and skip the ANY class, which is just an OR of the
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
502 /* Map reload register type to a register in the register class. */
503 struct reload_reg_map_type {
504 const char *name; /* Register class name. */
505 int reg; /* Register in the register class. */
508 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
509 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
510 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
511 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
512 { "Any", -1 }, /* RELOAD_REG_ANY. */
515 /* Mask bits for each register class, indexed per mode. Historically the
516 compiler has been more restrictive which types can do PRE_MODIFY instead of
517 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
518 typedef unsigned char addr_mask_type;
520 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
521 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
522 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
523 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
526 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
527 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
529 /* Register type masks based on the type, of valid addressing modes. */
530 struct rs6000_reg_addr {
531 enum insn_code reload_load; /* INSN to reload for loading. */
532 enum insn_code reload_store; /* INSN to reload for storing. */
533 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
534 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
535 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
536 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
537 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
540 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
542 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
544 mode_supports_pre_incdec_p (machine_mode mode)
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
550 /* Helper function to say whether a mode supports PRE_MODIFY. */
552 mode_supports_pre_modify_p (machine_mode mode)
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
558 /* Return true if we have D-form addressing in altivec registers. */
560 mode_supports_vmx_dform (machine_mode mode)
562 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
565 /* Return true if we have D-form addressing in VSX registers. This addressing
566 is more limited than normal d-form addressing in that the offset must be
567 aligned on a 16-byte boundary. */
569 mode_supports_dq_form (machine_mode mode)
571 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
575 /* Given that there exists at least one variable that is set (produced)
576 by OUT_INSN and read (consumed) by IN_INSN, return true iff
577 IN_INSN represents one or more memory store operations and none of
578 the variables set by OUT_INSN is used by IN_INSN as the address of a
579 store operation. If either IN_INSN or OUT_INSN does not represent
580 a "single" RTL SET expression (as loosely defined by the
581 implementation of the single_set function) or a PARALLEL with only
582 SETs, CLOBBERs, and USEs inside, this function returns false.
584 This rs6000-specific version of store_data_bypass_p checks for
585 certain conditions that result in assertion failures (and internal
586 compiler errors) in the generic store_data_bypass_p function and
587 returns false rather than calling store_data_bypass_p if one of the
588 problematic conditions is detected. */
591 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
598 in_set = single_set (in_insn);
601 if (MEM_P (SET_DEST (in_set)))
603 out_set = single_set (out_insn);
606 out_pat = PATTERN (out_insn);
607 if (GET_CODE (out_pat) == PARALLEL)
609 for (i = 0; i < XVECLEN (out_pat, 0); i++)
611 out_exp = XVECEXP (out_pat, 0, i);
612 if ((GET_CODE (out_exp) == CLOBBER)
613 || (GET_CODE (out_exp) == USE))
615 else if (GET_CODE (out_exp) != SET)
624 in_pat = PATTERN (in_insn);
625 if (GET_CODE (in_pat) != PARALLEL)
628 for (i = 0; i < XVECLEN (in_pat, 0); i++)
630 in_exp = XVECEXP (in_pat, 0, i);
631 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
633 else if (GET_CODE (in_exp) != SET)
636 if (MEM_P (SET_DEST (in_exp)))
638 out_set = single_set (out_insn);
641 out_pat = PATTERN (out_insn);
642 if (GET_CODE (out_pat) != PARALLEL)
644 for (j = 0; j < XVECLEN (out_pat, 0); j++)
646 out_exp = XVECEXP (out_pat, 0, j);
647 if ((GET_CODE (out_exp) == CLOBBER)
648 || (GET_CODE (out_exp) == USE))
650 else if (GET_CODE (out_exp) != SET)
657 return store_data_bypass_p (out_insn, in_insn);
661 /* Processor costs (relative to an add) */
663 const struct processor_costs *rs6000_cost;
665 /* Instruction size costs on 32bit processors. */
667 struct processor_costs size32_cost = {
668 COSTS_N_INSNS (1), /* mulsi */
669 COSTS_N_INSNS (1), /* mulsi_const */
670 COSTS_N_INSNS (1), /* mulsi_const9 */
671 COSTS_N_INSNS (1), /* muldi */
672 COSTS_N_INSNS (1), /* divsi */
673 COSTS_N_INSNS (1), /* divdi */
674 COSTS_N_INSNS (1), /* fp */
675 COSTS_N_INSNS (1), /* dmul */
676 COSTS_N_INSNS (1), /* sdiv */
677 COSTS_N_INSNS (1), /* ddiv */
678 32, /* cache line size */
682 0, /* SF->DF convert */
685 /* Instruction size costs on 64bit processors. */
687 struct processor_costs size64_cost = {
688 COSTS_N_INSNS (1), /* mulsi */
689 COSTS_N_INSNS (1), /* mulsi_const */
690 COSTS_N_INSNS (1), /* mulsi_const9 */
691 COSTS_N_INSNS (1), /* muldi */
692 COSTS_N_INSNS (1), /* divsi */
693 COSTS_N_INSNS (1), /* divdi */
694 COSTS_N_INSNS (1), /* fp */
695 COSTS_N_INSNS (1), /* dmul */
696 COSTS_N_INSNS (1), /* sdiv */
697 COSTS_N_INSNS (1), /* ddiv */
698 128, /* cache line size */
702 0, /* SF->DF convert */
705 /* Instruction costs on RS64A processors. */
707 struct processor_costs rs64a_cost = {
708 COSTS_N_INSNS (20), /* mulsi */
709 COSTS_N_INSNS (12), /* mulsi_const */
710 COSTS_N_INSNS (8), /* mulsi_const9 */
711 COSTS_N_INSNS (34), /* muldi */
712 COSTS_N_INSNS (65), /* divsi */
713 COSTS_N_INSNS (67), /* divdi */
714 COSTS_N_INSNS (4), /* fp */
715 COSTS_N_INSNS (4), /* dmul */
716 COSTS_N_INSNS (31), /* sdiv */
717 COSTS_N_INSNS (31), /* ddiv */
718 128, /* cache line size */
722 0, /* SF->DF convert */
725 /* Instruction costs on MPCCORE processors. */
727 struct processor_costs mpccore_cost = {
728 COSTS_N_INSNS (2), /* mulsi */
729 COSTS_N_INSNS (2), /* mulsi_const */
730 COSTS_N_INSNS (2), /* mulsi_const9 */
731 COSTS_N_INSNS (2), /* muldi */
732 COSTS_N_INSNS (6), /* divsi */
733 COSTS_N_INSNS (6), /* divdi */
734 COSTS_N_INSNS (4), /* fp */
735 COSTS_N_INSNS (5), /* dmul */
736 COSTS_N_INSNS (10), /* sdiv */
737 COSTS_N_INSNS (17), /* ddiv */
738 32, /* cache line size */
742 0, /* SF->DF convert */
745 /* Instruction costs on PPC403 processors. */
747 struct processor_costs ppc403_cost = {
748 COSTS_N_INSNS (4), /* mulsi */
749 COSTS_N_INSNS (4), /* mulsi_const */
750 COSTS_N_INSNS (4), /* mulsi_const9 */
751 COSTS_N_INSNS (4), /* muldi */
752 COSTS_N_INSNS (33), /* divsi */
753 COSTS_N_INSNS (33), /* divdi */
754 COSTS_N_INSNS (11), /* fp */
755 COSTS_N_INSNS (11), /* dmul */
756 COSTS_N_INSNS (11), /* sdiv */
757 COSTS_N_INSNS (11), /* ddiv */
758 32, /* cache line size */
762 0, /* SF->DF convert */
765 /* Instruction costs on PPC405 processors. */
767 struct processor_costs ppc405_cost = {
768 COSTS_N_INSNS (5), /* mulsi */
769 COSTS_N_INSNS (4), /* mulsi_const */
770 COSTS_N_INSNS (3), /* mulsi_const9 */
771 COSTS_N_INSNS (5), /* muldi */
772 COSTS_N_INSNS (35), /* divsi */
773 COSTS_N_INSNS (35), /* divdi */
774 COSTS_N_INSNS (11), /* fp */
775 COSTS_N_INSNS (11), /* dmul */
776 COSTS_N_INSNS (11), /* sdiv */
777 COSTS_N_INSNS (11), /* ddiv */
778 32, /* cache line size */
782 0, /* SF->DF convert */
785 /* Instruction costs on PPC440 processors. */
787 struct processor_costs ppc440_cost = {
788 COSTS_N_INSNS (3), /* mulsi */
789 COSTS_N_INSNS (2), /* mulsi_const */
790 COSTS_N_INSNS (2), /* mulsi_const9 */
791 COSTS_N_INSNS (3), /* muldi */
792 COSTS_N_INSNS (34), /* divsi */
793 COSTS_N_INSNS (34), /* divdi */
794 COSTS_N_INSNS (5), /* fp */
795 COSTS_N_INSNS (5), /* dmul */
796 COSTS_N_INSNS (19), /* sdiv */
797 COSTS_N_INSNS (33), /* ddiv */
798 32, /* cache line size */
802 0, /* SF->DF convert */
805 /* Instruction costs on PPC476 processors. */
807 struct processor_costs ppc476_cost = {
808 COSTS_N_INSNS (4), /* mulsi */
809 COSTS_N_INSNS (4), /* mulsi_const */
810 COSTS_N_INSNS (4), /* mulsi_const9 */
811 COSTS_N_INSNS (4), /* muldi */
812 COSTS_N_INSNS (11), /* divsi */
813 COSTS_N_INSNS (11), /* divdi */
814 COSTS_N_INSNS (6), /* fp */
815 COSTS_N_INSNS (6), /* dmul */
816 COSTS_N_INSNS (19), /* sdiv */
817 COSTS_N_INSNS (33), /* ddiv */
818 32, /* l1 cache line size */
822 0, /* SF->DF convert */
825 /* Instruction costs on PPC601 processors. */
827 struct processor_costs ppc601_cost = {
828 COSTS_N_INSNS (5), /* mulsi */
829 COSTS_N_INSNS (5), /* mulsi_const */
830 COSTS_N_INSNS (5), /* mulsi_const9 */
831 COSTS_N_INSNS (5), /* muldi */
832 COSTS_N_INSNS (36), /* divsi */
833 COSTS_N_INSNS (36), /* divdi */
834 COSTS_N_INSNS (4), /* fp */
835 COSTS_N_INSNS (5), /* dmul */
836 COSTS_N_INSNS (17), /* sdiv */
837 COSTS_N_INSNS (31), /* ddiv */
838 32, /* cache line size */
842 0, /* SF->DF convert */
845 /* Instruction costs on PPC603 processors. */
847 struct processor_costs ppc603_cost = {
848 COSTS_N_INSNS (5), /* mulsi */
849 COSTS_N_INSNS (3), /* mulsi_const */
850 COSTS_N_INSNS (2), /* mulsi_const9 */
851 COSTS_N_INSNS (5), /* muldi */
852 COSTS_N_INSNS (37), /* divsi */
853 COSTS_N_INSNS (37), /* divdi */
854 COSTS_N_INSNS (3), /* fp */
855 COSTS_N_INSNS (4), /* dmul */
856 COSTS_N_INSNS (18), /* sdiv */
857 COSTS_N_INSNS (33), /* ddiv */
858 32, /* cache line size */
862 0, /* SF->DF convert */
865 /* Instruction costs on PPC604 processors. */
867 struct processor_costs ppc604_cost = {
868 COSTS_N_INSNS (4), /* mulsi */
869 COSTS_N_INSNS (4), /* mulsi_const */
870 COSTS_N_INSNS (4), /* mulsi_const9 */
871 COSTS_N_INSNS (4), /* muldi */
872 COSTS_N_INSNS (20), /* divsi */
873 COSTS_N_INSNS (20), /* divdi */
874 COSTS_N_INSNS (3), /* fp */
875 COSTS_N_INSNS (3), /* dmul */
876 COSTS_N_INSNS (18), /* sdiv */
877 COSTS_N_INSNS (32), /* ddiv */
878 32, /* cache line size */
882 0, /* SF->DF convert */
885 /* Instruction costs on PPC604e processors. */
887 struct processor_costs ppc604e_cost = {
888 COSTS_N_INSNS (2), /* mulsi */
889 COSTS_N_INSNS (2), /* mulsi_const */
890 COSTS_N_INSNS (2), /* mulsi_const9 */
891 COSTS_N_INSNS (2), /* muldi */
892 COSTS_N_INSNS (20), /* divsi */
893 COSTS_N_INSNS (20), /* divdi */
894 COSTS_N_INSNS (3), /* fp */
895 COSTS_N_INSNS (3), /* dmul */
896 COSTS_N_INSNS (18), /* sdiv */
897 COSTS_N_INSNS (32), /* ddiv */
898 32, /* cache line size */
902 0, /* SF->DF convert */
905 /* Instruction costs on PPC620 processors. */
907 struct processor_costs ppc620_cost = {
908 COSTS_N_INSNS (5), /* mulsi */
909 COSTS_N_INSNS (4), /* mulsi_const */
910 COSTS_N_INSNS (3), /* mulsi_const9 */
911 COSTS_N_INSNS (7), /* muldi */
912 COSTS_N_INSNS (21), /* divsi */
913 COSTS_N_INSNS (37), /* divdi */
914 COSTS_N_INSNS (3), /* fp */
915 COSTS_N_INSNS (3), /* dmul */
916 COSTS_N_INSNS (18), /* sdiv */
917 COSTS_N_INSNS (32), /* ddiv */
918 128, /* cache line size */
922 0, /* SF->DF convert */
925 /* Instruction costs on PPC630 processors. */
927 struct processor_costs ppc630_cost = {
928 COSTS_N_INSNS (5), /* mulsi */
929 COSTS_N_INSNS (4), /* mulsi_const */
930 COSTS_N_INSNS (3), /* mulsi_const9 */
931 COSTS_N_INSNS (7), /* muldi */
932 COSTS_N_INSNS (21), /* divsi */
933 COSTS_N_INSNS (37), /* divdi */
934 COSTS_N_INSNS (3), /* fp */
935 COSTS_N_INSNS (3), /* dmul */
936 COSTS_N_INSNS (17), /* sdiv */
937 COSTS_N_INSNS (21), /* ddiv */
938 128, /* cache line size */
942 0, /* SF->DF convert */
945 /* Instruction costs on Cell processor. */
946 /* COSTS_N_INSNS (1) ~ one add. */
948 struct processor_costs ppccell_cost = {
949 COSTS_N_INSNS (9/2)+2, /* mulsi */
950 COSTS_N_INSNS (6/2), /* mulsi_const */
951 COSTS_N_INSNS (6/2), /* mulsi_const9 */
952 COSTS_N_INSNS (15/2)+2, /* muldi */
953 COSTS_N_INSNS (38/2), /* divsi */
954 COSTS_N_INSNS (70/2), /* divdi */
955 COSTS_N_INSNS (10/2), /* fp */
956 COSTS_N_INSNS (10/2), /* dmul */
957 COSTS_N_INSNS (74/2), /* sdiv */
958 COSTS_N_INSNS (74/2), /* ddiv */
959 128, /* cache line size */
963 0, /* SF->DF convert */
966 /* Instruction costs on PPC750 and PPC7400 processors. */
968 struct processor_costs ppc750_cost = {
969 COSTS_N_INSNS (5), /* mulsi */
970 COSTS_N_INSNS (3), /* mulsi_const */
971 COSTS_N_INSNS (2), /* mulsi_const9 */
972 COSTS_N_INSNS (5), /* muldi */
973 COSTS_N_INSNS (17), /* divsi */
974 COSTS_N_INSNS (17), /* divdi */
975 COSTS_N_INSNS (3), /* fp */
976 COSTS_N_INSNS (3), /* dmul */
977 COSTS_N_INSNS (17), /* sdiv */
978 COSTS_N_INSNS (31), /* ddiv */
979 32, /* cache line size */
983 0, /* SF->DF convert */
986 /* Instruction costs on PPC7450 processors. */
988 struct processor_costs ppc7450_cost = {
989 COSTS_N_INSNS (4), /* mulsi */
990 COSTS_N_INSNS (3), /* mulsi_const */
991 COSTS_N_INSNS (3), /* mulsi_const9 */
992 COSTS_N_INSNS (4), /* muldi */
993 COSTS_N_INSNS (23), /* divsi */
994 COSTS_N_INSNS (23), /* divdi */
995 COSTS_N_INSNS (5), /* fp */
996 COSTS_N_INSNS (5), /* dmul */
997 COSTS_N_INSNS (21), /* sdiv */
998 COSTS_N_INSNS (35), /* ddiv */
999 32, /* cache line size */
1001 1024, /* l2 cache */
1003 0, /* SF->DF convert */
1006 /* Instruction costs on PPC8540 processors. */
1008 struct processor_costs ppc8540_cost = {
1009 COSTS_N_INSNS (4), /* mulsi */
1010 COSTS_N_INSNS (4), /* mulsi_const */
1011 COSTS_N_INSNS (4), /* mulsi_const9 */
1012 COSTS_N_INSNS (4), /* muldi */
1013 COSTS_N_INSNS (19), /* divsi */
1014 COSTS_N_INSNS (19), /* divdi */
1015 COSTS_N_INSNS (4), /* fp */
1016 COSTS_N_INSNS (4), /* dmul */
1017 COSTS_N_INSNS (29), /* sdiv */
1018 COSTS_N_INSNS (29), /* ddiv */
1019 32, /* cache line size */
1022 1, /* prefetch streams /*/
1023 0, /* SF->DF convert */
1026 /* Instruction costs on E300C2 and E300C3 cores. */
1028 struct processor_costs ppce300c2c3_cost = {
1029 COSTS_N_INSNS (4), /* mulsi */
1030 COSTS_N_INSNS (4), /* mulsi_const */
1031 COSTS_N_INSNS (4), /* mulsi_const9 */
1032 COSTS_N_INSNS (4), /* muldi */
1033 COSTS_N_INSNS (19), /* divsi */
1034 COSTS_N_INSNS (19), /* divdi */
1035 COSTS_N_INSNS (3), /* fp */
1036 COSTS_N_INSNS (4), /* dmul */
1037 COSTS_N_INSNS (18), /* sdiv */
1038 COSTS_N_INSNS (33), /* ddiv */
1042 1, /* prefetch streams /*/
1043 0, /* SF->DF convert */
1046 /* Instruction costs on PPCE500MC processors. */
1048 struct processor_costs ppce500mc_cost = {
1049 COSTS_N_INSNS (4), /* mulsi */
1050 COSTS_N_INSNS (4), /* mulsi_const */
1051 COSTS_N_INSNS (4), /* mulsi_const9 */
1052 COSTS_N_INSNS (4), /* muldi */
1053 COSTS_N_INSNS (14), /* divsi */
1054 COSTS_N_INSNS (14), /* divdi */
1055 COSTS_N_INSNS (8), /* fp */
1056 COSTS_N_INSNS (10), /* dmul */
1057 COSTS_N_INSNS (36), /* sdiv */
1058 COSTS_N_INSNS (66), /* ddiv */
1059 64, /* cache line size */
1062 1, /* prefetch streams /*/
1063 0, /* SF->DF convert */
1066 /* Instruction costs on PPCE500MC64 processors. */
1068 struct processor_costs ppce500mc64_cost = {
1069 COSTS_N_INSNS (4), /* mulsi */
1070 COSTS_N_INSNS (4), /* mulsi_const */
1071 COSTS_N_INSNS (4), /* mulsi_const9 */
1072 COSTS_N_INSNS (4), /* muldi */
1073 COSTS_N_INSNS (14), /* divsi */
1074 COSTS_N_INSNS (14), /* divdi */
1075 COSTS_N_INSNS (4), /* fp */
1076 COSTS_N_INSNS (10), /* dmul */
1077 COSTS_N_INSNS (36), /* sdiv */
1078 COSTS_N_INSNS (66), /* ddiv */
1079 64, /* cache line size */
1082 1, /* prefetch streams /*/
1083 0, /* SF->DF convert */
1086 /* Instruction costs on PPCE5500 processors. */
1088 struct processor_costs ppce5500_cost = {
1089 COSTS_N_INSNS (5), /* mulsi */
1090 COSTS_N_INSNS (5), /* mulsi_const */
1091 COSTS_N_INSNS (4), /* mulsi_const9 */
1092 COSTS_N_INSNS (5), /* muldi */
1093 COSTS_N_INSNS (14), /* divsi */
1094 COSTS_N_INSNS (14), /* divdi */
1095 COSTS_N_INSNS (7), /* fp */
1096 COSTS_N_INSNS (10), /* dmul */
1097 COSTS_N_INSNS (36), /* sdiv */
1098 COSTS_N_INSNS (66), /* ddiv */
1099 64, /* cache line size */
1102 1, /* prefetch streams /*/
1103 0, /* SF->DF convert */
1106 /* Instruction costs on PPCE6500 processors. */
1108 struct processor_costs ppce6500_cost = {
1109 COSTS_N_INSNS (5), /* mulsi */
1110 COSTS_N_INSNS (5), /* mulsi_const */
1111 COSTS_N_INSNS (4), /* mulsi_const9 */
1112 COSTS_N_INSNS (5), /* muldi */
1113 COSTS_N_INSNS (14), /* divsi */
1114 COSTS_N_INSNS (14), /* divdi */
1115 COSTS_N_INSNS (7), /* fp */
1116 COSTS_N_INSNS (10), /* dmul */
1117 COSTS_N_INSNS (36), /* sdiv */
1118 COSTS_N_INSNS (66), /* ddiv */
1119 64, /* cache line size */
1122 1, /* prefetch streams /*/
1123 0, /* SF->DF convert */
1126 /* Instruction costs on AppliedMicro Titan processors. */
1128 struct processor_costs titan_cost = {
1129 COSTS_N_INSNS (5), /* mulsi */
1130 COSTS_N_INSNS (5), /* mulsi_const */
1131 COSTS_N_INSNS (5), /* mulsi_const9 */
1132 COSTS_N_INSNS (5), /* muldi */
1133 COSTS_N_INSNS (18), /* divsi */
1134 COSTS_N_INSNS (18), /* divdi */
1135 COSTS_N_INSNS (10), /* fp */
1136 COSTS_N_INSNS (10), /* dmul */
1137 COSTS_N_INSNS (46), /* sdiv */
1138 COSTS_N_INSNS (72), /* ddiv */
1139 32, /* cache line size */
1142 1, /* prefetch streams /*/
1143 0, /* SF->DF convert */
1146 /* Instruction costs on POWER4 and POWER5 processors. */
1148 struct processor_costs power4_cost = {
1149 COSTS_N_INSNS (3), /* mulsi */
1150 COSTS_N_INSNS (2), /* mulsi_const */
1151 COSTS_N_INSNS (2), /* mulsi_const9 */
1152 COSTS_N_INSNS (4), /* muldi */
1153 COSTS_N_INSNS (18), /* divsi */
1154 COSTS_N_INSNS (34), /* divdi */
1155 COSTS_N_INSNS (3), /* fp */
1156 COSTS_N_INSNS (3), /* dmul */
1157 COSTS_N_INSNS (17), /* sdiv */
1158 COSTS_N_INSNS (17), /* ddiv */
1159 128, /* cache line size */
1161 1024, /* l2 cache */
1162 8, /* prefetch streams /*/
1163 0, /* SF->DF convert */
1166 /* Instruction costs on POWER6 processors. */
1168 struct processor_costs power6_cost = {
1169 COSTS_N_INSNS (8), /* mulsi */
1170 COSTS_N_INSNS (8), /* mulsi_const */
1171 COSTS_N_INSNS (8), /* mulsi_const9 */
1172 COSTS_N_INSNS (8), /* muldi */
1173 COSTS_N_INSNS (22), /* divsi */
1174 COSTS_N_INSNS (28), /* divdi */
1175 COSTS_N_INSNS (3), /* fp */
1176 COSTS_N_INSNS (3), /* dmul */
1177 COSTS_N_INSNS (13), /* sdiv */
1178 COSTS_N_INSNS (16), /* ddiv */
1179 128, /* cache line size */
1181 2048, /* l2 cache */
1182 16, /* prefetch streams */
1183 0, /* SF->DF convert */
1186 /* Instruction costs on POWER7 processors. */
1188 struct processor_costs power7_cost = {
1189 COSTS_N_INSNS (2), /* mulsi */
1190 COSTS_N_INSNS (2), /* mulsi_const */
1191 COSTS_N_INSNS (2), /* mulsi_const9 */
1192 COSTS_N_INSNS (2), /* muldi */
1193 COSTS_N_INSNS (18), /* divsi */
1194 COSTS_N_INSNS (34), /* divdi */
1195 COSTS_N_INSNS (3), /* fp */
1196 COSTS_N_INSNS (3), /* dmul */
1197 COSTS_N_INSNS (13), /* sdiv */
1198 COSTS_N_INSNS (16), /* ddiv */
1199 128, /* cache line size */
1202 12, /* prefetch streams */
1203 COSTS_N_INSNS (3), /* SF->DF convert */
1206 /* Instruction costs on POWER8 processors. */
1208 struct processor_costs power8_cost = {
1209 COSTS_N_INSNS (3), /* mulsi */
1210 COSTS_N_INSNS (3), /* mulsi_const */
1211 COSTS_N_INSNS (3), /* mulsi_const9 */
1212 COSTS_N_INSNS (3), /* muldi */
1213 COSTS_N_INSNS (19), /* divsi */
1214 COSTS_N_INSNS (35), /* divdi */
1215 COSTS_N_INSNS (3), /* fp */
1216 COSTS_N_INSNS (3), /* dmul */
1217 COSTS_N_INSNS (14), /* sdiv */
1218 COSTS_N_INSNS (17), /* ddiv */
1219 128, /* cache line size */
1222 12, /* prefetch streams */
1223 COSTS_N_INSNS (3), /* SF->DF convert */
1226 /* Instruction costs on POWER9 processors. */
1228 struct processor_costs power9_cost = {
1229 COSTS_N_INSNS (3), /* mulsi */
1230 COSTS_N_INSNS (3), /* mulsi_const */
1231 COSTS_N_INSNS (3), /* mulsi_const9 */
1232 COSTS_N_INSNS (3), /* muldi */
1233 COSTS_N_INSNS (8), /* divsi */
1234 COSTS_N_INSNS (12), /* divdi */
1235 COSTS_N_INSNS (3), /* fp */
1236 COSTS_N_INSNS (3), /* dmul */
1237 COSTS_N_INSNS (13), /* sdiv */
1238 COSTS_N_INSNS (18), /* ddiv */
1239 128, /* cache line size */
1242 8, /* prefetch streams */
1243 COSTS_N_INSNS (3), /* SF->DF convert */
1246 /* Instruction costs on POWER A2 processors. */
1248 struct processor_costs ppca2_cost = {
1249 COSTS_N_INSNS (16), /* mulsi */
1250 COSTS_N_INSNS (16), /* mulsi_const */
1251 COSTS_N_INSNS (16), /* mulsi_const9 */
1252 COSTS_N_INSNS (16), /* muldi */
1253 COSTS_N_INSNS (22), /* divsi */
1254 COSTS_N_INSNS (28), /* divdi */
1255 COSTS_N_INSNS (3), /* fp */
1256 COSTS_N_INSNS (3), /* dmul */
1257 COSTS_N_INSNS (59), /* sdiv */
1258 COSTS_N_INSNS (72), /* ddiv */
1261 2048, /* l2 cache */
1262 16, /* prefetch streams */
1263 0, /* SF->DF convert */
1267 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1268 #undef RS6000_BUILTIN_0
1269 #undef RS6000_BUILTIN_1
1270 #undef RS6000_BUILTIN_2
1271 #undef RS6000_BUILTIN_3
1272 #undef RS6000_BUILTIN_A
1273 #undef RS6000_BUILTIN_D
1274 #undef RS6000_BUILTIN_H
1275 #undef RS6000_BUILTIN_P
1276 #undef RS6000_BUILTIN_X
1278 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1279 { NAME, ICODE, MASK, ATTR },
1281 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1282 { NAME, ICODE, MASK, ATTR },
1284 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1285 { NAME, ICODE, MASK, ATTR },
1287 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 struct rs6000_builtin_info_type {
1307 const enum insn_code icode;
1308 const HOST_WIDE_INT mask;
1309 const unsigned attr;
1312 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1314 #include "rs6000-builtin.def"
1317 #undef RS6000_BUILTIN_0
1318 #undef RS6000_BUILTIN_1
1319 #undef RS6000_BUILTIN_2
1320 #undef RS6000_BUILTIN_3
1321 #undef RS6000_BUILTIN_A
1322 #undef RS6000_BUILTIN_D
1323 #undef RS6000_BUILTIN_H
1324 #undef RS6000_BUILTIN_P
1325 #undef RS6000_BUILTIN_X
1327 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1328 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1331 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1332 static struct machine_function * rs6000_init_machine_status (void);
1333 static int rs6000_ra_ever_killed (void);
1334 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1335 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1336 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1337 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1338 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1339 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1340 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1341 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1343 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1345 static bool is_microcoded_insn (rtx_insn *);
1346 static bool is_nonpipeline_insn (rtx_insn *);
1347 static bool is_cracked_insn (rtx_insn *);
1348 static bool is_load_insn (rtx, rtx *);
1349 static bool is_store_insn (rtx, rtx *);
1350 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1351 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1352 static bool insn_must_be_first_in_group (rtx_insn *);
1353 static bool insn_must_be_last_in_group (rtx_insn *);
1354 static void altivec_init_builtins (void);
1355 static tree builtin_function_type (machine_mode, machine_mode,
1356 machine_mode, machine_mode,
1357 enum rs6000_builtins, const char *name);
1358 static void rs6000_common_init_builtins (void);
1359 static void htm_init_builtins (void);
1360 static rs6000_stack_t *rs6000_stack_info (void);
1361 static void is_altivec_return_reg (rtx, void *);
1362 int easy_vector_constant (rtx, machine_mode);
1363 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1364 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1365 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1368 static void macho_branch_islands (void);
1369 static tree get_prev_label (tree);
1371 static bool rs6000_mode_dependent_address (const_rtx);
1372 static bool rs6000_debug_mode_dependent_address (const_rtx);
1373 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1374 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1376 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1379 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1380 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1382 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1385 static bool rs6000_debug_can_change_mode_class (machine_mode,
1388 static bool rs6000_save_toc_in_prologue_p (void);
1389 static rtx rs6000_internal_arg_pointer (void);
1391 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1392 = rs6000_mode_dependent_address;
1394 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1396 = rs6000_secondary_reload_class;
1398 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1399 = rs6000_preferred_reload_class;
1401 const int INSN_NOT_AVAILABLE = -1;
1403 static void rs6000_print_isa_options (FILE *, int, const char *,
1405 static void rs6000_print_builtin_options (FILE *, int, const char *,
1407 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1409 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1410 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1411 enum rs6000_reg_type,
1413 secondary_reload_info *,
1415 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1416 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1417 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1419 /* Hash table stuff for keeping track of TOC entries. */
1421 struct GTY((for_user)) toc_hash_struct
1423 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1424 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1426 machine_mode key_mode;
1430 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1432 static hashval_t hash (toc_hash_struct *);
1433 static bool equal (toc_hash_struct *, toc_hash_struct *);
1436 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1438 /* Hash table to keep track of the argument types for builtin functions. */
1440 struct GTY((for_user)) builtin_hash_struct
1443 machine_mode mode[4]; /* return value + 3 arguments. */
1444 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1447 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1449 static hashval_t hash (builtin_hash_struct *);
1450 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1453 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1456 /* Default register names. */
1457 char rs6000_reg_names[][8] =
1460 "0", "1", "2", "3", "4", "5", "6", "7",
1461 "8", "9", "10", "11", "12", "13", "14", "15",
1462 "16", "17", "18", "19", "20", "21", "22", "23",
1463 "24", "25", "26", "27", "28", "29", "30", "31",
1465 "0", "1", "2", "3", "4", "5", "6", "7",
1466 "8", "9", "10", "11", "12", "13", "14", "15",
1467 "16", "17", "18", "19", "20", "21", "22", "23",
1468 "24", "25", "26", "27", "28", "29", "30", "31",
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1475 "lr", "ctr", "ca", "ap",
1477 "0", "1", "2", "3", "4", "5", "6", "7",
1478 /* vrsave vscr sfp */
1479 "vrsave", "vscr", "sfp",
1482 #ifdef TARGET_REGNAMES
1483 static const char alt_reg_names[][8] =
1486 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1487 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1488 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1489 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1491 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1492 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1493 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1494 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1496 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1497 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1498 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1499 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1501 "lr", "ctr", "ca", "ap",
1503 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1504 /* vrsave vscr sfp */
1505 "vrsave", "vscr", "sfp",
1509 /* Table of valid machine attributes. */
1511 static const struct attribute_spec rs6000_attribute_table[] =
1513 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1514 affects_type_identity, handler, exclude } */
1515 { "altivec", 1, 1, false, true, false, false,
1516 rs6000_handle_altivec_attribute, NULL },
1517 { "longcall", 0, 0, false, true, true, false,
1518 rs6000_handle_longcall_attribute, NULL },
1519 { "shortcall", 0, 0, false, true, true, false,
1520 rs6000_handle_longcall_attribute, NULL },
1521 { "ms_struct", 0, 0, false, false, false, false,
1522 rs6000_handle_struct_attribute, NULL },
1523 { "gcc_struct", 0, 0, false, false, false, false,
1524 rs6000_handle_struct_attribute, NULL },
1525 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1526 SUBTARGET_ATTRIBUTE_TABLE,
1528 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1531 #ifndef TARGET_PROFILE_KERNEL
1532 #define TARGET_PROFILE_KERNEL 0
1535 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1536 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1538 /* Initialize the GCC target structure. */
1539 #undef TARGET_ATTRIBUTE_TABLE
1540 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1541 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1542 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1543 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1544 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1546 #undef TARGET_ASM_ALIGNED_DI_OP
1547 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1549 /* Default unaligned ops are only provided for ELF. Find the ops needed
1550 for non-ELF systems. */
1551 #ifndef OBJECT_FORMAT_ELF
1553 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1555 #undef TARGET_ASM_UNALIGNED_HI_OP
1556 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1557 #undef TARGET_ASM_UNALIGNED_SI_OP
1558 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1559 #undef TARGET_ASM_UNALIGNED_DI_OP
1560 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1563 #undef TARGET_ASM_UNALIGNED_HI_OP
1564 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1565 #undef TARGET_ASM_UNALIGNED_SI_OP
1566 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1567 #undef TARGET_ASM_UNALIGNED_DI_OP
1568 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1569 #undef TARGET_ASM_ALIGNED_DI_OP
1570 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1574 /* This hook deals with fixups for relocatable code and DI-mode objects
1576 #undef TARGET_ASM_INTEGER
1577 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1579 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1580 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1581 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1584 #undef TARGET_SET_UP_BY_PROLOGUE
1585 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1587 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1588 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1589 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1590 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1591 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1592 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1593 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1594 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1595 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1596 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1597 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1598 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1600 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1601 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1603 #undef TARGET_INTERNAL_ARG_POINTER
1604 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1606 #undef TARGET_HAVE_TLS
1607 #define TARGET_HAVE_TLS HAVE_AS_TLS
1609 #undef TARGET_CANNOT_FORCE_CONST_MEM
1610 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1612 #undef TARGET_DELEGITIMIZE_ADDRESS
1613 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1615 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1616 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1618 #undef TARGET_LEGITIMATE_COMBINED_INSN
1619 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1621 #undef TARGET_ASM_FUNCTION_PROLOGUE
1622 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1623 #undef TARGET_ASM_FUNCTION_EPILOGUE
1624 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1626 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1627 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1629 #undef TARGET_LEGITIMIZE_ADDRESS
1630 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1632 #undef TARGET_SCHED_VARIABLE_ISSUE
1633 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1635 #undef TARGET_SCHED_ISSUE_RATE
1636 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1637 #undef TARGET_SCHED_ADJUST_COST
1638 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1639 #undef TARGET_SCHED_ADJUST_PRIORITY
1640 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1641 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1642 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1643 #undef TARGET_SCHED_INIT
1644 #define TARGET_SCHED_INIT rs6000_sched_init
1645 #undef TARGET_SCHED_FINISH
1646 #define TARGET_SCHED_FINISH rs6000_sched_finish
1647 #undef TARGET_SCHED_REORDER
1648 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1649 #undef TARGET_SCHED_REORDER2
1650 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1652 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1653 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1655 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1656 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1658 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1659 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1660 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1661 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1662 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1663 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1664 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1665 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1667 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1668 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1670 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1671 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1672 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1673 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1674 rs6000_builtin_support_vector_misalignment
1675 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1676 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1677 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1678 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1679 rs6000_builtin_vectorization_cost
1680 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1681 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1682 rs6000_preferred_simd_mode
1683 #undef TARGET_VECTORIZE_INIT_COST
1684 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1685 #undef TARGET_VECTORIZE_ADD_STMT_COST
1686 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1687 #undef TARGET_VECTORIZE_FINISH_COST
1688 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1689 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1690 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1692 #undef TARGET_INIT_BUILTINS
1693 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1694 #undef TARGET_BUILTIN_DECL
1695 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1697 #undef TARGET_FOLD_BUILTIN
1698 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1699 #undef TARGET_GIMPLE_FOLD_BUILTIN
1700 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1702 #undef TARGET_EXPAND_BUILTIN
1703 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1705 #undef TARGET_MANGLE_TYPE
1706 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1708 #undef TARGET_INIT_LIBFUNCS
1709 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1712 #undef TARGET_BINDS_LOCAL_P
1713 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1716 #undef TARGET_MS_BITFIELD_LAYOUT_P
1717 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1719 #undef TARGET_ASM_OUTPUT_MI_THUNK
1720 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1722 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1723 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1725 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1726 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1728 #undef TARGET_REGISTER_MOVE_COST
1729 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1730 #undef TARGET_MEMORY_MOVE_COST
1731 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1732 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
1733 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
1734 rs6000_ira_change_pseudo_allocno_class
1735 #undef TARGET_CANNOT_COPY_INSN_P
1736 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1737 #undef TARGET_RTX_COSTS
1738 #define TARGET_RTX_COSTS rs6000_rtx_costs
1739 #undef TARGET_ADDRESS_COST
1740 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1741 #undef TARGET_INSN_COST
1742 #define TARGET_INSN_COST rs6000_insn_cost
1744 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1745 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1747 #undef TARGET_PROMOTE_FUNCTION_MODE
1748 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1750 #undef TARGET_RETURN_IN_MEMORY
1751 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1753 #undef TARGET_RETURN_IN_MSB
1754 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1756 #undef TARGET_SETUP_INCOMING_VARARGS
1757 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1759 /* Always strict argument naming on rs6000. */
1760 #undef TARGET_STRICT_ARGUMENT_NAMING
1761 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1762 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1763 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_SPLIT_COMPLEX_ARG
1765 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1766 #undef TARGET_MUST_PASS_IN_STACK
1767 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1768 #undef TARGET_PASS_BY_REFERENCE
1769 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1770 #undef TARGET_ARG_PARTIAL_BYTES
1771 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1772 #undef TARGET_FUNCTION_ARG_ADVANCE
1773 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1774 #undef TARGET_FUNCTION_ARG
1775 #define TARGET_FUNCTION_ARG rs6000_function_arg
1776 #undef TARGET_FUNCTION_ARG_PADDING
1777 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1778 #undef TARGET_FUNCTION_ARG_BOUNDARY
1779 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1781 #undef TARGET_BUILD_BUILTIN_VA_LIST
1782 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1784 #undef TARGET_EXPAND_BUILTIN_VA_START
1785 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1787 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1788 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1790 #undef TARGET_EH_RETURN_FILTER_MODE
1791 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1793 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1794 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1796 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1797 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1799 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1800 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1802 #undef TARGET_FLOATN_MODE
1803 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1805 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1806 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1808 #undef TARGET_MD_ASM_ADJUST
1809 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1811 #undef TARGET_OPTION_OVERRIDE
1812 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1814 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1815 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1816 rs6000_builtin_vectorized_function
1818 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1819 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1820 rs6000_builtin_md_vectorized_function
1822 #undef TARGET_STACK_PROTECT_GUARD
1823 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1826 #undef TARGET_STACK_PROTECT_FAIL
1827 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1831 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1832 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1835 /* Use a 32-bit anchor range. This leads to sequences like:
1837 addis tmp,anchor,high
1840 where tmp itself acts as an anchor, and can be shared between
1841 accesses to the same 64k page. */
1842 #undef TARGET_MIN_ANCHOR_OFFSET
1843 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1844 #undef TARGET_MAX_ANCHOR_OFFSET
1845 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1846 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1847 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1848 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1849 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1851 #undef TARGET_BUILTIN_RECIPROCAL
1852 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1854 #undef TARGET_SECONDARY_RELOAD
1855 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1856 #undef TARGET_SECONDARY_MEMORY_NEEDED
1857 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1859 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1861 #undef TARGET_LEGITIMATE_ADDRESS_P
1862 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1864 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1865 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1867 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1868 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1870 #undef TARGET_CAN_ELIMINATE
1871 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1873 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1874 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1876 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1877 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1879 #undef TARGET_TRAMPOLINE_INIT
1880 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1882 #undef TARGET_FUNCTION_VALUE
1883 #define TARGET_FUNCTION_VALUE rs6000_function_value
1885 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1886 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1888 #undef TARGET_OPTION_SAVE
1889 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1891 #undef TARGET_OPTION_RESTORE
1892 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1894 #undef TARGET_OPTION_PRINT
1895 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1897 #undef TARGET_CAN_INLINE_P
1898 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1900 #undef TARGET_SET_CURRENT_FUNCTION
1901 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1903 #undef TARGET_LEGITIMATE_CONSTANT_P
1904 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1906 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1907 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1909 #undef TARGET_CAN_USE_DOLOOP_P
1910 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1912 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1913 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1915 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1916 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1917 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1918 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1919 #undef TARGET_UNWIND_WORD_MODE
1920 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1922 #undef TARGET_OFFLOAD_OPTIONS
1923 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1925 #undef TARGET_C_MODE_FOR_SUFFIX
1926 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1928 #undef TARGET_INVALID_BINARY_OP
1929 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1931 #undef TARGET_OPTAB_SUPPORTED_P
1932 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1934 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1935 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1937 #undef TARGET_COMPARE_VERSION_PRIORITY
1938 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1940 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1941 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1942 rs6000_generate_version_dispatcher_body
1944 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1945 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1946 rs6000_get_function_versions_dispatcher
1948 #undef TARGET_OPTION_FUNCTION_VERSIONS
1949 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1951 #undef TARGET_HARD_REGNO_NREGS
1952 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1953 #undef TARGET_HARD_REGNO_MODE_OK
1954 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1956 #undef TARGET_MODES_TIEABLE_P
1957 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1959 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1960 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1961 rs6000_hard_regno_call_part_clobbered
1963 #undef TARGET_SLOW_UNALIGNED_ACCESS
1964 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1966 #undef TARGET_CAN_CHANGE_MODE_CLASS
1967 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1969 #undef TARGET_CONSTANT_ALIGNMENT
1970 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1972 #undef TARGET_STARTING_FRAME_OFFSET
1973 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1975 #if TARGET_ELF && RS6000_WEAK
1976 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1977 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1980 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1981 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1983 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1984 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1987 /* Processor table. */
1990 const char *const name; /* Canonical processor name. */
1991 const enum processor_type processor; /* Processor type enum value. */
1992 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1995 static struct rs6000_ptt const processor_target_table[] =
1997 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1998 #include "rs6000-cpus.def"
2002 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2006 rs6000_cpu_name_lookup (const char *name)
2012 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2013 if (! strcmp (name, processor_target_table[i].name))
2021 /* Return number of consecutive hard regs needed starting at reg REGNO
2022 to hold something of mode MODE.
2023 This is ordinarily the length in words of a value of mode MODE
2024 but can be less for certain modes in special long registers.
2026 POWER and PowerPC GPRs hold 32 bits worth;
2027 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2030 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2032 unsigned HOST_WIDE_INT reg_size;
2034 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2035 128-bit floating point that can go in vector registers, which has VSX
2036 memory addressing. */
2037 if (FP_REGNO_P (regno))
2038 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2039 ? UNITS_PER_VSX_WORD
2040 : UNITS_PER_FP_WORD);
2042 else if (ALTIVEC_REGNO_P (regno))
2043 reg_size = UNITS_PER_ALTIVEC_WORD;
2046 reg_size = UNITS_PER_WORD;
2048 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2051 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2054 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2056 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2058 if (COMPLEX_MODE_P (mode))
2059 mode = GET_MODE_INNER (mode);
2061 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2062 register combinations, and use PTImode where we need to deal with quad
2063 word memory operations. Don't allow quad words in the argument or frame
2064 pointer registers, just registers 0..31. */
2065 if (mode == PTImode)
2066 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2067 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2068 && ((regno & 1) == 0));
2070 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2071 implementations. Don't allow an item to be split between a FP register
2072 and an Altivec register. Allow TImode in all VSX registers if the user
2074 if (TARGET_VSX && VSX_REGNO_P (regno)
2075 && (VECTOR_MEM_VSX_P (mode)
2076 || FLOAT128_VECTOR_P (mode)
2077 || reg_addr[mode].scalar_in_vmx_p
2079 || (TARGET_VADDUQM && mode == V1TImode)))
2081 if (FP_REGNO_P (regno))
2082 return FP_REGNO_P (last_regno);
2084 if (ALTIVEC_REGNO_P (regno))
2086 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2089 return ALTIVEC_REGNO_P (last_regno);
2093 /* The GPRs can hold any mode, but values bigger than one register
2094 cannot go past R31. */
2095 if (INT_REGNO_P (regno))
2096 return INT_REGNO_P (last_regno);
2098 /* The float registers (except for VSX vector modes) can only hold floating
2099 modes and DImode. */
2100 if (FP_REGNO_P (regno))
2102 if (FLOAT128_VECTOR_P (mode))
2105 if (SCALAR_FLOAT_MODE_P (mode)
2106 && (mode != TDmode || (regno % 2) == 0)
2107 && FP_REGNO_P (last_regno))
2110 if (GET_MODE_CLASS (mode) == MODE_INT)
2112 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2115 if (TARGET_P8_VECTOR && (mode == SImode))
2118 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2125 /* The CR register can only hold CC modes. */
2126 if (CR_REGNO_P (regno))
2127 return GET_MODE_CLASS (mode) == MODE_CC;
2129 if (CA_REGNO_P (regno))
2130 return mode == Pmode || mode == SImode;
2132 /* AltiVec only in AldyVec registers. */
2133 if (ALTIVEC_REGNO_P (regno))
2134 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2135 || mode == V1TImode);
2137 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2138 and it must be able to fit within the register set. */
2140 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2143 /* Implement TARGET_HARD_REGNO_NREGS. */
2146 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2148 return rs6000_hard_regno_nregs[mode][regno];
2151 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2154 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2156 return rs6000_hard_regno_mode_ok_p[mode][regno];
2159 /* Implement TARGET_MODES_TIEABLE_P.
2161 PTImode cannot tie with other modes because PTImode is restricted to even
2162 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2165 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2166 128-bit floating point on VSX systems ties with other vectors. */
2169 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2171 if (mode1 == PTImode)
2172 return mode2 == PTImode;
2173 if (mode2 == PTImode)
2176 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2177 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2181 if (SCALAR_FLOAT_MODE_P (mode1))
2182 return SCALAR_FLOAT_MODE_P (mode2);
2183 if (SCALAR_FLOAT_MODE_P (mode2))
2186 if (GET_MODE_CLASS (mode1) == MODE_CC)
2187 return GET_MODE_CLASS (mode2) == MODE_CC;
2188 if (GET_MODE_CLASS (mode2) == MODE_CC)
2194 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2197 rs6000_hard_regno_call_part_clobbered (rtx_insn *insn ATTRIBUTE_UNUSED,
2198 unsigned int regno, machine_mode mode)
2202 && GET_MODE_SIZE (mode) > 4
2203 && INT_REGNO_P (regno))
2207 && FP_REGNO_P (regno)
2208 && GET_MODE_SIZE (mode) > 8
2209 && !FLOAT128_2REG_P (mode))
2215 /* Print interesting facts about registers. */
2217 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2221 for (r = first_regno; r <= last_regno; ++r)
2223 const char *comma = "";
2226 if (first_regno == last_regno)
2227 fprintf (stderr, "%s:\t", reg_name);
2229 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2232 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2233 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2237 fprintf (stderr, ",\n\t");
2242 if (rs6000_hard_regno_nregs[m][r] > 1)
2243 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2244 rs6000_hard_regno_nregs[m][r]);
2246 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2251 if (call_used_regs[r])
2255 fprintf (stderr, ",\n\t");
2260 len += fprintf (stderr, "%s%s", comma, "call-used");
2268 fprintf (stderr, ",\n\t");
2273 len += fprintf (stderr, "%s%s", comma, "fixed");
2279 fprintf (stderr, ",\n\t");
2283 len += fprintf (stderr, "%sreg-class = %s", comma,
2284 reg_class_names[(int)rs6000_regno_regclass[r]]);
2289 fprintf (stderr, ",\n\t");
2293 fprintf (stderr, "%sregno = %d\n", comma, r);
2298 rs6000_debug_vector_unit (enum rs6000_vector v)
2304 case VECTOR_NONE: ret = "none"; break;
2305 case VECTOR_ALTIVEC: ret = "altivec"; break;
2306 case VECTOR_VSX: ret = "vsx"; break;
2307 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2308 default: ret = "unknown"; break;
2314 /* Inner function printing just the address mask for a particular reload
2316 DEBUG_FUNCTION char *
2317 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2322 if ((mask & RELOAD_REG_VALID) != 0)
2324 else if (keep_spaces)
2327 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2329 else if (keep_spaces)
2332 if ((mask & RELOAD_REG_INDEXED) != 0)
2334 else if (keep_spaces)
2337 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2339 else if ((mask & RELOAD_REG_OFFSET) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2346 else if (keep_spaces)
2349 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2351 else if (keep_spaces)
2354 if ((mask & RELOAD_REG_AND_M16) != 0)
2356 else if (keep_spaces)
2364 /* Print the address masks in a human readble fashion. */
2366 rs6000_debug_print_mode (ssize_t m)
2371 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2372 for (rc = 0; rc < N_RELOAD_REG; rc++)
2373 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2374 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2376 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2377 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2379 fprintf (stderr, "%*s Reload=%c%c", spaces, "",
2380 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2381 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2385 spaces += sizeof (" Reload=sl") - 1;
2387 if (reg_addr[m].scalar_in_vmx_p)
2389 fprintf (stderr, "%*s Upper=y", spaces, "");
2393 spaces += sizeof (" Upper=y") - 1;
2395 if (rs6000_vector_unit[m] != VECTOR_NONE
2396 || rs6000_vector_mem[m] != VECTOR_NONE)
2398 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2400 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2401 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2404 fputs ("\n", stderr);
2407 #define DEBUG_FMT_ID "%-32s= "
2408 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2409 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2410 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2412 /* Print various interesting information with -mdebug=reg. */
2414 rs6000_debug_reg_global (void)
2416 static const char *const tf[2] = { "false", "true" };
2417 const char *nl = (const char *)0;
2420 char costly_num[20];
2422 char flags_buffer[40];
2423 const char *costly_str;
2424 const char *nop_str;
2425 const char *trace_str;
2426 const char *abi_str;
2427 const char *cmodel_str;
2428 struct cl_target_option cl_opts;
2430 /* Modes we want tieable information on. */
2431 static const machine_mode print_tieable_modes[] = {
2465 /* Virtual regs we are interested in. */
2466 const static struct {
2467 int regno; /* register number. */
2468 const char *name; /* register name. */
2469 } virtual_regs[] = {
2470 { STACK_POINTER_REGNUM, "stack pointer:" },
2471 { TOC_REGNUM, "toc: " },
2472 { STATIC_CHAIN_REGNUM, "static chain: " },
2473 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2474 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2475 { ARG_POINTER_REGNUM, "arg pointer: " },
2476 { FRAME_POINTER_REGNUM, "frame pointer:" },
2477 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2478 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2479 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2480 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2481 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2482 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2483 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2484 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2485 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2488 fputs ("\nHard register information:\n", stderr);
2489 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2490 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2491 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2494 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2495 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2496 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2497 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2498 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2499 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2501 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2502 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2503 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2507 "d reg_class = %s\n"
2508 "f reg_class = %s\n"
2509 "v reg_class = %s\n"
2510 "wa reg_class = %s\n"
2511 "wd reg_class = %s\n"
2512 "we reg_class = %s\n"
2513 "wf reg_class = %s\n"
2514 "wg reg_class = %s\n"
2515 "wi reg_class = %s\n"
2516 "wp reg_class = %s\n"
2517 "wq reg_class = %s\n"
2518 "wr reg_class = %s\n"
2519 "ws reg_class = %s\n"
2520 "wt reg_class = %s\n"
2521 "wv reg_class = %s\n"
2522 "ww reg_class = %s\n"
2523 "wx reg_class = %s\n"
2524 "wA reg_class = %s\n"
2526 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2527 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2528 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2529 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2530 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2531 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2532 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2533 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2534 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2535 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2536 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2537 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2538 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2539 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2540 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2541 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2542 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2543 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
2546 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2547 rs6000_debug_print_mode (m);
2549 fputs ("\n", stderr);
2551 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2553 machine_mode mode1 = print_tieable_modes[m1];
2554 bool first_time = true;
2556 nl = (const char *)0;
2557 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2559 machine_mode mode2 = print_tieable_modes[m2];
2560 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2564 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2569 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2574 fputs ("\n", stderr);
2580 if (rs6000_recip_control)
2582 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2584 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2585 if (rs6000_recip_bits[m])
2588 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2590 (RS6000_RECIP_AUTO_RE_P (m)
2592 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2593 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2595 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2598 fputs ("\n", stderr);
2601 if (rs6000_cpu_index >= 0)
2603 const char *name = processor_target_table[rs6000_cpu_index].name;
2605 = processor_target_table[rs6000_cpu_index].target_enable;
2607 sprintf (flags_buffer, "-mcpu=%s flags", name);
2608 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2611 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2613 if (rs6000_tune_index >= 0)
2615 const char *name = processor_target_table[rs6000_tune_index].name;
2617 = processor_target_table[rs6000_tune_index].target_enable;
2619 sprintf (flags_buffer, "-mtune=%s flags", name);
2620 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2623 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2625 cl_target_option_save (&cl_opts, &global_options);
2626 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2629 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2630 rs6000_isa_flags_explicit);
2632 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2633 rs6000_builtin_mask);
2635 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2637 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2638 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2640 switch (rs6000_sched_costly_dep)
2642 case max_dep_latency:
2643 costly_str = "max_dep_latency";
2647 costly_str = "no_dep_costly";
2650 case all_deps_costly:
2651 costly_str = "all_deps_costly";
2654 case true_store_to_load_dep_costly:
2655 costly_str = "true_store_to_load_dep_costly";
2658 case store_to_load_dep_costly:
2659 costly_str = "store_to_load_dep_costly";
2663 costly_str = costly_num;
2664 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2668 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2670 switch (rs6000_sched_insert_nops)
2672 case sched_finish_regroup_exact:
2673 nop_str = "sched_finish_regroup_exact";
2676 case sched_finish_pad_groups:
2677 nop_str = "sched_finish_pad_groups";
2680 case sched_finish_none:
2681 nop_str = "sched_finish_none";
2686 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2690 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2692 switch (rs6000_sdata)
2699 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2703 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2707 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2712 switch (rs6000_traceback)
2714 case traceback_default: trace_str = "default"; break;
2715 case traceback_none: trace_str = "none"; break;
2716 case traceback_part: trace_str = "part"; break;
2717 case traceback_full: trace_str = "full"; break;
2718 default: trace_str = "unknown"; break;
2721 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2723 switch (rs6000_current_cmodel)
2725 case CMODEL_SMALL: cmodel_str = "small"; break;
2726 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2727 case CMODEL_LARGE: cmodel_str = "large"; break;
2728 default: cmodel_str = "unknown"; break;
2731 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2733 switch (rs6000_current_abi)
2735 case ABI_NONE: abi_str = "none"; break;
2736 case ABI_AIX: abi_str = "aix"; break;
2737 case ABI_ELFv2: abi_str = "ELFv2"; break;
2738 case ABI_V4: abi_str = "V4"; break;
2739 case ABI_DARWIN: abi_str = "darwin"; break;
2740 default: abi_str = "unknown"; break;
2743 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2745 if (rs6000_altivec_abi)
2746 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2748 if (rs6000_darwin64_abi)
2749 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2751 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2752 (TARGET_SOFT_FLOAT ? "true" : "false"));
2754 if (TARGET_LINK_STACK)
2755 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2757 if (TARGET_P8_FUSION)
2761 strcpy (options, "power8");
2762 if (TARGET_P8_FUSION_SIGN)
2763 strcat (options, ", sign");
2765 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2768 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2769 TARGET_SECURE_PLT ? "secure" : "bss");
2770 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2771 aix_struct_return ? "aix" : "sysv");
2772 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2773 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2774 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2775 tf[!!rs6000_align_branch_targets]);
2776 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2777 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2778 rs6000_long_double_type_size);
2779 if (rs6000_long_double_type_size > 64)
2781 fprintf (stderr, DEBUG_FMT_S, "long double type",
2782 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2783 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2784 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2786 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2787 (int)rs6000_sched_restricted_insns_priority);
2788 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2790 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2791 (int)RS6000_BUILTIN_COUNT);
2793 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2794 (int)TARGET_FLOAT128_ENABLE_TYPE);
2797 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2798 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2800 if (TARGET_DIRECT_MOVE_128)
2801 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2802 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2806 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2807 legitimate address support to figure out the appropriate addressing to
2811 rs6000_setup_reg_addr_masks (void)
2813 ssize_t rc, reg, m, nregs;
2814 addr_mask_type any_addr_mask, addr_mask;
2816 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2818 machine_mode m2 = (machine_mode) m;
2819 bool complex_p = false;
2820 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2823 if (COMPLEX_MODE_P (m2))
2826 m2 = GET_MODE_INNER (m2);
2829 msize = GET_MODE_SIZE (m2);
2831 /* SDmode is special in that we want to access it only via REG+REG
2832 addressing on power7 and above, since we want to use the LFIWZX and
2833 STFIWZX instructions to load it. */
2834 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2837 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2840 reg = reload_reg_map[rc].reg;
2842 /* Can mode values go in the GPR/FPR/Altivec registers? */
2843 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2845 bool small_int_vsx_p = (small_int_p
2846 && (rc == RELOAD_REG_FPR
2847 || rc == RELOAD_REG_VMX));
2849 nregs = rs6000_hard_regno_nregs[m][reg];
2850 addr_mask |= RELOAD_REG_VALID;
2852 /* Indicate if the mode takes more than 1 physical register. If
2853 it takes a single register, indicate it can do REG+REG
2854 addressing. Small integers in VSX registers can only do
2855 REG+REG addressing. */
2856 if (small_int_vsx_p)
2857 addr_mask |= RELOAD_REG_INDEXED;
2858 else if (nregs > 1 || m == BLKmode || complex_p)
2859 addr_mask |= RELOAD_REG_MULTIPLE;
2861 addr_mask |= RELOAD_REG_INDEXED;
2863 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2864 addressing. If we allow scalars into Altivec registers,
2865 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2867 For VSX systems, we don't allow update addressing for
2868 DFmode/SFmode if those registers can go in both the
2869 traditional floating point registers and Altivec registers.
2870 The load/store instructions for the Altivec registers do not
2871 have update forms. If we allowed update addressing, it seems
2872 to break IV-OPT code using floating point if the index type is
2873 int instead of long (PR target/81550 and target/84042). */
2876 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2878 && !VECTOR_MODE_P (m2)
2879 && !FLOAT128_VECTOR_P (m2)
2881 && (m != E_DFmode || !TARGET_VSX)
2882 && (m != E_SFmode || !TARGET_P8_VECTOR)
2883 && !small_int_vsx_p)
2885 addr_mask |= RELOAD_REG_PRE_INCDEC;
2887 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2888 we don't allow PRE_MODIFY for some multi-register
2893 addr_mask |= RELOAD_REG_PRE_MODIFY;
2897 if (TARGET_POWERPC64)
2898 addr_mask |= RELOAD_REG_PRE_MODIFY;
2903 if (TARGET_HARD_FLOAT)
2904 addr_mask |= RELOAD_REG_PRE_MODIFY;
2910 /* GPR and FPR registers can do REG+OFFSET addressing, except
2911 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2912 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2913 if ((addr_mask != 0) && !indexed_only_p
2915 && (rc == RELOAD_REG_GPR
2916 || ((msize == 8 || m2 == SFmode)
2917 && (rc == RELOAD_REG_FPR
2918 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
2919 addr_mask |= RELOAD_REG_OFFSET;
2921 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2922 instructions are enabled. The offset for 128-bit VSX registers is
2923 only 12-bits. While GPRs can handle the full offset range, VSX
2924 registers can only handle the restricted range. */
2925 else if ((addr_mask != 0) && !indexed_only_p
2926 && msize == 16 && TARGET_P9_VECTOR
2927 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
2928 || (m2 == TImode && TARGET_VSX)))
2930 addr_mask |= RELOAD_REG_OFFSET;
2931 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
2932 addr_mask |= RELOAD_REG_QUAD_OFFSET;
2935 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2936 addressing on 128-bit types. */
2937 if (rc == RELOAD_REG_VMX && msize == 16
2938 && (addr_mask & RELOAD_REG_VALID) != 0)
2939 addr_mask |= RELOAD_REG_AND_M16;
2941 reg_addr[m].addr_mask[rc] = addr_mask;
2942 any_addr_mask |= addr_mask;
2945 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
2950 /* Initialize the various global tables that are based on register size. */
2952 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2958 /* Precalculate REGNO_REG_CLASS. */
2959 rs6000_regno_regclass[0] = GENERAL_REGS;
2960 for (r = 1; r < 32; ++r)
2961 rs6000_regno_regclass[r] = BASE_REGS;
2963 for (r = 32; r < 64; ++r)
2964 rs6000_regno_regclass[r] = FLOAT_REGS;
2966 for (r = 64; HARD_REGISTER_NUM_P (r); ++r)
2967 rs6000_regno_regclass[r] = NO_REGS;
2969 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2970 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2972 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2973 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2974 rs6000_regno_regclass[r] = CR_REGS;
2976 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2977 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2978 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
2979 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2980 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2981 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2982 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2984 /* Precalculate register class to simpler reload register class. We don't
2985 need all of the register classes that are combinations of different
2986 classes, just the simple ones that have constraint letters. */
2987 for (c = 0; c < N_REG_CLASSES; c++)
2988 reg_class_to_reg_type[c] = NO_REG_TYPE;
2990 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
2991 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
2992 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
2993 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
2994 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
2995 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
2996 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
2997 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
2998 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
2999 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3003 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3004 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3008 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3009 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3012 /* Precalculate the valid memory formats as well as the vector information,
3013 this must be set up before the rs6000_hard_regno_nregs_internal calls
3015 gcc_assert ((int)VECTOR_NONE == 0);
3016 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3017 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_mem));
3019 gcc_assert ((int)CODE_FOR_nothing == 0);
3020 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3022 gcc_assert ((int)NO_REGS == 0);
3023 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3025 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3026 believes it can use native alignment or still uses 128-bit alignment. */
3027 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3038 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3039 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3040 if (TARGET_FLOAT128_TYPE)
3042 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3043 rs6000_vector_align[KFmode] = 128;
3045 if (FLOAT128_IEEE_P (TFmode))
3047 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3048 rs6000_vector_align[TFmode] = 128;
3052 /* V2DF mode, VSX only. */
3055 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3056 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3057 rs6000_vector_align[V2DFmode] = align64;
3060 /* V4SF mode, either VSX or Altivec. */
3063 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3064 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3065 rs6000_vector_align[V4SFmode] = align32;
3067 else if (TARGET_ALTIVEC)
3069 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3070 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3071 rs6000_vector_align[V4SFmode] = align32;
3074 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3078 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3079 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3080 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3081 rs6000_vector_align[V4SImode] = align32;
3082 rs6000_vector_align[V8HImode] = align32;
3083 rs6000_vector_align[V16QImode] = align32;
3087 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3088 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3089 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3093 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3094 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3095 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3099 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3100 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3103 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3104 rs6000_vector_unit[V2DImode]
3105 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3106 rs6000_vector_align[V2DImode] = align64;
3108 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3109 rs6000_vector_unit[V1TImode]
3110 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3111 rs6000_vector_align[V1TImode] = 128;
3114 /* DFmode, see if we want to use the VSX unit. Memory is handled
3115 differently, so don't set rs6000_vector_mem. */
3118 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3119 rs6000_vector_align[DFmode] = 64;
3122 /* SFmode, see if we want to use the VSX unit. */
3123 if (TARGET_P8_VECTOR)
3125 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3126 rs6000_vector_align[SFmode] = 32;
3129 /* Allow TImode in VSX register and set the VSX memory macros. */
3132 rs6000_vector_mem[TImode] = VECTOR_VSX;
3133 rs6000_vector_align[TImode] = align64;
3136 /* Register class constraints for the constraints that depend on compile
3137 switches. When the VSX code was added, different constraints were added
3138 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3139 of the VSX registers are used. The register classes for scalar floating
3140 point types is set, based on whether we allow that type into the upper
3141 (Altivec) registers. GCC has register classes to target the Altivec
3142 registers for load/store operations, to select using a VSX memory
3143 operation instead of the traditional floating point operation. The
3146 d - Register class to use with traditional DFmode instructions.
3147 f - Register class to use with traditional SFmode instructions.
3148 v - Altivec register.
3149 wa - Any VSX register.
3150 wc - Reserved to represent individual CR bits (used in LLVM).
3151 wd - Preferred register class for V2DFmode.
3152 wf - Preferred register class for V4SFmode.
3153 wg - Float register for power6x move insns.
3154 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3155 wn - always NO_REGS.
3156 wr - GPR if 64-bit mode is permitted.
3157 ws - Register class to do ISA 2.06 DF operations.
3158 wt - VSX register for TImode in VSX registers.
3159 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3160 ww - Register class to do SF conversions in with VSX operations.
3161 wx - Float register if we can do 32-bit int stores. */
3163 if (TARGET_HARD_FLOAT)
3165 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3166 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3171 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3172 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3173 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3174 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3175 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3176 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3177 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3180 /* Add conditional constraints based on various options, to allow us to
3181 collapse multiple insn patterns. */
3183 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3185 if (TARGET_MFPGPR) /* DFmode */
3186 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3188 if (TARGET_POWERPC64)
3190 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3191 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3194 if (TARGET_P8_VECTOR) /* SFmode */
3195 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3196 else if (TARGET_VSX)
3197 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3200 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3202 if (TARGET_FLOAT128_TYPE)
3204 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3205 if (FLOAT128_IEEE_P (TFmode))
3206 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3209 /* Support for new direct moves (ISA 3.0 + 64bit). */
3210 if (TARGET_DIRECT_MOVE_128)
3211 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3213 /* Set up the reload helper and direct move functions. */
3214 if (TARGET_VSX || TARGET_ALTIVEC)
3218 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3219 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3220 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3221 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3222 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3223 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3224 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3225 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3226 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3227 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3228 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3229 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3230 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3231 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3232 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3233 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3234 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3235 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3236 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3237 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3239 if (FLOAT128_VECTOR_P (KFmode))
3241 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3242 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3245 if (FLOAT128_VECTOR_P (TFmode))
3247 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3248 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3251 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3253 if (TARGET_NO_SDMODE_STACK)
3255 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3256 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3261 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3262 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3265 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3267 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3268 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3269 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3270 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3271 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3272 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3273 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3274 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3275 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3277 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3278 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3279 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3280 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3281 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3282 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3283 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3284 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3285 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3287 if (FLOAT128_VECTOR_P (KFmode))
3289 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3290 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3293 if (FLOAT128_VECTOR_P (TFmode))
3295 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3296 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3302 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3303 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3304 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3305 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3306 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3307 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3308 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3309 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3310 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3311 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3312 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3313 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3314 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3315 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3316 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3317 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3318 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3319 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3320 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3321 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3323 if (FLOAT128_VECTOR_P (KFmode))
3325 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3326 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3329 if (FLOAT128_IEEE_P (TFmode))
3331 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3332 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3335 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3337 if (TARGET_NO_SDMODE_STACK)
3339 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3340 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3345 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3346 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3349 if (TARGET_DIRECT_MOVE)
3351 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3352 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3353 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3357 reg_addr[DFmode].scalar_in_vmx_p = true;
3358 reg_addr[DImode].scalar_in_vmx_p = true;
3360 if (TARGET_P8_VECTOR)
3362 reg_addr[SFmode].scalar_in_vmx_p = true;
3363 reg_addr[SImode].scalar_in_vmx_p = true;
3365 if (TARGET_P9_VECTOR)
3367 reg_addr[HImode].scalar_in_vmx_p = true;
3368 reg_addr[QImode].scalar_in_vmx_p = true;
3373 /* Precalculate HARD_REGNO_NREGS. */
3374 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3375 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3376 rs6000_hard_regno_nregs[m][r]
3377 = rs6000_hard_regno_nregs_internal (r, (machine_mode) m);
3379 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3380 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3381 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3382 rs6000_hard_regno_mode_ok_p[m][r]
3383 = rs6000_hard_regno_mode_ok_uncached (r, (machine_mode) m);
3385 /* Precalculate CLASS_MAX_NREGS sizes. */
3386 for (c = 0; c < LIM_REG_CLASSES; ++c)
3390 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3391 reg_size = UNITS_PER_VSX_WORD;
3393 else if (c == ALTIVEC_REGS)
3394 reg_size = UNITS_PER_ALTIVEC_WORD;
3396 else if (c == FLOAT_REGS)
3397 reg_size = UNITS_PER_FP_WORD;
3400 reg_size = UNITS_PER_WORD;
3402 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3404 machine_mode m2 = (machine_mode)m;
3405 int reg_size2 = reg_size;
3407 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3409 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3410 reg_size2 = UNITS_PER_FP_WORD;
3412 rs6000_class_max_nregs[m][c]
3413 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3417 /* Calculate which modes to automatically generate code to use a the
3418 reciprocal divide and square root instructions. In the future, possibly
3419 automatically generate the instructions even if the user did not specify
3420 -mrecip. The older machines double precision reciprocal sqrt estimate is
3421 not accurate enough. */
3422 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3424 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3426 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3427 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3428 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3429 if (VECTOR_UNIT_VSX_P (V2DFmode))
3430 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3432 if (TARGET_FRSQRTES)
3433 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3435 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3436 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3437 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3438 if (VECTOR_UNIT_VSX_P (V2DFmode))
3439 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3441 if (rs6000_recip_control)
3443 if (!flag_finite_math_only)
3444 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3446 if (flag_trapping_math)
3447 warning (0, "%qs requires %qs or %qs", "-mrecip",
3448 "-fno-trapping-math", "-ffast-math");
3449 if (!flag_reciprocal_math)
3450 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3452 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3454 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3455 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3456 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3458 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3459 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3460 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3462 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3463 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3464 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3466 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3467 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3468 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3470 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3471 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3472 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3474 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3475 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3476 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3478 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3479 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3480 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3482 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3483 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3484 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3488 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3489 legitimate address support to figure out the appropriate addressing to
3491 rs6000_setup_reg_addr_masks ();
3493 if (global_init_p || TARGET_DEBUG_TARGET)
3495 if (TARGET_DEBUG_REG)
3496 rs6000_debug_reg_global ();
3498 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3500 "SImode variable mult cost = %d\n"
3501 "SImode constant mult cost = %d\n"
3502 "SImode short constant mult cost = %d\n"
3503 "DImode multipliciation cost = %d\n"
3504 "SImode division cost = %d\n"
3505 "DImode division cost = %d\n"
3506 "Simple fp operation cost = %d\n"
3507 "DFmode multiplication cost = %d\n"
3508 "SFmode division cost = %d\n"
3509 "DFmode division cost = %d\n"
3510 "cache line size = %d\n"
3511 "l1 cache size = %d\n"
3512 "l2 cache size = %d\n"
3513 "simultaneous prefetches = %d\n"
3516 rs6000_cost->mulsi_const,
3517 rs6000_cost->mulsi_const9,
3525 rs6000_cost->cache_line_size,
3526 rs6000_cost->l1_cache_size,
3527 rs6000_cost->l2_cache_size,
3528 rs6000_cost->simultaneous_prefetches);
3533 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3536 darwin_rs6000_override_options (void)
3538 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3540 rs6000_altivec_abi = 1;
3541 TARGET_ALTIVEC_VRSAVE = 1;
3542 rs6000_current_abi = ABI_DARWIN;
3544 if (DEFAULT_ABI == ABI_DARWIN
3546 darwin_one_byte_bool = 1;
3548 if (TARGET_64BIT && ! TARGET_POWERPC64)
3550 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3551 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3555 rs6000_default_long_calls = 1;
3556 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3559 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3561 if (!flag_mkernel && !flag_apple_kext
3563 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3564 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3566 /* Unless the user (not the configurer) has explicitly overridden
3567 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3568 G4 unless targeting the kernel. */
3571 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3572 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3573 && ! global_options_set.x_rs6000_cpu_index)
3575 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3580 /* If not otherwise specified by a target, make 'long double' equivalent to
3583 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3584 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3587 /* Return the builtin mask of the various options used that could affect which
3588 builtins were used. In the past we used target_flags, but we've run out of
3589 bits, and some options are no longer in target_flags. */
3592 rs6000_builtin_mask_calculate (void)
3594 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3595 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3596 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3597 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3598 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3599 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3600 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3601 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3602 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3603 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3604 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3605 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3606 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3607 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3608 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3609 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3610 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3611 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3612 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3613 | ((TARGET_LONG_DOUBLE_128
3614 && TARGET_HARD_FLOAT
3615 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3616 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3617 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3620 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3621 to clobber the XER[CA] bit because clobbering that bit without telling
3622 the compiler worked just fine with versions of GCC before GCC 5, and
3623 breaking a lot of older code in ways that are hard to track down is
3624 not such a great idea. */
3627 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3628 vec<const char *> &/*constraints*/,
3629 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3631 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3632 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3636 /* Override command line options.
3638 Combine build-specific configuration information with options
3639 specified on the command line to set various state variables which
3640 influence code generation, optimization, and expansion of built-in
3641 functions. Assure that command-line configuration preferences are
3642 compatible with each other and with the build configuration; issue
3643 warnings while adjusting configuration or error messages while
3644 rejecting configuration.
3646 Upon entry to this function:
3648 This function is called once at the beginning of
3649 compilation, and then again at the start and end of compiling
3650 each section of code that has a different configuration, as
3651 indicated, for example, by adding the
3653 __attribute__((__target__("cpu=power9")))
3655 qualifier to a function definition or, for example, by bracketing
3658 #pragma GCC target("altivec")
3662 #pragma GCC reset_options
3664 directives. Parameter global_init_p is true for the initial
3665 invocation, which initializes global variables, and false for all
3666 subsequent invocations.
3669 Various global state information is assumed to be valid. This
3670 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3671 default CPU specified at build configure time, TARGET_DEFAULT,
3672 representing the default set of option flags for the default
3673 target, and global_options_set.x_rs6000_isa_flags, representing
3674 which options were requested on the command line.
3676 Upon return from this function:
3678 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3679 was set by name on the command line. Additionally, if certain
3680 attributes are automatically enabled or disabled by this function
3681 in order to assure compatibility between options and
3682 configuration, the flags associated with those attributes are
3683 also set. By setting these "explicit bits", we avoid the risk
3684 that other code might accidentally overwrite these particular
3685 attributes with "default values".
3687 The various bits of rs6000_isa_flags are set to indicate the
3688 target options that have been selected for the most current
3689 compilation efforts. This has the effect of also turning on the
3690 associated TARGET_XXX values since these are macros which are
3691 generally defined to test the corresponding bit of the
3692 rs6000_isa_flags variable.
3694 The variable rs6000_builtin_mask is set to represent the target
3695 options for the most current compilation efforts, consistent with
3696 the current contents of rs6000_isa_flags. This variable controls
3697 expansion of built-in functions.
3699 Various other global variables and fields of global structures
3700 (over 50 in all) are initialized to reflect the desired options
3701 for the most current compilation efforts. */
3704 rs6000_option_override_internal (bool global_init_p)
3708 HOST_WIDE_INT set_masks;
3709 HOST_WIDE_INT ignore_masks;
3712 struct cl_target_option *main_target_opt
3713 = ((global_init_p || target_option_default_node == NULL)
3714 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
3716 /* Print defaults. */
3717 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
3718 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
3720 /* Remember the explicit arguments. */
3722 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
3724 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3725 library functions, so warn about it. The flag may be useful for
3726 performance studies from time to time though, so don't disable it
3728 if (global_options_set.x_rs6000_alignment_flags
3729 && rs6000_alignment_flags == MASK_ALIGN_POWER
3730 && DEFAULT_ABI == ABI_DARWIN
3732 warning (0, "%qs is not supported for 64-bit Darwin;"
3733 " it is incompatible with the installed C and C++ libraries",
3736 /* Numerous experiment shows that IRA based loop pressure
3737 calculation works better for RTL loop invariant motion on targets
3738 with enough (>= 32) registers. It is an expensive optimization.
3739 So it is on only for peak performance. */
3740 if (optimize >= 3 && global_init_p
3741 && !global_options_set.x_flag_ira_loop_pressure)
3742 flag_ira_loop_pressure = 1;
3744 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3745 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3746 options were already specified. */
3747 if (flag_sanitize & SANITIZE_USER_ADDRESS
3748 && !global_options_set.x_flag_asynchronous_unwind_tables)
3749 flag_asynchronous_unwind_tables = 1;
3751 /* Set the pointer size. */
3754 rs6000_pmode = DImode;
3755 rs6000_pointer_size = 64;
3759 rs6000_pmode = SImode;
3760 rs6000_pointer_size = 32;
3763 /* Some OSs don't support saving the high part of 64-bit registers on context
3764 switch. Other OSs don't support saving Altivec registers. On those OSs,
3765 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3766 if the user wants either, the user must explicitly specify them and we
3767 won't interfere with the user's specification. */
3769 set_masks = POWERPC_MASKS;
3770 #ifdef OS_MISSING_POWERPC64
3771 if (OS_MISSING_POWERPC64)
3772 set_masks &= ~OPTION_MASK_POWERPC64;
3774 #ifdef OS_MISSING_ALTIVEC
3775 if (OS_MISSING_ALTIVEC)
3776 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
3777 | OTHER_VSX_VECTOR_MASKS);
3780 /* Don't override by the processor default if given explicitly. */
3781 set_masks &= ~rs6000_isa_flags_explicit;
3783 if (global_init_p && rs6000_dejagnu_cpu_index >= 0)
3784 rs6000_cpu_index = rs6000_dejagnu_cpu_index;
3786 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3787 the cpu in a target attribute or pragma, but did not specify a tuning
3788 option, use the cpu for the tuning option rather than the option specified
3789 with -mtune on the command line. Process a '--with-cpu' configuration
3790 request as an implicit --cpu. */
3791 if (rs6000_cpu_index >= 0)
3792 cpu_index = rs6000_cpu_index;
3793 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
3794 cpu_index = main_target_opt->x_rs6000_cpu_index;
3795 else if (OPTION_TARGET_CPU_DEFAULT)
3796 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
3798 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3799 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3800 with those from the cpu, except for options that were explicitly set. If
3801 we don't have a cpu, do not override the target bits set in
3805 rs6000_cpu_index = cpu_index;
3806 rs6000_isa_flags &= ~set_masks;
3807 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3812 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3813 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3814 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3815 to using rs6000_isa_flags, we need to do the initialization here.
3817 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3818 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3819 HOST_WIDE_INT flags;
3821 flags = TARGET_DEFAULT;
3824 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3825 const char *default_cpu = (!TARGET_POWERPC64
3830 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
3831 flags = processor_target_table[default_cpu_index].target_enable;
3833 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
3836 if (rs6000_tune_index >= 0)
3837 tune_index = rs6000_tune_index;
3838 else if (cpu_index >= 0)
3839 rs6000_tune_index = tune_index = cpu_index;
3843 enum processor_type tune_proc
3844 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
3847 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
3848 if (processor_target_table[i].processor == tune_proc)
3856 rs6000_cpu = processor_target_table[cpu_index].processor;
3858 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
3860 gcc_assert (tune_index >= 0);
3861 rs6000_tune = processor_target_table[tune_index].processor;
3863 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
3864 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
3865 || rs6000_cpu == PROCESSOR_PPCE5500)
3868 error ("AltiVec not supported in this target");
3871 /* If we are optimizing big endian systems for space, use the load/store
3872 multiple instructions. */
3873 if (BYTES_BIG_ENDIAN && optimize_size)
3874 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
3876 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3877 because the hardware doesn't support the instructions used in little
3878 endian mode, and causes an alignment trap. The 750 does not cause an
3879 alignment trap (except when the target is unaligned). */
3881 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
3883 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
3884 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
3885 warning (0, "%qs is not supported on little endian systems",
3889 /* If little-endian, default to -mstrict-align on older processors.
3890 Testing for htm matches power8 and later. */
3891 if (!BYTES_BIG_ENDIAN
3892 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
3893 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
3895 if (!rs6000_fold_gimple)
3897 "gimple folding of rs6000 builtins has been disabled.\n");
3899 /* Add some warnings for VSX. */
3902 const char *msg = NULL;
3903 if (!TARGET_HARD_FLOAT)
3905 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3906 msg = N_("%<-mvsx%> requires hardware floating point");
3909 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3910 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3913 else if (TARGET_AVOID_XFORM > 0)
3914 msg = N_("%<-mvsx%> needs indexed addressing");
3915 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
3916 & OPTION_MASK_ALTIVEC))
3918 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3919 msg = N_("%<-mvsx%> and %<-mno-altivec%> are incompatible");
3921 msg = N_("%<-mno-altivec%> disables vsx");
3927 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3928 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3932 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3933 the -mcpu setting to enable options that conflict. */
3934 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
3935 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
3936 | OPTION_MASK_ALTIVEC
3937 | OPTION_MASK_VSX)) != 0)
3938 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
3939 | OPTION_MASK_DIRECT_MOVE)
3940 & ~rs6000_isa_flags_explicit);
3942 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3943 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
3945 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
3946 off all of the options that depend on those flags. */
3947 ignore_masks = rs6000_disable_incompatible_switches ();
3949 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3950 unless the user explicitly used the -mno-<option> to disable the code. */
3951 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
3952 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3953 else if (TARGET_P9_MINMAX)
3957 if (cpu_index == PROCESSOR_POWER9)
3959 /* legacy behavior: allow -mcpu=power9 with certain
3960 capabilities explicitly disabled. */
3961 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3964 error ("power9 target option is incompatible with %<%s=<xxx>%> "
3965 "for <xxx> less than power9", "-mcpu");
3967 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
3968 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
3969 & rs6000_isa_flags_explicit))
3970 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
3971 were explicitly cleared. */
3972 error ("%qs incompatible with explicitly disabled options",
3975 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
3977 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
3978 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
3979 else if (TARGET_VSX)
3980 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
3981 else if (TARGET_POPCNTD)
3982 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
3983 else if (TARGET_DFP)
3984 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
3985 else if (TARGET_CMPB)
3986 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
3987 else if (TARGET_FPRND)
3988 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
3989 else if (TARGET_POPCNTB)
3990 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
3991 else if (TARGET_ALTIVEC)
3992 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
3994 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
3996 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
3997 error ("%qs requires %qs", "-mcrypto", "-maltivec");
3998 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4001 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4003 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4004 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4005 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4008 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4010 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4011 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4012 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4015 if (TARGET_P8_VECTOR && !TARGET_VSX)
4017 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4018 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4019 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4020 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4022 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4023 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4024 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4028 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4030 rs6000_isa_flags |= OPTION_MASK_VSX;
4031 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4035 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4037 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4038 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4039 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4042 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4043 silently turn off quad memory mode. */
4044 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4046 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4047 warning (0, N_("%<-mquad-memory%> requires 64-bit mode"));
4049 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4050 warning (0, N_("%<-mquad-memory-atomic%> requires 64-bit mode"));
4052 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4053 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4056 /* Non-atomic quad memory load/store are disabled for little endian, since
4057 the words are reversed, but atomic operations can still be done by
4058 swapping the words. */
4059 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4061 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4062 warning (0, N_("%<-mquad-memory%> is not available in little endian "
4065 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4068 /* Assume if the user asked for normal quad memory instructions, they want
4069 the atomic versions as well, unless they explicity told us not to use quad
4070 word atomic instructions. */
4071 if (TARGET_QUAD_MEMORY
4072 && !TARGET_QUAD_MEMORY_ATOMIC
4073 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4074 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4076 /* If we can shrink-wrap the TOC register save separately, then use
4077 -msave-toc-indirect unless explicitly disabled. */
4078 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4079 && flag_shrink_wrap_separate
4080 && optimize_function_for_speed_p (cfun))
4081 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4083 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4084 generating power8 instructions. Power9 does not optimize power8 fusion
4086 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4088 if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
4089 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4091 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4094 /* Setting additional fusion flags turns on base fusion. */
4095 if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
4097 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4099 if (TARGET_P8_FUSION_SIGN)
4100 error ("%qs requires %qs", "-mpower8-fusion-sign",
4103 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4106 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4109 /* Power8 does not fuse sign extended loads with the addis. If we are
4110 optimizing at high levels for speed, convert a sign extended load into a
4111 zero extending load, and an explicit sign extension. */
4112 if (TARGET_P8_FUSION
4113 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4114 && optimize_function_for_speed_p (cfun)
4116 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4118 /* ISA 3.0 vector instructions include ISA 2.07. */
4119 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4121 /* We prefer to not mention undocumented options in
4122 error messages. However, if users have managed to select
4123 power9-vector without selecting power8-vector, they
4124 already know about undocumented flags. */
4125 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4126 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4127 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4128 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4130 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4131 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4132 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4136 /* OPTION_MASK_P9_VECTOR is explicit and
4137 OPTION_MASK_P8_VECTOR is not explicit. */
4138 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4139 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4143 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4144 support. If we only have ISA 2.06 support, and the user did not specify
4145 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4146 but we don't enable the full vectorization support */
4147 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4148 TARGET_ALLOW_MOVMISALIGN = 1;
4150 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4152 if (TARGET_ALLOW_MOVMISALIGN > 0
4153 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4154 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4156 TARGET_ALLOW_MOVMISALIGN = 0;
4159 /* Determine when unaligned vector accesses are permitted, and when
4160 they are preferred over masked Altivec loads. Note that if
4161 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4162 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4164 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4168 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4169 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4171 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4174 else if (!TARGET_ALLOW_MOVMISALIGN)
4176 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4177 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4178 "-mallow-movmisalign");
4180 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4184 /* Use long double size to select the appropriate long double. We use
4185 TYPE_PRECISION to differentiate the 3 different long double types. We map
4186 128 into the precision used for TFmode. */
4187 int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
4189 : FLOAT_PRECISION_TFmode);
4191 /* Set long double size before the IEEE 128-bit tests. */
4192 if (!global_options_set.x_rs6000_long_double_type_size)
4194 if (main_target_opt != NULL
4195 && (main_target_opt->x_rs6000_long_double_type_size
4196 != default_long_double_size))
4197 error ("target attribute or pragma changes %<long double%> size");
4199 rs6000_long_double_type_size = default_long_double_size;
4201 else if (rs6000_long_double_type_size == 128)
4202 rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
4203 else if (global_options_set.x_rs6000_ieeequad)
4205 if (global_options.x_rs6000_ieeequad)
4206 error ("%qs requires %qs", "-mabi=ieeelongdouble", "-mlong-double-128");
4208 error ("%qs requires %qs", "-mabi=ibmlongdouble", "-mlong-double-128");
4211 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4212 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4213 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4214 those systems will not pick up this default. Warn if the user changes the
4215 default unless -Wno-psabi. */
4216 if (!global_options_set.x_rs6000_ieeequad)
4217 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4221 if (global_options.x_rs6000_ieeequad
4222 && (!TARGET_POPCNTD || !TARGET_VSX))
4223 error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
4225 if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4227 static bool warned_change_long_double;
4228 if (!warned_change_long_double)
4230 warned_change_long_double = true;
4231 if (TARGET_IEEEQUAD)
4232 warning (OPT_Wpsabi, "Using IEEE extended precision "
4235 warning (OPT_Wpsabi, "Using IBM extended precision "
4241 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4242 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4243 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4244 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4245 the keyword as well as the type. */
4246 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4248 /* IEEE 128-bit floating point requires VSX support. */
4249 if (TARGET_FLOAT128_KEYWORD)
4253 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4254 error ("%qs requires VSX support", "%<-mfloat128%>");
4256 TARGET_FLOAT128_TYPE = 0;
4257 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4258 | OPTION_MASK_FLOAT128_HW);
4260 else if (!TARGET_FLOAT128_TYPE)
4262 TARGET_FLOAT128_TYPE = 1;
4263 warning (0, "The %<-mfloat128%> option may not be fully supported");
4267 /* Enable the __float128 keyword under Linux by default. */
4268 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4269 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4270 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4272 /* If we have are supporting the float128 type and full ISA 3.0 support,
4273 enable -mfloat128-hardware by default. However, don't enable the
4274 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4275 because sometimes the compiler wants to put things in an integer
4276 container, and if we don't have __int128 support, it is impossible. */
4277 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4278 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4279 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4280 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4282 if (TARGET_FLOAT128_HW
4283 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4285 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4286 error ("%qs requires full ISA 3.0 support", "%<-mfloat128-hardware%>");
4288 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4291 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4293 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4294 error ("%qs requires %qs", "%<-mfloat128-hardware%>", "-m64");
4296 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4299 /* Print the options after updating the defaults. */
4300 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4301 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4303 /* E500mc does "better" if we inline more aggressively. Respect the
4304 user's opinion, though. */
4305 if (rs6000_block_move_inline_limit == 0
4306 && (rs6000_tune == PROCESSOR_PPCE500MC
4307 || rs6000_tune == PROCESSOR_PPCE500MC64
4308 || rs6000_tune == PROCESSOR_PPCE5500
4309 || rs6000_tune == PROCESSOR_PPCE6500))
4310 rs6000_block_move_inline_limit = 128;
4312 /* store_one_arg depends on expand_block_move to handle at least the
4313 size of reg_parm_stack_space. */
4314 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4315 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4319 /* If the appropriate debug option is enabled, replace the target hooks
4320 with debug versions that call the real version and then prints
4321 debugging information. */
4322 if (TARGET_DEBUG_COST)
4324 targetm.rtx_costs = rs6000_debug_rtx_costs;
4325 targetm.address_cost = rs6000_debug_address_cost;
4326 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4329 if (TARGET_DEBUG_ADDR)
4331 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4332 targetm.legitimize_address = rs6000_debug_legitimize_address;
4333 rs6000_secondary_reload_class_ptr
4334 = rs6000_debug_secondary_reload_class;
4335 targetm.secondary_memory_needed
4336 = rs6000_debug_secondary_memory_needed;
4337 targetm.can_change_mode_class
4338 = rs6000_debug_can_change_mode_class;
4339 rs6000_preferred_reload_class_ptr
4340 = rs6000_debug_preferred_reload_class;
4341 rs6000_mode_dependent_address_ptr
4342 = rs6000_debug_mode_dependent_address;
4345 if (rs6000_veclibabi_name)
4347 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4348 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4351 error ("unknown vectorization library ABI type (%qs) for "
4352 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4358 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4359 target attribute or pragma which automatically enables both options,
4360 unless the altivec ABI was set. This is set by default for 64-bit, but
4362 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4364 TARGET_FLOAT128_TYPE = 0;
4365 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4366 | OPTION_MASK_FLOAT128_KEYWORD)
4367 & ~rs6000_isa_flags_explicit);
4370 /* Enable Altivec ABI for AIX -maltivec. */
4371 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4373 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4374 error ("target attribute or pragma changes AltiVec ABI");
4376 rs6000_altivec_abi = 1;
4379 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4380 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4381 be explicitly overridden in either case. */
4384 if (!global_options_set.x_rs6000_altivec_abi
4385 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4387 if (main_target_opt != NULL &&
4388 !main_target_opt->x_rs6000_altivec_abi)
4389 error ("target attribute or pragma changes AltiVec ABI");
4391 rs6000_altivec_abi = 1;
4395 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4396 So far, the only darwin64 targets are also MACH-O. */
4398 && DEFAULT_ABI == ABI_DARWIN
4401 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4402 error ("target attribute or pragma changes darwin64 ABI");
4405 rs6000_darwin64_abi = 1;
4406 /* Default to natural alignment, for better performance. */
4407 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4411 /* Place FP constants in the constant pool instead of TOC
4412 if section anchors enabled. */
4413 if (flag_section_anchors
4414 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4415 TARGET_NO_FP_IN_TOC = 1;
4417 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4418 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4420 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4421 SUBTARGET_OVERRIDE_OPTIONS;
4423 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4424 SUBSUBTARGET_OVERRIDE_OPTIONS;
4426 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4427 SUB3TARGET_OVERRIDE_OPTIONS;
4430 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4431 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4433 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4434 && rs6000_tune != PROCESSOR_POWER5
4435 && rs6000_tune != PROCESSOR_POWER6
4436 && rs6000_tune != PROCESSOR_POWER7
4437 && rs6000_tune != PROCESSOR_POWER8
4438 && rs6000_tune != PROCESSOR_POWER9
4439 && rs6000_tune != PROCESSOR_PPCA2
4440 && rs6000_tune != PROCESSOR_CELL
4441 && rs6000_tune != PROCESSOR_PPC476);
4442 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4443 || rs6000_tune == PROCESSOR_POWER5
4444 || rs6000_tune == PROCESSOR_POWER7
4445 || rs6000_tune == PROCESSOR_POWER8);
4446 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4447 || rs6000_tune == PROCESSOR_POWER5
4448 || rs6000_tune == PROCESSOR_POWER6
4449 || rs6000_tune == PROCESSOR_POWER7
4450 || rs6000_tune == PROCESSOR_POWER8
4451 || rs6000_tune == PROCESSOR_POWER9
4452 || rs6000_tune == PROCESSOR_PPCE500MC
4453 || rs6000_tune == PROCESSOR_PPCE500MC64
4454 || rs6000_tune == PROCESSOR_PPCE5500
4455 || rs6000_tune == PROCESSOR_PPCE6500);
4457 /* Allow debug switches to override the above settings. These are set to -1
4458 in rs6000.opt to indicate the user hasn't directly set the switch. */
4459 if (TARGET_ALWAYS_HINT >= 0)
4460 rs6000_always_hint = TARGET_ALWAYS_HINT;
4462 if (TARGET_SCHED_GROUPS >= 0)
4463 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4465 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4466 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4468 rs6000_sched_restricted_insns_priority
4469 = (rs6000_sched_groups ? 1 : 0);
4471 /* Handle -msched-costly-dep option. */
4472 rs6000_sched_costly_dep
4473 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4475 if (rs6000_sched_costly_dep_str)
4477 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4478 rs6000_sched_costly_dep = no_dep_costly;
4479 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4480 rs6000_sched_costly_dep = all_deps_costly;
4481 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4482 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4483 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4484 rs6000_sched_costly_dep = store_to_load_dep_costly;
4486 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4487 atoi (rs6000_sched_costly_dep_str));
4490 /* Handle -minsert-sched-nops option. */
4491 rs6000_sched_insert_nops
4492 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4494 if (rs6000_sched_insert_nops_str)
4496 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4497 rs6000_sched_insert_nops = sched_finish_none;
4498 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4499 rs6000_sched_insert_nops = sched_finish_pad_groups;
4500 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4501 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4503 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4504 atoi (rs6000_sched_insert_nops_str));
4507 /* Handle stack protector */
4508 if (!global_options_set.x_rs6000_stack_protector_guard)
4509 #ifdef TARGET_THREAD_SSP_OFFSET
4510 rs6000_stack_protector_guard = SSP_TLS;
4512 rs6000_stack_protector_guard = SSP_GLOBAL;
4515 #ifdef TARGET_THREAD_SSP_OFFSET
4516 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4517 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4520 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4523 const char *str = rs6000_stack_protector_guard_offset_str;
4526 long offset = strtol (str, &endp, 0);
4527 if (!*str || *endp || errno)
4528 error ("%qs is not a valid number in %qs", str,
4529 "-mstack-protector-guard-offset=");
4531 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4532 || (TARGET_64BIT && (offset & 3)))
4533 error ("%qs is not a valid offset in %qs", str,
4534 "-mstack-protector-guard-offset=");
4536 rs6000_stack_protector_guard_offset = offset;
4539 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4541 const char *str = rs6000_stack_protector_guard_reg_str;
4542 int reg = decode_reg_name (str);
4544 if (!IN_RANGE (reg, 1, 31))
4545 error ("%qs is not a valid base register in %qs", str,
4546 "-mstack-protector-guard-reg=");
4548 rs6000_stack_protector_guard_reg = reg;
4551 if (rs6000_stack_protector_guard == SSP_TLS
4552 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4553 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4557 #ifdef TARGET_REGNAMES
4558 /* If the user desires alternate register names, copy in the
4559 alternate names now. */
4560 if (TARGET_REGNAMES)
4561 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4564 /* Set aix_struct_return last, after the ABI is determined.
4565 If -maix-struct-return or -msvr4-struct-return was explicitly
4566 used, don't override with the ABI default. */
4567 if (!global_options_set.x_aix_struct_return)
4568 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4571 /* IBM XL compiler defaults to unsigned bitfields. */
4572 if (TARGET_XL_COMPAT)
4573 flag_signed_bitfields = 0;
4576 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4577 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4579 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4581 /* We can only guarantee the availability of DI pseudo-ops when
4582 assembling for 64-bit targets. */
4585 targetm.asm_out.aligned_op.di = NULL;
4586 targetm.asm_out.unaligned_op.di = NULL;
4590 /* Set branch target alignment, if not optimizing for size. */
4593 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4594 aligned 8byte to avoid misprediction by the branch predictor. */
4595 if (rs6000_tune == PROCESSOR_TITAN
4596 || rs6000_tune == PROCESSOR_CELL)
4598 if (flag_align_functions && !str_align_functions)
4599 str_align_functions = "8";
4600 if (flag_align_jumps && !str_align_jumps)
4601 str_align_jumps = "8";
4602 if (flag_align_loops && !str_align_loops)
4603 str_align_loops = "8";
4605 if (rs6000_align_branch_targets)
4607 if (flag_align_functions && !str_align_functions)
4608 str_align_functions = "16";
4609 if (flag_align_jumps && !str_align_jumps)
4610 str_align_jumps = "16";
4611 if (flag_align_loops && !str_align_loops)
4613 can_override_loop_align = 1;
4614 str_align_loops = "16";
4618 if (flag_align_jumps && !str_align_jumps)
4619 str_align_jumps = "16";
4620 if (flag_align_loops && !str_align_loops)
4621 str_align_loops = "16";
4624 /* Arrange to save and restore machine status around nested functions. */
4625 init_machine_status = rs6000_init_machine_status;
4627 /* We should always be splitting complex arguments, but we can't break
4628 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4629 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4630 targetm.calls.split_complex_arg = NULL;
4632 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4633 if (DEFAULT_ABI == ABI_AIX)
4634 targetm.calls.custom_function_descriptors = 0;
4637 /* Initialize rs6000_cost with the appropriate target costs. */
4639 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4641 switch (rs6000_tune)
4643 case PROCESSOR_RS64A:
4644 rs6000_cost = &rs64a_cost;
4647 case PROCESSOR_MPCCORE:
4648 rs6000_cost = &mpccore_cost;
4651 case PROCESSOR_PPC403:
4652 rs6000_cost = &ppc403_cost;
4655 case PROCESSOR_PPC405:
4656 rs6000_cost = &ppc405_cost;
4659 case PROCESSOR_PPC440:
4660 rs6000_cost = &ppc440_cost;
4663 case PROCESSOR_PPC476:
4664 rs6000_cost = &ppc476_cost;
4667 case PROCESSOR_PPC601:
4668 rs6000_cost = &ppc601_cost;
4671 case PROCESSOR_PPC603:
4672 rs6000_cost = &ppc603_cost;
4675 case PROCESSOR_PPC604:
4676 rs6000_cost = &ppc604_cost;
4679 case PROCESSOR_PPC604e:
4680 rs6000_cost = &ppc604e_cost;
4683 case PROCESSOR_PPC620:
4684 rs6000_cost = &ppc620_cost;
4687 case PROCESSOR_PPC630:
4688 rs6000_cost = &ppc630_cost;
4691 case PROCESSOR_CELL:
4692 rs6000_cost = &ppccell_cost;
4695 case PROCESSOR_PPC750:
4696 case PROCESSOR_PPC7400:
4697 rs6000_cost = &ppc750_cost;
4700 case PROCESSOR_PPC7450:
4701 rs6000_cost = &ppc7450_cost;
4704 case PROCESSOR_PPC8540:
4705 case PROCESSOR_PPC8548:
4706 rs6000_cost = &ppc8540_cost;
4709 case PROCESSOR_PPCE300C2:
4710 case PROCESSOR_PPCE300C3:
4711 rs6000_cost = &ppce300c2c3_cost;
4714 case PROCESSOR_PPCE500MC:
4715 rs6000_cost = &ppce500mc_cost;
4718 case PROCESSOR_PPCE500MC64:
4719 rs6000_cost = &ppce500mc64_cost;
4722 case PROCESSOR_PPCE5500:
4723 rs6000_cost = &ppce5500_cost;
4726 case PROCESSOR_PPCE6500:
4727 rs6000_cost = &ppce6500_cost;
4730 case PROCESSOR_TITAN:
4731 rs6000_cost = &titan_cost;
4734 case PROCESSOR_POWER4:
4735 case PROCESSOR_POWER5:
4736 rs6000_cost = &power4_cost;
4739 case PROCESSOR_POWER6:
4740 rs6000_cost = &power6_cost;
4743 case PROCESSOR_POWER7:
4744 rs6000_cost = &power7_cost;
4747 case PROCESSOR_POWER8:
4748 rs6000_cost = &power8_cost;
4751 case PROCESSOR_POWER9:
4752 rs6000_cost = &power9_cost;
4755 case PROCESSOR_PPCA2:
4756 rs6000_cost = &ppca2_cost;
4765 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
4766 rs6000_cost->simultaneous_prefetches,
4767 global_options.x_param_values,
4768 global_options_set.x_param_values);
4769 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
4770 global_options.x_param_values,
4771 global_options_set.x_param_values);
4772 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
4773 rs6000_cost->cache_line_size,
4774 global_options.x_param_values,
4775 global_options_set.x_param_values);
4776 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
4777 global_options.x_param_values,
4778 global_options_set.x_param_values);
4780 /* Increase loop peeling limits based on performance analysis. */
4781 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
4782 global_options.x_param_values,
4783 global_options_set.x_param_values);
4784 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
4785 global_options.x_param_values,
4786 global_options_set.x_param_values);
4788 /* Use the 'model' -fsched-pressure algorithm by default. */
4789 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
4790 SCHED_PRESSURE_MODEL,
4791 global_options.x_param_values,
4792 global_options_set.x_param_values);
4794 /* If using typedef char *va_list, signal that
4795 __builtin_va_start (&ap, 0) can be optimized to
4796 ap = __builtin_next_arg (0). */
4797 if (DEFAULT_ABI != ABI_V4)
4798 targetm.expand_builtin_va_start = NULL;
4801 /* If not explicitly specified via option, decide whether to generate indexed
4802 load/store instructions. A value of -1 indicates that the
4803 initial value of this variable has not been overwritten. During
4804 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4805 if (TARGET_AVOID_XFORM == -1)
4806 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4807 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4808 need indexed accesses and the type used is the scalar type of the element
4809 being loaded or stored. */
4810 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
4811 && !TARGET_ALTIVEC);
4813 /* Set the -mrecip options. */
4814 if (rs6000_recip_name)
4816 char *p = ASTRDUP (rs6000_recip_name);
4818 unsigned int mask, i;
4821 while ((q = strtok (p, ",")) != NULL)
4832 if (!strcmp (q, "default"))
4833 mask = ((TARGET_RECIP_PRECISION)
4834 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
4837 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
4838 if (!strcmp (q, recip_options[i].string))
4840 mask = recip_options[i].mask;
4844 if (i == ARRAY_SIZE (recip_options))
4846 error ("unknown option for %<%s=%s%>", "-mrecip", q);
4854 rs6000_recip_control &= ~mask;
4856 rs6000_recip_control |= mask;
4860 /* Set the builtin mask of the various options used that could affect which
4861 builtins were used. In the past we used target_flags, but we've run out
4862 of bits, and some options are no longer in target_flags. */
4863 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
4864 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
4865 rs6000_print_builtin_options (stderr, 0, "builtin mask",
4866 rs6000_builtin_mask);
4868 /* Initialize all of the registers. */
4869 rs6000_init_hard_regno_mode_ok (global_init_p);
4871 /* Save the initial options in case the user does function specific options */
4873 target_option_default_node = target_option_current_node
4874 = build_target_option_node (&global_options);
4876 /* If not explicitly specified via option, decide whether to generate the
4877 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4878 if (TARGET_LINK_STACK == -1)
4879 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
4881 /* Deprecate use of -mno-speculate-indirect-jumps. */
4882 if (!rs6000_speculate_indirect_jumps)
4883 warning (0, "%qs is deprecated and not recommended in any circumstances",
4884 "-mno-speculate-indirect-jumps");
4889 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4890 define the target cpu type. */
4893 rs6000_option_override (void)
4895 (void) rs6000_option_override_internal (true);
4899 /* Implement targetm.vectorize.builtin_mask_for_load. */
4901 rs6000_builtin_mask_for_load (void)
4903 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4904 if ((TARGET_ALTIVEC && !TARGET_VSX)
4905 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
4906 return altivec_builtin_mask_for_load;
4911 /* Implement LOOP_ALIGN. */
4913 rs6000_loop_align (rtx label)
4918 /* Don't override loop alignment if -falign-loops was specified. */
4919 if (!can_override_loop_align)
4922 bb = BLOCK_FOR_INSN (label);
4923 ninsns = num_loop_insns(bb->loop_father);
4925 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4926 if (ninsns > 4 && ninsns <= 8
4927 && (rs6000_tune == PROCESSOR_POWER4
4928 || rs6000_tune == PROCESSOR_POWER5
4929 || rs6000_tune == PROCESSOR_POWER6
4930 || rs6000_tune == PROCESSOR_POWER7
4931 || rs6000_tune == PROCESSOR_POWER8))
4932 return align_flags (5);
4937 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4938 after applying N number of iterations. This routine does not determine
4939 how may iterations are required to reach desired alignment. */
4942 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
4949 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
4952 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
4962 /* Assuming that all other types are naturally aligned. CHECKME! */
4967 /* Return true if the vector misalignment factor is supported by the
4970 rs6000_builtin_support_vector_misalignment (machine_mode mode,
4977 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4980 /* Return if movmisalign pattern is not supported for this mode. */
4981 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
4984 if (misalignment == -1)
4986 /* Misalignment factor is unknown at compile time but we know
4987 it's word aligned. */
4988 if (rs6000_vector_alignment_reachable (type, is_packed))
4990 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
4992 if (element_size == 64 || element_size == 32)
4999 /* VSX supports word-aligned vector. */
5000 if (misalignment % 4 == 0)
5006 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5008 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5009 tree vectype, int misalign)
5014 switch (type_of_cost)
5024 case cond_branch_not_taken:
5033 case vec_promote_demote:
5039 case cond_branch_taken:
5042 case unaligned_load:
5043 case vector_gather_load:
5044 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5047 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5049 elements = TYPE_VECTOR_SUBPARTS (vectype);
5051 /* Double word aligned. */
5059 /* Double word aligned. */
5063 /* Unknown misalignment. */
5076 /* Misaligned loads are not supported. */
5081 case unaligned_store:
5082 case vector_scatter_store:
5083 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5086 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5088 elements = TYPE_VECTOR_SUBPARTS (vectype);
5090 /* Double word aligned. */
5098 /* Double word aligned. */
5102 /* Unknown misalignment. */
5115 /* Misaligned stores are not supported. */
5121 /* This is a rough approximation assuming non-constant elements
5122 constructed into a vector via element insertion. FIXME:
5123 vec_construct is not granular enough for uniformly good
5124 decisions. If the initialization is a splat, this is
5125 cheaper than we estimate. Improve this someday. */
5126 elem_type = TREE_TYPE (vectype);
5127 /* 32-bit vectors loaded into registers are stored as double
5128 precision, so we need 2 permutes, 2 converts, and 1 merge
5129 to construct a vector of short floats from them. */
5130 if (SCALAR_FLOAT_TYPE_P (elem_type)
5131 && TYPE_PRECISION (elem_type) == 32)
5133 /* On POWER9, integer vector types are built up in GPRs and then
5134 use a direct move (2 cycles). For POWER8 this is even worse,
5135 as we need two direct moves and a merge, and the direct moves
5137 else if (INTEGRAL_TYPE_P (elem_type))
5139 if (TARGET_P9_VECTOR)
5140 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5142 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5145 /* V2DFmode doesn't need a direct move. */
5153 /* Implement targetm.vectorize.preferred_simd_mode. */
5156 rs6000_preferred_simd_mode (scalar_mode mode)
5165 if (TARGET_ALTIVEC || TARGET_VSX)
5185 typedef struct _rs6000_cost_data
5187 struct loop *loop_info;
5191 /* Test for likely overcommitment of vector hardware resources. If a
5192 loop iteration is relatively large, and too large a percentage of
5193 instructions in the loop are vectorized, the cost model may not
5194 adequately reflect delays from unavailable vector resources.
5195 Penalize the loop body cost for this case. */
5198 rs6000_density_test (rs6000_cost_data *data)
5200 const int DENSITY_PCT_THRESHOLD = 85;
5201 const int DENSITY_SIZE_THRESHOLD = 70;
5202 const int DENSITY_PENALTY = 10;
5203 struct loop *loop = data->loop_info;
5204 basic_block *bbs = get_loop_body (loop);
5205 int nbbs = loop->num_nodes;
5206 loop_vec_info loop_vinfo = loop_vec_info_for_loop (data->loop_info);
5207 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5210 for (i = 0; i < nbbs; i++)
5212 basic_block bb = bbs[i];
5213 gimple_stmt_iterator gsi;
5215 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5217 gimple *stmt = gsi_stmt (gsi);
5218 stmt_vec_info stmt_info = loop_vinfo->lookup_stmt (stmt);
5220 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5221 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5227 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5229 if (density_pct > DENSITY_PCT_THRESHOLD
5230 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5232 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5233 if (dump_enabled_p ())
5234 dump_printf_loc (MSG_NOTE, vect_location,
5235 "density %d%%, cost %d exceeds threshold, penalizing "
5236 "loop body cost by %d%%", density_pct,
5237 vec_cost + not_vec_cost, DENSITY_PENALTY);
5241 /* Implement targetm.vectorize.init_cost. */
5243 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5244 instruction is needed by the vectorization. */
5245 static bool rs6000_vect_nonmem;
5248 rs6000_init_cost (struct loop *loop_info)
5250 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5251 data->loop_info = loop_info;
5252 data->cost[vect_prologue] = 0;
5253 data->cost[vect_body] = 0;
5254 data->cost[vect_epilogue] = 0;
5255 rs6000_vect_nonmem = false;
5259 /* Implement targetm.vectorize.add_stmt_cost. */
5262 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5263 struct _stmt_vec_info *stmt_info, int misalign,
5264 enum vect_cost_model_location where)
5266 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5267 unsigned retval = 0;
5269 if (flag_vect_cost_model)
5271 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5272 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5274 /* Statements in an inner loop relative to the loop being
5275 vectorized are weighted more heavily. The value here is
5276 arbitrary and could potentially be improved with analysis. */
5277 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5278 count *= 50; /* FIXME. */
5280 retval = (unsigned) (count * stmt_cost);
5281 cost_data->cost[where] += retval;
5283 /* Check whether we're doing something other than just a copy loop.
5284 Not all such loops may be profitably vectorized; see
5285 rs6000_finish_cost. */
5286 if ((kind == vec_to_scalar || kind == vec_perm
5287 || kind == vec_promote_demote || kind == vec_construct
5288 || kind == scalar_to_vec)
5289 || (where == vect_body && kind == vector_stmt))
5290 rs6000_vect_nonmem = true;
5296 /* Implement targetm.vectorize.finish_cost. */
5299 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5300 unsigned *body_cost, unsigned *epilogue_cost)
5302 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5304 if (cost_data->loop_info)
5305 rs6000_density_test (cost_data);
5307 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5308 that require versioning for any reason. The vectorization is at
5309 best a wash inside the loop, and the versioning checks make
5310 profitability highly unlikely and potentially quite harmful. */
5311 if (cost_data->loop_info)
5313 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5314 if (!rs6000_vect_nonmem
5315 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5316 && LOOP_REQUIRES_VERSIONING (vec_info))
5317 cost_data->cost[vect_body] += 10000;
5320 *prologue_cost = cost_data->cost[vect_prologue];
5321 *body_cost = cost_data->cost[vect_body];
5322 *epilogue_cost = cost_data->cost[vect_epilogue];
5325 /* Implement targetm.vectorize.destroy_cost_data. */
5328 rs6000_destroy_cost_data (void *data)
5333 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5334 library with vectorized intrinsics. */
5337 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5341 const char *suffix = NULL;
5342 tree fntype, new_fndecl, bdecl = NULL_TREE;
5345 machine_mode el_mode, in_mode;
5348 /* Libmass is suitable for unsafe math only as it does not correctly support
5349 parts of IEEE with the required precision such as denormals. Only support
5350 it if we have VSX to use the simd d2 or f4 functions.
5351 XXX: Add variable length support. */
5352 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5355 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5356 n = TYPE_VECTOR_SUBPARTS (type_out);
5357 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5358 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5359 if (el_mode != in_mode
5395 if (el_mode == DFmode && n == 2)
5397 bdecl = mathfn_built_in (double_type_node, fn);
5398 suffix = "d2"; /* pow -> powd2 */
5400 else if (el_mode == SFmode && n == 4)
5402 bdecl = mathfn_built_in (float_type_node, fn);
5403 suffix = "4"; /* powf -> powf4 */
5415 gcc_assert (suffix != NULL);
5416 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5420 strcpy (name, bname + sizeof ("__builtin_") - 1);
5421 strcat (name, suffix);
5424 fntype = build_function_type_list (type_out, type_in, NULL);
5425 else if (n_args == 2)
5426 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5430 /* Build a function declaration for the vectorized function. */
5431 new_fndecl = build_decl (BUILTINS_LOCATION,
5432 FUNCTION_DECL, get_identifier (name), fntype);
5433 TREE_PUBLIC (new_fndecl) = 1;
5434 DECL_EXTERNAL (new_fndecl) = 1;
5435 DECL_IS_NOVOPS (new_fndecl) = 1;
5436 TREE_READONLY (new_fndecl) = 1;
5441 /* Returns a function decl for a vectorized version of the builtin function
5442 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5443 if it is not available. */
5446 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5449 machine_mode in_mode, out_mode;
5452 if (TARGET_DEBUG_BUILTIN)
5453 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5454 combined_fn_name (combined_fn (fn)),
5455 GET_MODE_NAME (TYPE_MODE (type_out)),
5456 GET_MODE_NAME (TYPE_MODE (type_in)));
5458 if (TREE_CODE (type_out) != VECTOR_TYPE
5459 || TREE_CODE (type_in) != VECTOR_TYPE)
5462 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5463 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5464 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5465 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5470 if (VECTOR_UNIT_VSX_P (V2DFmode)
5471 && out_mode == DFmode && out_n == 2
5472 && in_mode == DFmode && in_n == 2)
5473 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5474 if (VECTOR_UNIT_VSX_P (V4SFmode)
5475 && out_mode == SFmode && out_n == 4
5476 && in_mode == SFmode && in_n == 4)
5477 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5478 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5479 && out_mode == SFmode && out_n == 4
5480 && in_mode == SFmode && in_n == 4)
5481 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5484 if (VECTOR_UNIT_VSX_P (V2DFmode)
5485 && out_mode == DFmode && out_n == 2
5486 && in_mode == DFmode && in_n == 2)
5487 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5488 if (VECTOR_UNIT_VSX_P (V4SFmode)
5489 && out_mode == SFmode && out_n == 4
5490 && in_mode == SFmode && in_n == 4)
5491 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5492 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5493 && out_mode == SFmode && out_n == 4
5494 && in_mode == SFmode && in_n == 4)
5495 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5498 if (VECTOR_UNIT_VSX_P (V2DFmode)
5499 && out_mode == DFmode && out_n == 2
5500 && in_mode == DFmode && in_n == 2)
5501 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5502 if (VECTOR_UNIT_VSX_P (V4SFmode)
5503 && out_mode == SFmode && out_n == 4
5504 && in_mode == SFmode && in_n == 4)
5505 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5506 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5507 && out_mode == SFmode && out_n == 4
5508 && in_mode == SFmode && in_n == 4)
5509 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5512 if (VECTOR_UNIT_VSX_P (V2DFmode)
5513 && out_mode == DFmode && out_n == 2
5514 && in_mode == DFmode && in_n == 2)
5515 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5516 if (VECTOR_UNIT_VSX_P (V4SFmode)
5517 && out_mode == SFmode && out_n == 4
5518 && in_mode == SFmode && in_n == 4)
5519 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5520 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5521 && out_mode == SFmode && out_n == 4
5522 && in_mode == SFmode && in_n == 4)
5523 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5526 if (VECTOR_UNIT_VSX_P (V2DFmode)
5527 && out_mode == DFmode && out_n == 2
5528 && in_mode == DFmode && in_n == 2)
5529 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5530 if (VECTOR_UNIT_VSX_P (V4SFmode)
5531 && out_mode == SFmode && out_n == 4
5532 && in_mode == SFmode && in_n == 4)
5533 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5534 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5535 && out_mode == SFmode && out_n == 4
5536 && in_mode == SFmode && in_n == 4)
5537 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5540 if (VECTOR_UNIT_VSX_P (V2DFmode)
5541 && flag_unsafe_math_optimizations
5542 && out_mode == DFmode && out_n == 2
5543 && in_mode == DFmode && in_n == 2)
5544 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5545 if (VECTOR_UNIT_VSX_P (V4SFmode)
5546 && flag_unsafe_math_optimizations
5547 && out_mode == SFmode && out_n == 4
5548 && in_mode == SFmode && in_n == 4)
5549 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5552 if (VECTOR_UNIT_VSX_P (V2DFmode)
5553 && !flag_trapping_math
5554 && out_mode == DFmode && out_n == 2
5555 && in_mode == DFmode && in_n == 2)
5556 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5557 if (VECTOR_UNIT_VSX_P (V4SFmode)
5558 && !flag_trapping_math
5559 && out_mode == SFmode && out_n == 4
5560 && in_mode == SFmode && in_n == 4)
5561 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5567 /* Generate calls to libmass if appropriate. */
5568 if (rs6000_veclib_handler)
5569 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5574 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5577 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5580 machine_mode in_mode, out_mode;
5583 if (TARGET_DEBUG_BUILTIN)
5584 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5585 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5586 GET_MODE_NAME (TYPE_MODE (type_out)),
5587 GET_MODE_NAME (TYPE_MODE (type_in)));
5589 if (TREE_CODE (type_out) != VECTOR_TYPE
5590 || TREE_CODE (type_in) != VECTOR_TYPE)
5593 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5594 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5595 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5596 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5598 enum rs6000_builtins fn
5599 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5602 case RS6000_BUILTIN_RSQRTF:
5603 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5604 && out_mode == SFmode && out_n == 4
5605 && in_mode == SFmode && in_n == 4)
5606 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5608 case RS6000_BUILTIN_RSQRT:
5609 if (VECTOR_UNIT_VSX_P (V2DFmode)
5610 && out_mode == DFmode && out_n == 2
5611 && in_mode == DFmode && in_n == 2)
5612 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5614 case RS6000_BUILTIN_RECIPF:
5615 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5616 && out_mode == SFmode && out_n == 4
5617 && in_mode == SFmode && in_n == 4)
5618 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5620 case RS6000_BUILTIN_RECIP:
5621 if (VECTOR_UNIT_VSX_P (V2DFmode)
5622 && out_mode == DFmode && out_n == 2
5623 && in_mode == DFmode && in_n == 2)
5624 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5632 /* Default CPU string for rs6000*_file_start functions. */
5633 static const char *rs6000_default_cpu;
5635 #ifdef USING_ELFOS_H
5636 static const char *rs6000_machine;
5639 rs6000_machine_from_flags (void)
5641 if ((rs6000_isa_flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
5643 if ((rs6000_isa_flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
5645 if ((rs6000_isa_flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
5647 if ((rs6000_isa_flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
5649 if ((rs6000_isa_flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
5651 if ((rs6000_isa_flags & ISA_2_1_MASKS) != 0)
5653 if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
5659 emit_asm_machine (void)
5661 fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine);
5665 /* Do anything needed at the start of the asm file. */
5668 rs6000_file_start (void)
5671 const char *start = buffer;
5672 FILE *file = asm_out_file;
5674 rs6000_default_cpu = TARGET_CPU_DEFAULT;
5676 default_file_start ();
5678 if (flag_verbose_asm)
5680 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
5682 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
5684 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
5688 if (global_options_set.x_rs6000_cpu_index)
5690 fprintf (file, "%s -mcpu=%s", start,
5691 processor_target_table[rs6000_cpu_index].name);
5695 if (global_options_set.x_rs6000_tune_index)
5697 fprintf (file, "%s -mtune=%s", start,
5698 processor_target_table[rs6000_tune_index].name);
5702 if (PPC405_ERRATUM77)
5704 fprintf (file, "%s PPC405CR_ERRATUM77", start);
5708 #ifdef USING_ELFOS_H
5709 switch (rs6000_sdata)
5711 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
5712 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
5713 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
5714 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
5717 if (rs6000_sdata && g_switch_value)
5719 fprintf (file, "%s -G %d", start,
5729 #ifdef USING_ELFOS_H
5730 rs6000_machine = rs6000_machine_from_flags ();
5731 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
5732 && !global_options_set.x_rs6000_cpu_index)
5733 emit_asm_machine ();
5736 if (DEFAULT_ABI == ABI_ELFv2)
5737 fprintf (file, "\t.abiversion 2\n");
5741 /* Return nonzero if this function is known to have a null epilogue. */
5744 direct_return (void)
5746 if (reload_completed)
5748 rs6000_stack_t *info = rs6000_stack_info ();
5750 if (info->first_gp_reg_save == 32
5751 && info->first_fp_reg_save == 64
5752 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
5753 && ! info->lr_save_p
5754 && ! info->cr_save_p
5755 && info->vrsave_size == 0
5763 /* Helper for num_insns_constant. Calculate number of instructions to
5764 load VALUE to a single gpr using combinations of addi, addis, ori,
5765 oris and sldi instructions. */
5768 num_insns_constant_gpr (HOST_WIDE_INT value)
5770 /* signed constant loadable with addi */
5771 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
5774 /* constant loadable with addis */
5775 else if ((value & 0xffff) == 0
5776 && (value >> 31 == -1 || value >> 31 == 0))
5779 else if (TARGET_POWERPC64)
5781 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
5782 HOST_WIDE_INT high = value >> 31;
5784 if (high == 0 || high == -1)
5790 return num_insns_constant_gpr (high) + 1;
5792 return num_insns_constant_gpr (low) + 1;
5794 return (num_insns_constant_gpr (high)
5795 + num_insns_constant_gpr (low) + 1);
5802 /* Helper for num_insns_constant. Allow constants formed by the
5803 num_insns_constant_gpr sequences, plus li -1, rldicl/rldicr/rlwinm,
5804 and handle modes that require multiple gprs. */
5807 num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
5809 int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5813 HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
5814 int insns = num_insns_constant_gpr (low);
5816 /* We won't get more than 2 from num_insns_constant_gpr
5817 except when TARGET_POWERPC64 and mode is DImode or
5818 wider, so the register mode must be DImode. */
5819 && rs6000_is_valid_and_mask (GEN_INT (low), DImode))
5822 value >>= BITS_PER_WORD;
5827 /* Return the number of instructions it takes to form a constant in as
5828 many gprs are needed for MODE. */
5831 num_insns_constant (rtx op, machine_mode mode)
5835 switch (GET_CODE (op))
5841 case CONST_WIDE_INT:
5844 for (int i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
5845 insns += num_insns_constant_multi (CONST_WIDE_INT_ELT (op, i),
5852 const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
5854 if (mode == SFmode || mode == SDmode)
5859 REAL_VALUE_TO_TARGET_DECIMAL32 (*rv, l);
5861 REAL_VALUE_TO_TARGET_SINGLE (*rv, l);
5862 /* See the first define_split in rs6000.md handling a
5863 const_double_operand. */
5867 else if (mode == DFmode || mode == DDmode)
5872 REAL_VALUE_TO_TARGET_DECIMAL64 (*rv, l);
5874 REAL_VALUE_TO_TARGET_DOUBLE (*rv, l);
5876 /* See the second (32-bit) and third (64-bit) define_split
5877 in rs6000.md handling a const_double_operand. */
5878 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 1] << 32;
5879 val |= l[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffffUL;
5882 else if (mode == TFmode || mode == TDmode
5883 || mode == KFmode || mode == IFmode)
5889 REAL_VALUE_TO_TARGET_DECIMAL128 (*rv, l);
5891 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*rv, l);
5893 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 3] << 32;
5894 val |= l[WORDS_BIG_ENDIAN ? 1 : 2] & 0xffffffffUL;
5895 insns = num_insns_constant_multi (val, DImode);
5896 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 2 : 1] << 32;
5897 val |= l[WORDS_BIG_ENDIAN ? 3 : 0] & 0xffffffffUL;
5898 insns += num_insns_constant_multi (val, DImode);
5910 return num_insns_constant_multi (val, mode);
5913 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5914 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5915 corresponding element of the vector, but for V4SFmode, the
5916 corresponding "float" is interpreted as an SImode integer. */
5919 const_vector_elt_as_int (rtx op, unsigned int elt)
5923 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5924 gcc_assert (GET_MODE (op) != V2DImode
5925 && GET_MODE (op) != V2DFmode);
5927 tmp = CONST_VECTOR_ELT (op, elt);
5928 if (GET_MODE (op) == V4SFmode)
5929 tmp = gen_lowpart (SImode, tmp);
5930 return INTVAL (tmp);
5933 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5934 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5935 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5936 all items are set to the same value and contain COPIES replicas of the
5937 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5938 operand and the others are set to the value of the operand's msb. */
5941 vspltis_constant (rtx op, unsigned step, unsigned copies)
5943 machine_mode mode = GET_MODE (op);
5944 machine_mode inner = GET_MODE_INNER (mode);
5952 HOST_WIDE_INT splat_val;
5953 HOST_WIDE_INT msb_val;
5955 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
5958 nunits = GET_MODE_NUNITS (mode);
5959 bitsize = GET_MODE_BITSIZE (inner);
5960 mask = GET_MODE_MASK (inner);
5962 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5964 msb_val = val >= 0 ? 0 : -1;
5966 /* Construct the value to be splatted, if possible. If not, return 0. */
5967 for (i = 2; i <= copies; i *= 2)
5969 HOST_WIDE_INT small_val;
5971 small_val = splat_val >> bitsize;
5973 if (splat_val != ((HOST_WIDE_INT)
5974 ((unsigned HOST_WIDE_INT) small_val << bitsize)
5975 | (small_val & mask)))
5977 splat_val = small_val;
5980 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5981 if (EASY_VECTOR_15 (splat_val))
5984 /* Also check if we can splat, and then add the result to itself. Do so if
5985 the value is positive, of if the splat instruction is using OP's mode;
5986 for splat_val < 0, the splat and the add should use the same mode. */
5987 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
5988 && (splat_val >= 0 || (step == 1 && copies == 1)))
5991 /* Also check if are loading up the most significant bit which can be done by
5992 loading up -1 and shifting the value left by -1. */
5993 else if (EASY_VECTOR_MSB (splat_val, inner))
5999 /* Check if VAL is present in every STEP-th element, and the
6000 other elements are filled with its most significant bit. */
6001 for (i = 1; i < nunits; ++i)
6003 HOST_WIDE_INT desired_val;
6004 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6005 if ((i & (step - 1)) == 0)
6008 desired_val = msb_val;
6010 if (desired_val != const_vector_elt_as_int (op, elt))
6017 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6018 instruction, filling in the bottom elements with 0 or -1.
6020 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6021 for the number of zeroes to shift in, or negative for the number of 0xff
6024 OP is a CONST_VECTOR. */
6027 vspltis_shifted (rtx op)
6029 machine_mode mode = GET_MODE (op);
6030 machine_mode inner = GET_MODE_INNER (mode);
6038 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6041 /* We need to create pseudo registers to do the shift, so don't recognize
6042 shift vector constants after reload. */
6043 if (!can_create_pseudo_p ())
6046 nunits = GET_MODE_NUNITS (mode);
6047 mask = GET_MODE_MASK (inner);
6049 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6051 /* Check if the value can really be the operand of a vspltis[bhw]. */
6052 if (EASY_VECTOR_15 (val))
6055 /* Also check if we are loading up the most significant bit which can be done
6056 by loading up -1 and shifting the value left by -1. */
6057 else if (EASY_VECTOR_MSB (val, inner))
6063 /* Check if VAL is present in every STEP-th element until we find elements
6064 that are 0 or all 1 bits. */
6065 for (i = 1; i < nunits; ++i)
6067 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6068 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6070 /* If the value isn't the splat value, check for the remaining elements
6076 for (j = i+1; j < nunits; ++j)
6078 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6079 if (const_vector_elt_as_int (op, elt2) != 0)
6083 return (nunits - i) * GET_MODE_SIZE (inner);
6086 else if ((elt_val & mask) == mask)
6088 for (j = i+1; j < nunits; ++j)
6090 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6091 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6095 return -((nunits - i) * GET_MODE_SIZE (inner));
6103 /* If all elements are equal, we don't need to do VLSDOI. */
6108 /* Return true if OP is of the given MODE and can be synthesized
6109 with a vspltisb, vspltish or vspltisw. */
6112 easy_altivec_constant (rtx op, machine_mode mode)
6114 unsigned step, copies;
6116 if (mode == VOIDmode)
6117 mode = GET_MODE (op);
6118 else if (mode != GET_MODE (op))
6121 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6123 if (mode == V2DFmode)
6124 return zero_constant (op, mode);
6126 else if (mode == V2DImode)
6128 if (!CONST_INT_P (CONST_VECTOR_ELT (op, 0))
6129 || !CONST_INT_P (CONST_VECTOR_ELT (op, 1)))
6132 if (zero_constant (op, mode))
6135 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6136 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6142 /* V1TImode is a special container for TImode. Ignore for now. */
6143 else if (mode == V1TImode)
6146 /* Start with a vspltisw. */
6147 step = GET_MODE_NUNITS (mode) / 4;
6150 if (vspltis_constant (op, step, copies))
6153 /* Then try with a vspltish. */
6159 if (vspltis_constant (op, step, copies))
6162 /* And finally a vspltisb. */
6168 if (vspltis_constant (op, step, copies))
6171 if (vspltis_shifted (op) != 0)
6177 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6178 result is OP. Abort if it is not possible. */
6181 gen_easy_altivec_constant (rtx op)
6183 machine_mode mode = GET_MODE (op);
6184 int nunits = GET_MODE_NUNITS (mode);
6185 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6186 unsigned step = nunits / 4;
6187 unsigned copies = 1;
6189 /* Start with a vspltisw. */
6190 if (vspltis_constant (op, step, copies))
6191 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6193 /* Then try with a vspltish. */
6199 if (vspltis_constant (op, step, copies))
6200 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6202 /* And finally a vspltisb. */
6208 if (vspltis_constant (op, step, copies))
6209 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6214 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6215 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6217 Return the number of instructions needed (1 or 2) into the address pointed
6220 Return the constant that is being split via CONSTANT_PTR. */
6223 xxspltib_constant_p (rtx op,
6228 size_t nunits = GET_MODE_NUNITS (mode);
6230 HOST_WIDE_INT value;
6233 /* Set the returned values to out of bound values. */
6234 *num_insns_ptr = -1;
6235 *constant_ptr = 256;
6237 if (!TARGET_P9_VECTOR)
6240 if (mode == VOIDmode)
6241 mode = GET_MODE (op);
6243 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6246 /* Handle (vec_duplicate <constant>). */
6247 if (GET_CODE (op) == VEC_DUPLICATE)
6249 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6250 && mode != V2DImode)
6253 element = XEXP (op, 0);
6254 if (!CONST_INT_P (element))
6257 value = INTVAL (element);
6258 if (!IN_RANGE (value, -128, 127))
6262 /* Handle (const_vector [...]). */
6263 else if (GET_CODE (op) == CONST_VECTOR)
6265 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6266 && mode != V2DImode)
6269 element = CONST_VECTOR_ELT (op, 0);
6270 if (!CONST_INT_P (element))
6273 value = INTVAL (element);
6274 if (!IN_RANGE (value, -128, 127))
6277 for (i = 1; i < nunits; i++)
6279 element = CONST_VECTOR_ELT (op, i);
6280 if (!CONST_INT_P (element))
6283 if (value != INTVAL (element))
6288 /* Handle integer constants being loaded into the upper part of the VSX
6289 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6290 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6291 else if (CONST_INT_P (op))
6293 if (!SCALAR_INT_MODE_P (mode))
6296 value = INTVAL (op);
6297 if (!IN_RANGE (value, -128, 127))
6300 if (!IN_RANGE (value, -1, 0))
6302 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6305 if (EASY_VECTOR_15 (value))
6313 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6314 sign extend. Special case 0/-1 to allow getting any VSX register instead
6315 of an Altivec register. */
6316 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6317 && EASY_VECTOR_15 (value))
6320 /* Return # of instructions and the constant byte for XXSPLTIB. */
6321 if (mode == V16QImode)
6324 else if (IN_RANGE (value, -1, 0))
6330 *constant_ptr = (int) value;
6335 output_vec_const_move (rtx *operands)
6343 mode = GET_MODE (dest);
6347 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6348 int xxspltib_value = 256;
6351 if (zero_constant (vec, mode))
6353 if (TARGET_P9_VECTOR)
6354 return "xxspltib %x0,0";
6356 else if (dest_vmx_p)
6357 return "vspltisw %0,0";
6360 return "xxlxor %x0,%x0,%x0";
6363 if (all_ones_constant (vec, mode))
6365 if (TARGET_P9_VECTOR)
6366 return "xxspltib %x0,255";
6368 else if (dest_vmx_p)
6369 return "vspltisw %0,-1";
6371 else if (TARGET_P8_VECTOR)
6372 return "xxlorc %x0,%x0,%x0";
6378 if (TARGET_P9_VECTOR
6379 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6383 operands[2] = GEN_INT (xxspltib_value & 0xff);
6384 return "xxspltib %x0,%2";
6395 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6396 if (zero_constant (vec, mode))
6397 return "vspltisw %0,0";
6399 if (all_ones_constant (vec, mode))
6400 return "vspltisw %0,-1";
6402 /* Do we need to construct a value using VSLDOI? */
6403 shift = vspltis_shifted (vec);
6407 splat_vec = gen_easy_altivec_constant (vec);
6408 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6409 operands[1] = XEXP (splat_vec, 0);
6410 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6413 switch (GET_MODE (splat_vec))
6416 return "vspltisw %0,%1";
6419 return "vspltish %0,%1";
6422 return "vspltisb %0,%1";
6432 /* Initialize vector TARGET to VALS. */
6435 rs6000_expand_vector_init (rtx target, rtx vals)
6437 machine_mode mode = GET_MODE (target);
6438 machine_mode inner_mode = GET_MODE_INNER (mode);
6439 int n_elts = GET_MODE_NUNITS (mode);
6440 int n_var = 0, one_var = -1;
6441 bool all_same = true, all_const_zero = true;
6445 for (i = 0; i < n_elts; ++i)
6447 x = XVECEXP (vals, 0, i);
6448 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6449 ++n_var, one_var = i;
6450 else if (x != CONST0_RTX (inner_mode))
6451 all_const_zero = false;
6453 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6459 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6460 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6461 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6463 /* Zero register. */
6464 emit_move_insn (target, CONST0_RTX (mode));
6467 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6469 /* Splat immediate. */
6470 emit_insn (gen_rtx_SET (target, const_vec));
6475 /* Load from constant pool. */
6476 emit_move_insn (target, const_vec);
6481 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6482 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6486 size_t num_elements = all_same ? 1 : 2;
6487 for (i = 0; i < num_elements; i++)
6489 op[i] = XVECEXP (vals, 0, i);
6490 /* Just in case there is a SUBREG with a smaller mode, do a
6492 if (GET_MODE (op[i]) != inner_mode)
6494 rtx tmp = gen_reg_rtx (inner_mode);
6495 convert_move (tmp, op[i], 0);
6498 /* Allow load with splat double word. */
6499 else if (MEM_P (op[i]))
6502 op[i] = force_reg (inner_mode, op[i]);
6504 else if (!REG_P (op[i]))
6505 op[i] = force_reg (inner_mode, op[i]);
6510 if (mode == V2DFmode)
6511 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6513 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6517 if (mode == V2DFmode)
6518 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6520 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6525 /* Special case initializing vector int if we are on 64-bit systems with
6526 direct move or we have the ISA 3.0 instructions. */
6527 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6528 && TARGET_DIRECT_MOVE_64BIT)
6532 rtx element0 = XVECEXP (vals, 0, 0);
6533 if (MEM_P (element0))
6534 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6536 element0 = force_reg (SImode, element0);
6538 if (TARGET_P9_VECTOR)
6539 emit_insn (gen_vsx_splat_v4si (target, element0));
6542 rtx tmp = gen_reg_rtx (DImode);
6543 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6544 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6553 for (i = 0; i < 4; i++)
6554 elements[i] = force_reg (SImode, XVECEXP (vals, 0, i));
6556 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6557 elements[2], elements[3]));
6562 /* With single precision floating point on VSX, know that internally single
6563 precision is actually represented as a double, and either make 2 V2DF
6564 vectors, and convert these vectors to single precision, or do one
6565 conversion, and splat the result to the other elements. */
6566 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6570 rtx element0 = XVECEXP (vals, 0, 0);
6572 if (TARGET_P9_VECTOR)
6574 if (MEM_P (element0))
6575 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6577 emit_insn (gen_vsx_splat_v4sf (target, element0));
6582 rtx freg = gen_reg_rtx (V4SFmode);
6583 rtx sreg = force_reg (SFmode, element0);
6584 rtx cvt = (TARGET_XSCVDPSPN
6585 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6586 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6589 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6595 rtx dbl_even = gen_reg_rtx (V2DFmode);
6596 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6597 rtx flt_even = gen_reg_rtx (V4SFmode);
6598 rtx flt_odd = gen_reg_rtx (V4SFmode);
6599 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6600 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6601 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6602 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6604 /* Use VMRGEW if we can instead of doing a permute. */
6605 if (TARGET_P8_VECTOR)
6607 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6608 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6609 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6610 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6611 if (BYTES_BIG_ENDIAN)
6612 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6614 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6618 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6619 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6620 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6621 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6622 rs6000_expand_extract_even (target, flt_even, flt_odd);
6628 /* Special case initializing vector short/char that are splats if we are on
6629 64-bit systems with direct move. */
6630 if (all_same && TARGET_DIRECT_MOVE_64BIT
6631 && (mode == V16QImode || mode == V8HImode))
6633 rtx op0 = XVECEXP (vals, 0, 0);
6634 rtx di_tmp = gen_reg_rtx (DImode);
6637 op0 = force_reg (GET_MODE_INNER (mode), op0);
6639 if (mode == V16QImode)
6641 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6642 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6646 if (mode == V8HImode)
6648 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6649 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6654 /* Store value to stack temp. Load vector element. Splat. However, splat
6655 of 64-bit items is not supported on Altivec. */
6656 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6658 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6659 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6660 XVECEXP (vals, 0, 0));
6661 x = gen_rtx_UNSPEC (VOIDmode,
6662 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6663 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6665 gen_rtx_SET (target, mem),
6667 x = gen_rtx_VEC_SELECT (inner_mode, target,
6668 gen_rtx_PARALLEL (VOIDmode,
6669 gen_rtvec (1, const0_rtx)));
6670 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6674 /* One field is non-constant. Load constant then overwrite
6678 rtx copy = copy_rtx (vals);
6680 /* Load constant part of vector, substitute neighboring value for
6682 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6683 rs6000_expand_vector_init (target, copy);
6685 /* Insert variable. */
6686 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
6690 /* Construct the vector in memory one field at a time
6691 and load the whole vector. */
6692 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6693 for (i = 0; i < n_elts; i++)
6694 emit_move_insn (adjust_address_nv (mem, inner_mode,
6695 i * GET_MODE_SIZE (inner_mode)),
6696 XVECEXP (vals, 0, i));
6697 emit_move_insn (target, mem);
6700 /* Set field ELT of TARGET to VAL. */
6703 rs6000_expand_vector_set (rtx target, rtx val, int elt)
6705 machine_mode mode = GET_MODE (target);
6706 machine_mode inner_mode = GET_MODE_INNER (mode);
6707 rtx reg = gen_reg_rtx (mode);
6709 int width = GET_MODE_SIZE (inner_mode);
6712 val = force_reg (GET_MODE (val), val);
6714 if (VECTOR_MEM_VSX_P (mode))
6716 rtx insn = NULL_RTX;
6717 rtx elt_rtx = GEN_INT (elt);
6719 if (mode == V2DFmode)
6720 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
6722 else if (mode == V2DImode)
6723 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
6725 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
6727 if (mode == V4SImode)
6728 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
6729 else if (mode == V8HImode)
6730 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
6731 else if (mode == V16QImode)
6732 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
6733 else if (mode == V4SFmode)
6734 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
6744 /* Simplify setting single element vectors like V1TImode. */
6745 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
6747 emit_move_insn (target, gen_lowpart (mode, val));
6751 /* Load single variable value. */
6752 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6753 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
6754 x = gen_rtx_UNSPEC (VOIDmode,
6755 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6756 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6758 gen_rtx_SET (reg, mem),
6761 /* Linear sequence. */
6762 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
6763 for (i = 0; i < 16; ++i)
6764 XVECEXP (mask, 0, i) = GEN_INT (i);
6766 /* Set permute mask to insert element into target. */
6767 for (i = 0; i < width; ++i)
6768 XVECEXP (mask, 0, elt*width + i)
6769 = GEN_INT (i + 0x10);
6770 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
6772 if (BYTES_BIG_ENDIAN)
6773 x = gen_rtx_UNSPEC (mode,
6774 gen_rtvec (3, target, reg,
6775 force_reg (V16QImode, x)),
6779 if (TARGET_P9_VECTOR)
6780 x = gen_rtx_UNSPEC (mode,
6781 gen_rtvec (3, reg, target,
6782 force_reg (V16QImode, x)),
6786 /* Invert selector. We prefer to generate VNAND on P8 so
6787 that future fusion opportunities can kick in, but must
6788 generate VNOR elsewhere. */
6789 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
6790 rtx iorx = (TARGET_P8_VECTOR
6791 ? gen_rtx_IOR (V16QImode, notx, notx)
6792 : gen_rtx_AND (V16QImode, notx, notx));
6793 rtx tmp = gen_reg_rtx (V16QImode);
6794 emit_insn (gen_rtx_SET (tmp, iorx));
6796 /* Permute with operands reversed and adjusted selector. */
6797 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
6802 emit_insn (gen_rtx_SET (target, x));
6805 /* Extract field ELT from VEC into TARGET. */
6808 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
6810 machine_mode mode = GET_MODE (vec);
6811 machine_mode inner_mode = GET_MODE_INNER (mode);
6814 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
6821 emit_move_insn (target, gen_lowpart (TImode, vec));
6824 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
6827 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
6830 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
6833 if (TARGET_DIRECT_MOVE_64BIT)
6835 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
6841 if (TARGET_DIRECT_MOVE_64BIT)
6843 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
6849 if (TARGET_DIRECT_MOVE_64BIT)
6851 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
6857 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
6858 && TARGET_DIRECT_MOVE_64BIT)
6860 if (GET_MODE (elt) != DImode)
6862 rtx tmp = gen_reg_rtx (DImode);
6863 convert_move (tmp, elt, 0);
6866 else if (!REG_P (elt))
6867 elt = force_reg (DImode, elt);
6872 emit_move_insn (target, gen_lowpart (TImode, vec));
6876 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
6880 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
6884 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
6888 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
6892 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
6896 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
6904 /* Allocate mode-sized buffer. */
6905 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6907 emit_move_insn (mem, vec);
6908 if (CONST_INT_P (elt))
6910 int modulo_elt = INTVAL (elt) % GET_MODE_NUNITS (mode);
6912 /* Add offset to field within buffer matching vector element. */
6913 mem = adjust_address_nv (mem, inner_mode,
6914 modulo_elt * GET_MODE_SIZE (inner_mode));
6915 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
6919 unsigned int ele_size = GET_MODE_SIZE (inner_mode);
6920 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
6921 rtx new_addr = gen_reg_rtx (Pmode);
6923 elt = gen_rtx_AND (Pmode, elt, num_ele_m1);
6925 elt = gen_rtx_MULT (Pmode, elt, GEN_INT (ele_size));
6926 new_addr = gen_rtx_PLUS (Pmode, XEXP (mem, 0), elt);
6927 new_addr = change_address (mem, inner_mode, new_addr);
6928 emit_move_insn (target, new_addr);
6932 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6933 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6934 temporary (BASE_TMP) to fixup the address. Return the new memory address
6935 that is valid for reads or writes to a given register (SCALAR_REG). */
6938 rs6000_adjust_vec_address (rtx scalar_reg,
6942 machine_mode scalar_mode)
6944 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
6945 rtx addr = XEXP (mem, 0);
6950 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6951 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
6953 /* Calculate what we need to add to the address to get the element
6955 if (CONST_INT_P (element))
6956 element_offset = GEN_INT (INTVAL (element) * scalar_size);
6959 int byte_shift = exact_log2 (scalar_size);
6960 gcc_assert (byte_shift >= 0);
6962 if (byte_shift == 0)
6963 element_offset = element;
6967 if (TARGET_POWERPC64)
6968 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
6970 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
6972 element_offset = base_tmp;
6976 /* Create the new address pointing to the element within the vector. If we
6977 are adding 0, we don't have to change the address. */
6978 if (element_offset == const0_rtx)
6981 /* A simple indirect address can be converted into a reg + offset
6983 else if (REG_P (addr) || SUBREG_P (addr))
6984 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
6986 /* Optimize D-FORM addresses with constant offset with a constant element, to
6987 include the element offset in the address directly. */
6988 else if (GET_CODE (addr) == PLUS)
6990 rtx op0 = XEXP (addr, 0);
6991 rtx op1 = XEXP (addr, 1);
6994 gcc_assert (REG_P (op0) || SUBREG_P (op0));
6995 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
6997 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
6998 rtx offset_rtx = GEN_INT (offset);
7000 if (IN_RANGE (offset, -32768, 32767)
7001 && (scalar_size < 8 || (offset & 0x3) == 0))
7002 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7005 emit_move_insn (base_tmp, offset_rtx);
7006 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7011 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7012 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7014 /* Note, ADDI requires the register being added to be a base
7015 register. If the register was R0, load it up into the temporary
7018 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7020 insn = gen_add3_insn (base_tmp, op1, element_offset);
7021 gcc_assert (insn != NULL_RTX);
7026 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7028 insn = gen_add3_insn (base_tmp, element_offset, op1);
7029 gcc_assert (insn != NULL_RTX);
7035 emit_move_insn (base_tmp, op1);
7036 emit_insn (gen_add2_insn (base_tmp, element_offset));
7039 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7045 emit_move_insn (base_tmp, addr);
7046 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7049 /* If we have a PLUS, we need to see whether the particular register class
7050 allows for D-FORM or X-FORM addressing. */
7051 if (GET_CODE (new_addr) == PLUS)
7053 rtx op1 = XEXP (new_addr, 1);
7054 addr_mask_type addr_mask;
7055 unsigned int scalar_regno = reg_or_subregno (scalar_reg);
7057 gcc_assert (HARD_REGISTER_NUM_P (scalar_regno));
7058 if (INT_REGNO_P (scalar_regno))
7059 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7061 else if (FP_REGNO_P (scalar_regno))
7062 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7064 else if (ALTIVEC_REGNO_P (scalar_regno))
7065 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7070 if (REG_P (op1) || SUBREG_P (op1))
7071 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7073 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7076 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7077 valid_addr_p = true;
7080 valid_addr_p = false;
7084 emit_move_insn (base_tmp, new_addr);
7085 new_addr = base_tmp;
7088 return change_address (mem, scalar_mode, new_addr);
7091 /* Split a variable vec_extract operation into the component instructions. */
7094 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7097 machine_mode mode = GET_MODE (src);
7098 machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (src));
7099 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7100 int byte_shift = exact_log2 (scalar_size);
7102 gcc_assert (byte_shift >= 0);
7104 /* If we are given a memory address, optimize to load just the element. We
7105 don't have to adjust the vector element number on little endian
7109 int num_elements = GET_MODE_NUNITS (mode);
7110 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7112 emit_insn (gen_anddi3 (element, element, num_ele_m1));
7113 gcc_assert (REG_P (tmp_gpr));
7114 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7115 tmp_gpr, scalar_mode));
7119 else if (REG_P (src) || SUBREG_P (src))
7121 int num_elements = GET_MODE_NUNITS (mode);
7122 int bits_in_element = mode_to_bits (GET_MODE_INNER (mode));
7123 int bit_shift = 7 - exact_log2 (num_elements);
7125 unsigned int dest_regno = reg_or_subregno (dest);
7126 unsigned int src_regno = reg_or_subregno (src);
7127 unsigned int element_regno = reg_or_subregno (element);
7129 gcc_assert (REG_P (tmp_gpr));
7131 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7132 a general purpose register. */
7133 if (TARGET_P9_VECTOR
7134 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7135 && INT_REGNO_P (dest_regno)
7136 && ALTIVEC_REGNO_P (src_regno)
7137 && INT_REGNO_P (element_regno))
7139 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7140 rtx element_si = gen_rtx_REG (SImode, element_regno);
7142 if (mode == V16QImode)
7143 emit_insn (BYTES_BIG_ENDIAN
7144 ? gen_vextublx (dest_si, element_si, src)
7145 : gen_vextubrx (dest_si, element_si, src));
7147 else if (mode == V8HImode)
7149 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7150 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7151 emit_insn (BYTES_BIG_ENDIAN
7152 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7153 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7159 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7160 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7161 emit_insn (BYTES_BIG_ENDIAN
7162 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7163 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7170 gcc_assert (REG_P (tmp_altivec));
7172 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7173 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7174 will shift the element into the upper position (adding 3 to convert a
7175 byte shift into a bit shift). */
7176 if (scalar_size == 8)
7178 if (!BYTES_BIG_ENDIAN)
7180 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7186 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7188 emit_insn (gen_rtx_SET (tmp_gpr,
7189 gen_rtx_AND (DImode,
7190 gen_rtx_ASHIFT (DImode,
7197 if (!BYTES_BIG_ENDIAN)
7199 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7201 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7202 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7208 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7211 /* Get the value into the lower byte of the Altivec register where VSLO
7213 if (TARGET_P9_VECTOR)
7214 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7215 else if (can_create_pseudo_p ())
7216 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7219 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7220 emit_move_insn (tmp_di, tmp_gpr);
7221 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7224 /* Do the VSLO to get the value into the final location. */
7228 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7232 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7237 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7238 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7239 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7240 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7243 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7251 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7252 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7253 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7254 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7256 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7257 emit_insn (gen_lshrdi3 (tmp_gpr_di, tmp_gpr_di,
7258 GEN_INT (64 - bits_in_element)));
7272 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7273 selects whether the alignment is abi mandated, optional, or
7274 both abi and optional alignment. */
7277 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7279 if (how != align_opt)
7281 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7285 if (how != align_abi)
7287 if (TREE_CODE (type) == ARRAY_TYPE
7288 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7290 if (align < BITS_PER_WORD)
7291 align = BITS_PER_WORD;
7298 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7299 instructions simply ignore the low bits; VSX memory instructions
7300 are aligned to 4 or 8 bytes. */
7303 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7305 return (STRICT_ALIGNMENT
7306 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7307 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7308 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7309 && (int) align < VECTOR_ALIGN (mode)))));
7312 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7315 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7317 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7319 if (computed != 128)
7322 if (!warned && warn_psabi)
7325 inform (input_location,
7326 "the layout of aggregates containing vectors with"
7327 " %d-byte alignment has changed in GCC 5",
7328 computed / BITS_PER_UNIT);
7331 /* In current GCC there is no special case. */
7338 /* AIX increases natural record alignment to doubleword if the first
7339 field is an FP double while the FP fields remain word aligned. */
7342 rs6000_special_round_type_align (tree type, unsigned int computed,
7343 unsigned int specified)
7345 unsigned int align = MAX (computed, specified);
7346 tree field = TYPE_FIELDS (type);
7348 /* Skip all non field decls */
7349 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7350 field = DECL_CHAIN (field);
7352 if (field != NULL && field != type)
7354 type = TREE_TYPE (field);
7355 while (TREE_CODE (type) == ARRAY_TYPE)
7356 type = TREE_TYPE (type);
7358 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7359 align = MAX (align, 64);
7365 /* Darwin increases record alignment to the natural alignment of
7369 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7370 unsigned int specified)
7372 unsigned int align = MAX (computed, specified);
7374 if (TYPE_PACKED (type))
7377 /* Find the first field, looking down into aggregates. */
7379 tree field = TYPE_FIELDS (type);
7380 /* Skip all non field decls */
7381 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7382 field = DECL_CHAIN (field);
7385 /* A packed field does not contribute any extra alignment. */
7386 if (DECL_PACKED (field))
7388 type = TREE_TYPE (field);
7389 while (TREE_CODE (type) == ARRAY_TYPE)
7390 type = TREE_TYPE (type);
7391 } while (AGGREGATE_TYPE_P (type));
7393 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7394 align = MAX (align, TYPE_ALIGN (type));
7399 /* Return 1 for an operand in small memory on V.4/eabi. */
7402 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7403 machine_mode mode ATTRIBUTE_UNUSED)
7408 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7411 if (DEFAULT_ABI != ABI_V4)
7414 if (SYMBOL_REF_P (op))
7417 else if (GET_CODE (op) != CONST
7418 || GET_CODE (XEXP (op, 0)) != PLUS
7419 || !SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
7420 || !CONST_INT_P (XEXP (XEXP (op, 0), 1)))
7425 rtx sum = XEXP (op, 0);
7426 HOST_WIDE_INT summand;
7428 /* We have to be careful here, because it is the referenced address
7429 that must be 32k from _SDA_BASE_, not just the symbol. */
7430 summand = INTVAL (XEXP (sum, 1));
7431 if (summand < 0 || summand > g_switch_value)
7434 sym_ref = XEXP (sum, 0);
7437 return SYMBOL_REF_SMALL_P (sym_ref);
7443 /* Return true if either operand is a general purpose register. */
7446 gpr_or_gpr_p (rtx op0, rtx op1)
7448 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7449 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7452 /* Return true if this is a move direct operation between GPR registers and
7453 floating point/VSX registers. */
7456 direct_move_p (rtx op0, rtx op1)
7460 if (!REG_P (op0) || !REG_P (op1))
7463 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
7466 regno0 = REGNO (op0);
7467 regno1 = REGNO (op1);
7468 if (!HARD_REGISTER_NUM_P (regno0) || !HARD_REGISTER_NUM_P (regno1))
7471 if (INT_REGNO_P (regno0))
7472 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
7474 else if (INT_REGNO_P (regno1))
7476 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
7479 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
7486 /* Return true if the OFFSET is valid for the quad address instructions that
7487 use d-form (register + offset) addressing. */
7490 quad_address_offset_p (HOST_WIDE_INT offset)
7492 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7495 /* Return true if the ADDR is an acceptable address for a quad memory
7496 operation of mode MODE (either LQ/STQ for general purpose registers, or
7497 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7498 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7499 3.0 LXV/STXV instruction. */
7502 quad_address_p (rtx addr, machine_mode mode, bool strict)
7506 if (GET_MODE_SIZE (mode) != 16)
7509 if (legitimate_indirect_address_p (addr, strict))
7512 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7515 if (GET_CODE (addr) != PLUS)
7518 op0 = XEXP (addr, 0);
7519 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7522 op1 = XEXP (addr, 1);
7523 if (!CONST_INT_P (op1))
7526 return quad_address_offset_p (INTVAL (op1));
7529 /* Return true if this is a load or store quad operation. This function does
7530 not handle the atomic quad memory instructions. */
7533 quad_load_store_p (rtx op0, rtx op1)
7537 if (!TARGET_QUAD_MEMORY)
7540 else if (REG_P (op0) && MEM_P (op1))
7541 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7542 && quad_memory_operand (op1, GET_MODE (op1))
7543 && !reg_overlap_mentioned_p (op0, op1));
7545 else if (MEM_P (op0) && REG_P (op1))
7546 ret = (quad_memory_operand (op0, GET_MODE (op0))
7547 && quad_int_reg_operand (op1, GET_MODE (op1)));
7552 if (TARGET_DEBUG_ADDR)
7554 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7555 ret ? "true" : "false");
7556 debug_rtx (gen_rtx_SET (op0, op1));
7562 /* Given an address, return a constant offset term if one exists. */
7565 address_offset (rtx op)
7567 if (GET_CODE (op) == PRE_INC
7568 || GET_CODE (op) == PRE_DEC)
7570 else if (GET_CODE (op) == PRE_MODIFY
7571 || GET_CODE (op) == LO_SUM)
7574 if (GET_CODE (op) == CONST)
7577 if (GET_CODE (op) == PLUS)
7580 if (CONST_INT_P (op))
7586 /* Return true if the MEM operand is a memory operand suitable for use
7587 with a (full width, possibly multiple) gpr load/store. On
7588 powerpc64 this means the offset must be divisible by 4.
7589 Implements 'Y' constraint.
7591 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7592 a constraint function we know the operand has satisfied a suitable
7595 Offsetting a lo_sum should not be allowed, except where we know by
7596 alignment that a 32k boundary is not crossed. Note that by
7597 "offsetting" here we mean a further offset to access parts of the
7598 MEM. It's fine to have a lo_sum where the inner address is offset
7599 from a sym, since the same sym+offset will appear in the high part
7600 of the address calculation. */
7603 mem_operand_gpr (rtx op, machine_mode mode)
7605 unsigned HOST_WIDE_INT offset;
7607 rtx addr = XEXP (op, 0);
7609 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7611 && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
7612 && mode_supports_pre_incdec_p (mode)
7613 && legitimate_indirect_address_p (XEXP (addr, 0), false))
7616 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7617 if (!rs6000_offsettable_memref_p (op, mode, false))
7620 op = address_offset (addr);
7624 offset = INTVAL (op);
7625 if (TARGET_POWERPC64 && (offset & 3) != 0)
7628 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7632 if (GET_CODE (addr) == LO_SUM)
7633 /* For lo_sum addresses, we must allow any offset except one that
7634 causes a wrap, so test only the low 16 bits. */
7635 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7637 return offset + 0x8000 < 0x10000u - extra;
7640 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7641 enforce an offset divisible by 4 even for 32-bit. */
7644 mem_operand_ds_form (rtx op, machine_mode mode)
7646 unsigned HOST_WIDE_INT offset;
7648 rtx addr = XEXP (op, 0);
7650 if (!offsettable_address_p (false, mode, addr))
7653 op = address_offset (addr);
7657 offset = INTVAL (op);
7658 if ((offset & 3) != 0)
7661 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7665 if (GET_CODE (addr) == LO_SUM)
7666 /* For lo_sum addresses, we must allow any offset except one that
7667 causes a wrap, so test only the low 16 bits. */
7668 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7670 return offset + 0x8000 < 0x10000u - extra;
7673 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7676 reg_offset_addressing_ok_p (machine_mode mode)
7690 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7691 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7692 a vector mode, if we want to use the VSX registers to move it around,
7693 we need to restrict ourselves to reg+reg addressing. Similarly for
7694 IEEE 128-bit floating point that is passed in a single vector
7696 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
7697 return mode_supports_dq_form (mode);
7701 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7702 addressing for the LFIWZX and STFIWX instructions. */
7703 if (TARGET_NO_SDMODE_STACK)
7715 virtual_stack_registers_memory_p (rtx op)
7720 regnum = REGNO (op);
7722 else if (GET_CODE (op) == PLUS
7723 && REG_P (XEXP (op, 0))
7724 && CONST_INT_P (XEXP (op, 1)))
7725 regnum = REGNO (XEXP (op, 0));
7730 return (regnum >= FIRST_VIRTUAL_REGISTER
7731 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
7734 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7735 is known to not straddle a 32k boundary. This function is used
7736 to determine whether -mcmodel=medium code can use TOC pointer
7737 relative addressing for OP. This means the alignment of the TOC
7738 pointer must also be taken into account, and unfortunately that is
7741 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7742 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7746 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
7750 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
7752 if (!SYMBOL_REF_P (op))
7755 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7757 if (mode_supports_dq_form (mode))
7760 dsize = GET_MODE_SIZE (mode);
7761 decl = SYMBOL_REF_DECL (op);
7767 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7768 replacing memory addresses with an anchor plus offset. We
7769 could find the decl by rummaging around in the block->objects
7770 VEC for the given offset but that seems like too much work. */
7771 dalign = BITS_PER_UNIT;
7772 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
7773 && SYMBOL_REF_ANCHOR_P (op)
7774 && SYMBOL_REF_BLOCK (op) != NULL)
7776 struct object_block *block = SYMBOL_REF_BLOCK (op);
7778 dalign = block->alignment;
7779 offset += SYMBOL_REF_BLOCK_OFFSET (op);
7781 else if (CONSTANT_POOL_ADDRESS_P (op))
7783 /* It would be nice to have get_pool_align().. */
7784 machine_mode cmode = get_pool_mode (op);
7786 dalign = GET_MODE_ALIGNMENT (cmode);
7789 else if (DECL_P (decl))
7791 dalign = DECL_ALIGN (decl);
7795 /* Allow BLKmode when the entire object is known to not
7796 cross a 32k boundary. */
7797 if (!DECL_SIZE_UNIT (decl))
7800 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
7803 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
7807 dalign /= BITS_PER_UNIT;
7808 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7809 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7810 return dalign >= dsize;
7816 /* Find how many bits of the alignment we know for this access. */
7817 dalign /= BITS_PER_UNIT;
7818 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7819 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7821 lsb = offset & -offset;
7825 return dalign >= dsize;
7829 constant_pool_expr_p (rtx op)
7833 split_const (op, &base, &offset);
7834 return (SYMBOL_REF_P (base)
7835 && CONSTANT_POOL_ADDRESS_P (base)
7836 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
7839 /* These are only used to pass through from print_operand/print_operand_address
7840 to rs6000_output_addr_const_extra over the intervening function
7841 output_addr_const which is not target code. */
7842 static const_rtx tocrel_base_oac, tocrel_offset_oac;
7844 /* Return true if OP is a toc pointer relative address (the output
7845 of create_TOC_reference). If STRICT, do not match non-split
7846 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7847 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7848 TOCREL_OFFSET_RET respectively. */
7851 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
7852 const_rtx *tocrel_offset_ret)
7857 if (TARGET_CMODEL != CMODEL_SMALL)
7859 /* When strict ensure we have everything tidy. */
7861 && !(GET_CODE (op) == LO_SUM
7862 && REG_P (XEXP (op, 0))
7863 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
7866 /* When not strict, allow non-split TOC addresses and also allow
7867 (lo_sum (high ..)) TOC addresses created during reload. */
7868 if (GET_CODE (op) == LO_SUM)
7872 const_rtx tocrel_base = op;
7873 const_rtx tocrel_offset = const0_rtx;
7875 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
7877 tocrel_base = XEXP (op, 0);
7878 tocrel_offset = XEXP (op, 1);
7881 if (tocrel_base_ret)
7882 *tocrel_base_ret = tocrel_base;
7883 if (tocrel_offset_ret)
7884 *tocrel_offset_ret = tocrel_offset;
7886 return (GET_CODE (tocrel_base) == UNSPEC
7887 && XINT (tocrel_base, 1) == UNSPEC_TOCREL
7888 && REG_P (XVECEXP (tocrel_base, 0, 1))
7889 && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER);
7892 /* Return true if X is a constant pool address, and also for cmodel=medium
7893 if X is a toc-relative address known to be offsettable within MODE. */
7896 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
7899 const_rtx tocrel_base, tocrel_offset;
7900 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
7901 && (TARGET_CMODEL != CMODEL_MEDIUM
7902 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
7904 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
7905 INTVAL (tocrel_offset), mode)));
7909 legitimate_small_data_p (machine_mode mode, rtx x)
7911 return (DEFAULT_ABI == ABI_V4
7912 && !flag_pic && !TARGET_TOC
7913 && (SYMBOL_REF_P (x) || GET_CODE (x) == CONST)
7914 && small_data_operand (x, mode));
7918 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
7919 bool strict, bool worst_case)
7921 unsigned HOST_WIDE_INT offset;
7924 if (GET_CODE (x) != PLUS)
7926 if (!REG_P (XEXP (x, 0)))
7928 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
7930 if (mode_supports_dq_form (mode))
7931 return quad_address_p (x, mode, strict);
7932 if (!reg_offset_addressing_ok_p (mode))
7933 return virtual_stack_registers_memory_p (x);
7934 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
7936 if (!CONST_INT_P (XEXP (x, 1)))
7939 offset = INTVAL (XEXP (x, 1));
7946 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7948 if (VECTOR_MEM_VSX_P (mode))
7953 if (!TARGET_POWERPC64)
7955 else if (offset & 3)
7968 if (!TARGET_POWERPC64)
7970 else if (offset & 3)
7979 return offset < 0x10000 - extra;
7983 legitimate_indexed_address_p (rtx x, int strict)
7987 if (GET_CODE (x) != PLUS)
7993 return (REG_P (op0) && REG_P (op1)
7994 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
7995 && INT_REG_OK_FOR_INDEX_P (op1, strict))
7996 || (INT_REG_OK_FOR_BASE_P (op1, strict)
7997 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8001 avoiding_indexed_address_p (machine_mode mode)
8003 /* Avoid indexed addressing for modes that have non-indexed
8004 load/store instruction forms. */
8005 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8009 legitimate_indirect_address_p (rtx x, int strict)
8011 return REG_P (x) && INT_REG_OK_FOR_BASE_P (x, strict);
8015 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8017 if (!TARGET_MACHO || !flag_pic
8018 || mode != SImode || !MEM_P (x))
8022 if (GET_CODE (x) != LO_SUM)
8024 if (!REG_P (XEXP (x, 0)))
8026 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8030 return CONSTANT_P (x);
8034 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8036 if (GET_CODE (x) != LO_SUM)
8038 if (!REG_P (XEXP (x, 0)))
8040 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8042 /* quad word addresses are restricted, and we can't use LO_SUM. */
8043 if (mode_supports_dq_form (mode))
8047 if (TARGET_ELF || TARGET_MACHO)
8051 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8053 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8054 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8055 recognizes some LO_SUM addresses as valid although this
8056 function says opposite. In most cases, LRA through different
8057 transformations can generate correct code for address reloads.
8058 It cannot manage only some LO_SUM cases. So we need to add
8059 code here saying that some addresses are still valid. */
8060 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8061 && small_toc_ref (x, VOIDmode));
8062 if (TARGET_TOC && ! large_toc_ok)
8064 if (GET_MODE_NUNITS (mode) != 1)
8066 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8067 && !(/* ??? Assume floating point reg based on mode? */
8068 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8071 return CONSTANT_P (x) || large_toc_ok;
8078 /* Try machine-dependent ways of modifying an illegitimate address
8079 to be legitimate. If we find one, return the new, valid address.
8080 This is used from only one place: `memory_address' in explow.c.
8082 OLDX is the address as it was before break_out_memory_refs was
8083 called. In some cases it is useful to look at this to decide what
8086 It is always safe for this function to do nothing. It exists to
8087 recognize opportunities to optimize the output.
8089 On RS/6000, first check for the sum of a register with a constant
8090 integer that is out of range. If so, generate code to add the
8091 constant with the low-order 16 bits masked to the register and force
8092 this result into another register (this can be done with `cau').
8093 Then generate an address of REG+(CONST&0xffff), allowing for the
8094 possibility of bit 16 being a one.
8096 Then check for the sum of a register and something not constant, try to
8097 load the other things into a register and return the sum. */
8100 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8105 if (!reg_offset_addressing_ok_p (mode)
8106 || mode_supports_dq_form (mode))
8108 if (virtual_stack_registers_memory_p (x))
8111 /* In theory we should not be seeing addresses of the form reg+0,
8112 but just in case it is generated, optimize it away. */
8113 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8114 return force_reg (Pmode, XEXP (x, 0));
8116 /* For TImode with load/store quad, restrict addresses to just a single
8117 pointer, so it works with both GPRs and VSX registers. */
8118 /* Make sure both operands are registers. */
8119 else if (GET_CODE (x) == PLUS
8120 && (mode != TImode || !TARGET_VSX))
8121 return gen_rtx_PLUS (Pmode,
8122 force_reg (Pmode, XEXP (x, 0)),
8123 force_reg (Pmode, XEXP (x, 1)));
8125 return force_reg (Pmode, x);
8127 if (SYMBOL_REF_P (x))
8129 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8131 return rs6000_legitimize_tls_address (x, model);
8143 /* As in legitimate_offset_address_p we do not assume
8144 worst-case. The mode here is just a hint as to the registers
8145 used. A TImode is usually in gprs, but may actually be in
8146 fprs. Leave worst-case scenario for reload to handle via
8147 insn constraints. PTImode is only GPRs. */
8154 if (GET_CODE (x) == PLUS
8155 && REG_P (XEXP (x, 0))
8156 && CONST_INT_P (XEXP (x, 1))
8157 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8158 >= 0x10000 - extra))
8160 HOST_WIDE_INT high_int, low_int;
8162 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8163 if (low_int >= 0x8000 - extra)
8165 high_int = INTVAL (XEXP (x, 1)) - low_int;
8166 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8167 GEN_INT (high_int)), 0);
8168 return plus_constant (Pmode, sum, low_int);
8170 else if (GET_CODE (x) == PLUS
8171 && REG_P (XEXP (x, 0))
8172 && !CONST_INT_P (XEXP (x, 1))
8173 && GET_MODE_NUNITS (mode) == 1
8174 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8175 || (/* ??? Assume floating point reg based on mode? */
8176 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8177 && !avoiding_indexed_address_p (mode))
8179 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8180 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8182 else if ((TARGET_ELF
8184 || !MACHO_DYNAMIC_NO_PIC_P
8191 && !CONST_WIDE_INT_P (x)
8192 && !CONST_DOUBLE_P (x)
8194 && GET_MODE_NUNITS (mode) == 1
8195 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8196 || (/* ??? Assume floating point reg based on mode? */
8197 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8199 rtx reg = gen_reg_rtx (Pmode);
8201 emit_insn (gen_elf_high (reg, x));
8203 emit_insn (gen_macho_high (reg, x));
8204 return gen_rtx_LO_SUM (Pmode, reg, x);
8208 && constant_pool_expr_p (x)
8209 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8210 return create_TOC_reference (x, NULL_RTX);
8215 /* Debug version of rs6000_legitimize_address. */
8217 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8223 ret = rs6000_legitimize_address (x, oldx, mode);
8224 insns = get_insns ();
8230 "\nrs6000_legitimize_address: mode %s, old code %s, "
8231 "new code %s, modified\n",
8232 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8233 GET_RTX_NAME (GET_CODE (ret)));
8235 fprintf (stderr, "Original address:\n");
8238 fprintf (stderr, "oldx:\n");
8241 fprintf (stderr, "New address:\n");
8246 fprintf (stderr, "Insns added:\n");
8247 debug_rtx_list (insns, 20);
8253 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8254 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8265 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8266 We need to emit DTP-relative relocations. */
8268 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8270 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8275 fputs ("\t.long\t", file);
8278 fputs (DOUBLE_INT_ASM_OP, file);
8283 output_addr_const (file, x);
8285 fputs ("@dtprel+0x8000", file);
8286 else if (TARGET_XCOFF && SYMBOL_REF_P (x))
8288 switch (SYMBOL_REF_TLS_MODEL (x))
8292 case TLS_MODEL_LOCAL_EXEC:
8293 fputs ("@le", file);
8295 case TLS_MODEL_INITIAL_EXEC:
8296 fputs ("@ie", file);
8298 case TLS_MODEL_GLOBAL_DYNAMIC:
8299 case TLS_MODEL_LOCAL_DYNAMIC:
8308 /* Return true if X is a symbol that refers to real (rather than emulated)
8312 rs6000_real_tls_symbol_ref_p (rtx x)
8314 return (SYMBOL_REF_P (x)
8315 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8318 /* In the name of slightly smaller debug output, and to cater to
8319 general assembler lossage, recognize various UNSPEC sequences
8320 and turn them back into a direct symbol reference. */
8323 rs6000_delegitimize_address (rtx orig_x)
8327 if (GET_CODE (orig_x) == UNSPEC && XINT (orig_x, 1) == UNSPEC_FUSION_GPR)
8328 orig_x = XVECEXP (orig_x, 0, 0);
8330 orig_x = delegitimize_mem_from_attrs (orig_x);
8337 if (TARGET_CMODEL != CMODEL_SMALL && GET_CODE (y) == LO_SUM)
8341 if (GET_CODE (y) == PLUS
8342 && GET_MODE (y) == Pmode
8343 && CONST_INT_P (XEXP (y, 1)))
8345 offset = XEXP (y, 1);
8349 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_TOCREL)
8351 y = XVECEXP (y, 0, 0);
8354 /* Do not associate thread-local symbols with the original
8355 constant pool symbol. */
8358 && CONSTANT_POOL_ADDRESS_P (y)
8359 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8363 if (offset != NULL_RTX)
8364 y = gen_rtx_PLUS (Pmode, y, offset);
8365 if (!MEM_P (orig_x))
8368 return replace_equiv_address_nv (orig_x, y);
8372 && GET_CODE (orig_x) == LO_SUM
8373 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8375 y = XEXP (XEXP (orig_x, 1), 0);
8376 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8377 return XVECEXP (y, 0, 0);
8383 /* Return true if X shouldn't be emitted into the debug info.
8384 The linker doesn't like .toc section references from
8385 .debug_* sections, so reject .toc section symbols. */
8388 rs6000_const_not_ok_for_debug_p (rtx x)
8390 if (GET_CODE (x) == UNSPEC)
8392 if (SYMBOL_REF_P (x)
8393 && CONSTANT_POOL_ADDRESS_P (x))
8395 rtx c = get_pool_constant (x);
8396 machine_mode cmode = get_pool_mode (x);
8397 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8404 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8407 rs6000_legitimate_combined_insn (rtx_insn *insn)
8409 int icode = INSN_CODE (insn);
8411 /* Reject creating doloop insns. Combine should not be allowed
8412 to create these for a number of reasons:
8413 1) In a nested loop, if combine creates one of these in an
8414 outer loop and the register allocator happens to allocate ctr
8415 to the outer loop insn, then the inner loop can't use ctr.
8416 Inner loops ought to be more highly optimized.
8417 2) Combine often wants to create one of these from what was
8418 originally a three insn sequence, first combining the three
8419 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8420 allocated ctr, the splitter takes use back to the three insn
8421 sequence. It's better to stop combine at the two insn
8423 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8424 insns, the register allocator sometimes uses floating point
8425 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8426 jump insn and output reloads are not implemented for jumps,
8427 the ctrsi/ctrdi splitters need to handle all possible cases.
8428 That's a pain, and it gets to be seriously difficult when a
8429 splitter that runs after reload needs memory to transfer from
8430 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8431 for the difficult case. It's better to not create problems
8432 in the first place. */
8433 if (icode != CODE_FOR_nothing
8434 && (icode == CODE_FOR_bdz_si
8435 || icode == CODE_FOR_bdz_di
8436 || icode == CODE_FOR_bdnz_si
8437 || icode == CODE_FOR_bdnz_di
8438 || icode == CODE_FOR_bdztf_si
8439 || icode == CODE_FOR_bdztf_di
8440 || icode == CODE_FOR_bdnztf_si
8441 || icode == CODE_FOR_bdnztf_di))
8447 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8449 static GTY(()) rtx rs6000_tls_symbol;
8451 rs6000_tls_get_addr (void)
8453 if (!rs6000_tls_symbol)
8454 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8456 return rs6000_tls_symbol;
8459 /* Construct the SYMBOL_REF for TLS GOT references. */
8461 static GTY(()) rtx rs6000_got_symbol;
8463 rs6000_got_sym (void)
8465 if (!rs6000_got_symbol)
8467 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8468 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8469 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8472 return rs6000_got_symbol;
8475 /* AIX Thread-Local Address support. */
8478 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8480 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8484 name = XSTR (addr, 0);
8485 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8486 or the symbol will be in TLS private data section. */
8487 if (name[strlen (name) - 1] != ']'
8488 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8489 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8491 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8492 strcpy (tlsname, name);
8494 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8495 tlsaddr = copy_rtx (addr);
8496 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8501 /* Place addr into TOC constant pool. */
8502 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8504 /* Output the TOC entry and create the MEM referencing the value. */
8505 if (constant_pool_expr_p (XEXP (sym, 0))
8506 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8508 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8509 mem = gen_const_mem (Pmode, tocref);
8510 set_mem_alias_set (mem, get_TOC_alias_set ());
8515 /* Use global-dynamic for local-dynamic. */
8516 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8517 || model == TLS_MODEL_LOCAL_DYNAMIC)
8519 /* Create new TOC reference for @m symbol. */
8520 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8521 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8522 strcpy (tlsname, "*LCM");
8523 strcat (tlsname, name + 3);
8524 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8525 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8526 tocref = create_TOC_reference (modaddr, NULL_RTX);
8527 rtx modmem = gen_const_mem (Pmode, tocref);
8528 set_mem_alias_set (modmem, get_TOC_alias_set ());
8530 rtx modreg = gen_reg_rtx (Pmode);
8531 emit_insn (gen_rtx_SET (modreg, modmem));
8533 tmpreg = gen_reg_rtx (Pmode);
8534 emit_insn (gen_rtx_SET (tmpreg, mem));
8536 dest = gen_reg_rtx (Pmode);
8538 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8540 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8543 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8544 else if (TARGET_32BIT)
8546 tlsreg = gen_reg_rtx (SImode);
8547 emit_insn (gen_tls_get_tpointer (tlsreg));
8550 tlsreg = gen_rtx_REG (DImode, 13);
8552 /* Load the TOC value into temporary register. */
8553 tmpreg = gen_reg_rtx (Pmode);
8554 emit_insn (gen_rtx_SET (tmpreg, mem));
8555 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8556 gen_rtx_MINUS (Pmode, addr, tlsreg));
8558 /* Add TOC symbol value to TLS pointer. */
8559 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8564 /* Output arg setup instructions for a !TARGET_TLS_MARKERS
8565 __tls_get_addr call. */
8568 rs6000_output_tlsargs (rtx *operands)
8570 /* Set up operands for output_asm_insn, without modifying OPERANDS. */
8573 /* The set dest of the call, ie. r3, which is also the first arg reg. */
8574 op[0] = operands[0];
8575 /* The TLS symbol from global_tlsarg stashed as CALL operand 2. */
8576 op[1] = XVECEXP (operands[2], 0, 0);
8577 if (XINT (operands[2], 1) == UNSPEC_TLSGD)
8579 /* The GOT register. */
8580 op[2] = XVECEXP (operands[2], 0, 1);
8581 if (TARGET_CMODEL != CMODEL_SMALL)
8582 output_asm_insn ("addis %0,%2,%1@got@tlsgd@ha\n\t"
8583 "addi %0,%0,%1@got@tlsgd@l", op);
8585 output_asm_insn ("addi %0,%2,%1@got@tlsgd", op);
8587 else if (XINT (operands[2], 1) == UNSPEC_TLSLD)
8589 if (TARGET_CMODEL != CMODEL_SMALL)
8590 output_asm_insn ("addis %0,%1,%&@got@tlsld@ha\n\t"
8591 "addi %0,%0,%&@got@tlsld@l", op);
8593 output_asm_insn ("addi %0,%1,%&@got@tlsld", op);
8599 /* Passes the tls arg value for global dynamic and local dynamic
8600 emit_library_call_value in rs6000_legitimize_tls_address to
8601 rs6000_call_aix and rs6000_call_sysv. This is used to emit the
8602 marker relocs put on __tls_get_addr calls. */
8603 static rtx global_tlsarg;
8605 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8606 this (thread-local) address. */
8609 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8614 return rs6000_legitimize_tls_address_aix (addr, model);
8616 dest = gen_reg_rtx (Pmode);
8617 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8623 tlsreg = gen_rtx_REG (Pmode, 13);
8624 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8628 tlsreg = gen_rtx_REG (Pmode, 2);
8629 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8633 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8637 tmp = gen_reg_rtx (Pmode);
8640 tlsreg = gen_rtx_REG (Pmode, 13);
8641 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8645 tlsreg = gen_rtx_REG (Pmode, 2);
8646 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8650 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8652 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8657 rtx got, tga, tmp1, tmp2;
8659 /* We currently use relocations like @got@tlsgd for tls, which
8660 means the linker will handle allocation of tls entries, placing
8661 them in the .got section. So use a pointer to the .got section,
8662 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8663 or to secondary GOT sections used by 32-bit -fPIC. */
8665 got = gen_rtx_REG (Pmode, 2);
8669 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8672 rtx gsym = rs6000_got_sym ();
8673 got = gen_reg_rtx (Pmode);
8675 rs6000_emit_move (got, gsym, Pmode);
8680 tmp1 = gen_reg_rtx (Pmode);
8681 tmp2 = gen_reg_rtx (Pmode);
8682 mem = gen_const_mem (Pmode, tmp1);
8683 lab = gen_label_rtx ();
8684 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
8685 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
8686 if (TARGET_LINK_STACK)
8687 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
8688 emit_move_insn (tmp2, mem);
8689 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
8690 set_unique_reg_note (last, REG_EQUAL, gsym);
8695 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
8697 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addr, got),
8699 tga = rs6000_tls_get_addr ();
8700 global_tlsarg = arg;
8701 if (TARGET_TLS_MARKERS)
8703 rtx argreg = gen_rtx_REG (Pmode, 3);
8704 emit_insn (gen_rtx_SET (argreg, arg));
8705 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
8709 emit_library_call_value (tga, dest, LCT_CONST, Pmode);
8710 global_tlsarg = NULL_RTX;
8712 /* Make a note so that the result of this call can be CSEd. */
8713 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8714 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8715 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8717 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
8719 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got), UNSPEC_TLSLD);
8720 tga = rs6000_tls_get_addr ();
8721 tmp1 = gen_reg_rtx (Pmode);
8722 global_tlsarg = arg;
8723 if (TARGET_TLS_MARKERS)
8725 rtx argreg = gen_rtx_REG (Pmode, 3);
8726 emit_insn (gen_rtx_SET (argreg, arg));
8727 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
8731 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode);
8732 global_tlsarg = NULL_RTX;
8734 /* Make a note so that the result of this call can be CSEd. */
8735 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8736 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8737 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8739 if (rs6000_tls_size == 16)
8742 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
8744 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
8746 else if (rs6000_tls_size == 32)
8748 tmp2 = gen_reg_rtx (Pmode);
8750 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
8752 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
8755 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
8757 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
8761 tmp2 = gen_reg_rtx (Pmode);
8763 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
8765 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
8767 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
8773 /* IE, or 64-bit offset LE. */
8774 tmp2 = gen_reg_rtx (Pmode);
8776 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
8778 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
8781 insn = gen_tls_tls_64 (dest, tmp2, addr);
8783 insn = gen_tls_tls_32 (dest, tmp2, addr);
8791 /* Only create the global variable for the stack protect guard if we are using
8792 the global flavor of that guard. */
8794 rs6000_init_stack_protect_guard (void)
8796 if (rs6000_stack_protector_guard == SSP_GLOBAL)
8797 return default_stack_protect_guard ();
8802 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8805 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
8807 if (GET_CODE (x) == HIGH
8808 && GET_CODE (XEXP (x, 0)) == UNSPEC)
8811 /* A TLS symbol in the TOC cannot contain a sum. */
8812 if (GET_CODE (x) == CONST
8813 && GET_CODE (XEXP (x, 0)) == PLUS
8814 && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
8815 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
8818 /* Do not place an ELF TLS symbol in the constant pool. */
8819 return TARGET_ELF && tls_referenced_p (x);
8822 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8823 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8824 can be addressed relative to the toc pointer. */
8827 use_toc_relative_ref (rtx sym, machine_mode mode)
8829 return ((constant_pool_expr_p (sym)
8830 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
8831 get_pool_mode (sym)))
8832 || (TARGET_CMODEL == CMODEL_MEDIUM
8833 && SYMBOL_REF_LOCAL_P (sym)
8834 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
8837 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
8838 that is a valid memory address for an instruction.
8839 The MODE argument is the machine mode for the MEM expression
8840 that wants to use this address.
8842 On the RS/6000, there are four valid address: a SYMBOL_REF that
8843 refers to a constant pool entry of an address (or the sum of it
8844 plus a constant), a short (16-bit signed) constant plus a register,
8845 the sum of two registers, or a register indirect, possibly with an
8846 auto-increment. For DFmode, DDmode and DImode with a constant plus
8847 register, we must ensure that both words are addressable or PowerPC64
8848 with offset word aligned.
8850 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
8851 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
8852 because adjacent memory cells are accessed by adding word-sized offsets
8853 during assembly output. */
8855 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
8857 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
8858 bool quad_offset_p = mode_supports_dq_form (mode);
8860 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
8861 if (VECTOR_MEM_ALTIVEC_P (mode)
8862 && GET_CODE (x) == AND
8863 && CONST_INT_P (XEXP (x, 1))
8864 && INTVAL (XEXP (x, 1)) == -16)
8867 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
8869 if (legitimate_indirect_address_p (x, reg_ok_strict))
8872 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
8873 && mode_supports_pre_incdec_p (mode)
8874 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
8876 /* Handle restricted vector d-form offsets in ISA 3.0. */
8879 if (quad_address_p (x, mode, reg_ok_strict))
8882 else if (virtual_stack_registers_memory_p (x))
8885 else if (reg_offset_p)
8887 if (legitimate_small_data_p (mode, x))
8889 if (legitimate_constant_pool_address_p (x, mode,
8890 reg_ok_strict || lra_in_progress))
8894 /* For TImode, if we have TImode in VSX registers, only allow register
8895 indirect addresses. This will allow the values to go in either GPRs
8896 or VSX registers without reloading. The vector types would tend to
8897 go into VSX registers, so we allow REG+REG, while TImode seems
8898 somewhat split, in that some uses are GPR based, and some VSX based. */
8899 /* FIXME: We could loosen this by changing the following to
8900 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
8901 but currently we cannot allow REG+REG addressing for TImode. See
8902 PR72827 for complete details on how this ends up hoodwinking DSE. */
8903 if (mode == TImode && TARGET_VSX)
8905 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
8908 && GET_CODE (x) == PLUS
8909 && REG_P (XEXP (x, 0))
8910 && (XEXP (x, 0) == virtual_stack_vars_rtx
8911 || XEXP (x, 0) == arg_pointer_rtx)
8912 && CONST_INT_P (XEXP (x, 1)))
8914 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
8916 if (!FLOAT128_2REG_P (mode)
8917 && (TARGET_HARD_FLOAT
8919 || (mode != DFmode && mode != DDmode))
8920 && (TARGET_POWERPC64 || mode != DImode)
8921 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
8923 && !avoiding_indexed_address_p (mode)
8924 && legitimate_indexed_address_p (x, reg_ok_strict))
8926 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
8927 && mode_supports_pre_modify_p (mode)
8928 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
8929 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
8930 reg_ok_strict, false)
8931 || (!avoiding_indexed_address_p (mode)
8932 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
8933 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8935 if (reg_offset_p && !quad_offset_p
8936 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
8941 /* Debug version of rs6000_legitimate_address_p. */
8943 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
8946 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
8948 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
8949 "strict = %d, reload = %s, code = %s\n",
8950 ret ? "true" : "false",
8951 GET_MODE_NAME (mode),
8953 (reload_completed ? "after" : "before"),
8954 GET_RTX_NAME (GET_CODE (x)));
8960 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
8963 rs6000_mode_dependent_address_p (const_rtx addr,
8964 addr_space_t as ATTRIBUTE_UNUSED)
8966 return rs6000_mode_dependent_address_ptr (addr);
8969 /* Go to LABEL if ADDR (a legitimate address expression)
8970 has an effect that depends on the machine mode it is used for.
8972 On the RS/6000 this is true of all integral offsets (since AltiVec
8973 and VSX modes don't allow them) or is a pre-increment or decrement.
8975 ??? Except that due to conceptual problems in offsettable_address_p
8976 we can't really report the problems of integral offsets. So leave
8977 this assuming that the adjustable offset must be valid for the
8978 sub-words of a TFmode operand, which is what we had before. */
8981 rs6000_mode_dependent_address (const_rtx addr)
8983 switch (GET_CODE (addr))
8986 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
8987 is considered a legitimate address before reload, so there
8988 are no offset restrictions in that case. Note that this
8989 condition is safe in strict mode because any address involving
8990 virtual_stack_vars_rtx or arg_pointer_rtx would already have
8991 been rejected as illegitimate. */
8992 if (XEXP (addr, 0) != virtual_stack_vars_rtx
8993 && XEXP (addr, 0) != arg_pointer_rtx
8994 && CONST_INT_P (XEXP (addr, 1)))
8996 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
8997 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9002 /* Anything in the constant pool is sufficiently aligned that
9003 all bytes have the same high part address. */
9004 return !legitimate_constant_pool_address_p (addr, QImode, false);
9006 /* Auto-increment cases are now treated generically in recog.c. */
9008 return TARGET_UPDATE;
9010 /* AND is only allowed in Altivec loads. */
9021 /* Debug version of rs6000_mode_dependent_address. */
9023 rs6000_debug_mode_dependent_address (const_rtx addr)
9025 bool ret = rs6000_mode_dependent_address (addr);
9027 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9028 ret ? "true" : "false");
9034 /* Implement FIND_BASE_TERM. */
9037 rs6000_find_base_term (rtx op)
9042 if (GET_CODE (base) == CONST)
9043 base = XEXP (base, 0);
9044 if (GET_CODE (base) == PLUS)
9045 base = XEXP (base, 0);
9046 if (GET_CODE (base) == UNSPEC)
9047 switch (XINT (base, 1))
9050 case UNSPEC_MACHOPIC_OFFSET:
9051 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9052 for aliasing purposes. */
9053 return XVECEXP (base, 0, 0);
9059 /* More elaborate version of recog's offsettable_memref_p predicate
9060 that works around the ??? note of rs6000_mode_dependent_address.
9061 In particular it accepts
9063 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9065 in 32-bit mode, that the recog predicate rejects. */
9068 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9075 /* First mimic offsettable_memref_p. */
9076 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9079 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9080 the latter predicate knows nothing about the mode of the memory
9081 reference and, therefore, assumes that it is the largest supported
9082 mode (TFmode). As a consequence, legitimate offsettable memory
9083 references are rejected. rs6000_legitimate_offset_address_p contains
9084 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9085 at least with a little bit of help here given that we know the
9086 actual registers used. */
9087 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9088 || GET_MODE_SIZE (reg_mode) == 4);
9089 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9090 strict, worst_case);
9093 /* Determine the reassociation width to be used in reassociate_bb.
9094 This takes into account how many parallel operations we
9095 can actually do of a given type, and also the latency.
9099 vect add/sub/mul 2/cycle
9100 fp add/sub/mul 2/cycle
9105 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9108 switch (rs6000_tune)
9110 case PROCESSOR_POWER8:
9111 case PROCESSOR_POWER9:
9112 if (DECIMAL_FLOAT_MODE_P (mode))
9114 if (VECTOR_MODE_P (mode))
9116 if (INTEGRAL_MODE_P (mode))
9118 if (FLOAT_MODE_P (mode))
9127 /* Change register usage conditional on target flags. */
9129 rs6000_conditional_register_usage (void)
9133 if (TARGET_DEBUG_TARGET)
9134 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9136 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9138 fixed_regs[13] = call_used_regs[13]
9139 = call_really_used_regs[13] = 1;
9141 /* Conditionally disable FPRs. */
9142 if (TARGET_SOFT_FLOAT)
9143 for (i = 32; i < 64; i++)
9144 fixed_regs[i] = call_used_regs[i]
9145 = call_really_used_regs[i] = 1;
9147 /* The TOC register is not killed across calls in a way that is
9148 visible to the compiler. */
9149 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9150 call_really_used_regs[2] = 0;
9152 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9153 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9155 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9156 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9157 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9158 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9160 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9161 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9162 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9163 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9165 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9166 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9167 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9169 if (!TARGET_ALTIVEC && !TARGET_VSX)
9171 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9172 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9173 call_really_used_regs[VRSAVE_REGNO] = 1;
9176 if (TARGET_ALTIVEC || TARGET_VSX)
9177 global_regs[VSCR_REGNO] = 1;
9179 if (TARGET_ALTIVEC_ABI)
9181 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9182 call_used_regs[i] = call_really_used_regs[i] = 1;
9184 /* AIX reserves VR20:31 in non-extended ABI mode. */
9186 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9187 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9192 /* Output insns to set DEST equal to the constant SOURCE as a series of
9193 lis, ori and shl instructions and return TRUE. */
9196 rs6000_emit_set_const (rtx dest, rtx source)
9198 machine_mode mode = GET_MODE (dest);
9203 gcc_checking_assert (CONST_INT_P (source));
9204 c = INTVAL (source);
9209 emit_insn (gen_rtx_SET (dest, source));
9213 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9215 emit_insn (gen_rtx_SET (copy_rtx (temp),
9216 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9217 emit_insn (gen_rtx_SET (dest,
9218 gen_rtx_IOR (SImode, copy_rtx (temp),
9219 GEN_INT (c & 0xffff))));
9223 if (!TARGET_POWERPC64)
9227 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9229 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9231 emit_move_insn (hi, GEN_INT (c >> 32));
9232 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9233 emit_move_insn (lo, GEN_INT (c));
9236 rs6000_emit_set_long_const (dest, c);
9243 insn = get_last_insn ();
9244 set = single_set (insn);
9245 if (! CONSTANT_P (SET_SRC (set)))
9246 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9251 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9252 Output insns to set DEST equal to the constant C as a series of
9253 lis, ori and shl instructions. */
9256 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9259 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9269 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9270 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9271 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9273 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9274 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9276 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9278 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9279 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9281 emit_move_insn (dest,
9282 gen_rtx_IOR (DImode, copy_rtx (temp),
9285 else if (ud3 == 0 && ud4 == 0)
9287 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9289 gcc_assert (ud2 & 0x8000);
9290 emit_move_insn (copy_rtx (temp),
9291 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9293 emit_move_insn (copy_rtx (temp),
9294 gen_rtx_IOR (DImode, copy_rtx (temp),
9296 emit_move_insn (dest,
9297 gen_rtx_ZERO_EXTEND (DImode,
9298 gen_lowpart (SImode,
9301 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9302 || (ud4 == 0 && ! (ud3 & 0x8000)))
9304 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9306 emit_move_insn (copy_rtx (temp),
9307 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9309 emit_move_insn (copy_rtx (temp),
9310 gen_rtx_IOR (DImode, copy_rtx (temp),
9312 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9313 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9316 emit_move_insn (dest,
9317 gen_rtx_IOR (DImode, copy_rtx (temp),
9322 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9324 emit_move_insn (copy_rtx (temp),
9325 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9327 emit_move_insn (copy_rtx (temp),
9328 gen_rtx_IOR (DImode, copy_rtx (temp),
9331 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9332 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9335 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9336 gen_rtx_IOR (DImode, copy_rtx (temp),
9337 GEN_INT (ud2 << 16)));
9339 emit_move_insn (dest,
9340 gen_rtx_IOR (DImode, copy_rtx (temp),
9345 /* Helper for the following. Get rid of [r+r] memory refs
9346 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9349 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9351 if (MEM_P (operands[0])
9352 && !REG_P (XEXP (operands[0], 0))
9353 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9354 GET_MODE (operands[0]), false))
9356 = replace_equiv_address (operands[0],
9357 copy_addr_to_reg (XEXP (operands[0], 0)));
9359 if (MEM_P (operands[1])
9360 && !REG_P (XEXP (operands[1], 0))
9361 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
9362 GET_MODE (operands[1]), false))
9364 = replace_equiv_address (operands[1],
9365 copy_addr_to_reg (XEXP (operands[1], 0)));
9368 /* Generate a vector of constants to permute MODE for a little-endian
9369 storage operation by swapping the two halves of a vector. */
9371 rs6000_const_vec (machine_mode mode)
9399 v = rtvec_alloc (subparts);
9401 for (i = 0; i < subparts / 2; ++i)
9402 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
9403 for (i = subparts / 2; i < subparts; ++i)
9404 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
9409 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9412 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
9414 /* Scalar permutations are easier to express in integer modes rather than
9415 floating-point modes, so cast them here. We use V1TImode instead
9416 of TImode to ensure that the values don't go through GPRs. */
9417 if (FLOAT128_VECTOR_P (mode))
9419 dest = gen_lowpart (V1TImode, dest);
9420 source = gen_lowpart (V1TImode, source);
9424 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9426 if (mode == TImode || mode == V1TImode)
9427 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
9431 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
9432 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
9436 /* Emit a little-endian load from vector memory location SOURCE to VSX
9437 register DEST in mode MODE. The load is done with two permuting
9438 insn's that represent an lxvd2x and xxpermdi. */
9440 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
9442 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9444 if (mode == TImode || mode == V1TImode)
9447 dest = gen_lowpart (V2DImode, dest);
9448 source = adjust_address (source, V2DImode, 0);
9451 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
9452 rs6000_emit_le_vsx_permute (tmp, source, mode);
9453 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9456 /* Emit a little-endian store to vector memory location DEST from VSX
9457 register SOURCE in mode MODE. The store is done with two permuting
9458 insn's that represent an xxpermdi and an stxvd2x. */
9460 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
9462 /* This should never be called during or after LRA, because it does
9463 not re-permute the source register. It is intended only for use
9465 gcc_assert (!lra_in_progress && !reload_completed);
9467 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9469 if (mode == TImode || mode == V1TImode)
9472 dest = adjust_address (dest, V2DImode, 0);
9473 source = gen_lowpart (V2DImode, source);
9476 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
9477 rs6000_emit_le_vsx_permute (tmp, source, mode);
9478 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9481 /* Emit a sequence representing a little-endian VSX load or store,
9482 moving data from SOURCE to DEST in mode MODE. This is done
9483 separately from rs6000_emit_move to ensure it is called only
9484 during expand. LE VSX loads and stores introduced later are
9485 handled with a split. The expand-time RTL generation allows
9486 us to optimize away redundant pairs of register-permutes. */
9488 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
9490 gcc_assert (!BYTES_BIG_ENDIAN
9491 && VECTOR_MEM_VSX_P (mode)
9492 && !TARGET_P9_VECTOR
9493 && !gpr_or_gpr_p (dest, source)
9494 && (MEM_P (source) ^ MEM_P (dest)));
9498 gcc_assert (REG_P (dest) || SUBREG_P (dest));
9499 rs6000_emit_le_vsx_load (dest, source, mode);
9503 if (!REG_P (source))
9504 source = force_reg (mode, source);
9505 rs6000_emit_le_vsx_store (dest, source, mode);
9509 /* Return whether a SFmode or SImode move can be done without converting one
9510 mode to another. This arrises when we have:
9512 (SUBREG:SF (REG:SI ...))
9513 (SUBREG:SI (REG:SF ...))
9515 and one of the values is in a floating point/vector register, where SFmode
9516 scalars are stored in DFmode format. */
9519 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
9521 if (TARGET_ALLOW_SF_SUBREG)
9524 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
9527 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
9530 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9531 if (SUBREG_P (dest))
9533 rtx dest_subreg = SUBREG_REG (dest);
9534 rtx src_subreg = SUBREG_REG (src);
9535 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
9542 /* Helper function to change moves with:
9544 (SUBREG:SF (REG:SI)) and
9545 (SUBREG:SI (REG:SF))
9547 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9548 values are stored as DFmode values in the VSX registers. We need to convert
9549 the bits before we can use a direct move or operate on the bits in the
9550 vector register as an integer type.
9552 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9555 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
9557 if (TARGET_DIRECT_MOVE_64BIT && !reload_completed
9558 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
9559 && SUBREG_P (source) && sf_subreg_operand (source, mode))
9561 rtx inner_source = SUBREG_REG (source);
9562 machine_mode inner_mode = GET_MODE (inner_source);
9564 if (mode == SImode && inner_mode == SFmode)
9566 emit_insn (gen_movsi_from_sf (dest, inner_source));
9570 if (mode == SFmode && inner_mode == SImode)
9572 emit_insn (gen_movsf_from_si (dest, inner_source));
9580 /* Emit a move from SOURCE to DEST in mode MODE. */
9582 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
9586 operands[1] = source;
9588 if (TARGET_DEBUG_ADDR)
9591 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9592 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9593 GET_MODE_NAME (mode),
9596 can_create_pseudo_p ());
9598 fprintf (stderr, "source:\n");
9602 /* Check that we get CONST_WIDE_INT only when we should. */
9603 if (CONST_WIDE_INT_P (operands[1])
9604 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9607 #ifdef HAVE_AS_GNU_ATTRIBUTE
9608 /* If we use a long double type, set the flags in .gnu_attribute that say
9609 what the long double type is. This is to allow the linker's warning
9610 message for the wrong long double to be useful, even if the function does
9611 not do a call (for example, doing a 128-bit add on power9 if the long
9612 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9613 used if they aren't the default long dobule type. */
9614 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
9616 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
9617 rs6000_passes_float = rs6000_passes_long_double = true;
9619 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
9620 rs6000_passes_float = rs6000_passes_long_double = true;
9624 /* See if we need to special case SImode/SFmode SUBREG moves. */
9625 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
9626 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
9629 /* Check if GCC is setting up a block move that will end up using FP
9630 registers as temporaries. We must make sure this is acceptable. */
9631 if (MEM_P (operands[0])
9632 && MEM_P (operands[1])
9634 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
9635 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
9636 && ! (rs6000_slow_unaligned_access (SImode,
9637 (MEM_ALIGN (operands[0]) > 32
9638 ? 32 : MEM_ALIGN (operands[0])))
9639 || rs6000_slow_unaligned_access (SImode,
9640 (MEM_ALIGN (operands[1]) > 32
9641 ? 32 : MEM_ALIGN (operands[1]))))
9642 && ! MEM_VOLATILE_P (operands [0])
9643 && ! MEM_VOLATILE_P (operands [1]))
9645 emit_move_insn (adjust_address (operands[0], SImode, 0),
9646 adjust_address (operands[1], SImode, 0));
9647 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
9648 adjust_address (copy_rtx (operands[1]), SImode, 4));
9652 if (can_create_pseudo_p () && MEM_P (operands[0])
9653 && !gpc_reg_operand (operands[1], mode))
9654 operands[1] = force_reg (mode, operands[1]);
9656 /* Recognize the case where operand[1] is a reference to thread-local
9657 data and load its address to a register. */
9658 if (tls_referenced_p (operands[1]))
9660 enum tls_model model;
9661 rtx tmp = operands[1];
9664 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
9666 addend = XEXP (XEXP (tmp, 0), 1);
9667 tmp = XEXP (XEXP (tmp, 0), 0);
9670 gcc_assert (SYMBOL_REF_P (tmp));
9671 model = SYMBOL_REF_TLS_MODEL (tmp);
9672 gcc_assert (model != 0);
9674 tmp = rs6000_legitimize_tls_address (tmp, model);
9677 tmp = gen_rtx_PLUS (mode, tmp, addend);
9678 tmp = force_operand (tmp, operands[0]);
9683 /* 128-bit constant floating-point values on Darwin should really be loaded
9684 as two parts. However, this premature splitting is a problem when DFmode
9685 values can go into Altivec registers. */
9686 if (TARGET_MACHO && CONST_DOUBLE_P (operands[1]) && FLOAT128_IBM_P (mode)
9687 && !reg_addr[DFmode].scalar_in_vmx_p)
9689 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
9690 simplify_gen_subreg (DFmode, operands[1], mode, 0),
9692 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
9693 GET_MODE_SIZE (DFmode)),
9694 simplify_gen_subreg (DFmode, operands[1], mode,
9695 GET_MODE_SIZE (DFmode)),
9700 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9701 p1:SD) if p1 is not of floating point class and p0 is spilled as
9702 we can have no analogous movsd_store for this. */
9703 if (lra_in_progress && mode == DDmode
9704 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9705 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9706 && SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))
9707 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
9710 int regno = REGNO (SUBREG_REG (operands[1]));
9712 if (!HARD_REGISTER_NUM_P (regno))
9714 cl = reg_preferred_class (regno);
9715 regno = reg_renumber[regno];
9717 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
9719 if (regno >= 0 && ! FP_REGNO_P (regno))
9722 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
9723 operands[1] = SUBREG_REG (operands[1]);
9728 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9729 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9730 && (REG_P (operands[1])
9731 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))))
9733 int regno = reg_or_subregno (operands[1]);
9736 if (!HARD_REGISTER_NUM_P (regno))
9738 cl = reg_preferred_class (regno);
9739 gcc_assert (cl != NO_REGS);
9740 regno = reg_renumber[regno];
9742 regno = ira_class_hard_regs[cl][0];
9744 if (FP_REGNO_P (regno))
9746 if (GET_MODE (operands[0]) != DDmode)
9747 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
9748 emit_insn (gen_movsd_store (operands[0], operands[1]));
9750 else if (INT_REGNO_P (regno))
9751 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9756 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
9757 p:DD)) if p0 is not of floating point class and p1 is spilled as
9758 we can have no analogous movsd_load for this. */
9759 if (lra_in_progress && mode == DDmode
9760 && SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))
9761 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
9762 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9763 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9766 int regno = REGNO (SUBREG_REG (operands[0]));
9768 if (!HARD_REGISTER_NUM_P (regno))
9770 cl = reg_preferred_class (regno);
9771 regno = reg_renumber[regno];
9773 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
9775 if (regno >= 0 && ! FP_REGNO_P (regno))
9778 operands[0] = SUBREG_REG (operands[0]);
9779 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
9784 && (REG_P (operands[0])
9785 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
9786 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9787 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9789 int regno = reg_or_subregno (operands[0]);
9792 if (!HARD_REGISTER_NUM_P (regno))
9794 cl = reg_preferred_class (regno);
9795 gcc_assert (cl != NO_REGS);
9796 regno = reg_renumber[regno];
9798 regno = ira_class_hard_regs[cl][0];
9800 if (FP_REGNO_P (regno))
9802 if (GET_MODE (operands[1]) != DDmode)
9803 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
9804 emit_insn (gen_movsd_load (operands[0], operands[1]));
9806 else if (INT_REGNO_P (regno))
9807 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9813 /* FIXME: In the long term, this switch statement should go away
9814 and be replaced by a sequence of tests based on things like
9820 if (CONSTANT_P (operands[1])
9821 && !CONST_INT_P (operands[1]))
9822 operands[1] = force_const_mem (mode, operands[1]);
9829 if (FLOAT128_2REG_P (mode))
9830 rs6000_eliminate_indexed_memrefs (operands);
9837 if (CONSTANT_P (operands[1])
9838 && ! easy_fp_constant (operands[1], mode))
9839 operands[1] = force_const_mem (mode, operands[1]);
9849 if (CONSTANT_P (operands[1])
9850 && !easy_vector_constant (operands[1], mode))
9851 operands[1] = force_const_mem (mode, operands[1]);
9856 /* Use default pattern for address of ELF small data */
9859 && DEFAULT_ABI == ABI_V4
9860 && (SYMBOL_REF_P (operands[1])
9861 || GET_CODE (operands[1]) == CONST)
9862 && small_data_operand (operands[1], mode))
9864 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9868 if (DEFAULT_ABI == ABI_V4
9869 && mode == Pmode && mode == SImode
9870 && flag_pic == 1 && got_operand (operands[1], mode))
9872 emit_insn (gen_movsi_got (operands[0], operands[1]));
9876 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
9880 && CONSTANT_P (operands[1])
9881 && GET_CODE (operands[1]) != HIGH
9882 && !CONST_INT_P (operands[1]))
9884 rtx target = (!can_create_pseudo_p ()
9886 : gen_reg_rtx (mode));
9888 /* If this is a function address on -mcall-aixdesc,
9889 convert it to the address of the descriptor. */
9890 if (DEFAULT_ABI == ABI_AIX
9891 && SYMBOL_REF_P (operands[1])
9892 && XSTR (operands[1], 0)[0] == '.')
9894 const char *name = XSTR (operands[1], 0);
9896 while (*name == '.')
9898 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
9899 CONSTANT_POOL_ADDRESS_P (new_ref)
9900 = CONSTANT_POOL_ADDRESS_P (operands[1]);
9901 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
9902 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
9903 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
9904 operands[1] = new_ref;
9907 if (DEFAULT_ABI == ABI_DARWIN)
9910 if (MACHO_DYNAMIC_NO_PIC_P)
9912 /* Take care of any required data indirection. */
9913 operands[1] = rs6000_machopic_legitimize_pic_address (
9914 operands[1], mode, operands[0]);
9915 if (operands[0] != operands[1])
9916 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9920 emit_insn (gen_macho_high (target, operands[1]));
9921 emit_insn (gen_macho_low (operands[0], target, operands[1]));
9925 emit_insn (gen_elf_high (target, operands[1]));
9926 emit_insn (gen_elf_low (operands[0], target, operands[1]));
9930 /* If this is a SYMBOL_REF that refers to a constant pool entry,
9931 and we have put it in the TOC, we just need to make a TOC-relative
9934 && SYMBOL_REF_P (operands[1])
9935 && use_toc_relative_ref (operands[1], mode))
9936 operands[1] = create_TOC_reference (operands[1], operands[0]);
9937 else if (mode == Pmode
9938 && CONSTANT_P (operands[1])
9939 && GET_CODE (operands[1]) != HIGH
9940 && ((REG_P (operands[0])
9941 && FP_REGNO_P (REGNO (operands[0])))
9942 || !CONST_INT_P (operands[1])
9943 || (num_insns_constant (operands[1], mode)
9944 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
9945 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
9946 && (TARGET_CMODEL == CMODEL_SMALL
9947 || can_create_pseudo_p ()
9948 || (REG_P (operands[0])
9949 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
9953 /* Darwin uses a special PIC legitimizer. */
9954 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
9957 rs6000_machopic_legitimize_pic_address (operands[1], mode,
9959 if (operands[0] != operands[1])
9960 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9965 /* If we are to limit the number of things we put in the TOC and
9966 this is a symbol plus a constant we can add in one insn,
9967 just put the symbol in the TOC and add the constant. */
9968 if (GET_CODE (operands[1]) == CONST
9969 && TARGET_NO_SUM_IN_TOC
9970 && GET_CODE (XEXP (operands[1], 0)) == PLUS
9971 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
9972 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
9973 || SYMBOL_REF_P (XEXP (XEXP (operands[1], 0), 0)))
9974 && ! side_effects_p (operands[0]))
9977 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
9978 rtx other = XEXP (XEXP (operands[1], 0), 1);
9980 sym = force_reg (mode, sym);
9981 emit_insn (gen_add3_insn (operands[0], sym, other));
9985 operands[1] = force_const_mem (mode, operands[1]);
9988 && SYMBOL_REF_P (XEXP (operands[1], 0))
9989 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
9991 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
9993 operands[1] = gen_const_mem (mode, tocref);
9994 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10000 if (!VECTOR_MEM_VSX_P (TImode))
10001 rs6000_eliminate_indexed_memrefs (operands);
10005 rs6000_eliminate_indexed_memrefs (operands);
10009 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10012 /* Above, we may have called force_const_mem which may have returned
10013 an invalid address. If we can, fix this up; otherwise, reload will
10014 have to deal with it. */
10015 if (MEM_P (operands[1]))
10016 operands[1] = validize_mem (operands[1]);
10018 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10021 /* Nonzero if we can use a floating-point register to pass this arg. */
10022 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10023 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10024 && (CUM)->fregno <= FP_ARG_MAX_REG \
10025 && TARGET_HARD_FLOAT)
10027 /* Nonzero if we can use an AltiVec register to pass this arg. */
10028 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10029 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10030 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10031 && TARGET_ALTIVEC_ABI \
10034 /* Walk down the type tree of TYPE counting consecutive base elements.
10035 If *MODEP is VOIDmode, then set it to the first valid floating point
10036 or vector type. If a non-floating point or vector type is found, or
10037 if a floating point or vector type that doesn't match a non-VOIDmode
10038 *MODEP is found, then return -1, otherwise return the count in the
10042 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10045 HOST_WIDE_INT size;
10047 switch (TREE_CODE (type))
10050 mode = TYPE_MODE (type);
10051 if (!SCALAR_FLOAT_MODE_P (mode))
10054 if (*modep == VOIDmode)
10057 if (*modep == mode)
10063 mode = TYPE_MODE (TREE_TYPE (type));
10064 if (!SCALAR_FLOAT_MODE_P (mode))
10067 if (*modep == VOIDmode)
10070 if (*modep == mode)
10076 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10079 /* Use V4SImode as representative of all 128-bit vector types. */
10080 size = int_size_in_bytes (type);
10090 if (*modep == VOIDmode)
10093 /* Vector modes are considered to be opaque: two vectors are
10094 equivalent for the purposes of being homogeneous aggregates
10095 if they are the same size. */
10096 if (*modep == mode)
10104 tree index = TYPE_DOMAIN (type);
10106 /* Can't handle incomplete types nor sizes that are not
10108 if (!COMPLETE_TYPE_P (type)
10109 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10112 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10115 || !TYPE_MAX_VALUE (index)
10116 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10117 || !TYPE_MIN_VALUE (index)
10118 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10122 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10123 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10125 /* There must be no padding. */
10126 if (wi::to_wide (TYPE_SIZE (type))
10127 != count * GET_MODE_BITSIZE (*modep))
10139 /* Can't handle incomplete types nor sizes that are not
10141 if (!COMPLETE_TYPE_P (type)
10142 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10145 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10147 if (TREE_CODE (field) != FIELD_DECL)
10150 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10153 count += sub_count;
10156 /* There must be no padding. */
10157 if (wi::to_wide (TYPE_SIZE (type))
10158 != count * GET_MODE_BITSIZE (*modep))
10165 case QUAL_UNION_TYPE:
10167 /* These aren't very interesting except in a degenerate case. */
10172 /* Can't handle incomplete types nor sizes that are not
10174 if (!COMPLETE_TYPE_P (type)
10175 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10178 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10180 if (TREE_CODE (field) != FIELD_DECL)
10183 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10186 count = count > sub_count ? count : sub_count;
10189 /* There must be no padding. */
10190 if (wi::to_wide (TYPE_SIZE (type))
10191 != count * GET_MODE_BITSIZE (*modep))
10204 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10205 float or vector aggregate that shall be passed in FP/vector registers
10206 according to the ELFv2 ABI, return the homogeneous element mode in
10207 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10209 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10212 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10213 machine_mode *elt_mode,
10216 /* Note that we do not accept complex types at the top level as
10217 homogeneous aggregates; these types are handled via the
10218 targetm.calls.split_complex_arg mechanism. Complex types
10219 can be elements of homogeneous aggregates, however. */
10220 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10221 && AGGREGATE_TYPE_P (type))
10223 machine_mode field_mode = VOIDmode;
10224 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10226 if (field_count > 0)
10228 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
10229 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
10231 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10232 up to AGGR_ARG_NUM_REG registers. */
10233 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
10236 *elt_mode = field_mode;
10238 *n_elts = field_count;
10251 /* Return a nonzero value to say to return the function value in
10252 memory, just as large structures are always returned. TYPE will be
10253 the data type of the value, and FNTYPE will be the type of the
10254 function doing the returning, or @code{NULL} for libcalls.
10256 The AIX ABI for the RS/6000 specifies that all structures are
10257 returned in memory. The Darwin ABI does the same.
10259 For the Darwin 64 Bit ABI, a function result can be returned in
10260 registers or in memory, depending on the size of the return data
10261 type. If it is returned in registers, the value occupies the same
10262 registers as it would if it were the first and only function
10263 argument. Otherwise, the function places its result in memory at
10264 the location pointed to by GPR3.
10266 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10267 but a draft put them in memory, and GCC used to implement the draft
10268 instead of the final standard. Therefore, aix_struct_return
10269 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10270 compatibility can change DRAFT_V4_STRUCT_RET to override the
10271 default, and -m switches get the final word. See
10272 rs6000_option_override_internal for more details.
10274 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10275 long double support is enabled. These values are returned in memory.
10277 int_size_in_bytes returns -1 for variable size objects, which go in
10278 memory always. The cast to unsigned makes -1 > 8. */
10281 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10283 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10285 && rs6000_darwin64_abi
10286 && TREE_CODE (type) == RECORD_TYPE
10287 && int_size_in_bytes (type) > 0)
10289 CUMULATIVE_ARGS valcum;
10293 valcum.fregno = FP_ARG_MIN_REG;
10294 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10295 /* Do a trial code generation as if this were going to be passed
10296 as an argument; if any part goes in memory, we return NULL. */
10297 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10300 /* Otherwise fall through to more conventional ABI rules. */
10303 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10304 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10308 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10309 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10310 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10313 if (AGGREGATE_TYPE_P (type)
10314 && (aix_struct_return
10315 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10318 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10319 modes only exist for GCC vector types if -maltivec. */
10320 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10321 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10324 /* Return synthetic vectors in memory. */
10325 if (TREE_CODE (type) == VECTOR_TYPE
10326 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10328 static bool warned_for_return_big_vectors = false;
10329 if (!warned_for_return_big_vectors)
10331 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10332 "non-standard ABI extension with no compatibility "
10334 warned_for_return_big_vectors = true;
10339 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10340 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10346 /* Specify whether values returned in registers should be at the most
10347 significant end of a register. We want aggregates returned by
10348 value to match the way aggregates are passed to functions. */
10351 rs6000_return_in_msb (const_tree valtype)
10353 return (DEFAULT_ABI == ABI_ELFv2
10354 && BYTES_BIG_ENDIAN
10355 && AGGREGATE_TYPE_P (valtype)
10356 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
10360 #ifdef HAVE_AS_GNU_ATTRIBUTE
10361 /* Return TRUE if a call to function FNDECL may be one that
10362 potentially affects the function calling ABI of the object file. */
10365 call_ABI_of_interest (tree fndecl)
10367 if (rs6000_gnu_attr && symtab->state == EXPANSION)
10369 struct cgraph_node *c_node;
10371 /* Libcalls are always interesting. */
10372 if (fndecl == NULL_TREE)
10375 /* Any call to an external function is interesting. */
10376 if (DECL_EXTERNAL (fndecl))
10379 /* Interesting functions that we are emitting in this object file. */
10380 c_node = cgraph_node::get (fndecl);
10381 c_node = c_node->ultimate_alias_target ();
10382 return !c_node->only_called_directly_p ();
10388 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10389 for a call to a function whose data type is FNTYPE.
10390 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10392 For incoming args we set the number of arguments in the prototype large
10393 so we never return a PARALLEL. */
10396 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
10397 rtx libname ATTRIBUTE_UNUSED, int incoming,
10398 int libcall, int n_named_args,
10400 machine_mode return_mode ATTRIBUTE_UNUSED)
10402 static CUMULATIVE_ARGS zero_cumulative;
10404 *cum = zero_cumulative;
10406 cum->fregno = FP_ARG_MIN_REG;
10407 cum->vregno = ALTIVEC_ARG_MIN_REG;
10408 cum->prototype = (fntype && prototype_p (fntype));
10409 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
10410 ? CALL_LIBCALL : CALL_NORMAL);
10411 cum->sysv_gregno = GP_ARG_MIN_REG;
10412 cum->stdarg = stdarg_p (fntype);
10413 cum->libcall = libcall;
10415 cum->nargs_prototype = 0;
10416 if (incoming || cum->prototype)
10417 cum->nargs_prototype = n_named_args;
10419 /* Check for a longcall attribute. */
10420 if ((!fntype && rs6000_default_long_calls)
10422 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
10423 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
10424 cum->call_cookie |= CALL_LONG;
10425 else if (DEFAULT_ABI != ABI_DARWIN)
10427 bool is_local = (fndecl
10428 && !DECL_EXTERNAL (fndecl)
10429 && !DECL_WEAK (fndecl)
10430 && (*targetm.binds_local_p) (fndecl));
10436 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
10437 cum->call_cookie |= CALL_LONG;
10442 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
10443 cum->call_cookie |= CALL_LONG;
10447 if (TARGET_DEBUG_ARG)
10449 fprintf (stderr, "\ninit_cumulative_args:");
10452 tree ret_type = TREE_TYPE (fntype);
10453 fprintf (stderr, " ret code = %s,",
10454 get_tree_code_name (TREE_CODE (ret_type)));
10457 if (cum->call_cookie & CALL_LONG)
10458 fprintf (stderr, " longcall,");
10460 fprintf (stderr, " proto = %d, nargs = %d\n",
10461 cum->prototype, cum->nargs_prototype);
10464 #ifdef HAVE_AS_GNU_ATTRIBUTE
10465 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
10467 cum->escapes = call_ABI_of_interest (fndecl);
10474 return_type = TREE_TYPE (fntype);
10475 return_mode = TYPE_MODE (return_type);
10478 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
10480 if (return_type != NULL)
10482 if (TREE_CODE (return_type) == RECORD_TYPE
10483 && TYPE_TRANSPARENT_AGGR (return_type))
10485 return_type = TREE_TYPE (first_field (return_type));
10486 return_mode = TYPE_MODE (return_type);
10488 if (AGGREGATE_TYPE_P (return_type)
10489 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
10491 rs6000_returns_struct = true;
10493 if (SCALAR_FLOAT_MODE_P (return_mode))
10495 rs6000_passes_float = true;
10496 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10497 && (FLOAT128_IBM_P (return_mode)
10498 || FLOAT128_IEEE_P (return_mode)
10499 || (return_type != NULL
10500 && (TYPE_MAIN_VARIANT (return_type)
10501 == long_double_type_node))))
10502 rs6000_passes_long_double = true;
10504 /* Note if we passed or return a IEEE 128-bit type. We changed
10505 the mangling for these types, and we may need to make an alias
10506 with the old mangling. */
10507 if (FLOAT128_IEEE_P (return_mode))
10508 rs6000_passes_ieee128 = true;
10510 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
10511 rs6000_passes_vector = true;
10518 && TARGET_ALTIVEC_ABI
10519 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
10521 error ("cannot return value in vector register because"
10522 " altivec instructions are disabled, use %qs"
10523 " to enable them", "-maltivec");
10527 /* The mode the ABI uses for a word. This is not the same as word_mode
10528 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10530 static scalar_int_mode
10531 rs6000_abi_word_mode (void)
10533 return TARGET_32BIT ? SImode : DImode;
10536 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10538 rs6000_offload_options (void)
10541 return xstrdup ("-foffload-abi=lp64");
10543 return xstrdup ("-foffload-abi=ilp32");
10546 /* On rs6000, function arguments are promoted, as are function return
10549 static machine_mode
10550 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
10552 int *punsignedp ATTRIBUTE_UNUSED,
10555 PROMOTE_MODE (mode, *punsignedp, type);
10560 /* Return true if TYPE must be passed on the stack and not in registers. */
10563 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
10565 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
10566 return must_pass_in_stack_var_size (mode, type);
10568 return must_pass_in_stack_var_size_or_pad (mode, type);
10572 is_complex_IBM_long_double (machine_mode mode)
10574 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
10577 /* Whether ABI_V4 passes MODE args to a function in floating point
10581 abi_v4_pass_in_fpr (machine_mode mode, bool named)
10583 if (!TARGET_HARD_FLOAT)
10585 if (mode == DFmode)
10587 if (mode == SFmode && named)
10589 /* ABI_V4 passes complex IBM long double in 8 gprs.
10590 Stupid, but we can't change the ABI now. */
10591 if (is_complex_IBM_long_double (mode))
10593 if (FLOAT128_2REG_P (mode))
10595 if (DECIMAL_FLOAT_MODE_P (mode))
10600 /* Implement TARGET_FUNCTION_ARG_PADDING.
10602 For the AIX ABI structs are always stored left shifted in their
10605 static pad_direction
10606 rs6000_function_arg_padding (machine_mode mode, const_tree type)
10608 #ifndef AGGREGATE_PADDING_FIXED
10609 #define AGGREGATE_PADDING_FIXED 0
10611 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10612 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10615 if (!AGGREGATE_PADDING_FIXED)
10617 /* GCC used to pass structures of the same size as integer types as
10618 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10619 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10620 passed padded downward, except that -mstrict-align further
10621 muddied the water in that multi-component structures of 2 and 4
10622 bytes in size were passed padded upward.
10624 The following arranges for best compatibility with previous
10625 versions of gcc, but removes the -mstrict-align dependency. */
10626 if (BYTES_BIG_ENDIAN)
10628 HOST_WIDE_INT size = 0;
10630 if (mode == BLKmode)
10632 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
10633 size = int_size_in_bytes (type);
10636 size = GET_MODE_SIZE (mode);
10638 if (size == 1 || size == 2 || size == 4)
10639 return PAD_DOWNWARD;
10644 if (AGGREGATES_PAD_UPWARD_ALWAYS)
10646 if (type != 0 && AGGREGATE_TYPE_P (type))
10650 /* Fall back to the default. */
10651 return default_function_arg_padding (mode, type);
10654 /* If defined, a C expression that gives the alignment boundary, in bits,
10655 of an argument with the specified mode and type. If it is not defined,
10656 PARM_BOUNDARY is used for all arguments.
10658 V.4 wants long longs and doubles to be double word aligned. Just
10659 testing the mode size is a boneheaded way to do this as it means
10660 that other types such as complex int are also double word aligned.
10661 However, we're stuck with this because changing the ABI might break
10662 existing library interfaces.
10664 Quadword align Altivec/VSX vectors.
10665 Quadword align large synthetic vector types. */
10667 static unsigned int
10668 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
10670 machine_mode elt_mode;
10673 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10675 if (DEFAULT_ABI == ABI_V4
10676 && (GET_MODE_SIZE (mode) == 8
10677 || (TARGET_HARD_FLOAT
10678 && !is_complex_IBM_long_double (mode)
10679 && FLOAT128_2REG_P (mode))))
10681 else if (FLOAT128_VECTOR_P (mode))
10683 else if (type && TREE_CODE (type) == VECTOR_TYPE
10684 && int_size_in_bytes (type) >= 8
10685 && int_size_in_bytes (type) < 16)
10687 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10688 || (type && TREE_CODE (type) == VECTOR_TYPE
10689 && int_size_in_bytes (type) >= 16))
10692 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10693 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10694 -mcompat-align-parm is used. */
10695 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
10696 || DEFAULT_ABI == ABI_ELFv2)
10697 && type && TYPE_ALIGN (type) > 64)
10699 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10700 or homogeneous float/vector aggregates here. We already handled
10701 vector aggregates above, but still need to check for float here. */
10702 bool aggregate_p = (AGGREGATE_TYPE_P (type)
10703 && !SCALAR_FLOAT_MODE_P (elt_mode));
10705 /* We used to check for BLKmode instead of the above aggregate type
10706 check. Warn when this results in any difference to the ABI. */
10707 if (aggregate_p != (mode == BLKmode))
10709 static bool warned;
10710 if (!warned && warn_psabi)
10713 inform (input_location,
10714 "the ABI of passing aggregates with %d-byte alignment"
10715 " has changed in GCC 5",
10716 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
10724 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10725 implement the "aggregate type" check as a BLKmode check here; this
10726 means certain aggregate types are in fact not aligned. */
10727 if (TARGET_MACHO && rs6000_darwin64_abi
10729 && type && TYPE_ALIGN (type) > 64)
10732 return PARM_BOUNDARY;
10735 /* The offset in words to the start of the parameter save area. */
10737 static unsigned int
10738 rs6000_parm_offset (void)
10740 return (DEFAULT_ABI == ABI_V4 ? 2
10741 : DEFAULT_ABI == ABI_ELFv2 ? 4
10745 /* For a function parm of MODE and TYPE, return the starting word in
10746 the parameter area. NWORDS of the parameter area are already used. */
10748 static unsigned int
10749 rs6000_parm_start (machine_mode mode, const_tree type,
10750 unsigned int nwords)
10752 unsigned int align;
10754 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
10755 return nwords + (-(rs6000_parm_offset () + nwords) & align);
10758 /* Compute the size (in words) of a function argument. */
10760 static unsigned long
10761 rs6000_arg_size (machine_mode mode, const_tree type)
10763 unsigned long size;
10765 if (mode != BLKmode)
10766 size = GET_MODE_SIZE (mode);
10768 size = int_size_in_bytes (type);
10771 return (size + 3) >> 2;
10773 return (size + 7) >> 3;
10776 /* Use this to flush pending int fields. */
10779 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
10780 HOST_WIDE_INT bitpos, int final)
10782 unsigned int startbit, endbit;
10783 int intregs, intoffset;
10785 /* Handle the situations where a float is taking up the first half
10786 of the GPR, and the other half is empty (typically due to
10787 alignment restrictions). We can detect this by a 8-byte-aligned
10788 int field, or by seeing that this is the final flush for this
10789 argument. Count the word and continue on. */
10790 if (cum->floats_in_gpr == 1
10791 && (cum->intoffset % 64 == 0
10792 || (cum->intoffset == -1 && final)))
10795 cum->floats_in_gpr = 0;
10798 if (cum->intoffset == -1)
10801 intoffset = cum->intoffset;
10802 cum->intoffset = -1;
10803 cum->floats_in_gpr = 0;
10805 if (intoffset % BITS_PER_WORD != 0)
10807 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
10808 if (!int_mode_for_size (bits, 0).exists ())
10810 /* We couldn't find an appropriate mode, which happens,
10811 e.g., in packed structs when there are 3 bytes to load.
10812 Back intoffset back to the beginning of the word in this
10814 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
10818 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
10819 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
10820 intregs = (endbit - startbit) / BITS_PER_WORD;
10821 cum->words += intregs;
10822 /* words should be unsigned. */
10823 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
10825 int pad = (endbit/BITS_PER_WORD) - cum->words;
10830 /* The darwin64 ABI calls for us to recurse down through structs,
10831 looking for elements passed in registers. Unfortunately, we have
10832 to track int register count here also because of misalignments
10833 in powerpc alignment mode. */
10836 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
10838 HOST_WIDE_INT startbitpos)
10842 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
10843 if (TREE_CODE (f) == FIELD_DECL)
10845 HOST_WIDE_INT bitpos = startbitpos;
10846 tree ftype = TREE_TYPE (f);
10848 if (ftype == error_mark_node)
10850 mode = TYPE_MODE (ftype);
10852 if (DECL_SIZE (f) != 0
10853 && tree_fits_uhwi_p (bit_position (f)))
10854 bitpos += int_bit_position (f);
10856 /* ??? FIXME: else assume zero offset. */
10858 if (TREE_CODE (ftype) == RECORD_TYPE)
10859 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
10860 else if (USE_FP_FOR_ARG_P (cum, mode))
10862 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
10863 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10864 cum->fregno += n_fpregs;
10865 /* Single-precision floats present a special problem for
10866 us, because they are smaller than an 8-byte GPR, and so
10867 the structure-packing rules combined with the standard
10868 varargs behavior mean that we want to pack float/float
10869 and float/int combinations into a single register's
10870 space. This is complicated by the arg advance flushing,
10871 which works on arbitrarily large groups of int-type
10873 if (mode == SFmode)
10875 if (cum->floats_in_gpr == 1)
10877 /* Two floats in a word; count the word and reset
10878 the float count. */
10880 cum->floats_in_gpr = 0;
10882 else if (bitpos % 64 == 0)
10884 /* A float at the beginning of an 8-byte word;
10885 count it and put off adjusting cum->words until
10886 we see if a arg advance flush is going to do it
10888 cum->floats_in_gpr++;
10892 /* The float is at the end of a word, preceded
10893 by integer fields, so the arg advance flush
10894 just above has already set cum->words and
10895 everything is taken care of. */
10899 cum->words += n_fpregs;
10901 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
10903 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10907 else if (cum->intoffset == -1)
10908 cum->intoffset = bitpos;
10912 /* Check for an item that needs to be considered specially under the darwin 64
10913 bit ABI. These are record types where the mode is BLK or the structure is
10914 8 bytes in size. */
10916 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
10918 return rs6000_darwin64_abi
10919 && ((mode == BLKmode
10920 && TREE_CODE (type) == RECORD_TYPE
10921 && int_size_in_bytes (type) > 0)
10922 || (type && TREE_CODE (type) == RECORD_TYPE
10923 && int_size_in_bytes (type) == 8)) ? 1 : 0;
10926 /* Update the data in CUM to advance over an argument
10927 of mode MODE and data type TYPE.
10928 (TYPE is null for libcalls where that information may not be available.)
10930 Note that for args passed by reference, function_arg will be called
10931 with MODE and TYPE set to that of the pointer to the arg, not the arg
10935 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
10936 const_tree type, bool named, int depth)
10938 machine_mode elt_mode;
10941 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10943 /* Only tick off an argument if we're not recursing. */
10945 cum->nargs_prototype--;
10947 #ifdef HAVE_AS_GNU_ATTRIBUTE
10948 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
10951 if (SCALAR_FLOAT_MODE_P (mode))
10953 rs6000_passes_float = true;
10954 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10955 && (FLOAT128_IBM_P (mode)
10956 || FLOAT128_IEEE_P (mode)
10958 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
10959 rs6000_passes_long_double = true;
10961 /* Note if we passed or return a IEEE 128-bit type. We changed the
10962 mangling for these types, and we may need to make an alias with
10963 the old mangling. */
10964 if (FLOAT128_IEEE_P (mode))
10965 rs6000_passes_ieee128 = true;
10967 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
10968 rs6000_passes_vector = true;
10972 if (TARGET_ALTIVEC_ABI
10973 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10974 || (type && TREE_CODE (type) == VECTOR_TYPE
10975 && int_size_in_bytes (type) == 16)))
10977 bool stack = false;
10979 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
10981 cum->vregno += n_elts;
10983 if (!TARGET_ALTIVEC)
10984 error ("cannot pass argument in vector register because"
10985 " altivec instructions are disabled, use %qs"
10986 " to enable them", "-maltivec");
10988 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
10989 even if it is going to be passed in a vector register.
10990 Darwin does the same for variable-argument functions. */
10991 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10993 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11003 /* Vector parameters must be 16-byte aligned. In 32-bit
11004 mode this means we need to take into account the offset
11005 to the parameter save area. In 64-bit mode, they just
11006 have to start on an even word, since the parameter save
11007 area is 16-byte aligned. */
11009 align = -(rs6000_parm_offset () + cum->words) & 3;
11011 align = cum->words & 1;
11012 cum->words += align + rs6000_arg_size (mode, type);
11014 if (TARGET_DEBUG_ARG)
11016 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11017 cum->words, align);
11018 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11019 cum->nargs_prototype, cum->prototype,
11020 GET_MODE_NAME (mode));
11024 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11026 int size = int_size_in_bytes (type);
11027 /* Variable sized types have size == -1 and are
11028 treated as if consisting entirely of ints.
11029 Pad to 16 byte boundary if needed. */
11030 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11031 && (cum->words % 2) != 0)
11033 /* For varargs, we can just go up by the size of the struct. */
11035 cum->words += (size + 7) / 8;
11038 /* It is tempting to say int register count just goes up by
11039 sizeof(type)/8, but this is wrong in a case such as
11040 { int; double; int; } [powerpc alignment]. We have to
11041 grovel through the fields for these too. */
11042 cum->intoffset = 0;
11043 cum->floats_in_gpr = 0;
11044 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11045 rs6000_darwin64_record_arg_advance_flush (cum,
11046 size * BITS_PER_UNIT, 1);
11048 if (TARGET_DEBUG_ARG)
11050 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11051 cum->words, TYPE_ALIGN (type), size);
11053 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11054 cum->nargs_prototype, cum->prototype,
11055 GET_MODE_NAME (mode));
11058 else if (DEFAULT_ABI == ABI_V4)
11060 if (abi_v4_pass_in_fpr (mode, named))
11062 /* _Decimal128 must use an even/odd register pair. This assumes
11063 that the register number is odd when fregno is odd. */
11064 if (mode == TDmode && (cum->fregno % 2) == 1)
11067 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11068 <= FP_ARG_V4_MAX_REG)
11069 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11072 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11073 if (mode == DFmode || FLOAT128_IBM_P (mode)
11074 || mode == DDmode || mode == TDmode)
11075 cum->words += cum->words & 1;
11076 cum->words += rs6000_arg_size (mode, type);
11081 int n_words = rs6000_arg_size (mode, type);
11082 int gregno = cum->sysv_gregno;
11084 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11085 As does any other 2 word item such as complex int due to a
11086 historical mistake. */
11088 gregno += (1 - gregno) & 1;
11090 /* Multi-reg args are not split between registers and stack. */
11091 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11093 /* Long long is aligned on the stack. So are other 2 word
11094 items such as complex int due to a historical mistake. */
11096 cum->words += cum->words & 1;
11097 cum->words += n_words;
11100 /* Note: continuing to accumulate gregno past when we've started
11101 spilling to the stack indicates the fact that we've started
11102 spilling to the stack to expand_builtin_saveregs. */
11103 cum->sysv_gregno = gregno + n_words;
11106 if (TARGET_DEBUG_ARG)
11108 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11109 cum->words, cum->fregno);
11110 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11111 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11112 fprintf (stderr, "mode = %4s, named = %d\n",
11113 GET_MODE_NAME (mode), named);
11118 int n_words = rs6000_arg_size (mode, type);
11119 int start_words = cum->words;
11120 int align_words = rs6000_parm_start (mode, type, start_words);
11122 cum->words = align_words + n_words;
11124 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11126 /* _Decimal128 must be passed in an even/odd float register pair.
11127 This assumes that the register number is odd when fregno is
11129 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11131 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11134 if (TARGET_DEBUG_ARG)
11136 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11137 cum->words, cum->fregno);
11138 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11139 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11140 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11141 named, align_words - start_words, depth);
11147 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11148 const_tree type, bool named)
11150 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11154 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11155 structure between cum->intoffset and bitpos to integer registers. */
11158 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11159 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11162 unsigned int regno;
11163 unsigned int startbit, endbit;
11164 int this_regno, intregs, intoffset;
11167 if (cum->intoffset == -1)
11170 intoffset = cum->intoffset;
11171 cum->intoffset = -1;
11173 /* If this is the trailing part of a word, try to only load that
11174 much into the register. Otherwise load the whole register. Note
11175 that in the latter case we may pick up unwanted bits. It's not a
11176 problem at the moment but may wish to revisit. */
11178 if (intoffset % BITS_PER_WORD != 0)
11180 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11181 if (!int_mode_for_size (bits, 0).exists (&mode))
11183 /* We couldn't find an appropriate mode, which happens,
11184 e.g., in packed structs when there are 3 bytes to load.
11185 Back intoffset back to the beginning of the word in this
11187 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11194 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11195 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11196 intregs = (endbit - startbit) / BITS_PER_WORD;
11197 this_regno = cum->words + intoffset / BITS_PER_WORD;
11199 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11200 cum->use_stack = 1;
11202 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11206 intoffset /= BITS_PER_UNIT;
11209 regno = GP_ARG_MIN_REG + this_regno;
11210 reg = gen_rtx_REG (mode, regno);
11212 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11215 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11219 while (intregs > 0);
11222 /* Recursive workhorse for the following. */
11225 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11226 HOST_WIDE_INT startbitpos, rtx rvec[],
11231 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11232 if (TREE_CODE (f) == FIELD_DECL)
11234 HOST_WIDE_INT bitpos = startbitpos;
11235 tree ftype = TREE_TYPE (f);
11237 if (ftype == error_mark_node)
11239 mode = TYPE_MODE (ftype);
11241 if (DECL_SIZE (f) != 0
11242 && tree_fits_uhwi_p (bit_position (f)))
11243 bitpos += int_bit_position (f);
11245 /* ??? FIXME: else assume zero offset. */
11247 if (TREE_CODE (ftype) == RECORD_TYPE)
11248 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11249 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11251 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11255 case E_SCmode: mode = SFmode; break;
11256 case E_DCmode: mode = DFmode; break;
11257 case E_TCmode: mode = TFmode; break;
11261 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11262 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11264 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11265 && (mode == TFmode || mode == TDmode));
11266 /* Long double or _Decimal128 split over regs and memory. */
11267 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11271 = gen_rtx_EXPR_LIST (VOIDmode,
11272 gen_rtx_REG (mode, cum->fregno++),
11273 GEN_INT (bitpos / BITS_PER_UNIT));
11274 if (FLOAT128_2REG_P (mode))
11277 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11279 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11281 = gen_rtx_EXPR_LIST (VOIDmode,
11282 gen_rtx_REG (mode, cum->vregno++),
11283 GEN_INT (bitpos / BITS_PER_UNIT));
11285 else if (cum->intoffset == -1)
11286 cum->intoffset = bitpos;
11290 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11291 the register(s) to be used for each field and subfield of a struct
11292 being passed by value, along with the offset of where the
11293 register's value may be found in the block. FP fields go in FP
11294 register, vector fields go in vector registers, and everything
11295 else goes in int registers, packed as in memory.
11297 This code is also used for function return values. RETVAL indicates
11298 whether this is the case.
11300 Much of this is taken from the SPARC V9 port, which has a similar
11301 calling convention. */
11304 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11305 bool named, bool retval)
11307 rtx rvec[FIRST_PSEUDO_REGISTER];
11308 int k = 1, kbase = 1;
11309 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11310 /* This is a copy; modifications are not visible to our caller. */
11311 CUMULATIVE_ARGS copy_cum = *orig_cum;
11312 CUMULATIVE_ARGS *cum = ©_cum;
11314 /* Pad to 16 byte boundary if needed. */
11315 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11316 && (cum->words % 2) != 0)
11319 cum->intoffset = 0;
11320 cum->use_stack = 0;
11321 cum->named = named;
11323 /* Put entries into rvec[] for individual FP and vector fields, and
11324 for the chunks of memory that go in int regs. Note we start at
11325 element 1; 0 is reserved for an indication of using memory, and
11326 may or may not be filled in below. */
11327 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11328 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11330 /* If any part of the struct went on the stack put all of it there.
11331 This hack is because the generic code for
11332 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11333 parts of the struct are not at the beginning. */
11334 if (cum->use_stack)
11337 return NULL_RTX; /* doesn't go in registers at all */
11339 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11341 if (k > 1 || cum->use_stack)
11342 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11347 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11350 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11355 rtx rvec[GP_ARG_NUM_REG + 1];
11357 if (align_words >= GP_ARG_NUM_REG)
11360 n_units = rs6000_arg_size (mode, type);
11362 /* Optimize the simple case where the arg fits in one gpr, except in
11363 the case of BLKmode due to assign_parms assuming that registers are
11364 BITS_PER_WORD wide. */
11366 || (n_units == 1 && mode != BLKmode))
11367 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11370 if (align_words + n_units > GP_ARG_NUM_REG)
11371 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11372 using a magic NULL_RTX component.
11373 This is not strictly correct. Only some of the arg belongs in
11374 memory, not all of it. However, the normal scheme using
11375 function_arg_partial_nregs can result in unusual subregs, eg.
11376 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11377 store the whole arg to memory is often more efficient than code
11378 to store pieces, and we know that space is available in the right
11379 place for the whole arg. */
11380 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11385 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
11386 rtx off = GEN_INT (i++ * 4);
11387 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11389 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
11391 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11394 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11395 but must also be copied into the parameter save area starting at
11396 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11397 to the GPRs and/or memory. Return the number of elements used. */
11400 rs6000_psave_function_arg (machine_mode mode, const_tree type,
11401 int align_words, rtx *rvec)
11405 if (align_words < GP_ARG_NUM_REG)
11407 int n_words = rs6000_arg_size (mode, type);
11409 if (align_words + n_words > GP_ARG_NUM_REG
11411 || (TARGET_32BIT && TARGET_POWERPC64))
11413 /* If this is partially on the stack, then we only
11414 include the portion actually in registers here. */
11415 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11418 if (align_words + n_words > GP_ARG_NUM_REG)
11420 /* Not all of the arg fits in gprs. Say that it goes in memory
11421 too, using a magic NULL_RTX component. Also see comment in
11422 rs6000_mixed_function_arg for why the normal
11423 function_arg_partial_nregs scheme doesn't work in this case. */
11424 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11429 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11430 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
11431 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11433 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11437 /* The whole arg fits in gprs. */
11438 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11439 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
11444 /* It's entirely in memory. */
11445 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11451 /* RVEC is a vector of K components of an argument of mode MODE.
11452 Construct the final function_arg return value from it. */
11455 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
11457 gcc_assert (k >= 1);
11459 /* Avoid returning a PARALLEL in the trivial cases. */
11462 if (XEXP (rvec[0], 0) == NULL_RTX)
11465 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
11466 return XEXP (rvec[0], 0);
11469 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11472 /* Determine where to put an argument to a function.
11473 Value is zero to push the argument on the stack,
11474 or a hard register in which to store the argument.
11476 MODE is the argument's machine mode.
11477 TYPE is the data type of the argument (as a tree).
11478 This is null for libcalls where that information may
11480 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11481 the preceding args and about the function being called. It is
11482 not modified in this routine.
11483 NAMED is nonzero if this argument is a named parameter
11484 (otherwise it is an extra parameter matching an ellipsis).
11486 On RS/6000 the first eight words of non-FP are normally in registers
11487 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11488 Under V.4, the first 8 FP args are in registers.
11490 If this is floating-point and no prototype is specified, we use
11491 both an FP and integer register (or possibly FP reg and stack). Library
11492 functions (when CALL_LIBCALL is set) always have the proper types for args,
11493 so we can pass the FP value just in one register. emit_library_function
11494 doesn't support PARALLEL anyway.
11496 Note that for args passed by reference, function_arg will be called
11497 with MODE and TYPE set to that of the pointer to the arg, not the arg
11501 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
11502 const_tree type, bool named)
11504 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11505 enum rs6000_abi abi = DEFAULT_ABI;
11506 machine_mode elt_mode;
11509 /* Return a marker to indicate whether CR1 needs to set or clear the
11510 bit that V.4 uses to say fp args were passed in registers.
11511 Assume that we don't need the marker for software floating point,
11512 or compiler generated library calls. */
11513 if (mode == VOIDmode)
11516 && (cum->call_cookie & CALL_LIBCALL) == 0
11518 || (cum->nargs_prototype < 0
11519 && (cum->prototype || TARGET_NO_PROTOTYPE)))
11520 && TARGET_HARD_FLOAT)
11521 return GEN_INT (cum->call_cookie
11522 | ((cum->fregno == FP_ARG_MIN_REG)
11523 ? CALL_V4_SET_FP_ARGS
11524 : CALL_V4_CLEAR_FP_ARGS));
11526 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
11529 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11531 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11533 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
11534 if (rslt != NULL_RTX)
11536 /* Else fall through to usual handling. */
11539 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11541 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11545 /* Do we also need to pass this argument in the parameter save area?
11546 Library support functions for IEEE 128-bit are assumed to not need the
11547 value passed both in GPRs and in vector registers. */
11548 if (TARGET_64BIT && !cum->prototype
11549 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11551 int align_words = ROUND_UP (cum->words, 2);
11552 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11555 /* Describe where this argument goes in the vector registers. */
11556 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
11558 r = gen_rtx_REG (elt_mode, cum->vregno + i);
11559 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11560 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11563 return rs6000_finish_function_arg (mode, rvec, k);
11565 else if (TARGET_ALTIVEC_ABI
11566 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
11567 || (type && TREE_CODE (type) == VECTOR_TYPE
11568 && int_size_in_bytes (type) == 16)))
11570 if (named || abi == ABI_V4)
11574 /* Vector parameters to varargs functions under AIX or Darwin
11575 get passed in memory and possibly also in GPRs. */
11576 int align, align_words, n_words;
11577 machine_mode part_mode;
11579 /* Vector parameters must be 16-byte aligned. In 32-bit
11580 mode this means we need to take into account the offset
11581 to the parameter save area. In 64-bit mode, they just
11582 have to start on an even word, since the parameter save
11583 area is 16-byte aligned. */
11585 align = -(rs6000_parm_offset () + cum->words) & 3;
11587 align = cum->words & 1;
11588 align_words = cum->words + align;
11590 /* Out of registers? Memory, then. */
11591 if (align_words >= GP_ARG_NUM_REG)
11594 if (TARGET_32BIT && TARGET_POWERPC64)
11595 return rs6000_mixed_function_arg (mode, type, align_words);
11597 /* The vector value goes in GPRs. Only the part of the
11598 value in GPRs is reported here. */
11600 n_words = rs6000_arg_size (mode, type);
11601 if (align_words + n_words > GP_ARG_NUM_REG)
11602 /* Fortunately, there are only two possibilities, the value
11603 is either wholly in GPRs or half in GPRs and half not. */
11604 part_mode = DImode;
11606 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
11610 else if (abi == ABI_V4)
11612 if (abi_v4_pass_in_fpr (mode, named))
11614 /* _Decimal128 must use an even/odd register pair. This assumes
11615 that the register number is odd when fregno is odd. */
11616 if (mode == TDmode && (cum->fregno % 2) == 1)
11619 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11620 <= FP_ARG_V4_MAX_REG)
11621 return gen_rtx_REG (mode, cum->fregno);
11627 int n_words = rs6000_arg_size (mode, type);
11628 int gregno = cum->sysv_gregno;
11630 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11631 As does any other 2 word item such as complex int due to a
11632 historical mistake. */
11634 gregno += (1 - gregno) & 1;
11636 /* Multi-reg args are not split between registers and stack. */
11637 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11640 if (TARGET_32BIT && TARGET_POWERPC64)
11641 return rs6000_mixed_function_arg (mode, type,
11642 gregno - GP_ARG_MIN_REG);
11643 return gen_rtx_REG (mode, gregno);
11648 int align_words = rs6000_parm_start (mode, type, cum->words);
11650 /* _Decimal128 must be passed in an even/odd float register pair.
11651 This assumes that the register number is odd when fregno is odd. */
11652 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11655 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11656 && !(TARGET_AIX && !TARGET_ELF
11657 && type != NULL && AGGREGATE_TYPE_P (type)))
11659 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11662 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11665 /* Do we also need to pass this argument in the parameter
11667 if (type && (cum->nargs_prototype <= 0
11668 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11669 && TARGET_XL_COMPAT
11670 && align_words >= GP_ARG_NUM_REG)))
11671 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11673 /* Describe where this argument goes in the fprs. */
11674 for (i = 0; i < n_elts
11675 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
11677 /* Check if the argument is split over registers and memory.
11678 This can only ever happen for long double or _Decimal128;
11679 complex types are handled via split_complex_arg. */
11680 machine_mode fmode = elt_mode;
11681 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
11683 gcc_assert (FLOAT128_2REG_P (fmode));
11684 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
11687 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
11688 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11689 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11692 /* If there were not enough FPRs to hold the argument, the rest
11693 usually goes into memory. However, if the current position
11694 is still within the register parameter area, a portion may
11695 actually have to go into GPRs.
11697 Note that it may happen that the portion of the argument
11698 passed in the first "half" of the first GPR was already
11699 passed in the last FPR as well.
11701 For unnamed arguments, we already set up GPRs to cover the
11702 whole argument in rs6000_psave_function_arg, so there is
11703 nothing further to do at this point. */
11704 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
11705 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
11706 && cum->nargs_prototype > 0)
11708 static bool warned;
11710 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11711 int n_words = rs6000_arg_size (mode, type);
11713 align_words += fpr_words;
11714 n_words -= fpr_words;
11718 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11719 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
11720 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11722 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11724 if (!warned && warn_psabi)
11727 inform (input_location,
11728 "the ABI of passing homogeneous %<float%> aggregates"
11729 " has changed in GCC 5");
11733 return rs6000_finish_function_arg (mode, rvec, k);
11735 else if (align_words < GP_ARG_NUM_REG)
11737 if (TARGET_32BIT && TARGET_POWERPC64)
11738 return rs6000_mixed_function_arg (mode, type, align_words);
11740 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11747 /* For an arg passed partly in registers and partly in memory, this is
11748 the number of bytes passed in registers. For args passed entirely in
11749 registers or entirely in memory, zero. When an arg is described by a
11750 PARALLEL, perhaps using more than one register type, this function
11751 returns the number of bytes used by the first element of the PARALLEL. */
11754 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
11755 tree type, bool named)
11757 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11758 bool passed_in_gprs = true;
11761 machine_mode elt_mode;
11764 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11766 if (DEFAULT_ABI == ABI_V4)
11769 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11771 /* If we are passing this arg in the fixed parameter save area (gprs or
11772 memory) as well as VRs, we do not use the partial bytes mechanism;
11773 instead, rs6000_function_arg will return a PARALLEL including a memory
11774 element as necessary. Library support functions for IEEE 128-bit are
11775 assumed to not need the value passed both in GPRs and in vector
11777 if (TARGET_64BIT && !cum->prototype
11778 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11781 /* Otherwise, we pass in VRs only. Check for partial copies. */
11782 passed_in_gprs = false;
11783 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
11784 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
11787 /* In this complicated case we just disable the partial_nregs code. */
11788 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11791 align_words = rs6000_parm_start (mode, type, cum->words);
11793 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11794 && !(TARGET_AIX && !TARGET_ELF
11795 && type != NULL && AGGREGATE_TYPE_P (type)))
11797 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11799 /* If we are passing this arg in the fixed parameter save area
11800 (gprs or memory) as well as FPRs, we do not use the partial
11801 bytes mechanism; instead, rs6000_function_arg will return a
11802 PARALLEL including a memory element as necessary. */
11804 && (cum->nargs_prototype <= 0
11805 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11806 && TARGET_XL_COMPAT
11807 && align_words >= GP_ARG_NUM_REG)))
11810 /* Otherwise, we pass in FPRs only. Check for partial copies. */
11811 passed_in_gprs = false;
11812 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
11814 /* Compute number of bytes / words passed in FPRs. If there
11815 is still space available in the register parameter area
11816 *after* that amount, a part of the argument will be passed
11817 in GPRs. In that case, the total amount passed in any
11818 registers is equal to the amount that would have been passed
11819 in GPRs if everything were passed there, so we fall back to
11820 the GPR code below to compute the appropriate value. */
11821 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
11822 * MIN (8, GET_MODE_SIZE (elt_mode)));
11823 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
11825 if (align_words + fpr_words < GP_ARG_NUM_REG)
11826 passed_in_gprs = true;
11833 && align_words < GP_ARG_NUM_REG
11834 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
11835 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
11837 if (ret != 0 && TARGET_DEBUG_ARG)
11838 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
11843 /* A C expression that indicates when an argument must be passed by
11844 reference. If nonzero for an argument, a copy of that argument is
11845 made in memory and a pointer to the argument is passed instead of
11846 the argument itself. The pointer is passed in whatever way is
11847 appropriate for passing a pointer to that type.
11849 Under V.4, aggregates and long double are passed by reference.
11851 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
11852 reference unless the AltiVec vector extension ABI is in force.
11854 As an extension to all ABIs, variable sized types are passed by
11858 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
11859 machine_mode mode, const_tree type,
11860 bool named ATTRIBUTE_UNUSED)
11865 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11866 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11868 if (TARGET_DEBUG_ARG)
11869 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
11873 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
11875 if (TARGET_DEBUG_ARG)
11876 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
11880 if (int_size_in_bytes (type) < 0)
11882 if (TARGET_DEBUG_ARG)
11883 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
11887 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11888 modes only exist for GCC vector types if -maltivec. */
11889 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11891 if (TARGET_DEBUG_ARG)
11892 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
11896 /* Pass synthetic vectors in memory. */
11897 if (TREE_CODE (type) == VECTOR_TYPE
11898 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11900 static bool warned_for_pass_big_vectors = false;
11901 if (TARGET_DEBUG_ARG)
11902 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
11903 if (!warned_for_pass_big_vectors)
11905 warning (OPT_Wpsabi, "GCC vector passed by reference: "
11906 "non-standard ABI extension with no compatibility "
11908 warned_for_pass_big_vectors = true;
11916 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
11917 already processes. Return true if the parameter must be passed
11918 (fully or partially) on the stack. */
11921 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
11927 /* Catch errors. */
11928 if (type == NULL || type == error_mark_node)
11931 /* Handle types with no storage requirement. */
11932 if (TYPE_MODE (type) == VOIDmode)
11935 /* Handle complex types. */
11936 if (TREE_CODE (type) == COMPLEX_TYPE)
11937 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
11938 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
11940 /* Handle transparent aggregates. */
11941 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
11942 && TYPE_TRANSPARENT_AGGR (type))
11943 type = TREE_TYPE (first_field (type));
11945 /* See if this arg was passed by invisible reference. */
11946 if (pass_by_reference (get_cumulative_args (args_so_far),
11947 TYPE_MODE (type), type, true))
11948 type = build_pointer_type (type);
11950 /* Find mode as it is passed by the ABI. */
11951 unsignedp = TYPE_UNSIGNED (type);
11952 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
11954 /* If we must pass in stack, we need a stack. */
11955 if (rs6000_must_pass_in_stack (mode, type))
11958 /* If there is no incoming register, we need a stack. */
11959 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
11960 if (entry_parm == NULL)
11963 /* Likewise if we need to pass both in registers and on the stack. */
11964 if (GET_CODE (entry_parm) == PARALLEL
11965 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
11968 /* Also true if we're partially in registers and partially not. */
11969 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
11972 /* Update info on where next arg arrives in registers. */
11973 rs6000_function_arg_advance (args_so_far, mode, type, true);
11977 /* Return true if FUN has no prototype, has a variable argument
11978 list, or passes any parameter in memory. */
11981 rs6000_function_parms_need_stack (tree fun, bool incoming)
11983 tree fntype, result;
11984 CUMULATIVE_ARGS args_so_far_v;
11985 cumulative_args_t args_so_far;
11988 /* Must be a libcall, all of which only use reg parms. */
11993 fntype = TREE_TYPE (fun);
11995 /* Varargs functions need the parameter save area. */
11996 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
11999 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12000 args_so_far = pack_cumulative_args (&args_so_far_v);
12002 /* When incoming, we will have been passed the function decl.
12003 It is necessary to use the decl to handle K&R style functions,
12004 where TYPE_ARG_TYPES may not be available. */
12007 gcc_assert (DECL_P (fun));
12008 result = DECL_RESULT (fun);
12011 result = TREE_TYPE (fntype);
12013 if (result && aggregate_value_p (result, fntype))
12015 if (!TYPE_P (result))
12016 result = TREE_TYPE (result);
12017 result = build_pointer_type (result);
12018 rs6000_parm_needs_stack (args_so_far, result);
12025 for (parm = DECL_ARGUMENTS (fun);
12026 parm && parm != void_list_node;
12027 parm = TREE_CHAIN (parm))
12028 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12033 function_args_iterator args_iter;
12036 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12037 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12044 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12045 usually a constant depending on the ABI. However, in the ELFv2 ABI
12046 the register parameter area is optional when calling a function that
12047 has a prototype is scope, has no variable argument list, and passes
12048 all parameters in registers. */
12051 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12053 int reg_parm_stack_space;
12055 switch (DEFAULT_ABI)
12058 reg_parm_stack_space = 0;
12063 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12067 /* ??? Recomputing this every time is a bit expensive. Is there
12068 a place to cache this information? */
12069 if (rs6000_function_parms_need_stack (fun, incoming))
12070 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12072 reg_parm_stack_space = 0;
12076 return reg_parm_stack_space;
12080 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12083 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12088 for (i = 0; i < nregs; i++)
12090 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12091 if (reload_completed)
12093 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12096 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12097 i * GET_MODE_SIZE (reg_mode));
12100 tem = replace_equiv_address (tem, XEXP (tem, 0));
12104 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12108 /* Perform any needed actions needed for a function that is receiving a
12109 variable number of arguments.
12113 MODE and TYPE are the mode and type of the current parameter.
12115 PRETEND_SIZE is a variable that should be set to the amount of stack
12116 that must be pushed by the prolog to pretend that our caller pushed
12119 Normally, this macro will push all remaining incoming registers on the
12120 stack and set PRETEND_SIZE to the length of the registers pushed. */
12123 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12124 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12127 CUMULATIVE_ARGS next_cum;
12128 int reg_size = TARGET_32BIT ? 4 : 8;
12129 rtx save_area = NULL_RTX, mem;
12130 int first_reg_offset;
12131 alias_set_type set;
12133 /* Skip the last named argument. */
12134 next_cum = *get_cumulative_args (cum);
12135 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12137 if (DEFAULT_ABI == ABI_V4)
12139 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12143 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12144 HOST_WIDE_INT offset = 0;
12146 /* Try to optimize the size of the varargs save area.
12147 The ABI requires that ap.reg_save_area is doubleword
12148 aligned, but we don't need to allocate space for all
12149 the bytes, only those to which we actually will save
12151 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12152 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12153 if (TARGET_HARD_FLOAT
12154 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12155 && cfun->va_list_fpr_size)
12158 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12159 * UNITS_PER_FP_WORD;
12160 if (cfun->va_list_fpr_size
12161 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12162 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12164 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12165 * UNITS_PER_FP_WORD;
12169 offset = -((first_reg_offset * reg_size) & ~7);
12170 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12172 gpr_reg_num = cfun->va_list_gpr_size;
12173 if (reg_size == 4 && (first_reg_offset & 1))
12176 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12179 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12180 * UNITS_PER_FP_WORD
12181 - (int) (GP_ARG_NUM_REG * reg_size);
12183 if (gpr_size + fpr_size)
12186 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12187 gcc_assert (MEM_P (reg_save_area));
12188 reg_save_area = XEXP (reg_save_area, 0);
12189 if (GET_CODE (reg_save_area) == PLUS)
12191 gcc_assert (XEXP (reg_save_area, 0)
12192 == virtual_stack_vars_rtx);
12193 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
12194 offset += INTVAL (XEXP (reg_save_area, 1));
12197 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12200 cfun->machine->varargs_save_offset = offset;
12201 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12206 first_reg_offset = next_cum.words;
12207 save_area = crtl->args.internal_arg_pointer;
12209 if (targetm.calls.must_pass_in_stack (mode, type))
12210 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12213 set = get_varargs_alias_set ();
12214 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12215 && cfun->va_list_gpr_size)
12217 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12219 if (va_list_gpr_counter_field)
12220 /* V4 va_list_gpr_size counts number of registers needed. */
12221 n_gpr = cfun->va_list_gpr_size;
12223 /* char * va_list instead counts number of bytes needed. */
12224 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12229 mem = gen_rtx_MEM (BLKmode,
12230 plus_constant (Pmode, save_area,
12231 first_reg_offset * reg_size));
12232 MEM_NOTRAP_P (mem) = 1;
12233 set_mem_alias_set (mem, set);
12234 set_mem_align (mem, BITS_PER_WORD);
12236 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12240 /* Save FP registers if needed. */
12241 if (DEFAULT_ABI == ABI_V4
12242 && TARGET_HARD_FLOAT
12244 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12245 && cfun->va_list_fpr_size)
12247 int fregno = next_cum.fregno, nregs;
12248 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12249 rtx lab = gen_label_rtx ();
12250 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12251 * UNITS_PER_FP_WORD);
12254 (gen_rtx_SET (pc_rtx,
12255 gen_rtx_IF_THEN_ELSE (VOIDmode,
12256 gen_rtx_NE (VOIDmode, cr1,
12258 gen_rtx_LABEL_REF (VOIDmode, lab),
12262 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12263 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12265 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12266 plus_constant (Pmode, save_area, off));
12267 MEM_NOTRAP_P (mem) = 1;
12268 set_mem_alias_set (mem, set);
12269 set_mem_align (mem, GET_MODE_ALIGNMENT (
12270 TARGET_HARD_FLOAT ? DFmode : SFmode));
12271 emit_move_insn (mem, gen_rtx_REG (
12272 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12279 /* Create the va_list data type. */
12282 rs6000_build_builtin_va_list (void)
12284 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12286 /* For AIX, prefer 'char *' because that's what the system
12287 header files like. */
12288 if (DEFAULT_ABI != ABI_V4)
12289 return build_pointer_type (char_type_node);
12291 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12292 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12293 get_identifier ("__va_list_tag"), record);
12295 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12296 unsigned_char_type_node);
12297 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12298 unsigned_char_type_node);
12299 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12300 every user file. */
12301 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12302 get_identifier ("reserved"), short_unsigned_type_node);
12303 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12304 get_identifier ("overflow_arg_area"),
12306 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12307 get_identifier ("reg_save_area"),
12310 va_list_gpr_counter_field = f_gpr;
12311 va_list_fpr_counter_field = f_fpr;
12313 DECL_FIELD_CONTEXT (f_gpr) = record;
12314 DECL_FIELD_CONTEXT (f_fpr) = record;
12315 DECL_FIELD_CONTEXT (f_res) = record;
12316 DECL_FIELD_CONTEXT (f_ovf) = record;
12317 DECL_FIELD_CONTEXT (f_sav) = record;
12319 TYPE_STUB_DECL (record) = type_decl;
12320 TYPE_NAME (record) = type_decl;
12321 TYPE_FIELDS (record) = f_gpr;
12322 DECL_CHAIN (f_gpr) = f_fpr;
12323 DECL_CHAIN (f_fpr) = f_res;
12324 DECL_CHAIN (f_res) = f_ovf;
12325 DECL_CHAIN (f_ovf) = f_sav;
12327 layout_type (record);
12329 /* The correct type is an array type of one element. */
12330 return build_array_type (record, build_index_type (size_zero_node));
12333 /* Implement va_start. */
12336 rs6000_va_start (tree valist, rtx nextarg)
12338 HOST_WIDE_INT words, n_gpr, n_fpr;
12339 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12340 tree gpr, fpr, ovf, sav, t;
12342 /* Only SVR4 needs something special. */
12343 if (DEFAULT_ABI != ABI_V4)
12345 std_expand_builtin_va_start (valist, nextarg);
12349 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12350 f_fpr = DECL_CHAIN (f_gpr);
12351 f_res = DECL_CHAIN (f_fpr);
12352 f_ovf = DECL_CHAIN (f_res);
12353 f_sav = DECL_CHAIN (f_ovf);
12355 valist = build_simple_mem_ref (valist);
12356 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12357 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12359 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12361 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12364 /* Count number of gp and fp argument registers used. */
12365 words = crtl->args.info.words;
12366 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12368 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12371 if (TARGET_DEBUG_ARG)
12372 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12373 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12374 words, n_gpr, n_fpr);
12376 if (cfun->va_list_gpr_size)
12378 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
12379 build_int_cst (NULL_TREE, n_gpr));
12380 TREE_SIDE_EFFECTS (t) = 1;
12381 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12384 if (cfun->va_list_fpr_size)
12386 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
12387 build_int_cst (NULL_TREE, n_fpr));
12388 TREE_SIDE_EFFECTS (t) = 1;
12389 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12391 #ifdef HAVE_AS_GNU_ATTRIBUTE
12392 if (call_ABI_of_interest (cfun->decl))
12393 rs6000_passes_float = true;
12397 /* Find the overflow area. */
12398 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
12400 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
12401 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
12402 TREE_SIDE_EFFECTS (t) = 1;
12403 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12405 /* If there were no va_arg invocations, don't set up the register
12407 if (!cfun->va_list_gpr_size
12408 && !cfun->va_list_fpr_size
12409 && n_gpr < GP_ARG_NUM_REG
12410 && n_fpr < FP_ARG_V4_MAX_REG)
12413 /* Find the register save area. */
12414 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
12415 if (cfun->machine->varargs_save_offset)
12416 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
12417 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
12418 TREE_SIDE_EFFECTS (t) = 1;
12419 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12422 /* Implement va_arg. */
12425 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
12426 gimple_seq *post_p)
12428 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12429 tree gpr, fpr, ovf, sav, reg, t, u;
12430 int size, rsize, n_reg, sav_ofs, sav_scale;
12431 tree lab_false, lab_over, addr;
12433 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
12437 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
12439 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
12440 return build_va_arg_indirect_ref (t);
12443 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12444 earlier version of gcc, with the property that it always applied alignment
12445 adjustments to the va-args (even for zero-sized types). The cheapest way
12446 to deal with this is to replicate the effect of the part of
12447 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12449 We don't need to check for pass-by-reference because of the test above.
12450 We can return a simplifed answer, since we know there's no offset to add. */
12453 && rs6000_darwin64_abi)
12454 || DEFAULT_ABI == ABI_ELFv2
12455 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
12456 && integer_zerop (TYPE_SIZE (type)))
12458 unsigned HOST_WIDE_INT align, boundary;
12459 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
12460 align = PARM_BOUNDARY / BITS_PER_UNIT;
12461 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
12462 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
12463 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
12464 boundary /= BITS_PER_UNIT;
12465 if (boundary > align)
12468 /* This updates arg ptr by the amount that would be necessary
12469 to align the zero-sized (but not zero-alignment) item. */
12470 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12471 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
12472 gimplify_and_add (t, pre_p);
12474 t = fold_convert (sizetype, valist_tmp);
12475 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12476 fold_convert (TREE_TYPE (valist),
12477 fold_build2 (BIT_AND_EXPR, sizetype, t,
12478 size_int (-boundary))));
12479 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
12480 gimplify_and_add (t, pre_p);
12482 /* Since it is zero-sized there's no increment for the item itself. */
12483 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
12484 return build_va_arg_indirect_ref (valist_tmp);
12487 if (DEFAULT_ABI != ABI_V4)
12489 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
12491 tree elem_type = TREE_TYPE (type);
12492 machine_mode elem_mode = TYPE_MODE (elem_type);
12493 int elem_size = GET_MODE_SIZE (elem_mode);
12495 if (elem_size < UNITS_PER_WORD)
12497 tree real_part, imag_part;
12498 gimple_seq post = NULL;
12500 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12502 /* Copy the value into a temporary, lest the formal temporary
12503 be reused out from under us. */
12504 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
12505 gimple_seq_add_seq (pre_p, post);
12507 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12510 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
12514 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
12517 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12518 f_fpr = DECL_CHAIN (f_gpr);
12519 f_res = DECL_CHAIN (f_fpr);
12520 f_ovf = DECL_CHAIN (f_res);
12521 f_sav = DECL_CHAIN (f_ovf);
12523 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12524 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12526 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12528 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12531 size = int_size_in_bytes (type);
12532 rsize = (size + 3) / 4;
12533 int pad = 4 * rsize - size;
12536 machine_mode mode = TYPE_MODE (type);
12537 if (abi_v4_pass_in_fpr (mode, false))
12539 /* FP args go in FP registers, if present. */
12541 n_reg = (size + 7) / 8;
12542 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
12543 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
12544 if (mode != SFmode && mode != SDmode)
12549 /* Otherwise into GP registers. */
12558 /* Pull the value out of the saved registers.... */
12561 addr = create_tmp_var (ptr_type_node, "addr");
12563 /* AltiVec vectors never go in registers when -mabi=altivec. */
12564 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12568 lab_false = create_artificial_label (input_location);
12569 lab_over = create_artificial_label (input_location);
12571 /* Long long is aligned in the registers. As are any other 2 gpr
12572 item such as complex int due to a historical mistake. */
12574 if (n_reg == 2 && reg == gpr)
12577 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12578 build_int_cst (TREE_TYPE (reg), n_reg - 1));
12579 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
12580 unshare_expr (reg), u);
12582 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12583 reg number is 0 for f1, so we want to make it odd. */
12584 else if (reg == fpr && mode == TDmode)
12586 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12587 build_int_cst (TREE_TYPE (reg), 1));
12588 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
12591 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
12592 t = build2 (GE_EXPR, boolean_type_node, u, t);
12593 u = build1 (GOTO_EXPR, void_type_node, lab_false);
12594 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
12595 gimplify_and_add (t, pre_p);
12599 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
12601 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12602 build_int_cst (TREE_TYPE (reg), n_reg));
12603 u = fold_convert (sizetype, u);
12604 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
12605 t = fold_build_pointer_plus (t, u);
12607 /* _Decimal32 varargs are located in the second word of the 64-bit
12608 FP register for 32-bit binaries. */
12609 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
12610 t = fold_build_pointer_plus_hwi (t, size);
12612 /* Args are passed right-aligned. */
12613 if (BYTES_BIG_ENDIAN)
12614 t = fold_build_pointer_plus_hwi (t, pad);
12616 gimplify_assign (addr, t, pre_p);
12618 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
12620 stmt = gimple_build_label (lab_false);
12621 gimple_seq_add_stmt (pre_p, stmt);
12623 if ((n_reg == 2 && !regalign) || n_reg > 2)
12625 /* Ensure that we don't find any more args in regs.
12626 Alignment has taken care of for special cases. */
12627 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
12631 /* ... otherwise out of the overflow area. */
12633 /* Care for on-stack alignment if needed. */
12637 t = fold_build_pointer_plus_hwi (t, align - 1);
12638 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
12639 build_int_cst (TREE_TYPE (t), -align));
12642 /* Args are passed right-aligned. */
12643 if (BYTES_BIG_ENDIAN)
12644 t = fold_build_pointer_plus_hwi (t, pad);
12646 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
12648 gimplify_assign (unshare_expr (addr), t, pre_p);
12650 t = fold_build_pointer_plus_hwi (t, size);
12651 gimplify_assign (unshare_expr (ovf), t, pre_p);
12655 stmt = gimple_build_label (lab_over);
12656 gimple_seq_add_stmt (pre_p, stmt);
12659 if (STRICT_ALIGNMENT
12660 && (TYPE_ALIGN (type)
12661 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
12663 /* The value (of type complex double, for example) may not be
12664 aligned in memory in the saved registers, so copy via a
12665 temporary. (This is the same code as used for SPARC.) */
12666 tree tmp = create_tmp_var (type, "va_arg_tmp");
12667 tree dest_addr = build_fold_addr_expr (tmp);
12669 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
12670 3, dest_addr, addr, size_int (rsize * 4));
12671 TREE_ADDRESSABLE (tmp) = 1;
12673 gimplify_and_add (copy, pre_p);
12677 addr = fold_convert (ptrtype, addr);
12678 return build_va_arg_indirect_ref (addr);
12684 def_builtin (const char *name, tree type, enum rs6000_builtins code)
12687 unsigned classify = rs6000_builtin_info[(int)code].attr;
12688 const char *attr_string = "";
12690 gcc_assert (name != NULL);
12691 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
12693 if (rs6000_builtin_decls[(int)code])
12694 fatal_error (input_location,
12695 "internal error: builtin function %qs already processed",
12698 rs6000_builtin_decls[(int)code] = t =
12699 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
12701 /* Set any special attributes. */
12702 if ((classify & RS6000_BTC_CONST) != 0)
12704 /* const function, function only depends on the inputs. */
12705 TREE_READONLY (t) = 1;
12706 TREE_NOTHROW (t) = 1;
12707 attr_string = ", const";
12709 else if ((classify & RS6000_BTC_PURE) != 0)
12711 /* pure function, function can read global memory, but does not set any
12713 DECL_PURE_P (t) = 1;
12714 TREE_NOTHROW (t) = 1;
12715 attr_string = ", pure";
12717 else if ((classify & RS6000_BTC_FP) != 0)
12719 /* Function is a math function. If rounding mode is on, then treat the
12720 function as not reading global memory, but it can have arbitrary side
12721 effects. If it is off, then assume the function is a const function.
12722 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12723 builtin-attribute.def that is used for the math functions. */
12724 TREE_NOTHROW (t) = 1;
12725 if (flag_rounding_math)
12727 DECL_PURE_P (t) = 1;
12728 DECL_IS_NOVOPS (t) = 1;
12729 attr_string = ", fp, pure";
12733 TREE_READONLY (t) = 1;
12734 attr_string = ", fp, const";
12737 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
12738 gcc_unreachable ();
12740 if (TARGET_DEBUG_BUILTIN)
12741 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
12742 (int)code, name, attr_string);
12745 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
12747 #undef RS6000_BUILTIN_0
12748 #undef RS6000_BUILTIN_1
12749 #undef RS6000_BUILTIN_2
12750 #undef RS6000_BUILTIN_3
12751 #undef RS6000_BUILTIN_A
12752 #undef RS6000_BUILTIN_D
12753 #undef RS6000_BUILTIN_H
12754 #undef RS6000_BUILTIN_P
12755 #undef RS6000_BUILTIN_X
12757 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12758 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12759 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12760 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
12761 { MASK, ICODE, NAME, ENUM },
12763 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12764 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12765 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12766 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12767 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12769 static const struct builtin_description bdesc_3arg[] =
12771 #include "rs6000-builtin.def"
12774 /* DST operations: void foo (void *, const int, const char). */
12776 #undef RS6000_BUILTIN_0
12777 #undef RS6000_BUILTIN_1
12778 #undef RS6000_BUILTIN_2
12779 #undef RS6000_BUILTIN_3
12780 #undef RS6000_BUILTIN_A
12781 #undef RS6000_BUILTIN_D
12782 #undef RS6000_BUILTIN_H
12783 #undef RS6000_BUILTIN_P
12784 #undef RS6000_BUILTIN_X
12786 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12787 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12788 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12789 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12790 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12791 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
12792 { MASK, ICODE, NAME, ENUM },
12794 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12795 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12796 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12798 static const struct builtin_description bdesc_dst[] =
12800 #include "rs6000-builtin.def"
12803 /* Simple binary operations: VECc = foo (VECa, VECb). */
12805 #undef RS6000_BUILTIN_0
12806 #undef RS6000_BUILTIN_1
12807 #undef RS6000_BUILTIN_2
12808 #undef RS6000_BUILTIN_3
12809 #undef RS6000_BUILTIN_A
12810 #undef RS6000_BUILTIN_D
12811 #undef RS6000_BUILTIN_H
12812 #undef RS6000_BUILTIN_P
12813 #undef RS6000_BUILTIN_X
12815 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12816 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12817 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
12818 { MASK, ICODE, NAME, ENUM },
12820 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12821 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12822 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12823 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12824 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12825 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12827 static const struct builtin_description bdesc_2arg[] =
12829 #include "rs6000-builtin.def"
12832 #undef RS6000_BUILTIN_0
12833 #undef RS6000_BUILTIN_1
12834 #undef RS6000_BUILTIN_2
12835 #undef RS6000_BUILTIN_3
12836 #undef RS6000_BUILTIN_A
12837 #undef RS6000_BUILTIN_D
12838 #undef RS6000_BUILTIN_H
12839 #undef RS6000_BUILTIN_P
12840 #undef RS6000_BUILTIN_X
12842 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12843 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12844 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12845 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12846 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12847 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12848 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12849 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
12850 { MASK, ICODE, NAME, ENUM },
12852 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12854 /* AltiVec predicates. */
12856 static const struct builtin_description bdesc_altivec_preds[] =
12858 #include "rs6000-builtin.def"
12861 /* ABS* operations. */
12863 #undef RS6000_BUILTIN_0
12864 #undef RS6000_BUILTIN_1
12865 #undef RS6000_BUILTIN_2
12866 #undef RS6000_BUILTIN_3
12867 #undef RS6000_BUILTIN_A
12868 #undef RS6000_BUILTIN_D
12869 #undef RS6000_BUILTIN_H
12870 #undef RS6000_BUILTIN_P
12871 #undef RS6000_BUILTIN_X
12873 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12874 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12875 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12876 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12877 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
12878 { MASK, ICODE, NAME, ENUM },
12880 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12881 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12882 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12883 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12885 static const struct builtin_description bdesc_abs[] =
12887 #include "rs6000-builtin.def"
12890 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
12893 #undef RS6000_BUILTIN_0
12894 #undef RS6000_BUILTIN_1
12895 #undef RS6000_BUILTIN_2
12896 #undef RS6000_BUILTIN_3
12897 #undef RS6000_BUILTIN_A
12898 #undef RS6000_BUILTIN_D
12899 #undef RS6000_BUILTIN_H
12900 #undef RS6000_BUILTIN_P
12901 #undef RS6000_BUILTIN_X
12903 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12904 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
12905 { MASK, ICODE, NAME, ENUM },
12907 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12908 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12909 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12910 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12911 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12912 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12913 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12915 static const struct builtin_description bdesc_1arg[] =
12917 #include "rs6000-builtin.def"
12920 /* Simple no-argument operations: result = __builtin_darn_32 () */
12922 #undef RS6000_BUILTIN_0
12923 #undef RS6000_BUILTIN_1
12924 #undef RS6000_BUILTIN_2
12925 #undef RS6000_BUILTIN_3
12926 #undef RS6000_BUILTIN_A
12927 #undef RS6000_BUILTIN_D
12928 #undef RS6000_BUILTIN_H
12929 #undef RS6000_BUILTIN_P
12930 #undef RS6000_BUILTIN_X
12932 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
12933 { MASK, ICODE, NAME, ENUM },
12935 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12936 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12937 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12938 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12939 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12940 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12941 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12942 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12944 static const struct builtin_description bdesc_0arg[] =
12946 #include "rs6000-builtin.def"
12949 /* HTM builtins. */
12950 #undef RS6000_BUILTIN_0
12951 #undef RS6000_BUILTIN_1
12952 #undef RS6000_BUILTIN_2
12953 #undef RS6000_BUILTIN_3
12954 #undef RS6000_BUILTIN_A
12955 #undef RS6000_BUILTIN_D
12956 #undef RS6000_BUILTIN_H
12957 #undef RS6000_BUILTIN_P
12958 #undef RS6000_BUILTIN_X
12960 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12961 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12962 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12963 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12964 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12965 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12966 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12967 { MASK, ICODE, NAME, ENUM },
12969 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12970 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12972 static const struct builtin_description bdesc_htm[] =
12974 #include "rs6000-builtin.def"
12977 #undef RS6000_BUILTIN_0
12978 #undef RS6000_BUILTIN_1
12979 #undef RS6000_BUILTIN_2
12980 #undef RS6000_BUILTIN_3
12981 #undef RS6000_BUILTIN_A
12982 #undef RS6000_BUILTIN_D
12983 #undef RS6000_BUILTIN_H
12984 #undef RS6000_BUILTIN_P
12986 /* Return true if a builtin function is overloaded. */
12988 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
12990 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
12994 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
12996 return rs6000_builtin_info[(int)fncode].name;
12999 /* Expand an expression EXP that calls a builtin without arguments. */
13001 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13004 machine_mode tmode = insn_data[icode].operand[0].mode;
13006 if (icode == CODE_FOR_nothing)
13007 /* Builtin not supported on this processor. */
13010 if (icode == CODE_FOR_rs6000_mffsl
13011 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13013 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
13018 || GET_MODE (target) != tmode
13019 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13020 target = gen_reg_rtx (tmode);
13022 pat = GEN_FCN (icode) (target);
13032 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13035 tree arg0 = CALL_EXPR_ARG (exp, 0);
13036 tree arg1 = CALL_EXPR_ARG (exp, 1);
13037 rtx op0 = expand_normal (arg0);
13038 rtx op1 = expand_normal (arg1);
13039 machine_mode mode0 = insn_data[icode].operand[0].mode;
13040 machine_mode mode1 = insn_data[icode].operand[1].mode;
13042 if (icode == CODE_FOR_nothing)
13043 /* Builtin not supported on this processor. */
13046 /* If we got invalid arguments bail out before generating bad rtl. */
13047 if (arg0 == error_mark_node || arg1 == error_mark_node)
13050 if (!CONST_INT_P (op0)
13051 || INTVAL (op0) > 255
13052 || INTVAL (op0) < 0)
13054 error ("argument 1 must be an 8-bit field value");
13058 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13059 op0 = copy_to_mode_reg (mode0, op0);
13061 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13062 op1 = copy_to_mode_reg (mode1, op1);
13064 pat = GEN_FCN (icode) (op0, op1);
13073 rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
13076 tree arg0 = CALL_EXPR_ARG (exp, 0);
13077 rtx op0 = expand_normal (arg0);
13079 if (icode == CODE_FOR_nothing)
13080 /* Builtin not supported on this processor. */
13083 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13085 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
13086 "%<-msoft-float%>");
13090 /* If we got invalid arguments bail out before generating bad rtl. */
13091 if (arg0 == error_mark_node)
13094 /* Only allow bit numbers 0 to 31. */
13095 if (!u5bit_cint_operand (op0, VOIDmode))
13097 error ("Argument must be a constant between 0 and 31.");
13101 pat = GEN_FCN (icode) (op0);
13110 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
13113 tree arg0 = CALL_EXPR_ARG (exp, 0);
13114 rtx op0 = expand_normal (arg0);
13115 machine_mode mode0 = insn_data[icode].operand[0].mode;
13117 if (icode == CODE_FOR_nothing)
13118 /* Builtin not supported on this processor. */
13121 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13123 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
13127 /* If we got invalid arguments bail out before generating bad rtl. */
13128 if (arg0 == error_mark_node)
13131 /* If the argument is a constant, check the range. Argument can only be a
13132 2-bit value. Unfortunately, can't check the range of the value at
13133 compile time if the argument is a variable. The least significant two
13134 bits of the argument, regardless of type, are used to set the rounding
13135 mode. All other bits are ignored. */
13136 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
13138 error ("Argument must be a value between 0 and 3.");
13142 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13143 op0 = copy_to_mode_reg (mode0, op0);
13145 pat = GEN_FCN (icode) (op0);
13153 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
13156 tree arg0 = CALL_EXPR_ARG (exp, 0);
13157 rtx op0 = expand_normal (arg0);
13158 machine_mode mode0 = insn_data[icode].operand[0].mode;
13161 /* Builtin not supported in 32-bit mode. */
13162 fatal_error (input_location,
13163 "%<__builtin_set_fpscr_drn%> is not supported "
13166 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13168 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
13172 if (icode == CODE_FOR_nothing)
13173 /* Builtin not supported on this processor. */
13176 /* If we got invalid arguments bail out before generating bad rtl. */
13177 if (arg0 == error_mark_node)
13180 /* If the argument is a constant, check the range. Agrument can only be a
13181 3-bit value. Unfortunately, can't check the range of the value at
13182 compile time if the argument is a variable. The least significant two
13183 bits of the argument, regardless of type, are used to set the rounding
13184 mode. All other bits are ignored. */
13185 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
13187 error ("Argument must be a value between 0 and 7.");
13191 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13192 op0 = copy_to_mode_reg (mode0, op0);
13194 pat = GEN_FCN (icode) (op0);
13203 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13206 tree arg0 = CALL_EXPR_ARG (exp, 0);
13207 rtx op0 = expand_normal (arg0);
13208 machine_mode tmode = insn_data[icode].operand[0].mode;
13209 machine_mode mode0 = insn_data[icode].operand[1].mode;
13211 if (icode == CODE_FOR_nothing)
13212 /* Builtin not supported on this processor. */
13215 /* If we got invalid arguments bail out before generating bad rtl. */
13216 if (arg0 == error_mark_node)
13219 if (icode == CODE_FOR_altivec_vspltisb
13220 || icode == CODE_FOR_altivec_vspltish
13221 || icode == CODE_FOR_altivec_vspltisw)
13223 /* Only allow 5-bit *signed* literals. */
13224 if (!CONST_INT_P (op0)
13225 || INTVAL (op0) > 15
13226 || INTVAL (op0) < -16)
13228 error ("argument 1 must be a 5-bit signed literal");
13229 return CONST0_RTX (tmode);
13234 || GET_MODE (target) != tmode
13235 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13236 target = gen_reg_rtx (tmode);
13238 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13239 op0 = copy_to_mode_reg (mode0, op0);
13241 pat = GEN_FCN (icode) (target, op0);
13250 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13252 rtx pat, scratch1, scratch2;
13253 tree arg0 = CALL_EXPR_ARG (exp, 0);
13254 rtx op0 = expand_normal (arg0);
13255 machine_mode tmode = insn_data[icode].operand[0].mode;
13256 machine_mode mode0 = insn_data[icode].operand[1].mode;
13258 /* If we have invalid arguments, bail out before generating bad rtl. */
13259 if (arg0 == error_mark_node)
13263 || GET_MODE (target) != tmode
13264 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13265 target = gen_reg_rtx (tmode);
13267 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13268 op0 = copy_to_mode_reg (mode0, op0);
13270 scratch1 = gen_reg_rtx (mode0);
13271 scratch2 = gen_reg_rtx (mode0);
13273 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13282 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13285 tree arg0 = CALL_EXPR_ARG (exp, 0);
13286 tree arg1 = CALL_EXPR_ARG (exp, 1);
13287 rtx op0 = expand_normal (arg0);
13288 rtx op1 = expand_normal (arg1);
13289 machine_mode tmode = insn_data[icode].operand[0].mode;
13290 machine_mode mode0 = insn_data[icode].operand[1].mode;
13291 machine_mode mode1 = insn_data[icode].operand[2].mode;
13293 if (icode == CODE_FOR_nothing)
13294 /* Builtin not supported on this processor. */
13297 /* If we got invalid arguments bail out before generating bad rtl. */
13298 if (arg0 == error_mark_node || arg1 == error_mark_node)
13301 if (icode == CODE_FOR_unpackv1ti
13302 || icode == CODE_FOR_unpackkf
13303 || icode == CODE_FOR_unpacktf
13304 || icode == CODE_FOR_unpackif
13305 || icode == CODE_FOR_unpacktd)
13307 /* Only allow 1-bit unsigned literals. */
13309 if (TREE_CODE (arg1) != INTEGER_CST
13310 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13312 error ("argument 2 must be a 1-bit unsigned literal");
13313 return CONST0_RTX (tmode);
13316 else if (icode == CODE_FOR_altivec_vspltw)
13318 /* Only allow 2-bit unsigned literals. */
13320 if (TREE_CODE (arg1) != INTEGER_CST
13321 || TREE_INT_CST_LOW (arg1) & ~3)
13323 error ("argument 2 must be a 2-bit unsigned literal");
13324 return CONST0_RTX (tmode);
13327 else if (icode == CODE_FOR_altivec_vsplth)
13329 /* Only allow 3-bit unsigned literals. */
13331 if (TREE_CODE (arg1) != INTEGER_CST
13332 || TREE_INT_CST_LOW (arg1) & ~7)
13334 error ("argument 2 must be a 3-bit unsigned literal");
13335 return CONST0_RTX (tmode);
13338 else if (icode == CODE_FOR_altivec_vspltb)
13340 /* Only allow 4-bit unsigned literals. */
13342 if (TREE_CODE (arg1) != INTEGER_CST
13343 || TREE_INT_CST_LOW (arg1) & ~15)
13345 error ("argument 2 must be a 4-bit unsigned literal");
13346 return CONST0_RTX (tmode);
13349 else if (icode == CODE_FOR_altivec_vcfux
13350 || icode == CODE_FOR_altivec_vcfsx
13351 || icode == CODE_FOR_altivec_vctsxs
13352 || icode == CODE_FOR_altivec_vctuxs)
13354 /* Only allow 5-bit unsigned literals. */
13356 if (TREE_CODE (arg1) != INTEGER_CST
13357 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13359 error ("argument 2 must be a 5-bit unsigned literal");
13360 return CONST0_RTX (tmode);
13363 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13364 || icode == CODE_FOR_dfptstsfi_lt_dd
13365 || icode == CODE_FOR_dfptstsfi_gt_dd
13366 || icode == CODE_FOR_dfptstsfi_unordered_dd
13367 || icode == CODE_FOR_dfptstsfi_eq_td
13368 || icode == CODE_FOR_dfptstsfi_lt_td
13369 || icode == CODE_FOR_dfptstsfi_gt_td
13370 || icode == CODE_FOR_dfptstsfi_unordered_td)
13372 /* Only allow 6-bit unsigned literals. */
13374 if (TREE_CODE (arg0) != INTEGER_CST
13375 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13377 error ("argument 1 must be a 6-bit unsigned literal");
13378 return CONST0_RTX (tmode);
13381 else if (icode == CODE_FOR_xststdcqp_kf
13382 || icode == CODE_FOR_xststdcqp_tf
13383 || icode == CODE_FOR_xststdcdp
13384 || icode == CODE_FOR_xststdcsp
13385 || icode == CODE_FOR_xvtstdcdp
13386 || icode == CODE_FOR_xvtstdcsp)
13388 /* Only allow 7-bit unsigned literals. */
13390 if (TREE_CODE (arg1) != INTEGER_CST
13391 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13393 error ("argument 2 must be a 7-bit unsigned literal");
13394 return CONST0_RTX (tmode);
13399 || GET_MODE (target) != tmode
13400 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13401 target = gen_reg_rtx (tmode);
13403 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13404 op0 = copy_to_mode_reg (mode0, op0);
13405 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13406 op1 = copy_to_mode_reg (mode1, op1);
13408 pat = GEN_FCN (icode) (target, op0, op1);
13417 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13420 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13421 tree arg0 = CALL_EXPR_ARG (exp, 1);
13422 tree arg1 = CALL_EXPR_ARG (exp, 2);
13423 rtx op0 = expand_normal (arg0);
13424 rtx op1 = expand_normal (arg1);
13425 machine_mode tmode = SImode;
13426 machine_mode mode0 = insn_data[icode].operand[1].mode;
13427 machine_mode mode1 = insn_data[icode].operand[2].mode;
13430 if (TREE_CODE (cr6_form) != INTEGER_CST)
13432 error ("argument 1 of %qs must be a constant",
13433 "__builtin_altivec_predicate");
13437 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13439 gcc_assert (mode0 == mode1);
13441 /* If we have invalid arguments, bail out before generating bad rtl. */
13442 if (arg0 == error_mark_node || arg1 == error_mark_node)
13446 || GET_MODE (target) != tmode
13447 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13448 target = gen_reg_rtx (tmode);
13450 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13451 op0 = copy_to_mode_reg (mode0, op0);
13452 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13453 op1 = copy_to_mode_reg (mode1, op1);
13455 /* Note that for many of the relevant operations (e.g. cmpne or
13456 cmpeq) with float or double operands, it makes more sense for the
13457 mode of the allocated scratch register to select a vector of
13458 integer. But the choice to copy the mode of operand 0 was made
13459 long ago and there are no plans to change it. */
13460 scratch = gen_reg_rtx (mode0);
13462 pat = GEN_FCN (icode) (scratch, op0, op1);
13467 /* The vec_any* and vec_all* predicates use the same opcodes for two
13468 different operations, but the bits in CR6 will be different
13469 depending on what information we want. So we have to play tricks
13470 with CR6 to get the right bits out.
13472 If you think this is disgusting, look at the specs for the
13473 AltiVec predicates. */
13475 switch (cr6_form_int)
13478 emit_insn (gen_cr6_test_for_zero (target));
13481 emit_insn (gen_cr6_test_for_zero_reverse (target));
13484 emit_insn (gen_cr6_test_for_lt (target));
13487 emit_insn (gen_cr6_test_for_lt_reverse (target));
13490 error ("argument 1 of %qs is out of range",
13491 "__builtin_altivec_predicate");
13499 swap_endian_selector_for_mode (machine_mode mode)
13501 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13502 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13503 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13504 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13506 unsigned int *swaparray, i;
13526 gcc_unreachable ();
13529 for (i = 0; i < 16; ++i)
13530 perm[i] = GEN_INT (swaparray[i]);
13532 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13533 gen_rtvec_v (16, perm)));
13537 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13540 tree arg0 = CALL_EXPR_ARG (exp, 0);
13541 tree arg1 = CALL_EXPR_ARG (exp, 1);
13542 machine_mode tmode = insn_data[icode].operand[0].mode;
13543 machine_mode mode0 = Pmode;
13544 machine_mode mode1 = Pmode;
13545 rtx op0 = expand_normal (arg0);
13546 rtx op1 = expand_normal (arg1);
13548 if (icode == CODE_FOR_nothing)
13549 /* Builtin not supported on this processor. */
13552 /* If we got invalid arguments bail out before generating bad rtl. */
13553 if (arg0 == error_mark_node || arg1 == error_mark_node)
13557 || GET_MODE (target) != tmode
13558 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13559 target = gen_reg_rtx (tmode);
13561 op1 = copy_to_mode_reg (mode1, op1);
13563 /* For LVX, express the RTL accurately by ANDing the address with -16.
13564 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13565 so the raw address is fine. */
13566 if (icode == CODE_FOR_altivec_lvx_v1ti
13567 || icode == CODE_FOR_altivec_lvx_v2df
13568 || icode == CODE_FOR_altivec_lvx_v2di
13569 || icode == CODE_FOR_altivec_lvx_v4sf
13570 || icode == CODE_FOR_altivec_lvx_v4si
13571 || icode == CODE_FOR_altivec_lvx_v8hi
13572 || icode == CODE_FOR_altivec_lvx_v16qi)
13575 if (op0 == const0_rtx)
13579 op0 = copy_to_mode_reg (mode0, op0);
13580 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
13582 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13583 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
13585 emit_insn (gen_rtx_SET (target, addr));
13589 if (op0 == const0_rtx)
13590 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
13593 op0 = copy_to_mode_reg (mode0, op0);
13594 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
13595 gen_rtx_PLUS (Pmode, op1, op0));
13598 pat = GEN_FCN (icode) (target, addr);
13608 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
13611 tree arg0 = CALL_EXPR_ARG (exp, 0);
13612 tree arg1 = CALL_EXPR_ARG (exp, 1);
13613 tree arg2 = CALL_EXPR_ARG (exp, 2);
13614 rtx op0 = expand_normal (arg0);
13615 rtx op1 = expand_normal (arg1);
13616 rtx op2 = expand_normal (arg2);
13617 machine_mode mode0 = insn_data[icode].operand[0].mode;
13618 machine_mode mode1 = insn_data[icode].operand[1].mode;
13619 machine_mode mode2 = insn_data[icode].operand[2].mode;
13621 if (icode == CODE_FOR_nothing)
13622 /* Builtin not supported on this processor. */
13625 /* If we got invalid arguments bail out before generating bad rtl. */
13626 if (arg0 == error_mark_node
13627 || arg1 == error_mark_node
13628 || arg2 == error_mark_node)
13631 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13632 op0 = copy_to_mode_reg (mode0, op0);
13633 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13634 op1 = copy_to_mode_reg (mode1, op1);
13635 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13636 op2 = copy_to_mode_reg (mode2, op2);
13638 pat = GEN_FCN (icode) (op0, op1, op2);
13646 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
13648 tree arg0 = CALL_EXPR_ARG (exp, 0);
13649 tree arg1 = CALL_EXPR_ARG (exp, 1);
13650 tree arg2 = CALL_EXPR_ARG (exp, 2);
13651 rtx op0 = expand_normal (arg0);
13652 rtx op1 = expand_normal (arg1);
13653 rtx op2 = expand_normal (arg2);
13654 rtx pat, addr, rawaddr;
13655 machine_mode tmode = insn_data[icode].operand[0].mode;
13656 machine_mode smode = insn_data[icode].operand[1].mode;
13657 machine_mode mode1 = Pmode;
13658 machine_mode mode2 = Pmode;
13660 /* Invalid arguments. Bail before doing anything stoopid! */
13661 if (arg0 == error_mark_node
13662 || arg1 == error_mark_node
13663 || arg2 == error_mark_node)
13666 op2 = copy_to_mode_reg (mode2, op2);
13668 /* For STVX, express the RTL accurately by ANDing the address with -16.
13669 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13670 so the raw address is fine. */
13671 if (icode == CODE_FOR_altivec_stvx_v2df
13672 || icode == CODE_FOR_altivec_stvx_v2di
13673 || icode == CODE_FOR_altivec_stvx_v4sf
13674 || icode == CODE_FOR_altivec_stvx_v4si
13675 || icode == CODE_FOR_altivec_stvx_v8hi
13676 || icode == CODE_FOR_altivec_stvx_v16qi)
13678 if (op1 == const0_rtx)
13682 op1 = copy_to_mode_reg (mode1, op1);
13683 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
13686 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13687 addr = gen_rtx_MEM (tmode, addr);
13689 op0 = copy_to_mode_reg (tmode, op0);
13691 emit_insn (gen_rtx_SET (addr, op0));
13695 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
13696 op0 = copy_to_mode_reg (smode, op0);
13698 if (op1 == const0_rtx)
13699 addr = gen_rtx_MEM (tmode, op2);
13702 op1 = copy_to_mode_reg (mode1, op1);
13703 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
13706 pat = GEN_FCN (icode) (addr, op0);
13714 /* Return the appropriate SPR number associated with the given builtin. */
13715 static inline HOST_WIDE_INT
13716 htm_spr_num (enum rs6000_builtins code)
13718 if (code == HTM_BUILTIN_GET_TFHAR
13719 || code == HTM_BUILTIN_SET_TFHAR)
13721 else if (code == HTM_BUILTIN_GET_TFIAR
13722 || code == HTM_BUILTIN_SET_TFIAR)
13724 else if (code == HTM_BUILTIN_GET_TEXASR
13725 || code == HTM_BUILTIN_SET_TEXASR)
13727 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
13728 || code == HTM_BUILTIN_SET_TEXASRU);
13729 return TEXASRU_SPR;
13732 /* Return the correct ICODE value depending on whether we are
13733 setting or reading the HTM SPRs. */
13734 static inline enum insn_code
13735 rs6000_htm_spr_icode (bool nonvoid)
13738 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
13740 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
13743 /* Expand the HTM builtin in EXP and store the result in TARGET.
13744 Store true in *EXPANDEDP if we found a builtin to expand. */
13746 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
13748 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13749 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
13750 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13751 const struct builtin_description *d;
13756 if (!TARGET_POWERPC64
13757 && (fcode == HTM_BUILTIN_TABORTDC
13758 || fcode == HTM_BUILTIN_TABORTDCI))
13760 size_t uns_fcode = (size_t)fcode;
13761 const char *name = rs6000_builtin_info[uns_fcode].name;
13762 error ("builtin %qs is only valid in 64-bit mode", name);
13766 /* Expand the HTM builtins. */
13768 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
13769 if (d->code == fcode)
13771 rtx op[MAX_HTM_OPERANDS], pat;
13774 call_expr_arg_iterator iter;
13775 unsigned attr = rs6000_builtin_info[fcode].attr;
13776 enum insn_code icode = d->icode;
13777 const struct insn_operand_data *insn_op;
13778 bool uses_spr = (attr & RS6000_BTC_SPR);
13782 icode = rs6000_htm_spr_icode (nonvoid);
13783 insn_op = &insn_data[icode].operand[0];
13787 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
13789 || GET_MODE (target) != tmode
13790 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
13791 target = gen_reg_rtx (tmode);
13793 op[nopnds++] = target;
13796 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
13798 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
13801 insn_op = &insn_data[icode].operand[nopnds];
13803 op[nopnds] = expand_normal (arg);
13805 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
13807 if (!strcmp (insn_op->constraint, "n"))
13809 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
13810 if (!CONST_INT_P (op[nopnds]))
13811 error ("argument %d must be an unsigned literal", arg_num);
13813 error ("argument %d is an unsigned literal that is "
13814 "out of range", arg_num);
13817 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
13823 /* Handle the builtins for extended mnemonics. These accept
13824 no arguments, but map to builtins that take arguments. */
13827 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
13828 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
13829 op[nopnds++] = GEN_INT (1);
13831 attr |= RS6000_BTC_UNARY;
13833 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
13834 op[nopnds++] = GEN_INT (0);
13836 attr |= RS6000_BTC_UNARY;
13842 /* If this builtin accesses SPRs, then pass in the appropriate
13843 SPR number and SPR regno as the last two operands. */
13846 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
13847 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
13849 /* If this builtin accesses a CR, then pass in a scratch
13850 CR as the last operand. */
13851 else if (attr & RS6000_BTC_CR)
13852 { cr = gen_reg_rtx (CCmode);
13858 int expected_nopnds = 0;
13859 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
13860 expected_nopnds = 1;
13861 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
13862 expected_nopnds = 2;
13863 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
13864 expected_nopnds = 3;
13865 if (!(attr & RS6000_BTC_VOID))
13866 expected_nopnds += 1;
13868 expected_nopnds += 1;
13870 gcc_assert (nopnds == expected_nopnds
13871 && nopnds <= MAX_HTM_OPERANDS);
13877 pat = GEN_FCN (icode) (op[0]);
13880 pat = GEN_FCN (icode) (op[0], op[1]);
13883 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
13886 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
13889 gcc_unreachable ();
13895 if (attr & RS6000_BTC_CR)
13897 if (fcode == HTM_BUILTIN_TBEGIN)
13899 /* Emit code to set TARGET to true or false depending on
13900 whether the tbegin. instruction successfully or failed
13901 to start a transaction. We do this by placing the 1's
13902 complement of CR's EQ bit into TARGET. */
13903 rtx scratch = gen_reg_rtx (SImode);
13904 emit_insn (gen_rtx_SET (scratch,
13905 gen_rtx_EQ (SImode, cr,
13907 emit_insn (gen_rtx_SET (target,
13908 gen_rtx_XOR (SImode, scratch,
13913 /* Emit code to copy the 4-bit condition register field
13914 CR into the least significant end of register TARGET. */
13915 rtx scratch1 = gen_reg_rtx (SImode);
13916 rtx scratch2 = gen_reg_rtx (SImode);
13917 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
13918 emit_insn (gen_movcc (subreg, cr));
13919 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
13920 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
13929 *expandedp = false;
13933 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
13936 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
13939 /* __builtin_cpu_init () is a nop, so expand to nothing. */
13940 if (fcode == RS6000_BUILTIN_CPU_INIT)
13943 if (target == 0 || GET_MODE (target) != SImode)
13944 target = gen_reg_rtx (SImode);
13946 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
13947 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
13948 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
13949 to a STRING_CST. */
13950 if (TREE_CODE (arg) == ARRAY_REF
13951 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
13952 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
13953 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
13954 arg = TREE_OPERAND (arg, 0);
13956 if (TREE_CODE (arg) != STRING_CST)
13958 error ("builtin %qs only accepts a string argument",
13959 rs6000_builtin_info[(size_t) fcode].name);
13963 if (fcode == RS6000_BUILTIN_CPU_IS)
13965 const char *cpu = TREE_STRING_POINTER (arg);
13966 rtx cpuid = NULL_RTX;
13967 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
13968 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
13970 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
13971 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
13974 if (cpuid == NULL_RTX)
13976 /* Invalid CPU argument. */
13977 error ("cpu %qs is an invalid argument to builtin %qs",
13978 cpu, rs6000_builtin_info[(size_t) fcode].name);
13982 rtx platform = gen_reg_rtx (SImode);
13983 rtx tcbmem = gen_const_mem (SImode,
13984 gen_rtx_PLUS (Pmode,
13985 gen_rtx_REG (Pmode, TLS_REGNUM),
13986 GEN_INT (TCB_PLATFORM_OFFSET)));
13987 emit_move_insn (platform, tcbmem);
13988 emit_insn (gen_eqsi3 (target, platform, cpuid));
13990 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
13992 const char *hwcap = TREE_STRING_POINTER (arg);
13993 rtx mask = NULL_RTX;
13995 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
13996 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
13998 mask = GEN_INT (cpu_supports_info[i].mask);
13999 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14002 if (mask == NULL_RTX)
14004 /* Invalid HWCAP argument. */
14005 error ("%s %qs is an invalid argument to builtin %qs",
14006 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14010 rtx tcb_hwcap = gen_reg_rtx (SImode);
14011 rtx tcbmem = gen_const_mem (SImode,
14012 gen_rtx_PLUS (Pmode,
14013 gen_rtx_REG (Pmode, TLS_REGNUM),
14014 GEN_INT (hwcap_offset)));
14015 emit_move_insn (tcb_hwcap, tcbmem);
14016 rtx scratch1 = gen_reg_rtx (SImode);
14017 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14018 rtx scratch2 = gen_reg_rtx (SImode);
14019 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14020 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14023 gcc_unreachable ();
14025 /* Record that we have expanded a CPU builtin, so that we can later
14026 emit a reference to the special symbol exported by LIBC to ensure we
14027 do not link against an old LIBC that doesn't support this feature. */
14028 cpu_builtin_p = true;
14031 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14032 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14034 /* For old LIBCs, always return FALSE. */
14035 emit_move_insn (target, GEN_INT (0));
14036 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14042 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14045 tree arg0 = CALL_EXPR_ARG (exp, 0);
14046 tree arg1 = CALL_EXPR_ARG (exp, 1);
14047 tree arg2 = CALL_EXPR_ARG (exp, 2);
14048 rtx op0 = expand_normal (arg0);
14049 rtx op1 = expand_normal (arg1);
14050 rtx op2 = expand_normal (arg2);
14051 machine_mode tmode = insn_data[icode].operand[0].mode;
14052 machine_mode mode0 = insn_data[icode].operand[1].mode;
14053 machine_mode mode1 = insn_data[icode].operand[2].mode;
14054 machine_mode mode2 = insn_data[icode].operand[3].mode;
14056 if (icode == CODE_FOR_nothing)
14057 /* Builtin not supported on this processor. */
14060 /* If we got invalid arguments bail out before generating bad rtl. */
14061 if (arg0 == error_mark_node
14062 || arg1 == error_mark_node
14063 || arg2 == error_mark_node)
14066 /* Check and prepare argument depending on the instruction code.
14068 Note that a switch statement instead of the sequence of tests
14069 would be incorrect as many of the CODE_FOR values could be
14070 CODE_FOR_nothing and that would yield multiple alternatives
14071 with identical values. We'd never reach here at runtime in
14073 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14074 || icode == CODE_FOR_altivec_vsldoi_v2df
14075 || icode == CODE_FOR_altivec_vsldoi_v4si
14076 || icode == CODE_FOR_altivec_vsldoi_v8hi
14077 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14079 /* Only allow 4-bit unsigned literals. */
14081 if (TREE_CODE (arg2) != INTEGER_CST
14082 || TREE_INT_CST_LOW (arg2) & ~0xf)
14084 error ("argument 3 must be a 4-bit unsigned literal");
14085 return CONST0_RTX (tmode);
14088 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14089 || icode == CODE_FOR_vsx_xxpermdi_v2di
14090 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14091 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14092 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14093 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14094 || icode == CODE_FOR_vsx_xxpermdi_v4si
14095 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14096 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14097 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14098 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14099 || icode == CODE_FOR_vsx_xxsldwi_v4si
14100 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14101 || icode == CODE_FOR_vsx_xxsldwi_v2di
14102 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14104 /* Only allow 2-bit unsigned literals. */
14106 if (TREE_CODE (arg2) != INTEGER_CST
14107 || TREE_INT_CST_LOW (arg2) & ~0x3)
14109 error ("argument 3 must be a 2-bit unsigned literal");
14110 return CONST0_RTX (tmode);
14113 else if (icode == CODE_FOR_vsx_set_v2df
14114 || icode == CODE_FOR_vsx_set_v2di
14115 || icode == CODE_FOR_bcdadd
14116 || icode == CODE_FOR_bcdadd_lt
14117 || icode == CODE_FOR_bcdadd_eq
14118 || icode == CODE_FOR_bcdadd_gt
14119 || icode == CODE_FOR_bcdsub
14120 || icode == CODE_FOR_bcdsub_lt
14121 || icode == CODE_FOR_bcdsub_eq
14122 || icode == CODE_FOR_bcdsub_gt)
14124 /* Only allow 1-bit unsigned literals. */
14126 if (TREE_CODE (arg2) != INTEGER_CST
14127 || TREE_INT_CST_LOW (arg2) & ~0x1)
14129 error ("argument 3 must be a 1-bit unsigned literal");
14130 return CONST0_RTX (tmode);
14133 else if (icode == CODE_FOR_dfp_ddedpd_dd
14134 || icode == CODE_FOR_dfp_ddedpd_td)
14136 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14138 if (TREE_CODE (arg0) != INTEGER_CST
14139 || TREE_INT_CST_LOW (arg2) & ~0x3)
14141 error ("argument 1 must be 0 or 2");
14142 return CONST0_RTX (tmode);
14145 else if (icode == CODE_FOR_dfp_denbcd_dd
14146 || icode == CODE_FOR_dfp_denbcd_td)
14148 /* Only allow 1-bit unsigned literals. */
14150 if (TREE_CODE (arg0) != INTEGER_CST
14151 || TREE_INT_CST_LOW (arg0) & ~0x1)
14153 error ("argument 1 must be a 1-bit unsigned literal");
14154 return CONST0_RTX (tmode);
14157 else if (icode == CODE_FOR_dfp_dscli_dd
14158 || icode == CODE_FOR_dfp_dscli_td
14159 || icode == CODE_FOR_dfp_dscri_dd
14160 || icode == CODE_FOR_dfp_dscri_td)
14162 /* Only allow 6-bit unsigned literals. */
14164 if (TREE_CODE (arg1) != INTEGER_CST
14165 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14167 error ("argument 2 must be a 6-bit unsigned literal");
14168 return CONST0_RTX (tmode);
14171 else if (icode == CODE_FOR_crypto_vshasigmaw
14172 || icode == CODE_FOR_crypto_vshasigmad)
14174 /* Check whether the 2nd and 3rd arguments are integer constants and in
14175 range and prepare arguments. */
14177 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14179 error ("argument 2 must be 0 or 1");
14180 return CONST0_RTX (tmode);
14184 if (TREE_CODE (arg2) != INTEGER_CST
14185 || wi::geu_p (wi::to_wide (arg2), 16))
14187 error ("argument 3 must be in the range [0, 15]");
14188 return CONST0_RTX (tmode);
14193 || GET_MODE (target) != tmode
14194 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14195 target = gen_reg_rtx (tmode);
14197 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14198 op0 = copy_to_mode_reg (mode0, op0);
14199 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14200 op1 = copy_to_mode_reg (mode1, op1);
14201 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14202 op2 = copy_to_mode_reg (mode2, op2);
14204 pat = GEN_FCN (icode) (target, op0, op1, op2);
14213 /* Expand the dst builtins. */
14215 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14218 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14219 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14220 tree arg0, arg1, arg2;
14221 machine_mode mode0, mode1;
14222 rtx pat, op0, op1, op2;
14223 const struct builtin_description *d;
14226 *expandedp = false;
14228 /* Handle DST variants. */
14230 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14231 if (d->code == fcode)
14233 arg0 = CALL_EXPR_ARG (exp, 0);
14234 arg1 = CALL_EXPR_ARG (exp, 1);
14235 arg2 = CALL_EXPR_ARG (exp, 2);
14236 op0 = expand_normal (arg0);
14237 op1 = expand_normal (arg1);
14238 op2 = expand_normal (arg2);
14239 mode0 = insn_data[d->icode].operand[0].mode;
14240 mode1 = insn_data[d->icode].operand[1].mode;
14242 /* Invalid arguments, bail out before generating bad rtl. */
14243 if (arg0 == error_mark_node
14244 || arg1 == error_mark_node
14245 || arg2 == error_mark_node)
14250 if (TREE_CODE (arg2) != INTEGER_CST
14251 || TREE_INT_CST_LOW (arg2) & ~0x3)
14253 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14257 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14258 op0 = copy_to_mode_reg (Pmode, op0);
14259 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14260 op1 = copy_to_mode_reg (mode1, op1);
14262 pat = GEN_FCN (d->icode) (op0, op1, op2);
14272 /* Expand vec_init builtin. */
14274 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14276 machine_mode tmode = TYPE_MODE (type);
14277 machine_mode inner_mode = GET_MODE_INNER (tmode);
14278 int i, n_elt = GET_MODE_NUNITS (tmode);
14280 gcc_assert (VECTOR_MODE_P (tmode));
14281 gcc_assert (n_elt == call_expr_nargs (exp));
14283 if (!target || !register_operand (target, tmode))
14284 target = gen_reg_rtx (tmode);
14286 /* If we have a vector compromised of a single element, such as V1TImode, do
14287 the initialization directly. */
14288 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14290 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14291 emit_move_insn (target, gen_lowpart (tmode, x));
14295 rtvec v = rtvec_alloc (n_elt);
14297 for (i = 0; i < n_elt; ++i)
14299 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14300 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14303 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14309 /* Return the integer constant in ARG. Constrain it to be in the range
14310 of the subparts of VEC_TYPE; issue an error if not. */
14313 get_element_number (tree vec_type, tree arg)
14315 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14317 if (!tree_fits_uhwi_p (arg)
14318 || (elt = tree_to_uhwi (arg), elt > max))
14320 error ("selector must be an integer constant in the range [0, %wi]", max);
14327 /* Expand vec_set builtin. */
14329 altivec_expand_vec_set_builtin (tree exp)
14331 machine_mode tmode, mode1;
14332 tree arg0, arg1, arg2;
14336 arg0 = CALL_EXPR_ARG (exp, 0);
14337 arg1 = CALL_EXPR_ARG (exp, 1);
14338 arg2 = CALL_EXPR_ARG (exp, 2);
14340 tmode = TYPE_MODE (TREE_TYPE (arg0));
14341 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14342 gcc_assert (VECTOR_MODE_P (tmode));
14344 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14345 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14346 elt = get_element_number (TREE_TYPE (arg0), arg2);
14348 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14349 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14351 op0 = force_reg (tmode, op0);
14352 op1 = force_reg (mode1, op1);
14354 rs6000_expand_vector_set (op0, op1, elt);
14359 /* Expand vec_ext builtin. */
14361 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14363 machine_mode tmode, mode0;
14368 arg0 = CALL_EXPR_ARG (exp, 0);
14369 arg1 = CALL_EXPR_ARG (exp, 1);
14371 op0 = expand_normal (arg0);
14372 op1 = expand_normal (arg1);
14374 if (TREE_CODE (arg1) == INTEGER_CST)
14376 unsigned HOST_WIDE_INT elt;
14377 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
14378 unsigned int truncated_selector;
14379 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
14380 returns low-order bits of INTEGER_CST for modulo indexing. */
14381 elt = TREE_INT_CST_LOW (arg1);
14382 truncated_selector = elt % size;
14383 op1 = GEN_INT (truncated_selector);
14386 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14387 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14388 gcc_assert (VECTOR_MODE_P (mode0));
14390 op0 = force_reg (mode0, op0);
14392 if (optimize || !target || !register_operand (target, tmode))
14393 target = gen_reg_rtx (tmode);
14395 rs6000_expand_vector_extract (target, op0, op1);
14400 /* Expand the builtin in EXP and store the result in TARGET. Store
14401 true in *EXPANDEDP if we found a builtin to expand. */
14403 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14405 const struct builtin_description *d;
14407 enum insn_code icode;
14408 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14409 tree arg0, arg1, arg2;
14411 machine_mode tmode, mode0;
14412 enum rs6000_builtins fcode
14413 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14415 if (rs6000_overloaded_builtin_p (fcode))
14418 error ("unresolved overload for Altivec builtin %qF", fndecl);
14420 /* Given it is invalid, just generate a normal call. */
14421 return expand_call (exp, target, false);
14424 target = altivec_expand_dst_builtin (exp, target, expandedp);
14432 case ALTIVEC_BUILTIN_STVX_V2DF:
14433 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14434 case ALTIVEC_BUILTIN_STVX_V2DI:
14435 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14436 case ALTIVEC_BUILTIN_STVX_V4SF:
14437 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14438 case ALTIVEC_BUILTIN_STVX:
14439 case ALTIVEC_BUILTIN_STVX_V4SI:
14440 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14441 case ALTIVEC_BUILTIN_STVX_V8HI:
14442 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14443 case ALTIVEC_BUILTIN_STVX_V16QI:
14444 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14445 case ALTIVEC_BUILTIN_STVEBX:
14446 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14447 case ALTIVEC_BUILTIN_STVEHX:
14448 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14449 case ALTIVEC_BUILTIN_STVEWX:
14450 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14451 case ALTIVEC_BUILTIN_STVXL_V2DF:
14452 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14453 case ALTIVEC_BUILTIN_STVXL_V2DI:
14454 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14455 case ALTIVEC_BUILTIN_STVXL_V4SF:
14456 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14457 case ALTIVEC_BUILTIN_STVXL:
14458 case ALTIVEC_BUILTIN_STVXL_V4SI:
14459 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14460 case ALTIVEC_BUILTIN_STVXL_V8HI:
14461 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14462 case ALTIVEC_BUILTIN_STVXL_V16QI:
14463 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14465 case ALTIVEC_BUILTIN_STVLX:
14466 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14467 case ALTIVEC_BUILTIN_STVLXL:
14468 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14469 case ALTIVEC_BUILTIN_STVRX:
14470 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14471 case ALTIVEC_BUILTIN_STVRXL:
14472 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14474 case P9V_BUILTIN_STXVL:
14475 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14477 case P9V_BUILTIN_XST_LEN_R:
14478 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14480 case VSX_BUILTIN_STXVD2X_V1TI:
14481 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14482 case VSX_BUILTIN_STXVD2X_V2DF:
14483 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14484 case VSX_BUILTIN_STXVD2X_V2DI:
14485 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14486 case VSX_BUILTIN_STXVW4X_V4SF:
14487 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14488 case VSX_BUILTIN_STXVW4X_V4SI:
14489 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14490 case VSX_BUILTIN_STXVW4X_V8HI:
14491 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14492 case VSX_BUILTIN_STXVW4X_V16QI:
14493 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14495 /* For the following on big endian, it's ok to use any appropriate
14496 unaligned-supporting store, so use a generic expander. For
14497 little-endian, the exact element-reversing instruction must
14499 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14501 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14502 : CODE_FOR_vsx_st_elemrev_v1ti);
14503 return altivec_expand_stv_builtin (code, exp);
14505 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14507 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14508 : CODE_FOR_vsx_st_elemrev_v2df);
14509 return altivec_expand_stv_builtin (code, exp);
14511 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14513 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14514 : CODE_FOR_vsx_st_elemrev_v2di);
14515 return altivec_expand_stv_builtin (code, exp);
14517 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14519 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14520 : CODE_FOR_vsx_st_elemrev_v4sf);
14521 return altivec_expand_stv_builtin (code, exp);
14523 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14525 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14526 : CODE_FOR_vsx_st_elemrev_v4si);
14527 return altivec_expand_stv_builtin (code, exp);
14529 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14531 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14532 : CODE_FOR_vsx_st_elemrev_v8hi);
14533 return altivec_expand_stv_builtin (code, exp);
14535 case VSX_BUILTIN_ST_ELEMREV_V16QI:
14537 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
14538 : CODE_FOR_vsx_st_elemrev_v16qi);
14539 return altivec_expand_stv_builtin (code, exp);
14542 case ALTIVEC_BUILTIN_MFVSCR:
14543 icode = CODE_FOR_altivec_mfvscr;
14544 tmode = insn_data[icode].operand[0].mode;
14547 || GET_MODE (target) != tmode
14548 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14549 target = gen_reg_rtx (tmode);
14551 pat = GEN_FCN (icode) (target);
14557 case ALTIVEC_BUILTIN_MTVSCR:
14558 icode = CODE_FOR_altivec_mtvscr;
14559 arg0 = CALL_EXPR_ARG (exp, 0);
14560 op0 = expand_normal (arg0);
14561 mode0 = insn_data[icode].operand[0].mode;
14563 /* If we got invalid arguments bail out before generating bad rtl. */
14564 if (arg0 == error_mark_node)
14567 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14568 op0 = copy_to_mode_reg (mode0, op0);
14570 pat = GEN_FCN (icode) (op0);
14575 case ALTIVEC_BUILTIN_DSSALL:
14576 emit_insn (gen_altivec_dssall ());
14579 case ALTIVEC_BUILTIN_DSS:
14580 icode = CODE_FOR_altivec_dss;
14581 arg0 = CALL_EXPR_ARG (exp, 0);
14583 op0 = expand_normal (arg0);
14584 mode0 = insn_data[icode].operand[0].mode;
14586 /* If we got invalid arguments bail out before generating bad rtl. */
14587 if (arg0 == error_mark_node)
14590 if (TREE_CODE (arg0) != INTEGER_CST
14591 || TREE_INT_CST_LOW (arg0) & ~0x3)
14593 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14597 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14598 op0 = copy_to_mode_reg (mode0, op0);
14600 emit_insn (gen_altivec_dss (op0));
14603 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
14604 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
14605 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
14606 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
14607 case VSX_BUILTIN_VEC_INIT_V2DF:
14608 case VSX_BUILTIN_VEC_INIT_V2DI:
14609 case VSX_BUILTIN_VEC_INIT_V1TI:
14610 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
14612 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
14613 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
14614 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
14615 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
14616 case VSX_BUILTIN_VEC_SET_V2DF:
14617 case VSX_BUILTIN_VEC_SET_V2DI:
14618 case VSX_BUILTIN_VEC_SET_V1TI:
14619 return altivec_expand_vec_set_builtin (exp);
14621 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
14622 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
14623 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
14624 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
14625 case VSX_BUILTIN_VEC_EXT_V2DF:
14626 case VSX_BUILTIN_VEC_EXT_V2DI:
14627 case VSX_BUILTIN_VEC_EXT_V1TI:
14628 return altivec_expand_vec_ext_builtin (exp, target);
14630 case P9V_BUILTIN_VEC_EXTRACT4B:
14631 arg1 = CALL_EXPR_ARG (exp, 1);
14634 /* Generate a normal call if it is invalid. */
14635 if (arg1 == error_mark_node)
14636 return expand_call (exp, target, false);
14638 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
14640 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
14641 return expand_call (exp, target, false);
14645 case P9V_BUILTIN_VEC_INSERT4B:
14646 arg2 = CALL_EXPR_ARG (exp, 2);
14649 /* Generate a normal call if it is invalid. */
14650 if (arg2 == error_mark_node)
14651 return expand_call (exp, target, false);
14653 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
14655 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
14656 return expand_call (exp, target, false);
14662 /* Fall through. */
14665 /* Expand abs* operations. */
14667 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14668 if (d->code == fcode)
14669 return altivec_expand_abs_builtin (d->icode, exp, target);
14671 /* Expand the AltiVec predicates. */
14672 d = bdesc_altivec_preds;
14673 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14674 if (d->code == fcode)
14675 return altivec_expand_predicate_builtin (d->icode, exp, target);
14677 /* LV* are funky. We initialized them differently. */
14680 case ALTIVEC_BUILTIN_LVSL:
14681 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
14682 exp, target, false);
14683 case ALTIVEC_BUILTIN_LVSR:
14684 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
14685 exp, target, false);
14686 case ALTIVEC_BUILTIN_LVEBX:
14687 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
14688 exp, target, false);
14689 case ALTIVEC_BUILTIN_LVEHX:
14690 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
14691 exp, target, false);
14692 case ALTIVEC_BUILTIN_LVEWX:
14693 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
14694 exp, target, false);
14695 case ALTIVEC_BUILTIN_LVXL_V2DF:
14696 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
14697 exp, target, false);
14698 case ALTIVEC_BUILTIN_LVXL_V2DI:
14699 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
14700 exp, target, false);
14701 case ALTIVEC_BUILTIN_LVXL_V4SF:
14702 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
14703 exp, target, false);
14704 case ALTIVEC_BUILTIN_LVXL:
14705 case ALTIVEC_BUILTIN_LVXL_V4SI:
14706 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
14707 exp, target, false);
14708 case ALTIVEC_BUILTIN_LVXL_V8HI:
14709 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
14710 exp, target, false);
14711 case ALTIVEC_BUILTIN_LVXL_V16QI:
14712 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
14713 exp, target, false);
14714 case ALTIVEC_BUILTIN_LVX_V1TI:
14715 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
14716 exp, target, false);
14717 case ALTIVEC_BUILTIN_LVX_V2DF:
14718 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
14719 exp, target, false);
14720 case ALTIVEC_BUILTIN_LVX_V2DI:
14721 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
14722 exp, target, false);
14723 case ALTIVEC_BUILTIN_LVX_V4SF:
14724 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
14725 exp, target, false);
14726 case ALTIVEC_BUILTIN_LVX:
14727 case ALTIVEC_BUILTIN_LVX_V4SI:
14728 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
14729 exp, target, false);
14730 case ALTIVEC_BUILTIN_LVX_V8HI:
14731 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
14732 exp, target, false);
14733 case ALTIVEC_BUILTIN_LVX_V16QI:
14734 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
14735 exp, target, false);
14736 case ALTIVEC_BUILTIN_LVLX:
14737 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
14738 exp, target, true);
14739 case ALTIVEC_BUILTIN_LVLXL:
14740 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
14741 exp, target, true);
14742 case ALTIVEC_BUILTIN_LVRX:
14743 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
14744 exp, target, true);
14745 case ALTIVEC_BUILTIN_LVRXL:
14746 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
14747 exp, target, true);
14748 case VSX_BUILTIN_LXVD2X_V1TI:
14749 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
14750 exp, target, false);
14751 case VSX_BUILTIN_LXVD2X_V2DF:
14752 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
14753 exp, target, false);
14754 case VSX_BUILTIN_LXVD2X_V2DI:
14755 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
14756 exp, target, false);
14757 case VSX_BUILTIN_LXVW4X_V4SF:
14758 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
14759 exp, target, false);
14760 case VSX_BUILTIN_LXVW4X_V4SI:
14761 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
14762 exp, target, false);
14763 case VSX_BUILTIN_LXVW4X_V8HI:
14764 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
14765 exp, target, false);
14766 case VSX_BUILTIN_LXVW4X_V16QI:
14767 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
14768 exp, target, false);
14769 /* For the following on big endian, it's ok to use any appropriate
14770 unaligned-supporting load, so use a generic expander. For
14771 little-endian, the exact element-reversing instruction must
14773 case VSX_BUILTIN_LD_ELEMREV_V2DF:
14775 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
14776 : CODE_FOR_vsx_ld_elemrev_v2df);
14777 return altivec_expand_lv_builtin (code, exp, target, false);
14779 case VSX_BUILTIN_LD_ELEMREV_V1TI:
14781 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
14782 : CODE_FOR_vsx_ld_elemrev_v1ti);
14783 return altivec_expand_lv_builtin (code, exp, target, false);
14785 case VSX_BUILTIN_LD_ELEMREV_V2DI:
14787 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
14788 : CODE_FOR_vsx_ld_elemrev_v2di);
14789 return altivec_expand_lv_builtin (code, exp, target, false);
14791 case VSX_BUILTIN_LD_ELEMREV_V4SF:
14793 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
14794 : CODE_FOR_vsx_ld_elemrev_v4sf);
14795 return altivec_expand_lv_builtin (code, exp, target, false);
14797 case VSX_BUILTIN_LD_ELEMREV_V4SI:
14799 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
14800 : CODE_FOR_vsx_ld_elemrev_v4si);
14801 return altivec_expand_lv_builtin (code, exp, target, false);
14803 case VSX_BUILTIN_LD_ELEMREV_V8HI:
14805 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
14806 : CODE_FOR_vsx_ld_elemrev_v8hi);
14807 return altivec_expand_lv_builtin (code, exp, target, false);
14809 case VSX_BUILTIN_LD_ELEMREV_V16QI:
14811 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
14812 : CODE_FOR_vsx_ld_elemrev_v16qi);
14813 return altivec_expand_lv_builtin (code, exp, target, false);
14818 /* Fall through. */
14821 *expandedp = false;
14825 /* Check whether a builtin function is supported in this target
14828 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
14830 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
14831 if ((fnmask & rs6000_builtin_mask) != fnmask)
14837 /* Raise an error message for a builtin function that is called without the
14838 appropriate target options being set. */
14841 rs6000_invalid_builtin (enum rs6000_builtins fncode)
14843 size_t uns_fncode = (size_t) fncode;
14844 const char *name = rs6000_builtin_info[uns_fncode].name;
14845 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
14847 gcc_assert (name != NULL);
14848 if ((fnmask & RS6000_BTM_CELL) != 0)
14849 error ("builtin function %qs is only valid for the cell processor", name);
14850 else if ((fnmask & RS6000_BTM_VSX) != 0)
14851 error ("builtin function %qs requires the %qs option", name, "-mvsx");
14852 else if ((fnmask & RS6000_BTM_HTM) != 0)
14853 error ("builtin function %qs requires the %qs option", name, "-mhtm");
14854 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
14855 error ("builtin function %qs requires the %qs option", name, "-maltivec");
14856 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14857 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14858 error ("builtin function %qs requires the %qs and %qs options",
14859 name, "-mhard-dfp", "-mpower8-vector");
14860 else if ((fnmask & RS6000_BTM_DFP) != 0)
14861 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
14862 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
14863 error ("builtin function %qs requires the %qs option", name,
14864 "-mpower8-vector");
14865 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14866 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14867 error ("builtin function %qs requires the %qs and %qs options",
14868 name, "-mcpu=power9", "-m64");
14869 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
14870 error ("builtin function %qs requires the %qs option", name,
14872 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14873 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14874 error ("builtin function %qs requires the %qs and %qs options",
14875 name, "-mcpu=power9", "-m64");
14876 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
14877 error ("builtin function %qs requires the %qs option", name,
14879 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
14881 if (!TARGET_HARD_FLOAT)
14882 error ("builtin function %qs requires the %qs option", name,
14885 error ("builtin function %qs requires the %qs option", name,
14886 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
14888 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
14889 error ("builtin function %qs requires the %qs option", name,
14891 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
14892 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
14894 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
14895 error ("builtin function %qs requires the %qs option", name,
14897 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14898 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14899 error ("builtin function %qs requires the %qs (or newer), and "
14900 "%qs or %qs options",
14901 name, "-mcpu=power7", "-m64", "-mpowerpc64");
14903 error ("builtin function %qs is not supported with the current options",
14907 /* Target hook for early folding of built-ins, shamelessly stolen
14911 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
14912 int n_args ATTRIBUTE_UNUSED,
14913 tree *args ATTRIBUTE_UNUSED,
14914 bool ignore ATTRIBUTE_UNUSED)
14916 #ifdef SUBTARGET_FOLD_BUILTIN
14917 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
14923 /* Helper function to sort out which built-ins may be valid without having
14926 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
14930 case ALTIVEC_BUILTIN_STVX_V16QI:
14931 case ALTIVEC_BUILTIN_STVX_V8HI:
14932 case ALTIVEC_BUILTIN_STVX_V4SI:
14933 case ALTIVEC_BUILTIN_STVX_V4SF:
14934 case ALTIVEC_BUILTIN_STVX_V2DI:
14935 case ALTIVEC_BUILTIN_STVX_V2DF:
14936 case VSX_BUILTIN_STXVW4X_V16QI:
14937 case VSX_BUILTIN_STXVW4X_V8HI:
14938 case VSX_BUILTIN_STXVW4X_V4SF:
14939 case VSX_BUILTIN_STXVW4X_V4SI:
14940 case VSX_BUILTIN_STXVD2X_V2DF:
14941 case VSX_BUILTIN_STXVD2X_V2DI:
14948 /* Helper function to handle the gimple folding of a vector compare
14949 operation. This sets up true/false vectors, and uses the
14950 VEC_COND_EXPR operation.
14951 CODE indicates which comparison is to be made. (EQ, GT, ...).
14952 TYPE indicates the type of the result. */
14954 fold_build_vec_cmp (tree_code code, tree type,
14955 tree arg0, tree arg1)
14957 tree cmp_type = build_same_sized_truth_vector_type (type);
14958 tree zero_vec = build_zero_cst (type);
14959 tree minus_one_vec = build_minus_one_cst (type);
14960 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
14961 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
14964 /* Helper function to handle the in-between steps for the
14965 vector compare built-ins. */
14967 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
14969 tree arg0 = gimple_call_arg (stmt, 0);
14970 tree arg1 = gimple_call_arg (stmt, 1);
14971 tree lhs = gimple_call_lhs (stmt);
14972 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
14973 gimple *g = gimple_build_assign (lhs, cmp);
14974 gimple_set_location (g, gimple_location (stmt));
14975 gsi_replace (gsi, g, true);
14978 /* Helper function to map V2DF and V4SF types to their
14979 integral equivalents (V2DI and V4SI). */
14980 tree map_to_integral_tree_type (tree input_tree_type)
14982 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
14983 return input_tree_type;
14986 if (types_compatible_p (TREE_TYPE (input_tree_type),
14987 TREE_TYPE (V2DF_type_node)))
14988 return V2DI_type_node;
14989 else if (types_compatible_p (TREE_TYPE (input_tree_type),
14990 TREE_TYPE (V4SF_type_node)))
14991 return V4SI_type_node;
14993 gcc_unreachable ();
14997 /* Helper function to handle the vector merge[hl] built-ins. The
14998 implementation difference between h and l versions for this code are in
14999 the values used when building of the permute vector for high word versus
15000 low word merge. The variance is keyed off the use_high parameter. */
15002 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
15004 tree arg0 = gimple_call_arg (stmt, 0);
15005 tree arg1 = gimple_call_arg (stmt, 1);
15006 tree lhs = gimple_call_lhs (stmt);
15007 tree lhs_type = TREE_TYPE (lhs);
15008 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15009 int midpoint = n_elts / 2;
15015 /* The permute_type will match the lhs for integral types. For double and
15016 float types, the permute type needs to map to the V2 or V4 type that
15019 permute_type = map_to_integral_tree_type (lhs_type);
15020 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15022 for (int i = 0; i < midpoint; i++)
15024 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15026 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15027 offset + n_elts + i));
15030 tree permute = elts.build ();
15032 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15033 gimple_set_location (g, gimple_location (stmt));
15034 gsi_replace (gsi, g, true);
15037 /* Helper function to handle the vector merge[eo] built-ins. */
15039 fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
15041 tree arg0 = gimple_call_arg (stmt, 0);
15042 tree arg1 = gimple_call_arg (stmt, 1);
15043 tree lhs = gimple_call_lhs (stmt);
15044 tree lhs_type = TREE_TYPE (lhs);
15045 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15047 /* The permute_type will match the lhs for integral types. For double and
15048 float types, the permute type needs to map to the V2 or V4 type that
15051 permute_type = map_to_integral_tree_type (lhs_type);
15053 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15055 /* Build the permute vector. */
15056 for (int i = 0; i < n_elts / 2; i++)
15058 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15060 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15061 2*i + use_odd + n_elts));
15064 tree permute = elts.build ();
15066 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15067 gimple_set_location (g, gimple_location (stmt));
15068 gsi_replace (gsi, g, true);
15071 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15072 a constant, use rs6000_fold_builtin.) */
15075 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15077 gimple *stmt = gsi_stmt (*gsi);
15078 tree fndecl = gimple_call_fndecl (stmt);
15079 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15080 enum rs6000_builtins fn_code
15081 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15082 tree arg0, arg1, lhs, temp;
15083 enum tree_code bcode;
15086 size_t uns_fncode = (size_t) fn_code;
15087 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15088 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15089 const char *fn_name2 = (icode != CODE_FOR_nothing)
15090 ? get_insn_name ((int) icode)
15093 if (TARGET_DEBUG_BUILTIN)
15094 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15095 fn_code, fn_name1, fn_name2);
15097 if (!rs6000_fold_gimple)
15100 /* Prevent gimple folding for code that does not have a LHS, unless it is
15101 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15102 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15105 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15106 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15107 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15113 /* Flavors of vec_add. We deliberately don't expand
15114 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15115 TImode, resulting in much poorer code generation. */
15116 case ALTIVEC_BUILTIN_VADDUBM:
15117 case ALTIVEC_BUILTIN_VADDUHM:
15118 case ALTIVEC_BUILTIN_VADDUWM:
15119 case P8V_BUILTIN_VADDUDM:
15120 case ALTIVEC_BUILTIN_VADDFP:
15121 case VSX_BUILTIN_XVADDDP:
15124 arg0 = gimple_call_arg (stmt, 0);
15125 arg1 = gimple_call_arg (stmt, 1);
15126 lhs = gimple_call_lhs (stmt);
15127 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
15128 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
15130 /* Ensure the binary operation is performed in a type
15131 that wraps if it is integral type. */
15132 gimple_seq stmts = NULL;
15133 tree type = unsigned_type_for (TREE_TYPE (lhs));
15134 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15136 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15138 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
15139 type, uarg0, uarg1);
15140 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15141 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
15142 build1 (VIEW_CONVERT_EXPR,
15143 TREE_TYPE (lhs), res));
15144 gsi_replace (gsi, g, true);
15147 g = gimple_build_assign (lhs, bcode, arg0, arg1);
15148 gimple_set_location (g, gimple_location (stmt));
15149 gsi_replace (gsi, g, true);
15151 /* Flavors of vec_sub. We deliberately don't expand
15152 P8V_BUILTIN_VSUBUQM. */
15153 case ALTIVEC_BUILTIN_VSUBUBM:
15154 case ALTIVEC_BUILTIN_VSUBUHM:
15155 case ALTIVEC_BUILTIN_VSUBUWM:
15156 case P8V_BUILTIN_VSUBUDM:
15157 case ALTIVEC_BUILTIN_VSUBFP:
15158 case VSX_BUILTIN_XVSUBDP:
15159 bcode = MINUS_EXPR;
15161 case VSX_BUILTIN_XVMULSP:
15162 case VSX_BUILTIN_XVMULDP:
15163 arg0 = gimple_call_arg (stmt, 0);
15164 arg1 = gimple_call_arg (stmt, 1);
15165 lhs = gimple_call_lhs (stmt);
15166 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15167 gimple_set_location (g, gimple_location (stmt));
15168 gsi_replace (gsi, g, true);
15170 /* Even element flavors of vec_mul (signed). */
15171 case ALTIVEC_BUILTIN_VMULESB:
15172 case ALTIVEC_BUILTIN_VMULESH:
15173 case P8V_BUILTIN_VMULESW:
15174 /* Even element flavors of vec_mul (unsigned). */
15175 case ALTIVEC_BUILTIN_VMULEUB:
15176 case ALTIVEC_BUILTIN_VMULEUH:
15177 case P8V_BUILTIN_VMULEUW:
15178 arg0 = gimple_call_arg (stmt, 0);
15179 arg1 = gimple_call_arg (stmt, 1);
15180 lhs = gimple_call_lhs (stmt);
15181 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15182 gimple_set_location (g, gimple_location (stmt));
15183 gsi_replace (gsi, g, true);
15185 /* Odd element flavors of vec_mul (signed). */
15186 case ALTIVEC_BUILTIN_VMULOSB:
15187 case ALTIVEC_BUILTIN_VMULOSH:
15188 case P8V_BUILTIN_VMULOSW:
15189 /* Odd element flavors of vec_mul (unsigned). */
15190 case ALTIVEC_BUILTIN_VMULOUB:
15191 case ALTIVEC_BUILTIN_VMULOUH:
15192 case P8V_BUILTIN_VMULOUW:
15193 arg0 = gimple_call_arg (stmt, 0);
15194 arg1 = gimple_call_arg (stmt, 1);
15195 lhs = gimple_call_lhs (stmt);
15196 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15197 gimple_set_location (g, gimple_location (stmt));
15198 gsi_replace (gsi, g, true);
15200 /* Flavors of vec_div (Integer). */
15201 case VSX_BUILTIN_DIV_V2DI:
15202 case VSX_BUILTIN_UDIV_V2DI:
15203 arg0 = gimple_call_arg (stmt, 0);
15204 arg1 = gimple_call_arg (stmt, 1);
15205 lhs = gimple_call_lhs (stmt);
15206 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15207 gimple_set_location (g, gimple_location (stmt));
15208 gsi_replace (gsi, g, true);
15210 /* Flavors of vec_div (Float). */
15211 case VSX_BUILTIN_XVDIVSP:
15212 case VSX_BUILTIN_XVDIVDP:
15213 arg0 = gimple_call_arg (stmt, 0);
15214 arg1 = gimple_call_arg (stmt, 1);
15215 lhs = gimple_call_lhs (stmt);
15216 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15217 gimple_set_location (g, gimple_location (stmt));
15218 gsi_replace (gsi, g, true);
15220 /* Flavors of vec_and. */
15221 case ALTIVEC_BUILTIN_VAND:
15222 arg0 = gimple_call_arg (stmt, 0);
15223 arg1 = gimple_call_arg (stmt, 1);
15224 lhs = gimple_call_lhs (stmt);
15225 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15226 gimple_set_location (g, gimple_location (stmt));
15227 gsi_replace (gsi, g, true);
15229 /* Flavors of vec_andc. */
15230 case ALTIVEC_BUILTIN_VANDC:
15231 arg0 = gimple_call_arg (stmt, 0);
15232 arg1 = gimple_call_arg (stmt, 1);
15233 lhs = gimple_call_lhs (stmt);
15234 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15235 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15236 gimple_set_location (g, gimple_location (stmt));
15237 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15238 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15239 gimple_set_location (g, gimple_location (stmt));
15240 gsi_replace (gsi, g, true);
15242 /* Flavors of vec_nand. */
15243 case P8V_BUILTIN_VEC_NAND:
15244 case P8V_BUILTIN_NAND_V16QI:
15245 case P8V_BUILTIN_NAND_V8HI:
15246 case P8V_BUILTIN_NAND_V4SI:
15247 case P8V_BUILTIN_NAND_V4SF:
15248 case P8V_BUILTIN_NAND_V2DF:
15249 case P8V_BUILTIN_NAND_V2DI:
15250 arg0 = gimple_call_arg (stmt, 0);
15251 arg1 = gimple_call_arg (stmt, 1);
15252 lhs = gimple_call_lhs (stmt);
15253 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15254 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15255 gimple_set_location (g, gimple_location (stmt));
15256 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15257 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15258 gimple_set_location (g, gimple_location (stmt));
15259 gsi_replace (gsi, g, true);
15261 /* Flavors of vec_or. */
15262 case ALTIVEC_BUILTIN_VOR:
15263 arg0 = gimple_call_arg (stmt, 0);
15264 arg1 = gimple_call_arg (stmt, 1);
15265 lhs = gimple_call_lhs (stmt);
15266 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15267 gimple_set_location (g, gimple_location (stmt));
15268 gsi_replace (gsi, g, true);
15270 /* flavors of vec_orc. */
15271 case P8V_BUILTIN_ORC_V16QI:
15272 case P8V_BUILTIN_ORC_V8HI:
15273 case P8V_BUILTIN_ORC_V4SI:
15274 case P8V_BUILTIN_ORC_V4SF:
15275 case P8V_BUILTIN_ORC_V2DF:
15276 case P8V_BUILTIN_ORC_V2DI:
15277 arg0 = gimple_call_arg (stmt, 0);
15278 arg1 = gimple_call_arg (stmt, 1);
15279 lhs = gimple_call_lhs (stmt);
15280 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15281 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15282 gimple_set_location (g, gimple_location (stmt));
15283 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15284 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15285 gimple_set_location (g, gimple_location (stmt));
15286 gsi_replace (gsi, g, true);
15288 /* Flavors of vec_xor. */
15289 case ALTIVEC_BUILTIN_VXOR:
15290 arg0 = gimple_call_arg (stmt, 0);
15291 arg1 = gimple_call_arg (stmt, 1);
15292 lhs = gimple_call_lhs (stmt);
15293 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15294 gimple_set_location (g, gimple_location (stmt));
15295 gsi_replace (gsi, g, true);
15297 /* Flavors of vec_nor. */
15298 case ALTIVEC_BUILTIN_VNOR:
15299 arg0 = gimple_call_arg (stmt, 0);
15300 arg1 = gimple_call_arg (stmt, 1);
15301 lhs = gimple_call_lhs (stmt);
15302 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15303 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15304 gimple_set_location (g, gimple_location (stmt));
15305 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15306 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15307 gimple_set_location (g, gimple_location (stmt));
15308 gsi_replace (gsi, g, true);
15310 /* flavors of vec_abs. */
15311 case ALTIVEC_BUILTIN_ABS_V16QI:
15312 case ALTIVEC_BUILTIN_ABS_V8HI:
15313 case ALTIVEC_BUILTIN_ABS_V4SI:
15314 case ALTIVEC_BUILTIN_ABS_V4SF:
15315 case P8V_BUILTIN_ABS_V2DI:
15316 case VSX_BUILTIN_XVABSDP:
15317 arg0 = gimple_call_arg (stmt, 0);
15318 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15319 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15321 lhs = gimple_call_lhs (stmt);
15322 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15323 gimple_set_location (g, gimple_location (stmt));
15324 gsi_replace (gsi, g, true);
15326 /* flavors of vec_min. */
15327 case VSX_BUILTIN_XVMINDP:
15328 case P8V_BUILTIN_VMINSD:
15329 case P8V_BUILTIN_VMINUD:
15330 case ALTIVEC_BUILTIN_VMINSB:
15331 case ALTIVEC_BUILTIN_VMINSH:
15332 case ALTIVEC_BUILTIN_VMINSW:
15333 case ALTIVEC_BUILTIN_VMINUB:
15334 case ALTIVEC_BUILTIN_VMINUH:
15335 case ALTIVEC_BUILTIN_VMINUW:
15336 case ALTIVEC_BUILTIN_VMINFP:
15337 arg0 = gimple_call_arg (stmt, 0);
15338 arg1 = gimple_call_arg (stmt, 1);
15339 lhs = gimple_call_lhs (stmt);
15340 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15341 gimple_set_location (g, gimple_location (stmt));
15342 gsi_replace (gsi, g, true);
15344 /* flavors of vec_max. */
15345 case VSX_BUILTIN_XVMAXDP:
15346 case P8V_BUILTIN_VMAXSD:
15347 case P8V_BUILTIN_VMAXUD:
15348 case ALTIVEC_BUILTIN_VMAXSB:
15349 case ALTIVEC_BUILTIN_VMAXSH:
15350 case ALTIVEC_BUILTIN_VMAXSW:
15351 case ALTIVEC_BUILTIN_VMAXUB:
15352 case ALTIVEC_BUILTIN_VMAXUH:
15353 case ALTIVEC_BUILTIN_VMAXUW:
15354 case ALTIVEC_BUILTIN_VMAXFP:
15355 arg0 = gimple_call_arg (stmt, 0);
15356 arg1 = gimple_call_arg (stmt, 1);
15357 lhs = gimple_call_lhs (stmt);
15358 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15359 gimple_set_location (g, gimple_location (stmt));
15360 gsi_replace (gsi, g, true);
15362 /* Flavors of vec_eqv. */
15363 case P8V_BUILTIN_EQV_V16QI:
15364 case P8V_BUILTIN_EQV_V8HI:
15365 case P8V_BUILTIN_EQV_V4SI:
15366 case P8V_BUILTIN_EQV_V4SF:
15367 case P8V_BUILTIN_EQV_V2DF:
15368 case P8V_BUILTIN_EQV_V2DI:
15369 arg0 = gimple_call_arg (stmt, 0);
15370 arg1 = gimple_call_arg (stmt, 1);
15371 lhs = gimple_call_lhs (stmt);
15372 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15373 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15374 gimple_set_location (g, gimple_location (stmt));
15375 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15376 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15377 gimple_set_location (g, gimple_location (stmt));
15378 gsi_replace (gsi, g, true);
15380 /* Flavors of vec_rotate_left. */
15381 case ALTIVEC_BUILTIN_VRLB:
15382 case ALTIVEC_BUILTIN_VRLH:
15383 case ALTIVEC_BUILTIN_VRLW:
15384 case P8V_BUILTIN_VRLD:
15385 arg0 = gimple_call_arg (stmt, 0);
15386 arg1 = gimple_call_arg (stmt, 1);
15387 lhs = gimple_call_lhs (stmt);
15388 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15389 gimple_set_location (g, gimple_location (stmt));
15390 gsi_replace (gsi, g, true);
15392 /* Flavors of vector shift right algebraic.
15393 vec_sra{b,h,w} -> vsra{b,h,w}. */
15394 case ALTIVEC_BUILTIN_VSRAB:
15395 case ALTIVEC_BUILTIN_VSRAH:
15396 case ALTIVEC_BUILTIN_VSRAW:
15397 case P8V_BUILTIN_VSRAD:
15399 arg0 = gimple_call_arg (stmt, 0);
15400 arg1 = gimple_call_arg (stmt, 1);
15401 lhs = gimple_call_lhs (stmt);
15402 tree arg1_type = TREE_TYPE (arg1);
15403 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15404 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15405 location_t loc = gimple_location (stmt);
15406 /* Force arg1 into the range valid matching the arg0 type. */
15407 /* Build a vector consisting of the max valid bit-size values. */
15408 int n_elts = VECTOR_CST_NELTS (arg1);
15409 tree element_size = build_int_cst (unsigned_element_type,
15411 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15412 for (int i = 0; i < n_elts; i++)
15413 elts.safe_push (element_size);
15414 tree modulo_tree = elts.build ();
15415 /* Modulo the provided shift value against that vector. */
15416 gimple_seq stmts = NULL;
15417 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15418 unsigned_arg1_type, arg1);
15419 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15420 unsigned_arg1_type, unsigned_arg1,
15422 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15423 /* And finally, do the shift. */
15424 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
15425 gimple_set_location (g, loc);
15426 gsi_replace (gsi, g, true);
15429 /* Flavors of vector shift left.
15430 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15431 case ALTIVEC_BUILTIN_VSLB:
15432 case ALTIVEC_BUILTIN_VSLH:
15433 case ALTIVEC_BUILTIN_VSLW:
15434 case P8V_BUILTIN_VSLD:
15437 gimple_seq stmts = NULL;
15438 arg0 = gimple_call_arg (stmt, 0);
15439 tree arg0_type = TREE_TYPE (arg0);
15440 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
15441 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
15443 arg1 = gimple_call_arg (stmt, 1);
15444 tree arg1_type = TREE_TYPE (arg1);
15445 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15446 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15447 loc = gimple_location (stmt);
15448 lhs = gimple_call_lhs (stmt);
15449 /* Force arg1 into the range valid matching the arg0 type. */
15450 /* Build a vector consisting of the max valid bit-size values. */
15451 int n_elts = VECTOR_CST_NELTS (arg1);
15452 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
15454 tree element_size = build_int_cst (unsigned_element_type,
15455 tree_size_in_bits / n_elts);
15456 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
15457 for (int i = 0; i < n_elts; i++)
15458 elts.safe_push (element_size);
15459 tree modulo_tree = elts.build ();
15460 /* Modulo the provided shift value against that vector. */
15461 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15462 unsigned_arg1_type, arg1);
15463 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15464 unsigned_arg1_type, unsigned_arg1,
15466 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15467 /* And finally, do the shift. */
15468 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
15469 gimple_set_location (g, gimple_location (stmt));
15470 gsi_replace (gsi, g, true);
15473 /* Flavors of vector shift right. */
15474 case ALTIVEC_BUILTIN_VSRB:
15475 case ALTIVEC_BUILTIN_VSRH:
15476 case ALTIVEC_BUILTIN_VSRW:
15477 case P8V_BUILTIN_VSRD:
15479 arg0 = gimple_call_arg (stmt, 0);
15480 arg1 = gimple_call_arg (stmt, 1);
15481 lhs = gimple_call_lhs (stmt);
15482 tree arg1_type = TREE_TYPE (arg1);
15483 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15484 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15485 location_t loc = gimple_location (stmt);
15486 gimple_seq stmts = NULL;
15487 /* Convert arg0 to unsigned. */
15489 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15490 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15491 /* Force arg1 into the range valid matching the arg0 type. */
15492 /* Build a vector consisting of the max valid bit-size values. */
15493 int n_elts = VECTOR_CST_NELTS (arg1);
15494 tree element_size = build_int_cst (unsigned_element_type,
15496 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15497 for (int i = 0; i < n_elts; i++)
15498 elts.safe_push (element_size);
15499 tree modulo_tree = elts.build ();
15500 /* Modulo the provided shift value against that vector. */
15501 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15502 unsigned_arg1_type, arg1);
15503 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15504 unsigned_arg1_type, unsigned_arg1,
15506 /* Do the shift. */
15508 = gimple_build (&stmts, RSHIFT_EXPR,
15509 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
15510 /* Convert result back to the lhs type. */
15511 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15512 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15513 update_call_from_tree (gsi, res);
15516 /* Vector loads. */
15517 case ALTIVEC_BUILTIN_LVX_V16QI:
15518 case ALTIVEC_BUILTIN_LVX_V8HI:
15519 case ALTIVEC_BUILTIN_LVX_V4SI:
15520 case ALTIVEC_BUILTIN_LVX_V4SF:
15521 case ALTIVEC_BUILTIN_LVX_V2DI:
15522 case ALTIVEC_BUILTIN_LVX_V2DF:
15523 case ALTIVEC_BUILTIN_LVX_V1TI:
15525 arg0 = gimple_call_arg (stmt, 0); // offset
15526 arg1 = gimple_call_arg (stmt, 1); // address
15527 lhs = gimple_call_lhs (stmt);
15528 location_t loc = gimple_location (stmt);
15529 /* Since arg1 may be cast to a different type, just use ptr_type_node
15530 here instead of trying to enforce TBAA on pointer types. */
15531 tree arg1_type = ptr_type_node;
15532 tree lhs_type = TREE_TYPE (lhs);
15533 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15534 the tree using the value from arg0. The resulting type will match
15535 the type of arg1. */
15536 gimple_seq stmts = NULL;
15537 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15538 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15539 arg1_type, arg1, temp_offset);
15540 /* Mask off any lower bits from the address. */
15541 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15542 arg1_type, temp_addr,
15543 build_int_cst (arg1_type, -16));
15544 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15545 if (!is_gimple_mem_ref_addr (aligned_addr))
15547 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15548 gimple *g = gimple_build_assign (t, aligned_addr);
15549 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15552 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15553 take an offset, but since we've already incorporated the offset
15554 above, here we just pass in a zero. */
15556 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15557 build_int_cst (arg1_type, 0)));
15558 gimple_set_location (g, loc);
15559 gsi_replace (gsi, g, true);
15562 /* Vector stores. */
15563 case ALTIVEC_BUILTIN_STVX_V16QI:
15564 case ALTIVEC_BUILTIN_STVX_V8HI:
15565 case ALTIVEC_BUILTIN_STVX_V4SI:
15566 case ALTIVEC_BUILTIN_STVX_V4SF:
15567 case ALTIVEC_BUILTIN_STVX_V2DI:
15568 case ALTIVEC_BUILTIN_STVX_V2DF:
15570 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15571 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15572 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15573 location_t loc = gimple_location (stmt);
15574 tree arg0_type = TREE_TYPE (arg0);
15575 /* Use ptr_type_node (no TBAA) for the arg2_type.
15576 FIXME: (Richard) "A proper fix would be to transition this type as
15577 seen from the frontend to GIMPLE, for example in a similar way we
15578 do for MEM_REFs by piggy-backing that on an extra argument, a
15579 constant zero pointer of the alias pointer type to use (which would
15580 also serve as a type indicator of the store itself). I'd use a
15581 target specific internal function for this (not sure if we can have
15582 those target specific, but I guess if it's folded away then that's
15583 fine) and get away with the overload set." */
15584 tree arg2_type = ptr_type_node;
15585 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15586 the tree using the value from arg0. The resulting type will match
15587 the type of arg2. */
15588 gimple_seq stmts = NULL;
15589 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15590 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15591 arg2_type, arg2, temp_offset);
15592 /* Mask off any lower bits from the address. */
15593 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15594 arg2_type, temp_addr,
15595 build_int_cst (arg2_type, -16));
15596 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15597 if (!is_gimple_mem_ref_addr (aligned_addr))
15599 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15600 gimple *g = gimple_build_assign (t, aligned_addr);
15601 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15604 /* The desired gimple result should be similar to:
15605 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15607 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15608 build_int_cst (arg2_type, 0)), arg0);
15609 gimple_set_location (g, loc);
15610 gsi_replace (gsi, g, true);
15614 /* unaligned Vector loads. */
15615 case VSX_BUILTIN_LXVW4X_V16QI:
15616 case VSX_BUILTIN_LXVW4X_V8HI:
15617 case VSX_BUILTIN_LXVW4X_V4SF:
15618 case VSX_BUILTIN_LXVW4X_V4SI:
15619 case VSX_BUILTIN_LXVD2X_V2DF:
15620 case VSX_BUILTIN_LXVD2X_V2DI:
15622 arg0 = gimple_call_arg (stmt, 0); // offset
15623 arg1 = gimple_call_arg (stmt, 1); // address
15624 lhs = gimple_call_lhs (stmt);
15625 location_t loc = gimple_location (stmt);
15626 /* Since arg1 may be cast to a different type, just use ptr_type_node
15627 here instead of trying to enforce TBAA on pointer types. */
15628 tree arg1_type = ptr_type_node;
15629 tree lhs_type = TREE_TYPE (lhs);
15630 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15631 required alignment (power) is 4 bytes regardless of data type. */
15632 tree align_ltype = build_aligned_type (lhs_type, 4);
15633 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15634 the tree using the value from arg0. The resulting type will match
15635 the type of arg1. */
15636 gimple_seq stmts = NULL;
15637 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15638 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15639 arg1_type, arg1, temp_offset);
15640 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15641 if (!is_gimple_mem_ref_addr (temp_addr))
15643 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15644 gimple *g = gimple_build_assign (t, temp_addr);
15645 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15648 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15649 take an offset, but since we've already incorporated the offset
15650 above, here we just pass in a zero. */
15652 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
15653 build_int_cst (arg1_type, 0)));
15654 gimple_set_location (g, loc);
15655 gsi_replace (gsi, g, true);
15659 /* unaligned Vector stores. */
15660 case VSX_BUILTIN_STXVW4X_V16QI:
15661 case VSX_BUILTIN_STXVW4X_V8HI:
15662 case VSX_BUILTIN_STXVW4X_V4SF:
15663 case VSX_BUILTIN_STXVW4X_V4SI:
15664 case VSX_BUILTIN_STXVD2X_V2DF:
15665 case VSX_BUILTIN_STXVD2X_V2DI:
15667 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15668 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15669 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15670 location_t loc = gimple_location (stmt);
15671 tree arg0_type = TREE_TYPE (arg0);
15672 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15673 tree arg2_type = ptr_type_node;
15674 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15675 required alignment (power) is 4 bytes regardless of data type. */
15676 tree align_stype = build_aligned_type (arg0_type, 4);
15677 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15678 the tree using the value from arg1. */
15679 gimple_seq stmts = NULL;
15680 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15681 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15682 arg2_type, arg2, temp_offset);
15683 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15684 if (!is_gimple_mem_ref_addr (temp_addr))
15686 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15687 gimple *g = gimple_build_assign (t, temp_addr);
15688 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15692 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
15693 build_int_cst (arg2_type, 0)), arg0);
15694 gimple_set_location (g, loc);
15695 gsi_replace (gsi, g, true);
15699 /* Vector Fused multiply-add (fma). */
15700 case ALTIVEC_BUILTIN_VMADDFP:
15701 case VSX_BUILTIN_XVMADDDP:
15702 case ALTIVEC_BUILTIN_VMLADDUHM:
15704 arg0 = gimple_call_arg (stmt, 0);
15705 arg1 = gimple_call_arg (stmt, 1);
15706 tree arg2 = gimple_call_arg (stmt, 2);
15707 lhs = gimple_call_lhs (stmt);
15708 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15709 gimple_call_set_lhs (g, lhs);
15710 gimple_call_set_nothrow (g, true);
15711 gimple_set_location (g, gimple_location (stmt));
15712 gsi_replace (gsi, g, true);
15716 /* Vector compares; EQ, NE, GE, GT, LE. */
15717 case ALTIVEC_BUILTIN_VCMPEQUB:
15718 case ALTIVEC_BUILTIN_VCMPEQUH:
15719 case ALTIVEC_BUILTIN_VCMPEQUW:
15720 case P8V_BUILTIN_VCMPEQUD:
15721 fold_compare_helper (gsi, EQ_EXPR, stmt);
15724 case P9V_BUILTIN_CMPNEB:
15725 case P9V_BUILTIN_CMPNEH:
15726 case P9V_BUILTIN_CMPNEW:
15727 fold_compare_helper (gsi, NE_EXPR, stmt);
15730 case VSX_BUILTIN_CMPGE_16QI:
15731 case VSX_BUILTIN_CMPGE_U16QI:
15732 case VSX_BUILTIN_CMPGE_8HI:
15733 case VSX_BUILTIN_CMPGE_U8HI:
15734 case VSX_BUILTIN_CMPGE_4SI:
15735 case VSX_BUILTIN_CMPGE_U4SI:
15736 case VSX_BUILTIN_CMPGE_2DI:
15737 case VSX_BUILTIN_CMPGE_U2DI:
15738 fold_compare_helper (gsi, GE_EXPR, stmt);
15741 case ALTIVEC_BUILTIN_VCMPGTSB:
15742 case ALTIVEC_BUILTIN_VCMPGTUB:
15743 case ALTIVEC_BUILTIN_VCMPGTSH:
15744 case ALTIVEC_BUILTIN_VCMPGTUH:
15745 case ALTIVEC_BUILTIN_VCMPGTSW:
15746 case ALTIVEC_BUILTIN_VCMPGTUW:
15747 case P8V_BUILTIN_VCMPGTUD:
15748 case P8V_BUILTIN_VCMPGTSD:
15749 fold_compare_helper (gsi, GT_EXPR, stmt);
15752 case VSX_BUILTIN_CMPLE_16QI:
15753 case VSX_BUILTIN_CMPLE_U16QI:
15754 case VSX_BUILTIN_CMPLE_8HI:
15755 case VSX_BUILTIN_CMPLE_U8HI:
15756 case VSX_BUILTIN_CMPLE_4SI:
15757 case VSX_BUILTIN_CMPLE_U4SI:
15758 case VSX_BUILTIN_CMPLE_2DI:
15759 case VSX_BUILTIN_CMPLE_U2DI:
15760 fold_compare_helper (gsi, LE_EXPR, stmt);
15763 /* flavors of vec_splat_[us]{8,16,32}. */
15764 case ALTIVEC_BUILTIN_VSPLTISB:
15765 case ALTIVEC_BUILTIN_VSPLTISH:
15766 case ALTIVEC_BUILTIN_VSPLTISW:
15768 arg0 = gimple_call_arg (stmt, 0);
15769 lhs = gimple_call_lhs (stmt);
15771 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15772 5-bit signed constant in range -16 to +15. */
15773 if (TREE_CODE (arg0) != INTEGER_CST
15774 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
15776 gimple_seq stmts = NULL;
15777 location_t loc = gimple_location (stmt);
15778 tree splat_value = gimple_convert (&stmts, loc,
15779 TREE_TYPE (TREE_TYPE (lhs)), arg0);
15780 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15781 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
15782 g = gimple_build_assign (lhs, splat_tree);
15783 gimple_set_location (g, gimple_location (stmt));
15784 gsi_replace (gsi, g, true);
15788 /* Flavors of vec_splat. */
15789 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
15790 case ALTIVEC_BUILTIN_VSPLTB:
15791 case ALTIVEC_BUILTIN_VSPLTH:
15792 case ALTIVEC_BUILTIN_VSPLTW:
15793 case VSX_BUILTIN_XXSPLTD_V2DI:
15794 case VSX_BUILTIN_XXSPLTD_V2DF:
15796 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
15797 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
15798 /* Only fold the vec_splat_*() if arg1 is both a constant value and
15799 is a valid index into the arg0 vector. */
15800 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
15801 if (TREE_CODE (arg1) != INTEGER_CST
15802 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
15804 lhs = gimple_call_lhs (stmt);
15805 tree lhs_type = TREE_TYPE (lhs);
15806 tree arg0_type = TREE_TYPE (arg0);
15808 if (TREE_CODE (arg0) == VECTOR_CST)
15809 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
15812 /* Determine (in bits) the length and start location of the
15813 splat value for a call to the tree_vec_extract helper. */
15814 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
15815 * BITS_PER_UNIT / n_elts;
15816 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
15817 tree len = build_int_cst (bitsizetype, splat_elem_size);
15818 tree start = build_int_cst (bitsizetype, splat_start_bit);
15819 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
15822 /* And finally, build the new vector. */
15823 tree splat_tree = build_vector_from_val (lhs_type, splat);
15824 g = gimple_build_assign (lhs, splat_tree);
15825 gimple_set_location (g, gimple_location (stmt));
15826 gsi_replace (gsi, g, true);
15830 /* vec_mergel (integrals). */
15831 case ALTIVEC_BUILTIN_VMRGLH:
15832 case ALTIVEC_BUILTIN_VMRGLW:
15833 case VSX_BUILTIN_XXMRGLW_4SI:
15834 case ALTIVEC_BUILTIN_VMRGLB:
15835 case VSX_BUILTIN_VEC_MERGEL_V2DI:
15836 case VSX_BUILTIN_XXMRGLW_4SF:
15837 case VSX_BUILTIN_VEC_MERGEL_V2DF:
15838 fold_mergehl_helper (gsi, stmt, 1);
15840 /* vec_mergeh (integrals). */
15841 case ALTIVEC_BUILTIN_VMRGHH:
15842 case ALTIVEC_BUILTIN_VMRGHW:
15843 case VSX_BUILTIN_XXMRGHW_4SI:
15844 case ALTIVEC_BUILTIN_VMRGHB:
15845 case VSX_BUILTIN_VEC_MERGEH_V2DI:
15846 case VSX_BUILTIN_XXMRGHW_4SF:
15847 case VSX_BUILTIN_VEC_MERGEH_V2DF:
15848 fold_mergehl_helper (gsi, stmt, 0);
15851 /* Flavors of vec_mergee. */
15852 case P8V_BUILTIN_VMRGEW_V4SI:
15853 case P8V_BUILTIN_VMRGEW_V2DI:
15854 case P8V_BUILTIN_VMRGEW_V4SF:
15855 case P8V_BUILTIN_VMRGEW_V2DF:
15856 fold_mergeeo_helper (gsi, stmt, 0);
15858 /* Flavors of vec_mergeo. */
15859 case P8V_BUILTIN_VMRGOW_V4SI:
15860 case P8V_BUILTIN_VMRGOW_V2DI:
15861 case P8V_BUILTIN_VMRGOW_V4SF:
15862 case P8V_BUILTIN_VMRGOW_V2DF:
15863 fold_mergeeo_helper (gsi, stmt, 1);
15866 /* d = vec_pack (a, b) */
15867 case P8V_BUILTIN_VPKUDUM:
15868 case ALTIVEC_BUILTIN_VPKUHUM:
15869 case ALTIVEC_BUILTIN_VPKUWUM:
15871 arg0 = gimple_call_arg (stmt, 0);
15872 arg1 = gimple_call_arg (stmt, 1);
15873 lhs = gimple_call_lhs (stmt);
15874 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
15875 gimple_set_location (g, gimple_location (stmt));
15876 gsi_replace (gsi, g, true);
15880 /* d = vec_unpackh (a) */
15881 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
15882 in this code is sensitive to endian-ness, and needs to be inverted to
15883 handle both LE and BE targets. */
15884 case ALTIVEC_BUILTIN_VUPKHSB:
15885 case ALTIVEC_BUILTIN_VUPKHSH:
15886 case P8V_BUILTIN_VUPKHSW:
15888 arg0 = gimple_call_arg (stmt, 0);
15889 lhs = gimple_call_lhs (stmt);
15890 if (BYTES_BIG_ENDIAN)
15891 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15893 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15894 gimple_set_location (g, gimple_location (stmt));
15895 gsi_replace (gsi, g, true);
15898 /* d = vec_unpackl (a) */
15899 case ALTIVEC_BUILTIN_VUPKLSB:
15900 case ALTIVEC_BUILTIN_VUPKLSH:
15901 case P8V_BUILTIN_VUPKLSW:
15903 arg0 = gimple_call_arg (stmt, 0);
15904 lhs = gimple_call_lhs (stmt);
15905 if (BYTES_BIG_ENDIAN)
15906 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15908 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15909 gimple_set_location (g, gimple_location (stmt));
15910 gsi_replace (gsi, g, true);
15913 /* There is no gimple type corresponding with pixel, so just return. */
15914 case ALTIVEC_BUILTIN_VUPKHPX:
15915 case ALTIVEC_BUILTIN_VUPKLPX:
15919 case ALTIVEC_BUILTIN_VPERM_16QI:
15920 case ALTIVEC_BUILTIN_VPERM_8HI:
15921 case ALTIVEC_BUILTIN_VPERM_4SI:
15922 case ALTIVEC_BUILTIN_VPERM_2DI:
15923 case ALTIVEC_BUILTIN_VPERM_4SF:
15924 case ALTIVEC_BUILTIN_VPERM_2DF:
15926 arg0 = gimple_call_arg (stmt, 0);
15927 arg1 = gimple_call_arg (stmt, 1);
15928 tree permute = gimple_call_arg (stmt, 2);
15929 lhs = gimple_call_lhs (stmt);
15930 location_t loc = gimple_location (stmt);
15931 gimple_seq stmts = NULL;
15932 // convert arg0 and arg1 to match the type of the permute
15933 // for the VEC_PERM_EXPR operation.
15934 tree permute_type = (TREE_TYPE (permute));
15935 tree arg0_ptype = gimple_convert (&stmts, loc, permute_type, arg0);
15936 tree arg1_ptype = gimple_convert (&stmts, loc, permute_type, arg1);
15937 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
15938 permute_type, arg0_ptype, arg1_ptype,
15940 // Convert the result back to the desired lhs type upon completion.
15941 tree temp = gimple_convert (&stmts, loc, TREE_TYPE (lhs), lhs_ptype);
15942 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15943 g = gimple_build_assign (lhs, temp);
15944 gimple_set_location (g, loc);
15945 gsi_replace (gsi, g, true);
15950 if (TARGET_DEBUG_BUILTIN)
15951 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
15952 fn_code, fn_name1, fn_name2);
15959 /* Expand an expression EXP that calls a built-in function,
15960 with result going to TARGET if that's convenient
15961 (and in mode MODE if that's convenient).
15962 SUBTARGET may be used as the target for computing one of EXP's operands.
15963 IGNORE is nonzero if the value is to be ignored. */
15966 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15967 machine_mode mode ATTRIBUTE_UNUSED,
15968 int ignore ATTRIBUTE_UNUSED)
15970 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15971 enum rs6000_builtins fcode
15972 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
15973 size_t uns_fcode = (size_t)fcode;
15974 const struct builtin_description *d;
15978 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
15979 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
15980 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
15982 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
15983 floating point type, depending on whether long double is the IBM extended
15984 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
15985 we only define one variant of the built-in function, and switch the code
15986 when defining it, rather than defining two built-ins and using the
15987 overload table in rs6000-c.c to switch between the two. If we don't have
15988 the proper assembler, don't do this switch because CODE_FOR_*kf* and
15989 CODE_FOR_*tf* will be CODE_FOR_nothing. */
15990 if (FLOAT128_IEEE_P (TFmode))
15996 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
15997 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
15998 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
15999 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16000 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16001 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16002 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16003 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16004 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16005 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16006 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16007 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16008 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16011 if (TARGET_DEBUG_BUILTIN)
16013 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16014 const char *name2 = (icode != CODE_FOR_nothing)
16015 ? get_insn_name ((int) icode)
16019 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16021 default: name3 = "unknown"; break;
16022 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16023 case RS6000_BTC_UNARY: name3 = "unary"; break;
16024 case RS6000_BTC_BINARY: name3 = "binary"; break;
16025 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16026 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16027 case RS6000_BTC_ABS: name3 = "abs"; break;
16028 case RS6000_BTC_DST: name3 = "dst"; break;
16033 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16034 (name1) ? name1 : "---", fcode,
16035 (name2) ? name2 : "---", (int) icode,
16037 func_valid_p ? "" : ", not valid");
16042 rs6000_invalid_builtin (fcode);
16044 /* Given it is invalid, just generate a normal call. */
16045 return expand_call (exp, target, ignore);
16050 case RS6000_BUILTIN_RECIP:
16051 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16053 case RS6000_BUILTIN_RECIPF:
16054 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16056 case RS6000_BUILTIN_RSQRTF:
16057 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16059 case RS6000_BUILTIN_RSQRT:
16060 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16062 case POWER7_BUILTIN_BPERMD:
16063 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16064 ? CODE_FOR_bpermd_di
16065 : CODE_FOR_bpermd_si), exp, target);
16067 case RS6000_BUILTIN_GET_TB:
16068 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16071 case RS6000_BUILTIN_MFTB:
16072 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16073 ? CODE_FOR_rs6000_mftb_di
16074 : CODE_FOR_rs6000_mftb_si),
16077 case RS6000_BUILTIN_MFFS:
16078 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16080 case RS6000_BUILTIN_MTFSB0:
16081 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
16083 case RS6000_BUILTIN_MTFSB1:
16084 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
16086 case RS6000_BUILTIN_SET_FPSCR_RN:
16087 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
16090 case RS6000_BUILTIN_SET_FPSCR_DRN:
16092 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
16095 case RS6000_BUILTIN_MFFSL:
16096 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
16098 case RS6000_BUILTIN_MTFSF:
16099 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16101 case RS6000_BUILTIN_CPU_INIT:
16102 case RS6000_BUILTIN_CPU_IS:
16103 case RS6000_BUILTIN_CPU_SUPPORTS:
16104 return cpu_expand_builtin (fcode, exp, target);
16106 case MISC_BUILTIN_SPEC_BARRIER:
16108 emit_insn (gen_speculation_barrier ());
16112 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16113 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16115 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16116 : (int) CODE_FOR_altivec_lvsl_direct);
16117 machine_mode tmode = insn_data[icode2].operand[0].mode;
16118 machine_mode mode = insn_data[icode2].operand[1].mode;
16122 gcc_assert (TARGET_ALTIVEC);
16124 arg = CALL_EXPR_ARG (exp, 0);
16125 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16126 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16127 addr = memory_address (mode, op);
16128 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16132 /* For the load case need to negate the address. */
16133 op = gen_reg_rtx (GET_MODE (addr));
16134 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16136 op = gen_rtx_MEM (mode, op);
16139 || GET_MODE (target) != tmode
16140 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16141 target = gen_reg_rtx (tmode);
16143 pat = GEN_FCN (icode2) (target, op);
16151 case ALTIVEC_BUILTIN_VCFUX:
16152 case ALTIVEC_BUILTIN_VCFSX:
16153 case ALTIVEC_BUILTIN_VCTUXS:
16154 case ALTIVEC_BUILTIN_VCTSXS:
16155 /* FIXME: There's got to be a nicer way to handle this case than
16156 constructing a new CALL_EXPR. */
16157 if (call_expr_nargs (exp) == 1)
16159 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16160 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16164 /* For the pack and unpack int128 routines, fix up the builtin so it
16165 uses the correct IBM128 type. */
16166 case MISC_BUILTIN_PACK_IF:
16167 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16169 icode = CODE_FOR_packtf;
16170 fcode = MISC_BUILTIN_PACK_TF;
16171 uns_fcode = (size_t)fcode;
16175 case MISC_BUILTIN_UNPACK_IF:
16176 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16178 icode = CODE_FOR_unpacktf;
16179 fcode = MISC_BUILTIN_UNPACK_TF;
16180 uns_fcode = (size_t)fcode;
16188 if (TARGET_ALTIVEC)
16190 ret = altivec_expand_builtin (exp, target, &success);
16197 ret = htm_expand_builtin (exp, target, &success);
16203 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16204 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16205 gcc_assert (attr == RS6000_BTC_UNARY
16206 || attr == RS6000_BTC_BINARY
16207 || attr == RS6000_BTC_TERNARY
16208 || attr == RS6000_BTC_SPECIAL);
16210 /* Handle simple unary operations. */
16212 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16213 if (d->code == fcode)
16214 return rs6000_expand_unop_builtin (icode, exp, target);
16216 /* Handle simple binary operations. */
16218 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16219 if (d->code == fcode)
16220 return rs6000_expand_binop_builtin (icode, exp, target);
16222 /* Handle simple ternary operations. */
16224 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16225 if (d->code == fcode)
16226 return rs6000_expand_ternop_builtin (icode, exp, target);
16228 /* Handle simple no-argument operations. */
16230 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16231 if (d->code == fcode)
16232 return rs6000_expand_zeroop_builtin (icode, target);
16234 gcc_unreachable ();
16237 /* Create a builtin vector type with a name. Taking care not to give
16238 the canonical type a name. */
16241 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16243 tree result = build_vector_type (elt_type, num_elts);
16245 /* Copy so we don't give the canonical type a name. */
16246 result = build_variant_type_copy (result);
16248 add_builtin_type (name, result);
16254 rs6000_init_builtins (void)
16260 if (TARGET_DEBUG_BUILTIN)
16261 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16262 (TARGET_ALTIVEC) ? ", altivec" : "",
16263 (TARGET_VSX) ? ", vsx" : "");
16265 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16266 : "__vector long long",
16267 intDI_type_node, 2);
16268 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16269 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16270 intSI_type_node, 4);
16271 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16272 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16273 intHI_type_node, 8);
16274 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16275 intQI_type_node, 16);
16277 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16278 unsigned_intQI_type_node, 16);
16279 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16280 unsigned_intHI_type_node, 8);
16281 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16282 unsigned_intSI_type_node, 4);
16283 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16284 ? "__vector unsigned long"
16285 : "__vector unsigned long long",
16286 unsigned_intDI_type_node, 2);
16288 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16290 const_str_type_node
16291 = build_pointer_type (build_qualified_type (char_type_node,
16294 /* We use V1TI mode as a special container to hold __int128_t items that
16295 must live in VSX registers. */
16296 if (intTI_type_node)
16298 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16299 intTI_type_node, 1);
16300 unsigned_V1TI_type_node
16301 = rs6000_vector_type ("__vector unsigned __int128",
16302 unsigned_intTI_type_node, 1);
16305 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16306 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16307 'vector unsigned short'. */
16309 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16310 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16311 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16312 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16313 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16315 long_integer_type_internal_node = long_integer_type_node;
16316 long_unsigned_type_internal_node = long_unsigned_type_node;
16317 long_long_integer_type_internal_node = long_long_integer_type_node;
16318 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16319 intQI_type_internal_node = intQI_type_node;
16320 uintQI_type_internal_node = unsigned_intQI_type_node;
16321 intHI_type_internal_node = intHI_type_node;
16322 uintHI_type_internal_node = unsigned_intHI_type_node;
16323 intSI_type_internal_node = intSI_type_node;
16324 uintSI_type_internal_node = unsigned_intSI_type_node;
16325 intDI_type_internal_node = intDI_type_node;
16326 uintDI_type_internal_node = unsigned_intDI_type_node;
16327 intTI_type_internal_node = intTI_type_node;
16328 uintTI_type_internal_node = unsigned_intTI_type_node;
16329 float_type_internal_node = float_type_node;
16330 double_type_internal_node = double_type_node;
16331 long_double_type_internal_node = long_double_type_node;
16332 dfloat64_type_internal_node = dfloat64_type_node;
16333 dfloat128_type_internal_node = dfloat128_type_node;
16334 void_type_internal_node = void_type_node;
16336 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16337 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16338 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16339 format that uses a pair of doubles, depending on the switches and
16342 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16343 floating point, we need make sure the type is non-zero or else self-test
16344 fails during bootstrap.
16346 Always create __ibm128 as a separate type, even if the current long double
16347 format is IBM extended double.
16349 For IEEE 128-bit floating point, always create the type __ieee128. If the
16350 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16352 if (TARGET_FLOAT128_TYPE)
16354 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16355 ibm128_float_type_node = long_double_type_node;
16358 ibm128_float_type_node = make_node (REAL_TYPE);
16359 TYPE_PRECISION (ibm128_float_type_node) = 128;
16360 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16361 layout_type (ibm128_float_type_node);
16364 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16367 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16368 ieee128_float_type_node = long_double_type_node;
16370 ieee128_float_type_node = float128_type_node;
16372 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16377 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16379 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16381 builtin_mode_to_type[QImode][0] = integer_type_node;
16382 builtin_mode_to_type[HImode][0] = integer_type_node;
16383 builtin_mode_to_type[SImode][0] = intSI_type_node;
16384 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16385 builtin_mode_to_type[DImode][0] = intDI_type_node;
16386 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16387 builtin_mode_to_type[TImode][0] = intTI_type_node;
16388 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16389 builtin_mode_to_type[SFmode][0] = float_type_node;
16390 builtin_mode_to_type[DFmode][0] = double_type_node;
16391 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16392 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16393 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16394 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16395 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16396 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16397 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16398 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16399 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16400 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16401 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16402 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16403 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16404 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16405 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16406 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16407 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16409 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16410 TYPE_NAME (bool_char_type_node) = tdecl;
16412 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16413 TYPE_NAME (bool_short_type_node) = tdecl;
16415 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16416 TYPE_NAME (bool_int_type_node) = tdecl;
16418 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16419 TYPE_NAME (pixel_type_node) = tdecl;
16421 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16422 bool_char_type_node, 16);
16423 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16424 bool_short_type_node, 8);
16425 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16426 bool_int_type_node, 4);
16427 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16428 ? "__vector __bool long"
16429 : "__vector __bool long long",
16430 bool_long_long_type_node, 2);
16431 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16432 pixel_type_node, 8);
16434 /* Create Altivec and VSX builtins on machines with at least the
16435 general purpose extensions (970 and newer) to allow the use of
16436 the target attribute. */
16437 if (TARGET_EXTRA_BUILTINS)
16438 altivec_init_builtins ();
16440 htm_init_builtins ();
16442 if (TARGET_EXTRA_BUILTINS)
16443 rs6000_common_init_builtins ();
16445 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16446 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16447 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16449 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16450 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16451 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16453 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16454 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16455 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16457 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16458 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16459 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16461 mode = (TARGET_64BIT) ? DImode : SImode;
16462 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16463 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16464 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16466 ftype = build_function_type_list (unsigned_intDI_type_node,
16468 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16471 ftype = build_function_type_list (unsigned_intDI_type_node,
16474 ftype = build_function_type_list (unsigned_intSI_type_node,
16476 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16478 ftype = build_function_type_list (double_type_node, NULL_TREE);
16479 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16481 ftype = build_function_type_list (double_type_node, NULL_TREE);
16482 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
16484 ftype = build_function_type_list (void_type_node,
16487 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
16489 ftype = build_function_type_list (void_type_node,
16492 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
16494 ftype = build_function_type_list (void_type_node,
16497 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
16499 ftype = build_function_type_list (void_type_node,
16502 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
16504 ftype = build_function_type_list (void_type_node,
16505 intSI_type_node, double_type_node,
16507 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16509 ftype = build_function_type_list (void_type_node, NULL_TREE);
16510 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16511 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16512 MISC_BUILTIN_SPEC_BARRIER);
16514 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16516 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16517 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16519 /* AIX libm provides clog as __clog. */
16520 if (TARGET_XCOFF &&
16521 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16522 set_user_assembler_name (tdecl, "__clog");
16524 #ifdef SUBTARGET_INIT_BUILTINS
16525 SUBTARGET_INIT_BUILTINS;
16529 /* Returns the rs6000 builtin decl for CODE. */
16532 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16534 HOST_WIDE_INT fnmask;
16536 if (code >= RS6000_BUILTIN_COUNT)
16537 return error_mark_node;
16539 fnmask = rs6000_builtin_info[code].mask;
16540 if ((fnmask & rs6000_builtin_mask) != fnmask)
16542 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16543 return error_mark_node;
16546 return rs6000_builtin_decls[code];
16550 altivec_init_builtins (void)
16552 const struct builtin_description *d;
16556 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16558 tree pvoid_type_node = build_pointer_type (void_type_node);
16560 tree pcvoid_type_node
16561 = build_pointer_type (build_qualified_type (void_type_node,
16564 tree int_ftype_opaque
16565 = build_function_type_list (integer_type_node,
16566 opaque_V4SI_type_node, NULL_TREE);
16567 tree opaque_ftype_opaque
16568 = build_function_type_list (integer_type_node, NULL_TREE);
16569 tree opaque_ftype_opaque_int
16570 = build_function_type_list (opaque_V4SI_type_node,
16571 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16572 tree opaque_ftype_opaque_opaque_int
16573 = build_function_type_list (opaque_V4SI_type_node,
16574 opaque_V4SI_type_node, opaque_V4SI_type_node,
16575 integer_type_node, NULL_TREE);
16576 tree opaque_ftype_opaque_opaque_opaque
16577 = build_function_type_list (opaque_V4SI_type_node,
16578 opaque_V4SI_type_node, opaque_V4SI_type_node,
16579 opaque_V4SI_type_node, NULL_TREE);
16580 tree opaque_ftype_opaque_opaque
16581 = build_function_type_list (opaque_V4SI_type_node,
16582 opaque_V4SI_type_node, opaque_V4SI_type_node,
16584 tree int_ftype_int_opaque_opaque
16585 = build_function_type_list (integer_type_node,
16586 integer_type_node, opaque_V4SI_type_node,
16587 opaque_V4SI_type_node, NULL_TREE);
16588 tree int_ftype_int_v4si_v4si
16589 = build_function_type_list (integer_type_node,
16590 integer_type_node, V4SI_type_node,
16591 V4SI_type_node, NULL_TREE);
16592 tree int_ftype_int_v2di_v2di
16593 = build_function_type_list (integer_type_node,
16594 integer_type_node, V2DI_type_node,
16595 V2DI_type_node, NULL_TREE);
16596 tree void_ftype_v4si
16597 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16598 tree v8hi_ftype_void
16599 = build_function_type_list (V8HI_type_node, NULL_TREE);
16600 tree void_ftype_void
16601 = build_function_type_list (void_type_node, NULL_TREE);
16602 tree void_ftype_int
16603 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16605 tree opaque_ftype_long_pcvoid
16606 = build_function_type_list (opaque_V4SI_type_node,
16607 long_integer_type_node, pcvoid_type_node,
16609 tree v16qi_ftype_long_pcvoid
16610 = build_function_type_list (V16QI_type_node,
16611 long_integer_type_node, pcvoid_type_node,
16613 tree v8hi_ftype_long_pcvoid
16614 = build_function_type_list (V8HI_type_node,
16615 long_integer_type_node, pcvoid_type_node,
16617 tree v4si_ftype_long_pcvoid
16618 = build_function_type_list (V4SI_type_node,
16619 long_integer_type_node, pcvoid_type_node,
16621 tree v4sf_ftype_long_pcvoid
16622 = build_function_type_list (V4SF_type_node,
16623 long_integer_type_node, pcvoid_type_node,
16625 tree v2df_ftype_long_pcvoid
16626 = build_function_type_list (V2DF_type_node,
16627 long_integer_type_node, pcvoid_type_node,
16629 tree v2di_ftype_long_pcvoid
16630 = build_function_type_list (V2DI_type_node,
16631 long_integer_type_node, pcvoid_type_node,
16633 tree v1ti_ftype_long_pcvoid
16634 = build_function_type_list (V1TI_type_node,
16635 long_integer_type_node, pcvoid_type_node,
16638 tree void_ftype_opaque_long_pvoid
16639 = build_function_type_list (void_type_node,
16640 opaque_V4SI_type_node, long_integer_type_node,
16641 pvoid_type_node, NULL_TREE);
16642 tree void_ftype_v4si_long_pvoid
16643 = build_function_type_list (void_type_node,
16644 V4SI_type_node, long_integer_type_node,
16645 pvoid_type_node, NULL_TREE);
16646 tree void_ftype_v16qi_long_pvoid
16647 = build_function_type_list (void_type_node,
16648 V16QI_type_node, long_integer_type_node,
16649 pvoid_type_node, NULL_TREE);
16651 tree void_ftype_v16qi_pvoid_long
16652 = build_function_type_list (void_type_node,
16653 V16QI_type_node, pvoid_type_node,
16654 long_integer_type_node, NULL_TREE);
16656 tree void_ftype_v8hi_long_pvoid
16657 = build_function_type_list (void_type_node,
16658 V8HI_type_node, long_integer_type_node,
16659 pvoid_type_node, NULL_TREE);
16660 tree void_ftype_v4sf_long_pvoid
16661 = build_function_type_list (void_type_node,
16662 V4SF_type_node, long_integer_type_node,
16663 pvoid_type_node, NULL_TREE);
16664 tree void_ftype_v2df_long_pvoid
16665 = build_function_type_list (void_type_node,
16666 V2DF_type_node, long_integer_type_node,
16667 pvoid_type_node, NULL_TREE);
16668 tree void_ftype_v1ti_long_pvoid
16669 = build_function_type_list (void_type_node,
16670 V1TI_type_node, long_integer_type_node,
16671 pvoid_type_node, NULL_TREE);
16672 tree void_ftype_v2di_long_pvoid
16673 = build_function_type_list (void_type_node,
16674 V2DI_type_node, long_integer_type_node,
16675 pvoid_type_node, NULL_TREE);
16676 tree int_ftype_int_v8hi_v8hi
16677 = build_function_type_list (integer_type_node,
16678 integer_type_node, V8HI_type_node,
16679 V8HI_type_node, NULL_TREE);
16680 tree int_ftype_int_v16qi_v16qi
16681 = build_function_type_list (integer_type_node,
16682 integer_type_node, V16QI_type_node,
16683 V16QI_type_node, NULL_TREE);
16684 tree int_ftype_int_v4sf_v4sf
16685 = build_function_type_list (integer_type_node,
16686 integer_type_node, V4SF_type_node,
16687 V4SF_type_node, NULL_TREE);
16688 tree int_ftype_int_v2df_v2df
16689 = build_function_type_list (integer_type_node,
16690 integer_type_node, V2DF_type_node,
16691 V2DF_type_node, NULL_TREE);
16692 tree v2di_ftype_v2di
16693 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16694 tree v4si_ftype_v4si
16695 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16696 tree v8hi_ftype_v8hi
16697 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16698 tree v16qi_ftype_v16qi
16699 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16700 tree v4sf_ftype_v4sf
16701 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16702 tree v2df_ftype_v2df
16703 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16704 tree void_ftype_pcvoid_int_int
16705 = build_function_type_list (void_type_node,
16706 pcvoid_type_node, integer_type_node,
16707 integer_type_node, NULL_TREE);
16709 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16710 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16711 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16712 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16713 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16714 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16715 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16716 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16717 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16718 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16719 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16720 ALTIVEC_BUILTIN_LVXL_V2DF);
16721 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16722 ALTIVEC_BUILTIN_LVXL_V2DI);
16723 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16724 ALTIVEC_BUILTIN_LVXL_V4SF);
16725 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16726 ALTIVEC_BUILTIN_LVXL_V4SI);
16727 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16728 ALTIVEC_BUILTIN_LVXL_V8HI);
16729 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16730 ALTIVEC_BUILTIN_LVXL_V16QI);
16731 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16732 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16733 ALTIVEC_BUILTIN_LVX_V1TI);
16734 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16735 ALTIVEC_BUILTIN_LVX_V2DF);
16736 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16737 ALTIVEC_BUILTIN_LVX_V2DI);
16738 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16739 ALTIVEC_BUILTIN_LVX_V4SF);
16740 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16741 ALTIVEC_BUILTIN_LVX_V4SI);
16742 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16743 ALTIVEC_BUILTIN_LVX_V8HI);
16744 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16745 ALTIVEC_BUILTIN_LVX_V16QI);
16746 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16747 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16748 ALTIVEC_BUILTIN_STVX_V2DF);
16749 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16750 ALTIVEC_BUILTIN_STVX_V2DI);
16751 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16752 ALTIVEC_BUILTIN_STVX_V4SF);
16753 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16754 ALTIVEC_BUILTIN_STVX_V4SI);
16755 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16756 ALTIVEC_BUILTIN_STVX_V8HI);
16757 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16758 ALTIVEC_BUILTIN_STVX_V16QI);
16759 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16760 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16761 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16762 ALTIVEC_BUILTIN_STVXL_V2DF);
16763 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16764 ALTIVEC_BUILTIN_STVXL_V2DI);
16765 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16766 ALTIVEC_BUILTIN_STVXL_V4SF);
16767 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16768 ALTIVEC_BUILTIN_STVXL_V4SI);
16769 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16770 ALTIVEC_BUILTIN_STVXL_V8HI);
16771 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16772 ALTIVEC_BUILTIN_STVXL_V16QI);
16773 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16774 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16775 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16776 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16777 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16778 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16779 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16780 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16781 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16782 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16783 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16784 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16785 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16786 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16787 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16788 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16790 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16791 VSX_BUILTIN_LXVD2X_V2DF);
16792 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16793 VSX_BUILTIN_LXVD2X_V2DI);
16794 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16795 VSX_BUILTIN_LXVW4X_V4SF);
16796 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16797 VSX_BUILTIN_LXVW4X_V4SI);
16798 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16799 VSX_BUILTIN_LXVW4X_V8HI);
16800 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16801 VSX_BUILTIN_LXVW4X_V16QI);
16802 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16803 VSX_BUILTIN_STXVD2X_V2DF);
16804 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16805 VSX_BUILTIN_STXVD2X_V2DI);
16806 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16807 VSX_BUILTIN_STXVW4X_V4SF);
16808 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16809 VSX_BUILTIN_STXVW4X_V4SI);
16810 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16811 VSX_BUILTIN_STXVW4X_V8HI);
16812 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16813 VSX_BUILTIN_STXVW4X_V16QI);
16815 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16816 VSX_BUILTIN_LD_ELEMREV_V2DF);
16817 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16818 VSX_BUILTIN_LD_ELEMREV_V2DI);
16819 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16820 VSX_BUILTIN_LD_ELEMREV_V4SF);
16821 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16822 VSX_BUILTIN_LD_ELEMREV_V4SI);
16823 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16824 VSX_BUILTIN_LD_ELEMREV_V8HI);
16825 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16826 VSX_BUILTIN_LD_ELEMREV_V16QI);
16827 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16828 VSX_BUILTIN_ST_ELEMREV_V2DF);
16829 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16830 VSX_BUILTIN_ST_ELEMREV_V1TI);
16831 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16832 VSX_BUILTIN_ST_ELEMREV_V2DI);
16833 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
16834 VSX_BUILTIN_ST_ELEMREV_V4SF);
16835 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
16836 VSX_BUILTIN_ST_ELEMREV_V4SI);
16837 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
16838 VSX_BUILTIN_ST_ELEMREV_V8HI);
16839 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
16840 VSX_BUILTIN_ST_ELEMREV_V16QI);
16842 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
16843 VSX_BUILTIN_VEC_LD);
16844 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
16845 VSX_BUILTIN_VEC_ST);
16846 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
16847 VSX_BUILTIN_VEC_XL);
16848 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
16849 VSX_BUILTIN_VEC_XL_BE);
16850 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
16851 VSX_BUILTIN_VEC_XST);
16852 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
16853 VSX_BUILTIN_VEC_XST_BE);
16855 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
16856 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
16857 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
16859 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
16860 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
16861 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
16862 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
16863 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
16864 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
16865 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
16866 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
16867 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
16868 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
16869 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
16870 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
16872 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
16873 ALTIVEC_BUILTIN_VEC_ADDE);
16874 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
16875 ALTIVEC_BUILTIN_VEC_ADDEC);
16876 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
16877 ALTIVEC_BUILTIN_VEC_CMPNE);
16878 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
16879 ALTIVEC_BUILTIN_VEC_MUL);
16880 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
16881 ALTIVEC_BUILTIN_VEC_SUBE);
16882 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
16883 ALTIVEC_BUILTIN_VEC_SUBEC);
16885 /* Cell builtins. */
16886 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
16887 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
16888 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
16889 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
16891 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
16892 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
16893 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
16894 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
16896 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
16897 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
16898 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
16899 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
16901 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
16902 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
16903 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
16904 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
16906 if (TARGET_P9_VECTOR)
16908 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
16909 P9V_BUILTIN_STXVL);
16910 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
16911 P9V_BUILTIN_XST_LEN_R);
16914 /* Add the DST variants. */
16916 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
16918 HOST_WIDE_INT mask = d->mask;
16920 /* It is expected that these dst built-in functions may have
16921 d->icode equal to CODE_FOR_nothing. */
16922 if ((mask & builtin_mask) != mask)
16924 if (TARGET_DEBUG_BUILTIN)
16925 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
16929 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
16932 /* Initialize the predicates. */
16933 d = bdesc_altivec_preds;
16934 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
16936 machine_mode mode1;
16938 HOST_WIDE_INT mask = d->mask;
16940 if ((mask & builtin_mask) != mask)
16942 if (TARGET_DEBUG_BUILTIN)
16943 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
16948 if (rs6000_overloaded_builtin_p (d->code))
16952 /* Cannot define builtin if the instruction is disabled. */
16953 gcc_assert (d->icode != CODE_FOR_nothing);
16954 mode1 = insn_data[d->icode].operand[1].mode;
16960 type = int_ftype_int_opaque_opaque;
16963 type = int_ftype_int_v2di_v2di;
16966 type = int_ftype_int_v4si_v4si;
16969 type = int_ftype_int_v8hi_v8hi;
16972 type = int_ftype_int_v16qi_v16qi;
16975 type = int_ftype_int_v4sf_v4sf;
16978 type = int_ftype_int_v2df_v2df;
16981 gcc_unreachable ();
16984 def_builtin (d->name, type, d->code);
16987 /* Initialize the abs* operators. */
16989 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
16991 machine_mode mode0;
16993 HOST_WIDE_INT mask = d->mask;
16995 if ((mask & builtin_mask) != mask)
16997 if (TARGET_DEBUG_BUILTIN)
16998 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17003 /* Cannot define builtin if the instruction is disabled. */
17004 gcc_assert (d->icode != CODE_FOR_nothing);
17005 mode0 = insn_data[d->icode].operand[0].mode;
17010 type = v2di_ftype_v2di;
17013 type = v4si_ftype_v4si;
17016 type = v8hi_ftype_v8hi;
17019 type = v16qi_ftype_v16qi;
17022 type = v4sf_ftype_v4sf;
17025 type = v2df_ftype_v2df;
17028 gcc_unreachable ();
17031 def_builtin (d->name, type, d->code);
17034 /* Initialize target builtin that implements
17035 targetm.vectorize.builtin_mask_for_load. */
17037 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17038 v16qi_ftype_long_pcvoid,
17039 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17040 BUILT_IN_MD, NULL, NULL_TREE);
17041 TREE_READONLY (decl) = 1;
17042 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17043 altivec_builtin_mask_for_load = decl;
17045 /* Access to the vec_init patterns. */
17046 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17047 integer_type_node, integer_type_node,
17048 integer_type_node, NULL_TREE);
17049 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17051 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17052 short_integer_type_node,
17053 short_integer_type_node,
17054 short_integer_type_node,
17055 short_integer_type_node,
17056 short_integer_type_node,
17057 short_integer_type_node,
17058 short_integer_type_node, NULL_TREE);
17059 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17061 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17062 char_type_node, char_type_node,
17063 char_type_node, char_type_node,
17064 char_type_node, char_type_node,
17065 char_type_node, char_type_node,
17066 char_type_node, char_type_node,
17067 char_type_node, char_type_node,
17068 char_type_node, char_type_node,
17069 char_type_node, NULL_TREE);
17070 def_builtin ("__builtin_vec_init_v16qi", ftype,
17071 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17073 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17074 float_type_node, float_type_node,
17075 float_type_node, NULL_TREE);
17076 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17078 /* VSX builtins. */
17079 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17080 double_type_node, NULL_TREE);
17081 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17083 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17084 intDI_type_node, NULL_TREE);
17085 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17087 /* Access to the vec_set patterns. */
17088 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17090 integer_type_node, NULL_TREE);
17091 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17093 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17095 integer_type_node, NULL_TREE);
17096 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17098 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17100 integer_type_node, NULL_TREE);
17101 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17103 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17105 integer_type_node, NULL_TREE);
17106 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17108 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17110 integer_type_node, NULL_TREE);
17111 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17113 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17115 integer_type_node, NULL_TREE);
17116 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17118 /* Access to the vec_extract patterns. */
17119 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17120 integer_type_node, NULL_TREE);
17121 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17123 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17124 integer_type_node, NULL_TREE);
17125 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17127 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17128 integer_type_node, NULL_TREE);
17129 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17131 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17132 integer_type_node, NULL_TREE);
17133 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17135 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17136 integer_type_node, NULL_TREE);
17137 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17139 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17140 integer_type_node, NULL_TREE);
17141 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17144 if (V1TI_type_node)
17146 tree v1ti_ftype_long_pcvoid
17147 = build_function_type_list (V1TI_type_node,
17148 long_integer_type_node, pcvoid_type_node,
17150 tree void_ftype_v1ti_long_pvoid
17151 = build_function_type_list (void_type_node,
17152 V1TI_type_node, long_integer_type_node,
17153 pvoid_type_node, NULL_TREE);
17154 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17155 VSX_BUILTIN_LD_ELEMREV_V1TI);
17156 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17157 VSX_BUILTIN_LXVD2X_V1TI);
17158 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17159 VSX_BUILTIN_STXVD2X_V1TI);
17160 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17161 NULL_TREE, NULL_TREE);
17162 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17163 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17165 integer_type_node, NULL_TREE);
17166 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17167 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17168 integer_type_node, NULL_TREE);
17169 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17175 htm_init_builtins (void)
17177 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17178 const struct builtin_description *d;
17182 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17184 tree op[MAX_HTM_OPERANDS], type;
17185 HOST_WIDE_INT mask = d->mask;
17186 unsigned attr = rs6000_builtin_info[d->code].attr;
17187 bool void_func = (attr & RS6000_BTC_VOID);
17188 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17190 tree gpr_type_node;
17194 /* It is expected that these htm built-in functions may have
17195 d->icode equal to CODE_FOR_nothing. */
17197 if (TARGET_32BIT && TARGET_POWERPC64)
17198 gpr_type_node = long_long_unsigned_type_node;
17200 gpr_type_node = long_unsigned_type_node;
17202 if (attr & RS6000_BTC_SPR)
17204 rettype = gpr_type_node;
17205 argtype = gpr_type_node;
17207 else if (d->code == HTM_BUILTIN_TABORTDC
17208 || d->code == HTM_BUILTIN_TABORTDCI)
17210 rettype = unsigned_type_node;
17211 argtype = gpr_type_node;
17215 rettype = unsigned_type_node;
17216 argtype = unsigned_type_node;
17219 if ((mask & builtin_mask) != mask)
17221 if (TARGET_DEBUG_BUILTIN)
17222 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17228 if (TARGET_DEBUG_BUILTIN)
17229 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17230 (long unsigned) i);
17234 op[nopnds++] = (void_func) ? void_type_node : rettype;
17236 if (attr_args == RS6000_BTC_UNARY)
17237 op[nopnds++] = argtype;
17238 else if (attr_args == RS6000_BTC_BINARY)
17240 op[nopnds++] = argtype;
17241 op[nopnds++] = argtype;
17243 else if (attr_args == RS6000_BTC_TERNARY)
17245 op[nopnds++] = argtype;
17246 op[nopnds++] = argtype;
17247 op[nopnds++] = argtype;
17253 type = build_function_type_list (op[0], NULL_TREE);
17256 type = build_function_type_list (op[0], op[1], NULL_TREE);
17259 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17262 type = build_function_type_list (op[0], op[1], op[2], op[3],
17266 gcc_unreachable ();
17269 def_builtin (d->name, type, d->code);
17273 /* Hash function for builtin functions with up to 3 arguments and a return
17276 builtin_hasher::hash (builtin_hash_struct *bh)
17281 for (i = 0; i < 4; i++)
17283 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17284 ret = (ret * 2) + bh->uns_p[i];
17290 /* Compare builtin hash entries H1 and H2 for equivalence. */
17292 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17294 return ((p1->mode[0] == p2->mode[0])
17295 && (p1->mode[1] == p2->mode[1])
17296 && (p1->mode[2] == p2->mode[2])
17297 && (p1->mode[3] == p2->mode[3])
17298 && (p1->uns_p[0] == p2->uns_p[0])
17299 && (p1->uns_p[1] == p2->uns_p[1])
17300 && (p1->uns_p[2] == p2->uns_p[2])
17301 && (p1->uns_p[3] == p2->uns_p[3]));
17304 /* Map types for builtin functions with an explicit return type and up to 3
17305 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17306 of the argument. */
17308 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17309 machine_mode mode_arg1, machine_mode mode_arg2,
17310 enum rs6000_builtins builtin, const char *name)
17312 struct builtin_hash_struct h;
17313 struct builtin_hash_struct *h2;
17316 tree ret_type = NULL_TREE;
17317 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17319 /* Create builtin_hash_table. */
17320 if (builtin_hash_table == NULL)
17321 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17323 h.type = NULL_TREE;
17324 h.mode[0] = mode_ret;
17325 h.mode[1] = mode_arg0;
17326 h.mode[2] = mode_arg1;
17327 h.mode[3] = mode_arg2;
17333 /* If the builtin is a type that produces unsigned results or takes unsigned
17334 arguments, and it is returned as a decl for the vectorizer (such as
17335 widening multiplies, permute), make sure the arguments and return value
17336 are type correct. */
17339 /* unsigned 1 argument functions. */
17340 case CRYPTO_BUILTIN_VSBOX:
17341 case CRYPTO_BUILTIN_VSBOX_BE:
17342 case P8V_BUILTIN_VGBBD:
17343 case MISC_BUILTIN_CDTBCD:
17344 case MISC_BUILTIN_CBCDTD:
17349 /* unsigned 2 argument functions. */
17350 case ALTIVEC_BUILTIN_VMULEUB:
17351 case ALTIVEC_BUILTIN_VMULEUH:
17352 case P8V_BUILTIN_VMULEUW:
17353 case ALTIVEC_BUILTIN_VMULOUB:
17354 case ALTIVEC_BUILTIN_VMULOUH:
17355 case P8V_BUILTIN_VMULOUW:
17356 case CRYPTO_BUILTIN_VCIPHER:
17357 case CRYPTO_BUILTIN_VCIPHER_BE:
17358 case CRYPTO_BUILTIN_VCIPHERLAST:
17359 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
17360 case CRYPTO_BUILTIN_VNCIPHER:
17361 case CRYPTO_BUILTIN_VNCIPHER_BE:
17362 case CRYPTO_BUILTIN_VNCIPHERLAST:
17363 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
17364 case CRYPTO_BUILTIN_VPMSUMB:
17365 case CRYPTO_BUILTIN_VPMSUMH:
17366 case CRYPTO_BUILTIN_VPMSUMW:
17367 case CRYPTO_BUILTIN_VPMSUMD:
17368 case CRYPTO_BUILTIN_VPMSUM:
17369 case MISC_BUILTIN_ADDG6S:
17370 case MISC_BUILTIN_DIVWEU:
17371 case MISC_BUILTIN_DIVDEU:
17372 case VSX_BUILTIN_UDIV_V2DI:
17373 case ALTIVEC_BUILTIN_VMAXUB:
17374 case ALTIVEC_BUILTIN_VMINUB:
17375 case ALTIVEC_BUILTIN_VMAXUH:
17376 case ALTIVEC_BUILTIN_VMINUH:
17377 case ALTIVEC_BUILTIN_VMAXUW:
17378 case ALTIVEC_BUILTIN_VMINUW:
17379 case P8V_BUILTIN_VMAXUD:
17380 case P8V_BUILTIN_VMINUD:
17386 /* unsigned 3 argument functions. */
17387 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17388 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17389 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17390 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17391 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17392 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17393 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17394 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17395 case VSX_BUILTIN_VPERM_16QI_UNS:
17396 case VSX_BUILTIN_VPERM_8HI_UNS:
17397 case VSX_BUILTIN_VPERM_4SI_UNS:
17398 case VSX_BUILTIN_VPERM_2DI_UNS:
17399 case VSX_BUILTIN_XXSEL_16QI_UNS:
17400 case VSX_BUILTIN_XXSEL_8HI_UNS:
17401 case VSX_BUILTIN_XXSEL_4SI_UNS:
17402 case VSX_BUILTIN_XXSEL_2DI_UNS:
17403 case CRYPTO_BUILTIN_VPERMXOR:
17404 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17405 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17406 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17407 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17408 case CRYPTO_BUILTIN_VSHASIGMAW:
17409 case CRYPTO_BUILTIN_VSHASIGMAD:
17410 case CRYPTO_BUILTIN_VSHASIGMA:
17417 /* signed permute functions with unsigned char mask. */
17418 case ALTIVEC_BUILTIN_VPERM_16QI:
17419 case ALTIVEC_BUILTIN_VPERM_8HI:
17420 case ALTIVEC_BUILTIN_VPERM_4SI:
17421 case ALTIVEC_BUILTIN_VPERM_4SF:
17422 case ALTIVEC_BUILTIN_VPERM_2DI:
17423 case ALTIVEC_BUILTIN_VPERM_2DF:
17424 case VSX_BUILTIN_VPERM_16QI:
17425 case VSX_BUILTIN_VPERM_8HI:
17426 case VSX_BUILTIN_VPERM_4SI:
17427 case VSX_BUILTIN_VPERM_4SF:
17428 case VSX_BUILTIN_VPERM_2DI:
17429 case VSX_BUILTIN_VPERM_2DF:
17433 /* unsigned args, signed return. */
17434 case VSX_BUILTIN_XVCVUXDSP:
17435 case VSX_BUILTIN_XVCVUXDDP_UNS:
17436 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17440 /* signed args, unsigned return. */
17441 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17442 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17443 case MISC_BUILTIN_UNPACK_TD:
17444 case MISC_BUILTIN_UNPACK_V1TI:
17448 /* unsigned arguments, bool return (compares). */
17449 case ALTIVEC_BUILTIN_VCMPEQUB:
17450 case ALTIVEC_BUILTIN_VCMPEQUH:
17451 case ALTIVEC_BUILTIN_VCMPEQUW:
17452 case P8V_BUILTIN_VCMPEQUD:
17453 case VSX_BUILTIN_CMPGE_U16QI:
17454 case VSX_BUILTIN_CMPGE_U8HI:
17455 case VSX_BUILTIN_CMPGE_U4SI:
17456 case VSX_BUILTIN_CMPGE_U2DI:
17457 case ALTIVEC_BUILTIN_VCMPGTUB:
17458 case ALTIVEC_BUILTIN_VCMPGTUH:
17459 case ALTIVEC_BUILTIN_VCMPGTUW:
17460 case P8V_BUILTIN_VCMPGTUD:
17465 /* unsigned arguments for 128-bit pack instructions. */
17466 case MISC_BUILTIN_PACK_TD:
17467 case MISC_BUILTIN_PACK_V1TI:
17472 /* unsigned second arguments (vector shift right). */
17473 case ALTIVEC_BUILTIN_VSRB:
17474 case ALTIVEC_BUILTIN_VSRH:
17475 case ALTIVEC_BUILTIN_VSRW:
17476 case P8V_BUILTIN_VSRD:
17484 /* Figure out how many args are present. */
17485 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17488 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17489 if (!ret_type && h.uns_p[0])
17490 ret_type = builtin_mode_to_type[h.mode[0]][0];
17493 fatal_error (input_location,
17494 "internal error: builtin function %qs had an unexpected "
17495 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17497 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17498 arg_type[i] = NULL_TREE;
17500 for (i = 0; i < num_args; i++)
17502 int m = (int) h.mode[i+1];
17503 int uns_p = h.uns_p[i+1];
17505 arg_type[i] = builtin_mode_to_type[m][uns_p];
17506 if (!arg_type[i] && uns_p)
17507 arg_type[i] = builtin_mode_to_type[m][0];
17510 fatal_error (input_location,
17511 "internal error: builtin function %qs, argument %d "
17512 "had unexpected argument type %qs", name, i,
17513 GET_MODE_NAME (m));
17516 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17517 if (*found == NULL)
17519 h2 = ggc_alloc<builtin_hash_struct> ();
17523 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17524 arg_type[2], NULL_TREE);
17527 return (*found)->type;
17531 rs6000_common_init_builtins (void)
17533 const struct builtin_description *d;
17536 tree opaque_ftype_opaque = NULL_TREE;
17537 tree opaque_ftype_opaque_opaque = NULL_TREE;
17538 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17539 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17541 /* Create Altivec and VSX builtins on machines with at least the
17542 general purpose extensions (970 and newer) to allow the use of
17543 the target attribute. */
17545 if (TARGET_EXTRA_BUILTINS)
17546 builtin_mask |= RS6000_BTM_COMMON;
17548 /* Add the ternary operators. */
17550 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17553 HOST_WIDE_INT mask = d->mask;
17555 if ((mask & builtin_mask) != mask)
17557 if (TARGET_DEBUG_BUILTIN)
17558 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17562 if (rs6000_overloaded_builtin_p (d->code))
17564 if (! (type = opaque_ftype_opaque_opaque_opaque))
17565 type = opaque_ftype_opaque_opaque_opaque
17566 = build_function_type_list (opaque_V4SI_type_node,
17567 opaque_V4SI_type_node,
17568 opaque_V4SI_type_node,
17569 opaque_V4SI_type_node,
17574 enum insn_code icode = d->icode;
17577 if (TARGET_DEBUG_BUILTIN)
17578 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17584 if (icode == CODE_FOR_nothing)
17586 if (TARGET_DEBUG_BUILTIN)
17587 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17593 type = builtin_function_type (insn_data[icode].operand[0].mode,
17594 insn_data[icode].operand[1].mode,
17595 insn_data[icode].operand[2].mode,
17596 insn_data[icode].operand[3].mode,
17600 def_builtin (d->name, type, d->code);
17603 /* Add the binary operators. */
17605 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17607 machine_mode mode0, mode1, mode2;
17609 HOST_WIDE_INT mask = d->mask;
17611 if ((mask & builtin_mask) != mask)
17613 if (TARGET_DEBUG_BUILTIN)
17614 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17618 if (rs6000_overloaded_builtin_p (d->code))
17620 if (! (type = opaque_ftype_opaque_opaque))
17621 type = opaque_ftype_opaque_opaque
17622 = build_function_type_list (opaque_V4SI_type_node,
17623 opaque_V4SI_type_node,
17624 opaque_V4SI_type_node,
17629 enum insn_code icode = d->icode;
17632 if (TARGET_DEBUG_BUILTIN)
17633 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17639 if (icode == CODE_FOR_nothing)
17641 if (TARGET_DEBUG_BUILTIN)
17642 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17648 mode0 = insn_data[icode].operand[0].mode;
17649 mode1 = insn_data[icode].operand[1].mode;
17650 mode2 = insn_data[icode].operand[2].mode;
17652 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17656 def_builtin (d->name, type, d->code);
17659 /* Add the simple unary operators. */
17661 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17663 machine_mode mode0, mode1;
17665 HOST_WIDE_INT mask = d->mask;
17667 if ((mask & builtin_mask) != mask)
17669 if (TARGET_DEBUG_BUILTIN)
17670 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17674 if (rs6000_overloaded_builtin_p (d->code))
17676 if (! (type = opaque_ftype_opaque))
17677 type = opaque_ftype_opaque
17678 = build_function_type_list (opaque_V4SI_type_node,
17679 opaque_V4SI_type_node,
17684 enum insn_code icode = d->icode;
17687 if (TARGET_DEBUG_BUILTIN)
17688 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17694 if (icode == CODE_FOR_nothing)
17696 if (TARGET_DEBUG_BUILTIN)
17697 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17703 mode0 = insn_data[icode].operand[0].mode;
17704 mode1 = insn_data[icode].operand[1].mode;
17706 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17710 def_builtin (d->name, type, d->code);
17713 /* Add the simple no-argument operators. */
17715 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17717 machine_mode mode0;
17719 HOST_WIDE_INT mask = d->mask;
17721 if ((mask & builtin_mask) != mask)
17723 if (TARGET_DEBUG_BUILTIN)
17724 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17727 if (rs6000_overloaded_builtin_p (d->code))
17729 if (!opaque_ftype_opaque)
17730 opaque_ftype_opaque
17731 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17732 type = opaque_ftype_opaque;
17736 enum insn_code icode = d->icode;
17739 if (TARGET_DEBUG_BUILTIN)
17740 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17741 (long unsigned) i);
17744 if (icode == CODE_FOR_nothing)
17746 if (TARGET_DEBUG_BUILTIN)
17748 "rs6000_builtin, skip no-argument %s (no code)\n",
17752 mode0 = insn_data[icode].operand[0].mode;
17753 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17756 def_builtin (d->name, type, d->code);
17760 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17762 init_float128_ibm (machine_mode mode)
17764 if (!TARGET_XL_COMPAT)
17766 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17767 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17768 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17769 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17771 if (!TARGET_HARD_FLOAT)
17773 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17774 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17775 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17776 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17777 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17778 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17779 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17780 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17782 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17783 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17784 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17785 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17786 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17787 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17788 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17789 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17794 set_optab_libfunc (add_optab, mode, "_xlqadd");
17795 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17796 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17797 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17800 /* Add various conversions for IFmode to use the traditional TFmode
17802 if (mode == IFmode)
17804 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf");
17805 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf");
17806 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdtf");
17807 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd");
17808 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd");
17809 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtftd");
17811 if (TARGET_POWERPC64)
17813 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17814 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17815 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17816 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17821 /* Create a decl for either complex long double multiply or complex long double
17822 divide when long double is IEEE 128-bit floating point. We can't use
17823 __multc3 and __divtc3 because the original long double using IBM extended
17824 double used those names. The complex multiply/divide functions are encoded
17825 as builtin functions with a complex result and 4 scalar inputs. */
17828 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17830 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17833 set_builtin_decl (fncode, fndecl, true);
17835 if (TARGET_DEBUG_BUILTIN)
17836 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
17841 /* Set up IEEE 128-bit floating point routines. Use different names if the
17842 arguments can be passed in a vector register. The historical PowerPC
17843 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
17844 continue to use that if we aren't using vector registers to pass IEEE
17845 128-bit floating point. */
17848 init_float128_ieee (machine_mode mode)
17850 if (FLOAT128_VECTOR_P (mode))
17852 static bool complex_muldiv_init_p = false;
17854 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
17855 we have clone or target attributes, this will be called a second
17856 time. We want to create the built-in function only once. */
17857 if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
17859 complex_muldiv_init_p = true;
17860 built_in_function fncode_mul =
17861 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
17862 - MIN_MODE_COMPLEX_FLOAT);
17863 built_in_function fncode_div =
17864 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
17865 - MIN_MODE_COMPLEX_FLOAT);
17867 tree fntype = build_function_type_list (complex_long_double_type_node,
17868 long_double_type_node,
17869 long_double_type_node,
17870 long_double_type_node,
17871 long_double_type_node,
17874 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
17875 create_complex_muldiv ("__divkc3", fncode_div, fntype);
17878 set_optab_libfunc (add_optab, mode, "__addkf3");
17879 set_optab_libfunc (sub_optab, mode, "__subkf3");
17880 set_optab_libfunc (neg_optab, mode, "__negkf2");
17881 set_optab_libfunc (smul_optab, mode, "__mulkf3");
17882 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
17883 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
17884 set_optab_libfunc (abs_optab, mode, "__abskf2");
17885 set_optab_libfunc (powi_optab, mode, "__powikf2");
17887 set_optab_libfunc (eq_optab, mode, "__eqkf2");
17888 set_optab_libfunc (ne_optab, mode, "__nekf2");
17889 set_optab_libfunc (gt_optab, mode, "__gtkf2");
17890 set_optab_libfunc (ge_optab, mode, "__gekf2");
17891 set_optab_libfunc (lt_optab, mode, "__ltkf2");
17892 set_optab_libfunc (le_optab, mode, "__lekf2");
17893 set_optab_libfunc (unord_optab, mode, "__unordkf2");
17895 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
17896 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
17897 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
17898 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
17900 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
17901 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17902 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
17904 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
17905 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17906 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
17908 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf");
17909 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf");
17910 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdkf");
17911 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd");
17912 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd");
17913 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendkftd");
17915 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
17916 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
17917 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
17918 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
17920 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
17921 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
17922 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
17923 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
17925 if (TARGET_POWERPC64)
17927 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
17928 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
17929 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
17930 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
17936 set_optab_libfunc (add_optab, mode, "_q_add");
17937 set_optab_libfunc (sub_optab, mode, "_q_sub");
17938 set_optab_libfunc (neg_optab, mode, "_q_neg");
17939 set_optab_libfunc (smul_optab, mode, "_q_mul");
17940 set_optab_libfunc (sdiv_optab, mode, "_q_div");
17941 if (TARGET_PPC_GPOPT)
17942 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
17944 set_optab_libfunc (eq_optab, mode, "_q_feq");
17945 set_optab_libfunc (ne_optab, mode, "_q_fne");
17946 set_optab_libfunc (gt_optab, mode, "_q_fgt");
17947 set_optab_libfunc (ge_optab, mode, "_q_fge");
17948 set_optab_libfunc (lt_optab, mode, "_q_flt");
17949 set_optab_libfunc (le_optab, mode, "_q_fle");
17951 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
17952 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
17953 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
17954 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
17955 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
17956 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
17957 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
17958 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
17963 rs6000_init_libfuncs (void)
17965 /* __float128 support. */
17966 if (TARGET_FLOAT128_TYPE)
17968 init_float128_ibm (IFmode);
17969 init_float128_ieee (KFmode);
17972 /* AIX/Darwin/64-bit Linux quad floating point routines. */
17973 if (TARGET_LONG_DOUBLE_128)
17975 if (!TARGET_IEEEQUAD)
17976 init_float128_ibm (TFmode);
17978 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
17980 init_float128_ieee (TFmode);
17984 /* Emit a potentially record-form instruction, setting DST from SRC.
17985 If DOT is 0, that is all; otherwise, set CCREG to the result of the
17986 signed comparison of DST with zero. If DOT is 1, the generated RTL
17987 doesn't care about the DST result; if DOT is 2, it does. If CCREG
17988 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
17989 a separate COMPARE. */
17992 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
17996 emit_move_insn (dst, src);
18000 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18002 emit_move_insn (dst, src);
18003 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18007 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18010 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18011 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18015 rtx set = gen_rtx_SET (dst, src);
18016 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18021 /* A validation routine: say whether CODE, a condition code, and MODE
18022 match. The other alternatives either don't make sense or should
18023 never be generated. */
18026 validate_condition_mode (enum rtx_code code, machine_mode mode)
18028 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18029 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18030 && GET_MODE_CLASS (mode) == MODE_CC);
18032 /* These don't make sense. */
18033 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18034 || mode != CCUNSmode);
18036 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18037 || mode == CCUNSmode);
18039 gcc_assert (mode == CCFPmode
18040 || (code != ORDERED && code != UNORDERED
18041 && code != UNEQ && code != LTGT
18042 && code != UNGT && code != UNLT
18043 && code != UNGE && code != UNLE));
18045 /* These should never be generated except for
18046 flag_finite_math_only. */
18047 gcc_assert (mode != CCFPmode
18048 || flag_finite_math_only
18049 || (code != LE && code != GE
18050 && code != UNEQ && code != LTGT
18051 && code != UNGT && code != UNLT));
18053 /* These are invalid; the information is not there. */
18054 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18058 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18059 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18060 not zero, store there the bit offset (counted from the right) where
18061 the single stretch of 1 bits begins; and similarly for B, the bit
18062 offset where it ends. */
18065 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18067 unsigned HOST_WIDE_INT val = INTVAL (mask);
18068 unsigned HOST_WIDE_INT bit;
18070 int n = GET_MODE_PRECISION (mode);
18072 if (mode != DImode && mode != SImode)
18075 if (INTVAL (mask) >= 0)
18078 ne = exact_log2 (bit);
18079 nb = exact_log2 (val + bit);
18081 else if (val + 1 == 0)
18090 nb = exact_log2 (bit);
18091 ne = exact_log2 (val + bit);
18096 ne = exact_log2 (bit);
18097 if (val + bit == 0)
18105 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18116 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18117 or rldicr instruction, to implement an AND with it in mode MODE. */
18120 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18124 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18127 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18129 if (mode == DImode)
18130 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18132 /* For SImode, rlwinm can do everything. */
18133 if (mode == SImode)
18134 return (nb < 32 && ne < 32);
18139 /* Return the instruction template for an AND with mask in mode MODE, with
18140 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18143 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18147 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18148 gcc_unreachable ();
18150 if (mode == DImode && ne == 0)
18152 operands[3] = GEN_INT (63 - nb);
18154 return "rldicl. %0,%1,0,%3";
18155 return "rldicl %0,%1,0,%3";
18158 if (mode == DImode && nb == 63)
18160 operands[3] = GEN_INT (63 - ne);
18162 return "rldicr. %0,%1,0,%3";
18163 return "rldicr %0,%1,0,%3";
18166 if (nb < 32 && ne < 32)
18168 operands[3] = GEN_INT (31 - nb);
18169 operands[4] = GEN_INT (31 - ne);
18171 return "rlwinm. %0,%1,0,%3,%4";
18172 return "rlwinm %0,%1,0,%3,%4";
18175 gcc_unreachable ();
18178 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18179 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18180 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18183 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18187 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18190 int n = GET_MODE_PRECISION (mode);
18193 if (CONST_INT_P (XEXP (shift, 1)))
18195 sh = INTVAL (XEXP (shift, 1));
18196 if (sh < 0 || sh >= n)
18200 rtx_code code = GET_CODE (shift);
18202 /* Convert any shift by 0 to a rotate, to simplify below code. */
18206 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18207 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18209 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18215 /* DImode rotates need rld*. */
18216 if (mode == DImode && code == ROTATE)
18217 return (nb == 63 || ne == 0 || ne == sh);
18219 /* SImode rotates need rlw*. */
18220 if (mode == SImode && code == ROTATE)
18221 return (nb < 32 && ne < 32 && sh < 32);
18223 /* Wrap-around masks are only okay for rotates. */
18227 /* Variable shifts are only okay for rotates. */
18231 /* Don't allow ASHIFT if the mask is wrong for that. */
18232 if (code == ASHIFT && ne < sh)
18235 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18236 if the mask is wrong for that. */
18237 if (nb < 32 && ne < 32 && sh < 32
18238 && !(code == LSHIFTRT && nb >= 32 - sh))
18241 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18242 if the mask is wrong for that. */
18243 if (code == LSHIFTRT)
18245 if (nb == 63 || ne == 0 || ne == sh)
18246 return !(code == LSHIFTRT && nb >= sh);
18251 /* Return the instruction template for a shift with mask in mode MODE, with
18252 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18255 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18259 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18260 gcc_unreachable ();
18262 if (mode == DImode && ne == 0)
18264 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18265 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18266 operands[3] = GEN_INT (63 - nb);
18268 return "rld%I2cl. %0,%1,%2,%3";
18269 return "rld%I2cl %0,%1,%2,%3";
18272 if (mode == DImode && nb == 63)
18274 operands[3] = GEN_INT (63 - ne);
18276 return "rld%I2cr. %0,%1,%2,%3";
18277 return "rld%I2cr %0,%1,%2,%3";
18281 && GET_CODE (operands[4]) != LSHIFTRT
18282 && CONST_INT_P (operands[2])
18283 && ne == INTVAL (operands[2]))
18285 operands[3] = GEN_INT (63 - nb);
18287 return "rld%I2c. %0,%1,%2,%3";
18288 return "rld%I2c %0,%1,%2,%3";
18291 if (nb < 32 && ne < 32)
18293 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18294 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18295 operands[3] = GEN_INT (31 - nb);
18296 operands[4] = GEN_INT (31 - ne);
18297 /* This insn can also be a 64-bit rotate with mask that really makes
18298 it just a shift right (with mask); the %h below are to adjust for
18299 that situation (shift count is >= 32 in that case). */
18301 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18302 return "rlw%I2nm %0,%1,%h2,%3,%4";
18305 gcc_unreachable ();
18308 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18309 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18310 ASHIFT, or LSHIFTRT) in mode MODE. */
18313 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18317 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18320 int n = GET_MODE_PRECISION (mode);
18322 int sh = INTVAL (XEXP (shift, 1));
18323 if (sh < 0 || sh >= n)
18326 rtx_code code = GET_CODE (shift);
18328 /* Convert any shift by 0 to a rotate, to simplify below code. */
18332 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18333 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18335 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18341 /* DImode rotates need rldimi. */
18342 if (mode == DImode && code == ROTATE)
18345 /* SImode rotates need rlwimi. */
18346 if (mode == SImode && code == ROTATE)
18347 return (nb < 32 && ne < 32 && sh < 32);
18349 /* Wrap-around masks are only okay for rotates. */
18353 /* Don't allow ASHIFT if the mask is wrong for that. */
18354 if (code == ASHIFT && ne < sh)
18357 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18358 if the mask is wrong for that. */
18359 if (nb < 32 && ne < 32 && sh < 32
18360 && !(code == LSHIFTRT && nb >= 32 - sh))
18363 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18364 if the mask is wrong for that. */
18365 if (code == LSHIFTRT)
18368 return !(code == LSHIFTRT && nb >= sh);
18373 /* Return the instruction template for an insert with mask in mode MODE, with
18374 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18377 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18381 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18382 gcc_unreachable ();
18384 /* Prefer rldimi because rlwimi is cracked. */
18385 if (TARGET_POWERPC64
18386 && (!dot || mode == DImode)
18387 && GET_CODE (operands[4]) != LSHIFTRT
18388 && ne == INTVAL (operands[2]))
18390 operands[3] = GEN_INT (63 - nb);
18392 return "rldimi. %0,%1,%2,%3";
18393 return "rldimi %0,%1,%2,%3";
18396 if (nb < 32 && ne < 32)
18398 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18399 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18400 operands[3] = GEN_INT (31 - nb);
18401 operands[4] = GEN_INT (31 - ne);
18403 return "rlwimi. %0,%1,%2,%3,%4";
18404 return "rlwimi %0,%1,%2,%3,%4";
18407 gcc_unreachable ();
18410 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18411 using two machine instructions. */
18414 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18416 /* There are two kinds of AND we can handle with two insns:
18417 1) those we can do with two rl* insn;
18420 We do not handle that last case yet. */
18422 /* If there is just one stretch of ones, we can do it. */
18423 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18426 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18427 one insn, we can do the whole thing with two. */
18428 unsigned HOST_WIDE_INT val = INTVAL (c);
18429 unsigned HOST_WIDE_INT bit1 = val & -val;
18430 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18431 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18432 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18433 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18436 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18437 If EXPAND is true, split rotate-and-mask instructions we generate to
18438 their constituent parts as well (this is used during expand); if DOT
18439 is 1, make the last insn a record-form instruction clobbering the
18440 destination GPR and setting the CC reg (from operands[3]); if 2, set
18441 that GPR as well as the CC reg. */
18444 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18446 gcc_assert (!(expand && dot));
18448 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18450 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18451 shift right. This generates better code than doing the masks without
18452 shifts, or shifting first right and then left. */
18454 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18456 gcc_assert (mode == DImode);
18458 int shift = 63 - nb;
18461 rtx tmp1 = gen_reg_rtx (DImode);
18462 rtx tmp2 = gen_reg_rtx (DImode);
18463 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18464 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18465 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18469 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18470 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18471 emit_move_insn (operands[0], tmp);
18472 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18473 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18478 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18479 that does the rest. */
18480 unsigned HOST_WIDE_INT bit1 = val & -val;
18481 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18482 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18483 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18485 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18486 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18488 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18490 /* Two "no-rotate"-and-mask instructions, for SImode. */
18491 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18493 gcc_assert (mode == SImode);
18495 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18496 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18497 emit_move_insn (reg, tmp);
18498 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18499 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18503 gcc_assert (mode == DImode);
18505 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18506 insns; we have to do the first in SImode, because it wraps. */
18507 if (mask2 <= 0xffffffff
18508 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18510 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18511 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18513 rtx reg_low = gen_lowpart (SImode, reg);
18514 emit_move_insn (reg_low, tmp);
18515 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18516 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18520 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18521 at the top end), rotate back and clear the other hole. */
18522 int right = exact_log2 (bit3);
18523 int left = 64 - right;
18525 /* Rotate the mask too. */
18526 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18530 rtx tmp1 = gen_reg_rtx (DImode);
18531 rtx tmp2 = gen_reg_rtx (DImode);
18532 rtx tmp3 = gen_reg_rtx (DImode);
18533 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18534 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18535 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18536 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18540 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18541 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18542 emit_move_insn (operands[0], tmp);
18543 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18544 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18545 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18549 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18550 for lfq and stfq insns iff the registers are hard registers. */
18553 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18555 /* We might have been passed a SUBREG. */
18556 if (!REG_P (reg1) || !REG_P (reg2))
18559 /* We might have been passed non floating point registers. */
18560 if (!FP_REGNO_P (REGNO (reg1))
18561 || !FP_REGNO_P (REGNO (reg2)))
18564 return (REGNO (reg1) == REGNO (reg2) - 1);
18567 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18568 addr1 and addr2 must be in consecutive memory locations
18569 (addr2 == addr1 + 8). */
18572 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18575 unsigned int reg1, reg2;
18576 int offset1, offset2;
18578 /* The mems cannot be volatile. */
18579 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18582 addr1 = XEXP (mem1, 0);
18583 addr2 = XEXP (mem2, 0);
18585 /* Extract an offset (if used) from the first addr. */
18586 if (GET_CODE (addr1) == PLUS)
18588 /* If not a REG, return zero. */
18589 if (!REG_P (XEXP (addr1, 0)))
18593 reg1 = REGNO (XEXP (addr1, 0));
18594 /* The offset must be constant! */
18595 if (!CONST_INT_P (XEXP (addr1, 1)))
18597 offset1 = INTVAL (XEXP (addr1, 1));
18600 else if (!REG_P (addr1))
18604 reg1 = REGNO (addr1);
18605 /* This was a simple (mem (reg)) expression. Offset is 0. */
18609 /* And now for the second addr. */
18610 if (GET_CODE (addr2) == PLUS)
18612 /* If not a REG, return zero. */
18613 if (!REG_P (XEXP (addr2, 0)))
18617 reg2 = REGNO (XEXP (addr2, 0));
18618 /* The offset must be constant. */
18619 if (!CONST_INT_P (XEXP (addr2, 1)))
18621 offset2 = INTVAL (XEXP (addr2, 1));
18624 else if (!REG_P (addr2))
18628 reg2 = REGNO (addr2);
18629 /* This was a simple (mem (reg)) expression. Offset is 0. */
18633 /* Both of these must have the same base register. */
18637 /* The offset for the second addr must be 8 more than the first addr. */
18638 if (offset2 != offset1 + 8)
18641 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18646 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18647 need to use DDmode, in all other cases we can use the same mode. */
18648 static machine_mode
18649 rs6000_secondary_memory_needed_mode (machine_mode mode)
18651 if (lra_in_progress && mode == SDmode)
18656 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18657 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18658 only work on the traditional altivec registers, note if an altivec register
18661 static enum rs6000_reg_type
18662 register_to_reg_type (rtx reg, bool *is_altivec)
18664 HOST_WIDE_INT regno;
18665 enum reg_class rclass;
18667 if (SUBREG_P (reg))
18668 reg = SUBREG_REG (reg);
18671 return NO_REG_TYPE;
18673 regno = REGNO (reg);
18674 if (!HARD_REGISTER_NUM_P (regno))
18676 if (!lra_in_progress && !reload_completed)
18677 return PSEUDO_REG_TYPE;
18679 regno = true_regnum (reg);
18680 if (regno < 0 || !HARD_REGISTER_NUM_P (regno))
18681 return PSEUDO_REG_TYPE;
18684 gcc_assert (regno >= 0);
18686 if (is_altivec && ALTIVEC_REGNO_P (regno))
18687 *is_altivec = true;
18689 rclass = rs6000_regno_regclass[regno];
18690 return reg_class_to_reg_type[(int)rclass];
18693 /* Helper function to return the cost of adding a TOC entry address. */
18696 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18700 if (TARGET_CMODEL != CMODEL_SMALL)
18701 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18704 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18709 /* Helper function for rs6000_secondary_reload to determine whether the memory
18710 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18711 needs reloading. Return negative if the memory is not handled by the memory
18712 helper functions and to try a different reload method, 0 if no additional
18713 instructions are need, and positive to give the extra cost for the
18717 rs6000_secondary_reload_memory (rtx addr,
18718 enum reg_class rclass,
18721 int extra_cost = 0;
18722 rtx reg, and_arg, plus_arg0, plus_arg1;
18723 addr_mask_type addr_mask;
18724 const char *type = NULL;
18725 const char *fail_msg = NULL;
18727 if (GPR_REG_CLASS_P (rclass))
18728 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18730 else if (rclass == FLOAT_REGS)
18731 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18733 else if (rclass == ALTIVEC_REGS)
18734 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18736 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18737 else if (rclass == VSX_REGS)
18738 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18739 & ~RELOAD_REG_AND_M16);
18741 /* If the register allocator hasn't made up its mind yet on the register
18742 class to use, settle on defaults to use. */
18743 else if (rclass == NO_REGS)
18745 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18746 & ~RELOAD_REG_AND_M16);
18748 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18749 addr_mask &= ~(RELOAD_REG_INDEXED
18750 | RELOAD_REG_PRE_INCDEC
18751 | RELOAD_REG_PRE_MODIFY);
18757 /* If the register isn't valid in this register class, just return now. */
18758 if ((addr_mask & RELOAD_REG_VALID) == 0)
18760 if (TARGET_DEBUG_ADDR)
18763 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18764 "not valid in class\n",
18765 GET_MODE_NAME (mode), reg_class_names[rclass]);
18772 switch (GET_CODE (addr))
18774 /* Does the register class supports auto update forms for this mode? We
18775 don't need a scratch register, since the powerpc only supports
18776 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18779 reg = XEXP (addr, 0);
18780 if (!base_reg_operand (addr, GET_MODE (reg)))
18782 fail_msg = "no base register #1";
18786 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18794 reg = XEXP (addr, 0);
18795 plus_arg1 = XEXP (addr, 1);
18796 if (!base_reg_operand (reg, GET_MODE (reg))
18797 || GET_CODE (plus_arg1) != PLUS
18798 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18800 fail_msg = "bad PRE_MODIFY";
18804 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18811 /* Do we need to simulate AND -16 to clear the bottom address bits used
18812 in VMX load/stores? Only allow the AND for vector sizes. */
18814 and_arg = XEXP (addr, 0);
18815 if (GET_MODE_SIZE (mode) != 16
18816 || !CONST_INT_P (XEXP (addr, 1))
18817 || INTVAL (XEXP (addr, 1)) != -16)
18819 fail_msg = "bad Altivec AND #1";
18823 if (rclass != ALTIVEC_REGS)
18825 if (legitimate_indirect_address_p (and_arg, false))
18828 else if (legitimate_indexed_address_p (and_arg, false))
18833 fail_msg = "bad Altivec AND #2";
18841 /* If this is an indirect address, make sure it is a base register. */
18844 if (!legitimate_indirect_address_p (addr, false))
18851 /* If this is an indexed address, make sure the register class can handle
18852 indexed addresses for this mode. */
18854 plus_arg0 = XEXP (addr, 0);
18855 plus_arg1 = XEXP (addr, 1);
18857 /* (plus (plus (reg) (constant)) (constant)) is generated during
18858 push_reload processing, so handle it now. */
18859 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
18861 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18868 /* (plus (plus (reg) (constant)) (reg)) is also generated during
18869 push_reload processing, so handle it now. */
18870 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
18872 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
18875 type = "indexed #2";
18879 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
18881 fail_msg = "no base register #2";
18885 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
18887 if ((addr_mask & RELOAD_REG_INDEXED) == 0
18888 || !legitimate_indexed_address_p (addr, false))
18895 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
18896 && CONST_INT_P (plus_arg1))
18898 if (!quad_address_offset_p (INTVAL (plus_arg1)))
18901 type = "vector d-form offset";
18905 /* Make sure the register class can handle offset addresses. */
18906 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
18908 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18911 type = "offset #2";
18917 fail_msg = "bad PLUS";
18924 /* Quad offsets are restricted and can't handle normal addresses. */
18925 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18928 type = "vector d-form lo_sum";
18931 else if (!legitimate_lo_sum_address_p (mode, addr, false))
18933 fail_msg = "bad LO_SUM";
18937 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18944 /* Static addresses need to create a TOC entry. */
18948 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18951 type = "vector d-form lo_sum #2";
18957 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
18961 /* TOC references look like offsetable memory. */
18963 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
18965 fail_msg = "bad UNSPEC";
18969 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18972 type = "vector d-form lo_sum #3";
18975 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18978 type = "toc reference";
18984 fail_msg = "bad address";
18989 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
18991 if (extra_cost < 0)
18993 "rs6000_secondary_reload_memory error: mode = %s, "
18994 "class = %s, addr_mask = '%s', %s\n",
18995 GET_MODE_NAME (mode),
18996 reg_class_names[rclass],
18997 rs6000_debug_addr_mask (addr_mask, false),
18998 (fail_msg != NULL) ? fail_msg : "<bad address>");
19002 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19003 "addr_mask = '%s', extra cost = %d, %s\n",
19004 GET_MODE_NAME (mode),
19005 reg_class_names[rclass],
19006 rs6000_debug_addr_mask (addr_mask, false),
19008 (type) ? type : "<none>");
19016 /* Helper function for rs6000_secondary_reload to return true if a move to a
19017 different register classe is really a simple move. */
19020 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19021 enum rs6000_reg_type from_type,
19024 int size = GET_MODE_SIZE (mode);
19026 /* Add support for various direct moves available. In this function, we only
19027 look at cases where we don't need any extra registers, and one or more
19028 simple move insns are issued. Originally small integers are not allowed
19029 in FPR/VSX registers. Single precision binary floating is not a simple
19030 move because we need to convert to the single precision memory layout.
19031 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19032 need special direct move handling, which we do not support yet. */
19033 if (TARGET_DIRECT_MOVE
19034 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19035 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19037 if (TARGET_POWERPC64)
19039 /* ISA 2.07: MTVSRD or MVFVSRD. */
19043 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19044 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19048 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19049 if (TARGET_P8_VECTOR)
19051 if (mode == SImode)
19054 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19058 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19059 if (mode == SDmode)
19063 /* Power6+: MFTGPR or MFFGPR. */
19064 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19065 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19066 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19069 /* Move to/from SPR. */
19070 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19071 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19072 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19078 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19079 special direct moves that involve allocating an extra register, return the
19080 insn code of the helper function if there is such a function or
19081 CODE_FOR_nothing if not. */
19084 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19085 enum rs6000_reg_type from_type,
19087 secondary_reload_info *sri,
19091 enum insn_code icode = CODE_FOR_nothing;
19093 int size = GET_MODE_SIZE (mode);
19095 if (TARGET_POWERPC64 && size == 16)
19097 /* Handle moving 128-bit values from GPRs to VSX point registers on
19098 ISA 2.07 (power8, power9) when running in 64-bit mode using
19099 XXPERMDI to glue the two 64-bit values back together. */
19100 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19102 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19103 icode = reg_addr[mode].reload_vsx_gpr;
19106 /* Handle moving 128-bit values from VSX point registers to GPRs on
19107 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19108 bottom 64-bit value. */
19109 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19111 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19112 icode = reg_addr[mode].reload_gpr_vsx;
19116 else if (TARGET_POWERPC64 && mode == SFmode)
19118 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19120 cost = 3; /* xscvdpspn, mfvsrd, and. */
19121 icode = reg_addr[mode].reload_gpr_vsx;
19124 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19126 cost = 2; /* mtvsrz, xscvspdpn. */
19127 icode = reg_addr[mode].reload_vsx_gpr;
19131 else if (!TARGET_POWERPC64 && size == 8)
19133 /* Handle moving 64-bit values from GPRs to floating point registers on
19134 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19135 32-bit values back together. Altivec register classes must be handled
19136 specially since a different instruction is used, and the secondary
19137 reload support requires a single instruction class in the scratch
19138 register constraint. However, right now TFmode is not allowed in
19139 Altivec registers, so the pattern will never match. */
19140 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19142 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19143 icode = reg_addr[mode].reload_fpr_gpr;
19147 if (icode != CODE_FOR_nothing)
19152 sri->icode = icode;
19153 sri->extra_cost = cost;
19160 /* Return whether a move between two register classes can be done either
19161 directly (simple move) or via a pattern that uses a single extra temporary
19162 (using ISA 2.07's direct move in this case. */
19165 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19166 enum rs6000_reg_type from_type,
19168 secondary_reload_info *sri,
19171 /* Fall back to load/store reloads if either type is not a register. */
19172 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19175 /* If we haven't allocated registers yet, assume the move can be done for the
19176 standard register types. */
19177 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19178 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19179 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19182 /* Moves to the same set of registers is a simple move for non-specialized
19184 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19187 /* Check whether a simple move can be done directly. */
19188 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19192 sri->icode = CODE_FOR_nothing;
19193 sri->extra_cost = 0;
19198 /* Now check if we can do it in a few steps. */
19199 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19203 /* Inform reload about cases where moving X with a mode MODE to a register in
19204 RCLASS requires an extra scratch or immediate register. Return the class
19205 needed for the immediate register.
19207 For VSX and Altivec, we may need a register to convert sp+offset into
19210 For misaligned 64-bit gpr loads and stores we need a register to
19211 convert an offset address to indirect. */
19214 rs6000_secondary_reload (bool in_p,
19216 reg_class_t rclass_i,
19218 secondary_reload_info *sri)
19220 enum reg_class rclass = (enum reg_class) rclass_i;
19221 reg_class_t ret = ALL_REGS;
19222 enum insn_code icode;
19223 bool default_p = false;
19224 bool done_p = false;
19226 /* Allow subreg of memory before/during reload. */
19227 bool memory_p = (MEM_P (x)
19228 || (!reload_completed && SUBREG_P (x)
19229 && MEM_P (SUBREG_REG (x))));
19231 sri->icode = CODE_FOR_nothing;
19232 sri->t_icode = CODE_FOR_nothing;
19233 sri->extra_cost = 0;
19235 ? reg_addr[mode].reload_load
19236 : reg_addr[mode].reload_store);
19238 if (REG_P (x) || register_operand (x, mode))
19240 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19241 bool altivec_p = (rclass == ALTIVEC_REGS);
19242 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19245 std::swap (to_type, from_type);
19247 /* Can we do a direct move of some sort? */
19248 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19251 icode = (enum insn_code)sri->icode;
19258 /* Make sure 0.0 is not reloaded or forced into memory. */
19259 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19266 /* If this is a scalar floating point value and we want to load it into the
19267 traditional Altivec registers, do it via a move via a traditional floating
19268 point register, unless we have D-form addressing. Also make sure that
19269 non-zero constants use a FPR. */
19270 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19271 && !mode_supports_vmx_dform (mode)
19272 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19273 && (memory_p || CONST_DOUBLE_P (x)))
19280 /* Handle reload of load/stores if we have reload helper functions. */
19281 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19283 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19286 if (extra_cost >= 0)
19290 if (extra_cost > 0)
19292 sri->extra_cost = extra_cost;
19293 sri->icode = icode;
19298 /* Handle unaligned loads and stores of integer registers. */
19299 if (!done_p && TARGET_POWERPC64
19300 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19302 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19304 rtx addr = XEXP (x, 0);
19305 rtx off = address_offset (addr);
19307 if (off != NULL_RTX)
19309 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19310 unsigned HOST_WIDE_INT offset = INTVAL (off);
19312 /* We need a secondary reload when our legitimate_address_p
19313 says the address is good (as otherwise the entire address
19314 will be reloaded), and the offset is not a multiple of
19315 four or we have an address wrap. Address wrap will only
19316 occur for LO_SUMs since legitimate_offset_address_p
19317 rejects addresses for 16-byte mems that will wrap. */
19318 if (GET_CODE (addr) == LO_SUM
19319 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19320 && ((offset & 3) != 0
19321 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19322 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19323 && (offset & 3) != 0))
19325 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19327 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19328 : CODE_FOR_reload_di_load);
19330 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19331 : CODE_FOR_reload_di_store);
19332 sri->extra_cost = 2;
19343 if (!done_p && !TARGET_POWERPC64
19344 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19346 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19348 rtx addr = XEXP (x, 0);
19349 rtx off = address_offset (addr);
19351 if (off != NULL_RTX)
19353 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19354 unsigned HOST_WIDE_INT offset = INTVAL (off);
19356 /* We need a secondary reload when our legitimate_address_p
19357 says the address is good (as otherwise the entire address
19358 will be reloaded), and we have a wrap.
19360 legitimate_lo_sum_address_p allows LO_SUM addresses to
19361 have any offset so test for wrap in the low 16 bits.
19363 legitimate_offset_address_p checks for the range
19364 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19365 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19366 [0x7ff4,0x7fff] respectively, so test for the
19367 intersection of these ranges, [0x7ffc,0x7fff] and
19368 [0x7ff4,0x7ff7] respectively.
19370 Note that the address we see here may have been
19371 manipulated by legitimize_reload_address. */
19372 if (GET_CODE (addr) == LO_SUM
19373 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19374 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19377 sri->icode = CODE_FOR_reload_si_load;
19379 sri->icode = CODE_FOR_reload_si_store;
19380 sri->extra_cost = 2;
19395 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19397 gcc_assert (ret != ALL_REGS);
19399 if (TARGET_DEBUG_ADDR)
19402 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19404 reg_class_names[ret],
19405 in_p ? "true" : "false",
19406 reg_class_names[rclass],
19407 GET_MODE_NAME (mode));
19409 if (reload_completed)
19410 fputs (", after reload", stderr);
19413 fputs (", done_p not set", stderr);
19416 fputs (", default secondary reload", stderr);
19418 if (sri->icode != CODE_FOR_nothing)
19419 fprintf (stderr, ", reload func = %s, extra cost = %d",
19420 insn_data[sri->icode].name, sri->extra_cost);
19422 else if (sri->extra_cost > 0)
19423 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19425 fputs ("\n", stderr);
19432 /* Better tracing for rs6000_secondary_reload_inner. */
19435 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19440 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19442 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19443 store_p ? "store" : "load");
19446 set = gen_rtx_SET (mem, reg);
19448 set = gen_rtx_SET (reg, mem);
19450 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19451 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19454 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19455 ATTRIBUTE_NORETURN;
19458 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19461 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19462 gcc_unreachable ();
19465 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19466 reload helper functions. These were identified in
19467 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19468 reload, it calls the insns:
19469 reload_<RELOAD:mode>_<P:mptrsize>_store
19470 reload_<RELOAD:mode>_<P:mptrsize>_load
19472 which in turn calls this function, to do whatever is necessary to create
19473 valid addresses. */
19476 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19478 int regno = true_regnum (reg);
19479 machine_mode mode = GET_MODE (reg);
19480 addr_mask_type addr_mask;
19483 rtx op_reg, op0, op1;
19488 if (regno < 0 || !HARD_REGISTER_NUM_P (regno) || !MEM_P (mem)
19489 || !base_reg_operand (scratch, GET_MODE (scratch)))
19490 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19492 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19493 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19495 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19496 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19498 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19499 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19502 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19504 /* Make sure the mode is valid in this register class. */
19505 if ((addr_mask & RELOAD_REG_VALID) == 0)
19506 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19508 if (TARGET_DEBUG_ADDR)
19509 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19511 new_addr = addr = XEXP (mem, 0);
19512 switch (GET_CODE (addr))
19514 /* Does the register class support auto update forms for this mode? If
19515 not, do the update now. We don't need a scratch register, since the
19516 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19519 op_reg = XEXP (addr, 0);
19520 if (!base_reg_operand (op_reg, Pmode))
19521 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19523 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19525 int delta = GET_MODE_SIZE (mode);
19526 if (GET_CODE (addr) == PRE_DEC)
19528 emit_insn (gen_add2_insn (op_reg, GEN_INT (delta)));
19534 op0 = XEXP (addr, 0);
19535 op1 = XEXP (addr, 1);
19536 if (!base_reg_operand (op0, Pmode)
19537 || GET_CODE (op1) != PLUS
19538 || !rtx_equal_p (op0, XEXP (op1, 0)))
19539 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19541 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19543 emit_insn (gen_rtx_SET (op0, op1));
19548 /* Do we need to simulate AND -16 to clear the bottom address bits used
19549 in VMX load/stores? */
19551 op0 = XEXP (addr, 0);
19552 op1 = XEXP (addr, 1);
19553 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19555 if (REG_P (op0) || SUBREG_P (op0))
19558 else if (GET_CODE (op1) == PLUS)
19560 emit_insn (gen_rtx_SET (scratch, op1));
19565 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19567 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19568 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19569 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19570 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19571 new_addr = scratch;
19575 /* If this is an indirect address, make sure it is a base register. */
19578 if (!base_reg_operand (addr, GET_MODE (addr)))
19580 emit_insn (gen_rtx_SET (scratch, addr));
19581 new_addr = scratch;
19585 /* If this is an indexed address, make sure the register class can handle
19586 indexed addresses for this mode. */
19588 op0 = XEXP (addr, 0);
19589 op1 = XEXP (addr, 1);
19590 if (!base_reg_operand (op0, Pmode))
19591 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19593 else if (int_reg_operand (op1, Pmode))
19595 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19597 emit_insn (gen_rtx_SET (scratch, addr));
19598 new_addr = scratch;
19602 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19604 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19605 || !quad_address_p (addr, mode, false))
19607 emit_insn (gen_rtx_SET (scratch, addr));
19608 new_addr = scratch;
19612 /* Make sure the register class can handle offset addresses. */
19613 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19615 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19617 emit_insn (gen_rtx_SET (scratch, addr));
19618 new_addr = scratch;
19623 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19628 op0 = XEXP (addr, 0);
19629 op1 = XEXP (addr, 1);
19630 if (!base_reg_operand (op0, Pmode))
19631 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19633 else if (int_reg_operand (op1, Pmode))
19635 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19637 emit_insn (gen_rtx_SET (scratch, addr));
19638 new_addr = scratch;
19642 /* Quad offsets are restricted and can't handle normal addresses. */
19643 else if (mode_supports_dq_form (mode))
19645 emit_insn (gen_rtx_SET (scratch, addr));
19646 new_addr = scratch;
19649 /* Make sure the register class can handle offset addresses. */
19650 else if (legitimate_lo_sum_address_p (mode, addr, false))
19652 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19654 emit_insn (gen_rtx_SET (scratch, addr));
19655 new_addr = scratch;
19660 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19667 rs6000_emit_move (scratch, addr, Pmode);
19668 new_addr = scratch;
19672 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19675 /* Adjust the address if it changed. */
19676 if (addr != new_addr)
19678 mem = replace_equiv_address_nv (mem, new_addr);
19679 if (TARGET_DEBUG_ADDR)
19680 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19683 /* Now create the move. */
19685 emit_insn (gen_rtx_SET (mem, reg));
19687 emit_insn (gen_rtx_SET (reg, mem));
19692 /* Convert reloads involving 64-bit gprs and misaligned offset
19693 addressing, or multiple 32-bit gprs and offsets that are too large,
19694 to use indirect addressing. */
19697 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19699 int regno = true_regnum (reg);
19700 enum reg_class rclass;
19702 rtx scratch_or_premodify = scratch;
19704 if (TARGET_DEBUG_ADDR)
19706 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19707 store_p ? "store" : "load");
19708 fprintf (stderr, "reg:\n");
19710 fprintf (stderr, "mem:\n");
19712 fprintf (stderr, "scratch:\n");
19713 debug_rtx (scratch);
19716 gcc_assert (regno >= 0 && HARD_REGISTER_NUM_P (regno));
19717 gcc_assert (MEM_P (mem));
19718 rclass = REGNO_REG_CLASS (regno);
19719 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19720 addr = XEXP (mem, 0);
19722 if (GET_CODE (addr) == PRE_MODIFY)
19724 gcc_assert (REG_P (XEXP (addr, 0))
19725 && GET_CODE (XEXP (addr, 1)) == PLUS
19726 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19727 scratch_or_premodify = XEXP (addr, 0);
19728 addr = XEXP (addr, 1);
19730 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19732 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19734 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19736 /* Now create the move. */
19738 emit_insn (gen_rtx_SET (mem, reg));
19740 emit_insn (gen_rtx_SET (reg, mem));
19745 /* Given an rtx X being reloaded into a reg required to be
19746 in class CLASS, return the class of reg to actually use.
19747 In general this is just CLASS; but on some machines
19748 in some cases it is preferable to use a more restrictive class.
19750 On the RS/6000, we have to return NO_REGS when we want to reload a
19751 floating-point CONST_DOUBLE to force it to be copied to memory.
19753 We also don't want to reload integer values into floating-point
19754 registers if we can at all help it. In fact, this can
19755 cause reload to die, if it tries to generate a reload of CTR
19756 into a FP register and discovers it doesn't have the memory location
19759 ??? Would it be a good idea to have reload do the converse, that is
19760 try to reload floating modes into FP registers if possible?
19763 static enum reg_class
19764 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19766 machine_mode mode = GET_MODE (x);
19767 bool is_constant = CONSTANT_P (x);
19769 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19770 reload class for it. */
19771 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19772 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19775 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19776 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19779 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19780 the reloading of address expressions using PLUS into floating point
19782 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19786 /* Zero is always allowed in all VSX registers. */
19787 if (x == CONST0_RTX (mode))
19790 /* If this is a vector constant that can be formed with a few Altivec
19791 instructions, we want altivec registers. */
19792 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19793 return ALTIVEC_REGS;
19795 /* If this is an integer constant that can easily be loaded into
19796 vector registers, allow it. */
19797 if (CONST_INT_P (x))
19799 HOST_WIDE_INT value = INTVAL (x);
19801 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19802 2.06 can generate it in the Altivec registers with
19806 if (TARGET_P8_VECTOR)
19808 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19809 return ALTIVEC_REGS;
19814 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19815 a sign extend in the Altivec registers. */
19816 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19817 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19818 return ALTIVEC_REGS;
19821 /* Force constant to memory. */
19825 /* D-form addressing can easily reload the value. */
19826 if (mode_supports_vmx_dform (mode)
19827 || mode_supports_dq_form (mode))
19830 /* If this is a scalar floating point value and we don't have D-form
19831 addressing, prefer the traditional floating point registers so that we
19832 can use D-form (register+offset) addressing. */
19833 if (rclass == VSX_REGS
19834 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19837 /* Prefer the Altivec registers if Altivec is handling the vector
19838 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
19840 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
19841 || mode == V1TImode)
19842 return ALTIVEC_REGS;
19847 if (is_constant || GET_CODE (x) == PLUS)
19849 if (reg_class_subset_p (GENERAL_REGS, rclass))
19850 return GENERAL_REGS;
19851 if (reg_class_subset_p (BASE_REGS, rclass))
19856 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == GEN_OR_FLOAT_REGS)
19857 return GENERAL_REGS;
19862 /* Debug version of rs6000_preferred_reload_class. */
19863 static enum reg_class
19864 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
19866 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
19869 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
19871 reg_class_names[ret], reg_class_names[rclass],
19872 GET_MODE_NAME (GET_MODE (x)));
19878 /* If we are copying between FP or AltiVec registers and anything else, we need
19879 a memory location. The exception is when we are targeting ppc64 and the
19880 move to/from fpr to gpr instructions are available. Also, under VSX, you
19881 can copy vector registers from the FP register set to the Altivec register
19882 set and vice versa. */
19885 rs6000_secondary_memory_needed (machine_mode mode,
19886 reg_class_t from_class,
19887 reg_class_t to_class)
19889 enum rs6000_reg_type from_type, to_type;
19890 bool altivec_p = ((from_class == ALTIVEC_REGS)
19891 || (to_class == ALTIVEC_REGS));
19893 /* If a simple/direct move is available, we don't need secondary memory */
19894 from_type = reg_class_to_reg_type[(int)from_class];
19895 to_type = reg_class_to_reg_type[(int)to_class];
19897 if (rs6000_secondary_reload_move (to_type, from_type, mode,
19898 (secondary_reload_info *)0, altivec_p))
19901 /* If we have a floating point or vector register class, we need to use
19902 memory to transfer the data. */
19903 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
19909 /* Debug version of rs6000_secondary_memory_needed. */
19911 rs6000_debug_secondary_memory_needed (machine_mode mode,
19912 reg_class_t from_class,
19913 reg_class_t to_class)
19915 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
19918 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
19919 "to_class = %s, mode = %s\n",
19920 ret ? "true" : "false",
19921 reg_class_names[from_class],
19922 reg_class_names[to_class],
19923 GET_MODE_NAME (mode));
19928 /* Return the register class of a scratch register needed to copy IN into
19929 or out of a register in RCLASS in MODE. If it can be done directly,
19930 NO_REGS is returned. */
19932 static enum reg_class
19933 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
19938 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
19940 && MACHOPIC_INDIRECT
19944 /* We cannot copy a symbolic operand directly into anything
19945 other than BASE_REGS for TARGET_ELF. So indicate that a
19946 register from BASE_REGS is needed as an intermediate
19949 On Darwin, pic addresses require a load from memory, which
19950 needs a base register. */
19951 if (rclass != BASE_REGS
19952 && (SYMBOL_REF_P (in)
19953 || GET_CODE (in) == HIGH
19954 || GET_CODE (in) == LABEL_REF
19955 || GET_CODE (in) == CONST))
19961 regno = REGNO (in);
19962 if (!HARD_REGISTER_NUM_P (regno))
19964 regno = true_regnum (in);
19965 if (!HARD_REGISTER_NUM_P (regno))
19969 else if (SUBREG_P (in))
19971 regno = true_regnum (in);
19972 if (!HARD_REGISTER_NUM_P (regno))
19978 /* If we have VSX register moves, prefer moving scalar values between
19979 Altivec registers and GPR by going via an FPR (and then via memory)
19980 instead of reloading the secondary memory address for Altivec moves. */
19982 && GET_MODE_SIZE (mode) < 16
19983 && !mode_supports_vmx_dform (mode)
19984 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
19985 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
19986 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19987 && (regno >= 0 && INT_REGNO_P (regno)))))
19990 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
19992 if (rclass == GENERAL_REGS || rclass == BASE_REGS
19993 || (regno >= 0 && INT_REGNO_P (regno)))
19996 /* Constants, memory, and VSX registers can go into VSX registers (both the
19997 traditional floating point and the altivec registers). */
19998 if (rclass == VSX_REGS
19999 && (regno == -1 || VSX_REGNO_P (regno)))
20002 /* Constants, memory, and FP registers can go into FP registers. */
20003 if ((regno == -1 || FP_REGNO_P (regno))
20004 && (rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS))
20005 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20007 /* Memory, and AltiVec registers can go into AltiVec registers. */
20008 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20009 && rclass == ALTIVEC_REGS)
20012 /* We can copy among the CR registers. */
20013 if ((rclass == CR_REGS || rclass == CR0_REGS)
20014 && regno >= 0 && CR_REGNO_P (regno))
20017 /* Otherwise, we need GENERAL_REGS. */
20018 return GENERAL_REGS;
20021 /* Debug version of rs6000_secondary_reload_class. */
20022 static enum reg_class
20023 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20024 machine_mode mode, rtx in)
20026 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20028 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20029 "mode = %s, input rtx:\n",
20030 reg_class_names[ret], reg_class_names[rclass],
20031 GET_MODE_NAME (mode));
20037 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20040 rs6000_can_change_mode_class (machine_mode from,
20042 reg_class_t rclass)
20044 unsigned from_size = GET_MODE_SIZE (from);
20045 unsigned to_size = GET_MODE_SIZE (to);
20047 if (from_size != to_size)
20049 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20051 if (reg_classes_intersect_p (xclass, rclass))
20053 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20054 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20055 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20056 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20058 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20059 single register under VSX because the scalar part of the register
20060 is in the upper 64-bits, and not the lower 64-bits. Types like
20061 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20062 IEEE floating point can't overlap, and neither can small
20065 if (to_float128_vector_p && from_float128_vector_p)
20068 else if (to_float128_vector_p || from_float128_vector_p)
20071 /* TDmode in floating-mode registers must always go into a register
20072 pair with the most significant word in the even-numbered register
20073 to match ISA requirements. In little-endian mode, this does not
20074 match subreg numbering, so we cannot allow subregs. */
20075 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20078 if (from_size < 8 || to_size < 8)
20081 if (from_size == 8 && (8 * to_nregs) != to_size)
20084 if (to_size == 8 && (8 * from_nregs) != from_size)
20093 /* Since the VSX register set includes traditional floating point registers
20094 and altivec registers, just check for the size being different instead of
20095 trying to check whether the modes are vector modes. Otherwise it won't
20096 allow say DF and DI to change classes. For types like TFmode and TDmode
20097 that take 2 64-bit registers, rather than a single 128-bit register, don't
20098 allow subregs of those types to other 128 bit types. */
20099 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20101 unsigned num_regs = (from_size + 15) / 16;
20102 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20103 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20106 return (from_size == 8 || from_size == 16);
20109 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20110 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20116 /* Debug version of rs6000_can_change_mode_class. */
20118 rs6000_debug_can_change_mode_class (machine_mode from,
20120 reg_class_t rclass)
20122 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20125 "rs6000_can_change_mode_class, return %s, from = %s, "
20126 "to = %s, rclass = %s\n",
20127 ret ? "true" : "false",
20128 GET_MODE_NAME (from), GET_MODE_NAME (to),
20129 reg_class_names[rclass]);
20134 /* Return a string to do a move operation of 128 bits of data. */
20137 rs6000_output_move_128bit (rtx operands[])
20139 rtx dest = operands[0];
20140 rtx src = operands[1];
20141 machine_mode mode = GET_MODE (dest);
20144 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20145 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20149 dest_regno = REGNO (dest);
20150 dest_gpr_p = INT_REGNO_P (dest_regno);
20151 dest_fp_p = FP_REGNO_P (dest_regno);
20152 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20153 dest_vsx_p = dest_fp_p | dest_vmx_p;
20158 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20163 src_regno = REGNO (src);
20164 src_gpr_p = INT_REGNO_P (src_regno);
20165 src_fp_p = FP_REGNO_P (src_regno);
20166 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20167 src_vsx_p = src_fp_p | src_vmx_p;
20172 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20175 /* Register moves. */
20176 if (dest_regno >= 0 && src_regno >= 0)
20183 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20184 return (WORDS_BIG_ENDIAN
20185 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20186 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20188 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20192 else if (TARGET_VSX && dest_vsx_p)
20195 return "xxlor %x0,%x1,%x1";
20197 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20198 return (WORDS_BIG_ENDIAN
20199 ? "mtvsrdd %x0,%1,%L1"
20200 : "mtvsrdd %x0,%L1,%1");
20202 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20206 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20207 return "vor %0,%1,%1";
20209 else if (dest_fp_p && src_fp_p)
20214 else if (dest_regno >= 0 && MEM_P (src))
20218 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20224 else if (TARGET_ALTIVEC && dest_vmx_p
20225 && altivec_indexed_or_indirect_operand (src, mode))
20226 return "lvx %0,%y1";
20228 else if (TARGET_VSX && dest_vsx_p)
20230 if (mode_supports_dq_form (mode)
20231 && quad_address_p (XEXP (src, 0), mode, true))
20232 return "lxv %x0,%1";
20234 else if (TARGET_P9_VECTOR)
20235 return "lxvx %x0,%y1";
20237 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20238 return "lxvw4x %x0,%y1";
20241 return "lxvd2x %x0,%y1";
20244 else if (TARGET_ALTIVEC && dest_vmx_p)
20245 return "lvx %0,%y1";
20247 else if (dest_fp_p)
20252 else if (src_regno >= 0 && MEM_P (dest))
20256 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20257 return "stq %1,%0";
20262 else if (TARGET_ALTIVEC && src_vmx_p
20263 && altivec_indexed_or_indirect_operand (dest, mode))
20264 return "stvx %1,%y0";
20266 else if (TARGET_VSX && src_vsx_p)
20268 if (mode_supports_dq_form (mode)
20269 && quad_address_p (XEXP (dest, 0), mode, true))
20270 return "stxv %x1,%0";
20272 else if (TARGET_P9_VECTOR)
20273 return "stxvx %x1,%y0";
20275 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20276 return "stxvw4x %x1,%y0";
20279 return "stxvd2x %x1,%y0";
20282 else if (TARGET_ALTIVEC && src_vmx_p)
20283 return "stvx %1,%y0";
20290 else if (dest_regno >= 0
20291 && (CONST_INT_P (src)
20292 || CONST_WIDE_INT_P (src)
20293 || CONST_DOUBLE_P (src)
20294 || GET_CODE (src) == CONST_VECTOR))
20299 else if ((dest_vmx_p && TARGET_ALTIVEC)
20300 || (dest_vsx_p && TARGET_VSX))
20301 return output_vec_const_move (operands);
20304 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20307 /* Validate a 128-bit move. */
20309 rs6000_move_128bit_ok_p (rtx operands[])
20311 machine_mode mode = GET_MODE (operands[0]);
20312 return (gpc_reg_operand (operands[0], mode)
20313 || gpc_reg_operand (operands[1], mode));
20316 /* Return true if a 128-bit move needs to be split. */
20318 rs6000_split_128bit_ok_p (rtx operands[])
20320 if (!reload_completed)
20323 if (!gpr_or_gpr_p (operands[0], operands[1]))
20326 if (quad_load_store_p (operands[0], operands[1]))
20333 /* Given a comparison operation, return the bit number in CCR to test. We
20334 know this is a valid comparison.
20336 SCC_P is 1 if this is for an scc. That means that %D will have been
20337 used instead of %C, so the bits will be in different places.
20339 Return -1 if OP isn't a valid comparison for some reason. */
20342 ccr_bit (rtx op, int scc_p)
20344 enum rtx_code code = GET_CODE (op);
20345 machine_mode cc_mode;
20350 if (!COMPARISON_P (op))
20353 reg = XEXP (op, 0);
20355 if (!REG_P (reg) || !CR_REGNO_P (REGNO (reg)))
20358 cc_mode = GET_MODE (reg);
20359 cc_regnum = REGNO (reg);
20360 base_bit = 4 * (cc_regnum - CR0_REGNO);
20362 validate_condition_mode (code, cc_mode);
20364 /* When generating a sCOND operation, only positive conditions are
20383 return scc_p ? base_bit + 3 : base_bit + 2;
20385 return base_bit + 2;
20386 case GT: case GTU: case UNLE:
20387 return base_bit + 1;
20388 case LT: case LTU: case UNGE:
20390 case ORDERED: case UNORDERED:
20391 return base_bit + 3;
20394 /* If scc, we will have done a cror to put the bit in the
20395 unordered position. So test that bit. For integer, this is ! LT
20396 unless this is an scc insn. */
20397 return scc_p ? base_bit + 3 : base_bit;
20400 return scc_p ? base_bit + 3 : base_bit + 1;
20407 /* Return the GOT register. */
20410 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20412 /* The second flow pass currently (June 1999) can't update
20413 regs_ever_live without disturbing other parts of the compiler, so
20414 update it here to make the prolog/epilogue code happy. */
20415 if (!can_create_pseudo_p ()
20416 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20417 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20419 crtl->uses_pic_offset_table = 1;
20421 return pic_offset_table_rtx;
20424 static rs6000_stack_t stack_info;
20426 /* Function to init struct machine_function.
20427 This will be called, via a pointer variable,
20428 from push_function_context. */
20430 static struct machine_function *
20431 rs6000_init_machine_status (void)
20433 stack_info.reload_completed = 0;
20434 return ggc_cleared_alloc<machine_function> ();
20437 #define INT_P(X) (CONST_INT_P (X) && GET_MODE (X) == VOIDmode)
20439 /* Write out a function code label. */
20442 rs6000_output_function_entry (FILE *file, const char *fname)
20444 if (fname[0] != '.')
20446 switch (DEFAULT_ABI)
20449 gcc_unreachable ();
20455 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20465 RS6000_OUTPUT_BASENAME (file, fname);
20468 /* Print an operand. Recognize special options, documented below. */
20471 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20472 only introduced by the linker, when applying the sda21
20474 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20475 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20477 #define SMALL_DATA_RELOC "sda21"
20478 #define SMALL_DATA_REG 0
20482 print_operand (FILE *file, rtx x, int code)
20485 unsigned HOST_WIDE_INT uval;
20489 /* %a is output_address. */
20491 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20495 /* Like 'J' but get to the GT bit only. */
20496 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20498 output_operand_lossage ("invalid %%D value");
20502 /* Bit 1 is GT bit. */
20503 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20505 /* Add one for shift count in rlinm for scc. */
20506 fprintf (file, "%d", i + 1);
20510 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20513 output_operand_lossage ("invalid %%e value");
20518 if ((uval & 0xffff) == 0 && uval != 0)
20523 /* X is a CR register. Print the number of the EQ bit of the CR */
20524 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20525 output_operand_lossage ("invalid %%E value");
20527 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20531 /* X is a CR register. Print the shift count needed to move it
20532 to the high-order four bits. */
20533 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20534 output_operand_lossage ("invalid %%f value");
20536 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20540 /* Similar, but print the count for the rotate in the opposite
20542 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20543 output_operand_lossage ("invalid %%F value");
20545 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20549 /* X is a constant integer. If it is negative, print "m",
20550 otherwise print "z". This is to make an aze or ame insn. */
20551 if (!CONST_INT_P (x))
20552 output_operand_lossage ("invalid %%G value");
20553 else if (INTVAL (x) >= 0)
20560 /* If constant, output low-order five bits. Otherwise, write
20563 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20565 print_operand (file, x, 0);
20569 /* If constant, output low-order six bits. Otherwise, write
20572 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20574 print_operand (file, x, 0);
20578 /* Print `i' if this is a constant, else nothing. */
20584 /* Write the bit number in CCR for jump. */
20585 i = ccr_bit (x, 0);
20587 output_operand_lossage ("invalid %%j code");
20589 fprintf (file, "%d", i);
20593 /* Similar, but add one for shift count in rlinm for scc and pass
20594 scc flag to `ccr_bit'. */
20595 i = ccr_bit (x, 1);
20597 output_operand_lossage ("invalid %%J code");
20599 /* If we want bit 31, write a shift count of zero, not 32. */
20600 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20604 /* X must be a constant. Write the 1's complement of the
20607 output_operand_lossage ("invalid %%k value");
20609 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20613 /* X must be a symbolic constant on ELF. Write an
20614 expression suitable for an 'addi' that adds in the low 16
20615 bits of the MEM. */
20616 if (GET_CODE (x) == CONST)
20618 if (GET_CODE (XEXP (x, 0)) != PLUS
20619 || (!SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
20620 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20621 || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
20622 output_operand_lossage ("invalid %%K value");
20624 print_operand_address (file, x);
20625 fputs ("@l", file);
20628 /* %l is output_asm_label. */
20631 /* Write second word of DImode or DFmode reference. Works on register
20632 or non-indexed memory only. */
20634 fputs (reg_names[REGNO (x) + 1], file);
20635 else if (MEM_P (x))
20637 machine_mode mode = GET_MODE (x);
20638 /* Handle possible auto-increment. Since it is pre-increment and
20639 we have already done it, we can just use an offset of word. */
20640 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20641 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20642 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20644 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20645 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20648 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20652 if (small_data_operand (x, GET_MODE (x)))
20653 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20654 reg_names[SMALL_DATA_REG]);
20658 case 'N': /* Unused */
20659 /* Write the number of elements in the vector times 4. */
20660 if (GET_CODE (x) != PARALLEL)
20661 output_operand_lossage ("invalid %%N value");
20663 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20666 case 'O': /* Unused */
20667 /* Similar, but subtract 1 first. */
20668 if (GET_CODE (x) != PARALLEL)
20669 output_operand_lossage ("invalid %%O value");
20671 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20675 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20678 || (i = exact_log2 (INTVAL (x))) < 0)
20679 output_operand_lossage ("invalid %%p value");
20681 fprintf (file, "%d", i);
20685 /* The operand must be an indirect memory reference. The result
20686 is the register name. */
20687 if (!MEM_P (x) || !REG_P (XEXP (x, 0))
20688 || REGNO (XEXP (x, 0)) >= 32)
20689 output_operand_lossage ("invalid %%P value");
20691 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20695 /* This outputs the logical code corresponding to a boolean
20696 expression. The expression may have one or both operands
20697 negated (if one, only the first one). For condition register
20698 logical operations, it will also treat the negated
20699 CR codes as NOTs, but not handle NOTs of them. */
20701 const char *const *t = 0;
20703 enum rtx_code code = GET_CODE (x);
20704 static const char * const tbl[3][3] = {
20705 { "and", "andc", "nor" },
20706 { "or", "orc", "nand" },
20707 { "xor", "eqv", "xor" } };
20711 else if (code == IOR)
20713 else if (code == XOR)
20716 output_operand_lossage ("invalid %%q value");
20718 if (GET_CODE (XEXP (x, 0)) != NOT)
20722 if (GET_CODE (XEXP (x, 1)) == NOT)
20733 if (! TARGET_MFCRF)
20739 /* X is a CR register. Print the mask for `mtcrf'. */
20740 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20741 output_operand_lossage ("invalid %%R value");
20743 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20747 /* Low 5 bits of 32 - value */
20749 output_operand_lossage ("invalid %%s value");
20751 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20755 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20756 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20758 output_operand_lossage ("invalid %%t value");
20762 /* Bit 3 is OV bit. */
20763 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20765 /* If we want bit 31, write a shift count of zero, not 32. */
20766 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20770 /* Print the symbolic name of a branch target register. */
20771 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20772 x = XVECEXP (x, 0, 0);
20773 if (!REG_P (x) || (REGNO (x) != LR_REGNO
20774 && REGNO (x) != CTR_REGNO))
20775 output_operand_lossage ("invalid %%T value");
20776 else if (REGNO (x) == LR_REGNO)
20777 fputs ("lr", file);
20779 fputs ("ctr", file);
20783 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20784 for use in unsigned operand. */
20787 output_operand_lossage ("invalid %%u value");
20792 if ((uval & 0xffff) == 0)
20795 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20799 /* High-order 16 bits of constant for use in signed operand. */
20801 output_operand_lossage ("invalid %%v value");
20803 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20804 (INTVAL (x) >> 16) & 0xffff);
20808 /* Print `u' if this has an auto-increment or auto-decrement. */
20810 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20811 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20812 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20817 /* Print the trap code for this operand. */
20818 switch (GET_CODE (x))
20821 fputs ("eq", file); /* 4 */
20824 fputs ("ne", file); /* 24 */
20827 fputs ("lt", file); /* 16 */
20830 fputs ("le", file); /* 20 */
20833 fputs ("gt", file); /* 8 */
20836 fputs ("ge", file); /* 12 */
20839 fputs ("llt", file); /* 2 */
20842 fputs ("lle", file); /* 6 */
20845 fputs ("lgt", file); /* 1 */
20848 fputs ("lge", file); /* 5 */
20851 output_operand_lossage ("invalid %%V value");
20856 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
20859 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
20860 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
20862 print_operand (file, x, 0);
20866 /* X is a FPR or Altivec register used in a VSX context. */
20867 if (!REG_P (x) || !VSX_REGNO_P (REGNO (x)))
20868 output_operand_lossage ("invalid %%x value");
20871 int reg = REGNO (x);
20872 int vsx_reg = (FP_REGNO_P (reg)
20874 : reg - FIRST_ALTIVEC_REGNO + 32);
20876 #ifdef TARGET_REGNAMES
20877 if (TARGET_REGNAMES)
20878 fprintf (file, "%%vs%d", vsx_reg);
20881 fprintf (file, "%d", vsx_reg);
20887 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
20888 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
20889 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
20894 /* Like 'L', for third word of TImode/PTImode */
20896 fputs (reg_names[REGNO (x) + 2], file);
20897 else if (MEM_P (x))
20899 machine_mode mode = GET_MODE (x);
20900 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20901 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20902 output_address (mode, plus_constant (Pmode,
20903 XEXP (XEXP (x, 0), 0), 8));
20904 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20905 output_address (mode, plus_constant (Pmode,
20906 XEXP (XEXP (x, 0), 0), 8));
20908 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
20909 if (small_data_operand (x, GET_MODE (x)))
20910 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20911 reg_names[SMALL_DATA_REG]);
20916 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20917 x = XVECEXP (x, 0, 1);
20918 /* X is a SYMBOL_REF. Write out the name preceded by a
20919 period and without any trailing data in brackets. Used for function
20920 names. If we are configured for System V (or the embedded ABI) on
20921 the PowerPC, do not emit the period, since those systems do not use
20922 TOCs and the like. */
20923 if (!SYMBOL_REF_P (x))
20925 output_operand_lossage ("invalid %%z value");
20929 /* For macho, check to see if we need a stub. */
20932 const char *name = XSTR (x, 0);
20934 if (darwin_emit_branch_islands
20935 && MACHOPIC_INDIRECT
20936 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
20937 name = machopic_indirection_name (x, /*stub_p=*/true);
20939 assemble_name (file, name);
20941 else if (!DOT_SYMBOLS)
20942 assemble_name (file, XSTR (x, 0));
20944 rs6000_output_function_entry (file, XSTR (x, 0));
20948 /* Like 'L', for last word of TImode/PTImode. */
20950 fputs (reg_names[REGNO (x) + 3], file);
20951 else if (MEM_P (x))
20953 machine_mode mode = GET_MODE (x);
20954 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20955 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20956 output_address (mode, plus_constant (Pmode,
20957 XEXP (XEXP (x, 0), 0), 12));
20958 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20959 output_address (mode, plus_constant (Pmode,
20960 XEXP (XEXP (x, 0), 0), 12));
20962 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
20963 if (small_data_operand (x, GET_MODE (x)))
20964 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20965 reg_names[SMALL_DATA_REG]);
20969 /* Print AltiVec memory operand. */
20974 gcc_assert (MEM_P (x));
20978 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
20979 && GET_CODE (tmp) == AND
20980 && CONST_INT_P (XEXP (tmp, 1))
20981 && INTVAL (XEXP (tmp, 1)) == -16)
20982 tmp = XEXP (tmp, 0);
20983 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
20984 && GET_CODE (tmp) == PRE_MODIFY)
20985 tmp = XEXP (tmp, 1);
20987 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
20990 if (GET_CODE (tmp) != PLUS
20991 || !REG_P (XEXP (tmp, 0))
20992 || !REG_P (XEXP (tmp, 1)))
20994 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
20998 if (REGNO (XEXP (tmp, 0)) == 0)
20999 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21000 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21002 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21003 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21010 fprintf (file, "%s", reg_names[REGNO (x)]);
21011 else if (MEM_P (x))
21013 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21014 know the width from the mode. */
21015 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21016 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21017 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21018 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21019 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21020 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21021 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21022 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21024 output_address (GET_MODE (x), XEXP (x, 0));
21026 else if (toc_relative_expr_p (x, false,
21027 &tocrel_base_oac, &tocrel_offset_oac))
21028 /* This hack along with a corresponding hack in
21029 rs6000_output_addr_const_extra arranges to output addends
21030 where the assembler expects to find them. eg.
21031 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21032 without this hack would be output as "x@toc+4". We
21034 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21035 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
21036 output_addr_const (file, XVECEXP (x, 0, 0));
21037 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
21038 output_addr_const (file, XVECEXP (x, 0, 1));
21040 output_addr_const (file, x);
21044 if (const char *name = get_some_local_dynamic_name ())
21045 assemble_name (file, name);
21047 output_operand_lossage ("'%%&' used without any "
21048 "local dynamic TLS references");
21052 output_operand_lossage ("invalid %%xn code");
21056 /* Print the address of an operand. */
21059 print_operand_address (FILE *file, rtx x)
21062 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21063 else if (SYMBOL_REF_P (x) || GET_CODE (x) == CONST
21064 || GET_CODE (x) == LABEL_REF)
21066 output_addr_const (file, x);
21067 if (small_data_operand (x, GET_MODE (x)))
21068 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21069 reg_names[SMALL_DATA_REG]);
21071 gcc_assert (!TARGET_TOC);
21073 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21074 && REG_P (XEXP (x, 1)))
21076 if (REGNO (XEXP (x, 0)) == 0)
21077 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21078 reg_names[ REGNO (XEXP (x, 0)) ]);
21080 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21081 reg_names[ REGNO (XEXP (x, 1)) ]);
21083 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21084 && CONST_INT_P (XEXP (x, 1)))
21085 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21086 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21088 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21089 && CONSTANT_P (XEXP (x, 1)))
21091 fprintf (file, "lo16(");
21092 output_addr_const (file, XEXP (x, 1));
21093 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21097 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21098 && CONSTANT_P (XEXP (x, 1)))
21100 output_addr_const (file, XEXP (x, 1));
21101 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21104 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21106 /* This hack along with a corresponding hack in
21107 rs6000_output_addr_const_extra arranges to output addends
21108 where the assembler expects to find them. eg.
21110 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21111 without this hack would be output as "x@toc+8@l(9)". We
21112 want "x+8@toc@l(9)". */
21113 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21114 if (GET_CODE (x) == LO_SUM)
21115 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21117 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21120 output_addr_const (file, x);
21123 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21126 rs6000_output_addr_const_extra (FILE *file, rtx x)
21128 if (GET_CODE (x) == UNSPEC)
21129 switch (XINT (x, 1))
21131 case UNSPEC_TOCREL:
21132 gcc_checking_assert (SYMBOL_REF_P (XVECEXP (x, 0, 0))
21133 && REG_P (XVECEXP (x, 0, 1))
21134 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21135 output_addr_const (file, XVECEXP (x, 0, 0));
21136 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21138 if (INTVAL (tocrel_offset_oac) >= 0)
21139 fprintf (file, "+");
21140 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21142 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21145 assemble_name (file, toc_label_name);
21148 else if (TARGET_ELF)
21149 fputs ("@toc", file);
21153 case UNSPEC_MACHOPIC_OFFSET:
21154 output_addr_const (file, XVECEXP (x, 0, 0));
21156 machopic_output_function_base_name (file);
21163 /* Target hook for assembling integer objects. The PowerPC version has
21164 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21165 is defined. It also needs to handle DI-mode objects on 64-bit
21169 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21171 #ifdef RELOCATABLE_NEEDS_FIXUP
21172 /* Special handling for SI values. */
21173 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21175 static int recurse = 0;
21177 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21178 the .fixup section. Since the TOC section is already relocated, we
21179 don't need to mark it here. We used to skip the text section, but it
21180 should never be valid for relocated addresses to be placed in the text
21182 if (DEFAULT_ABI == ABI_V4
21183 && (TARGET_RELOCATABLE || flag_pic > 1)
21184 && in_section != toc_section
21186 && !CONST_SCALAR_INT_P (x)
21192 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21194 ASM_OUTPUT_LABEL (asm_out_file, buf);
21195 fprintf (asm_out_file, "\t.long\t(");
21196 output_addr_const (asm_out_file, x);
21197 fprintf (asm_out_file, ")@fixup\n");
21198 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21199 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21200 fprintf (asm_out_file, "\t.long\t");
21201 assemble_name (asm_out_file, buf);
21202 fprintf (asm_out_file, "\n\t.previous\n");
21206 /* Remove initial .'s to turn a -mcall-aixdesc function
21207 address into the address of the descriptor, not the function
21209 else if (SYMBOL_REF_P (x)
21210 && XSTR (x, 0)[0] == '.'
21211 && DEFAULT_ABI == ABI_AIX)
21213 const char *name = XSTR (x, 0);
21214 while (*name == '.')
21217 fprintf (asm_out_file, "\t.long\t%s\n", name);
21221 #endif /* RELOCATABLE_NEEDS_FIXUP */
21222 return default_assemble_integer (x, size, aligned_p);
21225 /* Return a template string for assembly to emit when making an
21226 external call. FUNOP is the call mem argument operand number. */
21228 static const char *
21229 rs6000_call_template_1 (rtx *operands, unsigned int funop, bool sibcall)
21231 /* -Wformat-overflow workaround, without which gcc thinks that %u
21232 might produce 10 digits. */
21233 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21237 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21239 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21240 sprintf (arg, "(%%%u@tlsgd)", funop + 1);
21241 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21242 sprintf (arg, "(%%&@tlsld)");
21244 gcc_unreachable ();
21247 /* The magic 32768 offset here corresponds to the offset of
21248 r30 in .got2, as given by LCTOC1. See sysv4.h:toc_section. */
21250 sprintf (z, "%%z%u%s", funop,
21251 (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == 2
21254 static char str[32]; /* 2 spare */
21255 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
21256 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21257 sibcall ? "" : "\n\tnop");
21258 else if (DEFAULT_ABI == ABI_V4)
21259 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21260 flag_pic ? "@plt" : "");
21262 /* If/when we remove the mlongcall opt, we can share the AIX/ELGv2 case. */
21263 else if (DEFAULT_ABI == ABI_DARWIN)
21265 /* The cookie is in operand func+2. */
21266 gcc_checking_assert (GET_CODE (operands[funop + 2]) == CONST_INT);
21267 int cookie = INTVAL (operands[funop + 2]);
21268 if (cookie & CALL_LONG)
21270 tree funname = get_identifier (XSTR (operands[funop], 0));
21271 tree labelname = get_prev_label (funname);
21272 gcc_checking_assert (labelname && !sibcall);
21274 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21275 instruction will reach 'foo', otherwise link as 'bl L42'".
21276 "L42" should be a 'branch island', that will do a far jump to
21277 'foo'. Branch islands are generated in
21278 macho_branch_islands(). */
21279 sprintf (str, "jbsr %%z%u,%.10s", funop,
21280 IDENTIFIER_POINTER (labelname));
21283 /* Same as AIX or ELFv2, except to keep backwards compat, no nop
21285 sprintf (str, "b%s %s%s", sibcall ? "" : "l", z, arg);
21289 gcc_unreachable ();
21294 rs6000_call_template (rtx *operands, unsigned int funop)
21296 return rs6000_call_template_1 (operands, funop, false);
21300 rs6000_sibcall_template (rtx *operands, unsigned int funop)
21302 return rs6000_call_template_1 (operands, funop, true);
21305 /* As above, for indirect calls. */
21307 static const char *
21308 rs6000_indirect_call_template_1 (rtx *operands, unsigned int funop,
21311 /* -Wformat-overflow workaround, without which gcc thinks that %u
21312 might produce 10 digits. Note that -Wformat-overflow will not
21313 currently warn here for str[], so do not rely on a warning to
21314 ensure str[] is correctly sized. */
21315 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21317 /* Currently, funop is either 0 or 1. The maximum string is always
21318 a !speculate 64-bit __tls_get_addr call.
21322 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21323 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21325 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21326 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21333 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21334 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21336 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21337 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21344 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21345 . 35 .reloc .,R_PPC64_PLTSEQ,%z1+32768\n\t
21347 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21348 . 36 .reloc .,R_PPC64_PLTCALL,%z1+32768\n\t
21352 static char str[160]; /* 8 spare */
21354 const char *ptrload = TARGET_64BIT ? "d" : "wz";
21356 if (DEFAULT_ABI == ABI_AIX)
21359 ptrload, funop + 2);
21361 /* We don't need the extra code to stop indirect call speculation if
21363 bool speculate = (TARGET_MACHO
21364 || rs6000_speculate_indirect_jumps
21365 || (REG_P (operands[funop])
21366 && REGNO (operands[funop]) == LR_REGNO));
21368 if (TARGET_PLTSEQ && GET_CODE (operands[funop]) == UNSPEC)
21370 const char *rel64 = TARGET_64BIT ? "64" : "";
21373 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21375 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21376 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%%u\n\t",
21378 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21379 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21382 gcc_unreachable ();
21385 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21386 && flag_pic == 2 ? "+32768" : "");
21390 "%s.reloc .,R_PPC%s_PLTSEQ,%%z%u%s\n\t",
21391 tls, rel64, funop, addend);
21392 s += sprintf (s, "crset 2\n\t");
21395 "%s.reloc .,R_PPC%s_PLTCALL,%%z%u%s\n\t",
21396 tls, rel64, funop, addend);
21398 else if (!speculate)
21399 s += sprintf (s, "crset 2\n\t");
21401 if (DEFAULT_ABI == ABI_AIX)
21407 funop, ptrload, funop + 3);
21412 funop, ptrload, funop + 3);
21414 else if (DEFAULT_ABI == ABI_ELFv2)
21420 funop, ptrload, funop + 2);
21425 funop, ptrload, funop + 2);
21432 funop, sibcall ? "" : "l");
21436 funop, sibcall ? "" : "l", sibcall ? "\n\tb $" : "");
21442 rs6000_indirect_call_template (rtx *operands, unsigned int funop)
21444 return rs6000_indirect_call_template_1 (operands, funop, false);
21448 rs6000_indirect_sibcall_template (rtx *operands, unsigned int funop)
21450 return rs6000_indirect_call_template_1 (operands, funop, true);
21454 /* Output indirect call insns.
21455 WHICH is 0 for tocsave, 1 for plt16_ha, 2 for plt16_lo, 3 for mtctr. */
21457 rs6000_pltseq_template (rtx *operands, int which)
21459 const char *rel64 = TARGET_64BIT ? "64" : "";
21462 if (TARGET_TLS_MARKERS && GET_CODE (operands[3]) == UNSPEC)
21464 if (XINT (operands[3], 1) == UNSPEC_TLSGD)
21465 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%3\n\t",
21467 else if (XINT (operands[3], 1) == UNSPEC_TLSLD)
21468 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21471 gcc_unreachable ();
21474 gcc_assert (DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_V4);
21475 static char str[96]; /* 15 spare */
21476 const char *off = WORDS_BIG_ENDIAN ? "+2" : "";
21477 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21478 && flag_pic == 2 ? "+32768" : "");
21483 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2\n\t"
21485 tls, rel64, TARGET_64BIT ? "d 2,24(1)" : "w 2,12(1)");
21488 if (DEFAULT_ABI == ABI_V4 && !flag_pic)
21490 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2\n\t"
21495 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2%s\n\t"
21497 tls, off, rel64, addend);
21501 "%s.reloc .%s,R_PPC%s_PLT16_LO%s,%%z2%s\n\t"
21503 tls, off, rel64, TARGET_64BIT ? "_DS" : "", addend,
21504 TARGET_64BIT ? "d" : "wz");
21508 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2%s\n\t"
21510 tls, rel64, addend);
21513 gcc_unreachable ();
21519 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21520 /* Emit an assembler directive to set symbol visibility for DECL to
21521 VISIBILITY_TYPE. */
21524 rs6000_assemble_visibility (tree decl, int vis)
21529 /* Functions need to have their entry point symbol visibility set as
21530 well as their descriptor symbol visibility. */
21531 if (DEFAULT_ABI == ABI_AIX
21533 && TREE_CODE (decl) == FUNCTION_DECL)
21535 static const char * const visibility_types[] = {
21536 NULL, "protected", "hidden", "internal"
21539 const char *name, *type;
21541 name = ((* targetm.strip_name_encoding)
21542 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21543 type = visibility_types[vis];
21545 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21546 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21549 default_assemble_visibility (decl, vis);
21554 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21556 /* Reversal of FP compares takes care -- an ordered compare
21557 becomes an unordered compare and vice versa. */
21558 if (mode == CCFPmode
21559 && (!flag_finite_math_only
21560 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21561 || code == UNEQ || code == LTGT))
21562 return reverse_condition_maybe_unordered (code);
21564 return reverse_condition (code);
21567 /* Generate a compare for CODE. Return a brand-new rtx that
21568 represents the result of the compare. */
21571 rs6000_generate_compare (rtx cmp, machine_mode mode)
21573 machine_mode comp_mode;
21574 rtx compare_result;
21575 enum rtx_code code = GET_CODE (cmp);
21576 rtx op0 = XEXP (cmp, 0);
21577 rtx op1 = XEXP (cmp, 1);
21579 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21580 comp_mode = CCmode;
21581 else if (FLOAT_MODE_P (mode))
21582 comp_mode = CCFPmode;
21583 else if (code == GTU || code == LTU
21584 || code == GEU || code == LEU)
21585 comp_mode = CCUNSmode;
21586 else if ((code == EQ || code == NE)
21587 && unsigned_reg_p (op0)
21588 && (unsigned_reg_p (op1)
21589 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21590 /* These are unsigned values, perhaps there will be a later
21591 ordering compare that can be shared with this one. */
21592 comp_mode = CCUNSmode;
21594 comp_mode = CCmode;
21596 /* If we have an unsigned compare, make sure we don't have a signed value as
21598 if (comp_mode == CCUNSmode && CONST_INT_P (op1)
21599 && INTVAL (op1) < 0)
21601 op0 = copy_rtx_if_shared (op0);
21602 op1 = force_reg (GET_MODE (op0), op1);
21603 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21606 /* First, the compare. */
21607 compare_result = gen_reg_rtx (comp_mode);
21609 /* IEEE 128-bit support in VSX registers when we do not have hardware
21611 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21613 rtx libfunc = NULL_RTX;
21614 bool check_nan = false;
21621 libfunc = optab_libfunc (eq_optab, mode);
21626 libfunc = optab_libfunc (ge_optab, mode);
21631 libfunc = optab_libfunc (le_optab, mode);
21636 libfunc = optab_libfunc (unord_optab, mode);
21637 code = (code == UNORDERED) ? NE : EQ;
21643 libfunc = optab_libfunc (ge_optab, mode);
21644 code = (code == UNGE) ? GE : GT;
21650 libfunc = optab_libfunc (le_optab, mode);
21651 code = (code == UNLE) ? LE : LT;
21657 libfunc = optab_libfunc (eq_optab, mode);
21658 code = (code = UNEQ) ? EQ : NE;
21662 gcc_unreachable ();
21665 gcc_assert (libfunc);
21668 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21669 SImode, op0, mode, op1, mode);
21671 /* The library signals an exception for signalling NaNs, so we need to
21672 handle isgreater, etc. by first checking isordered. */
21675 rtx ne_rtx, normal_dest, unord_dest;
21676 rtx unord_func = optab_libfunc (unord_optab, mode);
21677 rtx join_label = gen_label_rtx ();
21678 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21679 rtx unord_cmp = gen_reg_rtx (comp_mode);
21682 /* Test for either value being a NaN. */
21683 gcc_assert (unord_func);
21684 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21685 SImode, op0, mode, op1, mode);
21687 /* Set value (0) if either value is a NaN, and jump to the join
21689 dest = gen_reg_rtx (SImode);
21690 emit_move_insn (dest, const1_rtx);
21691 emit_insn (gen_rtx_SET (unord_cmp,
21692 gen_rtx_COMPARE (comp_mode, unord_dest,
21695 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21696 emit_jump_insn (gen_rtx_SET (pc_rtx,
21697 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21701 /* Do the normal comparison, knowing that the values are not
21703 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21704 SImode, op0, mode, op1, mode);
21706 emit_insn (gen_cstoresi4 (dest,
21707 gen_rtx_fmt_ee (code, SImode, normal_dest,
21709 normal_dest, const0_rtx));
21711 /* Join NaN and non-Nan paths. Compare dest against 0. */
21712 emit_label (join_label);
21716 emit_insn (gen_rtx_SET (compare_result,
21717 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21722 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21723 CLOBBERs to match cmptf_internal2 pattern. */
21724 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21725 && FLOAT128_IBM_P (GET_MODE (op0))
21726 && TARGET_HARD_FLOAT)
21727 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21729 gen_rtx_SET (compare_result,
21730 gen_rtx_COMPARE (comp_mode, op0, op1)),
21731 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21732 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21733 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21734 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21735 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21736 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21737 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21738 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21739 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21740 else if (GET_CODE (op1) == UNSPEC
21741 && XINT (op1, 1) == UNSPEC_SP_TEST)
21743 rtx op1b = XVECEXP (op1, 0, 0);
21744 comp_mode = CCEQmode;
21745 compare_result = gen_reg_rtx (CCEQmode);
21747 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21749 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21752 emit_insn (gen_rtx_SET (compare_result,
21753 gen_rtx_COMPARE (comp_mode, op0, op1)));
21756 /* Some kinds of FP comparisons need an OR operation;
21757 under flag_finite_math_only we don't bother. */
21758 if (FLOAT_MODE_P (mode)
21759 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21760 && !flag_finite_math_only
21761 && (code == LE || code == GE
21762 || code == UNEQ || code == LTGT
21763 || code == UNGT || code == UNLT))
21765 enum rtx_code or1, or2;
21766 rtx or1_rtx, or2_rtx, compare2_rtx;
21767 rtx or_result = gen_reg_rtx (CCEQmode);
21771 case LE: or1 = LT; or2 = EQ; break;
21772 case GE: or1 = GT; or2 = EQ; break;
21773 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21774 case LTGT: or1 = LT; or2 = GT; break;
21775 case UNGT: or1 = UNORDERED; or2 = GT; break;
21776 case UNLT: or1 = UNORDERED; or2 = LT; break;
21777 default: gcc_unreachable ();
21779 validate_condition_mode (or1, comp_mode);
21780 validate_condition_mode (or2, comp_mode);
21781 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21782 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21783 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21784 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21786 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21788 compare_result = or_result;
21792 validate_condition_mode (code, GET_MODE (compare_result));
21794 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21798 /* Return the diagnostic message string if the binary operation OP is
21799 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21802 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21806 machine_mode mode1 = TYPE_MODE (type1);
21807 machine_mode mode2 = TYPE_MODE (type2);
21809 /* For complex modes, use the inner type. */
21810 if (COMPLEX_MODE_P (mode1))
21811 mode1 = GET_MODE_INNER (mode1);
21813 if (COMPLEX_MODE_P (mode2))
21814 mode2 = GET_MODE_INNER (mode2);
21816 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21817 double to intermix unless -mfloat128-convert. */
21818 if (mode1 == mode2)
21821 if (!TARGET_FLOAT128_CVT)
21823 if ((mode1 == KFmode && mode2 == IFmode)
21824 || (mode1 == IFmode && mode2 == KFmode))
21825 return N_("__float128 and __ibm128 cannot be used in the same "
21828 if (TARGET_IEEEQUAD
21829 && ((mode1 == IFmode && mode2 == TFmode)
21830 || (mode1 == TFmode && mode2 == IFmode)))
21831 return N_("__ibm128 and long double cannot be used in the same "
21834 if (!TARGET_IEEEQUAD
21835 && ((mode1 == KFmode && mode2 == TFmode)
21836 || (mode1 == TFmode && mode2 == KFmode)))
21837 return N_("__float128 and long double cannot be used in the same "
21845 /* Expand floating point conversion to/from __float128 and __ibm128. */
21848 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21850 machine_mode dest_mode = GET_MODE (dest);
21851 machine_mode src_mode = GET_MODE (src);
21852 convert_optab cvt = unknown_optab;
21853 bool do_move = false;
21854 rtx libfunc = NULL_RTX;
21856 typedef rtx (*rtx_2func_t) (rtx, rtx);
21857 rtx_2func_t hw_convert = (rtx_2func_t)0;
21861 rtx_2func_t from_df;
21862 rtx_2func_t from_sf;
21863 rtx_2func_t from_si_sign;
21864 rtx_2func_t from_si_uns;
21865 rtx_2func_t from_di_sign;
21866 rtx_2func_t from_di_uns;
21869 rtx_2func_t to_si_sign;
21870 rtx_2func_t to_si_uns;
21871 rtx_2func_t to_di_sign;
21872 rtx_2func_t to_di_uns;
21873 } hw_conversions[2] = {
21874 /* convertions to/from KFmode */
21876 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21877 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21878 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21879 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21880 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21881 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21882 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21883 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21884 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21885 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21886 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21887 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21890 /* convertions to/from TFmode */
21892 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21893 gen_extendsftf2_hw, /* TFmode <- SFmode. */
21894 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
21895 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
21896 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
21897 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
21898 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
21899 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
21900 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
21901 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
21902 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
21903 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
21907 if (dest_mode == src_mode)
21908 gcc_unreachable ();
21910 /* Eliminate memory operations. */
21912 src = force_reg (src_mode, src);
21916 rtx tmp = gen_reg_rtx (dest_mode);
21917 rs6000_expand_float128_convert (tmp, src, unsigned_p);
21918 rs6000_emit_move (dest, tmp, dest_mode);
21922 /* Convert to IEEE 128-bit floating point. */
21923 if (FLOAT128_IEEE_P (dest_mode))
21925 if (dest_mode == KFmode)
21927 else if (dest_mode == TFmode)
21930 gcc_unreachable ();
21936 hw_convert = hw_conversions[kf_or_tf].from_df;
21941 hw_convert = hw_conversions[kf_or_tf].from_sf;
21947 if (FLOAT128_IBM_P (src_mode))
21956 cvt = ufloat_optab;
21957 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
21961 cvt = sfloat_optab;
21962 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
21969 cvt = ufloat_optab;
21970 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
21974 cvt = sfloat_optab;
21975 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
21980 gcc_unreachable ();
21984 /* Convert from IEEE 128-bit floating point. */
21985 else if (FLOAT128_IEEE_P (src_mode))
21987 if (src_mode == KFmode)
21989 else if (src_mode == TFmode)
21992 gcc_unreachable ();
21998 hw_convert = hw_conversions[kf_or_tf].to_df;
22003 hw_convert = hw_conversions[kf_or_tf].to_sf;
22009 if (FLOAT128_IBM_P (dest_mode))
22019 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22024 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22032 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22037 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22042 gcc_unreachable ();
22046 /* Both IBM format. */
22047 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22051 gcc_unreachable ();
22053 /* Handle conversion between TFmode/KFmode/IFmode. */
22055 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
22057 /* Handle conversion if we have hardware support. */
22058 else if (TARGET_FLOAT128_HW && hw_convert)
22059 emit_insn ((hw_convert) (dest, src));
22061 /* Call an external function to do the conversion. */
22062 else if (cvt != unknown_optab)
22064 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22065 gcc_assert (libfunc != NULL_RTX);
22067 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22070 gcc_assert (dest2 != NULL_RTX);
22071 if (!rtx_equal_p (dest, dest2))
22072 emit_move_insn (dest, dest2);
22076 gcc_unreachable ();
22082 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22083 can be used as that dest register. Return the dest register. */
22086 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22088 if (op2 == const0_rtx)
22091 if (GET_CODE (scratch) == SCRATCH)
22092 scratch = gen_reg_rtx (mode);
22094 if (logical_operand (op2, mode))
22095 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22097 emit_insn (gen_rtx_SET (scratch,
22098 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22104 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22107 machine_mode op_mode;
22108 enum rtx_code cond_code;
22109 rtx result = operands[0];
22111 condition_rtx = rs6000_generate_compare (operands[1], mode);
22112 cond_code = GET_CODE (condition_rtx);
22114 if (cond_code == NE
22115 || cond_code == GE || cond_code == LE
22116 || cond_code == GEU || cond_code == LEU
22117 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22119 rtx not_result = gen_reg_rtx (CCEQmode);
22120 rtx not_op, rev_cond_rtx;
22121 machine_mode cc_mode;
22123 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22125 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22126 SImode, XEXP (condition_rtx, 0), const0_rtx);
22127 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22128 emit_insn (gen_rtx_SET (not_result, not_op));
22129 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22132 op_mode = GET_MODE (XEXP (operands[1], 0));
22133 if (op_mode == VOIDmode)
22134 op_mode = GET_MODE (XEXP (operands[1], 1));
22136 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22138 PUT_MODE (condition_rtx, DImode);
22139 convert_move (result, condition_rtx, 0);
22143 PUT_MODE (condition_rtx, SImode);
22144 emit_insn (gen_rtx_SET (result, condition_rtx));
22148 /* Emit a branch of kind CODE to location LOC. */
22151 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22153 rtx condition_rtx, loc_ref;
22155 condition_rtx = rs6000_generate_compare (operands[0], mode);
22156 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22157 emit_jump_insn (gen_rtx_SET (pc_rtx,
22158 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22159 loc_ref, pc_rtx)));
22162 /* Return the string to output a conditional branch to LABEL, which is
22163 the operand template of the label, or NULL if the branch is really a
22164 conditional return.
22166 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22167 condition code register and its mode specifies what kind of
22168 comparison we made.
22170 REVERSED is nonzero if we should reverse the sense of the comparison.
22172 INSN is the insn. */
22175 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22177 static char string[64];
22178 enum rtx_code code = GET_CODE (op);
22179 rtx cc_reg = XEXP (op, 0);
22180 machine_mode mode = GET_MODE (cc_reg);
22181 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22182 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22183 int really_reversed = reversed ^ need_longbranch;
22189 validate_condition_mode (code, mode);
22191 /* Work out which way this really branches. We could use
22192 reverse_condition_maybe_unordered here always but this
22193 makes the resulting assembler clearer. */
22194 if (really_reversed)
22196 /* Reversal of FP compares takes care -- an ordered compare
22197 becomes an unordered compare and vice versa. */
22198 if (mode == CCFPmode)
22199 code = reverse_condition_maybe_unordered (code);
22201 code = reverse_condition (code);
22206 /* Not all of these are actually distinct opcodes, but
22207 we distinguish them for clarity of the resulting assembler. */
22208 case NE: case LTGT:
22209 ccode = "ne"; break;
22210 case EQ: case UNEQ:
22211 ccode = "eq"; break;
22213 ccode = "ge"; break;
22214 case GT: case GTU: case UNGT:
22215 ccode = "gt"; break;
22217 ccode = "le"; break;
22218 case LT: case LTU: case UNLT:
22219 ccode = "lt"; break;
22220 case UNORDERED: ccode = "un"; break;
22221 case ORDERED: ccode = "nu"; break;
22222 case UNGE: ccode = "nl"; break;
22223 case UNLE: ccode = "ng"; break;
22225 gcc_unreachable ();
22228 /* Maybe we have a guess as to how likely the branch is. */
22230 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22231 if (note != NULL_RTX)
22233 /* PROB is the difference from 50%. */
22234 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22235 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22237 /* Only hint for highly probable/improbable branches on newer cpus when
22238 we have real profile data, as static prediction overrides processor
22239 dynamic prediction. For older cpus we may as well always hint, but
22240 assume not taken for branches that are very close to 50% as a
22241 mispredicted taken branch is more expensive than a
22242 mispredicted not-taken branch. */
22243 if (rs6000_always_hint
22244 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22245 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22246 && br_prob_note_reliable_p (note)))
22248 if (abs (prob) > REG_BR_PROB_BASE / 20
22249 && ((prob > 0) ^ need_longbranch))
22257 s += sprintf (s, "b%slr%s ", ccode, pred);
22259 s += sprintf (s, "b%s%s ", ccode, pred);
22261 /* We need to escape any '%' characters in the reg_names string.
22262 Assume they'd only be the first character.... */
22263 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22265 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22269 /* If the branch distance was too far, we may have to use an
22270 unconditional branch to go the distance. */
22271 if (need_longbranch)
22272 s += sprintf (s, ",$+8\n\tb %s", label);
22274 s += sprintf (s, ",%s", label);
22280 /* Return insn for VSX or Altivec comparisons. */
22283 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22286 machine_mode mode = GET_MODE (op0);
22294 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22305 mask = gen_reg_rtx (mode);
22306 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22313 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22314 DMODE is expected destination mode. This is a recursive function. */
22317 rs6000_emit_vector_compare (enum rtx_code rcode,
22319 machine_mode dmode)
22322 bool swap_operands = false;
22323 bool try_again = false;
22325 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22326 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22328 /* See if the comparison works as is. */
22329 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22337 swap_operands = true;
22342 swap_operands = true;
22350 /* Invert condition and try again.
22351 e.g., A != B becomes ~(A==B). */
22353 enum rtx_code rev_code;
22354 enum insn_code nor_code;
22357 rev_code = reverse_condition_maybe_unordered (rcode);
22358 if (rev_code == UNKNOWN)
22361 nor_code = optab_handler (one_cmpl_optab, dmode);
22362 if (nor_code == CODE_FOR_nothing)
22365 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22369 mask = gen_reg_rtx (dmode);
22370 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22378 /* Try GT/GTU/LT/LTU OR EQ */
22381 enum insn_code ior_code;
22382 enum rtx_code new_code;
22403 gcc_unreachable ();
22406 ior_code = optab_handler (ior_optab, dmode);
22407 if (ior_code == CODE_FOR_nothing)
22410 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22414 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22418 mask = gen_reg_rtx (dmode);
22419 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22430 std::swap (op0, op1);
22432 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22437 /* You only get two chances. */
22441 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22442 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22443 operands for the relation operation COND. */
22446 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22447 rtx cond, rtx cc_op0, rtx cc_op1)
22449 machine_mode dest_mode = GET_MODE (dest);
22450 machine_mode mask_mode = GET_MODE (cc_op0);
22451 enum rtx_code rcode = GET_CODE (cond);
22452 machine_mode cc_mode = CCmode;
22455 bool invert_move = false;
22457 if (VECTOR_UNIT_NONE_P (dest_mode))
22460 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22461 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22465 /* Swap operands if we can, and fall back to doing the operation as
22466 specified, and doing a NOR to invert the test. */
22472 /* Invert condition and try again.
22473 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22474 invert_move = true;
22475 rcode = reverse_condition_maybe_unordered (rcode);
22476 if (rcode == UNKNOWN)
22482 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22484 /* Invert condition to avoid compound test. */
22485 invert_move = true;
22486 rcode = reverse_condition (rcode);
22494 /* Mark unsigned tests with CCUNSmode. */
22495 cc_mode = CCUNSmode;
22497 /* Invert condition to avoid compound test if necessary. */
22498 if (rcode == GEU || rcode == LEU)
22500 invert_move = true;
22501 rcode = reverse_condition (rcode);
22509 /* Get the vector mask for the given relational operations. */
22510 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22516 std::swap (op_true, op_false);
22518 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22519 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22520 && (GET_CODE (op_true) == CONST_VECTOR
22521 || GET_CODE (op_false) == CONST_VECTOR))
22523 rtx constant_0 = CONST0_RTX (dest_mode);
22524 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22526 if (op_true == constant_m1 && op_false == constant_0)
22528 emit_move_insn (dest, mask);
22532 else if (op_true == constant_0 && op_false == constant_m1)
22534 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22538 /* If we can't use the vector comparison directly, perhaps we can use
22539 the mask for the true or false fields, instead of loading up a
22541 if (op_true == constant_m1)
22544 if (op_false == constant_0)
22548 if (!REG_P (op_true) && !SUBREG_P (op_true))
22549 op_true = force_reg (dest_mode, op_true);
22551 if (!REG_P (op_false) && !SUBREG_P (op_false))
22552 op_false = force_reg (dest_mode, op_false);
22554 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22555 CONST0_RTX (dest_mode));
22556 emit_insn (gen_rtx_SET (dest,
22557 gen_rtx_IF_THEN_ELSE (dest_mode,
22564 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22565 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22566 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22567 hardware has no such operation. */
22570 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22572 enum rtx_code code = GET_CODE (op);
22573 rtx op0 = XEXP (op, 0);
22574 rtx op1 = XEXP (op, 1);
22575 machine_mode compare_mode = GET_MODE (op0);
22576 machine_mode result_mode = GET_MODE (dest);
22577 bool max_p = false;
22579 if (result_mode != compare_mode)
22582 if (code == GE || code == GT)
22584 else if (code == LE || code == LT)
22589 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22592 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22598 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22602 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22603 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22604 operands of the last comparison is nonzero/true, FALSE_COND if it is
22605 zero/false. Return 0 if the hardware has no such operation. */
22608 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22610 enum rtx_code code = GET_CODE (op);
22611 rtx op0 = XEXP (op, 0);
22612 rtx op1 = XEXP (op, 1);
22613 machine_mode result_mode = GET_MODE (dest);
22618 if (!can_create_pseudo_p ())
22631 code = swap_condition (code);
22632 std::swap (op0, op1);
22639 /* Generate: [(parallel [(set (dest)
22640 (if_then_else (op (cmp1) (cmp2))
22643 (clobber (scratch))])]. */
22645 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22646 cmove_rtx = gen_rtx_SET (dest,
22647 gen_rtx_IF_THEN_ELSE (result_mode,
22652 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22653 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22654 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22659 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22660 operands of the last comparison is nonzero/true, FALSE_COND if it
22661 is zero/false. Return 0 if the hardware has no such operation. */
22664 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22666 enum rtx_code code = GET_CODE (op);
22667 rtx op0 = XEXP (op, 0);
22668 rtx op1 = XEXP (op, 1);
22669 machine_mode compare_mode = GET_MODE (op0);
22670 machine_mode result_mode = GET_MODE (dest);
22672 bool is_against_zero;
22674 /* These modes should always match. */
22675 if (GET_MODE (op1) != compare_mode
22676 /* In the isel case however, we can use a compare immediate, so
22677 op1 may be a small constant. */
22678 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22680 if (GET_MODE (true_cond) != result_mode)
22682 if (GET_MODE (false_cond) != result_mode)
22685 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22686 if (TARGET_P9_MINMAX
22687 && (compare_mode == SFmode || compare_mode == DFmode)
22688 && (result_mode == SFmode || result_mode == DFmode))
22690 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22693 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22697 /* Don't allow using floating point comparisons for integer results for
22699 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22702 /* First, work out if the hardware can do this at all, or
22703 if it's too slow.... */
22704 if (!FLOAT_MODE_P (compare_mode))
22707 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22711 is_against_zero = op1 == CONST0_RTX (compare_mode);
22713 /* A floating-point subtract might overflow, underflow, or produce
22714 an inexact result, thus changing the floating-point flags, so it
22715 can't be generated if we care about that. It's safe if one side
22716 of the construct is zero, since then no subtract will be
22718 if (SCALAR_FLOAT_MODE_P (compare_mode)
22719 && flag_trapping_math && ! is_against_zero)
22722 /* Eliminate half of the comparisons by switching operands, this
22723 makes the remaining code simpler. */
22724 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22725 || code == LTGT || code == LT || code == UNLE)
22727 code = reverse_condition_maybe_unordered (code);
22729 true_cond = false_cond;
22733 /* UNEQ and LTGT take four instructions for a comparison with zero,
22734 it'll probably be faster to use a branch here too. */
22735 if (code == UNEQ && HONOR_NANS (compare_mode))
22738 /* We're going to try to implement comparisons by performing
22739 a subtract, then comparing against zero. Unfortunately,
22740 Inf - Inf is NaN which is not zero, and so if we don't
22741 know that the operand is finite and the comparison
22742 would treat EQ different to UNORDERED, we can't do it. */
22743 if (HONOR_INFINITIES (compare_mode)
22744 && code != GT && code != UNGE
22745 && (!CONST_DOUBLE_P (op1)
22746 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22747 /* Constructs of the form (a OP b ? a : b) are safe. */
22748 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22749 || (! rtx_equal_p (op0, true_cond)
22750 && ! rtx_equal_p (op1, true_cond))))
22753 /* At this point we know we can use fsel. */
22755 /* Reduce the comparison to a comparison against zero. */
22756 if (! is_against_zero)
22758 temp = gen_reg_rtx (compare_mode);
22759 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22761 op1 = CONST0_RTX (compare_mode);
22764 /* If we don't care about NaNs we can reduce some of the comparisons
22765 down to faster ones. */
22766 if (! HONOR_NANS (compare_mode))
22772 true_cond = false_cond;
22785 /* Now, reduce everything down to a GE. */
22792 temp = gen_reg_rtx (compare_mode);
22793 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22798 temp = gen_reg_rtx (compare_mode);
22799 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22804 temp = gen_reg_rtx (compare_mode);
22805 emit_insn (gen_rtx_SET (temp,
22806 gen_rtx_NEG (compare_mode,
22807 gen_rtx_ABS (compare_mode, op0))));
22812 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22813 temp = gen_reg_rtx (result_mode);
22814 emit_insn (gen_rtx_SET (temp,
22815 gen_rtx_IF_THEN_ELSE (result_mode,
22816 gen_rtx_GE (VOIDmode,
22818 true_cond, false_cond)));
22819 false_cond = true_cond;
22822 temp = gen_reg_rtx (compare_mode);
22823 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22828 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22829 temp = gen_reg_rtx (result_mode);
22830 emit_insn (gen_rtx_SET (temp,
22831 gen_rtx_IF_THEN_ELSE (result_mode,
22832 gen_rtx_GE (VOIDmode,
22834 true_cond, false_cond)));
22835 true_cond = false_cond;
22838 temp = gen_reg_rtx (compare_mode);
22839 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22844 gcc_unreachable ();
22847 emit_insn (gen_rtx_SET (dest,
22848 gen_rtx_IF_THEN_ELSE (result_mode,
22849 gen_rtx_GE (VOIDmode,
22851 true_cond, false_cond)));
22855 /* Same as above, but for ints (isel). */
22858 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22860 rtx condition_rtx, cr;
22861 machine_mode mode = GET_MODE (dest);
22862 enum rtx_code cond_code;
22863 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22866 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22869 /* We still have to do the compare, because isel doesn't do a
22870 compare, it just looks at the CRx bits set by a previous compare
22872 condition_rtx = rs6000_generate_compare (op, mode);
22873 cond_code = GET_CODE (condition_rtx);
22874 cr = XEXP (condition_rtx, 0);
22875 signedp = GET_MODE (cr) == CCmode;
22877 isel_func = (mode == SImode
22878 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22879 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22883 case LT: case GT: case LTU: case GTU: case EQ:
22884 /* isel handles these directly. */
22888 /* We need to swap the sense of the comparison. */
22890 std::swap (false_cond, true_cond);
22891 PUT_CODE (condition_rtx, reverse_condition (cond_code));
22896 false_cond = force_reg (mode, false_cond);
22897 if (true_cond != const0_rtx)
22898 true_cond = force_reg (mode, true_cond);
22900 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
22906 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
22908 machine_mode mode = GET_MODE (op0);
22912 /* VSX/altivec have direct min/max insns. */
22913 if ((code == SMAX || code == SMIN)
22914 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
22915 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
22917 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
22921 if (code == SMAX || code == SMIN)
22926 if (code == SMAX || code == UMAX)
22927 target = emit_conditional_move (dest, c, op0, op1, mode,
22928 op0, op1, mode, 0);
22930 target = emit_conditional_move (dest, c, op0, op1, mode,
22931 op1, op0, mode, 0);
22932 gcc_assert (target);
22933 if (target != dest)
22934 emit_move_insn (dest, target);
22937 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22938 COND is true. Mark the jump as unlikely to be taken. */
22941 emit_unlikely_jump (rtx cond, rtx label)
22943 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
22944 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
22945 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
22948 /* A subroutine of the atomic operation splitters. Emit a load-locked
22949 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22950 the zero_extend operation. */
22953 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
22955 rtx (*fn) (rtx, rtx) = NULL;
22960 fn = gen_load_lockedqi;
22963 fn = gen_load_lockedhi;
22966 if (GET_MODE (mem) == QImode)
22967 fn = gen_load_lockedqi_si;
22968 else if (GET_MODE (mem) == HImode)
22969 fn = gen_load_lockedhi_si;
22971 fn = gen_load_lockedsi;
22974 fn = gen_load_lockeddi;
22977 fn = gen_load_lockedti;
22980 gcc_unreachable ();
22982 emit_insn (fn (reg, mem));
22985 /* A subroutine of the atomic operation splitters. Emit a store-conditional
22986 instruction in MODE. */
22989 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
22991 rtx (*fn) (rtx, rtx, rtx) = NULL;
22996 fn = gen_store_conditionalqi;
22999 fn = gen_store_conditionalhi;
23002 fn = gen_store_conditionalsi;
23005 fn = gen_store_conditionaldi;
23008 fn = gen_store_conditionalti;
23011 gcc_unreachable ();
23014 /* Emit sync before stwcx. to address PPC405 Erratum. */
23015 if (PPC405_ERRATUM77)
23016 emit_insn (gen_hwsync ());
23018 emit_insn (fn (res, mem, val));
23021 /* Expand barriers before and after a load_locked/store_cond sequence. */
23024 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23026 rtx addr = XEXP (mem, 0);
23028 if (!legitimate_indirect_address_p (addr, reload_completed)
23029 && !legitimate_indexed_address_p (addr, reload_completed))
23031 addr = force_reg (Pmode, addr);
23032 mem = replace_equiv_address_nv (mem, addr);
23037 case MEMMODEL_RELAXED:
23038 case MEMMODEL_CONSUME:
23039 case MEMMODEL_ACQUIRE:
23041 case MEMMODEL_RELEASE:
23042 case MEMMODEL_ACQ_REL:
23043 emit_insn (gen_lwsync ());
23045 case MEMMODEL_SEQ_CST:
23046 emit_insn (gen_hwsync ());
23049 gcc_unreachable ();
23055 rs6000_post_atomic_barrier (enum memmodel model)
23059 case MEMMODEL_RELAXED:
23060 case MEMMODEL_CONSUME:
23061 case MEMMODEL_RELEASE:
23063 case MEMMODEL_ACQUIRE:
23064 case MEMMODEL_ACQ_REL:
23065 case MEMMODEL_SEQ_CST:
23066 emit_insn (gen_isync ());
23069 gcc_unreachable ();
23073 /* A subroutine of the various atomic expanders. For sub-word operations,
23074 we must adjust things to operate on SImode. Given the original MEM,
23075 return a new aligned memory. Also build and return the quantities by
23076 which to shift and mask. */
23079 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23081 rtx addr, align, shift, mask, mem;
23082 HOST_WIDE_INT shift_mask;
23083 machine_mode mode = GET_MODE (orig_mem);
23085 /* For smaller modes, we have to implement this via SImode. */
23086 shift_mask = (mode == QImode ? 0x18 : 0x10);
23088 addr = XEXP (orig_mem, 0);
23089 addr = force_reg (GET_MODE (addr), addr);
23091 /* Aligned memory containing subword. Generate a new memory. We
23092 do not want any of the existing MEM_ATTR data, as we're now
23093 accessing memory outside the original object. */
23094 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23095 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23096 mem = gen_rtx_MEM (SImode, align);
23097 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23098 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23099 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23101 /* Shift amount for subword relative to aligned word. */
23102 shift = gen_reg_rtx (SImode);
23103 addr = gen_lowpart (SImode, addr);
23104 rtx tmp = gen_reg_rtx (SImode);
23105 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23106 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23107 if (BYTES_BIG_ENDIAN)
23108 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23109 shift, 1, OPTAB_LIB_WIDEN);
23112 /* Mask for insertion. */
23113 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23114 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23120 /* A subroutine of the various atomic expanders. For sub-word operands,
23121 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23124 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23128 x = gen_reg_rtx (SImode);
23129 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23130 gen_rtx_NOT (SImode, mask),
23133 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23138 /* A subroutine of the various atomic expanders. For sub-word operands,
23139 extract WIDE to NARROW via SHIFT. */
23142 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23144 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23145 wide, 1, OPTAB_LIB_WIDEN);
23146 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23149 /* Expand an atomic compare and swap operation. */
23152 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23154 rtx boolval, retval, mem, oldval, newval, cond;
23155 rtx label1, label2, x, mask, shift;
23156 machine_mode mode, orig_mode;
23157 enum memmodel mod_s, mod_f;
23160 boolval = operands[0];
23161 retval = operands[1];
23163 oldval = operands[3];
23164 newval = operands[4];
23165 is_weak = (INTVAL (operands[5]) != 0);
23166 mod_s = memmodel_base (INTVAL (operands[6]));
23167 mod_f = memmodel_base (INTVAL (operands[7]));
23168 orig_mode = mode = GET_MODE (mem);
23170 mask = shift = NULL_RTX;
23171 if (mode == QImode || mode == HImode)
23173 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23174 lwarx and shift/mask operations. With power8, we need to do the
23175 comparison in SImode, but the store is still done in QI/HImode. */
23176 oldval = convert_modes (SImode, mode, oldval, 1);
23178 if (!TARGET_SYNC_HI_QI)
23180 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23182 /* Shift and mask OLDVAL into position with the word. */
23183 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23184 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23186 /* Shift and mask NEWVAL into position within the word. */
23187 newval = convert_modes (SImode, mode, newval, 1);
23188 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23189 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23192 /* Prepare to adjust the return value. */
23193 retval = gen_reg_rtx (SImode);
23196 else if (reg_overlap_mentioned_p (retval, oldval))
23197 oldval = copy_to_reg (oldval);
23199 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23200 oldval = copy_to_mode_reg (mode, oldval);
23202 if (reg_overlap_mentioned_p (retval, newval))
23203 newval = copy_to_reg (newval);
23205 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23210 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23211 emit_label (XEXP (label1, 0));
23213 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23215 emit_load_locked (mode, retval, mem);
23219 x = expand_simple_binop (SImode, AND, retval, mask,
23220 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23222 cond = gen_reg_rtx (CCmode);
23223 /* If we have TImode, synthesize a comparison. */
23224 if (mode != TImode)
23225 x = gen_rtx_COMPARE (CCmode, x, oldval);
23228 rtx xor1_result = gen_reg_rtx (DImode);
23229 rtx xor2_result = gen_reg_rtx (DImode);
23230 rtx or_result = gen_reg_rtx (DImode);
23231 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23232 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23233 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23234 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23236 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23237 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23238 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23239 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23242 emit_insn (gen_rtx_SET (cond, x));
23244 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23245 emit_unlikely_jump (x, label2);
23249 x = rs6000_mask_atomic_subword (retval, newval, mask);
23251 emit_store_conditional (orig_mode, cond, mem, x);
23255 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23256 emit_unlikely_jump (x, label1);
23259 if (!is_mm_relaxed (mod_f))
23260 emit_label (XEXP (label2, 0));
23262 rs6000_post_atomic_barrier (mod_s);
23264 if (is_mm_relaxed (mod_f))
23265 emit_label (XEXP (label2, 0));
23268 rs6000_finish_atomic_subword (operands[1], retval, shift);
23269 else if (mode != GET_MODE (operands[1]))
23270 convert_move (operands[1], retval, 1);
23272 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23273 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23274 emit_insn (gen_rtx_SET (boolval, x));
23277 /* Expand an atomic exchange operation. */
23280 rs6000_expand_atomic_exchange (rtx operands[])
23282 rtx retval, mem, val, cond;
23284 enum memmodel model;
23285 rtx label, x, mask, shift;
23287 retval = operands[0];
23290 model = memmodel_base (INTVAL (operands[3]));
23291 mode = GET_MODE (mem);
23293 mask = shift = NULL_RTX;
23294 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23296 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23298 /* Shift and mask VAL into position with the word. */
23299 val = convert_modes (SImode, mode, val, 1);
23300 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23301 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23303 /* Prepare to adjust the return value. */
23304 retval = gen_reg_rtx (SImode);
23308 mem = rs6000_pre_atomic_barrier (mem, model);
23310 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23311 emit_label (XEXP (label, 0));
23313 emit_load_locked (mode, retval, mem);
23317 x = rs6000_mask_atomic_subword (retval, val, mask);
23319 cond = gen_reg_rtx (CCmode);
23320 emit_store_conditional (mode, cond, mem, x);
23322 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23323 emit_unlikely_jump (x, label);
23325 rs6000_post_atomic_barrier (model);
23328 rs6000_finish_atomic_subword (operands[0], retval, shift);
23331 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23332 to perform. MEM is the memory on which to operate. VAL is the second
23333 operand of the binary operator. BEFORE and AFTER are optional locations to
23334 return the value of MEM either before of after the operation. MODEL_RTX
23335 is a CONST_INT containing the memory model to use. */
23338 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23339 rtx orig_before, rtx orig_after, rtx model_rtx)
23341 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23342 machine_mode mode = GET_MODE (mem);
23343 machine_mode store_mode = mode;
23344 rtx label, x, cond, mask, shift;
23345 rtx before = orig_before, after = orig_after;
23347 mask = shift = NULL_RTX;
23348 /* On power8, we want to use SImode for the operation. On previous systems,
23349 use the operation in a subword and shift/mask to get the proper byte or
23351 if (mode == QImode || mode == HImode)
23353 if (TARGET_SYNC_HI_QI)
23355 val = convert_modes (SImode, mode, val, 1);
23357 /* Prepare to adjust the return value. */
23358 before = gen_reg_rtx (SImode);
23360 after = gen_reg_rtx (SImode);
23365 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23367 /* Shift and mask VAL into position with the word. */
23368 val = convert_modes (SImode, mode, val, 1);
23369 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23370 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23376 /* We've already zero-extended VAL. That is sufficient to
23377 make certain that it does not affect other bits. */
23382 /* If we make certain that all of the other bits in VAL are
23383 set, that will be sufficient to not affect other bits. */
23384 x = gen_rtx_NOT (SImode, mask);
23385 x = gen_rtx_IOR (SImode, x, val);
23386 emit_insn (gen_rtx_SET (val, x));
23393 /* These will all affect bits outside the field and need
23394 adjustment via MASK within the loop. */
23398 gcc_unreachable ();
23401 /* Prepare to adjust the return value. */
23402 before = gen_reg_rtx (SImode);
23404 after = gen_reg_rtx (SImode);
23405 store_mode = mode = SImode;
23409 mem = rs6000_pre_atomic_barrier (mem, model);
23411 label = gen_label_rtx ();
23412 emit_label (label);
23413 label = gen_rtx_LABEL_REF (VOIDmode, label);
23415 if (before == NULL_RTX)
23416 before = gen_reg_rtx (mode);
23418 emit_load_locked (mode, before, mem);
23422 x = expand_simple_binop (mode, AND, before, val,
23423 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23424 after = expand_simple_unop (mode, NOT, x, after, 1);
23428 after = expand_simple_binop (mode, code, before, val,
23429 after, 1, OPTAB_LIB_WIDEN);
23435 x = expand_simple_binop (SImode, AND, after, mask,
23436 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23437 x = rs6000_mask_atomic_subword (before, x, mask);
23439 else if (store_mode != mode)
23440 x = convert_modes (store_mode, mode, x, 1);
23442 cond = gen_reg_rtx (CCmode);
23443 emit_store_conditional (store_mode, cond, mem, x);
23445 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23446 emit_unlikely_jump (x, label);
23448 rs6000_post_atomic_barrier (model);
23452 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23453 then do the calcuations in a SImode register. */
23455 rs6000_finish_atomic_subword (orig_before, before, shift);
23457 rs6000_finish_atomic_subword (orig_after, after, shift);
23459 else if (store_mode != mode)
23461 /* QImode/HImode on machines with lbarx/lharx where we do the native
23462 operation and then do the calcuations in a SImode register. */
23464 convert_move (orig_before, before, 1);
23466 convert_move (orig_after, after, 1);
23468 else if (orig_after && after != orig_after)
23469 emit_move_insn (orig_after, after);
23472 /* Emit instructions to move SRC to DST. Called by splitters for
23473 multi-register moves. It will emit at most one instruction for
23474 each register that is accessed; that is, it won't emit li/lis pairs
23475 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23479 rs6000_split_multireg_move (rtx dst, rtx src)
23481 /* The register number of the first register being moved. */
23483 /* The mode that is to be moved. */
23485 /* The mode that the move is being done in, and its size. */
23486 machine_mode reg_mode;
23488 /* The number of registers that will be moved. */
23491 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23492 mode = GET_MODE (dst);
23493 nregs = hard_regno_nregs (reg, mode);
23494 if (FP_REGNO_P (reg))
23495 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23496 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23497 else if (ALTIVEC_REGNO_P (reg))
23498 reg_mode = V16QImode;
23500 reg_mode = word_mode;
23501 reg_mode_size = GET_MODE_SIZE (reg_mode);
23503 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23505 /* TDmode residing in FP registers is special, since the ISA requires that
23506 the lower-numbered word of a register pair is always the most significant
23507 word, even in little-endian mode. This does not match the usual subreg
23508 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23509 the appropriate constituent registers "by hand" in little-endian mode.
23511 Note we do not need to check for destructive overlap here since TDmode
23512 can only reside in even/odd register pairs. */
23513 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23518 for (i = 0; i < nregs; i++)
23520 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23521 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23523 p_src = simplify_gen_subreg (reg_mode, src, mode,
23524 i * reg_mode_size);
23526 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23527 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23529 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23530 i * reg_mode_size);
23532 emit_insn (gen_rtx_SET (p_dst, p_src));
23538 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23540 /* Move register range backwards, if we might have destructive
23543 for (i = nregs - 1; i >= 0; i--)
23544 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23545 i * reg_mode_size),
23546 simplify_gen_subreg (reg_mode, src, mode,
23547 i * reg_mode_size)));
23553 bool used_update = false;
23554 rtx restore_basereg = NULL_RTX;
23556 if (MEM_P (src) && INT_REGNO_P (reg))
23560 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23561 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23564 breg = XEXP (XEXP (src, 0), 0);
23565 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23566 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23567 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23568 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23569 src = replace_equiv_address (src, breg);
23571 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23573 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23575 rtx basereg = XEXP (XEXP (src, 0), 0);
23578 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23579 emit_insn (gen_rtx_SET (ndst,
23580 gen_rtx_MEM (reg_mode,
23582 used_update = true;
23585 emit_insn (gen_rtx_SET (basereg,
23586 XEXP (XEXP (src, 0), 1)));
23587 src = replace_equiv_address (src, basereg);
23591 rtx basereg = gen_rtx_REG (Pmode, reg);
23592 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23593 src = replace_equiv_address (src, basereg);
23597 breg = XEXP (src, 0);
23598 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23599 breg = XEXP (breg, 0);
23601 /* If the base register we are using to address memory is
23602 also a destination reg, then change that register last. */
23604 && REGNO (breg) >= REGNO (dst)
23605 && REGNO (breg) < REGNO (dst) + nregs)
23606 j = REGNO (breg) - REGNO (dst);
23608 else if (MEM_P (dst) && INT_REGNO_P (reg))
23612 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23613 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23616 breg = XEXP (XEXP (dst, 0), 0);
23617 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23618 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23619 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23621 /* We have to update the breg before doing the store.
23622 Use store with update, if available. */
23626 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23627 emit_insn (TARGET_32BIT
23628 ? (TARGET_POWERPC64
23629 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23630 : gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
23631 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23632 used_update = true;
23635 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23636 dst = replace_equiv_address (dst, breg);
23638 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23639 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23641 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23643 rtx basereg = XEXP (XEXP (dst, 0), 0);
23646 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23647 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23650 used_update = true;
23653 emit_insn (gen_rtx_SET (basereg,
23654 XEXP (XEXP (dst, 0), 1)));
23655 dst = replace_equiv_address (dst, basereg);
23659 rtx basereg = XEXP (XEXP (dst, 0), 0);
23660 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23661 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23663 && REG_P (offsetreg)
23664 && REGNO (basereg) != REGNO (offsetreg));
23665 if (REGNO (basereg) == 0)
23667 rtx tmp = offsetreg;
23668 offsetreg = basereg;
23671 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23672 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23673 dst = replace_equiv_address (dst, basereg);
23676 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23677 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23680 for (i = 0; i < nregs; i++)
23682 /* Calculate index to next subword. */
23687 /* If compiler already emitted move of first word by
23688 store with update, no need to do anything. */
23689 if (j == 0 && used_update)
23692 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23693 j * reg_mode_size),
23694 simplify_gen_subreg (reg_mode, src, mode,
23695 j * reg_mode_size)));
23697 if (restore_basereg != NULL_RTX)
23698 emit_insn (restore_basereg);
23703 /* This page contains routines that are used to determine what the
23704 function prologue and epilogue code will do and write them out. */
23706 /* Determine whether the REG is really used. */
23709 save_reg_p (int reg)
23711 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23713 /* When calling eh_return, we must return true for all the cases
23714 where conditional_register_usage marks the PIC offset reg
23715 call used or fixed. */
23716 if (crtl->calls_eh_return
23717 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23718 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23719 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23722 /* We need to mark the PIC offset register live for the same
23723 conditions as it is set up in rs6000_emit_prologue, or
23724 otherwise it won't be saved before we clobber it. */
23725 if (TARGET_TOC && TARGET_MINIMAL_TOC
23726 && !constant_pool_empty_p ())
23729 if (DEFAULT_ABI == ABI_V4
23730 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
23731 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
23734 if (DEFAULT_ABI == ABI_DARWIN
23735 && flag_pic && crtl->uses_pic_offset_table)
23739 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23742 /* Return the first fixed-point register that is required to be
23743 saved. 32 if none. */
23746 first_reg_to_save (void)
23750 /* Find lowest numbered live register. */
23751 for (first_reg = 13; first_reg <= 31; first_reg++)
23752 if (save_reg_p (first_reg))
23758 /* Similar, for FP regs. */
23761 first_fp_reg_to_save (void)
23765 /* Find lowest numbered live register. */
23766 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23767 if (save_reg_p (first_reg))
23773 /* Similar, for AltiVec regs. */
23776 first_altivec_reg_to_save (void)
23780 /* Stack frame remains as is unless we are in AltiVec ABI. */
23781 if (! TARGET_ALTIVEC_ABI)
23782 return LAST_ALTIVEC_REGNO + 1;
23784 /* On Darwin, the unwind routines are compiled without
23785 TARGET_ALTIVEC, and use save_world to save/restore the
23786 altivec registers when necessary. */
23787 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23788 && ! TARGET_ALTIVEC)
23789 return FIRST_ALTIVEC_REGNO + 20;
23791 /* Find lowest numbered live register. */
23792 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23793 if (save_reg_p (i))
23799 /* Return a 32-bit mask of the AltiVec registers we need to set in
23800 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23801 the 32-bit word is 0. */
23803 static unsigned int
23804 compute_vrsave_mask (void)
23806 unsigned int i, mask = 0;
23808 /* On Darwin, the unwind routines are compiled without
23809 TARGET_ALTIVEC, and use save_world to save/restore the
23810 call-saved altivec registers when necessary. */
23811 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23812 && ! TARGET_ALTIVEC)
23815 /* First, find out if we use _any_ altivec registers. */
23816 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23817 if (df_regs_ever_live_p (i))
23818 mask |= ALTIVEC_REG_BIT (i);
23823 /* Next, remove the argument registers from the set. These must
23824 be in the VRSAVE mask set by the caller, so we don't need to add
23825 them in again. More importantly, the mask we compute here is
23826 used to generate CLOBBERs in the set_vrsave insn, and we do not
23827 wish the argument registers to die. */
23828 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23829 mask &= ~ALTIVEC_REG_BIT (i);
23831 /* Similarly, remove the return value from the set. */
23834 diddle_return_value (is_altivec_return_reg, &yes);
23836 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23842 /* For a very restricted set of circumstances, we can cut down the
23843 size of prologues/epilogues by calling our own save/restore-the-world
23847 compute_save_world_info (rs6000_stack_t *info)
23849 info->world_save_p = 1;
23851 = (WORLD_SAVE_P (info)
23852 && DEFAULT_ABI == ABI_DARWIN
23853 && !cfun->has_nonlocal_label
23854 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23855 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23856 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23857 && info->cr_save_p);
23859 /* This will not work in conjunction with sibcalls. Make sure there
23860 are none. (This check is expensive, but seldom executed.) */
23861 if (WORLD_SAVE_P (info))
23864 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23865 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23867 info->world_save_p = 0;
23872 if (WORLD_SAVE_P (info))
23874 /* Even if we're not touching VRsave, make sure there's room on the
23875 stack for it, if it looks like we're calling SAVE_WORLD, which
23876 will attempt to save it. */
23877 info->vrsave_size = 4;
23879 /* If we are going to save the world, we need to save the link register too. */
23880 info->lr_save_p = 1;
23882 /* "Save" the VRsave register too if we're saving the world. */
23883 if (info->vrsave_mask == 0)
23884 info->vrsave_mask = compute_vrsave_mask ();
23886 /* Because the Darwin register save/restore routines only handle
23887 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23889 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23890 && (info->first_altivec_reg_save
23891 >= FIRST_SAVED_ALTIVEC_REGNO));
23899 is_altivec_return_reg (rtx reg, void *xyes)
23901 bool *yes = (bool *) xyes;
23902 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
23907 /* Return whether REG is a global user reg or has been specifed by
23908 -ffixed-REG. We should not restore these, and so cannot use
23909 lmw or out-of-line restore functions if there are any. We also
23910 can't save them (well, emit frame notes for them), because frame
23911 unwinding during exception handling will restore saved registers. */
23914 fixed_reg_p (int reg)
23916 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23917 backend sets it, overriding anything the user might have given. */
23918 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23919 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23920 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23921 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23924 return fixed_regs[reg];
23927 /* Determine the strategy for savings/restoring registers. */
23930 SAVE_MULTIPLE = 0x1,
23931 SAVE_INLINE_GPRS = 0x2,
23932 SAVE_INLINE_FPRS = 0x4,
23933 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
23934 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
23935 SAVE_INLINE_VRS = 0x20,
23936 REST_MULTIPLE = 0x100,
23937 REST_INLINE_GPRS = 0x200,
23938 REST_INLINE_FPRS = 0x400,
23939 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
23940 REST_INLINE_VRS = 0x1000
23944 rs6000_savres_strategy (rs6000_stack_t *info,
23945 bool using_static_chain_p)
23949 /* Select between in-line and out-of-line save and restore of regs.
23950 First, all the obvious cases where we don't use out-of-line. */
23951 if (crtl->calls_eh_return
23952 || cfun->machine->ra_need_lr)
23953 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
23954 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
23955 | SAVE_INLINE_VRS | REST_INLINE_VRS);
23957 if (info->first_gp_reg_save == 32)
23958 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23960 if (info->first_fp_reg_save == 64)
23961 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23963 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
23964 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23966 /* Define cutoff for using out-of-line functions to save registers. */
23967 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
23969 if (!optimize_size)
23971 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23972 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23973 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23977 /* Prefer out-of-line restore if it will exit. */
23978 if (info->first_fp_reg_save > 61)
23979 strategy |= SAVE_INLINE_FPRS;
23980 if (info->first_gp_reg_save > 29)
23982 if (info->first_fp_reg_save == 64)
23983 strategy |= SAVE_INLINE_GPRS;
23985 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23987 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
23988 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23991 else if (DEFAULT_ABI == ABI_DARWIN)
23993 if (info->first_fp_reg_save > 60)
23994 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23995 if (info->first_gp_reg_save > 29)
23996 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23997 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24001 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24002 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24003 || info->first_fp_reg_save > 61)
24004 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24005 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24006 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24009 /* Don't bother to try to save things out-of-line if r11 is occupied
24010 by the static chain. It would require too much fiddling and the
24011 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24012 pointer on Darwin, and AIX uses r1 or r12. */
24013 if (using_static_chain_p
24014 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24015 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24017 | SAVE_INLINE_VRS);
24019 /* Don't ever restore fixed regs. That means we can't use the
24020 out-of-line register restore functions if a fixed reg is in the
24021 range of regs restored. */
24022 if (!(strategy & REST_INLINE_FPRS))
24023 for (int i = info->first_fp_reg_save; i < 64; i++)
24026 strategy |= REST_INLINE_FPRS;
24030 /* We can only use the out-of-line routines to restore fprs if we've
24031 saved all the registers from first_fp_reg_save in the prologue.
24032 Otherwise, we risk loading garbage. Of course, if we have saved
24033 out-of-line then we know we haven't skipped any fprs. */
24034 if ((strategy & SAVE_INLINE_FPRS)
24035 && !(strategy & REST_INLINE_FPRS))
24036 for (int i = info->first_fp_reg_save; i < 64; i++)
24037 if (!save_reg_p (i))
24039 strategy |= REST_INLINE_FPRS;
24043 /* Similarly, for altivec regs. */
24044 if (!(strategy & REST_INLINE_VRS))
24045 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24048 strategy |= REST_INLINE_VRS;
24052 if ((strategy & SAVE_INLINE_VRS)
24053 && !(strategy & REST_INLINE_VRS))
24054 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24055 if (!save_reg_p (i))
24057 strategy |= REST_INLINE_VRS;
24061 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24062 saved is an out-of-line save or restore. Set up the value for
24063 the next test (excluding out-of-line gprs). */
24064 bool lr_save_p = (info->lr_save_p
24065 || !(strategy & SAVE_INLINE_FPRS)
24066 || !(strategy & SAVE_INLINE_VRS)
24067 || !(strategy & REST_INLINE_FPRS)
24068 || !(strategy & REST_INLINE_VRS));
24070 if (TARGET_MULTIPLE
24071 && !TARGET_POWERPC64
24072 && info->first_gp_reg_save < 31
24073 && !(flag_shrink_wrap
24074 && flag_shrink_wrap_separate
24075 && optimize_function_for_speed_p (cfun)))
24078 for (int i = info->first_gp_reg_save; i < 32; i++)
24079 if (save_reg_p (i))
24083 /* Don't use store multiple if only one reg needs to be
24084 saved. This can occur for example when the ABI_V4 pic reg
24085 (r30) needs to be saved to make calls, but r31 is not
24087 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24090 /* Prefer store multiple for saves over out-of-line
24091 routines, since the store-multiple instruction will
24092 always be smaller. */
24093 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24095 /* The situation is more complicated with load multiple.
24096 We'd prefer to use the out-of-line routines for restores,
24097 since the "exit" out-of-line routines can handle the
24098 restore of LR and the frame teardown. However if doesn't
24099 make sense to use the out-of-line routine if that is the
24100 only reason we'd need to save LR, and we can't use the
24101 "exit" out-of-line gpr restore if we have saved some
24102 fprs; In those cases it is advantageous to use load
24103 multiple when available. */
24104 if (info->first_fp_reg_save != 64 || !lr_save_p)
24105 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24109 /* Using the "exit" out-of-line routine does not improve code size
24110 if using it would require lr to be saved and if only saving one
24112 else if (!lr_save_p && info->first_gp_reg_save > 29)
24113 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24115 /* Don't ever restore fixed regs. */
24116 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24117 for (int i = info->first_gp_reg_save; i < 32; i++)
24118 if (fixed_reg_p (i))
24120 strategy |= REST_INLINE_GPRS;
24121 strategy &= ~REST_MULTIPLE;
24125 /* We can only use load multiple or the out-of-line routines to
24126 restore gprs if we've saved all the registers from
24127 first_gp_reg_save. Otherwise, we risk loading garbage.
24128 Of course, if we have saved out-of-line or used stmw then we know
24129 we haven't skipped any gprs. */
24130 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24131 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24132 for (int i = info->first_gp_reg_save; i < 32; i++)
24133 if (!save_reg_p (i))
24135 strategy |= REST_INLINE_GPRS;
24136 strategy &= ~REST_MULTIPLE;
24140 if (TARGET_ELF && TARGET_64BIT)
24142 if (!(strategy & SAVE_INLINE_FPRS))
24143 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24144 else if (!(strategy & SAVE_INLINE_GPRS)
24145 && info->first_fp_reg_save == 64)
24146 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24148 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24149 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24151 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24152 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24157 /* Calculate the stack information for the current function. This is
24158 complicated by having two separate calling sequences, the AIX calling
24159 sequence and the V.4 calling sequence.
24161 AIX (and Darwin/Mac OS X) stack frames look like:
24163 SP----> +---------------------------------------+
24164 | back chain to caller | 0 0
24165 +---------------------------------------+
24166 | saved CR | 4 8 (8-11)
24167 +---------------------------------------+
24169 +---------------------------------------+
24170 | reserved for compilers | 12 24
24171 +---------------------------------------+
24172 | reserved for binders | 16 32
24173 +---------------------------------------+
24174 | saved TOC pointer | 20 40
24175 +---------------------------------------+
24176 | Parameter save area (+padding*) (P) | 24 48
24177 +---------------------------------------+
24178 | Alloca space (A) | 24+P etc.
24179 +---------------------------------------+
24180 | Local variable space (L) | 24+P+A
24181 +---------------------------------------+
24182 | Float/int conversion temporary (X) | 24+P+A+L
24183 +---------------------------------------+
24184 | Save area for AltiVec registers (W) | 24+P+A+L+X
24185 +---------------------------------------+
24186 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24187 +---------------------------------------+
24188 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24189 +---------------------------------------+
24190 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24191 +---------------------------------------+
24192 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24193 +---------------------------------------+
24194 old SP->| back chain to caller's caller |
24195 +---------------------------------------+
24197 * If the alloca area is present, the parameter save area is
24198 padded so that the former starts 16-byte aligned.
24200 The required alignment for AIX configurations is two words (i.e., 8
24203 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24205 SP----> +---------------------------------------+
24206 | Back chain to caller | 0
24207 +---------------------------------------+
24208 | Save area for CR | 8
24209 +---------------------------------------+
24211 +---------------------------------------+
24212 | Saved TOC pointer | 24
24213 +---------------------------------------+
24214 | Parameter save area (+padding*) (P) | 32
24215 +---------------------------------------+
24216 | Alloca space (A) | 32+P
24217 +---------------------------------------+
24218 | Local variable space (L) | 32+P+A
24219 +---------------------------------------+
24220 | Save area for AltiVec registers (W) | 32+P+A+L
24221 +---------------------------------------+
24222 | AltiVec alignment padding (Y) | 32+P+A+L+W
24223 +---------------------------------------+
24224 | Save area for GP registers (G) | 32+P+A+L+W+Y
24225 +---------------------------------------+
24226 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24227 +---------------------------------------+
24228 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24229 +---------------------------------------+
24231 * If the alloca area is present, the parameter save area is
24232 padded so that the former starts 16-byte aligned.
24234 V.4 stack frames look like:
24236 SP----> +---------------------------------------+
24237 | back chain to caller | 0
24238 +---------------------------------------+
24239 | caller's saved LR | 4
24240 +---------------------------------------+
24241 | Parameter save area (+padding*) (P) | 8
24242 +---------------------------------------+
24243 | Alloca space (A) | 8+P
24244 +---------------------------------------+
24245 | Varargs save area (V) | 8+P+A
24246 +---------------------------------------+
24247 | Local variable space (L) | 8+P+A+V
24248 +---------------------------------------+
24249 | Float/int conversion temporary (X) | 8+P+A+V+L
24250 +---------------------------------------+
24251 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24252 +---------------------------------------+
24253 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24254 +---------------------------------------+
24255 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24256 +---------------------------------------+
24257 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24258 +---------------------------------------+
24259 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24260 +---------------------------------------+
24261 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24262 +---------------------------------------+
24263 old SP->| back chain to caller's caller |
24264 +---------------------------------------+
24266 * If the alloca area is present and the required alignment is
24267 16 bytes, the parameter save area is padded so that the
24268 alloca area starts 16-byte aligned.
24270 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24271 given. (But note below and in sysv4.h that we require only 8 and
24272 may round up the size of our stack frame anyways. The historical
24273 reason is early versions of powerpc-linux which didn't properly
24274 align the stack at program startup. A happy side-effect is that
24275 -mno-eabi libraries can be used with -meabi programs.)
24277 The EABI configuration defaults to the V.4 layout. However,
24278 the stack alignment requirements may differ. If -mno-eabi is not
24279 given, the required stack alignment is 8 bytes; if -mno-eabi is
24280 given, the required alignment is 16 bytes. (But see V.4 comment
24283 #ifndef ABI_STACK_BOUNDARY
24284 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24287 static rs6000_stack_t *
24288 rs6000_stack_info (void)
24290 /* We should never be called for thunks, we are not set up for that. */
24291 gcc_assert (!cfun->is_thunk);
24293 rs6000_stack_t *info = &stack_info;
24294 int reg_size = TARGET_32BIT ? 4 : 8;
24299 HOST_WIDE_INT non_fixed_size;
24300 bool using_static_chain_p;
24302 if (reload_completed && info->reload_completed)
24305 memset (info, 0, sizeof (*info));
24306 info->reload_completed = reload_completed;
24308 /* Select which calling sequence. */
24309 info->abi = DEFAULT_ABI;
24311 /* Calculate which registers need to be saved & save area size. */
24312 info->first_gp_reg_save = first_reg_to_save ();
24313 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24314 even if it currently looks like we won't. Reload may need it to
24315 get at a constant; if so, it will have already created a constant
24316 pool entry for it. */
24317 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24318 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24319 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24320 && crtl->uses_const_pool
24321 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24322 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24324 first_gp = info->first_gp_reg_save;
24326 info->gp_size = reg_size * (32 - first_gp);
24328 info->first_fp_reg_save = first_fp_reg_to_save ();
24329 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24331 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24332 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24333 - info->first_altivec_reg_save);
24335 /* Does this function call anything? */
24336 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24338 /* Determine if we need to save the condition code registers. */
24339 if (save_reg_p (CR2_REGNO)
24340 || save_reg_p (CR3_REGNO)
24341 || save_reg_p (CR4_REGNO))
24343 info->cr_save_p = 1;
24344 if (DEFAULT_ABI == ABI_V4)
24345 info->cr_size = reg_size;
24348 /* If the current function calls __builtin_eh_return, then we need
24349 to allocate stack space for registers that will hold data for
24350 the exception handler. */
24351 if (crtl->calls_eh_return)
24354 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24357 ehrd_size = i * UNITS_PER_WORD;
24362 /* In the ELFv2 ABI, we also need to allocate space for separate
24363 CR field save areas if the function calls __builtin_eh_return. */
24364 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24366 /* This hard-codes that we have three call-saved CR fields. */
24367 ehcr_size = 3 * reg_size;
24368 /* We do *not* use the regular CR save mechanism. */
24369 info->cr_save_p = 0;
24374 /* Determine various sizes. */
24375 info->reg_size = reg_size;
24376 info->fixed_size = RS6000_SAVE_AREA;
24377 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24378 if (cfun->calls_alloca)
24380 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24381 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24383 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24384 TARGET_ALTIVEC ? 16 : 8);
24385 if (FRAME_GROWS_DOWNWARD)
24387 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24388 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24389 - (info->fixed_size + info->vars_size + info->parm_size);
24391 if (TARGET_ALTIVEC_ABI)
24392 info->vrsave_mask = compute_vrsave_mask ();
24394 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24395 info->vrsave_size = 4;
24397 compute_save_world_info (info);
24399 /* Calculate the offsets. */
24400 switch (DEFAULT_ABI)
24404 gcc_unreachable ();
24409 info->fp_save_offset = -info->fp_size;
24410 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24412 if (TARGET_ALTIVEC_ABI)
24414 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24416 /* Align stack so vector save area is on a quadword boundary.
24417 The padding goes above the vectors. */
24418 if (info->altivec_size != 0)
24419 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24421 info->altivec_save_offset = info->vrsave_save_offset
24422 - info->altivec_padding_size
24423 - info->altivec_size;
24424 gcc_assert (info->altivec_size == 0
24425 || info->altivec_save_offset % 16 == 0);
24427 /* Adjust for AltiVec case. */
24428 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24431 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24433 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24434 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24435 info->lr_save_offset = 2*reg_size;
24439 info->fp_save_offset = -info->fp_size;
24440 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24441 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24443 if (TARGET_ALTIVEC_ABI)
24445 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24447 /* Align stack so vector save area is on a quadword boundary. */
24448 if (info->altivec_size != 0)
24449 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24451 info->altivec_save_offset = info->vrsave_save_offset
24452 - info->altivec_padding_size
24453 - info->altivec_size;
24455 /* Adjust for AltiVec case. */
24456 info->ehrd_offset = info->altivec_save_offset;
24459 info->ehrd_offset = info->cr_save_offset;
24461 info->ehrd_offset -= ehrd_size;
24462 info->lr_save_offset = reg_size;
24465 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24466 info->save_size = RS6000_ALIGN (info->fp_size
24468 + info->altivec_size
24469 + info->altivec_padding_size
24473 + info->vrsave_size,
24476 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24478 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24479 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24481 /* Determine if we need to save the link register. */
24483 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24485 && !TARGET_PROFILE_KERNEL)
24486 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24487 #ifdef TARGET_RELOCATABLE
24488 || (DEFAULT_ABI == ABI_V4
24489 && (TARGET_RELOCATABLE || flag_pic > 1)
24490 && !constant_pool_empty_p ())
24492 || rs6000_ra_ever_killed ())
24493 info->lr_save_p = 1;
24495 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24496 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24497 && call_used_regs[STATIC_CHAIN_REGNUM]);
24498 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24500 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24501 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24502 || !(info->savres_strategy & SAVE_INLINE_VRS)
24503 || !(info->savres_strategy & REST_INLINE_GPRS)
24504 || !(info->savres_strategy & REST_INLINE_FPRS)
24505 || !(info->savres_strategy & REST_INLINE_VRS))
24506 info->lr_save_p = 1;
24508 if (info->lr_save_p)
24509 df_set_regs_ever_live (LR_REGNO, true);
24511 /* Determine if we need to allocate any stack frame:
24513 For AIX we need to push the stack if a frame pointer is needed
24514 (because the stack might be dynamically adjusted), if we are
24515 debugging, if we make calls, or if the sum of fp_save, gp_save,
24516 and local variables are more than the space needed to save all
24517 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24518 + 18*8 = 288 (GPR13 reserved).
24520 For V.4 we don't have the stack cushion that AIX uses, but assume
24521 that the debugger can handle stackless frames. */
24526 else if (DEFAULT_ABI == ABI_V4)
24527 info->push_p = non_fixed_size != 0;
24529 else if (frame_pointer_needed)
24532 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24536 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24542 debug_stack_info (rs6000_stack_t *info)
24544 const char *abi_string;
24547 info = rs6000_stack_info ();
24549 fprintf (stderr, "\nStack information for function %s:\n",
24550 ((current_function_decl && DECL_NAME (current_function_decl))
24551 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24556 default: abi_string = "Unknown"; break;
24557 case ABI_NONE: abi_string = "NONE"; break;
24558 case ABI_AIX: abi_string = "AIX"; break;
24559 case ABI_ELFv2: abi_string = "ELFv2"; break;
24560 case ABI_DARWIN: abi_string = "Darwin"; break;
24561 case ABI_V4: abi_string = "V.4"; break;
24564 fprintf (stderr, "\tABI = %5s\n", abi_string);
24566 if (TARGET_ALTIVEC_ABI)
24567 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24569 if (info->first_gp_reg_save != 32)
24570 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24572 if (info->first_fp_reg_save != 64)
24573 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24575 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24576 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24577 info->first_altivec_reg_save);
24579 if (info->lr_save_p)
24580 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24582 if (info->cr_save_p)
24583 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24585 if (info->vrsave_mask)
24586 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24589 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24592 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24595 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24598 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24600 if (info->altivec_size)
24601 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24602 info->altivec_save_offset);
24604 if (info->vrsave_size)
24605 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24606 info->vrsave_save_offset);
24608 if (info->lr_save_p)
24609 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24611 if (info->cr_save_p)
24612 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24614 if (info->varargs_save_offset)
24615 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24617 if (info->total_size)
24618 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24621 if (info->vars_size)
24622 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24625 if (info->parm_size)
24626 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24628 if (info->fixed_size)
24629 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24632 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24635 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24637 if (info->altivec_size)
24638 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24640 if (info->vrsave_size)
24641 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24643 if (info->altivec_padding_size)
24644 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24645 info->altivec_padding_size);
24648 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24650 if (info->save_size)
24651 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24653 if (info->reg_size != 4)
24654 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24656 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24658 if (info->abi == ABI_DARWIN)
24659 fprintf (stderr, "\tWORLD_SAVE_P = %5d\n", WORLD_SAVE_P(info));
24661 fprintf (stderr, "\n");
24665 rs6000_return_addr (int count, rtx frame)
24667 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24668 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24670 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24672 cfun->machine->ra_needs_full_frame = 1;
24675 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24676 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24677 frame = stack_pointer_rtx;
24678 rtx prev_frame_addr = memory_address (Pmode, frame);
24679 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24680 rtx lr_save_off = plus_constant (Pmode,
24681 prev_frame, RETURN_ADDRESS_OFFSET);
24682 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24683 return gen_rtx_MEM (Pmode, lr_save_addr);
24686 cfun->machine->ra_need_lr = 1;
24687 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24690 /* Say whether a function is a candidate for sibcall handling or not. */
24693 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24697 /* The sibcall epilogue may clobber the static chain register.
24698 ??? We could work harder and avoid that, but it's probably
24699 not worth the hassle in practice. */
24700 if (CALL_EXPR_STATIC_CHAIN (exp))
24704 fntype = TREE_TYPE (decl);
24706 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24708 /* We can't do it if the called function has more vector parameters
24709 than the current function; there's nowhere to put the VRsave code. */
24710 if (TARGET_ALTIVEC_ABI
24711 && TARGET_ALTIVEC_VRSAVE
24712 && !(decl && decl == current_function_decl))
24714 function_args_iterator args_iter;
24718 /* Functions with vector parameters are required to have a
24719 prototype, so the argument type info must be available
24721 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24722 if (TREE_CODE (type) == VECTOR_TYPE
24723 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24726 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24727 if (TREE_CODE (type) == VECTOR_TYPE
24728 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24735 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24736 functions, because the callee may have a different TOC pointer to
24737 the caller and there's no way to ensure we restore the TOC when
24738 we return. With the secure-plt SYSV ABI we can't make non-local
24739 calls when -fpic/PIC because the plt call stubs use r30. */
24740 if (DEFAULT_ABI == ABI_DARWIN
24741 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24743 && !DECL_EXTERNAL (decl)
24744 && !DECL_WEAK (decl)
24745 && (*targetm.binds_local_p) (decl))
24746 || (DEFAULT_ABI == ABI_V4
24747 && (!TARGET_SECURE_PLT
24750 && (*targetm.binds_local_p) (decl)))))
24752 tree attr_list = TYPE_ATTRIBUTES (fntype);
24754 if (!lookup_attribute ("longcall", attr_list)
24755 || lookup_attribute ("shortcall", attr_list))
24763 rs6000_ra_ever_killed (void)
24769 if (cfun->is_thunk)
24772 if (cfun->machine->lr_save_state)
24773 return cfun->machine->lr_save_state - 1;
24775 /* regs_ever_live has LR marked as used if any sibcalls are present,
24776 but this should not force saving and restoring in the
24777 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24778 clobbers LR, so that is inappropriate. */
24780 /* Also, the prologue can generate a store into LR that
24781 doesn't really count, like this:
24784 bcl to set PIC register
24788 When we're called from the epilogue, we need to avoid counting
24789 this as a store. */
24791 push_topmost_sequence ();
24792 top = get_insns ();
24793 pop_topmost_sequence ();
24794 reg = gen_rtx_REG (Pmode, LR_REGNO);
24796 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24802 if (!SIBLING_CALL_P (insn))
24805 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24807 else if (set_of (reg, insn) != NULL_RTX
24808 && !prologue_epilogue_contains (insn))
24815 /* Emit instructions needed to load the TOC register.
24816 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24817 a constant pool; or for SVR4 -fpic. */
24820 rs6000_emit_load_toc_table (int fromprolog)
24823 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24825 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24828 rtx lab, tmp1, tmp2, got;
24830 lab = gen_label_rtx ();
24831 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24832 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24835 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24839 got = rs6000_got_sym ();
24840 tmp1 = tmp2 = dest;
24843 tmp1 = gen_reg_rtx (Pmode);
24844 tmp2 = gen_reg_rtx (Pmode);
24846 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24847 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24848 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24849 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24851 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24853 emit_insn (gen_load_toc_v4_pic_si ());
24854 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24856 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24859 rtx temp0 = (fromprolog
24860 ? gen_rtx_REG (Pmode, 0)
24861 : gen_reg_rtx (Pmode));
24867 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24868 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24870 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
24871 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24873 emit_insn (gen_load_toc_v4_PIC_1 (symF));
24874 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24875 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
24881 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24883 lab = gen_label_rtx ();
24884 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
24885 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24886 if (TARGET_LINK_STACK)
24887 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
24888 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
24890 emit_insn (gen_addsi3 (dest, temp0, dest));
24892 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
24894 /* This is for AIX code running in non-PIC ELF32. */
24895 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24898 emit_insn (gen_elf_high (dest, realsym));
24899 emit_insn (gen_elf_low (dest, dest, realsym));
24903 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24906 emit_insn (gen_load_toc_aix_si (dest));
24908 emit_insn (gen_load_toc_aix_di (dest));
24912 /* Emit instructions to restore the link register after determining where
24913 its value has been stored. */
24916 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
24918 rs6000_stack_t *info = rs6000_stack_info ();
24921 operands[0] = source;
24922 operands[1] = scratch;
24924 if (info->lr_save_p)
24926 rtx frame_rtx = stack_pointer_rtx;
24927 HOST_WIDE_INT sp_offset = 0;
24930 if (frame_pointer_needed
24931 || cfun->calls_alloca
24932 || info->total_size > 32767)
24934 tmp = gen_frame_mem (Pmode, frame_rtx);
24935 emit_move_insn (operands[1], tmp);
24936 frame_rtx = operands[1];
24938 else if (info->push_p)
24939 sp_offset = info->total_size;
24941 tmp = plus_constant (Pmode, frame_rtx,
24942 info->lr_save_offset + sp_offset);
24943 tmp = gen_frame_mem (Pmode, tmp);
24944 emit_move_insn (tmp, operands[0]);
24947 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
24949 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24950 state of lr_save_p so any change from here on would be a bug. In
24951 particular, stop rs6000_ra_ever_killed from considering the SET
24952 of lr we may have added just above. */
24953 cfun->machine->lr_save_state = info->lr_save_p + 1;
24956 static GTY(()) alias_set_type set = -1;
24959 get_TOC_alias_set (void)
24962 set = new_alias_set ();
24966 /* This returns nonzero if the current function uses the TOC. This is
24967 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24968 is generated by the ABI_V4 load_toc_* patterns.
24969 Return 2 instead of 1 if the load_toc_* pattern is in the function
24970 partition that doesn't start the function. */
24978 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24982 rtx pat = PATTERN (insn);
24985 if (GET_CODE (pat) == PARALLEL)
24986 for (i = 0; i < XVECLEN (pat, 0); i++)
24988 rtx sub = XVECEXP (pat, 0, i);
24989 if (GET_CODE (sub) == USE)
24991 sub = XEXP (sub, 0);
24992 if (GET_CODE (sub) == UNSPEC
24993 && XINT (sub, 1) == UNSPEC_TOC)
24998 else if (crtl->has_bb_partition
25000 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25008 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25010 rtx tocrel, tocreg, hi;
25012 if (TARGET_DEBUG_ADDR)
25014 if (SYMBOL_REF_P (symbol))
25015 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25019 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25020 GET_RTX_NAME (GET_CODE (symbol)));
25021 debug_rtx (symbol);
25025 if (!can_create_pseudo_p ())
25026 df_set_regs_ever_live (TOC_REGISTER, true);
25028 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25029 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25030 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25033 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25034 if (largetoc_reg != NULL)
25036 emit_move_insn (largetoc_reg, hi);
25039 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25042 /* Issue assembly directives that create a reference to the given DWARF
25043 FRAME_TABLE_LABEL from the current function section. */
25045 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25047 fprintf (asm_out_file, "\t.ref %s\n",
25048 (* targetm.strip_name_encoding) (frame_table_label));
25051 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25052 and the change to the stack pointer. */
25055 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25062 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25063 if (hard_frame_needed)
25064 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25065 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25066 || (hard_frame_needed
25067 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25070 p = rtvec_alloc (i);
25073 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25074 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25077 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25080 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25081 and set the appropriate attributes for the generated insn. Return the
25082 first insn which adjusts the stack pointer or the last insn before
25083 the stack adjustment loop.
25085 SIZE_INT is used to create the CFI note for the allocation.
25087 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25088 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25090 ORIG_SP contains the backchain value that must be stored at *sp. */
25093 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25097 rtx size_rtx = GEN_INT (-size_int);
25098 if (size_int > 32767)
25100 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25101 /* Need a note here so that try_split doesn't get confused. */
25102 if (get_last_insn () == NULL_RTX)
25103 emit_note (NOTE_INSN_DELETED);
25104 insn = emit_move_insn (tmp_reg, size_rtx);
25105 try_split (PATTERN (insn), insn, 0);
25106 size_rtx = tmp_reg;
25110 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25115 insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
25119 rtx par = PATTERN (insn);
25120 gcc_assert (GET_CODE (par) == PARALLEL);
25121 rtx set = XVECEXP (par, 0, 0);
25122 gcc_assert (GET_CODE (set) == SET);
25123 rtx mem = SET_DEST (set);
25124 gcc_assert (MEM_P (mem));
25125 MEM_NOTRAP_P (mem) = 1;
25126 set_mem_alias_set (mem, get_frame_alias_set ());
25128 RTX_FRAME_RELATED_P (insn) = 1;
25129 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25130 gen_rtx_SET (stack_pointer_rtx,
25131 gen_rtx_PLUS (Pmode,
25133 GEN_INT (-size_int))));
25135 /* Emit a blockage to ensure the allocation/probing insns are
25136 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25137 note for similar reasons. */
25138 if (flag_stack_clash_protection)
25140 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25141 emit_insn (gen_blockage ());
25147 static HOST_WIDE_INT
25148 get_stack_clash_protection_probe_interval (void)
25150 return (HOST_WIDE_INT_1U
25151 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25154 static HOST_WIDE_INT
25155 get_stack_clash_protection_guard_size (void)
25157 return (HOST_WIDE_INT_1U
25158 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25161 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25162 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25164 COPY_REG, if non-null, should contain a copy of the original
25165 stack pointer at exit from this function.
25167 This is subtly different than the Ada probing in that it tries hard to
25168 prevent attacks that jump the stack guard. Thus it is never allowed to
25169 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25170 space without a suitable probe. */
25172 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25175 rtx orig_sp = copy_reg;
25177 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25179 /* Round the size down to a multiple of PROBE_INTERVAL. */
25180 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25182 /* If explicitly requested,
25183 or the rounded size is not the same as the original size
25184 or the the rounded size is greater than a page,
25185 then we will need a copy of the original stack pointer. */
25186 if (rounded_size != orig_size
25187 || rounded_size > probe_interval
25190 /* If the caller did not request a copy of the incoming stack
25191 pointer, then we use r0 to hold the copy. */
25193 orig_sp = gen_rtx_REG (Pmode, 0);
25194 emit_move_insn (orig_sp, stack_pointer_rtx);
25197 /* There's three cases here.
25199 One is a single probe which is the most common and most efficiently
25200 implemented as it does not have to have a copy of the original
25201 stack pointer if there are no residuals.
25203 Second is unrolled allocation/probes which we use if there's just
25204 a few of them. It needs to save the original stack pointer into a
25205 temporary for use as a source register in the allocation/probe.
25207 Last is a loop. This is the most uncommon case and least efficient. */
25208 rtx_insn *retval = NULL;
25209 if (rounded_size == probe_interval)
25211 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25213 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25215 else if (rounded_size <= 8 * probe_interval)
25217 /* The ABI requires using the store with update insns to allocate
25218 space and store the backchain into the stack
25220 So we save the current stack pointer into a temporary, then
25221 emit the store-with-update insns to store the saved stack pointer
25222 into the right location in each new page. */
25223 for (int i = 0; i < rounded_size; i += probe_interval)
25226 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25228 /* Save the first stack adjustment in RETVAL. */
25233 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25237 /* Compute the ending address. */
25239 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25240 rtx rs = GEN_INT (-rounded_size);
25242 if (add_operand (rs, Pmode))
25243 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25246 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25247 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25248 stack_pointer_rtx));
25249 /* Describe the effect of INSN to the CFI engine. */
25250 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25251 gen_rtx_SET (end_addr,
25252 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25255 RTX_FRAME_RELATED_P (insn) = 1;
25257 /* Emit the loop. */
25259 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25260 stack_pointer_rtx, orig_sp,
25263 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25264 stack_pointer_rtx, orig_sp,
25266 RTX_FRAME_RELATED_P (retval) = 1;
25267 /* Describe the effect of INSN to the CFI engine. */
25268 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25269 gen_rtx_SET (stack_pointer_rtx, end_addr));
25271 /* Emit a blockage to ensure the allocation/probing insns are
25272 not optimized, combined, removed, etc. Other cases handle this
25273 within their call to rs6000_emit_allocate_stack_1. */
25274 emit_insn (gen_blockage ());
25276 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25279 if (orig_size != rounded_size)
25281 /* Allocate (and implicitly probe) any residual space. */
25282 HOST_WIDE_INT residual = orig_size - rounded_size;
25284 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25286 /* If the residual was the only allocation, then we can return the
25287 allocating insn. */
25295 /* Emit the correct code for allocating stack space, as insns.
25296 If COPY_REG, make sure a copy of the old frame is left there.
25297 The generated code may use hard register 0 as a temporary. */
25300 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25303 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25304 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25305 rtx todec = gen_int_mode (-size, Pmode);
25307 if (INTVAL (todec) != -size)
25309 warning (0, "stack frame too large");
25310 emit_insn (gen_trap ());
25314 if (crtl->limit_stack)
25316 if (REG_P (stack_limit_rtx)
25317 && REGNO (stack_limit_rtx) > 1
25318 && REGNO (stack_limit_rtx) <= 31)
25321 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25324 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25326 else if (SYMBOL_REF_P (stack_limit_rtx)
25328 && DEFAULT_ABI == ABI_V4
25331 rtx toload = gen_rtx_CONST (VOIDmode,
25332 gen_rtx_PLUS (Pmode,
25336 emit_insn (gen_elf_high (tmp_reg, toload));
25337 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25338 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25342 warning (0, "stack limit expression is not supported");
25345 if (flag_stack_clash_protection)
25347 if (size < get_stack_clash_protection_guard_size ())
25348 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25351 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25354 /* If we asked for a copy with an offset, then we still need add in
25356 if (copy_reg && copy_off)
25357 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25365 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25367 emit_move_insn (copy_reg, stack_reg);
25370 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25371 it now and set the alias set/attributes. The above gen_*_update
25372 calls will generate a PARALLEL with the MEM set being the first
25374 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25378 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25380 #if PROBE_INTERVAL > 32768
25381 #error Cannot use indexed addressing mode for stack probing
25384 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25385 inclusive. These are offsets from the current stack pointer. */
25388 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25390 /* See if we have a constant small number of probes to generate. If so,
25391 that's the easy case. */
25392 if (first + size <= 32768)
25396 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25397 it exceeds SIZE. If only one probe is needed, this will not
25398 generate any code. Then probe at FIRST + SIZE. */
25399 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25400 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25403 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25407 /* Otherwise, do the same as above, but in a loop. Note that we must be
25408 extra careful with variables wrapping around because we might be at
25409 the very top (or the very bottom) of the address space and we have
25410 to be able to handle this case properly; in particular, we use an
25411 equality test for the loop condition. */
25414 HOST_WIDE_INT rounded_size;
25415 rtx r12 = gen_rtx_REG (Pmode, 12);
25416 rtx r0 = gen_rtx_REG (Pmode, 0);
25418 /* Sanity check for the addressing mode we're going to use. */
25419 gcc_assert (first <= 32768);
25421 /* Step 1: round SIZE to the previous multiple of the interval. */
25423 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25426 /* Step 2: compute initial and final value of the loop counter. */
25428 /* TEST_ADDR = SP + FIRST. */
25429 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25432 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25433 if (rounded_size > 32768)
25435 emit_move_insn (r0, GEN_INT (-rounded_size));
25436 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25439 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25443 /* Step 3: the loop
25447 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25450 while (TEST_ADDR != LAST_ADDR)
25452 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25453 until it is equal to ROUNDED_SIZE. */
25456 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25458 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25461 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25462 that SIZE is equal to ROUNDED_SIZE. */
25464 if (size != rounded_size)
25465 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25469 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25470 addresses, not offsets. */
25472 static const char *
25473 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25475 static int labelno = 0;
25479 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25482 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25484 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25486 xops[1] = GEN_INT (-PROBE_INTERVAL);
25487 output_asm_insn ("addi %0,%0,%1", xops);
25489 /* Probe at TEST_ADDR. */
25490 xops[1] = gen_rtx_REG (Pmode, 0);
25491 output_asm_insn ("stw %1,0(%0)", xops);
25493 /* Test if TEST_ADDR == LAST_ADDR. */
25496 output_asm_insn ("cmpd 0,%0,%1", xops);
25498 output_asm_insn ("cmpw 0,%0,%1", xops);
25501 fputs ("\tbne 0,", asm_out_file);
25502 assemble_name_raw (asm_out_file, loop_lab);
25503 fputc ('\n', asm_out_file);
25508 /* This function is called when rs6000_frame_related is processing
25509 SETs within a PARALLEL, and returns whether the REGNO save ought to
25510 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25511 for out-of-line register save functions, store multiple, and the
25512 Darwin world_save. They may contain registers that don't really
25516 interesting_frame_related_regno (unsigned int regno)
25518 /* Saves apparently of r0 are actually saving LR. It doesn't make
25519 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25520 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25521 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25522 as frame related. */
25525 /* If we see CR2 then we are here on a Darwin world save. Saves of
25526 CR2 signify the whole CR is being saved. This is a long-standing
25527 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25528 that CR needs to be saved. */
25529 if (regno == CR2_REGNO)
25531 /* Omit frame info for any user-defined global regs. If frame info
25532 is supplied for them, frame unwinding will restore a user reg.
25533 Also omit frame info for any reg we don't need to save, as that
25534 bloats frame info and can cause problems with shrink wrapping.
25535 Since global regs won't be seen as needing to be saved, both of
25536 these conditions are covered by save_reg_p. */
25537 return save_reg_p (regno);
25540 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25541 addresses, not offsets.
25543 REG2 contains the backchain that must be stored into *sp at each allocation.
25545 This is subtly different than the Ada probing above in that it tries hard
25546 to prevent attacks that jump the stack guard. Thus, it is never allowed
25547 to allocate more than PROBE_INTERVAL bytes of stack space without a
25550 static const char *
25551 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25553 static int labelno = 0;
25557 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25559 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25561 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25563 /* This allocates and probes. */
25566 xops[2] = GEN_INT (-probe_interval);
25568 output_asm_insn ("stdu %1,%2(%0)", xops);
25570 output_asm_insn ("stwu %1,%2(%0)", xops);
25572 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25576 output_asm_insn ("cmpd 0,%0,%1", xops);
25578 output_asm_insn ("cmpw 0,%0,%1", xops);
25580 fputs ("\tbne 0,", asm_out_file);
25581 assemble_name_raw (asm_out_file, loop_lab);
25582 fputc ('\n', asm_out_file);
25587 /* Wrapper around the output_probe_stack_range routines. */
25589 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25591 if (flag_stack_clash_protection)
25592 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25594 return output_probe_stack_range_1 (reg1, reg3);
25597 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25598 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25599 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25600 deduce these equivalences by itself so it wasn't necessary to hold
25601 its hand so much. Don't be tempted to always supply d2_f_d_e with
25602 the actual cfa register, ie. r31 when we are using a hard frame
25603 pointer. That fails when saving regs off r1, and sched moves the
25604 r31 setup past the reg saves. */
25607 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25608 rtx reg2, rtx repl2)
25612 if (REGNO (reg) == STACK_POINTER_REGNUM)
25614 gcc_checking_assert (val == 0);
25618 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25621 rtx pat = PATTERN (insn);
25622 if (!repl && !reg2)
25624 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25625 if (GET_CODE (pat) == PARALLEL)
25626 for (int i = 0; i < XVECLEN (pat, 0); i++)
25627 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25629 rtx set = XVECEXP (pat, 0, i);
25631 if (!REG_P (SET_SRC (set))
25632 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25633 RTX_FRAME_RELATED_P (set) = 1;
25635 RTX_FRAME_RELATED_P (insn) = 1;
25639 /* We expect that 'pat' is either a SET or a PARALLEL containing
25640 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25641 are important so they all have to be marked RTX_FRAME_RELATED_P.
25642 Call simplify_replace_rtx on the SETs rather than the whole insn
25643 so as to leave the other stuff alone (for example USE of r12). */
25645 set_used_flags (pat);
25646 if (GET_CODE (pat) == SET)
25649 pat = simplify_replace_rtx (pat, reg, repl);
25651 pat = simplify_replace_rtx (pat, reg2, repl2);
25653 else if (GET_CODE (pat) == PARALLEL)
25655 pat = shallow_copy_rtx (pat);
25656 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25658 for (int i = 0; i < XVECLEN (pat, 0); i++)
25659 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25661 rtx set = XVECEXP (pat, 0, i);
25664 set = simplify_replace_rtx (set, reg, repl);
25666 set = simplify_replace_rtx (set, reg2, repl2);
25667 XVECEXP (pat, 0, i) = set;
25669 if (!REG_P (SET_SRC (set))
25670 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25671 RTX_FRAME_RELATED_P (set) = 1;
25675 gcc_unreachable ();
25677 RTX_FRAME_RELATED_P (insn) = 1;
25678 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25683 /* Returns an insn that has a vrsave set operation with the
25684 appropriate CLOBBERs. */
25687 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25690 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25691 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25694 = gen_rtx_SET (vrsave,
25695 gen_rtx_UNSPEC_VOLATILE (SImode,
25696 gen_rtvec (2, reg, vrsave),
25697 UNSPECV_SET_VRSAVE));
25701 /* We need to clobber the registers in the mask so the scheduler
25702 does not move sets to VRSAVE before sets of AltiVec registers.
25704 However, if the function receives nonlocal gotos, reload will set
25705 all call saved registers live. We will end up with:
25707 (set (reg 999) (mem))
25708 (parallel [ (set (reg vrsave) (unspec blah))
25709 (clobber (reg 999))])
25711 The clobber will cause the store into reg 999 to be dead, and
25712 flow will attempt to delete an epilogue insn. In this case, we
25713 need an unspec use/set of the register. */
25715 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25716 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25718 if (!epiloguep || call_used_regs [i])
25719 clobs[nclobs++] = gen_hard_reg_clobber (V4SImode, i);
25722 rtx reg = gen_rtx_REG (V4SImode, i);
25725 = gen_rtx_SET (reg,
25726 gen_rtx_UNSPEC (V4SImode,
25727 gen_rtvec (1, reg), 27));
25731 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25733 for (i = 0; i < nclobs; ++i)
25734 XVECEXP (insn, 0, i) = clobs[i];
25740 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25744 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25745 mem = gen_frame_mem (GET_MODE (reg), addr);
25746 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25750 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25752 return gen_frame_set (reg, frame_reg, offset, false);
25756 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25758 return gen_frame_set (reg, frame_reg, offset, true);
25761 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25762 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25765 emit_frame_save (rtx frame_reg, machine_mode mode,
25766 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25770 /* Some cases that need register indexed addressing. */
25771 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25772 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25774 reg = gen_rtx_REG (mode, regno);
25775 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25776 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25777 NULL_RTX, NULL_RTX);
25780 /* Emit an offset memory reference suitable for a frame store, while
25781 converting to a valid addressing mode. */
25784 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25786 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25789 #ifndef TARGET_FIX_AND_CONTINUE
25790 #define TARGET_FIX_AND_CONTINUE 0
25793 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25794 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25795 #define LAST_SAVRES_REGISTER 31
25796 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25807 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25809 /* Temporary holding space for an out-of-line register save/restore
25811 static char savres_routine_name[30];
25813 /* Return the name for an out-of-line register save/restore routine.
25814 We are saving/restoring GPRs if GPR is true. */
25817 rs6000_savres_routine_name (int regno, int sel)
25819 const char *prefix = "";
25820 const char *suffix = "";
25822 /* Different targets are supposed to define
25823 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25824 routine name could be defined with:
25826 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25828 This is a nice idea in practice, but in reality, things are
25829 complicated in several ways:
25831 - ELF targets have save/restore routines for GPRs.
25833 - PPC64 ELF targets have routines for save/restore of GPRs that
25834 differ in what they do with the link register, so having a set
25835 prefix doesn't work. (We only use one of the save routines at
25836 the moment, though.)
25838 - PPC32 elf targets have "exit" versions of the restore routines
25839 that restore the link register and can save some extra space.
25840 These require an extra suffix. (There are also "tail" versions
25841 of the restore routines and "GOT" versions of the save routines,
25842 but we don't generate those at present. Same problems apply,
25845 We deal with all this by synthesizing our own prefix/suffix and
25846 using that for the simple sprintf call shown above. */
25847 if (DEFAULT_ABI == ABI_V4)
25852 if ((sel & SAVRES_REG) == SAVRES_GPR)
25853 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25854 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25855 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25856 else if ((sel & SAVRES_REG) == SAVRES_VR)
25857 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25861 if ((sel & SAVRES_LR))
25864 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25866 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25867 /* No out-of-line save/restore routines for GPRs on AIX. */
25868 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
25872 if ((sel & SAVRES_REG) == SAVRES_GPR)
25873 prefix = ((sel & SAVRES_SAVE)
25874 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
25875 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
25876 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25878 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25879 if ((sel & SAVRES_LR))
25880 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
25884 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
25885 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
25888 else if ((sel & SAVRES_REG) == SAVRES_VR)
25889 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25894 if (DEFAULT_ABI == ABI_DARWIN)
25896 /* The Darwin approach is (slightly) different, in order to be
25897 compatible with code generated by the system toolchain. There is a
25898 single symbol for the start of save sequence, and the code here
25899 embeds an offset into that code on the basis of the first register
25901 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
25902 if ((sel & SAVRES_REG) == SAVRES_GPR)
25903 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
25904 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
25905 (regno - 13) * 4, prefix, regno);
25906 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25907 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
25908 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
25909 else if ((sel & SAVRES_REG) == SAVRES_VR)
25910 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
25911 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
25916 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
25918 return savres_routine_name;
25921 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25922 We are saving/restoring GPRs if GPR is true. */
25925 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
25927 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
25928 ? info->first_gp_reg_save
25929 : (sel & SAVRES_REG) == SAVRES_FPR
25930 ? info->first_fp_reg_save - 32
25931 : (sel & SAVRES_REG) == SAVRES_VR
25932 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
25937 /* Don't generate bogus routine names. */
25938 gcc_assert (FIRST_SAVRES_REGISTER <= regno
25939 && regno <= LAST_SAVRES_REGISTER
25940 && select >= 0 && select <= 12);
25942 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
25948 name = rs6000_savres_routine_name (regno, sel);
25950 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
25951 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
25952 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
25958 /* Emit a sequence of insns, including a stack tie if needed, for
25959 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25960 reset the stack pointer, but move the base of the frame into
25961 reg UPDT_REGNO for use by out-of-line register restore routines. */
25964 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
25965 unsigned updt_regno)
25967 /* If there is nothing to do, don't do anything. */
25968 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
25971 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
25973 /* This blockage is needed so that sched doesn't decide to move
25974 the sp change before the register restores. */
25975 if (DEFAULT_ABI == ABI_V4)
25976 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
25977 GEN_INT (frame_off)));
25979 /* If we are restoring registers out-of-line, we will be using the
25980 "exit" variants of the restore routines, which will reset the
25981 stack for us. But we do need to point updt_reg into the
25982 right place for those routines. */
25983 if (frame_off != 0)
25984 return emit_insn (gen_add3_insn (updt_reg_rtx,
25985 frame_reg_rtx, GEN_INT (frame_off)));
25987 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
25992 /* Return the register number used as a pointer by out-of-line
25993 save/restore functions. */
25995 static inline unsigned
25996 ptr_regno_for_savres (int sel)
25998 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25999 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26000 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26003 /* Construct a parallel rtx describing the effect of a call to an
26004 out-of-line register save/restore routine, and emit the insn
26005 or jump_insn as appropriate. */
26008 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26009 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26010 machine_mode reg_mode, int sel)
26013 int offset, start_reg, end_reg, n_regs, use_reg;
26014 int reg_size = GET_MODE_SIZE (reg_mode);
26021 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26022 ? info->first_gp_reg_save
26023 : (sel & SAVRES_REG) == SAVRES_FPR
26024 ? info->first_fp_reg_save
26025 : (sel & SAVRES_REG) == SAVRES_VR
26026 ? info->first_altivec_reg_save
26028 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26030 : (sel & SAVRES_REG) == SAVRES_FPR
26032 : (sel & SAVRES_REG) == SAVRES_VR
26033 ? LAST_ALTIVEC_REGNO + 1
26035 n_regs = end_reg - start_reg;
26036 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26037 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26040 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26041 RTVEC_ELT (p, offset++) = ret_rtx;
26043 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
26045 sym = rs6000_savres_routine_sym (info, sel);
26046 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26048 use_reg = ptr_regno_for_savres (sel);
26049 if ((sel & SAVRES_REG) == SAVRES_VR)
26051 /* Vector regs are saved/restored using [reg+reg] addressing. */
26052 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, use_reg);
26053 RTVEC_ELT (p, offset++)
26054 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26057 RTVEC_ELT (p, offset++)
26058 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26060 for (i = 0; i < end_reg - start_reg; i++)
26061 RTVEC_ELT (p, i + offset)
26062 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26063 frame_reg_rtx, save_area_offset + reg_size * i,
26064 (sel & SAVRES_SAVE) != 0);
26066 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26067 RTVEC_ELT (p, i + offset)
26068 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26070 par = gen_rtx_PARALLEL (VOIDmode, p);
26072 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26074 insn = emit_jump_insn (par);
26075 JUMP_LABEL (insn) = ret_rtx;
26078 insn = emit_insn (par);
26082 /* Emit prologue code to store CR fields that need to be saved into REG. This
26083 function should only be called when moving the non-volatile CRs to REG, it
26084 is not a general purpose routine to move the entire set of CRs to REG.
26085 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26089 rs6000_emit_prologue_move_from_cr (rtx reg)
26091 /* Only the ELFv2 ABI allows storing only selected fields. */
26092 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26094 int i, cr_reg[8], count = 0;
26096 /* Collect CR fields that must be saved. */
26097 for (i = 0; i < 8; i++)
26098 if (save_reg_p (CR0_REGNO + i))
26099 cr_reg[count++] = i;
26101 /* If it's just a single one, use mfcrf. */
26104 rtvec p = rtvec_alloc (1);
26105 rtvec r = rtvec_alloc (2);
26106 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26107 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26109 = gen_rtx_SET (reg,
26110 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26112 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26116 /* ??? It might be better to handle count == 2 / 3 cases here
26117 as well, using logical operations to combine the values. */
26120 emit_insn (gen_prologue_movesi_from_cr (reg));
26123 /* Return whether the split-stack arg pointer (r12) is used. */
26126 split_stack_arg_pointer_used_p (void)
26128 /* If the pseudo holding the arg pointer is no longer a pseudo,
26129 then the arg pointer is used. */
26130 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26131 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26132 || HARD_REGISTER_P (cfun->machine->split_stack_arg_pointer)))
26135 /* Unfortunately we also need to do some code scanning, since
26136 r12 may have been substituted for the pseudo. */
26138 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26139 FOR_BB_INSNS (bb, insn)
26140 if (NONDEBUG_INSN_P (insn))
26142 /* A call destroys r12. */
26147 FOR_EACH_INSN_USE (use, insn)
26149 rtx x = DF_REF_REG (use);
26150 if (REG_P (x) && REGNO (x) == 12)
26154 FOR_EACH_INSN_DEF (def, insn)
26156 rtx x = DF_REF_REG (def);
26157 if (REG_P (x) && REGNO (x) == 12)
26161 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26164 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26167 rs6000_global_entry_point_needed_p (void)
26169 /* Only needed for the ELFv2 ABI. */
26170 if (DEFAULT_ABI != ABI_ELFv2)
26173 /* With -msingle-pic-base, we assume the whole program shares the same
26174 TOC, so no global entry point prologues are needed anywhere. */
26175 if (TARGET_SINGLE_PIC_BASE)
26178 /* Ensure we have a global entry point for thunks. ??? We could
26179 avoid that if the target routine doesn't need a global entry point,
26180 but we do not know whether this is the case at this point. */
26181 if (cfun->is_thunk)
26184 /* For regular functions, rs6000_emit_prologue sets this flag if the
26185 routine ever uses the TOC pointer. */
26186 return cfun->machine->r2_setup_needed;
26189 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26191 rs6000_get_separate_components (void)
26193 rs6000_stack_t *info = rs6000_stack_info ();
26195 if (WORLD_SAVE_P (info))
26198 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26199 && !(info->savres_strategy & REST_MULTIPLE));
26201 /* Component 0 is the save/restore of LR (done via GPR0).
26202 Component 2 is the save of the TOC (GPR2).
26203 Components 13..31 are the save/restore of GPR13..GPR31.
26204 Components 46..63 are the save/restore of FPR14..FPR31. */
26206 cfun->machine->n_components = 64;
26208 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26209 bitmap_clear (components);
26211 int reg_size = TARGET_32BIT ? 4 : 8;
26212 int fp_reg_size = 8;
26214 /* The GPRs we need saved to the frame. */
26215 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26216 && (info->savres_strategy & REST_INLINE_GPRS))
26218 int offset = info->gp_save_offset;
26220 offset += info->total_size;
26222 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26224 if (IN_RANGE (offset, -0x8000, 0x7fff)
26225 && save_reg_p (regno))
26226 bitmap_set_bit (components, regno);
26228 offset += reg_size;
26232 /* Don't mess with the hard frame pointer. */
26233 if (frame_pointer_needed)
26234 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26236 /* Don't mess with the fixed TOC register. */
26237 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26238 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26239 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26240 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26242 /* The FPRs we need saved to the frame. */
26243 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26244 && (info->savres_strategy & REST_INLINE_FPRS))
26246 int offset = info->fp_save_offset;
26248 offset += info->total_size;
26250 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26252 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26253 bitmap_set_bit (components, regno);
26255 offset += fp_reg_size;
26259 /* Optimize LR save and restore if we can. This is component 0. Any
26260 out-of-line register save/restore routines need LR. */
26261 if (info->lr_save_p
26262 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26263 && (info->savres_strategy & SAVE_INLINE_GPRS)
26264 && (info->savres_strategy & REST_INLINE_GPRS)
26265 && (info->savres_strategy & SAVE_INLINE_FPRS)
26266 && (info->savres_strategy & REST_INLINE_FPRS)
26267 && (info->savres_strategy & SAVE_INLINE_VRS)
26268 && (info->savres_strategy & REST_INLINE_VRS))
26270 int offset = info->lr_save_offset;
26272 offset += info->total_size;
26273 if (IN_RANGE (offset, -0x8000, 0x7fff))
26274 bitmap_set_bit (components, 0);
26277 /* Optimize saving the TOC. This is component 2. */
26278 if (cfun->machine->save_toc_in_prologue)
26279 bitmap_set_bit (components, 2);
26284 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26286 rs6000_components_for_bb (basic_block bb)
26288 rs6000_stack_t *info = rs6000_stack_info ();
26290 bitmap in = DF_LIVE_IN (bb);
26291 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26292 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26294 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26295 bitmap_clear (components);
26297 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26300 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26301 if (bitmap_bit_p (in, regno)
26302 || bitmap_bit_p (gen, regno)
26303 || bitmap_bit_p (kill, regno))
26304 bitmap_set_bit (components, regno);
26307 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26308 if (bitmap_bit_p (in, regno)
26309 || bitmap_bit_p (gen, regno)
26310 || bitmap_bit_p (kill, regno))
26311 bitmap_set_bit (components, regno);
26313 /* The link register. */
26314 if (bitmap_bit_p (in, LR_REGNO)
26315 || bitmap_bit_p (gen, LR_REGNO)
26316 || bitmap_bit_p (kill, LR_REGNO))
26317 bitmap_set_bit (components, 0);
26319 /* The TOC save. */
26320 if (bitmap_bit_p (in, TOC_REGNUM)
26321 || bitmap_bit_p (gen, TOC_REGNUM)
26322 || bitmap_bit_p (kill, TOC_REGNUM))
26323 bitmap_set_bit (components, 2);
26328 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26330 rs6000_disqualify_components (sbitmap components, edge e,
26331 sbitmap edge_components, bool /*is_prologue*/)
26333 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26334 live where we want to place that code. */
26335 if (bitmap_bit_p (edge_components, 0)
26336 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26339 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26340 "on entry to bb %d\n", e->dest->index);
26341 bitmap_clear_bit (components, 0);
26345 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26347 rs6000_emit_prologue_components (sbitmap components)
26349 rs6000_stack_t *info = rs6000_stack_info ();
26350 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26351 ? HARD_FRAME_POINTER_REGNUM
26352 : STACK_POINTER_REGNUM);
26354 machine_mode reg_mode = Pmode;
26355 int reg_size = TARGET_32BIT ? 4 : 8;
26356 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26357 int fp_reg_size = 8;
26359 /* Prologue for LR. */
26360 if (bitmap_bit_p (components, 0))
26362 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26363 rtx reg = gen_rtx_REG (reg_mode, 0);
26364 rtx_insn *insn = emit_move_insn (reg, lr);
26365 RTX_FRAME_RELATED_P (insn) = 1;
26366 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26368 int offset = info->lr_save_offset;
26370 offset += info->total_size;
26372 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26373 RTX_FRAME_RELATED_P (insn) = 1;
26374 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26375 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26378 /* Prologue for TOC. */
26379 if (bitmap_bit_p (components, 2))
26381 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26382 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26383 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26386 /* Prologue for the GPRs. */
26387 int offset = info->gp_save_offset;
26389 offset += info->total_size;
26391 for (int i = info->first_gp_reg_save; i < 32; i++)
26393 if (bitmap_bit_p (components, i))
26395 rtx reg = gen_rtx_REG (reg_mode, i);
26396 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26397 RTX_FRAME_RELATED_P (insn) = 1;
26398 rtx set = copy_rtx (single_set (insn));
26399 add_reg_note (insn, REG_CFA_OFFSET, set);
26402 offset += reg_size;
26405 /* Prologue for the FPRs. */
26406 offset = info->fp_save_offset;
26408 offset += info->total_size;
26410 for (int i = info->first_fp_reg_save; i < 64; i++)
26412 if (bitmap_bit_p (components, i))
26414 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26415 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26416 RTX_FRAME_RELATED_P (insn) = 1;
26417 rtx set = copy_rtx (single_set (insn));
26418 add_reg_note (insn, REG_CFA_OFFSET, set);
26421 offset += fp_reg_size;
26425 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26427 rs6000_emit_epilogue_components (sbitmap components)
26429 rs6000_stack_t *info = rs6000_stack_info ();
26430 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26431 ? HARD_FRAME_POINTER_REGNUM
26432 : STACK_POINTER_REGNUM);
26434 machine_mode reg_mode = Pmode;
26435 int reg_size = TARGET_32BIT ? 4 : 8;
26437 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26438 int fp_reg_size = 8;
26440 /* Epilogue for the FPRs. */
26441 int offset = info->fp_save_offset;
26443 offset += info->total_size;
26445 for (int i = info->first_fp_reg_save; i < 64; i++)
26447 if (bitmap_bit_p (components, i))
26449 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26450 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26451 RTX_FRAME_RELATED_P (insn) = 1;
26452 add_reg_note (insn, REG_CFA_RESTORE, reg);
26455 offset += fp_reg_size;
26458 /* Epilogue for the GPRs. */
26459 offset = info->gp_save_offset;
26461 offset += info->total_size;
26463 for (int i = info->first_gp_reg_save; i < 32; i++)
26465 if (bitmap_bit_p (components, i))
26467 rtx reg = gen_rtx_REG (reg_mode, i);
26468 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26469 RTX_FRAME_RELATED_P (insn) = 1;
26470 add_reg_note (insn, REG_CFA_RESTORE, reg);
26473 offset += reg_size;
26476 /* Epilogue for LR. */
26477 if (bitmap_bit_p (components, 0))
26479 int offset = info->lr_save_offset;
26481 offset += info->total_size;
26483 rtx reg = gen_rtx_REG (reg_mode, 0);
26484 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26486 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26487 insn = emit_move_insn (lr, reg);
26488 RTX_FRAME_RELATED_P (insn) = 1;
26489 add_reg_note (insn, REG_CFA_RESTORE, lr);
26493 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26495 rs6000_set_handled_components (sbitmap components)
26497 rs6000_stack_t *info = rs6000_stack_info ();
26499 for (int i = info->first_gp_reg_save; i < 32; i++)
26500 if (bitmap_bit_p (components, i))
26501 cfun->machine->gpr_is_wrapped_separately[i] = true;
26503 for (int i = info->first_fp_reg_save; i < 64; i++)
26504 if (bitmap_bit_p (components, i))
26505 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26507 if (bitmap_bit_p (components, 0))
26508 cfun->machine->lr_is_wrapped_separately = true;
26510 if (bitmap_bit_p (components, 2))
26511 cfun->machine->toc_is_wrapped_separately = true;
26514 /* VRSAVE is a bit vector representing which AltiVec registers
26515 are used. The OS uses this to determine which vector
26516 registers to save on a context switch. We need to save
26517 VRSAVE on the stack frame, add whatever AltiVec registers we
26518 used in this function, and do the corresponding magic in the
26521 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26522 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26524 /* Get VRSAVE into a GPR. */
26525 rtx reg = gen_rtx_REG (SImode, save_regno);
26526 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26528 emit_insn (gen_get_vrsave_internal (reg));
26530 emit_insn (gen_rtx_SET (reg, vrsave));
26533 int offset = info->vrsave_save_offset + frame_off;
26534 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26536 /* Include the registers in the mask. */
26537 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26539 emit_insn (generate_set_vrsave (reg, info, 0));
26542 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26543 called, it left the arg pointer to the old stack in r29. Otherwise, the
26544 arg pointer is the top of the current frame. */
26546 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26547 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26549 cfun->machine->split_stack_argp_used = true;
26553 rtx r12 = gen_rtx_REG (Pmode, 12);
26554 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26555 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26556 emit_insn_before (set_r12, sp_adjust);
26558 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26560 rtx r12 = gen_rtx_REG (Pmode, 12);
26561 if (frame_off == 0)
26562 emit_move_insn (r12, frame_reg_rtx);
26564 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26569 rtx r12 = gen_rtx_REG (Pmode, 12);
26570 rtx r29 = gen_rtx_REG (Pmode, 29);
26571 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26572 rtx not_more = gen_label_rtx ();
26575 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26576 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26577 gen_rtx_LABEL_REF (VOIDmode, not_more),
26579 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26580 JUMP_LABEL (jump) = not_more;
26581 LABEL_NUSES (not_more) += 1;
26582 emit_move_insn (r12, r29);
26583 emit_label (not_more);
26587 /* Emit function prologue as insns. */
26590 rs6000_emit_prologue (void)
26592 rs6000_stack_t *info = rs6000_stack_info ();
26593 machine_mode reg_mode = Pmode;
26594 int reg_size = TARGET_32BIT ? 4 : 8;
26595 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26596 int fp_reg_size = 8;
26597 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26598 rtx frame_reg_rtx = sp_reg_rtx;
26599 unsigned int cr_save_regno;
26600 rtx cr_save_rtx = NULL_RTX;
26603 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26604 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26605 && call_used_regs[STATIC_CHAIN_REGNUM]);
26606 int using_split_stack = (flag_split_stack
26607 && (lookup_attribute ("no_split_stack",
26608 DECL_ATTRIBUTES (cfun->decl))
26611 /* Offset to top of frame for frame_reg and sp respectively. */
26612 HOST_WIDE_INT frame_off = 0;
26613 HOST_WIDE_INT sp_off = 0;
26614 /* sp_adjust is the stack adjusting instruction, tracked so that the
26615 insn setting up the split-stack arg pointer can be emitted just
26616 prior to it, when r12 is not used here for other purposes. */
26617 rtx_insn *sp_adjust = 0;
26620 /* Track and check usage of r0, r11, r12. */
26621 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26622 #define START_USE(R) do \
26624 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26625 reg_inuse |= 1 << (R); \
26627 #define END_USE(R) do \
26629 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26630 reg_inuse &= ~(1 << (R)); \
26632 #define NOT_INUSE(R) do \
26634 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26637 #define START_USE(R) do {} while (0)
26638 #define END_USE(R) do {} while (0)
26639 #define NOT_INUSE(R) do {} while (0)
26642 if (DEFAULT_ABI == ABI_ELFv2
26643 && !TARGET_SINGLE_PIC_BASE)
26645 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26647 /* With -mminimal-toc we may generate an extra use of r2 below. */
26648 if (TARGET_TOC && TARGET_MINIMAL_TOC
26649 && !constant_pool_empty_p ())
26650 cfun->machine->r2_setup_needed = true;
26654 if (flag_stack_usage_info)
26655 current_function_static_stack_size = info->total_size;
26657 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26659 HOST_WIDE_INT size = info->total_size;
26661 if (crtl->is_leaf && !cfun->calls_alloca)
26663 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26664 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26665 size - get_stack_check_protect ());
26668 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26671 if (TARGET_FIX_AND_CONTINUE)
26673 /* gdb on darwin arranges to forward a function from the old
26674 address by modifying the first 5 instructions of the function
26675 to branch to the overriding function. This is necessary to
26676 permit function pointers that point to the old function to
26677 actually forward to the new function. */
26678 emit_insn (gen_nop ());
26679 emit_insn (gen_nop ());
26680 emit_insn (gen_nop ());
26681 emit_insn (gen_nop ());
26682 emit_insn (gen_nop ());
26685 /* Handle world saves specially here. */
26686 if (WORLD_SAVE_P (info))
26693 /* save_world expects lr in r0. */
26694 reg0 = gen_rtx_REG (Pmode, 0);
26695 if (info->lr_save_p)
26697 insn = emit_move_insn (reg0,
26698 gen_rtx_REG (Pmode, LR_REGNO));
26699 RTX_FRAME_RELATED_P (insn) = 1;
26702 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26703 assumptions about the offsets of various bits of the stack
26705 gcc_assert (info->gp_save_offset == -220
26706 && info->fp_save_offset == -144
26707 && info->lr_save_offset == 8
26708 && info->cr_save_offset == 4
26711 && (!crtl->calls_eh_return
26712 || info->ehrd_offset == -432)
26713 && info->vrsave_save_offset == -224
26714 && info->altivec_save_offset == -416);
26716 treg = gen_rtx_REG (SImode, 11);
26717 emit_move_insn (treg, GEN_INT (-info->total_size));
26719 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26720 in R11. It also clobbers R12, so beware! */
26722 /* Preserve CR2 for save_world prologues */
26724 sz += 32 - info->first_gp_reg_save;
26725 sz += 64 - info->first_fp_reg_save;
26726 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26727 p = rtvec_alloc (sz);
26729 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, LR_REGNO);
26730 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26731 gen_rtx_SYMBOL_REF (Pmode,
26733 /* We do floats first so that the instruction pattern matches
26735 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26737 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26738 info->first_fp_reg_save + i),
26740 info->fp_save_offset + frame_off + 8 * i);
26741 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26743 = gen_frame_store (gen_rtx_REG (V4SImode,
26744 info->first_altivec_reg_save + i),
26746 info->altivec_save_offset + frame_off + 16 * i);
26747 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26749 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26751 info->gp_save_offset + frame_off + reg_size * i);
26753 /* CR register traditionally saved as CR2. */
26755 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26756 frame_reg_rtx, info->cr_save_offset + frame_off);
26757 /* Explain about use of R0. */
26758 if (info->lr_save_p)
26760 = gen_frame_store (reg0,
26761 frame_reg_rtx, info->lr_save_offset + frame_off);
26762 /* Explain what happens to the stack pointer. */
26764 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26765 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26768 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26769 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26770 treg, GEN_INT (-info->total_size));
26771 sp_off = frame_off = info->total_size;
26774 strategy = info->savres_strategy;
26776 /* For V.4, update stack before we do any saving and set back pointer. */
26777 if (! WORLD_SAVE_P (info)
26779 && (DEFAULT_ABI == ABI_V4
26780 || crtl->calls_eh_return))
26782 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26783 || !(strategy & SAVE_INLINE_GPRS)
26784 || !(strategy & SAVE_INLINE_VRS));
26785 int ptr_regno = -1;
26786 rtx ptr_reg = NULL_RTX;
26789 if (info->total_size < 32767)
26790 frame_off = info->total_size;
26793 else if (info->cr_save_p
26795 || info->first_fp_reg_save < 64
26796 || info->first_gp_reg_save < 32
26797 || info->altivec_size != 0
26798 || info->vrsave_size != 0
26799 || crtl->calls_eh_return)
26803 /* The prologue won't be saving any regs so there is no need
26804 to set up a frame register to access any frame save area.
26805 We also won't be using frame_off anywhere below, but set
26806 the correct value anyway to protect against future
26807 changes to this function. */
26808 frame_off = info->total_size;
26810 if (ptr_regno != -1)
26812 /* Set up the frame offset to that needed by the first
26813 out-of-line save function. */
26814 START_USE (ptr_regno);
26815 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26816 frame_reg_rtx = ptr_reg;
26817 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26818 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26819 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26820 ptr_off = info->gp_save_offset + info->gp_size;
26821 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26822 ptr_off = info->altivec_save_offset + info->altivec_size;
26823 frame_off = -ptr_off;
26825 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26827 if (REGNO (frame_reg_rtx) == 12)
26829 sp_off = info->total_size;
26830 if (frame_reg_rtx != sp_reg_rtx)
26831 rs6000_emit_stack_tie (frame_reg_rtx, false);
26834 /* If we use the link register, get it into r0. */
26835 if (!WORLD_SAVE_P (info) && info->lr_save_p
26836 && !cfun->machine->lr_is_wrapped_separately)
26838 rtx addr, reg, mem;
26840 reg = gen_rtx_REG (Pmode, 0);
26842 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26843 RTX_FRAME_RELATED_P (insn) = 1;
26845 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26846 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26848 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26849 GEN_INT (info->lr_save_offset + frame_off));
26850 mem = gen_rtx_MEM (Pmode, addr);
26851 /* This should not be of rs6000_sr_alias_set, because of
26852 __builtin_return_address. */
26854 insn = emit_move_insn (mem, reg);
26855 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26856 NULL_RTX, NULL_RTX);
26861 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26862 r12 will be needed by out-of-line gpr save. */
26863 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26864 && !(strategy & (SAVE_INLINE_GPRS
26865 | SAVE_NOINLINE_GPRS_SAVES_LR))
26867 if (!WORLD_SAVE_P (info)
26869 && REGNO (frame_reg_rtx) != cr_save_regno
26870 && !(using_static_chain_p && cr_save_regno == 11)
26871 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
26873 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
26874 START_USE (cr_save_regno);
26875 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26878 /* Do any required saving of fpr's. If only one or two to save, do
26879 it ourselves. Otherwise, call function. */
26880 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
26882 int offset = info->fp_save_offset + frame_off;
26883 for (int i = info->first_fp_reg_save; i < 64; i++)
26886 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
26887 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
26888 sp_off - frame_off);
26890 offset += fp_reg_size;
26893 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
26895 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
26896 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
26897 unsigned ptr_regno = ptr_regno_for_savres (sel);
26898 rtx ptr_reg = frame_reg_rtx;
26900 if (REGNO (frame_reg_rtx) == ptr_regno)
26901 gcc_checking_assert (frame_off == 0);
26904 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26905 NOT_INUSE (ptr_regno);
26906 emit_insn (gen_add3_insn (ptr_reg,
26907 frame_reg_rtx, GEN_INT (frame_off)));
26909 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26910 info->fp_save_offset,
26911 info->lr_save_offset,
26913 rs6000_frame_related (insn, ptr_reg, sp_off,
26914 NULL_RTX, NULL_RTX);
26919 /* Save GPRs. This is done as a PARALLEL if we are using
26920 the store-multiple instructions. */
26921 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
26923 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
26924 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
26925 unsigned ptr_regno = ptr_regno_for_savres (sel);
26926 rtx ptr_reg = frame_reg_rtx;
26927 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
26928 int end_save = info->gp_save_offset + info->gp_size;
26931 if (ptr_regno == 12)
26934 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26936 /* Need to adjust r11 (r12) if we saved any FPRs. */
26937 if (end_save + frame_off != 0)
26939 rtx offset = GEN_INT (end_save + frame_off);
26942 frame_off = -end_save;
26944 NOT_INUSE (ptr_regno);
26945 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
26947 else if (!ptr_set_up)
26949 NOT_INUSE (ptr_regno);
26950 emit_move_insn (ptr_reg, frame_reg_rtx);
26952 ptr_off = -end_save;
26953 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26954 info->gp_save_offset + ptr_off,
26955 info->lr_save_offset + ptr_off,
26957 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
26958 NULL_RTX, NULL_RTX);
26962 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
26966 p = rtvec_alloc (32 - info->first_gp_reg_save);
26967 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26969 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26971 info->gp_save_offset + frame_off + reg_size * i);
26972 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26973 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26974 NULL_RTX, NULL_RTX);
26976 else if (!WORLD_SAVE_P (info))
26978 int offset = info->gp_save_offset + frame_off;
26979 for (int i = info->first_gp_reg_save; i < 32; i++)
26982 && !cfun->machine->gpr_is_wrapped_separately[i])
26983 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
26984 sp_off - frame_off);
26986 offset += reg_size;
26990 if (crtl->calls_eh_return)
26997 unsigned int regno = EH_RETURN_DATA_REGNO (i);
26998 if (regno == INVALID_REGNUM)
27002 p = rtvec_alloc (i);
27006 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27007 if (regno == INVALID_REGNUM)
27011 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27013 info->ehrd_offset + sp_off + reg_size * (int) i);
27014 RTVEC_ELT (p, i) = set;
27015 RTX_FRAME_RELATED_P (set) = 1;
27018 insn = emit_insn (gen_blockage ());
27019 RTX_FRAME_RELATED_P (insn) = 1;
27020 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27023 /* In AIX ABI we need to make sure r2 is really saved. */
27024 if (TARGET_AIX && crtl->calls_eh_return)
27026 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27027 rtx join_insn, note;
27028 rtx_insn *save_insn;
27029 long toc_restore_insn;
27031 tmp_reg = gen_rtx_REG (Pmode, 11);
27032 tmp_reg_si = gen_rtx_REG (SImode, 11);
27033 if (using_static_chain_p)
27036 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27040 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27041 /* Peek at instruction to which this function returns. If it's
27042 restoring r2, then we know we've already saved r2. We can't
27043 unconditionally save r2 because the value we have will already
27044 be updated if we arrived at this function via a plt call or
27045 toc adjusting stub. */
27046 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27047 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27048 + RS6000_TOC_SAVE_SLOT);
27049 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27050 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27051 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27052 validate_condition_mode (EQ, CCUNSmode);
27053 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27054 emit_insn (gen_rtx_SET (compare_result,
27055 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27056 toc_save_done = gen_label_rtx ();
27057 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27058 gen_rtx_EQ (VOIDmode, compare_result,
27060 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27062 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27063 JUMP_LABEL (jump) = toc_save_done;
27064 LABEL_NUSES (toc_save_done) += 1;
27066 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27067 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27068 sp_off - frame_off);
27070 emit_label (toc_save_done);
27072 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27073 have a CFG that has different saves along different paths.
27074 Move the note to a dummy blockage insn, which describes that
27075 R2 is unconditionally saved after the label. */
27076 /* ??? An alternate representation might be a special insn pattern
27077 containing both the branch and the store. That might let the
27078 code that minimizes the number of DW_CFA_advance opcodes better
27079 freedom in placing the annotations. */
27080 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27082 remove_note (save_insn, note);
27084 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27085 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27086 RTX_FRAME_RELATED_P (save_insn) = 0;
27088 join_insn = emit_insn (gen_blockage ());
27089 REG_NOTES (join_insn) = note;
27090 RTX_FRAME_RELATED_P (join_insn) = 1;
27092 if (using_static_chain_p)
27094 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27101 /* Save CR if we use any that must be preserved. */
27102 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27104 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27105 GEN_INT (info->cr_save_offset + frame_off));
27106 rtx mem = gen_frame_mem (SImode, addr);
27108 /* If we didn't copy cr before, do so now using r0. */
27109 if (cr_save_rtx == NULL_RTX)
27112 cr_save_rtx = gen_rtx_REG (SImode, 0);
27113 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27116 /* Saving CR requires a two-instruction sequence: one instruction
27117 to move the CR to a general-purpose register, and a second
27118 instruction that stores the GPR to memory.
27120 We do not emit any DWARF CFI records for the first of these,
27121 because we cannot properly represent the fact that CR is saved in
27122 a register. One reason is that we cannot express that multiple
27123 CR fields are saved; another reason is that on 64-bit, the size
27124 of the CR register in DWARF (4 bytes) differs from the size of
27125 a general-purpose register.
27127 This means if any intervening instruction were to clobber one of
27128 the call-saved CR fields, we'd have incorrect CFI. To prevent
27129 this from happening, we mark the store to memory as a use of
27130 those CR fields, which prevents any such instruction from being
27131 scheduled in between the two instructions. */
27136 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27137 for (i = 0; i < 8; i++)
27138 if (save_reg_p (CR0_REGNO + i))
27139 crsave_v[n_crsave++]
27140 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27142 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27143 gen_rtvec_v (n_crsave, crsave_v)));
27144 END_USE (REGNO (cr_save_rtx));
27146 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27147 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27148 so we need to construct a frame expression manually. */
27149 RTX_FRAME_RELATED_P (insn) = 1;
27151 /* Update address to be stack-pointer relative, like
27152 rs6000_frame_related would do. */
27153 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27154 GEN_INT (info->cr_save_offset + sp_off));
27155 mem = gen_frame_mem (SImode, addr);
27157 if (DEFAULT_ABI == ABI_ELFv2)
27159 /* In the ELFv2 ABI we generate separate CFI records for each
27160 CR field that was actually saved. They all point to the
27161 same 32-bit stack slot. */
27165 for (i = 0; i < 8; i++)
27166 if (save_reg_p (CR0_REGNO + i))
27169 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27171 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27175 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27176 gen_rtx_PARALLEL (VOIDmode,
27177 gen_rtvec_v (n_crframe, crframe)));
27181 /* In other ABIs, by convention, we use a single CR regnum to
27182 represent the fact that all call-saved CR fields are saved.
27183 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27184 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27185 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27189 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27190 *separate* slots if the routine calls __builtin_eh_return, so
27191 that they can be independently restored by the unwinder. */
27192 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27194 int i, cr_off = info->ehcr_offset;
27197 /* ??? We might get better performance by using multiple mfocrf
27199 crsave = gen_rtx_REG (SImode, 0);
27200 emit_insn (gen_prologue_movesi_from_cr (crsave));
27202 for (i = 0; i < 8; i++)
27203 if (!call_used_regs[CR0_REGNO + i])
27205 rtvec p = rtvec_alloc (2);
27207 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27209 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27211 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27213 RTX_FRAME_RELATED_P (insn) = 1;
27214 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27215 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27216 sp_reg_rtx, cr_off + sp_off));
27218 cr_off += reg_size;
27222 /* If we are emitting stack probes, but allocate no stack, then
27223 just note that in the dump file. */
27224 if (flag_stack_clash_protection
27227 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27229 /* Update stack and set back pointer unless this is V.4,
27230 for which it was done previously. */
27231 if (!WORLD_SAVE_P (info) && info->push_p
27232 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27234 rtx ptr_reg = NULL;
27237 /* If saving altivec regs we need to be able to address all save
27238 locations using a 16-bit offset. */
27239 if ((strategy & SAVE_INLINE_VRS) == 0
27240 || (info->altivec_size != 0
27241 && (info->altivec_save_offset + info->altivec_size - 16
27242 + info->total_size - frame_off) > 32767)
27243 || (info->vrsave_size != 0
27244 && (info->vrsave_save_offset
27245 + info->total_size - frame_off) > 32767))
27247 int sel = SAVRES_SAVE | SAVRES_VR;
27248 unsigned ptr_regno = ptr_regno_for_savres (sel);
27250 if (using_static_chain_p
27251 && ptr_regno == STATIC_CHAIN_REGNUM)
27253 if (REGNO (frame_reg_rtx) != ptr_regno)
27254 START_USE (ptr_regno);
27255 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27256 frame_reg_rtx = ptr_reg;
27257 ptr_off = info->altivec_save_offset + info->altivec_size;
27258 frame_off = -ptr_off;
27260 else if (REGNO (frame_reg_rtx) == 1)
27261 frame_off = info->total_size;
27262 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27264 if (REGNO (frame_reg_rtx) == 12)
27266 sp_off = info->total_size;
27267 if (frame_reg_rtx != sp_reg_rtx)
27268 rs6000_emit_stack_tie (frame_reg_rtx, false);
27271 /* Set frame pointer, if needed. */
27272 if (frame_pointer_needed)
27274 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27276 RTX_FRAME_RELATED_P (insn) = 1;
27279 /* Save AltiVec registers if needed. Save here because the red zone does
27280 not always include AltiVec registers. */
27281 if (!WORLD_SAVE_P (info)
27282 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27284 int end_save = info->altivec_save_offset + info->altivec_size;
27286 /* Oddly, the vector save/restore functions point r0 at the end
27287 of the save area, then use r11 or r12 to load offsets for
27288 [reg+reg] addressing. */
27289 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27290 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27291 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27293 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27295 if (scratch_regno == 12)
27297 if (end_save + frame_off != 0)
27299 rtx offset = GEN_INT (end_save + frame_off);
27301 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27304 emit_move_insn (ptr_reg, frame_reg_rtx);
27306 ptr_off = -end_save;
27307 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27308 info->altivec_save_offset + ptr_off,
27309 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27310 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27311 NULL_RTX, NULL_RTX);
27312 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27314 /* The oddity mentioned above clobbered our frame reg. */
27315 emit_move_insn (frame_reg_rtx, ptr_reg);
27316 frame_off = ptr_off;
27319 else if (!WORLD_SAVE_P (info)
27320 && info->altivec_size != 0)
27324 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27325 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27327 rtx areg, savereg, mem;
27328 HOST_WIDE_INT offset;
27330 offset = (info->altivec_save_offset + frame_off
27331 + 16 * (i - info->first_altivec_reg_save));
27333 savereg = gen_rtx_REG (V4SImode, i);
27335 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27337 mem = gen_frame_mem (V4SImode,
27338 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27339 GEN_INT (offset)));
27340 insn = emit_insn (gen_rtx_SET (mem, savereg));
27346 areg = gen_rtx_REG (Pmode, 0);
27347 emit_move_insn (areg, GEN_INT (offset));
27349 /* AltiVec addressing mode is [reg+reg]. */
27350 mem = gen_frame_mem (V4SImode,
27351 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27353 /* Rather than emitting a generic move, force use of the stvx
27354 instruction, which we always want on ISA 2.07 (power8) systems.
27355 In particular we don't want xxpermdi/stxvd2x for little
27357 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27360 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27361 areg, GEN_INT (offset));
27365 /* VRSAVE is a bit vector representing which AltiVec registers
27366 are used. The OS uses this to determine which vector
27367 registers to save on a context switch. We need to save
27368 VRSAVE on the stack frame, add whatever AltiVec registers we
27369 used in this function, and do the corresponding magic in the
27372 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27374 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27375 be using r12 as frame_reg_rtx and r11 as the static chain
27376 pointer for nested functions. */
27377 int save_regno = 12;
27378 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27379 && !using_static_chain_p)
27381 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27384 if (using_static_chain_p)
27387 NOT_INUSE (save_regno);
27389 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27392 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27393 if (!TARGET_SINGLE_PIC_BASE
27394 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27395 && !constant_pool_empty_p ())
27396 || (DEFAULT_ABI == ABI_V4
27397 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27398 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27400 /* If emit_load_toc_table will use the link register, we need to save
27401 it. We use R12 for this purpose because emit_load_toc_table
27402 can use register 0. This allows us to use a plain 'blr' to return
27403 from the procedure more often. */
27404 int save_LR_around_toc_setup = (TARGET_ELF
27405 && DEFAULT_ABI == ABI_V4
27407 && ! info->lr_save_p
27408 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27409 if (save_LR_around_toc_setup)
27411 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27412 rtx tmp = gen_rtx_REG (Pmode, 12);
27415 insn = emit_move_insn (tmp, lr);
27416 RTX_FRAME_RELATED_P (insn) = 1;
27418 rs6000_emit_load_toc_table (TRUE);
27420 insn = emit_move_insn (lr, tmp);
27421 add_reg_note (insn, REG_CFA_RESTORE, lr);
27422 RTX_FRAME_RELATED_P (insn) = 1;
27425 rs6000_emit_load_toc_table (TRUE);
27429 if (!TARGET_SINGLE_PIC_BASE
27430 && DEFAULT_ABI == ABI_DARWIN
27431 && flag_pic && crtl->uses_pic_offset_table)
27433 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27434 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27436 /* Save and restore LR locally around this call (in R0). */
27437 if (!info->lr_save_p)
27438 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27440 emit_insn (gen_load_macho_picbase (src));
27442 emit_move_insn (gen_rtx_REG (Pmode,
27443 RS6000_PIC_OFFSET_TABLE_REGNUM),
27446 if (!info->lr_save_p)
27447 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27451 /* If we need to, save the TOC register after doing the stack setup.
27452 Do not emit eh frame info for this save. The unwinder wants info,
27453 conceptually attached to instructions in this function, about
27454 register values in the caller of this function. This R2 may have
27455 already been changed from the value in the caller.
27456 We don't attempt to write accurate DWARF EH frame info for R2
27457 because code emitted by gcc for a (non-pointer) function call
27458 doesn't save and restore R2. Instead, R2 is managed out-of-line
27459 by a linker generated plt call stub when the function resides in
27460 a shared library. This behavior is costly to describe in DWARF,
27461 both in terms of the size of DWARF info and the time taken in the
27462 unwinder to interpret it. R2 changes, apart from the
27463 calls_eh_return case earlier in this function, are handled by
27464 linux-unwind.h frob_update_context. */
27465 if (rs6000_save_toc_in_prologue_p ()
27466 && !cfun->machine->toc_is_wrapped_separately)
27468 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27469 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27472 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27473 if (using_split_stack && split_stack_arg_pointer_used_p ())
27474 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27477 /* Output .extern statements for the save/restore routines we use. */
27480 rs6000_output_savres_externs (FILE *file)
27482 rs6000_stack_t *info = rs6000_stack_info ();
27484 if (TARGET_DEBUG_STACK)
27485 debug_stack_info (info);
27487 /* Write .extern for any function we will call to save and restore
27489 if (info->first_fp_reg_save < 64
27494 int regno = info->first_fp_reg_save - 32;
27496 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27498 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27499 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27500 name = rs6000_savres_routine_name (regno, sel);
27501 fprintf (file, "\t.extern %s\n", name);
27503 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27505 bool lr = (info->savres_strategy
27506 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27507 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27508 name = rs6000_savres_routine_name (regno, sel);
27509 fprintf (file, "\t.extern %s\n", name);
27514 /* Write function prologue. */
27517 rs6000_output_function_prologue (FILE *file)
27519 if (!cfun->is_thunk)
27521 rs6000_output_savres_externs (file);
27522 #ifdef USING_ELFOS_H
27523 const char *curr_machine = rs6000_machine_from_flags ();
27524 if (rs6000_machine != curr_machine)
27526 rs6000_machine = curr_machine;
27527 emit_asm_machine ();
27532 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27533 immediately after the global entry point label. */
27534 if (rs6000_global_entry_point_needed_p ())
27536 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27538 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27540 if (TARGET_CMODEL != CMODEL_LARGE)
27542 /* In the small and medium code models, we assume the TOC is less
27543 2 GB away from the text section, so it can be computed via the
27544 following two-instruction sequence. */
27547 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27548 fprintf (file, "0:\taddis 2,12,.TOC.-");
27549 assemble_name (file, buf);
27550 fprintf (file, "@ha\n");
27551 fprintf (file, "\taddi 2,2,.TOC.-");
27552 assemble_name (file, buf);
27553 fprintf (file, "@l\n");
27557 /* In the large code model, we allow arbitrary offsets between the
27558 TOC and the text section, so we have to load the offset from
27559 memory. The data field is emitted directly before the global
27560 entry point in rs6000_elf_declare_function_name. */
27563 #ifdef HAVE_AS_ENTRY_MARKERS
27564 /* If supported by the linker, emit a marker relocation. If the
27565 total code size of the final executable or shared library
27566 happens to fit into 2 GB after all, the linker will replace
27567 this code sequence with the sequence for the small or medium
27569 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27571 fprintf (file, "\tld 2,");
27572 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27573 assemble_name (file, buf);
27574 fprintf (file, "-");
27575 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27576 assemble_name (file, buf);
27577 fprintf (file, "(12)\n");
27578 fprintf (file, "\tadd 2,2,12\n");
27581 fputs ("\t.localentry\t", file);
27582 assemble_name (file, name);
27583 fputs (",.-", file);
27584 assemble_name (file, name);
27585 fputs ("\n", file);
27588 /* Output -mprofile-kernel code. This needs to be done here instead of
27589 in output_function_profile since it must go after the ELFv2 ABI
27590 local entry point. */
27591 if (TARGET_PROFILE_KERNEL && crtl->profile)
27593 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27594 gcc_assert (!TARGET_32BIT);
27596 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27598 /* In the ELFv2 ABI we have no compiler stack word. It must be
27599 the resposibility of _mcount to preserve the static chain
27600 register if required. */
27601 if (DEFAULT_ABI != ABI_ELFv2
27602 && cfun->static_chain_decl != NULL)
27604 asm_fprintf (file, "\tstd %s,24(%s)\n",
27605 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27606 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27607 asm_fprintf (file, "\tld %s,24(%s)\n",
27608 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27611 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27614 rs6000_pic_labelno++;
27617 /* -mprofile-kernel code calls mcount before the function prolog,
27618 so a profiled leaf function should stay a leaf function. */
27620 rs6000_keep_leaf_when_profiled ()
27622 return TARGET_PROFILE_KERNEL;
27625 /* Non-zero if vmx regs are restored before the frame pop, zero if
27626 we restore after the pop when possible. */
27627 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27629 /* Restoring cr is a two step process: loading a reg from the frame
27630 save, then moving the reg to cr. For ABI_V4 we must let the
27631 unwinder know that the stack location is no longer valid at or
27632 before the stack deallocation, but we can't emit a cfa_restore for
27633 cr at the stack deallocation like we do for other registers.
27634 The trouble is that it is possible for the move to cr to be
27635 scheduled after the stack deallocation. So say exactly where cr
27636 is located on each of the two insns. */
27639 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27641 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27642 rtx reg = gen_rtx_REG (SImode, regno);
27643 rtx_insn *insn = emit_move_insn (reg, mem);
27645 if (!exit_func && DEFAULT_ABI == ABI_V4)
27647 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27648 rtx set = gen_rtx_SET (reg, cr);
27650 add_reg_note (insn, REG_CFA_REGISTER, set);
27651 RTX_FRAME_RELATED_P (insn) = 1;
27656 /* Reload CR from REG. */
27659 restore_saved_cr (rtx reg, bool using_mfcr_multiple, bool exit_func)
27664 if (using_mfcr_multiple)
27666 for (i = 0; i < 8; i++)
27667 if (save_reg_p (CR0_REGNO + i))
27669 gcc_assert (count);
27672 if (using_mfcr_multiple && count > 1)
27678 p = rtvec_alloc (count);
27681 for (i = 0; i < 8; i++)
27682 if (save_reg_p (CR0_REGNO + i))
27684 rtvec r = rtvec_alloc (2);
27685 RTVEC_ELT (r, 0) = reg;
27686 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27687 RTVEC_ELT (p, ndx) =
27688 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27689 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27692 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27693 gcc_assert (ndx == count);
27695 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27696 CR field separately. */
27697 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27699 for (i = 0; i < 8; i++)
27700 if (save_reg_p (CR0_REGNO + i))
27701 add_reg_note (insn, REG_CFA_RESTORE,
27702 gen_rtx_REG (SImode, CR0_REGNO + i));
27704 RTX_FRAME_RELATED_P (insn) = 1;
27708 for (i = 0; i < 8; i++)
27709 if (save_reg_p (CR0_REGNO + i))
27711 rtx insn = emit_insn (gen_movsi_to_cr_one
27712 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27714 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27715 CR field separately, attached to the insn that in fact
27716 restores this particular CR field. */
27717 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27719 add_reg_note (insn, REG_CFA_RESTORE,
27720 gen_rtx_REG (SImode, CR0_REGNO + i));
27722 RTX_FRAME_RELATED_P (insn) = 1;
27726 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27727 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27728 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27730 rtx_insn *insn = get_last_insn ();
27731 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27733 add_reg_note (insn, REG_CFA_RESTORE, cr);
27734 RTX_FRAME_RELATED_P (insn) = 1;
27738 /* Like cr, the move to lr instruction can be scheduled after the
27739 stack deallocation, but unlike cr, its stack frame save is still
27740 valid. So we only need to emit the cfa_restore on the correct
27744 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27746 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27747 rtx reg = gen_rtx_REG (Pmode, regno);
27749 emit_move_insn (reg, mem);
27753 restore_saved_lr (int regno, bool exit_func)
27755 rtx reg = gen_rtx_REG (Pmode, regno);
27756 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27757 rtx_insn *insn = emit_move_insn (lr, reg);
27759 if (!exit_func && flag_shrink_wrap)
27761 add_reg_note (insn, REG_CFA_RESTORE, lr);
27762 RTX_FRAME_RELATED_P (insn) = 1;
27767 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27769 if (DEFAULT_ABI == ABI_ELFv2)
27772 for (i = 0; i < 8; i++)
27773 if (save_reg_p (CR0_REGNO + i))
27775 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27776 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27780 else if (info->cr_save_p)
27781 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27782 gen_rtx_REG (SImode, CR2_REGNO),
27785 if (info->lr_save_p)
27786 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27787 gen_rtx_REG (Pmode, LR_REGNO),
27789 return cfa_restores;
27792 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27793 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27794 below stack pointer not cloberred by signals. */
27797 offset_below_red_zone_p (HOST_WIDE_INT offset)
27799 return offset < (DEFAULT_ABI == ABI_V4
27801 : TARGET_32BIT ? -220 : -288);
27804 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27807 emit_cfa_restores (rtx cfa_restores)
27809 rtx_insn *insn = get_last_insn ();
27810 rtx *loc = ®_NOTES (insn);
27813 loc = &XEXP (*loc, 1);
27814 *loc = cfa_restores;
27815 RTX_FRAME_RELATED_P (insn) = 1;
27818 /* Emit function epilogue as insns. */
27821 rs6000_emit_epilogue (enum epilogue_type epilogue_type)
27823 HOST_WIDE_INT frame_off = 0;
27824 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27825 rtx frame_reg_rtx = sp_reg_rtx;
27826 rtx cfa_restores = NULL_RTX;
27828 rtx cr_save_reg = NULL_RTX;
27829 machine_mode reg_mode = Pmode;
27830 int reg_size = TARGET_32BIT ? 4 : 8;
27831 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27832 int fp_reg_size = 8;
27834 unsigned ptr_regno;
27836 rs6000_stack_t *info = rs6000_stack_info ();
27838 if (epilogue_type == EPILOGUE_TYPE_NORMAL && crtl->calls_eh_return)
27839 epilogue_type = EPILOGUE_TYPE_EH_RETURN;
27841 int strategy = info->savres_strategy;
27842 bool using_load_multiple = !!(strategy & REST_MULTIPLE);
27843 bool restoring_GPRs_inline = !!(strategy & REST_INLINE_GPRS);
27844 bool restoring_FPRs_inline = !!(strategy & REST_INLINE_FPRS);
27845 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
27847 restoring_GPRs_inline = true;
27848 restoring_FPRs_inline = true;
27851 bool using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
27852 || rs6000_tune == PROCESSOR_PPC603
27853 || rs6000_tune == PROCESSOR_PPC750
27856 /* Restore via the backchain when we have a large frame, since this
27857 is more efficient than an addis, addi pair. The second condition
27858 here will not trigger at the moment; We don't actually need a
27859 frame pointer for alloca, but the generic parts of the compiler
27860 give us one anyway. */
27861 bool use_backchain_to_restore_sp
27862 = (info->total_size + (info->lr_save_p ? info->lr_save_offset : 0) > 32767
27863 || (cfun->calls_alloca && !frame_pointer_needed));
27865 bool restore_lr = (info->lr_save_p
27866 && (restoring_FPRs_inline
27867 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
27868 && (restoring_GPRs_inline
27869 || info->first_fp_reg_save < 64)
27870 && !cfun->machine->lr_is_wrapped_separately);
27873 if (WORLD_SAVE_P (info))
27875 gcc_assert (epilogue_type != EPILOGUE_TYPE_SIBCALL);
27877 /* eh_rest_world_r10 will return to the location saved in the LR
27878 stack slot (which is not likely to be our caller.)
27879 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27880 rest_world is similar, except any R10 parameter is ignored.
27881 The exception-handling stuff that was here in 2.95 is no
27882 longer necessary. */
27886 + 32 - info->first_gp_reg_save
27887 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
27888 + 63 + 1 - info->first_fp_reg_save);
27891 switch (epilogue_type)
27893 case EPILOGUE_TYPE_NORMAL:
27894 rname = ggc_strdup ("*rest_world");
27897 case EPILOGUE_TYPE_EH_RETURN:
27898 rname = ggc_strdup ("*eh_rest_world_r10");
27902 gcc_unreachable ();
27906 RTVEC_ELT (p, j++) = ret_rtx;
27908 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, rname));
27909 /* The instruction pattern requires a clobber here;
27910 it is shared with the restVEC helper. */
27911 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 11);
27914 /* CR register traditionally saved as CR2. */
27915 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
27917 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
27918 if (flag_shrink_wrap)
27920 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27921 gen_rtx_REG (Pmode, LR_REGNO),
27923 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27928 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27930 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
27932 = gen_frame_load (reg,
27933 frame_reg_rtx, info->gp_save_offset + reg_size * i);
27934 if (flag_shrink_wrap
27935 && save_reg_p (info->first_gp_reg_save + i))
27936 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27938 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27940 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
27942 = gen_frame_load (reg,
27943 frame_reg_rtx, info->altivec_save_offset + 16 * i);
27944 if (flag_shrink_wrap
27945 && save_reg_p (info->first_altivec_reg_save + i))
27946 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27948 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
27950 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
27951 info->first_fp_reg_save + i);
27953 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
27954 if (flag_shrink_wrap
27955 && save_reg_p (info->first_fp_reg_save + i))
27956 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27958 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 0);
27959 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 12);
27960 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 7);
27961 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 8);
27963 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
27964 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
27966 if (flag_shrink_wrap)
27968 REG_NOTES (insn) = cfa_restores;
27969 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27970 RTX_FRAME_RELATED_P (insn) = 1;
27975 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
27977 frame_off = info->total_size;
27979 /* Restore AltiVec registers if we must do so before adjusting the
27981 if (info->altivec_size != 0
27982 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27983 || (DEFAULT_ABI != ABI_V4
27984 && offset_below_red_zone_p (info->altivec_save_offset))))
27987 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27989 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27990 if (use_backchain_to_restore_sp)
27992 int frame_regno = 11;
27994 if ((strategy & REST_INLINE_VRS) == 0)
27996 /* Of r11 and r12, select the one not clobbered by an
27997 out-of-line restore function for the frame register. */
27998 frame_regno = 11 + 12 - scratch_regno;
28000 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28001 emit_move_insn (frame_reg_rtx,
28002 gen_rtx_MEM (Pmode, sp_reg_rtx));
28005 else if (frame_pointer_needed)
28006 frame_reg_rtx = hard_frame_pointer_rtx;
28008 if ((strategy & REST_INLINE_VRS) == 0)
28010 int end_save = info->altivec_save_offset + info->altivec_size;
28012 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28013 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28015 if (end_save + frame_off != 0)
28017 rtx offset = GEN_INT (end_save + frame_off);
28019 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28022 emit_move_insn (ptr_reg, frame_reg_rtx);
28024 ptr_off = -end_save;
28025 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28026 info->altivec_save_offset + ptr_off,
28027 0, V4SImode, SAVRES_VR);
28031 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28032 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28034 rtx addr, areg, mem, insn;
28035 rtx reg = gen_rtx_REG (V4SImode, i);
28036 HOST_WIDE_INT offset
28037 = (info->altivec_save_offset + frame_off
28038 + 16 * (i - info->first_altivec_reg_save));
28040 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28042 mem = gen_frame_mem (V4SImode,
28043 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28044 GEN_INT (offset)));
28045 insn = gen_rtx_SET (reg, mem);
28049 areg = gen_rtx_REG (Pmode, 0);
28050 emit_move_insn (areg, GEN_INT (offset));
28052 /* AltiVec addressing mode is [reg+reg]. */
28053 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28054 mem = gen_frame_mem (V4SImode, addr);
28056 /* Rather than emitting a generic move, force use of the
28057 lvx instruction, which we always want. In particular we
28058 don't want lxvd2x/xxpermdi for little endian. */
28059 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28062 (void) emit_insn (insn);
28066 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28067 if (((strategy & REST_INLINE_VRS) == 0
28068 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28069 && (flag_shrink_wrap
28070 || (offset_below_red_zone_p
28071 (info->altivec_save_offset
28072 + 16 * (i - info->first_altivec_reg_save))))
28075 rtx reg = gen_rtx_REG (V4SImode, i);
28076 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28080 /* Restore VRSAVE if we must do so before adjusting the stack. */
28081 if (info->vrsave_size != 0
28082 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28083 || (DEFAULT_ABI != ABI_V4
28084 && offset_below_red_zone_p (info->vrsave_save_offset))))
28088 if (frame_reg_rtx == sp_reg_rtx)
28090 if (use_backchain_to_restore_sp)
28092 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28093 emit_move_insn (frame_reg_rtx,
28094 gen_rtx_MEM (Pmode, sp_reg_rtx));
28097 else if (frame_pointer_needed)
28098 frame_reg_rtx = hard_frame_pointer_rtx;
28101 reg = gen_rtx_REG (SImode, 12);
28102 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28103 info->vrsave_save_offset + frame_off));
28105 emit_insn (generate_set_vrsave (reg, info, 1));
28109 /* If we have a large stack frame, restore the old stack pointer
28110 using the backchain. */
28111 if (use_backchain_to_restore_sp)
28113 if (frame_reg_rtx == sp_reg_rtx)
28115 /* Under V.4, don't reset the stack pointer until after we're done
28116 loading the saved registers. */
28117 if (DEFAULT_ABI == ABI_V4)
28118 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28120 insn = emit_move_insn (frame_reg_rtx,
28121 gen_rtx_MEM (Pmode, sp_reg_rtx));
28124 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28125 && DEFAULT_ABI == ABI_V4)
28126 /* frame_reg_rtx has been set up by the altivec restore. */
28130 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28131 frame_reg_rtx = sp_reg_rtx;
28134 /* If we have a frame pointer, we can restore the old stack pointer
28136 else if (frame_pointer_needed)
28138 frame_reg_rtx = sp_reg_rtx;
28139 if (DEFAULT_ABI == ABI_V4)
28140 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28141 /* Prevent reordering memory accesses against stack pointer restore. */
28142 else if (cfun->calls_alloca
28143 || offset_below_red_zone_p (-info->total_size))
28144 rs6000_emit_stack_tie (frame_reg_rtx, true);
28146 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28147 GEN_INT (info->total_size)));
28150 else if (info->push_p
28151 && DEFAULT_ABI != ABI_V4
28152 && epilogue_type != EPILOGUE_TYPE_EH_RETURN)
28154 /* Prevent reordering memory accesses against stack pointer restore. */
28155 if (cfun->calls_alloca
28156 || offset_below_red_zone_p (-info->total_size))
28157 rs6000_emit_stack_tie (frame_reg_rtx, false);
28158 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28159 GEN_INT (info->total_size)));
28162 if (insn && frame_reg_rtx == sp_reg_rtx)
28166 REG_NOTES (insn) = cfa_restores;
28167 cfa_restores = NULL_RTX;
28169 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28170 RTX_FRAME_RELATED_P (insn) = 1;
28173 /* Restore AltiVec registers if we have not done so already. */
28174 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28175 && info->altivec_size != 0
28176 && (DEFAULT_ABI == ABI_V4
28177 || !offset_below_red_zone_p (info->altivec_save_offset)))
28181 if ((strategy & REST_INLINE_VRS) == 0)
28183 int end_save = info->altivec_save_offset + info->altivec_size;
28185 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28186 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28187 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28189 if (end_save + frame_off != 0)
28191 rtx offset = GEN_INT (end_save + frame_off);
28193 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28196 emit_move_insn (ptr_reg, frame_reg_rtx);
28198 ptr_off = -end_save;
28199 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28200 info->altivec_save_offset + ptr_off,
28201 0, V4SImode, SAVRES_VR);
28202 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28204 /* Frame reg was clobbered by out-of-line save. Restore it
28205 from ptr_reg, and if we are calling out-of-line gpr or
28206 fpr restore set up the correct pointer and offset. */
28207 unsigned newptr_regno = 1;
28208 if (!restoring_GPRs_inline)
28210 bool lr = info->gp_save_offset + info->gp_size == 0;
28211 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28212 newptr_regno = ptr_regno_for_savres (sel);
28213 end_save = info->gp_save_offset + info->gp_size;
28215 else if (!restoring_FPRs_inline)
28217 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28218 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28219 newptr_regno = ptr_regno_for_savres (sel);
28220 end_save = info->fp_save_offset + info->fp_size;
28223 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28224 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28226 if (end_save + ptr_off != 0)
28228 rtx offset = GEN_INT (end_save + ptr_off);
28230 frame_off = -end_save;
28232 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28235 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28240 frame_off = ptr_off;
28241 emit_move_insn (frame_reg_rtx, ptr_reg);
28247 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28248 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28250 rtx addr, areg, mem, insn;
28251 rtx reg = gen_rtx_REG (V4SImode, i);
28252 HOST_WIDE_INT offset
28253 = (info->altivec_save_offset + frame_off
28254 + 16 * (i - info->first_altivec_reg_save));
28256 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28258 mem = gen_frame_mem (V4SImode,
28259 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28260 GEN_INT (offset)));
28261 insn = gen_rtx_SET (reg, mem);
28265 areg = gen_rtx_REG (Pmode, 0);
28266 emit_move_insn (areg, GEN_INT (offset));
28268 /* AltiVec addressing mode is [reg+reg]. */
28269 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28270 mem = gen_frame_mem (V4SImode, addr);
28272 /* Rather than emitting a generic move, force use of the
28273 lvx instruction, which we always want. In particular we
28274 don't want lxvd2x/xxpermdi for little endian. */
28275 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28278 (void) emit_insn (insn);
28282 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28283 if (((strategy & REST_INLINE_VRS) == 0
28284 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28285 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28288 rtx reg = gen_rtx_REG (V4SImode, i);
28289 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28293 /* Restore VRSAVE if we have not done so already. */
28294 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28295 && info->vrsave_size != 0
28296 && (DEFAULT_ABI == ABI_V4
28297 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28301 reg = gen_rtx_REG (SImode, 12);
28302 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28303 info->vrsave_save_offset + frame_off));
28305 emit_insn (generate_set_vrsave (reg, info, 1));
28308 /* If we exit by an out-of-line restore function on ABI_V4 then that
28309 function will deallocate the stack, so we don't need to worry
28310 about the unwinder restoring cr from an invalid stack frame
28312 bool exit_func = (!restoring_FPRs_inline
28313 || (!restoring_GPRs_inline
28314 && info->first_fp_reg_save == 64));
28316 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28317 *separate* slots if the routine calls __builtin_eh_return, so
28318 that they can be independently restored by the unwinder. */
28319 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28321 int i, cr_off = info->ehcr_offset;
28323 for (i = 0; i < 8; i++)
28324 if (!call_used_regs[CR0_REGNO + i])
28326 rtx reg = gen_rtx_REG (SImode, 0);
28327 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28328 cr_off + frame_off));
28330 insn = emit_insn (gen_movsi_to_cr_one
28331 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28333 if (!exit_func && flag_shrink_wrap)
28335 add_reg_note (insn, REG_CFA_RESTORE,
28336 gen_rtx_REG (SImode, CR0_REGNO + i));
28338 RTX_FRAME_RELATED_P (insn) = 1;
28341 cr_off += reg_size;
28345 /* Get the old lr if we saved it. If we are restoring registers
28346 out-of-line, then the out-of-line routines can do this for us. */
28347 if (restore_lr && restoring_GPRs_inline)
28348 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28350 /* Get the old cr if we saved it. */
28351 if (info->cr_save_p)
28353 unsigned cr_save_regno = 12;
28355 if (!restoring_GPRs_inline)
28357 /* Ensure we don't use the register used by the out-of-line
28358 gpr register restore below. */
28359 bool lr = info->gp_save_offset + info->gp_size == 0;
28360 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28361 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28363 if (gpr_ptr_regno == 12)
28364 cr_save_regno = 11;
28365 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28367 else if (REGNO (frame_reg_rtx) == 12)
28368 cr_save_regno = 11;
28370 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28371 info->cr_save_offset + frame_off,
28375 /* Set LR here to try to overlap restores below. */
28376 if (restore_lr && restoring_GPRs_inline)
28377 restore_saved_lr (0, exit_func);
28379 /* Load exception handler data registers, if needed. */
28380 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28382 unsigned int i, regno;
28386 rtx reg = gen_rtx_REG (reg_mode, 2);
28387 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28388 frame_off + RS6000_TOC_SAVE_SLOT));
28395 regno = EH_RETURN_DATA_REGNO (i);
28396 if (regno == INVALID_REGNUM)
28399 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28400 info->ehrd_offset + frame_off
28401 + reg_size * (int) i);
28403 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28407 /* Restore GPRs. This is done as a PARALLEL if we are using
28408 the load-multiple instructions. */
28409 if (!restoring_GPRs_inline)
28411 /* We are jumping to an out-of-line function. */
28413 int end_save = info->gp_save_offset + info->gp_size;
28414 bool can_use_exit = end_save == 0;
28415 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28418 /* Emit stack reset code if we need it. */
28419 ptr_regno = ptr_regno_for_savres (sel);
28420 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28422 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28423 else if (end_save + frame_off != 0)
28424 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28425 GEN_INT (end_save + frame_off)));
28426 else if (REGNO (frame_reg_rtx) != ptr_regno)
28427 emit_move_insn (ptr_reg, frame_reg_rtx);
28428 if (REGNO (frame_reg_rtx) == ptr_regno)
28429 frame_off = -end_save;
28431 if (can_use_exit && info->cr_save_p)
28432 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28434 ptr_off = -end_save;
28435 rs6000_emit_savres_rtx (info, ptr_reg,
28436 info->gp_save_offset + ptr_off,
28437 info->lr_save_offset + ptr_off,
28440 else if (using_load_multiple)
28443 p = rtvec_alloc (32 - info->first_gp_reg_save);
28444 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28446 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28448 info->gp_save_offset + frame_off + reg_size * i);
28449 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28453 int offset = info->gp_save_offset + frame_off;
28454 for (i = info->first_gp_reg_save; i < 32; i++)
28457 && !cfun->machine->gpr_is_wrapped_separately[i])
28459 rtx reg = gen_rtx_REG (reg_mode, i);
28460 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28463 offset += reg_size;
28467 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28469 /* If the frame pointer was used then we can't delay emitting
28470 a REG_CFA_DEF_CFA note. This must happen on the insn that
28471 restores the frame pointer, r31. We may have already emitted
28472 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28473 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28474 be harmless if emitted. */
28475 if (frame_pointer_needed)
28477 insn = get_last_insn ();
28478 add_reg_note (insn, REG_CFA_DEF_CFA,
28479 plus_constant (Pmode, frame_reg_rtx, frame_off));
28480 RTX_FRAME_RELATED_P (insn) = 1;
28483 /* Set up cfa_restores. We always need these when
28484 shrink-wrapping. If not shrink-wrapping then we only need
28485 the cfa_restore when the stack location is no longer valid.
28486 The cfa_restores must be emitted on or before the insn that
28487 invalidates the stack, and of course must not be emitted
28488 before the insn that actually does the restore. The latter
28489 is why it is a bad idea to emit the cfa_restores as a group
28490 on the last instruction here that actually does a restore:
28491 That insn may be reordered with respect to others doing
28493 if (flag_shrink_wrap
28494 && !restoring_GPRs_inline
28495 && info->first_fp_reg_save == 64)
28496 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28498 for (i = info->first_gp_reg_save; i < 32; i++)
28500 && !cfun->machine->gpr_is_wrapped_separately[i])
28502 rtx reg = gen_rtx_REG (reg_mode, i);
28503 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28507 if (!restoring_GPRs_inline
28508 && info->first_fp_reg_save == 64)
28510 /* We are jumping to an out-of-line function. */
28512 emit_cfa_restores (cfa_restores);
28516 if (restore_lr && !restoring_GPRs_inline)
28518 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28519 restore_saved_lr (0, exit_func);
28522 /* Restore fpr's if we need to do it without calling a function. */
28523 if (restoring_FPRs_inline)
28525 int offset = info->fp_save_offset + frame_off;
28526 for (i = info->first_fp_reg_save; i < 64; i++)
28529 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28531 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28532 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28533 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28534 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28538 offset += fp_reg_size;
28542 /* If we saved cr, restore it here. Just those that were used. */
28543 if (info->cr_save_p)
28544 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28546 /* If this is V.4, unwind the stack pointer after all of the loads
28547 have been done, or set up r11 if we are restoring fp out of line. */
28549 if (!restoring_FPRs_inline)
28551 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28552 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28553 ptr_regno = ptr_regno_for_savres (sel);
28556 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28557 if (REGNO (frame_reg_rtx) == ptr_regno)
28560 if (insn && restoring_FPRs_inline)
28564 REG_NOTES (insn) = cfa_restores;
28565 cfa_restores = NULL_RTX;
28567 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28568 RTX_FRAME_RELATED_P (insn) = 1;
28571 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28573 rtx sa = EH_RETURN_STACKADJ_RTX;
28574 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28577 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && restoring_FPRs_inline)
28581 /* We can't hang the cfa_restores off a simple return,
28582 since the shrink-wrap code sometimes uses an existing
28583 return. This means there might be a path from
28584 pre-prologue code to this return, and dwarf2cfi code
28585 wants the eh_frame unwinder state to be the same on
28586 all paths to any point. So we need to emit the
28587 cfa_restores before the return. For -m64 we really
28588 don't need epilogue cfa_restores at all, except for
28589 this irritating dwarf2cfi with shrink-wrap
28590 requirement; The stack red-zone means eh_frame info
28591 from the prologue telling the unwinder to restore
28592 from the stack is perfectly good right to the end of
28594 emit_insn (gen_blockage ());
28595 emit_cfa_restores (cfa_restores);
28596 cfa_restores = NULL_RTX;
28599 emit_jump_insn (targetm.gen_simple_return ());
28602 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && !restoring_FPRs_inline)
28604 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28605 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28607 RTVEC_ELT (p, elt++) = ret_rtx;
28609 RTVEC_ELT (p, elt++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
28611 /* We have to restore more than two FP registers, so branch to the
28612 restore function. It will return to our caller. */
28617 if (flag_shrink_wrap)
28618 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28620 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28621 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28622 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28623 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28625 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28627 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28629 RTVEC_ELT (p, elt++)
28630 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28631 if (flag_shrink_wrap
28632 && save_reg_p (info->first_fp_reg_save + i))
28633 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28636 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28641 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
28642 /* Ensure the cfa_restores are hung off an insn that won't
28643 be reordered above other restores. */
28644 emit_insn (gen_blockage ());
28646 emit_cfa_restores (cfa_restores);
28650 /* Write function epilogue. */
28653 rs6000_output_function_epilogue (FILE *file)
28656 macho_branch_islands ();
28659 rtx_insn *insn = get_last_insn ();
28660 rtx_insn *deleted_debug_label = NULL;
28662 /* Mach-O doesn't support labels at the end of objects, so if
28663 it looks like we might want one, take special action.
28665 First, collect any sequence of deleted debug labels. */
28668 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28670 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28671 notes only, instead set their CODE_LABEL_NUMBER to -1,
28672 otherwise there would be code generation differences
28673 in between -g and -g0. */
28674 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28675 deleted_debug_label = insn;
28676 insn = PREV_INSN (insn);
28679 /* Second, if we have:
28682 then this needs to be detected, so skip past the barrier. */
28684 if (insn && BARRIER_P (insn))
28685 insn = PREV_INSN (insn);
28687 /* Up to now we've only seen notes or barriers. */
28692 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28693 /* Trailing label: <barrier>. */
28694 fputs ("\tnop\n", file);
28697 /* Lastly, see if we have a completely empty function body. */
28698 while (insn && ! INSN_P (insn))
28699 insn = PREV_INSN (insn);
28700 /* If we don't find any insns, we've got an empty function body;
28701 I.e. completely empty - without a return or branch. This is
28702 taken as the case where a function body has been removed
28703 because it contains an inline __builtin_unreachable(). GCC
28704 states that reaching __builtin_unreachable() means UB so we're
28705 not obliged to do anything special; however, we want
28706 non-zero-sized function bodies. To meet this, and help the
28707 user out, let's trap the case. */
28709 fputs ("\ttrap\n", file);
28712 else if (deleted_debug_label)
28713 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28714 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28715 CODE_LABEL_NUMBER (insn) = -1;
28719 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28722 We don't output a traceback table if -finhibit-size-directive was
28723 used. The documentation for -finhibit-size-directive reads
28724 ``don't output a @code{.size} assembler directive, or anything
28725 else that would cause trouble if the function is split in the
28726 middle, and the two halves are placed at locations far apart in
28727 memory.'' The traceback table has this property, since it
28728 includes the offset from the start of the function to the
28729 traceback table itself.
28731 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28732 different traceback table. */
28733 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28734 && ! flag_inhibit_size_directive
28735 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28737 const char *fname = NULL;
28738 const char *language_string = lang_hooks.name;
28739 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28741 int optional_tbtab;
28742 rs6000_stack_t *info = rs6000_stack_info ();
28744 if (rs6000_traceback == traceback_full)
28745 optional_tbtab = 1;
28746 else if (rs6000_traceback == traceback_part)
28747 optional_tbtab = 0;
28749 optional_tbtab = !optimize_size && !TARGET_ELF;
28751 if (optional_tbtab)
28753 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28754 while (*fname == '.') /* V.4 encodes . in the name */
28757 /* Need label immediately before tbtab, so we can compute
28758 its offset from the function start. */
28759 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28760 ASM_OUTPUT_LABEL (file, fname);
28763 /* The .tbtab pseudo-op can only be used for the first eight
28764 expressions, since it can't handle the possibly variable
28765 length fields that follow. However, if you omit the optional
28766 fields, the assembler outputs zeros for all optional fields
28767 anyways, giving each variable length field is minimum length
28768 (as defined in sys/debug.h). Thus we cannot use the .tbtab
28769 pseudo-op at all. */
28771 /* An all-zero word flags the start of the tbtab, for debuggers
28772 that have to find it by searching forward from the entry
28773 point or from the current pc. */
28774 fputs ("\t.long 0\n", file);
28776 /* Tbtab format type. Use format type 0. */
28777 fputs ("\t.byte 0,", file);
28779 /* Language type. Unfortunately, there does not seem to be any
28780 official way to discover the language being compiled, so we
28781 use language_string.
28782 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28783 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28784 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28785 numbers either, so for now use 0. */
28787 || ! strcmp (language_string, "GNU GIMPLE")
28788 || ! strcmp (language_string, "GNU Go")
28789 || ! strcmp (language_string, "GNU D")
28790 || ! strcmp (language_string, "libgccjit"))
28792 else if (! strcmp (language_string, "GNU F77")
28793 || lang_GNU_Fortran ())
28795 else if (! strcmp (language_string, "GNU Ada"))
28797 else if (lang_GNU_CXX ()
28798 || ! strcmp (language_string, "GNU Objective-C++"))
28800 else if (! strcmp (language_string, "GNU Java"))
28802 else if (! strcmp (language_string, "GNU Objective-C"))
28805 gcc_unreachable ();
28806 fprintf (file, "%d,", i);
28808 /* 8 single bit fields: global linkage (not set for C extern linkage,
28809 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28810 from start of procedure stored in tbtab, internal function, function
28811 has controlled storage, function has no toc, function uses fp,
28812 function logs/aborts fp operations. */
28813 /* Assume that fp operations are used if any fp reg must be saved. */
28814 fprintf (file, "%d,",
28815 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28817 /* 6 bitfields: function is interrupt handler, name present in
28818 proc table, function calls alloca, on condition directives
28819 (controls stack walks, 3 bits), saves condition reg, saves
28821 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28822 set up as a frame pointer, even when there is no alloca call. */
28823 fprintf (file, "%d,",
28824 ((optional_tbtab << 6)
28825 | ((optional_tbtab & frame_pointer_needed) << 5)
28826 | (info->cr_save_p << 1)
28827 | (info->lr_save_p)));
28829 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28831 fprintf (file, "%d,",
28832 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28834 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28835 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28837 if (optional_tbtab)
28839 /* Compute the parameter info from the function decl argument
28842 int next_parm_info_bit = 31;
28844 for (decl = DECL_ARGUMENTS (current_function_decl);
28845 decl; decl = DECL_CHAIN (decl))
28847 rtx parameter = DECL_INCOMING_RTL (decl);
28848 machine_mode mode = GET_MODE (parameter);
28850 if (REG_P (parameter))
28852 if (SCALAR_FLOAT_MODE_P (mode))
28875 gcc_unreachable ();
28878 /* If only one bit will fit, don't or in this entry. */
28879 if (next_parm_info_bit > 0)
28880 parm_info |= (bits << (next_parm_info_bit - 1));
28881 next_parm_info_bit -= 2;
28885 fixed_parms += ((GET_MODE_SIZE (mode)
28886 + (UNITS_PER_WORD - 1))
28888 next_parm_info_bit -= 1;
28894 /* Number of fixed point parameters. */
28895 /* This is actually the number of words of fixed point parameters; thus
28896 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28897 fprintf (file, "%d,", fixed_parms);
28899 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28901 /* This is actually the number of fp registers that hold parameters;
28902 and thus the maximum value is 13. */
28903 /* Set parameters on stack bit if parameters are not in their original
28904 registers, regardless of whether they are on the stack? Xlc
28905 seems to set the bit when not optimizing. */
28906 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
28908 if (optional_tbtab)
28910 /* Optional fields follow. Some are variable length. */
28912 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28913 float, 11 double float. */
28914 /* There is an entry for each parameter in a register, in the order
28915 that they occur in the parameter list. Any intervening arguments
28916 on the stack are ignored. If the list overflows a long (max
28917 possible length 34 bits) then completely leave off all elements
28919 /* Only emit this long if there was at least one parameter. */
28920 if (fixed_parms || float_parms)
28921 fprintf (file, "\t.long %d\n", parm_info);
28923 /* Offset from start of code to tb table. */
28924 fputs ("\t.long ", file);
28925 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28926 RS6000_OUTPUT_BASENAME (file, fname);
28928 rs6000_output_function_entry (file, fname);
28931 /* Interrupt handler mask. */
28932 /* Omit this long, since we never set the interrupt handler bit
28935 /* Number of CTL (controlled storage) anchors. */
28936 /* Omit this long, since the has_ctl bit is never set above. */
28938 /* Displacement into stack of each CTL anchor. */
28939 /* Omit this list of longs, because there are no CTL anchors. */
28941 /* Length of function name. */
28944 fprintf (file, "\t.short %d\n", (int) strlen (fname));
28946 /* Function name. */
28947 assemble_string (fname, strlen (fname));
28949 /* Register for alloca automatic storage; this is always reg 31.
28950 Only emit this if the alloca bit was set above. */
28951 if (frame_pointer_needed)
28952 fputs ("\t.byte 31\n", file);
28954 fputs ("\t.align 2\n", file);
28958 /* Arrange to define .LCTOC1 label, if not already done. */
28962 if (!toc_initialized)
28964 switch_to_section (toc_section);
28965 switch_to_section (current_function_section ());
28970 /* -fsplit-stack support. */
28972 /* A SYMBOL_REF for __morestack. */
28973 static GTY(()) rtx morestack_ref;
28976 gen_add3_const (rtx rt, rtx ra, long c)
28979 return gen_adddi3 (rt, ra, GEN_INT (c));
28981 return gen_addsi3 (rt, ra, GEN_INT (c));
28984 /* Emit -fsplit-stack prologue, which goes before the regular function
28985 prologue (at local entry point in the case of ELFv2). */
28988 rs6000_expand_split_stack_prologue (void)
28990 rs6000_stack_t *info = rs6000_stack_info ();
28991 unsigned HOST_WIDE_INT allocate;
28992 long alloc_hi, alloc_lo;
28993 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
28996 gcc_assert (flag_split_stack && reload_completed);
29001 if (global_regs[29])
29003 error ("%qs uses register r29", "%<-fsplit-stack%>");
29004 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29005 "conflicts with %qD", global_regs_decl[29]);
29008 allocate = info->total_size;
29009 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29011 sorry ("Stack frame larger than 2G is not supported for "
29012 "%<-fsplit-stack%>");
29015 if (morestack_ref == NULL_RTX)
29017 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29018 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29019 | SYMBOL_FLAG_FUNCTION);
29022 r0 = gen_rtx_REG (Pmode, 0);
29023 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29024 r12 = gen_rtx_REG (Pmode, 12);
29025 emit_insn (gen_load_split_stack_limit (r0));
29026 /* Always emit two insns here to calculate the requested stack,
29027 so that the linker can edit them when adjusting size for calling
29028 non-split-stack code. */
29029 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29030 alloc_lo = -allocate - alloc_hi;
29033 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29035 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29037 emit_insn (gen_nop ());
29041 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29042 emit_insn (gen_nop ());
29045 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29046 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29047 ok_label = gen_label_rtx ();
29048 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29049 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29050 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29052 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29053 JUMP_LABEL (insn) = ok_label;
29054 /* Mark the jump as very likely to be taken. */
29055 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29057 lr = gen_rtx_REG (Pmode, LR_REGNO);
29058 insn = emit_move_insn (r0, lr);
29059 RTX_FRAME_RELATED_P (insn) = 1;
29060 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29061 RTX_FRAME_RELATED_P (insn) = 1;
29063 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29064 const0_rtx, const0_rtx));
29065 call_fusage = NULL_RTX;
29066 use_reg (&call_fusage, r12);
29067 /* Say the call uses r0, even though it doesn't, to stop regrename
29068 from twiddling with the insns saving lr, trashing args for cfun.
29069 The insns restoring lr are similarly protected by making
29070 split_stack_return use r0. */
29071 use_reg (&call_fusage, r0);
29072 add_function_usage_to (insn, call_fusage);
29073 /* Indicate that this function can't jump to non-local gotos. */
29074 make_reg_eh_region_note_nothrow_nononlocal (insn);
29075 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29076 insn = emit_move_insn (lr, r0);
29077 add_reg_note (insn, REG_CFA_RESTORE, lr);
29078 RTX_FRAME_RELATED_P (insn) = 1;
29079 emit_insn (gen_split_stack_return ());
29081 emit_label (ok_label);
29082 LABEL_NUSES (ok_label) = 1;
29085 /* Return the internal arg pointer used for function incoming
29086 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29087 to copy it to a pseudo in order for it to be preserved over calls
29088 and suchlike. We'd really like to use a pseudo here for the
29089 internal arg pointer but data-flow analysis is not prepared to
29090 accept pseudos as live at the beginning of a function. */
29093 rs6000_internal_arg_pointer (void)
29095 if (flag_split_stack
29096 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29100 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29104 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29105 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29107 /* Put the pseudo initialization right after the note at the
29108 beginning of the function. */
29109 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29110 gen_rtx_REG (Pmode, 12));
29111 push_topmost_sequence ();
29112 emit_insn_after (pat, get_insns ());
29113 pop_topmost_sequence ();
29115 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29116 FIRST_PARM_OFFSET (current_function_decl));
29117 return copy_to_reg (ret);
29119 return virtual_incoming_args_rtx;
29122 /* We may have to tell the dataflow pass that the split stack prologue
29123 is initializing a register. */
29126 rs6000_live_on_entry (bitmap regs)
29128 if (flag_split_stack)
29129 bitmap_set_bit (regs, 12);
29132 /* Emit -fsplit-stack dynamic stack allocation space check. */
29135 rs6000_split_stack_space_check (rtx size, rtx label)
29137 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29138 rtx limit = gen_reg_rtx (Pmode);
29139 rtx requested = gen_reg_rtx (Pmode);
29140 rtx cmp = gen_reg_rtx (CCUNSmode);
29143 emit_insn (gen_load_split_stack_limit (limit));
29144 if (CONST_INT_P (size))
29145 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29148 size = force_reg (Pmode, size);
29149 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29151 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29152 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29153 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29154 gen_rtx_LABEL_REF (VOIDmode, label),
29156 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29157 JUMP_LABEL (jump) = label;
29160 /* A C compound statement that outputs the assembler code for a thunk
29161 function, used to implement C++ virtual function calls with
29162 multiple inheritance. The thunk acts as a wrapper around a virtual
29163 function, adjusting the implicit object parameter before handing
29164 control off to the real function.
29166 First, emit code to add the integer DELTA to the location that
29167 contains the incoming first argument. Assume that this argument
29168 contains a pointer, and is the one used to pass the `this' pointer
29169 in C++. This is the incoming argument *before* the function
29170 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29171 values of all other incoming arguments.
29173 After the addition, emit code to jump to FUNCTION, which is a
29174 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29175 not touch the return address. Hence returning from FUNCTION will
29176 return to whoever called the current `thunk'.
29178 The effect must be as if FUNCTION had been called directly with the
29179 adjusted first argument. This macro is responsible for emitting
29180 all of the code for a thunk function; output_function_prologue()
29181 and output_function_epilogue() are not invoked.
29183 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29184 been extracted from it.) It might possibly be useful on some
29185 targets, but probably not.
29187 If you do not define this macro, the target-independent code in the
29188 C++ frontend will generate a less efficient heavyweight thunk that
29189 calls FUNCTION instead of jumping to it. The generic approach does
29190 not support varargs. */
29193 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29194 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29197 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
29198 rtx this_rtx, funexp;
29201 reload_completed = 1;
29202 epilogue_completed = 1;
29204 /* Mark the end of the (empty) prologue. */
29205 emit_note (NOTE_INSN_PROLOGUE_END);
29207 /* Find the "this" pointer. If the function returns a structure,
29208 the structure return pointer is in r3. */
29209 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29210 this_rtx = gen_rtx_REG (Pmode, 4);
29212 this_rtx = gen_rtx_REG (Pmode, 3);
29214 /* Apply the constant offset, if required. */
29216 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29218 /* Apply the offset from the vtable, if required. */
29221 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29222 rtx tmp = gen_rtx_REG (Pmode, 12);
29224 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29225 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29227 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29228 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29232 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29234 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29236 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29239 /* Generate a tail call to the target function. */
29240 if (!TREE_USED (function))
29242 assemble_external (function);
29243 TREE_USED (function) = 1;
29245 funexp = XEXP (DECL_RTL (function), 0);
29246 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29249 if (MACHOPIC_INDIRECT)
29250 funexp = machopic_indirect_call_target (funexp);
29253 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29254 generate sibcall RTL explicitly. */
29255 insn = emit_call_insn (
29256 gen_rtx_PARALLEL (VOIDmode,
29258 gen_rtx_CALL (VOIDmode,
29259 funexp, const0_rtx),
29260 gen_rtx_USE (VOIDmode, const0_rtx),
29261 simple_return_rtx)));
29262 SIBLING_CALL_P (insn) = 1;
29265 /* Run just enough of rest_of_compilation to get the insns emitted.
29266 There's not really enough bulk here to make other passes such as
29267 instruction scheduling worth while. Note that use_thunk calls
29268 assemble_start_function and assemble_end_function. */
29269 insn = get_insns ();
29270 shorten_branches (insn);
29271 assemble_start_function (thunk_fndecl, fnname);
29272 final_start_function (insn, file, 1);
29273 final (insn, file, 1);
29274 final_end_function ();
29275 assemble_end_function (thunk_fndecl, fnname);
29277 reload_completed = 0;
29278 epilogue_completed = 0;
29281 /* A quick summary of the various types of 'constant-pool tables'
29284 Target Flags Name One table per
29285 AIX (none) AIX TOC object file
29286 AIX -mfull-toc AIX TOC object file
29287 AIX -mminimal-toc AIX minimal TOC translation unit
29288 SVR4/EABI (none) SVR4 SDATA object file
29289 SVR4/EABI -fpic SVR4 pic object file
29290 SVR4/EABI -fPIC SVR4 PIC translation unit
29291 SVR4/EABI -mrelocatable EABI TOC function
29292 SVR4/EABI -maix AIX TOC object file
29293 SVR4/EABI -maix -mminimal-toc
29294 AIX minimal TOC translation unit
29296 Name Reg. Set by entries contains:
29297 made by addrs? fp? sum?
29299 AIX TOC 2 crt0 as Y option option
29300 AIX minimal TOC 30 prolog gcc Y Y option
29301 SVR4 SDATA 13 crt0 gcc N Y N
29302 SVR4 pic 30 prolog ld Y not yet N
29303 SVR4 PIC 30 prolog gcc Y option option
29304 EABI TOC 30 prolog gcc Y option option
29308 /* Hash functions for the hash table. */
29311 rs6000_hash_constant (rtx k)
29313 enum rtx_code code = GET_CODE (k);
29314 machine_mode mode = GET_MODE (k);
29315 unsigned result = (code << 3) ^ mode;
29316 const char *format;
29319 format = GET_RTX_FORMAT (code);
29320 flen = strlen (format);
29326 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29328 case CONST_WIDE_INT:
29331 flen = CONST_WIDE_INT_NUNITS (k);
29332 for (i = 0; i < flen; i++)
29333 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29338 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29348 for (; fidx < flen; fidx++)
29349 switch (format[fidx])
29354 const char *str = XSTR (k, fidx);
29355 len = strlen (str);
29356 result = result * 613 + len;
29357 for (i = 0; i < len; i++)
29358 result = result * 613 + (unsigned) str[i];
29363 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29367 result = result * 613 + (unsigned) XINT (k, fidx);
29370 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29371 result = result * 613 + (unsigned) XWINT (k, fidx);
29375 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29376 result = result * 613 + (unsigned) (XWINT (k, fidx)
29383 gcc_unreachable ();
29390 toc_hasher::hash (toc_hash_struct *thc)
29392 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29395 /* Compare H1 and H2 for equivalence. */
29398 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29403 if (h1->key_mode != h2->key_mode)
29406 return rtx_equal_p (r1, r2);
29409 /* These are the names given by the C++ front-end to vtables, and
29410 vtable-like objects. Ideally, this logic should not be here;
29411 instead, there should be some programmatic way of inquiring as
29412 to whether or not an object is a vtable. */
29414 #define VTABLE_NAME_P(NAME) \
29415 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29416 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29417 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29418 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29419 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29421 #ifdef NO_DOLLAR_IN_LABEL
29422 /* Return a GGC-allocated character string translating dollar signs in
29423 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29426 rs6000_xcoff_strip_dollar (const char *name)
29432 q = (const char *) strchr (name, '$');
29434 if (q == 0 || q == name)
29437 len = strlen (name);
29438 strip = XALLOCAVEC (char, len + 1);
29439 strcpy (strip, name);
29440 p = strip + (q - name);
29444 p = strchr (p + 1, '$');
29447 return ggc_alloc_string (strip, len);
29452 rs6000_output_symbol_ref (FILE *file, rtx x)
29454 const char *name = XSTR (x, 0);
29456 /* Currently C++ toc references to vtables can be emitted before it
29457 is decided whether the vtable is public or private. If this is
29458 the case, then the linker will eventually complain that there is
29459 a reference to an unknown section. Thus, for vtables only,
29460 we emit the TOC reference to reference the identifier and not the
29462 if (VTABLE_NAME_P (name))
29464 RS6000_OUTPUT_BASENAME (file, name);
29467 assemble_name (file, name);
29470 /* Output a TOC entry. We derive the entry name from what is being
29474 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29477 const char *name = buf;
29479 HOST_WIDE_INT offset = 0;
29481 gcc_assert (!TARGET_NO_TOC);
29483 /* When the linker won't eliminate them, don't output duplicate
29484 TOC entries (this happens on AIX if there is any kind of TOC,
29485 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29487 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29489 struct toc_hash_struct *h;
29491 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29492 time because GGC is not initialized at that point. */
29493 if (toc_hash_table == NULL)
29494 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29496 h = ggc_alloc<toc_hash_struct> ();
29498 h->key_mode = mode;
29499 h->labelno = labelno;
29501 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29502 if (*found == NULL)
29504 else /* This is indeed a duplicate.
29505 Set this label equal to that label. */
29507 fputs ("\t.set ", file);
29508 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29509 fprintf (file, "%d,", labelno);
29510 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29511 fprintf (file, "%d\n", ((*found)->labelno));
29514 if (TARGET_XCOFF && SYMBOL_REF_P (x)
29515 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29516 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29518 fputs ("\t.set ", file);
29519 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29520 fprintf (file, "%d,", labelno);
29521 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29522 fprintf (file, "%d\n", ((*found)->labelno));
29529 /* If we're going to put a double constant in the TOC, make sure it's
29530 aligned properly when strict alignment is on. */
29531 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29532 && STRICT_ALIGNMENT
29533 && GET_MODE_BITSIZE (mode) >= 64
29534 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29535 ASM_OUTPUT_ALIGN (file, 3);
29538 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29540 /* Handle FP constants specially. Note that if we have a minimal
29541 TOC, things we put here aren't actually in the TOC, so we can allow
29543 if (CONST_DOUBLE_P (x)
29544 && (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29545 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29549 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29550 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29552 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29556 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29557 fputs (DOUBLE_INT_ASM_OP, file);
29559 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29560 k[0] & 0xffffffff, k[1] & 0xffffffff,
29561 k[2] & 0xffffffff, k[3] & 0xffffffff);
29562 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29563 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29564 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29565 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29566 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29571 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29572 fputs ("\t.long ", file);
29574 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29575 k[0] & 0xffffffff, k[1] & 0xffffffff,
29576 k[2] & 0xffffffff, k[3] & 0xffffffff);
29577 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29578 k[0] & 0xffffffff, k[1] & 0xffffffff,
29579 k[2] & 0xffffffff, k[3] & 0xffffffff);
29583 else if (CONST_DOUBLE_P (x)
29584 && (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29588 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29589 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29591 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29595 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29596 fputs (DOUBLE_INT_ASM_OP, file);
29598 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29599 k[0] & 0xffffffff, k[1] & 0xffffffff);
29600 fprintf (file, "0x%lx%08lx\n",
29601 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29602 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29607 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29608 fputs ("\t.long ", file);
29610 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29611 k[0] & 0xffffffff, k[1] & 0xffffffff);
29612 fprintf (file, "0x%lx,0x%lx\n",
29613 k[0] & 0xffffffff, k[1] & 0xffffffff);
29617 else if (CONST_DOUBLE_P (x)
29618 && (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29622 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29623 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29625 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29629 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29630 fputs (DOUBLE_INT_ASM_OP, file);
29632 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29633 if (WORDS_BIG_ENDIAN)
29634 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29636 fprintf (file, "0x%lx\n", l & 0xffffffff);
29641 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29642 fputs ("\t.long ", file);
29644 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29645 fprintf (file, "0x%lx\n", l & 0xffffffff);
29649 else if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
29651 unsigned HOST_WIDE_INT low;
29652 HOST_WIDE_INT high;
29654 low = INTVAL (x) & 0xffffffff;
29655 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29657 /* TOC entries are always Pmode-sized, so when big-endian
29658 smaller integer constants in the TOC need to be padded.
29659 (This is still a win over putting the constants in
29660 a separate constant pool, because then we'd have
29661 to have both a TOC entry _and_ the actual constant.)
29663 For a 32-bit target, CONST_INT values are loaded and shifted
29664 entirely within `low' and can be stored in one TOC entry. */
29666 /* It would be easy to make this work, but it doesn't now. */
29667 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29669 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29672 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29673 high = (HOST_WIDE_INT) low >> 32;
29679 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29680 fputs (DOUBLE_INT_ASM_OP, file);
29682 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29683 (long) high & 0xffffffff, (long) low & 0xffffffff);
29684 fprintf (file, "0x%lx%08lx\n",
29685 (long) high & 0xffffffff, (long) low & 0xffffffff);
29690 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29692 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29693 fputs ("\t.long ", file);
29695 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29696 (long) high & 0xffffffff, (long) low & 0xffffffff);
29697 fprintf (file, "0x%lx,0x%lx\n",
29698 (long) high & 0xffffffff, (long) low & 0xffffffff);
29702 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29703 fputs ("\t.long ", file);
29705 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29706 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29712 if (GET_CODE (x) == CONST)
29714 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29715 && CONST_INT_P (XEXP (XEXP (x, 0), 1)));
29717 base = XEXP (XEXP (x, 0), 0);
29718 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29721 switch (GET_CODE (base))
29724 name = XSTR (base, 0);
29728 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29729 CODE_LABEL_NUMBER (XEXP (base, 0)));
29733 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29737 gcc_unreachable ();
29740 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29741 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29744 fputs ("\t.tc ", file);
29745 RS6000_OUTPUT_BASENAME (file, name);
29748 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29750 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29752 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29753 after other TOC symbols, reducing overflow of small TOC access
29754 to [TC] symbols. */
29755 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29756 ? "[TE]," : "[TC],", file);
29759 /* Currently C++ toc references to vtables can be emitted before it
29760 is decided whether the vtable is public or private. If this is
29761 the case, then the linker will eventually complain that there is
29762 a TOC reference to an unknown section. Thus, for vtables only,
29763 we emit the TOC reference to reference the symbol and not the
29765 if (VTABLE_NAME_P (name))
29767 RS6000_OUTPUT_BASENAME (file, name);
29769 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29770 else if (offset > 0)
29771 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29774 output_addr_const (file, x);
29777 if (TARGET_XCOFF && SYMBOL_REF_P (base))
29779 switch (SYMBOL_REF_TLS_MODEL (base))
29783 case TLS_MODEL_LOCAL_EXEC:
29784 fputs ("@le", file);
29786 case TLS_MODEL_INITIAL_EXEC:
29787 fputs ("@ie", file);
29789 /* Use global-dynamic for local-dynamic. */
29790 case TLS_MODEL_GLOBAL_DYNAMIC:
29791 case TLS_MODEL_LOCAL_DYNAMIC:
29793 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29794 fputs ("\t.tc .", file);
29795 RS6000_OUTPUT_BASENAME (file, name);
29796 fputs ("[TC],", file);
29797 output_addr_const (file, x);
29798 fputs ("@m", file);
29801 gcc_unreachable ();
29809 /* Output an assembler pseudo-op to write an ASCII string of N characters
29810 starting at P to FILE.
29812 On the RS/6000, we have to do this using the .byte operation and
29813 write out special characters outside the quoted string.
29814 Also, the assembler is broken; very long strings are truncated,
29815 so we must artificially break them up early. */
29818 output_ascii (FILE *file, const char *p, int n)
29821 int i, count_string;
29822 const char *for_string = "\t.byte \"";
29823 const char *for_decimal = "\t.byte ";
29824 const char *to_close = NULL;
29827 for (i = 0; i < n; i++)
29830 if (c >= ' ' && c < 0177)
29833 fputs (for_string, file);
29836 /* Write two quotes to get one. */
29844 for_decimal = "\"\n\t.byte ";
29848 if (count_string >= 512)
29850 fputs (to_close, file);
29852 for_string = "\t.byte \"";
29853 for_decimal = "\t.byte ";
29861 fputs (for_decimal, file);
29862 fprintf (file, "%d", c);
29864 for_string = "\n\t.byte \"";
29865 for_decimal = ", ";
29871 /* Now close the string if we have written one. Then end the line. */
29873 fputs (to_close, file);
29876 /* Generate a unique section name for FILENAME for a section type
29877 represented by SECTION_DESC. Output goes into BUF.
29879 SECTION_DESC can be any string, as long as it is different for each
29880 possible section type.
29882 We name the section in the same manner as xlc. The name begins with an
29883 underscore followed by the filename (after stripping any leading directory
29884 names) with the last period replaced by the string SECTION_DESC. If
29885 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29889 rs6000_gen_section_name (char **buf, const char *filename,
29890 const char *section_desc)
29892 const char *q, *after_last_slash, *last_period = 0;
29896 after_last_slash = filename;
29897 for (q = filename; *q; q++)
29900 after_last_slash = q + 1;
29901 else if (*q == '.')
29905 len = strlen (after_last_slash) + strlen (section_desc) + 2;
29906 *buf = (char *) xmalloc (len);
29911 for (q = after_last_slash; *q; q++)
29913 if (q == last_period)
29915 strcpy (p, section_desc);
29916 p += strlen (section_desc);
29920 else if (ISALNUM (*q))
29924 if (last_period == 0)
29925 strcpy (p, section_desc);
29930 /* Emit profile function. */
29933 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
29935 /* Non-standard profiling for kernels, which just saves LR then calls
29936 _mcount without worrying about arg saves. The idea is to change
29937 the function prologue as little as possible as it isn't easy to
29938 account for arg save/restore code added just for _mcount. */
29939 if (TARGET_PROFILE_KERNEL)
29942 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29944 #ifndef NO_PROFILE_COUNTERS
29945 # define NO_PROFILE_COUNTERS 0
29947 if (NO_PROFILE_COUNTERS)
29948 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29949 LCT_NORMAL, VOIDmode);
29953 const char *label_name;
29956 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29957 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
29958 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
29960 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29961 LCT_NORMAL, VOIDmode, fun, Pmode);
29964 else if (DEFAULT_ABI == ABI_DARWIN)
29966 const char *mcount_name = RS6000_MCOUNT;
29967 int caller_addr_regno = LR_REGNO;
29969 /* Be conservative and always set this, at least for now. */
29970 crtl->uses_pic_offset_table = 1;
29973 /* For PIC code, set up a stub and collect the caller's address
29974 from r0, which is where the prologue puts it. */
29975 if (MACHOPIC_INDIRECT
29976 && crtl->uses_pic_offset_table)
29977 caller_addr_regno = 0;
29979 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
29980 LCT_NORMAL, VOIDmode,
29981 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
29985 /* Write function profiler code. */
29988 output_function_profiler (FILE *file, int labelno)
29992 switch (DEFAULT_ABI)
29995 gcc_unreachable ();
30000 warning (0, "no profiling of 64-bit code for this ABI");
30003 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30004 fprintf (file, "\tmflr %s\n", reg_names[0]);
30005 if (NO_PROFILE_COUNTERS)
30007 asm_fprintf (file, "\tstw %s,4(%s)\n",
30008 reg_names[0], reg_names[1]);
30010 else if (TARGET_SECURE_PLT && flag_pic)
30012 if (TARGET_LINK_STACK)
30015 get_ppc476_thunk_name (name);
30016 asm_fprintf (file, "\tbl %s\n", name);
30019 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30020 asm_fprintf (file, "\tstw %s,4(%s)\n",
30021 reg_names[0], reg_names[1]);
30022 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30023 asm_fprintf (file, "\taddis %s,%s,",
30024 reg_names[12], reg_names[12]);
30025 assemble_name (file, buf);
30026 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30027 assemble_name (file, buf);
30028 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30030 else if (flag_pic == 1)
30032 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30033 asm_fprintf (file, "\tstw %s,4(%s)\n",
30034 reg_names[0], reg_names[1]);
30035 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30036 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30037 assemble_name (file, buf);
30038 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30040 else if (flag_pic > 1)
30042 asm_fprintf (file, "\tstw %s,4(%s)\n",
30043 reg_names[0], reg_names[1]);
30044 /* Now, we need to get the address of the label. */
30045 if (TARGET_LINK_STACK)
30048 get_ppc476_thunk_name (name);
30049 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30050 assemble_name (file, buf);
30051 fputs ("-.\n1:", file);
30052 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30053 asm_fprintf (file, "\taddi %s,%s,4\n",
30054 reg_names[11], reg_names[11]);
30058 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30059 assemble_name (file, buf);
30060 fputs ("-.\n1:", file);
30061 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30063 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30064 reg_names[0], reg_names[11]);
30065 asm_fprintf (file, "\tadd %s,%s,%s\n",
30066 reg_names[0], reg_names[0], reg_names[11]);
30070 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30071 assemble_name (file, buf);
30072 fputs ("@ha\n", file);
30073 asm_fprintf (file, "\tstw %s,4(%s)\n",
30074 reg_names[0], reg_names[1]);
30075 asm_fprintf (file, "\tla %s,", reg_names[0]);
30076 assemble_name (file, buf);
30077 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30080 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30081 fprintf (file, "\tbl %s%s\n",
30082 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30088 /* Don't do anything, done in output_profile_hook (). */
30095 /* The following variable value is the last issued insn. */
30097 static rtx_insn *last_scheduled_insn;
30099 /* The following variable helps to balance issuing of load and
30100 store instructions */
30102 static int load_store_pendulum;
30104 /* The following variable helps pair divide insns during scheduling. */
30105 static int divide_cnt;
30106 /* The following variable helps pair and alternate vector and vector load
30107 insns during scheduling. */
30108 static int vec_pairing;
30111 /* Power4 load update and store update instructions are cracked into a
30112 load or store and an integer insn which are executed in the same cycle.
30113 Branches have their own dispatch slot which does not count against the
30114 GCC issue rate, but it changes the program flow so there are no other
30115 instructions to issue in this cycle. */
30118 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30120 last_scheduled_insn = insn;
30121 if (GET_CODE (PATTERN (insn)) == USE
30122 || GET_CODE (PATTERN (insn)) == CLOBBER)
30124 cached_can_issue_more = more;
30125 return cached_can_issue_more;
30128 if (insn_terminates_group_p (insn, current_group))
30130 cached_can_issue_more = 0;
30131 return cached_can_issue_more;
30134 /* If no reservation, but reach here */
30135 if (recog_memoized (insn) < 0)
30138 if (rs6000_sched_groups)
30140 if (is_microcoded_insn (insn))
30141 cached_can_issue_more = 0;
30142 else if (is_cracked_insn (insn))
30143 cached_can_issue_more = more > 2 ? more - 2 : 0;
30145 cached_can_issue_more = more - 1;
30147 return cached_can_issue_more;
30150 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30153 cached_can_issue_more = more - 1;
30154 return cached_can_issue_more;
30158 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30160 int r = rs6000_variable_issue_1 (insn, more);
30162 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30166 /* Adjust the cost of a scheduling dependency. Return the new cost of
30167 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30170 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30173 enum attr_type attr_type;
30175 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30182 /* Data dependency; DEP_INSN writes a register that INSN reads
30183 some cycles later. */
30185 /* Separate a load from a narrower, dependent store. */
30186 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30187 && GET_CODE (PATTERN (insn)) == SET
30188 && GET_CODE (PATTERN (dep_insn)) == SET
30189 && MEM_P (XEXP (PATTERN (insn), 1))
30190 && MEM_P (XEXP (PATTERN (dep_insn), 0))
30191 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30192 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30195 attr_type = get_attr_type (insn);
30200 /* Tell the first scheduling pass about the latency between
30201 a mtctr and bctr (and mtlr and br/blr). The first
30202 scheduling pass will not know about this latency since
30203 the mtctr instruction, which has the latency associated
30204 to it, will be generated by reload. */
30207 /* Leave some extra cycles between a compare and its
30208 dependent branch, to inhibit expensive mispredicts. */
30209 if ((rs6000_tune == PROCESSOR_PPC603
30210 || rs6000_tune == PROCESSOR_PPC604
30211 || rs6000_tune == PROCESSOR_PPC604e
30212 || rs6000_tune == PROCESSOR_PPC620
30213 || rs6000_tune == PROCESSOR_PPC630
30214 || rs6000_tune == PROCESSOR_PPC750
30215 || rs6000_tune == PROCESSOR_PPC7400
30216 || rs6000_tune == PROCESSOR_PPC7450
30217 || rs6000_tune == PROCESSOR_PPCE5500
30218 || rs6000_tune == PROCESSOR_PPCE6500
30219 || rs6000_tune == PROCESSOR_POWER4
30220 || rs6000_tune == PROCESSOR_POWER5
30221 || rs6000_tune == PROCESSOR_POWER7
30222 || rs6000_tune == PROCESSOR_POWER8
30223 || rs6000_tune == PROCESSOR_POWER9
30224 || rs6000_tune == PROCESSOR_CELL)
30225 && recog_memoized (dep_insn)
30226 && (INSN_CODE (dep_insn) >= 0))
30228 switch (get_attr_type (dep_insn))
30231 case TYPE_FPCOMPARE:
30232 case TYPE_CR_LOGICAL:
30236 if (get_attr_dot (dep_insn) == DOT_YES)
30241 if (get_attr_dot (dep_insn) == DOT_YES
30242 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30253 if ((rs6000_tune == PROCESSOR_POWER6)
30254 && recog_memoized (dep_insn)
30255 && (INSN_CODE (dep_insn) >= 0))
30258 if (GET_CODE (PATTERN (insn)) != SET)
30259 /* If this happens, we have to extend this to schedule
30260 optimally. Return default for now. */
30263 /* Adjust the cost for the case where the value written
30264 by a fixed point operation is used as the address
30265 gen value on a store. */
30266 switch (get_attr_type (dep_insn))
30271 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30272 return get_attr_sign_extend (dep_insn)
30273 == SIGN_EXTEND_YES ? 6 : 4;
30278 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30279 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30289 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30297 if (get_attr_update (dep_insn) == UPDATE_YES
30298 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30304 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30310 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30311 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30321 if ((rs6000_tune == PROCESSOR_POWER6)
30322 && recog_memoized (dep_insn)
30323 && (INSN_CODE (dep_insn) >= 0))
30326 /* Adjust the cost for the case where the value written
30327 by a fixed point instruction is used within the address
30328 gen portion of a subsequent load(u)(x) */
30329 switch (get_attr_type (dep_insn))
30334 if (set_to_load_agen (dep_insn, insn))
30335 return get_attr_sign_extend (dep_insn)
30336 == SIGN_EXTEND_YES ? 6 : 4;
30341 if (set_to_load_agen (dep_insn, insn))
30342 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30352 if (set_to_load_agen (dep_insn, insn))
30360 if (get_attr_update (dep_insn) == UPDATE_YES
30361 && set_to_load_agen (dep_insn, insn))
30367 if (set_to_load_agen (dep_insn, insn))
30373 if (set_to_load_agen (dep_insn, insn))
30374 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30384 if ((rs6000_tune == PROCESSOR_POWER6)
30385 && get_attr_update (insn) == UPDATE_NO
30386 && recog_memoized (dep_insn)
30387 && (INSN_CODE (dep_insn) >= 0)
30388 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30395 /* Fall out to return default cost. */
30399 case REG_DEP_OUTPUT:
30400 /* Output dependency; DEP_INSN writes a register that INSN writes some
30402 if ((rs6000_tune == PROCESSOR_POWER6)
30403 && recog_memoized (dep_insn)
30404 && (INSN_CODE (dep_insn) >= 0))
30406 attr_type = get_attr_type (insn);
30411 case TYPE_FPSIMPLE:
30412 if (get_attr_type (dep_insn) == TYPE_FP
30413 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30417 if (get_attr_update (insn) == UPDATE_NO
30418 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30425 /* Fall through, no cost for output dependency. */
30429 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30434 gcc_unreachable ();
30440 /* Debug version of rs6000_adjust_cost. */
30443 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30444 int cost, unsigned int dw)
30446 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30454 default: dep = "unknown depencency"; break;
30455 case REG_DEP_TRUE: dep = "data dependency"; break;
30456 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30457 case REG_DEP_ANTI: dep = "anti depencency"; break;
30461 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30462 "%s, insn:\n", ret, cost, dep);
30470 /* The function returns a true if INSN is microcoded.
30471 Return false otherwise. */
30474 is_microcoded_insn (rtx_insn *insn)
30476 if (!insn || !NONDEBUG_INSN_P (insn)
30477 || GET_CODE (PATTERN (insn)) == USE
30478 || GET_CODE (PATTERN (insn)) == CLOBBER)
30481 if (rs6000_tune == PROCESSOR_CELL)
30482 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30484 if (rs6000_sched_groups
30485 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30487 enum attr_type type = get_attr_type (insn);
30488 if ((type == TYPE_LOAD
30489 && get_attr_update (insn) == UPDATE_YES
30490 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30491 || ((type == TYPE_LOAD || type == TYPE_STORE)
30492 && get_attr_update (insn) == UPDATE_YES
30493 && get_attr_indexed (insn) == INDEXED_YES)
30494 || type == TYPE_MFCR)
30501 /* The function returns true if INSN is cracked into 2 instructions
30502 by the processor (and therefore occupies 2 issue slots). */
30505 is_cracked_insn (rtx_insn *insn)
30507 if (!insn || !NONDEBUG_INSN_P (insn)
30508 || GET_CODE (PATTERN (insn)) == USE
30509 || GET_CODE (PATTERN (insn)) == CLOBBER)
30512 if (rs6000_sched_groups
30513 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30515 enum attr_type type = get_attr_type (insn);
30516 if ((type == TYPE_LOAD
30517 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30518 && get_attr_update (insn) == UPDATE_NO)
30519 || (type == TYPE_LOAD
30520 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30521 && get_attr_update (insn) == UPDATE_YES
30522 && get_attr_indexed (insn) == INDEXED_NO)
30523 || (type == TYPE_STORE
30524 && get_attr_update (insn) == UPDATE_YES
30525 && get_attr_indexed (insn) == INDEXED_NO)
30526 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30527 && get_attr_update (insn) == UPDATE_YES)
30528 || (type == TYPE_CR_LOGICAL
30529 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30530 || (type == TYPE_EXTS
30531 && get_attr_dot (insn) == DOT_YES)
30532 || (type == TYPE_SHIFT
30533 && get_attr_dot (insn) == DOT_YES
30534 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30535 || (type == TYPE_MUL
30536 && get_attr_dot (insn) == DOT_YES)
30537 || type == TYPE_DIV
30538 || (type == TYPE_INSERT
30539 && get_attr_size (insn) == SIZE_32))
30546 /* The function returns true if INSN can be issued only from
30547 the branch slot. */
30550 is_branch_slot_insn (rtx_insn *insn)
30552 if (!insn || !NONDEBUG_INSN_P (insn)
30553 || GET_CODE (PATTERN (insn)) == USE
30554 || GET_CODE (PATTERN (insn)) == CLOBBER)
30557 if (rs6000_sched_groups)
30559 enum attr_type type = get_attr_type (insn);
30560 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30568 /* The function returns true if out_inst sets a value that is
30569 used in the address generation computation of in_insn */
30571 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30573 rtx out_set, in_set;
30575 /* For performance reasons, only handle the simple case where
30576 both loads are a single_set. */
30577 out_set = single_set (out_insn);
30580 in_set = single_set (in_insn);
30582 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30588 /* Try to determine base/offset/size parts of the given MEM.
30589 Return true if successful, false if all the values couldn't
30592 This function only looks for REG or REG+CONST address forms.
30593 REG+REG address form will return false. */
30596 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30597 HOST_WIDE_INT *size)
30600 if MEM_SIZE_KNOWN_P (mem)
30601 *size = MEM_SIZE (mem);
30605 addr_rtx = (XEXP (mem, 0));
30606 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30607 addr_rtx = XEXP (addr_rtx, 1);
30610 while (GET_CODE (addr_rtx) == PLUS
30611 && CONST_INT_P (XEXP (addr_rtx, 1)))
30613 *offset += INTVAL (XEXP (addr_rtx, 1));
30614 addr_rtx = XEXP (addr_rtx, 0);
30616 if (!REG_P (addr_rtx))
30623 /* The function returns true if the target storage location of
30624 mem1 is adjacent to the target storage location of mem2 */
30625 /* Return 1 if memory locations are adjacent. */
30628 adjacent_mem_locations (rtx mem1, rtx mem2)
30631 HOST_WIDE_INT off1, size1, off2, size2;
30633 if (get_memref_parts (mem1, ®1, &off1, &size1)
30634 && get_memref_parts (mem2, ®2, &off2, &size2))
30635 return ((REGNO (reg1) == REGNO (reg2))
30636 && ((off1 + size1 == off2)
30637 || (off2 + size2 == off1)));
30642 /* This function returns true if it can be determined that the two MEM
30643 locations overlap by at least 1 byte based on base reg/offset/size. */
30646 mem_locations_overlap (rtx mem1, rtx mem2)
30649 HOST_WIDE_INT off1, size1, off2, size2;
30651 if (get_memref_parts (mem1, ®1, &off1, &size1)
30652 && get_memref_parts (mem2, ®2, &off2, &size2))
30653 return ((REGNO (reg1) == REGNO (reg2))
30654 && (((off1 <= off2) && (off1 + size1 > off2))
30655 || ((off2 <= off1) && (off2 + size2 > off1))));
30660 /* A C statement (sans semicolon) to update the integer scheduling
30661 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30662 INSN earlier, reduce the priority to execute INSN later. Do not
30663 define this macro if you do not need to adjust the scheduling
30664 priorities of insns. */
30667 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30669 rtx load_mem, str_mem;
30670 /* On machines (like the 750) which have asymmetric integer units,
30671 where one integer unit can do multiply and divides and the other
30672 can't, reduce the priority of multiply/divide so it is scheduled
30673 before other integer operations. */
30676 if (! INSN_P (insn))
30679 if (GET_CODE (PATTERN (insn)) == USE)
30682 switch (rs6000_tune) {
30683 case PROCESSOR_PPC750:
30684 switch (get_attr_type (insn))
30691 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30692 priority, priority);
30693 if (priority >= 0 && priority < 0x01000000)
30700 if (insn_must_be_first_in_group (insn)
30701 && reload_completed
30702 && current_sched_info->sched_max_insns_priority
30703 && rs6000_sched_restricted_insns_priority)
30706 /* Prioritize insns that can be dispatched only in the first
30708 if (rs6000_sched_restricted_insns_priority == 1)
30709 /* Attach highest priority to insn. This means that in
30710 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30711 precede 'priority' (critical path) considerations. */
30712 return current_sched_info->sched_max_insns_priority;
30713 else if (rs6000_sched_restricted_insns_priority == 2)
30714 /* Increase priority of insn by a minimal amount. This means that in
30715 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30716 considerations precede dispatch-slot restriction considerations. */
30717 return (priority + 1);
30720 if (rs6000_tune == PROCESSOR_POWER6
30721 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30722 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30723 /* Attach highest priority to insn if the scheduler has just issued two
30724 stores and this instruction is a load, or two loads and this instruction
30725 is a store. Power6 wants loads and stores scheduled alternately
30727 return current_sched_info->sched_max_insns_priority;
30732 /* Return true if the instruction is nonpipelined on the Cell. */
30734 is_nonpipeline_insn (rtx_insn *insn)
30736 enum attr_type type;
30737 if (!insn || !NONDEBUG_INSN_P (insn)
30738 || GET_CODE (PATTERN (insn)) == USE
30739 || GET_CODE (PATTERN (insn)) == CLOBBER)
30742 type = get_attr_type (insn);
30743 if (type == TYPE_MUL
30744 || type == TYPE_DIV
30745 || type == TYPE_SDIV
30746 || type == TYPE_DDIV
30747 || type == TYPE_SSQRT
30748 || type == TYPE_DSQRT
30749 || type == TYPE_MFCR
30750 || type == TYPE_MFCRF
30751 || type == TYPE_MFJMPR)
30759 /* Return how many instructions the machine can issue per cycle. */
30762 rs6000_issue_rate (void)
30764 /* Unless scheduling for register pressure, use issue rate of 1 for
30765 first scheduling pass to decrease degradation. */
30766 if (!reload_completed && !flag_sched_pressure)
30769 switch (rs6000_tune) {
30770 case PROCESSOR_RS64A:
30771 case PROCESSOR_PPC601: /* ? */
30772 case PROCESSOR_PPC7450:
30774 case PROCESSOR_PPC440:
30775 case PROCESSOR_PPC603:
30776 case PROCESSOR_PPC750:
30777 case PROCESSOR_PPC7400:
30778 case PROCESSOR_PPC8540:
30779 case PROCESSOR_PPC8548:
30780 case PROCESSOR_CELL:
30781 case PROCESSOR_PPCE300C2:
30782 case PROCESSOR_PPCE300C3:
30783 case PROCESSOR_PPCE500MC:
30784 case PROCESSOR_PPCE500MC64:
30785 case PROCESSOR_PPCE5500:
30786 case PROCESSOR_PPCE6500:
30787 case PROCESSOR_TITAN:
30789 case PROCESSOR_PPC476:
30790 case PROCESSOR_PPC604:
30791 case PROCESSOR_PPC604e:
30792 case PROCESSOR_PPC620:
30793 case PROCESSOR_PPC630:
30795 case PROCESSOR_POWER4:
30796 case PROCESSOR_POWER5:
30797 case PROCESSOR_POWER6:
30798 case PROCESSOR_POWER7:
30800 case PROCESSOR_POWER8:
30802 case PROCESSOR_POWER9:
30809 /* Return how many instructions to look ahead for better insn
30813 rs6000_use_sched_lookahead (void)
30815 switch (rs6000_tune)
30817 case PROCESSOR_PPC8540:
30818 case PROCESSOR_PPC8548:
30821 case PROCESSOR_CELL:
30822 return (reload_completed ? 8 : 0);
30829 /* We are choosing insn from the ready queue. Return zero if INSN can be
30832 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30834 if (ready_index == 0)
30837 if (rs6000_tune != PROCESSOR_CELL)
30840 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30842 if (!reload_completed
30843 || is_nonpipeline_insn (insn)
30844 || is_microcoded_insn (insn))
30850 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30851 and return true. */
30854 find_mem_ref (rtx pat, rtx *mem_ref)
30859 /* stack_tie does not produce any real memory traffic. */
30860 if (tie_operand (pat, VOIDmode))
30869 /* Recursively process the pattern. */
30870 fmt = GET_RTX_FORMAT (GET_CODE (pat));
30872 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
30876 if (find_mem_ref (XEXP (pat, i), mem_ref))
30879 else if (fmt[i] == 'E')
30880 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
30882 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
30890 /* Determine if PAT is a PATTERN of a load insn. */
30893 is_load_insn1 (rtx pat, rtx *load_mem)
30895 if (!pat || pat == NULL_RTX)
30898 if (GET_CODE (pat) == SET)
30899 return find_mem_ref (SET_SRC (pat), load_mem);
30901 if (GET_CODE (pat) == PARALLEL)
30905 for (i = 0; i < XVECLEN (pat, 0); i++)
30906 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
30913 /* Determine if INSN loads from memory. */
30916 is_load_insn (rtx insn, rtx *load_mem)
30918 if (!insn || !INSN_P (insn))
30924 return is_load_insn1 (PATTERN (insn), load_mem);
30927 /* Determine if PAT is a PATTERN of a store insn. */
30930 is_store_insn1 (rtx pat, rtx *str_mem)
30932 if (!pat || pat == NULL_RTX)
30935 if (GET_CODE (pat) == SET)
30936 return find_mem_ref (SET_DEST (pat), str_mem);
30938 if (GET_CODE (pat) == PARALLEL)
30942 for (i = 0; i < XVECLEN (pat, 0); i++)
30943 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
30950 /* Determine if INSN stores to memory. */
30953 is_store_insn (rtx insn, rtx *str_mem)
30955 if (!insn || !INSN_P (insn))
30958 return is_store_insn1 (PATTERN (insn), str_mem);
30961 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30964 is_power9_pairable_vec_type (enum attr_type type)
30968 case TYPE_VECSIMPLE:
30969 case TYPE_VECCOMPLEX:
30973 case TYPE_VECFLOAT:
30975 case TYPE_VECDOUBLE:
30983 /* Returns whether the dependence between INSN and NEXT is considered
30984 costly by the given target. */
30987 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
30991 rtx load_mem, str_mem;
30993 /* If the flag is not enabled - no dependence is considered costly;
30994 allow all dependent insns in the same group.
30995 This is the most aggressive option. */
30996 if (rs6000_sched_costly_dep == no_dep_costly)
30999 /* If the flag is set to 1 - a dependence is always considered costly;
31000 do not allow dependent instructions in the same group.
31001 This is the most conservative option. */
31002 if (rs6000_sched_costly_dep == all_deps_costly)
31005 insn = DEP_PRO (dep);
31006 next = DEP_CON (dep);
31008 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31009 && is_load_insn (next, &load_mem)
31010 && is_store_insn (insn, &str_mem))
31011 /* Prevent load after store in the same group. */
31014 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31015 && is_load_insn (next, &load_mem)
31016 && is_store_insn (insn, &str_mem)
31017 && DEP_TYPE (dep) == REG_DEP_TRUE
31018 && mem_locations_overlap(str_mem, load_mem))
31019 /* Prevent load after store in the same group if it is a true
31023 /* The flag is set to X; dependences with latency >= X are considered costly,
31024 and will not be scheduled in the same group. */
31025 if (rs6000_sched_costly_dep <= max_dep_latency
31026 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31032 /* Return the next insn after INSN that is found before TAIL is reached,
31033 skipping any "non-active" insns - insns that will not actually occupy
31034 an issue slot. Return NULL_RTX if such an insn is not found. */
31037 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31039 if (insn == NULL_RTX || insn == tail)
31044 insn = NEXT_INSN (insn);
31045 if (insn == NULL_RTX || insn == tail)
31049 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31050 || (NONJUMP_INSN_P (insn)
31051 && GET_CODE (PATTERN (insn)) != USE
31052 && GET_CODE (PATTERN (insn)) != CLOBBER
31053 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31059 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31062 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31067 enum attr_type type, type2;
31069 type = get_attr_type (last_scheduled_insn);
31071 /* Try to issue fixed point divides back-to-back in pairs so they will be
31072 routed to separate execution units and execute in parallel. */
31073 if (type == TYPE_DIV && divide_cnt == 0)
31075 /* First divide has been scheduled. */
31078 /* Scan the ready list looking for another divide, if found move it
31079 to the end of the list so it is chosen next. */
31083 if (recog_memoized (ready[pos]) >= 0
31084 && get_attr_type (ready[pos]) == TYPE_DIV)
31087 for (i = pos; i < lastpos; i++)
31088 ready[i] = ready[i + 1];
31089 ready[lastpos] = tmp;
31097 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31100 /* The best dispatch throughput for vector and vector load insns can be
31101 achieved by interleaving a vector and vector load such that they'll
31102 dispatch to the same superslice. If this pairing cannot be achieved
31103 then it is best to pair vector insns together and vector load insns
31106 To aid in this pairing, vec_pairing maintains the current state with
31107 the following values:
31109 0 : Initial state, no vecload/vector pairing has been started.
31111 1 : A vecload or vector insn has been issued and a candidate for
31112 pairing has been found and moved to the end of the ready
31114 if (type == TYPE_VECLOAD)
31116 /* Issued a vecload. */
31117 if (vec_pairing == 0)
31119 int vecload_pos = -1;
31120 /* We issued a single vecload, look for a vector insn to pair it
31121 with. If one isn't found, try to pair another vecload. */
31125 if (recog_memoized (ready[pos]) >= 0)
31127 type2 = get_attr_type (ready[pos]);
31128 if (is_power9_pairable_vec_type (type2))
31130 /* Found a vector insn to pair with, move it to the
31131 end of the ready list so it is scheduled next. */
31133 for (i = pos; i < lastpos; i++)
31134 ready[i] = ready[i + 1];
31135 ready[lastpos] = tmp;
31137 return cached_can_issue_more;
31139 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31140 /* Remember position of first vecload seen. */
31145 if (vecload_pos >= 0)
31147 /* Didn't find a vector to pair with but did find a vecload,
31148 move it to the end of the ready list. */
31149 tmp = ready[vecload_pos];
31150 for (i = vecload_pos; i < lastpos; i++)
31151 ready[i] = ready[i + 1];
31152 ready[lastpos] = tmp;
31154 return cached_can_issue_more;
31158 else if (is_power9_pairable_vec_type (type))
31160 /* Issued a vector operation. */
31161 if (vec_pairing == 0)
31164 /* We issued a single vector insn, look for a vecload to pair it
31165 with. If one isn't found, try to pair another vector. */
31169 if (recog_memoized (ready[pos]) >= 0)
31171 type2 = get_attr_type (ready[pos]);
31172 if (type2 == TYPE_VECLOAD)
31174 /* Found a vecload insn to pair with, move it to the
31175 end of the ready list so it is scheduled next. */
31177 for (i = pos; i < lastpos; i++)
31178 ready[i] = ready[i + 1];
31179 ready[lastpos] = tmp;
31181 return cached_can_issue_more;
31183 else if (is_power9_pairable_vec_type (type2)
31185 /* Remember position of first vector insn seen. */
31192 /* Didn't find a vecload to pair with but did find a vector
31193 insn, move it to the end of the ready list. */
31194 tmp = ready[vec_pos];
31195 for (i = vec_pos; i < lastpos; i++)
31196 ready[i] = ready[i + 1];
31197 ready[lastpos] = tmp;
31199 return cached_can_issue_more;
31204 /* We've either finished a vec/vecload pair, couldn't find an insn to
31205 continue the current pair, or the last insn had nothing to do with
31206 with pairing. In any case, reset the state. */
31210 return cached_can_issue_more;
31213 /* We are about to begin issuing insns for this clock cycle. */
31216 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31217 rtx_insn **ready ATTRIBUTE_UNUSED,
31218 int *pn_ready ATTRIBUTE_UNUSED,
31219 int clock_var ATTRIBUTE_UNUSED)
31221 int n_ready = *pn_ready;
31224 fprintf (dump, "// rs6000_sched_reorder :\n");
31226 /* Reorder the ready list, if the second to last ready insn
31227 is a nonepipeline insn. */
31228 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31230 if (is_nonpipeline_insn (ready[n_ready - 1])
31231 && (recog_memoized (ready[n_ready - 2]) > 0))
31232 /* Simply swap first two insns. */
31233 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31236 if (rs6000_tune == PROCESSOR_POWER6)
31237 load_store_pendulum = 0;
31239 return rs6000_issue_rate ();
31242 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31245 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31246 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31249 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31251 /* For Power6, we need to handle some special cases to try and keep the
31252 store queue from overflowing and triggering expensive flushes.
31254 This code monitors how load and store instructions are being issued
31255 and skews the ready list one way or the other to increase the likelihood
31256 that a desired instruction is issued at the proper time.
31258 A couple of things are done. First, we maintain a "load_store_pendulum"
31259 to track the current state of load/store issue.
31261 - If the pendulum is at zero, then no loads or stores have been
31262 issued in the current cycle so we do nothing.
31264 - If the pendulum is 1, then a single load has been issued in this
31265 cycle and we attempt to locate another load in the ready list to
31268 - If the pendulum is -2, then two stores have already been
31269 issued in this cycle, so we increase the priority of the first load
31270 in the ready list to increase it's likelihood of being chosen first
31273 - If the pendulum is -1, then a single store has been issued in this
31274 cycle and we attempt to locate another store in the ready list to
31275 issue with it, preferring a store to an adjacent memory location to
31276 facilitate store pairing in the store queue.
31278 - If the pendulum is 2, then two loads have already been
31279 issued in this cycle, so we increase the priority of the first store
31280 in the ready list to increase it's likelihood of being chosen first
31283 - If the pendulum < -2 or > 2, then do nothing.
31285 Note: This code covers the most common scenarios. There exist non
31286 load/store instructions which make use of the LSU and which
31287 would need to be accounted for to strictly model the behavior
31288 of the machine. Those instructions are currently unaccounted
31289 for to help minimize compile time overhead of this code.
31291 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31296 rtx load_mem, str_mem;
31298 if (is_store_insn (last_scheduled_insn, &str_mem))
31299 /* Issuing a store, swing the load_store_pendulum to the left */
31300 load_store_pendulum--;
31301 else if (is_load_insn (last_scheduled_insn, &load_mem))
31302 /* Issuing a load, swing the load_store_pendulum to the right */
31303 load_store_pendulum++;
31305 return cached_can_issue_more;
31307 /* If the pendulum is balanced, or there is only one instruction on
31308 the ready list, then all is well, so return. */
31309 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31310 return cached_can_issue_more;
31312 if (load_store_pendulum == 1)
31314 /* A load has been issued in this cycle. Scan the ready list
31315 for another load to issue with it */
31320 if (is_load_insn (ready[pos], &load_mem))
31322 /* Found a load. Move it to the head of the ready list,
31323 and adjust it's priority so that it is more likely to
31326 for (i=pos; i<*pn_ready-1; i++)
31327 ready[i] = ready[i + 1];
31328 ready[*pn_ready-1] = tmp;
31330 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31331 INSN_PRIORITY (tmp)++;
31337 else if (load_store_pendulum == -2)
31339 /* Two stores have been issued in this cycle. Increase the
31340 priority of the first load in the ready list to favor it for
31341 issuing in the next cycle. */
31346 if (is_load_insn (ready[pos], &load_mem)
31348 && INSN_PRIORITY_KNOWN (ready[pos]))
31350 INSN_PRIORITY (ready[pos])++;
31352 /* Adjust the pendulum to account for the fact that a load
31353 was found and increased in priority. This is to prevent
31354 increasing the priority of multiple loads */
31355 load_store_pendulum--;
31362 else if (load_store_pendulum == -1)
31364 /* A store has been issued in this cycle. Scan the ready list for
31365 another store to issue with it, preferring a store to an adjacent
31367 int first_store_pos = -1;
31373 if (is_store_insn (ready[pos], &str_mem))
31376 /* Maintain the index of the first store found on the
31378 if (first_store_pos == -1)
31379 first_store_pos = pos;
31381 if (is_store_insn (last_scheduled_insn, &str_mem2)
31382 && adjacent_mem_locations (str_mem, str_mem2))
31384 /* Found an adjacent store. Move it to the head of the
31385 ready list, and adjust it's priority so that it is
31386 more likely to stay there */
31388 for (i=pos; i<*pn_ready-1; i++)
31389 ready[i] = ready[i + 1];
31390 ready[*pn_ready-1] = tmp;
31392 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31393 INSN_PRIORITY (tmp)++;
31395 first_store_pos = -1;
31403 if (first_store_pos >= 0)
31405 /* An adjacent store wasn't found, but a non-adjacent store was,
31406 so move the non-adjacent store to the front of the ready
31407 list, and adjust its priority so that it is more likely to
31409 tmp = ready[first_store_pos];
31410 for (i=first_store_pos; i<*pn_ready-1; i++)
31411 ready[i] = ready[i + 1];
31412 ready[*pn_ready-1] = tmp;
31413 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31414 INSN_PRIORITY (tmp)++;
31417 else if (load_store_pendulum == 2)
31419 /* Two loads have been issued in this cycle. Increase the priority
31420 of the first store in the ready list to favor it for issuing in
31426 if (is_store_insn (ready[pos], &str_mem)
31428 && INSN_PRIORITY_KNOWN (ready[pos]))
31430 INSN_PRIORITY (ready[pos])++;
31432 /* Adjust the pendulum to account for the fact that a store
31433 was found and increased in priority. This is to prevent
31434 increasing the priority of multiple stores */
31435 load_store_pendulum++;
31444 /* Do Power9 dependent reordering if necessary. */
31445 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31446 && recog_memoized (last_scheduled_insn) >= 0)
31447 return power9_sched_reorder2 (ready, *pn_ready - 1);
31449 return cached_can_issue_more;
31452 /* Return whether the presence of INSN causes a dispatch group termination
31453 of group WHICH_GROUP.
31455 If WHICH_GROUP == current_group, this function will return true if INSN
31456 causes the termination of the current group (i.e, the dispatch group to
31457 which INSN belongs). This means that INSN will be the last insn in the
31458 group it belongs to.
31460 If WHICH_GROUP == previous_group, this function will return true if INSN
31461 causes the termination of the previous group (i.e, the dispatch group that
31462 precedes the group to which INSN belongs). This means that INSN will be
31463 the first insn in the group it belongs to). */
31466 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31473 first = insn_must_be_first_in_group (insn);
31474 last = insn_must_be_last_in_group (insn);
31479 if (which_group == current_group)
31481 else if (which_group == previous_group)
31489 insn_must_be_first_in_group (rtx_insn *insn)
31491 enum attr_type type;
31495 || DEBUG_INSN_P (insn)
31496 || GET_CODE (PATTERN (insn)) == USE
31497 || GET_CODE (PATTERN (insn)) == CLOBBER)
31500 switch (rs6000_tune)
31502 case PROCESSOR_POWER5:
31503 if (is_cracked_insn (insn))
31506 case PROCESSOR_POWER4:
31507 if (is_microcoded_insn (insn))
31510 if (!rs6000_sched_groups)
31513 type = get_attr_type (insn);
31520 case TYPE_CR_LOGICAL:
31533 case PROCESSOR_POWER6:
31534 type = get_attr_type (insn);
31543 case TYPE_FPCOMPARE:
31554 if (get_attr_dot (insn) == DOT_NO
31555 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31560 if (get_attr_size (insn) == SIZE_32)
31568 if (get_attr_update (insn) == UPDATE_YES)
31576 case PROCESSOR_POWER7:
31577 type = get_attr_type (insn);
31581 case TYPE_CR_LOGICAL:
31595 if (get_attr_dot (insn) == DOT_YES)
31600 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31601 || get_attr_update (insn) == UPDATE_YES)
31608 if (get_attr_update (insn) == UPDATE_YES)
31616 case PROCESSOR_POWER8:
31617 type = get_attr_type (insn);
31621 case TYPE_CR_LOGICAL:
31629 case TYPE_VECSTORE:
31636 if (get_attr_dot (insn) == DOT_YES)
31641 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31642 || get_attr_update (insn) == UPDATE_YES)
31647 if (get_attr_update (insn) == UPDATE_YES
31648 && get_attr_indexed (insn) == INDEXED_YES)
31664 insn_must_be_last_in_group (rtx_insn *insn)
31666 enum attr_type type;
31670 || DEBUG_INSN_P (insn)
31671 || GET_CODE (PATTERN (insn)) == USE
31672 || GET_CODE (PATTERN (insn)) == CLOBBER)
31675 switch (rs6000_tune) {
31676 case PROCESSOR_POWER4:
31677 case PROCESSOR_POWER5:
31678 if (is_microcoded_insn (insn))
31681 if (is_branch_slot_insn (insn))
31685 case PROCESSOR_POWER6:
31686 type = get_attr_type (insn);
31694 case TYPE_FPCOMPARE:
31705 if (get_attr_dot (insn) == DOT_NO
31706 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31711 if (get_attr_size (insn) == SIZE_32)
31719 case PROCESSOR_POWER7:
31720 type = get_attr_type (insn);
31730 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31731 && get_attr_update (insn) == UPDATE_YES)
31736 if (get_attr_update (insn) == UPDATE_YES
31737 && get_attr_indexed (insn) == INDEXED_YES)
31745 case PROCESSOR_POWER8:
31746 type = get_attr_type (insn);
31758 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31759 && get_attr_update (insn) == UPDATE_YES)
31764 if (get_attr_update (insn) == UPDATE_YES
31765 && get_attr_indexed (insn) == INDEXED_YES)
31780 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31781 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31784 is_costly_group (rtx *group_insns, rtx next_insn)
31787 int issue_rate = rs6000_issue_rate ();
31789 for (i = 0; i < issue_rate; i++)
31791 sd_iterator_def sd_it;
31793 rtx insn = group_insns[i];
31798 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31800 rtx next = DEP_CON (dep);
31802 if (next == next_insn
31803 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31811 /* Utility of the function redefine_groups.
31812 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31813 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31814 to keep it "far" (in a separate group) from GROUP_INSNS, following
31815 one of the following schemes, depending on the value of the flag
31816 -minsert_sched_nops = X:
31817 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31818 in order to force NEXT_INSN into a separate group.
31819 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31820 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31821 insertion (has a group just ended, how many vacant issue slots remain in the
31822 last group, and how many dispatch groups were encountered so far). */
31825 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31826 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31831 int issue_rate = rs6000_issue_rate ();
31832 bool end = *group_end;
31835 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31836 return can_issue_more;
31838 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31839 return can_issue_more;
31841 force = is_costly_group (group_insns, next_insn);
31843 return can_issue_more;
31845 if (sched_verbose > 6)
31846 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
31847 *group_count ,can_issue_more);
31849 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
31852 can_issue_more = 0;
31854 /* Since only a branch can be issued in the last issue_slot, it is
31855 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31856 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31857 in this case the last nop will start a new group and the branch
31858 will be forced to the new group. */
31859 if (can_issue_more && !is_branch_slot_insn (next_insn))
31862 /* Do we have a special group ending nop? */
31863 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
31864 || rs6000_tune == PROCESSOR_POWER8)
31866 nop = gen_group_ending_nop ();
31867 emit_insn_before (nop, next_insn);
31868 can_issue_more = 0;
31871 while (can_issue_more > 0)
31874 emit_insn_before (nop, next_insn);
31882 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
31884 int n_nops = rs6000_sched_insert_nops;
31886 /* Nops can't be issued from the branch slot, so the effective
31887 issue_rate for nops is 'issue_rate - 1'. */
31888 if (can_issue_more == 0)
31889 can_issue_more = issue_rate;
31891 if (can_issue_more == 0)
31893 can_issue_more = issue_rate - 1;
31896 for (i = 0; i < issue_rate; i++)
31898 group_insns[i] = 0;
31905 emit_insn_before (nop, next_insn);
31906 if (can_issue_more == issue_rate - 1) /* new group begins */
31909 if (can_issue_more == 0)
31911 can_issue_more = issue_rate - 1;
31914 for (i = 0; i < issue_rate; i++)
31916 group_insns[i] = 0;
31922 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31925 /* Is next_insn going to start a new group? */
31928 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31929 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31930 || (can_issue_more < issue_rate &&
31931 insn_terminates_group_p (next_insn, previous_group)));
31932 if (*group_end && end)
31935 if (sched_verbose > 6)
31936 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
31937 *group_count, can_issue_more);
31938 return can_issue_more;
31941 return can_issue_more;
31944 /* This function tries to synch the dispatch groups that the compiler "sees"
31945 with the dispatch groups that the processor dispatcher is expected to
31946 form in practice. It tries to achieve this synchronization by forcing the
31947 estimated processor grouping on the compiler (as opposed to the function
31948 'pad_goups' which tries to force the scheduler's grouping on the processor).
31950 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31951 examines the (estimated) dispatch groups that will be formed by the processor
31952 dispatcher. It marks these group boundaries to reflect the estimated
31953 processor grouping, overriding the grouping that the scheduler had marked.
31954 Depending on the value of the flag '-minsert-sched-nops' this function can
31955 force certain insns into separate groups or force a certain distance between
31956 them by inserting nops, for example, if there exists a "costly dependence"
31959 The function estimates the group boundaries that the processor will form as
31960 follows: It keeps track of how many vacant issue slots are available after
31961 each insn. A subsequent insn will start a new group if one of the following
31963 - no more vacant issue slots remain in the current dispatch group.
31964 - only the last issue slot, which is the branch slot, is vacant, but the next
31965 insn is not a branch.
31966 - only the last 2 or less issue slots, including the branch slot, are vacant,
31967 which means that a cracked insn (which occupies two issue slots) can't be
31968 issued in this group.
31969 - less than 'issue_rate' slots are vacant, and the next insn always needs to
31970 start a new group. */
31973 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31976 rtx_insn *insn, *next_insn;
31978 int can_issue_more;
31981 int group_count = 0;
31985 issue_rate = rs6000_issue_rate ();
31986 group_insns = XALLOCAVEC (rtx, issue_rate);
31987 for (i = 0; i < issue_rate; i++)
31989 group_insns[i] = 0;
31991 can_issue_more = issue_rate;
31993 insn = get_next_active_insn (prev_head_insn, tail);
31996 while (insn != NULL_RTX)
31998 slot = (issue_rate - can_issue_more);
31999 group_insns[slot] = insn;
32001 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32002 if (insn_terminates_group_p (insn, current_group))
32003 can_issue_more = 0;
32005 next_insn = get_next_active_insn (insn, tail);
32006 if (next_insn == NULL_RTX)
32007 return group_count + 1;
32009 /* Is next_insn going to start a new group? */
32011 = (can_issue_more == 0
32012 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32013 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32014 || (can_issue_more < issue_rate &&
32015 insn_terminates_group_p (next_insn, previous_group)));
32017 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32018 next_insn, &group_end, can_issue_more,
32024 can_issue_more = 0;
32025 for (i = 0; i < issue_rate; i++)
32027 group_insns[i] = 0;
32031 if (GET_MODE (next_insn) == TImode && can_issue_more)
32032 PUT_MODE (next_insn, VOIDmode);
32033 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32034 PUT_MODE (next_insn, TImode);
32037 if (can_issue_more == 0)
32038 can_issue_more = issue_rate;
32041 return group_count;
32044 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32045 dispatch group boundaries that the scheduler had marked. Pad with nops
32046 any dispatch groups which have vacant issue slots, in order to force the
32047 scheduler's grouping on the processor dispatcher. The function
32048 returns the number of dispatch groups found. */
32051 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32054 rtx_insn *insn, *next_insn;
32057 int can_issue_more;
32059 int group_count = 0;
32061 /* Initialize issue_rate. */
32062 issue_rate = rs6000_issue_rate ();
32063 can_issue_more = issue_rate;
32065 insn = get_next_active_insn (prev_head_insn, tail);
32066 next_insn = get_next_active_insn (insn, tail);
32068 while (insn != NULL_RTX)
32071 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32073 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32075 if (next_insn == NULL_RTX)
32080 /* If the scheduler had marked group termination at this location
32081 (between insn and next_insn), and neither insn nor next_insn will
32082 force group termination, pad the group with nops to force group
32085 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32086 && !insn_terminates_group_p (insn, current_group)
32087 && !insn_terminates_group_p (next_insn, previous_group))
32089 if (!is_branch_slot_insn (next_insn))
32092 while (can_issue_more)
32095 emit_insn_before (nop, next_insn);
32100 can_issue_more = issue_rate;
32105 next_insn = get_next_active_insn (insn, tail);
32108 return group_count;
32111 /* We're beginning a new block. Initialize data structures as necessary. */
32114 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32115 int sched_verbose ATTRIBUTE_UNUSED,
32116 int max_ready ATTRIBUTE_UNUSED)
32118 last_scheduled_insn = NULL;
32119 load_store_pendulum = 0;
32124 /* The following function is called at the end of scheduling BB.
32125 After reload, it inserts nops at insn group bundling. */
32128 rs6000_sched_finish (FILE *dump, int sched_verbose)
32133 fprintf (dump, "=== Finishing schedule.\n");
32135 if (reload_completed && rs6000_sched_groups)
32137 /* Do not run sched_finish hook when selective scheduling enabled. */
32138 if (sel_sched_p ())
32141 if (rs6000_sched_insert_nops == sched_finish_none)
32144 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32145 n_groups = pad_groups (dump, sched_verbose,
32146 current_sched_info->prev_head,
32147 current_sched_info->next_tail);
32149 n_groups = redefine_groups (dump, sched_verbose,
32150 current_sched_info->prev_head,
32151 current_sched_info->next_tail);
32153 if (sched_verbose >= 6)
32155 fprintf (dump, "ngroups = %d\n", n_groups);
32156 print_rtl (dump, current_sched_info->prev_head);
32157 fprintf (dump, "Done finish_sched\n");
32162 struct rs6000_sched_context
32164 short cached_can_issue_more;
32165 rtx_insn *last_scheduled_insn;
32166 int load_store_pendulum;
32171 typedef struct rs6000_sched_context rs6000_sched_context_def;
32172 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32174 /* Allocate store for new scheduling context. */
32176 rs6000_alloc_sched_context (void)
32178 return xmalloc (sizeof (rs6000_sched_context_def));
32181 /* If CLEAN_P is true then initializes _SC with clean data,
32182 and from the global context otherwise. */
32184 rs6000_init_sched_context (void *_sc, bool clean_p)
32186 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32190 sc->cached_can_issue_more = 0;
32191 sc->last_scheduled_insn = NULL;
32192 sc->load_store_pendulum = 0;
32193 sc->divide_cnt = 0;
32194 sc->vec_pairing = 0;
32198 sc->cached_can_issue_more = cached_can_issue_more;
32199 sc->last_scheduled_insn = last_scheduled_insn;
32200 sc->load_store_pendulum = load_store_pendulum;
32201 sc->divide_cnt = divide_cnt;
32202 sc->vec_pairing = vec_pairing;
32206 /* Sets the global scheduling context to the one pointed to by _SC. */
32208 rs6000_set_sched_context (void *_sc)
32210 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32212 gcc_assert (sc != NULL);
32214 cached_can_issue_more = sc->cached_can_issue_more;
32215 last_scheduled_insn = sc->last_scheduled_insn;
32216 load_store_pendulum = sc->load_store_pendulum;
32217 divide_cnt = sc->divide_cnt;
32218 vec_pairing = sc->vec_pairing;
32223 rs6000_free_sched_context (void *_sc)
32225 gcc_assert (_sc != NULL);
32231 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32233 switch (get_attr_type (insn))
32248 /* Length in units of the trampoline for entering a nested function. */
32251 rs6000_trampoline_size (void)
32255 switch (DEFAULT_ABI)
32258 gcc_unreachable ();
32261 ret = (TARGET_32BIT) ? 12 : 24;
32265 gcc_assert (!TARGET_32BIT);
32271 ret = (TARGET_32BIT) ? 40 : 48;
32278 /* Emit RTL insns to initialize the variable parts of a trampoline.
32279 FNADDR is an RTX for the address of the function's pure code.
32280 CXT is an RTX for the static chain value for the function. */
32283 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32285 int regsize = (TARGET_32BIT) ? 4 : 8;
32286 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32287 rtx ctx_reg = force_reg (Pmode, cxt);
32288 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32290 switch (DEFAULT_ABI)
32293 gcc_unreachable ();
32295 /* Under AIX, just build the 3 word function descriptor */
32298 rtx fnmem, fn_reg, toc_reg;
32300 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32301 error ("you cannot take the address of a nested function if you use "
32302 "the %qs option", "-mno-pointers-to-nested-functions");
32304 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32305 fn_reg = gen_reg_rtx (Pmode);
32306 toc_reg = gen_reg_rtx (Pmode);
32308 /* Macro to shorten the code expansions below. */
32309 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32311 m_tramp = replace_equiv_address (m_tramp, addr);
32313 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32314 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32315 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32316 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32317 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32323 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32327 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32328 LCT_NORMAL, VOIDmode,
32330 GEN_INT (rs6000_trampoline_size ()), SImode,
32338 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32339 identifier as an argument, so the front end shouldn't look it up. */
32342 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32344 return is_attribute_p ("altivec", attr_id);
32347 /* Handle the "altivec" attribute. The attribute may have
32348 arguments as follows:
32350 __attribute__((altivec(vector__)))
32351 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32352 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32354 and may appear more than once (e.g., 'vector bool char') in a
32355 given declaration. */
32358 rs6000_handle_altivec_attribute (tree *node,
32359 tree name ATTRIBUTE_UNUSED,
32361 int flags ATTRIBUTE_UNUSED,
32362 bool *no_add_attrs)
32364 tree type = *node, result = NULL_TREE;
32368 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32369 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32370 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32373 while (POINTER_TYPE_P (type)
32374 || TREE_CODE (type) == FUNCTION_TYPE
32375 || TREE_CODE (type) == METHOD_TYPE
32376 || TREE_CODE (type) == ARRAY_TYPE)
32377 type = TREE_TYPE (type);
32379 mode = TYPE_MODE (type);
32381 /* Check for invalid AltiVec type qualifiers. */
32382 if (type == long_double_type_node)
32383 error ("use of %<long double%> in AltiVec types is invalid");
32384 else if (type == boolean_type_node)
32385 error ("use of boolean types in AltiVec types is invalid");
32386 else if (TREE_CODE (type) == COMPLEX_TYPE)
32387 error ("use of %<complex%> in AltiVec types is invalid");
32388 else if (DECIMAL_FLOAT_MODE_P (mode))
32389 error ("use of decimal floating point types in AltiVec types is invalid");
32390 else if (!TARGET_VSX)
32392 if (type == long_unsigned_type_node || type == long_integer_type_node)
32395 error ("use of %<long%> in AltiVec types is invalid for "
32396 "64-bit code without %qs", "-mvsx");
32397 else if (rs6000_warn_altivec_long)
32398 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32401 else if (type == long_long_unsigned_type_node
32402 || type == long_long_integer_type_node)
32403 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32405 else if (type == double_type_node)
32406 error ("use of %<double%> in AltiVec types is invalid without %qs",
32410 switch (altivec_type)
32413 unsigned_p = TYPE_UNSIGNED (type);
32417 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32420 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32423 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32426 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32429 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32431 case E_SFmode: result = V4SF_type_node; break;
32432 case E_DFmode: result = V2DF_type_node; break;
32433 /* If the user says 'vector int bool', we may be handed the 'bool'
32434 attribute _before_ the 'vector' attribute, and so select the
32435 proper type in the 'b' case below. */
32436 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32437 case E_V2DImode: case E_V2DFmode:
32445 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32446 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32447 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32448 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32455 case E_V8HImode: result = pixel_V8HI_type_node;
32461 /* Propagate qualifiers attached to the element type
32462 onto the vector type. */
32463 if (result && result != type && TYPE_QUALS (type))
32464 result = build_qualified_type (result, TYPE_QUALS (type));
32466 *no_add_attrs = true; /* No need to hang on to the attribute. */
32469 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32474 /* AltiVec defines five built-in scalar types that serve as vector
32475 elements; we must teach the compiler how to mangle them. The 128-bit
32476 floating point mangling is target-specific as well. */
32478 static const char *
32479 rs6000_mangle_type (const_tree type)
32481 type = TYPE_MAIN_VARIANT (type);
32483 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32484 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32487 if (type == bool_char_type_node) return "U6__boolc";
32488 if (type == bool_short_type_node) return "U6__bools";
32489 if (type == pixel_type_node) return "u7__pixel";
32490 if (type == bool_int_type_node) return "U6__booli";
32491 if (type == bool_long_long_type_node) return "U6__boolx";
32493 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32495 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32496 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32498 /* For all other types, use the default mangling. */
32502 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32503 struct attribute_spec.handler. */
32506 rs6000_handle_longcall_attribute (tree *node, tree name,
32507 tree args ATTRIBUTE_UNUSED,
32508 int flags ATTRIBUTE_UNUSED,
32509 bool *no_add_attrs)
32511 if (TREE_CODE (*node) != FUNCTION_TYPE
32512 && TREE_CODE (*node) != FIELD_DECL
32513 && TREE_CODE (*node) != TYPE_DECL)
32515 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32517 *no_add_attrs = true;
32523 /* Set longcall attributes on all functions declared when
32524 rs6000_default_long_calls is true. */
32526 rs6000_set_default_type_attributes (tree type)
32528 if (rs6000_default_long_calls
32529 && (TREE_CODE (type) == FUNCTION_TYPE
32530 || TREE_CODE (type) == METHOD_TYPE))
32531 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32533 TYPE_ATTRIBUTES (type));
32536 darwin_set_default_type_attributes (type);
32540 /* Return a reference suitable for calling a function with the
32541 longcall attribute. */
32544 rs6000_longcall_ref (rtx call_ref, rtx arg)
32546 /* System V adds '.' to the internal name, so skip them. */
32547 const char *call_name = XSTR (call_ref, 0);
32548 if (*call_name == '.')
32550 while (*call_name == '.')
32553 tree node = get_identifier (call_name);
32554 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32559 rtx base = const0_rtx;
32561 if (DEFAULT_ABI == ABI_ELFv2)
32563 base = gen_rtx_REG (Pmode, TOC_REGISTER);
32569 base = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
32572 /* Reg must match that used by linker PLT stubs. For ELFv2, r12
32573 may be used by a function global entry point. For SysV4, r11
32574 is used by __glink_PLTresolve lazy resolver entry. */
32575 rtx reg = gen_rtx_REG (Pmode, regno);
32576 rtx hi = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg),
32578 rtx lo = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, reg, call_ref, arg),
32580 emit_insn (gen_rtx_SET (reg, hi));
32581 emit_insn (gen_rtx_SET (reg, lo));
32585 return force_reg (Pmode, call_ref);
32588 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32589 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32592 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32593 struct attribute_spec.handler. */
32595 rs6000_handle_struct_attribute (tree *node, tree name,
32596 tree args ATTRIBUTE_UNUSED,
32597 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32600 if (DECL_P (*node))
32602 if (TREE_CODE (*node) == TYPE_DECL)
32603 type = &TREE_TYPE (*node);
32608 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32609 || TREE_CODE (*type) == UNION_TYPE)))
32611 warning (OPT_Wattributes, "%qE attribute ignored", name);
32612 *no_add_attrs = true;
32615 else if ((is_attribute_p ("ms_struct", name)
32616 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32617 || ((is_attribute_p ("gcc_struct", name)
32618 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32620 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32622 *no_add_attrs = true;
32629 rs6000_ms_bitfield_layout_p (const_tree record_type)
32631 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32632 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32633 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32636 #ifdef USING_ELFOS_H
32638 /* A get_unnamed_section callback, used for switching to toc_section. */
32641 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32643 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32644 && TARGET_MINIMAL_TOC)
32646 if (!toc_initialized)
32648 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32649 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32650 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32651 fprintf (asm_out_file, "\t.tc ");
32652 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32653 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32654 fprintf (asm_out_file, "\n");
32656 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32657 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32658 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32659 fprintf (asm_out_file, " = .+32768\n");
32660 toc_initialized = 1;
32663 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32665 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32667 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32668 if (!toc_initialized)
32670 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32671 toc_initialized = 1;
32676 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32677 if (!toc_initialized)
32679 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32680 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32681 fprintf (asm_out_file, " = .+32768\n");
32682 toc_initialized = 1;
32687 /* Implement TARGET_ASM_INIT_SECTIONS. */
32690 rs6000_elf_asm_init_sections (void)
32693 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32696 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32697 SDATA2_SECTION_ASM_OP);
32700 /* Implement TARGET_SELECT_RTX_SECTION. */
32703 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32704 unsigned HOST_WIDE_INT align)
32706 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32707 return toc_section;
32709 return default_elf_select_rtx_section (mode, x, align);
32712 /* For a SYMBOL_REF, set generic flags and then perform some
32713 target-specific processing.
32715 When the AIX ABI is requested on a non-AIX system, replace the
32716 function name with the real name (with a leading .) rather than the
32717 function descriptor name. This saves a lot of overriding code to
32718 read the prefixes. */
32720 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32722 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32724 default_encode_section_info (decl, rtl, first);
32727 && TREE_CODE (decl) == FUNCTION_DECL
32729 && DEFAULT_ABI == ABI_AIX)
32731 rtx sym_ref = XEXP (rtl, 0);
32732 size_t len = strlen (XSTR (sym_ref, 0));
32733 char *str = XALLOCAVEC (char, len + 2);
32735 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32736 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32741 compare_section_name (const char *section, const char *templ)
32745 len = strlen (templ);
32746 return (strncmp (section, templ, len) == 0
32747 && (section[len] == 0 || section[len] == '.'));
32751 rs6000_elf_in_small_data_p (const_tree decl)
32753 if (rs6000_sdata == SDATA_NONE)
32756 /* We want to merge strings, so we never consider them small data. */
32757 if (TREE_CODE (decl) == STRING_CST)
32760 /* Functions are never in the small data area. */
32761 if (TREE_CODE (decl) == FUNCTION_DECL)
32764 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32766 const char *section = DECL_SECTION_NAME (decl);
32767 if (compare_section_name (section, ".sdata")
32768 || compare_section_name (section, ".sdata2")
32769 || compare_section_name (section, ".gnu.linkonce.s")
32770 || compare_section_name (section, ".sbss")
32771 || compare_section_name (section, ".sbss2")
32772 || compare_section_name (section, ".gnu.linkonce.sb")
32773 || strcmp (section, ".PPC.EMB.sdata0") == 0
32774 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32779 /* If we are told not to put readonly data in sdata, then don't. */
32780 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32781 && !rs6000_readonly_in_sdata)
32784 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32787 && size <= g_switch_value
32788 /* If it's not public, and we're not going to reference it there,
32789 there's no need to put it in the small data section. */
32790 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32797 #endif /* USING_ELFOS_H */
32799 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32802 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32804 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32807 /* Do not place thread-local symbols refs in the object blocks. */
32810 rs6000_use_blocks_for_decl_p (const_tree decl)
32812 return !DECL_THREAD_LOCAL_P (decl);
32815 /* Return a REG that occurs in ADDR with coefficient 1.
32816 ADDR can be effectively incremented by incrementing REG.
32818 r0 is special and we must not select it as an address
32819 register by this routine since our caller will try to
32820 increment the returned register via an "la" instruction. */
32823 find_addr_reg (rtx addr)
32825 while (GET_CODE (addr) == PLUS)
32827 if (REG_P (XEXP (addr, 0))
32828 && REGNO (XEXP (addr, 0)) != 0)
32829 addr = XEXP (addr, 0);
32830 else if (REG_P (XEXP (addr, 1))
32831 && REGNO (XEXP (addr, 1)) != 0)
32832 addr = XEXP (addr, 1);
32833 else if (CONSTANT_P (XEXP (addr, 0)))
32834 addr = XEXP (addr, 1);
32835 else if (CONSTANT_P (XEXP (addr, 1)))
32836 addr = XEXP (addr, 0);
32838 gcc_unreachable ();
32840 gcc_assert (REG_P (addr) && REGNO (addr) != 0);
32845 rs6000_fatal_bad_address (rtx op)
32847 fatal_insn ("bad address", op);
32852 typedef struct branch_island_d {
32853 tree function_name;
32859 static vec<branch_island, va_gc> *branch_islands;
32861 /* Remember to generate a branch island for far calls to the given
32865 add_compiler_branch_island (tree label_name, tree function_name,
32868 branch_island bi = {function_name, label_name, line_number};
32869 vec_safe_push (branch_islands, bi);
32872 /* Generate far-jump branch islands for everything recorded in
32873 branch_islands. Invoked immediately after the last instruction of
32874 the epilogue has been emitted; the branch islands must be appended
32875 to, and contiguous with, the function body. Mach-O stubs are
32876 generated in machopic_output_stub(). */
32879 macho_branch_islands (void)
32883 while (!vec_safe_is_empty (branch_islands))
32885 branch_island *bi = &branch_islands->last ();
32886 const char *label = IDENTIFIER_POINTER (bi->label_name);
32887 const char *name = IDENTIFIER_POINTER (bi->function_name);
32888 char name_buf[512];
32889 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32890 if (name[0] == '*' || name[0] == '&')
32891 strcpy (name_buf, name+1);
32895 strcpy (name_buf+1, name);
32897 strcpy (tmp_buf, "\n");
32898 strcat (tmp_buf, label);
32899 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32900 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32901 dbxout_stabd (N_SLINE, bi->line_number);
32902 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32905 if (TARGET_LINK_STACK)
32908 get_ppc476_thunk_name (name);
32909 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
32910 strcat (tmp_buf, name);
32911 strcat (tmp_buf, "\n");
32912 strcat (tmp_buf, label);
32913 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32917 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
32918 strcat (tmp_buf, label);
32919 strcat (tmp_buf, "_pic\n");
32920 strcat (tmp_buf, label);
32921 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32924 strcat (tmp_buf, "\taddis r11,r11,ha16(");
32925 strcat (tmp_buf, name_buf);
32926 strcat (tmp_buf, " - ");
32927 strcat (tmp_buf, label);
32928 strcat (tmp_buf, "_pic)\n");
32930 strcat (tmp_buf, "\tmtlr r0\n");
32932 strcat (tmp_buf, "\taddi r12,r11,lo16(");
32933 strcat (tmp_buf, name_buf);
32934 strcat (tmp_buf, " - ");
32935 strcat (tmp_buf, label);
32936 strcat (tmp_buf, "_pic)\n");
32938 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
32942 strcat (tmp_buf, ":\n\tlis r12,hi16(");
32943 strcat (tmp_buf, name_buf);
32944 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
32945 strcat (tmp_buf, name_buf);
32946 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
32948 output_asm_insn (tmp_buf, 0);
32949 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32950 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32951 dbxout_stabd (N_SLINE, bi->line_number);
32952 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32953 branch_islands->pop ();
32957 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32958 already there or not. */
32961 no_previous_def (tree function_name)
32966 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32967 if (function_name == bi->function_name)
32972 /* GET_PREV_LABEL gets the label name from the previous definition of
32976 get_prev_label (tree function_name)
32981 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32982 if (function_name == bi->function_name)
32983 return bi->label_name;
32987 /* Generate PIC and indirect symbol stubs. */
32990 machopic_output_stub (FILE *file, const char *symb, const char *stub)
32992 unsigned int length;
32993 char *symbol_name, *lazy_ptr_name;
32994 char *local_label_0;
32995 static unsigned label = 0;
32997 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
32998 symb = (*targetm.strip_name_encoding) (symb);
33001 length = strlen (symb);
33002 symbol_name = XALLOCAVEC (char, length + 32);
33003 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33005 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33006 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33009 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33011 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33015 fprintf (file, "\t.align 5\n");
33017 fprintf (file, "%s:\n", stub);
33018 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33021 local_label_0 = XALLOCAVEC (char, 16);
33022 sprintf (local_label_0, "L%u$spb", label);
33024 fprintf (file, "\tmflr r0\n");
33025 if (TARGET_LINK_STACK)
33028 get_ppc476_thunk_name (name);
33029 fprintf (file, "\tbl %s\n", name);
33030 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33034 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33035 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33037 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33038 lazy_ptr_name, local_label_0);
33039 fprintf (file, "\tmtlr r0\n");
33040 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33041 (TARGET_64BIT ? "ldu" : "lwzu"),
33042 lazy_ptr_name, local_label_0);
33043 fprintf (file, "\tmtctr r12\n");
33044 fprintf (file, "\tbctr\n");
33048 fprintf (file, "\t.align 4\n");
33050 fprintf (file, "%s:\n", stub);
33051 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33053 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33054 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33055 (TARGET_64BIT ? "ldu" : "lwzu"),
33057 fprintf (file, "\tmtctr r12\n");
33058 fprintf (file, "\tbctr\n");
33061 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33062 fprintf (file, "%s:\n", lazy_ptr_name);
33063 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33064 fprintf (file, "%sdyld_stub_binding_helper\n",
33065 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33068 /* Legitimize PIC addresses. If the address is already
33069 position-independent, we return ORIG. Newly generated
33070 position-independent addresses go into a reg. This is REG if non
33071 zero, otherwise we allocate register(s) as necessary. */
33073 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33076 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33081 if (reg == NULL && !reload_completed)
33082 reg = gen_reg_rtx (Pmode);
33084 if (GET_CODE (orig) == CONST)
33088 if (GET_CODE (XEXP (orig, 0)) == PLUS
33089 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33092 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33094 /* Use a different reg for the intermediate value, as
33095 it will be marked UNCHANGING. */
33096 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33097 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33100 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33103 if (CONST_INT_P (offset))
33105 if (SMALL_INT (offset))
33106 return plus_constant (Pmode, base, INTVAL (offset));
33107 else if (!reload_completed)
33108 offset = force_reg (Pmode, offset);
33111 rtx mem = force_const_mem (Pmode, orig);
33112 return machopic_legitimize_pic_address (mem, Pmode, reg);
33115 return gen_rtx_PLUS (Pmode, base, offset);
33118 /* Fall back on generic machopic code. */
33119 return machopic_legitimize_pic_address (orig, mode, reg);
33122 /* Output a .machine directive for the Darwin assembler, and call
33123 the generic start_file routine. */
33126 rs6000_darwin_file_start (void)
33128 static const struct
33132 HOST_WIDE_INT if_set;
33134 { "ppc64", "ppc64", MASK_64BIT },
33135 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33136 { "power4", "ppc970", 0 },
33137 { "G5", "ppc970", 0 },
33138 { "7450", "ppc7450", 0 },
33139 { "7400", "ppc7400", MASK_ALTIVEC },
33140 { "G4", "ppc7400", 0 },
33141 { "750", "ppc750", 0 },
33142 { "740", "ppc750", 0 },
33143 { "G3", "ppc750", 0 },
33144 { "604e", "ppc604e", 0 },
33145 { "604", "ppc604", 0 },
33146 { "603e", "ppc603", 0 },
33147 { "603", "ppc603", 0 },
33148 { "601", "ppc601", 0 },
33149 { NULL, "ppc", 0 } };
33150 const char *cpu_id = "";
33153 rs6000_file_start ();
33154 darwin_file_start ();
33156 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33158 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33159 cpu_id = rs6000_default_cpu;
33161 if (global_options_set.x_rs6000_cpu_index)
33162 cpu_id = processor_target_table[rs6000_cpu_index].name;
33164 /* Look through the mapping array. Pick the first name that either
33165 matches the argument, has a bit set in IF_SET that is also set
33166 in the target flags, or has a NULL name. */
33169 while (mapping[i].arg != NULL
33170 && strcmp (mapping[i].arg, cpu_id) != 0
33171 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33174 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33177 #endif /* TARGET_MACHO */
33181 rs6000_elf_reloc_rw_mask (void)
33185 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33191 /* Record an element in the table of global constructors. SYMBOL is
33192 a SYMBOL_REF of the function to be called; PRIORITY is a number
33193 between 0 and MAX_INIT_PRIORITY.
33195 This differs from default_named_section_asm_out_constructor in
33196 that we have special handling for -mrelocatable. */
33198 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33200 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33202 const char *section = ".ctors";
33205 if (priority != DEFAULT_INIT_PRIORITY)
33207 sprintf (buf, ".ctors.%.5u",
33208 /* Invert the numbering so the linker puts us in the proper
33209 order; constructors are run from right to left, and the
33210 linker sorts in increasing order. */
33211 MAX_INIT_PRIORITY - priority);
33215 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33216 assemble_align (POINTER_SIZE);
33218 if (DEFAULT_ABI == ABI_V4
33219 && (TARGET_RELOCATABLE || flag_pic > 1))
33221 fputs ("\t.long (", asm_out_file);
33222 output_addr_const (asm_out_file, symbol);
33223 fputs (")@fixup\n", asm_out_file);
33226 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33229 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33231 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33233 const char *section = ".dtors";
33236 if (priority != DEFAULT_INIT_PRIORITY)
33238 sprintf (buf, ".dtors.%.5u",
33239 /* Invert the numbering so the linker puts us in the proper
33240 order; constructors are run from right to left, and the
33241 linker sorts in increasing order. */
33242 MAX_INIT_PRIORITY - priority);
33246 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33247 assemble_align (POINTER_SIZE);
33249 if (DEFAULT_ABI == ABI_V4
33250 && (TARGET_RELOCATABLE || flag_pic > 1))
33252 fputs ("\t.long (", asm_out_file);
33253 output_addr_const (asm_out_file, symbol);
33254 fputs (")@fixup\n", asm_out_file);
33257 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33261 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33263 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33265 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33266 ASM_OUTPUT_LABEL (file, name);
33267 fputs (DOUBLE_INT_ASM_OP, file);
33268 rs6000_output_function_entry (file, name);
33269 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33272 fputs ("\t.size\t", file);
33273 assemble_name (file, name);
33274 fputs (",24\n\t.type\t.", file);
33275 assemble_name (file, name);
33276 fputs (",@function\n", file);
33277 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33279 fputs ("\t.globl\t.", file);
33280 assemble_name (file, name);
33285 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33286 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33287 rs6000_output_function_entry (file, name);
33288 fputs (":\n", file);
33293 if (DEFAULT_ABI == ABI_V4
33294 && (TARGET_RELOCATABLE || flag_pic > 1)
33295 && !TARGET_SECURE_PLT
33296 && (!constant_pool_empty_p () || crtl->profile)
33297 && (uses_toc = uses_TOC ()))
33302 switch_to_other_text_partition ();
33303 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33305 fprintf (file, "\t.long ");
33306 assemble_name (file, toc_label_name);
33309 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33310 assemble_name (file, buf);
33313 switch_to_other_text_partition ();
33316 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33317 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33319 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33323 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33325 fprintf (file, "\t.quad .TOC.-");
33326 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33327 assemble_name (file, buf);
33331 if (DEFAULT_ABI == ABI_AIX)
33333 const char *desc_name, *orig_name;
33335 orig_name = (*targetm.strip_name_encoding) (name);
33336 desc_name = orig_name;
33337 while (*desc_name == '.')
33340 if (TREE_PUBLIC (decl))
33341 fprintf (file, "\t.globl %s\n", desc_name);
33343 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33344 fprintf (file, "%s:\n", desc_name);
33345 fprintf (file, "\t.long %s\n", orig_name);
33346 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33347 fputs ("\t.long 0\n", file);
33348 fprintf (file, "\t.previous\n");
33350 ASM_OUTPUT_LABEL (file, name);
33353 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33355 rs6000_elf_file_end (void)
33357 #ifdef HAVE_AS_GNU_ATTRIBUTE
33358 /* ??? The value emitted depends on options active at file end.
33359 Assume anyone using #pragma or attributes that might change
33360 options knows what they are doing. */
33361 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33362 && rs6000_passes_float)
33366 if (TARGET_HARD_FLOAT)
33370 if (rs6000_passes_long_double)
33372 if (!TARGET_LONG_DOUBLE_128)
33374 else if (TARGET_IEEEQUAD)
33379 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33381 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33383 if (rs6000_passes_vector)
33384 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33385 (TARGET_ALTIVEC_ABI ? 2 : 1));
33386 if (rs6000_returns_struct)
33387 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33388 aix_struct_return ? 2 : 1);
33391 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33392 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33393 file_end_indicate_exec_stack ();
33396 if (flag_split_stack)
33397 file_end_indicate_split_stack ();
33401 /* We have expanded a CPU builtin, so we need to emit a reference to
33402 the special symbol that LIBC uses to declare it supports the
33403 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33404 switch_to_section (data_section);
33405 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33406 fprintf (asm_out_file, "\t%s %s\n",
33407 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33414 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33415 #define HAVE_XCOFF_DWARF_EXTRAS 0
33418 static enum unwind_info_type
33419 rs6000_xcoff_debug_unwind_info (void)
33425 rs6000_xcoff_asm_output_anchor (rtx symbol)
33429 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33430 SYMBOL_REF_BLOCK_OFFSET (symbol));
33431 fprintf (asm_out_file, "%s", SET_ASM_OP);
33432 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33433 fprintf (asm_out_file, ",");
33434 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33435 fprintf (asm_out_file, "\n");
33439 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33441 fputs (GLOBAL_ASM_OP, stream);
33442 RS6000_OUTPUT_BASENAME (stream, name);
33443 putc ('\n', stream);
33446 /* A get_unnamed_decl callback, used for read-only sections. PTR
33447 points to the section string variable. */
33450 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33452 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33453 *(const char *const *) directive,
33454 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33457 /* Likewise for read-write sections. */
33460 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33462 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33463 *(const char *const *) directive,
33464 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33468 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33470 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33471 *(const char *const *) directive,
33472 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33475 /* A get_unnamed_section callback, used for switching to toc_section. */
33478 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33480 if (TARGET_MINIMAL_TOC)
33482 /* toc_section is always selected at least once from
33483 rs6000_xcoff_file_start, so this is guaranteed to
33484 always be defined once and only once in each file. */
33485 if (!toc_initialized)
33487 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33488 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33489 toc_initialized = 1;
33491 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33492 (TARGET_32BIT ? "" : ",3"));
33495 fputs ("\t.toc\n", asm_out_file);
33498 /* Implement TARGET_ASM_INIT_SECTIONS. */
33501 rs6000_xcoff_asm_init_sections (void)
33503 read_only_data_section
33504 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33505 &xcoff_read_only_section_name);
33507 private_data_section
33508 = get_unnamed_section (SECTION_WRITE,
33509 rs6000_xcoff_output_readwrite_section_asm_op,
33510 &xcoff_private_data_section_name);
33512 read_only_private_data_section
33513 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33514 &xcoff_private_rodata_section_name);
33517 = get_unnamed_section (SECTION_TLS,
33518 rs6000_xcoff_output_tls_section_asm_op,
33519 &xcoff_tls_data_section_name);
33521 tls_private_data_section
33522 = get_unnamed_section (SECTION_TLS,
33523 rs6000_xcoff_output_tls_section_asm_op,
33524 &xcoff_private_data_section_name);
33527 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33529 readonly_data_section = read_only_data_section;
33533 rs6000_xcoff_reloc_rw_mask (void)
33539 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33540 tree decl ATTRIBUTE_UNUSED)
33543 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33545 if (flags & SECTION_EXCLUDE)
33547 else if (flags & SECTION_DEBUG)
33549 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33552 else if (flags & SECTION_CODE)
33554 else if (flags & SECTION_TLS)
33556 else if (flags & SECTION_WRITE)
33561 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33562 (flags & SECTION_CODE) ? "." : "",
33563 name, suffix[smclass], flags & SECTION_ENTSIZE);
33566 #define IN_NAMED_SECTION(DECL) \
33567 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33568 && DECL_SECTION_NAME (DECL) != NULL)
33571 rs6000_xcoff_select_section (tree decl, int reloc,
33572 unsigned HOST_WIDE_INT align)
33574 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33576 if (align > BIGGEST_ALIGNMENT)
33578 resolve_unique_section (decl, reloc, true);
33579 if (IN_NAMED_SECTION (decl))
33580 return get_named_section (decl, NULL, reloc);
33583 if (decl_readonly_section (decl, reloc))
33585 if (TREE_PUBLIC (decl))
33586 return read_only_data_section;
33588 return read_only_private_data_section;
33593 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33595 if (TREE_PUBLIC (decl))
33596 return tls_data_section;
33597 else if (bss_initializer_p (decl))
33599 /* Convert to COMMON to emit in BSS. */
33600 DECL_COMMON (decl) = 1;
33601 return tls_comm_section;
33604 return tls_private_data_section;
33608 if (TREE_PUBLIC (decl))
33609 return data_section;
33611 return private_data_section;
33616 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33620 /* Use select_section for private data and uninitialized data with
33621 alignment <= BIGGEST_ALIGNMENT. */
33622 if (!TREE_PUBLIC (decl)
33623 || DECL_COMMON (decl)
33624 || (DECL_INITIAL (decl) == NULL_TREE
33625 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33626 || DECL_INITIAL (decl) == error_mark_node
33627 || (flag_zero_initialized_in_bss
33628 && initializer_zerop (DECL_INITIAL (decl))))
33631 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33632 name = (*targetm.strip_name_encoding) (name);
33633 set_decl_section_name (decl, name);
33636 /* Select section for constant in constant pool.
33638 On RS/6000, all constants are in the private read-only data area.
33639 However, if this is being placed in the TOC it must be output as a
33643 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33644 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33646 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33647 return toc_section;
33649 return read_only_private_data_section;
33652 /* Remove any trailing [DS] or the like from the symbol name. */
33654 static const char *
33655 rs6000_xcoff_strip_name_encoding (const char *name)
33660 len = strlen (name);
33661 if (name[len - 1] == ']')
33662 return ggc_alloc_string (name, len - 4);
33667 /* Section attributes. AIX is always PIC. */
33669 static unsigned int
33670 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33672 unsigned int align;
33673 unsigned int flags = default_section_type_flags (decl, name, reloc);
33675 /* Align to at least UNIT size. */
33676 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33677 align = MIN_UNITS_PER_WORD;
33679 /* Increase alignment of large objects if not already stricter. */
33680 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33681 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33682 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33684 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33687 /* Output at beginning of assembler file.
33689 Initialize the section names for the RS/6000 at this point.
33691 Specify filename, including full path, to assembler.
33693 We want to go into the TOC section so at least one .toc will be emitted.
33694 Also, in order to output proper .bs/.es pairs, we need at least one static
33695 [RW] section emitted.
33697 Finally, declare mcount when profiling to make the assembler happy. */
33700 rs6000_xcoff_file_start (void)
33702 rs6000_gen_section_name (&xcoff_bss_section_name,
33703 main_input_filename, ".bss_");
33704 rs6000_gen_section_name (&xcoff_private_data_section_name,
33705 main_input_filename, ".rw_");
33706 rs6000_gen_section_name (&xcoff_private_rodata_section_name,
33707 main_input_filename, ".rop_");
33708 rs6000_gen_section_name (&xcoff_read_only_section_name,
33709 main_input_filename, ".ro_");
33710 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33711 main_input_filename, ".tls_");
33712 rs6000_gen_section_name (&xcoff_tbss_section_name,
33713 main_input_filename, ".tbss_[UL]");
33715 fputs ("\t.file\t", asm_out_file);
33716 output_quoted_string (asm_out_file, main_input_filename);
33717 fputc ('\n', asm_out_file);
33718 if (write_symbols != NO_DEBUG)
33719 switch_to_section (private_data_section);
33720 switch_to_section (toc_section);
33721 switch_to_section (text_section);
33723 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33724 rs6000_file_start ();
33727 /* Output at end of assembler file.
33728 On the RS/6000, referencing data should automatically pull in text. */
33731 rs6000_xcoff_file_end (void)
33733 switch_to_section (text_section);
33734 fputs ("_section_.text:\n", asm_out_file);
33735 switch_to_section (data_section);
33736 fputs (TARGET_32BIT
33737 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33741 struct declare_alias_data
33744 bool function_descriptor;
33747 /* Declare alias N. A helper function for for_node_and_aliases. */
33750 rs6000_declare_alias (struct symtab_node *n, void *d)
33752 struct declare_alias_data *data = (struct declare_alias_data *)d;
33753 /* Main symbol is output specially, because varasm machinery does part of
33754 the job for us - we do not need to declare .globl/lglobs and such. */
33755 if (!n->alias || n->weakref)
33758 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33761 /* Prevent assemble_alias from trying to use .set pseudo operation
33762 that does not behave as expected by the middle-end. */
33763 TREE_ASM_WRITTEN (n->decl) = true;
33765 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33766 char *buffer = (char *) alloca (strlen (name) + 2);
33768 int dollar_inside = 0;
33770 strcpy (buffer, name);
33771 p = strchr (buffer, '$');
33775 p = strchr (p + 1, '$');
33777 if (TREE_PUBLIC (n->decl))
33779 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33781 if (dollar_inside) {
33782 if (data->function_descriptor)
33783 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33784 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33786 if (data->function_descriptor)
33788 fputs ("\t.globl .", data->file);
33789 RS6000_OUTPUT_BASENAME (data->file, buffer);
33790 putc ('\n', data->file);
33792 fputs ("\t.globl ", data->file);
33793 RS6000_OUTPUT_BASENAME (data->file, buffer);
33794 putc ('\n', data->file);
33796 #ifdef ASM_WEAKEN_DECL
33797 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33798 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33805 if (data->function_descriptor)
33806 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33807 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33809 if (data->function_descriptor)
33811 fputs ("\t.lglobl .", data->file);
33812 RS6000_OUTPUT_BASENAME (data->file, buffer);
33813 putc ('\n', data->file);
33815 fputs ("\t.lglobl ", data->file);
33816 RS6000_OUTPUT_BASENAME (data->file, buffer);
33817 putc ('\n', data->file);
33819 if (data->function_descriptor)
33820 fputs (".", data->file);
33821 RS6000_OUTPUT_BASENAME (data->file, buffer);
33822 fputs (":\n", data->file);
33827 #ifdef HAVE_GAS_HIDDEN
33828 /* Helper function to calculate visibility of a DECL
33829 and return the value as a const string. */
33831 static const char *
33832 rs6000_xcoff_visibility (tree decl)
33834 static const char * const visibility_types[] = {
33835 "", ",protected", ",hidden", ",internal"
33838 enum symbol_visibility vis = DECL_VISIBILITY (decl);
33839 return visibility_types[vis];
33844 /* This macro produces the initial definition of a function name.
33845 On the RS/6000, we need to place an extra '.' in the function name and
33846 output the function descriptor.
33847 Dollar signs are converted to underscores.
33849 The csect for the function will have already been created when
33850 text_section was selected. We do have to go back to that csect, however.
33852 The third and fourth parameters to the .function pseudo-op (16 and 044)
33853 are placeholders which no longer have any use.
33855 Because AIX assembler's .set command has unexpected semantics, we output
33856 all aliases as alternative labels in front of the definition. */
33859 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
33861 char *buffer = (char *) alloca (strlen (name) + 1);
33863 int dollar_inside = 0;
33864 struct declare_alias_data data = {file, false};
33866 strcpy (buffer, name);
33867 p = strchr (buffer, '$');
33871 p = strchr (p + 1, '$');
33873 if (TREE_PUBLIC (decl))
33875 if (!RS6000_WEAK || !DECL_WEAK (decl))
33877 if (dollar_inside) {
33878 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33879 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33881 fputs ("\t.globl .", file);
33882 RS6000_OUTPUT_BASENAME (file, buffer);
33883 #ifdef HAVE_GAS_HIDDEN
33884 fputs (rs6000_xcoff_visibility (decl), file);
33891 if (dollar_inside) {
33892 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33893 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33895 fputs ("\t.lglobl .", file);
33896 RS6000_OUTPUT_BASENAME (file, buffer);
33899 fputs ("\t.csect ", file);
33900 RS6000_OUTPUT_BASENAME (file, buffer);
33901 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
33902 RS6000_OUTPUT_BASENAME (file, buffer);
33903 fputs (":\n", file);
33904 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33906 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
33907 RS6000_OUTPUT_BASENAME (file, buffer);
33908 fputs (", TOC[tc0], 0\n", file);
33910 switch_to_section (function_section (decl));
33912 RS6000_OUTPUT_BASENAME (file, buffer);
33913 fputs (":\n", file);
33914 data.function_descriptor = true;
33915 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33917 if (!DECL_IGNORED_P (decl))
33919 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33920 xcoffout_declare_function (file, decl, buffer);
33921 else if (write_symbols == DWARF2_DEBUG)
33923 name = (*targetm.strip_name_encoding) (name);
33924 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
33931 /* Output assembly language to globalize a symbol from a DECL,
33932 possibly with visibility. */
33935 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
33937 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
33938 fputs (GLOBAL_ASM_OP, stream);
33939 RS6000_OUTPUT_BASENAME (stream, name);
33940 #ifdef HAVE_GAS_HIDDEN
33941 fputs (rs6000_xcoff_visibility (decl), stream);
33943 putc ('\n', stream);
33946 /* Output assembly language to define a symbol as COMMON from a DECL,
33947 possibly with visibility. */
33950 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
33951 tree decl ATTRIBUTE_UNUSED,
33953 unsigned HOST_WIDE_INT size,
33954 unsigned HOST_WIDE_INT align)
33956 unsigned HOST_WIDE_INT align2 = 2;
33959 align2 = floor_log2 (align / BITS_PER_UNIT);
33963 fputs (COMMON_ASM_OP, stream);
33964 RS6000_OUTPUT_BASENAME (stream, name);
33967 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
33970 #ifdef HAVE_GAS_HIDDEN
33972 fputs (rs6000_xcoff_visibility (decl), stream);
33974 putc ('\n', stream);
33977 /* This macro produces the initial definition of a object (variable) name.
33978 Because AIX assembler's .set command has unexpected semantics, we output
33979 all aliases as alternative labels in front of the definition. */
33982 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
33984 struct declare_alias_data data = {file, false};
33985 RS6000_OUTPUT_BASENAME (file, name);
33986 fputs (":\n", file);
33987 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33991 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
33994 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
33996 fputs (integer_asm_op (size, FALSE), file);
33997 assemble_name (file, label);
33998 fputs ("-$", file);
34001 /* Output a symbol offset relative to the dbase for the current object.
34002 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34005 __gcc_unwind_dbase is embedded in all executables/libraries through
34006 libgcc/config/rs6000/crtdbase.S. */
34009 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34011 fputs (integer_asm_op (size, FALSE), file);
34012 assemble_name (file, label);
34013 fputs("-__gcc_unwind_dbase", file);
34018 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34022 const char *symname;
34024 default_encode_section_info (decl, rtl, first);
34026 /* Careful not to prod global register variables. */
34029 symbol = XEXP (rtl, 0);
34030 if (!SYMBOL_REF_P (symbol))
34033 flags = SYMBOL_REF_FLAGS (symbol);
34035 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34036 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34038 SYMBOL_REF_FLAGS (symbol) = flags;
34040 /* Append mapping class to extern decls. */
34041 symname = XSTR (symbol, 0);
34042 if (decl /* sync condition with assemble_external () */
34043 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34044 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34045 || TREE_CODE (decl) == FUNCTION_DECL)
34046 && symname[strlen (symname) - 1] != ']')
34048 char *newname = (char *) alloca (strlen (symname) + 5);
34049 strcpy (newname, symname);
34050 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34051 ? "[DS]" : "[UA]"));
34052 XSTR (symbol, 0) = ggc_strdup (newname);
34055 #endif /* HAVE_AS_TLS */
34056 #endif /* TARGET_XCOFF */
34059 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34060 const char *name, const char *val)
34062 fputs ("\t.weak\t", stream);
34063 RS6000_OUTPUT_BASENAME (stream, name);
34064 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34065 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34068 fputs ("[DS]", stream);
34069 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34071 fputs (rs6000_xcoff_visibility (decl), stream);
34073 fputs ("\n\t.weak\t.", stream);
34074 RS6000_OUTPUT_BASENAME (stream, name);
34076 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34078 fputs (rs6000_xcoff_visibility (decl), stream);
34080 fputc ('\n', stream);
34083 #ifdef ASM_OUTPUT_DEF
34084 ASM_OUTPUT_DEF (stream, name, val);
34086 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34087 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34089 fputs ("\t.set\t.", stream);
34090 RS6000_OUTPUT_BASENAME (stream, name);
34091 fputs (",.", stream);
34092 RS6000_OUTPUT_BASENAME (stream, val);
34093 fputc ('\n', stream);
34099 /* Return true if INSN should not be copied. */
34102 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34104 return recog_memoized (insn) >= 0
34105 && get_attr_cannot_copy (insn);
34108 /* Compute a (partial) cost for rtx X. Return true if the complete
34109 cost has been computed, and false if subexpressions should be
34110 scanned. In either case, *TOTAL contains the cost result. */
34113 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34114 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34116 int code = GET_CODE (x);
34120 /* On the RS/6000, if it is valid in the insn, it is free. */
34122 if (((outer_code == SET
34123 || outer_code == PLUS
34124 || outer_code == MINUS)
34125 && (satisfies_constraint_I (x)
34126 || satisfies_constraint_L (x)))
34127 || (outer_code == AND
34128 && (satisfies_constraint_K (x)
34130 ? satisfies_constraint_L (x)
34131 : satisfies_constraint_J (x))))
34132 || ((outer_code == IOR || outer_code == XOR)
34133 && (satisfies_constraint_K (x)
34135 ? satisfies_constraint_L (x)
34136 : satisfies_constraint_J (x))))
34137 || outer_code == ASHIFT
34138 || outer_code == ASHIFTRT
34139 || outer_code == LSHIFTRT
34140 || outer_code == ROTATE
34141 || outer_code == ROTATERT
34142 || outer_code == ZERO_EXTRACT
34143 || (outer_code == MULT
34144 && satisfies_constraint_I (x))
34145 || ((outer_code == DIV || outer_code == UDIV
34146 || outer_code == MOD || outer_code == UMOD)
34147 && exact_log2 (INTVAL (x)) >= 0)
34148 || (outer_code == COMPARE
34149 && (satisfies_constraint_I (x)
34150 || satisfies_constraint_K (x)))
34151 || ((outer_code == EQ || outer_code == NE)
34152 && (satisfies_constraint_I (x)
34153 || satisfies_constraint_K (x)
34155 ? satisfies_constraint_L (x)
34156 : satisfies_constraint_J (x))))
34157 || (outer_code == GTU
34158 && satisfies_constraint_I (x))
34159 || (outer_code == LTU
34160 && satisfies_constraint_P (x)))
34165 else if ((outer_code == PLUS
34166 && reg_or_add_cint_operand (x, VOIDmode))
34167 || (outer_code == MINUS
34168 && reg_or_sub_cint_operand (x, VOIDmode))
34169 || ((outer_code == SET
34170 || outer_code == IOR
34171 || outer_code == XOR)
34173 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34175 *total = COSTS_N_INSNS (1);
34181 case CONST_WIDE_INT:
34185 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34189 /* When optimizing for size, MEM should be slightly more expensive
34190 than generating address, e.g., (plus (reg) (const)).
34191 L1 cache latency is about two instructions. */
34192 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34193 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34194 *total += COSTS_N_INSNS (100);
34203 if (FLOAT_MODE_P (mode))
34204 *total = rs6000_cost->fp;
34206 *total = COSTS_N_INSNS (1);
34210 if (CONST_INT_P (XEXP (x, 1))
34211 && satisfies_constraint_I (XEXP (x, 1)))
34213 if (INTVAL (XEXP (x, 1)) >= -256
34214 && INTVAL (XEXP (x, 1)) <= 255)
34215 *total = rs6000_cost->mulsi_const9;
34217 *total = rs6000_cost->mulsi_const;
34219 else if (mode == SFmode)
34220 *total = rs6000_cost->fp;
34221 else if (FLOAT_MODE_P (mode))
34222 *total = rs6000_cost->dmul;
34223 else if (mode == DImode)
34224 *total = rs6000_cost->muldi;
34226 *total = rs6000_cost->mulsi;
34230 if (mode == SFmode)
34231 *total = rs6000_cost->fp;
34233 *total = rs6000_cost->dmul;
34238 if (FLOAT_MODE_P (mode))
34240 *total = mode == DFmode ? rs6000_cost->ddiv
34241 : rs6000_cost->sdiv;
34248 if (CONST_INT_P (XEXP (x, 1))
34249 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34251 if (code == DIV || code == MOD)
34253 *total = COSTS_N_INSNS (2);
34256 *total = COSTS_N_INSNS (1);
34260 if (GET_MODE (XEXP (x, 1)) == DImode)
34261 *total = rs6000_cost->divdi;
34263 *total = rs6000_cost->divsi;
34265 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34266 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34267 *total += COSTS_N_INSNS (2);
34271 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34275 *total = COSTS_N_INSNS (4);
34279 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34283 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34287 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34290 *total = COSTS_N_INSNS (1);
34294 if (CONST_INT_P (XEXP (x, 1)))
34296 rtx left = XEXP (x, 0);
34297 rtx_code left_code = GET_CODE (left);
34299 /* rotate-and-mask: 1 insn. */
34300 if ((left_code == ROTATE
34301 || left_code == ASHIFT
34302 || left_code == LSHIFTRT)
34303 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34305 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34306 if (!CONST_INT_P (XEXP (left, 1)))
34307 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34308 *total += COSTS_N_INSNS (1);
34312 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34313 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34314 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34315 || (val & 0xffff) == val
34316 || (val & 0xffff0000) == val
34317 || ((val & 0xffff) == 0 && mode == SImode))
34319 *total = rtx_cost (left, mode, AND, 0, speed);
34320 *total += COSTS_N_INSNS (1);
34325 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34327 *total = rtx_cost (left, mode, AND, 0, speed);
34328 *total += COSTS_N_INSNS (2);
34333 *total = COSTS_N_INSNS (1);
34338 *total = COSTS_N_INSNS (1);
34344 *total = COSTS_N_INSNS (1);
34348 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34349 the sign extend and shift separately within the insn. */
34350 if (TARGET_EXTSWSLI && mode == DImode
34351 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34352 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34363 /* Handle mul_highpart. */
34364 if (outer_code == TRUNCATE
34365 && GET_CODE (XEXP (x, 0)) == MULT)
34367 if (mode == DImode)
34368 *total = rs6000_cost->muldi;
34370 *total = rs6000_cost->mulsi;
34373 else if (outer_code == AND)
34376 *total = COSTS_N_INSNS (1);
34381 if (MEM_P (XEXP (x, 0)))
34384 *total = COSTS_N_INSNS (1);
34390 if (!FLOAT_MODE_P (mode))
34392 *total = COSTS_N_INSNS (1);
34398 case UNSIGNED_FLOAT:
34401 case FLOAT_TRUNCATE:
34402 *total = rs6000_cost->fp;
34406 if (mode == DFmode)
34407 *total = rs6000_cost->sfdf_convert;
34409 *total = rs6000_cost->fp;
34413 switch (XINT (x, 1))
34416 *total = rs6000_cost->fp;
34428 *total = COSTS_N_INSNS (1);
34431 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34433 *total = rs6000_cost->fp;
34442 /* Carry bit requires mode == Pmode.
34443 NEG or PLUS already counted so only add one. */
34445 && (outer_code == NEG || outer_code == PLUS))
34447 *total = COSTS_N_INSNS (1);
34455 if (outer_code == SET)
34457 if (XEXP (x, 1) == const0_rtx)
34459 *total = COSTS_N_INSNS (2);
34464 *total = COSTS_N_INSNS (3);
34469 if (outer_code == COMPARE)
34483 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34486 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34487 int opno, int *total, bool speed)
34489 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34492 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34493 "opno = %d, total = %d, speed = %s, x:\n",
34494 ret ? "complete" : "scan inner",
34495 GET_MODE_NAME (mode),
34496 GET_RTX_NAME (outer_code),
34499 speed ? "true" : "false");
34507 rs6000_insn_cost (rtx_insn *insn, bool speed)
34509 if (recog_memoized (insn) < 0)
34513 return get_attr_length (insn);
34515 int cost = get_attr_cost (insn);
34519 int n = get_attr_length (insn) / 4;
34520 enum attr_type type = get_attr_type (insn);
34527 cost = COSTS_N_INSNS (n + 1);
34531 switch (get_attr_size (insn))
34534 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34537 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34540 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34543 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34546 gcc_unreachable ();
34550 switch (get_attr_size (insn))
34553 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34556 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34559 gcc_unreachable ();
34564 cost = n * rs6000_cost->fp;
34567 cost = n * rs6000_cost->dmul;
34570 cost = n * rs6000_cost->sdiv;
34573 cost = n * rs6000_cost->ddiv;
34580 cost = COSTS_N_INSNS (n + 2);
34584 cost = COSTS_N_INSNS (n);
34590 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34593 rs6000_debug_address_cost (rtx x, machine_mode mode,
34594 addr_space_t as, bool speed)
34596 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34598 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34599 ret, speed ? "true" : "false");
34606 /* A C expression returning the cost of moving data from a register of class
34607 CLASS1 to one of CLASS2. */
34610 rs6000_register_move_cost (machine_mode mode,
34611 reg_class_t from, reg_class_t to)
34614 reg_class_t rclass;
34616 if (TARGET_DEBUG_COST)
34619 /* If we have VSX, we can easily move between FPR or Altivec registers,
34620 otherwise we can only easily move within classes.
34621 Do this first so we give best-case answers for union classes
34622 containing both gprs and vsx regs. */
34623 HARD_REG_SET to_vsx, from_vsx;
34624 COPY_HARD_REG_SET (to_vsx, reg_class_contents[to]);
34625 AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
34626 COPY_HARD_REG_SET (from_vsx, reg_class_contents[from]);
34627 AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
34628 if (!hard_reg_set_empty_p (to_vsx)
34629 && !hard_reg_set_empty_p (from_vsx)
34631 || hard_reg_set_intersect_p (to_vsx, from_vsx)))
34633 int reg = FIRST_FPR_REGNO;
34635 || (TEST_HARD_REG_BIT (to_vsx, FIRST_ALTIVEC_REGNO)
34636 && TEST_HARD_REG_BIT (from_vsx, FIRST_ALTIVEC_REGNO)))
34637 reg = FIRST_ALTIVEC_REGNO;
34638 ret = 2 * hard_regno_nregs (reg, mode);
34641 /* Moves from/to GENERAL_REGS. */
34642 else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
34643 || (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
34645 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34647 if (TARGET_DIRECT_MOVE)
34649 /* Keep the cost for direct moves above that for within
34650 a register class even if the actual processor cost is
34651 comparable. We do this because a direct move insn
34652 can't be a nop, whereas with ideal register
34653 allocation a move within the same class might turn
34654 out to be a nop. */
34655 if (rs6000_tune == PROCESSOR_POWER9)
34656 ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34658 ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34659 /* SFmode requires a conversion when moving between gprs
34661 if (mode == SFmode)
34665 ret = (rs6000_memory_move_cost (mode, rclass, false)
34666 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34669 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34671 else if (rclass == CR_REGS)
34674 /* For those processors that have slow LR/CTR moves, make them more
34675 expensive than memory in order to bias spills to memory .*/
34676 else if ((rs6000_tune == PROCESSOR_POWER6
34677 || rs6000_tune == PROCESSOR_POWER7
34678 || rs6000_tune == PROCESSOR_POWER8
34679 || rs6000_tune == PROCESSOR_POWER9)
34680 && reg_class_subset_p (rclass, SPECIAL_REGS))
34681 ret = 6 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34684 /* A move will cost one instruction per GPR moved. */
34685 ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34688 /* Everything else has to go through GENERAL_REGS. */
34690 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34691 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34693 if (TARGET_DEBUG_COST)
34695 if (dbg_cost_ctrl == 1)
34697 "rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n",
34698 ret, GET_MODE_NAME (mode), reg_class_names[from],
34699 reg_class_names[to]);
34706 /* A C expressions returning the cost of moving data of MODE from a register to
34710 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34711 bool in ATTRIBUTE_UNUSED)
34715 if (TARGET_DEBUG_COST)
34718 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34719 ret = 4 * hard_regno_nregs (0, mode);
34720 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34721 || reg_classes_intersect_p (rclass, VSX_REGS)))
34722 ret = 4 * hard_regno_nregs (32, mode);
34723 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34724 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34726 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34728 if (TARGET_DEBUG_COST)
34730 if (dbg_cost_ctrl == 1)
34732 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34733 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34740 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
34742 The register allocator chooses GEN_OR_VSX_REGS for the allocno
34743 class if GENERAL_REGS and VSX_REGS cost is lower than the memory
34744 cost. This happens a lot when TARGET_DIRECT_MOVE makes the register
34745 move cost between GENERAL_REGS and VSX_REGS low.
34747 It might seem reasonable to use a union class. After all, if usage
34748 of vsr is low and gpr high, it might make sense to spill gpr to vsr
34749 rather than memory. However, in cases where register pressure of
34750 both is high, like the cactus_adm spec test, allowing
34751 GEN_OR_VSX_REGS as the allocno class results in bad decisions in
34752 the first scheduling pass. This is partly due to an allocno of
34753 GEN_OR_VSX_REGS wrongly contributing to the GENERAL_REGS pressure
34754 class, which gives too high a pressure for GENERAL_REGS and too low
34755 for VSX_REGS. So, force a choice of the subclass here.
34757 The best class is also the union if GENERAL_REGS and VSX_REGS have
34758 the same cost. In that case we do use GEN_OR_VSX_REGS as the
34759 allocno class, since trying to narrow down the class by regno mode
34760 is prone to error. For example, SImode is allowed in VSX regs and
34761 in some cases (eg. gcc.target/powerpc/p9-xxbr-3.c do_bswap32_vect)
34762 it would be wrong to choose an allocno of GENERAL_REGS based on
34766 rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
34767 reg_class_t allocno_class,
34768 reg_class_t best_class)
34770 switch (allocno_class)
34772 case GEN_OR_VSX_REGS:
34773 /* best_class must be a subset of allocno_class. */
34774 gcc_checking_assert (best_class == GEN_OR_VSX_REGS
34775 || best_class == GEN_OR_FLOAT_REGS
34776 || best_class == VSX_REGS
34777 || best_class == ALTIVEC_REGS
34778 || best_class == FLOAT_REGS
34779 || best_class == GENERAL_REGS
34780 || best_class == BASE_REGS);
34781 /* Use best_class but choose wider classes when copying from the
34782 wider class to best_class is cheap. This mimics IRA choice
34783 of allocno class. */
34784 if (best_class == BASE_REGS)
34785 return GENERAL_REGS;
34787 && (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS))
34795 return allocno_class;
34798 /* Returns a code for a target-specific builtin that implements
34799 reciprocal of the function, or NULL_TREE if not available. */
34802 rs6000_builtin_reciprocal (tree fndecl)
34804 switch (DECL_FUNCTION_CODE (fndecl))
34806 case VSX_BUILTIN_XVSQRTDP:
34807 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34810 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34812 case VSX_BUILTIN_XVSQRTSP:
34813 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34816 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34823 /* Load up a constant. If the mode is a vector mode, splat the value across
34824 all of the vector elements. */
34827 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34831 if (mode == SFmode || mode == DFmode)
34833 rtx d = const_double_from_real_value (dconst, mode);
34834 reg = force_reg (mode, d);
34836 else if (mode == V4SFmode)
34838 rtx d = const_double_from_real_value (dconst, SFmode);
34839 rtvec v = gen_rtvec (4, d, d, d, d);
34840 reg = gen_reg_rtx (mode);
34841 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34843 else if (mode == V2DFmode)
34845 rtx d = const_double_from_real_value (dconst, DFmode);
34846 rtvec v = gen_rtvec (2, d, d);
34847 reg = gen_reg_rtx (mode);
34848 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34851 gcc_unreachable ();
34856 /* Generate an FMA instruction. */
34859 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
34861 machine_mode mode = GET_MODE (target);
34864 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
34865 gcc_assert (dst != NULL);
34868 emit_move_insn (target, dst);
34871 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34874 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
34876 machine_mode mode = GET_MODE (dst);
34879 /* This is a tad more complicated, since the fnma_optab is for
34880 a different expression: fma(-m1, m2, a), which is the same
34881 thing except in the case of signed zeros.
34883 Fortunately we know that if FMA is supported that FNMSUB is
34884 also supported in the ISA. Just expand it directly. */
34886 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
34888 r = gen_rtx_NEG (mode, a);
34889 r = gen_rtx_FMA (mode, m1, m2, r);
34890 r = gen_rtx_NEG (mode, r);
34891 emit_insn (gen_rtx_SET (dst, r));
34894 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34895 add a reg_note saying that this was a division. Support both scalar and
34896 vector divide. Assumes no trapping math and finite arguments. */
34899 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
34901 machine_mode mode = GET_MODE (dst);
34902 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
34905 /* Low precision estimates guarantee 5 bits of accuracy. High
34906 precision estimates guarantee 14 bits of accuracy. SFmode
34907 requires 23 bits of accuracy. DFmode requires 52 bits of
34908 accuracy. Each pass at least doubles the accuracy, leading
34909 to the following. */
34910 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34911 if (mode == DFmode || mode == V2DFmode)
34914 enum insn_code code = optab_handler (smul_optab, mode);
34915 insn_gen_fn gen_mul = GEN_FCN (code);
34917 gcc_assert (code != CODE_FOR_nothing);
34919 one = rs6000_load_constant_and_splat (mode, dconst1);
34921 /* x0 = 1./d estimate */
34922 x0 = gen_reg_rtx (mode);
34923 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
34926 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34929 /* e0 = 1. - d * x0 */
34930 e0 = gen_reg_rtx (mode);
34931 rs6000_emit_nmsub (e0, d, x0, one);
34933 /* x1 = x0 + e0 * x0 */
34934 x1 = gen_reg_rtx (mode);
34935 rs6000_emit_madd (x1, e0, x0, x0);
34937 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
34938 ++i, xprev = xnext, eprev = enext) {
34940 /* enext = eprev * eprev */
34941 enext = gen_reg_rtx (mode);
34942 emit_insn (gen_mul (enext, eprev, eprev));
34944 /* xnext = xprev + enext * xprev */
34945 xnext = gen_reg_rtx (mode);
34946 rs6000_emit_madd (xnext, enext, xprev, xprev);
34952 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34954 /* u = n * xprev */
34955 u = gen_reg_rtx (mode);
34956 emit_insn (gen_mul (u, n, xprev));
34958 /* v = n - (d * u) */
34959 v = gen_reg_rtx (mode);
34960 rs6000_emit_nmsub (v, d, u, n);
34962 /* dst = (v * xprev) + u */
34963 rs6000_emit_madd (dst, v, xprev, u);
34966 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
34969 /* Goldschmidt's Algorithm for single/double-precision floating point
34970 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34973 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
34975 machine_mode mode = GET_MODE (src);
34976 rtx e = gen_reg_rtx (mode);
34977 rtx g = gen_reg_rtx (mode);
34978 rtx h = gen_reg_rtx (mode);
34980 /* Low precision estimates guarantee 5 bits of accuracy. High
34981 precision estimates guarantee 14 bits of accuracy. SFmode
34982 requires 23 bits of accuracy. DFmode requires 52 bits of
34983 accuracy. Each pass at least doubles the accuracy, leading
34984 to the following. */
34985 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34986 if (mode == DFmode || mode == V2DFmode)
34991 enum insn_code code = optab_handler (smul_optab, mode);
34992 insn_gen_fn gen_mul = GEN_FCN (code);
34994 gcc_assert (code != CODE_FOR_nothing);
34996 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
34998 /* e = rsqrt estimate */
34999 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35002 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35005 rtx zero = force_reg (mode, CONST0_RTX (mode));
35007 if (mode == SFmode)
35009 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35012 emit_move_insn (e, target);
35016 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35017 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35021 /* g = sqrt estimate. */
35022 emit_insn (gen_mul (g, e, src));
35023 /* h = 1/(2*sqrt) estimate. */
35024 emit_insn (gen_mul (h, e, mhalf));
35030 rtx t = gen_reg_rtx (mode);
35031 rs6000_emit_nmsub (t, g, h, mhalf);
35032 /* Apply correction directly to 1/rsqrt estimate. */
35033 rs6000_emit_madd (dst, e, t, e);
35037 for (i = 0; i < passes; i++)
35039 rtx t1 = gen_reg_rtx (mode);
35040 rtx g1 = gen_reg_rtx (mode);
35041 rtx h1 = gen_reg_rtx (mode);
35043 rs6000_emit_nmsub (t1, g, h, mhalf);
35044 rs6000_emit_madd (g1, g, t1, g);
35045 rs6000_emit_madd (h1, h, t1, h);
35050 /* Multiply by 2 for 1/rsqrt. */
35051 emit_insn (gen_add3_insn (dst, h, h));
35056 rtx t = gen_reg_rtx (mode);
35057 rs6000_emit_nmsub (t, g, h, mhalf);
35058 rs6000_emit_madd (dst, g, t, g);
35064 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35065 (Power7) targets. DST is the target, and SRC is the argument operand. */
35068 rs6000_emit_popcount (rtx dst, rtx src)
35070 machine_mode mode = GET_MODE (dst);
35073 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35074 if (TARGET_POPCNTD)
35076 if (mode == SImode)
35077 emit_insn (gen_popcntdsi2 (dst, src));
35079 emit_insn (gen_popcntddi2 (dst, src));
35083 tmp1 = gen_reg_rtx (mode);
35085 if (mode == SImode)
35087 emit_insn (gen_popcntbsi2 (tmp1, src));
35088 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35090 tmp2 = force_reg (SImode, tmp2);
35091 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35095 emit_insn (gen_popcntbdi2 (tmp1, src));
35096 tmp2 = expand_mult (DImode, tmp1,
35097 GEN_INT ((HOST_WIDE_INT)
35098 0x01010101 << 32 | 0x01010101),
35100 tmp2 = force_reg (DImode, tmp2);
35101 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35106 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35107 target, and SRC is the argument operand. */
35110 rs6000_emit_parity (rtx dst, rtx src)
35112 machine_mode mode = GET_MODE (dst);
35115 tmp = gen_reg_rtx (mode);
35117 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35120 if (mode == SImode)
35122 emit_insn (gen_popcntbsi2 (tmp, src));
35123 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35127 emit_insn (gen_popcntbdi2 (tmp, src));
35128 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35133 if (mode == SImode)
35135 /* Is mult+shift >= shift+xor+shift+xor? */
35136 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35138 rtx tmp1, tmp2, tmp3, tmp4;
35140 tmp1 = gen_reg_rtx (SImode);
35141 emit_insn (gen_popcntbsi2 (tmp1, src));
35143 tmp2 = gen_reg_rtx (SImode);
35144 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35145 tmp3 = gen_reg_rtx (SImode);
35146 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35148 tmp4 = gen_reg_rtx (SImode);
35149 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35150 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35153 rs6000_emit_popcount (tmp, src);
35154 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35158 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35159 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35161 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35163 tmp1 = gen_reg_rtx (DImode);
35164 emit_insn (gen_popcntbdi2 (tmp1, src));
35166 tmp2 = gen_reg_rtx (DImode);
35167 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35168 tmp3 = gen_reg_rtx (DImode);
35169 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35171 tmp4 = gen_reg_rtx (DImode);
35172 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35173 tmp5 = gen_reg_rtx (DImode);
35174 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35176 tmp6 = gen_reg_rtx (DImode);
35177 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35178 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35181 rs6000_emit_popcount (tmp, src);
35182 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35186 /* Expand an Altivec constant permutation for little endian mode.
35187 OP0 and OP1 are the input vectors and TARGET is the output vector.
35188 SEL specifies the constant permutation vector.
35190 There are two issues: First, the two input operands must be
35191 swapped so that together they form a double-wide array in LE
35192 order. Second, the vperm instruction has surprising behavior
35193 in LE mode: it interprets the elements of the source vectors
35194 in BE mode ("left to right") and interprets the elements of
35195 the destination vector in LE mode ("right to left"). To
35196 correct for this, we must subtract each element of the permute
35197 control vector from 31.
35199 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35200 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35201 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35202 serve as the permute control vector. Then, in BE mode,
35206 places the desired result in vr9. However, in LE mode the
35207 vector contents will be
35209 vr10 = 00000003 00000002 00000001 00000000
35210 vr11 = 00000007 00000006 00000005 00000004
35212 The result of the vperm using the same permute control vector is
35214 vr9 = 05000000 07000000 01000000 03000000
35216 That is, the leftmost 4 bytes of vr10 are interpreted as the
35217 source for the rightmost 4 bytes of vr9, and so on.
35219 If we change the permute control vector to
35221 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35229 vr9 = 00000006 00000004 00000002 00000000. */
35232 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35233 const vec_perm_indices &sel)
35237 rtx constv, unspec;
35239 /* Unpack and adjust the constant selector. */
35240 for (i = 0; i < 16; ++i)
35242 unsigned int elt = 31 - (sel[i] & 31);
35243 perm[i] = GEN_INT (elt);
35246 /* Expand to a permute, swapping the inputs and using the
35247 adjusted selector. */
35249 op0 = force_reg (V16QImode, op0);
35251 op1 = force_reg (V16QImode, op1);
35253 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35254 constv = force_reg (V16QImode, constv);
35255 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35257 if (!REG_P (target))
35259 rtx tmp = gen_reg_rtx (V16QImode);
35260 emit_move_insn (tmp, unspec);
35264 emit_move_insn (target, unspec);
35267 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35268 permute control vector. But here it's not a constant, so we must
35269 generate a vector NAND or NOR to do the adjustment. */
35272 altivec_expand_vec_perm_le (rtx operands[4])
35274 rtx notx, iorx, unspec;
35275 rtx target = operands[0];
35276 rtx op0 = operands[1];
35277 rtx op1 = operands[2];
35278 rtx sel = operands[3];
35280 rtx norreg = gen_reg_rtx (V16QImode);
35281 machine_mode mode = GET_MODE (target);
35283 /* Get everything in regs so the pattern matches. */
35285 op0 = force_reg (mode, op0);
35287 op1 = force_reg (mode, op1);
35289 sel = force_reg (V16QImode, sel);
35290 if (!REG_P (target))
35291 tmp = gen_reg_rtx (mode);
35293 if (TARGET_P9_VECTOR)
35295 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35300 /* Invert the selector with a VNAND if available, else a VNOR.
35301 The VNAND is preferred for future fusion opportunities. */
35302 notx = gen_rtx_NOT (V16QImode, sel);
35303 iorx = (TARGET_P8_VECTOR
35304 ? gen_rtx_IOR (V16QImode, notx, notx)
35305 : gen_rtx_AND (V16QImode, notx, notx));
35306 emit_insn (gen_rtx_SET (norreg, iorx));
35308 /* Permute with operands reversed and adjusted selector. */
35309 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35313 /* Copy into target, possibly by way of a register. */
35314 if (!REG_P (target))
35316 emit_move_insn (tmp, unspec);
35320 emit_move_insn (target, unspec);
35323 /* Expand an Altivec constant permutation. Return true if we match
35324 an efficient implementation; false to fall back to VPERM.
35326 OP0 and OP1 are the input vectors and TARGET is the output vector.
35327 SEL specifies the constant permutation vector. */
35330 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35331 const vec_perm_indices &sel)
35333 struct altivec_perm_insn {
35334 HOST_WIDE_INT mask;
35335 enum insn_code impl;
35336 unsigned char perm[16];
35338 static const struct altivec_perm_insn patterns[] = {
35339 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35340 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35341 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35342 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35343 { OPTION_MASK_ALTIVEC,
35344 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35345 : CODE_FOR_altivec_vmrglb_direct),
35346 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35347 { OPTION_MASK_ALTIVEC,
35348 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35349 : CODE_FOR_altivec_vmrglh_direct),
35350 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35351 { OPTION_MASK_ALTIVEC,
35352 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35353 : CODE_FOR_altivec_vmrglw_direct),
35354 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35355 { OPTION_MASK_ALTIVEC,
35356 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35357 : CODE_FOR_altivec_vmrghb_direct),
35358 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35359 { OPTION_MASK_ALTIVEC,
35360 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35361 : CODE_FOR_altivec_vmrghh_direct),
35362 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35363 { OPTION_MASK_ALTIVEC,
35364 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35365 : CODE_FOR_altivec_vmrghw_direct),
35366 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35367 { OPTION_MASK_P8_VECTOR,
35368 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35369 : CODE_FOR_p8_vmrgow_v4sf_direct),
35370 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35371 { OPTION_MASK_P8_VECTOR,
35372 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35373 : CODE_FOR_p8_vmrgew_v4sf_direct),
35374 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35377 unsigned int i, j, elt, which;
35378 unsigned char perm[16];
35382 /* Unpack the constant selector. */
35383 for (i = which = 0; i < 16; ++i)
35386 which |= (elt < 16 ? 1 : 2);
35390 /* Simplify the constant selector based on operands. */
35394 gcc_unreachable ();
35398 if (!rtx_equal_p (op0, op1))
35403 for (i = 0; i < 16; ++i)
35415 /* Look for splat patterns. */
35420 for (i = 0; i < 16; ++i)
35421 if (perm[i] != elt)
35425 if (!BYTES_BIG_ENDIAN)
35427 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35433 for (i = 0; i < 16; i += 2)
35434 if (perm[i] != elt || perm[i + 1] != elt + 1)
35438 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35439 x = gen_reg_rtx (V8HImode);
35440 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35442 emit_move_insn (target, gen_lowpart (V16QImode, x));
35449 for (i = 0; i < 16; i += 4)
35451 || perm[i + 1] != elt + 1
35452 || perm[i + 2] != elt + 2
35453 || perm[i + 3] != elt + 3)
35457 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35458 x = gen_reg_rtx (V4SImode);
35459 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35461 emit_move_insn (target, gen_lowpart (V16QImode, x));
35467 /* Look for merge and pack patterns. */
35468 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35472 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35475 elt = patterns[j].perm[0];
35476 if (perm[0] == elt)
35478 else if (perm[0] == elt + 16)
35482 for (i = 1; i < 16; ++i)
35484 elt = patterns[j].perm[i];
35486 elt = (elt >= 16 ? elt - 16 : elt + 16);
35487 else if (one_vec && elt >= 16)
35489 if (perm[i] != elt)
35494 enum insn_code icode = patterns[j].impl;
35495 machine_mode omode = insn_data[icode].operand[0].mode;
35496 machine_mode imode = insn_data[icode].operand[1].mode;
35498 /* For little-endian, don't use vpkuwum and vpkuhum if the
35499 underlying vector type is not V4SI and V8HI, respectively.
35500 For example, using vpkuwum with a V8HI picks up the even
35501 halfwords (BE numbering) when the even halfwords (LE
35502 numbering) are what we need. */
35503 if (!BYTES_BIG_ENDIAN
35504 && icode == CODE_FOR_altivec_vpkuwum_direct
35506 && GET_MODE (op0) != V4SImode)
35508 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35510 if (!BYTES_BIG_ENDIAN
35511 && icode == CODE_FOR_altivec_vpkuhum_direct
35513 && GET_MODE (op0) != V8HImode)
35515 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35518 /* For little-endian, the two input operands must be swapped
35519 (or swapped back) to ensure proper right-to-left numbering
35521 if (swapped ^ !BYTES_BIG_ENDIAN)
35522 std::swap (op0, op1);
35523 if (imode != V16QImode)
35525 op0 = gen_lowpart (imode, op0);
35526 op1 = gen_lowpart (imode, op1);
35528 if (omode == V16QImode)
35531 x = gen_reg_rtx (omode);
35532 emit_insn (GEN_FCN (icode) (x, op0, op1));
35533 if (omode != V16QImode)
35534 emit_move_insn (target, gen_lowpart (V16QImode, x));
35539 if (!BYTES_BIG_ENDIAN)
35541 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35548 /* Expand a VSX Permute Doubleword constant permutation.
35549 Return true if we match an efficient implementation. */
35552 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35553 unsigned char perm0, unsigned char perm1)
35557 /* If both selectors come from the same operand, fold to single op. */
35558 if ((perm0 & 2) == (perm1 & 2))
35565 /* If both operands are equal, fold to simpler permutation. */
35566 if (rtx_equal_p (op0, op1))
35569 perm1 = (perm1 & 1) + 2;
35571 /* If the first selector comes from the second operand, swap. */
35572 else if (perm0 & 2)
35578 std::swap (op0, op1);
35580 /* If the second selector does not come from the second operand, fail. */
35581 else if ((perm1 & 2) == 0)
35585 if (target != NULL)
35587 machine_mode vmode, dmode;
35590 vmode = GET_MODE (target);
35591 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35592 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35593 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35594 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35595 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35596 emit_insn (gen_rtx_SET (target, x));
35601 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35604 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35605 rtx op1, const vec_perm_indices &sel)
35607 bool testing_p = !target;
35609 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35610 if (TARGET_ALTIVEC && testing_p)
35613 /* Check for ps_merge* or xxpermdi insns. */
35614 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35618 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35619 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35621 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35625 if (TARGET_ALTIVEC)
35627 /* Force the target-independent code to lower to V16QImode. */
35628 if (vmode != V16QImode)
35630 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35637 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35638 OP0 and OP1 are the input vectors and TARGET is the output vector.
35639 PERM specifies the constant permutation vector. */
35642 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35643 machine_mode vmode, const vec_perm_builder &perm)
35645 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35647 emit_move_insn (target, x);
35650 /* Expand an extract even operation. */
35653 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35655 machine_mode vmode = GET_MODE (target);
35656 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35657 vec_perm_builder perm (nelt, nelt, 1);
35659 for (i = 0; i < nelt; i++)
35660 perm.quick_push (i * 2);
35662 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35665 /* Expand a vector interleave operation. */
35668 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35670 machine_mode vmode = GET_MODE (target);
35671 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35672 vec_perm_builder perm (nelt, nelt, 1);
35674 high = (highp ? 0 : nelt / 2);
35675 for (i = 0; i < nelt / 2; i++)
35677 perm.quick_push (i + high);
35678 perm.quick_push (i + nelt + high);
35681 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35684 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35686 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35688 HOST_WIDE_INT hwi_scale (scale);
35689 REAL_VALUE_TYPE r_pow;
35690 rtvec v = rtvec_alloc (2);
35692 rtx scale_vec = gen_reg_rtx (V2DFmode);
35693 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35694 elt = const_double_from_real_value (r_pow, DFmode);
35695 RTVEC_ELT (v, 0) = elt;
35696 RTVEC_ELT (v, 1) = elt;
35697 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35698 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35701 /* Return an RTX representing where to find the function value of a
35702 function returning MODE. */
35704 rs6000_complex_function_value (machine_mode mode)
35706 unsigned int regno;
35708 machine_mode inner = GET_MODE_INNER (mode);
35709 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35711 if (TARGET_FLOAT128_TYPE
35713 || (mode == TCmode && TARGET_IEEEQUAD)))
35714 regno = ALTIVEC_ARG_RETURN;
35716 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35717 regno = FP_ARG_RETURN;
35721 regno = GP_ARG_RETURN;
35723 /* 32-bit is OK since it'll go in r3/r4. */
35724 if (TARGET_32BIT && inner_bytes >= 4)
35725 return gen_rtx_REG (mode, regno);
35728 if (inner_bytes >= 8)
35729 return gen_rtx_REG (mode, regno);
35731 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35733 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35734 GEN_INT (inner_bytes));
35735 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35738 /* Return an rtx describing a return value of MODE as a PARALLEL
35739 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35740 stride REG_STRIDE. */
35743 rs6000_parallel_return (machine_mode mode,
35744 int n_elts, machine_mode elt_mode,
35745 unsigned int regno, unsigned int reg_stride)
35747 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35750 for (i = 0; i < n_elts; i++)
35752 rtx r = gen_rtx_REG (elt_mode, regno);
35753 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35754 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35755 regno += reg_stride;
35761 /* Target hook for TARGET_FUNCTION_VALUE.
35763 An integer value is in r3 and a floating-point value is in fp1,
35764 unless -msoft-float. */
35767 rs6000_function_value (const_tree valtype,
35768 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35769 bool outgoing ATTRIBUTE_UNUSED)
35772 unsigned int regno;
35773 machine_mode elt_mode;
35776 /* Special handling for structs in darwin64. */
35778 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35780 CUMULATIVE_ARGS valcum;
35784 valcum.fregno = FP_ARG_MIN_REG;
35785 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35786 /* Do a trial code generation as if this were going to be passed as
35787 an argument; if any part goes in memory, we return NULL. */
35788 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35791 /* Otherwise fall through to standard ABI rules. */
35794 mode = TYPE_MODE (valtype);
35796 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35797 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35799 int first_reg, n_regs;
35801 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35803 /* _Decimal128 must use even/odd register pairs. */
35804 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35805 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35809 first_reg = ALTIVEC_ARG_RETURN;
35813 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35816 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35817 if (TARGET_32BIT && TARGET_POWERPC64)
35826 int count = GET_MODE_SIZE (mode) / 4;
35827 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35830 if ((INTEGRAL_TYPE_P (valtype)
35831 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35832 || POINTER_TYPE_P (valtype))
35833 mode = TARGET_32BIT ? SImode : DImode;
35835 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35836 /* _Decimal128 must use an even/odd register pair. */
35837 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35838 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
35839 && !FLOAT128_VECTOR_P (mode))
35840 regno = FP_ARG_RETURN;
35841 else if (TREE_CODE (valtype) == COMPLEX_TYPE
35842 && targetm.calls.split_complex_arg)
35843 return rs6000_complex_function_value (mode);
35844 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35845 return register is used in both cases, and we won't see V2DImode/V2DFmode
35846 for pure altivec, combine the two cases. */
35847 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
35848 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
35849 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
35850 regno = ALTIVEC_ARG_RETURN;
35852 regno = GP_ARG_RETURN;
35854 return gen_rtx_REG (mode, regno);
35857 /* Define how to find the value returned by a library function
35858 assuming the value has mode MODE. */
35860 rs6000_libcall_value (machine_mode mode)
35862 unsigned int regno;
35864 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35865 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
35866 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
35868 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35869 /* _Decimal128 must use an even/odd register pair. */
35870 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35871 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
35872 regno = FP_ARG_RETURN;
35873 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35874 return register is used in both cases, and we won't see V2DImode/V2DFmode
35875 for pure altivec, combine the two cases. */
35876 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
35877 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
35878 regno = ALTIVEC_ARG_RETURN;
35879 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
35880 return rs6000_complex_function_value (mode);
35882 regno = GP_ARG_RETURN;
35884 return gen_rtx_REG (mode, regno);
35887 /* Compute register pressure classes. We implement the target hook to avoid
35888 IRA picking something like GEN_OR_FLOAT_REGS as a pressure class, which can
35889 lead to incorrect estimates of number of available registers and therefor
35890 increased register pressure/spill. */
35892 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
35897 pressure_classes[n++] = GENERAL_REGS;
35899 pressure_classes[n++] = VSX_REGS;
35902 if (TARGET_ALTIVEC)
35903 pressure_classes[n++] = ALTIVEC_REGS;
35904 if (TARGET_HARD_FLOAT)
35905 pressure_classes[n++] = FLOAT_REGS;
35907 pressure_classes[n++] = CR_REGS;
35908 pressure_classes[n++] = SPECIAL_REGS;
35913 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35914 Frame pointer elimination is automatically handled.
35916 For the RS/6000, if frame pointer elimination is being done, we would like
35917 to convert ap into fp, not sp.
35919 We need r30 if -mminimal-toc was specified, and there are constant pool
35923 rs6000_can_eliminate (const int from, const int to)
35925 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
35926 ? ! frame_pointer_needed
35927 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
35928 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
35929 || constant_pool_empty_p ()
35933 /* Define the offset between two registers, FROM to be eliminated and its
35934 replacement TO, at the start of a routine. */
35936 rs6000_initial_elimination_offset (int from, int to)
35938 rs6000_stack_t *info = rs6000_stack_info ();
35939 HOST_WIDE_INT offset;
35941 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35942 offset = info->push_p ? 0 : -info->total_size;
35943 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35945 offset = info->push_p ? 0 : -info->total_size;
35946 if (FRAME_GROWS_DOWNWARD)
35947 offset += info->fixed_size + info->vars_size + info->parm_size;
35949 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35950 offset = FRAME_GROWS_DOWNWARD
35951 ? info->fixed_size + info->vars_size + info->parm_size
35953 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35954 offset = info->total_size;
35955 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35956 offset = info->push_p ? info->total_size : 0;
35957 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
35960 gcc_unreachable ();
35965 /* Fill in sizes of registers used by unwinder. */
35968 rs6000_init_dwarf_reg_sizes_extra (tree address)
35970 if (TARGET_MACHO && ! TARGET_ALTIVEC)
35973 machine_mode mode = TYPE_MODE (char_type_node);
35974 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
35975 rtx mem = gen_rtx_MEM (BLKmode, addr);
35976 rtx value = gen_int_mode (16, mode);
35978 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35979 The unwinder still needs to know the size of Altivec registers. */
35981 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
35983 int column = DWARF_REG_TO_UNWIND_COLUMN
35984 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
35985 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
35987 emit_move_insn (adjust_address (mem, mode, offset), value);
35992 /* Map internal gcc register numbers to debug format register numbers.
35993 FORMAT specifies the type of debug register number to use:
35994 0 -- debug information, except for frame-related sections
35995 1 -- DWARF .debug_frame section
35996 2 -- DWARF .eh_frame section */
35999 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36001 /* On some platforms, we use the standard DWARF register
36002 numbering for .debug_info and .debug_frame. */
36003 if ((format == 0 && write_symbols == DWARF2_DEBUG) || format == 1)
36005 #ifdef RS6000_USE_DWARF_NUMBERING
36008 if (FP_REGNO_P (regno))
36009 return regno - FIRST_FPR_REGNO + 32;
36010 if (ALTIVEC_REGNO_P (regno))
36011 return regno - FIRST_ALTIVEC_REGNO + 1124;
36012 if (regno == LR_REGNO)
36014 if (regno == CTR_REGNO)
36016 if (regno == CA_REGNO)
36017 return 101; /* XER */
36018 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36019 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36020 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36021 to the DWARF reg for CR. */
36022 if (format == 1 && regno == CR2_REGNO)
36024 if (CR_REGNO_P (regno))
36025 return regno - CR0_REGNO + 86;
36026 if (regno == VRSAVE_REGNO)
36028 if (regno == VSCR_REGNO)
36031 /* These do not make much sense. */
36032 if (regno == FRAME_POINTER_REGNUM)
36034 if (regno == ARG_POINTER_REGNUM)
36039 gcc_unreachable ();
36043 /* We use the GCC 7 (and before) internal number for non-DWARF debug
36044 information, and also for .eh_frame. */
36045 /* Translate the regnos to their numbers in GCC 7 (and before). */
36048 if (FP_REGNO_P (regno))
36049 return regno - FIRST_FPR_REGNO + 32;
36050 if (ALTIVEC_REGNO_P (regno))
36051 return regno - FIRST_ALTIVEC_REGNO + 77;
36052 if (regno == LR_REGNO)
36054 if (regno == CTR_REGNO)
36056 if (regno == CA_REGNO)
36057 return 76; /* XER */
36058 if (CR_REGNO_P (regno))
36059 return regno - CR0_REGNO + 68;
36060 if (regno == VRSAVE_REGNO)
36062 if (regno == VSCR_REGNO)
36065 if (regno == FRAME_POINTER_REGNUM)
36067 if (regno == ARG_POINTER_REGNUM)
36072 gcc_unreachable ();
36075 /* target hook eh_return_filter_mode */
36076 static scalar_int_mode
36077 rs6000_eh_return_filter_mode (void)
36079 return TARGET_32BIT ? SImode : word_mode;
36082 /* Target hook for translate_mode_attribute. */
36083 static machine_mode
36084 rs6000_translate_mode_attribute (machine_mode mode)
36086 if ((FLOAT128_IEEE_P (mode)
36087 && ieee128_float_type_node == long_double_type_node)
36088 || (FLOAT128_IBM_P (mode)
36089 && ibm128_float_type_node == long_double_type_node))
36090 return COMPLEX_MODE_P (mode) ? E_TCmode : E_TFmode;
36094 /* Target hook for scalar_mode_supported_p. */
36096 rs6000_scalar_mode_supported_p (scalar_mode mode)
36098 /* -m32 does not support TImode. This is the default, from
36099 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36100 same ABI as for -m32. But default_scalar_mode_supported_p allows
36101 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36102 for -mpowerpc64. */
36103 if (TARGET_32BIT && mode == TImode)
36106 if (DECIMAL_FLOAT_MODE_P (mode))
36107 return default_decimal_float_supported_p ();
36108 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36111 return default_scalar_mode_supported_p (mode);
36114 /* Target hook for vector_mode_supported_p. */
36116 rs6000_vector_mode_supported_p (machine_mode mode)
36118 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36119 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36121 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36128 /* Target hook for floatn_mode. */
36129 static opt_scalar_float_mode
36130 rs6000_floatn_mode (int n, bool extended)
36140 if (TARGET_FLOAT128_TYPE)
36141 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36143 return opt_scalar_float_mode ();
36146 return opt_scalar_float_mode ();
36149 /* Those are the only valid _FloatNx types. */
36150 gcc_unreachable ();
36164 if (TARGET_FLOAT128_TYPE)
36165 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36167 return opt_scalar_float_mode ();
36170 return opt_scalar_float_mode ();
36176 /* Target hook for c_mode_for_suffix. */
36177 static machine_mode
36178 rs6000_c_mode_for_suffix (char suffix)
36180 if (TARGET_FLOAT128_TYPE)
36182 if (suffix == 'q' || suffix == 'Q')
36183 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36185 /* At the moment, we are not defining a suffix for IBM extended double.
36186 If/when the default for -mabi=ieeelongdouble is changed, and we want
36187 to support __ibm128 constants in legacy library code, we may need to
36188 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36189 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36190 __float80 constants. */
36196 /* Target hook for invalid_arg_for_unprototyped_fn. */
36197 static const char *
36198 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36200 return (!rs6000_darwin64_abi
36202 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36203 && (funcdecl == NULL_TREE
36204 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36205 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36206 ? N_("AltiVec argument passed to unprototyped function")
36210 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36211 setup by using __stack_chk_fail_local hidden function instead of
36212 calling __stack_chk_fail directly. Otherwise it is better to call
36213 __stack_chk_fail directly. */
36215 static tree ATTRIBUTE_UNUSED
36216 rs6000_stack_protect_fail (void)
36218 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36219 ? default_hidden_stack_protect_fail ()
36220 : default_external_stack_protect_fail ();
36223 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36226 static unsigned HOST_WIDE_INT
36227 rs6000_asan_shadow_offset (void)
36229 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36233 /* Mask options that we want to support inside of attribute((target)) and
36234 #pragma GCC target operations. Note, we do not include things like
36235 64/32-bit, endianness, hard/soft floating point, etc. that would have
36236 different calling sequences. */
36238 struct rs6000_opt_mask {
36239 const char *name; /* option name */
36240 HOST_WIDE_INT mask; /* mask to set */
36241 bool invert; /* invert sense of mask */
36242 bool valid_target; /* option is a target option */
36245 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36247 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36248 { "cmpb", OPTION_MASK_CMPB, false, true },
36249 { "crypto", OPTION_MASK_CRYPTO, false, true },
36250 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36251 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36252 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36254 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36255 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36256 { "fprnd", OPTION_MASK_FPRND, false, true },
36257 { "hard-dfp", OPTION_MASK_DFP, false, true },
36258 { "htm", OPTION_MASK_HTM, false, true },
36259 { "isel", OPTION_MASK_ISEL, false, true },
36260 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36261 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36262 { "modulo", OPTION_MASK_MODULO, false, true },
36263 { "mulhw", OPTION_MASK_MULHW, false, true },
36264 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36265 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36266 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36267 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36268 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36269 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36270 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36271 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36272 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36273 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36274 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36275 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36276 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36277 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36278 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36279 { "string", 0, false, true },
36280 { "update", OPTION_MASK_NO_UPDATE, true , true },
36281 { "vsx", OPTION_MASK_VSX, false, true },
36282 #ifdef OPTION_MASK_64BIT
36284 { "aix64", OPTION_MASK_64BIT, false, false },
36285 { "aix32", OPTION_MASK_64BIT, true, false },
36287 { "64", OPTION_MASK_64BIT, false, false },
36288 { "32", OPTION_MASK_64BIT, true, false },
36291 #ifdef OPTION_MASK_EABI
36292 { "eabi", OPTION_MASK_EABI, false, false },
36294 #ifdef OPTION_MASK_LITTLE_ENDIAN
36295 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36296 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36298 #ifdef OPTION_MASK_RELOCATABLE
36299 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36301 #ifdef OPTION_MASK_STRICT_ALIGN
36302 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36304 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36305 { "string", 0, false, false },
36308 /* Builtin mask mapping for printing the flags. */
36309 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36311 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36312 { "vsx", RS6000_BTM_VSX, false, false },
36313 { "fre", RS6000_BTM_FRE, false, false },
36314 { "fres", RS6000_BTM_FRES, false, false },
36315 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36316 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36317 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36318 { "cell", RS6000_BTM_CELL, false, false },
36319 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36320 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36321 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36322 { "crypto", RS6000_BTM_CRYPTO, false, false },
36323 { "htm", RS6000_BTM_HTM, false, false },
36324 { "hard-dfp", RS6000_BTM_DFP, false, false },
36325 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36326 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36327 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
36328 { "float128", RS6000_BTM_FLOAT128, false, false },
36329 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36332 /* Option variables that we want to support inside attribute((target)) and
36333 #pragma GCC target operations. */
36335 struct rs6000_opt_var {
36336 const char *name; /* option name */
36337 size_t global_offset; /* offset of the option in global_options. */
36338 size_t target_offset; /* offset of the option in target options. */
36341 static struct rs6000_opt_var const rs6000_opt_vars[] =
36344 offsetof (struct gcc_options, x_TARGET_FRIZ),
36345 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36346 { "avoid-indexed-addresses",
36347 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36348 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36350 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36351 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36352 { "optimize-swaps",
36353 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36354 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36355 { "allow-movmisalign",
36356 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36357 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36359 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36360 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36362 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36363 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36364 { "align-branch-targets",
36365 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36366 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36368 offsetof (struct gcc_options, x_tls_markers),
36369 offsetof (struct cl_target_option, x_tls_markers), },
36371 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36372 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36374 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36375 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36376 { "speculate-indirect-jumps",
36377 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36378 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36381 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36382 parsing. Return true if there were no errors. */
36385 rs6000_inner_target_options (tree args, bool attr_p)
36389 if (args == NULL_TREE)
36392 else if (TREE_CODE (args) == STRING_CST)
36394 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36397 while ((q = strtok (p, ",")) != NULL)
36399 bool error_p = false;
36400 bool not_valid_p = false;
36401 const char *cpu_opt = NULL;
36404 if (strncmp (q, "cpu=", 4) == 0)
36406 int cpu_index = rs6000_cpu_name_lookup (q+4);
36407 if (cpu_index >= 0)
36408 rs6000_cpu_index = cpu_index;
36415 else if (strncmp (q, "tune=", 5) == 0)
36417 int tune_index = rs6000_cpu_name_lookup (q+5);
36418 if (tune_index >= 0)
36419 rs6000_tune_index = tune_index;
36429 bool invert = false;
36433 if (strncmp (r, "no-", 3) == 0)
36439 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36440 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36442 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36444 if (!rs6000_opt_masks[i].valid_target)
36445 not_valid_p = true;
36449 rs6000_isa_flags_explicit |= mask;
36451 /* VSX needs altivec, so -mvsx automagically sets
36452 altivec and disables -mavoid-indexed-addresses. */
36455 if (mask == OPTION_MASK_VSX)
36457 mask |= OPTION_MASK_ALTIVEC;
36458 TARGET_AVOID_XFORM = 0;
36462 if (rs6000_opt_masks[i].invert)
36466 rs6000_isa_flags &= ~mask;
36468 rs6000_isa_flags |= mask;
36473 if (error_p && !not_valid_p)
36475 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36476 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36478 size_t j = rs6000_opt_vars[i].global_offset;
36479 *((int *) ((char *)&global_options + j)) = !invert;
36481 not_valid_p = false;
36489 const char *eprefix, *esuffix;
36494 eprefix = "__attribute__((__target__(";
36499 eprefix = "#pragma GCC target ";
36504 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36506 else if (not_valid_p)
36507 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36509 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36514 else if (TREE_CODE (args) == TREE_LIST)
36518 tree value = TREE_VALUE (args);
36521 bool ret2 = rs6000_inner_target_options (value, attr_p);
36525 args = TREE_CHAIN (args);
36527 while (args != NULL_TREE);
36532 error ("attribute %<target%> argument not a string");
36539 /* Print out the target options as a list for -mdebug=target. */
36542 rs6000_debug_target_options (tree args, const char *prefix)
36544 if (args == NULL_TREE)
36545 fprintf (stderr, "%s<NULL>", prefix);
36547 else if (TREE_CODE (args) == STRING_CST)
36549 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36552 while ((q = strtok (p, ",")) != NULL)
36555 fprintf (stderr, "%s\"%s\"", prefix, q);
36560 else if (TREE_CODE (args) == TREE_LIST)
36564 tree value = TREE_VALUE (args);
36567 rs6000_debug_target_options (value, prefix);
36570 args = TREE_CHAIN (args);
36572 while (args != NULL_TREE);
36576 gcc_unreachable ();
36582 /* Hook to validate attribute((target("..."))). */
36585 rs6000_valid_attribute_p (tree fndecl,
36586 tree ARG_UNUSED (name),
36590 struct cl_target_option cur_target;
36593 tree new_target, new_optimize;
36594 tree func_optimize;
36596 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36598 if (TARGET_DEBUG_TARGET)
36600 tree tname = DECL_NAME (fndecl);
36601 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36603 fprintf (stderr, "function: %.*s\n",
36604 (int) IDENTIFIER_LENGTH (tname),
36605 IDENTIFIER_POINTER (tname));
36607 fprintf (stderr, "function: unknown\n");
36609 fprintf (stderr, "args:");
36610 rs6000_debug_target_options (args, " ");
36611 fprintf (stderr, "\n");
36614 fprintf (stderr, "flags: 0x%x\n", flags);
36616 fprintf (stderr, "--------------------\n");
36619 /* attribute((target("default"))) does nothing, beyond
36620 affecting multi-versioning. */
36621 if (TREE_VALUE (args)
36622 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36623 && TREE_CHAIN (args) == NULL_TREE
36624 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36627 old_optimize = build_optimization_node (&global_options);
36628 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36630 /* If the function changed the optimization levels as well as setting target
36631 options, start with the optimizations specified. */
36632 if (func_optimize && func_optimize != old_optimize)
36633 cl_optimization_restore (&global_options,
36634 TREE_OPTIMIZATION (func_optimize));
36636 /* The target attributes may also change some optimization flags, so update
36637 the optimization options if necessary. */
36638 cl_target_option_save (&cur_target, &global_options);
36639 rs6000_cpu_index = rs6000_tune_index = -1;
36640 ret = rs6000_inner_target_options (args, true);
36642 /* Set up any additional state. */
36645 ret = rs6000_option_override_internal (false);
36646 new_target = build_target_option_node (&global_options);
36651 new_optimize = build_optimization_node (&global_options);
36658 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36660 if (old_optimize != new_optimize)
36661 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36664 cl_target_option_restore (&global_options, &cur_target);
36666 if (old_optimize != new_optimize)
36667 cl_optimization_restore (&global_options,
36668 TREE_OPTIMIZATION (old_optimize));
36674 /* Hook to validate the current #pragma GCC target and set the state, and
36675 update the macros based on what was changed. If ARGS is NULL, then
36676 POP_TARGET is used to reset the options. */
36679 rs6000_pragma_target_parse (tree args, tree pop_target)
36681 tree prev_tree = build_target_option_node (&global_options);
36683 struct cl_target_option *prev_opt, *cur_opt;
36684 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36685 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36687 if (TARGET_DEBUG_TARGET)
36689 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36690 fprintf (stderr, "args:");
36691 rs6000_debug_target_options (args, " ");
36692 fprintf (stderr, "\n");
36696 fprintf (stderr, "pop_target:\n");
36697 debug_tree (pop_target);
36700 fprintf (stderr, "pop_target: <NULL>\n");
36702 fprintf (stderr, "--------------------\n");
36707 cur_tree = ((pop_target)
36709 : target_option_default_node);
36710 cl_target_option_restore (&global_options,
36711 TREE_TARGET_OPTION (cur_tree));
36715 rs6000_cpu_index = rs6000_tune_index = -1;
36716 if (!rs6000_inner_target_options (args, false)
36717 || !rs6000_option_override_internal (false)
36718 || (cur_tree = build_target_option_node (&global_options))
36721 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36722 fprintf (stderr, "invalid pragma\n");
36728 target_option_current_node = cur_tree;
36729 rs6000_activate_target_options (target_option_current_node);
36731 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36732 change the macros that are defined. */
36733 if (rs6000_target_modify_macros_ptr)
36735 prev_opt = TREE_TARGET_OPTION (prev_tree);
36736 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36737 prev_flags = prev_opt->x_rs6000_isa_flags;
36739 cur_opt = TREE_TARGET_OPTION (cur_tree);
36740 cur_flags = cur_opt->x_rs6000_isa_flags;
36741 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36743 diff_bumask = (prev_bumask ^ cur_bumask);
36744 diff_flags = (prev_flags ^ cur_flags);
36746 if ((diff_flags != 0) || (diff_bumask != 0))
36748 /* Delete old macros. */
36749 rs6000_target_modify_macros_ptr (false,
36750 prev_flags & diff_flags,
36751 prev_bumask & diff_bumask);
36753 /* Define new macros. */
36754 rs6000_target_modify_macros_ptr (true,
36755 cur_flags & diff_flags,
36756 cur_bumask & diff_bumask);
36764 /* Remember the last target of rs6000_set_current_function. */
36765 static GTY(()) tree rs6000_previous_fndecl;
36767 /* Restore target's globals from NEW_TREE and invalidate the
36768 rs6000_previous_fndecl cache. */
36771 rs6000_activate_target_options (tree new_tree)
36773 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36774 if (TREE_TARGET_GLOBALS (new_tree))
36775 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36776 else if (new_tree == target_option_default_node)
36777 restore_target_globals (&default_target_globals);
36779 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36780 rs6000_previous_fndecl = NULL_TREE;
36783 /* Establish appropriate back-end context for processing the function
36784 FNDECL. The argument might be NULL to indicate processing at top
36785 level, outside of any function scope. */
36787 rs6000_set_current_function (tree fndecl)
36789 if (TARGET_DEBUG_TARGET)
36791 fprintf (stderr, "\n==================== rs6000_set_current_function");
36794 fprintf (stderr, ", fndecl %s (%p)",
36795 (DECL_NAME (fndecl)
36796 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36797 : "<unknown>"), (void *)fndecl);
36799 if (rs6000_previous_fndecl)
36800 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36802 fprintf (stderr, "\n");
36805 /* Only change the context if the function changes. This hook is called
36806 several times in the course of compiling a function, and we don't want to
36807 slow things down too much or call target_reinit when it isn't safe. */
36808 if (fndecl == rs6000_previous_fndecl)
36812 if (rs6000_previous_fndecl == NULL_TREE)
36813 old_tree = target_option_current_node;
36814 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36815 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36817 old_tree = target_option_default_node;
36820 if (fndecl == NULL_TREE)
36822 if (old_tree != target_option_current_node)
36823 new_tree = target_option_current_node;
36825 new_tree = NULL_TREE;
36829 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36830 if (new_tree == NULL_TREE)
36831 new_tree = target_option_default_node;
36834 if (TARGET_DEBUG_TARGET)
36838 fprintf (stderr, "\nnew fndecl target specific options:\n");
36839 debug_tree (new_tree);
36844 fprintf (stderr, "\nold fndecl target specific options:\n");
36845 debug_tree (old_tree);
36848 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
36849 fprintf (stderr, "--------------------\n");
36852 if (new_tree && old_tree != new_tree)
36853 rs6000_activate_target_options (new_tree);
36856 rs6000_previous_fndecl = fndecl;
36860 /* Save the current options */
36863 rs6000_function_specific_save (struct cl_target_option *ptr,
36864 struct gcc_options *opts)
36866 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
36867 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
36870 /* Restore the current options */
36873 rs6000_function_specific_restore (struct gcc_options *opts,
36874 struct cl_target_option *ptr)
36877 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
36878 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
36879 (void) rs6000_option_override_internal (false);
36882 /* Print the current options */
36885 rs6000_function_specific_print (FILE *file, int indent,
36886 struct cl_target_option *ptr)
36888 rs6000_print_isa_options (file, indent, "Isa options set",
36889 ptr->x_rs6000_isa_flags);
36891 rs6000_print_isa_options (file, indent, "Isa options explicit",
36892 ptr->x_rs6000_isa_flags_explicit);
36895 /* Helper function to print the current isa or misc options on a line. */
36898 rs6000_print_options_internal (FILE *file,
36900 const char *string,
36901 HOST_WIDE_INT flags,
36902 const char *prefix,
36903 const struct rs6000_opt_mask *opts,
36904 size_t num_elements)
36907 size_t start_column = 0;
36909 size_t max_column = 120;
36910 size_t prefix_len = strlen (prefix);
36911 size_t comma_len = 0;
36912 const char *comma = "";
36915 start_column += fprintf (file, "%*s", indent, "");
36919 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
36923 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
36925 /* Print the various mask options. */
36926 cur_column = start_column;
36927 for (i = 0; i < num_elements; i++)
36929 bool invert = opts[i].invert;
36930 const char *name = opts[i].name;
36931 const char *no_str = "";
36932 HOST_WIDE_INT mask = opts[i].mask;
36933 size_t len = comma_len + prefix_len + strlen (name);
36937 if ((flags & mask) == 0)
36940 len += sizeof ("no-") - 1;
36948 if ((flags & mask) != 0)
36951 len += sizeof ("no-") - 1;
36958 if (cur_column > max_column)
36960 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
36961 cur_column = start_column + len;
36965 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
36967 comma_len = sizeof (", ") - 1;
36970 fputs ("\n", file);
36973 /* Helper function to print the current isa options on a line. */
36976 rs6000_print_isa_options (FILE *file, int indent, const char *string,
36977 HOST_WIDE_INT flags)
36979 rs6000_print_options_internal (file, indent, string, flags, "-m",
36980 &rs6000_opt_masks[0],
36981 ARRAY_SIZE (rs6000_opt_masks));
36985 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
36986 HOST_WIDE_INT flags)
36988 rs6000_print_options_internal (file, indent, string, flags, "",
36989 &rs6000_builtin_mask_names[0],
36990 ARRAY_SIZE (rs6000_builtin_mask_names));
36993 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36994 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36995 -mupper-regs-df, etc.).
36997 If the user used -mno-power8-vector, we need to turn off all of the implicit
36998 ISA 2.07 and 3.0 options that relate to the vector unit.
37000 If the user used -mno-power9-vector, we need to turn off all of the implicit
37001 ISA 3.0 options that relate to the vector unit.
37003 This function does not handle explicit options such as the user specifying
37004 -mdirect-move. These are handled in rs6000_option_override_internal, and
37005 the appropriate error is given if needed.
37007 We return a mask of all of the implicit options that should not be enabled
37010 static HOST_WIDE_INT
37011 rs6000_disable_incompatible_switches (void)
37013 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37016 static const struct {
37017 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37018 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37019 const char *const name; /* name of the switch. */
37021 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37022 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37023 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37026 for (i = 0; i < ARRAY_SIZE (flags); i++)
37028 HOST_WIDE_INT no_flag = flags[i].no_flag;
37030 if ((rs6000_isa_flags & no_flag) == 0
37031 && (rs6000_isa_flags_explicit & no_flag) != 0)
37033 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37034 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37040 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37041 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37043 set_flags &= ~rs6000_opt_masks[j].mask;
37044 error ("%<-mno-%s%> turns off %<-m%s%>",
37046 rs6000_opt_masks[j].name);
37049 gcc_assert (!set_flags);
37052 rs6000_isa_flags &= ~dep_flags;
37053 ignore_masks |= no_flag | dep_flags;
37057 return ignore_masks;
37061 /* Helper function for printing the function name when debugging. */
37063 static const char *
37064 get_decl_name (tree fn)
37071 name = DECL_NAME (fn);
37073 return "<no-name>";
37075 return IDENTIFIER_POINTER (name);
37078 /* Return the clone id of the target we are compiling code for in a target
37079 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37080 the priority list for the target clones (ordered from lowest to
37084 rs6000_clone_priority (tree fndecl)
37086 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37087 HOST_WIDE_INT isa_masks;
37088 int ret = CLONE_DEFAULT;
37089 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37090 const char *attrs_str = NULL;
37092 attrs = TREE_VALUE (TREE_VALUE (attrs));
37093 attrs_str = TREE_STRING_POINTER (attrs);
37095 /* Return priority zero for default function. Return the ISA needed for the
37096 function if it is not the default. */
37097 if (strcmp (attrs_str, "default") != 0)
37099 if (fn_opts == NULL_TREE)
37100 fn_opts = target_option_default_node;
37102 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37103 isa_masks = rs6000_isa_flags;
37105 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37107 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37108 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37112 if (TARGET_DEBUG_TARGET)
37113 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37114 get_decl_name (fndecl), ret);
37119 /* This compares the priority of target features in function DECL1 and DECL2.
37120 It returns positive value if DECL1 is higher priority, negative value if
37121 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37122 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37125 rs6000_compare_version_priority (tree decl1, tree decl2)
37127 int priority1 = rs6000_clone_priority (decl1);
37128 int priority2 = rs6000_clone_priority (decl2);
37129 int ret = priority1 - priority2;
37131 if (TARGET_DEBUG_TARGET)
37132 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37133 get_decl_name (decl1), get_decl_name (decl2), ret);
37138 /* Make a dispatcher declaration for the multi-versioned function DECL.
37139 Calls to DECL function will be replaced with calls to the dispatcher
37140 by the front-end. Returns the decl of the dispatcher function. */
37143 rs6000_get_function_versions_dispatcher (void *decl)
37145 tree fn = (tree) decl;
37146 struct cgraph_node *node = NULL;
37147 struct cgraph_node *default_node = NULL;
37148 struct cgraph_function_version_info *node_v = NULL;
37149 struct cgraph_function_version_info *first_v = NULL;
37151 tree dispatch_decl = NULL;
37153 struct cgraph_function_version_info *default_version_info = NULL;
37154 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37156 if (TARGET_DEBUG_TARGET)
37157 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37158 get_decl_name (fn));
37160 node = cgraph_node::get (fn);
37161 gcc_assert (node != NULL);
37163 node_v = node->function_version ();
37164 gcc_assert (node_v != NULL);
37166 if (node_v->dispatcher_resolver != NULL)
37167 return node_v->dispatcher_resolver;
37169 /* Find the default version and make it the first node. */
37171 /* Go to the beginning of the chain. */
37172 while (first_v->prev != NULL)
37173 first_v = first_v->prev;
37175 default_version_info = first_v;
37176 while (default_version_info != NULL)
37178 const tree decl2 = default_version_info->this_node->decl;
37179 if (is_function_default_version (decl2))
37181 default_version_info = default_version_info->next;
37184 /* If there is no default node, just return NULL. */
37185 if (default_version_info == NULL)
37188 /* Make default info the first node. */
37189 if (first_v != default_version_info)
37191 default_version_info->prev->next = default_version_info->next;
37192 if (default_version_info->next)
37193 default_version_info->next->prev = default_version_info->prev;
37194 first_v->prev = default_version_info;
37195 default_version_info->next = first_v;
37196 default_version_info->prev = NULL;
37199 default_node = default_version_info->this_node;
37201 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37202 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37203 "%<target_clones%> attribute needs GLIBC (2.23 and newer) that "
37204 "exports hardware capability bits");
37207 if (targetm.has_ifunc_p ())
37209 struct cgraph_function_version_info *it_v = NULL;
37210 struct cgraph_node *dispatcher_node = NULL;
37211 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37213 /* Right now, the dispatching is done via ifunc. */
37214 dispatch_decl = make_dispatcher_decl (default_node->decl);
37216 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37217 gcc_assert (dispatcher_node != NULL);
37218 dispatcher_node->dispatcher_function = 1;
37219 dispatcher_version_info
37220 = dispatcher_node->insert_new_function_version ();
37221 dispatcher_version_info->next = default_version_info;
37222 dispatcher_node->definition = 1;
37224 /* Set the dispatcher for all the versions. */
37225 it_v = default_version_info;
37226 while (it_v != NULL)
37228 it_v->dispatcher_resolver = dispatch_decl;
37234 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37235 "multiversioning needs ifunc which is not supported "
37240 return dispatch_decl;
37243 /* Make the resolver function decl to dispatch the versions of a multi-
37244 versioned function, DEFAULT_DECL. Create an empty basic block in the
37245 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37249 make_resolver_func (const tree default_decl,
37250 const tree dispatch_decl,
37251 basic_block *empty_bb)
37253 /* Make the resolver function static. The resolver function returns
37255 tree decl_name = clone_function_name (default_decl, "resolver");
37256 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37257 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37258 tree decl = build_fn_decl (resolver_name, type);
37259 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37261 DECL_NAME (decl) = decl_name;
37262 TREE_USED (decl) = 1;
37263 DECL_ARTIFICIAL (decl) = 1;
37264 DECL_IGNORED_P (decl) = 0;
37265 TREE_PUBLIC (decl) = 0;
37266 DECL_UNINLINABLE (decl) = 1;
37268 /* Resolver is not external, body is generated. */
37269 DECL_EXTERNAL (decl) = 0;
37270 DECL_EXTERNAL (dispatch_decl) = 0;
37272 DECL_CONTEXT (decl) = NULL_TREE;
37273 DECL_INITIAL (decl) = make_node (BLOCK);
37274 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37276 /* Build result decl and add to function_decl. */
37277 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37278 DECL_CONTEXT (t) = decl;
37279 DECL_ARTIFICIAL (t) = 1;
37280 DECL_IGNORED_P (t) = 1;
37281 DECL_RESULT (decl) = t;
37283 gimplify_function_tree (decl);
37284 push_cfun (DECL_STRUCT_FUNCTION (decl));
37285 *empty_bb = init_lowered_empty_function (decl, false,
37286 profile_count::uninitialized ());
37288 cgraph_node::add_new_function (decl, true);
37289 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37293 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37294 DECL_ATTRIBUTES (dispatch_decl)
37295 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37297 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37302 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37303 return a pointer to VERSION_DECL if we are running on a machine that
37304 supports the index CLONE_ISA hardware architecture bits. This function will
37305 be called during version dispatch to decide which function version to
37306 execute. It returns the basic block at the end, to which more conditions
37310 add_condition_to_bb (tree function_decl, tree version_decl,
37311 int clone_isa, basic_block new_bb)
37313 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37315 gcc_assert (new_bb != NULL);
37316 gimple_seq gseq = bb_seq (new_bb);
37319 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37320 build_fold_addr_expr (version_decl));
37321 tree result_var = create_tmp_var (ptr_type_node);
37322 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37323 gimple *return_stmt = gimple_build_return (result_var);
37325 if (clone_isa == CLONE_DEFAULT)
37327 gimple_seq_add_stmt (&gseq, convert_stmt);
37328 gimple_seq_add_stmt (&gseq, return_stmt);
37329 set_bb_seq (new_bb, gseq);
37330 gimple_set_bb (convert_stmt, new_bb);
37331 gimple_set_bb (return_stmt, new_bb);
37336 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37337 tree cond_var = create_tmp_var (bool_int_type_node);
37338 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37339 const char *arg_str = rs6000_clone_map[clone_isa].name;
37340 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37341 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37342 gimple_call_set_lhs (call_cond_stmt, cond_var);
37344 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37345 gimple_set_bb (call_cond_stmt, new_bb);
37346 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37348 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37349 NULL_TREE, NULL_TREE);
37350 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37351 gimple_set_bb (if_else_stmt, new_bb);
37352 gimple_seq_add_stmt (&gseq, if_else_stmt);
37354 gimple_seq_add_stmt (&gseq, convert_stmt);
37355 gimple_seq_add_stmt (&gseq, return_stmt);
37356 set_bb_seq (new_bb, gseq);
37358 basic_block bb1 = new_bb;
37359 edge e12 = split_block (bb1, if_else_stmt);
37360 basic_block bb2 = e12->dest;
37361 e12->flags &= ~EDGE_FALLTHRU;
37362 e12->flags |= EDGE_TRUE_VALUE;
37364 edge e23 = split_block (bb2, return_stmt);
37365 gimple_set_bb (convert_stmt, bb2);
37366 gimple_set_bb (return_stmt, bb2);
37368 basic_block bb3 = e23->dest;
37369 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37372 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37378 /* This function generates the dispatch function for multi-versioned functions.
37379 DISPATCH_DECL is the function which will contain the dispatch logic.
37380 FNDECLS are the function choices for dispatch, and is a tree chain.
37381 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37382 code is generated. */
37385 dispatch_function_versions (tree dispatch_decl,
37387 basic_block *empty_bb)
37391 vec<tree> *fndecls;
37392 tree clones[CLONE_MAX];
37394 if (TARGET_DEBUG_TARGET)
37395 fputs ("dispatch_function_versions, top\n", stderr);
37397 gcc_assert (dispatch_decl != NULL
37398 && fndecls_p != NULL
37399 && empty_bb != NULL);
37401 /* fndecls_p is actually a vector. */
37402 fndecls = static_cast<vec<tree> *> (fndecls_p);
37404 /* At least one more version other than the default. */
37405 gcc_assert (fndecls->length () >= 2);
37407 /* The first version in the vector is the default decl. */
37408 memset ((void *) clones, '\0', sizeof (clones));
37409 clones[CLONE_DEFAULT] = (*fndecls)[0];
37411 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37412 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37413 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37414 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37415 to insert the code here to do the call. */
37417 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37419 int priority = rs6000_clone_priority (ele);
37420 if (!clones[priority])
37421 clones[priority] = ele;
37424 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37427 if (TARGET_DEBUG_TARGET)
37428 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37429 ix, get_decl_name (clones[ix]));
37431 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37438 /* Generate the dispatching code body to dispatch multi-versioned function
37439 DECL. The target hook is called to process the "target" attributes and
37440 provide the code to dispatch the right function at run-time. NODE points
37441 to the dispatcher decl whose body will be created. */
37444 rs6000_generate_version_dispatcher_body (void *node_p)
37447 basic_block empty_bb;
37448 struct cgraph_node *node = (cgraph_node *) node_p;
37449 struct cgraph_function_version_info *ninfo = node->function_version ();
37451 if (ninfo->dispatcher_resolver)
37452 return ninfo->dispatcher_resolver;
37454 /* node is going to be an alias, so remove the finalized bit. */
37455 node->definition = false;
37457 /* The first version in the chain corresponds to the default version. */
37458 ninfo->dispatcher_resolver = resolver
37459 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37461 if (TARGET_DEBUG_TARGET)
37462 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37463 get_decl_name (resolver));
37465 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37466 auto_vec<tree, 2> fn_ver_vec;
37468 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37470 vinfo = vinfo->next)
37472 struct cgraph_node *version = vinfo->this_node;
37473 /* Check for virtual functions here again, as by this time it should
37474 have been determined if this function needs a vtable index or
37475 not. This happens for methods in derived classes that override
37476 virtual methods in base classes but are not explicitly marked as
37478 if (DECL_VINDEX (version->decl))
37479 sorry ("Virtual function multiversioning not supported");
37481 fn_ver_vec.safe_push (version->decl);
37484 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37485 cgraph_edge::rebuild_edges ();
37491 /* Hook to determine if one function can safely inline another. */
37494 rs6000_can_inline_p (tree caller, tree callee)
37497 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37498 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37500 /* If callee has no option attributes, then it is ok to inline. */
37504 /* If caller has no option attributes, but callee does then it is not ok to
37506 else if (!caller_tree)
37511 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37512 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37514 /* Callee's options should a subset of the caller's, i.e. a vsx function
37515 can inline an altivec function but a non-vsx function can't inline a
37517 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37518 == callee_opts->x_rs6000_isa_flags)
37522 if (TARGET_DEBUG_TARGET)
37523 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37524 get_decl_name (caller), get_decl_name (callee),
37525 (ret ? "can" : "cannot"));
37530 /* Allocate a stack temp and fixup the address so it meets the particular
37531 memory requirements (either offetable or REG+REG addressing). */
37534 rs6000_allocate_stack_temp (machine_mode mode,
37535 bool offsettable_p,
37538 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37539 rtx addr = XEXP (stack, 0);
37540 int strict_p = reload_completed;
37542 if (!legitimate_indirect_address_p (addr, strict_p))
37545 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37546 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37548 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37549 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37555 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37556 convert to such a form to deal with memory reference instructions
37557 like STFIWX and LDBRX that only take reg+reg addressing. */
37560 rs6000_force_indexed_or_indirect_mem (rtx x)
37562 machine_mode mode = GET_MODE (x);
37564 gcc_assert (MEM_P (x));
37565 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x, mode))
37567 rtx addr = XEXP (x, 0);
37568 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37570 rtx reg = XEXP (addr, 0);
37571 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37572 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37573 gcc_assert (REG_P (reg));
37574 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37577 else if (GET_CODE (addr) == PRE_MODIFY)
37579 rtx reg = XEXP (addr, 0);
37580 rtx expr = XEXP (addr, 1);
37581 gcc_assert (REG_P (reg));
37582 gcc_assert (GET_CODE (expr) == PLUS);
37583 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37587 x = replace_equiv_address (x, force_reg (Pmode, addr));
37593 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37595 On the RS/6000, all integer constants are acceptable, most won't be valid
37596 for particular insns, though. Only easy FP constants are acceptable. */
37599 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37601 if (TARGET_ELF && tls_referenced_p (x))
37604 if (CONST_DOUBLE_P (x))
37605 return easy_fp_constant (x, mode);
37607 if (GET_CODE (x) == CONST_VECTOR)
37608 return easy_vector_constant (x, mode);
37614 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37617 chain_already_loaded (rtx_insn *last)
37619 for (; last != NULL; last = PREV_INSN (last))
37621 if (NONJUMP_INSN_P (last))
37623 rtx patt = PATTERN (last);
37625 if (GET_CODE (patt) == SET)
37627 rtx lhs = XEXP (patt, 0);
37629 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37637 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37640 rs6000_call_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37642 rtx func = func_desc;
37643 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37644 rtx toc_load = NULL_RTX;
37645 rtx toc_restore = NULL_RTX;
37647 rtx abi_reg = NULL_RTX;
37651 bool is_pltseq_longcall;
37654 tlsarg = global_tlsarg;
37656 /* Handle longcall attributes. */
37657 is_pltseq_longcall = false;
37658 if ((INTVAL (cookie) & CALL_LONG) != 0
37659 && GET_CODE (func_desc) == SYMBOL_REF)
37661 func = rs6000_longcall_ref (func_desc, tlsarg);
37663 is_pltseq_longcall = true;
37666 /* Handle indirect calls. */
37667 if (!SYMBOL_REF_P (func)
37668 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func)))
37670 /* Save the TOC into its reserved slot before the call,
37671 and prepare to restore it after the call. */
37672 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37673 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37674 gen_rtvec (1, stack_toc_offset),
37676 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37678 /* Can we optimize saving the TOC in the prologue or
37679 do we need to do it at every call? */
37680 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37681 cfun->machine->save_toc_in_prologue = true;
37684 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37685 rtx stack_toc_mem = gen_frame_mem (Pmode,
37686 gen_rtx_PLUS (Pmode, stack_ptr,
37687 stack_toc_offset));
37688 MEM_VOLATILE_P (stack_toc_mem) = 1;
37689 if (is_pltseq_longcall)
37691 /* Use USPEC_PLTSEQ here to emit every instruction in an
37692 inline PLT call sequence with a reloc, enabling the
37693 linker to edit the sequence back to a direct call
37694 when that makes sense. */
37695 rtvec v = gen_rtvec (3, toc_reg, func_desc, tlsarg);
37696 rtx mark_toc_reg = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37697 emit_insn (gen_rtx_SET (stack_toc_mem, mark_toc_reg));
37700 emit_move_insn (stack_toc_mem, toc_reg);
37703 if (DEFAULT_ABI == ABI_ELFv2)
37705 /* A function pointer in the ELFv2 ABI is just a plain address, but
37706 the ABI requires it to be loaded into r12 before the call. */
37707 func_addr = gen_rtx_REG (Pmode, 12);
37708 if (!rtx_equal_p (func_addr, func))
37709 emit_move_insn (func_addr, func);
37710 abi_reg = func_addr;
37711 /* Indirect calls via CTR are strongly preferred over indirect
37712 calls via LR, so move the address there. Needed to mark
37713 this insn for linker plt sequence editing too. */
37714 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37715 if (is_pltseq_longcall)
37717 rtvec v = gen_rtvec (3, abi_reg, func_desc, tlsarg);
37718 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37719 emit_insn (gen_rtx_SET (func_addr, mark_func));
37720 v = gen_rtvec (2, func_addr, func_desc);
37721 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37724 emit_move_insn (func_addr, abi_reg);
37728 /* A function pointer under AIX is a pointer to a data area whose
37729 first word contains the actual address of the function, whose
37730 second word contains a pointer to its TOC, and whose third word
37731 contains a value to place in the static chain register (r11).
37732 Note that if we load the static chain, our "trampoline" need
37733 not have any executable code. */
37735 /* Load up address of the actual function. */
37736 func = force_reg (Pmode, func);
37737 func_addr = gen_reg_rtx (Pmode);
37738 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func));
37740 /* Indirect calls via CTR are strongly preferred over indirect
37741 calls via LR, so move the address there. */
37742 rtx ctr_reg = gen_rtx_REG (Pmode, CTR_REGNO);
37743 emit_move_insn (ctr_reg, func_addr);
37744 func_addr = ctr_reg;
37746 /* Prepare to load the TOC of the called function. Note that the
37747 TOC load must happen immediately before the actual call so
37748 that unwinding the TOC registers works correctly. See the
37749 comment in frob_update_context. */
37750 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37751 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37752 gen_rtx_PLUS (Pmode, func,
37754 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37756 /* If we have a static chain, load it up. But, if the call was
37757 originally direct, the 3rd word has not been written since no
37758 trampoline has been built, so we ought not to load it, lest we
37759 override a static chain value. */
37760 if (!(GET_CODE (func_desc) == SYMBOL_REF
37761 && SYMBOL_REF_FUNCTION_P (func_desc))
37762 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37763 && !chain_already_loaded (get_current_sequence ()->next->last))
37765 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37766 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37767 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37768 gen_rtx_PLUS (Pmode, func,
37770 emit_move_insn (sc_reg, func_sc_mem);
37777 /* Direct calls use the TOC: for local calls, the callee will
37778 assume the TOC register is set; for non-local calls, the
37779 PLT stub needs the TOC register. */
37784 /* Create the call. */
37785 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37786 if (value != NULL_RTX)
37787 call[0] = gen_rtx_SET (value, call[0]);
37791 call[n_call++] = toc_load;
37793 call[n_call++] = toc_restore;
37795 call[n_call++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37797 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37798 insn = emit_call_insn (insn);
37800 /* Mention all registers defined by the ABI to hold information
37801 as uses in CALL_INSN_FUNCTION_USAGE. */
37803 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37806 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37809 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37814 gcc_assert (INTVAL (cookie) == 0);
37817 tlsarg = global_tlsarg;
37819 /* Create the call. */
37820 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), tlsarg);
37821 if (value != NULL_RTX)
37822 call[0] = gen_rtx_SET (value, call[0]);
37824 call[1] = simple_return_rtx;
37826 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37827 insn = emit_call_insn (insn);
37829 /* Note use of the TOC register. */
37830 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
37833 /* Expand code to perform a call under the SYSV4 ABI. */
37836 rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37838 rtx func = func_desc;
37842 rtx abi_reg = NULL_RTX;
37846 tlsarg = global_tlsarg;
37848 /* Handle longcall attributes. */
37849 if ((INTVAL (cookie) & CALL_LONG) != 0
37850 && GET_CODE (func_desc) == SYMBOL_REF)
37852 func = rs6000_longcall_ref (func_desc, tlsarg);
37853 /* If the longcall was implemented as an inline PLT call using
37854 PLT unspecs then func will be REG:r11. If not, func will be
37855 a pseudo reg. The inline PLT call sequence supports lazy
37856 linking (and longcalls to functions in dlopen'd libraries).
37857 The other style of longcalls don't. The lazy linking entry
37858 to the dynamic symbol resolver requires r11 be the function
37859 address (as it is for linker generated PLT stubs). Ensure
37860 r11 stays valid to the bctrl by marking r11 used by the call. */
37865 /* Handle indirect calls. */
37866 if (GET_CODE (func) != SYMBOL_REF)
37868 func = force_reg (Pmode, func);
37870 /* Indirect calls via CTR are strongly preferred over indirect
37871 calls via LR, so move the address there. That can't be left
37872 to reload because we want to mark every instruction in an
37873 inline PLT call sequence with a reloc, enabling the linker to
37874 edit the sequence back to a direct call when that makes sense. */
37875 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37878 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37879 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37880 emit_insn (gen_rtx_SET (func_addr, mark_func));
37881 v = gen_rtvec (2, func_addr, func_desc);
37882 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37885 emit_move_insn (func_addr, func);
37890 /* Create the call. */
37891 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37892 if (value != NULL_RTX)
37893 call[0] = gen_rtx_SET (value, call[0]);
37895 call[1] = gen_rtx_USE (VOIDmode, cookie);
37897 if (TARGET_SECURE_PLT
37899 && GET_CODE (func_addr) == SYMBOL_REF
37900 && !SYMBOL_REF_LOCAL_P (func_addr))
37901 call[n++] = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
37903 call[n++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37905 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n, call));
37906 insn = emit_call_insn (insn);
37908 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37911 /* Expand code to perform a sibling call under the SysV4 ABI. */
37914 rs6000_sibcall_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37916 rtx func = func_desc;
37920 rtx abi_reg = NULL_RTX;
37923 tlsarg = global_tlsarg;
37925 /* Handle longcall attributes. */
37926 if ((INTVAL (cookie) & CALL_LONG) != 0
37927 && GET_CODE (func_desc) == SYMBOL_REF)
37929 func = rs6000_longcall_ref (func_desc, tlsarg);
37930 /* If the longcall was implemented as an inline PLT call using
37931 PLT unspecs then func will be REG:r11. If not, func will be
37932 a pseudo reg. The inline PLT call sequence supports lazy
37933 linking (and longcalls to functions in dlopen'd libraries).
37934 The other style of longcalls don't. The lazy linking entry
37935 to the dynamic symbol resolver requires r11 be the function
37936 address (as it is for linker generated PLT stubs). Ensure
37937 r11 stays valid to the bctr by marking r11 used by the call. */
37942 /* Handle indirect calls. */
37943 if (GET_CODE (func) != SYMBOL_REF)
37945 func = force_reg (Pmode, func);
37947 /* Indirect sibcalls must go via CTR. That can't be left to
37948 reload because we want to mark every instruction in an inline
37949 PLT call sequence with a reloc, enabling the linker to edit
37950 the sequence back to a direct call when that makes sense. */
37951 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37954 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37955 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37956 emit_insn (gen_rtx_SET (func_addr, mark_func));
37957 v = gen_rtvec (2, func_addr, func_desc);
37958 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37961 emit_move_insn (func_addr, func);
37966 /* Create the call. */
37967 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37968 if (value != NULL_RTX)
37969 call[0] = gen_rtx_SET (value, call[0]);
37971 call[1] = gen_rtx_USE (VOIDmode, cookie);
37972 call[2] = simple_return_rtx;
37974 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
37975 insn = emit_call_insn (insn);
37977 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37982 /* Expand code to perform a call under the Darwin ABI.
37983 Modulo handling of mlongcall, this is much the same as sysv.
37984 if/when the longcall optimisation is removed, we could drop this
37985 code and use the sysv case (taking care to avoid the tls stuff).
37987 We can use this for sibcalls too, if needed. */
37990 rs6000_call_darwin_1 (rtx value, rtx func_desc, rtx tlsarg,
37991 rtx cookie, bool sibcall)
37993 rtx func = func_desc;
37997 int cookie_val = INTVAL (cookie);
37998 bool make_island = false;
38000 /* Handle longcall attributes, there are two cases for Darwin:
38001 1) Newer linkers are capable of synthesising any branch islands needed.
38002 2) We need a helper branch island synthesised by the compiler.
38003 The second case has mostly been retired and we don't use it for m64.
38004 In fact, it's is an optimisation, we could just indirect as sysv does..
38005 ... however, backwards compatibility for now.
38006 If we're going to use this, then we need to keep the CALL_LONG bit set,
38007 so that we can pick up the special insn form later. */
38008 if ((cookie_val & CALL_LONG) != 0
38009 && GET_CODE (func_desc) == SYMBOL_REF)
38011 if (darwin_emit_branch_islands && TARGET_32BIT)
38012 make_island = true; /* Do nothing yet, retain the CALL_LONG flag. */
38015 /* The linker is capable of doing this, but the user explicitly
38016 asked for -mlongcall, so we'll do the 'normal' version. */
38017 func = rs6000_longcall_ref (func_desc, NULL_RTX);
38018 cookie_val &= ~CALL_LONG; /* Handled, zap it. */
38022 /* Handle indirect calls. */
38023 if (GET_CODE (func) != SYMBOL_REF)
38025 func = force_reg (Pmode, func);
38027 /* Indirect calls via CTR are strongly preferred over indirect
38028 calls via LR, and are required for indirect sibcalls, so move
38029 the address there. */
38030 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
38031 emit_move_insn (func_addr, func);
38036 /* Create the call. */
38037 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38038 if (value != NULL_RTX)
38039 call[0] = gen_rtx_SET (value, call[0]);
38041 call[1] = gen_rtx_USE (VOIDmode, GEN_INT (cookie_val));
38044 call[2] = simple_return_rtx;
38046 call[2] = gen_hard_reg_clobber (Pmode, LR_REGNO);
38048 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
38049 insn = emit_call_insn (insn);
38050 /* Now we have the debug info in the insn, we can set up the branch island
38051 if we're using one. */
38054 tree funname = get_identifier (XSTR (func_desc, 0));
38056 if (no_previous_def (funname))
38058 rtx label_rtx = gen_label_rtx ();
38059 char *label_buf, temp_buf[256];
38060 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
38061 CODE_LABEL_NUMBER (label_rtx));
38062 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
38063 tree labelname = get_identifier (label_buf);
38064 add_compiler_branch_island (labelname, funname,
38065 insn_line ((const rtx_insn*)insn));
38072 rs6000_call_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38073 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38076 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, false);
38084 rs6000_sibcall_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38085 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38088 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, true);
38095 /* Return whether we need to always update the saved TOC pointer when we update
38096 the stack pointer. */
38099 rs6000_save_toc_in_prologue_p (void)
38101 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38104 #ifdef HAVE_GAS_HIDDEN
38105 # define USE_HIDDEN_LINKONCE 1
38107 # define USE_HIDDEN_LINKONCE 0
38110 /* Fills in the label name that should be used for a 476 link stack thunk. */
38113 get_ppc476_thunk_name (char name[32])
38115 gcc_assert (TARGET_LINK_STACK);
38117 if (USE_HIDDEN_LINKONCE)
38118 sprintf (name, "__ppc476.get_thunk");
38120 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38123 /* This function emits the simple thunk routine that is used to preserve
38124 the link stack on the 476 cpu. */
38126 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38128 rs6000_code_end (void)
38133 if (!TARGET_LINK_STACK)
38136 get_ppc476_thunk_name (name);
38138 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38139 build_function_type_list (void_type_node, NULL_TREE));
38140 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38141 NULL_TREE, void_type_node);
38142 TREE_PUBLIC (decl) = 1;
38143 TREE_STATIC (decl) = 1;
38146 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38148 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38149 targetm.asm_out.unique_section (decl, 0);
38150 switch_to_section (get_named_section (decl, NULL, 0));
38151 DECL_WEAK (decl) = 1;
38152 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38153 targetm.asm_out.globalize_label (asm_out_file, name);
38154 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38155 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38160 switch_to_section (text_section);
38161 ASM_OUTPUT_LABEL (asm_out_file, name);
38164 DECL_INITIAL (decl) = make_node (BLOCK);
38165 current_function_decl = decl;
38166 allocate_struct_function (decl, false);
38167 init_function_start (decl);
38168 first_function_block_is_cold = false;
38169 /* Make sure unwind info is emitted for the thunk if needed. */
38170 final_start_function (emit_barrier (), asm_out_file, 1);
38172 fputs ("\tblr\n", asm_out_file);
38174 final_end_function ();
38175 init_insn_lengths ();
38176 free_after_compilation (cfun);
38178 current_function_decl = NULL;
38181 /* Add r30 to hard reg set if the prologue sets it up and it is not
38182 pic_offset_table_rtx. */
38185 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38187 if (!TARGET_SINGLE_PIC_BASE
38189 && TARGET_MINIMAL_TOC
38190 && !constant_pool_empty_p ())
38191 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38192 if (cfun->machine->split_stack_argp_used)
38193 add_to_hard_reg_set (&set->set, Pmode, 12);
38195 /* Make sure the hard reg set doesn't include r2, which was possibly added
38196 via PIC_OFFSET_TABLE_REGNUM. */
38198 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38202 /* Helper function for rs6000_split_logical to emit a logical instruction after
38203 spliting the operation to single GPR registers.
38205 DEST is the destination register.
38206 OP1 and OP2 are the input source registers.
38207 CODE is the base operation (AND, IOR, XOR, NOT).
38208 MODE is the machine mode.
38209 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38210 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38211 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38214 rs6000_split_logical_inner (rtx dest,
38217 enum rtx_code code,
38219 bool complement_final_p,
38220 bool complement_op1_p,
38221 bool complement_op2_p)
38225 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38226 if (op2 && CONST_INT_P (op2)
38227 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38228 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38230 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38231 HOST_WIDE_INT value = INTVAL (op2) & mask;
38233 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38238 emit_insn (gen_rtx_SET (dest, const0_rtx));
38242 else if (value == mask)
38244 if (!rtx_equal_p (dest, op1))
38245 emit_insn (gen_rtx_SET (dest, op1));
38250 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38251 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38252 else if (code == IOR || code == XOR)
38256 if (!rtx_equal_p (dest, op1))
38257 emit_insn (gen_rtx_SET (dest, op1));
38263 if (code == AND && mode == SImode
38264 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38266 emit_insn (gen_andsi3 (dest, op1, op2));
38270 if (complement_op1_p)
38271 op1 = gen_rtx_NOT (mode, op1);
38273 if (complement_op2_p)
38274 op2 = gen_rtx_NOT (mode, op2);
38276 /* For canonical RTL, if only one arm is inverted it is the first. */
38277 if (!complement_op1_p && complement_op2_p)
38278 std::swap (op1, op2);
38280 bool_rtx = ((code == NOT)
38281 ? gen_rtx_NOT (mode, op1)
38282 : gen_rtx_fmt_ee (code, mode, op1, op2));
38284 if (complement_final_p)
38285 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38287 emit_insn (gen_rtx_SET (dest, bool_rtx));
38290 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38291 operations are split immediately during RTL generation to allow for more
38292 optimizations of the AND/IOR/XOR.
38294 OPERANDS is an array containing the destination and two input operands.
38295 CODE is the base operation (AND, IOR, XOR, NOT).
38296 MODE is the machine mode.
38297 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38298 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38299 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38300 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38301 formation of the AND instructions. */
38304 rs6000_split_logical_di (rtx operands[3],
38305 enum rtx_code code,
38306 bool complement_final_p,
38307 bool complement_op1_p,
38308 bool complement_op2_p)
38310 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38311 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38312 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38313 enum hi_lo { hi = 0, lo = 1 };
38314 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38317 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38318 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38319 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38320 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38323 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38326 if (!CONST_INT_P (operands[2]))
38328 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38329 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38333 HOST_WIDE_INT value = INTVAL (operands[2]);
38334 HOST_WIDE_INT value_hi_lo[2];
38336 gcc_assert (!complement_final_p);
38337 gcc_assert (!complement_op1_p);
38338 gcc_assert (!complement_op2_p);
38340 value_hi_lo[hi] = value >> 32;
38341 value_hi_lo[lo] = value & lower_32bits;
38343 for (i = 0; i < 2; i++)
38345 HOST_WIDE_INT sub_value = value_hi_lo[i];
38347 if (sub_value & sign_bit)
38348 sub_value |= upper_32bits;
38350 op2_hi_lo[i] = GEN_INT (sub_value);
38352 /* If this is an AND instruction, check to see if we need to load
38353 the value in a register. */
38354 if (code == AND && sub_value != -1 && sub_value != 0
38355 && !and_operand (op2_hi_lo[i], SImode))
38356 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38361 for (i = 0; i < 2; i++)
38363 /* Split large IOR/XOR operations. */
38364 if ((code == IOR || code == XOR)
38365 && CONST_INT_P (op2_hi_lo[i])
38366 && !complement_final_p
38367 && !complement_op1_p
38368 && !complement_op2_p
38369 && !logical_const_operand (op2_hi_lo[i], SImode))
38371 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38372 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38373 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38374 rtx tmp = gen_reg_rtx (SImode);
38376 /* Make sure the constant is sign extended. */
38377 if ((hi_16bits & sign_bit) != 0)
38378 hi_16bits |= upper_32bits;
38380 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38381 code, SImode, false, false, false);
38383 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38384 code, SImode, false, false, false);
38387 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38388 code, SImode, complement_final_p,
38389 complement_op1_p, complement_op2_p);
38395 /* Split the insns that make up boolean operations operating on multiple GPR
38396 registers. The boolean MD patterns ensure that the inputs either are
38397 exactly the same as the output registers, or there is no overlap.
38399 OPERANDS is an array containing the destination and two input operands.
38400 CODE is the base operation (AND, IOR, XOR, NOT).
38401 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38402 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38403 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38406 rs6000_split_logical (rtx operands[3],
38407 enum rtx_code code,
38408 bool complement_final_p,
38409 bool complement_op1_p,
38410 bool complement_op2_p)
38412 machine_mode mode = GET_MODE (operands[0]);
38413 machine_mode sub_mode;
38415 int sub_size, regno0, regno1, nregs, i;
38417 /* If this is DImode, use the specialized version that can run before
38418 register allocation. */
38419 if (mode == DImode && !TARGET_POWERPC64)
38421 rs6000_split_logical_di (operands, code, complement_final_p,
38422 complement_op1_p, complement_op2_p);
38428 op2 = (code == NOT) ? NULL_RTX : operands[2];
38429 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38430 sub_size = GET_MODE_SIZE (sub_mode);
38431 regno0 = REGNO (op0);
38432 regno1 = REGNO (op1);
38434 gcc_assert (reload_completed);
38435 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38436 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38438 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38439 gcc_assert (nregs > 1);
38441 if (op2 && REG_P (op2))
38442 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38444 for (i = 0; i < nregs; i++)
38446 int offset = i * sub_size;
38447 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38448 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38449 rtx sub_op2 = ((code == NOT)
38451 : simplify_subreg (sub_mode, op2, mode, offset));
38453 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38454 complement_final_p, complement_op1_p,
38462 /* Return true if the peephole2 can combine a load involving a combination of
38463 an addis instruction and a load with an offset that can be fused together on
38467 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38468 rtx addis_value, /* addis value. */
38469 rtx target, /* target register that is loaded. */
38470 rtx mem) /* bottom part of the memory addr. */
38475 /* Validate arguments. */
38476 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38479 if (!base_reg_operand (target, GET_MODE (target)))
38482 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38485 /* Allow sign/zero extension. */
38486 if (GET_CODE (mem) == ZERO_EXTEND
38487 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38488 mem = XEXP (mem, 0);
38493 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38496 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38497 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38500 /* Validate that the register used to load the high value is either the
38501 register being loaded, or we can safely replace its use.
38503 This function is only called from the peephole2 pass and we assume that
38504 there are 2 instructions in the peephole (addis and load), so we want to
38505 check if the target register was not used in the memory address and the
38506 register to hold the addis result is dead after the peephole. */
38507 if (REGNO (addis_reg) != REGNO (target))
38509 if (reg_mentioned_p (target, mem))
38512 if (!peep2_reg_dead_p (2, addis_reg))
38515 /* If the target register being loaded is the stack pointer, we must
38516 avoid loading any other value into it, even temporarily. */
38517 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38521 base_reg = XEXP (addr, 0);
38522 return REGNO (addis_reg) == REGNO (base_reg);
38525 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38526 sequence. We adjust the addis register to use the target register. If the
38527 load sign extends, we adjust the code to do the zero extending load, and an
38528 explicit sign extension later since the fusion only covers zero extending
38532 operands[0] register set with addis (to be replaced with target)
38533 operands[1] value set via addis
38534 operands[2] target register being loaded
38535 operands[3] D-form memory reference using operands[0]. */
38538 expand_fusion_gpr_load (rtx *operands)
38540 rtx addis_value = operands[1];
38541 rtx target = operands[2];
38542 rtx orig_mem = operands[3];
38543 rtx new_addr, new_mem, orig_addr, offset;
38544 enum rtx_code plus_or_lo_sum;
38545 machine_mode target_mode = GET_MODE (target);
38546 machine_mode extend_mode = target_mode;
38547 machine_mode ptr_mode = Pmode;
38548 enum rtx_code extend = UNKNOWN;
38550 if (GET_CODE (orig_mem) == ZERO_EXTEND
38551 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38553 extend = GET_CODE (orig_mem);
38554 orig_mem = XEXP (orig_mem, 0);
38555 target_mode = GET_MODE (orig_mem);
38558 gcc_assert (MEM_P (orig_mem));
38560 orig_addr = XEXP (orig_mem, 0);
38561 plus_or_lo_sum = GET_CODE (orig_addr);
38562 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38564 offset = XEXP (orig_addr, 1);
38565 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38566 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38568 if (extend != UNKNOWN)
38569 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38571 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38572 UNSPEC_FUSION_GPR);
38573 emit_insn (gen_rtx_SET (target, new_mem));
38575 if (extend == SIGN_EXTEND)
38577 int sub_off = ((BYTES_BIG_ENDIAN)
38578 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38581 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38583 emit_insn (gen_rtx_SET (target,
38584 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38590 /* Emit the addis instruction that will be part of a fused instruction
38594 emit_fusion_addis (rtx target, rtx addis_value)
38597 const char *addis_str = NULL;
38599 /* Emit the addis instruction. */
38600 fuse_ops[0] = target;
38601 if (satisfies_constraint_L (addis_value))
38603 fuse_ops[1] = addis_value;
38604 addis_str = "lis %0,%v1";
38607 else if (GET_CODE (addis_value) == PLUS)
38609 rtx op0 = XEXP (addis_value, 0);
38610 rtx op1 = XEXP (addis_value, 1);
38612 if (REG_P (op0) && CONST_INT_P (op1)
38613 && satisfies_constraint_L (op1))
38617 addis_str = "addis %0,%1,%v2";
38621 else if (GET_CODE (addis_value) == HIGH)
38623 rtx value = XEXP (addis_value, 0);
38624 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38626 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38627 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38629 addis_str = "addis %0,%2,%1@toc@ha";
38631 else if (TARGET_XCOFF)
38632 addis_str = "addis %0,%1@u(%2)";
38635 gcc_unreachable ();
38638 else if (GET_CODE (value) == PLUS)
38640 rtx op0 = XEXP (value, 0);
38641 rtx op1 = XEXP (value, 1);
38643 if (GET_CODE (op0) == UNSPEC
38644 && XINT (op0, 1) == UNSPEC_TOCREL
38645 && CONST_INT_P (op1))
38647 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38648 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38651 addis_str = "addis %0,%2,%1+%3@toc@ha";
38653 else if (TARGET_XCOFF)
38654 addis_str = "addis %0,%1+%3@u(%2)";
38657 gcc_unreachable ();
38661 else if (satisfies_constraint_L (value))
38663 fuse_ops[1] = value;
38664 addis_str = "lis %0,%v1";
38667 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38669 fuse_ops[1] = value;
38670 addis_str = "lis %0,%1@ha";
38675 fatal_insn ("Could not generate addis value for fusion", addis_value);
38677 output_asm_insn (addis_str, fuse_ops);
38680 /* Emit a D-form load or store instruction that is the second instruction
38681 of a fusion sequence. */
38684 emit_fusion_load (rtx load_reg, rtx addis_reg, rtx offset, const char *insn_str)
38687 char insn_template[80];
38689 fuse_ops[0] = load_reg;
38690 fuse_ops[1] = addis_reg;
38692 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38694 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38695 fuse_ops[2] = offset;
38696 output_asm_insn (insn_template, fuse_ops);
38699 else if (GET_CODE (offset) == UNSPEC
38700 && XINT (offset, 1) == UNSPEC_TOCREL)
38703 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38705 else if (TARGET_XCOFF)
38706 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38709 gcc_unreachable ();
38711 fuse_ops[2] = XVECEXP (offset, 0, 0);
38712 output_asm_insn (insn_template, fuse_ops);
38715 else if (GET_CODE (offset) == PLUS
38716 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38717 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38718 && CONST_INT_P (XEXP (offset, 1)))
38720 rtx tocrel_unspec = XEXP (offset, 0);
38722 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38724 else if (TARGET_XCOFF)
38725 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38728 gcc_unreachable ();
38730 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38731 fuse_ops[3] = XEXP (offset, 1);
38732 output_asm_insn (insn_template, fuse_ops);
38735 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38737 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38739 fuse_ops[2] = offset;
38740 output_asm_insn (insn_template, fuse_ops);
38744 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38749 /* Given an address, convert it into the addis and load offset parts. Addresses
38750 created during the peephole2 process look like:
38751 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38752 (unspec [(...)] UNSPEC_TOCREL)) */
38755 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38759 if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38761 hi = XEXP (addr, 0);
38762 lo = XEXP (addr, 1);
38765 gcc_unreachable ();
38771 /* Return a string to fuse an addis instruction with a gpr load to the same
38772 register that we loaded up the addis instruction. The address that is used
38773 is the logical address that was formed during peephole2:
38774 (lo_sum (high) (low-part))
38776 The code is complicated, so we call output_asm_insn directly, and just
38780 emit_fusion_gpr_load (rtx target, rtx mem)
38785 const char *load_str = NULL;
38788 if (GET_CODE (mem) == ZERO_EXTEND)
38789 mem = XEXP (mem, 0);
38791 gcc_assert (REG_P (target) && MEM_P (mem));
38793 addr = XEXP (mem, 0);
38794 fusion_split_address (addr, &addis_value, &load_offset);
38796 /* Now emit the load instruction to the same register. */
38797 mode = GET_MODE (mem);
38815 gcc_assert (TARGET_POWERPC64);
38820 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38823 /* Emit the addis instruction. */
38824 emit_fusion_addis (target, addis_value);
38826 /* Emit the D-form load instruction. */
38827 emit_fusion_load (target, target, load_offset, load_str);
38833 #ifdef RS6000_GLIBC_ATOMIC_FENV
38834 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38835 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
38838 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38841 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
38843 if (!TARGET_HARD_FLOAT)
38845 #ifdef RS6000_GLIBC_ATOMIC_FENV
38846 if (atomic_hold_decl == NULL_TREE)
38849 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38850 get_identifier ("__atomic_feholdexcept"),
38851 build_function_type_list (void_type_node,
38852 double_ptr_type_node,
38854 TREE_PUBLIC (atomic_hold_decl) = 1;
38855 DECL_EXTERNAL (atomic_hold_decl) = 1;
38858 if (atomic_clear_decl == NULL_TREE)
38861 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38862 get_identifier ("__atomic_feclearexcept"),
38863 build_function_type_list (void_type_node,
38865 TREE_PUBLIC (atomic_clear_decl) = 1;
38866 DECL_EXTERNAL (atomic_clear_decl) = 1;
38869 tree const_double = build_qualified_type (double_type_node,
38871 tree const_double_ptr = build_pointer_type (const_double);
38872 if (atomic_update_decl == NULL_TREE)
38875 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38876 get_identifier ("__atomic_feupdateenv"),
38877 build_function_type_list (void_type_node,
38880 TREE_PUBLIC (atomic_update_decl) = 1;
38881 DECL_EXTERNAL (atomic_update_decl) = 1;
38884 tree fenv_var = create_tmp_var_raw (double_type_node);
38885 TREE_ADDRESSABLE (fenv_var) = 1;
38886 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
38888 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
38889 *clear = build_call_expr (atomic_clear_decl, 0);
38890 *update = build_call_expr (atomic_update_decl, 1,
38891 fold_convert (const_double_ptr, fenv_addr));
38896 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
38897 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
38898 tree call_mffs = build_call_expr (mffs, 0);
38900 /* Generates the equivalent of feholdexcept (&fenv_var)
38902 *fenv_var = __builtin_mffs ();
38904 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38905 __builtin_mtfsf (0xff, fenv_hold); */
38907 /* Mask to clear everything except for the rounding modes and non-IEEE
38908 arithmetic flag. */
38909 const unsigned HOST_WIDE_INT hold_exception_mask =
38910 HOST_WIDE_INT_C (0xffffffff00000007);
38912 tree fenv_var = create_tmp_var_raw (double_type_node);
38914 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
38916 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
38917 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38918 build_int_cst (uint64_type_node,
38919 hold_exception_mask));
38921 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38924 tree hold_mtfsf = build_call_expr (mtfsf, 2,
38925 build_int_cst (unsigned_type_node, 0xff),
38928 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
38930 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38932 double fenv_clear = __builtin_mffs ();
38933 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38934 __builtin_mtfsf (0xff, fenv_clear); */
38936 /* Mask to clear everything except for the rounding modes and non-IEEE
38937 arithmetic flag. */
38938 const unsigned HOST_WIDE_INT clear_exception_mask =
38939 HOST_WIDE_INT_C (0xffffffff00000000);
38941 tree fenv_clear = create_tmp_var_raw (double_type_node);
38943 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
38945 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
38946 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
38948 build_int_cst (uint64_type_node,
38949 clear_exception_mask));
38951 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38952 fenv_clear_llu_and);
38954 tree clear_mtfsf = build_call_expr (mtfsf, 2,
38955 build_int_cst (unsigned_type_node, 0xff),
38958 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
38960 /* Generates the equivalent of feupdateenv (&fenv_var)
38962 double old_fenv = __builtin_mffs ();
38963 double fenv_update;
38964 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38965 (*(uint64_t*)fenv_var 0x1ff80fff);
38966 __builtin_mtfsf (0xff, fenv_update); */
38968 const unsigned HOST_WIDE_INT update_exception_mask =
38969 HOST_WIDE_INT_C (0xffffffff1fffff00);
38970 const unsigned HOST_WIDE_INT new_exception_mask =
38971 HOST_WIDE_INT_C (0x1ff80fff);
38973 tree old_fenv = create_tmp_var_raw (double_type_node);
38974 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
38976 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
38977 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
38978 build_int_cst (uint64_type_node,
38979 update_exception_mask));
38981 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38982 build_int_cst (uint64_type_node,
38983 new_exception_mask));
38985 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
38986 old_llu_and, new_llu_and);
38988 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38991 tree update_mtfsf = build_call_expr (mtfsf, 2,
38992 build_int_cst (unsigned_type_node, 0xff),
38993 fenv_update_mtfsf);
38995 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
38999 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
39001 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39003 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39004 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39006 /* The destination of the vmrgew instruction layout is:
39007 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39008 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39009 vmrgew instruction will be correct. */
39010 if (BYTES_BIG_ENDIAN)
39012 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
39014 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39019 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39020 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39023 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39024 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39026 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39027 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39029 if (BYTES_BIG_ENDIAN)
39030 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39032 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39036 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39038 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39040 rtx_tmp0 = gen_reg_rtx (V2DImode);
39041 rtx_tmp1 = gen_reg_rtx (V2DImode);
39043 /* The destination of the vmrgew instruction layout is:
39044 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39045 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39046 vmrgew instruction will be correct. */
39047 if (BYTES_BIG_ENDIAN)
39049 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39050 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39054 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39055 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39058 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39059 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39061 if (signed_convert)
39063 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39064 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39068 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39069 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39072 if (BYTES_BIG_ENDIAN)
39073 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39075 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39079 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39082 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39084 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39085 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39087 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39088 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39090 rtx_tmp2 = gen_reg_rtx (V4SImode);
39091 rtx_tmp3 = gen_reg_rtx (V4SImode);
39093 if (signed_convert)
39095 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39096 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39100 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39101 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39104 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39107 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39110 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39111 optimization_type opt_type)
39116 return (opt_type == OPTIMIZE_FOR_SPEED
39117 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39124 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39126 static HOST_WIDE_INT
39127 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39129 if (TREE_CODE (exp) == STRING_CST
39130 && (STRICT_ALIGNMENT || !optimize_size))
39131 return MAX (align, BITS_PER_WORD);
39135 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39137 static HOST_WIDE_INT
39138 rs6000_starting_frame_offset (void)
39140 if (FRAME_GROWS_DOWNWARD)
39142 return RS6000_STARTING_FRAME_OFFSET;
39146 /* Create an alias for a mangled name where we have changed the mangling (in
39147 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
39148 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
39150 #if TARGET_ELF && RS6000_WEAK
39152 rs6000_globalize_decl_name (FILE * stream, tree decl)
39154 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
39156 targetm.asm_out.globalize_label (stream, name);
39158 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
39160 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
39161 const char *old_name;
39163 ieee128_mangling_gcc_8_1 = true;
39164 lang_hooks.set_decl_assembler_name (decl);
39165 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
39166 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
39167 ieee128_mangling_gcc_8_1 = false;
39169 if (strcmp (name, old_name) != 0)
39171 fprintf (stream, "\t.weak %s\n", old_name);
39172 fprintf (stream, "\t.set %s,%s\n", old_name, name);
39179 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
39180 function names from <foo>l to <foo>f128 if the default long double type is
39181 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
39182 include file switches the names on systems that support long double as IEEE
39183 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
39184 In the future, glibc will export names like __ieee128_sinf128 and we can
39185 switch to using those instead of using sinf128, which pollutes the user's
39188 This will switch the names for Fortran math functions as well (which doesn't
39189 use math.h). However, Fortran needs other changes to the compiler and
39190 library before you can switch the real*16 type at compile time.
39192 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
39193 only do this if the default is that long double is IBM extended double, and
39194 the user asked for IEEE 128-bit. */
39197 rs6000_mangle_decl_assembler_name (tree decl, tree id)
39199 if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
39200 && TREE_CODE (decl) == FUNCTION_DECL && DECL_IS_BUILTIN (decl) )
39202 size_t len = IDENTIFIER_LENGTH (id);
39203 const char *name = IDENTIFIER_POINTER (id);
39205 if (name[len - 1] == 'l')
39207 bool uses_ieee128_p = false;
39208 tree type = TREE_TYPE (decl);
39209 machine_mode ret_mode = TYPE_MODE (type);
39211 /* See if the function returns a IEEE 128-bit floating point type or
39213 if (ret_mode == TFmode || ret_mode == TCmode)
39214 uses_ieee128_p = true;
39217 function_args_iterator args_iter;
39220 /* See if the function passes a IEEE 128-bit floating point type
39221 or complex type. */
39222 FOREACH_FUNCTION_ARGS (type, arg, args_iter)
39224 machine_mode arg_mode = TYPE_MODE (arg);
39225 if (arg_mode == TFmode || arg_mode == TCmode)
39227 uses_ieee128_p = true;
39233 /* If we passed or returned an IEEE 128-bit floating point type,
39234 change the name. */
39235 if (uses_ieee128_p)
39237 char *name2 = (char *) alloca (len + 4);
39238 memcpy (name2, name, len - 1);
39239 strcpy (name2 + len - 1, "f128");
39240 id = get_identifier (name2);
39249 struct gcc_target targetm = TARGET_INITIALIZER;
39251 #include "gt-rs6000.h"